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src/cpu/x86/vm/vm_version_x86.cpp

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 637     _features &= ~CPU_AVX2;
 638 
 639   if (UseAVX < 1) {
 640     _features &= ~CPU_AVX;
 641     _features &= ~CPU_VZEROUPPER;
 642   }
 643 
 644   if (!UseAES && !FLAG_IS_DEFAULT(UseAES))
 645     _features &= ~CPU_AES;
 646 
 647   if (logical_processors_per_package() == 1) {
 648     // HT processor could be installed on a system which doesn't support HT.
 649     _features &= ~CPU_HT;
 650   }
 651 
 652   if( is_intel() ) { // Intel cpus specific settings
 653     if ((cpu_family() == 0x06) &&
 654         ((extended_cpu_model() == 0x57) ||   // Xeon Phi 3200/5200/7200
 655         (extended_cpu_model() == 0x85))) {  // Future Xeon Phi
 656       _features &= ~CPU_VZEROUPPER;














 657     }
 658   }
 659 
 660   char buf[256];
 661   jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
 662                cores_per_cpu(), threads_per_core(),
 663                cpu_family(), _model, _stepping,
 664                (supports_cmov() ? ", cmov" : ""),
 665                (supports_cmpxchg8() ? ", cx8" : ""),
 666                (supports_fxsr() ? ", fxsr" : ""),
 667                (supports_mmx()  ? ", mmx"  : ""),
 668                (supports_sse()  ? ", sse"  : ""),
 669                (supports_sse2() ? ", sse2" : ""),
 670                (supports_sse3() ? ", sse3" : ""),
 671                (supports_ssse3()? ", ssse3": ""),
 672                (supports_sse4_1() ? ", sse4.1" : ""),
 673                (supports_sse4_2() ? ", sse4.2" : ""),
 674                (supports_popcnt() ? ", popcnt" : ""),
 675                (supports_avx()    ? ", avx" : ""),
 676                (supports_avx2()   ? ", avx2" : ""),


1176         if (UseSSE42Intrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
1177           warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled.");
1178         }
1179         FLAG_SET_DEFAULT(UseSSE42Intrinsics, false);
1180       }
1181     }
1182     if ((cpu_family() == 0x06) &&
1183         ((extended_cpu_model() == 0x36) || // Centerton
1184          (extended_cpu_model() == 0x37) || // Silvermont
1185          (extended_cpu_model() == 0x4D))) {
1186 #ifdef COMPILER2
1187       if (FLAG_IS_DEFAULT(OptoScheduling)) {
1188         OptoScheduling = true;
1189       }
1190 #endif
1191       if (supports_sse4_2()) { // Silvermont
1192         if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1193           UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
1194         }
1195       }



1196     }
1197     if(FLAG_IS_DEFAULT(AllocatePrefetchInstr) && supports_3dnow_prefetch()) {
1198       AllocatePrefetchInstr = 3;
1199     }
1200   }
1201 
1202 #ifdef _LP64
1203   if (UseSSE42Intrinsics) {
1204     if (FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic)) {
1205       UseVectorizedMismatchIntrinsic = true;
1206     }
1207   } else if (UseVectorizedMismatchIntrinsic) {
1208     if (!FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic))
1209       warning("vectorizedMismatch intrinsics are not available on this CPU");
1210     FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
1211   }
1212 #else
1213   if (UseVectorizedMismatchIntrinsic) {
1214     if (!FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic)) {
1215       warning("vectorizedMismatch intrinsic is not available in 32-bit VM");




 637     _features &= ~CPU_AVX2;
 638 
 639   if (UseAVX < 1) {
 640     _features &= ~CPU_AVX;
 641     _features &= ~CPU_VZEROUPPER;
 642   }
 643 
 644   if (!UseAES && !FLAG_IS_DEFAULT(UseAES))
 645     _features &= ~CPU_AES;
 646 
 647   if (logical_processors_per_package() == 1) {
 648     // HT processor could be installed on a system which doesn't support HT.
 649     _features &= ~CPU_HT;
 650   }
 651 
 652   if( is_intel() ) { // Intel cpus specific settings
 653     if ((cpu_family() == 0x06) &&
 654         ((extended_cpu_model() == 0x57) ||   // Xeon Phi 3200/5200/7200
 655         (extended_cpu_model() == 0x85))) {  // Future Xeon Phi
 656       _features &= ~CPU_VZEROUPPER;
 657      if (FLAG_IS_DEFAULT(UseIncDec)){
 658      FLAG_SET_DEFAULT(UseIncDec, false);
 659          }
 660 #ifdef COMPILER2
 661           if (FLAG_IS_DEFAULT(OptoScheduling)) {
 662                   OptoScheduling = true;
 663           }
 664 #endif
 665  if (supports_sse4_2()) { // Silvermont
 666   if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
 667          UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
 668         }
 669  }
 670 
 671         }
 672   }
 673 
 674   char buf[256];
 675   jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
 676                cores_per_cpu(), threads_per_core(),
 677                cpu_family(), _model, _stepping,
 678                (supports_cmov() ? ", cmov" : ""),
 679                (supports_cmpxchg8() ? ", cx8" : ""),
 680                (supports_fxsr() ? ", fxsr" : ""),
 681                (supports_mmx()  ? ", mmx"  : ""),
 682                (supports_sse()  ? ", sse"  : ""),
 683                (supports_sse2() ? ", sse2" : ""),
 684                (supports_sse3() ? ", sse3" : ""),
 685                (supports_ssse3()? ", ssse3": ""),
 686                (supports_sse4_1() ? ", sse4.1" : ""),
 687                (supports_sse4_2() ? ", sse4.2" : ""),
 688                (supports_popcnt() ? ", popcnt" : ""),
 689                (supports_avx()    ? ", avx" : ""),
 690                (supports_avx2()   ? ", avx2" : ""),


1190         if (UseSSE42Intrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
1191           warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled.");
1192         }
1193         FLAG_SET_DEFAULT(UseSSE42Intrinsics, false);
1194       }
1195     }
1196     if ((cpu_family() == 0x06) &&
1197         ((extended_cpu_model() == 0x36) || // Centerton
1198          (extended_cpu_model() == 0x37) || // Silvermont
1199          (extended_cpu_model() == 0x4D))) {
1200 #ifdef COMPILER2
1201       if (FLAG_IS_DEFAULT(OptoScheduling)) {
1202         OptoScheduling = true;
1203       }
1204 #endif
1205       if (supports_sse4_2()) { // Silvermont
1206         if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1207           UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
1208         }
1209       }
1210           if (FLAG_IS_DEFAULT(UseIncDec)){
1211                   FLAG_SET_DEFAULT(UseIncDec, false);
1212           }
1213         }
1214     if(FLAG_IS_DEFAULT(AllocatePrefetchInstr) && supports_3dnow_prefetch()) {
1215       AllocatePrefetchInstr = 3;
1216     }
1217   }
1218 
1219 #ifdef _LP64
1220   if (UseSSE42Intrinsics) {
1221     if (FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic)) {
1222       UseVectorizedMismatchIntrinsic = true;
1223     }
1224   } else if (UseVectorizedMismatchIntrinsic) {
1225     if (!FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic))
1226       warning("vectorizedMismatch intrinsics are not available on this CPU");
1227     FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
1228   }
1229 #else
1230   if (UseVectorizedMismatchIntrinsic) {
1231     if (!FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic)) {
1232       warning("vectorizedMismatch intrinsic is not available in 32-bit VM");


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