1 /* 2 * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "asm/assembler.hpp" 27 #include "asm/assembler.inline.hpp" 28 #include "gc/shared/cardTableModRefBS.hpp" 29 #include "gc/shared/collectedHeap.inline.hpp" 30 #include "interpreter/interpreter.hpp" 31 #include "memory/resourceArea.hpp" 32 #include "prims/methodHandles.hpp" 33 #include "runtime/biasedLocking.hpp" 34 #include "runtime/interfaceSupport.hpp" 35 #include "runtime/objectMonitor.hpp" 36 #include "runtime/os.hpp" 37 #include "runtime/sharedRuntime.hpp" 38 #include "runtime/stubRoutines.hpp" 39 #include "utilities/macros.hpp" 40 #if INCLUDE_ALL_GCS 41 #include "gc/g1/g1CollectedHeap.inline.hpp" 42 #include "gc/g1/g1SATBCardTableModRefBS.hpp" 43 #include "gc/g1/heapRegion.hpp" 44 #endif // INCLUDE_ALL_GCS 45 46 #ifdef PRODUCT 47 #define BLOCK_COMMENT(str) /* nothing */ 48 #define STOP(error) stop(error) 49 #else 50 #define BLOCK_COMMENT(str) block_comment(str) 51 #define STOP(error) block_comment(error); stop(error) 52 #endif 53 54 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":") 55 // Implementation of AddressLiteral 56 57 // A 2-D table for managing compressed displacement(disp8) on EVEX enabled platforms. 58 unsigned char tuple_table[Assembler::EVEX_ETUP + 1][Assembler::AVX_512bit + 1] = { 59 // -----------------Table 4.5 -------------------- // 60 16, 32, 64, // EVEX_FV(0) 61 4, 4, 4, // EVEX_FV(1) - with Evex.b 62 16, 32, 64, // EVEX_FV(2) - with Evex.w 63 8, 8, 8, // EVEX_FV(3) - with Evex.w and Evex.b 64 8, 16, 32, // EVEX_HV(0) 65 4, 4, 4, // EVEX_HV(1) - with Evex.b 66 // -----------------Table 4.6 -------------------- // 67 16, 32, 64, // EVEX_FVM(0) 68 1, 1, 1, // EVEX_T1S(0) 69 2, 2, 2, // EVEX_T1S(1) 70 4, 4, 4, // EVEX_T1S(2) 71 8, 8, 8, // EVEX_T1S(3) 72 4, 4, 4, // EVEX_T1F(0) 73 8, 8, 8, // EVEX_T1F(1) 74 8, 8, 8, // EVEX_T2(0) 75 0, 16, 16, // EVEX_T2(1) 76 0, 16, 16, // EVEX_T4(0) 77 0, 0, 32, // EVEX_T4(1) 78 0, 0, 32, // EVEX_T8(0) 79 8, 16, 32, // EVEX_HVM(0) 80 4, 8, 16, // EVEX_QVM(0) 81 2, 4, 8, // EVEX_OVM(0) 82 16, 16, 16, // EVEX_M128(0) 83 8, 32, 64, // EVEX_DUP(0) 84 0, 0, 0 // EVEX_NTUP 85 }; 86 87 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) { 88 _is_lval = false; 89 _target = target; 90 switch (rtype) { 91 case relocInfo::oop_type: 92 case relocInfo::metadata_type: 93 // Oops are a special case. Normally they would be their own section 94 // but in cases like icBuffer they are literals in the code stream that 95 // we don't have a section for. We use none so that we get a literal address 96 // which is always patchable. 97 break; 98 case relocInfo::external_word_type: 99 _rspec = external_word_Relocation::spec(target); 100 break; 101 case relocInfo::internal_word_type: 102 _rspec = internal_word_Relocation::spec(target); 103 break; 104 case relocInfo::opt_virtual_call_type: 105 _rspec = opt_virtual_call_Relocation::spec(); 106 break; 107 case relocInfo::static_call_type: 108 _rspec = static_call_Relocation::spec(); 109 break; 110 case relocInfo::runtime_call_type: 111 _rspec = runtime_call_Relocation::spec(); 112 break; 113 case relocInfo::poll_type: 114 case relocInfo::poll_return_type: 115 _rspec = Relocation::spec_simple(rtype); 116 break; 117 case relocInfo::none: 118 break; 119 default: 120 ShouldNotReachHere(); 121 break; 122 } 123 } 124 125 // Implementation of Address 126 127 #ifdef _LP64 128 129 Address Address::make_array(ArrayAddress adr) { 130 // Not implementable on 64bit machines 131 // Should have been handled higher up the call chain. 132 ShouldNotReachHere(); 133 return Address(); 134 } 135 136 // exceedingly dangerous constructor 137 Address::Address(int disp, address loc, relocInfo::relocType rtype) { 138 _base = noreg; 139 _index = noreg; 140 _scale = no_scale; 141 _disp = disp; 142 switch (rtype) { 143 case relocInfo::external_word_type: 144 _rspec = external_word_Relocation::spec(loc); 145 break; 146 case relocInfo::internal_word_type: 147 _rspec = internal_word_Relocation::spec(loc); 148 break; 149 case relocInfo::runtime_call_type: 150 // HMM 151 _rspec = runtime_call_Relocation::spec(); 152 break; 153 case relocInfo::poll_type: 154 case relocInfo::poll_return_type: 155 _rspec = Relocation::spec_simple(rtype); 156 break; 157 case relocInfo::none: 158 break; 159 default: 160 ShouldNotReachHere(); 161 } 162 } 163 #else // LP64 164 165 Address Address::make_array(ArrayAddress adr) { 166 AddressLiteral base = adr.base(); 167 Address index = adr.index(); 168 assert(index._disp == 0, "must not have disp"); // maybe it can? 169 Address array(index._base, index._index, index._scale, (intptr_t) base.target()); 170 array._rspec = base._rspec; 171 return array; 172 } 173 174 // exceedingly dangerous constructor 175 Address::Address(address loc, RelocationHolder spec) { 176 _base = noreg; 177 _index = noreg; 178 _scale = no_scale; 179 _disp = (intptr_t) loc; 180 _rspec = spec; 181 } 182 183 #endif // _LP64 184 185 186 187 // Convert the raw encoding form into the form expected by the constructor for 188 // Address. An index of 4 (rsp) corresponds to having no index, so convert 189 // that to noreg for the Address constructor. 190 Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) { 191 RelocationHolder rspec; 192 if (disp_reloc != relocInfo::none) { 193 rspec = Relocation::spec_simple(disp_reloc); 194 } 195 bool valid_index = index != rsp->encoding(); 196 if (valid_index) { 197 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp)); 198 madr._rspec = rspec; 199 return madr; 200 } else { 201 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp)); 202 madr._rspec = rspec; 203 return madr; 204 } 205 } 206 207 // Implementation of Assembler 208 209 int AbstractAssembler::code_fill_byte() { 210 return (u_char)'\xF4'; // hlt 211 } 212 213 // make this go away someday 214 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) { 215 if (rtype == relocInfo::none) 216 emit_int32(data); 217 else 218 emit_data(data, Relocation::spec_simple(rtype), format); 219 } 220 221 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) { 222 assert(imm_operand == 0, "default format must be immediate in this file"); 223 assert(inst_mark() != NULL, "must be inside InstructionMark"); 224 if (rspec.type() != relocInfo::none) { 225 #ifdef ASSERT 226 check_relocation(rspec, format); 227 #endif 228 // Do not use AbstractAssembler::relocate, which is not intended for 229 // embedded words. Instead, relocate to the enclosing instruction. 230 231 // hack. call32 is too wide for mask so use disp32 232 if (format == call32_operand) 233 code_section()->relocate(inst_mark(), rspec, disp32_operand); 234 else 235 code_section()->relocate(inst_mark(), rspec, format); 236 } 237 emit_int32(data); 238 } 239 240 static int encode(Register r) { 241 int enc = r->encoding(); 242 if (enc >= 8) { 243 enc -= 8; 244 } 245 return enc; 246 } 247 248 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) { 249 assert(dst->has_byte_register(), "must have byte register"); 250 assert(isByte(op1) && isByte(op2), "wrong opcode"); 251 assert(isByte(imm8), "not a byte"); 252 assert((op1 & 0x01) == 0, "should be 8bit operation"); 253 emit_int8(op1); 254 emit_int8(op2 | encode(dst)); 255 emit_int8(imm8); 256 } 257 258 259 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) { 260 assert(isByte(op1) && isByte(op2), "wrong opcode"); 261 assert((op1 & 0x01) == 1, "should be 32bit operation"); 262 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); 263 if (is8bit(imm32)) { 264 emit_int8(op1 | 0x02); // set sign bit 265 emit_int8(op2 | encode(dst)); 266 emit_int8(imm32 & 0xFF); 267 } else { 268 emit_int8(op1); 269 emit_int8(op2 | encode(dst)); 270 emit_int32(imm32); 271 } 272 } 273 274 // Force generation of a 4 byte immediate value even if it fits into 8bit 275 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) { 276 assert(isByte(op1) && isByte(op2), "wrong opcode"); 277 assert((op1 & 0x01) == 1, "should be 32bit operation"); 278 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); 279 emit_int8(op1); 280 emit_int8(op2 | encode(dst)); 281 emit_int32(imm32); 282 } 283 284 // immediate-to-memory forms 285 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) { 286 assert((op1 & 0x01) == 1, "should be 32bit operation"); 287 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); 288 if (is8bit(imm32)) { 289 emit_int8(op1 | 0x02); // set sign bit 290 emit_operand(rm, adr, 1); 291 emit_int8(imm32 & 0xFF); 292 } else { 293 emit_int8(op1); 294 emit_operand(rm, adr, 4); 295 emit_int32(imm32); 296 } 297 } 298 299 300 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) { 301 assert(isByte(op1) && isByte(op2), "wrong opcode"); 302 emit_int8(op1); 303 emit_int8(op2 | encode(dst) << 3 | encode(src)); 304 } 305 306 307 bool Assembler::query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len, 308 int cur_tuple_type, int in_size_in_bits, int cur_encoding) { 309 int mod_idx = 0; 310 // We will test if the displacement fits the compressed format and if so 311 // apply the compression to the displacment iff the result is8bit. 312 if (VM_Version::supports_evex() && is_evex_inst) { 313 switch (cur_tuple_type) { 314 case EVEX_FV: 315 if ((cur_encoding & VEX_W) == VEX_W) { 316 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2; 317 } else { 318 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0; 319 } 320 break; 321 322 case EVEX_HV: 323 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0; 324 break; 325 326 case EVEX_FVM: 327 break; 328 329 case EVEX_T1S: 330 switch (in_size_in_bits) { 331 case EVEX_8bit: 332 break; 333 334 case EVEX_16bit: 335 mod_idx = 1; 336 break; 337 338 case EVEX_32bit: 339 mod_idx = 2; 340 break; 341 342 case EVEX_64bit: 343 mod_idx = 3; 344 break; 345 } 346 break; 347 348 case EVEX_T1F: 349 case EVEX_T2: 350 case EVEX_T4: 351 mod_idx = (in_size_in_bits == EVEX_64bit) ? 1 : 0; 352 break; 353 354 case EVEX_T8: 355 break; 356 357 case EVEX_HVM: 358 break; 359 360 case EVEX_QVM: 361 break; 362 363 case EVEX_OVM: 364 break; 365 366 case EVEX_M128: 367 break; 368 369 case EVEX_DUP: 370 break; 371 372 default: 373 assert(0, "no valid evex tuple_table entry"); 374 break; 375 } 376 377 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) { 378 int disp_factor = tuple_table[cur_tuple_type + mod_idx][vector_len]; 379 if ((disp % disp_factor) == 0) { 380 int new_disp = disp / disp_factor; 381 if ((-0x80 <= new_disp && new_disp < 0x80)) { 382 disp = new_disp; 383 } 384 } else { 385 return false; 386 } 387 } 388 } 389 return (-0x80 <= disp && disp < 0x80); 390 } 391 392 393 bool Assembler::emit_compressed_disp_byte(int &disp) { 394 int mod_idx = 0; 395 // We will test if the displacement fits the compressed format and if so 396 // apply the compression to the displacment iff the result is8bit. 397 if (VM_Version::supports_evex() && _attributes && _attributes->is_evex_instruction()) { 398 int evex_encoding = _attributes->get_evex_encoding(); 399 int tuple_type = _attributes->get_tuple_type(); 400 switch (tuple_type) { 401 case EVEX_FV: 402 if ((evex_encoding & VEX_W) == VEX_W) { 403 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2; 404 } else { 405 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0; 406 } 407 break; 408 409 case EVEX_HV: 410 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0; 411 break; 412 413 case EVEX_FVM: 414 break; 415 416 case EVEX_T1S: 417 switch (_attributes->get_input_size()) { 418 case EVEX_8bit: 419 break; 420 421 case EVEX_16bit: 422 mod_idx = 1; 423 break; 424 425 case EVEX_32bit: 426 mod_idx = 2; 427 break; 428 429 case EVEX_64bit: 430 mod_idx = 3; 431 break; 432 } 433 break; 434 435 case EVEX_T1F: 436 case EVEX_T2: 437 case EVEX_T4: 438 mod_idx = (_attributes->get_input_size() == EVEX_64bit) ? 1 : 0; 439 break; 440 441 case EVEX_T8: 442 break; 443 444 case EVEX_HVM: 445 break; 446 447 case EVEX_QVM: 448 break; 449 450 case EVEX_OVM: 451 break; 452 453 case EVEX_M128: 454 break; 455 456 case EVEX_DUP: 457 break; 458 459 default: 460 assert(0, "no valid evex tuple_table entry"); 461 break; 462 } 463 464 int vector_len = _attributes->get_vector_len(); 465 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) { 466 int disp_factor = tuple_table[tuple_type + mod_idx][vector_len]; 467 if ((disp % disp_factor) == 0) { 468 int new_disp = disp / disp_factor; 469 if (is8bit(new_disp)) { 470 disp = new_disp; 471 } 472 } else { 473 return false; 474 } 475 } 476 } 477 return is8bit(disp); 478 } 479 480 481 void Assembler::emit_operand(Register reg, Register base, Register index, 482 Address::ScaleFactor scale, int disp, 483 RelocationHolder const& rspec, 484 int rip_relative_correction) { 485 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type(); 486 487 // Encode the registers as needed in the fields they are used in 488 489 int regenc = encode(reg) << 3; 490 int indexenc = index->is_valid() ? encode(index) << 3 : 0; 491 int baseenc = base->is_valid() ? encode(base) : 0; 492 493 if (base->is_valid()) { 494 if (index->is_valid()) { 495 assert(scale != Address::no_scale, "inconsistent address"); 496 // [base + index*scale + disp] 497 if (disp == 0 && rtype == relocInfo::none && 498 base != rbp LP64_ONLY(&& base != r13)) { 499 // [base + index*scale] 500 // [00 reg 100][ss index base] 501 assert(index != rsp, "illegal addressing mode"); 502 emit_int8(0x04 | regenc); 503 emit_int8(scale << 6 | indexenc | baseenc); 504 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) { 505 // [base + index*scale + imm8] 506 // [01 reg 100][ss index base] imm8 507 assert(index != rsp, "illegal addressing mode"); 508 emit_int8(0x44 | regenc); 509 emit_int8(scale << 6 | indexenc | baseenc); 510 emit_int8(disp & 0xFF); 511 } else { 512 // [base + index*scale + disp32] 513 // [10 reg 100][ss index base] disp32 514 assert(index != rsp, "illegal addressing mode"); 515 emit_int8(0x84 | regenc); 516 emit_int8(scale << 6 | indexenc | baseenc); 517 emit_data(disp, rspec, disp32_operand); 518 } 519 } else if (base == rsp LP64_ONLY(|| base == r12)) { 520 // [rsp + disp] 521 if (disp == 0 && rtype == relocInfo::none) { 522 // [rsp] 523 // [00 reg 100][00 100 100] 524 emit_int8(0x04 | regenc); 525 emit_int8(0x24); 526 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) { 527 // [rsp + imm8] 528 // [01 reg 100][00 100 100] disp8 529 emit_int8(0x44 | regenc); 530 emit_int8(0x24); 531 emit_int8(disp & 0xFF); 532 } else { 533 // [rsp + imm32] 534 // [10 reg 100][00 100 100] disp32 535 emit_int8(0x84 | regenc); 536 emit_int8(0x24); 537 emit_data(disp, rspec, disp32_operand); 538 } 539 } else { 540 // [base + disp] 541 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode"); 542 if (disp == 0 && rtype == relocInfo::none && 543 base != rbp LP64_ONLY(&& base != r13)) { 544 // [base] 545 // [00 reg base] 546 emit_int8(0x00 | regenc | baseenc); 547 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) { 548 // [base + disp8] 549 // [01 reg base] disp8 550 emit_int8(0x40 | regenc | baseenc); 551 emit_int8(disp & 0xFF); 552 } else { 553 // [base + disp32] 554 // [10 reg base] disp32 555 emit_int8(0x80 | regenc | baseenc); 556 emit_data(disp, rspec, disp32_operand); 557 } 558 } 559 } else { 560 if (index->is_valid()) { 561 assert(scale != Address::no_scale, "inconsistent address"); 562 // [index*scale + disp] 563 // [00 reg 100][ss index 101] disp32 564 assert(index != rsp, "illegal addressing mode"); 565 emit_int8(0x04 | regenc); 566 emit_int8(scale << 6 | indexenc | 0x05); 567 emit_data(disp, rspec, disp32_operand); 568 } else if (rtype != relocInfo::none ) { 569 // [disp] (64bit) RIP-RELATIVE (32bit) abs 570 // [00 000 101] disp32 571 572 emit_int8(0x05 | regenc); 573 // Note that the RIP-rel. correction applies to the generated 574 // disp field, but _not_ to the target address in the rspec. 575 576 // disp was created by converting the target address minus the pc 577 // at the start of the instruction. That needs more correction here. 578 // intptr_t disp = target - next_ip; 579 assert(inst_mark() != NULL, "must be inside InstructionMark"); 580 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction; 581 int64_t adjusted = disp; 582 // Do rip-rel adjustment for 64bit 583 LP64_ONLY(adjusted -= (next_ip - inst_mark())); 584 assert(is_simm32(adjusted), 585 "must be 32bit offset (RIP relative address)"); 586 emit_data((int32_t) adjusted, rspec, disp32_operand); 587 588 } else { 589 // 32bit never did this, did everything as the rip-rel/disp code above 590 // [disp] ABSOLUTE 591 // [00 reg 100][00 100 101] disp32 592 emit_int8(0x04 | regenc); 593 emit_int8(0x25); 594 emit_data(disp, rspec, disp32_operand); 595 } 596 } 597 } 598 599 void Assembler::emit_operand(XMMRegister reg, Register base, Register index, 600 Address::ScaleFactor scale, int disp, 601 RelocationHolder const& rspec) { 602 if (UseAVX > 2) { 603 int xreg_enc = reg->encoding(); 604 if (xreg_enc > 15) { 605 XMMRegister new_reg = as_XMMRegister(xreg_enc & 0xf); 606 emit_operand((Register)new_reg, base, index, scale, disp, rspec); 607 return; 608 } 609 } 610 emit_operand((Register)reg, base, index, scale, disp, rspec); 611 } 612 613 // Secret local extension to Assembler::WhichOperand: 614 #define end_pc_operand (_WhichOperand_limit) 615 616 address Assembler::locate_operand(address inst, WhichOperand which) { 617 // Decode the given instruction, and return the address of 618 // an embedded 32-bit operand word. 619 620 // If "which" is disp32_operand, selects the displacement portion 621 // of an effective address specifier. 622 // If "which" is imm64_operand, selects the trailing immediate constant. 623 // If "which" is call32_operand, selects the displacement of a call or jump. 624 // Caller is responsible for ensuring that there is such an operand, 625 // and that it is 32/64 bits wide. 626 627 // If "which" is end_pc_operand, find the end of the instruction. 628 629 address ip = inst; 630 bool is_64bit = false; 631 632 debug_only(bool has_disp32 = false); 633 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn 634 635 again_after_prefix: 636 switch (0xFF & *ip++) { 637 638 // These convenience macros generate groups of "case" labels for the switch. 639 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3 640 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \ 641 case (x)+4: case (x)+5: case (x)+6: case (x)+7 642 #define REP16(x) REP8((x)+0): \ 643 case REP8((x)+8) 644 645 case CS_segment: 646 case SS_segment: 647 case DS_segment: 648 case ES_segment: 649 case FS_segment: 650 case GS_segment: 651 // Seems dubious 652 LP64_ONLY(assert(false, "shouldn't have that prefix")); 653 assert(ip == inst+1, "only one prefix allowed"); 654 goto again_after_prefix; 655 656 case 0x67: 657 case REX: 658 case REX_B: 659 case REX_X: 660 case REX_XB: 661 case REX_R: 662 case REX_RB: 663 case REX_RX: 664 case REX_RXB: 665 NOT_LP64(assert(false, "64bit prefixes")); 666 goto again_after_prefix; 667 668 case REX_W: 669 case REX_WB: 670 case REX_WX: 671 case REX_WXB: 672 case REX_WR: 673 case REX_WRB: 674 case REX_WRX: 675 case REX_WRXB: 676 NOT_LP64(assert(false, "64bit prefixes")); 677 is_64bit = true; 678 goto again_after_prefix; 679 680 case 0xFF: // pushq a; decl a; incl a; call a; jmp a 681 case 0x88: // movb a, r 682 case 0x89: // movl a, r 683 case 0x8A: // movb r, a 684 case 0x8B: // movl r, a 685 case 0x8F: // popl a 686 debug_only(has_disp32 = true); 687 break; 688 689 case 0x68: // pushq #32 690 if (which == end_pc_operand) { 691 return ip + 4; 692 } 693 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate"); 694 return ip; // not produced by emit_operand 695 696 case 0x66: // movw ... (size prefix) 697 again_after_size_prefix2: 698 switch (0xFF & *ip++) { 699 case REX: 700 case REX_B: 701 case REX_X: 702 case REX_XB: 703 case REX_R: 704 case REX_RB: 705 case REX_RX: 706 case REX_RXB: 707 case REX_W: 708 case REX_WB: 709 case REX_WX: 710 case REX_WXB: 711 case REX_WR: 712 case REX_WRB: 713 case REX_WRX: 714 case REX_WRXB: 715 NOT_LP64(assert(false, "64bit prefix found")); 716 goto again_after_size_prefix2; 717 case 0x8B: // movw r, a 718 case 0x89: // movw a, r 719 debug_only(has_disp32 = true); 720 break; 721 case 0xC7: // movw a, #16 722 debug_only(has_disp32 = true); 723 tail_size = 2; // the imm16 724 break; 725 case 0x0F: // several SSE/SSE2 variants 726 ip--; // reparse the 0x0F 727 goto again_after_prefix; 728 default: 729 ShouldNotReachHere(); 730 } 731 break; 732 733 case REP8(0xB8): // movl/q r, #32/#64(oop?) 734 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4); 735 // these asserts are somewhat nonsensical 736 #ifndef _LP64 737 assert(which == imm_operand || which == disp32_operand, 738 "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip)); 739 #else 740 assert((which == call32_operand || which == imm_operand) && is_64bit || 741 which == narrow_oop_operand && !is_64bit, 742 "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip)); 743 #endif // _LP64 744 return ip; 745 746 case 0x69: // imul r, a, #32 747 case 0xC7: // movl a, #32(oop?) 748 tail_size = 4; 749 debug_only(has_disp32 = true); // has both kinds of operands! 750 break; 751 752 case 0x0F: // movx..., etc. 753 switch (0xFF & *ip++) { 754 case 0x3A: // pcmpestri 755 tail_size = 1; 756 case 0x38: // ptest, pmovzxbw 757 ip++; // skip opcode 758 debug_only(has_disp32 = true); // has both kinds of operands! 759 break; 760 761 case 0x70: // pshufd r, r/a, #8 762 debug_only(has_disp32 = true); // has both kinds of operands! 763 case 0x73: // psrldq r, #8 764 tail_size = 1; 765 break; 766 767 case 0x12: // movlps 768 case 0x28: // movaps 769 case 0x2E: // ucomiss 770 case 0x2F: // comiss 771 case 0x54: // andps 772 case 0x55: // andnps 773 case 0x56: // orps 774 case 0x57: // xorps 775 case 0x58: // addpd 776 case 0x59: // mulpd 777 case 0x6E: // movd 778 case 0x7E: // movd 779 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush 780 case 0xFE: // paddd 781 debug_only(has_disp32 = true); 782 break; 783 784 case 0xAD: // shrd r, a, %cl 785 case 0xAF: // imul r, a 786 case 0xBE: // movsbl r, a (movsxb) 787 case 0xBF: // movswl r, a (movsxw) 788 case 0xB6: // movzbl r, a (movzxb) 789 case 0xB7: // movzwl r, a (movzxw) 790 case REP16(0x40): // cmovl cc, r, a 791 case 0xB0: // cmpxchgb 792 case 0xB1: // cmpxchg 793 case 0xC1: // xaddl 794 case 0xC7: // cmpxchg8 795 case REP16(0x90): // setcc a 796 debug_only(has_disp32 = true); 797 // fall out of the switch to decode the address 798 break; 799 800 case 0xC4: // pinsrw r, a, #8 801 debug_only(has_disp32 = true); 802 case 0xC5: // pextrw r, r, #8 803 tail_size = 1; // the imm8 804 break; 805 806 case 0xAC: // shrd r, a, #8 807 debug_only(has_disp32 = true); 808 tail_size = 1; // the imm8 809 break; 810 811 case REP16(0x80): // jcc rdisp32 812 if (which == end_pc_operand) return ip + 4; 813 assert(which == call32_operand, "jcc has no disp32 or imm"); 814 return ip; 815 default: 816 ShouldNotReachHere(); 817 } 818 break; 819 820 case 0x81: // addl a, #32; addl r, #32 821 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl 822 // on 32bit in the case of cmpl, the imm might be an oop 823 tail_size = 4; 824 debug_only(has_disp32 = true); // has both kinds of operands! 825 break; 826 827 case 0x83: // addl a, #8; addl r, #8 828 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl 829 debug_only(has_disp32 = true); // has both kinds of operands! 830 tail_size = 1; 831 break; 832 833 case 0x9B: 834 switch (0xFF & *ip++) { 835 case 0xD9: // fnstcw a 836 debug_only(has_disp32 = true); 837 break; 838 default: 839 ShouldNotReachHere(); 840 } 841 break; 842 843 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a 844 case REP4(0x10): // adc... 845 case REP4(0x20): // and... 846 case REP4(0x30): // xor... 847 case REP4(0x08): // or... 848 case REP4(0x18): // sbb... 849 case REP4(0x28): // sub... 850 case 0xF7: // mull a 851 case 0x8D: // lea r, a 852 case 0x87: // xchg r, a 853 case REP4(0x38): // cmp... 854 case 0x85: // test r, a 855 debug_only(has_disp32 = true); // has both kinds of operands! 856 break; 857 858 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8 859 case 0xC6: // movb a, #8 860 case 0x80: // cmpb a, #8 861 case 0x6B: // imul r, a, #8 862 debug_only(has_disp32 = true); // has both kinds of operands! 863 tail_size = 1; // the imm8 864 break; 865 866 case 0xC4: // VEX_3bytes 867 case 0xC5: // VEX_2bytes 868 assert((UseAVX > 0), "shouldn't have VEX prefix"); 869 assert(ip == inst+1, "no prefixes allowed"); 870 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions 871 // but they have prefix 0x0F and processed when 0x0F processed above. 872 // 873 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES 874 // instructions (these instructions are not supported in 64-bit mode). 875 // To distinguish them bits [7:6] are set in the VEX second byte since 876 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set 877 // those VEX bits REX and vvvv bits are inverted. 878 // 879 // Fortunately C2 doesn't generate these instructions so we don't need 880 // to check for them in product version. 881 882 // Check second byte 883 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions")); 884 885 int vex_opcode; 886 // First byte 887 if ((0xFF & *inst) == VEX_3bytes) { 888 vex_opcode = VEX_OPCODE_MASK & *ip; 889 ip++; // third byte 890 is_64bit = ((VEX_W & *ip) == VEX_W); 891 } else { 892 vex_opcode = VEX_OPCODE_0F; 893 } 894 ip++; // opcode 895 // To find the end of instruction (which == end_pc_operand). 896 switch (vex_opcode) { 897 case VEX_OPCODE_0F: 898 switch (0xFF & *ip) { 899 case 0x70: // pshufd r, r/a, #8 900 case 0x71: // ps[rl|ra|ll]w r, #8 901 case 0x72: // ps[rl|ra|ll]d r, #8 902 case 0x73: // ps[rl|ra|ll]q r, #8 903 case 0xC2: // cmp[ps|pd|ss|sd] r, r, r/a, #8 904 case 0xC4: // pinsrw r, r, r/a, #8 905 case 0xC5: // pextrw r/a, r, #8 906 case 0xC6: // shufp[s|d] r, r, r/a, #8 907 tail_size = 1; // the imm8 908 break; 909 } 910 break; 911 case VEX_OPCODE_0F_3A: 912 tail_size = 1; 913 break; 914 } 915 ip++; // skip opcode 916 debug_only(has_disp32 = true); // has both kinds of operands! 917 break; 918 919 case 0x62: // EVEX_4bytes 920 assert(VM_Version::supports_evex(), "shouldn't have EVEX prefix"); 921 assert(ip == inst+1, "no prefixes allowed"); 922 // no EVEX collisions, all instructions that have 0x62 opcodes 923 // have EVEX versions and are subopcodes of 0x66 924 ip++; // skip P0 and exmaine W in P1 925 is_64bit = ((VEX_W & *ip) == VEX_W); 926 ip++; // move to P2 927 ip++; // skip P2, move to opcode 928 // To find the end of instruction (which == end_pc_operand). 929 switch (0xFF & *ip) { 930 case 0x22: // pinsrd r, r/a, #8 931 case 0x61: // pcmpestri r, r/a, #8 932 case 0x70: // pshufd r, r/a, #8 933 case 0x73: // psrldq r, #8 934 tail_size = 1; // the imm8 935 break; 936 default: 937 break; 938 } 939 ip++; // skip opcode 940 debug_only(has_disp32 = true); // has both kinds of operands! 941 break; 942 943 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1 944 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl 945 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a 946 case 0xDD: // fld_d a; fst_d a; fstp_d a 947 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a 948 case 0xDF: // fild_d a; fistp_d a 949 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a 950 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a 951 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a 952 debug_only(has_disp32 = true); 953 break; 954 955 case 0xE8: // call rdisp32 956 case 0xE9: // jmp rdisp32 957 if (which == end_pc_operand) return ip + 4; 958 assert(which == call32_operand, "call has no disp32 or imm"); 959 return ip; 960 961 case 0xF0: // Lock 962 assert(os::is_MP(), "only on MP"); 963 goto again_after_prefix; 964 965 case 0xF3: // For SSE 966 case 0xF2: // For SSE2 967 switch (0xFF & *ip++) { 968 case REX: 969 case REX_B: 970 case REX_X: 971 case REX_XB: 972 case REX_R: 973 case REX_RB: 974 case REX_RX: 975 case REX_RXB: 976 case REX_W: 977 case REX_WB: 978 case REX_WX: 979 case REX_WXB: 980 case REX_WR: 981 case REX_WRB: 982 case REX_WRX: 983 case REX_WRXB: 984 NOT_LP64(assert(false, "found 64bit prefix")); 985 ip++; 986 default: 987 ip++; 988 } 989 debug_only(has_disp32 = true); // has both kinds of operands! 990 break; 991 992 default: 993 ShouldNotReachHere(); 994 995 #undef REP8 996 #undef REP16 997 } 998 999 assert(which != call32_operand, "instruction is not a call, jmp, or jcc"); 1000 #ifdef _LP64 1001 assert(which != imm_operand, "instruction is not a movq reg, imm64"); 1002 #else 1003 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field"); 1004 assert(which != imm_operand || has_disp32, "instruction has no imm32 field"); 1005 #endif // LP64 1006 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field"); 1007 1008 // parse the output of emit_operand 1009 int op2 = 0xFF & *ip++; 1010 int base = op2 & 0x07; 1011 int op3 = -1; 1012 const int b100 = 4; 1013 const int b101 = 5; 1014 if (base == b100 && (op2 >> 6) != 3) { 1015 op3 = 0xFF & *ip++; 1016 base = op3 & 0x07; // refetch the base 1017 } 1018 // now ip points at the disp (if any) 1019 1020 switch (op2 >> 6) { 1021 case 0: 1022 // [00 reg 100][ss index base] 1023 // [00 reg 100][00 100 esp] 1024 // [00 reg base] 1025 // [00 reg 100][ss index 101][disp32] 1026 // [00 reg 101] [disp32] 1027 1028 if (base == b101) { 1029 if (which == disp32_operand) 1030 return ip; // caller wants the disp32 1031 ip += 4; // skip the disp32 1032 } 1033 break; 1034 1035 case 1: 1036 // [01 reg 100][ss index base][disp8] 1037 // [01 reg 100][00 100 esp][disp8] 1038 // [01 reg base] [disp8] 1039 ip += 1; // skip the disp8 1040 break; 1041 1042 case 2: 1043 // [10 reg 100][ss index base][disp32] 1044 // [10 reg 100][00 100 esp][disp32] 1045 // [10 reg base] [disp32] 1046 if (which == disp32_operand) 1047 return ip; // caller wants the disp32 1048 ip += 4; // skip the disp32 1049 break; 1050 1051 case 3: 1052 // [11 reg base] (not a memory addressing mode) 1053 break; 1054 } 1055 1056 if (which == end_pc_operand) { 1057 return ip + tail_size; 1058 } 1059 1060 #ifdef _LP64 1061 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32"); 1062 #else 1063 assert(which == imm_operand, "instruction has only an imm field"); 1064 #endif // LP64 1065 return ip; 1066 } 1067 1068 address Assembler::locate_next_instruction(address inst) { 1069 // Secretly share code with locate_operand: 1070 return locate_operand(inst, end_pc_operand); 1071 } 1072 1073 1074 #ifdef ASSERT 1075 void Assembler::check_relocation(RelocationHolder const& rspec, int format) { 1076 address inst = inst_mark(); 1077 assert(inst != NULL && inst < pc(), "must point to beginning of instruction"); 1078 address opnd; 1079 1080 Relocation* r = rspec.reloc(); 1081 if (r->type() == relocInfo::none) { 1082 return; 1083 } else if (r->is_call() || format == call32_operand) { 1084 // assert(format == imm32_operand, "cannot specify a nonzero format"); 1085 opnd = locate_operand(inst, call32_operand); 1086 } else if (r->is_data()) { 1087 assert(format == imm_operand || format == disp32_operand 1088 LP64_ONLY(|| format == narrow_oop_operand), "format ok"); 1089 opnd = locate_operand(inst, (WhichOperand)format); 1090 } else { 1091 assert(format == imm_operand, "cannot specify a format"); 1092 return; 1093 } 1094 assert(opnd == pc(), "must put operand where relocs can find it"); 1095 } 1096 #endif // ASSERT 1097 1098 void Assembler::emit_operand32(Register reg, Address adr) { 1099 assert(reg->encoding() < 8, "no extended registers"); 1100 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); 1101 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, 1102 adr._rspec); 1103 } 1104 1105 void Assembler::emit_operand(Register reg, Address adr, 1106 int rip_relative_correction) { 1107 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, 1108 adr._rspec, 1109 rip_relative_correction); 1110 } 1111 1112 void Assembler::emit_operand(XMMRegister reg, Address adr) { 1113 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, 1114 adr._rspec); 1115 } 1116 1117 // MMX operations 1118 void Assembler::emit_operand(MMXRegister reg, Address adr) { 1119 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); 1120 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec); 1121 } 1122 1123 // work around gcc (3.2.1-7a) bug 1124 void Assembler::emit_operand(Address adr, MMXRegister reg) { 1125 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); 1126 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec); 1127 } 1128 1129 1130 void Assembler::emit_farith(int b1, int b2, int i) { 1131 assert(isByte(b1) && isByte(b2), "wrong opcode"); 1132 assert(0 <= i && i < 8, "illegal stack offset"); 1133 emit_int8(b1); 1134 emit_int8(b2 + i); 1135 } 1136 1137 1138 // Now the Assembler instructions (identical for 32/64 bits) 1139 1140 void Assembler::adcl(Address dst, int32_t imm32) { 1141 InstructionMark im(this); 1142 prefix(dst); 1143 emit_arith_operand(0x81, rdx, dst, imm32); 1144 } 1145 1146 void Assembler::adcl(Address dst, Register src) { 1147 InstructionMark im(this); 1148 prefix(dst, src); 1149 emit_int8(0x11); 1150 emit_operand(src, dst); 1151 } 1152 1153 void Assembler::adcl(Register dst, int32_t imm32) { 1154 prefix(dst); 1155 emit_arith(0x81, 0xD0, dst, imm32); 1156 } 1157 1158 void Assembler::adcl(Register dst, Address src) { 1159 InstructionMark im(this); 1160 prefix(src, dst); 1161 emit_int8(0x13); 1162 emit_operand(dst, src); 1163 } 1164 1165 void Assembler::adcl(Register dst, Register src) { 1166 (void) prefix_and_encode(dst->encoding(), src->encoding()); 1167 emit_arith(0x13, 0xC0, dst, src); 1168 } 1169 1170 void Assembler::addl(Address dst, int32_t imm32) { 1171 InstructionMark im(this); 1172 prefix(dst); 1173 emit_arith_operand(0x81, rax, dst, imm32); 1174 } 1175 1176 void Assembler::addb(Address dst, int imm8) { 1177 InstructionMark im(this); 1178 prefix(dst); 1179 emit_int8((unsigned char)0x80); 1180 emit_operand(rax, dst, 1); 1181 emit_int8(imm8); 1182 } 1183 1184 void Assembler::addw(Address dst, int imm16) { 1185 InstructionMark im(this); 1186 emit_int8(0x66); 1187 prefix(dst); 1188 emit_int8((unsigned char)0x81); 1189 emit_operand(rax, dst, 2); 1190 emit_int16(imm16); 1191 } 1192 1193 void Assembler::addl(Address dst, Register src) { 1194 InstructionMark im(this); 1195 prefix(dst, src); 1196 emit_int8(0x01); 1197 emit_operand(src, dst); 1198 } 1199 1200 void Assembler::addl(Register dst, int32_t imm32) { 1201 prefix(dst); 1202 emit_arith(0x81, 0xC0, dst, imm32); 1203 } 1204 1205 void Assembler::addl(Register dst, Address src) { 1206 InstructionMark im(this); 1207 prefix(src, dst); 1208 emit_int8(0x03); 1209 emit_operand(dst, src); 1210 } 1211 1212 void Assembler::addl(Register dst, Register src) { 1213 (void) prefix_and_encode(dst->encoding(), src->encoding()); 1214 emit_arith(0x03, 0xC0, dst, src); 1215 } 1216 1217 void Assembler::addr_nop_4() { 1218 assert(UseAddressNop, "no CPU support"); 1219 // 4 bytes: NOP DWORD PTR [EAX+0] 1220 emit_int8(0x0F); 1221 emit_int8(0x1F); 1222 emit_int8(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc); 1223 emit_int8(0); // 8-bits offset (1 byte) 1224 } 1225 1226 void Assembler::addr_nop_5() { 1227 assert(UseAddressNop, "no CPU support"); 1228 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset 1229 emit_int8(0x0F); 1230 emit_int8(0x1F); 1231 emit_int8(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4); 1232 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc); 1233 emit_int8(0); // 8-bits offset (1 byte) 1234 } 1235 1236 void Assembler::addr_nop_7() { 1237 assert(UseAddressNop, "no CPU support"); 1238 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset 1239 emit_int8(0x0F); 1240 emit_int8(0x1F); 1241 emit_int8((unsigned char)0x80); 1242 // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc); 1243 emit_int32(0); // 32-bits offset (4 bytes) 1244 } 1245 1246 void Assembler::addr_nop_8() { 1247 assert(UseAddressNop, "no CPU support"); 1248 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset 1249 emit_int8(0x0F); 1250 emit_int8(0x1F); 1251 emit_int8((unsigned char)0x84); 1252 // emit_rm(cbuf, 0x2, EAX_enc, 0x4); 1253 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc); 1254 emit_int32(0); // 32-bits offset (4 bytes) 1255 } 1256 1257 void Assembler::addsd(XMMRegister dst, XMMRegister src) { 1258 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1259 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1260 attributes.set_rex_vex_w_reverted(); 1261 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 1262 emit_int8(0x58); 1263 emit_int8((unsigned char)(0xC0 | encode)); 1264 } 1265 1266 void Assembler::addsd(XMMRegister dst, Address src) { 1267 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1268 InstructionMark im(this); 1269 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1270 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 1271 attributes.set_rex_vex_w_reverted(); 1272 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 1273 emit_int8(0x58); 1274 emit_operand(dst, src); 1275 } 1276 1277 void Assembler::addss(XMMRegister dst, XMMRegister src) { 1278 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1279 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1280 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 1281 emit_int8(0x58); 1282 emit_int8((unsigned char)(0xC0 | encode)); 1283 } 1284 1285 void Assembler::addss(XMMRegister dst, Address src) { 1286 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1287 InstructionMark im(this); 1288 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1289 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 1290 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 1291 emit_int8(0x58); 1292 emit_operand(dst, src); 1293 } 1294 1295 void Assembler::aesdec(XMMRegister dst, Address src) { 1296 assert(VM_Version::supports_aes(), ""); 1297 InstructionMark im(this); 1298 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 1299 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 1300 emit_int8((unsigned char)0xDE); 1301 emit_operand(dst, src); 1302 } 1303 1304 void Assembler::aesdec(XMMRegister dst, XMMRegister src) { 1305 assert(VM_Version::supports_aes(), ""); 1306 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 1307 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 1308 emit_int8((unsigned char)0xDE); 1309 emit_int8(0xC0 | encode); 1310 } 1311 1312 void Assembler::aesdeclast(XMMRegister dst, Address src) { 1313 assert(VM_Version::supports_aes(), ""); 1314 InstructionMark im(this); 1315 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 1316 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 1317 emit_int8((unsigned char)0xDF); 1318 emit_operand(dst, src); 1319 } 1320 1321 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) { 1322 assert(VM_Version::supports_aes(), ""); 1323 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 1324 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 1325 emit_int8((unsigned char)0xDF); 1326 emit_int8((unsigned char)(0xC0 | encode)); 1327 } 1328 1329 void Assembler::aesenc(XMMRegister dst, Address src) { 1330 assert(VM_Version::supports_aes(), ""); 1331 InstructionMark im(this); 1332 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 1333 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 1334 emit_int8((unsigned char)0xDC); 1335 emit_operand(dst, src); 1336 } 1337 1338 void Assembler::aesenc(XMMRegister dst, XMMRegister src) { 1339 assert(VM_Version::supports_aes(), ""); 1340 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 1341 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 1342 emit_int8((unsigned char)0xDC); 1343 emit_int8(0xC0 | encode); 1344 } 1345 1346 void Assembler::aesenclast(XMMRegister dst, Address src) { 1347 assert(VM_Version::supports_aes(), ""); 1348 InstructionMark im(this); 1349 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 1350 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 1351 emit_int8((unsigned char)0xDD); 1352 emit_operand(dst, src); 1353 } 1354 1355 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) { 1356 assert(VM_Version::supports_aes(), ""); 1357 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 1358 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 1359 emit_int8((unsigned char)0xDD); 1360 emit_int8((unsigned char)(0xC0 | encode)); 1361 } 1362 1363 void Assembler::andl(Address dst, int32_t imm32) { 1364 InstructionMark im(this); 1365 prefix(dst); 1366 emit_int8((unsigned char)0x81); 1367 emit_operand(rsp, dst, 4); 1368 emit_int32(imm32); 1369 } 1370 1371 void Assembler::andl(Register dst, int32_t imm32) { 1372 prefix(dst); 1373 emit_arith(0x81, 0xE0, dst, imm32); 1374 } 1375 1376 void Assembler::andl(Register dst, Address src) { 1377 InstructionMark im(this); 1378 prefix(src, dst); 1379 emit_int8(0x23); 1380 emit_operand(dst, src); 1381 } 1382 1383 void Assembler::andl(Register dst, Register src) { 1384 (void) prefix_and_encode(dst->encoding(), src->encoding()); 1385 emit_arith(0x23, 0xC0, dst, src); 1386 } 1387 1388 void Assembler::andnl(Register dst, Register src1, Register src2) { 1389 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 1390 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 1391 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 1392 emit_int8((unsigned char)0xF2); 1393 emit_int8((unsigned char)(0xC0 | encode)); 1394 } 1395 1396 void Assembler::andnl(Register dst, Register src1, Address src2) { 1397 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 1398 InstructionMark im(this); 1399 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 1400 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 1401 emit_int8((unsigned char)0xF2); 1402 emit_operand(dst, src2); 1403 } 1404 1405 void Assembler::bsfl(Register dst, Register src) { 1406 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 1407 emit_int8(0x0F); 1408 emit_int8((unsigned char)0xBC); 1409 emit_int8((unsigned char)(0xC0 | encode)); 1410 } 1411 1412 void Assembler::bsrl(Register dst, Register src) { 1413 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 1414 emit_int8(0x0F); 1415 emit_int8((unsigned char)0xBD); 1416 emit_int8((unsigned char)(0xC0 | encode)); 1417 } 1418 1419 void Assembler::bswapl(Register reg) { // bswap 1420 int encode = prefix_and_encode(reg->encoding()); 1421 emit_int8(0x0F); 1422 emit_int8((unsigned char)(0xC8 | encode)); 1423 } 1424 1425 void Assembler::blsil(Register dst, Register src) { 1426 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 1427 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 1428 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 1429 emit_int8((unsigned char)0xF3); 1430 emit_int8((unsigned char)(0xC0 | encode)); 1431 } 1432 1433 void Assembler::blsil(Register dst, Address src) { 1434 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 1435 InstructionMark im(this); 1436 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 1437 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 1438 emit_int8((unsigned char)0xF3); 1439 emit_operand(rbx, src); 1440 } 1441 1442 void Assembler::blsmskl(Register dst, Register src) { 1443 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 1444 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 1445 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 1446 emit_int8((unsigned char)0xF3); 1447 emit_int8((unsigned char)(0xC0 | encode)); 1448 } 1449 1450 void Assembler::blsmskl(Register dst, Address src) { 1451 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 1452 InstructionMark im(this); 1453 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 1454 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 1455 emit_int8((unsigned char)0xF3); 1456 emit_operand(rdx, src); 1457 } 1458 1459 void Assembler::blsrl(Register dst, Register src) { 1460 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 1461 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 1462 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 1463 emit_int8((unsigned char)0xF3); 1464 emit_int8((unsigned char)(0xC0 | encode)); 1465 } 1466 1467 void Assembler::blsrl(Register dst, Address src) { 1468 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 1469 InstructionMark im(this); 1470 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 1471 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 1472 emit_int8((unsigned char)0xF3); 1473 emit_operand(rcx, src); 1474 } 1475 1476 void Assembler::call(Label& L, relocInfo::relocType rtype) { 1477 // suspect disp32 is always good 1478 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand); 1479 1480 if (L.is_bound()) { 1481 const int long_size = 5; 1482 int offs = (int)( target(L) - pc() ); 1483 assert(offs <= 0, "assembler error"); 1484 InstructionMark im(this); 1485 // 1110 1000 #32-bit disp 1486 emit_int8((unsigned char)0xE8); 1487 emit_data(offs - long_size, rtype, operand); 1488 } else { 1489 InstructionMark im(this); 1490 // 1110 1000 #32-bit disp 1491 L.add_patch_at(code(), locator()); 1492 1493 emit_int8((unsigned char)0xE8); 1494 emit_data(int(0), rtype, operand); 1495 } 1496 } 1497 1498 void Assembler::call(Register dst) { 1499 int encode = prefix_and_encode(dst->encoding()); 1500 emit_int8((unsigned char)0xFF); 1501 emit_int8((unsigned char)(0xD0 | encode)); 1502 } 1503 1504 1505 void Assembler::call(Address adr) { 1506 InstructionMark im(this); 1507 prefix(adr); 1508 emit_int8((unsigned char)0xFF); 1509 emit_operand(rdx, adr); 1510 } 1511 1512 void Assembler::call_literal(address entry, RelocationHolder const& rspec) { 1513 assert(entry != NULL, "call most probably wrong"); 1514 InstructionMark im(this); 1515 emit_int8((unsigned char)0xE8); 1516 intptr_t disp = entry - (pc() + sizeof(int32_t)); 1517 assert(is_simm32(disp), "must be 32bit offset (call2)"); 1518 // Technically, should use call32_operand, but this format is 1519 // implied by the fact that we're emitting a call instruction. 1520 1521 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand); 1522 emit_data((int) disp, rspec, operand); 1523 } 1524 1525 void Assembler::cdql() { 1526 emit_int8((unsigned char)0x99); 1527 } 1528 1529 void Assembler::cld() { 1530 emit_int8((unsigned char)0xFC); 1531 } 1532 1533 void Assembler::cmovl(Condition cc, Register dst, Register src) { 1534 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction")); 1535 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 1536 emit_int8(0x0F); 1537 emit_int8(0x40 | cc); 1538 emit_int8((unsigned char)(0xC0 | encode)); 1539 } 1540 1541 1542 void Assembler::cmovl(Condition cc, Register dst, Address src) { 1543 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction")); 1544 prefix(src, dst); 1545 emit_int8(0x0F); 1546 emit_int8(0x40 | cc); 1547 emit_operand(dst, src); 1548 } 1549 1550 void Assembler::cmpb(Address dst, int imm8) { 1551 InstructionMark im(this); 1552 prefix(dst); 1553 emit_int8((unsigned char)0x80); 1554 emit_operand(rdi, dst, 1); 1555 emit_int8(imm8); 1556 } 1557 1558 void Assembler::cmpl(Address dst, int32_t imm32) { 1559 InstructionMark im(this); 1560 prefix(dst); 1561 emit_int8((unsigned char)0x81); 1562 emit_operand(rdi, dst, 4); 1563 emit_int32(imm32); 1564 } 1565 1566 void Assembler::cmpl(Register dst, int32_t imm32) { 1567 prefix(dst); 1568 emit_arith(0x81, 0xF8, dst, imm32); 1569 } 1570 1571 void Assembler::cmpl(Register dst, Register src) { 1572 (void) prefix_and_encode(dst->encoding(), src->encoding()); 1573 emit_arith(0x3B, 0xC0, dst, src); 1574 } 1575 1576 void Assembler::cmpl(Register dst, Address src) { 1577 InstructionMark im(this); 1578 prefix(src, dst); 1579 emit_int8((unsigned char)0x3B); 1580 emit_operand(dst, src); 1581 } 1582 1583 void Assembler::cmpw(Address dst, int imm16) { 1584 InstructionMark im(this); 1585 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers"); 1586 emit_int8(0x66); 1587 emit_int8((unsigned char)0x81); 1588 emit_operand(rdi, dst, 2); 1589 emit_int16(imm16); 1590 } 1591 1592 // The 32-bit cmpxchg compares the value at adr with the contents of rax, 1593 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,. 1594 // The ZF is set if the compared values were equal, and cleared otherwise. 1595 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg 1596 InstructionMark im(this); 1597 prefix(adr, reg); 1598 emit_int8(0x0F); 1599 emit_int8((unsigned char)0xB1); 1600 emit_operand(reg, adr); 1601 } 1602 1603 // The 8-bit cmpxchg compares the value at adr with the contents of rax, 1604 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,. 1605 // The ZF is set if the compared values were equal, and cleared otherwise. 1606 void Assembler::cmpxchgb(Register reg, Address adr) { // cmpxchg 1607 InstructionMark im(this); 1608 prefix(adr, reg, true); 1609 emit_int8(0x0F); 1610 emit_int8((unsigned char)0xB0); 1611 emit_operand(reg, adr); 1612 } 1613 1614 void Assembler::comisd(XMMRegister dst, Address src) { 1615 // NOTE: dbx seems to decode this as comiss even though the 1616 // 0x66 is there. Strangly ucomisd comes out correct 1617 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1618 InstructionMark im(this); 1619 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);; 1620 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 1621 attributes.set_rex_vex_w_reverted(); 1622 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 1623 emit_int8(0x2F); 1624 emit_operand(dst, src); 1625 } 1626 1627 void Assembler::comisd(XMMRegister dst, XMMRegister src) { 1628 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1629 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1630 attributes.set_rex_vex_w_reverted(); 1631 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 1632 emit_int8(0x2F); 1633 emit_int8((unsigned char)(0xC0 | encode)); 1634 } 1635 1636 void Assembler::comiss(XMMRegister dst, Address src) { 1637 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1638 InstructionMark im(this); 1639 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1640 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 1641 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 1642 emit_int8(0x2F); 1643 emit_operand(dst, src); 1644 } 1645 1646 void Assembler::comiss(XMMRegister dst, XMMRegister src) { 1647 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1648 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1649 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 1650 emit_int8(0x2F); 1651 emit_int8((unsigned char)(0xC0 | encode)); 1652 } 1653 1654 void Assembler::cpuid() { 1655 emit_int8(0x0F); 1656 emit_int8((unsigned char)0xA2); 1657 } 1658 1659 // Opcode / Instruction Op / En 64 - Bit Mode Compat / Leg Mode Description Implemented 1660 // F2 0F 38 F0 / r CRC32 r32, r / m8 RM Valid Valid Accumulate CRC32 on r / m8. v 1661 // F2 REX 0F 38 F0 / r CRC32 r32, r / m8* RM Valid N.E. Accumulate CRC32 on r / m8. - 1662 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E. Accumulate CRC32 on r / m8. - 1663 // 1664 // F2 0F 38 F1 / r CRC32 r32, r / m16 RM Valid Valid Accumulate CRC32 on r / m16. v 1665 // 1666 // F2 0F 38 F1 / r CRC32 r32, r / m32 RM Valid Valid Accumulate CRC32 on r / m32. v 1667 // 1668 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E. Accumulate CRC32 on r / m64. v 1669 void Assembler::crc32(Register crc, Register v, int8_t sizeInBytes) { 1670 assert(VM_Version::supports_sse4_2(), ""); 1671 int8_t w = 0x01; 1672 Prefix p = Prefix_EMPTY; 1673 1674 emit_int8((int8_t)0xF2); 1675 switch (sizeInBytes) { 1676 case 1: 1677 w = 0; 1678 break; 1679 case 2: 1680 case 4: 1681 break; 1682 LP64_ONLY(case 8:) 1683 // This instruction is not valid in 32 bits 1684 // Note: 1685 // http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf 1686 // 1687 // Page B - 72 Vol. 2C says 1688 // qwreg2 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : 11 qwreg1 qwreg2 1689 // mem64 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : mod qwreg r / m 1690 // F0!!! 1691 // while 3 - 208 Vol. 2A 1692 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E.Accumulate CRC32 on r / m64. 1693 // 1694 // the 0 on a last bit is reserved for a different flavor of this instruction : 1695 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E.Accumulate CRC32 on r / m8. 1696 p = REX_W; 1697 break; 1698 default: 1699 assert(0, "Unsupported value for a sizeInBytes argument"); 1700 break; 1701 } 1702 LP64_ONLY(prefix(crc, v, p);) 1703 emit_int8((int8_t)0x0F); 1704 emit_int8(0x38); 1705 emit_int8((int8_t)(0xF0 | w)); 1706 emit_int8(0xC0 | ((crc->encoding() & 0x7) << 3) | (v->encoding() & 7)); 1707 } 1708 1709 void Assembler::crc32(Register crc, Address adr, int8_t sizeInBytes) { 1710 assert(VM_Version::supports_sse4_2(), ""); 1711 InstructionMark im(this); 1712 int8_t w = 0x01; 1713 Prefix p = Prefix_EMPTY; 1714 1715 emit_int8((int8_t)0xF2); 1716 switch (sizeInBytes) { 1717 case 1: 1718 w = 0; 1719 break; 1720 case 2: 1721 case 4: 1722 break; 1723 LP64_ONLY(case 8:) 1724 // This instruction is not valid in 32 bits 1725 p = REX_W; 1726 break; 1727 default: 1728 assert(0, "Unsupported value for a sizeInBytes argument"); 1729 break; 1730 } 1731 LP64_ONLY(prefix(crc, adr, p);) 1732 emit_int8((int8_t)0x0F); 1733 emit_int8(0x38); 1734 emit_int8((int8_t)(0xF0 | w)); 1735 emit_operand(crc, adr); 1736 } 1737 1738 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) { 1739 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1740 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 1741 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 1742 emit_int8((unsigned char)0xE6); 1743 emit_int8((unsigned char)(0xC0 | encode)); 1744 } 1745 1746 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) { 1747 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1748 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 1749 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 1750 emit_int8(0x5B); 1751 emit_int8((unsigned char)(0xC0 | encode)); 1752 } 1753 1754 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) { 1755 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1756 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1757 attributes.set_rex_vex_w_reverted(); 1758 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 1759 emit_int8(0x5A); 1760 emit_int8((unsigned char)(0xC0 | encode)); 1761 } 1762 1763 void Assembler::cvtsd2ss(XMMRegister dst, Address src) { 1764 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1765 InstructionMark im(this); 1766 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1767 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 1768 attributes.set_rex_vex_w_reverted(); 1769 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 1770 emit_int8(0x5A); 1771 emit_operand(dst, src); 1772 } 1773 1774 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) { 1775 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1776 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1777 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 1778 emit_int8(0x2A); 1779 emit_int8((unsigned char)(0xC0 | encode)); 1780 } 1781 1782 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) { 1783 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1784 InstructionMark im(this); 1785 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1786 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 1787 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 1788 emit_int8(0x2A); 1789 emit_operand(dst, src); 1790 } 1791 1792 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) { 1793 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1794 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1795 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 1796 emit_int8(0x2A); 1797 emit_int8((unsigned char)(0xC0 | encode)); 1798 } 1799 1800 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) { 1801 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1802 InstructionMark im(this); 1803 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1804 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 1805 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 1806 emit_int8(0x2A); 1807 emit_operand(dst, src); 1808 } 1809 1810 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) { 1811 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1812 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1813 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 1814 emit_int8(0x2A); 1815 emit_int8((unsigned char)(0xC0 | encode)); 1816 } 1817 1818 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) { 1819 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1820 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1821 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 1822 emit_int8(0x5A); 1823 emit_int8((unsigned char)(0xC0 | encode)); 1824 } 1825 1826 void Assembler::cvtss2sd(XMMRegister dst, Address src) { 1827 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1828 InstructionMark im(this); 1829 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1830 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 1831 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 1832 emit_int8(0x5A); 1833 emit_operand(dst, src); 1834 } 1835 1836 1837 void Assembler::cvttsd2sil(Register dst, XMMRegister src) { 1838 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1839 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1840 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 1841 emit_int8(0x2C); 1842 emit_int8((unsigned char)(0xC0 | encode)); 1843 } 1844 1845 void Assembler::cvttss2sil(Register dst, XMMRegister src) { 1846 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1847 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1848 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 1849 emit_int8(0x2C); 1850 emit_int8((unsigned char)(0xC0 | encode)); 1851 } 1852 1853 void Assembler::cvttpd2dq(XMMRegister dst, XMMRegister src) { 1854 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1855 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit; 1856 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 1857 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 1858 emit_int8((unsigned char)0xE6); 1859 emit_int8((unsigned char)(0xC0 | encode)); 1860 } 1861 1862 void Assembler::decl(Address dst) { 1863 // Don't use it directly. Use MacroAssembler::decrement() instead. 1864 InstructionMark im(this); 1865 prefix(dst); 1866 emit_int8((unsigned char)0xFF); 1867 emit_operand(rcx, dst); 1868 } 1869 1870 void Assembler::divsd(XMMRegister dst, Address src) { 1871 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1872 InstructionMark im(this); 1873 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1874 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 1875 attributes.set_rex_vex_w_reverted(); 1876 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 1877 emit_int8(0x5E); 1878 emit_operand(dst, src); 1879 } 1880 1881 void Assembler::divsd(XMMRegister dst, XMMRegister src) { 1882 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1883 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1884 attributes.set_rex_vex_w_reverted(); 1885 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 1886 emit_int8(0x5E); 1887 emit_int8((unsigned char)(0xC0 | encode)); 1888 } 1889 1890 void Assembler::divss(XMMRegister dst, Address src) { 1891 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1892 InstructionMark im(this); 1893 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1894 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 1895 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 1896 emit_int8(0x5E); 1897 emit_operand(dst, src); 1898 } 1899 1900 void Assembler::divss(XMMRegister dst, XMMRegister src) { 1901 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1902 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1903 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 1904 emit_int8(0x5E); 1905 emit_int8((unsigned char)(0xC0 | encode)); 1906 } 1907 1908 void Assembler::emms() { 1909 NOT_LP64(assert(VM_Version::supports_mmx(), "")); 1910 emit_int8(0x0F); 1911 emit_int8(0x77); 1912 } 1913 1914 void Assembler::hlt() { 1915 emit_int8((unsigned char)0xF4); 1916 } 1917 1918 void Assembler::idivl(Register src) { 1919 int encode = prefix_and_encode(src->encoding()); 1920 emit_int8((unsigned char)0xF7); 1921 emit_int8((unsigned char)(0xF8 | encode)); 1922 } 1923 1924 void Assembler::divl(Register src) { // Unsigned 1925 int encode = prefix_and_encode(src->encoding()); 1926 emit_int8((unsigned char)0xF7); 1927 emit_int8((unsigned char)(0xF0 | encode)); 1928 } 1929 1930 void Assembler::imull(Register src) { 1931 int encode = prefix_and_encode(src->encoding()); 1932 emit_int8((unsigned char)0xF7); 1933 emit_int8((unsigned char)(0xE8 | encode)); 1934 } 1935 1936 void Assembler::imull(Register dst, Register src) { 1937 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 1938 emit_int8(0x0F); 1939 emit_int8((unsigned char)0xAF); 1940 emit_int8((unsigned char)(0xC0 | encode)); 1941 } 1942 1943 1944 void Assembler::imull(Register dst, Register src, int value) { 1945 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 1946 if (is8bit(value)) { 1947 emit_int8(0x6B); 1948 emit_int8((unsigned char)(0xC0 | encode)); 1949 emit_int8(value & 0xFF); 1950 } else { 1951 emit_int8(0x69); 1952 emit_int8((unsigned char)(0xC0 | encode)); 1953 emit_int32(value); 1954 } 1955 } 1956 1957 void Assembler::imull(Register dst, Address src) { 1958 InstructionMark im(this); 1959 prefix(src, dst); 1960 emit_int8(0x0F); 1961 emit_int8((unsigned char) 0xAF); 1962 emit_operand(dst, src); 1963 } 1964 1965 1966 void Assembler::incl(Address dst) { 1967 // Don't use it directly. Use MacroAssembler::increment() instead. 1968 InstructionMark im(this); 1969 prefix(dst); 1970 emit_int8((unsigned char)0xFF); 1971 emit_operand(rax, dst); 1972 } 1973 1974 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) { 1975 InstructionMark im(this); 1976 assert((0 <= cc) && (cc < 16), "illegal cc"); 1977 if (L.is_bound()) { 1978 address dst = target(L); 1979 assert(dst != NULL, "jcc most probably wrong"); 1980 1981 const int short_size = 2; 1982 const int long_size = 6; 1983 intptr_t offs = (intptr_t)dst - (intptr_t)pc(); 1984 if (maybe_short && is8bit(offs - short_size)) { 1985 // 0111 tttn #8-bit disp 1986 emit_int8(0x70 | cc); 1987 emit_int8((offs - short_size) & 0xFF); 1988 } else { 1989 // 0000 1111 1000 tttn #32-bit disp 1990 assert(is_simm32(offs - long_size), 1991 "must be 32bit offset (call4)"); 1992 emit_int8(0x0F); 1993 emit_int8((unsigned char)(0x80 | cc)); 1994 emit_int32(offs - long_size); 1995 } 1996 } else { 1997 // Note: could eliminate cond. jumps to this jump if condition 1998 // is the same however, seems to be rather unlikely case. 1999 // Note: use jccb() if label to be bound is very close to get 2000 // an 8-bit displacement 2001 L.add_patch_at(code(), locator()); 2002 emit_int8(0x0F); 2003 emit_int8((unsigned char)(0x80 | cc)); 2004 emit_int32(0); 2005 } 2006 } 2007 2008 void Assembler::jccb(Condition cc, Label& L) { 2009 if (L.is_bound()) { 2010 const int short_size = 2; 2011 address entry = target(L); 2012 #ifdef ASSERT 2013 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size); 2014 intptr_t delta = short_branch_delta(); 2015 if (delta != 0) { 2016 dist += (dist < 0 ? (-delta) :delta); 2017 } 2018 assert(is8bit(dist), "Dispacement too large for a short jmp"); 2019 #endif 2020 intptr_t offs = (intptr_t)entry - (intptr_t)pc(); 2021 // 0111 tttn #8-bit disp 2022 emit_int8(0x70 | cc); 2023 emit_int8((offs - short_size) & 0xFF); 2024 } else { 2025 InstructionMark im(this); 2026 L.add_patch_at(code(), locator()); 2027 emit_int8(0x70 | cc); 2028 emit_int8(0); 2029 } 2030 } 2031 2032 void Assembler::jmp(Address adr) { 2033 InstructionMark im(this); 2034 prefix(adr); 2035 emit_int8((unsigned char)0xFF); 2036 emit_operand(rsp, adr); 2037 } 2038 2039 void Assembler::jmp(Label& L, bool maybe_short) { 2040 if (L.is_bound()) { 2041 address entry = target(L); 2042 assert(entry != NULL, "jmp most probably wrong"); 2043 InstructionMark im(this); 2044 const int short_size = 2; 2045 const int long_size = 5; 2046 intptr_t offs = entry - pc(); 2047 if (maybe_short && is8bit(offs - short_size)) { 2048 emit_int8((unsigned char)0xEB); 2049 emit_int8((offs - short_size) & 0xFF); 2050 } else { 2051 emit_int8((unsigned char)0xE9); 2052 emit_int32(offs - long_size); 2053 } 2054 } else { 2055 // By default, forward jumps are always 32-bit displacements, since 2056 // we can't yet know where the label will be bound. If you're sure that 2057 // the forward jump will not run beyond 256 bytes, use jmpb to 2058 // force an 8-bit displacement. 2059 InstructionMark im(this); 2060 L.add_patch_at(code(), locator()); 2061 emit_int8((unsigned char)0xE9); 2062 emit_int32(0); 2063 } 2064 } 2065 2066 void Assembler::jmp(Register entry) { 2067 int encode = prefix_and_encode(entry->encoding()); 2068 emit_int8((unsigned char)0xFF); 2069 emit_int8((unsigned char)(0xE0 | encode)); 2070 } 2071 2072 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) { 2073 InstructionMark im(this); 2074 emit_int8((unsigned char)0xE9); 2075 assert(dest != NULL, "must have a target"); 2076 intptr_t disp = dest - (pc() + sizeof(int32_t)); 2077 assert(is_simm32(disp), "must be 32bit offset (jmp)"); 2078 emit_data(disp, rspec.reloc(), call32_operand); 2079 } 2080 2081 void Assembler::jmpb(Label& L) { 2082 if (L.is_bound()) { 2083 const int short_size = 2; 2084 address entry = target(L); 2085 assert(entry != NULL, "jmp most probably wrong"); 2086 #ifdef ASSERT 2087 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size); 2088 intptr_t delta = short_branch_delta(); 2089 if (delta != 0) { 2090 dist += (dist < 0 ? (-delta) :delta); 2091 } 2092 assert(is8bit(dist), "Dispacement too large for a short jmp"); 2093 #endif 2094 intptr_t offs = entry - pc(); 2095 emit_int8((unsigned char)0xEB); 2096 emit_int8((offs - short_size) & 0xFF); 2097 } else { 2098 InstructionMark im(this); 2099 L.add_patch_at(code(), locator()); 2100 emit_int8((unsigned char)0xEB); 2101 emit_int8(0); 2102 } 2103 } 2104 2105 void Assembler::ldmxcsr( Address src) { 2106 if (UseAVX > 0 ) { 2107 InstructionMark im(this); 2108 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2109 vex_prefix(src, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2110 emit_int8((unsigned char)0xAE); 2111 emit_operand(as_Register(2), src); 2112 } else { 2113 NOT_LP64(assert(VM_Version::supports_sse(), "")); 2114 InstructionMark im(this); 2115 prefix(src); 2116 emit_int8(0x0F); 2117 emit_int8((unsigned char)0xAE); 2118 emit_operand(as_Register(2), src); 2119 } 2120 } 2121 2122 void Assembler::leal(Register dst, Address src) { 2123 InstructionMark im(this); 2124 #ifdef _LP64 2125 emit_int8(0x67); // addr32 2126 prefix(src, dst); 2127 #endif // LP64 2128 emit_int8((unsigned char)0x8D); 2129 emit_operand(dst, src); 2130 } 2131 2132 void Assembler::lfence() { 2133 emit_int8(0x0F); 2134 emit_int8((unsigned char)0xAE); 2135 emit_int8((unsigned char)0xE8); 2136 } 2137 2138 void Assembler::lock() { 2139 emit_int8((unsigned char)0xF0); 2140 } 2141 2142 void Assembler::lzcntl(Register dst, Register src) { 2143 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR"); 2144 emit_int8((unsigned char)0xF3); 2145 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 2146 emit_int8(0x0F); 2147 emit_int8((unsigned char)0xBD); 2148 emit_int8((unsigned char)(0xC0 | encode)); 2149 } 2150 2151 // Emit mfence instruction 2152 void Assembler::mfence() { 2153 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");) 2154 emit_int8(0x0F); 2155 emit_int8((unsigned char)0xAE); 2156 emit_int8((unsigned char)0xF0); 2157 } 2158 2159 void Assembler::mov(Register dst, Register src) { 2160 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); 2161 } 2162 2163 void Assembler::movapd(XMMRegister dst, XMMRegister src) { 2164 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2165 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit; 2166 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 2167 attributes.set_rex_vex_w_reverted(); 2168 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2169 emit_int8(0x28); 2170 emit_int8((unsigned char)(0xC0 | encode)); 2171 } 2172 2173 void Assembler::movaps(XMMRegister dst, XMMRegister src) { 2174 NOT_LP64(assert(VM_Version::supports_sse(), "")); 2175 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit; 2176 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 2177 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2178 emit_int8(0x28); 2179 emit_int8((unsigned char)(0xC0 | encode)); 2180 } 2181 2182 void Assembler::movlhps(XMMRegister dst, XMMRegister src) { 2183 NOT_LP64(assert(VM_Version::supports_sse(), "")); 2184 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2185 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2186 emit_int8(0x16); 2187 emit_int8((unsigned char)(0xC0 | encode)); 2188 } 2189 2190 void Assembler::movb(Register dst, Address src) { 2191 NOT_LP64(assert(dst->has_byte_register(), "must have byte register")); 2192 InstructionMark im(this); 2193 prefix(src, dst, true); 2194 emit_int8((unsigned char)0x8A); 2195 emit_operand(dst, src); 2196 } 2197 2198 void Assembler::movddup(XMMRegister dst, XMMRegister src) { 2199 NOT_LP64(assert(VM_Version::supports_sse3(), "")); 2200 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit; 2201 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2202 attributes.set_rex_vex_w_reverted(); 2203 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2204 emit_int8(0x12); 2205 emit_int8(0xC0 | encode); 2206 } 2207 2208 void Assembler::kmovbl(KRegister dst, Register src) { 2209 assert(VM_Version::supports_avx512dq(), ""); 2210 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2211 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2212 emit_int8((unsigned char)0x92); 2213 emit_int8((unsigned char)(0xC0 | encode)); 2214 } 2215 2216 void Assembler::kmovbl(Register dst, KRegister src) { 2217 assert(VM_Version::supports_avx512dq(), ""); 2218 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2219 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2220 emit_int8((unsigned char)0x93); 2221 emit_int8((unsigned char)(0xC0 | encode)); 2222 } 2223 2224 void Assembler::kmovwl(KRegister dst, Register src) { 2225 assert(VM_Version::supports_evex(), ""); 2226 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2227 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2228 emit_int8((unsigned char)0x92); 2229 emit_int8((unsigned char)(0xC0 | encode)); 2230 } 2231 2232 void Assembler::kmovwl(Register dst, KRegister src) { 2233 assert(VM_Version::supports_evex(), ""); 2234 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2235 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2236 emit_int8((unsigned char)0x93); 2237 emit_int8((unsigned char)(0xC0 | encode)); 2238 } 2239 2240 void Assembler::kmovwl(KRegister dst, Address src) { 2241 assert(VM_Version::supports_evex(), ""); 2242 InstructionMark im(this); 2243 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2244 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2245 emit_int8((unsigned char)0x90); 2246 emit_operand((Register)dst, src); 2247 } 2248 2249 void Assembler::kmovdl(KRegister dst, Register src) { 2250 assert(VM_Version::supports_avx512bw(), ""); 2251 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2252 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2253 emit_int8((unsigned char)0x92); 2254 emit_int8((unsigned char)(0xC0 | encode)); 2255 } 2256 2257 void Assembler::kmovdl(Register dst, KRegister src) { 2258 assert(VM_Version::supports_avx512bw(), ""); 2259 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2260 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2261 emit_int8((unsigned char)0x93); 2262 emit_int8((unsigned char)(0xC0 | encode)); 2263 } 2264 2265 void Assembler::kmovql(KRegister dst, KRegister src) { 2266 assert(VM_Version::supports_avx512bw(), ""); 2267 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2268 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2269 emit_int8((unsigned char)0x90); 2270 emit_int8((unsigned char)(0xC0 | encode)); 2271 } 2272 2273 void Assembler::kmovql(KRegister dst, Address src) { 2274 assert(VM_Version::supports_avx512bw(), ""); 2275 InstructionMark im(this); 2276 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2277 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2278 emit_int8((unsigned char)0x90); 2279 emit_operand((Register)dst, src); 2280 } 2281 2282 void Assembler::kmovql(Address dst, KRegister src) { 2283 assert(VM_Version::supports_avx512bw(), ""); 2284 InstructionMark im(this); 2285 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2286 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2287 emit_int8((unsigned char)0x90); 2288 emit_operand((Register)src, dst); 2289 } 2290 2291 void Assembler::kmovql(KRegister dst, Register src) { 2292 assert(VM_Version::supports_avx512bw(), ""); 2293 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2294 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2295 emit_int8((unsigned char)0x92); 2296 emit_int8((unsigned char)(0xC0 | encode)); 2297 } 2298 2299 void Assembler::kmovql(Register dst, KRegister src) { 2300 assert(VM_Version::supports_avx512bw(), ""); 2301 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2302 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2303 emit_int8((unsigned char)0x93); 2304 emit_int8((unsigned char)(0xC0 | encode)); 2305 } 2306 2307 void Assembler::knotwl(KRegister dst, KRegister src) { 2308 assert(VM_Version::supports_evex(), ""); 2309 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2310 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2311 emit_int8((unsigned char)0x44); 2312 emit_int8((unsigned char)(0xC0 | encode)); 2313 } 2314 2315 // This instruction produces ZF or CF flags 2316 void Assembler::kortestbl(KRegister src1, KRegister src2) { 2317 assert(VM_Version::supports_avx512dq(), ""); 2318 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2319 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2320 emit_int8((unsigned char)0x98); 2321 emit_int8((unsigned char)(0xC0 | encode)); 2322 } 2323 2324 // This instruction produces ZF or CF flags 2325 void Assembler::kortestwl(KRegister src1, KRegister src2) { 2326 assert(VM_Version::supports_evex(), ""); 2327 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2328 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2329 emit_int8((unsigned char)0x98); 2330 emit_int8((unsigned char)(0xC0 | encode)); 2331 } 2332 2333 // This instruction produces ZF or CF flags 2334 void Assembler::kortestdl(KRegister src1, KRegister src2) { 2335 assert(VM_Version::supports_avx512bw(), ""); 2336 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2337 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2338 emit_int8((unsigned char)0x98); 2339 emit_int8((unsigned char)(0xC0 | encode)); 2340 } 2341 2342 // This instruction produces ZF or CF flags 2343 void Assembler::kortestql(KRegister src1, KRegister src2) { 2344 assert(VM_Version::supports_avx512bw(), ""); 2345 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2346 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2347 emit_int8((unsigned char)0x98); 2348 emit_int8((unsigned char)(0xC0 | encode)); 2349 } 2350 2351 // This instruction produces ZF or CF flags 2352 void Assembler::ktestql(KRegister src1, KRegister src2) { 2353 assert(VM_Version::supports_avx512bw(), ""); 2354 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2355 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2356 emit_int8((unsigned char)0x99); 2357 emit_int8((unsigned char)(0xC0 | encode)); 2358 } 2359 2360 void Assembler::ktestq(KRegister src1, KRegister src2) { 2361 assert(VM_Version::supports_avx512bw(), ""); 2362 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2363 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2364 emit_int8((unsigned char)0x99); 2365 emit_int8((unsigned char)(0xC0 | encode)); 2366 } 2367 2368 void Assembler::ktestd(KRegister src1, KRegister src2) { 2369 assert(VM_Version::supports_avx512bw(), ""); 2370 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2371 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2372 emit_int8((unsigned char)0x99); 2373 emit_int8((unsigned char)(0xC0 | encode)); 2374 } 2375 2376 void Assembler::movb(Address dst, int imm8) { 2377 InstructionMark im(this); 2378 prefix(dst); 2379 emit_int8((unsigned char)0xC6); 2380 emit_operand(rax, dst, 1); 2381 emit_int8(imm8); 2382 } 2383 2384 2385 void Assembler::movb(Address dst, Register src) { 2386 assert(src->has_byte_register(), "must have byte register"); 2387 InstructionMark im(this); 2388 prefix(dst, src, true); 2389 emit_int8((unsigned char)0x88); 2390 emit_operand(src, dst); 2391 } 2392 2393 void Assembler::movdl(XMMRegister dst, Register src) { 2394 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2395 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2396 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2397 emit_int8(0x6E); 2398 emit_int8((unsigned char)(0xC0 | encode)); 2399 } 2400 2401 void Assembler::movdl(Register dst, XMMRegister src) { 2402 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2403 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2404 // swap src/dst to get correct prefix 2405 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2406 emit_int8(0x7E); 2407 emit_int8((unsigned char)(0xC0 | encode)); 2408 } 2409 2410 void Assembler::movdl(XMMRegister dst, Address src) { 2411 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2412 InstructionMark im(this); 2413 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2414 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 2415 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2416 emit_int8(0x6E); 2417 emit_operand(dst, src); 2418 } 2419 2420 void Assembler::movdl(Address dst, XMMRegister src) { 2421 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2422 InstructionMark im(this); 2423 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2424 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 2425 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2426 emit_int8(0x7E); 2427 emit_operand(src, dst); 2428 } 2429 2430 void Assembler::movdqa(XMMRegister dst, XMMRegister src) { 2431 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2432 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit; 2433 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2434 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2435 emit_int8(0x6F); 2436 emit_int8((unsigned char)(0xC0 | encode)); 2437 } 2438 2439 void Assembler::movdqa(XMMRegister dst, Address src) { 2440 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2441 InstructionMark im(this); 2442 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2443 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2444 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2445 emit_int8(0x6F); 2446 emit_operand(dst, src); 2447 } 2448 2449 void Assembler::movdqu(XMMRegister dst, Address src) { 2450 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2451 InstructionMark im(this); 2452 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2453 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2454 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2455 emit_int8(0x6F); 2456 emit_operand(dst, src); 2457 } 2458 2459 void Assembler::movdqu(XMMRegister dst, XMMRegister src) { 2460 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2461 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2462 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2463 emit_int8(0x6F); 2464 emit_int8((unsigned char)(0xC0 | encode)); 2465 } 2466 2467 void Assembler::movdqu(Address dst, XMMRegister src) { 2468 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2469 InstructionMark im(this); 2470 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2471 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2472 attributes.reset_is_clear_context(); 2473 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2474 emit_int8(0x7F); 2475 emit_operand(src, dst); 2476 } 2477 2478 // Move Unaligned 256bit Vector 2479 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) { 2480 assert(UseAVX > 0, ""); 2481 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2482 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2483 emit_int8(0x6F); 2484 emit_int8((unsigned char)(0xC0 | encode)); 2485 } 2486 2487 void Assembler::vmovdqu(XMMRegister dst, Address src) { 2488 assert(UseAVX > 0, ""); 2489 InstructionMark im(this); 2490 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2491 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2492 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2493 emit_int8(0x6F); 2494 emit_operand(dst, src); 2495 } 2496 2497 void Assembler::vmovdqu(Address dst, XMMRegister src) { 2498 assert(UseAVX > 0, ""); 2499 InstructionMark im(this); 2500 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2501 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2502 attributes.reset_is_clear_context(); 2503 // swap src<->dst for encoding 2504 assert(src != xnoreg, "sanity"); 2505 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2506 emit_int8(0x7F); 2507 emit_operand(src, dst); 2508 } 2509 2510 // Move Unaligned EVEX enabled Vector (programmable : 8,16,32,64) 2511 void Assembler::evmovdqub(XMMRegister dst, XMMRegister src, int vector_len) { 2512 assert(VM_Version::supports_evex(), ""); 2513 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 2514 attributes.set_is_evex_instruction(); 2515 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3; 2516 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes); 2517 emit_int8(0x6F); 2518 emit_int8((unsigned char)(0xC0 | encode)); 2519 } 2520 2521 void Assembler::evmovdqub(XMMRegister dst, Address src, int vector_len) { 2522 assert(VM_Version::supports_evex(), ""); 2523 InstructionMark im(this); 2524 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 2525 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3; 2526 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2527 attributes.set_is_evex_instruction(); 2528 vex_prefix(src, 0, dst->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes); 2529 emit_int8(0x6F); 2530 emit_operand(dst, src); 2531 } 2532 2533 void Assembler::evmovdqub(Address dst, XMMRegister src, int vector_len) { 2534 assert(VM_Version::supports_evex(), ""); 2535 assert(src != xnoreg, "sanity"); 2536 InstructionMark im(this); 2537 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 2538 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3; 2539 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2540 attributes.set_is_evex_instruction(); 2541 vex_prefix(dst, 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes); 2542 emit_int8(0x7F); 2543 emit_operand(src, dst); 2544 } 2545 2546 void Assembler::evmovdqub(XMMRegister dst, KRegister mask, Address src, int vector_len) { 2547 assert(VM_Version::supports_avx512vlbw(), ""); 2548 assert(is_vector_masking(), ""); // For stub code use only 2549 InstructionMark im(this); 2550 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true); 2551 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2552 attributes.set_embedded_opmask_register_specifier(mask); 2553 attributes.set_is_evex_instruction(); 2554 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2555 emit_int8(0x6F); 2556 emit_operand(dst, src); 2557 } 2558 2559 void Assembler::evmovdquw(XMMRegister dst, Address src, int vector_len) { 2560 assert(VM_Version::supports_evex(), ""); 2561 InstructionMark im(this); 2562 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 2563 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2564 attributes.set_is_evex_instruction(); 2565 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3; 2566 vex_prefix(src, 0, dst->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes); 2567 emit_int8(0x6F); 2568 emit_operand(dst, src); 2569 } 2570 2571 void Assembler::evmovdquw(XMMRegister dst, KRegister mask, Address src, int vector_len) { 2572 assert(is_vector_masking(), ""); 2573 assert(VM_Version::supports_avx512vlbw(), ""); 2574 InstructionMark im(this); 2575 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true); 2576 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2577 attributes.set_embedded_opmask_register_specifier(mask); 2578 attributes.set_is_evex_instruction(); 2579 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2580 emit_int8(0x6F); 2581 emit_operand(dst, src); 2582 } 2583 2584 void Assembler::evmovdquw(Address dst, XMMRegister src, int vector_len) { 2585 assert(VM_Version::supports_evex(), ""); 2586 assert(src != xnoreg, "sanity"); 2587 InstructionMark im(this); 2588 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 2589 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2590 attributes.set_is_evex_instruction(); 2591 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3; 2592 vex_prefix(dst, 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes); 2593 emit_int8(0x7F); 2594 emit_operand(src, dst); 2595 } 2596 2597 void Assembler::evmovdquw(Address dst, KRegister mask, XMMRegister src, int vector_len) { 2598 assert(VM_Version::supports_avx512vlbw(), ""); 2599 assert(src != xnoreg, "sanity"); 2600 InstructionMark im(this); 2601 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2602 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2603 attributes.reset_is_clear_context(); 2604 attributes.set_embedded_opmask_register_specifier(mask); 2605 attributes.set_is_evex_instruction(); 2606 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2607 emit_int8(0x7F); 2608 emit_operand(src, dst); 2609 } 2610 2611 void Assembler::evmovdqul(XMMRegister dst, XMMRegister src, int vector_len) { 2612 assert(VM_Version::supports_evex(), ""); 2613 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2614 attributes.set_is_evex_instruction(); 2615 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2616 emit_int8(0x6F); 2617 emit_int8((unsigned char)(0xC0 | encode)); 2618 } 2619 2620 void Assembler::evmovdqul(XMMRegister dst, Address src, int vector_len) { 2621 assert(VM_Version::supports_evex(), ""); 2622 InstructionMark im(this); 2623 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false , /* uses_vl */ true); 2624 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2625 attributes.set_is_evex_instruction(); 2626 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2627 emit_int8(0x6F); 2628 emit_operand(dst, src); 2629 } 2630 2631 void Assembler::evmovdqul(Address dst, XMMRegister src, int vector_len) { 2632 assert(VM_Version::supports_evex(), ""); 2633 assert(src != xnoreg, "sanity"); 2634 InstructionMark im(this); 2635 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2636 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2637 attributes.reset_is_clear_context(); 2638 attributes.set_is_evex_instruction(); 2639 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2640 emit_int8(0x7F); 2641 emit_operand(src, dst); 2642 } 2643 2644 void Assembler::evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) { 2645 assert(VM_Version::supports_evex(), ""); 2646 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2647 attributes.set_is_evex_instruction(); 2648 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2649 emit_int8(0x6F); 2650 emit_int8((unsigned char)(0xC0 | encode)); 2651 } 2652 2653 void Assembler::evmovdquq(XMMRegister dst, Address src, int vector_len) { 2654 assert(VM_Version::supports_evex(), ""); 2655 InstructionMark im(this); 2656 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2657 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2658 attributes.set_is_evex_instruction(); 2659 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2660 emit_int8(0x6F); 2661 emit_operand(dst, src); 2662 } 2663 2664 void Assembler::evmovdquq(Address dst, XMMRegister src, int vector_len) { 2665 assert(VM_Version::supports_evex(), ""); 2666 assert(src != xnoreg, "sanity"); 2667 InstructionMark im(this); 2668 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2669 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2670 attributes.reset_is_clear_context(); 2671 attributes.set_is_evex_instruction(); 2672 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2673 emit_int8(0x7F); 2674 emit_operand(src, dst); 2675 } 2676 2677 // Uses zero extension on 64bit 2678 2679 void Assembler::movl(Register dst, int32_t imm32) { 2680 int encode = prefix_and_encode(dst->encoding()); 2681 emit_int8((unsigned char)(0xB8 | encode)); 2682 emit_int32(imm32); 2683 } 2684 2685 void Assembler::movl(Register dst, Register src) { 2686 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 2687 emit_int8((unsigned char)0x8B); 2688 emit_int8((unsigned char)(0xC0 | encode)); 2689 } 2690 2691 void Assembler::movl(Register dst, Address src) { 2692 InstructionMark im(this); 2693 prefix(src, dst); 2694 emit_int8((unsigned char)0x8B); 2695 emit_operand(dst, src); 2696 } 2697 2698 void Assembler::movl(Address dst, int32_t imm32) { 2699 InstructionMark im(this); 2700 prefix(dst); 2701 emit_int8((unsigned char)0xC7); 2702 emit_operand(rax, dst, 4); 2703 emit_int32(imm32); 2704 } 2705 2706 void Assembler::movl(Address dst, Register src) { 2707 InstructionMark im(this); 2708 prefix(dst, src); 2709 emit_int8((unsigned char)0x89); 2710 emit_operand(src, dst); 2711 } 2712 2713 // New cpus require to use movsd and movss to avoid partial register stall 2714 // when loading from memory. But for old Opteron use movlpd instead of movsd. 2715 // The selection is done in MacroAssembler::movdbl() and movflt(). 2716 void Assembler::movlpd(XMMRegister dst, Address src) { 2717 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2718 InstructionMark im(this); 2719 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2720 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 2721 attributes.set_rex_vex_w_reverted(); 2722 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2723 emit_int8(0x12); 2724 emit_operand(dst, src); 2725 } 2726 2727 void Assembler::movq( MMXRegister dst, Address src ) { 2728 assert( VM_Version::supports_mmx(), "" ); 2729 emit_int8(0x0F); 2730 emit_int8(0x6F); 2731 emit_operand(dst, src); 2732 } 2733 2734 void Assembler::movq( Address dst, MMXRegister src ) { 2735 assert( VM_Version::supports_mmx(), "" ); 2736 emit_int8(0x0F); 2737 emit_int8(0x7F); 2738 // workaround gcc (3.2.1-7a) bug 2739 // In that version of gcc with only an emit_operand(MMX, Address) 2740 // gcc will tail jump and try and reverse the parameters completely 2741 // obliterating dst in the process. By having a version available 2742 // that doesn't need to swap the args at the tail jump the bug is 2743 // avoided. 2744 emit_operand(dst, src); 2745 } 2746 2747 void Assembler::movq(XMMRegister dst, Address src) { 2748 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2749 InstructionMark im(this); 2750 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2751 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 2752 attributes.set_rex_vex_w_reverted(); 2753 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2754 emit_int8(0x7E); 2755 emit_operand(dst, src); 2756 } 2757 2758 void Assembler::movq(Address dst, XMMRegister src) { 2759 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2760 InstructionMark im(this); 2761 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2762 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 2763 attributes.set_rex_vex_w_reverted(); 2764 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2765 emit_int8((unsigned char)0xD6); 2766 emit_operand(src, dst); 2767 } 2768 2769 void Assembler::movsbl(Register dst, Address src) { // movsxb 2770 InstructionMark im(this); 2771 prefix(src, dst); 2772 emit_int8(0x0F); 2773 emit_int8((unsigned char)0xBE); 2774 emit_operand(dst, src); 2775 } 2776 2777 void Assembler::movsbl(Register dst, Register src) { // movsxb 2778 NOT_LP64(assert(src->has_byte_register(), "must have byte register")); 2779 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true); 2780 emit_int8(0x0F); 2781 emit_int8((unsigned char)0xBE); 2782 emit_int8((unsigned char)(0xC0 | encode)); 2783 } 2784 2785 void Assembler::movsd(XMMRegister dst, XMMRegister src) { 2786 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2787 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2788 attributes.set_rex_vex_w_reverted(); 2789 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2790 emit_int8(0x10); 2791 emit_int8((unsigned char)(0xC0 | encode)); 2792 } 2793 2794 void Assembler::movsd(XMMRegister dst, Address src) { 2795 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2796 InstructionMark im(this); 2797 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2798 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 2799 attributes.set_rex_vex_w_reverted(); 2800 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2801 emit_int8(0x10); 2802 emit_operand(dst, src); 2803 } 2804 2805 void Assembler::movsd(Address dst, XMMRegister src) { 2806 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2807 InstructionMark im(this); 2808 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2809 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 2810 attributes.reset_is_clear_context(); 2811 attributes.set_rex_vex_w_reverted(); 2812 simd_prefix(src, xnoreg, dst, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2813 emit_int8(0x11); 2814 emit_operand(src, dst); 2815 } 2816 2817 void Assembler::movss(XMMRegister dst, XMMRegister src) { 2818 NOT_LP64(assert(VM_Version::supports_sse(), "")); 2819 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2820 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2821 emit_int8(0x10); 2822 emit_int8((unsigned char)(0xC0 | encode)); 2823 } 2824 2825 void Assembler::movss(XMMRegister dst, Address src) { 2826 NOT_LP64(assert(VM_Version::supports_sse(), "")); 2827 InstructionMark im(this); 2828 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2829 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 2830 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2831 emit_int8(0x10); 2832 emit_operand(dst, src); 2833 } 2834 2835 void Assembler::movss(Address dst, XMMRegister src) { 2836 NOT_LP64(assert(VM_Version::supports_sse(), "")); 2837 InstructionMark im(this); 2838 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2839 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 2840 attributes.reset_is_clear_context(); 2841 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2842 emit_int8(0x11); 2843 emit_operand(src, dst); 2844 } 2845 2846 void Assembler::movswl(Register dst, Address src) { // movsxw 2847 InstructionMark im(this); 2848 prefix(src, dst); 2849 emit_int8(0x0F); 2850 emit_int8((unsigned char)0xBF); 2851 emit_operand(dst, src); 2852 } 2853 2854 void Assembler::movswl(Register dst, Register src) { // movsxw 2855 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 2856 emit_int8(0x0F); 2857 emit_int8((unsigned char)0xBF); 2858 emit_int8((unsigned char)(0xC0 | encode)); 2859 } 2860 2861 void Assembler::movw(Address dst, int imm16) { 2862 InstructionMark im(this); 2863 2864 emit_int8(0x66); // switch to 16-bit mode 2865 prefix(dst); 2866 emit_int8((unsigned char)0xC7); 2867 emit_operand(rax, dst, 2); 2868 emit_int16(imm16); 2869 } 2870 2871 void Assembler::movw(Register dst, Address src) { 2872 InstructionMark im(this); 2873 emit_int8(0x66); 2874 prefix(src, dst); 2875 emit_int8((unsigned char)0x8B); 2876 emit_operand(dst, src); 2877 } 2878 2879 void Assembler::movw(Address dst, Register src) { 2880 InstructionMark im(this); 2881 emit_int8(0x66); 2882 prefix(dst, src); 2883 emit_int8((unsigned char)0x89); 2884 emit_operand(src, dst); 2885 } 2886 2887 void Assembler::movzbl(Register dst, Address src) { // movzxb 2888 InstructionMark im(this); 2889 prefix(src, dst); 2890 emit_int8(0x0F); 2891 emit_int8((unsigned char)0xB6); 2892 emit_operand(dst, src); 2893 } 2894 2895 void Assembler::movzbl(Register dst, Register src) { // movzxb 2896 NOT_LP64(assert(src->has_byte_register(), "must have byte register")); 2897 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true); 2898 emit_int8(0x0F); 2899 emit_int8((unsigned char)0xB6); 2900 emit_int8(0xC0 | encode); 2901 } 2902 2903 void Assembler::movzwl(Register dst, Address src) { // movzxw 2904 InstructionMark im(this); 2905 prefix(src, dst); 2906 emit_int8(0x0F); 2907 emit_int8((unsigned char)0xB7); 2908 emit_operand(dst, src); 2909 } 2910 2911 void Assembler::movzwl(Register dst, Register src) { // movzxw 2912 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 2913 emit_int8(0x0F); 2914 emit_int8((unsigned char)0xB7); 2915 emit_int8(0xC0 | encode); 2916 } 2917 2918 void Assembler::mull(Address src) { 2919 InstructionMark im(this); 2920 prefix(src); 2921 emit_int8((unsigned char)0xF7); 2922 emit_operand(rsp, src); 2923 } 2924 2925 void Assembler::mull(Register src) { 2926 int encode = prefix_and_encode(src->encoding()); 2927 emit_int8((unsigned char)0xF7); 2928 emit_int8((unsigned char)(0xE0 | encode)); 2929 } 2930 2931 void Assembler::mulsd(XMMRegister dst, Address src) { 2932 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2933 InstructionMark im(this); 2934 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2935 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 2936 attributes.set_rex_vex_w_reverted(); 2937 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2938 emit_int8(0x59); 2939 emit_operand(dst, src); 2940 } 2941 2942 void Assembler::mulsd(XMMRegister dst, XMMRegister src) { 2943 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2944 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2945 attributes.set_rex_vex_w_reverted(); 2946 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2947 emit_int8(0x59); 2948 emit_int8((unsigned char)(0xC0 | encode)); 2949 } 2950 2951 void Assembler::mulss(XMMRegister dst, Address src) { 2952 NOT_LP64(assert(VM_Version::supports_sse(), "")); 2953 InstructionMark im(this); 2954 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2955 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 2956 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2957 emit_int8(0x59); 2958 emit_operand(dst, src); 2959 } 2960 2961 void Assembler::mulss(XMMRegister dst, XMMRegister src) { 2962 NOT_LP64(assert(VM_Version::supports_sse(), "")); 2963 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2964 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2965 emit_int8(0x59); 2966 emit_int8((unsigned char)(0xC0 | encode)); 2967 } 2968 2969 void Assembler::negl(Register dst) { 2970 int encode = prefix_and_encode(dst->encoding()); 2971 emit_int8((unsigned char)0xF7); 2972 emit_int8((unsigned char)(0xD8 | encode)); 2973 } 2974 2975 void Assembler::nop(int i) { 2976 #ifdef ASSERT 2977 assert(i > 0, " "); 2978 // The fancy nops aren't currently recognized by debuggers making it a 2979 // pain to disassemble code while debugging. If asserts are on clearly 2980 // speed is not an issue so simply use the single byte traditional nop 2981 // to do alignment. 2982 2983 for (; i > 0 ; i--) emit_int8((unsigned char)0x90); 2984 return; 2985 2986 #endif // ASSERT 2987 2988 if (UseAddressNop && VM_Version::is_intel()) { 2989 // 2990 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel 2991 // 1: 0x90 2992 // 2: 0x66 0x90 2993 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding) 2994 // 4: 0x0F 0x1F 0x40 0x00 2995 // 5: 0x0F 0x1F 0x44 0x00 0x00 2996 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00 2997 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 2998 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 2999 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 3000 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 3001 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 3002 3003 // The rest coding is Intel specific - don't use consecutive address nops 3004 3005 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 3006 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 3007 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 3008 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 3009 3010 while(i >= 15) { 3011 // For Intel don't generate consecutive addess nops (mix with regular nops) 3012 i -= 15; 3013 emit_int8(0x66); // size prefix 3014 emit_int8(0x66); // size prefix 3015 emit_int8(0x66); // size prefix 3016 addr_nop_8(); 3017 emit_int8(0x66); // size prefix 3018 emit_int8(0x66); // size prefix 3019 emit_int8(0x66); // size prefix 3020 emit_int8((unsigned char)0x90); 3021 // nop 3022 } 3023 switch (i) { 3024 case 14: 3025 emit_int8(0x66); // size prefix 3026 case 13: 3027 emit_int8(0x66); // size prefix 3028 case 12: 3029 addr_nop_8(); 3030 emit_int8(0x66); // size prefix 3031 emit_int8(0x66); // size prefix 3032 emit_int8(0x66); // size prefix 3033 emit_int8((unsigned char)0x90); 3034 // nop 3035 break; 3036 case 11: 3037 emit_int8(0x66); // size prefix 3038 case 10: 3039 emit_int8(0x66); // size prefix 3040 case 9: 3041 emit_int8(0x66); // size prefix 3042 case 8: 3043 addr_nop_8(); 3044 break; 3045 case 7: 3046 addr_nop_7(); 3047 break; 3048 case 6: 3049 emit_int8(0x66); // size prefix 3050 case 5: 3051 addr_nop_5(); 3052 break; 3053 case 4: 3054 addr_nop_4(); 3055 break; 3056 case 3: 3057 // Don't use "0x0F 0x1F 0x00" - need patching safe padding 3058 emit_int8(0x66); // size prefix 3059 case 2: 3060 emit_int8(0x66); // size prefix 3061 case 1: 3062 emit_int8((unsigned char)0x90); 3063 // nop 3064 break; 3065 default: 3066 assert(i == 0, " "); 3067 } 3068 return; 3069 } 3070 if (UseAddressNop && VM_Version::is_amd()) { 3071 // 3072 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD. 3073 // 1: 0x90 3074 // 2: 0x66 0x90 3075 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding) 3076 // 4: 0x0F 0x1F 0x40 0x00 3077 // 5: 0x0F 0x1F 0x44 0x00 0x00 3078 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00 3079 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 3080 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 3081 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 3082 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 3083 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 3084 3085 // The rest coding is AMD specific - use consecutive address nops 3086 3087 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00 3088 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00 3089 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 3090 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 3091 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 3092 // Size prefixes (0x66) are added for larger sizes 3093 3094 while(i >= 22) { 3095 i -= 11; 3096 emit_int8(0x66); // size prefix 3097 emit_int8(0x66); // size prefix 3098 emit_int8(0x66); // size prefix 3099 addr_nop_8(); 3100 } 3101 // Generate first nop for size between 21-12 3102 switch (i) { 3103 case 21: 3104 i -= 1; 3105 emit_int8(0x66); // size prefix 3106 case 20: 3107 case 19: 3108 i -= 1; 3109 emit_int8(0x66); // size prefix 3110 case 18: 3111 case 17: 3112 i -= 1; 3113 emit_int8(0x66); // size prefix 3114 case 16: 3115 case 15: 3116 i -= 8; 3117 addr_nop_8(); 3118 break; 3119 case 14: 3120 case 13: 3121 i -= 7; 3122 addr_nop_7(); 3123 break; 3124 case 12: 3125 i -= 6; 3126 emit_int8(0x66); // size prefix 3127 addr_nop_5(); 3128 break; 3129 default: 3130 assert(i < 12, " "); 3131 } 3132 3133 // Generate second nop for size between 11-1 3134 switch (i) { 3135 case 11: 3136 emit_int8(0x66); // size prefix 3137 case 10: 3138 emit_int8(0x66); // size prefix 3139 case 9: 3140 emit_int8(0x66); // size prefix 3141 case 8: 3142 addr_nop_8(); 3143 break; 3144 case 7: 3145 addr_nop_7(); 3146 break; 3147 case 6: 3148 emit_int8(0x66); // size prefix 3149 case 5: 3150 addr_nop_5(); 3151 break; 3152 case 4: 3153 addr_nop_4(); 3154 break; 3155 case 3: 3156 // Don't use "0x0F 0x1F 0x00" - need patching safe padding 3157 emit_int8(0x66); // size prefix 3158 case 2: 3159 emit_int8(0x66); // size prefix 3160 case 1: 3161 emit_int8((unsigned char)0x90); 3162 // nop 3163 break; 3164 default: 3165 assert(i == 0, " "); 3166 } 3167 return; 3168 } 3169 3170 // Using nops with size prefixes "0x66 0x90". 3171 // From AMD Optimization Guide: 3172 // 1: 0x90 3173 // 2: 0x66 0x90 3174 // 3: 0x66 0x66 0x90 3175 // 4: 0x66 0x66 0x66 0x90 3176 // 5: 0x66 0x66 0x90 0x66 0x90 3177 // 6: 0x66 0x66 0x90 0x66 0x66 0x90 3178 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 3179 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90 3180 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90 3181 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90 3182 // 3183 while(i > 12) { 3184 i -= 4; 3185 emit_int8(0x66); // size prefix 3186 emit_int8(0x66); 3187 emit_int8(0x66); 3188 emit_int8((unsigned char)0x90); 3189 // nop 3190 } 3191 // 1 - 12 nops 3192 if(i > 8) { 3193 if(i > 9) { 3194 i -= 1; 3195 emit_int8(0x66); 3196 } 3197 i -= 3; 3198 emit_int8(0x66); 3199 emit_int8(0x66); 3200 emit_int8((unsigned char)0x90); 3201 } 3202 // 1 - 8 nops 3203 if(i > 4) { 3204 if(i > 6) { 3205 i -= 1; 3206 emit_int8(0x66); 3207 } 3208 i -= 3; 3209 emit_int8(0x66); 3210 emit_int8(0x66); 3211 emit_int8((unsigned char)0x90); 3212 } 3213 switch (i) { 3214 case 4: 3215 emit_int8(0x66); 3216 case 3: 3217 emit_int8(0x66); 3218 case 2: 3219 emit_int8(0x66); 3220 case 1: 3221 emit_int8((unsigned char)0x90); 3222 break; 3223 default: 3224 assert(i == 0, " "); 3225 } 3226 } 3227 3228 void Assembler::notl(Register dst) { 3229 int encode = prefix_and_encode(dst->encoding()); 3230 emit_int8((unsigned char)0xF7); 3231 emit_int8((unsigned char)(0xD0 | encode)); 3232 } 3233 3234 void Assembler::orl(Address dst, int32_t imm32) { 3235 InstructionMark im(this); 3236 prefix(dst); 3237 emit_arith_operand(0x81, rcx, dst, imm32); 3238 } 3239 3240 void Assembler::orl(Register dst, int32_t imm32) { 3241 prefix(dst); 3242 emit_arith(0x81, 0xC8, dst, imm32); 3243 } 3244 3245 void Assembler::orl(Register dst, Address src) { 3246 InstructionMark im(this); 3247 prefix(src, dst); 3248 emit_int8(0x0B); 3249 emit_operand(dst, src); 3250 } 3251 3252 void Assembler::orl(Register dst, Register src) { 3253 (void) prefix_and_encode(dst->encoding(), src->encoding()); 3254 emit_arith(0x0B, 0xC0, dst, src); 3255 } 3256 3257 void Assembler::orl(Address dst, Register src) { 3258 InstructionMark im(this); 3259 prefix(dst, src); 3260 emit_int8(0x09); 3261 emit_operand(src, dst); 3262 } 3263 3264 void Assembler::packuswb(XMMRegister dst, Address src) { 3265 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 3266 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); 3267 InstructionMark im(this); 3268 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 3269 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 3270 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3271 emit_int8(0x67); 3272 emit_operand(dst, src); 3273 } 3274 3275 void Assembler::packuswb(XMMRegister dst, XMMRegister src) { 3276 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 3277 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 3278 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3279 emit_int8(0x67); 3280 emit_int8((unsigned char)(0xC0 | encode)); 3281 } 3282 3283 void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 3284 assert(UseAVX > 0, "some form of AVX must be enabled"); 3285 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 3286 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3287 emit_int8(0x67); 3288 emit_int8((unsigned char)(0xC0 | encode)); 3289 } 3290 3291 void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len) { 3292 assert(VM_Version::supports_avx2(), ""); 3293 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 3294 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3295 emit_int8(0x00); 3296 emit_int8(0xC0 | encode); 3297 emit_int8(imm8); 3298 } 3299 3300 void Assembler::vperm2i128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) { 3301 assert(VM_Version::supports_avx2(), ""); 3302 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 3303 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3304 emit_int8(0x46); 3305 emit_int8(0xC0 | encode); 3306 emit_int8(imm8); 3307 } 3308 3309 void Assembler::vperm2f128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) { 3310 assert(VM_Version::supports_avx(), ""); 3311 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 3312 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3313 emit_int8(0x06); 3314 emit_int8(0xC0 | encode); 3315 emit_int8(imm8); 3316 } 3317 3318 3319 void Assembler::pause() { 3320 emit_int8((unsigned char)0xF3); 3321 emit_int8((unsigned char)0x90); 3322 } 3323 3324 void Assembler::ud2() { 3325 emit_int8(0x0F); 3326 emit_int8(0x0B); 3327 } 3328 3329 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) { 3330 assert(VM_Version::supports_sse4_2(), ""); 3331 InstructionMark im(this); 3332 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 3333 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3334 emit_int8(0x61); 3335 emit_operand(dst, src); 3336 emit_int8(imm8); 3337 } 3338 3339 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) { 3340 assert(VM_Version::supports_sse4_2(), ""); 3341 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 3342 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3343 emit_int8(0x61); 3344 emit_int8((unsigned char)(0xC0 | encode)); 3345 emit_int8(imm8); 3346 } 3347 3348 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst 3349 void Assembler::pcmpeqb(XMMRegister dst, XMMRegister src) { 3350 assert(VM_Version::supports_sse2(), ""); 3351 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 3352 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3353 emit_int8(0x74); 3354 emit_int8((unsigned char)(0xC0 | encode)); 3355 } 3356 3357 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst 3358 void Assembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 3359 assert(VM_Version::supports_avx(), ""); 3360 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 3361 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3362 emit_int8(0x74); 3363 emit_int8((unsigned char)(0xC0 | encode)); 3364 } 3365 3366 // In this context, kdst is written the mask used to process the equal components 3367 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) { 3368 assert(VM_Version::supports_avx512bw(), ""); 3369 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 3370 attributes.set_is_evex_instruction(); 3371 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3372 emit_int8(0x74); 3373 emit_int8((unsigned char)(0xC0 | encode)); 3374 } 3375 3376 void Assembler::evpcmpgtb(KRegister kdst, XMMRegister nds, Address src, int vector_len) { 3377 assert(VM_Version::supports_avx512vlbw(), ""); 3378 InstructionMark im(this); 3379 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 3380 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 3381 attributes.set_is_evex_instruction(); 3382 int dst_enc = kdst->encoding(); 3383 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3384 emit_int8(0x64); 3385 emit_operand(as_Register(dst_enc), src); 3386 } 3387 3388 void Assembler::evpcmpgtb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len) { 3389 assert(is_vector_masking(), ""); 3390 assert(VM_Version::supports_avx512vlbw(), ""); 3391 InstructionMark im(this); 3392 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 3393 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 3394 attributes.reset_is_clear_context(); 3395 attributes.set_embedded_opmask_register_specifier(mask); 3396 attributes.set_is_evex_instruction(); 3397 int dst_enc = kdst->encoding(); 3398 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3399 emit_int8(0x64); 3400 emit_operand(as_Register(dst_enc), src); 3401 } 3402 3403 void Assembler::evpcmpuw(KRegister kdst, XMMRegister nds, XMMRegister src, ComparisonPredicate vcc, int vector_len) { 3404 assert(VM_Version::supports_avx512vlbw(), ""); 3405 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 3406 attributes.set_is_evex_instruction(); 3407 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3408 emit_int8(0x3E); 3409 emit_int8((unsigned char)(0xC0 | encode)); 3410 emit_int8(vcc); 3411 } 3412 3413 void Assembler::evpcmpuw(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, ComparisonPredicate vcc, int vector_len) { 3414 assert(is_vector_masking(), ""); 3415 assert(VM_Version::supports_avx512vlbw(), ""); 3416 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 3417 attributes.reset_is_clear_context(); 3418 attributes.set_embedded_opmask_register_specifier(mask); 3419 attributes.set_is_evex_instruction(); 3420 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3421 emit_int8(0x3E); 3422 emit_int8((unsigned char)(0xC0 | encode)); 3423 emit_int8(vcc); 3424 } 3425 3426 void Assembler::evpcmpuw(KRegister kdst, XMMRegister nds, Address src, ComparisonPredicate vcc, int vector_len) { 3427 assert(VM_Version::supports_avx512vlbw(), ""); 3428 InstructionMark im(this); 3429 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 3430 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 3431 attributes.set_is_evex_instruction(); 3432 int dst_enc = kdst->encoding(); 3433 vex_prefix(src, nds->encoding(), kdst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3434 emit_int8(0x3E); 3435 emit_operand(as_Register(dst_enc), src); 3436 emit_int8(vcc); 3437 } 3438 3439 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, Address src, int vector_len) { 3440 assert(VM_Version::supports_avx512bw(), ""); 3441 InstructionMark im(this); 3442 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 3443 attributes.set_is_evex_instruction(); 3444 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 3445 int dst_enc = kdst->encoding(); 3446 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3447 emit_int8(0x74); 3448 emit_operand(as_Register(dst_enc), src); 3449 } 3450 3451 void Assembler::evpcmpeqb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len) { 3452 assert(VM_Version::supports_avx512vlbw(), ""); 3453 assert(is_vector_masking(), ""); // For stub code use only 3454 InstructionMark im(this); 3455 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_reg_mask */ false, /* uses_vl */ false); 3456 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 3457 attributes.reset_is_clear_context(); 3458 attributes.set_embedded_opmask_register_specifier(mask); 3459 attributes.set_is_evex_instruction(); 3460 vex_prefix(src, nds->encoding(), kdst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3461 emit_int8(0x74); 3462 emit_operand(as_Register(kdst->encoding()), src); 3463 } 3464 3465 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst 3466 void Assembler::pcmpeqw(XMMRegister dst, XMMRegister src) { 3467 assert(VM_Version::supports_sse2(), ""); 3468 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 3469 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3470 emit_int8(0x75); 3471 emit_int8((unsigned char)(0xC0 | encode)); 3472 } 3473 3474 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst 3475 void Assembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 3476 assert(VM_Version::supports_avx(), ""); 3477 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 3478 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3479 emit_int8(0x75); 3480 emit_int8((unsigned char)(0xC0 | encode)); 3481 } 3482 3483 // In this context, kdst is written the mask used to process the equal components 3484 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) { 3485 assert(VM_Version::supports_avx512bw(), ""); 3486 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 3487 attributes.set_is_evex_instruction(); 3488 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3489 emit_int8(0x75); 3490 emit_int8((unsigned char)(0xC0 | encode)); 3491 } 3492 3493 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, Address src, int vector_len) { 3494 assert(VM_Version::supports_avx512bw(), ""); 3495 InstructionMark im(this); 3496 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 3497 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 3498 attributes.set_is_evex_instruction(); 3499 int dst_enc = kdst->encoding(); 3500 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3501 emit_int8(0x75); 3502 emit_operand(as_Register(dst_enc), src); 3503 } 3504 3505 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst 3506 void Assembler::pcmpeqd(XMMRegister dst, XMMRegister src) { 3507 assert(VM_Version::supports_sse2(), ""); 3508 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 3509 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3510 emit_int8(0x76); 3511 emit_int8((unsigned char)(0xC0 | encode)); 3512 } 3513 3514 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst 3515 void Assembler::vpcmpeqd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 3516 assert(VM_Version::supports_avx(), ""); 3517 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 3518 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3519 emit_int8(0x76); 3520 emit_int8((unsigned char)(0xC0 | encode)); 3521 } 3522 3523 // In this context, kdst is written the mask used to process the equal components 3524 void Assembler::evpcmpeqd(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) { 3525 assert(VM_Version::supports_evex(), ""); 3526 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 3527 attributes.set_is_evex_instruction(); 3528 attributes.reset_is_clear_context(); 3529 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3530 emit_int8(0x76); 3531 emit_int8((unsigned char)(0xC0 | encode)); 3532 } 3533 3534 void Assembler::evpcmpeqd(KRegister kdst, XMMRegister nds, Address src, int vector_len) { 3535 assert(VM_Version::supports_evex(), ""); 3536 InstructionMark im(this); 3537 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 3538 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 3539 attributes.reset_is_clear_context(); 3540 attributes.set_is_evex_instruction(); 3541 int dst_enc = kdst->encoding(); 3542 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3543 emit_int8(0x76); 3544 emit_operand(as_Register(dst_enc), src); 3545 } 3546 3547 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst 3548 void Assembler::pcmpeqq(XMMRegister dst, XMMRegister src) { 3549 assert(VM_Version::supports_sse4_1(), ""); 3550 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 3551 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 3552 emit_int8(0x29); 3553 emit_int8((unsigned char)(0xC0 | encode)); 3554 } 3555 3556 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst 3557 void Assembler::vpcmpeqq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 3558 assert(VM_Version::supports_avx(), ""); 3559 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 3560 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 3561 emit_int8(0x29); 3562 emit_int8((unsigned char)(0xC0 | encode)); 3563 } 3564 3565 // In this context, kdst is written the mask used to process the equal components 3566 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) { 3567 assert(VM_Version::supports_evex(), ""); 3568 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 3569 attributes.reset_is_clear_context(); 3570 attributes.set_is_evex_instruction(); 3571 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 3572 emit_int8(0x29); 3573 emit_int8((unsigned char)(0xC0 | encode)); 3574 } 3575 3576 // In this context, kdst is written the mask used to process the equal components 3577 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, Address src, int vector_len) { 3578 assert(VM_Version::supports_evex(), ""); 3579 InstructionMark im(this); 3580 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 3581 attributes.reset_is_clear_context(); 3582 attributes.set_is_evex_instruction(); 3583 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 3584 int dst_enc = kdst->encoding(); 3585 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 3586 emit_int8(0x29); 3587 emit_operand(as_Register(dst_enc), src); 3588 } 3589 3590 void Assembler::pmovmskb(Register dst, XMMRegister src) { 3591 assert(VM_Version::supports_sse2(), ""); 3592 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 3593 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3594 emit_int8((unsigned char)0xD7); 3595 emit_int8((unsigned char)(0xC0 | encode)); 3596 } 3597 3598 void Assembler::vpmovmskb(Register dst, XMMRegister src) { 3599 assert(VM_Version::supports_avx2(), ""); 3600 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 3601 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3602 emit_int8((unsigned char)0xD7); 3603 emit_int8((unsigned char)(0xC0 | encode)); 3604 } 3605 3606 void Assembler::pextrd(Register dst, XMMRegister src, int imm8) { 3607 assert(VM_Version::supports_sse4_1(), ""); 3608 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false); 3609 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3610 emit_int8(0x16); 3611 emit_int8((unsigned char)(0xC0 | encode)); 3612 emit_int8(imm8); 3613 } 3614 3615 void Assembler::pextrd(Address dst, XMMRegister src, int imm8) { 3616 assert(VM_Version::supports_sse4_1(), ""); 3617 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false); 3618 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 3619 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3620 emit_int8(0x16); 3621 emit_operand(src, dst); 3622 emit_int8(imm8); 3623 } 3624 3625 void Assembler::pextrq(Register dst, XMMRegister src, int imm8) { 3626 assert(VM_Version::supports_sse4_1(), ""); 3627 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false); 3628 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3629 emit_int8(0x16); 3630 emit_int8((unsigned char)(0xC0 | encode)); 3631 emit_int8(imm8); 3632 } 3633 3634 void Assembler::pextrq(Address dst, XMMRegister src, int imm8) { 3635 assert(VM_Version::supports_sse4_1(), ""); 3636 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false); 3637 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 3638 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3639 emit_int8(0x16); 3640 emit_operand(src, dst); 3641 emit_int8(imm8); 3642 } 3643 3644 void Assembler::pextrw(Register dst, XMMRegister src, int imm8) { 3645 assert(VM_Version::supports_sse2(), ""); 3646 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false); 3647 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3648 emit_int8((unsigned char)0xC5); 3649 emit_int8((unsigned char)(0xC0 | encode)); 3650 emit_int8(imm8); 3651 } 3652 3653 void Assembler::pextrw(Address dst, XMMRegister src, int imm8) { 3654 assert(VM_Version::supports_sse4_1(), ""); 3655 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false); 3656 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit); 3657 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3658 emit_int8((unsigned char)0x15); 3659 emit_operand(src, dst); 3660 emit_int8(imm8); 3661 } 3662 3663 void Assembler::pextrb(Address dst, XMMRegister src, int imm8) { 3664 assert(VM_Version::supports_sse4_1(), ""); 3665 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false); 3666 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit); 3667 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3668 emit_int8(0x14); 3669 emit_operand(src, dst); 3670 emit_int8(imm8); 3671 } 3672 3673 void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) { 3674 assert(VM_Version::supports_sse4_1(), ""); 3675 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false); 3676 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3677 emit_int8(0x22); 3678 emit_int8((unsigned char)(0xC0 | encode)); 3679 emit_int8(imm8); 3680 } 3681 3682 void Assembler::pinsrd(XMMRegister dst, Address src, int imm8) { 3683 assert(VM_Version::supports_sse4_1(), ""); 3684 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false); 3685 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 3686 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3687 emit_int8(0x22); 3688 emit_operand(dst,src); 3689 emit_int8(imm8); 3690 } 3691 3692 void Assembler::pinsrq(XMMRegister dst, Register src, int imm8) { 3693 assert(VM_Version::supports_sse4_1(), ""); 3694 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false); 3695 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3696 emit_int8(0x22); 3697 emit_int8((unsigned char)(0xC0 | encode)); 3698 emit_int8(imm8); 3699 } 3700 3701 void Assembler::pinsrq(XMMRegister dst, Address src, int imm8) { 3702 assert(VM_Version::supports_sse4_1(), ""); 3703 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false); 3704 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 3705 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3706 emit_int8(0x22); 3707 emit_operand(dst, src); 3708 emit_int8(imm8); 3709 } 3710 3711 void Assembler::pinsrw(XMMRegister dst, Register src, int imm8) { 3712 assert(VM_Version::supports_sse2(), ""); 3713 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false); 3714 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3715 emit_int8((unsigned char)0xC4); 3716 emit_int8((unsigned char)(0xC0 | encode)); 3717 emit_int8(imm8); 3718 } 3719 3720 void Assembler::pinsrw(XMMRegister dst, Address src, int imm8) { 3721 assert(VM_Version::supports_sse2(), ""); 3722 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false); 3723 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit); 3724 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3725 emit_int8((unsigned char)0xC4); 3726 emit_operand(dst, src); 3727 emit_int8(imm8); 3728 } 3729 3730 void Assembler::pinsrb(XMMRegister dst, Address src, int imm8) { 3731 assert(VM_Version::supports_sse4_1(), ""); 3732 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false); 3733 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit); 3734 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3735 emit_int8(0x20); 3736 emit_operand(dst, src); 3737 emit_int8(imm8); 3738 } 3739 3740 void Assembler::pmovzxbw(XMMRegister dst, Address src) { 3741 assert(VM_Version::supports_sse4_1(), ""); 3742 InstructionMark im(this); 3743 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false); 3744 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit); 3745 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 3746 emit_int8(0x30); 3747 emit_operand(dst, src); 3748 } 3749 3750 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) { 3751 assert(VM_Version::supports_sse4_1(), ""); 3752 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false); 3753 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 3754 emit_int8(0x30); 3755 emit_int8((unsigned char)(0xC0 | encode)); 3756 } 3757 3758 void Assembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) { 3759 assert(VM_Version::supports_avx(), ""); 3760 InstructionMark im(this); 3761 assert(dst != xnoreg, "sanity"); 3762 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false); 3763 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit); 3764 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 3765 emit_int8(0x30); 3766 emit_operand(dst, src); 3767 } 3768 3769 void Assembler::evpmovzxbw(XMMRegister dst, KRegister mask, Address src, int vector_len) { 3770 assert(is_vector_masking(), ""); 3771 assert(VM_Version::supports_avx512vlbw(), ""); 3772 assert(dst != xnoreg, "sanity"); 3773 InstructionMark im(this); 3774 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 3775 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit); 3776 attributes.set_embedded_opmask_register_specifier(mask); 3777 attributes.set_is_evex_instruction(); 3778 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 3779 emit_int8(0x30); 3780 emit_operand(dst, src); 3781 } 3782 3783 void Assembler::evpmovwb(Address dst, XMMRegister src, int vector_len) { 3784 assert(VM_Version::supports_avx512vlbw(), ""); 3785 assert(src != xnoreg, "sanity"); 3786 InstructionMark im(this); 3787 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 3788 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit); 3789 attributes.set_is_evex_instruction(); 3790 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes); 3791 emit_int8(0x30); 3792 emit_operand(src, dst); 3793 } 3794 3795 void Assembler::evpmovwb(Address dst, KRegister mask, XMMRegister src, int vector_len) { 3796 assert(is_vector_masking(), ""); 3797 assert(VM_Version::supports_avx512vlbw(), ""); 3798 assert(src != xnoreg, "sanity"); 3799 InstructionMark im(this); 3800 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 3801 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit); 3802 attributes.reset_is_clear_context(); 3803 attributes.set_embedded_opmask_register_specifier(mask); 3804 attributes.set_is_evex_instruction(); 3805 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes); 3806 emit_int8(0x30); 3807 emit_operand(src, dst); 3808 } 3809 3810 // generic 3811 void Assembler::pop(Register dst) { 3812 int encode = prefix_and_encode(dst->encoding()); 3813 emit_int8(0x58 | encode); 3814 } 3815 3816 void Assembler::popcntl(Register dst, Address src) { 3817 assert(VM_Version::supports_popcnt(), "must support"); 3818 InstructionMark im(this); 3819 emit_int8((unsigned char)0xF3); 3820 prefix(src, dst); 3821 emit_int8(0x0F); 3822 emit_int8((unsigned char)0xB8); 3823 emit_operand(dst, src); 3824 } 3825 3826 void Assembler::popcntl(Register dst, Register src) { 3827 assert(VM_Version::supports_popcnt(), "must support"); 3828 emit_int8((unsigned char)0xF3); 3829 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 3830 emit_int8(0x0F); 3831 emit_int8((unsigned char)0xB8); 3832 emit_int8((unsigned char)(0xC0 | encode)); 3833 } 3834 3835 void Assembler::popf() { 3836 emit_int8((unsigned char)0x9D); 3837 } 3838 3839 #ifndef _LP64 // no 32bit push/pop on amd64 3840 void Assembler::popl(Address dst) { 3841 // NOTE: this will adjust stack by 8byte on 64bits 3842 InstructionMark im(this); 3843 prefix(dst); 3844 emit_int8((unsigned char)0x8F); 3845 emit_operand(rax, dst); 3846 } 3847 #endif 3848 3849 void Assembler::prefetch_prefix(Address src) { 3850 prefix(src); 3851 emit_int8(0x0F); 3852 } 3853 3854 void Assembler::prefetchnta(Address src) { 3855 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); 3856 InstructionMark im(this); 3857 prefetch_prefix(src); 3858 emit_int8(0x18); 3859 emit_operand(rax, src); // 0, src 3860 } 3861 3862 void Assembler::prefetchr(Address src) { 3863 assert(VM_Version::supports_3dnow_prefetch(), "must support"); 3864 InstructionMark im(this); 3865 prefetch_prefix(src); 3866 emit_int8(0x0D); 3867 emit_operand(rax, src); // 0, src 3868 } 3869 3870 void Assembler::prefetcht0(Address src) { 3871 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); 3872 InstructionMark im(this); 3873 prefetch_prefix(src); 3874 emit_int8(0x18); 3875 emit_operand(rcx, src); // 1, src 3876 } 3877 3878 void Assembler::prefetcht1(Address src) { 3879 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); 3880 InstructionMark im(this); 3881 prefetch_prefix(src); 3882 emit_int8(0x18); 3883 emit_operand(rdx, src); // 2, src 3884 } 3885 3886 void Assembler::prefetcht2(Address src) { 3887 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); 3888 InstructionMark im(this); 3889 prefetch_prefix(src); 3890 emit_int8(0x18); 3891 emit_operand(rbx, src); // 3, src 3892 } 3893 3894 void Assembler::prefetchw(Address src) { 3895 assert(VM_Version::supports_3dnow_prefetch(), "must support"); 3896 InstructionMark im(this); 3897 prefetch_prefix(src); 3898 emit_int8(0x0D); 3899 emit_operand(rcx, src); // 1, src 3900 } 3901 3902 void Assembler::prefix(Prefix p) { 3903 emit_int8(p); 3904 } 3905 3906 void Assembler::pshufb(XMMRegister dst, XMMRegister src) { 3907 assert(VM_Version::supports_ssse3(), ""); 3908 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false); 3909 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 3910 emit_int8(0x00); 3911 emit_int8((unsigned char)(0xC0 | encode)); 3912 } 3913 3914 void Assembler::vpshufb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 3915 assert(vector_len == AVX_128bit? VM_Version::supports_avx() : 3916 vector_len == AVX_256bit? VM_Version::supports_avx2() : 3917 0, ""); 3918 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 3919 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 3920 emit_int8(0x00); 3921 emit_int8((unsigned char)(0xC0 | encode)); 3922 } 3923 3924 void Assembler::pshufb(XMMRegister dst, Address src) { 3925 assert(VM_Version::supports_ssse3(), ""); 3926 InstructionMark im(this); 3927 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false); 3928 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 3929 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 3930 emit_int8(0x00); 3931 emit_operand(dst, src); 3932 } 3933 3934 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) { 3935 assert(isByte(mode), "invalid value"); 3936 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 3937 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit; 3938 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 3939 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3940 emit_int8(0x70); 3941 emit_int8((unsigned char)(0xC0 | encode)); 3942 emit_int8(mode & 0xFF); 3943 } 3944 3945 void Assembler::vpshufd(XMMRegister dst, XMMRegister src, int mode, int vector_len) { 3946 assert(vector_len == AVX_128bit? VM_Version::supports_avx() : 3947 vector_len == AVX_256bit? VM_Version::supports_avx2() : 3948 0, ""); 3949 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 3950 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 3951 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3952 emit_int8(0x70); 3953 emit_int8((unsigned char)(0xC0 | encode)); 3954 emit_int8(mode & 0xFF); 3955 } 3956 3957 void Assembler::pshufd(XMMRegister dst, Address src, int mode) { 3958 assert(isByte(mode), "invalid value"); 3959 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 3960 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); 3961 InstructionMark im(this); 3962 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 3963 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 3964 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3965 emit_int8(0x70); 3966 emit_operand(dst, src); 3967 emit_int8(mode & 0xFF); 3968 } 3969 3970 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) { 3971 assert(isByte(mode), "invalid value"); 3972 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 3973 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false); 3974 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 3975 emit_int8(0x70); 3976 emit_int8((unsigned char)(0xC0 | encode)); 3977 emit_int8(mode & 0xFF); 3978 } 3979 3980 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) { 3981 assert(isByte(mode), "invalid value"); 3982 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 3983 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); 3984 InstructionMark im(this); 3985 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false); 3986 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 3987 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 3988 emit_int8(0x70); 3989 emit_operand(dst, src); 3990 emit_int8(mode & 0xFF); 3991 } 3992 3993 void Assembler::psrldq(XMMRegister dst, int shift) { 3994 // Shift left 128 bit value in dst XMMRegister by shift number of bytes. 3995 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 3996 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false); 3997 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3998 emit_int8(0x73); 3999 emit_int8((unsigned char)(0xC0 | encode)); 4000 emit_int8(shift); 4001 } 4002 4003 void Assembler::pslldq(XMMRegister dst, int shift) { 4004 // Shift left 128 bit value in dst XMMRegister by shift number of bytes. 4005 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4006 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false); 4007 // XMM7 is for /7 encoding: 66 0F 73 /7 ib 4008 int encode = simd_prefix_and_encode(xmm7, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4009 emit_int8(0x73); 4010 emit_int8((unsigned char)(0xC0 | encode)); 4011 emit_int8(shift); 4012 } 4013 4014 void Assembler::ptest(XMMRegister dst, Address src) { 4015 assert(VM_Version::supports_sse4_1(), ""); 4016 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); 4017 InstructionMark im(this); 4018 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 4019 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 4020 emit_int8(0x17); 4021 emit_operand(dst, src); 4022 } 4023 4024 void Assembler::ptest(XMMRegister dst, XMMRegister src) { 4025 assert(VM_Version::supports_sse4_1(), ""); 4026 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 4027 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 4028 emit_int8(0x17); 4029 emit_int8((unsigned char)(0xC0 | encode)); 4030 } 4031 4032 void Assembler::vptest(XMMRegister dst, Address src) { 4033 assert(VM_Version::supports_avx(), ""); 4034 InstructionMark im(this); 4035 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 4036 assert(dst != xnoreg, "sanity"); 4037 // swap src<->dst for encoding 4038 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 4039 emit_int8(0x17); 4040 emit_operand(dst, src); 4041 } 4042 4043 void Assembler::vptest(XMMRegister dst, XMMRegister src) { 4044 assert(VM_Version::supports_avx(), ""); 4045 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 4046 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 4047 emit_int8(0x17); 4048 emit_int8((unsigned char)(0xC0 | encode)); 4049 } 4050 4051 void Assembler::punpcklbw(XMMRegister dst, Address src) { 4052 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4053 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); 4054 InstructionMark im(this); 4055 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ false, /* uses_vl */ true); 4056 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 4057 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4058 emit_int8(0x60); 4059 emit_operand(dst, src); 4060 } 4061 4062 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) { 4063 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4064 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ false, /* uses_vl */ true); 4065 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4066 emit_int8(0x60); 4067 emit_int8((unsigned char)(0xC0 | encode)); 4068 } 4069 4070 void Assembler::punpckldq(XMMRegister dst, Address src) { 4071 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4072 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); 4073 InstructionMark im(this); 4074 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 4075 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 4076 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4077 emit_int8(0x62); 4078 emit_operand(dst, src); 4079 } 4080 4081 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) { 4082 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4083 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 4084 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4085 emit_int8(0x62); 4086 emit_int8((unsigned char)(0xC0 | encode)); 4087 } 4088 4089 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) { 4090 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4091 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 4092 attributes.set_rex_vex_w_reverted(); 4093 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4094 emit_int8(0x6C); 4095 emit_int8((unsigned char)(0xC0 | encode)); 4096 } 4097 4098 void Assembler::push(int32_t imm32) { 4099 // in 64bits we push 64bits onto the stack but only 4100 // take a 32bit immediate 4101 emit_int8(0x68); 4102 emit_int32(imm32); 4103 } 4104 4105 void Assembler::push(Register src) { 4106 int encode = prefix_and_encode(src->encoding()); 4107 4108 emit_int8(0x50 | encode); 4109 } 4110 4111 void Assembler::pushf() { 4112 emit_int8((unsigned char)0x9C); 4113 } 4114 4115 #ifndef _LP64 // no 32bit push/pop on amd64 4116 void Assembler::pushl(Address src) { 4117 // Note this will push 64bit on 64bit 4118 InstructionMark im(this); 4119 prefix(src); 4120 emit_int8((unsigned char)0xFF); 4121 emit_operand(rsi, src); 4122 } 4123 #endif 4124 4125 void Assembler::rcll(Register dst, int imm8) { 4126 assert(isShiftCount(imm8), "illegal shift count"); 4127 int encode = prefix_and_encode(dst->encoding()); 4128 if (imm8 == 1) { 4129 emit_int8((unsigned char)0xD1); 4130 emit_int8((unsigned char)(0xD0 | encode)); 4131 } else { 4132 emit_int8((unsigned char)0xC1); 4133 emit_int8((unsigned char)0xD0 | encode); 4134 emit_int8(imm8); 4135 } 4136 } 4137 4138 void Assembler::rcpps(XMMRegister dst, XMMRegister src) { 4139 NOT_LP64(assert(VM_Version::supports_sse(), "")); 4140 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 4141 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 4142 emit_int8(0x53); 4143 emit_int8((unsigned char)(0xC0 | encode)); 4144 } 4145 4146 void Assembler::rcpss(XMMRegister dst, XMMRegister src) { 4147 NOT_LP64(assert(VM_Version::supports_sse(), "")); 4148 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 4149 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 4150 emit_int8(0x53); 4151 emit_int8((unsigned char)(0xC0 | encode)); 4152 } 4153 4154 void Assembler::rdtsc() { 4155 emit_int8((unsigned char)0x0F); 4156 emit_int8((unsigned char)0x31); 4157 } 4158 4159 // copies data from [esi] to [edi] using rcx pointer sized words 4160 // generic 4161 void Assembler::rep_mov() { 4162 emit_int8((unsigned char)0xF3); 4163 // MOVSQ 4164 LP64_ONLY(prefix(REX_W)); 4165 emit_int8((unsigned char)0xA5); 4166 } 4167 4168 // sets rcx bytes with rax, value at [edi] 4169 void Assembler::rep_stosb() { 4170 emit_int8((unsigned char)0xF3); // REP 4171 LP64_ONLY(prefix(REX_W)); 4172 emit_int8((unsigned char)0xAA); // STOSB 4173 } 4174 4175 // sets rcx pointer sized words with rax, value at [edi] 4176 // generic 4177 void Assembler::rep_stos() { 4178 emit_int8((unsigned char)0xF3); // REP 4179 LP64_ONLY(prefix(REX_W)); // LP64:STOSQ, LP32:STOSD 4180 emit_int8((unsigned char)0xAB); 4181 } 4182 4183 // scans rcx pointer sized words at [edi] for occurance of rax, 4184 // generic 4185 void Assembler::repne_scan() { // repne_scan 4186 emit_int8((unsigned char)0xF2); 4187 // SCASQ 4188 LP64_ONLY(prefix(REX_W)); 4189 emit_int8((unsigned char)0xAF); 4190 } 4191 4192 #ifdef _LP64 4193 // scans rcx 4 byte words at [edi] for occurance of rax, 4194 // generic 4195 void Assembler::repne_scanl() { // repne_scan 4196 emit_int8((unsigned char)0xF2); 4197 // SCASL 4198 emit_int8((unsigned char)0xAF); 4199 } 4200 #endif 4201 4202 void Assembler::ret(int imm16) { 4203 if (imm16 == 0) { 4204 emit_int8((unsigned char)0xC3); 4205 } else { 4206 emit_int8((unsigned char)0xC2); 4207 emit_int16(imm16); 4208 } 4209 } 4210 4211 void Assembler::sahf() { 4212 #ifdef _LP64 4213 // Not supported in 64bit mode 4214 ShouldNotReachHere(); 4215 #endif 4216 emit_int8((unsigned char)0x9E); 4217 } 4218 4219 void Assembler::sarl(Register dst, int imm8) { 4220 int encode = prefix_and_encode(dst->encoding()); 4221 assert(isShiftCount(imm8), "illegal shift count"); 4222 if (imm8 == 1) { 4223 emit_int8((unsigned char)0xD1); 4224 emit_int8((unsigned char)(0xF8 | encode)); 4225 } else { 4226 emit_int8((unsigned char)0xC1); 4227 emit_int8((unsigned char)(0xF8 | encode)); 4228 emit_int8(imm8); 4229 } 4230 } 4231 4232 void Assembler::sarl(Register dst) { 4233 int encode = prefix_and_encode(dst->encoding()); 4234 emit_int8((unsigned char)0xD3); 4235 emit_int8((unsigned char)(0xF8 | encode)); 4236 } 4237 4238 void Assembler::sbbl(Address dst, int32_t imm32) { 4239 InstructionMark im(this); 4240 prefix(dst); 4241 emit_arith_operand(0x81, rbx, dst, imm32); 4242 } 4243 4244 void Assembler::sbbl(Register dst, int32_t imm32) { 4245 prefix(dst); 4246 emit_arith(0x81, 0xD8, dst, imm32); 4247 } 4248 4249 4250 void Assembler::sbbl(Register dst, Address src) { 4251 InstructionMark im(this); 4252 prefix(src, dst); 4253 emit_int8(0x1B); 4254 emit_operand(dst, src); 4255 } 4256 4257 void Assembler::sbbl(Register dst, Register src) { 4258 (void) prefix_and_encode(dst->encoding(), src->encoding()); 4259 emit_arith(0x1B, 0xC0, dst, src); 4260 } 4261 4262 void Assembler::setb(Condition cc, Register dst) { 4263 assert(0 <= cc && cc < 16, "illegal cc"); 4264 int encode = prefix_and_encode(dst->encoding(), true); 4265 emit_int8(0x0F); 4266 emit_int8((unsigned char)0x90 | cc); 4267 emit_int8((unsigned char)(0xC0 | encode)); 4268 } 4269 4270 void Assembler::palignr(XMMRegister dst, XMMRegister src, int imm8) { 4271 assert(VM_Version::supports_ssse3(), ""); 4272 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ false); 4273 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 4274 emit_int8((unsigned char)0x0F); 4275 emit_int8((unsigned char)(0xC0 | encode)); 4276 emit_int8(imm8); 4277 } 4278 4279 void Assembler::vpalignr(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) { 4280 assert(vector_len == AVX_128bit? VM_Version::supports_avx() : 4281 vector_len == AVX_256bit? VM_Version::supports_avx2() : 4282 0, ""); 4283 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true); 4284 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 4285 emit_int8((unsigned char)0x0F); 4286 emit_int8((unsigned char)(0xC0 | encode)); 4287 emit_int8(imm8); 4288 } 4289 4290 void Assembler::pblendw(XMMRegister dst, XMMRegister src, int imm8) { 4291 assert(VM_Version::supports_sse4_1(), ""); 4292 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 4293 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 4294 emit_int8((unsigned char)0x0E); 4295 emit_int8((unsigned char)(0xC0 | encode)); 4296 emit_int8(imm8); 4297 } 4298 4299 void Assembler::sha1rnds4(XMMRegister dst, XMMRegister src, int imm8) { 4300 assert(VM_Version::supports_sha(), ""); 4301 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3A, /* rex_w */ false); 4302 emit_int8((unsigned char)0xCC); 4303 emit_int8((unsigned char)(0xC0 | encode)); 4304 emit_int8((unsigned char)imm8); 4305 } 4306 4307 void Assembler::sha1nexte(XMMRegister dst, XMMRegister src) { 4308 assert(VM_Version::supports_sha(), ""); 4309 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false); 4310 emit_int8((unsigned char)0xC8); 4311 emit_int8((unsigned char)(0xC0 | encode)); 4312 } 4313 4314 void Assembler::sha1msg1(XMMRegister dst, XMMRegister src) { 4315 assert(VM_Version::supports_sha(), ""); 4316 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false); 4317 emit_int8((unsigned char)0xC9); 4318 emit_int8((unsigned char)(0xC0 | encode)); 4319 } 4320 4321 void Assembler::sha1msg2(XMMRegister dst, XMMRegister src) { 4322 assert(VM_Version::supports_sha(), ""); 4323 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false); 4324 emit_int8((unsigned char)0xCA); 4325 emit_int8((unsigned char)(0xC0 | encode)); 4326 } 4327 4328 // xmm0 is implicit additional source to this instruction. 4329 void Assembler::sha256rnds2(XMMRegister dst, XMMRegister src) { 4330 assert(VM_Version::supports_sha(), ""); 4331 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false); 4332 emit_int8((unsigned char)0xCB); 4333 emit_int8((unsigned char)(0xC0 | encode)); 4334 } 4335 4336 void Assembler::sha256msg1(XMMRegister dst, XMMRegister src) { 4337 assert(VM_Version::supports_sha(), ""); 4338 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false); 4339 emit_int8((unsigned char)0xCC); 4340 emit_int8((unsigned char)(0xC0 | encode)); 4341 } 4342 4343 void Assembler::sha256msg2(XMMRegister dst, XMMRegister src) { 4344 assert(VM_Version::supports_sha(), ""); 4345 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false); 4346 emit_int8((unsigned char)0xCD); 4347 emit_int8((unsigned char)(0xC0 | encode)); 4348 } 4349 4350 4351 void Assembler::shll(Register dst, int imm8) { 4352 assert(isShiftCount(imm8), "illegal shift count"); 4353 int encode = prefix_and_encode(dst->encoding()); 4354 if (imm8 == 1 ) { 4355 emit_int8((unsigned char)0xD1); 4356 emit_int8((unsigned char)(0xE0 | encode)); 4357 } else { 4358 emit_int8((unsigned char)0xC1); 4359 emit_int8((unsigned char)(0xE0 | encode)); 4360 emit_int8(imm8); 4361 } 4362 } 4363 4364 void Assembler::shll(Register dst) { 4365 int encode = prefix_and_encode(dst->encoding()); 4366 emit_int8((unsigned char)0xD3); 4367 emit_int8((unsigned char)(0xE0 | encode)); 4368 } 4369 4370 void Assembler::shrl(Register dst, int imm8) { 4371 assert(isShiftCount(imm8), "illegal shift count"); 4372 int encode = prefix_and_encode(dst->encoding()); 4373 emit_int8((unsigned char)0xC1); 4374 emit_int8((unsigned char)(0xE8 | encode)); 4375 emit_int8(imm8); 4376 } 4377 4378 void Assembler::shrl(Register dst) { 4379 int encode = prefix_and_encode(dst->encoding()); 4380 emit_int8((unsigned char)0xD3); 4381 emit_int8((unsigned char)(0xE8 | encode)); 4382 } 4383 4384 // copies a single word from [esi] to [edi] 4385 void Assembler::smovl() { 4386 emit_int8((unsigned char)0xA5); 4387 } 4388 4389 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) { 4390 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4391 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4392 attributes.set_rex_vex_w_reverted(); 4393 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 4394 emit_int8(0x51); 4395 emit_int8((unsigned char)(0xC0 | encode)); 4396 } 4397 4398 void Assembler::sqrtsd(XMMRegister dst, Address src) { 4399 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4400 InstructionMark im(this); 4401 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4402 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 4403 attributes.set_rex_vex_w_reverted(); 4404 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 4405 emit_int8(0x51); 4406 emit_operand(dst, src); 4407 } 4408 4409 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) { 4410 NOT_LP64(assert(VM_Version::supports_sse(), "")); 4411 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4412 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 4413 emit_int8(0x51); 4414 emit_int8((unsigned char)(0xC0 | encode)); 4415 } 4416 4417 void Assembler::std() { 4418 emit_int8((unsigned char)0xFD); 4419 } 4420 4421 void Assembler::sqrtss(XMMRegister dst, Address src) { 4422 NOT_LP64(assert(VM_Version::supports_sse(), "")); 4423 InstructionMark im(this); 4424 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4425 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 4426 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 4427 emit_int8(0x51); 4428 emit_operand(dst, src); 4429 } 4430 4431 void Assembler::stmxcsr( Address dst) { 4432 if (UseAVX > 0 ) { 4433 assert(VM_Version::supports_avx(), ""); 4434 InstructionMark im(this); 4435 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 4436 vex_prefix(dst, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 4437 emit_int8((unsigned char)0xAE); 4438 emit_operand(as_Register(3), dst); 4439 } else { 4440 NOT_LP64(assert(VM_Version::supports_sse(), "")); 4441 InstructionMark im(this); 4442 prefix(dst); 4443 emit_int8(0x0F); 4444 emit_int8((unsigned char)0xAE); 4445 emit_operand(as_Register(3), dst); 4446 } 4447 } 4448 4449 void Assembler::subl(Address dst, int32_t imm32) { 4450 InstructionMark im(this); 4451 prefix(dst); 4452 emit_arith_operand(0x81, rbp, dst, imm32); 4453 } 4454 4455 void Assembler::subl(Address dst, Register src) { 4456 InstructionMark im(this); 4457 prefix(dst, src); 4458 emit_int8(0x29); 4459 emit_operand(src, dst); 4460 } 4461 4462 void Assembler::subl(Register dst, int32_t imm32) { 4463 prefix(dst); 4464 emit_arith(0x81, 0xE8, dst, imm32); 4465 } 4466 4467 // Force generation of a 4 byte immediate value even if it fits into 8bit 4468 void Assembler::subl_imm32(Register dst, int32_t imm32) { 4469 prefix(dst); 4470 emit_arith_imm32(0x81, 0xE8, dst, imm32); 4471 } 4472 4473 void Assembler::subl(Register dst, Address src) { 4474 InstructionMark im(this); 4475 prefix(src, dst); 4476 emit_int8(0x2B); 4477 emit_operand(dst, src); 4478 } 4479 4480 void Assembler::subl(Register dst, Register src) { 4481 (void) prefix_and_encode(dst->encoding(), src->encoding()); 4482 emit_arith(0x2B, 0xC0, dst, src); 4483 } 4484 4485 void Assembler::subsd(XMMRegister dst, XMMRegister src) { 4486 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4487 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4488 attributes.set_rex_vex_w_reverted(); 4489 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 4490 emit_int8(0x5C); 4491 emit_int8((unsigned char)(0xC0 | encode)); 4492 } 4493 4494 void Assembler::subsd(XMMRegister dst, Address src) { 4495 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4496 InstructionMark im(this); 4497 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4498 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 4499 attributes.set_rex_vex_w_reverted(); 4500 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 4501 emit_int8(0x5C); 4502 emit_operand(dst, src); 4503 } 4504 4505 void Assembler::subss(XMMRegister dst, XMMRegister src) { 4506 NOT_LP64(assert(VM_Version::supports_sse(), "")); 4507 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true , /* uses_vl */ false); 4508 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 4509 emit_int8(0x5C); 4510 emit_int8((unsigned char)(0xC0 | encode)); 4511 } 4512 4513 void Assembler::subss(XMMRegister dst, Address src) { 4514 NOT_LP64(assert(VM_Version::supports_sse(), "")); 4515 InstructionMark im(this); 4516 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4517 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 4518 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 4519 emit_int8(0x5C); 4520 emit_operand(dst, src); 4521 } 4522 4523 void Assembler::testb(Register dst, int imm8) { 4524 NOT_LP64(assert(dst->has_byte_register(), "must have byte register")); 4525 (void) prefix_and_encode(dst->encoding(), true); 4526 emit_arith_b(0xF6, 0xC0, dst, imm8); 4527 } 4528 4529 void Assembler::testb(Address dst, int imm8) { 4530 InstructionMark im(this); 4531 prefix(dst); 4532 emit_int8((unsigned char)0xF6); 4533 emit_operand(rax, dst, 1); 4534 emit_int8(imm8); 4535 } 4536 4537 void Assembler::testl(Register dst, int32_t imm32) { 4538 // not using emit_arith because test 4539 // doesn't support sign-extension of 4540 // 8bit operands 4541 int encode = dst->encoding(); 4542 if (encode == 0) { 4543 emit_int8((unsigned char)0xA9); 4544 } else { 4545 encode = prefix_and_encode(encode); 4546 emit_int8((unsigned char)0xF7); 4547 emit_int8((unsigned char)(0xC0 | encode)); 4548 } 4549 emit_int32(imm32); 4550 } 4551 4552 void Assembler::testl(Register dst, Register src) { 4553 (void) prefix_and_encode(dst->encoding(), src->encoding()); 4554 emit_arith(0x85, 0xC0, dst, src); 4555 } 4556 4557 void Assembler::testl(Register dst, Address src) { 4558 InstructionMark im(this); 4559 prefix(src, dst); 4560 emit_int8((unsigned char)0x85); 4561 emit_operand(dst, src); 4562 } 4563 4564 void Assembler::tzcntl(Register dst, Register src) { 4565 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported"); 4566 emit_int8((unsigned char)0xF3); 4567 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 4568 emit_int8(0x0F); 4569 emit_int8((unsigned char)0xBC); 4570 emit_int8((unsigned char)0xC0 | encode); 4571 } 4572 4573 void Assembler::tzcntq(Register dst, Register src) { 4574 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported"); 4575 emit_int8((unsigned char)0xF3); 4576 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 4577 emit_int8(0x0F); 4578 emit_int8((unsigned char)0xBC); 4579 emit_int8((unsigned char)(0xC0 | encode)); 4580 } 4581 4582 void Assembler::ucomisd(XMMRegister dst, Address src) { 4583 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4584 InstructionMark im(this); 4585 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4586 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 4587 attributes.set_rex_vex_w_reverted(); 4588 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4589 emit_int8(0x2E); 4590 emit_operand(dst, src); 4591 } 4592 4593 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) { 4594 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4595 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4596 attributes.set_rex_vex_w_reverted(); 4597 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4598 emit_int8(0x2E); 4599 emit_int8((unsigned char)(0xC0 | encode)); 4600 } 4601 4602 void Assembler::ucomiss(XMMRegister dst, Address src) { 4603 NOT_LP64(assert(VM_Version::supports_sse(), "")); 4604 InstructionMark im(this); 4605 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4606 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 4607 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 4608 emit_int8(0x2E); 4609 emit_operand(dst, src); 4610 } 4611 4612 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) { 4613 NOT_LP64(assert(VM_Version::supports_sse(), "")); 4614 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4615 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 4616 emit_int8(0x2E); 4617 emit_int8((unsigned char)(0xC0 | encode)); 4618 } 4619 4620 void Assembler::xabort(int8_t imm8) { 4621 emit_int8((unsigned char)0xC6); 4622 emit_int8((unsigned char)0xF8); 4623 emit_int8((unsigned char)(imm8 & 0xFF)); 4624 } 4625 4626 void Assembler::xaddb(Address dst, Register src) { 4627 InstructionMark im(this); 4628 prefix(dst, src, true); 4629 emit_int8(0x0F); 4630 emit_int8((unsigned char)0xC0); 4631 emit_operand(src, dst); 4632 } 4633 4634 void Assembler::xaddw(Address dst, Register src) { 4635 InstructionMark im(this); 4636 emit_int8(0x66); 4637 prefix(dst, src); 4638 emit_int8(0x0F); 4639 emit_int8((unsigned char)0xC1); 4640 emit_operand(src, dst); 4641 } 4642 4643 void Assembler::xaddl(Address dst, Register src) { 4644 InstructionMark im(this); 4645 prefix(dst, src); 4646 emit_int8(0x0F); 4647 emit_int8((unsigned char)0xC1); 4648 emit_operand(src, dst); 4649 } 4650 4651 void Assembler::xbegin(Label& abort, relocInfo::relocType rtype) { 4652 InstructionMark im(this); 4653 relocate(rtype); 4654 if (abort.is_bound()) { 4655 address entry = target(abort); 4656 assert(entry != NULL, "abort entry NULL"); 4657 intptr_t offset = entry - pc(); 4658 emit_int8((unsigned char)0xC7); 4659 emit_int8((unsigned char)0xF8); 4660 emit_int32(offset - 6); // 2 opcode + 4 address 4661 } else { 4662 abort.add_patch_at(code(), locator()); 4663 emit_int8((unsigned char)0xC7); 4664 emit_int8((unsigned char)0xF8); 4665 emit_int32(0); 4666 } 4667 } 4668 4669 void Assembler::xchgb(Register dst, Address src) { // xchg 4670 InstructionMark im(this); 4671 prefix(src, dst, true); 4672 emit_int8((unsigned char)0x86); 4673 emit_operand(dst, src); 4674 } 4675 4676 void Assembler::xchgw(Register dst, Address src) { // xchg 4677 InstructionMark im(this); 4678 emit_int8(0x66); 4679 prefix(src, dst); 4680 emit_int8((unsigned char)0x87); 4681 emit_operand(dst, src); 4682 } 4683 4684 void Assembler::xchgl(Register dst, Address src) { // xchg 4685 InstructionMark im(this); 4686 prefix(src, dst); 4687 emit_int8((unsigned char)0x87); 4688 emit_operand(dst, src); 4689 } 4690 4691 void Assembler::xchgl(Register dst, Register src) { 4692 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 4693 emit_int8((unsigned char)0x87); 4694 emit_int8((unsigned char)(0xC0 | encode)); 4695 } 4696 4697 void Assembler::xend() { 4698 emit_int8((unsigned char)0x0F); 4699 emit_int8((unsigned char)0x01); 4700 emit_int8((unsigned char)0xD5); 4701 } 4702 4703 void Assembler::xgetbv() { 4704 emit_int8(0x0F); 4705 emit_int8(0x01); 4706 emit_int8((unsigned char)0xD0); 4707 } 4708 4709 void Assembler::xorl(Register dst, int32_t imm32) { 4710 prefix(dst); 4711 emit_arith(0x81, 0xF0, dst, imm32); 4712 } 4713 4714 void Assembler::xorl(Register dst, Address src) { 4715 InstructionMark im(this); 4716 prefix(src, dst); 4717 emit_int8(0x33); 4718 emit_operand(dst, src); 4719 } 4720 4721 void Assembler::xorl(Register dst, Register src) { 4722 (void) prefix_and_encode(dst->encoding(), src->encoding()); 4723 emit_arith(0x33, 0xC0, dst, src); 4724 } 4725 4726 void Assembler::xorb(Register dst, Address src) { 4727 InstructionMark im(this); 4728 prefix(src, dst); 4729 emit_int8(0x32); 4730 emit_operand(dst, src); 4731 } 4732 4733 // AVX 3-operands scalar float-point arithmetic instructions 4734 4735 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) { 4736 assert(VM_Version::supports_avx(), ""); 4737 InstructionMark im(this); 4738 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4739 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 4740 attributes.set_rex_vex_w_reverted(); 4741 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 4742 emit_int8(0x58); 4743 emit_operand(dst, src); 4744 } 4745 4746 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { 4747 assert(VM_Version::supports_avx(), ""); 4748 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4749 attributes.set_rex_vex_w_reverted(); 4750 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 4751 emit_int8(0x58); 4752 emit_int8((unsigned char)(0xC0 | encode)); 4753 } 4754 4755 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) { 4756 assert(VM_Version::supports_avx(), ""); 4757 InstructionMark im(this); 4758 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4759 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 4760 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 4761 emit_int8(0x58); 4762 emit_operand(dst, src); 4763 } 4764 4765 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { 4766 assert(VM_Version::supports_avx(), ""); 4767 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4768 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 4769 emit_int8(0x58); 4770 emit_int8((unsigned char)(0xC0 | encode)); 4771 } 4772 4773 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) { 4774 assert(VM_Version::supports_avx(), ""); 4775 InstructionMark im(this); 4776 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4777 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 4778 attributes.set_rex_vex_w_reverted(); 4779 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 4780 emit_int8(0x5E); 4781 emit_operand(dst, src); 4782 } 4783 4784 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { 4785 assert(VM_Version::supports_avx(), ""); 4786 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4787 attributes.set_rex_vex_w_reverted(); 4788 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 4789 emit_int8(0x5E); 4790 emit_int8((unsigned char)(0xC0 | encode)); 4791 } 4792 4793 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) { 4794 assert(VM_Version::supports_avx(), ""); 4795 InstructionMark im(this); 4796 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4797 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 4798 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 4799 emit_int8(0x5E); 4800 emit_operand(dst, src); 4801 } 4802 4803 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { 4804 assert(VM_Version::supports_avx(), ""); 4805 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4806 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 4807 emit_int8(0x5E); 4808 emit_int8((unsigned char)(0xC0 | encode)); 4809 } 4810 4811 void Assembler::vfmadd231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) { 4812 assert(VM_Version::supports_fma(), ""); 4813 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4814 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 4815 emit_int8((unsigned char)0xB9); 4816 emit_int8((unsigned char)(0xC0 | encode)); 4817 } 4818 4819 void Assembler::vfmadd231ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) { 4820 assert(VM_Version::supports_fma(), ""); 4821 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4822 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 4823 emit_int8((unsigned char)0xB9); 4824 emit_int8((unsigned char)(0xC0 | encode)); 4825 } 4826 4827 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) { 4828 assert(VM_Version::supports_avx(), ""); 4829 InstructionMark im(this); 4830 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4831 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 4832 attributes.set_rex_vex_w_reverted(); 4833 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 4834 emit_int8(0x59); 4835 emit_operand(dst, src); 4836 } 4837 4838 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { 4839 assert(VM_Version::supports_avx(), ""); 4840 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4841 attributes.set_rex_vex_w_reverted(); 4842 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 4843 emit_int8(0x59); 4844 emit_int8((unsigned char)(0xC0 | encode)); 4845 } 4846 4847 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) { 4848 assert(VM_Version::supports_avx(), ""); 4849 InstructionMark im(this); 4850 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4851 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 4852 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 4853 emit_int8(0x59); 4854 emit_operand(dst, src); 4855 } 4856 4857 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { 4858 assert(VM_Version::supports_avx(), ""); 4859 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4860 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 4861 emit_int8(0x59); 4862 emit_int8((unsigned char)(0xC0 | encode)); 4863 } 4864 4865 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) { 4866 assert(VM_Version::supports_avx(), ""); 4867 InstructionMark im(this); 4868 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4869 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 4870 attributes.set_rex_vex_w_reverted(); 4871 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 4872 emit_int8(0x5C); 4873 emit_operand(dst, src); 4874 } 4875 4876 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { 4877 assert(VM_Version::supports_avx(), ""); 4878 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4879 attributes.set_rex_vex_w_reverted(); 4880 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 4881 emit_int8(0x5C); 4882 emit_int8((unsigned char)(0xC0 | encode)); 4883 } 4884 4885 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) { 4886 assert(VM_Version::supports_avx(), ""); 4887 InstructionMark im(this); 4888 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4889 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 4890 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 4891 emit_int8(0x5C); 4892 emit_operand(dst, src); 4893 } 4894 4895 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { 4896 assert(VM_Version::supports_avx(), ""); 4897 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4898 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 4899 emit_int8(0x5C); 4900 emit_int8((unsigned char)(0xC0 | encode)); 4901 } 4902 4903 //====================VECTOR ARITHMETIC===================================== 4904 4905 // Float-point vector arithmetic 4906 4907 void Assembler::addpd(XMMRegister dst, XMMRegister src) { 4908 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4909 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 4910 attributes.set_rex_vex_w_reverted(); 4911 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4912 emit_int8(0x58); 4913 emit_int8((unsigned char)(0xC0 | encode)); 4914 } 4915 4916 void Assembler::addpd(XMMRegister dst, Address src) { 4917 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4918 InstructionMark im(this); 4919 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 4920 attributes.set_rex_vex_w_reverted(); 4921 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 4922 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4923 emit_int8(0x58); 4924 emit_operand(dst, src); 4925 } 4926 4927 4928 void Assembler::addps(XMMRegister dst, XMMRegister src) { 4929 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4930 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 4931 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 4932 emit_int8(0x58); 4933 emit_int8((unsigned char)(0xC0 | encode)); 4934 } 4935 4936 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4937 assert(VM_Version::supports_avx(), ""); 4938 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 4939 attributes.set_rex_vex_w_reverted(); 4940 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4941 emit_int8(0x58); 4942 emit_int8((unsigned char)(0xC0 | encode)); 4943 } 4944 4945 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4946 assert(VM_Version::supports_avx(), ""); 4947 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 4948 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 4949 emit_int8(0x58); 4950 emit_int8((unsigned char)(0xC0 | encode)); 4951 } 4952 4953 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4954 assert(VM_Version::supports_avx(), ""); 4955 InstructionMark im(this); 4956 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 4957 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 4958 attributes.set_rex_vex_w_reverted(); 4959 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4960 emit_int8(0x58); 4961 emit_operand(dst, src); 4962 } 4963 4964 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4965 assert(VM_Version::supports_avx(), ""); 4966 InstructionMark im(this); 4967 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 4968 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 4969 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 4970 emit_int8(0x58); 4971 emit_operand(dst, src); 4972 } 4973 4974 void Assembler::subpd(XMMRegister dst, XMMRegister src) { 4975 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4976 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 4977 attributes.set_rex_vex_w_reverted(); 4978 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4979 emit_int8(0x5C); 4980 emit_int8((unsigned char)(0xC0 | encode)); 4981 } 4982 4983 void Assembler::subps(XMMRegister dst, XMMRegister src) { 4984 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4985 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 4986 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 4987 emit_int8(0x5C); 4988 emit_int8((unsigned char)(0xC0 | encode)); 4989 } 4990 4991 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4992 assert(VM_Version::supports_avx(), ""); 4993 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 4994 attributes.set_rex_vex_w_reverted(); 4995 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4996 emit_int8(0x5C); 4997 emit_int8((unsigned char)(0xC0 | encode)); 4998 } 4999 5000 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5001 assert(VM_Version::supports_avx(), ""); 5002 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5003 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5004 emit_int8(0x5C); 5005 emit_int8((unsigned char)(0xC0 | encode)); 5006 } 5007 5008 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5009 assert(VM_Version::supports_avx(), ""); 5010 InstructionMark im(this); 5011 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5012 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5013 attributes.set_rex_vex_w_reverted(); 5014 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5015 emit_int8(0x5C); 5016 emit_operand(dst, src); 5017 } 5018 5019 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5020 assert(VM_Version::supports_avx(), ""); 5021 InstructionMark im(this); 5022 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5023 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 5024 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5025 emit_int8(0x5C); 5026 emit_operand(dst, src); 5027 } 5028 5029 void Assembler::mulpd(XMMRegister dst, XMMRegister src) { 5030 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5031 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5032 attributes.set_rex_vex_w_reverted(); 5033 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5034 emit_int8(0x59); 5035 emit_int8((unsigned char)(0xC0 | encode)); 5036 } 5037 5038 void Assembler::mulpd(XMMRegister dst, Address src) { 5039 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5040 InstructionMark im(this); 5041 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5042 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5043 attributes.set_rex_vex_w_reverted(); 5044 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5045 emit_int8(0x59); 5046 emit_operand(dst, src); 5047 } 5048 5049 void Assembler::mulps(XMMRegister dst, XMMRegister src) { 5050 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5051 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5052 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5053 emit_int8(0x59); 5054 emit_int8((unsigned char)(0xC0 | encode)); 5055 } 5056 5057 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5058 assert(VM_Version::supports_avx(), ""); 5059 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5060 attributes.set_rex_vex_w_reverted(); 5061 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5062 emit_int8(0x59); 5063 emit_int8((unsigned char)(0xC0 | encode)); 5064 } 5065 5066 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5067 assert(VM_Version::supports_avx(), ""); 5068 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5069 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5070 emit_int8(0x59); 5071 emit_int8((unsigned char)(0xC0 | encode)); 5072 } 5073 5074 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5075 assert(VM_Version::supports_avx(), ""); 5076 InstructionMark im(this); 5077 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5078 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5079 attributes.set_rex_vex_w_reverted(); 5080 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5081 emit_int8(0x59); 5082 emit_operand(dst, src); 5083 } 5084 5085 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5086 assert(VM_Version::supports_avx(), ""); 5087 InstructionMark im(this); 5088 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5089 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 5090 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5091 emit_int8(0x59); 5092 emit_operand(dst, src); 5093 } 5094 5095 void Assembler::vfmadd231pd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len) { 5096 assert(VM_Version::supports_fma(), ""); 5097 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5098 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 5099 emit_int8((unsigned char)0xB8); 5100 emit_int8((unsigned char)(0xC0 | encode)); 5101 } 5102 5103 void Assembler::vfmadd231ps(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len) { 5104 assert(VM_Version::supports_fma(), ""); 5105 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5106 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 5107 emit_int8((unsigned char)0xB8); 5108 emit_int8((unsigned char)(0xC0 | encode)); 5109 } 5110 5111 void Assembler::vfmadd231pd(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) { 5112 assert(VM_Version::supports_fma(), ""); 5113 InstructionMark im(this); 5114 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5115 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5116 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 5117 emit_int8((unsigned char)0xB8); 5118 emit_operand(dst, src2); 5119 } 5120 5121 void Assembler::vfmadd231ps(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) { 5122 assert(VM_Version::supports_fma(), ""); 5123 InstructionMark im(this); 5124 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5125 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 5126 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 5127 emit_int8((unsigned char)0xB8); 5128 emit_operand(dst, src2); 5129 } 5130 5131 void Assembler::divpd(XMMRegister dst, XMMRegister src) { 5132 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5133 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5134 attributes.set_rex_vex_w_reverted(); 5135 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5136 emit_int8(0x5E); 5137 emit_int8((unsigned char)(0xC0 | encode)); 5138 } 5139 5140 void Assembler::divps(XMMRegister dst, XMMRegister src) { 5141 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5142 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5143 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5144 emit_int8(0x5E); 5145 emit_int8((unsigned char)(0xC0 | encode)); 5146 } 5147 5148 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5149 assert(VM_Version::supports_avx(), ""); 5150 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5151 attributes.set_rex_vex_w_reverted(); 5152 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5153 emit_int8(0x5E); 5154 emit_int8((unsigned char)(0xC0 | encode)); 5155 } 5156 5157 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5158 assert(VM_Version::supports_avx(), ""); 5159 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5160 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5161 emit_int8(0x5E); 5162 emit_int8((unsigned char)(0xC0 | encode)); 5163 } 5164 5165 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5166 assert(VM_Version::supports_avx(), ""); 5167 InstructionMark im(this); 5168 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5169 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5170 attributes.set_rex_vex_w_reverted(); 5171 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5172 emit_int8(0x5E); 5173 emit_operand(dst, src); 5174 } 5175 5176 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5177 assert(VM_Version::supports_avx(), ""); 5178 InstructionMark im(this); 5179 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5180 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 5181 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5182 emit_int8(0x5E); 5183 emit_operand(dst, src); 5184 } 5185 5186 void Assembler::vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len) { 5187 assert(VM_Version::supports_avx(), ""); 5188 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5189 attributes.set_rex_vex_w_reverted(); 5190 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5191 emit_int8(0x51); 5192 emit_int8((unsigned char)(0xC0 | encode)); 5193 } 5194 5195 void Assembler::vsqrtpd(XMMRegister dst, Address src, int vector_len) { 5196 assert(VM_Version::supports_avx(), ""); 5197 InstructionMark im(this); 5198 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5199 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5200 attributes.set_rex_vex_w_reverted(); 5201 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5202 emit_int8(0x51); 5203 emit_operand(dst, src); 5204 } 5205 5206 void Assembler::andpd(XMMRegister dst, XMMRegister src) { 5207 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5208 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5209 attributes.set_rex_vex_w_reverted(); 5210 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5211 emit_int8(0x54); 5212 emit_int8((unsigned char)(0xC0 | encode)); 5213 } 5214 5215 void Assembler::andps(XMMRegister dst, XMMRegister src) { 5216 NOT_LP64(assert(VM_Version::supports_sse(), "")); 5217 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5218 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5219 emit_int8(0x54); 5220 emit_int8((unsigned char)(0xC0 | encode)); 5221 } 5222 5223 void Assembler::andps(XMMRegister dst, Address src) { 5224 NOT_LP64(assert(VM_Version::supports_sse(), "")); 5225 InstructionMark im(this); 5226 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5227 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 5228 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5229 emit_int8(0x54); 5230 emit_operand(dst, src); 5231 } 5232 5233 void Assembler::andpd(XMMRegister dst, Address src) { 5234 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5235 InstructionMark im(this); 5236 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5237 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5238 attributes.set_rex_vex_w_reverted(); 5239 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5240 emit_int8(0x54); 5241 emit_operand(dst, src); 5242 } 5243 5244 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5245 assert(VM_Version::supports_avx(), ""); 5246 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5247 attributes.set_rex_vex_w_reverted(); 5248 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5249 emit_int8(0x54); 5250 emit_int8((unsigned char)(0xC0 | encode)); 5251 } 5252 5253 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5254 assert(VM_Version::supports_avx(), ""); 5255 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5256 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5257 emit_int8(0x54); 5258 emit_int8((unsigned char)(0xC0 | encode)); 5259 } 5260 5261 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5262 assert(VM_Version::supports_avx(), ""); 5263 InstructionMark im(this); 5264 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5265 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5266 attributes.set_rex_vex_w_reverted(); 5267 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5268 emit_int8(0x54); 5269 emit_operand(dst, src); 5270 } 5271 5272 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5273 assert(VM_Version::supports_avx(), ""); 5274 InstructionMark im(this); 5275 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5276 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 5277 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5278 emit_int8(0x54); 5279 emit_operand(dst, src); 5280 } 5281 5282 void Assembler::unpckhpd(XMMRegister dst, XMMRegister src) { 5283 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5284 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5285 attributes.set_rex_vex_w_reverted(); 5286 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5287 emit_int8(0x15); 5288 emit_int8((unsigned char)(0xC0 | encode)); 5289 } 5290 5291 void Assembler::unpcklpd(XMMRegister dst, XMMRegister src) { 5292 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5293 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5294 attributes.set_rex_vex_w_reverted(); 5295 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5296 emit_int8(0x14); 5297 emit_int8((unsigned char)(0xC0 | encode)); 5298 } 5299 5300 void Assembler::xorpd(XMMRegister dst, XMMRegister src) { 5301 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5302 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5303 attributes.set_rex_vex_w_reverted(); 5304 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5305 emit_int8(0x57); 5306 emit_int8((unsigned char)(0xC0 | encode)); 5307 } 5308 5309 void Assembler::xorps(XMMRegister dst, XMMRegister src) { 5310 NOT_LP64(assert(VM_Version::supports_sse(), "")); 5311 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5312 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5313 emit_int8(0x57); 5314 emit_int8((unsigned char)(0xC0 | encode)); 5315 } 5316 5317 void Assembler::xorpd(XMMRegister dst, Address src) { 5318 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5319 InstructionMark im(this); 5320 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5321 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5322 attributes.set_rex_vex_w_reverted(); 5323 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5324 emit_int8(0x57); 5325 emit_operand(dst, src); 5326 } 5327 5328 void Assembler::xorps(XMMRegister dst, Address src) { 5329 NOT_LP64(assert(VM_Version::supports_sse(), "")); 5330 InstructionMark im(this); 5331 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5332 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 5333 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5334 emit_int8(0x57); 5335 emit_operand(dst, src); 5336 } 5337 5338 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5339 assert(VM_Version::supports_avx(), ""); 5340 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5341 attributes.set_rex_vex_w_reverted(); 5342 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5343 emit_int8(0x57); 5344 emit_int8((unsigned char)(0xC0 | encode)); 5345 } 5346 5347 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5348 assert(VM_Version::supports_avx(), ""); 5349 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5350 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5351 emit_int8(0x57); 5352 emit_int8((unsigned char)(0xC0 | encode)); 5353 } 5354 5355 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5356 assert(VM_Version::supports_avx(), ""); 5357 InstructionMark im(this); 5358 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5359 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5360 attributes.set_rex_vex_w_reverted(); 5361 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5362 emit_int8(0x57); 5363 emit_operand(dst, src); 5364 } 5365 5366 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5367 assert(VM_Version::supports_avx(), ""); 5368 InstructionMark im(this); 5369 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5370 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 5371 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5372 emit_int8(0x57); 5373 emit_operand(dst, src); 5374 } 5375 5376 // Integer vector arithmetic 5377 void Assembler::vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5378 assert(VM_Version::supports_avx() && (vector_len == 0) || 5379 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); 5380 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 5381 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 5382 emit_int8(0x01); 5383 emit_int8((unsigned char)(0xC0 | encode)); 5384 } 5385 5386 void Assembler::vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5387 assert(VM_Version::supports_avx() && (vector_len == 0) || 5388 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); 5389 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 5390 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 5391 emit_int8(0x02); 5392 emit_int8((unsigned char)(0xC0 | encode)); 5393 } 5394 5395 void Assembler::paddb(XMMRegister dst, XMMRegister src) { 5396 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5397 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5398 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5399 emit_int8((unsigned char)0xFC); 5400 emit_int8((unsigned char)(0xC0 | encode)); 5401 } 5402 5403 void Assembler::paddw(XMMRegister dst, XMMRegister src) { 5404 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5405 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5406 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5407 emit_int8((unsigned char)0xFD); 5408 emit_int8((unsigned char)(0xC0 | encode)); 5409 } 5410 5411 void Assembler::paddd(XMMRegister dst, XMMRegister src) { 5412 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5413 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5414 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5415 emit_int8((unsigned char)0xFE); 5416 emit_int8((unsigned char)(0xC0 | encode)); 5417 } 5418 5419 void Assembler::paddd(XMMRegister dst, Address src) { 5420 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5421 InstructionMark im(this); 5422 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5423 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5424 emit_int8((unsigned char)0xFE); 5425 emit_operand(dst, src); 5426 } 5427 5428 void Assembler::paddq(XMMRegister dst, XMMRegister src) { 5429 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5430 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5431 attributes.set_rex_vex_w_reverted(); 5432 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5433 emit_int8((unsigned char)0xD4); 5434 emit_int8((unsigned char)(0xC0 | encode)); 5435 } 5436 5437 void Assembler::phaddw(XMMRegister dst, XMMRegister src) { 5438 assert(VM_Version::supports_sse3(), ""); 5439 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 5440 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 5441 emit_int8(0x01); 5442 emit_int8((unsigned char)(0xC0 | encode)); 5443 } 5444 5445 void Assembler::phaddd(XMMRegister dst, XMMRegister src) { 5446 assert(VM_Version::supports_sse3(), ""); 5447 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 5448 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 5449 emit_int8(0x02); 5450 emit_int8((unsigned char)(0xC0 | encode)); 5451 } 5452 5453 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5454 assert(UseAVX > 0, "requires some form of AVX"); 5455 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5456 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5457 emit_int8((unsigned char)0xFC); 5458 emit_int8((unsigned char)(0xC0 | encode)); 5459 } 5460 5461 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5462 assert(UseAVX > 0, "requires some form of AVX"); 5463 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5464 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5465 emit_int8((unsigned char)0xFD); 5466 emit_int8((unsigned char)(0xC0 | encode)); 5467 } 5468 5469 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5470 assert(UseAVX > 0, "requires some form of AVX"); 5471 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5472 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5473 emit_int8((unsigned char)0xFE); 5474 emit_int8((unsigned char)(0xC0 | encode)); 5475 } 5476 5477 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5478 assert(UseAVX > 0, "requires some form of AVX"); 5479 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5480 attributes.set_rex_vex_w_reverted(); 5481 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5482 emit_int8((unsigned char)0xD4); 5483 emit_int8((unsigned char)(0xC0 | encode)); 5484 } 5485 5486 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5487 assert(UseAVX > 0, "requires some form of AVX"); 5488 InstructionMark im(this); 5489 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5490 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 5491 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5492 emit_int8((unsigned char)0xFC); 5493 emit_operand(dst, src); 5494 } 5495 5496 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5497 assert(UseAVX > 0, "requires some form of AVX"); 5498 InstructionMark im(this); 5499 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5500 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 5501 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5502 emit_int8((unsigned char)0xFD); 5503 emit_operand(dst, src); 5504 } 5505 5506 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5507 assert(UseAVX > 0, "requires some form of AVX"); 5508 InstructionMark im(this); 5509 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5510 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 5511 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5512 emit_int8((unsigned char)0xFE); 5513 emit_operand(dst, src); 5514 } 5515 5516 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5517 assert(UseAVX > 0, "requires some form of AVX"); 5518 InstructionMark im(this); 5519 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5520 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5521 attributes.set_rex_vex_w_reverted(); 5522 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5523 emit_int8((unsigned char)0xD4); 5524 emit_operand(dst, src); 5525 } 5526 5527 void Assembler::psubb(XMMRegister dst, XMMRegister src) { 5528 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5529 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5530 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5531 emit_int8((unsigned char)0xF8); 5532 emit_int8((unsigned char)(0xC0 | encode)); 5533 } 5534 5535 void Assembler::psubw(XMMRegister dst, XMMRegister src) { 5536 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5537 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5538 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5539 emit_int8((unsigned char)0xF9); 5540 emit_int8((unsigned char)(0xC0 | encode)); 5541 } 5542 5543 void Assembler::psubd(XMMRegister dst, XMMRegister src) { 5544 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5545 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5546 emit_int8((unsigned char)0xFA); 5547 emit_int8((unsigned char)(0xC0 | encode)); 5548 } 5549 5550 void Assembler::psubq(XMMRegister dst, XMMRegister src) { 5551 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5552 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5553 attributes.set_rex_vex_w_reverted(); 5554 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5555 emit_int8((unsigned char)0xFB); 5556 emit_int8((unsigned char)(0xC0 | encode)); 5557 } 5558 5559 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5560 assert(UseAVX > 0, "requires some form of AVX"); 5561 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5562 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5563 emit_int8((unsigned char)0xF8); 5564 emit_int8((unsigned char)(0xC0 | encode)); 5565 } 5566 5567 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5568 assert(UseAVX > 0, "requires some form of AVX"); 5569 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5570 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5571 emit_int8((unsigned char)0xF9); 5572 emit_int8((unsigned char)(0xC0 | encode)); 5573 } 5574 5575 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5576 assert(UseAVX > 0, "requires some form of AVX"); 5577 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5578 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5579 emit_int8((unsigned char)0xFA); 5580 emit_int8((unsigned char)(0xC0 | encode)); 5581 } 5582 5583 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5584 assert(UseAVX > 0, "requires some form of AVX"); 5585 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5586 attributes.set_rex_vex_w_reverted(); 5587 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5588 emit_int8((unsigned char)0xFB); 5589 emit_int8((unsigned char)(0xC0 | encode)); 5590 } 5591 5592 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5593 assert(UseAVX > 0, "requires some form of AVX"); 5594 InstructionMark im(this); 5595 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5596 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 5597 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5598 emit_int8((unsigned char)0xF8); 5599 emit_operand(dst, src); 5600 } 5601 5602 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5603 assert(UseAVX > 0, "requires some form of AVX"); 5604 InstructionMark im(this); 5605 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5606 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 5607 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5608 emit_int8((unsigned char)0xF9); 5609 emit_operand(dst, src); 5610 } 5611 5612 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5613 assert(UseAVX > 0, "requires some form of AVX"); 5614 InstructionMark im(this); 5615 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5616 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 5617 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5618 emit_int8((unsigned char)0xFA); 5619 emit_operand(dst, src); 5620 } 5621 5622 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5623 assert(UseAVX > 0, "requires some form of AVX"); 5624 InstructionMark im(this); 5625 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5626 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5627 attributes.set_rex_vex_w_reverted(); 5628 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5629 emit_int8((unsigned char)0xFB); 5630 emit_operand(dst, src); 5631 } 5632 5633 void Assembler::pmullw(XMMRegister dst, XMMRegister src) { 5634 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5635 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5636 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5637 emit_int8((unsigned char)0xD5); 5638 emit_int8((unsigned char)(0xC0 | encode)); 5639 } 5640 5641 void Assembler::pmulld(XMMRegister dst, XMMRegister src) { 5642 assert(VM_Version::supports_sse4_1(), ""); 5643 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5644 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 5645 emit_int8(0x40); 5646 emit_int8((unsigned char)(0xC0 | encode)); 5647 } 5648 5649 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5650 assert(UseAVX > 0, "requires some form of AVX"); 5651 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5652 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5653 emit_int8((unsigned char)0xD5); 5654 emit_int8((unsigned char)(0xC0 | encode)); 5655 } 5656 5657 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5658 assert(UseAVX > 0, "requires some form of AVX"); 5659 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5660 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 5661 emit_int8(0x40); 5662 emit_int8((unsigned char)(0xC0 | encode)); 5663 } 5664 5665 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5666 assert(UseAVX > 2, "requires some form of EVEX"); 5667 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5668 attributes.set_is_evex_instruction(); 5669 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 5670 emit_int8(0x40); 5671 emit_int8((unsigned char)(0xC0 | encode)); 5672 } 5673 5674 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5675 assert(UseAVX > 0, "requires some form of AVX"); 5676 InstructionMark im(this); 5677 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5678 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 5679 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5680 emit_int8((unsigned char)0xD5); 5681 emit_operand(dst, src); 5682 } 5683 5684 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5685 assert(UseAVX > 0, "requires some form of AVX"); 5686 InstructionMark im(this); 5687 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5688 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 5689 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 5690 emit_int8(0x40); 5691 emit_operand(dst, src); 5692 } 5693 5694 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5695 assert(UseAVX > 2, "requires some form of EVEX"); 5696 InstructionMark im(this); 5697 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5698 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5699 attributes.set_is_evex_instruction(); 5700 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 5701 emit_int8(0x40); 5702 emit_operand(dst, src); 5703 } 5704 5705 // Shift packed integers left by specified number of bits. 5706 void Assembler::psllw(XMMRegister dst, int shift) { 5707 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5708 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5709 // XMM6 is for /6 encoding: 66 0F 71 /6 ib 5710 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5711 emit_int8(0x71); 5712 emit_int8((unsigned char)(0xC0 | encode)); 5713 emit_int8(shift & 0xFF); 5714 } 5715 5716 void Assembler::pslld(XMMRegister dst, int shift) { 5717 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5718 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5719 // XMM6 is for /6 encoding: 66 0F 72 /6 ib 5720 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5721 emit_int8(0x72); 5722 emit_int8((unsigned char)(0xC0 | encode)); 5723 emit_int8(shift & 0xFF); 5724 } 5725 5726 void Assembler::psllq(XMMRegister dst, int shift) { 5727 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5728 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5729 // XMM6 is for /6 encoding: 66 0F 73 /6 ib 5730 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5731 emit_int8(0x73); 5732 emit_int8((unsigned char)(0xC0 | encode)); 5733 emit_int8(shift & 0xFF); 5734 } 5735 5736 void Assembler::psllw(XMMRegister dst, XMMRegister shift) { 5737 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5738 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5739 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5740 emit_int8((unsigned char)0xF1); 5741 emit_int8((unsigned char)(0xC0 | encode)); 5742 } 5743 5744 void Assembler::pslld(XMMRegister dst, XMMRegister shift) { 5745 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5746 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5747 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5748 emit_int8((unsigned char)0xF2); 5749 emit_int8((unsigned char)(0xC0 | encode)); 5750 } 5751 5752 void Assembler::psllq(XMMRegister dst, XMMRegister shift) { 5753 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5754 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5755 attributes.set_rex_vex_w_reverted(); 5756 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5757 emit_int8((unsigned char)0xF3); 5758 emit_int8((unsigned char)(0xC0 | encode)); 5759 } 5760 5761 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len) { 5762 assert(UseAVX > 0, "requires some form of AVX"); 5763 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5764 // XMM6 is for /6 encoding: 66 0F 71 /6 ib 5765 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5766 emit_int8(0x71); 5767 emit_int8((unsigned char)(0xC0 | encode)); 5768 emit_int8(shift & 0xFF); 5769 } 5770 5771 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len) { 5772 assert(UseAVX > 0, "requires some form of AVX"); 5773 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5774 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5775 // XMM6 is for /6 encoding: 66 0F 72 /6 ib 5776 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5777 emit_int8(0x72); 5778 emit_int8((unsigned char)(0xC0 | encode)); 5779 emit_int8(shift & 0xFF); 5780 } 5781 5782 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len) { 5783 assert(UseAVX > 0, "requires some form of AVX"); 5784 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5785 attributes.set_rex_vex_w_reverted(); 5786 // XMM6 is for /6 encoding: 66 0F 73 /6 ib 5787 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5788 emit_int8(0x73); 5789 emit_int8((unsigned char)(0xC0 | encode)); 5790 emit_int8(shift & 0xFF); 5791 } 5792 5793 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { 5794 assert(UseAVX > 0, "requires some form of AVX"); 5795 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5796 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5797 emit_int8((unsigned char)0xF1); 5798 emit_int8((unsigned char)(0xC0 | encode)); 5799 } 5800 5801 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { 5802 assert(UseAVX > 0, "requires some form of AVX"); 5803 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5804 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5805 emit_int8((unsigned char)0xF2); 5806 emit_int8((unsigned char)(0xC0 | encode)); 5807 } 5808 5809 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { 5810 assert(UseAVX > 0, "requires some form of AVX"); 5811 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5812 attributes.set_rex_vex_w_reverted(); 5813 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5814 emit_int8((unsigned char)0xF3); 5815 emit_int8((unsigned char)(0xC0 | encode)); 5816 } 5817 5818 // Shift packed integers logically right by specified number of bits. 5819 void Assembler::psrlw(XMMRegister dst, int shift) { 5820 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5821 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5822 // XMM2 is for /2 encoding: 66 0F 71 /2 ib 5823 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5824 emit_int8(0x71); 5825 emit_int8((unsigned char)(0xC0 | encode)); 5826 emit_int8(shift & 0xFF); 5827 } 5828 5829 void Assembler::psrld(XMMRegister dst, int shift) { 5830 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5831 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5832 // XMM2 is for /2 encoding: 66 0F 72 /2 ib 5833 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5834 emit_int8(0x72); 5835 emit_int8((unsigned char)(0xC0 | encode)); 5836 emit_int8(shift & 0xFF); 5837 } 5838 5839 void Assembler::psrlq(XMMRegister dst, int shift) { 5840 // Do not confuse it with psrldq SSE2 instruction which 5841 // shifts 128 bit value in xmm register by number of bytes. 5842 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5843 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5844 attributes.set_rex_vex_w_reverted(); 5845 // XMM2 is for /2 encoding: 66 0F 73 /2 ib 5846 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5847 emit_int8(0x73); 5848 emit_int8((unsigned char)(0xC0 | encode)); 5849 emit_int8(shift & 0xFF); 5850 } 5851 5852 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) { 5853 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5854 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5855 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5856 emit_int8((unsigned char)0xD1); 5857 emit_int8((unsigned char)(0xC0 | encode)); 5858 } 5859 5860 void Assembler::psrld(XMMRegister dst, XMMRegister shift) { 5861 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5862 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5863 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5864 emit_int8((unsigned char)0xD2); 5865 emit_int8((unsigned char)(0xC0 | encode)); 5866 } 5867 5868 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) { 5869 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5870 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5871 attributes.set_rex_vex_w_reverted(); 5872 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5873 emit_int8((unsigned char)0xD3); 5874 emit_int8((unsigned char)(0xC0 | encode)); 5875 } 5876 5877 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len) { 5878 assert(UseAVX > 0, "requires some form of AVX"); 5879 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5880 // XMM2 is for /2 encoding: 66 0F 71 /2 ib 5881 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5882 emit_int8(0x71); 5883 emit_int8((unsigned char)(0xC0 | encode)); 5884 emit_int8(shift & 0xFF); 5885 } 5886 5887 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len) { 5888 assert(UseAVX > 0, "requires some form of AVX"); 5889 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5890 // XMM2 is for /2 encoding: 66 0F 72 /2 ib 5891 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5892 emit_int8(0x72); 5893 emit_int8((unsigned char)(0xC0 | encode)); 5894 emit_int8(shift & 0xFF); 5895 } 5896 5897 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len) { 5898 assert(UseAVX > 0, "requires some form of AVX"); 5899 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5900 attributes.set_rex_vex_w_reverted(); 5901 // XMM2 is for /2 encoding: 66 0F 73 /2 ib 5902 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5903 emit_int8(0x73); 5904 emit_int8((unsigned char)(0xC0 | encode)); 5905 emit_int8(shift & 0xFF); 5906 } 5907 5908 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { 5909 assert(UseAVX > 0, "requires some form of AVX"); 5910 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5911 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5912 emit_int8((unsigned char)0xD1); 5913 emit_int8((unsigned char)(0xC0 | encode)); 5914 } 5915 5916 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { 5917 assert(UseAVX > 0, "requires some form of AVX"); 5918 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5919 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5920 emit_int8((unsigned char)0xD2); 5921 emit_int8((unsigned char)(0xC0 | encode)); 5922 } 5923 5924 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { 5925 assert(UseAVX > 0, "requires some form of AVX"); 5926 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5927 attributes.set_rex_vex_w_reverted(); 5928 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5929 emit_int8((unsigned char)0xD3); 5930 emit_int8((unsigned char)(0xC0 | encode)); 5931 } 5932 5933 // Shift packed integers arithmetically right by specified number of bits. 5934 void Assembler::psraw(XMMRegister dst, int shift) { 5935 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5936 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5937 // XMM4 is for /4 encoding: 66 0F 71 /4 ib 5938 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5939 emit_int8(0x71); 5940 emit_int8((unsigned char)(0xC0 | encode)); 5941 emit_int8(shift & 0xFF); 5942 } 5943 5944 void Assembler::psrad(XMMRegister dst, int shift) { 5945 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5946 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5947 // XMM4 is for /4 encoding: 66 0F 72 /4 ib 5948 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5949 emit_int8(0x72); 5950 emit_int8((unsigned char)(0xC0 | encode)); 5951 emit_int8(shift & 0xFF); 5952 } 5953 5954 void Assembler::psraw(XMMRegister dst, XMMRegister shift) { 5955 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5956 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5957 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5958 emit_int8((unsigned char)0xE1); 5959 emit_int8((unsigned char)(0xC0 | encode)); 5960 } 5961 5962 void Assembler::psrad(XMMRegister dst, XMMRegister shift) { 5963 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5964 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5965 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5966 emit_int8((unsigned char)0xE2); 5967 emit_int8((unsigned char)(0xC0 | encode)); 5968 } 5969 5970 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len) { 5971 assert(UseAVX > 0, "requires some form of AVX"); 5972 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5973 // XMM4 is for /4 encoding: 66 0F 71 /4 ib 5974 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5975 emit_int8(0x71); 5976 emit_int8((unsigned char)(0xC0 | encode)); 5977 emit_int8(shift & 0xFF); 5978 } 5979 5980 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len) { 5981 assert(UseAVX > 0, "requires some form of AVX"); 5982 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5983 // XMM4 is for /4 encoding: 66 0F 71 /4 ib 5984 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5985 emit_int8(0x72); 5986 emit_int8((unsigned char)(0xC0 | encode)); 5987 emit_int8(shift & 0xFF); 5988 } 5989 5990 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { 5991 assert(UseAVX > 0, "requires some form of AVX"); 5992 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5993 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5994 emit_int8((unsigned char)0xE1); 5995 emit_int8((unsigned char)(0xC0 | encode)); 5996 } 5997 5998 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { 5999 assert(UseAVX > 0, "requires some form of AVX"); 6000 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6001 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6002 emit_int8((unsigned char)0xE2); 6003 emit_int8((unsigned char)(0xC0 | encode)); 6004 } 6005 6006 6007 // logical operations packed integers 6008 void Assembler::pand(XMMRegister dst, XMMRegister src) { 6009 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 6010 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6011 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6012 emit_int8((unsigned char)0xDB); 6013 emit_int8((unsigned char)(0xC0 | encode)); 6014 } 6015 6016 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 6017 assert(UseAVX > 0, "requires some form of AVX"); 6018 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6019 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6020 emit_int8((unsigned char)0xDB); 6021 emit_int8((unsigned char)(0xC0 | encode)); 6022 } 6023 6024 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 6025 assert(UseAVX > 0, "requires some form of AVX"); 6026 InstructionMark im(this); 6027 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6028 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 6029 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6030 emit_int8((unsigned char)0xDB); 6031 emit_operand(dst, src); 6032 } 6033 6034 void Assembler::pandn(XMMRegister dst, XMMRegister src) { 6035 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 6036 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6037 attributes.set_rex_vex_w_reverted(); 6038 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6039 emit_int8((unsigned char)0xDF); 6040 emit_int8((unsigned char)(0xC0 | encode)); 6041 } 6042 6043 void Assembler::por(XMMRegister dst, XMMRegister src) { 6044 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 6045 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6046 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6047 emit_int8((unsigned char)0xEB); 6048 emit_int8((unsigned char)(0xC0 | encode)); 6049 } 6050 6051 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 6052 assert(UseAVX > 0, "requires some form of AVX"); 6053 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6054 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6055 emit_int8((unsigned char)0xEB); 6056 emit_int8((unsigned char)(0xC0 | encode)); 6057 } 6058 6059 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 6060 assert(UseAVX > 0, "requires some form of AVX"); 6061 InstructionMark im(this); 6062 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6063 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 6064 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6065 emit_int8((unsigned char)0xEB); 6066 emit_operand(dst, src); 6067 } 6068 6069 void Assembler::pxor(XMMRegister dst, XMMRegister src) { 6070 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 6071 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6072 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6073 emit_int8((unsigned char)0xEF); 6074 emit_int8((unsigned char)(0xC0 | encode)); 6075 } 6076 6077 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 6078 assert(UseAVX > 0, "requires some form of AVX"); 6079 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6080 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6081 emit_int8((unsigned char)0xEF); 6082 emit_int8((unsigned char)(0xC0 | encode)); 6083 } 6084 6085 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 6086 assert(UseAVX > 0, "requires some form of AVX"); 6087 InstructionMark im(this); 6088 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6089 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 6090 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6091 emit_int8((unsigned char)0xEF); 6092 emit_operand(dst, src); 6093 } 6094 6095 6096 // vinserti forms 6097 6098 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) { 6099 assert(VM_Version::supports_avx2(), ""); 6100 assert(imm8 <= 0x01, "imm8: %u", imm8); 6101 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit; 6102 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6103 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6104 emit_int8(0x38); 6105 emit_int8((unsigned char)(0xC0 | encode)); 6106 // 0x00 - insert into lower 128 bits 6107 // 0x01 - insert into upper 128 bits 6108 emit_int8(imm8 & 0x01); 6109 } 6110 6111 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) { 6112 assert(VM_Version::supports_avx2(), ""); 6113 assert(dst != xnoreg, "sanity"); 6114 assert(imm8 <= 0x01, "imm8: %u", imm8); 6115 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit; 6116 InstructionMark im(this); 6117 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6118 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit); 6119 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6120 emit_int8(0x38); 6121 emit_operand(dst, src); 6122 // 0x00 - insert into lower 128 bits 6123 // 0x01 - insert into upper 128 bits 6124 emit_int8(imm8 & 0x01); 6125 } 6126 6127 void Assembler::vinserti32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) { 6128 assert(VM_Version::supports_evex(), ""); 6129 assert(imm8 <= 0x03, "imm8: %u", imm8); 6130 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6131 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6132 emit_int8(0x38); 6133 emit_int8((unsigned char)(0xC0 | encode)); 6134 // 0x00 - insert into q0 128 bits (0..127) 6135 // 0x01 - insert into q1 128 bits (128..255) 6136 // 0x02 - insert into q2 128 bits (256..383) 6137 // 0x03 - insert into q3 128 bits (384..511) 6138 emit_int8(imm8 & 0x03); 6139 } 6140 6141 void Assembler::vinserti32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) { 6142 assert(VM_Version::supports_avx(), ""); 6143 assert(dst != xnoreg, "sanity"); 6144 assert(imm8 <= 0x03, "imm8: %u", imm8); 6145 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit; 6146 InstructionMark im(this); 6147 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6148 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit); 6149 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6150 emit_int8(0x18); 6151 emit_operand(dst, src); 6152 // 0x00 - insert into q0 128 bits (0..127) 6153 // 0x01 - insert into q1 128 bits (128..255) 6154 // 0x02 - insert into q2 128 bits (256..383) 6155 // 0x03 - insert into q3 128 bits (384..511) 6156 emit_int8(imm8 & 0x03); 6157 } 6158 6159 void Assembler::vinserti64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) { 6160 assert(VM_Version::supports_evex(), ""); 6161 assert(imm8 <= 0x01, "imm8: %u", imm8); 6162 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6163 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6164 emit_int8(0x38); 6165 emit_int8((unsigned char)(0xC0 | encode)); 6166 // 0x00 - insert into lower 256 bits 6167 // 0x01 - insert into upper 256 bits 6168 emit_int8(imm8 & 0x01); 6169 } 6170 6171 6172 // vinsertf forms 6173 6174 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) { 6175 assert(VM_Version::supports_avx(), ""); 6176 assert(imm8 <= 0x01, "imm8: %u", imm8); 6177 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit; 6178 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6179 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6180 emit_int8(0x18); 6181 emit_int8((unsigned char)(0xC0 | encode)); 6182 // 0x00 - insert into lower 128 bits 6183 // 0x01 - insert into upper 128 bits 6184 emit_int8(imm8 & 0x01); 6185 } 6186 6187 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) { 6188 assert(VM_Version::supports_avx(), ""); 6189 assert(dst != xnoreg, "sanity"); 6190 assert(imm8 <= 0x01, "imm8: %u", imm8); 6191 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit; 6192 InstructionMark im(this); 6193 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6194 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit); 6195 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6196 emit_int8(0x18); 6197 emit_operand(dst, src); 6198 // 0x00 - insert into lower 128 bits 6199 // 0x01 - insert into upper 128 bits 6200 emit_int8(imm8 & 0x01); 6201 } 6202 6203 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) { 6204 assert(VM_Version::supports_evex(), ""); 6205 assert(imm8 <= 0x03, "imm8: %u", imm8); 6206 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6207 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6208 emit_int8(0x18); 6209 emit_int8((unsigned char)(0xC0 | encode)); 6210 // 0x00 - insert into q0 128 bits (0..127) 6211 // 0x01 - insert into q1 128 bits (128..255) 6212 // 0x02 - insert into q2 128 bits (256..383) 6213 // 0x03 - insert into q3 128 bits (384..511) 6214 emit_int8(imm8 & 0x03); 6215 } 6216 6217 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) { 6218 assert(VM_Version::supports_avx(), ""); 6219 assert(dst != xnoreg, "sanity"); 6220 assert(imm8 <= 0x03, "imm8: %u", imm8); 6221 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit; 6222 InstructionMark im(this); 6223 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6224 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit); 6225 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6226 emit_int8(0x18); 6227 emit_operand(dst, src); 6228 // 0x00 - insert into q0 128 bits (0..127) 6229 // 0x01 - insert into q1 128 bits (128..255) 6230 // 0x02 - insert into q2 128 bits (256..383) 6231 // 0x03 - insert into q3 128 bits (384..511) 6232 emit_int8(imm8 & 0x03); 6233 } 6234 6235 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) { 6236 assert(VM_Version::supports_evex(), ""); 6237 assert(imm8 <= 0x01, "imm8: %u", imm8); 6238 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6239 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6240 emit_int8(0x1A); 6241 emit_int8((unsigned char)(0xC0 | encode)); 6242 // 0x00 - insert into lower 256 bits 6243 // 0x01 - insert into upper 256 bits 6244 emit_int8(imm8 & 0x01); 6245 } 6246 6247 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) { 6248 assert(VM_Version::supports_evex(), ""); 6249 assert(dst != xnoreg, "sanity"); 6250 assert(imm8 <= 0x01, "imm8: %u", imm8); 6251 InstructionMark im(this); 6252 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6253 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_64bit); 6254 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6255 emit_int8(0x1A); 6256 emit_operand(dst, src); 6257 // 0x00 - insert into lower 256 bits 6258 // 0x01 - insert into upper 256 bits 6259 emit_int8(imm8 & 0x01); 6260 } 6261 6262 6263 // vextracti forms 6264 6265 void Assembler::vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) { 6266 assert(VM_Version::supports_avx(), ""); 6267 assert(imm8 <= 0x01, "imm8: %u", imm8); 6268 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit; 6269 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6270 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6271 emit_int8(0x39); 6272 emit_int8((unsigned char)(0xC0 | encode)); 6273 // 0x00 - extract from lower 128 bits 6274 // 0x01 - extract from upper 128 bits 6275 emit_int8(imm8 & 0x01); 6276 } 6277 6278 void Assembler::vextracti128(Address dst, XMMRegister src, uint8_t imm8) { 6279 assert(VM_Version::supports_avx2(), ""); 6280 assert(src != xnoreg, "sanity"); 6281 assert(imm8 <= 0x01, "imm8: %u", imm8); 6282 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit; 6283 InstructionMark im(this); 6284 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6285 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit); 6286 attributes.reset_is_clear_context(); 6287 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6288 emit_int8(0x39); 6289 emit_operand(src, dst); 6290 // 0x00 - extract from lower 128 bits 6291 // 0x01 - extract from upper 128 bits 6292 emit_int8(imm8 & 0x01); 6293 } 6294 6295 void Assembler::vextracti32x4(XMMRegister dst, XMMRegister src, uint8_t imm8) { 6296 assert(VM_Version::supports_avx(), ""); 6297 assert(imm8 <= 0x03, "imm8: %u", imm8); 6298 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit; 6299 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6300 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6301 emit_int8(0x39); 6302 emit_int8((unsigned char)(0xC0 | encode)); 6303 // 0x00 - extract from bits 127:0 6304 // 0x01 - extract from bits 255:128 6305 // 0x02 - extract from bits 383:256 6306 // 0x03 - extract from bits 511:384 6307 emit_int8(imm8 & 0x03); 6308 } 6309 6310 void Assembler::vextracti32x4(Address dst, XMMRegister src, uint8_t imm8) { 6311 assert(VM_Version::supports_evex(), ""); 6312 assert(src != xnoreg, "sanity"); 6313 assert(imm8 <= 0x03, "imm8: %u", imm8); 6314 InstructionMark im(this); 6315 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6316 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit); 6317 attributes.reset_is_clear_context(); 6318 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6319 emit_int8(0x39); 6320 emit_operand(src, dst); 6321 // 0x00 - extract from bits 127:0 6322 // 0x01 - extract from bits 255:128 6323 // 0x02 - extract from bits 383:256 6324 // 0x03 - extract from bits 511:384 6325 emit_int8(imm8 & 0x03); 6326 } 6327 6328 void Assembler::vextracti64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) { 6329 assert(VM_Version::supports_avx512dq(), ""); 6330 assert(imm8 <= 0x03, "imm8: %u", imm8); 6331 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6332 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6333 emit_int8(0x39); 6334 emit_int8((unsigned char)(0xC0 | encode)); 6335 // 0x00 - extract from bits 127:0 6336 // 0x01 - extract from bits 255:128 6337 // 0x02 - extract from bits 383:256 6338 // 0x03 - extract from bits 511:384 6339 emit_int8(imm8 & 0x03); 6340 } 6341 6342 void Assembler::vextracti64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) { 6343 assert(VM_Version::supports_evex(), ""); 6344 assert(imm8 <= 0x01, "imm8: %u", imm8); 6345 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6346 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6347 emit_int8(0x3B); 6348 emit_int8((unsigned char)(0xC0 | encode)); 6349 // 0x00 - extract from lower 256 bits 6350 // 0x01 - extract from upper 256 bits 6351 emit_int8(imm8 & 0x01); 6352 } 6353 6354 6355 // vextractf forms 6356 6357 void Assembler::vextractf128(XMMRegister dst, XMMRegister src, uint8_t imm8) { 6358 assert(VM_Version::supports_avx(), ""); 6359 assert(imm8 <= 0x01, "imm8: %u", imm8); 6360 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit; 6361 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6362 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6363 emit_int8(0x19); 6364 emit_int8((unsigned char)(0xC0 | encode)); 6365 // 0x00 - extract from lower 128 bits 6366 // 0x01 - extract from upper 128 bits 6367 emit_int8(imm8 & 0x01); 6368 } 6369 6370 void Assembler::vextractf128(Address dst, XMMRegister src, uint8_t imm8) { 6371 assert(VM_Version::supports_avx(), ""); 6372 assert(src != xnoreg, "sanity"); 6373 assert(imm8 <= 0x01, "imm8: %u", imm8); 6374 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit; 6375 InstructionMark im(this); 6376 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6377 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit); 6378 attributes.reset_is_clear_context(); 6379 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6380 emit_int8(0x19); 6381 emit_operand(src, dst); 6382 // 0x00 - extract from lower 128 bits 6383 // 0x01 - extract from upper 128 bits 6384 emit_int8(imm8 & 0x01); 6385 } 6386 6387 void Assembler::vextractf32x4(XMMRegister dst, XMMRegister src, uint8_t imm8) { 6388 assert(VM_Version::supports_avx(), ""); 6389 assert(imm8 <= 0x03, "imm8: %u", imm8); 6390 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit; 6391 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6392 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6393 emit_int8(0x19); 6394 emit_int8((unsigned char)(0xC0 | encode)); 6395 // 0x00 - extract from bits 127:0 6396 // 0x01 - extract from bits 255:128 6397 // 0x02 - extract from bits 383:256 6398 // 0x03 - extract from bits 511:384 6399 emit_int8(imm8 & 0x03); 6400 } 6401 6402 void Assembler::vextractf32x4(Address dst, XMMRegister src, uint8_t imm8) { 6403 assert(VM_Version::supports_evex(), ""); 6404 assert(src != xnoreg, "sanity"); 6405 assert(imm8 <= 0x03, "imm8: %u", imm8); 6406 InstructionMark im(this); 6407 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6408 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit); 6409 attributes.reset_is_clear_context(); 6410 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6411 emit_int8(0x19); 6412 emit_operand(src, dst); 6413 // 0x00 - extract from bits 127:0 6414 // 0x01 - extract from bits 255:128 6415 // 0x02 - extract from bits 383:256 6416 // 0x03 - extract from bits 511:384 6417 emit_int8(imm8 & 0x03); 6418 } 6419 6420 void Assembler::vextractf64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) { 6421 assert(VM_Version::supports_avx512dq(), ""); 6422 assert(imm8 <= 0x03, "imm8: %u", imm8); 6423 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6424 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6425 emit_int8(0x19); 6426 emit_int8((unsigned char)(0xC0 | encode)); 6427 // 0x00 - extract from bits 127:0 6428 // 0x01 - extract from bits 255:128 6429 // 0x02 - extract from bits 383:256 6430 // 0x03 - extract from bits 511:384 6431 emit_int8(imm8 & 0x03); 6432 } 6433 6434 void Assembler::vextractf64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) { 6435 assert(VM_Version::supports_evex(), ""); 6436 assert(imm8 <= 0x01, "imm8: %u", imm8); 6437 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6438 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6439 emit_int8(0x1B); 6440 emit_int8((unsigned char)(0xC0 | encode)); 6441 // 0x00 - extract from lower 256 bits 6442 // 0x01 - extract from upper 256 bits 6443 emit_int8(imm8 & 0x01); 6444 } 6445 6446 void Assembler::vextractf64x4(Address dst, XMMRegister src, uint8_t imm8) { 6447 assert(VM_Version::supports_evex(), ""); 6448 assert(src != xnoreg, "sanity"); 6449 assert(imm8 <= 0x01, "imm8: %u", imm8); 6450 InstructionMark im(this); 6451 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6452 attributes.set_address_attributes(/* tuple_type */ EVEX_T4,/* input_size_in_bits */ EVEX_64bit); 6453 attributes.reset_is_clear_context(); 6454 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6455 emit_int8(0x1B); 6456 emit_operand(src, dst); 6457 // 0x00 - extract from lower 256 bits 6458 // 0x01 - extract from upper 256 bits 6459 emit_int8(imm8 & 0x01); 6460 } 6461 6462 6463 // legacy word/dword replicate 6464 void Assembler::vpbroadcastw(XMMRegister dst, XMMRegister src) { 6465 assert(VM_Version::supports_avx2(), ""); 6466 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 6467 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6468 emit_int8(0x79); 6469 emit_int8((unsigned char)(0xC0 | encode)); 6470 } 6471 6472 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src) { 6473 assert(VM_Version::supports_avx2(), ""); 6474 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6475 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6476 emit_int8(0x58); 6477 emit_int8((unsigned char)(0xC0 | encode)); 6478 } 6479 6480 6481 // xmm/mem sourced byte/word/dword/qword replicate 6482 6483 // duplicate 1-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL 6484 void Assembler::evpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len) { 6485 assert(VM_Version::supports_evex(), ""); 6486 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 6487 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6488 emit_int8(0x78); 6489 emit_int8((unsigned char)(0xC0 | encode)); 6490 } 6491 6492 void Assembler::evpbroadcastb(XMMRegister dst, Address src, int vector_len) { 6493 assert(VM_Version::supports_evex(), ""); 6494 assert(dst != xnoreg, "sanity"); 6495 InstructionMark im(this); 6496 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 6497 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit); 6498 // swap src<->dst for encoding 6499 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6500 emit_int8(0x78); 6501 emit_operand(dst, src); 6502 } 6503 6504 // duplicate 2-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL 6505 void Assembler::evpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len) { 6506 assert(VM_Version::supports_evex(), ""); 6507 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 6508 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6509 emit_int8(0x79); 6510 emit_int8((unsigned char)(0xC0 | encode)); 6511 } 6512 6513 void Assembler::evpbroadcastw(XMMRegister dst, Address src, int vector_len) { 6514 assert(VM_Version::supports_evex(), ""); 6515 assert(dst != xnoreg, "sanity"); 6516 InstructionMark im(this); 6517 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 6518 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit); 6519 // swap src<->dst for encoding 6520 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6521 emit_int8(0x79); 6522 emit_operand(dst, src); 6523 } 6524 6525 // duplicate 4-byte integer data from src into programmed locations in dest : requires AVX512VL 6526 void Assembler::evpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len) { 6527 assert(VM_Version::supports_evex(), ""); 6528 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6529 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6530 emit_int8(0x58); 6531 emit_int8((unsigned char)(0xC0 | encode)); 6532 } 6533 6534 void Assembler::evpbroadcastd(XMMRegister dst, Address src, int vector_len) { 6535 assert(VM_Version::supports_evex(), ""); 6536 assert(dst != xnoreg, "sanity"); 6537 InstructionMark im(this); 6538 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6539 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 6540 // swap src<->dst for encoding 6541 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6542 emit_int8(0x58); 6543 emit_operand(dst, src); 6544 } 6545 6546 // duplicate 8-byte integer data from src into programmed locations in dest : requires AVX512VL 6547 void Assembler::evpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len) { 6548 assert(VM_Version::supports_evex(), ""); 6549 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6550 attributes.set_rex_vex_w_reverted(); 6551 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6552 emit_int8(0x59); 6553 emit_int8((unsigned char)(0xC0 | encode)); 6554 } 6555 6556 void Assembler::evpbroadcastq(XMMRegister dst, Address src, int vector_len) { 6557 assert(VM_Version::supports_evex(), ""); 6558 assert(dst != xnoreg, "sanity"); 6559 InstructionMark im(this); 6560 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6561 attributes.set_rex_vex_w_reverted(); 6562 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 6563 // swap src<->dst for encoding 6564 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6565 emit_int8(0x59); 6566 emit_operand(dst, src); 6567 } 6568 6569 6570 // scalar single/double precision replicate 6571 6572 // duplicate single precision data from src into programmed locations in dest : requires AVX512VL 6573 void Assembler::evpbroadcastss(XMMRegister dst, XMMRegister src, int vector_len) { 6574 assert(VM_Version::supports_evex(), ""); 6575 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6576 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6577 emit_int8(0x18); 6578 emit_int8((unsigned char)(0xC0 | encode)); 6579 } 6580 6581 void Assembler::evpbroadcastss(XMMRegister dst, Address src, int vector_len) { 6582 assert(VM_Version::supports_evex(), ""); 6583 assert(dst != xnoreg, "sanity"); 6584 InstructionMark im(this); 6585 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6586 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 6587 // swap src<->dst for encoding 6588 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6589 emit_int8(0x18); 6590 emit_operand(dst, src); 6591 } 6592 6593 // duplicate double precision data from src into programmed locations in dest : requires AVX512VL 6594 void Assembler::evpbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len) { 6595 assert(VM_Version::supports_evex(), ""); 6596 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6597 attributes.set_rex_vex_w_reverted(); 6598 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6599 emit_int8(0x19); 6600 emit_int8((unsigned char)(0xC0 | encode)); 6601 } 6602 6603 void Assembler::evpbroadcastsd(XMMRegister dst, Address src, int vector_len) { 6604 assert(VM_Version::supports_evex(), ""); 6605 assert(dst != xnoreg, "sanity"); 6606 InstructionMark im(this); 6607 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6608 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 6609 attributes.set_rex_vex_w_reverted(); 6610 // swap src<->dst for encoding 6611 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6612 emit_int8(0x19); 6613 emit_operand(dst, src); 6614 } 6615 6616 6617 // gpr source broadcast forms 6618 6619 // duplicate 1-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL 6620 void Assembler::evpbroadcastb(XMMRegister dst, Register src, int vector_len) { 6621 assert(VM_Version::supports_evex(), ""); 6622 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 6623 attributes.set_is_evex_instruction(); 6624 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6625 emit_int8(0x7A); 6626 emit_int8((unsigned char)(0xC0 | encode)); 6627 } 6628 6629 // duplicate 2-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL 6630 void Assembler::evpbroadcastw(XMMRegister dst, Register src, int vector_len) { 6631 assert(VM_Version::supports_evex(), ""); 6632 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 6633 attributes.set_is_evex_instruction(); 6634 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6635 emit_int8(0x7B); 6636 emit_int8((unsigned char)(0xC0 | encode)); 6637 } 6638 6639 // duplicate 4-byte integer data from src into programmed locations in dest : requires AVX512VL 6640 void Assembler::evpbroadcastd(XMMRegister dst, Register src, int vector_len) { 6641 assert(VM_Version::supports_evex(), ""); 6642 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6643 attributes.set_is_evex_instruction(); 6644 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6645 emit_int8(0x7C); 6646 emit_int8((unsigned char)(0xC0 | encode)); 6647 } 6648 6649 // duplicate 8-byte integer data from src into programmed locations in dest : requires AVX512VL 6650 void Assembler::evpbroadcastq(XMMRegister dst, Register src, int vector_len) { 6651 assert(VM_Version::supports_evex(), ""); 6652 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6653 attributes.set_is_evex_instruction(); 6654 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6655 emit_int8(0x7C); 6656 emit_int8((unsigned char)(0xC0 | encode)); 6657 } 6658 6659 6660 // Carry-Less Multiplication Quadword 6661 void Assembler::pclmulqdq(XMMRegister dst, XMMRegister src, int mask) { 6662 assert(VM_Version::supports_clmul(), ""); 6663 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 6664 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6665 emit_int8(0x44); 6666 emit_int8((unsigned char)(0xC0 | encode)); 6667 emit_int8((unsigned char)mask); 6668 } 6669 6670 // Carry-Less Multiplication Quadword 6671 void Assembler::vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask) { 6672 assert(VM_Version::supports_avx() && VM_Version::supports_clmul(), ""); 6673 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 6674 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6675 emit_int8(0x44); 6676 emit_int8((unsigned char)(0xC0 | encode)); 6677 emit_int8((unsigned char)mask); 6678 } 6679 6680 void Assembler::vzeroupper() { 6681 if (VM_Version::supports_vzeroupper()) { 6682 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 6683 (void)vex_prefix_and_encode(0, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 6684 emit_int8(0x77); 6685 } 6686 } 6687 6688 #ifndef _LP64 6689 // 32bit only pieces of the assembler 6690 6691 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) { 6692 // NO PREFIX AS NEVER 64BIT 6693 InstructionMark im(this); 6694 emit_int8((unsigned char)0x81); 6695 emit_int8((unsigned char)(0xF8 | src1->encoding())); 6696 emit_data(imm32, rspec, 0); 6697 } 6698 6699 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) { 6700 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs 6701 InstructionMark im(this); 6702 emit_int8((unsigned char)0x81); 6703 emit_operand(rdi, src1); 6704 emit_data(imm32, rspec, 0); 6705 } 6706 6707 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax, 6708 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded 6709 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise. 6710 void Assembler::cmpxchg8(Address adr) { 6711 InstructionMark im(this); 6712 emit_int8(0x0F); 6713 emit_int8((unsigned char)0xC7); 6714 emit_operand(rcx, adr); 6715 } 6716 6717 void Assembler::decl(Register dst) { 6718 // Don't use it directly. Use MacroAssembler::decrementl() instead. 6719 emit_int8(0x48 | dst->encoding()); 6720 } 6721 6722 #endif // _LP64 6723 6724 // 64bit typically doesn't use the x87 but needs to for the trig funcs 6725 6726 void Assembler::fabs() { 6727 emit_int8((unsigned char)0xD9); 6728 emit_int8((unsigned char)0xE1); 6729 } 6730 6731 void Assembler::fadd(int i) { 6732 emit_farith(0xD8, 0xC0, i); 6733 } 6734 6735 void Assembler::fadd_d(Address src) { 6736 InstructionMark im(this); 6737 emit_int8((unsigned char)0xDC); 6738 emit_operand32(rax, src); 6739 } 6740 6741 void Assembler::fadd_s(Address src) { 6742 InstructionMark im(this); 6743 emit_int8((unsigned char)0xD8); 6744 emit_operand32(rax, src); 6745 } 6746 6747 void Assembler::fadda(int i) { 6748 emit_farith(0xDC, 0xC0, i); 6749 } 6750 6751 void Assembler::faddp(int i) { 6752 emit_farith(0xDE, 0xC0, i); 6753 } 6754 6755 void Assembler::fchs() { 6756 emit_int8((unsigned char)0xD9); 6757 emit_int8((unsigned char)0xE0); 6758 } 6759 6760 void Assembler::fcom(int i) { 6761 emit_farith(0xD8, 0xD0, i); 6762 } 6763 6764 void Assembler::fcomp(int i) { 6765 emit_farith(0xD8, 0xD8, i); 6766 } 6767 6768 void Assembler::fcomp_d(Address src) { 6769 InstructionMark im(this); 6770 emit_int8((unsigned char)0xDC); 6771 emit_operand32(rbx, src); 6772 } 6773 6774 void Assembler::fcomp_s(Address src) { 6775 InstructionMark im(this); 6776 emit_int8((unsigned char)0xD8); 6777 emit_operand32(rbx, src); 6778 } 6779 6780 void Assembler::fcompp() { 6781 emit_int8((unsigned char)0xDE); 6782 emit_int8((unsigned char)0xD9); 6783 } 6784 6785 void Assembler::fcos() { 6786 emit_int8((unsigned char)0xD9); 6787 emit_int8((unsigned char)0xFF); 6788 } 6789 6790 void Assembler::fdecstp() { 6791 emit_int8((unsigned char)0xD9); 6792 emit_int8((unsigned char)0xF6); 6793 } 6794 6795 void Assembler::fdiv(int i) { 6796 emit_farith(0xD8, 0xF0, i); 6797 } 6798 6799 void Assembler::fdiv_d(Address src) { 6800 InstructionMark im(this); 6801 emit_int8((unsigned char)0xDC); 6802 emit_operand32(rsi, src); 6803 } 6804 6805 void Assembler::fdiv_s(Address src) { 6806 InstructionMark im(this); 6807 emit_int8((unsigned char)0xD8); 6808 emit_operand32(rsi, src); 6809 } 6810 6811 void Assembler::fdiva(int i) { 6812 emit_farith(0xDC, 0xF8, i); 6813 } 6814 6815 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994) 6816 // is erroneous for some of the floating-point instructions below. 6817 6818 void Assembler::fdivp(int i) { 6819 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong) 6820 } 6821 6822 void Assembler::fdivr(int i) { 6823 emit_farith(0xD8, 0xF8, i); 6824 } 6825 6826 void Assembler::fdivr_d(Address src) { 6827 InstructionMark im(this); 6828 emit_int8((unsigned char)0xDC); 6829 emit_operand32(rdi, src); 6830 } 6831 6832 void Assembler::fdivr_s(Address src) { 6833 InstructionMark im(this); 6834 emit_int8((unsigned char)0xD8); 6835 emit_operand32(rdi, src); 6836 } 6837 6838 void Assembler::fdivra(int i) { 6839 emit_farith(0xDC, 0xF0, i); 6840 } 6841 6842 void Assembler::fdivrp(int i) { 6843 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong) 6844 } 6845 6846 void Assembler::ffree(int i) { 6847 emit_farith(0xDD, 0xC0, i); 6848 } 6849 6850 void Assembler::fild_d(Address adr) { 6851 InstructionMark im(this); 6852 emit_int8((unsigned char)0xDF); 6853 emit_operand32(rbp, adr); 6854 } 6855 6856 void Assembler::fild_s(Address adr) { 6857 InstructionMark im(this); 6858 emit_int8((unsigned char)0xDB); 6859 emit_operand32(rax, adr); 6860 } 6861 6862 void Assembler::fincstp() { 6863 emit_int8((unsigned char)0xD9); 6864 emit_int8((unsigned char)0xF7); 6865 } 6866 6867 void Assembler::finit() { 6868 emit_int8((unsigned char)0x9B); 6869 emit_int8((unsigned char)0xDB); 6870 emit_int8((unsigned char)0xE3); 6871 } 6872 6873 void Assembler::fist_s(Address adr) { 6874 InstructionMark im(this); 6875 emit_int8((unsigned char)0xDB); 6876 emit_operand32(rdx, adr); 6877 } 6878 6879 void Assembler::fistp_d(Address adr) { 6880 InstructionMark im(this); 6881 emit_int8((unsigned char)0xDF); 6882 emit_operand32(rdi, adr); 6883 } 6884 6885 void Assembler::fistp_s(Address adr) { 6886 InstructionMark im(this); 6887 emit_int8((unsigned char)0xDB); 6888 emit_operand32(rbx, adr); 6889 } 6890 6891 void Assembler::fld1() { 6892 emit_int8((unsigned char)0xD9); 6893 emit_int8((unsigned char)0xE8); 6894 } 6895 6896 void Assembler::fld_d(Address adr) { 6897 InstructionMark im(this); 6898 emit_int8((unsigned char)0xDD); 6899 emit_operand32(rax, adr); 6900 } 6901 6902 void Assembler::fld_s(Address adr) { 6903 InstructionMark im(this); 6904 emit_int8((unsigned char)0xD9); 6905 emit_operand32(rax, adr); 6906 } 6907 6908 6909 void Assembler::fld_s(int index) { 6910 emit_farith(0xD9, 0xC0, index); 6911 } 6912 6913 void Assembler::fld_x(Address adr) { 6914 InstructionMark im(this); 6915 emit_int8((unsigned char)0xDB); 6916 emit_operand32(rbp, adr); 6917 } 6918 6919 void Assembler::fldcw(Address src) { 6920 InstructionMark im(this); 6921 emit_int8((unsigned char)0xD9); 6922 emit_operand32(rbp, src); 6923 } 6924 6925 void Assembler::fldenv(Address src) { 6926 InstructionMark im(this); 6927 emit_int8((unsigned char)0xD9); 6928 emit_operand32(rsp, src); 6929 } 6930 6931 void Assembler::fldlg2() { 6932 emit_int8((unsigned char)0xD9); 6933 emit_int8((unsigned char)0xEC); 6934 } 6935 6936 void Assembler::fldln2() { 6937 emit_int8((unsigned char)0xD9); 6938 emit_int8((unsigned char)0xED); 6939 } 6940 6941 void Assembler::fldz() { 6942 emit_int8((unsigned char)0xD9); 6943 emit_int8((unsigned char)0xEE); 6944 } 6945 6946 void Assembler::flog() { 6947 fldln2(); 6948 fxch(); 6949 fyl2x(); 6950 } 6951 6952 void Assembler::flog10() { 6953 fldlg2(); 6954 fxch(); 6955 fyl2x(); 6956 } 6957 6958 void Assembler::fmul(int i) { 6959 emit_farith(0xD8, 0xC8, i); 6960 } 6961 6962 void Assembler::fmul_d(Address src) { 6963 InstructionMark im(this); 6964 emit_int8((unsigned char)0xDC); 6965 emit_operand32(rcx, src); 6966 } 6967 6968 void Assembler::fmul_s(Address src) { 6969 InstructionMark im(this); 6970 emit_int8((unsigned char)0xD8); 6971 emit_operand32(rcx, src); 6972 } 6973 6974 void Assembler::fmula(int i) { 6975 emit_farith(0xDC, 0xC8, i); 6976 } 6977 6978 void Assembler::fmulp(int i) { 6979 emit_farith(0xDE, 0xC8, i); 6980 } 6981 6982 void Assembler::fnsave(Address dst) { 6983 InstructionMark im(this); 6984 emit_int8((unsigned char)0xDD); 6985 emit_operand32(rsi, dst); 6986 } 6987 6988 void Assembler::fnstcw(Address src) { 6989 InstructionMark im(this); 6990 emit_int8((unsigned char)0x9B); 6991 emit_int8((unsigned char)0xD9); 6992 emit_operand32(rdi, src); 6993 } 6994 6995 void Assembler::fnstsw_ax() { 6996 emit_int8((unsigned char)0xDF); 6997 emit_int8((unsigned char)0xE0); 6998 } 6999 7000 void Assembler::fprem() { 7001 emit_int8((unsigned char)0xD9); 7002 emit_int8((unsigned char)0xF8); 7003 } 7004 7005 void Assembler::fprem1() { 7006 emit_int8((unsigned char)0xD9); 7007 emit_int8((unsigned char)0xF5); 7008 } 7009 7010 void Assembler::frstor(Address src) { 7011 InstructionMark im(this); 7012 emit_int8((unsigned char)0xDD); 7013 emit_operand32(rsp, src); 7014 } 7015 7016 void Assembler::fsin() { 7017 emit_int8((unsigned char)0xD9); 7018 emit_int8((unsigned char)0xFE); 7019 } 7020 7021 void Assembler::fsqrt() { 7022 emit_int8((unsigned char)0xD9); 7023 emit_int8((unsigned char)0xFA); 7024 } 7025 7026 void Assembler::fst_d(Address adr) { 7027 InstructionMark im(this); 7028 emit_int8((unsigned char)0xDD); 7029 emit_operand32(rdx, adr); 7030 } 7031 7032 void Assembler::fst_s(Address adr) { 7033 InstructionMark im(this); 7034 emit_int8((unsigned char)0xD9); 7035 emit_operand32(rdx, adr); 7036 } 7037 7038 void Assembler::fstp_d(Address adr) { 7039 InstructionMark im(this); 7040 emit_int8((unsigned char)0xDD); 7041 emit_operand32(rbx, adr); 7042 } 7043 7044 void Assembler::fstp_d(int index) { 7045 emit_farith(0xDD, 0xD8, index); 7046 } 7047 7048 void Assembler::fstp_s(Address adr) { 7049 InstructionMark im(this); 7050 emit_int8((unsigned char)0xD9); 7051 emit_operand32(rbx, adr); 7052 } 7053 7054 void Assembler::fstp_x(Address adr) { 7055 InstructionMark im(this); 7056 emit_int8((unsigned char)0xDB); 7057 emit_operand32(rdi, adr); 7058 } 7059 7060 void Assembler::fsub(int i) { 7061 emit_farith(0xD8, 0xE0, i); 7062 } 7063 7064 void Assembler::fsub_d(Address src) { 7065 InstructionMark im(this); 7066 emit_int8((unsigned char)0xDC); 7067 emit_operand32(rsp, src); 7068 } 7069 7070 void Assembler::fsub_s(Address src) { 7071 InstructionMark im(this); 7072 emit_int8((unsigned char)0xD8); 7073 emit_operand32(rsp, src); 7074 } 7075 7076 void Assembler::fsuba(int i) { 7077 emit_farith(0xDC, 0xE8, i); 7078 } 7079 7080 void Assembler::fsubp(int i) { 7081 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong) 7082 } 7083 7084 void Assembler::fsubr(int i) { 7085 emit_farith(0xD8, 0xE8, i); 7086 } 7087 7088 void Assembler::fsubr_d(Address src) { 7089 InstructionMark im(this); 7090 emit_int8((unsigned char)0xDC); 7091 emit_operand32(rbp, src); 7092 } 7093 7094 void Assembler::fsubr_s(Address src) { 7095 InstructionMark im(this); 7096 emit_int8((unsigned char)0xD8); 7097 emit_operand32(rbp, src); 7098 } 7099 7100 void Assembler::fsubra(int i) { 7101 emit_farith(0xDC, 0xE0, i); 7102 } 7103 7104 void Assembler::fsubrp(int i) { 7105 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong) 7106 } 7107 7108 void Assembler::ftan() { 7109 emit_int8((unsigned char)0xD9); 7110 emit_int8((unsigned char)0xF2); 7111 emit_int8((unsigned char)0xDD); 7112 emit_int8((unsigned char)0xD8); 7113 } 7114 7115 void Assembler::ftst() { 7116 emit_int8((unsigned char)0xD9); 7117 emit_int8((unsigned char)0xE4); 7118 } 7119 7120 void Assembler::fucomi(int i) { 7121 // make sure the instruction is supported (introduced for P6, together with cmov) 7122 guarantee(VM_Version::supports_cmov(), "illegal instruction"); 7123 emit_farith(0xDB, 0xE8, i); 7124 } 7125 7126 void Assembler::fucomip(int i) { 7127 // make sure the instruction is supported (introduced for P6, together with cmov) 7128 guarantee(VM_Version::supports_cmov(), "illegal instruction"); 7129 emit_farith(0xDF, 0xE8, i); 7130 } 7131 7132 void Assembler::fwait() { 7133 emit_int8((unsigned char)0x9B); 7134 } 7135 7136 void Assembler::fxch(int i) { 7137 emit_farith(0xD9, 0xC8, i); 7138 } 7139 7140 void Assembler::fyl2x() { 7141 emit_int8((unsigned char)0xD9); 7142 emit_int8((unsigned char)0xF1); 7143 } 7144 7145 void Assembler::frndint() { 7146 emit_int8((unsigned char)0xD9); 7147 emit_int8((unsigned char)0xFC); 7148 } 7149 7150 void Assembler::f2xm1() { 7151 emit_int8((unsigned char)0xD9); 7152 emit_int8((unsigned char)0xF0); 7153 } 7154 7155 void Assembler::fldl2e() { 7156 emit_int8((unsigned char)0xD9); 7157 emit_int8((unsigned char)0xEA); 7158 } 7159 7160 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding. 7161 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 }; 7162 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding. 7163 static int simd_opc[4] = { 0, 0, 0x38, 0x3A }; 7164 7165 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding. 7166 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) { 7167 if (pre > 0) { 7168 emit_int8(simd_pre[pre]); 7169 } 7170 if (rex_w) { 7171 prefixq(adr, xreg); 7172 } else { 7173 prefix(adr, xreg); 7174 } 7175 if (opc > 0) { 7176 emit_int8(0x0F); 7177 int opc2 = simd_opc[opc]; 7178 if (opc2 > 0) { 7179 emit_int8(opc2); 7180 } 7181 } 7182 } 7183 7184 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) { 7185 if (pre > 0) { 7186 emit_int8(simd_pre[pre]); 7187 } 7188 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) : prefix_and_encode(dst_enc, src_enc); 7189 if (opc > 0) { 7190 emit_int8(0x0F); 7191 int opc2 = simd_opc[opc]; 7192 if (opc2 > 0) { 7193 emit_int8(opc2); 7194 } 7195 } 7196 return encode; 7197 } 7198 7199 7200 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc) { 7201 int vector_len = _attributes->get_vector_len(); 7202 bool vex_w = _attributes->is_rex_vex_w(); 7203 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) { 7204 prefix(VEX_3bytes); 7205 7206 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0); 7207 byte1 = (~byte1) & 0xE0; 7208 byte1 |= opc; 7209 emit_int8(byte1); 7210 7211 int byte2 = ((~nds_enc) & 0xf) << 3; 7212 byte2 |= (vex_w ? VEX_W : 0) | ((vector_len > 0) ? 4 : 0) | pre; 7213 emit_int8(byte2); 7214 } else { 7215 prefix(VEX_2bytes); 7216 7217 int byte1 = vex_r ? VEX_R : 0; 7218 byte1 = (~byte1) & 0x80; 7219 byte1 |= ((~nds_enc) & 0xf) << 3; 7220 byte1 |= ((vector_len > 0 ) ? 4 : 0) | pre; 7221 emit_int8(byte1); 7222 } 7223 } 7224 7225 // This is a 4 byte encoding 7226 void Assembler::evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_r, bool evex_v, int nds_enc, VexSimdPrefix pre, VexOpcode opc){ 7227 // EVEX 0x62 prefix 7228 prefix(EVEX_4bytes); 7229 bool vex_w = _attributes->is_rex_vex_w(); 7230 int evex_encoding = (vex_w ? VEX_W : 0); 7231 // EVEX.b is not currently used for broadcast of single element or data rounding modes 7232 _attributes->set_evex_encoding(evex_encoding); 7233 7234 // P0: byte 2, initialized to RXBR`00mm 7235 // instead of not'd 7236 int byte2 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0) | (evex_r ? EVEX_Rb : 0); 7237 byte2 = (~byte2) & 0xF0; 7238 // confine opc opcode extensions in mm bits to lower two bits 7239 // of form {0F, 0F_38, 0F_3A} 7240 byte2 |= opc; 7241 emit_int8(byte2); 7242 7243 // P1: byte 3 as Wvvvv1pp 7244 int byte3 = ((~nds_enc) & 0xf) << 3; 7245 // p[10] is always 1 7246 byte3 |= EVEX_F; 7247 byte3 |= (vex_w & 1) << 7; 7248 // confine pre opcode extensions in pp bits to lower two bits 7249 // of form {66, F3, F2} 7250 byte3 |= pre; 7251 emit_int8(byte3); 7252 7253 // P2: byte 4 as zL'Lbv'aaa 7254 // kregs are implemented in the low 3 bits as aaa (hard code k1, it will be initialized for now) 7255 int byte4 = (_attributes->is_no_reg_mask()) ? 7256 0 : 7257 _attributes->get_embedded_opmask_register_specifier(); 7258 // EVEX.v` for extending EVEX.vvvv or VIDX 7259 byte4 |= (evex_v ? 0: EVEX_V); 7260 // third EXEC.b for broadcast actions 7261 byte4 |= (_attributes->is_extended_context() ? EVEX_Rb : 0); 7262 // fourth EVEX.L'L for vector length : 0 is 128, 1 is 256, 2 is 512, currently we do not support 1024 7263 byte4 |= ((_attributes->get_vector_len())& 0x3) << 5; 7264 // last is EVEX.z for zero/merge actions 7265 if (_attributes->is_no_reg_mask() == false) { 7266 byte4 |= (_attributes->is_clear_context() ? EVEX_Z : 0); 7267 } 7268 emit_int8(byte4); 7269 } 7270 7271 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) { 7272 bool vex_r = ((xreg_enc & 8) == 8) ? 1 : 0; 7273 bool vex_b = adr.base_needs_rex(); 7274 bool vex_x = adr.index_needs_rex(); 7275 set_attributes(attributes); 7276 attributes->set_current_assembler(this); 7277 7278 // if vector length is turned off, revert to AVX for vectors smaller than 512-bit 7279 if (UseAVX > 2 && _legacy_mode_vl && attributes->uses_vl()) { 7280 switch (attributes->get_vector_len()) { 7281 case AVX_128bit: 7282 case AVX_256bit: 7283 attributes->set_is_legacy_mode(); 7284 break; 7285 } 7286 } 7287 7288 // For pure EVEX check and see if this instruction 7289 // is allowed in legacy mode and has resources which will 7290 // fit in it. Pure EVEX instructions will use set_is_evex_instruction in their definition, 7291 // else that field is set when we encode to EVEX 7292 if (UseAVX > 2 && !attributes->is_legacy_mode() && 7293 !_is_managed && !attributes->is_evex_instruction()) { 7294 if (!_legacy_mode_vl && attributes->get_vector_len() != AVX_512bit) { 7295 bool check_register_bank = NOT_IA32(true) IA32_ONLY(false); 7296 if (check_register_bank) { 7297 // check nds_enc and xreg_enc for upper bank usage 7298 if (nds_enc < 16 && xreg_enc < 16) { 7299 attributes->set_is_legacy_mode(); 7300 } 7301 } else { 7302 attributes->set_is_legacy_mode(); 7303 } 7304 } 7305 } 7306 7307 _is_managed = false; 7308 if (UseAVX > 2 && !attributes->is_legacy_mode()) 7309 { 7310 bool evex_r = (xreg_enc >= 16); 7311 bool evex_v = (nds_enc >= 16); 7312 attributes->set_is_evex_instruction(); 7313 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc); 7314 } else { 7315 if (UseAVX > 2 && attributes->is_rex_vex_w_reverted()) { 7316 attributes->set_rex_vex_w(false); 7317 } 7318 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc); 7319 } 7320 } 7321 7322 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) { 7323 bool vex_r = ((dst_enc & 8) == 8) ? 1 : 0; 7324 bool vex_b = ((src_enc & 8) == 8) ? 1 : 0; 7325 bool vex_x = false; 7326 set_attributes(attributes); 7327 attributes->set_current_assembler(this); 7328 bool check_register_bank = NOT_IA32(true) IA32_ONLY(false); 7329 7330 // if vector length is turned off, revert to AVX for vectors smaller than 512-bit 7331 if (UseAVX > 2 && _legacy_mode_vl && attributes->uses_vl()) { 7332 switch (attributes->get_vector_len()) { 7333 case AVX_128bit: 7334 case AVX_256bit: 7335 if (check_register_bank) { 7336 if (dst_enc >= 16 || nds_enc >= 16 || src_enc >= 16) { 7337 // up propagate arithmetic instructions to meet RA requirements 7338 attributes->set_vector_len(AVX_512bit); 7339 } else { 7340 attributes->set_is_legacy_mode(); 7341 } 7342 } else { 7343 attributes->set_is_legacy_mode(); 7344 } 7345 break; 7346 } 7347 } 7348 7349 // For pure EVEX check and see if this instruction 7350 // is allowed in legacy mode and has resources which will 7351 // fit in it. Pure EVEX instructions will use set_is_evex_instruction in their definition, 7352 // else that field is set when we encode to EVEX 7353 if (UseAVX > 2 && !attributes->is_legacy_mode() && 7354 !_is_managed && !attributes->is_evex_instruction()) { 7355 if (!_legacy_mode_vl && attributes->get_vector_len() != AVX_512bit) { 7356 if (check_register_bank) { 7357 // check dst_enc, nds_enc and src_enc for upper bank usage 7358 if (dst_enc < 16 && nds_enc < 16 && src_enc < 16) { 7359 attributes->set_is_legacy_mode(); 7360 } 7361 } else { 7362 attributes->set_is_legacy_mode(); 7363 } 7364 } 7365 } 7366 7367 _is_managed = false; 7368 if (UseAVX > 2 && !attributes->is_legacy_mode()) 7369 { 7370 bool evex_r = (dst_enc >= 16); 7371 bool evex_v = (nds_enc >= 16); 7372 // can use vex_x as bank extender on rm encoding 7373 vex_x = (src_enc >= 16); 7374 attributes->set_is_evex_instruction(); 7375 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc); 7376 } else { 7377 if (UseAVX > 2 && attributes->is_rex_vex_w_reverted()) { 7378 attributes->set_rex_vex_w(false); 7379 } 7380 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc); 7381 } 7382 7383 // return modrm byte components for operands 7384 return (((dst_enc & 7) << 3) | (src_enc & 7)); 7385 } 7386 7387 7388 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre, 7389 VexOpcode opc, InstructionAttr *attributes) { 7390 if (UseAVX > 0) { 7391 int xreg_enc = xreg->encoding(); 7392 int nds_enc = nds->is_valid() ? nds->encoding() : 0; 7393 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, attributes); 7394 } else { 7395 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding"); 7396 rex_prefix(adr, xreg, pre, opc, attributes->is_rex_vex_w()); 7397 } 7398 } 7399 7400 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre, 7401 VexOpcode opc, InstructionAttr *attributes) { 7402 int dst_enc = dst->encoding(); 7403 int src_enc = src->encoding(); 7404 if (UseAVX > 0) { 7405 int nds_enc = nds->is_valid() ? nds->encoding() : 0; 7406 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, attributes); 7407 } else { 7408 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding"); 7409 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, attributes->is_rex_vex_w()); 7410 } 7411 } 7412 7413 void Assembler::cmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) { 7414 assert(VM_Version::supports_avx(), ""); 7415 assert(!VM_Version::supports_evex(), ""); 7416 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 7417 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 7418 emit_int8((unsigned char)0xC2); 7419 emit_int8((unsigned char)(0xC0 | encode)); 7420 emit_int8((unsigned char)(0xF & cop)); 7421 } 7422 7423 void Assembler::blendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) { 7424 assert(VM_Version::supports_avx(), ""); 7425 assert(!VM_Version::supports_evex(), ""); 7426 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 7427 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 7428 emit_int8((unsigned char)0x4B); 7429 emit_int8((unsigned char)(0xC0 | encode)); 7430 int src2_enc = src2->encoding(); 7431 emit_int8((unsigned char)(0xF0 & src2_enc<<4)); 7432 } 7433 7434 void Assembler::vpblendd(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) { 7435 assert(VM_Version::supports_avx2(), ""); 7436 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 7437 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 7438 emit_int8((unsigned char)0x02); 7439 emit_int8((unsigned char)(0xC0 | encode)); 7440 emit_int8((unsigned char)imm8); 7441 } 7442 7443 void Assembler::shlxl(Register dst, Register src1, Register src2) { 7444 assert(VM_Version::supports_bmi2(), ""); 7445 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 7446 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 7447 emit_int8((unsigned char)0xF7); 7448 emit_int8((unsigned char)(0xC0 | encode)); 7449 } 7450 7451 void Assembler::shlxq(Register dst, Register src1, Register src2) { 7452 assert(VM_Version::supports_bmi2(), ""); 7453 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 7454 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 7455 emit_int8((unsigned char)0xF7); 7456 emit_int8((unsigned char)(0xC0 | encode)); 7457 } 7458 7459 #ifndef _LP64 7460 7461 void Assembler::incl(Register dst) { 7462 // Don't use it directly. Use MacroAssembler::incrementl() instead. 7463 emit_int8(0x40 | dst->encoding()); 7464 } 7465 7466 void Assembler::lea(Register dst, Address src) { 7467 leal(dst, src); 7468 } 7469 7470 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) { 7471 InstructionMark im(this); 7472 emit_int8((unsigned char)0xC7); 7473 emit_operand(rax, dst); 7474 emit_data((int)imm32, rspec, 0); 7475 } 7476 7477 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) { 7478 InstructionMark im(this); 7479 int encode = prefix_and_encode(dst->encoding()); 7480 emit_int8((unsigned char)(0xB8 | encode)); 7481 emit_data((int)imm32, rspec, 0); 7482 } 7483 7484 void Assembler::popa() { // 32bit 7485 emit_int8(0x61); 7486 } 7487 7488 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) { 7489 InstructionMark im(this); 7490 emit_int8(0x68); 7491 emit_data(imm32, rspec, 0); 7492 } 7493 7494 void Assembler::pusha() { // 32bit 7495 emit_int8(0x60); 7496 } 7497 7498 void Assembler::set_byte_if_not_zero(Register dst) { 7499 emit_int8(0x0F); 7500 emit_int8((unsigned char)0x95); 7501 emit_int8((unsigned char)(0xE0 | dst->encoding())); 7502 } 7503 7504 void Assembler::shldl(Register dst, Register src) { 7505 emit_int8(0x0F); 7506 emit_int8((unsigned char)0xA5); 7507 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding())); 7508 } 7509 7510 // 0F A4 / r ib 7511 void Assembler::shldl(Register dst, Register src, int8_t imm8) { 7512 emit_int8(0x0F); 7513 emit_int8((unsigned char)0xA4); 7514 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding())); 7515 emit_int8(imm8); 7516 } 7517 7518 void Assembler::shrdl(Register dst, Register src) { 7519 emit_int8(0x0F); 7520 emit_int8((unsigned char)0xAD); 7521 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding())); 7522 } 7523 7524 #else // LP64 7525 7526 void Assembler::set_byte_if_not_zero(Register dst) { 7527 int enc = prefix_and_encode(dst->encoding(), true); 7528 emit_int8(0x0F); 7529 emit_int8((unsigned char)0x95); 7530 emit_int8((unsigned char)(0xE0 | enc)); 7531 } 7532 7533 // 64bit only pieces of the assembler 7534 // This should only be used by 64bit instructions that can use rip-relative 7535 // it cannot be used by instructions that want an immediate value. 7536 7537 bool Assembler::reachable(AddressLiteral adr) { 7538 int64_t disp; 7539 // None will force a 64bit literal to the code stream. Likely a placeholder 7540 // for something that will be patched later and we need to certain it will 7541 // always be reachable. 7542 if (adr.reloc() == relocInfo::none) { 7543 return false; 7544 } 7545 if (adr.reloc() == relocInfo::internal_word_type) { 7546 // This should be rip relative and easily reachable. 7547 return true; 7548 } 7549 if (adr.reloc() == relocInfo::virtual_call_type || 7550 adr.reloc() == relocInfo::opt_virtual_call_type || 7551 adr.reloc() == relocInfo::static_call_type || 7552 adr.reloc() == relocInfo::static_stub_type ) { 7553 // This should be rip relative within the code cache and easily 7554 // reachable until we get huge code caches. (At which point 7555 // ic code is going to have issues). 7556 return true; 7557 } 7558 if (adr.reloc() != relocInfo::external_word_type && 7559 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special 7560 adr.reloc() != relocInfo::poll_type && // relocs to identify them 7561 adr.reloc() != relocInfo::runtime_call_type ) { 7562 return false; 7563 } 7564 7565 // Stress the correction code 7566 if (ForceUnreachable) { 7567 // Must be runtimecall reloc, see if it is in the codecache 7568 // Flipping stuff in the codecache to be unreachable causes issues 7569 // with things like inline caches where the additional instructions 7570 // are not handled. 7571 if (CodeCache::find_blob(adr._target) == NULL) { 7572 return false; 7573 } 7574 } 7575 // For external_word_type/runtime_call_type if it is reachable from where we 7576 // are now (possibly a temp buffer) and where we might end up 7577 // anywhere in the codeCache then we are always reachable. 7578 // This would have to change if we ever save/restore shared code 7579 // to be more pessimistic. 7580 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int)); 7581 if (!is_simm32(disp)) return false; 7582 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int)); 7583 if (!is_simm32(disp)) return false; 7584 7585 disp = (int64_t)adr._target - ((int64_t)pc() + sizeof(int)); 7586 7587 // Because rip relative is a disp + address_of_next_instruction and we 7588 // don't know the value of address_of_next_instruction we apply a fudge factor 7589 // to make sure we will be ok no matter the size of the instruction we get placed into. 7590 // We don't have to fudge the checks above here because they are already worst case. 7591 7592 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal 7593 // + 4 because better safe than sorry. 7594 const int fudge = 12 + 4; 7595 if (disp < 0) { 7596 disp -= fudge; 7597 } else { 7598 disp += fudge; 7599 } 7600 return is_simm32(disp); 7601 } 7602 7603 // Check if the polling page is not reachable from the code cache using rip-relative 7604 // addressing. 7605 bool Assembler::is_polling_page_far() { 7606 intptr_t addr = (intptr_t)os::get_polling_page(); 7607 return ForceUnreachable || 7608 !is_simm32(addr - (intptr_t)CodeCache::low_bound()) || 7609 !is_simm32(addr - (intptr_t)CodeCache::high_bound()); 7610 } 7611 7612 void Assembler::emit_data64(jlong data, 7613 relocInfo::relocType rtype, 7614 int format) { 7615 if (rtype == relocInfo::none) { 7616 emit_int64(data); 7617 } else { 7618 emit_data64(data, Relocation::spec_simple(rtype), format); 7619 } 7620 } 7621 7622 void Assembler::emit_data64(jlong data, 7623 RelocationHolder const& rspec, 7624 int format) { 7625 assert(imm_operand == 0, "default format must be immediate in this file"); 7626 assert(imm_operand == format, "must be immediate"); 7627 assert(inst_mark() != NULL, "must be inside InstructionMark"); 7628 // Do not use AbstractAssembler::relocate, which is not intended for 7629 // embedded words. Instead, relocate to the enclosing instruction. 7630 code_section()->relocate(inst_mark(), rspec, format); 7631 #ifdef ASSERT 7632 check_relocation(rspec, format); 7633 #endif 7634 emit_int64(data); 7635 } 7636 7637 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) { 7638 if (reg_enc >= 8) { 7639 prefix(REX_B); 7640 reg_enc -= 8; 7641 } else if (byteinst && reg_enc >= 4) { 7642 prefix(REX); 7643 } 7644 return reg_enc; 7645 } 7646 7647 int Assembler::prefixq_and_encode(int reg_enc) { 7648 if (reg_enc < 8) { 7649 prefix(REX_W); 7650 } else { 7651 prefix(REX_WB); 7652 reg_enc -= 8; 7653 } 7654 return reg_enc; 7655 } 7656 7657 int Assembler::prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte) { 7658 if (dst_enc < 8) { 7659 if (src_enc >= 8) { 7660 prefix(REX_B); 7661 src_enc -= 8; 7662 } else if ((src_is_byte && src_enc >= 4) || (dst_is_byte && dst_enc >= 4)) { 7663 prefix(REX); 7664 } 7665 } else { 7666 if (src_enc < 8) { 7667 prefix(REX_R); 7668 } else { 7669 prefix(REX_RB); 7670 src_enc -= 8; 7671 } 7672 dst_enc -= 8; 7673 } 7674 return dst_enc << 3 | src_enc; 7675 } 7676 7677 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) { 7678 if (dst_enc < 8) { 7679 if (src_enc < 8) { 7680 prefix(REX_W); 7681 } else { 7682 prefix(REX_WB); 7683 src_enc -= 8; 7684 } 7685 } else { 7686 if (src_enc < 8) { 7687 prefix(REX_WR); 7688 } else { 7689 prefix(REX_WRB); 7690 src_enc -= 8; 7691 } 7692 dst_enc -= 8; 7693 } 7694 return dst_enc << 3 | src_enc; 7695 } 7696 7697 void Assembler::prefix(Register reg) { 7698 if (reg->encoding() >= 8) { 7699 prefix(REX_B); 7700 } 7701 } 7702 7703 void Assembler::prefix(Register dst, Register src, Prefix p) { 7704 if (src->encoding() >= 8) { 7705 p = (Prefix)(p | REX_B); 7706 } 7707 if (dst->encoding() >= 8) { 7708 p = (Prefix)( p | REX_R); 7709 } 7710 if (p != Prefix_EMPTY) { 7711 // do not generate an empty prefix 7712 prefix(p); 7713 } 7714 } 7715 7716 void Assembler::prefix(Register dst, Address adr, Prefix p) { 7717 if (adr.base_needs_rex()) { 7718 if (adr.index_needs_rex()) { 7719 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X"); 7720 } else { 7721 prefix(REX_B); 7722 } 7723 } else { 7724 if (adr.index_needs_rex()) { 7725 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X"); 7726 } 7727 } 7728 if (dst->encoding() >= 8) { 7729 p = (Prefix)(p | REX_R); 7730 } 7731 if (p != Prefix_EMPTY) { 7732 // do not generate an empty prefix 7733 prefix(p); 7734 } 7735 } 7736 7737 void Assembler::prefix(Address adr) { 7738 if (adr.base_needs_rex()) { 7739 if (adr.index_needs_rex()) { 7740 prefix(REX_XB); 7741 } else { 7742 prefix(REX_B); 7743 } 7744 } else { 7745 if (adr.index_needs_rex()) { 7746 prefix(REX_X); 7747 } 7748 } 7749 } 7750 7751 void Assembler::prefixq(Address adr) { 7752 if (adr.base_needs_rex()) { 7753 if (adr.index_needs_rex()) { 7754 prefix(REX_WXB); 7755 } else { 7756 prefix(REX_WB); 7757 } 7758 } else { 7759 if (adr.index_needs_rex()) { 7760 prefix(REX_WX); 7761 } else { 7762 prefix(REX_W); 7763 } 7764 } 7765 } 7766 7767 7768 void Assembler::prefix(Address adr, Register reg, bool byteinst) { 7769 if (reg->encoding() < 8) { 7770 if (adr.base_needs_rex()) { 7771 if (adr.index_needs_rex()) { 7772 prefix(REX_XB); 7773 } else { 7774 prefix(REX_B); 7775 } 7776 } else { 7777 if (adr.index_needs_rex()) { 7778 prefix(REX_X); 7779 } else if (byteinst && reg->encoding() >= 4 ) { 7780 prefix(REX); 7781 } 7782 } 7783 } else { 7784 if (adr.base_needs_rex()) { 7785 if (adr.index_needs_rex()) { 7786 prefix(REX_RXB); 7787 } else { 7788 prefix(REX_RB); 7789 } 7790 } else { 7791 if (adr.index_needs_rex()) { 7792 prefix(REX_RX); 7793 } else { 7794 prefix(REX_R); 7795 } 7796 } 7797 } 7798 } 7799 7800 void Assembler::prefixq(Address adr, Register src) { 7801 if (src->encoding() < 8) { 7802 if (adr.base_needs_rex()) { 7803 if (adr.index_needs_rex()) { 7804 prefix(REX_WXB); 7805 } else { 7806 prefix(REX_WB); 7807 } 7808 } else { 7809 if (adr.index_needs_rex()) { 7810 prefix(REX_WX); 7811 } else { 7812 prefix(REX_W); 7813 } 7814 } 7815 } else { 7816 if (adr.base_needs_rex()) { 7817 if (adr.index_needs_rex()) { 7818 prefix(REX_WRXB); 7819 } else { 7820 prefix(REX_WRB); 7821 } 7822 } else { 7823 if (adr.index_needs_rex()) { 7824 prefix(REX_WRX); 7825 } else { 7826 prefix(REX_WR); 7827 } 7828 } 7829 } 7830 } 7831 7832 void Assembler::prefix(Address adr, XMMRegister reg) { 7833 if (reg->encoding() < 8) { 7834 if (adr.base_needs_rex()) { 7835 if (adr.index_needs_rex()) { 7836 prefix(REX_XB); 7837 } else { 7838 prefix(REX_B); 7839 } 7840 } else { 7841 if (adr.index_needs_rex()) { 7842 prefix(REX_X); 7843 } 7844 } 7845 } else { 7846 if (adr.base_needs_rex()) { 7847 if (adr.index_needs_rex()) { 7848 prefix(REX_RXB); 7849 } else { 7850 prefix(REX_RB); 7851 } 7852 } else { 7853 if (adr.index_needs_rex()) { 7854 prefix(REX_RX); 7855 } else { 7856 prefix(REX_R); 7857 } 7858 } 7859 } 7860 } 7861 7862 void Assembler::prefixq(Address adr, XMMRegister src) { 7863 if (src->encoding() < 8) { 7864 if (adr.base_needs_rex()) { 7865 if (adr.index_needs_rex()) { 7866 prefix(REX_WXB); 7867 } else { 7868 prefix(REX_WB); 7869 } 7870 } else { 7871 if (adr.index_needs_rex()) { 7872 prefix(REX_WX); 7873 } else { 7874 prefix(REX_W); 7875 } 7876 } 7877 } else { 7878 if (adr.base_needs_rex()) { 7879 if (adr.index_needs_rex()) { 7880 prefix(REX_WRXB); 7881 } else { 7882 prefix(REX_WRB); 7883 } 7884 } else { 7885 if (adr.index_needs_rex()) { 7886 prefix(REX_WRX); 7887 } else { 7888 prefix(REX_WR); 7889 } 7890 } 7891 } 7892 } 7893 7894 void Assembler::adcq(Register dst, int32_t imm32) { 7895 (void) prefixq_and_encode(dst->encoding()); 7896 emit_arith(0x81, 0xD0, dst, imm32); 7897 } 7898 7899 void Assembler::adcq(Register dst, Address src) { 7900 InstructionMark im(this); 7901 prefixq(src, dst); 7902 emit_int8(0x13); 7903 emit_operand(dst, src); 7904 } 7905 7906 void Assembler::adcq(Register dst, Register src) { 7907 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 7908 emit_arith(0x13, 0xC0, dst, src); 7909 } 7910 7911 void Assembler::addq(Address dst, int32_t imm32) { 7912 InstructionMark im(this); 7913 prefixq(dst); 7914 emit_arith_operand(0x81, rax, dst,imm32); 7915 } 7916 7917 void Assembler::addq(Address dst, Register src) { 7918 InstructionMark im(this); 7919 prefixq(dst, src); 7920 emit_int8(0x01); 7921 emit_operand(src, dst); 7922 } 7923 7924 void Assembler::addq(Register dst, int32_t imm32) { 7925 (void) prefixq_and_encode(dst->encoding()); 7926 emit_arith(0x81, 0xC0, dst, imm32); 7927 } 7928 7929 void Assembler::addq(Register dst, Address src) { 7930 InstructionMark im(this); 7931 prefixq(src, dst); 7932 emit_int8(0x03); 7933 emit_operand(dst, src); 7934 } 7935 7936 void Assembler::addq(Register dst, Register src) { 7937 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 7938 emit_arith(0x03, 0xC0, dst, src); 7939 } 7940 7941 void Assembler::adcxq(Register dst, Register src) { 7942 //assert(VM_Version::supports_adx(), "adx instructions not supported"); 7943 emit_int8((unsigned char)0x66); 7944 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 7945 emit_int8(0x0F); 7946 emit_int8(0x38); 7947 emit_int8((unsigned char)0xF6); 7948 emit_int8((unsigned char)(0xC0 | encode)); 7949 } 7950 7951 void Assembler::adoxq(Register dst, Register src) { 7952 //assert(VM_Version::supports_adx(), "adx instructions not supported"); 7953 emit_int8((unsigned char)0xF3); 7954 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 7955 emit_int8(0x0F); 7956 emit_int8(0x38); 7957 emit_int8((unsigned char)0xF6); 7958 emit_int8((unsigned char)(0xC0 | encode)); 7959 } 7960 7961 void Assembler::andq(Address dst, int32_t imm32) { 7962 InstructionMark im(this); 7963 prefixq(dst); 7964 emit_int8((unsigned char)0x81); 7965 emit_operand(rsp, dst, 4); 7966 emit_int32(imm32); 7967 } 7968 7969 void Assembler::andq(Register dst, int32_t imm32) { 7970 (void) prefixq_and_encode(dst->encoding()); 7971 emit_arith(0x81, 0xE0, dst, imm32); 7972 } 7973 7974 void Assembler::andq(Register dst, Address src) { 7975 InstructionMark im(this); 7976 prefixq(src, dst); 7977 emit_int8(0x23); 7978 emit_operand(dst, src); 7979 } 7980 7981 void Assembler::andq(Register dst, Register src) { 7982 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 7983 emit_arith(0x23, 0xC0, dst, src); 7984 } 7985 7986 void Assembler::andnq(Register dst, Register src1, Register src2) { 7987 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 7988 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 7989 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 7990 emit_int8((unsigned char)0xF2); 7991 emit_int8((unsigned char)(0xC0 | encode)); 7992 } 7993 7994 void Assembler::andnq(Register dst, Register src1, Address src2) { 7995 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 7996 InstructionMark im(this); 7997 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 7998 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 7999 emit_int8((unsigned char)0xF2); 8000 emit_operand(dst, src2); 8001 } 8002 8003 void Assembler::bsfq(Register dst, Register src) { 8004 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 8005 emit_int8(0x0F); 8006 emit_int8((unsigned char)0xBC); 8007 emit_int8((unsigned char)(0xC0 | encode)); 8008 } 8009 8010 void Assembler::bsrq(Register dst, Register src) { 8011 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 8012 emit_int8(0x0F); 8013 emit_int8((unsigned char)0xBD); 8014 emit_int8((unsigned char)(0xC0 | encode)); 8015 } 8016 8017 void Assembler::bswapq(Register reg) { 8018 int encode = prefixq_and_encode(reg->encoding()); 8019 emit_int8(0x0F); 8020 emit_int8((unsigned char)(0xC8 | encode)); 8021 } 8022 8023 void Assembler::blsiq(Register dst, Register src) { 8024 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 8025 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 8026 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 8027 emit_int8((unsigned char)0xF3); 8028 emit_int8((unsigned char)(0xC0 | encode)); 8029 } 8030 8031 void Assembler::blsiq(Register dst, Address src) { 8032 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 8033 InstructionMark im(this); 8034 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 8035 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 8036 emit_int8((unsigned char)0xF3); 8037 emit_operand(rbx, src); 8038 } 8039 8040 void Assembler::blsmskq(Register dst, Register src) { 8041 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 8042 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 8043 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 8044 emit_int8((unsigned char)0xF3); 8045 emit_int8((unsigned char)(0xC0 | encode)); 8046 } 8047 8048 void Assembler::blsmskq(Register dst, Address src) { 8049 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 8050 InstructionMark im(this); 8051 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 8052 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 8053 emit_int8((unsigned char)0xF3); 8054 emit_operand(rdx, src); 8055 } 8056 8057 void Assembler::blsrq(Register dst, Register src) { 8058 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 8059 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 8060 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 8061 emit_int8((unsigned char)0xF3); 8062 emit_int8((unsigned char)(0xC0 | encode)); 8063 } 8064 8065 void Assembler::blsrq(Register dst, Address src) { 8066 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 8067 InstructionMark im(this); 8068 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 8069 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 8070 emit_int8((unsigned char)0xF3); 8071 emit_operand(rcx, src); 8072 } 8073 8074 void Assembler::cdqq() { 8075 prefix(REX_W); 8076 emit_int8((unsigned char)0x99); 8077 } 8078 8079 void Assembler::clflush(Address adr) { 8080 prefix(adr); 8081 emit_int8(0x0F); 8082 emit_int8((unsigned char)0xAE); 8083 emit_operand(rdi, adr); 8084 } 8085 8086 void Assembler::cmovq(Condition cc, Register dst, Register src) { 8087 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 8088 emit_int8(0x0F); 8089 emit_int8(0x40 | cc); 8090 emit_int8((unsigned char)(0xC0 | encode)); 8091 } 8092 8093 void Assembler::cmovq(Condition cc, Register dst, Address src) { 8094 InstructionMark im(this); 8095 prefixq(src, dst); 8096 emit_int8(0x0F); 8097 emit_int8(0x40 | cc); 8098 emit_operand(dst, src); 8099 } 8100 8101 void Assembler::cmpq(Address dst, int32_t imm32) { 8102 InstructionMark im(this); 8103 prefixq(dst); 8104 emit_int8((unsigned char)0x81); 8105 emit_operand(rdi, dst, 4); 8106 emit_int32(imm32); 8107 } 8108 8109 void Assembler::cmpq(Register dst, int32_t imm32) { 8110 (void) prefixq_and_encode(dst->encoding()); 8111 emit_arith(0x81, 0xF8, dst, imm32); 8112 } 8113 8114 void Assembler::cmpq(Address dst, Register src) { 8115 InstructionMark im(this); 8116 prefixq(dst, src); 8117 emit_int8(0x3B); 8118 emit_operand(src, dst); 8119 } 8120 8121 void Assembler::cmpq(Register dst, Register src) { 8122 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 8123 emit_arith(0x3B, 0xC0, dst, src); 8124 } 8125 8126 void Assembler::cmpq(Register dst, Address src) { 8127 InstructionMark im(this); 8128 prefixq(src, dst); 8129 emit_int8(0x3B); 8130 emit_operand(dst, src); 8131 } 8132 8133 void Assembler::cmpxchgq(Register reg, Address adr) { 8134 InstructionMark im(this); 8135 prefixq(adr, reg); 8136 emit_int8(0x0F); 8137 emit_int8((unsigned char)0xB1); 8138 emit_operand(reg, adr); 8139 } 8140 8141 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) { 8142 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 8143 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 8144 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 8145 emit_int8(0x2A); 8146 emit_int8((unsigned char)(0xC0 | encode)); 8147 } 8148 8149 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) { 8150 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 8151 InstructionMark im(this); 8152 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 8153 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 8154 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 8155 emit_int8(0x2A); 8156 emit_operand(dst, src); 8157 } 8158 8159 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) { 8160 NOT_LP64(assert(VM_Version::supports_sse(), "")); 8161 InstructionMark im(this); 8162 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 8163 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 8164 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 8165 emit_int8(0x2A); 8166 emit_operand(dst, src); 8167 } 8168 8169 void Assembler::cvttsd2siq(Register dst, XMMRegister src) { 8170 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 8171 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 8172 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 8173 emit_int8(0x2C); 8174 emit_int8((unsigned char)(0xC0 | encode)); 8175 } 8176 8177 void Assembler::cvttss2siq(Register dst, XMMRegister src) { 8178 NOT_LP64(assert(VM_Version::supports_sse(), "")); 8179 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 8180 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 8181 emit_int8(0x2C); 8182 emit_int8((unsigned char)(0xC0 | encode)); 8183 } 8184 8185 void Assembler::decl(Register dst) { 8186 // Don't use it directly. Use MacroAssembler::decrementl() instead. 8187 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode) 8188 int encode = prefix_and_encode(dst->encoding()); 8189 emit_int8((unsigned char)0xFF); 8190 emit_int8((unsigned char)(0xC8 | encode)); 8191 } 8192 8193 void Assembler::decq(Register dst) { 8194 // Don't use it directly. Use MacroAssembler::decrementq() instead. 8195 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) 8196 int encode = prefixq_and_encode(dst->encoding()); 8197 emit_int8((unsigned char)0xFF); 8198 emit_int8(0xC8 | encode); 8199 } 8200 8201 void Assembler::decq(Address dst) { 8202 // Don't use it directly. Use MacroAssembler::decrementq() instead. 8203 InstructionMark im(this); 8204 prefixq(dst); 8205 emit_int8((unsigned char)0xFF); 8206 emit_operand(rcx, dst); 8207 } 8208 8209 void Assembler::fxrstor(Address src) { 8210 prefixq(src); 8211 emit_int8(0x0F); 8212 emit_int8((unsigned char)0xAE); 8213 emit_operand(as_Register(1), src); 8214 } 8215 8216 void Assembler::xrstor(Address src) { 8217 prefixq(src); 8218 emit_int8(0x0F); 8219 emit_int8((unsigned char)0xAE); 8220 emit_operand(as_Register(5), src); 8221 } 8222 8223 void Assembler::fxsave(Address dst) { 8224 prefixq(dst); 8225 emit_int8(0x0F); 8226 emit_int8((unsigned char)0xAE); 8227 emit_operand(as_Register(0), dst); 8228 } 8229 8230 void Assembler::xsave(Address dst) { 8231 prefixq(dst); 8232 emit_int8(0x0F); 8233 emit_int8((unsigned char)0xAE); 8234 emit_operand(as_Register(4), dst); 8235 } 8236 8237 void Assembler::idivq(Register src) { 8238 int encode = prefixq_and_encode(src->encoding()); 8239 emit_int8((unsigned char)0xF7); 8240 emit_int8((unsigned char)(0xF8 | encode)); 8241 } 8242 8243 void Assembler::imulq(Register dst, Register src) { 8244 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 8245 emit_int8(0x0F); 8246 emit_int8((unsigned char)0xAF); 8247 emit_int8((unsigned char)(0xC0 | encode)); 8248 } 8249 8250 void Assembler::imulq(Register dst, Register src, int value) { 8251 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 8252 if (is8bit(value)) { 8253 emit_int8(0x6B); 8254 emit_int8((unsigned char)(0xC0 | encode)); 8255 emit_int8(value & 0xFF); 8256 } else { 8257 emit_int8(0x69); 8258 emit_int8((unsigned char)(0xC0 | encode)); 8259 emit_int32(value); 8260 } 8261 } 8262 8263 void Assembler::imulq(Register dst, Address src) { 8264 InstructionMark im(this); 8265 prefixq(src, dst); 8266 emit_int8(0x0F); 8267 emit_int8((unsigned char) 0xAF); 8268 emit_operand(dst, src); 8269 } 8270 8271 void Assembler::incl(Register dst) { 8272 // Don't use it directly. Use MacroAssembler::incrementl() instead. 8273 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) 8274 int encode = prefix_and_encode(dst->encoding()); 8275 emit_int8((unsigned char)0xFF); 8276 emit_int8((unsigned char)(0xC0 | encode)); 8277 } 8278 8279 void Assembler::incq(Register dst) { 8280 // Don't use it directly. Use MacroAssembler::incrementq() instead. 8281 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) 8282 int encode = prefixq_and_encode(dst->encoding()); 8283 emit_int8((unsigned char)0xFF); 8284 emit_int8((unsigned char)(0xC0 | encode)); 8285 } 8286 8287 void Assembler::incq(Address dst) { 8288 // Don't use it directly. Use MacroAssembler::incrementq() instead. 8289 InstructionMark im(this); 8290 prefixq(dst); 8291 emit_int8((unsigned char)0xFF); 8292 emit_operand(rax, dst); 8293 } 8294 8295 void Assembler::lea(Register dst, Address src) { 8296 leaq(dst, src); 8297 } 8298 8299 void Assembler::leaq(Register dst, Address src) { 8300 InstructionMark im(this); 8301 prefixq(src, dst); 8302 emit_int8((unsigned char)0x8D); 8303 emit_operand(dst, src); 8304 } 8305 8306 void Assembler::mov64(Register dst, int64_t imm64) { 8307 InstructionMark im(this); 8308 int encode = prefixq_and_encode(dst->encoding()); 8309 emit_int8((unsigned char)(0xB8 | encode)); 8310 emit_int64(imm64); 8311 } 8312 8313 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) { 8314 InstructionMark im(this); 8315 int encode = prefixq_and_encode(dst->encoding()); 8316 emit_int8(0xB8 | encode); 8317 emit_data64(imm64, rspec); 8318 } 8319 8320 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) { 8321 InstructionMark im(this); 8322 int encode = prefix_and_encode(dst->encoding()); 8323 emit_int8((unsigned char)(0xB8 | encode)); 8324 emit_data((int)imm32, rspec, narrow_oop_operand); 8325 } 8326 8327 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) { 8328 InstructionMark im(this); 8329 prefix(dst); 8330 emit_int8((unsigned char)0xC7); 8331 emit_operand(rax, dst, 4); 8332 emit_data((int)imm32, rspec, narrow_oop_operand); 8333 } 8334 8335 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) { 8336 InstructionMark im(this); 8337 int encode = prefix_and_encode(src1->encoding()); 8338 emit_int8((unsigned char)0x81); 8339 emit_int8((unsigned char)(0xF8 | encode)); 8340 emit_data((int)imm32, rspec, narrow_oop_operand); 8341 } 8342 8343 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) { 8344 InstructionMark im(this); 8345 prefix(src1); 8346 emit_int8((unsigned char)0x81); 8347 emit_operand(rax, src1, 4); 8348 emit_data((int)imm32, rspec, narrow_oop_operand); 8349 } 8350 8351 void Assembler::lzcntq(Register dst, Register src) { 8352 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR"); 8353 emit_int8((unsigned char)0xF3); 8354 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 8355 emit_int8(0x0F); 8356 emit_int8((unsigned char)0xBD); 8357 emit_int8((unsigned char)(0xC0 | encode)); 8358 } 8359 8360 void Assembler::movdq(XMMRegister dst, Register src) { 8361 // table D-1 says MMX/SSE2 8362 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 8363 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 8364 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 8365 emit_int8(0x6E); 8366 emit_int8((unsigned char)(0xC0 | encode)); 8367 } 8368 8369 void Assembler::movdq(Register dst, XMMRegister src) { 8370 // table D-1 says MMX/SSE2 8371 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 8372 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 8373 // swap src/dst to get correct prefix 8374 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 8375 emit_int8(0x7E); 8376 emit_int8((unsigned char)(0xC0 | encode)); 8377 } 8378 8379 void Assembler::movq(Register dst, Register src) { 8380 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 8381 emit_int8((unsigned char)0x8B); 8382 emit_int8((unsigned char)(0xC0 | encode)); 8383 } 8384 8385 void Assembler::movq(Register dst, Address src) { 8386 InstructionMark im(this); 8387 prefixq(src, dst); 8388 emit_int8((unsigned char)0x8B); 8389 emit_operand(dst, src); 8390 } 8391 8392 void Assembler::movq(Address dst, Register src) { 8393 InstructionMark im(this); 8394 prefixq(dst, src); 8395 emit_int8((unsigned char)0x89); 8396 emit_operand(src, dst); 8397 } 8398 8399 void Assembler::movsbq(Register dst, Address src) { 8400 InstructionMark im(this); 8401 prefixq(src, dst); 8402 emit_int8(0x0F); 8403 emit_int8((unsigned char)0xBE); 8404 emit_operand(dst, src); 8405 } 8406 8407 void Assembler::movsbq(Register dst, Register src) { 8408 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 8409 emit_int8(0x0F); 8410 emit_int8((unsigned char)0xBE); 8411 emit_int8((unsigned char)(0xC0 | encode)); 8412 } 8413 8414 void Assembler::movslq(Register dst, int32_t imm32) { 8415 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx) 8416 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx) 8417 // as a result we shouldn't use until tested at runtime... 8418 ShouldNotReachHere(); 8419 InstructionMark im(this); 8420 int encode = prefixq_and_encode(dst->encoding()); 8421 emit_int8((unsigned char)(0xC7 | encode)); 8422 emit_int32(imm32); 8423 } 8424 8425 void Assembler::movslq(Address dst, int32_t imm32) { 8426 assert(is_simm32(imm32), "lost bits"); 8427 InstructionMark im(this); 8428 prefixq(dst); 8429 emit_int8((unsigned char)0xC7); 8430 emit_operand(rax, dst, 4); 8431 emit_int32(imm32); 8432 } 8433 8434 void Assembler::movslq(Register dst, Address src) { 8435 InstructionMark im(this); 8436 prefixq(src, dst); 8437 emit_int8(0x63); 8438 emit_operand(dst, src); 8439 } 8440 8441 void Assembler::movslq(Register dst, Register src) { 8442 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 8443 emit_int8(0x63); 8444 emit_int8((unsigned char)(0xC0 | encode)); 8445 } 8446 8447 void Assembler::movswq(Register dst, Address src) { 8448 InstructionMark im(this); 8449 prefixq(src, dst); 8450 emit_int8(0x0F); 8451 emit_int8((unsigned char)0xBF); 8452 emit_operand(dst, src); 8453 } 8454 8455 void Assembler::movswq(Register dst, Register src) { 8456 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 8457 emit_int8((unsigned char)0x0F); 8458 emit_int8((unsigned char)0xBF); 8459 emit_int8((unsigned char)(0xC0 | encode)); 8460 } 8461 8462 void Assembler::movzbq(Register dst, Address src) { 8463 InstructionMark im(this); 8464 prefixq(src, dst); 8465 emit_int8((unsigned char)0x0F); 8466 emit_int8((unsigned char)0xB6); 8467 emit_operand(dst, src); 8468 } 8469 8470 void Assembler::movzbq(Register dst, Register src) { 8471 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 8472 emit_int8(0x0F); 8473 emit_int8((unsigned char)0xB6); 8474 emit_int8(0xC0 | encode); 8475 } 8476 8477 void Assembler::movzwq(Register dst, Address src) { 8478 InstructionMark im(this); 8479 prefixq(src, dst); 8480 emit_int8((unsigned char)0x0F); 8481 emit_int8((unsigned char)0xB7); 8482 emit_operand(dst, src); 8483 } 8484 8485 void Assembler::movzwq(Register dst, Register src) { 8486 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 8487 emit_int8((unsigned char)0x0F); 8488 emit_int8((unsigned char)0xB7); 8489 emit_int8((unsigned char)(0xC0 | encode)); 8490 } 8491 8492 void Assembler::mulq(Address src) { 8493 InstructionMark im(this); 8494 prefixq(src); 8495 emit_int8((unsigned char)0xF7); 8496 emit_operand(rsp, src); 8497 } 8498 8499 void Assembler::mulq(Register src) { 8500 int encode = prefixq_and_encode(src->encoding()); 8501 emit_int8((unsigned char)0xF7); 8502 emit_int8((unsigned char)(0xE0 | encode)); 8503 } 8504 8505 void Assembler::mulxq(Register dst1, Register dst2, Register src) { 8506 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported"); 8507 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 8508 int encode = vex_prefix_and_encode(dst1->encoding(), dst2->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes); 8509 emit_int8((unsigned char)0xF6); 8510 emit_int8((unsigned char)(0xC0 | encode)); 8511 } 8512 8513 void Assembler::negq(Register dst) { 8514 int encode = prefixq_and_encode(dst->encoding()); 8515 emit_int8((unsigned char)0xF7); 8516 emit_int8((unsigned char)(0xD8 | encode)); 8517 } 8518 8519 void Assembler::notq(Register dst) { 8520 int encode = prefixq_and_encode(dst->encoding()); 8521 emit_int8((unsigned char)0xF7); 8522 emit_int8((unsigned char)(0xD0 | encode)); 8523 } 8524 8525 void Assembler::orq(Address dst, int32_t imm32) { 8526 InstructionMark im(this); 8527 prefixq(dst); 8528 emit_int8((unsigned char)0x81); 8529 emit_operand(rcx, dst, 4); 8530 emit_int32(imm32); 8531 } 8532 8533 void Assembler::orq(Register dst, int32_t imm32) { 8534 (void) prefixq_and_encode(dst->encoding()); 8535 emit_arith(0x81, 0xC8, dst, imm32); 8536 } 8537 8538 void Assembler::orq(Register dst, Address src) { 8539 InstructionMark im(this); 8540 prefixq(src, dst); 8541 emit_int8(0x0B); 8542 emit_operand(dst, src); 8543 } 8544 8545 void Assembler::orq(Register dst, Register src) { 8546 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 8547 emit_arith(0x0B, 0xC0, dst, src); 8548 } 8549 8550 void Assembler::popa() { // 64bit 8551 movq(r15, Address(rsp, 0)); 8552 movq(r14, Address(rsp, wordSize)); 8553 movq(r13, Address(rsp, 2 * wordSize)); 8554 movq(r12, Address(rsp, 3 * wordSize)); 8555 movq(r11, Address(rsp, 4 * wordSize)); 8556 movq(r10, Address(rsp, 5 * wordSize)); 8557 movq(r9, Address(rsp, 6 * wordSize)); 8558 movq(r8, Address(rsp, 7 * wordSize)); 8559 movq(rdi, Address(rsp, 8 * wordSize)); 8560 movq(rsi, Address(rsp, 9 * wordSize)); 8561 movq(rbp, Address(rsp, 10 * wordSize)); 8562 // skip rsp 8563 movq(rbx, Address(rsp, 12 * wordSize)); 8564 movq(rdx, Address(rsp, 13 * wordSize)); 8565 movq(rcx, Address(rsp, 14 * wordSize)); 8566 movq(rax, Address(rsp, 15 * wordSize)); 8567 8568 addq(rsp, 16 * wordSize); 8569 } 8570 8571 void Assembler::popcntq(Register dst, Address src) { 8572 assert(VM_Version::supports_popcnt(), "must support"); 8573 InstructionMark im(this); 8574 emit_int8((unsigned char)0xF3); 8575 prefixq(src, dst); 8576 emit_int8((unsigned char)0x0F); 8577 emit_int8((unsigned char)0xB8); 8578 emit_operand(dst, src); 8579 } 8580 8581 void Assembler::popcntq(Register dst, Register src) { 8582 assert(VM_Version::supports_popcnt(), "must support"); 8583 emit_int8((unsigned char)0xF3); 8584 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 8585 emit_int8((unsigned char)0x0F); 8586 emit_int8((unsigned char)0xB8); 8587 emit_int8((unsigned char)(0xC0 | encode)); 8588 } 8589 8590 void Assembler::popq(Address dst) { 8591 InstructionMark im(this); 8592 prefixq(dst); 8593 emit_int8((unsigned char)0x8F); 8594 emit_operand(rax, dst); 8595 } 8596 8597 void Assembler::pusha() { // 64bit 8598 // we have to store original rsp. ABI says that 128 bytes 8599 // below rsp are local scratch. 8600 movq(Address(rsp, -5 * wordSize), rsp); 8601 8602 subq(rsp, 16 * wordSize); 8603 8604 movq(Address(rsp, 15 * wordSize), rax); 8605 movq(Address(rsp, 14 * wordSize), rcx); 8606 movq(Address(rsp, 13 * wordSize), rdx); 8607 movq(Address(rsp, 12 * wordSize), rbx); 8608 // skip rsp 8609 movq(Address(rsp, 10 * wordSize), rbp); 8610 movq(Address(rsp, 9 * wordSize), rsi); 8611 movq(Address(rsp, 8 * wordSize), rdi); 8612 movq(Address(rsp, 7 * wordSize), r8); 8613 movq(Address(rsp, 6 * wordSize), r9); 8614 movq(Address(rsp, 5 * wordSize), r10); 8615 movq(Address(rsp, 4 * wordSize), r11); 8616 movq(Address(rsp, 3 * wordSize), r12); 8617 movq(Address(rsp, 2 * wordSize), r13); 8618 movq(Address(rsp, wordSize), r14); 8619 movq(Address(rsp, 0), r15); 8620 } 8621 8622 void Assembler::pushq(Address src) { 8623 InstructionMark im(this); 8624 prefixq(src); 8625 emit_int8((unsigned char)0xFF); 8626 emit_operand(rsi, src); 8627 } 8628 8629 void Assembler::rclq(Register dst, int imm8) { 8630 assert(isShiftCount(imm8 >> 1), "illegal shift count"); 8631 int encode = prefixq_and_encode(dst->encoding()); 8632 if (imm8 == 1) { 8633 emit_int8((unsigned char)0xD1); 8634 emit_int8((unsigned char)(0xD0 | encode)); 8635 } else { 8636 emit_int8((unsigned char)0xC1); 8637 emit_int8((unsigned char)(0xD0 | encode)); 8638 emit_int8(imm8); 8639 } 8640 } 8641 8642 void Assembler::rcrq(Register dst, int imm8) { 8643 assert(isShiftCount(imm8 >> 1), "illegal shift count"); 8644 int encode = prefixq_and_encode(dst->encoding()); 8645 if (imm8 == 1) { 8646 emit_int8((unsigned char)0xD1); 8647 emit_int8((unsigned char)(0xD8 | encode)); 8648 } else { 8649 emit_int8((unsigned char)0xC1); 8650 emit_int8((unsigned char)(0xD8 | encode)); 8651 emit_int8(imm8); 8652 } 8653 } 8654 8655 void Assembler::rorq(Register dst, int imm8) { 8656 assert(isShiftCount(imm8 >> 1), "illegal shift count"); 8657 int encode = prefixq_and_encode(dst->encoding()); 8658 if (imm8 == 1) { 8659 emit_int8((unsigned char)0xD1); 8660 emit_int8((unsigned char)(0xC8 | encode)); 8661 } else { 8662 emit_int8((unsigned char)0xC1); 8663 emit_int8((unsigned char)(0xc8 | encode)); 8664 emit_int8(imm8); 8665 } 8666 } 8667 8668 void Assembler::rorxq(Register dst, Register src, int imm8) { 8669 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported"); 8670 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 8671 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes); 8672 emit_int8((unsigned char)0xF0); 8673 emit_int8((unsigned char)(0xC0 | encode)); 8674 emit_int8(imm8); 8675 } 8676 8677 void Assembler::rorxd(Register dst, Register src, int imm8) { 8678 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported"); 8679 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 8680 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes); 8681 emit_int8((unsigned char)0xF0); 8682 emit_int8((unsigned char)(0xC0 | encode)); 8683 emit_int8(imm8); 8684 } 8685 8686 void Assembler::sarq(Register dst, int imm8) { 8687 assert(isShiftCount(imm8 >> 1), "illegal shift count"); 8688 int encode = prefixq_and_encode(dst->encoding()); 8689 if (imm8 == 1) { 8690 emit_int8((unsigned char)0xD1); 8691 emit_int8((unsigned char)(0xF8 | encode)); 8692 } else { 8693 emit_int8((unsigned char)0xC1); 8694 emit_int8((unsigned char)(0xF8 | encode)); 8695 emit_int8(imm8); 8696 } 8697 } 8698 8699 void Assembler::sarq(Register dst) { 8700 int encode = prefixq_and_encode(dst->encoding()); 8701 emit_int8((unsigned char)0xD3); 8702 emit_int8((unsigned char)(0xF8 | encode)); 8703 } 8704 8705 void Assembler::sbbq(Address dst, int32_t imm32) { 8706 InstructionMark im(this); 8707 prefixq(dst); 8708 emit_arith_operand(0x81, rbx, dst, imm32); 8709 } 8710 8711 void Assembler::sbbq(Register dst, int32_t imm32) { 8712 (void) prefixq_and_encode(dst->encoding()); 8713 emit_arith(0x81, 0xD8, dst, imm32); 8714 } 8715 8716 void Assembler::sbbq(Register dst, Address src) { 8717 InstructionMark im(this); 8718 prefixq(src, dst); 8719 emit_int8(0x1B); 8720 emit_operand(dst, src); 8721 } 8722 8723 void Assembler::sbbq(Register dst, Register src) { 8724 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 8725 emit_arith(0x1B, 0xC0, dst, src); 8726 } 8727 8728 void Assembler::shlq(Register dst, int imm8) { 8729 assert(isShiftCount(imm8 >> 1), "illegal shift count"); 8730 int encode = prefixq_and_encode(dst->encoding()); 8731 if (imm8 == 1) { 8732 emit_int8((unsigned char)0xD1); 8733 emit_int8((unsigned char)(0xE0 | encode)); 8734 } else { 8735 emit_int8((unsigned char)0xC1); 8736 emit_int8((unsigned char)(0xE0 | encode)); 8737 emit_int8(imm8); 8738 } 8739 } 8740 8741 void Assembler::shlq(Register dst) { 8742 int encode = prefixq_and_encode(dst->encoding()); 8743 emit_int8((unsigned char)0xD3); 8744 emit_int8((unsigned char)(0xE0 | encode)); 8745 } 8746 8747 void Assembler::shrq(Register dst, int imm8) { 8748 assert(isShiftCount(imm8 >> 1), "illegal shift count"); 8749 int encode = prefixq_and_encode(dst->encoding()); 8750 emit_int8((unsigned char)0xC1); 8751 emit_int8((unsigned char)(0xE8 | encode)); 8752 emit_int8(imm8); 8753 } 8754 8755 void Assembler::shrq(Register dst) { 8756 int encode = prefixq_and_encode(dst->encoding()); 8757 emit_int8((unsigned char)0xD3); 8758 emit_int8(0xE8 | encode); 8759 } 8760 8761 void Assembler::subq(Address dst, int32_t imm32) { 8762 InstructionMark im(this); 8763 prefixq(dst); 8764 emit_arith_operand(0x81, rbp, dst, imm32); 8765 } 8766 8767 void Assembler::subq(Address dst, Register src) { 8768 InstructionMark im(this); 8769 prefixq(dst, src); 8770 emit_int8(0x29); 8771 emit_operand(src, dst); 8772 } 8773 8774 void Assembler::subq(Register dst, int32_t imm32) { 8775 (void) prefixq_and_encode(dst->encoding()); 8776 emit_arith(0x81, 0xE8, dst, imm32); 8777 } 8778 8779 // Force generation of a 4 byte immediate value even if it fits into 8bit 8780 void Assembler::subq_imm32(Register dst, int32_t imm32) { 8781 (void) prefixq_and_encode(dst->encoding()); 8782 emit_arith_imm32(0x81, 0xE8, dst, imm32); 8783 } 8784 8785 void Assembler::subq(Register dst, Address src) { 8786 InstructionMark im(this); 8787 prefixq(src, dst); 8788 emit_int8(0x2B); 8789 emit_operand(dst, src); 8790 } 8791 8792 void Assembler::subq(Register dst, Register src) { 8793 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 8794 emit_arith(0x2B, 0xC0, dst, src); 8795 } 8796 8797 void Assembler::testq(Register dst, int32_t imm32) { 8798 // not using emit_arith because test 8799 // doesn't support sign-extension of 8800 // 8bit operands 8801 int encode = dst->encoding(); 8802 if (encode == 0) { 8803 prefix(REX_W); 8804 emit_int8((unsigned char)0xA9); 8805 } else { 8806 encode = prefixq_and_encode(encode); 8807 emit_int8((unsigned char)0xF7); 8808 emit_int8((unsigned char)(0xC0 | encode)); 8809 } 8810 emit_int32(imm32); 8811 } 8812 8813 void Assembler::testq(Register dst, Register src) { 8814 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 8815 emit_arith(0x85, 0xC0, dst, src); 8816 } 8817 8818 void Assembler::xaddq(Address dst, Register src) { 8819 InstructionMark im(this); 8820 prefixq(dst, src); 8821 emit_int8(0x0F); 8822 emit_int8((unsigned char)0xC1); 8823 emit_operand(src, dst); 8824 } 8825 8826 void Assembler::xchgq(Register dst, Address src) { 8827 InstructionMark im(this); 8828 prefixq(src, dst); 8829 emit_int8((unsigned char)0x87); 8830 emit_operand(dst, src); 8831 } 8832 8833 void Assembler::xchgq(Register dst, Register src) { 8834 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 8835 emit_int8((unsigned char)0x87); 8836 emit_int8((unsigned char)(0xc0 | encode)); 8837 } 8838 8839 void Assembler::xorq(Register dst, Register src) { 8840 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 8841 emit_arith(0x33, 0xC0, dst, src); 8842 } 8843 8844 void Assembler::xorq(Register dst, Address src) { 8845 InstructionMark im(this); 8846 prefixq(src, dst); 8847 emit_int8(0x33); 8848 emit_operand(dst, src); 8849 } 8850 8851 #endif // !LP64