1 /* 2 * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "jvm.h" 27 #include "asm/assembler.hpp" 28 #include "asm/assembler.inline.hpp" 29 #include "compiler/disassembler.hpp" 30 #include "gc/shared/cardTableModRefBS.hpp" 31 #include "gc/shared/collectedHeap.inline.hpp" 32 #include "interpreter/interpreter.hpp" 33 #include "memory/resourceArea.hpp" 34 #include "memory/universe.hpp" 35 #include "oops/klass.inline.hpp" 36 #include "prims/methodHandles.hpp" 37 #include "runtime/biasedLocking.hpp" 38 #include "runtime/interfaceSupport.hpp" 39 #include "runtime/objectMonitor.hpp" 40 #include "runtime/os.hpp" 41 #include "runtime/sharedRuntime.hpp" 42 #include "runtime/stubRoutines.hpp" 43 #include "runtime/thread.hpp" 44 #include "utilities/macros.hpp" 45 #if INCLUDE_ALL_GCS 46 #include "gc/g1/g1CollectedHeap.inline.hpp" 47 #include "gc/g1/g1SATBCardTableModRefBS.hpp" 48 #include "gc/g1/heapRegion.hpp" 49 #endif // INCLUDE_ALL_GCS 50 #include "crc32c.h" 51 #ifdef COMPILER2 52 #include "opto/intrinsicnode.hpp" 53 #endif 54 55 #ifdef PRODUCT 56 #define BLOCK_COMMENT(str) /* nothing */ 57 #define STOP(error) stop(error) 58 #else 59 #define BLOCK_COMMENT(str) block_comment(str) 60 #define STOP(error) block_comment(error); stop(error) 61 #endif 62 63 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":") 64 65 #ifdef ASSERT 66 bool AbstractAssembler::pd_check_instruction_mark() { return true; } 67 #endif 68 69 static Assembler::Condition reverse[] = { 70 Assembler::noOverflow /* overflow = 0x0 */ , 71 Assembler::overflow /* noOverflow = 0x1 */ , 72 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ , 73 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ , 74 Assembler::notZero /* zero = 0x4, equal = 0x4 */ , 75 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ , 76 Assembler::above /* belowEqual = 0x6 */ , 77 Assembler::belowEqual /* above = 0x7 */ , 78 Assembler::positive /* negative = 0x8 */ , 79 Assembler::negative /* positive = 0x9 */ , 80 Assembler::noParity /* parity = 0xa */ , 81 Assembler::parity /* noParity = 0xb */ , 82 Assembler::greaterEqual /* less = 0xc */ , 83 Assembler::less /* greaterEqual = 0xd */ , 84 Assembler::greater /* lessEqual = 0xe */ , 85 Assembler::lessEqual /* greater = 0xf, */ 86 87 }; 88 89 90 // Implementation of MacroAssembler 91 92 // First all the versions that have distinct versions depending on 32/64 bit 93 // Unless the difference is trivial (1 line or so). 94 95 #ifndef _LP64 96 97 // 32bit versions 98 99 Address MacroAssembler::as_Address(AddressLiteral adr) { 100 return Address(adr.target(), adr.rspec()); 101 } 102 103 Address MacroAssembler::as_Address(ArrayAddress adr) { 104 return Address::make_array(adr); 105 } 106 107 void MacroAssembler::call_VM_leaf_base(address entry_point, 108 int number_of_arguments) { 109 call(RuntimeAddress(entry_point)); 110 increment(rsp, number_of_arguments * wordSize); 111 } 112 113 void MacroAssembler::cmpklass(Address src1, Metadata* obj) { 114 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate()); 115 } 116 117 void MacroAssembler::cmpklass(Register src1, Metadata* obj) { 118 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate()); 119 } 120 121 void MacroAssembler::cmpoop(Address src1, jobject obj) { 122 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate()); 123 } 124 125 void MacroAssembler::cmpoop(Register src1, jobject obj) { 126 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate()); 127 } 128 129 void MacroAssembler::extend_sign(Register hi, Register lo) { 130 // According to Intel Doc. AP-526, "Integer Divide", p.18. 131 if (VM_Version::is_P6() && hi == rdx && lo == rax) { 132 cdql(); 133 } else { 134 movl(hi, lo); 135 sarl(hi, 31); 136 } 137 } 138 139 void MacroAssembler::jC2(Register tmp, Label& L) { 140 // set parity bit if FPU flag C2 is set (via rax) 141 save_rax(tmp); 142 fwait(); fnstsw_ax(); 143 sahf(); 144 restore_rax(tmp); 145 // branch 146 jcc(Assembler::parity, L); 147 } 148 149 void MacroAssembler::jnC2(Register tmp, Label& L) { 150 // set parity bit if FPU flag C2 is set (via rax) 151 save_rax(tmp); 152 fwait(); fnstsw_ax(); 153 sahf(); 154 restore_rax(tmp); 155 // branch 156 jcc(Assembler::noParity, L); 157 } 158 159 // 32bit can do a case table jump in one instruction but we no longer allow the base 160 // to be installed in the Address class 161 void MacroAssembler::jump(ArrayAddress entry) { 162 jmp(as_Address(entry)); 163 } 164 165 // Note: y_lo will be destroyed 166 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) { 167 // Long compare for Java (semantics as described in JVM spec.) 168 Label high, low, done; 169 170 cmpl(x_hi, y_hi); 171 jcc(Assembler::less, low); 172 jcc(Assembler::greater, high); 173 // x_hi is the return register 174 xorl(x_hi, x_hi); 175 cmpl(x_lo, y_lo); 176 jcc(Assembler::below, low); 177 jcc(Assembler::equal, done); 178 179 bind(high); 180 xorl(x_hi, x_hi); 181 increment(x_hi); 182 jmp(done); 183 184 bind(low); 185 xorl(x_hi, x_hi); 186 decrementl(x_hi); 187 188 bind(done); 189 } 190 191 void MacroAssembler::lea(Register dst, AddressLiteral src) { 192 mov_literal32(dst, (int32_t)src.target(), src.rspec()); 193 } 194 195 void MacroAssembler::lea(Address dst, AddressLiteral adr) { 196 // leal(dst, as_Address(adr)); 197 // see note in movl as to why we must use a move 198 mov_literal32(dst, (int32_t) adr.target(), adr.rspec()); 199 } 200 201 void MacroAssembler::leave() { 202 mov(rsp, rbp); 203 pop(rbp); 204 } 205 206 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) { 207 // Multiplication of two Java long values stored on the stack 208 // as illustrated below. Result is in rdx:rax. 209 // 210 // rsp ---> [ ?? ] \ \ 211 // .... | y_rsp_offset | 212 // [ y_lo ] / (in bytes) | x_rsp_offset 213 // [ y_hi ] | (in bytes) 214 // .... | 215 // [ x_lo ] / 216 // [ x_hi ] 217 // .... 218 // 219 // Basic idea: lo(result) = lo(x_lo * y_lo) 220 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) 221 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset); 222 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset); 223 Label quick; 224 // load x_hi, y_hi and check if quick 225 // multiplication is possible 226 movl(rbx, x_hi); 227 movl(rcx, y_hi); 228 movl(rax, rbx); 229 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0 230 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply 231 // do full multiplication 232 // 1st step 233 mull(y_lo); // x_hi * y_lo 234 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx, 235 // 2nd step 236 movl(rax, x_lo); 237 mull(rcx); // x_lo * y_hi 238 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx, 239 // 3rd step 240 bind(quick); // note: rbx, = 0 if quick multiply! 241 movl(rax, x_lo); 242 mull(y_lo); // x_lo * y_lo 243 addl(rdx, rbx); // correct hi(x_lo * y_lo) 244 } 245 246 void MacroAssembler::lneg(Register hi, Register lo) { 247 negl(lo); 248 adcl(hi, 0); 249 negl(hi); 250 } 251 252 void MacroAssembler::lshl(Register hi, Register lo) { 253 // Java shift left long support (semantics as described in JVM spec., p.305) 254 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n)) 255 // shift value is in rcx ! 256 assert(hi != rcx, "must not use rcx"); 257 assert(lo != rcx, "must not use rcx"); 258 const Register s = rcx; // shift count 259 const int n = BitsPerWord; 260 Label L; 261 andl(s, 0x3f); // s := s & 0x3f (s < 0x40) 262 cmpl(s, n); // if (s < n) 263 jcc(Assembler::less, L); // else (s >= n) 264 movl(hi, lo); // x := x << n 265 xorl(lo, lo); 266 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n! 267 bind(L); // s (mod n) < n 268 shldl(hi, lo); // x := x << s 269 shll(lo); 270 } 271 272 273 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) { 274 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310) 275 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n)) 276 assert(hi != rcx, "must not use rcx"); 277 assert(lo != rcx, "must not use rcx"); 278 const Register s = rcx; // shift count 279 const int n = BitsPerWord; 280 Label L; 281 andl(s, 0x3f); // s := s & 0x3f (s < 0x40) 282 cmpl(s, n); // if (s < n) 283 jcc(Assembler::less, L); // else (s >= n) 284 movl(lo, hi); // x := x >> n 285 if (sign_extension) sarl(hi, 31); 286 else xorl(hi, hi); 287 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n! 288 bind(L); // s (mod n) < n 289 shrdl(lo, hi); // x := x >> s 290 if (sign_extension) sarl(hi); 291 else shrl(hi); 292 } 293 294 void MacroAssembler::movoop(Register dst, jobject obj) { 295 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate()); 296 } 297 298 void MacroAssembler::movoop(Address dst, jobject obj) { 299 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate()); 300 } 301 302 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) { 303 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate()); 304 } 305 306 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) { 307 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate()); 308 } 309 310 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) { 311 // scratch register is not used, 312 // it is defined to match parameters of 64-bit version of this method. 313 if (src.is_lval()) { 314 mov_literal32(dst, (intptr_t)src.target(), src.rspec()); 315 } else { 316 movl(dst, as_Address(src)); 317 } 318 } 319 320 void MacroAssembler::movptr(ArrayAddress dst, Register src) { 321 movl(as_Address(dst), src); 322 } 323 324 void MacroAssembler::movptr(Register dst, ArrayAddress src) { 325 movl(dst, as_Address(src)); 326 } 327 328 // src should NEVER be a real pointer. Use AddressLiteral for true pointers 329 void MacroAssembler::movptr(Address dst, intptr_t src) { 330 movl(dst, src); 331 } 332 333 334 void MacroAssembler::pop_callee_saved_registers() { 335 pop(rcx); 336 pop(rdx); 337 pop(rdi); 338 pop(rsi); 339 } 340 341 void MacroAssembler::pop_fTOS() { 342 fld_d(Address(rsp, 0)); 343 addl(rsp, 2 * wordSize); 344 } 345 346 void MacroAssembler::push_callee_saved_registers() { 347 push(rsi); 348 push(rdi); 349 push(rdx); 350 push(rcx); 351 } 352 353 void MacroAssembler::push_fTOS() { 354 subl(rsp, 2 * wordSize); 355 fstp_d(Address(rsp, 0)); 356 } 357 358 359 void MacroAssembler::pushoop(jobject obj) { 360 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate()); 361 } 362 363 void MacroAssembler::pushklass(Metadata* obj) { 364 push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate()); 365 } 366 367 void MacroAssembler::pushptr(AddressLiteral src) { 368 if (src.is_lval()) { 369 push_literal32((int32_t)src.target(), src.rspec()); 370 } else { 371 pushl(as_Address(src)); 372 } 373 } 374 375 void MacroAssembler::set_word_if_not_zero(Register dst) { 376 xorl(dst, dst); 377 set_byte_if_not_zero(dst); 378 } 379 380 static void pass_arg0(MacroAssembler* masm, Register arg) { 381 masm->push(arg); 382 } 383 384 static void pass_arg1(MacroAssembler* masm, Register arg) { 385 masm->push(arg); 386 } 387 388 static void pass_arg2(MacroAssembler* masm, Register arg) { 389 masm->push(arg); 390 } 391 392 static void pass_arg3(MacroAssembler* masm, Register arg) { 393 masm->push(arg); 394 } 395 396 #ifndef PRODUCT 397 extern "C" void findpc(intptr_t x); 398 #endif 399 400 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) { 401 // In order to get locks to work, we need to fake a in_VM state 402 JavaThread* thread = JavaThread::current(); 403 JavaThreadState saved_state = thread->thread_state(); 404 thread->set_thread_state(_thread_in_vm); 405 if (ShowMessageBoxOnError) { 406 JavaThread* thread = JavaThread::current(); 407 JavaThreadState saved_state = thread->thread_state(); 408 thread->set_thread_state(_thread_in_vm); 409 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { 410 ttyLocker ttyl; 411 BytecodeCounter::print(); 412 } 413 // To see where a verify_oop failed, get $ebx+40/X for this frame. 414 // This is the value of eip which points to where verify_oop will return. 415 if (os::message_box(msg, "Execution stopped, print registers?")) { 416 print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip); 417 BREAKPOINT; 418 } 419 } else { 420 ttyLocker ttyl; 421 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg); 422 } 423 // Don't assert holding the ttyLock 424 assert(false, "DEBUG MESSAGE: %s", msg); 425 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state); 426 } 427 428 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) { 429 ttyLocker ttyl; 430 FlagSetting fs(Debugging, true); 431 tty->print_cr("eip = 0x%08x", eip); 432 #ifndef PRODUCT 433 if ((WizardMode || Verbose) && PrintMiscellaneous) { 434 tty->cr(); 435 findpc(eip); 436 tty->cr(); 437 } 438 #endif 439 #define PRINT_REG(rax) \ 440 { tty->print("%s = ", #rax); os::print_location(tty, rax); } 441 PRINT_REG(rax); 442 PRINT_REG(rbx); 443 PRINT_REG(rcx); 444 PRINT_REG(rdx); 445 PRINT_REG(rdi); 446 PRINT_REG(rsi); 447 PRINT_REG(rbp); 448 PRINT_REG(rsp); 449 #undef PRINT_REG 450 // Print some words near top of staack. 451 int* dump_sp = (int*) rsp; 452 for (int col1 = 0; col1 < 8; col1++) { 453 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp); 454 os::print_location(tty, *dump_sp++); 455 } 456 for (int row = 0; row < 16; row++) { 457 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp); 458 for (int col = 0; col < 8; col++) { 459 tty->print(" 0x%08x", *dump_sp++); 460 } 461 tty->cr(); 462 } 463 // Print some instructions around pc: 464 Disassembler::decode((address)eip-64, (address)eip); 465 tty->print_cr("--------"); 466 Disassembler::decode((address)eip, (address)eip+32); 467 } 468 469 void MacroAssembler::stop(const char* msg) { 470 ExternalAddress message((address)msg); 471 // push address of message 472 pushptr(message.addr()); 473 { Label L; call(L, relocInfo::none); bind(L); } // push eip 474 pusha(); // push registers 475 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32))); 476 hlt(); 477 } 478 479 void MacroAssembler::warn(const char* msg) { 480 push_CPU_state(); 481 482 ExternalAddress message((address) msg); 483 // push address of message 484 pushptr(message.addr()); 485 486 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning))); 487 addl(rsp, wordSize); // discard argument 488 pop_CPU_state(); 489 } 490 491 void MacroAssembler::print_state() { 492 { Label L; call(L, relocInfo::none); bind(L); } // push eip 493 pusha(); // push registers 494 495 push_CPU_state(); 496 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32))); 497 pop_CPU_state(); 498 499 popa(); 500 addl(rsp, wordSize); 501 } 502 503 #else // _LP64 504 505 // 64 bit versions 506 507 Address MacroAssembler::as_Address(AddressLiteral adr) { 508 // amd64 always does this as a pc-rel 509 // we can be absolute or disp based on the instruction type 510 // jmp/call are displacements others are absolute 511 assert(!adr.is_lval(), "must be rval"); 512 assert(reachable(adr), "must be"); 513 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc()); 514 515 } 516 517 Address MacroAssembler::as_Address(ArrayAddress adr) { 518 AddressLiteral base = adr.base(); 519 lea(rscratch1, base); 520 Address index = adr.index(); 521 assert(index._disp == 0, "must not have disp"); // maybe it can? 522 Address array(rscratch1, index._index, index._scale, index._disp); 523 return array; 524 } 525 526 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) { 527 Label L, E; 528 529 #ifdef _WIN64 530 // Windows always allocates space for it's register args 531 assert(num_args <= 4, "only register arguments supported"); 532 subq(rsp, frame::arg_reg_save_area_bytes); 533 #endif 534 535 // Align stack if necessary 536 testl(rsp, 15); 537 jcc(Assembler::zero, L); 538 539 subq(rsp, 8); 540 { 541 call(RuntimeAddress(entry_point)); 542 } 543 addq(rsp, 8); 544 jmp(E); 545 546 bind(L); 547 { 548 call(RuntimeAddress(entry_point)); 549 } 550 551 bind(E); 552 553 #ifdef _WIN64 554 // restore stack pointer 555 addq(rsp, frame::arg_reg_save_area_bytes); 556 #endif 557 558 } 559 560 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) { 561 assert(!src2.is_lval(), "should use cmpptr"); 562 563 if (reachable(src2)) { 564 cmpq(src1, as_Address(src2)); 565 } else { 566 lea(rscratch1, src2); 567 Assembler::cmpq(src1, Address(rscratch1, 0)); 568 } 569 } 570 571 int MacroAssembler::corrected_idivq(Register reg) { 572 // Full implementation of Java ldiv and lrem; checks for special 573 // case as described in JVM spec., p.243 & p.271. The function 574 // returns the (pc) offset of the idivl instruction - may be needed 575 // for implicit exceptions. 576 // 577 // normal case special case 578 // 579 // input : rax: dividend min_long 580 // reg: divisor (may not be eax/edx) -1 581 // 582 // output: rax: quotient (= rax idiv reg) min_long 583 // rdx: remainder (= rax irem reg) 0 584 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register"); 585 static const int64_t min_long = 0x8000000000000000; 586 Label normal_case, special_case; 587 588 // check for special case 589 cmp64(rax, ExternalAddress((address) &min_long)); 590 jcc(Assembler::notEqual, normal_case); 591 xorl(rdx, rdx); // prepare rdx for possible special case (where 592 // remainder = 0) 593 cmpq(reg, -1); 594 jcc(Assembler::equal, special_case); 595 596 // handle normal case 597 bind(normal_case); 598 cdqq(); 599 int idivq_offset = offset(); 600 idivq(reg); 601 602 // normal and special case exit 603 bind(special_case); 604 605 return idivq_offset; 606 } 607 608 void MacroAssembler::decrementq(Register reg, int value) { 609 if (value == min_jint) { subq(reg, value); return; } 610 if (value < 0) { incrementq(reg, -value); return; } 611 if (value == 0) { ; return; } 612 if (value == 1 && UseIncDec) { decq(reg) ; return; } 613 /* else */ { subq(reg, value) ; return; } 614 } 615 616 void MacroAssembler::decrementq(Address dst, int value) { 617 if (value == min_jint) { subq(dst, value); return; } 618 if (value < 0) { incrementq(dst, -value); return; } 619 if (value == 0) { ; return; } 620 if (value == 1 && UseIncDec) { decq(dst) ; return; } 621 /* else */ { subq(dst, value) ; return; } 622 } 623 624 void MacroAssembler::incrementq(AddressLiteral dst) { 625 if (reachable(dst)) { 626 incrementq(as_Address(dst)); 627 } else { 628 lea(rscratch1, dst); 629 incrementq(Address(rscratch1, 0)); 630 } 631 } 632 633 void MacroAssembler::incrementq(Register reg, int value) { 634 if (value == min_jint) { addq(reg, value); return; } 635 if (value < 0) { decrementq(reg, -value); return; } 636 if (value == 0) { ; return; } 637 if (value == 1 && UseIncDec) { incq(reg) ; return; } 638 /* else */ { addq(reg, value) ; return; } 639 } 640 641 void MacroAssembler::incrementq(Address dst, int value) { 642 if (value == min_jint) { addq(dst, value); return; } 643 if (value < 0) { decrementq(dst, -value); return; } 644 if (value == 0) { ; return; } 645 if (value == 1 && UseIncDec) { incq(dst) ; return; } 646 /* else */ { addq(dst, value) ; return; } 647 } 648 649 // 32bit can do a case table jump in one instruction but we no longer allow the base 650 // to be installed in the Address class 651 void MacroAssembler::jump(ArrayAddress entry) { 652 lea(rscratch1, entry.base()); 653 Address dispatch = entry.index(); 654 assert(dispatch._base == noreg, "must be"); 655 dispatch._base = rscratch1; 656 jmp(dispatch); 657 } 658 659 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) { 660 ShouldNotReachHere(); // 64bit doesn't use two regs 661 cmpq(x_lo, y_lo); 662 } 663 664 void MacroAssembler::lea(Register dst, AddressLiteral src) { 665 mov_literal64(dst, (intptr_t)src.target(), src.rspec()); 666 } 667 668 void MacroAssembler::lea(Address dst, AddressLiteral adr) { 669 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec()); 670 movptr(dst, rscratch1); 671 } 672 673 void MacroAssembler::leave() { 674 // %%% is this really better? Why not on 32bit too? 675 emit_int8((unsigned char)0xC9); // LEAVE 676 } 677 678 void MacroAssembler::lneg(Register hi, Register lo) { 679 ShouldNotReachHere(); // 64bit doesn't use two regs 680 negq(lo); 681 } 682 683 void MacroAssembler::movoop(Register dst, jobject obj) { 684 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate()); 685 } 686 687 void MacroAssembler::movoop(Address dst, jobject obj) { 688 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate()); 689 movq(dst, rscratch1); 690 } 691 692 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) { 693 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate()); 694 } 695 696 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) { 697 mov_literal64(rscratch1, (intptr_t)obj, metadata_Relocation::spec_for_immediate()); 698 movq(dst, rscratch1); 699 } 700 701 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) { 702 if (src.is_lval()) { 703 mov_literal64(dst, (intptr_t)src.target(), src.rspec()); 704 } else { 705 if (reachable(src)) { 706 movq(dst, as_Address(src)); 707 } else { 708 lea(scratch, src); 709 movq(dst, Address(scratch, 0)); 710 } 711 } 712 } 713 714 void MacroAssembler::movptr(ArrayAddress dst, Register src) { 715 movq(as_Address(dst), src); 716 } 717 718 void MacroAssembler::movptr(Register dst, ArrayAddress src) { 719 movq(dst, as_Address(src)); 720 } 721 722 // src should NEVER be a real pointer. Use AddressLiteral for true pointers 723 void MacroAssembler::movptr(Address dst, intptr_t src) { 724 mov64(rscratch1, src); 725 movq(dst, rscratch1); 726 } 727 728 // These are mostly for initializing NULL 729 void MacroAssembler::movptr(Address dst, int32_t src) { 730 movslq(dst, src); 731 } 732 733 void MacroAssembler::movptr(Register dst, int32_t src) { 734 mov64(dst, (intptr_t)src); 735 } 736 737 void MacroAssembler::pushoop(jobject obj) { 738 movoop(rscratch1, obj); 739 push(rscratch1); 740 } 741 742 void MacroAssembler::pushklass(Metadata* obj) { 743 mov_metadata(rscratch1, obj); 744 push(rscratch1); 745 } 746 747 void MacroAssembler::pushptr(AddressLiteral src) { 748 lea(rscratch1, src); 749 if (src.is_lval()) { 750 push(rscratch1); 751 } else { 752 pushq(Address(rscratch1, 0)); 753 } 754 } 755 756 void MacroAssembler::reset_last_Java_frame(bool clear_fp) { 757 // we must set sp to zero to clear frame 758 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD); 759 // must clear fp, so that compiled frames are not confused; it is 760 // possible that we need it only for debugging 761 if (clear_fp) { 762 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD); 763 } 764 765 // Always clear the pc because it could have been set by make_walkable() 766 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD); 767 vzeroupper(); 768 } 769 770 void MacroAssembler::set_last_Java_frame(Register last_java_sp, 771 Register last_java_fp, 772 address last_java_pc) { 773 vzeroupper(); 774 // determine last_java_sp register 775 if (!last_java_sp->is_valid()) { 776 last_java_sp = rsp; 777 } 778 779 // last_java_fp is optional 780 if (last_java_fp->is_valid()) { 781 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), 782 last_java_fp); 783 } 784 785 // last_java_pc is optional 786 if (last_java_pc != NULL) { 787 Address java_pc(r15_thread, 788 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()); 789 lea(rscratch1, InternalAddress(last_java_pc)); 790 movptr(java_pc, rscratch1); 791 } 792 793 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp); 794 } 795 796 static void pass_arg0(MacroAssembler* masm, Register arg) { 797 if (c_rarg0 != arg ) { 798 masm->mov(c_rarg0, arg); 799 } 800 } 801 802 static void pass_arg1(MacroAssembler* masm, Register arg) { 803 if (c_rarg1 != arg ) { 804 masm->mov(c_rarg1, arg); 805 } 806 } 807 808 static void pass_arg2(MacroAssembler* masm, Register arg) { 809 if (c_rarg2 != arg ) { 810 masm->mov(c_rarg2, arg); 811 } 812 } 813 814 static void pass_arg3(MacroAssembler* masm, Register arg) { 815 if (c_rarg3 != arg ) { 816 masm->mov(c_rarg3, arg); 817 } 818 } 819 820 void MacroAssembler::stop(const char* msg) { 821 address rip = pc(); 822 pusha(); // get regs on stack 823 lea(c_rarg0, ExternalAddress((address) msg)); 824 lea(c_rarg1, InternalAddress(rip)); 825 movq(c_rarg2, rsp); // pass pointer to regs array 826 andq(rsp, -16); // align stack as required by ABI 827 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64))); 828 hlt(); 829 } 830 831 void MacroAssembler::warn(const char* msg) { 832 push(rbp); 833 movq(rbp, rsp); 834 andq(rsp, -16); // align stack as required by push_CPU_state and call 835 push_CPU_state(); // keeps alignment at 16 bytes 836 lea(c_rarg0, ExternalAddress((address) msg)); 837 call_VM_leaf(CAST_FROM_FN_PTR(address, warning), c_rarg0); 838 pop_CPU_state(); 839 mov(rsp, rbp); 840 pop(rbp); 841 } 842 843 void MacroAssembler::print_state() { 844 address rip = pc(); 845 pusha(); // get regs on stack 846 push(rbp); 847 movq(rbp, rsp); 848 andq(rsp, -16); // align stack as required by push_CPU_state and call 849 push_CPU_state(); // keeps alignment at 16 bytes 850 851 lea(c_rarg0, InternalAddress(rip)); 852 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array 853 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1); 854 855 pop_CPU_state(); 856 mov(rsp, rbp); 857 pop(rbp); 858 popa(); 859 } 860 861 #ifndef PRODUCT 862 extern "C" void findpc(intptr_t x); 863 #endif 864 865 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) { 866 // In order to get locks to work, we need to fake a in_VM state 867 if (ShowMessageBoxOnError) { 868 JavaThread* thread = JavaThread::current(); 869 JavaThreadState saved_state = thread->thread_state(); 870 thread->set_thread_state(_thread_in_vm); 871 #ifndef PRODUCT 872 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { 873 ttyLocker ttyl; 874 BytecodeCounter::print(); 875 } 876 #endif 877 // To see where a verify_oop failed, get $ebx+40/X for this frame. 878 // XXX correct this offset for amd64 879 // This is the value of eip which points to where verify_oop will return. 880 if (os::message_box(msg, "Execution stopped, print registers?")) { 881 print_state64(pc, regs); 882 BREAKPOINT; 883 assert(false, "start up GDB"); 884 } 885 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state); 886 } else { 887 ttyLocker ttyl; 888 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", 889 msg); 890 assert(false, "DEBUG MESSAGE: %s", msg); 891 } 892 } 893 894 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) { 895 ttyLocker ttyl; 896 FlagSetting fs(Debugging, true); 897 tty->print_cr("rip = 0x%016lx", (intptr_t)pc); 898 #ifndef PRODUCT 899 tty->cr(); 900 findpc(pc); 901 tty->cr(); 902 #endif 903 #define PRINT_REG(rax, value) \ 904 { tty->print("%s = ", #rax); os::print_location(tty, value); } 905 PRINT_REG(rax, regs[15]); 906 PRINT_REG(rbx, regs[12]); 907 PRINT_REG(rcx, regs[14]); 908 PRINT_REG(rdx, regs[13]); 909 PRINT_REG(rdi, regs[8]); 910 PRINT_REG(rsi, regs[9]); 911 PRINT_REG(rbp, regs[10]); 912 PRINT_REG(rsp, regs[11]); 913 PRINT_REG(r8 , regs[7]); 914 PRINT_REG(r9 , regs[6]); 915 PRINT_REG(r10, regs[5]); 916 PRINT_REG(r11, regs[4]); 917 PRINT_REG(r12, regs[3]); 918 PRINT_REG(r13, regs[2]); 919 PRINT_REG(r14, regs[1]); 920 PRINT_REG(r15, regs[0]); 921 #undef PRINT_REG 922 // Print some words near top of staack. 923 int64_t* rsp = (int64_t*) regs[11]; 924 int64_t* dump_sp = rsp; 925 for (int col1 = 0; col1 < 8; col1++) { 926 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp); 927 os::print_location(tty, *dump_sp++); 928 } 929 for (int row = 0; row < 25; row++) { 930 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp); 931 for (int col = 0; col < 4; col++) { 932 tty->print(" 0x%016lx", (intptr_t)*dump_sp++); 933 } 934 tty->cr(); 935 } 936 // Print some instructions around pc: 937 Disassembler::decode((address)pc-64, (address)pc); 938 tty->print_cr("--------"); 939 Disassembler::decode((address)pc, (address)pc+32); 940 } 941 942 #endif // _LP64 943 944 // Now versions that are common to 32/64 bit 945 946 void MacroAssembler::addptr(Register dst, int32_t imm32) { 947 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32)); 948 } 949 950 void MacroAssembler::addptr(Register dst, Register src) { 951 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); 952 } 953 954 void MacroAssembler::addptr(Address dst, Register src) { 955 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); 956 } 957 958 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) { 959 if (reachable(src)) { 960 Assembler::addsd(dst, as_Address(src)); 961 } else { 962 lea(rscratch1, src); 963 Assembler::addsd(dst, Address(rscratch1, 0)); 964 } 965 } 966 967 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) { 968 if (reachable(src)) { 969 addss(dst, as_Address(src)); 970 } else { 971 lea(rscratch1, src); 972 addss(dst, Address(rscratch1, 0)); 973 } 974 } 975 976 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src) { 977 if (reachable(src)) { 978 Assembler::addpd(dst, as_Address(src)); 979 } else { 980 lea(rscratch1, src); 981 Assembler::addpd(dst, Address(rscratch1, 0)); 982 } 983 } 984 985 void MacroAssembler::align(int modulus) { 986 align(modulus, offset()); 987 } 988 989 void MacroAssembler::align(int modulus, int target) { 990 if (target % modulus != 0) { 991 nop(modulus - (target % modulus)); 992 } 993 } 994 995 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) { 996 // Used in sign-masking with aligned address. 997 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); 998 if (reachable(src)) { 999 Assembler::andpd(dst, as_Address(src)); 1000 } else { 1001 lea(rscratch1, src); 1002 Assembler::andpd(dst, Address(rscratch1, 0)); 1003 } 1004 } 1005 1006 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src) { 1007 // Used in sign-masking with aligned address. 1008 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); 1009 if (reachable(src)) { 1010 Assembler::andps(dst, as_Address(src)); 1011 } else { 1012 lea(rscratch1, src); 1013 Assembler::andps(dst, Address(rscratch1, 0)); 1014 } 1015 } 1016 1017 void MacroAssembler::andptr(Register dst, int32_t imm32) { 1018 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32)); 1019 } 1020 1021 void MacroAssembler::atomic_incl(Address counter_addr) { 1022 if (os::is_MP()) 1023 lock(); 1024 incrementl(counter_addr); 1025 } 1026 1027 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register scr) { 1028 if (reachable(counter_addr)) { 1029 atomic_incl(as_Address(counter_addr)); 1030 } else { 1031 lea(scr, counter_addr); 1032 atomic_incl(Address(scr, 0)); 1033 } 1034 } 1035 1036 #ifdef _LP64 1037 void MacroAssembler::atomic_incq(Address counter_addr) { 1038 if (os::is_MP()) 1039 lock(); 1040 incrementq(counter_addr); 1041 } 1042 1043 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register scr) { 1044 if (reachable(counter_addr)) { 1045 atomic_incq(as_Address(counter_addr)); 1046 } else { 1047 lea(scr, counter_addr); 1048 atomic_incq(Address(scr, 0)); 1049 } 1050 } 1051 #endif 1052 1053 // Writes to stack successive pages until offset reached to check for 1054 // stack overflow + shadow pages. This clobbers tmp. 1055 void MacroAssembler::bang_stack_size(Register size, Register tmp) { 1056 movptr(tmp, rsp); 1057 // Bang stack for total size given plus shadow page size. 1058 // Bang one page at a time because large size can bang beyond yellow and 1059 // red zones. 1060 Label loop; 1061 bind(loop); 1062 movl(Address(tmp, (-os::vm_page_size())), size ); 1063 subptr(tmp, os::vm_page_size()); 1064 subl(size, os::vm_page_size()); 1065 jcc(Assembler::greater, loop); 1066 1067 // Bang down shadow pages too. 1068 // At this point, (tmp-0) is the last address touched, so don't 1069 // touch it again. (It was touched as (tmp-pagesize) but then tmp 1070 // was post-decremented.) Skip this address by starting at i=1, and 1071 // touch a few more pages below. N.B. It is important to touch all 1072 // the way down including all pages in the shadow zone. 1073 for (int i = 1; i < ((int)JavaThread::stack_shadow_zone_size() / os::vm_page_size()); i++) { 1074 // this could be any sized move but this is can be a debugging crumb 1075 // so the bigger the better. 1076 movptr(Address(tmp, (-i*os::vm_page_size())), size ); 1077 } 1078 } 1079 1080 void MacroAssembler::reserved_stack_check() { 1081 // testing if reserved zone needs to be enabled 1082 Label no_reserved_zone_enabling; 1083 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread); 1084 NOT_LP64(get_thread(rsi);) 1085 1086 cmpptr(rsp, Address(thread, JavaThread::reserved_stack_activation_offset())); 1087 jcc(Assembler::below, no_reserved_zone_enabling); 1088 1089 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), thread); 1090 jump(RuntimeAddress(StubRoutines::throw_delayed_StackOverflowError_entry())); 1091 should_not_reach_here(); 1092 1093 bind(no_reserved_zone_enabling); 1094 } 1095 1096 int MacroAssembler::biased_locking_enter(Register lock_reg, 1097 Register obj_reg, 1098 Register swap_reg, 1099 Register tmp_reg, 1100 bool swap_reg_contains_mark, 1101 Label& done, 1102 Label* slow_case, 1103 BiasedLockingCounters* counters) { 1104 assert(UseBiasedLocking, "why call this otherwise?"); 1105 assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq"); 1106 assert(tmp_reg != noreg, "tmp_reg must be supplied"); 1107 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg); 1108 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout"); 1109 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes()); 1110 NOT_LP64( Address saved_mark_addr(lock_reg, 0); ) 1111 1112 if (PrintBiasedLockingStatistics && counters == NULL) { 1113 counters = BiasedLocking::counters(); 1114 } 1115 // Biased locking 1116 // See whether the lock is currently biased toward our thread and 1117 // whether the epoch is still valid 1118 // Note that the runtime guarantees sufficient alignment of JavaThread 1119 // pointers to allow age to be placed into low bits 1120 // First check to see whether biasing is even enabled for this object 1121 Label cas_label; 1122 int null_check_offset = -1; 1123 if (!swap_reg_contains_mark) { 1124 null_check_offset = offset(); 1125 movptr(swap_reg, mark_addr); 1126 } 1127 movptr(tmp_reg, swap_reg); 1128 andptr(tmp_reg, markOopDesc::biased_lock_mask_in_place); 1129 cmpptr(tmp_reg, markOopDesc::biased_lock_pattern); 1130 jcc(Assembler::notEqual, cas_label); 1131 // The bias pattern is present in the object's header. Need to check 1132 // whether the bias owner and the epoch are both still current. 1133 #ifndef _LP64 1134 // Note that because there is no current thread register on x86_32 we 1135 // need to store off the mark word we read out of the object to 1136 // avoid reloading it and needing to recheck invariants below. This 1137 // store is unfortunate but it makes the overall code shorter and 1138 // simpler. 1139 movptr(saved_mark_addr, swap_reg); 1140 #endif 1141 if (swap_reg_contains_mark) { 1142 null_check_offset = offset(); 1143 } 1144 load_prototype_header(tmp_reg, obj_reg); 1145 #ifdef _LP64 1146 orptr(tmp_reg, r15_thread); 1147 xorptr(tmp_reg, swap_reg); 1148 Register header_reg = tmp_reg; 1149 #else 1150 xorptr(tmp_reg, swap_reg); 1151 get_thread(swap_reg); 1152 xorptr(swap_reg, tmp_reg); 1153 Register header_reg = swap_reg; 1154 #endif 1155 andptr(header_reg, ~((int) markOopDesc::age_mask_in_place)); 1156 if (counters != NULL) { 1157 cond_inc32(Assembler::zero, 1158 ExternalAddress((address) counters->biased_lock_entry_count_addr())); 1159 } 1160 jcc(Assembler::equal, done); 1161 1162 Label try_revoke_bias; 1163 Label try_rebias; 1164 1165 // At this point we know that the header has the bias pattern and 1166 // that we are not the bias owner in the current epoch. We need to 1167 // figure out more details about the state of the header in order to 1168 // know what operations can be legally performed on the object's 1169 // header. 1170 1171 // If the low three bits in the xor result aren't clear, that means 1172 // the prototype header is no longer biased and we have to revoke 1173 // the bias on this object. 1174 testptr(header_reg, markOopDesc::biased_lock_mask_in_place); 1175 jccb(Assembler::notZero, try_revoke_bias); 1176 1177 // Biasing is still enabled for this data type. See whether the 1178 // epoch of the current bias is still valid, meaning that the epoch 1179 // bits of the mark word are equal to the epoch bits of the 1180 // prototype header. (Note that the prototype header's epoch bits 1181 // only change at a safepoint.) If not, attempt to rebias the object 1182 // toward the current thread. Note that we must be absolutely sure 1183 // that the current epoch is invalid in order to do this because 1184 // otherwise the manipulations it performs on the mark word are 1185 // illegal. 1186 testptr(header_reg, markOopDesc::epoch_mask_in_place); 1187 jccb(Assembler::notZero, try_rebias); 1188 1189 // The epoch of the current bias is still valid but we know nothing 1190 // about the owner; it might be set or it might be clear. Try to 1191 // acquire the bias of the object using an atomic operation. If this 1192 // fails we will go in to the runtime to revoke the object's bias. 1193 // Note that we first construct the presumed unbiased header so we 1194 // don't accidentally blow away another thread's valid bias. 1195 NOT_LP64( movptr(swap_reg, saved_mark_addr); ) 1196 andptr(swap_reg, 1197 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place); 1198 #ifdef _LP64 1199 movptr(tmp_reg, swap_reg); 1200 orptr(tmp_reg, r15_thread); 1201 #else 1202 get_thread(tmp_reg); 1203 orptr(tmp_reg, swap_reg); 1204 #endif 1205 if (os::is_MP()) { 1206 lock(); 1207 } 1208 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg 1209 // If the biasing toward our thread failed, this means that 1210 // another thread succeeded in biasing it toward itself and we 1211 // need to revoke that bias. The revocation will occur in the 1212 // interpreter runtime in the slow case. 1213 if (counters != NULL) { 1214 cond_inc32(Assembler::zero, 1215 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr())); 1216 } 1217 if (slow_case != NULL) { 1218 jcc(Assembler::notZero, *slow_case); 1219 } 1220 jmp(done); 1221 1222 bind(try_rebias); 1223 // At this point we know the epoch has expired, meaning that the 1224 // current "bias owner", if any, is actually invalid. Under these 1225 // circumstances _only_, we are allowed to use the current header's 1226 // value as the comparison value when doing the cas to acquire the 1227 // bias in the current epoch. In other words, we allow transfer of 1228 // the bias from one thread to another directly in this situation. 1229 // 1230 // FIXME: due to a lack of registers we currently blow away the age 1231 // bits in this situation. Should attempt to preserve them. 1232 load_prototype_header(tmp_reg, obj_reg); 1233 #ifdef _LP64 1234 orptr(tmp_reg, r15_thread); 1235 #else 1236 get_thread(swap_reg); 1237 orptr(tmp_reg, swap_reg); 1238 movptr(swap_reg, saved_mark_addr); 1239 #endif 1240 if (os::is_MP()) { 1241 lock(); 1242 } 1243 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg 1244 // If the biasing toward our thread failed, then another thread 1245 // succeeded in biasing it toward itself and we need to revoke that 1246 // bias. The revocation will occur in the runtime in the slow case. 1247 if (counters != NULL) { 1248 cond_inc32(Assembler::zero, 1249 ExternalAddress((address) counters->rebiased_lock_entry_count_addr())); 1250 } 1251 if (slow_case != NULL) { 1252 jcc(Assembler::notZero, *slow_case); 1253 } 1254 jmp(done); 1255 1256 bind(try_revoke_bias); 1257 // The prototype mark in the klass doesn't have the bias bit set any 1258 // more, indicating that objects of this data type are not supposed 1259 // to be biased any more. We are going to try to reset the mark of 1260 // this object to the prototype value and fall through to the 1261 // CAS-based locking scheme. Note that if our CAS fails, it means 1262 // that another thread raced us for the privilege of revoking the 1263 // bias of this particular object, so it's okay to continue in the 1264 // normal locking code. 1265 // 1266 // FIXME: due to a lack of registers we currently blow away the age 1267 // bits in this situation. Should attempt to preserve them. 1268 NOT_LP64( movptr(swap_reg, saved_mark_addr); ) 1269 load_prototype_header(tmp_reg, obj_reg); 1270 if (os::is_MP()) { 1271 lock(); 1272 } 1273 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg 1274 // Fall through to the normal CAS-based lock, because no matter what 1275 // the result of the above CAS, some thread must have succeeded in 1276 // removing the bias bit from the object's header. 1277 if (counters != NULL) { 1278 cond_inc32(Assembler::zero, 1279 ExternalAddress((address) counters->revoked_lock_entry_count_addr())); 1280 } 1281 1282 bind(cas_label); 1283 1284 return null_check_offset; 1285 } 1286 1287 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) { 1288 assert(UseBiasedLocking, "why call this otherwise?"); 1289 1290 // Check for biased locking unlock case, which is a no-op 1291 // Note: we do not have to check the thread ID for two reasons. 1292 // First, the interpreter checks for IllegalMonitorStateException at 1293 // a higher level. Second, if the bias was revoked while we held the 1294 // lock, the object could not be rebiased toward another thread, so 1295 // the bias bit would be clear. 1296 movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes())); 1297 andptr(temp_reg, markOopDesc::biased_lock_mask_in_place); 1298 cmpptr(temp_reg, markOopDesc::biased_lock_pattern); 1299 jcc(Assembler::equal, done); 1300 } 1301 1302 #ifdef COMPILER2 1303 1304 #if INCLUDE_RTM_OPT 1305 1306 // Update rtm_counters based on abort status 1307 // input: abort_status 1308 // rtm_counters (RTMLockingCounters*) 1309 // flags are killed 1310 void MacroAssembler::rtm_counters_update(Register abort_status, Register rtm_counters) { 1311 1312 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abort_count_offset())); 1313 if (PrintPreciseRTMLockingStatistics) { 1314 for (int i = 0; i < RTMLockingCounters::ABORT_STATUS_LIMIT; i++) { 1315 Label check_abort; 1316 testl(abort_status, (1<<i)); 1317 jccb(Assembler::equal, check_abort); 1318 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abortX_count_offset() + (i * sizeof(uintx)))); 1319 bind(check_abort); 1320 } 1321 } 1322 } 1323 1324 // Branch if (random & (count-1) != 0), count is 2^n 1325 // tmp, scr and flags are killed 1326 void MacroAssembler::branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel) { 1327 assert(tmp == rax, ""); 1328 assert(scr == rdx, ""); 1329 rdtsc(); // modifies EDX:EAX 1330 andptr(tmp, count-1); 1331 jccb(Assembler::notZero, brLabel); 1332 } 1333 1334 // Perform abort ratio calculation, set no_rtm bit if high ratio 1335 // input: rtm_counters_Reg (RTMLockingCounters* address) 1336 // tmpReg, rtm_counters_Reg and flags are killed 1337 void MacroAssembler::rtm_abort_ratio_calculation(Register tmpReg, 1338 Register rtm_counters_Reg, 1339 RTMLockingCounters* rtm_counters, 1340 Metadata* method_data) { 1341 Label L_done, L_check_always_rtm1, L_check_always_rtm2; 1342 1343 if (RTMLockingCalculationDelay > 0) { 1344 // Delay calculation 1345 movptr(tmpReg, ExternalAddress((address) RTMLockingCounters::rtm_calculation_flag_addr()), tmpReg); 1346 testptr(tmpReg, tmpReg); 1347 jccb(Assembler::equal, L_done); 1348 } 1349 // Abort ratio calculation only if abort_count > RTMAbortThreshold 1350 // Aborted transactions = abort_count * 100 1351 // All transactions = total_count * RTMTotalCountIncrRate 1352 // Set no_rtm bit if (Aborted transactions >= All transactions * RTMAbortRatio) 1353 1354 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::abort_count_offset())); 1355 cmpptr(tmpReg, RTMAbortThreshold); 1356 jccb(Assembler::below, L_check_always_rtm2); 1357 imulptr(tmpReg, tmpReg, 100); 1358 1359 Register scrReg = rtm_counters_Reg; 1360 movptr(scrReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset())); 1361 imulptr(scrReg, scrReg, RTMTotalCountIncrRate); 1362 imulptr(scrReg, scrReg, RTMAbortRatio); 1363 cmpptr(tmpReg, scrReg); 1364 jccb(Assembler::below, L_check_always_rtm1); 1365 if (method_data != NULL) { 1366 // set rtm_state to "no rtm" in MDO 1367 mov_metadata(tmpReg, method_data); 1368 if (os::is_MP()) { 1369 lock(); 1370 } 1371 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), NoRTM); 1372 } 1373 jmpb(L_done); 1374 bind(L_check_always_rtm1); 1375 // Reload RTMLockingCounters* address 1376 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters)); 1377 bind(L_check_always_rtm2); 1378 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset())); 1379 cmpptr(tmpReg, RTMLockingThreshold / RTMTotalCountIncrRate); 1380 jccb(Assembler::below, L_done); 1381 if (method_data != NULL) { 1382 // set rtm_state to "always rtm" in MDO 1383 mov_metadata(tmpReg, method_data); 1384 if (os::is_MP()) { 1385 lock(); 1386 } 1387 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), UseRTM); 1388 } 1389 bind(L_done); 1390 } 1391 1392 // Update counters and perform abort ratio calculation 1393 // input: abort_status_Reg 1394 // rtm_counters_Reg, flags are killed 1395 void MacroAssembler::rtm_profiling(Register abort_status_Reg, 1396 Register rtm_counters_Reg, 1397 RTMLockingCounters* rtm_counters, 1398 Metadata* method_data, 1399 bool profile_rtm) { 1400 1401 assert(rtm_counters != NULL, "should not be NULL when profiling RTM"); 1402 // update rtm counters based on rax value at abort 1403 // reads abort_status_Reg, updates flags 1404 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters)); 1405 rtm_counters_update(abort_status_Reg, rtm_counters_Reg); 1406 if (profile_rtm) { 1407 // Save abort status because abort_status_Reg is used by following code. 1408 if (RTMRetryCount > 0) { 1409 push(abort_status_Reg); 1410 } 1411 assert(rtm_counters != NULL, "should not be NULL when profiling RTM"); 1412 rtm_abort_ratio_calculation(abort_status_Reg, rtm_counters_Reg, rtm_counters, method_data); 1413 // restore abort status 1414 if (RTMRetryCount > 0) { 1415 pop(abort_status_Reg); 1416 } 1417 } 1418 } 1419 1420 // Retry on abort if abort's status is 0x6: can retry (0x2) | memory conflict (0x4) 1421 // inputs: retry_count_Reg 1422 // : abort_status_Reg 1423 // output: retry_count_Reg decremented by 1 1424 // flags are killed 1425 void MacroAssembler::rtm_retry_lock_on_abort(Register retry_count_Reg, Register abort_status_Reg, Label& retryLabel) { 1426 Label doneRetry; 1427 assert(abort_status_Reg == rax, ""); 1428 // The abort reason bits are in eax (see all states in rtmLocking.hpp) 1429 // 0x6 = conflict on which we can retry (0x2) | memory conflict (0x4) 1430 // if reason is in 0x6 and retry count != 0 then retry 1431 andptr(abort_status_Reg, 0x6); 1432 jccb(Assembler::zero, doneRetry); 1433 testl(retry_count_Reg, retry_count_Reg); 1434 jccb(Assembler::zero, doneRetry); 1435 pause(); 1436 decrementl(retry_count_Reg); 1437 jmp(retryLabel); 1438 bind(doneRetry); 1439 } 1440 1441 // Spin and retry if lock is busy, 1442 // inputs: box_Reg (monitor address) 1443 // : retry_count_Reg 1444 // output: retry_count_Reg decremented by 1 1445 // : clear z flag if retry count exceeded 1446 // tmp_Reg, scr_Reg, flags are killed 1447 void MacroAssembler::rtm_retry_lock_on_busy(Register retry_count_Reg, Register box_Reg, 1448 Register tmp_Reg, Register scr_Reg, Label& retryLabel) { 1449 Label SpinLoop, SpinExit, doneRetry; 1450 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner); 1451 1452 testl(retry_count_Reg, retry_count_Reg); 1453 jccb(Assembler::zero, doneRetry); 1454 decrementl(retry_count_Reg); 1455 movptr(scr_Reg, RTMSpinLoopCount); 1456 1457 bind(SpinLoop); 1458 pause(); 1459 decrementl(scr_Reg); 1460 jccb(Assembler::lessEqual, SpinExit); 1461 movptr(tmp_Reg, Address(box_Reg, owner_offset)); 1462 testptr(tmp_Reg, tmp_Reg); 1463 jccb(Assembler::notZero, SpinLoop); 1464 1465 bind(SpinExit); 1466 jmp(retryLabel); 1467 bind(doneRetry); 1468 incrementl(retry_count_Reg); // clear z flag 1469 } 1470 1471 // Use RTM for normal stack locks 1472 // Input: objReg (object to lock) 1473 void MacroAssembler::rtm_stack_locking(Register objReg, Register tmpReg, Register scrReg, 1474 Register retry_on_abort_count_Reg, 1475 RTMLockingCounters* stack_rtm_counters, 1476 Metadata* method_data, bool profile_rtm, 1477 Label& DONE_LABEL, Label& IsInflated) { 1478 assert(UseRTMForStackLocks, "why call this otherwise?"); 1479 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking"); 1480 assert(tmpReg == rax, ""); 1481 assert(scrReg == rdx, ""); 1482 Label L_rtm_retry, L_decrement_retry, L_on_abort; 1483 1484 if (RTMRetryCount > 0) { 1485 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort 1486 bind(L_rtm_retry); 1487 } 1488 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); 1489 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased 1490 jcc(Assembler::notZero, IsInflated); 1491 1492 if (PrintPreciseRTMLockingStatistics || profile_rtm) { 1493 Label L_noincrement; 1494 if (RTMTotalCountIncrRate > 1) { 1495 // tmpReg, scrReg and flags are killed 1496 branch_on_random_using_rdtsc(tmpReg, scrReg, RTMTotalCountIncrRate, L_noincrement); 1497 } 1498 assert(stack_rtm_counters != NULL, "should not be NULL when profiling RTM"); 1499 atomic_incptr(ExternalAddress((address)stack_rtm_counters->total_count_addr()), scrReg); 1500 bind(L_noincrement); 1501 } 1502 xbegin(L_on_abort); 1503 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // fetch markword 1504 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits 1505 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked 1506 jcc(Assembler::equal, DONE_LABEL); // all done if unlocked 1507 1508 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX 1509 if (UseRTMXendForLockBusy) { 1510 xend(); 1511 movptr(abort_status_Reg, 0x2); // Set the abort status to 2 (so we can retry) 1512 jmp(L_decrement_retry); 1513 } 1514 else { 1515 xabort(0); 1516 } 1517 bind(L_on_abort); 1518 if (PrintPreciseRTMLockingStatistics || profile_rtm) { 1519 rtm_profiling(abort_status_Reg, scrReg, stack_rtm_counters, method_data, profile_rtm); 1520 } 1521 bind(L_decrement_retry); 1522 if (RTMRetryCount > 0) { 1523 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4) 1524 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry); 1525 } 1526 } 1527 1528 // Use RTM for inflating locks 1529 // inputs: objReg (object to lock) 1530 // boxReg (on-stack box address (displaced header location) - KILLED) 1531 // tmpReg (ObjectMonitor address + markOopDesc::monitor_value) 1532 void MacroAssembler::rtm_inflated_locking(Register objReg, Register boxReg, Register tmpReg, 1533 Register scrReg, Register retry_on_busy_count_Reg, 1534 Register retry_on_abort_count_Reg, 1535 RTMLockingCounters* rtm_counters, 1536 Metadata* method_data, bool profile_rtm, 1537 Label& DONE_LABEL) { 1538 assert(UseRTMLocking, "why call this otherwise?"); 1539 assert(tmpReg == rax, ""); 1540 assert(scrReg == rdx, ""); 1541 Label L_rtm_retry, L_decrement_retry, L_on_abort; 1542 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner); 1543 1544 // Without cast to int32_t a movptr will destroy r10 which is typically obj 1545 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())); 1546 movptr(boxReg, tmpReg); // Save ObjectMonitor address 1547 1548 if (RTMRetryCount > 0) { 1549 movl(retry_on_busy_count_Reg, RTMRetryCount); // Retry on lock busy 1550 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort 1551 bind(L_rtm_retry); 1552 } 1553 if (PrintPreciseRTMLockingStatistics || profile_rtm) { 1554 Label L_noincrement; 1555 if (RTMTotalCountIncrRate > 1) { 1556 // tmpReg, scrReg and flags are killed 1557 branch_on_random_using_rdtsc(tmpReg, scrReg, RTMTotalCountIncrRate, L_noincrement); 1558 } 1559 assert(rtm_counters != NULL, "should not be NULL when profiling RTM"); 1560 atomic_incptr(ExternalAddress((address)rtm_counters->total_count_addr()), scrReg); 1561 bind(L_noincrement); 1562 } 1563 xbegin(L_on_abort); 1564 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); 1565 movptr(tmpReg, Address(tmpReg, owner_offset)); 1566 testptr(tmpReg, tmpReg); 1567 jcc(Assembler::zero, DONE_LABEL); 1568 if (UseRTMXendForLockBusy) { 1569 xend(); 1570 jmp(L_decrement_retry); 1571 } 1572 else { 1573 xabort(0); 1574 } 1575 bind(L_on_abort); 1576 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX 1577 if (PrintPreciseRTMLockingStatistics || profile_rtm) { 1578 rtm_profiling(abort_status_Reg, scrReg, rtm_counters, method_data, profile_rtm); 1579 } 1580 if (RTMRetryCount > 0) { 1581 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4) 1582 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry); 1583 } 1584 1585 movptr(tmpReg, Address(boxReg, owner_offset)) ; 1586 testptr(tmpReg, tmpReg) ; 1587 jccb(Assembler::notZero, L_decrement_retry) ; 1588 1589 // Appears unlocked - try to swing _owner from null to non-null. 1590 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. 1591 #ifdef _LP64 1592 Register threadReg = r15_thread; 1593 #else 1594 get_thread(scrReg); 1595 Register threadReg = scrReg; 1596 #endif 1597 if (os::is_MP()) { 1598 lock(); 1599 } 1600 cmpxchgptr(threadReg, Address(boxReg, owner_offset)); // Updates tmpReg 1601 1602 if (RTMRetryCount > 0) { 1603 // success done else retry 1604 jccb(Assembler::equal, DONE_LABEL) ; 1605 bind(L_decrement_retry); 1606 // Spin and retry if lock is busy. 1607 rtm_retry_lock_on_busy(retry_on_busy_count_Reg, boxReg, tmpReg, scrReg, L_rtm_retry); 1608 } 1609 else { 1610 bind(L_decrement_retry); 1611 } 1612 } 1613 1614 #endif // INCLUDE_RTM_OPT 1615 1616 // Fast_Lock and Fast_Unlock used by C2 1617 1618 // Because the transitions from emitted code to the runtime 1619 // monitorenter/exit helper stubs are so slow it's critical that 1620 // we inline both the stack-locking fast-path and the inflated fast path. 1621 // 1622 // See also: cmpFastLock and cmpFastUnlock. 1623 // 1624 // What follows is a specialized inline transliteration of the code 1625 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat 1626 // another option would be to emit TrySlowEnter and TrySlowExit methods 1627 // at startup-time. These methods would accept arguments as 1628 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure 1629 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply 1630 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit. 1631 // In practice, however, the # of lock sites is bounded and is usually small. 1632 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer 1633 // if the processor uses simple bimodal branch predictors keyed by EIP 1634 // Since the helper routines would be called from multiple synchronization 1635 // sites. 1636 // 1637 // An even better approach would be write "MonitorEnter()" and "MonitorExit()" 1638 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites 1639 // to those specialized methods. That'd give us a mostly platform-independent 1640 // implementation that the JITs could optimize and inline at their pleasure. 1641 // Done correctly, the only time we'd need to cross to native could would be 1642 // to park() or unpark() threads. We'd also need a few more unsafe operators 1643 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and 1644 // (b) explicit barriers or fence operations. 1645 // 1646 // TODO: 1647 // 1648 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr). 1649 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals. 1650 // Given TLAB allocation, Self is usually manifested in a register, so passing it into 1651 // the lock operators would typically be faster than reifying Self. 1652 // 1653 // * Ideally I'd define the primitives as: 1654 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED. 1655 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED 1656 // Unfortunately ADLC bugs prevent us from expressing the ideal form. 1657 // Instead, we're stuck with a rather awkward and brittle register assignments below. 1658 // Furthermore the register assignments are overconstrained, possibly resulting in 1659 // sub-optimal code near the synchronization site. 1660 // 1661 // * Eliminate the sp-proximity tests and just use "== Self" tests instead. 1662 // Alternately, use a better sp-proximity test. 1663 // 1664 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value. 1665 // Either one is sufficient to uniquely identify a thread. 1666 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead. 1667 // 1668 // * Intrinsify notify() and notifyAll() for the common cases where the 1669 // object is locked by the calling thread but the waitlist is empty. 1670 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll(). 1671 // 1672 // * use jccb and jmpb instead of jcc and jmp to improve code density. 1673 // But beware of excessive branch density on AMD Opterons. 1674 // 1675 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success 1676 // or failure of the fast-path. If the fast-path fails then we pass 1677 // control to the slow-path, typically in C. In Fast_Lock and 1678 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2 1679 // will emit a conditional branch immediately after the node. 1680 // So we have branches to branches and lots of ICC.ZF games. 1681 // Instead, it might be better to have C2 pass a "FailureLabel" 1682 // into Fast_Lock and Fast_Unlock. In the case of success, control 1683 // will drop through the node. ICC.ZF is undefined at exit. 1684 // In the case of failure, the node will branch directly to the 1685 // FailureLabel 1686 1687 1688 // obj: object to lock 1689 // box: on-stack box address (displaced header location) - KILLED 1690 // rax,: tmp -- KILLED 1691 // scr: tmp -- KILLED 1692 void MacroAssembler::fast_lock(Register objReg, Register boxReg, Register tmpReg, 1693 Register scrReg, Register cx1Reg, Register cx2Reg, 1694 BiasedLockingCounters* counters, 1695 RTMLockingCounters* rtm_counters, 1696 RTMLockingCounters* stack_rtm_counters, 1697 Metadata* method_data, 1698 bool use_rtm, bool profile_rtm) { 1699 // Ensure the register assignments are disjoint 1700 assert(tmpReg == rax, ""); 1701 1702 if (use_rtm) { 1703 assert_different_registers(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg); 1704 } else { 1705 assert(cx1Reg == noreg, ""); 1706 assert(cx2Reg == noreg, ""); 1707 assert_different_registers(objReg, boxReg, tmpReg, scrReg); 1708 } 1709 1710 if (counters != NULL) { 1711 atomic_incl(ExternalAddress((address)counters->total_entry_count_addr()), scrReg); 1712 } 1713 if (EmitSync & 1) { 1714 // set box->dhw = markOopDesc::unused_mark() 1715 // Force all sync thru slow-path: slow_enter() and slow_exit() 1716 movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())); 1717 cmpptr (rsp, (int32_t)NULL_WORD); 1718 } else { 1719 // Possible cases that we'll encounter in fast_lock 1720 // ------------------------------------------------ 1721 // * Inflated 1722 // -- unlocked 1723 // -- Locked 1724 // = by self 1725 // = by other 1726 // * biased 1727 // -- by Self 1728 // -- by other 1729 // * neutral 1730 // * stack-locked 1731 // -- by self 1732 // = sp-proximity test hits 1733 // = sp-proximity test generates false-negative 1734 // -- by other 1735 // 1736 1737 Label IsInflated, DONE_LABEL; 1738 1739 // it's stack-locked, biased or neutral 1740 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage 1741 // order to reduce the number of conditional branches in the most common cases. 1742 // Beware -- there's a subtle invariant that fetch of the markword 1743 // at [FETCH], below, will never observe a biased encoding (*101b). 1744 // If this invariant is not held we risk exclusion (safety) failure. 1745 if (UseBiasedLocking && !UseOptoBiasInlining) { 1746 biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, counters); 1747 } 1748 1749 #if INCLUDE_RTM_OPT 1750 if (UseRTMForStackLocks && use_rtm) { 1751 rtm_stack_locking(objReg, tmpReg, scrReg, cx2Reg, 1752 stack_rtm_counters, method_data, profile_rtm, 1753 DONE_LABEL, IsInflated); 1754 } 1755 #endif // INCLUDE_RTM_OPT 1756 1757 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // [FETCH] 1758 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased 1759 jccb(Assembler::notZero, IsInflated); 1760 1761 // Attempt stack-locking ... 1762 orptr (tmpReg, markOopDesc::unlocked_value); 1763 movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS 1764 if (os::is_MP()) { 1765 lock(); 1766 } 1767 cmpxchgptr(boxReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Updates tmpReg 1768 if (counters != NULL) { 1769 cond_inc32(Assembler::equal, 1770 ExternalAddress((address)counters->fast_path_entry_count_addr())); 1771 } 1772 jcc(Assembler::equal, DONE_LABEL); // Success 1773 1774 // Recursive locking. 1775 // The object is stack-locked: markword contains stack pointer to BasicLock. 1776 // Locked by current thread if difference with current SP is less than one page. 1777 subptr(tmpReg, rsp); 1778 // Next instruction set ZFlag == 1 (Success) if difference is less then one page. 1779 andptr(tmpReg, (int32_t) (NOT_LP64(0xFFFFF003) LP64_ONLY(7 - os::vm_page_size())) ); 1780 movptr(Address(boxReg, 0), tmpReg); 1781 if (counters != NULL) { 1782 cond_inc32(Assembler::equal, 1783 ExternalAddress((address)counters->fast_path_entry_count_addr())); 1784 } 1785 jmp(DONE_LABEL); 1786 1787 bind(IsInflated); 1788 // The object is inflated. tmpReg contains pointer to ObjectMonitor* + markOopDesc::monitor_value 1789 1790 #if INCLUDE_RTM_OPT 1791 // Use the same RTM locking code in 32- and 64-bit VM. 1792 if (use_rtm) { 1793 rtm_inflated_locking(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg, 1794 rtm_counters, method_data, profile_rtm, DONE_LABEL); 1795 } else { 1796 #endif // INCLUDE_RTM_OPT 1797 1798 #ifndef _LP64 1799 // The object is inflated. 1800 1801 // boxReg refers to the on-stack BasicLock in the current frame. 1802 // We'd like to write: 1803 // set box->_displaced_header = markOopDesc::unused_mark(). Any non-0 value suffices. 1804 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers 1805 // additional latency as we have another ST in the store buffer that must drain. 1806 1807 if (EmitSync & 8192) { 1808 movptr(Address(boxReg, 0), 3); // results in ST-before-CAS penalty 1809 get_thread (scrReg); 1810 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2] 1811 movptr(tmpReg, NULL_WORD); // consider: xor vs mov 1812 if (os::is_MP()) { 1813 lock(); 1814 } 1815 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1816 } else 1817 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS 1818 // register juggle because we need tmpReg for cmpxchgptr below 1819 movptr(scrReg, boxReg); 1820 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2] 1821 1822 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes 1823 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) { 1824 // prefetchw [eax + Offset(_owner)-2] 1825 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1826 } 1827 1828 if ((EmitSync & 64) == 0) { 1829 // Optimistic form: consider XORL tmpReg,tmpReg 1830 movptr(tmpReg, NULL_WORD); 1831 } else { 1832 // Can suffer RTS->RTO upgrades on shared or cold $ lines 1833 // Test-And-CAS instead of CAS 1834 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner 1835 testptr(tmpReg, tmpReg); // Locked ? 1836 jccb (Assembler::notZero, DONE_LABEL); 1837 } 1838 1839 // Appears unlocked - try to swing _owner from null to non-null. 1840 // Ideally, I'd manifest "Self" with get_thread and then attempt 1841 // to CAS the register containing Self into m->Owner. 1842 // But we don't have enough registers, so instead we can either try to CAS 1843 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds 1844 // we later store "Self" into m->Owner. Transiently storing a stack address 1845 // (rsp or the address of the box) into m->owner is harmless. 1846 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. 1847 if (os::is_MP()) { 1848 lock(); 1849 } 1850 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1851 movptr(Address(scrReg, 0), 3); // box->_displaced_header = 3 1852 // If we weren't able to swing _owner from NULL to the BasicLock 1853 // then take the slow path. 1854 jccb (Assembler::notZero, DONE_LABEL); 1855 // update _owner from BasicLock to thread 1856 get_thread (scrReg); // beware: clobbers ICCs 1857 movptr(Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), scrReg); 1858 xorptr(boxReg, boxReg); // set icc.ZFlag = 1 to indicate success 1859 1860 // If the CAS fails we can either retry or pass control to the slow-path. 1861 // We use the latter tactic. 1862 // Pass the CAS result in the icc.ZFlag into DONE_LABEL 1863 // If the CAS was successful ... 1864 // Self has acquired the lock 1865 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it. 1866 // Intentional fall-through into DONE_LABEL ... 1867 } else { 1868 movptr(Address(boxReg, 0), intptr_t(markOopDesc::unused_mark())); // results in ST-before-CAS penalty 1869 movptr(boxReg, tmpReg); 1870 1871 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes 1872 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) { 1873 // prefetchw [eax + Offset(_owner)-2] 1874 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1875 } 1876 1877 if ((EmitSync & 64) == 0) { 1878 // Optimistic form 1879 xorptr (tmpReg, tmpReg); 1880 } else { 1881 // Can suffer RTS->RTO upgrades on shared or cold $ lines 1882 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner 1883 testptr(tmpReg, tmpReg); // Locked ? 1884 jccb (Assembler::notZero, DONE_LABEL); 1885 } 1886 1887 // Appears unlocked - try to swing _owner from null to non-null. 1888 // Use either "Self" (in scr) or rsp as thread identity in _owner. 1889 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. 1890 get_thread (scrReg); 1891 if (os::is_MP()) { 1892 lock(); 1893 } 1894 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1895 1896 // If the CAS fails we can either retry or pass control to the slow-path. 1897 // We use the latter tactic. 1898 // Pass the CAS result in the icc.ZFlag into DONE_LABEL 1899 // If the CAS was successful ... 1900 // Self has acquired the lock 1901 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it. 1902 // Intentional fall-through into DONE_LABEL ... 1903 } 1904 #else // _LP64 1905 // It's inflated 1906 movq(scrReg, tmpReg); 1907 xorq(tmpReg, tmpReg); 1908 1909 if (os::is_MP()) { 1910 lock(); 1911 } 1912 cmpxchgptr(r15_thread, Address(scrReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1913 // Unconditionally set box->_displaced_header = markOopDesc::unused_mark(). 1914 // Without cast to int32_t movptr will destroy r10 which is typically obj. 1915 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())); 1916 // Intentional fall-through into DONE_LABEL ... 1917 // Propagate ICC.ZF from CAS above into DONE_LABEL. 1918 #endif // _LP64 1919 #if INCLUDE_RTM_OPT 1920 } // use_rtm() 1921 #endif 1922 // DONE_LABEL is a hot target - we'd really like to place it at the 1923 // start of cache line by padding with NOPs. 1924 // See the AMD and Intel software optimization manuals for the 1925 // most efficient "long" NOP encodings. 1926 // Unfortunately none of our alignment mechanisms suffice. 1927 bind(DONE_LABEL); 1928 1929 // At DONE_LABEL the icc ZFlag is set as follows ... 1930 // Fast_Unlock uses the same protocol. 1931 // ZFlag == 1 -> Success 1932 // ZFlag == 0 -> Failure - force control through the slow-path 1933 } 1934 } 1935 1936 // obj: object to unlock 1937 // box: box address (displaced header location), killed. Must be EAX. 1938 // tmp: killed, cannot be obj nor box. 1939 // 1940 // Some commentary on balanced locking: 1941 // 1942 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites. 1943 // Methods that don't have provably balanced locking are forced to run in the 1944 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock. 1945 // The interpreter provides two properties: 1946 // I1: At return-time the interpreter automatically and quietly unlocks any 1947 // objects acquired the current activation (frame). Recall that the 1948 // interpreter maintains an on-stack list of locks currently held by 1949 // a frame. 1950 // I2: If a method attempts to unlock an object that is not held by the 1951 // the frame the interpreter throws IMSX. 1952 // 1953 // Lets say A(), which has provably balanced locking, acquires O and then calls B(). 1954 // B() doesn't have provably balanced locking so it runs in the interpreter. 1955 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O 1956 // is still locked by A(). 1957 // 1958 // The only other source of unbalanced locking would be JNI. The "Java Native Interface: 1959 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter 1960 // should not be unlocked by "normal" java-level locking and vice-versa. The specification 1961 // doesn't specify what will occur if a program engages in such mixed-mode locking, however. 1962 // Arguably given that the spec legislates the JNI case as undefined our implementation 1963 // could reasonably *avoid* checking owner in Fast_Unlock(). 1964 // In the interest of performance we elide m->Owner==Self check in unlock. 1965 // A perfectly viable alternative is to elide the owner check except when 1966 // Xcheck:jni is enabled. 1967 1968 void MacroAssembler::fast_unlock(Register objReg, Register boxReg, Register tmpReg, bool use_rtm) { 1969 assert(boxReg == rax, ""); 1970 assert_different_registers(objReg, boxReg, tmpReg); 1971 1972 if (EmitSync & 4) { 1973 // Disable - inhibit all inlining. Force control through the slow-path 1974 cmpptr (rsp, 0); 1975 } else { 1976 Label DONE_LABEL, Stacked, CheckSucc; 1977 1978 // Critically, the biased locking test must have precedence over 1979 // and appear before the (box->dhw == 0) recursive stack-lock test. 1980 if (UseBiasedLocking && !UseOptoBiasInlining) { 1981 biased_locking_exit(objReg, tmpReg, DONE_LABEL); 1982 } 1983 1984 #if INCLUDE_RTM_OPT 1985 if (UseRTMForStackLocks && use_rtm) { 1986 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking"); 1987 Label L_regular_unlock; 1988 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // fetch markword 1989 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits 1990 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked 1991 jccb(Assembler::notEqual, L_regular_unlock); // if !HLE RegularLock 1992 xend(); // otherwise end... 1993 jmp(DONE_LABEL); // ... and we're done 1994 bind(L_regular_unlock); 1995 } 1996 #endif 1997 1998 cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD); // Examine the displaced header 1999 jcc (Assembler::zero, DONE_LABEL); // 0 indicates recursive stack-lock 2000 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Examine the object's markword 2001 testptr(tmpReg, markOopDesc::monitor_value); // Inflated? 2002 jccb (Assembler::zero, Stacked); 2003 2004 // It's inflated. 2005 #if INCLUDE_RTM_OPT 2006 if (use_rtm) { 2007 Label L_regular_inflated_unlock; 2008 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner); 2009 movptr(boxReg, Address(tmpReg, owner_offset)); 2010 testptr(boxReg, boxReg); 2011 jccb(Assembler::notZero, L_regular_inflated_unlock); 2012 xend(); 2013 jmpb(DONE_LABEL); 2014 bind(L_regular_inflated_unlock); 2015 } 2016 #endif 2017 2018 // Despite our balanced locking property we still check that m->_owner == Self 2019 // as java routines or native JNI code called by this thread might 2020 // have released the lock. 2021 // Refer to the comments in synchronizer.cpp for how we might encode extra 2022 // state in _succ so we can avoid fetching EntryList|cxq. 2023 // 2024 // I'd like to add more cases in fast_lock() and fast_unlock() -- 2025 // such as recursive enter and exit -- but we have to be wary of 2026 // I$ bloat, T$ effects and BP$ effects. 2027 // 2028 // If there's no contention try a 1-0 exit. That is, exit without 2029 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how 2030 // we detect and recover from the race that the 1-0 exit admits. 2031 // 2032 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier 2033 // before it STs null into _owner, releasing the lock. Updates 2034 // to data protected by the critical section must be visible before 2035 // we drop the lock (and thus before any other thread could acquire 2036 // the lock and observe the fields protected by the lock). 2037 // IA32's memory-model is SPO, so STs are ordered with respect to 2038 // each other and there's no need for an explicit barrier (fence). 2039 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html. 2040 #ifndef _LP64 2041 get_thread (boxReg); 2042 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) { 2043 // prefetchw [ebx + Offset(_owner)-2] 2044 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 2045 } 2046 2047 // Note that we could employ various encoding schemes to reduce 2048 // the number of loads below (currently 4) to just 2 or 3. 2049 // Refer to the comments in synchronizer.cpp. 2050 // In practice the chain of fetches doesn't seem to impact performance, however. 2051 xorptr(boxReg, boxReg); 2052 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) { 2053 // Attempt to reduce branch density - AMD's branch predictor. 2054 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions))); 2055 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList))); 2056 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq))); 2057 jccb (Assembler::notZero, DONE_LABEL); 2058 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD); 2059 jmpb (DONE_LABEL); 2060 } else { 2061 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions))); 2062 jccb (Assembler::notZero, DONE_LABEL); 2063 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList))); 2064 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq))); 2065 jccb (Assembler::notZero, CheckSucc); 2066 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD); 2067 jmpb (DONE_LABEL); 2068 } 2069 2070 // The Following code fragment (EmitSync & 65536) improves the performance of 2071 // contended applications and contended synchronization microbenchmarks. 2072 // Unfortunately the emission of the code - even though not executed - causes regressions 2073 // in scimark and jetstream, evidently because of $ effects. Replacing the code 2074 // with an equal number of never-executed NOPs results in the same regression. 2075 // We leave it off by default. 2076 2077 if ((EmitSync & 65536) != 0) { 2078 Label LSuccess, LGoSlowPath ; 2079 2080 bind (CheckSucc); 2081 2082 // Optional pre-test ... it's safe to elide this 2083 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD); 2084 jccb(Assembler::zero, LGoSlowPath); 2085 2086 // We have a classic Dekker-style idiom: 2087 // ST m->_owner = 0 ; MEMBAR; LD m->_succ 2088 // There are a number of ways to implement the barrier: 2089 // (1) lock:andl &m->_owner, 0 2090 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form. 2091 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0 2092 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8 2093 // (2) If supported, an explicit MFENCE is appealing. 2094 // In older IA32 processors MFENCE is slower than lock:add or xchg 2095 // particularly if the write-buffer is full as might be the case if 2096 // if stores closely precede the fence or fence-equivalent instruction. 2097 // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences 2098 // as the situation has changed with Nehalem and Shanghai. 2099 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack 2100 // The $lines underlying the top-of-stack should be in M-state. 2101 // The locked add instruction is serializing, of course. 2102 // (4) Use xchg, which is serializing 2103 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works 2104 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0. 2105 // The integer condition codes will tell us if succ was 0. 2106 // Since _succ and _owner should reside in the same $line and 2107 // we just stored into _owner, it's likely that the $line 2108 // remains in M-state for the lock:orl. 2109 // 2110 // We currently use (3), although it's likely that switching to (2) 2111 // is correct for the future. 2112 2113 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD); 2114 if (os::is_MP()) { 2115 lock(); addptr(Address(rsp, 0), 0); 2116 } 2117 // Ratify _succ remains non-null 2118 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), 0); 2119 jccb (Assembler::notZero, LSuccess); 2120 2121 xorptr(boxReg, boxReg); // box is really EAX 2122 if (os::is_MP()) { lock(); } 2123 cmpxchgptr(rsp, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 2124 // There's no successor so we tried to regrab the lock with the 2125 // placeholder value. If that didn't work, then another thread 2126 // grabbed the lock so we're done (and exit was a success). 2127 jccb (Assembler::notEqual, LSuccess); 2128 // Since we're low on registers we installed rsp as a placeholding in _owner. 2129 // Now install Self over rsp. This is safe as we're transitioning from 2130 // non-null to non=null 2131 get_thread (boxReg); 2132 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), boxReg); 2133 // Intentional fall-through into LGoSlowPath ... 2134 2135 bind (LGoSlowPath); 2136 orptr(boxReg, 1); // set ICC.ZF=0 to indicate failure 2137 jmpb (DONE_LABEL); 2138 2139 bind (LSuccess); 2140 xorptr(boxReg, boxReg); // set ICC.ZF=1 to indicate success 2141 jmpb (DONE_LABEL); 2142 } 2143 2144 bind (Stacked); 2145 // It's not inflated and it's not recursively stack-locked and it's not biased. 2146 // It must be stack-locked. 2147 // Try to reset the header to displaced header. 2148 // The "box" value on the stack is stable, so we can reload 2149 // and be assured we observe the same value as above. 2150 movptr(tmpReg, Address(boxReg, 0)); 2151 if (os::is_MP()) { 2152 lock(); 2153 } 2154 cmpxchgptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Uses RAX which is box 2155 // Intention fall-thru into DONE_LABEL 2156 2157 // DONE_LABEL is a hot target - we'd really like to place it at the 2158 // start of cache line by padding with NOPs. 2159 // See the AMD and Intel software optimization manuals for the 2160 // most efficient "long" NOP encodings. 2161 // Unfortunately none of our alignment mechanisms suffice. 2162 if ((EmitSync & 65536) == 0) { 2163 bind (CheckSucc); 2164 } 2165 #else // _LP64 2166 // It's inflated 2167 if (EmitSync & 1024) { 2168 // Emit code to check that _owner == Self 2169 // We could fold the _owner test into subsequent code more efficiently 2170 // than using a stand-alone check, but since _owner checking is off by 2171 // default we don't bother. We also might consider predicating the 2172 // _owner==Self check on Xcheck:jni or running on a debug build. 2173 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 2174 xorptr(boxReg, r15_thread); 2175 } else { 2176 xorptr(boxReg, boxReg); 2177 } 2178 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions))); 2179 jccb (Assembler::notZero, DONE_LABEL); 2180 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq))); 2181 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList))); 2182 jccb (Assembler::notZero, CheckSucc); 2183 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD); 2184 jmpb (DONE_LABEL); 2185 2186 if ((EmitSync & 65536) == 0) { 2187 // Try to avoid passing control into the slow_path ... 2188 Label LSuccess, LGoSlowPath ; 2189 bind (CheckSucc); 2190 2191 // The following optional optimization can be elided if necessary 2192 // Effectively: if (succ == null) goto SlowPath 2193 // The code reduces the window for a race, however, 2194 // and thus benefits performance. 2195 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD); 2196 jccb (Assembler::zero, LGoSlowPath); 2197 2198 xorptr(boxReg, boxReg); 2199 if ((EmitSync & 16) && os::is_MP()) { 2200 xchgptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 2201 } else { 2202 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD); 2203 if (os::is_MP()) { 2204 // Memory barrier/fence 2205 // Dekker pivot point -- fulcrum : ST Owner; MEMBAR; LD Succ 2206 // Instead of MFENCE we use a dummy locked add of 0 to the top-of-stack. 2207 // This is faster on Nehalem and AMD Shanghai/Barcelona. 2208 // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences 2209 // We might also restructure (ST Owner=0;barrier;LD _Succ) to 2210 // (mov box,0; xchgq box, &m->Owner; LD _succ) . 2211 lock(); addl(Address(rsp, 0), 0); 2212 } 2213 } 2214 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD); 2215 jccb (Assembler::notZero, LSuccess); 2216 2217 // Rare inopportune interleaving - race. 2218 // The successor vanished in the small window above. 2219 // The lock is contended -- (cxq|EntryList) != null -- and there's no apparent successor. 2220 // We need to ensure progress and succession. 2221 // Try to reacquire the lock. 2222 // If that fails then the new owner is responsible for succession and this 2223 // thread needs to take no further action and can exit via the fast path (success). 2224 // If the re-acquire succeeds then pass control into the slow path. 2225 // As implemented, this latter mode is horrible because we generated more 2226 // coherence traffic on the lock *and* artifically extended the critical section 2227 // length while by virtue of passing control into the slow path. 2228 2229 // box is really RAX -- the following CMPXCHG depends on that binding 2230 // cmpxchg R,[M] is equivalent to rax = CAS(M,rax,R) 2231 if (os::is_MP()) { lock(); } 2232 cmpxchgptr(r15_thread, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 2233 // There's no successor so we tried to regrab the lock. 2234 // If that didn't work, then another thread grabbed the 2235 // lock so we're done (and exit was a success). 2236 jccb (Assembler::notEqual, LSuccess); 2237 // Intentional fall-through into slow-path 2238 2239 bind (LGoSlowPath); 2240 orl (boxReg, 1); // set ICC.ZF=0 to indicate failure 2241 jmpb (DONE_LABEL); 2242 2243 bind (LSuccess); 2244 testl (boxReg, 0); // set ICC.ZF=1 to indicate success 2245 jmpb (DONE_LABEL); 2246 } 2247 2248 bind (Stacked); 2249 movptr(tmpReg, Address (boxReg, 0)); // re-fetch 2250 if (os::is_MP()) { lock(); } 2251 cmpxchgptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Uses RAX which is box 2252 2253 if (EmitSync & 65536) { 2254 bind (CheckSucc); 2255 } 2256 #endif 2257 bind(DONE_LABEL); 2258 } 2259 } 2260 #endif // COMPILER2 2261 2262 void MacroAssembler::c2bool(Register x) { 2263 // implements x == 0 ? 0 : 1 2264 // note: must only look at least-significant byte of x 2265 // since C-style booleans are stored in one byte 2266 // only! (was bug) 2267 andl(x, 0xFF); 2268 setb(Assembler::notZero, x); 2269 } 2270 2271 // Wouldn't need if AddressLiteral version had new name 2272 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) { 2273 Assembler::call(L, rtype); 2274 } 2275 2276 void MacroAssembler::call(Register entry) { 2277 Assembler::call(entry); 2278 } 2279 2280 void MacroAssembler::call(AddressLiteral entry) { 2281 if (reachable(entry)) { 2282 Assembler::call_literal(entry.target(), entry.rspec()); 2283 } else { 2284 lea(rscratch1, entry); 2285 Assembler::call(rscratch1); 2286 } 2287 } 2288 2289 void MacroAssembler::ic_call(address entry, jint method_index) { 2290 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index); 2291 movptr(rax, (intptr_t)Universe::non_oop_word()); 2292 call(AddressLiteral(entry, rh)); 2293 } 2294 2295 // Implementation of call_VM versions 2296 2297 void MacroAssembler::call_VM(Register oop_result, 2298 address entry_point, 2299 bool check_exceptions) { 2300 Label C, E; 2301 call(C, relocInfo::none); 2302 jmp(E); 2303 2304 bind(C); 2305 call_VM_helper(oop_result, entry_point, 0, check_exceptions); 2306 ret(0); 2307 2308 bind(E); 2309 } 2310 2311 void MacroAssembler::call_VM(Register oop_result, 2312 address entry_point, 2313 Register arg_1, 2314 bool check_exceptions) { 2315 Label C, E; 2316 call(C, relocInfo::none); 2317 jmp(E); 2318 2319 bind(C); 2320 pass_arg1(this, arg_1); 2321 call_VM_helper(oop_result, entry_point, 1, check_exceptions); 2322 ret(0); 2323 2324 bind(E); 2325 } 2326 2327 void MacroAssembler::call_VM(Register oop_result, 2328 address entry_point, 2329 Register arg_1, 2330 Register arg_2, 2331 bool check_exceptions) { 2332 Label C, E; 2333 call(C, relocInfo::none); 2334 jmp(E); 2335 2336 bind(C); 2337 2338 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2339 2340 pass_arg2(this, arg_2); 2341 pass_arg1(this, arg_1); 2342 call_VM_helper(oop_result, entry_point, 2, check_exceptions); 2343 ret(0); 2344 2345 bind(E); 2346 } 2347 2348 void MacroAssembler::call_VM(Register oop_result, 2349 address entry_point, 2350 Register arg_1, 2351 Register arg_2, 2352 Register arg_3, 2353 bool check_exceptions) { 2354 Label C, E; 2355 call(C, relocInfo::none); 2356 jmp(E); 2357 2358 bind(C); 2359 2360 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); 2361 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); 2362 pass_arg3(this, arg_3); 2363 2364 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2365 pass_arg2(this, arg_2); 2366 2367 pass_arg1(this, arg_1); 2368 call_VM_helper(oop_result, entry_point, 3, check_exceptions); 2369 ret(0); 2370 2371 bind(E); 2372 } 2373 2374 void MacroAssembler::call_VM(Register oop_result, 2375 Register last_java_sp, 2376 address entry_point, 2377 int number_of_arguments, 2378 bool check_exceptions) { 2379 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg); 2380 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions); 2381 } 2382 2383 void MacroAssembler::call_VM(Register oop_result, 2384 Register last_java_sp, 2385 address entry_point, 2386 Register arg_1, 2387 bool check_exceptions) { 2388 pass_arg1(this, arg_1); 2389 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); 2390 } 2391 2392 void MacroAssembler::call_VM(Register oop_result, 2393 Register last_java_sp, 2394 address entry_point, 2395 Register arg_1, 2396 Register arg_2, 2397 bool check_exceptions) { 2398 2399 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2400 pass_arg2(this, arg_2); 2401 pass_arg1(this, arg_1); 2402 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); 2403 } 2404 2405 void MacroAssembler::call_VM(Register oop_result, 2406 Register last_java_sp, 2407 address entry_point, 2408 Register arg_1, 2409 Register arg_2, 2410 Register arg_3, 2411 bool check_exceptions) { 2412 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); 2413 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); 2414 pass_arg3(this, arg_3); 2415 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2416 pass_arg2(this, arg_2); 2417 pass_arg1(this, arg_1); 2418 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); 2419 } 2420 2421 void MacroAssembler::super_call_VM(Register oop_result, 2422 Register last_java_sp, 2423 address entry_point, 2424 int number_of_arguments, 2425 bool check_exceptions) { 2426 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg); 2427 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions); 2428 } 2429 2430 void MacroAssembler::super_call_VM(Register oop_result, 2431 Register last_java_sp, 2432 address entry_point, 2433 Register arg_1, 2434 bool check_exceptions) { 2435 pass_arg1(this, arg_1); 2436 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); 2437 } 2438 2439 void MacroAssembler::super_call_VM(Register oop_result, 2440 Register last_java_sp, 2441 address entry_point, 2442 Register arg_1, 2443 Register arg_2, 2444 bool check_exceptions) { 2445 2446 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2447 pass_arg2(this, arg_2); 2448 pass_arg1(this, arg_1); 2449 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); 2450 } 2451 2452 void MacroAssembler::super_call_VM(Register oop_result, 2453 Register last_java_sp, 2454 address entry_point, 2455 Register arg_1, 2456 Register arg_2, 2457 Register arg_3, 2458 bool check_exceptions) { 2459 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); 2460 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); 2461 pass_arg3(this, arg_3); 2462 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2463 pass_arg2(this, arg_2); 2464 pass_arg1(this, arg_1); 2465 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); 2466 } 2467 2468 void MacroAssembler::call_VM_base(Register oop_result, 2469 Register java_thread, 2470 Register last_java_sp, 2471 address entry_point, 2472 int number_of_arguments, 2473 bool check_exceptions) { 2474 // determine java_thread register 2475 if (!java_thread->is_valid()) { 2476 #ifdef _LP64 2477 java_thread = r15_thread; 2478 #else 2479 java_thread = rdi; 2480 get_thread(java_thread); 2481 #endif // LP64 2482 } 2483 // determine last_java_sp register 2484 if (!last_java_sp->is_valid()) { 2485 last_java_sp = rsp; 2486 } 2487 // debugging support 2488 assert(number_of_arguments >= 0 , "cannot have negative number of arguments"); 2489 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register")); 2490 #ifdef ASSERT 2491 // TraceBytecodes does not use r12 but saves it over the call, so don't verify 2492 // r12 is the heapbase. 2493 LP64_ONLY(if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");) 2494 #endif // ASSERT 2495 2496 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result"); 2497 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp"); 2498 2499 // push java thread (becomes first argument of C function) 2500 2501 NOT_LP64(push(java_thread); number_of_arguments++); 2502 LP64_ONLY(mov(c_rarg0, r15_thread)); 2503 2504 // set last Java frame before call 2505 assert(last_java_sp != rbp, "can't use ebp/rbp"); 2506 2507 // Only interpreter should have to set fp 2508 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL); 2509 2510 // do the call, remove parameters 2511 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments); 2512 2513 // restore the thread (cannot use the pushed argument since arguments 2514 // may be overwritten by C code generated by an optimizing compiler); 2515 // however can use the register value directly if it is callee saved. 2516 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) { 2517 // rdi & rsi (also r15) are callee saved -> nothing to do 2518 #ifdef ASSERT 2519 guarantee(java_thread != rax, "change this code"); 2520 push(rax); 2521 { Label L; 2522 get_thread(rax); 2523 cmpptr(java_thread, rax); 2524 jcc(Assembler::equal, L); 2525 STOP("MacroAssembler::call_VM_base: rdi not callee saved?"); 2526 bind(L); 2527 } 2528 pop(rax); 2529 #endif 2530 } else { 2531 get_thread(java_thread); 2532 } 2533 // reset last Java frame 2534 // Only interpreter should have to clear fp 2535 reset_last_Java_frame(java_thread, true); 2536 2537 // C++ interp handles this in the interpreter 2538 check_and_handle_popframe(java_thread); 2539 check_and_handle_earlyret(java_thread); 2540 2541 if (check_exceptions) { 2542 // check for pending exceptions (java_thread is set upon return) 2543 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD); 2544 #ifndef _LP64 2545 jump_cc(Assembler::notEqual, 2546 RuntimeAddress(StubRoutines::forward_exception_entry())); 2547 #else 2548 // This used to conditionally jump to forward_exception however it is 2549 // possible if we relocate that the branch will not reach. So we must jump 2550 // around so we can always reach 2551 2552 Label ok; 2553 jcc(Assembler::equal, ok); 2554 jump(RuntimeAddress(StubRoutines::forward_exception_entry())); 2555 bind(ok); 2556 #endif // LP64 2557 } 2558 2559 // get oop result if there is one and reset the value in the thread 2560 if (oop_result->is_valid()) { 2561 get_vm_result(oop_result, java_thread); 2562 } 2563 } 2564 2565 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) { 2566 2567 // Calculate the value for last_Java_sp 2568 // somewhat subtle. call_VM does an intermediate call 2569 // which places a return address on the stack just under the 2570 // stack pointer as the user finsihed with it. This allows 2571 // use to retrieve last_Java_pc from last_Java_sp[-1]. 2572 // On 32bit we then have to push additional args on the stack to accomplish 2573 // the actual requested call. On 64bit call_VM only can use register args 2574 // so the only extra space is the return address that call_VM created. 2575 // This hopefully explains the calculations here. 2576 2577 #ifdef _LP64 2578 // We've pushed one address, correct last_Java_sp 2579 lea(rax, Address(rsp, wordSize)); 2580 #else 2581 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize)); 2582 #endif // LP64 2583 2584 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions); 2585 2586 } 2587 2588 // Use this method when MacroAssembler version of call_VM_leaf_base() should be called from Interpreter. 2589 void MacroAssembler::call_VM_leaf0(address entry_point) { 2590 MacroAssembler::call_VM_leaf_base(entry_point, 0); 2591 } 2592 2593 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) { 2594 call_VM_leaf_base(entry_point, number_of_arguments); 2595 } 2596 2597 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) { 2598 pass_arg0(this, arg_0); 2599 call_VM_leaf(entry_point, 1); 2600 } 2601 2602 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { 2603 2604 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 2605 pass_arg1(this, arg_1); 2606 pass_arg0(this, arg_0); 2607 call_VM_leaf(entry_point, 2); 2608 } 2609 2610 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) { 2611 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); 2612 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2613 pass_arg2(this, arg_2); 2614 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 2615 pass_arg1(this, arg_1); 2616 pass_arg0(this, arg_0); 2617 call_VM_leaf(entry_point, 3); 2618 } 2619 2620 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) { 2621 pass_arg0(this, arg_0); 2622 MacroAssembler::call_VM_leaf_base(entry_point, 1); 2623 } 2624 2625 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { 2626 2627 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 2628 pass_arg1(this, arg_1); 2629 pass_arg0(this, arg_0); 2630 MacroAssembler::call_VM_leaf_base(entry_point, 2); 2631 } 2632 2633 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) { 2634 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); 2635 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2636 pass_arg2(this, arg_2); 2637 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 2638 pass_arg1(this, arg_1); 2639 pass_arg0(this, arg_0); 2640 MacroAssembler::call_VM_leaf_base(entry_point, 3); 2641 } 2642 2643 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) { 2644 LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg")); 2645 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); 2646 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); 2647 pass_arg3(this, arg_3); 2648 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); 2649 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2650 pass_arg2(this, arg_2); 2651 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 2652 pass_arg1(this, arg_1); 2653 pass_arg0(this, arg_0); 2654 MacroAssembler::call_VM_leaf_base(entry_point, 4); 2655 } 2656 2657 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) { 2658 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset())); 2659 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD); 2660 verify_oop(oop_result, "broken oop in call_VM_base"); 2661 } 2662 2663 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) { 2664 movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset())); 2665 movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD); 2666 } 2667 2668 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { 2669 } 2670 2671 void MacroAssembler::check_and_handle_popframe(Register java_thread) { 2672 } 2673 2674 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) { 2675 if (reachable(src1)) { 2676 cmpl(as_Address(src1), imm); 2677 } else { 2678 lea(rscratch1, src1); 2679 cmpl(Address(rscratch1, 0), imm); 2680 } 2681 } 2682 2683 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) { 2684 assert(!src2.is_lval(), "use cmpptr"); 2685 if (reachable(src2)) { 2686 cmpl(src1, as_Address(src2)); 2687 } else { 2688 lea(rscratch1, src2); 2689 cmpl(src1, Address(rscratch1, 0)); 2690 } 2691 } 2692 2693 void MacroAssembler::cmp32(Register src1, int32_t imm) { 2694 Assembler::cmpl(src1, imm); 2695 } 2696 2697 void MacroAssembler::cmp32(Register src1, Address src2) { 2698 Assembler::cmpl(src1, src2); 2699 } 2700 2701 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) { 2702 ucomisd(opr1, opr2); 2703 2704 Label L; 2705 if (unordered_is_less) { 2706 movl(dst, -1); 2707 jcc(Assembler::parity, L); 2708 jcc(Assembler::below , L); 2709 movl(dst, 0); 2710 jcc(Assembler::equal , L); 2711 increment(dst); 2712 } else { // unordered is greater 2713 movl(dst, 1); 2714 jcc(Assembler::parity, L); 2715 jcc(Assembler::above , L); 2716 movl(dst, 0); 2717 jcc(Assembler::equal , L); 2718 decrementl(dst); 2719 } 2720 bind(L); 2721 } 2722 2723 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) { 2724 ucomiss(opr1, opr2); 2725 2726 Label L; 2727 if (unordered_is_less) { 2728 movl(dst, -1); 2729 jcc(Assembler::parity, L); 2730 jcc(Assembler::below , L); 2731 movl(dst, 0); 2732 jcc(Assembler::equal , L); 2733 increment(dst); 2734 } else { // unordered is greater 2735 movl(dst, 1); 2736 jcc(Assembler::parity, L); 2737 jcc(Assembler::above , L); 2738 movl(dst, 0); 2739 jcc(Assembler::equal , L); 2740 decrementl(dst); 2741 } 2742 bind(L); 2743 } 2744 2745 2746 void MacroAssembler::cmp8(AddressLiteral src1, int imm) { 2747 if (reachable(src1)) { 2748 cmpb(as_Address(src1), imm); 2749 } else { 2750 lea(rscratch1, src1); 2751 cmpb(Address(rscratch1, 0), imm); 2752 } 2753 } 2754 2755 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) { 2756 #ifdef _LP64 2757 if (src2.is_lval()) { 2758 movptr(rscratch1, src2); 2759 Assembler::cmpq(src1, rscratch1); 2760 } else if (reachable(src2)) { 2761 cmpq(src1, as_Address(src2)); 2762 } else { 2763 lea(rscratch1, src2); 2764 Assembler::cmpq(src1, Address(rscratch1, 0)); 2765 } 2766 #else 2767 if (src2.is_lval()) { 2768 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec()); 2769 } else { 2770 cmpl(src1, as_Address(src2)); 2771 } 2772 #endif // _LP64 2773 } 2774 2775 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) { 2776 assert(src2.is_lval(), "not a mem-mem compare"); 2777 #ifdef _LP64 2778 // moves src2's literal address 2779 movptr(rscratch1, src2); 2780 Assembler::cmpq(src1, rscratch1); 2781 #else 2782 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec()); 2783 #endif // _LP64 2784 } 2785 2786 void MacroAssembler::cmpoop(Register src1, Register src2) { 2787 cmpptr(src1, src2); 2788 } 2789 2790 void MacroAssembler::cmpoop(Register src1, Address src2) { 2791 cmpptr(src1, src2); 2792 } 2793 2794 #ifdef _LP64 2795 void MacroAssembler::cmpoop(Register src1, jobject src2) { 2796 movoop(rscratch1, src2); 2797 cmpptr(src1, rscratch1); 2798 } 2799 #endif 2800 2801 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) { 2802 if (reachable(adr)) { 2803 if (os::is_MP()) 2804 lock(); 2805 cmpxchgptr(reg, as_Address(adr)); 2806 } else { 2807 lea(rscratch1, adr); 2808 if (os::is_MP()) 2809 lock(); 2810 cmpxchgptr(reg, Address(rscratch1, 0)); 2811 } 2812 } 2813 2814 void MacroAssembler::cmpxchgptr(Register reg, Address adr) { 2815 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr)); 2816 } 2817 2818 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) { 2819 if (reachable(src)) { 2820 Assembler::comisd(dst, as_Address(src)); 2821 } else { 2822 lea(rscratch1, src); 2823 Assembler::comisd(dst, Address(rscratch1, 0)); 2824 } 2825 } 2826 2827 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) { 2828 if (reachable(src)) { 2829 Assembler::comiss(dst, as_Address(src)); 2830 } else { 2831 lea(rscratch1, src); 2832 Assembler::comiss(dst, Address(rscratch1, 0)); 2833 } 2834 } 2835 2836 2837 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) { 2838 Condition negated_cond = negate_condition(cond); 2839 Label L; 2840 jcc(negated_cond, L); 2841 pushf(); // Preserve flags 2842 atomic_incl(counter_addr); 2843 popf(); 2844 bind(L); 2845 } 2846 2847 int MacroAssembler::corrected_idivl(Register reg) { 2848 // Full implementation of Java idiv and irem; checks for 2849 // special case as described in JVM spec., p.243 & p.271. 2850 // The function returns the (pc) offset of the idivl 2851 // instruction - may be needed for implicit exceptions. 2852 // 2853 // normal case special case 2854 // 2855 // input : rax,: dividend min_int 2856 // reg: divisor (may not be rax,/rdx) -1 2857 // 2858 // output: rax,: quotient (= rax, idiv reg) min_int 2859 // rdx: remainder (= rax, irem reg) 0 2860 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register"); 2861 const int min_int = 0x80000000; 2862 Label normal_case, special_case; 2863 2864 // check for special case 2865 cmpl(rax, min_int); 2866 jcc(Assembler::notEqual, normal_case); 2867 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0) 2868 cmpl(reg, -1); 2869 jcc(Assembler::equal, special_case); 2870 2871 // handle normal case 2872 bind(normal_case); 2873 cdql(); 2874 int idivl_offset = offset(); 2875 idivl(reg); 2876 2877 // normal and special case exit 2878 bind(special_case); 2879 2880 return idivl_offset; 2881 } 2882 2883 2884 2885 void MacroAssembler::decrementl(Register reg, int value) { 2886 if (value == min_jint) {subl(reg, value) ; return; } 2887 if (value < 0) { incrementl(reg, -value); return; } 2888 if (value == 0) { ; return; } 2889 if (value == 1 && UseIncDec) { decl(reg) ; return; } 2890 /* else */ { subl(reg, value) ; return; } 2891 } 2892 2893 void MacroAssembler::decrementl(Address dst, int value) { 2894 if (value == min_jint) {subl(dst, value) ; return; } 2895 if (value < 0) { incrementl(dst, -value); return; } 2896 if (value == 0) { ; return; } 2897 if (value == 1 && UseIncDec) { decl(dst) ; return; } 2898 /* else */ { subl(dst, value) ; return; } 2899 } 2900 2901 void MacroAssembler::division_with_shift (Register reg, int shift_value) { 2902 assert (shift_value > 0, "illegal shift value"); 2903 Label _is_positive; 2904 testl (reg, reg); 2905 jcc (Assembler::positive, _is_positive); 2906 int offset = (1 << shift_value) - 1 ; 2907 2908 if (offset == 1) { 2909 incrementl(reg); 2910 } else { 2911 addl(reg, offset); 2912 } 2913 2914 bind (_is_positive); 2915 sarl(reg, shift_value); 2916 } 2917 2918 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) { 2919 if (reachable(src)) { 2920 Assembler::divsd(dst, as_Address(src)); 2921 } else { 2922 lea(rscratch1, src); 2923 Assembler::divsd(dst, Address(rscratch1, 0)); 2924 } 2925 } 2926 2927 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) { 2928 if (reachable(src)) { 2929 Assembler::divss(dst, as_Address(src)); 2930 } else { 2931 lea(rscratch1, src); 2932 Assembler::divss(dst, Address(rscratch1, 0)); 2933 } 2934 } 2935 2936 // !defined(COMPILER2) is because of stupid core builds 2937 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2) || INCLUDE_JVMCI 2938 void MacroAssembler::empty_FPU_stack() { 2939 if (VM_Version::supports_mmx()) { 2940 emms(); 2941 } else { 2942 for (int i = 8; i-- > 0; ) ffree(i); 2943 } 2944 } 2945 #endif // !LP64 || C1 || !C2 || INCLUDE_JVMCI 2946 2947 2948 // Defines obj, preserves var_size_in_bytes 2949 void MacroAssembler::eden_allocate(Register obj, 2950 Register var_size_in_bytes, 2951 int con_size_in_bytes, 2952 Register t1, 2953 Label& slow_case) { 2954 assert(obj == rax, "obj must be in rax, for cmpxchg"); 2955 assert_different_registers(obj, var_size_in_bytes, t1); 2956 if (!Universe::heap()->supports_inline_contig_alloc()) { 2957 jmp(slow_case); 2958 } else { 2959 Register end = t1; 2960 Label retry; 2961 bind(retry); 2962 ExternalAddress heap_top((address) Universe::heap()->top_addr()); 2963 movptr(obj, heap_top); 2964 if (var_size_in_bytes == noreg) { 2965 lea(end, Address(obj, con_size_in_bytes)); 2966 } else { 2967 lea(end, Address(obj, var_size_in_bytes, Address::times_1)); 2968 } 2969 // if end < obj then we wrapped around => object too long => slow case 2970 cmpptr(end, obj); 2971 jcc(Assembler::below, slow_case); 2972 cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr())); 2973 jcc(Assembler::above, slow_case); 2974 // Compare obj with the top addr, and if still equal, store the new top addr in 2975 // end at the address of the top addr pointer. Sets ZF if was equal, and clears 2976 // it otherwise. Use lock prefix for atomicity on MPs. 2977 locked_cmpxchgptr(end, heap_top); 2978 jcc(Assembler::notEqual, retry); 2979 } 2980 } 2981 2982 void MacroAssembler::enter() { 2983 push(rbp); 2984 mov(rbp, rsp); 2985 } 2986 2987 // A 5 byte nop that is safe for patching (see patch_verified_entry) 2988 void MacroAssembler::fat_nop() { 2989 if (UseAddressNop) { 2990 addr_nop_5(); 2991 } else { 2992 emit_int8(0x26); // es: 2993 emit_int8(0x2e); // cs: 2994 emit_int8(0x64); // fs: 2995 emit_int8(0x65); // gs: 2996 emit_int8((unsigned char)0x90); 2997 } 2998 } 2999 3000 void MacroAssembler::fcmp(Register tmp) { 3001 fcmp(tmp, 1, true, true); 3002 } 3003 3004 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) { 3005 assert(!pop_right || pop_left, "usage error"); 3006 if (VM_Version::supports_cmov()) { 3007 assert(tmp == noreg, "unneeded temp"); 3008 if (pop_left) { 3009 fucomip(index); 3010 } else { 3011 fucomi(index); 3012 } 3013 if (pop_right) { 3014 fpop(); 3015 } 3016 } else { 3017 assert(tmp != noreg, "need temp"); 3018 if (pop_left) { 3019 if (pop_right) { 3020 fcompp(); 3021 } else { 3022 fcomp(index); 3023 } 3024 } else { 3025 fcom(index); 3026 } 3027 // convert FPU condition into eflags condition via rax, 3028 save_rax(tmp); 3029 fwait(); fnstsw_ax(); 3030 sahf(); 3031 restore_rax(tmp); 3032 } 3033 // condition codes set as follows: 3034 // 3035 // CF (corresponds to C0) if x < y 3036 // PF (corresponds to C2) if unordered 3037 // ZF (corresponds to C3) if x = y 3038 } 3039 3040 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) { 3041 fcmp2int(dst, unordered_is_less, 1, true, true); 3042 } 3043 3044 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) { 3045 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right); 3046 Label L; 3047 if (unordered_is_less) { 3048 movl(dst, -1); 3049 jcc(Assembler::parity, L); 3050 jcc(Assembler::below , L); 3051 movl(dst, 0); 3052 jcc(Assembler::equal , L); 3053 increment(dst); 3054 } else { // unordered is greater 3055 movl(dst, 1); 3056 jcc(Assembler::parity, L); 3057 jcc(Assembler::above , L); 3058 movl(dst, 0); 3059 jcc(Assembler::equal , L); 3060 decrementl(dst); 3061 } 3062 bind(L); 3063 } 3064 3065 void MacroAssembler::fld_d(AddressLiteral src) { 3066 fld_d(as_Address(src)); 3067 } 3068 3069 void MacroAssembler::fld_s(AddressLiteral src) { 3070 fld_s(as_Address(src)); 3071 } 3072 3073 void MacroAssembler::fld_x(AddressLiteral src) { 3074 Assembler::fld_x(as_Address(src)); 3075 } 3076 3077 void MacroAssembler::fldcw(AddressLiteral src) { 3078 Assembler::fldcw(as_Address(src)); 3079 } 3080 3081 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src) { 3082 if (reachable(src)) { 3083 Assembler::mulpd(dst, as_Address(src)); 3084 } else { 3085 lea(rscratch1, src); 3086 Assembler::mulpd(dst, Address(rscratch1, 0)); 3087 } 3088 } 3089 3090 void MacroAssembler::increase_precision() { 3091 subptr(rsp, BytesPerWord); 3092 fnstcw(Address(rsp, 0)); 3093 movl(rax, Address(rsp, 0)); 3094 orl(rax, 0x300); 3095 push(rax); 3096 fldcw(Address(rsp, 0)); 3097 pop(rax); 3098 } 3099 3100 void MacroAssembler::restore_precision() { 3101 fldcw(Address(rsp, 0)); 3102 addptr(rsp, BytesPerWord); 3103 } 3104 3105 void MacroAssembler::fpop() { 3106 ffree(); 3107 fincstp(); 3108 } 3109 3110 void MacroAssembler::load_float(Address src) { 3111 if (UseSSE >= 1) { 3112 movflt(xmm0, src); 3113 } else { 3114 LP64_ONLY(ShouldNotReachHere()); 3115 NOT_LP64(fld_s(src)); 3116 } 3117 } 3118 3119 void MacroAssembler::store_float(Address dst) { 3120 if (UseSSE >= 1) { 3121 movflt(dst, xmm0); 3122 } else { 3123 LP64_ONLY(ShouldNotReachHere()); 3124 NOT_LP64(fstp_s(dst)); 3125 } 3126 } 3127 3128 void MacroAssembler::load_double(Address src) { 3129 if (UseSSE >= 2) { 3130 movdbl(xmm0, src); 3131 } else { 3132 LP64_ONLY(ShouldNotReachHere()); 3133 NOT_LP64(fld_d(src)); 3134 } 3135 } 3136 3137 void MacroAssembler::store_double(Address dst) { 3138 if (UseSSE >= 2) { 3139 movdbl(dst, xmm0); 3140 } else { 3141 LP64_ONLY(ShouldNotReachHere()); 3142 NOT_LP64(fstp_d(dst)); 3143 } 3144 } 3145 3146 void MacroAssembler::fremr(Register tmp) { 3147 save_rax(tmp); 3148 { Label L; 3149 bind(L); 3150 fprem(); 3151 fwait(); fnstsw_ax(); 3152 #ifdef _LP64 3153 testl(rax, 0x400); 3154 jcc(Assembler::notEqual, L); 3155 #else 3156 sahf(); 3157 jcc(Assembler::parity, L); 3158 #endif // _LP64 3159 } 3160 restore_rax(tmp); 3161 // Result is in ST0. 3162 // Note: fxch & fpop to get rid of ST1 3163 // (otherwise FPU stack could overflow eventually) 3164 fxch(1); 3165 fpop(); 3166 } 3167 3168 // dst = c = a * b + c 3169 void MacroAssembler::fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) { 3170 Assembler::vfmadd231sd(c, a, b); 3171 if (dst != c) { 3172 movdbl(dst, c); 3173 } 3174 } 3175 3176 // dst = c = a * b + c 3177 void MacroAssembler::fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) { 3178 Assembler::vfmadd231ss(c, a, b); 3179 if (dst != c) { 3180 movflt(dst, c); 3181 } 3182 } 3183 3184 // dst = c = a * b + c 3185 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) { 3186 Assembler::vfmadd231pd(c, a, b, vector_len); 3187 if (dst != c) { 3188 vmovdqu(dst, c); 3189 } 3190 } 3191 3192 // dst = c = a * b + c 3193 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) { 3194 Assembler::vfmadd231ps(c, a, b, vector_len); 3195 if (dst != c) { 3196 vmovdqu(dst, c); 3197 } 3198 } 3199 3200 // dst = c = a * b + c 3201 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) { 3202 Assembler::vfmadd231pd(c, a, b, vector_len); 3203 if (dst != c) { 3204 vmovdqu(dst, c); 3205 } 3206 } 3207 3208 // dst = c = a * b + c 3209 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) { 3210 Assembler::vfmadd231ps(c, a, b, vector_len); 3211 if (dst != c) { 3212 vmovdqu(dst, c); 3213 } 3214 } 3215 3216 void MacroAssembler::incrementl(AddressLiteral dst) { 3217 if (reachable(dst)) { 3218 incrementl(as_Address(dst)); 3219 } else { 3220 lea(rscratch1, dst); 3221 incrementl(Address(rscratch1, 0)); 3222 } 3223 } 3224 3225 void MacroAssembler::incrementl(ArrayAddress dst) { 3226 incrementl(as_Address(dst)); 3227 } 3228 3229 void MacroAssembler::incrementl(Register reg, int value) { 3230 if (value == min_jint) {addl(reg, value) ; return; } 3231 if (value < 0) { decrementl(reg, -value); return; } 3232 if (value == 0) { ; return; } 3233 if (value == 1 && UseIncDec) { incl(reg) ; return; } 3234 /* else */ { addl(reg, value) ; return; } 3235 } 3236 3237 void MacroAssembler::incrementl(Address dst, int value) { 3238 if (value == min_jint) {addl(dst, value) ; return; } 3239 if (value < 0) { decrementl(dst, -value); return; } 3240 if (value == 0) { ; return; } 3241 if (value == 1 && UseIncDec) { incl(dst) ; return; } 3242 /* else */ { addl(dst, value) ; return; } 3243 } 3244 3245 void MacroAssembler::jump(AddressLiteral dst) { 3246 if (reachable(dst)) { 3247 jmp_literal(dst.target(), dst.rspec()); 3248 } else { 3249 lea(rscratch1, dst); 3250 jmp(rscratch1); 3251 } 3252 } 3253 3254 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) { 3255 if (reachable(dst)) { 3256 InstructionMark im(this); 3257 relocate(dst.reloc()); 3258 const int short_size = 2; 3259 const int long_size = 6; 3260 int offs = (intptr_t)dst.target() - ((intptr_t)pc()); 3261 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) { 3262 // 0111 tttn #8-bit disp 3263 emit_int8(0x70 | cc); 3264 emit_int8((offs - short_size) & 0xFF); 3265 } else { 3266 // 0000 1111 1000 tttn #32-bit disp 3267 emit_int8(0x0F); 3268 emit_int8((unsigned char)(0x80 | cc)); 3269 emit_int32(offs - long_size); 3270 } 3271 } else { 3272 #ifdef ASSERT 3273 warning("reversing conditional branch"); 3274 #endif /* ASSERT */ 3275 Label skip; 3276 jccb(reverse[cc], skip); 3277 lea(rscratch1, dst); 3278 Assembler::jmp(rscratch1); 3279 bind(skip); 3280 } 3281 } 3282 3283 void MacroAssembler::ldmxcsr(AddressLiteral src) { 3284 if (reachable(src)) { 3285 Assembler::ldmxcsr(as_Address(src)); 3286 } else { 3287 lea(rscratch1, src); 3288 Assembler::ldmxcsr(Address(rscratch1, 0)); 3289 } 3290 } 3291 3292 int MacroAssembler::load_signed_byte(Register dst, Address src) { 3293 int off; 3294 if (LP64_ONLY(true ||) VM_Version::is_P6()) { 3295 off = offset(); 3296 movsbl(dst, src); // movsxb 3297 } else { 3298 off = load_unsigned_byte(dst, src); 3299 shll(dst, 24); 3300 sarl(dst, 24); 3301 } 3302 return off; 3303 } 3304 3305 // Note: load_signed_short used to be called load_signed_word. 3306 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler 3307 // manual, which means 16 bits, that usage is found nowhere in HotSpot code. 3308 // The term "word" in HotSpot means a 32- or 64-bit machine word. 3309 int MacroAssembler::load_signed_short(Register dst, Address src) { 3310 int off; 3311 if (LP64_ONLY(true ||) VM_Version::is_P6()) { 3312 // This is dubious to me since it seems safe to do a signed 16 => 64 bit 3313 // version but this is what 64bit has always done. This seems to imply 3314 // that users are only using 32bits worth. 3315 off = offset(); 3316 movswl(dst, src); // movsxw 3317 } else { 3318 off = load_unsigned_short(dst, src); 3319 shll(dst, 16); 3320 sarl(dst, 16); 3321 } 3322 return off; 3323 } 3324 3325 int MacroAssembler::load_unsigned_byte(Register dst, Address src) { 3326 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16, 3327 // and "3.9 Partial Register Penalties", p. 22). 3328 int off; 3329 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) { 3330 off = offset(); 3331 movzbl(dst, src); // movzxb 3332 } else { 3333 xorl(dst, dst); 3334 off = offset(); 3335 movb(dst, src); 3336 } 3337 return off; 3338 } 3339 3340 // Note: load_unsigned_short used to be called load_unsigned_word. 3341 int MacroAssembler::load_unsigned_short(Register dst, Address src) { 3342 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16, 3343 // and "3.9 Partial Register Penalties", p. 22). 3344 int off; 3345 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) { 3346 off = offset(); 3347 movzwl(dst, src); // movzxw 3348 } else { 3349 xorl(dst, dst); 3350 off = offset(); 3351 movw(dst, src); 3352 } 3353 return off; 3354 } 3355 3356 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) { 3357 switch (size_in_bytes) { 3358 #ifndef _LP64 3359 case 8: 3360 assert(dst2 != noreg, "second dest register required"); 3361 movl(dst, src); 3362 movl(dst2, src.plus_disp(BytesPerInt)); 3363 break; 3364 #else 3365 case 8: movq(dst, src); break; 3366 #endif 3367 case 4: movl(dst, src); break; 3368 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break; 3369 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break; 3370 default: ShouldNotReachHere(); 3371 } 3372 } 3373 3374 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) { 3375 switch (size_in_bytes) { 3376 #ifndef _LP64 3377 case 8: 3378 assert(src2 != noreg, "second source register required"); 3379 movl(dst, src); 3380 movl(dst.plus_disp(BytesPerInt), src2); 3381 break; 3382 #else 3383 case 8: movq(dst, src); break; 3384 #endif 3385 case 4: movl(dst, src); break; 3386 case 2: movw(dst, src); break; 3387 case 1: movb(dst, src); break; 3388 default: ShouldNotReachHere(); 3389 } 3390 } 3391 3392 void MacroAssembler::mov32(AddressLiteral dst, Register src) { 3393 if (reachable(dst)) { 3394 movl(as_Address(dst), src); 3395 } else { 3396 lea(rscratch1, dst); 3397 movl(Address(rscratch1, 0), src); 3398 } 3399 } 3400 3401 void MacroAssembler::mov32(Register dst, AddressLiteral src) { 3402 if (reachable(src)) { 3403 movl(dst, as_Address(src)); 3404 } else { 3405 lea(rscratch1, src); 3406 movl(dst, Address(rscratch1, 0)); 3407 } 3408 } 3409 3410 // C++ bool manipulation 3411 3412 void MacroAssembler::movbool(Register dst, Address src) { 3413 if(sizeof(bool) == 1) 3414 movb(dst, src); 3415 else if(sizeof(bool) == 2) 3416 movw(dst, src); 3417 else if(sizeof(bool) == 4) 3418 movl(dst, src); 3419 else 3420 // unsupported 3421 ShouldNotReachHere(); 3422 } 3423 3424 void MacroAssembler::movbool(Address dst, bool boolconst) { 3425 if(sizeof(bool) == 1) 3426 movb(dst, (int) boolconst); 3427 else if(sizeof(bool) == 2) 3428 movw(dst, (int) boolconst); 3429 else if(sizeof(bool) == 4) 3430 movl(dst, (int) boolconst); 3431 else 3432 // unsupported 3433 ShouldNotReachHere(); 3434 } 3435 3436 void MacroAssembler::movbool(Address dst, Register src) { 3437 if(sizeof(bool) == 1) 3438 movb(dst, src); 3439 else if(sizeof(bool) == 2) 3440 movw(dst, src); 3441 else if(sizeof(bool) == 4) 3442 movl(dst, src); 3443 else 3444 // unsupported 3445 ShouldNotReachHere(); 3446 } 3447 3448 void MacroAssembler::movbyte(ArrayAddress dst, int src) { 3449 movb(as_Address(dst), src); 3450 } 3451 3452 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src) { 3453 if (reachable(src)) { 3454 movdl(dst, as_Address(src)); 3455 } else { 3456 lea(rscratch1, src); 3457 movdl(dst, Address(rscratch1, 0)); 3458 } 3459 } 3460 3461 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src) { 3462 if (reachable(src)) { 3463 movq(dst, as_Address(src)); 3464 } else { 3465 lea(rscratch1, src); 3466 movq(dst, Address(rscratch1, 0)); 3467 } 3468 } 3469 3470 void MacroAssembler::setvectmask(Register dst, Register src) { 3471 Assembler::movl(dst, 1); 3472 Assembler::shlxl(dst, dst, src); 3473 Assembler::decl(dst); 3474 Assembler::kmovdl(k1, dst); 3475 Assembler::movl(dst, src); 3476 } 3477 3478 void MacroAssembler::restorevectmask() { 3479 Assembler::knotwl(k1, k0); 3480 } 3481 3482 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) { 3483 if (reachable(src)) { 3484 if (UseXmmLoadAndClearUpper) { 3485 movsd (dst, as_Address(src)); 3486 } else { 3487 movlpd(dst, as_Address(src)); 3488 } 3489 } else { 3490 lea(rscratch1, src); 3491 if (UseXmmLoadAndClearUpper) { 3492 movsd (dst, Address(rscratch1, 0)); 3493 } else { 3494 movlpd(dst, Address(rscratch1, 0)); 3495 } 3496 } 3497 } 3498 3499 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) { 3500 if (reachable(src)) { 3501 movss(dst, as_Address(src)); 3502 } else { 3503 lea(rscratch1, src); 3504 movss(dst, Address(rscratch1, 0)); 3505 } 3506 } 3507 3508 void MacroAssembler::movptr(Register dst, Register src) { 3509 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); 3510 } 3511 3512 void MacroAssembler::movptr(Register dst, Address src) { 3513 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); 3514 } 3515 3516 // src should NEVER be a real pointer. Use AddressLiteral for true pointers 3517 void MacroAssembler::movptr(Register dst, intptr_t src) { 3518 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src)); 3519 } 3520 3521 void MacroAssembler::movptr(Address dst, Register src) { 3522 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); 3523 } 3524 3525 void MacroAssembler::movdqu(Address dst, XMMRegister src) { 3526 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (src->encoding() > 15)) { 3527 Assembler::vextractf32x4(dst, src, 0); 3528 } else { 3529 Assembler::movdqu(dst, src); 3530 } 3531 } 3532 3533 void MacroAssembler::movdqu(XMMRegister dst, Address src) { 3534 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (dst->encoding() > 15)) { 3535 Assembler::vinsertf32x4(dst, dst, src, 0); 3536 } else { 3537 Assembler::movdqu(dst, src); 3538 } 3539 } 3540 3541 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) { 3542 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) { 3543 Assembler::evmovdqul(dst, src, Assembler::AVX_512bit); 3544 } else { 3545 Assembler::movdqu(dst, src); 3546 } 3547 } 3548 3549 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src, Register scratchReg) { 3550 if (reachable(src)) { 3551 movdqu(dst, as_Address(src)); 3552 } else { 3553 lea(scratchReg, src); 3554 movdqu(dst, Address(scratchReg, 0)); 3555 } 3556 } 3557 3558 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) { 3559 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (src->encoding() > 15)) { 3560 vextractf64x4_low(dst, src); 3561 } else { 3562 Assembler::vmovdqu(dst, src); 3563 } 3564 } 3565 3566 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) { 3567 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (dst->encoding() > 15)) { 3568 vinsertf64x4_low(dst, src); 3569 } else { 3570 Assembler::vmovdqu(dst, src); 3571 } 3572 } 3573 3574 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) { 3575 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) { 3576 Assembler::evmovdqul(dst, src, Assembler::AVX_512bit); 3577 } 3578 else { 3579 Assembler::vmovdqu(dst, src); 3580 } 3581 } 3582 3583 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src) { 3584 if (reachable(src)) { 3585 vmovdqu(dst, as_Address(src)); 3586 } 3587 else { 3588 lea(rscratch1, src); 3589 vmovdqu(dst, Address(rscratch1, 0)); 3590 } 3591 } 3592 3593 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src) { 3594 if (reachable(src)) { 3595 Assembler::movdqa(dst, as_Address(src)); 3596 } else { 3597 lea(rscratch1, src); 3598 Assembler::movdqa(dst, Address(rscratch1, 0)); 3599 } 3600 } 3601 3602 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) { 3603 if (reachable(src)) { 3604 Assembler::movsd(dst, as_Address(src)); 3605 } else { 3606 lea(rscratch1, src); 3607 Assembler::movsd(dst, Address(rscratch1, 0)); 3608 } 3609 } 3610 3611 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) { 3612 if (reachable(src)) { 3613 Assembler::movss(dst, as_Address(src)); 3614 } else { 3615 lea(rscratch1, src); 3616 Assembler::movss(dst, Address(rscratch1, 0)); 3617 } 3618 } 3619 3620 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) { 3621 if (reachable(src)) { 3622 Assembler::mulsd(dst, as_Address(src)); 3623 } else { 3624 lea(rscratch1, src); 3625 Assembler::mulsd(dst, Address(rscratch1, 0)); 3626 } 3627 } 3628 3629 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) { 3630 if (reachable(src)) { 3631 Assembler::mulss(dst, as_Address(src)); 3632 } else { 3633 lea(rscratch1, src); 3634 Assembler::mulss(dst, Address(rscratch1, 0)); 3635 } 3636 } 3637 3638 void MacroAssembler::null_check(Register reg, int offset) { 3639 if (needs_explicit_null_check(offset)) { 3640 // provoke OS NULL exception if reg = NULL by 3641 // accessing M[reg] w/o changing any (non-CC) registers 3642 // NOTE: cmpl is plenty here to provoke a segv 3643 cmpptr(rax, Address(reg, 0)); 3644 // Note: should probably use testl(rax, Address(reg, 0)); 3645 // may be shorter code (however, this version of 3646 // testl needs to be implemented first) 3647 } else { 3648 // nothing to do, (later) access of M[reg + offset] 3649 // will provoke OS NULL exception if reg = NULL 3650 } 3651 } 3652 3653 void MacroAssembler::os_breakpoint() { 3654 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability 3655 // (e.g., MSVC can't call ps() otherwise) 3656 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint))); 3657 } 3658 3659 void MacroAssembler::unimplemented(const char* what) { 3660 char* b = new char[1024]; 3661 jio_snprintf(b, 1024, "unimplemented: %s", what); 3662 stop(b); 3663 } 3664 3665 #ifdef _LP64 3666 #define XSTATE_BV 0x200 3667 #endif 3668 3669 void MacroAssembler::pop_CPU_state() { 3670 pop_FPU_state(); 3671 pop_IU_state(); 3672 } 3673 3674 void MacroAssembler::pop_FPU_state() { 3675 #ifndef _LP64 3676 frstor(Address(rsp, 0)); 3677 #else 3678 fxrstor(Address(rsp, 0)); 3679 #endif 3680 addptr(rsp, FPUStateSizeInWords * wordSize); 3681 } 3682 3683 void MacroAssembler::pop_IU_state() { 3684 popa(); 3685 LP64_ONLY(addq(rsp, 8)); 3686 popf(); 3687 } 3688 3689 // Save Integer and Float state 3690 // Warning: Stack must be 16 byte aligned (64bit) 3691 void MacroAssembler::push_CPU_state() { 3692 push_IU_state(); 3693 push_FPU_state(); 3694 } 3695 3696 void MacroAssembler::push_FPU_state() { 3697 subptr(rsp, FPUStateSizeInWords * wordSize); 3698 #ifndef _LP64 3699 fnsave(Address(rsp, 0)); 3700 fwait(); 3701 #else 3702 fxsave(Address(rsp, 0)); 3703 #endif // LP64 3704 } 3705 3706 void MacroAssembler::push_IU_state() { 3707 // Push flags first because pusha kills them 3708 pushf(); 3709 // Make sure rsp stays 16-byte aligned 3710 LP64_ONLY(subq(rsp, 8)); 3711 pusha(); 3712 } 3713 3714 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp) { // determine java_thread register 3715 if (!java_thread->is_valid()) { 3716 java_thread = rdi; 3717 get_thread(java_thread); 3718 } 3719 // we must set sp to zero to clear frame 3720 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD); 3721 if (clear_fp) { 3722 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD); 3723 } 3724 3725 // Always clear the pc because it could have been set by make_walkable() 3726 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD); 3727 3728 vzeroupper(); 3729 } 3730 3731 void MacroAssembler::restore_rax(Register tmp) { 3732 if (tmp == noreg) pop(rax); 3733 else if (tmp != rax) mov(rax, tmp); 3734 } 3735 3736 void MacroAssembler::round_to(Register reg, int modulus) { 3737 addptr(reg, modulus - 1); 3738 andptr(reg, -modulus); 3739 } 3740 3741 void MacroAssembler::save_rax(Register tmp) { 3742 if (tmp == noreg) push(rax); 3743 else if (tmp != rax) mov(tmp, rax); 3744 } 3745 3746 // Write serialization page so VM thread can do a pseudo remote membar. 3747 // We use the current thread pointer to calculate a thread specific 3748 // offset to write to within the page. This minimizes bus traffic 3749 // due to cache line collision. 3750 void MacroAssembler::serialize_memory(Register thread, Register tmp) { 3751 movl(tmp, thread); 3752 shrl(tmp, os::get_serialize_page_shift_count()); 3753 andl(tmp, (os::vm_page_size() - sizeof(int))); 3754 3755 Address index(noreg, tmp, Address::times_1); 3756 ExternalAddress page(os::get_memory_serialize_page()); 3757 3758 // Size of store must match masking code above 3759 movl(as_Address(ArrayAddress(page, index)), tmp); 3760 } 3761 3762 // Calls to C land 3763 // 3764 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded 3765 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp 3766 // has to be reset to 0. This is required to allow proper stack traversal. 3767 void MacroAssembler::set_last_Java_frame(Register java_thread, 3768 Register last_java_sp, 3769 Register last_java_fp, 3770 address last_java_pc) { 3771 vzeroupper(); 3772 // determine java_thread register 3773 if (!java_thread->is_valid()) { 3774 java_thread = rdi; 3775 get_thread(java_thread); 3776 } 3777 // determine last_java_sp register 3778 if (!last_java_sp->is_valid()) { 3779 last_java_sp = rsp; 3780 } 3781 3782 // last_java_fp is optional 3783 3784 if (last_java_fp->is_valid()) { 3785 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp); 3786 } 3787 3788 // last_java_pc is optional 3789 3790 if (last_java_pc != NULL) { 3791 lea(Address(java_thread, 3792 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()), 3793 InternalAddress(last_java_pc)); 3794 3795 } 3796 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp); 3797 } 3798 3799 void MacroAssembler::shlptr(Register dst, int imm8) { 3800 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8)); 3801 } 3802 3803 void MacroAssembler::shrptr(Register dst, int imm8) { 3804 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8)); 3805 } 3806 3807 void MacroAssembler::sign_extend_byte(Register reg) { 3808 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) { 3809 movsbl(reg, reg); // movsxb 3810 } else { 3811 shll(reg, 24); 3812 sarl(reg, 24); 3813 } 3814 } 3815 3816 void MacroAssembler::sign_extend_short(Register reg) { 3817 if (LP64_ONLY(true ||) VM_Version::is_P6()) { 3818 movswl(reg, reg); // movsxw 3819 } else { 3820 shll(reg, 16); 3821 sarl(reg, 16); 3822 } 3823 } 3824 3825 void MacroAssembler::testl(Register dst, AddressLiteral src) { 3826 assert(reachable(src), "Address should be reachable"); 3827 testl(dst, as_Address(src)); 3828 } 3829 3830 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) { 3831 int dst_enc = dst->encoding(); 3832 int src_enc = src->encoding(); 3833 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 3834 Assembler::pcmpeqb(dst, src); 3835 } else if ((dst_enc < 16) && (src_enc < 16)) { 3836 Assembler::pcmpeqb(dst, src); 3837 } else if (src_enc < 16) { 3838 subptr(rsp, 64); 3839 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3840 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 3841 Assembler::pcmpeqb(xmm0, src); 3842 movdqu(dst, xmm0); 3843 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3844 addptr(rsp, 64); 3845 } else if (dst_enc < 16) { 3846 subptr(rsp, 64); 3847 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3848 evmovdqul(xmm0, src, Assembler::AVX_512bit); 3849 Assembler::pcmpeqb(dst, xmm0); 3850 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3851 addptr(rsp, 64); 3852 } else { 3853 subptr(rsp, 64); 3854 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3855 subptr(rsp, 64); 3856 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 3857 movdqu(xmm0, src); 3858 movdqu(xmm1, dst); 3859 Assembler::pcmpeqb(xmm1, xmm0); 3860 movdqu(dst, xmm1); 3861 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 3862 addptr(rsp, 64); 3863 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3864 addptr(rsp, 64); 3865 } 3866 } 3867 3868 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) { 3869 int dst_enc = dst->encoding(); 3870 int src_enc = src->encoding(); 3871 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 3872 Assembler::pcmpeqw(dst, src); 3873 } else if ((dst_enc < 16) && (src_enc < 16)) { 3874 Assembler::pcmpeqw(dst, src); 3875 } else if (src_enc < 16) { 3876 subptr(rsp, 64); 3877 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3878 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 3879 Assembler::pcmpeqw(xmm0, src); 3880 movdqu(dst, xmm0); 3881 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3882 addptr(rsp, 64); 3883 } else if (dst_enc < 16) { 3884 subptr(rsp, 64); 3885 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3886 evmovdqul(xmm0, src, Assembler::AVX_512bit); 3887 Assembler::pcmpeqw(dst, xmm0); 3888 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3889 addptr(rsp, 64); 3890 } else { 3891 subptr(rsp, 64); 3892 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3893 subptr(rsp, 64); 3894 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 3895 movdqu(xmm0, src); 3896 movdqu(xmm1, dst); 3897 Assembler::pcmpeqw(xmm1, xmm0); 3898 movdqu(dst, xmm1); 3899 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 3900 addptr(rsp, 64); 3901 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3902 addptr(rsp, 64); 3903 } 3904 } 3905 3906 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) { 3907 int dst_enc = dst->encoding(); 3908 if (dst_enc < 16) { 3909 Assembler::pcmpestri(dst, src, imm8); 3910 } else { 3911 subptr(rsp, 64); 3912 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3913 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 3914 Assembler::pcmpestri(xmm0, src, imm8); 3915 movdqu(dst, xmm0); 3916 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3917 addptr(rsp, 64); 3918 } 3919 } 3920 3921 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) { 3922 int dst_enc = dst->encoding(); 3923 int src_enc = src->encoding(); 3924 if ((dst_enc < 16) && (src_enc < 16)) { 3925 Assembler::pcmpestri(dst, src, imm8); 3926 } else if (src_enc < 16) { 3927 subptr(rsp, 64); 3928 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3929 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 3930 Assembler::pcmpestri(xmm0, src, imm8); 3931 movdqu(dst, xmm0); 3932 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3933 addptr(rsp, 64); 3934 } else if (dst_enc < 16) { 3935 subptr(rsp, 64); 3936 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3937 evmovdqul(xmm0, src, Assembler::AVX_512bit); 3938 Assembler::pcmpestri(dst, xmm0, imm8); 3939 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3940 addptr(rsp, 64); 3941 } else { 3942 subptr(rsp, 64); 3943 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3944 subptr(rsp, 64); 3945 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 3946 movdqu(xmm0, src); 3947 movdqu(xmm1, dst); 3948 Assembler::pcmpestri(xmm1, xmm0, imm8); 3949 movdqu(dst, xmm1); 3950 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 3951 addptr(rsp, 64); 3952 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3953 addptr(rsp, 64); 3954 } 3955 } 3956 3957 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) { 3958 int dst_enc = dst->encoding(); 3959 int src_enc = src->encoding(); 3960 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 3961 Assembler::pmovzxbw(dst, src); 3962 } else if ((dst_enc < 16) && (src_enc < 16)) { 3963 Assembler::pmovzxbw(dst, src); 3964 } else if (src_enc < 16) { 3965 subptr(rsp, 64); 3966 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3967 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 3968 Assembler::pmovzxbw(xmm0, src); 3969 movdqu(dst, xmm0); 3970 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3971 addptr(rsp, 64); 3972 } else if (dst_enc < 16) { 3973 subptr(rsp, 64); 3974 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3975 evmovdqul(xmm0, src, Assembler::AVX_512bit); 3976 Assembler::pmovzxbw(dst, xmm0); 3977 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3978 addptr(rsp, 64); 3979 } else { 3980 subptr(rsp, 64); 3981 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3982 subptr(rsp, 64); 3983 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 3984 movdqu(xmm0, src); 3985 movdqu(xmm1, dst); 3986 Assembler::pmovzxbw(xmm1, xmm0); 3987 movdqu(dst, xmm1); 3988 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 3989 addptr(rsp, 64); 3990 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3991 addptr(rsp, 64); 3992 } 3993 } 3994 3995 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) { 3996 int dst_enc = dst->encoding(); 3997 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 3998 Assembler::pmovzxbw(dst, src); 3999 } else if (dst_enc < 16) { 4000 Assembler::pmovzxbw(dst, src); 4001 } else { 4002 subptr(rsp, 64); 4003 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4004 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4005 Assembler::pmovzxbw(xmm0, src); 4006 movdqu(dst, xmm0); 4007 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4008 addptr(rsp, 64); 4009 } 4010 } 4011 4012 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) { 4013 int src_enc = src->encoding(); 4014 if (src_enc < 16) { 4015 Assembler::pmovmskb(dst, src); 4016 } else { 4017 subptr(rsp, 64); 4018 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4019 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4020 Assembler::pmovmskb(dst, xmm0); 4021 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4022 addptr(rsp, 64); 4023 } 4024 } 4025 4026 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) { 4027 int dst_enc = dst->encoding(); 4028 int src_enc = src->encoding(); 4029 if ((dst_enc < 16) && (src_enc < 16)) { 4030 Assembler::ptest(dst, src); 4031 } else if (src_enc < 16) { 4032 subptr(rsp, 64); 4033 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4034 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4035 Assembler::ptest(xmm0, src); 4036 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4037 addptr(rsp, 64); 4038 } else if (dst_enc < 16) { 4039 subptr(rsp, 64); 4040 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4041 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4042 Assembler::ptest(dst, xmm0); 4043 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4044 addptr(rsp, 64); 4045 } else { 4046 subptr(rsp, 64); 4047 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4048 subptr(rsp, 64); 4049 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4050 movdqu(xmm0, src); 4051 movdqu(xmm1, dst); 4052 Assembler::ptest(xmm1, xmm0); 4053 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4054 addptr(rsp, 64); 4055 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4056 addptr(rsp, 64); 4057 } 4058 } 4059 4060 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) { 4061 if (reachable(src)) { 4062 Assembler::sqrtsd(dst, as_Address(src)); 4063 } else { 4064 lea(rscratch1, src); 4065 Assembler::sqrtsd(dst, Address(rscratch1, 0)); 4066 } 4067 } 4068 4069 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) { 4070 if (reachable(src)) { 4071 Assembler::sqrtss(dst, as_Address(src)); 4072 } else { 4073 lea(rscratch1, src); 4074 Assembler::sqrtss(dst, Address(rscratch1, 0)); 4075 } 4076 } 4077 4078 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) { 4079 if (reachable(src)) { 4080 Assembler::subsd(dst, as_Address(src)); 4081 } else { 4082 lea(rscratch1, src); 4083 Assembler::subsd(dst, Address(rscratch1, 0)); 4084 } 4085 } 4086 4087 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) { 4088 if (reachable(src)) { 4089 Assembler::subss(dst, as_Address(src)); 4090 } else { 4091 lea(rscratch1, src); 4092 Assembler::subss(dst, Address(rscratch1, 0)); 4093 } 4094 } 4095 4096 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) { 4097 if (reachable(src)) { 4098 Assembler::ucomisd(dst, as_Address(src)); 4099 } else { 4100 lea(rscratch1, src); 4101 Assembler::ucomisd(dst, Address(rscratch1, 0)); 4102 } 4103 } 4104 4105 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) { 4106 if (reachable(src)) { 4107 Assembler::ucomiss(dst, as_Address(src)); 4108 } else { 4109 lea(rscratch1, src); 4110 Assembler::ucomiss(dst, Address(rscratch1, 0)); 4111 } 4112 } 4113 4114 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) { 4115 // Used in sign-bit flipping with aligned address. 4116 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); 4117 if (reachable(src)) { 4118 Assembler::xorpd(dst, as_Address(src)); 4119 } else { 4120 lea(rscratch1, src); 4121 Assembler::xorpd(dst, Address(rscratch1, 0)); 4122 } 4123 } 4124 4125 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) { 4126 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) { 4127 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit); 4128 } 4129 else { 4130 Assembler::xorpd(dst, src); 4131 } 4132 } 4133 4134 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) { 4135 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) { 4136 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit); 4137 } else { 4138 Assembler::xorps(dst, src); 4139 } 4140 } 4141 4142 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) { 4143 // Used in sign-bit flipping with aligned address. 4144 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); 4145 if (reachable(src)) { 4146 Assembler::xorps(dst, as_Address(src)); 4147 } else { 4148 lea(rscratch1, src); 4149 Assembler::xorps(dst, Address(rscratch1, 0)); 4150 } 4151 } 4152 4153 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src) { 4154 // Used in sign-bit flipping with aligned address. 4155 bool aligned_adr = (((intptr_t)src.target() & 15) == 0); 4156 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes"); 4157 if (reachable(src)) { 4158 Assembler::pshufb(dst, as_Address(src)); 4159 } else { 4160 lea(rscratch1, src); 4161 Assembler::pshufb(dst, Address(rscratch1, 0)); 4162 } 4163 } 4164 4165 // AVX 3-operands instructions 4166 4167 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 4168 if (reachable(src)) { 4169 vaddsd(dst, nds, as_Address(src)); 4170 } else { 4171 lea(rscratch1, src); 4172 vaddsd(dst, nds, Address(rscratch1, 0)); 4173 } 4174 } 4175 4176 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 4177 if (reachable(src)) { 4178 vaddss(dst, nds, as_Address(src)); 4179 } else { 4180 lea(rscratch1, src); 4181 vaddss(dst, nds, Address(rscratch1, 0)); 4182 } 4183 } 4184 4185 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) { 4186 int dst_enc = dst->encoding(); 4187 int nds_enc = nds->encoding(); 4188 int src_enc = src->encoding(); 4189 if ((dst_enc < 16) && (nds_enc < 16)) { 4190 vandps(dst, nds, negate_field, vector_len); 4191 } else if ((src_enc < 16) && (dst_enc < 16)) { 4192 evmovdqul(src, nds, Assembler::AVX_512bit); 4193 vandps(dst, src, negate_field, vector_len); 4194 } else if (src_enc < 16) { 4195 evmovdqul(src, nds, Assembler::AVX_512bit); 4196 vandps(src, src, negate_field, vector_len); 4197 evmovdqul(dst, src, Assembler::AVX_512bit); 4198 } else if (dst_enc < 16) { 4199 evmovdqul(src, xmm0, Assembler::AVX_512bit); 4200 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4201 vandps(dst, xmm0, negate_field, vector_len); 4202 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4203 } else { 4204 if (src_enc != dst_enc) { 4205 evmovdqul(src, xmm0, Assembler::AVX_512bit); 4206 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4207 vandps(xmm0, xmm0, negate_field, vector_len); 4208 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4209 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4210 } else { 4211 subptr(rsp, 64); 4212 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4213 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4214 vandps(xmm0, xmm0, negate_field, vector_len); 4215 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4216 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4217 addptr(rsp, 64); 4218 } 4219 } 4220 } 4221 4222 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) { 4223 int dst_enc = dst->encoding(); 4224 int nds_enc = nds->encoding(); 4225 int src_enc = src->encoding(); 4226 if ((dst_enc < 16) && (nds_enc < 16)) { 4227 vandpd(dst, nds, negate_field, vector_len); 4228 } else if ((src_enc < 16) && (dst_enc < 16)) { 4229 evmovdqul(src, nds, Assembler::AVX_512bit); 4230 vandpd(dst, src, negate_field, vector_len); 4231 } else if (src_enc < 16) { 4232 evmovdqul(src, nds, Assembler::AVX_512bit); 4233 vandpd(src, src, negate_field, vector_len); 4234 evmovdqul(dst, src, Assembler::AVX_512bit); 4235 } else if (dst_enc < 16) { 4236 evmovdqul(src, xmm0, Assembler::AVX_512bit); 4237 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4238 vandpd(dst, xmm0, negate_field, vector_len); 4239 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4240 } else { 4241 if (src_enc != dst_enc) { 4242 evmovdqul(src, xmm0, Assembler::AVX_512bit); 4243 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4244 vandpd(xmm0, xmm0, negate_field, vector_len); 4245 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4246 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4247 } else { 4248 subptr(rsp, 64); 4249 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4250 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4251 vandpd(xmm0, xmm0, negate_field, vector_len); 4252 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4253 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4254 addptr(rsp, 64); 4255 } 4256 } 4257 } 4258 4259 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4260 int dst_enc = dst->encoding(); 4261 int nds_enc = nds->encoding(); 4262 int src_enc = src->encoding(); 4263 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4264 Assembler::vpaddb(dst, nds, src, vector_len); 4265 } else if ((dst_enc < 16) && (src_enc < 16)) { 4266 Assembler::vpaddb(dst, dst, src, vector_len); 4267 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4268 // use nds as scratch for src 4269 evmovdqul(nds, src, Assembler::AVX_512bit); 4270 Assembler::vpaddb(dst, dst, nds, vector_len); 4271 } else if ((src_enc < 16) && (nds_enc < 16)) { 4272 // use nds as scratch for dst 4273 evmovdqul(nds, dst, Assembler::AVX_512bit); 4274 Assembler::vpaddb(nds, nds, src, vector_len); 4275 evmovdqul(dst, nds, Assembler::AVX_512bit); 4276 } else if (dst_enc < 16) { 4277 // use nds as scatch for xmm0 to hold src 4278 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4279 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4280 Assembler::vpaddb(dst, dst, xmm0, vector_len); 4281 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4282 } else { 4283 // worse case scenario, all regs are in the upper bank 4284 subptr(rsp, 64); 4285 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4286 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4287 evmovdqul(xmm1, src, Assembler::AVX_512bit); 4288 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4289 Assembler::vpaddb(xmm0, xmm0, xmm1, vector_len); 4290 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4291 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4292 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4293 addptr(rsp, 64); 4294 } 4295 } 4296 4297 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4298 int dst_enc = dst->encoding(); 4299 int nds_enc = nds->encoding(); 4300 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4301 Assembler::vpaddb(dst, nds, src, vector_len); 4302 } else if (dst_enc < 16) { 4303 Assembler::vpaddb(dst, dst, src, vector_len); 4304 } else if (nds_enc < 16) { 4305 // implies dst_enc in upper bank with src as scratch 4306 evmovdqul(nds, dst, Assembler::AVX_512bit); 4307 Assembler::vpaddb(nds, nds, src, vector_len); 4308 evmovdqul(dst, nds, Assembler::AVX_512bit); 4309 } else { 4310 // worse case scenario, all regs in upper bank 4311 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4312 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4313 Assembler::vpaddb(xmm0, xmm0, src, vector_len); 4314 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4315 } 4316 } 4317 4318 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4319 int dst_enc = dst->encoding(); 4320 int nds_enc = nds->encoding(); 4321 int src_enc = src->encoding(); 4322 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4323 Assembler::vpaddw(dst, nds, src, vector_len); 4324 } else if ((dst_enc < 16) && (src_enc < 16)) { 4325 Assembler::vpaddw(dst, dst, src, vector_len); 4326 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4327 // use nds as scratch for src 4328 evmovdqul(nds, src, Assembler::AVX_512bit); 4329 Assembler::vpaddw(dst, dst, nds, vector_len); 4330 } else if ((src_enc < 16) && (nds_enc < 16)) { 4331 // use nds as scratch for dst 4332 evmovdqul(nds, dst, Assembler::AVX_512bit); 4333 Assembler::vpaddw(nds, nds, src, vector_len); 4334 evmovdqul(dst, nds, Assembler::AVX_512bit); 4335 } else if (dst_enc < 16) { 4336 // use nds as scatch for xmm0 to hold src 4337 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4338 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4339 Assembler::vpaddw(dst, dst, xmm0, vector_len); 4340 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4341 } else { 4342 // worse case scenario, all regs are in the upper bank 4343 subptr(rsp, 64); 4344 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4345 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4346 evmovdqul(xmm1, src, Assembler::AVX_512bit); 4347 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4348 Assembler::vpaddw(xmm0, xmm0, xmm1, vector_len); 4349 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4350 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4351 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4352 addptr(rsp, 64); 4353 } 4354 } 4355 4356 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4357 int dst_enc = dst->encoding(); 4358 int nds_enc = nds->encoding(); 4359 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4360 Assembler::vpaddw(dst, nds, src, vector_len); 4361 } else if (dst_enc < 16) { 4362 Assembler::vpaddw(dst, dst, src, vector_len); 4363 } else if (nds_enc < 16) { 4364 // implies dst_enc in upper bank with src as scratch 4365 evmovdqul(nds, dst, Assembler::AVX_512bit); 4366 Assembler::vpaddw(nds, nds, src, vector_len); 4367 evmovdqul(dst, nds, Assembler::AVX_512bit); 4368 } else { 4369 // worse case scenario, all regs in upper bank 4370 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4371 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4372 Assembler::vpaddw(xmm0, xmm0, src, vector_len); 4373 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4374 } 4375 } 4376 4377 void MacroAssembler::vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) { 4378 if (reachable(src)) { 4379 Assembler::vpand(dst, nds, as_Address(src), vector_len); 4380 } else { 4381 lea(rscratch1, src); 4382 Assembler::vpand(dst, nds, Address(rscratch1, 0), vector_len); 4383 } 4384 } 4385 4386 void MacroAssembler::vpbroadcastw(XMMRegister dst, XMMRegister src) { 4387 int dst_enc = dst->encoding(); 4388 int src_enc = src->encoding(); 4389 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4390 Assembler::vpbroadcastw(dst, src); 4391 } else if ((dst_enc < 16) && (src_enc < 16)) { 4392 Assembler::vpbroadcastw(dst, src); 4393 } else if (src_enc < 16) { 4394 subptr(rsp, 64); 4395 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4396 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4397 Assembler::vpbroadcastw(xmm0, src); 4398 movdqu(dst, xmm0); 4399 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4400 addptr(rsp, 64); 4401 } else if (dst_enc < 16) { 4402 subptr(rsp, 64); 4403 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4404 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4405 Assembler::vpbroadcastw(dst, xmm0); 4406 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4407 addptr(rsp, 64); 4408 } else { 4409 subptr(rsp, 64); 4410 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4411 subptr(rsp, 64); 4412 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4413 movdqu(xmm0, src); 4414 movdqu(xmm1, dst); 4415 Assembler::vpbroadcastw(xmm1, xmm0); 4416 movdqu(dst, xmm1); 4417 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4418 addptr(rsp, 64); 4419 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4420 addptr(rsp, 64); 4421 } 4422 } 4423 4424 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4425 int dst_enc = dst->encoding(); 4426 int nds_enc = nds->encoding(); 4427 int src_enc = src->encoding(); 4428 assert(dst_enc == nds_enc, ""); 4429 if ((dst_enc < 16) && (src_enc < 16)) { 4430 Assembler::vpcmpeqb(dst, nds, src, vector_len); 4431 } else if (src_enc < 16) { 4432 subptr(rsp, 64); 4433 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4434 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4435 Assembler::vpcmpeqb(xmm0, xmm0, src, vector_len); 4436 movdqu(dst, xmm0); 4437 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4438 addptr(rsp, 64); 4439 } else if (dst_enc < 16) { 4440 subptr(rsp, 64); 4441 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4442 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4443 Assembler::vpcmpeqb(dst, dst, xmm0, vector_len); 4444 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4445 addptr(rsp, 64); 4446 } else { 4447 subptr(rsp, 64); 4448 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4449 subptr(rsp, 64); 4450 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4451 movdqu(xmm0, src); 4452 movdqu(xmm1, dst); 4453 Assembler::vpcmpeqb(xmm1, xmm1, xmm0, vector_len); 4454 movdqu(dst, xmm1); 4455 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4456 addptr(rsp, 64); 4457 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4458 addptr(rsp, 64); 4459 } 4460 } 4461 4462 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4463 int dst_enc = dst->encoding(); 4464 int nds_enc = nds->encoding(); 4465 int src_enc = src->encoding(); 4466 assert(dst_enc == nds_enc, ""); 4467 if ((dst_enc < 16) && (src_enc < 16)) { 4468 Assembler::vpcmpeqw(dst, nds, src, vector_len); 4469 } else if (src_enc < 16) { 4470 subptr(rsp, 64); 4471 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4472 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4473 Assembler::vpcmpeqw(xmm0, xmm0, src, vector_len); 4474 movdqu(dst, xmm0); 4475 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4476 addptr(rsp, 64); 4477 } else if (dst_enc < 16) { 4478 subptr(rsp, 64); 4479 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4480 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4481 Assembler::vpcmpeqw(dst, dst, xmm0, vector_len); 4482 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4483 addptr(rsp, 64); 4484 } else { 4485 subptr(rsp, 64); 4486 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4487 subptr(rsp, 64); 4488 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4489 movdqu(xmm0, src); 4490 movdqu(xmm1, dst); 4491 Assembler::vpcmpeqw(xmm1, xmm1, xmm0, vector_len); 4492 movdqu(dst, xmm1); 4493 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4494 addptr(rsp, 64); 4495 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4496 addptr(rsp, 64); 4497 } 4498 } 4499 4500 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) { 4501 int dst_enc = dst->encoding(); 4502 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4503 Assembler::vpmovzxbw(dst, src, vector_len); 4504 } else if (dst_enc < 16) { 4505 Assembler::vpmovzxbw(dst, src, vector_len); 4506 } else { 4507 subptr(rsp, 64); 4508 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4509 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4510 Assembler::vpmovzxbw(xmm0, src, vector_len); 4511 movdqu(dst, xmm0); 4512 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4513 addptr(rsp, 64); 4514 } 4515 } 4516 4517 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src) { 4518 int src_enc = src->encoding(); 4519 if (src_enc < 16) { 4520 Assembler::vpmovmskb(dst, src); 4521 } else { 4522 subptr(rsp, 64); 4523 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4524 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4525 Assembler::vpmovmskb(dst, xmm0); 4526 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4527 addptr(rsp, 64); 4528 } 4529 } 4530 4531 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4532 int dst_enc = dst->encoding(); 4533 int nds_enc = nds->encoding(); 4534 int src_enc = src->encoding(); 4535 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4536 Assembler::vpmullw(dst, nds, src, vector_len); 4537 } else if ((dst_enc < 16) && (src_enc < 16)) { 4538 Assembler::vpmullw(dst, dst, src, vector_len); 4539 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4540 // use nds as scratch for src 4541 evmovdqul(nds, src, Assembler::AVX_512bit); 4542 Assembler::vpmullw(dst, dst, nds, vector_len); 4543 } else if ((src_enc < 16) && (nds_enc < 16)) { 4544 // use nds as scratch for dst 4545 evmovdqul(nds, dst, Assembler::AVX_512bit); 4546 Assembler::vpmullw(nds, nds, src, vector_len); 4547 evmovdqul(dst, nds, Assembler::AVX_512bit); 4548 } else if (dst_enc < 16) { 4549 // use nds as scatch for xmm0 to hold src 4550 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4551 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4552 Assembler::vpmullw(dst, dst, xmm0, vector_len); 4553 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4554 } else { 4555 // worse case scenario, all regs are in the upper bank 4556 subptr(rsp, 64); 4557 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4558 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4559 evmovdqul(xmm1, src, Assembler::AVX_512bit); 4560 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4561 Assembler::vpmullw(xmm0, xmm0, xmm1, vector_len); 4562 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4563 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4564 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4565 addptr(rsp, 64); 4566 } 4567 } 4568 4569 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4570 int dst_enc = dst->encoding(); 4571 int nds_enc = nds->encoding(); 4572 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4573 Assembler::vpmullw(dst, nds, src, vector_len); 4574 } else if (dst_enc < 16) { 4575 Assembler::vpmullw(dst, dst, src, vector_len); 4576 } else if (nds_enc < 16) { 4577 // implies dst_enc in upper bank with src as scratch 4578 evmovdqul(nds, dst, Assembler::AVX_512bit); 4579 Assembler::vpmullw(nds, nds, src, vector_len); 4580 evmovdqul(dst, nds, Assembler::AVX_512bit); 4581 } else { 4582 // worse case scenario, all regs in upper bank 4583 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4584 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4585 Assembler::vpmullw(xmm0, xmm0, src, vector_len); 4586 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4587 } 4588 } 4589 4590 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4591 int dst_enc = dst->encoding(); 4592 int nds_enc = nds->encoding(); 4593 int src_enc = src->encoding(); 4594 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4595 Assembler::vpsubb(dst, nds, src, vector_len); 4596 } else if ((dst_enc < 16) && (src_enc < 16)) { 4597 Assembler::vpsubb(dst, dst, src, vector_len); 4598 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4599 // use nds as scratch for src 4600 evmovdqul(nds, src, Assembler::AVX_512bit); 4601 Assembler::vpsubb(dst, dst, nds, vector_len); 4602 } else if ((src_enc < 16) && (nds_enc < 16)) { 4603 // use nds as scratch for dst 4604 evmovdqul(nds, dst, Assembler::AVX_512bit); 4605 Assembler::vpsubb(nds, nds, src, vector_len); 4606 evmovdqul(dst, nds, Assembler::AVX_512bit); 4607 } else if (dst_enc < 16) { 4608 // use nds as scatch for xmm0 to hold src 4609 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4610 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4611 Assembler::vpsubb(dst, dst, xmm0, vector_len); 4612 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4613 } else { 4614 // worse case scenario, all regs are in the upper bank 4615 subptr(rsp, 64); 4616 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4617 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4618 evmovdqul(xmm1, src, Assembler::AVX_512bit); 4619 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4620 Assembler::vpsubb(xmm0, xmm0, xmm1, vector_len); 4621 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4622 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4623 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4624 addptr(rsp, 64); 4625 } 4626 } 4627 4628 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4629 int dst_enc = dst->encoding(); 4630 int nds_enc = nds->encoding(); 4631 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4632 Assembler::vpsubb(dst, nds, src, vector_len); 4633 } else if (dst_enc < 16) { 4634 Assembler::vpsubb(dst, dst, src, vector_len); 4635 } else if (nds_enc < 16) { 4636 // implies dst_enc in upper bank with src as scratch 4637 evmovdqul(nds, dst, Assembler::AVX_512bit); 4638 Assembler::vpsubb(nds, nds, src, vector_len); 4639 evmovdqul(dst, nds, Assembler::AVX_512bit); 4640 } else { 4641 // worse case scenario, all regs in upper bank 4642 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4643 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4644 Assembler::vpsubw(xmm0, xmm0, src, vector_len); 4645 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4646 } 4647 } 4648 4649 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4650 int dst_enc = dst->encoding(); 4651 int nds_enc = nds->encoding(); 4652 int src_enc = src->encoding(); 4653 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4654 Assembler::vpsubw(dst, nds, src, vector_len); 4655 } else if ((dst_enc < 16) && (src_enc < 16)) { 4656 Assembler::vpsubw(dst, dst, src, vector_len); 4657 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4658 // use nds as scratch for src 4659 evmovdqul(nds, src, Assembler::AVX_512bit); 4660 Assembler::vpsubw(dst, dst, nds, vector_len); 4661 } else if ((src_enc < 16) && (nds_enc < 16)) { 4662 // use nds as scratch for dst 4663 evmovdqul(nds, dst, Assembler::AVX_512bit); 4664 Assembler::vpsubw(nds, nds, src, vector_len); 4665 evmovdqul(dst, nds, Assembler::AVX_512bit); 4666 } else if (dst_enc < 16) { 4667 // use nds as scatch for xmm0 to hold src 4668 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4669 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4670 Assembler::vpsubw(dst, dst, xmm0, vector_len); 4671 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4672 } else { 4673 // worse case scenario, all regs are in the upper bank 4674 subptr(rsp, 64); 4675 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4676 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4677 evmovdqul(xmm1, src, Assembler::AVX_512bit); 4678 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4679 Assembler::vpsubw(xmm0, xmm0, xmm1, vector_len); 4680 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4681 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4682 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4683 addptr(rsp, 64); 4684 } 4685 } 4686 4687 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4688 int dst_enc = dst->encoding(); 4689 int nds_enc = nds->encoding(); 4690 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4691 Assembler::vpsubw(dst, nds, src, vector_len); 4692 } else if (dst_enc < 16) { 4693 Assembler::vpsubw(dst, dst, src, vector_len); 4694 } else if (nds_enc < 16) { 4695 // implies dst_enc in upper bank with src as scratch 4696 evmovdqul(nds, dst, Assembler::AVX_512bit); 4697 Assembler::vpsubw(nds, nds, src, vector_len); 4698 evmovdqul(dst, nds, Assembler::AVX_512bit); 4699 } else { 4700 // worse case scenario, all regs in upper bank 4701 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4702 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4703 Assembler::vpsubw(xmm0, xmm0, src, vector_len); 4704 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4705 } 4706 } 4707 4708 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) { 4709 int dst_enc = dst->encoding(); 4710 int nds_enc = nds->encoding(); 4711 int shift_enc = shift->encoding(); 4712 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4713 Assembler::vpsraw(dst, nds, shift, vector_len); 4714 } else if ((dst_enc < 16) && (shift_enc < 16)) { 4715 Assembler::vpsraw(dst, dst, shift, vector_len); 4716 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4717 // use nds_enc as scratch with shift 4718 evmovdqul(nds, shift, Assembler::AVX_512bit); 4719 Assembler::vpsraw(dst, dst, nds, vector_len); 4720 } else if ((shift_enc < 16) && (nds_enc < 16)) { 4721 // use nds as scratch with dst 4722 evmovdqul(nds, dst, Assembler::AVX_512bit); 4723 Assembler::vpsraw(nds, nds, shift, vector_len); 4724 evmovdqul(dst, nds, Assembler::AVX_512bit); 4725 } else if (dst_enc < 16) { 4726 // use nds to save a copy of xmm0 and hold shift 4727 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4728 evmovdqul(xmm0, shift, Assembler::AVX_512bit); 4729 Assembler::vpsraw(dst, dst, xmm0, vector_len); 4730 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4731 } else if (nds_enc < 16) { 4732 // use nds as dest as temps 4733 evmovdqul(nds, dst, Assembler::AVX_512bit); 4734 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4735 evmovdqul(xmm0, shift, Assembler::AVX_512bit); 4736 Assembler::vpsraw(nds, nds, xmm0, vector_len); 4737 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4738 evmovdqul(dst, nds, Assembler::AVX_512bit); 4739 } else { 4740 // worse case scenario, all regs are in the upper bank 4741 subptr(rsp, 64); 4742 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4743 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4744 evmovdqul(xmm1, shift, Assembler::AVX_512bit); 4745 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4746 Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len); 4747 evmovdqul(xmm1, dst, Assembler::AVX_512bit); 4748 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4749 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4750 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4751 addptr(rsp, 64); 4752 } 4753 } 4754 4755 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) { 4756 int dst_enc = dst->encoding(); 4757 int nds_enc = nds->encoding(); 4758 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4759 Assembler::vpsraw(dst, nds, shift, vector_len); 4760 } else if (dst_enc < 16) { 4761 Assembler::vpsraw(dst, dst, shift, vector_len); 4762 } else if (nds_enc < 16) { 4763 // use nds as scratch 4764 evmovdqul(nds, dst, Assembler::AVX_512bit); 4765 Assembler::vpsraw(nds, nds, shift, vector_len); 4766 evmovdqul(dst, nds, Assembler::AVX_512bit); 4767 } else { 4768 // use nds as scratch for xmm0 4769 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4770 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4771 Assembler::vpsraw(xmm0, xmm0, shift, vector_len); 4772 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4773 } 4774 } 4775 4776 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) { 4777 int dst_enc = dst->encoding(); 4778 int nds_enc = nds->encoding(); 4779 int shift_enc = shift->encoding(); 4780 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4781 Assembler::vpsrlw(dst, nds, shift, vector_len); 4782 } else if ((dst_enc < 16) && (shift_enc < 16)) { 4783 Assembler::vpsrlw(dst, dst, shift, vector_len); 4784 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4785 // use nds_enc as scratch with shift 4786 evmovdqul(nds, shift, Assembler::AVX_512bit); 4787 Assembler::vpsrlw(dst, dst, nds, vector_len); 4788 } else if ((shift_enc < 16) && (nds_enc < 16)) { 4789 // use nds as scratch with dst 4790 evmovdqul(nds, dst, Assembler::AVX_512bit); 4791 Assembler::vpsrlw(nds, nds, shift, vector_len); 4792 evmovdqul(dst, nds, Assembler::AVX_512bit); 4793 } else if (dst_enc < 16) { 4794 // use nds to save a copy of xmm0 and hold shift 4795 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4796 evmovdqul(xmm0, shift, Assembler::AVX_512bit); 4797 Assembler::vpsrlw(dst, dst, xmm0, vector_len); 4798 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4799 } else if (nds_enc < 16) { 4800 // use nds as dest as temps 4801 evmovdqul(nds, dst, Assembler::AVX_512bit); 4802 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4803 evmovdqul(xmm0, shift, Assembler::AVX_512bit); 4804 Assembler::vpsrlw(nds, nds, xmm0, vector_len); 4805 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4806 evmovdqul(dst, nds, Assembler::AVX_512bit); 4807 } else { 4808 // worse case scenario, all regs are in the upper bank 4809 subptr(rsp, 64); 4810 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4811 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4812 evmovdqul(xmm1, shift, Assembler::AVX_512bit); 4813 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4814 Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len); 4815 evmovdqul(xmm1, dst, Assembler::AVX_512bit); 4816 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4817 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4818 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4819 addptr(rsp, 64); 4820 } 4821 } 4822 4823 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) { 4824 int dst_enc = dst->encoding(); 4825 int nds_enc = nds->encoding(); 4826 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4827 Assembler::vpsrlw(dst, nds, shift, vector_len); 4828 } else if (dst_enc < 16) { 4829 Assembler::vpsrlw(dst, dst, shift, vector_len); 4830 } else if (nds_enc < 16) { 4831 // use nds as scratch 4832 evmovdqul(nds, dst, Assembler::AVX_512bit); 4833 Assembler::vpsrlw(nds, nds, shift, vector_len); 4834 evmovdqul(dst, nds, Assembler::AVX_512bit); 4835 } else { 4836 // use nds as scratch for xmm0 4837 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4838 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4839 Assembler::vpsrlw(xmm0, xmm0, shift, vector_len); 4840 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4841 } 4842 } 4843 4844 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) { 4845 int dst_enc = dst->encoding(); 4846 int nds_enc = nds->encoding(); 4847 int shift_enc = shift->encoding(); 4848 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4849 Assembler::vpsllw(dst, nds, shift, vector_len); 4850 } else if ((dst_enc < 16) && (shift_enc < 16)) { 4851 Assembler::vpsllw(dst, dst, shift, vector_len); 4852 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4853 // use nds_enc as scratch with shift 4854 evmovdqul(nds, shift, Assembler::AVX_512bit); 4855 Assembler::vpsllw(dst, dst, nds, vector_len); 4856 } else if ((shift_enc < 16) && (nds_enc < 16)) { 4857 // use nds as scratch with dst 4858 evmovdqul(nds, dst, Assembler::AVX_512bit); 4859 Assembler::vpsllw(nds, nds, shift, vector_len); 4860 evmovdqul(dst, nds, Assembler::AVX_512bit); 4861 } else if (dst_enc < 16) { 4862 // use nds to save a copy of xmm0 and hold shift 4863 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4864 evmovdqul(xmm0, shift, Assembler::AVX_512bit); 4865 Assembler::vpsllw(dst, dst, xmm0, vector_len); 4866 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4867 } else if (nds_enc < 16) { 4868 // use nds as dest as temps 4869 evmovdqul(nds, dst, Assembler::AVX_512bit); 4870 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4871 evmovdqul(xmm0, shift, Assembler::AVX_512bit); 4872 Assembler::vpsllw(nds, nds, xmm0, vector_len); 4873 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4874 evmovdqul(dst, nds, Assembler::AVX_512bit); 4875 } else { 4876 // worse case scenario, all regs are in the upper bank 4877 subptr(rsp, 64); 4878 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4879 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4880 evmovdqul(xmm1, shift, Assembler::AVX_512bit); 4881 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4882 Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len); 4883 evmovdqul(xmm1, dst, Assembler::AVX_512bit); 4884 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4885 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4886 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4887 addptr(rsp, 64); 4888 } 4889 } 4890 4891 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) { 4892 int dst_enc = dst->encoding(); 4893 int nds_enc = nds->encoding(); 4894 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4895 Assembler::vpsllw(dst, nds, shift, vector_len); 4896 } else if (dst_enc < 16) { 4897 Assembler::vpsllw(dst, dst, shift, vector_len); 4898 } else if (nds_enc < 16) { 4899 // use nds as scratch 4900 evmovdqul(nds, dst, Assembler::AVX_512bit); 4901 Assembler::vpsllw(nds, nds, shift, vector_len); 4902 evmovdqul(dst, nds, Assembler::AVX_512bit); 4903 } else { 4904 // use nds as scratch for xmm0 4905 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4906 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4907 Assembler::vpsllw(xmm0, xmm0, shift, vector_len); 4908 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4909 } 4910 } 4911 4912 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) { 4913 int dst_enc = dst->encoding(); 4914 int src_enc = src->encoding(); 4915 if ((dst_enc < 16) && (src_enc < 16)) { 4916 Assembler::vptest(dst, src); 4917 } else if (src_enc < 16) { 4918 subptr(rsp, 64); 4919 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4920 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4921 Assembler::vptest(xmm0, src); 4922 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4923 addptr(rsp, 64); 4924 } else if (dst_enc < 16) { 4925 subptr(rsp, 64); 4926 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4927 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4928 Assembler::vptest(dst, xmm0); 4929 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4930 addptr(rsp, 64); 4931 } else { 4932 subptr(rsp, 64); 4933 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4934 subptr(rsp, 64); 4935 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4936 movdqu(xmm0, src); 4937 movdqu(xmm1, dst); 4938 Assembler::vptest(xmm1, xmm0); 4939 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4940 addptr(rsp, 64); 4941 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4942 addptr(rsp, 64); 4943 } 4944 } 4945 4946 // This instruction exists within macros, ergo we cannot control its input 4947 // when emitted through those patterns. 4948 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) { 4949 if (VM_Version::supports_avx512nobw()) { 4950 int dst_enc = dst->encoding(); 4951 int src_enc = src->encoding(); 4952 if (dst_enc == src_enc) { 4953 if (dst_enc < 16) { 4954 Assembler::punpcklbw(dst, src); 4955 } else { 4956 subptr(rsp, 64); 4957 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4958 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4959 Assembler::punpcklbw(xmm0, xmm0); 4960 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4961 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4962 addptr(rsp, 64); 4963 } 4964 } else { 4965 if ((src_enc < 16) && (dst_enc < 16)) { 4966 Assembler::punpcklbw(dst, src); 4967 } else if (src_enc < 16) { 4968 subptr(rsp, 64); 4969 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4970 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4971 Assembler::punpcklbw(xmm0, src); 4972 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4973 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4974 addptr(rsp, 64); 4975 } else if (dst_enc < 16) { 4976 subptr(rsp, 64); 4977 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4978 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4979 Assembler::punpcklbw(dst, xmm0); 4980 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4981 addptr(rsp, 64); 4982 } else { 4983 subptr(rsp, 64); 4984 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4985 subptr(rsp, 64); 4986 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4987 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4988 evmovdqul(xmm1, src, Assembler::AVX_512bit); 4989 Assembler::punpcklbw(xmm0, xmm1); 4990 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4991 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4992 addptr(rsp, 64); 4993 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4994 addptr(rsp, 64); 4995 } 4996 } 4997 } else { 4998 Assembler::punpcklbw(dst, src); 4999 } 5000 } 5001 5002 void MacroAssembler::pshufd(XMMRegister dst, Address src, int mode) { 5003 if (VM_Version::supports_avx512vl()) { 5004 Assembler::pshufd(dst, src, mode); 5005 } else { 5006 int dst_enc = dst->encoding(); 5007 if (dst_enc < 16) { 5008 Assembler::pshufd(dst, src, mode); 5009 } else { 5010 subptr(rsp, 64); 5011 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 5012 Assembler::pshufd(xmm0, src, mode); 5013 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 5014 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 5015 addptr(rsp, 64); 5016 } 5017 } 5018 } 5019 5020 // This instruction exists within macros, ergo we cannot control its input 5021 // when emitted through those patterns. 5022 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) { 5023 if (VM_Version::supports_avx512nobw()) { 5024 int dst_enc = dst->encoding(); 5025 int src_enc = src->encoding(); 5026 if (dst_enc == src_enc) { 5027 if (dst_enc < 16) { 5028 Assembler::pshuflw(dst, src, mode); 5029 } else { 5030 subptr(rsp, 64); 5031 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 5032 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 5033 Assembler::pshuflw(xmm0, xmm0, mode); 5034 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 5035 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 5036 addptr(rsp, 64); 5037 } 5038 } else { 5039 if ((src_enc < 16) && (dst_enc < 16)) { 5040 Assembler::pshuflw(dst, src, mode); 5041 } else if (src_enc < 16) { 5042 subptr(rsp, 64); 5043 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 5044 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 5045 Assembler::pshuflw(xmm0, src, mode); 5046 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 5047 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 5048 addptr(rsp, 64); 5049 } else if (dst_enc < 16) { 5050 subptr(rsp, 64); 5051 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 5052 evmovdqul(xmm0, src, Assembler::AVX_512bit); 5053 Assembler::pshuflw(dst, xmm0, mode); 5054 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 5055 addptr(rsp, 64); 5056 } else { 5057 subptr(rsp, 64); 5058 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 5059 subptr(rsp, 64); 5060 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 5061 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 5062 evmovdqul(xmm1, src, Assembler::AVX_512bit); 5063 Assembler::pshuflw(xmm0, xmm1, mode); 5064 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 5065 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 5066 addptr(rsp, 64); 5067 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 5068 addptr(rsp, 64); 5069 } 5070 } 5071 } else { 5072 Assembler::pshuflw(dst, src, mode); 5073 } 5074 } 5075 5076 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) { 5077 if (reachable(src)) { 5078 vandpd(dst, nds, as_Address(src), vector_len); 5079 } else { 5080 lea(rscratch1, src); 5081 vandpd(dst, nds, Address(rscratch1, 0), vector_len); 5082 } 5083 } 5084 5085 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) { 5086 if (reachable(src)) { 5087 vandps(dst, nds, as_Address(src), vector_len); 5088 } else { 5089 lea(rscratch1, src); 5090 vandps(dst, nds, Address(rscratch1, 0), vector_len); 5091 } 5092 } 5093 5094 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 5095 if (reachable(src)) { 5096 vdivsd(dst, nds, as_Address(src)); 5097 } else { 5098 lea(rscratch1, src); 5099 vdivsd(dst, nds, Address(rscratch1, 0)); 5100 } 5101 } 5102 5103 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 5104 if (reachable(src)) { 5105 vdivss(dst, nds, as_Address(src)); 5106 } else { 5107 lea(rscratch1, src); 5108 vdivss(dst, nds, Address(rscratch1, 0)); 5109 } 5110 } 5111 5112 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 5113 if (reachable(src)) { 5114 vmulsd(dst, nds, as_Address(src)); 5115 } else { 5116 lea(rscratch1, src); 5117 vmulsd(dst, nds, Address(rscratch1, 0)); 5118 } 5119 } 5120 5121 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 5122 if (reachable(src)) { 5123 vmulss(dst, nds, as_Address(src)); 5124 } else { 5125 lea(rscratch1, src); 5126 vmulss(dst, nds, Address(rscratch1, 0)); 5127 } 5128 } 5129 5130 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 5131 if (reachable(src)) { 5132 vsubsd(dst, nds, as_Address(src)); 5133 } else { 5134 lea(rscratch1, src); 5135 vsubsd(dst, nds, Address(rscratch1, 0)); 5136 } 5137 } 5138 5139 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 5140 if (reachable(src)) { 5141 vsubss(dst, nds, as_Address(src)); 5142 } else { 5143 lea(rscratch1, src); 5144 vsubss(dst, nds, Address(rscratch1, 0)); 5145 } 5146 } 5147 5148 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 5149 int nds_enc = nds->encoding(); 5150 int dst_enc = dst->encoding(); 5151 bool dst_upper_bank = (dst_enc > 15); 5152 bool nds_upper_bank = (nds_enc > 15); 5153 if (VM_Version::supports_avx512novl() && 5154 (nds_upper_bank || dst_upper_bank)) { 5155 if (dst_upper_bank) { 5156 subptr(rsp, 64); 5157 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 5158 movflt(xmm0, nds); 5159 vxorps(xmm0, xmm0, src, Assembler::AVX_128bit); 5160 movflt(dst, xmm0); 5161 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 5162 addptr(rsp, 64); 5163 } else { 5164 movflt(dst, nds); 5165 vxorps(dst, dst, src, Assembler::AVX_128bit); 5166 } 5167 } else { 5168 vxorps(dst, nds, src, Assembler::AVX_128bit); 5169 } 5170 } 5171 5172 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 5173 int nds_enc = nds->encoding(); 5174 int dst_enc = dst->encoding(); 5175 bool dst_upper_bank = (dst_enc > 15); 5176 bool nds_upper_bank = (nds_enc > 15); 5177 if (VM_Version::supports_avx512novl() && 5178 (nds_upper_bank || dst_upper_bank)) { 5179 if (dst_upper_bank) { 5180 subptr(rsp, 64); 5181 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 5182 movdbl(xmm0, nds); 5183 vxorpd(xmm0, xmm0, src, Assembler::AVX_128bit); 5184 movdbl(dst, xmm0); 5185 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 5186 addptr(rsp, 64); 5187 } else { 5188 movdbl(dst, nds); 5189 vxorpd(dst, dst, src, Assembler::AVX_128bit); 5190 } 5191 } else { 5192 vxorpd(dst, nds, src, Assembler::AVX_128bit); 5193 } 5194 } 5195 5196 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) { 5197 if (reachable(src)) { 5198 vxorpd(dst, nds, as_Address(src), vector_len); 5199 } else { 5200 lea(rscratch1, src); 5201 vxorpd(dst, nds, Address(rscratch1, 0), vector_len); 5202 } 5203 } 5204 5205 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) { 5206 if (reachable(src)) { 5207 vxorps(dst, nds, as_Address(src), vector_len); 5208 } else { 5209 lea(rscratch1, src); 5210 vxorps(dst, nds, Address(rscratch1, 0), vector_len); 5211 } 5212 } 5213 5214 5215 void MacroAssembler::resolve_jobject(Register value, 5216 Register thread, 5217 Register tmp) { 5218 assert_different_registers(value, thread, tmp); 5219 Label done, not_weak; 5220 testptr(value, value); 5221 jcc(Assembler::zero, done); // Use NULL as-is. 5222 testptr(value, JNIHandles::weak_tag_mask); // Test for jweak tag. 5223 jcc(Assembler::zero, not_weak); 5224 // Resolve jweak. 5225 movptr(value, Address(value, -JNIHandles::weak_tag_value)); 5226 verify_oop(value); 5227 #if INCLUDE_ALL_GCS 5228 if (UseG1GC) { 5229 g1_write_barrier_pre(noreg /* obj */, 5230 value /* pre_val */, 5231 thread /* thread */, 5232 tmp /* tmp */, 5233 true /* tosca_live */, 5234 true /* expand_call */); 5235 } 5236 #endif // INCLUDE_ALL_GCS 5237 jmp(done); 5238 bind(not_weak); 5239 // Resolve (untagged) jobject. 5240 movptr(value, Address(value, 0)); 5241 verify_oop(value); 5242 bind(done); 5243 } 5244 5245 void MacroAssembler::clear_jweak_tag(Register possibly_jweak) { 5246 const int32_t inverted_jweak_mask = ~static_cast<int32_t>(JNIHandles::weak_tag_mask); 5247 STATIC_ASSERT(inverted_jweak_mask == -2); // otherwise check this code 5248 // The inverted mask is sign-extended 5249 andptr(possibly_jweak, inverted_jweak_mask); 5250 } 5251 5252 ////////////////////////////////////////////////////////////////////////////////// 5253 #if INCLUDE_ALL_GCS 5254 5255 void MacroAssembler::g1_write_barrier_pre(Register obj, 5256 Register pre_val, 5257 Register thread, 5258 Register tmp, 5259 bool tosca_live, 5260 bool expand_call) { 5261 5262 // If expand_call is true then we expand the call_VM_leaf macro 5263 // directly to skip generating the check by 5264 // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp. 5265 5266 #ifdef _LP64 5267 assert(thread == r15_thread, "must be"); 5268 #endif // _LP64 5269 5270 Label done; 5271 Label runtime; 5272 5273 assert(pre_val != noreg, "check this code"); 5274 5275 if (obj != noreg) { 5276 assert_different_registers(obj, pre_val, tmp); 5277 assert(pre_val != rax, "check this code"); 5278 } 5279 5280 Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() + 5281 SATBMarkQueue::byte_offset_of_active())); 5282 Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() + 5283 SATBMarkQueue::byte_offset_of_index())); 5284 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() + 5285 SATBMarkQueue::byte_offset_of_buf())); 5286 5287 5288 // Is marking active? 5289 if (in_bytes(SATBMarkQueue::byte_width_of_active()) == 4) { 5290 cmpl(in_progress, 0); 5291 } else { 5292 assert(in_bytes(SATBMarkQueue::byte_width_of_active()) == 1, "Assumption"); 5293 cmpb(in_progress, 0); 5294 } 5295 jcc(Assembler::equal, done); 5296 5297 // Do we need to load the previous value? 5298 if (obj != noreg) { 5299 load_heap_oop(pre_val, Address(obj, 0)); 5300 } 5301 5302 // Is the previous value null? 5303 cmpptr(pre_val, (int32_t) NULL_WORD); 5304 jcc(Assembler::equal, done); 5305 5306 // Can we store original value in the thread's buffer? 5307 // Is index == 0? 5308 // (The index field is typed as size_t.) 5309 5310 movptr(tmp, index); // tmp := *index_adr 5311 cmpptr(tmp, 0); // tmp == 0? 5312 jcc(Assembler::equal, runtime); // If yes, goto runtime 5313 5314 subptr(tmp, wordSize); // tmp := tmp - wordSize 5315 movptr(index, tmp); // *index_adr := tmp 5316 addptr(tmp, buffer); // tmp := tmp + *buffer_adr 5317 5318 // Record the previous value 5319 movptr(Address(tmp, 0), pre_val); 5320 jmp(done); 5321 5322 bind(runtime); 5323 // save the live input values 5324 if(tosca_live) push(rax); 5325 5326 if (obj != noreg && obj != rax) 5327 push(obj); 5328 5329 if (pre_val != rax) 5330 push(pre_val); 5331 5332 // Calling the runtime using the regular call_VM_leaf mechanism generates 5333 // code (generated by InterpreterMacroAssember::call_VM_leaf_base) 5334 // that checks that the *(ebp+frame::interpreter_frame_last_sp) == NULL. 5335 // 5336 // If we care generating the pre-barrier without a frame (e.g. in the 5337 // intrinsified Reference.get() routine) then ebp might be pointing to 5338 // the caller frame and so this check will most likely fail at runtime. 5339 // 5340 // Expanding the call directly bypasses the generation of the check. 5341 // So when we do not have have a full interpreter frame on the stack 5342 // expand_call should be passed true. 5343 5344 NOT_LP64( push(thread); ) 5345 5346 if (expand_call) { 5347 LP64_ONLY( assert(pre_val != c_rarg1, "smashed arg"); ) 5348 pass_arg1(this, thread); 5349 pass_arg0(this, pre_val); 5350 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), 2); 5351 } else { 5352 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), pre_val, thread); 5353 } 5354 5355 NOT_LP64( pop(thread); ) 5356 5357 // save the live input values 5358 if (pre_val != rax) 5359 pop(pre_val); 5360 5361 if (obj != noreg && obj != rax) 5362 pop(obj); 5363 5364 if(tosca_live) pop(rax); 5365 5366 bind(done); 5367 } 5368 5369 void MacroAssembler::g1_write_barrier_post(Register store_addr, 5370 Register new_val, 5371 Register thread, 5372 Register tmp, 5373 Register tmp2) { 5374 #ifdef _LP64 5375 assert(thread == r15_thread, "must be"); 5376 #endif // _LP64 5377 5378 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() + 5379 DirtyCardQueue::byte_offset_of_index())); 5380 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() + 5381 DirtyCardQueue::byte_offset_of_buf())); 5382 5383 CardTableModRefBS* ct = 5384 barrier_set_cast<CardTableModRefBS>(Universe::heap()->barrier_set()); 5385 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); 5386 5387 Label done; 5388 Label runtime; 5389 5390 // Does store cross heap regions? 5391 5392 movptr(tmp, store_addr); 5393 xorptr(tmp, new_val); 5394 shrptr(tmp, HeapRegion::LogOfHRGrainBytes); 5395 jcc(Assembler::equal, done); 5396 5397 // crosses regions, storing NULL? 5398 5399 cmpptr(new_val, (int32_t) NULL_WORD); 5400 jcc(Assembler::equal, done); 5401 5402 // storing region crossing non-NULL, is card already dirty? 5403 5404 const Register card_addr = tmp; 5405 const Register cardtable = tmp2; 5406 5407 movptr(card_addr, store_addr); 5408 shrptr(card_addr, CardTableModRefBS::card_shift); 5409 // Do not use ExternalAddress to load 'byte_map_base', since 'byte_map_base' is NOT 5410 // a valid address and therefore is not properly handled by the relocation code. 5411 movptr(cardtable, (intptr_t)ct->byte_map_base); 5412 addptr(card_addr, cardtable); 5413 5414 cmpb(Address(card_addr, 0), (int)G1SATBCardTableModRefBS::g1_young_card_val()); 5415 jcc(Assembler::equal, done); 5416 5417 membar(Assembler::Membar_mask_bits(Assembler::StoreLoad)); 5418 cmpb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val()); 5419 jcc(Assembler::equal, done); 5420 5421 5422 // storing a region crossing, non-NULL oop, card is clean. 5423 // dirty card and log. 5424 5425 movb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val()); 5426 5427 cmpl(queue_index, 0); 5428 jcc(Assembler::equal, runtime); 5429 subl(queue_index, wordSize); 5430 movptr(tmp2, buffer); 5431 #ifdef _LP64 5432 movslq(rscratch1, queue_index); 5433 addq(tmp2, rscratch1); 5434 movq(Address(tmp2, 0), card_addr); 5435 #else 5436 addl(tmp2, queue_index); 5437 movl(Address(tmp2, 0), card_addr); 5438 #endif 5439 jmp(done); 5440 5441 bind(runtime); 5442 // save the live input values 5443 push(store_addr); 5444 push(new_val); 5445 #ifdef _LP64 5446 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, r15_thread); 5447 #else 5448 push(thread); 5449 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread); 5450 pop(thread); 5451 #endif 5452 pop(new_val); 5453 pop(store_addr); 5454 5455 bind(done); 5456 } 5457 5458 #endif // INCLUDE_ALL_GCS 5459 ////////////////////////////////////////////////////////////////////////////////// 5460 5461 5462 void MacroAssembler::store_check(Register obj, Address dst) { 5463 store_check(obj); 5464 } 5465 5466 void MacroAssembler::store_check(Register obj) { 5467 // Does a store check for the oop in register obj. The content of 5468 // register obj is destroyed afterwards. 5469 BarrierSet* bs = Universe::heap()->barrier_set(); 5470 assert(bs->kind() == BarrierSet::CardTableForRS || 5471 bs->kind() == BarrierSet::CardTableExtension, 5472 "Wrong barrier set kind"); 5473 5474 CardTableModRefBS* ct = barrier_set_cast<CardTableModRefBS>(bs); 5475 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); 5476 5477 shrptr(obj, CardTableModRefBS::card_shift); 5478 5479 Address card_addr; 5480 5481 // The calculation for byte_map_base is as follows: 5482 // byte_map_base = _byte_map - (uintptr_t(low_bound) >> card_shift); 5483 // So this essentially converts an address to a displacement and it will 5484 // never need to be relocated. On 64bit however the value may be too 5485 // large for a 32bit displacement. 5486 intptr_t disp = (intptr_t) ct->byte_map_base; 5487 if (is_simm32(disp)) { 5488 card_addr = Address(noreg, obj, Address::times_1, disp); 5489 } else { 5490 // By doing it as an ExternalAddress 'disp' could be converted to a rip-relative 5491 // displacement and done in a single instruction given favorable mapping and a 5492 // smarter version of as_Address. However, 'ExternalAddress' generates a relocation 5493 // entry and that entry is not properly handled by the relocation code. 5494 AddressLiteral cardtable((address)ct->byte_map_base, relocInfo::none); 5495 Address index(noreg, obj, Address::times_1); 5496 card_addr = as_Address(ArrayAddress(cardtable, index)); 5497 } 5498 5499 int dirty = CardTableModRefBS::dirty_card_val(); 5500 if (UseCondCardMark) { 5501 Label L_already_dirty; 5502 if (UseConcMarkSweepGC) { 5503 membar(Assembler::StoreLoad); 5504 } 5505 cmpb(card_addr, dirty); 5506 jcc(Assembler::equal, L_already_dirty); 5507 movb(card_addr, dirty); 5508 bind(L_already_dirty); 5509 } else { 5510 movb(card_addr, dirty); 5511 } 5512 } 5513 5514 void MacroAssembler::subptr(Register dst, int32_t imm32) { 5515 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32)); 5516 } 5517 5518 // Force generation of a 4 byte immediate value even if it fits into 8bit 5519 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) { 5520 LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32)); 5521 } 5522 5523 void MacroAssembler::subptr(Register dst, Register src) { 5524 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); 5525 } 5526 5527 // C++ bool manipulation 5528 void MacroAssembler::testbool(Register dst) { 5529 if(sizeof(bool) == 1) 5530 testb(dst, 0xff); 5531 else if(sizeof(bool) == 2) { 5532 // testw implementation needed for two byte bools 5533 ShouldNotReachHere(); 5534 } else if(sizeof(bool) == 4) 5535 testl(dst, dst); 5536 else 5537 // unsupported 5538 ShouldNotReachHere(); 5539 } 5540 5541 void MacroAssembler::testptr(Register dst, Register src) { 5542 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src)); 5543 } 5544 5545 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes. 5546 void MacroAssembler::tlab_allocate(Register obj, 5547 Register var_size_in_bytes, 5548 int con_size_in_bytes, 5549 Register t1, 5550 Register t2, 5551 Label& slow_case) { 5552 assert_different_registers(obj, t1, t2); 5553 assert_different_registers(obj, var_size_in_bytes, t1); 5554 Register end = t2; 5555 Register thread = NOT_LP64(t1) LP64_ONLY(r15_thread); 5556 5557 verify_tlab(); 5558 5559 NOT_LP64(get_thread(thread)); 5560 5561 movptr(obj, Address(thread, JavaThread::tlab_top_offset())); 5562 if (var_size_in_bytes == noreg) { 5563 lea(end, Address(obj, con_size_in_bytes)); 5564 } else { 5565 lea(end, Address(obj, var_size_in_bytes, Address::times_1)); 5566 } 5567 cmpptr(end, Address(thread, JavaThread::tlab_end_offset())); 5568 jcc(Assembler::above, slow_case); 5569 5570 // update the tlab top pointer 5571 movptr(Address(thread, JavaThread::tlab_top_offset()), end); 5572 5573 // recover var_size_in_bytes if necessary 5574 if (var_size_in_bytes == end) { 5575 subptr(var_size_in_bytes, obj); 5576 } 5577 verify_tlab(); 5578 } 5579 5580 // Preserves rbx, and rdx. 5581 Register MacroAssembler::tlab_refill(Label& retry, 5582 Label& try_eden, 5583 Label& slow_case) { 5584 Register top = rax; 5585 Register t1 = rcx; // object size 5586 Register t2 = rsi; 5587 Register thread_reg = NOT_LP64(rdi) LP64_ONLY(r15_thread); 5588 assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ rbx, rdx); 5589 Label do_refill, discard_tlab; 5590 5591 if (!Universe::heap()->supports_inline_contig_alloc()) { 5592 // No allocation in the shared eden. 5593 jmp(slow_case); 5594 } 5595 5596 NOT_LP64(get_thread(thread_reg)); 5597 5598 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); 5599 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset()))); 5600 5601 // calculate amount of free space 5602 subptr(t1, top); 5603 shrptr(t1, LogHeapWordSize); 5604 5605 // Retain tlab and allocate object in shared space if 5606 // the amount free in the tlab is too large to discard. 5607 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset()))); 5608 jcc(Assembler::lessEqual, discard_tlab); 5609 5610 // Retain 5611 // %%% yuck as movptr... 5612 movptr(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment()); 5613 addptr(Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())), t2); 5614 if (TLABStats) { 5615 // increment number of slow_allocations 5616 addl(Address(thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())), 1); 5617 } 5618 jmp(try_eden); 5619 5620 bind(discard_tlab); 5621 if (TLABStats) { 5622 // increment number of refills 5623 addl(Address(thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1); 5624 // accumulate wastage -- t1 is amount free in tlab 5625 addl(Address(thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1); 5626 } 5627 5628 // if tlab is currently allocated (top or end != null) then 5629 // fill [top, end + alignment_reserve) with array object 5630 testptr(top, top); 5631 jcc(Assembler::zero, do_refill); 5632 5633 // set up the mark word 5634 movptr(Address(top, oopDesc::mark_offset_in_bytes()), (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2)); 5635 // set the length to the remaining space 5636 subptr(t1, typeArrayOopDesc::header_size(T_INT)); 5637 addptr(t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve()); 5638 shlptr(t1, log2_intptr(HeapWordSize/sizeof(jint))); 5639 movl(Address(top, arrayOopDesc::length_offset_in_bytes()), t1); 5640 // set klass to intArrayKlass 5641 // dubious reloc why not an oop reloc? 5642 movptr(t1, ExternalAddress((address)Universe::intArrayKlassObj_addr())); 5643 // store klass last. concurrent gcs assumes klass length is valid if 5644 // klass field is not null. 5645 store_klass(top, t1); 5646 5647 movptr(t1, top); 5648 subptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset()))); 5649 incr_allocated_bytes(thread_reg, t1, 0); 5650 5651 // refill the tlab with an eden allocation 5652 bind(do_refill); 5653 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset()))); 5654 shlptr(t1, LogHeapWordSize); 5655 // allocate new tlab, address returned in top 5656 eden_allocate(top, t1, 0, t2, slow_case); 5657 5658 // Check that t1 was preserved in eden_allocate. 5659 #ifdef ASSERT 5660 if (UseTLAB) { 5661 Label ok; 5662 Register tsize = rsi; 5663 assert_different_registers(tsize, thread_reg, t1); 5664 push(tsize); 5665 movptr(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset()))); 5666 shlptr(tsize, LogHeapWordSize); 5667 cmpptr(t1, tsize); 5668 jcc(Assembler::equal, ok); 5669 STOP("assert(t1 != tlab size)"); 5670 should_not_reach_here(); 5671 5672 bind(ok); 5673 pop(tsize); 5674 } 5675 #endif 5676 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top); 5677 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top); 5678 addptr(top, t1); 5679 subptr(top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes()); 5680 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top); 5681 5682 if (ZeroTLAB) { 5683 // This is a fast TLAB refill, therefore the GC is not notified of it. 5684 // So compiled code must fill the new TLAB with zeroes. 5685 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset()))); 5686 zero_memory(top, t1, 0, t2); 5687 } 5688 5689 verify_tlab(); 5690 jmp(retry); 5691 5692 return thread_reg; // for use by caller 5693 } 5694 5695 // Preserves the contents of address, destroys the contents length_in_bytes and temp. 5696 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) { 5697 assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different"); 5698 assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord"); 5699 Label done; 5700 5701 testptr(length_in_bytes, length_in_bytes); 5702 jcc(Assembler::zero, done); 5703 5704 // initialize topmost word, divide index by 2, check if odd and test if zero 5705 // note: for the remaining code to work, index must be a multiple of BytesPerWord 5706 #ifdef ASSERT 5707 { 5708 Label L; 5709 testptr(length_in_bytes, BytesPerWord - 1); 5710 jcc(Assembler::zero, L); 5711 stop("length must be a multiple of BytesPerWord"); 5712 bind(L); 5713 } 5714 #endif 5715 Register index = length_in_bytes; 5716 xorptr(temp, temp); // use _zero reg to clear memory (shorter code) 5717 if (UseIncDec) { 5718 shrptr(index, 3); // divide by 8/16 and set carry flag if bit 2 was set 5719 } else { 5720 shrptr(index, 2); // use 2 instructions to avoid partial flag stall 5721 shrptr(index, 1); 5722 } 5723 #ifndef _LP64 5724 // index could have not been a multiple of 8 (i.e., bit 2 was set) 5725 { 5726 Label even; 5727 // note: if index was a multiple of 8, then it cannot 5728 // be 0 now otherwise it must have been 0 before 5729 // => if it is even, we don't need to check for 0 again 5730 jcc(Assembler::carryClear, even); 5731 // clear topmost word (no jump would be needed if conditional assignment worked here) 5732 movptr(Address(address, index, Address::times_8, offset_in_bytes - 0*BytesPerWord), temp); 5733 // index could be 0 now, must check again 5734 jcc(Assembler::zero, done); 5735 bind(even); 5736 } 5737 #endif // !_LP64 5738 // initialize remaining object fields: index is a multiple of 2 now 5739 { 5740 Label loop; 5741 bind(loop); 5742 movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp); 5743 NOT_LP64(movptr(Address(address, index, Address::times_8, offset_in_bytes - 2*BytesPerWord), temp);) 5744 decrement(index); 5745 jcc(Assembler::notZero, loop); 5746 } 5747 5748 bind(done); 5749 } 5750 5751 void MacroAssembler::incr_allocated_bytes(Register thread, 5752 Register var_size_in_bytes, 5753 int con_size_in_bytes, 5754 Register t1) { 5755 if (!thread->is_valid()) { 5756 #ifdef _LP64 5757 thread = r15_thread; 5758 #else 5759 assert(t1->is_valid(), "need temp reg"); 5760 thread = t1; 5761 get_thread(thread); 5762 #endif 5763 } 5764 5765 #ifdef _LP64 5766 if (var_size_in_bytes->is_valid()) { 5767 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes); 5768 } else { 5769 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes); 5770 } 5771 #else 5772 if (var_size_in_bytes->is_valid()) { 5773 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes); 5774 } else { 5775 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes); 5776 } 5777 adcl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())+4), 0); 5778 #endif 5779 } 5780 5781 // Look up the method for a megamorphic invokeinterface call. 5782 // The target method is determined by <intf_klass, itable_index>. 5783 // The receiver klass is in recv_klass. 5784 // On success, the result will be in method_result, and execution falls through. 5785 // On failure, execution transfers to the given label. 5786 void MacroAssembler::lookup_interface_method(Register recv_klass, 5787 Register intf_klass, 5788 RegisterOrConstant itable_index, 5789 Register method_result, 5790 Register scan_temp, 5791 Label& L_no_such_interface) { 5792 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp); 5793 assert(itable_index.is_constant() || itable_index.as_register() == method_result, 5794 "caller must use same register for non-constant itable index as for method"); 5795 5796 // Compute start of first itableOffsetEntry (which is at the end of the vtable) 5797 int vtable_base = in_bytes(Klass::vtable_start_offset()); 5798 int itentry_off = itableMethodEntry::method_offset_in_bytes(); 5799 int scan_step = itableOffsetEntry::size() * wordSize; 5800 int vte_size = vtableEntry::size_in_bytes(); 5801 Address::ScaleFactor times_vte_scale = Address::times_ptr; 5802 assert(vte_size == wordSize, "else adjust times_vte_scale"); 5803 5804 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset())); 5805 5806 // %%% Could store the aligned, prescaled offset in the klassoop. 5807 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base)); 5808 5809 // Adjust recv_klass by scaled itable_index, so we can free itable_index. 5810 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below"); 5811 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off)); 5812 5813 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) { 5814 // if (scan->interface() == intf) { 5815 // result = (klass + scan->offset() + itable_index); 5816 // } 5817 // } 5818 Label search, found_method; 5819 5820 for (int peel = 1; peel >= 0; peel--) { 5821 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes())); 5822 cmpptr(intf_klass, method_result); 5823 5824 if (peel) { 5825 jccb(Assembler::equal, found_method); 5826 } else { 5827 jccb(Assembler::notEqual, search); 5828 // (invert the test to fall through to found_method...) 5829 } 5830 5831 if (!peel) break; 5832 5833 bind(search); 5834 5835 // Check that the previous entry is non-null. A null entry means that 5836 // the receiver class doesn't implement the interface, and wasn't the 5837 // same as when the caller was compiled. 5838 testptr(method_result, method_result); 5839 jcc(Assembler::zero, L_no_such_interface); 5840 addptr(scan_temp, scan_step); 5841 } 5842 5843 bind(found_method); 5844 5845 // Got a hit. 5846 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes())); 5847 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1)); 5848 } 5849 5850 5851 // virtual method calling 5852 void MacroAssembler::lookup_virtual_method(Register recv_klass, 5853 RegisterOrConstant vtable_index, 5854 Register method_result) { 5855 const int base = in_bytes(Klass::vtable_start_offset()); 5856 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below"); 5857 Address vtable_entry_addr(recv_klass, 5858 vtable_index, Address::times_ptr, 5859 base + vtableEntry::method_offset_in_bytes()); 5860 movptr(method_result, vtable_entry_addr); 5861 } 5862 5863 5864 void MacroAssembler::check_klass_subtype(Register sub_klass, 5865 Register super_klass, 5866 Register temp_reg, 5867 Label& L_success) { 5868 Label L_failure; 5869 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL); 5870 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL); 5871 bind(L_failure); 5872 } 5873 5874 5875 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass, 5876 Register super_klass, 5877 Register temp_reg, 5878 Label* L_success, 5879 Label* L_failure, 5880 Label* L_slow_path, 5881 RegisterOrConstant super_check_offset) { 5882 assert_different_registers(sub_klass, super_klass, temp_reg); 5883 bool must_load_sco = (super_check_offset.constant_or_zero() == -1); 5884 if (super_check_offset.is_register()) { 5885 assert_different_registers(sub_klass, super_klass, 5886 super_check_offset.as_register()); 5887 } else if (must_load_sco) { 5888 assert(temp_reg != noreg, "supply either a temp or a register offset"); 5889 } 5890 5891 Label L_fallthrough; 5892 int label_nulls = 0; 5893 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } 5894 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } 5895 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; } 5896 assert(label_nulls <= 1, "at most one NULL in the batch"); 5897 5898 int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); 5899 int sco_offset = in_bytes(Klass::super_check_offset_offset()); 5900 Address super_check_offset_addr(super_klass, sco_offset); 5901 5902 // Hacked jcc, which "knows" that L_fallthrough, at least, is in 5903 // range of a jccb. If this routine grows larger, reconsider at 5904 // least some of these. 5905 #define local_jcc(assembler_cond, label) \ 5906 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \ 5907 else jcc( assembler_cond, label) /*omit semi*/ 5908 5909 // Hacked jmp, which may only be used just before L_fallthrough. 5910 #define final_jmp(label) \ 5911 if (&(label) == &L_fallthrough) { /*do nothing*/ } \ 5912 else jmp(label) /*omit semi*/ 5913 5914 // If the pointers are equal, we are done (e.g., String[] elements). 5915 // This self-check enables sharing of secondary supertype arrays among 5916 // non-primary types such as array-of-interface. Otherwise, each such 5917 // type would need its own customized SSA. 5918 // We move this check to the front of the fast path because many 5919 // type checks are in fact trivially successful in this manner, 5920 // so we get a nicely predicted branch right at the start of the check. 5921 cmpptr(sub_klass, super_klass); 5922 local_jcc(Assembler::equal, *L_success); 5923 5924 // Check the supertype display: 5925 if (must_load_sco) { 5926 // Positive movl does right thing on LP64. 5927 movl(temp_reg, super_check_offset_addr); 5928 super_check_offset = RegisterOrConstant(temp_reg); 5929 } 5930 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0); 5931 cmpptr(super_klass, super_check_addr); // load displayed supertype 5932 5933 // This check has worked decisively for primary supers. 5934 // Secondary supers are sought in the super_cache ('super_cache_addr'). 5935 // (Secondary supers are interfaces and very deeply nested subtypes.) 5936 // This works in the same check above because of a tricky aliasing 5937 // between the super_cache and the primary super display elements. 5938 // (The 'super_check_addr' can address either, as the case requires.) 5939 // Note that the cache is updated below if it does not help us find 5940 // what we need immediately. 5941 // So if it was a primary super, we can just fail immediately. 5942 // Otherwise, it's the slow path for us (no success at this point). 5943 5944 if (super_check_offset.is_register()) { 5945 local_jcc(Assembler::equal, *L_success); 5946 cmpl(super_check_offset.as_register(), sc_offset); 5947 if (L_failure == &L_fallthrough) { 5948 local_jcc(Assembler::equal, *L_slow_path); 5949 } else { 5950 local_jcc(Assembler::notEqual, *L_failure); 5951 final_jmp(*L_slow_path); 5952 } 5953 } else if (super_check_offset.as_constant() == sc_offset) { 5954 // Need a slow path; fast failure is impossible. 5955 if (L_slow_path == &L_fallthrough) { 5956 local_jcc(Assembler::equal, *L_success); 5957 } else { 5958 local_jcc(Assembler::notEqual, *L_slow_path); 5959 final_jmp(*L_success); 5960 } 5961 } else { 5962 // No slow path; it's a fast decision. 5963 if (L_failure == &L_fallthrough) { 5964 local_jcc(Assembler::equal, *L_success); 5965 } else { 5966 local_jcc(Assembler::notEqual, *L_failure); 5967 final_jmp(*L_success); 5968 } 5969 } 5970 5971 bind(L_fallthrough); 5972 5973 #undef local_jcc 5974 #undef final_jmp 5975 } 5976 5977 5978 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass, 5979 Register super_klass, 5980 Register temp_reg, 5981 Register temp2_reg, 5982 Label* L_success, 5983 Label* L_failure, 5984 bool set_cond_codes) { 5985 assert_different_registers(sub_klass, super_klass, temp_reg); 5986 if (temp2_reg != noreg) 5987 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg); 5988 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg) 5989 5990 Label L_fallthrough; 5991 int label_nulls = 0; 5992 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } 5993 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } 5994 assert(label_nulls <= 1, "at most one NULL in the batch"); 5995 5996 // a couple of useful fields in sub_klass: 5997 int ss_offset = in_bytes(Klass::secondary_supers_offset()); 5998 int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); 5999 Address secondary_supers_addr(sub_klass, ss_offset); 6000 Address super_cache_addr( sub_klass, sc_offset); 6001 6002 // Do a linear scan of the secondary super-klass chain. 6003 // This code is rarely used, so simplicity is a virtue here. 6004 // The repne_scan instruction uses fixed registers, which we must spill. 6005 // Don't worry too much about pre-existing connections with the input regs. 6006 6007 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super) 6008 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter) 6009 6010 // Get super_klass value into rax (even if it was in rdi or rcx). 6011 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false; 6012 if (super_klass != rax || UseCompressedOops) { 6013 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; } 6014 mov(rax, super_klass); 6015 } 6016 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; } 6017 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; } 6018 6019 #ifndef PRODUCT 6020 int* pst_counter = &SharedRuntime::_partial_subtype_ctr; 6021 ExternalAddress pst_counter_addr((address) pst_counter); 6022 NOT_LP64( incrementl(pst_counter_addr) ); 6023 LP64_ONLY( lea(rcx, pst_counter_addr) ); 6024 LP64_ONLY( incrementl(Address(rcx, 0)) ); 6025 #endif //PRODUCT 6026 6027 // We will consult the secondary-super array. 6028 movptr(rdi, secondary_supers_addr); 6029 // Load the array length. (Positive movl does right thing on LP64.) 6030 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes())); 6031 // Skip to start of data. 6032 addptr(rdi, Array<Klass*>::base_offset_in_bytes()); 6033 6034 // Scan RCX words at [RDI] for an occurrence of RAX. 6035 // Set NZ/Z based on last compare. 6036 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does 6037 // not change flags (only scas instruction which is repeated sets flags). 6038 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found. 6039 6040 testptr(rax,rax); // Set Z = 0 6041 repne_scan(); 6042 6043 // Unspill the temp. registers: 6044 if (pushed_rdi) pop(rdi); 6045 if (pushed_rcx) pop(rcx); 6046 if (pushed_rax) pop(rax); 6047 6048 if (set_cond_codes) { 6049 // Special hack for the AD files: rdi is guaranteed non-zero. 6050 assert(!pushed_rdi, "rdi must be left non-NULL"); 6051 // Also, the condition codes are properly set Z/NZ on succeed/failure. 6052 } 6053 6054 if (L_failure == &L_fallthrough) 6055 jccb(Assembler::notEqual, *L_failure); 6056 else jcc(Assembler::notEqual, *L_failure); 6057 6058 // Success. Cache the super we found and proceed in triumph. 6059 movptr(super_cache_addr, super_klass); 6060 6061 if (L_success != &L_fallthrough) { 6062 jmp(*L_success); 6063 } 6064 6065 #undef IS_A_TEMP 6066 6067 bind(L_fallthrough); 6068 } 6069 6070 6071 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) { 6072 if (VM_Version::supports_cmov()) { 6073 cmovl(cc, dst, src); 6074 } else { 6075 Label L; 6076 jccb(negate_condition(cc), L); 6077 movl(dst, src); 6078 bind(L); 6079 } 6080 } 6081 6082 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) { 6083 if (VM_Version::supports_cmov()) { 6084 cmovl(cc, dst, src); 6085 } else { 6086 Label L; 6087 jccb(negate_condition(cc), L); 6088 movl(dst, src); 6089 bind(L); 6090 } 6091 } 6092 6093 void MacroAssembler::verify_oop(Register reg, const char* s) { 6094 if (!VerifyOops) return; 6095 6096 // Pass register number to verify_oop_subroutine 6097 const char* b = NULL; 6098 { 6099 ResourceMark rm; 6100 stringStream ss; 6101 ss.print("verify_oop: %s: %s", reg->name(), s); 6102 b = code_string(ss.as_string()); 6103 } 6104 BLOCK_COMMENT("verify_oop {"); 6105 #ifdef _LP64 6106 push(rscratch1); // save r10, trashed by movptr() 6107 #endif 6108 push(rax); // save rax, 6109 push(reg); // pass register argument 6110 ExternalAddress buffer((address) b); 6111 // avoid using pushptr, as it modifies scratch registers 6112 // and our contract is not to modify anything 6113 movptr(rax, buffer.addr()); 6114 push(rax); 6115 // call indirectly to solve generation ordering problem 6116 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); 6117 call(rax); 6118 // Caller pops the arguments (oop, message) and restores rax, r10 6119 BLOCK_COMMENT("} verify_oop"); 6120 } 6121 6122 6123 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr, 6124 Register tmp, 6125 int offset) { 6126 intptr_t value = *delayed_value_addr; 6127 if (value != 0) 6128 return RegisterOrConstant(value + offset); 6129 6130 // load indirectly to solve generation ordering problem 6131 movptr(tmp, ExternalAddress((address) delayed_value_addr)); 6132 6133 #ifdef ASSERT 6134 { Label L; 6135 testptr(tmp, tmp); 6136 if (WizardMode) { 6137 const char* buf = NULL; 6138 { 6139 ResourceMark rm; 6140 stringStream ss; 6141 ss.print("DelayedValue=" INTPTR_FORMAT, delayed_value_addr[1]); 6142 buf = code_string(ss.as_string()); 6143 } 6144 jcc(Assembler::notZero, L); 6145 STOP(buf); 6146 } else { 6147 jccb(Assembler::notZero, L); 6148 hlt(); 6149 } 6150 bind(L); 6151 } 6152 #endif 6153 6154 if (offset != 0) 6155 addptr(tmp, offset); 6156 6157 return RegisterOrConstant(tmp); 6158 } 6159 6160 6161 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot, 6162 int extra_slot_offset) { 6163 // cf. TemplateTable::prepare_invoke(), if (load_receiver). 6164 int stackElementSize = Interpreter::stackElementSize; 6165 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0); 6166 #ifdef ASSERT 6167 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1); 6168 assert(offset1 - offset == stackElementSize, "correct arithmetic"); 6169 #endif 6170 Register scale_reg = noreg; 6171 Address::ScaleFactor scale_factor = Address::no_scale; 6172 if (arg_slot.is_constant()) { 6173 offset += arg_slot.as_constant() * stackElementSize; 6174 } else { 6175 scale_reg = arg_slot.as_register(); 6176 scale_factor = Address::times(stackElementSize); 6177 } 6178 offset += wordSize; // return PC is on stack 6179 return Address(rsp, scale_reg, scale_factor, offset); 6180 } 6181 6182 6183 void MacroAssembler::verify_oop_addr(Address addr, const char* s) { 6184 if (!VerifyOops) return; 6185 6186 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord); 6187 // Pass register number to verify_oop_subroutine 6188 const char* b = NULL; 6189 { 6190 ResourceMark rm; 6191 stringStream ss; 6192 ss.print("verify_oop_addr: %s", s); 6193 b = code_string(ss.as_string()); 6194 } 6195 #ifdef _LP64 6196 push(rscratch1); // save r10, trashed by movptr() 6197 #endif 6198 push(rax); // save rax, 6199 // addr may contain rsp so we will have to adjust it based on the push 6200 // we just did (and on 64 bit we do two pushes) 6201 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which 6202 // stores rax into addr which is backwards of what was intended. 6203 if (addr.uses(rsp)) { 6204 lea(rax, addr); 6205 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord)); 6206 } else { 6207 pushptr(addr); 6208 } 6209 6210 ExternalAddress buffer((address) b); 6211 // pass msg argument 6212 // avoid using pushptr, as it modifies scratch registers 6213 // and our contract is not to modify anything 6214 movptr(rax, buffer.addr()); 6215 push(rax); 6216 6217 // call indirectly to solve generation ordering problem 6218 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); 6219 call(rax); 6220 // Caller pops the arguments (addr, message) and restores rax, r10. 6221 } 6222 6223 void MacroAssembler::verify_tlab() { 6224 #ifdef ASSERT 6225 if (UseTLAB && VerifyOops) { 6226 Label next, ok; 6227 Register t1 = rsi; 6228 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread); 6229 6230 push(t1); 6231 NOT_LP64(push(thread_reg)); 6232 NOT_LP64(get_thread(thread_reg)); 6233 6234 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); 6235 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset()))); 6236 jcc(Assembler::aboveEqual, next); 6237 STOP("assert(top >= start)"); 6238 should_not_reach_here(); 6239 6240 bind(next); 6241 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset()))); 6242 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); 6243 jcc(Assembler::aboveEqual, ok); 6244 STOP("assert(top <= end)"); 6245 should_not_reach_here(); 6246 6247 bind(ok); 6248 NOT_LP64(pop(thread_reg)); 6249 pop(t1); 6250 } 6251 #endif 6252 } 6253 6254 class ControlWord { 6255 public: 6256 int32_t _value; 6257 6258 int rounding_control() const { return (_value >> 10) & 3 ; } 6259 int precision_control() const { return (_value >> 8) & 3 ; } 6260 bool precision() const { return ((_value >> 5) & 1) != 0; } 6261 bool underflow() const { return ((_value >> 4) & 1) != 0; } 6262 bool overflow() const { return ((_value >> 3) & 1) != 0; } 6263 bool zero_divide() const { return ((_value >> 2) & 1) != 0; } 6264 bool denormalized() const { return ((_value >> 1) & 1) != 0; } 6265 bool invalid() const { return ((_value >> 0) & 1) != 0; } 6266 6267 void print() const { 6268 // rounding control 6269 const char* rc; 6270 switch (rounding_control()) { 6271 case 0: rc = "round near"; break; 6272 case 1: rc = "round down"; break; 6273 case 2: rc = "round up "; break; 6274 case 3: rc = "chop "; break; 6275 }; 6276 // precision control 6277 const char* pc; 6278 switch (precision_control()) { 6279 case 0: pc = "24 bits "; break; 6280 case 1: pc = "reserved"; break; 6281 case 2: pc = "53 bits "; break; 6282 case 3: pc = "64 bits "; break; 6283 }; 6284 // flags 6285 char f[9]; 6286 f[0] = ' '; 6287 f[1] = ' '; 6288 f[2] = (precision ()) ? 'P' : 'p'; 6289 f[3] = (underflow ()) ? 'U' : 'u'; 6290 f[4] = (overflow ()) ? 'O' : 'o'; 6291 f[5] = (zero_divide ()) ? 'Z' : 'z'; 6292 f[6] = (denormalized()) ? 'D' : 'd'; 6293 f[7] = (invalid ()) ? 'I' : 'i'; 6294 f[8] = '\x0'; 6295 // output 6296 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc); 6297 } 6298 6299 }; 6300 6301 class StatusWord { 6302 public: 6303 int32_t _value; 6304 6305 bool busy() const { return ((_value >> 15) & 1) != 0; } 6306 bool C3() const { return ((_value >> 14) & 1) != 0; } 6307 bool C2() const { return ((_value >> 10) & 1) != 0; } 6308 bool C1() const { return ((_value >> 9) & 1) != 0; } 6309 bool C0() const { return ((_value >> 8) & 1) != 0; } 6310 int top() const { return (_value >> 11) & 7 ; } 6311 bool error_status() const { return ((_value >> 7) & 1) != 0; } 6312 bool stack_fault() const { return ((_value >> 6) & 1) != 0; } 6313 bool precision() const { return ((_value >> 5) & 1) != 0; } 6314 bool underflow() const { return ((_value >> 4) & 1) != 0; } 6315 bool overflow() const { return ((_value >> 3) & 1) != 0; } 6316 bool zero_divide() const { return ((_value >> 2) & 1) != 0; } 6317 bool denormalized() const { return ((_value >> 1) & 1) != 0; } 6318 bool invalid() const { return ((_value >> 0) & 1) != 0; } 6319 6320 void print() const { 6321 // condition codes 6322 char c[5]; 6323 c[0] = (C3()) ? '3' : '-'; 6324 c[1] = (C2()) ? '2' : '-'; 6325 c[2] = (C1()) ? '1' : '-'; 6326 c[3] = (C0()) ? '0' : '-'; 6327 c[4] = '\x0'; 6328 // flags 6329 char f[9]; 6330 f[0] = (error_status()) ? 'E' : '-'; 6331 f[1] = (stack_fault ()) ? 'S' : '-'; 6332 f[2] = (precision ()) ? 'P' : '-'; 6333 f[3] = (underflow ()) ? 'U' : '-'; 6334 f[4] = (overflow ()) ? 'O' : '-'; 6335 f[5] = (zero_divide ()) ? 'Z' : '-'; 6336 f[6] = (denormalized()) ? 'D' : '-'; 6337 f[7] = (invalid ()) ? 'I' : '-'; 6338 f[8] = '\x0'; 6339 // output 6340 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top()); 6341 } 6342 6343 }; 6344 6345 class TagWord { 6346 public: 6347 int32_t _value; 6348 6349 int tag_at(int i) const { return (_value >> (i*2)) & 3; } 6350 6351 void print() const { 6352 printf("%04x", _value & 0xFFFF); 6353 } 6354 6355 }; 6356 6357 class FPU_Register { 6358 public: 6359 int32_t _m0; 6360 int32_t _m1; 6361 int16_t _ex; 6362 6363 bool is_indefinite() const { 6364 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0; 6365 } 6366 6367 void print() const { 6368 char sign = (_ex < 0) ? '-' : '+'; 6369 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " "; 6370 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind); 6371 }; 6372 6373 }; 6374 6375 class FPU_State { 6376 public: 6377 enum { 6378 register_size = 10, 6379 number_of_registers = 8, 6380 register_mask = 7 6381 }; 6382 6383 ControlWord _control_word; 6384 StatusWord _status_word; 6385 TagWord _tag_word; 6386 int32_t _error_offset; 6387 int32_t _error_selector; 6388 int32_t _data_offset; 6389 int32_t _data_selector; 6390 int8_t _register[register_size * number_of_registers]; 6391 6392 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); } 6393 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; } 6394 6395 const char* tag_as_string(int tag) const { 6396 switch (tag) { 6397 case 0: return "valid"; 6398 case 1: return "zero"; 6399 case 2: return "special"; 6400 case 3: return "empty"; 6401 } 6402 ShouldNotReachHere(); 6403 return NULL; 6404 } 6405 6406 void print() const { 6407 // print computation registers 6408 { int t = _status_word.top(); 6409 for (int i = 0; i < number_of_registers; i++) { 6410 int j = (i - t) & register_mask; 6411 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j); 6412 st(j)->print(); 6413 printf(" %s\n", tag_as_string(_tag_word.tag_at(i))); 6414 } 6415 } 6416 printf("\n"); 6417 // print control registers 6418 printf("ctrl = "); _control_word.print(); printf("\n"); 6419 printf("stat = "); _status_word .print(); printf("\n"); 6420 printf("tags = "); _tag_word .print(); printf("\n"); 6421 } 6422 6423 }; 6424 6425 class Flag_Register { 6426 public: 6427 int32_t _value; 6428 6429 bool overflow() const { return ((_value >> 11) & 1) != 0; } 6430 bool direction() const { return ((_value >> 10) & 1) != 0; } 6431 bool sign() const { return ((_value >> 7) & 1) != 0; } 6432 bool zero() const { return ((_value >> 6) & 1) != 0; } 6433 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; } 6434 bool parity() const { return ((_value >> 2) & 1) != 0; } 6435 bool carry() const { return ((_value >> 0) & 1) != 0; } 6436 6437 void print() const { 6438 // flags 6439 char f[8]; 6440 f[0] = (overflow ()) ? 'O' : '-'; 6441 f[1] = (direction ()) ? 'D' : '-'; 6442 f[2] = (sign ()) ? 'S' : '-'; 6443 f[3] = (zero ()) ? 'Z' : '-'; 6444 f[4] = (auxiliary_carry()) ? 'A' : '-'; 6445 f[5] = (parity ()) ? 'P' : '-'; 6446 f[6] = (carry ()) ? 'C' : '-'; 6447 f[7] = '\x0'; 6448 // output 6449 printf("%08x flags = %s", _value, f); 6450 } 6451 6452 }; 6453 6454 class IU_Register { 6455 public: 6456 int32_t _value; 6457 6458 void print() const { 6459 printf("%08x %11d", _value, _value); 6460 } 6461 6462 }; 6463 6464 class IU_State { 6465 public: 6466 Flag_Register _eflags; 6467 IU_Register _rdi; 6468 IU_Register _rsi; 6469 IU_Register _rbp; 6470 IU_Register _rsp; 6471 IU_Register _rbx; 6472 IU_Register _rdx; 6473 IU_Register _rcx; 6474 IU_Register _rax; 6475 6476 void print() const { 6477 // computation registers 6478 printf("rax, = "); _rax.print(); printf("\n"); 6479 printf("rbx, = "); _rbx.print(); printf("\n"); 6480 printf("rcx = "); _rcx.print(); printf("\n"); 6481 printf("rdx = "); _rdx.print(); printf("\n"); 6482 printf("rdi = "); _rdi.print(); printf("\n"); 6483 printf("rsi = "); _rsi.print(); printf("\n"); 6484 printf("rbp, = "); _rbp.print(); printf("\n"); 6485 printf("rsp = "); _rsp.print(); printf("\n"); 6486 printf("\n"); 6487 // control registers 6488 printf("flgs = "); _eflags.print(); printf("\n"); 6489 } 6490 }; 6491 6492 6493 class CPU_State { 6494 public: 6495 FPU_State _fpu_state; 6496 IU_State _iu_state; 6497 6498 void print() const { 6499 printf("--------------------------------------------------\n"); 6500 _iu_state .print(); 6501 printf("\n"); 6502 _fpu_state.print(); 6503 printf("--------------------------------------------------\n"); 6504 } 6505 6506 }; 6507 6508 6509 static void _print_CPU_state(CPU_State* state) { 6510 state->print(); 6511 }; 6512 6513 6514 void MacroAssembler::print_CPU_state() { 6515 push_CPU_state(); 6516 push(rsp); // pass CPU state 6517 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state))); 6518 addptr(rsp, wordSize); // discard argument 6519 pop_CPU_state(); 6520 } 6521 6522 6523 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) { 6524 static int counter = 0; 6525 FPU_State* fs = &state->_fpu_state; 6526 counter++; 6527 // For leaf calls, only verify that the top few elements remain empty. 6528 // We only need 1 empty at the top for C2 code. 6529 if( stack_depth < 0 ) { 6530 if( fs->tag_for_st(7) != 3 ) { 6531 printf("FPR7 not empty\n"); 6532 state->print(); 6533 assert(false, "error"); 6534 return false; 6535 } 6536 return true; // All other stack states do not matter 6537 } 6538 6539 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std, 6540 "bad FPU control word"); 6541 6542 // compute stack depth 6543 int i = 0; 6544 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++; 6545 int d = i; 6546 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++; 6547 // verify findings 6548 if (i != FPU_State::number_of_registers) { 6549 // stack not contiguous 6550 printf("%s: stack not contiguous at ST%d\n", s, i); 6551 state->print(); 6552 assert(false, "error"); 6553 return false; 6554 } 6555 // check if computed stack depth corresponds to expected stack depth 6556 if (stack_depth < 0) { 6557 // expected stack depth is -stack_depth or less 6558 if (d > -stack_depth) { 6559 // too many elements on the stack 6560 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d); 6561 state->print(); 6562 assert(false, "error"); 6563 return false; 6564 } 6565 } else { 6566 // expected stack depth is stack_depth 6567 if (d != stack_depth) { 6568 // wrong stack depth 6569 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d); 6570 state->print(); 6571 assert(false, "error"); 6572 return false; 6573 } 6574 } 6575 // everything is cool 6576 return true; 6577 } 6578 6579 6580 void MacroAssembler::verify_FPU(int stack_depth, const char* s) { 6581 if (!VerifyFPU) return; 6582 push_CPU_state(); 6583 push(rsp); // pass CPU state 6584 ExternalAddress msg((address) s); 6585 // pass message string s 6586 pushptr(msg.addr()); 6587 push(stack_depth); // pass stack depth 6588 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU))); 6589 addptr(rsp, 3 * wordSize); // discard arguments 6590 // check for error 6591 { Label L; 6592 testl(rax, rax); 6593 jcc(Assembler::notZero, L); 6594 int3(); // break if error condition 6595 bind(L); 6596 } 6597 pop_CPU_state(); 6598 } 6599 6600 void MacroAssembler::restore_cpu_control_state_after_jni() { 6601 // Either restore the MXCSR register after returning from the JNI Call 6602 // or verify that it wasn't changed (with -Xcheck:jni flag). 6603 if (VM_Version::supports_sse()) { 6604 if (RestoreMXCSROnJNICalls) { 6605 ldmxcsr(ExternalAddress(StubRoutines::addr_mxcsr_std())); 6606 } else if (CheckJNICalls) { 6607 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry())); 6608 } 6609 } 6610 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty. 6611 vzeroupper(); 6612 // Reset k1 to 0xffff. 6613 if (VM_Version::supports_evex()) { 6614 push(rcx); 6615 movl(rcx, 0xffff); 6616 kmovwl(k1, rcx); 6617 pop(rcx); 6618 } 6619 6620 #ifndef _LP64 6621 // Either restore the x87 floating pointer control word after returning 6622 // from the JNI call or verify that it wasn't changed. 6623 if (CheckJNICalls) { 6624 call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry())); 6625 } 6626 #endif // _LP64 6627 } 6628 6629 // ((OopHandle)result).resolve(); 6630 void MacroAssembler::resolve_oop_handle(Register result) { 6631 // OopHandle::resolve is an indirection. 6632 movptr(result, Address(result, 0)); 6633 } 6634 6635 void MacroAssembler::load_mirror(Register mirror, Register method) { 6636 // get mirror 6637 const int mirror_offset = in_bytes(Klass::java_mirror_offset()); 6638 movptr(mirror, Address(method, Method::const_offset())); 6639 movptr(mirror, Address(mirror, ConstMethod::constants_offset())); 6640 movptr(mirror, Address(mirror, ConstantPool::pool_holder_offset_in_bytes())); 6641 movptr(mirror, Address(mirror, mirror_offset)); 6642 resolve_oop_handle(mirror); 6643 } 6644 6645 void MacroAssembler::load_klass(Register dst, Register src) { 6646 #ifdef _LP64 6647 if (UseCompressedClassPointers) { 6648 movl(dst, Address(src, oopDesc::klass_offset_in_bytes())); 6649 decode_klass_not_null(dst); 6650 } else 6651 #endif 6652 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes())); 6653 } 6654 6655 void MacroAssembler::load_prototype_header(Register dst, Register src) { 6656 load_klass(dst, src); 6657 movptr(dst, Address(dst, Klass::prototype_header_offset())); 6658 } 6659 6660 void MacroAssembler::store_klass(Register dst, Register src) { 6661 #ifdef _LP64 6662 if (UseCompressedClassPointers) { 6663 encode_klass_not_null(src); 6664 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src); 6665 } else 6666 #endif 6667 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src); 6668 } 6669 6670 void MacroAssembler::load_heap_oop(Register dst, Address src) { 6671 #ifdef _LP64 6672 // FIXME: Must change all places where we try to load the klass. 6673 if (UseCompressedOops) { 6674 movl(dst, src); 6675 decode_heap_oop(dst); 6676 } else 6677 #endif 6678 movptr(dst, src); 6679 } 6680 6681 // Doesn't do verfication, generates fixed size code 6682 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src) { 6683 #ifdef _LP64 6684 if (UseCompressedOops) { 6685 movl(dst, src); 6686 decode_heap_oop_not_null(dst); 6687 } else 6688 #endif 6689 movptr(dst, src); 6690 } 6691 6692 void MacroAssembler::store_heap_oop(Address dst, Register src) { 6693 #ifdef _LP64 6694 if (UseCompressedOops) { 6695 assert(!dst.uses(src), "not enough registers"); 6696 encode_heap_oop(src); 6697 movl(dst, src); 6698 } else 6699 #endif 6700 movptr(dst, src); 6701 } 6702 6703 void MacroAssembler::cmp_heap_oop(Register src1, Address src2, Register tmp) { 6704 assert_different_registers(src1, tmp); 6705 #ifdef _LP64 6706 if (UseCompressedOops) { 6707 bool did_push = false; 6708 if (tmp == noreg) { 6709 tmp = rax; 6710 push(tmp); 6711 did_push = true; 6712 assert(!src2.uses(rsp), "can't push"); 6713 } 6714 load_heap_oop(tmp, src2); 6715 cmpptr(src1, tmp); 6716 if (did_push) pop(tmp); 6717 } else 6718 #endif 6719 cmpptr(src1, src2); 6720 } 6721 6722 // Used for storing NULLs. 6723 void MacroAssembler::store_heap_oop_null(Address dst) { 6724 #ifdef _LP64 6725 if (UseCompressedOops) { 6726 movl(dst, (int32_t)NULL_WORD); 6727 } else { 6728 movslq(dst, (int32_t)NULL_WORD); 6729 } 6730 #else 6731 movl(dst, (int32_t)NULL_WORD); 6732 #endif 6733 } 6734 6735 #ifdef _LP64 6736 void MacroAssembler::store_klass_gap(Register dst, Register src) { 6737 if (UseCompressedClassPointers) { 6738 // Store to klass gap in destination 6739 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src); 6740 } 6741 } 6742 6743 #ifdef ASSERT 6744 void MacroAssembler::verify_heapbase(const char* msg) { 6745 assert (UseCompressedOops, "should be compressed"); 6746 assert (Universe::heap() != NULL, "java heap should be initialized"); 6747 if (CheckCompressedOops) { 6748 Label ok; 6749 push(rscratch1); // cmpptr trashes rscratch1 6750 cmpptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr())); 6751 jcc(Assembler::equal, ok); 6752 STOP(msg); 6753 bind(ok); 6754 pop(rscratch1); 6755 } 6756 } 6757 #endif 6758 6759 // Algorithm must match oop.inline.hpp encode_heap_oop. 6760 void MacroAssembler::encode_heap_oop(Register r) { 6761 #ifdef ASSERT 6762 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?"); 6763 #endif 6764 verify_oop(r, "broken oop in encode_heap_oop"); 6765 if (Universe::narrow_oop_base() == NULL) { 6766 if (Universe::narrow_oop_shift() != 0) { 6767 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 6768 shrq(r, LogMinObjAlignmentInBytes); 6769 } 6770 return; 6771 } 6772 testq(r, r); 6773 cmovq(Assembler::equal, r, r12_heapbase); 6774 subq(r, r12_heapbase); 6775 shrq(r, LogMinObjAlignmentInBytes); 6776 } 6777 6778 void MacroAssembler::encode_heap_oop_not_null(Register r) { 6779 #ifdef ASSERT 6780 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?"); 6781 if (CheckCompressedOops) { 6782 Label ok; 6783 testq(r, r); 6784 jcc(Assembler::notEqual, ok); 6785 STOP("null oop passed to encode_heap_oop_not_null"); 6786 bind(ok); 6787 } 6788 #endif 6789 verify_oop(r, "broken oop in encode_heap_oop_not_null"); 6790 if (Universe::narrow_oop_base() != NULL) { 6791 subq(r, r12_heapbase); 6792 } 6793 if (Universe::narrow_oop_shift() != 0) { 6794 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 6795 shrq(r, LogMinObjAlignmentInBytes); 6796 } 6797 } 6798 6799 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) { 6800 #ifdef ASSERT 6801 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?"); 6802 if (CheckCompressedOops) { 6803 Label ok; 6804 testq(src, src); 6805 jcc(Assembler::notEqual, ok); 6806 STOP("null oop passed to encode_heap_oop_not_null2"); 6807 bind(ok); 6808 } 6809 #endif 6810 verify_oop(src, "broken oop in encode_heap_oop_not_null2"); 6811 if (dst != src) { 6812 movq(dst, src); 6813 } 6814 if (Universe::narrow_oop_base() != NULL) { 6815 subq(dst, r12_heapbase); 6816 } 6817 if (Universe::narrow_oop_shift() != 0) { 6818 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 6819 shrq(dst, LogMinObjAlignmentInBytes); 6820 } 6821 } 6822 6823 void MacroAssembler::decode_heap_oop(Register r) { 6824 #ifdef ASSERT 6825 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?"); 6826 #endif 6827 if (Universe::narrow_oop_base() == NULL) { 6828 if (Universe::narrow_oop_shift() != 0) { 6829 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 6830 shlq(r, LogMinObjAlignmentInBytes); 6831 } 6832 } else { 6833 Label done; 6834 shlq(r, LogMinObjAlignmentInBytes); 6835 jccb(Assembler::equal, done); 6836 addq(r, r12_heapbase); 6837 bind(done); 6838 } 6839 verify_oop(r, "broken oop in decode_heap_oop"); 6840 } 6841 6842 void MacroAssembler::decode_heap_oop_not_null(Register r) { 6843 // Note: it will change flags 6844 assert (UseCompressedOops, "should only be used for compressed headers"); 6845 assert (Universe::heap() != NULL, "java heap should be initialized"); 6846 // Cannot assert, unverified entry point counts instructions (see .ad file) 6847 // vtableStubs also counts instructions in pd_code_size_limit. 6848 // Also do not verify_oop as this is called by verify_oop. 6849 if (Universe::narrow_oop_shift() != 0) { 6850 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 6851 shlq(r, LogMinObjAlignmentInBytes); 6852 if (Universe::narrow_oop_base() != NULL) { 6853 addq(r, r12_heapbase); 6854 } 6855 } else { 6856 assert (Universe::narrow_oop_base() == NULL, "sanity"); 6857 } 6858 } 6859 6860 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) { 6861 // Note: it will change flags 6862 assert (UseCompressedOops, "should only be used for compressed headers"); 6863 assert (Universe::heap() != NULL, "java heap should be initialized"); 6864 // Cannot assert, unverified entry point counts instructions (see .ad file) 6865 // vtableStubs also counts instructions in pd_code_size_limit. 6866 // Also do not verify_oop as this is called by verify_oop. 6867 if (Universe::narrow_oop_shift() != 0) { 6868 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 6869 if (LogMinObjAlignmentInBytes == Address::times_8) { 6870 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0)); 6871 } else { 6872 if (dst != src) { 6873 movq(dst, src); 6874 } 6875 shlq(dst, LogMinObjAlignmentInBytes); 6876 if (Universe::narrow_oop_base() != NULL) { 6877 addq(dst, r12_heapbase); 6878 } 6879 } 6880 } else { 6881 assert (Universe::narrow_oop_base() == NULL, "sanity"); 6882 if (dst != src) { 6883 movq(dst, src); 6884 } 6885 } 6886 } 6887 6888 void MacroAssembler::encode_klass_not_null(Register r) { 6889 if (Universe::narrow_klass_base() != NULL) { 6890 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base. 6891 assert(r != r12_heapbase, "Encoding a klass in r12"); 6892 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base()); 6893 subq(r, r12_heapbase); 6894 } 6895 if (Universe::narrow_klass_shift() != 0) { 6896 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 6897 shrq(r, LogKlassAlignmentInBytes); 6898 } 6899 if (Universe::narrow_klass_base() != NULL) { 6900 reinit_heapbase(); 6901 } 6902 } 6903 6904 void MacroAssembler::encode_klass_not_null(Register dst, Register src) { 6905 if (dst == src) { 6906 encode_klass_not_null(src); 6907 } else { 6908 if (Universe::narrow_klass_base() != NULL) { 6909 mov64(dst, (int64_t)Universe::narrow_klass_base()); 6910 negq(dst); 6911 addq(dst, src); 6912 } else { 6913 movptr(dst, src); 6914 } 6915 if (Universe::narrow_klass_shift() != 0) { 6916 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 6917 shrq(dst, LogKlassAlignmentInBytes); 6918 } 6919 } 6920 } 6921 6922 // Function instr_size_for_decode_klass_not_null() counts the instructions 6923 // generated by decode_klass_not_null(register r) and reinit_heapbase(), 6924 // when (Universe::heap() != NULL). Hence, if the instructions they 6925 // generate change, then this method needs to be updated. 6926 int MacroAssembler::instr_size_for_decode_klass_not_null() { 6927 assert (UseCompressedClassPointers, "only for compressed klass ptrs"); 6928 if (Universe::narrow_klass_base() != NULL) { 6929 // mov64 + addq + shlq? + mov64 (for reinit_heapbase()). 6930 return (Universe::narrow_klass_shift() == 0 ? 20 : 24); 6931 } else { 6932 // longest load decode klass function, mov64, leaq 6933 return 16; 6934 } 6935 } 6936 6937 // !!! If the instructions that get generated here change then function 6938 // instr_size_for_decode_klass_not_null() needs to get updated. 6939 void MacroAssembler::decode_klass_not_null(Register r) { 6940 // Note: it will change flags 6941 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 6942 assert(r != r12_heapbase, "Decoding a klass in r12"); 6943 // Cannot assert, unverified entry point counts instructions (see .ad file) 6944 // vtableStubs also counts instructions in pd_code_size_limit. 6945 // Also do not verify_oop as this is called by verify_oop. 6946 if (Universe::narrow_klass_shift() != 0) { 6947 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 6948 shlq(r, LogKlassAlignmentInBytes); 6949 } 6950 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base. 6951 if (Universe::narrow_klass_base() != NULL) { 6952 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base()); 6953 addq(r, r12_heapbase); 6954 reinit_heapbase(); 6955 } 6956 } 6957 6958 void MacroAssembler::decode_klass_not_null(Register dst, Register src) { 6959 // Note: it will change flags 6960 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 6961 if (dst == src) { 6962 decode_klass_not_null(dst); 6963 } else { 6964 // Cannot assert, unverified entry point counts instructions (see .ad file) 6965 // vtableStubs also counts instructions in pd_code_size_limit. 6966 // Also do not verify_oop as this is called by verify_oop. 6967 mov64(dst, (int64_t)Universe::narrow_klass_base()); 6968 if (Universe::narrow_klass_shift() != 0) { 6969 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 6970 assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?"); 6971 leaq(dst, Address(dst, src, Address::times_8, 0)); 6972 } else { 6973 addq(dst, src); 6974 } 6975 } 6976 } 6977 6978 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) { 6979 assert (UseCompressedOops, "should only be used for compressed headers"); 6980 assert (Universe::heap() != NULL, "java heap should be initialized"); 6981 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6982 int oop_index = oop_recorder()->find_index(obj); 6983 RelocationHolder rspec = oop_Relocation::spec(oop_index); 6984 mov_narrow_oop(dst, oop_index, rspec); 6985 } 6986 6987 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) { 6988 assert (UseCompressedOops, "should only be used for compressed headers"); 6989 assert (Universe::heap() != NULL, "java heap should be initialized"); 6990 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6991 int oop_index = oop_recorder()->find_index(obj); 6992 RelocationHolder rspec = oop_Relocation::spec(oop_index); 6993 mov_narrow_oop(dst, oop_index, rspec); 6994 } 6995 6996 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) { 6997 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 6998 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6999 int klass_index = oop_recorder()->find_index(k); 7000 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 7001 mov_narrow_oop(dst, Klass::encode_klass(k), rspec); 7002 } 7003 7004 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) { 7005 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 7006 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 7007 int klass_index = oop_recorder()->find_index(k); 7008 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 7009 mov_narrow_oop(dst, Klass::encode_klass(k), rspec); 7010 } 7011 7012 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) { 7013 assert (UseCompressedOops, "should only be used for compressed headers"); 7014 assert (Universe::heap() != NULL, "java heap should be initialized"); 7015 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 7016 int oop_index = oop_recorder()->find_index(obj); 7017 RelocationHolder rspec = oop_Relocation::spec(oop_index); 7018 Assembler::cmp_narrow_oop(dst, oop_index, rspec); 7019 } 7020 7021 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) { 7022 assert (UseCompressedOops, "should only be used for compressed headers"); 7023 assert (Universe::heap() != NULL, "java heap should be initialized"); 7024 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 7025 int oop_index = oop_recorder()->find_index(obj); 7026 RelocationHolder rspec = oop_Relocation::spec(oop_index); 7027 Assembler::cmp_narrow_oop(dst, oop_index, rspec); 7028 } 7029 7030 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) { 7031 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 7032 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 7033 int klass_index = oop_recorder()->find_index(k); 7034 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 7035 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec); 7036 } 7037 7038 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) { 7039 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 7040 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 7041 int klass_index = oop_recorder()->find_index(k); 7042 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 7043 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec); 7044 } 7045 7046 void MacroAssembler::reinit_heapbase() { 7047 if (UseCompressedOops || UseCompressedClassPointers) { 7048 if (Universe::heap() != NULL) { 7049 if (Universe::narrow_oop_base() == NULL) { 7050 MacroAssembler::xorptr(r12_heapbase, r12_heapbase); 7051 } else { 7052 mov64(r12_heapbase, (int64_t)Universe::narrow_ptrs_base()); 7053 } 7054 } else { 7055 movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr())); 7056 } 7057 } 7058 } 7059 7060 #endif // _LP64 7061 7062 // C2 compiled method's prolog code. 7063 void MacroAssembler::verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b) { 7064 7065 // WARNING: Initial instruction MUST be 5 bytes or longer so that 7066 // NativeJump::patch_verified_entry will be able to patch out the entry 7067 // code safely. The push to verify stack depth is ok at 5 bytes, 7068 // the frame allocation can be either 3 or 6 bytes. So if we don't do 7069 // stack bang then we must use the 6 byte frame allocation even if 7070 // we have no frame. :-( 7071 assert(stack_bang_size >= framesize || stack_bang_size <= 0, "stack bang size incorrect"); 7072 7073 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); 7074 // Remove word for return addr 7075 framesize -= wordSize; 7076 stack_bang_size -= wordSize; 7077 7078 // Calls to C2R adapters often do not accept exceptional returns. 7079 // We require that their callers must bang for them. But be careful, because 7080 // some VM calls (such as call site linkage) can use several kilobytes of 7081 // stack. But the stack safety zone should account for that. 7082 // See bugs 4446381, 4468289, 4497237. 7083 if (stack_bang_size > 0) { 7084 generate_stack_overflow_check(stack_bang_size); 7085 7086 // We always push rbp, so that on return to interpreter rbp, will be 7087 // restored correctly and we can correct the stack. 7088 push(rbp); 7089 // Save caller's stack pointer into RBP if the frame pointer is preserved. 7090 if (PreserveFramePointer) { 7091 mov(rbp, rsp); 7092 } 7093 // Remove word for ebp 7094 framesize -= wordSize; 7095 7096 // Create frame 7097 if (framesize) { 7098 subptr(rsp, framesize); 7099 } 7100 } else { 7101 // Create frame (force generation of a 4 byte immediate value) 7102 subptr_imm32(rsp, framesize); 7103 7104 // Save RBP register now. 7105 framesize -= wordSize; 7106 movptr(Address(rsp, framesize), rbp); 7107 // Save caller's stack pointer into RBP if the frame pointer is preserved. 7108 if (PreserveFramePointer) { 7109 movptr(rbp, rsp); 7110 if (framesize > 0) { 7111 addptr(rbp, framesize); 7112 } 7113 } 7114 } 7115 7116 if (VerifyStackAtCalls) { // Majik cookie to verify stack depth 7117 framesize -= wordSize; 7118 movptr(Address(rsp, framesize), (int32_t)0xbadb100d); 7119 } 7120 7121 #ifndef _LP64 7122 // If method sets FPU control word do it now 7123 if (fp_mode_24b) { 7124 fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); 7125 } 7126 if (UseSSE >= 2 && VerifyFPU) { 7127 verify_FPU(0, "FPU stack must be clean on entry"); 7128 } 7129 #endif 7130 7131 #ifdef ASSERT 7132 if (VerifyStackAtCalls) { 7133 Label L; 7134 push(rax); 7135 mov(rax, rsp); 7136 andptr(rax, StackAlignmentInBytes-1); 7137 cmpptr(rax, StackAlignmentInBytes-wordSize); 7138 pop(rax); 7139 jcc(Assembler::equal, L); 7140 STOP("Stack is not properly aligned!"); 7141 bind(L); 7142 } 7143 #endif 7144 7145 } 7146 7147 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp, bool is_large) { 7148 // cnt - number of qwords (8-byte words). 7149 // base - start address, qword aligned. 7150 // is_large - if optimizers know cnt is larger than InitArrayShortSize 7151 assert(base==rdi, "base register must be edi for rep stos"); 7152 assert(tmp==rax, "tmp register must be eax for rep stos"); 7153 assert(cnt==rcx, "cnt register must be ecx for rep stos"); 7154 assert(InitArrayShortSize % BytesPerLong == 0, 7155 "InitArrayShortSize should be the multiple of BytesPerLong"); 7156 7157 Label DONE; 7158 7159 xorptr(tmp, tmp); 7160 7161 if (!is_large) { 7162 Label LOOP, LONG; 7163 cmpptr(cnt, InitArrayShortSize/BytesPerLong); 7164 jccb(Assembler::greater, LONG); 7165 7166 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM 7167 7168 decrement(cnt); 7169 jccb(Assembler::negative, DONE); // Zero length 7170 7171 // Use individual pointer-sized stores for small counts: 7172 BIND(LOOP); 7173 movptr(Address(base, cnt, Address::times_ptr), tmp); 7174 decrement(cnt); 7175 jccb(Assembler::greaterEqual, LOOP); 7176 jmpb(DONE); 7177 7178 BIND(LONG); 7179 } 7180 7181 // Use longer rep-prefixed ops for non-small counts: 7182 if (UseFastStosb) { 7183 shlptr(cnt, 3); // convert to number of bytes 7184 rep_stosb(); 7185 } else { 7186 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM 7187 rep_stos(); 7188 } 7189 7190 BIND(DONE); 7191 } 7192 7193 #ifdef COMPILER2 7194 7195 // IndexOf for constant substrings with size >= 8 chars 7196 // which don't need to be loaded through stack. 7197 void MacroAssembler::string_indexofC8(Register str1, Register str2, 7198 Register cnt1, Register cnt2, 7199 int int_cnt2, Register result, 7200 XMMRegister vec, Register tmp, 7201 int ae) { 7202 ShortBranchVerifier sbv(this); 7203 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required"); 7204 assert(ae != StrIntrinsicNode::LU, "Invalid encoding"); 7205 7206 // This method uses the pcmpestri instruction with bound registers 7207 // inputs: 7208 // xmm - substring 7209 // rax - substring length (elements count) 7210 // mem - scanned string 7211 // rdx - string length (elements count) 7212 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts) 7213 // 0xc - mode: 1100 (substring search) + 00 (unsigned bytes) 7214 // outputs: 7215 // rcx - matched index in string 7216 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri"); 7217 int mode = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts 7218 int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8 7219 Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2; 7220 Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1; 7221 7222 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, 7223 RET_FOUND, RET_NOT_FOUND, EXIT, FOUND_SUBSTR, 7224 MATCH_SUBSTR_HEAD, RELOAD_STR, FOUND_CANDIDATE; 7225 7226 // Note, inline_string_indexOf() generates checks: 7227 // if (substr.count > string.count) return -1; 7228 // if (substr.count == 0) return 0; 7229 assert(int_cnt2 >= stride, "this code is used only for cnt2 >= 8 chars"); 7230 7231 // Load substring. 7232 if (ae == StrIntrinsicNode::UL) { 7233 pmovzxbw(vec, Address(str2, 0)); 7234 } else { 7235 movdqu(vec, Address(str2, 0)); 7236 } 7237 movl(cnt2, int_cnt2); 7238 movptr(result, str1); // string addr 7239 7240 if (int_cnt2 > stride) { 7241 jmpb(SCAN_TO_SUBSTR); 7242 7243 // Reload substr for rescan, this code 7244 // is executed only for large substrings (> 8 chars) 7245 bind(RELOAD_SUBSTR); 7246 if (ae == StrIntrinsicNode::UL) { 7247 pmovzxbw(vec, Address(str2, 0)); 7248 } else { 7249 movdqu(vec, Address(str2, 0)); 7250 } 7251 negptr(cnt2); // Jumped here with negative cnt2, convert to positive 7252 7253 bind(RELOAD_STR); 7254 // We came here after the beginning of the substring was 7255 // matched but the rest of it was not so we need to search 7256 // again. Start from the next element after the previous match. 7257 7258 // cnt2 is number of substring reminding elements and 7259 // cnt1 is number of string reminding elements when cmp failed. 7260 // Restored cnt1 = cnt1 - cnt2 + int_cnt2 7261 subl(cnt1, cnt2); 7262 addl(cnt1, int_cnt2); 7263 movl(cnt2, int_cnt2); // Now restore cnt2 7264 7265 decrementl(cnt1); // Shift to next element 7266 cmpl(cnt1, cnt2); 7267 jcc(Assembler::negative, RET_NOT_FOUND); // Left less then substring 7268 7269 addptr(result, (1<<scale1)); 7270 7271 } // (int_cnt2 > 8) 7272 7273 // Scan string for start of substr in 16-byte vectors 7274 bind(SCAN_TO_SUBSTR); 7275 pcmpestri(vec, Address(result, 0), mode); 7276 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1 7277 subl(cnt1, stride); 7278 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string 7279 cmpl(cnt1, cnt2); 7280 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring 7281 addptr(result, 16); 7282 jmpb(SCAN_TO_SUBSTR); 7283 7284 // Found a potential substr 7285 bind(FOUND_CANDIDATE); 7286 // Matched whole vector if first element matched (tmp(rcx) == 0). 7287 if (int_cnt2 == stride) { 7288 jccb(Assembler::overflow, RET_FOUND); // OF == 1 7289 } else { // int_cnt2 > 8 7290 jccb(Assembler::overflow, FOUND_SUBSTR); 7291 } 7292 // After pcmpestri tmp(rcx) contains matched element index 7293 // Compute start addr of substr 7294 lea(result, Address(result, tmp, scale1)); 7295 7296 // Make sure string is still long enough 7297 subl(cnt1, tmp); 7298 cmpl(cnt1, cnt2); 7299 if (int_cnt2 == stride) { 7300 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR); 7301 } else { // int_cnt2 > 8 7302 jccb(Assembler::greaterEqual, MATCH_SUBSTR_HEAD); 7303 } 7304 // Left less then substring. 7305 7306 bind(RET_NOT_FOUND); 7307 movl(result, -1); 7308 jmp(EXIT); 7309 7310 if (int_cnt2 > stride) { 7311 // This code is optimized for the case when whole substring 7312 // is matched if its head is matched. 7313 bind(MATCH_SUBSTR_HEAD); 7314 pcmpestri(vec, Address(result, 0), mode); 7315 // Reload only string if does not match 7316 jcc(Assembler::noOverflow, RELOAD_STR); // OF == 0 7317 7318 Label CONT_SCAN_SUBSTR; 7319 // Compare the rest of substring (> 8 chars). 7320 bind(FOUND_SUBSTR); 7321 // First 8 chars are already matched. 7322 negptr(cnt2); 7323 addptr(cnt2, stride); 7324 7325 bind(SCAN_SUBSTR); 7326 subl(cnt1, stride); 7327 cmpl(cnt2, -stride); // Do not read beyond substring 7328 jccb(Assembler::lessEqual, CONT_SCAN_SUBSTR); 7329 // Back-up strings to avoid reading beyond substring: 7330 // cnt1 = cnt1 - cnt2 + 8 7331 addl(cnt1, cnt2); // cnt2 is negative 7332 addl(cnt1, stride); 7333 movl(cnt2, stride); negptr(cnt2); 7334 bind(CONT_SCAN_SUBSTR); 7335 if (int_cnt2 < (int)G) { 7336 int tail_off1 = int_cnt2<<scale1; 7337 int tail_off2 = int_cnt2<<scale2; 7338 if (ae == StrIntrinsicNode::UL) { 7339 pmovzxbw(vec, Address(str2, cnt2, scale2, tail_off2)); 7340 } else { 7341 movdqu(vec, Address(str2, cnt2, scale2, tail_off2)); 7342 } 7343 pcmpestri(vec, Address(result, cnt2, scale1, tail_off1), mode); 7344 } else { 7345 // calculate index in register to avoid integer overflow (int_cnt2*2) 7346 movl(tmp, int_cnt2); 7347 addptr(tmp, cnt2); 7348 if (ae == StrIntrinsicNode::UL) { 7349 pmovzxbw(vec, Address(str2, tmp, scale2, 0)); 7350 } else { 7351 movdqu(vec, Address(str2, tmp, scale2, 0)); 7352 } 7353 pcmpestri(vec, Address(result, tmp, scale1, 0), mode); 7354 } 7355 // Need to reload strings pointers if not matched whole vector 7356 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0 7357 addptr(cnt2, stride); 7358 jcc(Assembler::negative, SCAN_SUBSTR); 7359 // Fall through if found full substring 7360 7361 } // (int_cnt2 > 8) 7362 7363 bind(RET_FOUND); 7364 // Found result if we matched full small substring. 7365 // Compute substr offset 7366 subptr(result, str1); 7367 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) { 7368 shrl(result, 1); // index 7369 } 7370 bind(EXIT); 7371 7372 } // string_indexofC8 7373 7374 // Small strings are loaded through stack if they cross page boundary. 7375 void MacroAssembler::string_indexof(Register str1, Register str2, 7376 Register cnt1, Register cnt2, 7377 int int_cnt2, Register result, 7378 XMMRegister vec, Register tmp, 7379 int ae) { 7380 ShortBranchVerifier sbv(this); 7381 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required"); 7382 assert(ae != StrIntrinsicNode::LU, "Invalid encoding"); 7383 7384 // 7385 // int_cnt2 is length of small (< 8 chars) constant substring 7386 // or (-1) for non constant substring in which case its length 7387 // is in cnt2 register. 7388 // 7389 // Note, inline_string_indexOf() generates checks: 7390 // if (substr.count > string.count) return -1; 7391 // if (substr.count == 0) return 0; 7392 // 7393 int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8 7394 assert(int_cnt2 == -1 || (0 < int_cnt2 && int_cnt2 < stride), "should be != 0"); 7395 // This method uses the pcmpestri instruction with bound registers 7396 // inputs: 7397 // xmm - substring 7398 // rax - substring length (elements count) 7399 // mem - scanned string 7400 // rdx - string length (elements count) 7401 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts) 7402 // 0xc - mode: 1100 (substring search) + 00 (unsigned bytes) 7403 // outputs: 7404 // rcx - matched index in string 7405 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri"); 7406 int mode = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts 7407 Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2; 7408 Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1; 7409 7410 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, ADJUST_STR, 7411 RET_FOUND, RET_NOT_FOUND, CLEANUP, FOUND_SUBSTR, 7412 FOUND_CANDIDATE; 7413 7414 { //======================================================== 7415 // We don't know where these strings are located 7416 // and we can't read beyond them. Load them through stack. 7417 Label BIG_STRINGS, CHECK_STR, COPY_SUBSTR, COPY_STR; 7418 7419 movptr(tmp, rsp); // save old SP 7420 7421 if (int_cnt2 > 0) { // small (< 8 chars) constant substring 7422 if (int_cnt2 == (1>>scale2)) { // One byte 7423 assert((ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL), "Only possible for latin1 encoding"); 7424 load_unsigned_byte(result, Address(str2, 0)); 7425 movdl(vec, result); // move 32 bits 7426 } else if (ae == StrIntrinsicNode::LL && int_cnt2 == 3) { // Three bytes 7427 // Not enough header space in 32-bit VM: 12+3 = 15. 7428 movl(result, Address(str2, -1)); 7429 shrl(result, 8); 7430 movdl(vec, result); // move 32 bits 7431 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (2>>scale2)) { // One char 7432 load_unsigned_short(result, Address(str2, 0)); 7433 movdl(vec, result); // move 32 bits 7434 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (4>>scale2)) { // Two chars 7435 movdl(vec, Address(str2, 0)); // move 32 bits 7436 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (8>>scale2)) { // Four chars 7437 movq(vec, Address(str2, 0)); // move 64 bits 7438 } else { // cnt2 = { 3, 5, 6, 7 } || (ae == StrIntrinsicNode::UL && cnt2 ={2, ..., 7}) 7439 // Array header size is 12 bytes in 32-bit VM 7440 // + 6 bytes for 3 chars == 18 bytes, 7441 // enough space to load vec and shift. 7442 assert(HeapWordSize*TypeArrayKlass::header_size() >= 12,"sanity"); 7443 if (ae == StrIntrinsicNode::UL) { 7444 int tail_off = int_cnt2-8; 7445 pmovzxbw(vec, Address(str2, tail_off)); 7446 psrldq(vec, -2*tail_off); 7447 } 7448 else { 7449 int tail_off = int_cnt2*(1<<scale2); 7450 movdqu(vec, Address(str2, tail_off-16)); 7451 psrldq(vec, 16-tail_off); 7452 } 7453 } 7454 } else { // not constant substring 7455 cmpl(cnt2, stride); 7456 jccb(Assembler::aboveEqual, BIG_STRINGS); // Both strings are big enough 7457 7458 // We can read beyond string if srt+16 does not cross page boundary 7459 // since heaps are aligned and mapped by pages. 7460 assert(os::vm_page_size() < (int)G, "default page should be small"); 7461 movl(result, str2); // We need only low 32 bits 7462 andl(result, (os::vm_page_size()-1)); 7463 cmpl(result, (os::vm_page_size()-16)); 7464 jccb(Assembler::belowEqual, CHECK_STR); 7465 7466 // Move small strings to stack to allow load 16 bytes into vec. 7467 subptr(rsp, 16); 7468 int stk_offset = wordSize-(1<<scale2); 7469 push(cnt2); 7470 7471 bind(COPY_SUBSTR); 7472 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL) { 7473 load_unsigned_byte(result, Address(str2, cnt2, scale2, -1)); 7474 movb(Address(rsp, cnt2, scale2, stk_offset), result); 7475 } else if (ae == StrIntrinsicNode::UU) { 7476 load_unsigned_short(result, Address(str2, cnt2, scale2, -2)); 7477 movw(Address(rsp, cnt2, scale2, stk_offset), result); 7478 } 7479 decrement(cnt2); 7480 jccb(Assembler::notZero, COPY_SUBSTR); 7481 7482 pop(cnt2); 7483 movptr(str2, rsp); // New substring address 7484 } // non constant 7485 7486 bind(CHECK_STR); 7487 cmpl(cnt1, stride); 7488 jccb(Assembler::aboveEqual, BIG_STRINGS); 7489 7490 // Check cross page boundary. 7491 movl(result, str1); // We need only low 32 bits 7492 andl(result, (os::vm_page_size()-1)); 7493 cmpl(result, (os::vm_page_size()-16)); 7494 jccb(Assembler::belowEqual, BIG_STRINGS); 7495 7496 subptr(rsp, 16); 7497 int stk_offset = -(1<<scale1); 7498 if (int_cnt2 < 0) { // not constant 7499 push(cnt2); 7500 stk_offset += wordSize; 7501 } 7502 movl(cnt2, cnt1); 7503 7504 bind(COPY_STR); 7505 if (ae == StrIntrinsicNode::LL) { 7506 load_unsigned_byte(result, Address(str1, cnt2, scale1, -1)); 7507 movb(Address(rsp, cnt2, scale1, stk_offset), result); 7508 } else { 7509 load_unsigned_short(result, Address(str1, cnt2, scale1, -2)); 7510 movw(Address(rsp, cnt2, scale1, stk_offset), result); 7511 } 7512 decrement(cnt2); 7513 jccb(Assembler::notZero, COPY_STR); 7514 7515 if (int_cnt2 < 0) { // not constant 7516 pop(cnt2); 7517 } 7518 movptr(str1, rsp); // New string address 7519 7520 bind(BIG_STRINGS); 7521 // Load substring. 7522 if (int_cnt2 < 0) { // -1 7523 if (ae == StrIntrinsicNode::UL) { 7524 pmovzxbw(vec, Address(str2, 0)); 7525 } else { 7526 movdqu(vec, Address(str2, 0)); 7527 } 7528 push(cnt2); // substr count 7529 push(str2); // substr addr 7530 push(str1); // string addr 7531 } else { 7532 // Small (< 8 chars) constant substrings are loaded already. 7533 movl(cnt2, int_cnt2); 7534 } 7535 push(tmp); // original SP 7536 7537 } // Finished loading 7538 7539 //======================================================== 7540 // Start search 7541 // 7542 7543 movptr(result, str1); // string addr 7544 7545 if (int_cnt2 < 0) { // Only for non constant substring 7546 jmpb(SCAN_TO_SUBSTR); 7547 7548 // SP saved at sp+0 7549 // String saved at sp+1*wordSize 7550 // Substr saved at sp+2*wordSize 7551 // Substr count saved at sp+3*wordSize 7552 7553 // Reload substr for rescan, this code 7554 // is executed only for large substrings (> 8 chars) 7555 bind(RELOAD_SUBSTR); 7556 movptr(str2, Address(rsp, 2*wordSize)); 7557 movl(cnt2, Address(rsp, 3*wordSize)); 7558 if (ae == StrIntrinsicNode::UL) { 7559 pmovzxbw(vec, Address(str2, 0)); 7560 } else { 7561 movdqu(vec, Address(str2, 0)); 7562 } 7563 // We came here after the beginning of the substring was 7564 // matched but the rest of it was not so we need to search 7565 // again. Start from the next element after the previous match. 7566 subptr(str1, result); // Restore counter 7567 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) { 7568 shrl(str1, 1); 7569 } 7570 addl(cnt1, str1); 7571 decrementl(cnt1); // Shift to next element 7572 cmpl(cnt1, cnt2); 7573 jcc(Assembler::negative, RET_NOT_FOUND); // Left less then substring 7574 7575 addptr(result, (1<<scale1)); 7576 } // non constant 7577 7578 // Scan string for start of substr in 16-byte vectors 7579 bind(SCAN_TO_SUBSTR); 7580 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri"); 7581 pcmpestri(vec, Address(result, 0), mode); 7582 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1 7583 subl(cnt1, stride); 7584 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string 7585 cmpl(cnt1, cnt2); 7586 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring 7587 addptr(result, 16); 7588 7589 bind(ADJUST_STR); 7590 cmpl(cnt1, stride); // Do not read beyond string 7591 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR); 7592 // Back-up string to avoid reading beyond string. 7593 lea(result, Address(result, cnt1, scale1, -16)); 7594 movl(cnt1, stride); 7595 jmpb(SCAN_TO_SUBSTR); 7596 7597 // Found a potential substr 7598 bind(FOUND_CANDIDATE); 7599 // After pcmpestri tmp(rcx) contains matched element index 7600 7601 // Make sure string is still long enough 7602 subl(cnt1, tmp); 7603 cmpl(cnt1, cnt2); 7604 jccb(Assembler::greaterEqual, FOUND_SUBSTR); 7605 // Left less then substring. 7606 7607 bind(RET_NOT_FOUND); 7608 movl(result, -1); 7609 jmpb(CLEANUP); 7610 7611 bind(FOUND_SUBSTR); 7612 // Compute start addr of substr 7613 lea(result, Address(result, tmp, scale1)); 7614 if (int_cnt2 > 0) { // Constant substring 7615 // Repeat search for small substring (< 8 chars) 7616 // from new point without reloading substring. 7617 // Have to check that we don't read beyond string. 7618 cmpl(tmp, stride-int_cnt2); 7619 jccb(Assembler::greater, ADJUST_STR); 7620 // Fall through if matched whole substring. 7621 } else { // non constant 7622 assert(int_cnt2 == -1, "should be != 0"); 7623 7624 addl(tmp, cnt2); 7625 // Found result if we matched whole substring. 7626 cmpl(tmp, stride); 7627 jccb(Assembler::lessEqual, RET_FOUND); 7628 7629 // Repeat search for small substring (<= 8 chars) 7630 // from new point 'str1' without reloading substring. 7631 cmpl(cnt2, stride); 7632 // Have to check that we don't read beyond string. 7633 jccb(Assembler::lessEqual, ADJUST_STR); 7634 7635 Label CHECK_NEXT, CONT_SCAN_SUBSTR, RET_FOUND_LONG; 7636 // Compare the rest of substring (> 8 chars). 7637 movptr(str1, result); 7638 7639 cmpl(tmp, cnt2); 7640 // First 8 chars are already matched. 7641 jccb(Assembler::equal, CHECK_NEXT); 7642 7643 bind(SCAN_SUBSTR); 7644 pcmpestri(vec, Address(str1, 0), mode); 7645 // Need to reload strings pointers if not matched whole vector 7646 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0 7647 7648 bind(CHECK_NEXT); 7649 subl(cnt2, stride); 7650 jccb(Assembler::lessEqual, RET_FOUND_LONG); // Found full substring 7651 addptr(str1, 16); 7652 if (ae == StrIntrinsicNode::UL) { 7653 addptr(str2, 8); 7654 } else { 7655 addptr(str2, 16); 7656 } 7657 subl(cnt1, stride); 7658 cmpl(cnt2, stride); // Do not read beyond substring 7659 jccb(Assembler::greaterEqual, CONT_SCAN_SUBSTR); 7660 // Back-up strings to avoid reading beyond substring. 7661 7662 if (ae == StrIntrinsicNode::UL) { 7663 lea(str2, Address(str2, cnt2, scale2, -8)); 7664 lea(str1, Address(str1, cnt2, scale1, -16)); 7665 } else { 7666 lea(str2, Address(str2, cnt2, scale2, -16)); 7667 lea(str1, Address(str1, cnt2, scale1, -16)); 7668 } 7669 subl(cnt1, cnt2); 7670 movl(cnt2, stride); 7671 addl(cnt1, stride); 7672 bind(CONT_SCAN_SUBSTR); 7673 if (ae == StrIntrinsicNode::UL) { 7674 pmovzxbw(vec, Address(str2, 0)); 7675 } else { 7676 movdqu(vec, Address(str2, 0)); 7677 } 7678 jmp(SCAN_SUBSTR); 7679 7680 bind(RET_FOUND_LONG); 7681 movptr(str1, Address(rsp, wordSize)); 7682 } // non constant 7683 7684 bind(RET_FOUND); 7685 // Compute substr offset 7686 subptr(result, str1); 7687 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) { 7688 shrl(result, 1); // index 7689 } 7690 bind(CLEANUP); 7691 pop(rsp); // restore SP 7692 7693 } // string_indexof 7694 7695 void MacroAssembler::string_indexof_char(Register str1, Register cnt1, Register ch, Register result, 7696 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp) { 7697 ShortBranchVerifier sbv(this); 7698 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required"); 7699 7700 int stride = 8; 7701 7702 Label FOUND_CHAR, SCAN_TO_CHAR, SCAN_TO_CHAR_LOOP, 7703 SCAN_TO_8_CHAR, SCAN_TO_8_CHAR_LOOP, SCAN_TO_16_CHAR_LOOP, 7704 RET_NOT_FOUND, SCAN_TO_8_CHAR_INIT, 7705 FOUND_SEQ_CHAR, DONE_LABEL; 7706 7707 movptr(result, str1); 7708 if (UseAVX >= 2) { 7709 cmpl(cnt1, stride); 7710 jcc(Assembler::less, SCAN_TO_CHAR_LOOP); 7711 cmpl(cnt1, 2*stride); 7712 jcc(Assembler::less, SCAN_TO_8_CHAR_INIT); 7713 movdl(vec1, ch); 7714 vpbroadcastw(vec1, vec1); 7715 vpxor(vec2, vec2); 7716 movl(tmp, cnt1); 7717 andl(tmp, 0xFFFFFFF0); //vector count (in chars) 7718 andl(cnt1,0x0000000F); //tail count (in chars) 7719 7720 bind(SCAN_TO_16_CHAR_LOOP); 7721 vmovdqu(vec3, Address(result, 0)); 7722 vpcmpeqw(vec3, vec3, vec1, 1); 7723 vptest(vec2, vec3); 7724 jcc(Assembler::carryClear, FOUND_CHAR); 7725 addptr(result, 32); 7726 subl(tmp, 2*stride); 7727 jccb(Assembler::notZero, SCAN_TO_16_CHAR_LOOP); 7728 jmp(SCAN_TO_8_CHAR); 7729 bind(SCAN_TO_8_CHAR_INIT); 7730 movdl(vec1, ch); 7731 pshuflw(vec1, vec1, 0x00); 7732 pshufd(vec1, vec1, 0); 7733 pxor(vec2, vec2); 7734 } 7735 bind(SCAN_TO_8_CHAR); 7736 cmpl(cnt1, stride); 7737 if (UseAVX >= 2) { 7738 jcc(Assembler::less, SCAN_TO_CHAR); 7739 } else { 7740 jcc(Assembler::less, SCAN_TO_CHAR_LOOP); 7741 movdl(vec1, ch); 7742 pshuflw(vec1, vec1, 0x00); 7743 pshufd(vec1, vec1, 0); 7744 pxor(vec2, vec2); 7745 } 7746 movl(tmp, cnt1); 7747 andl(tmp, 0xFFFFFFF8); //vector count (in chars) 7748 andl(cnt1,0x00000007); //tail count (in chars) 7749 7750 bind(SCAN_TO_8_CHAR_LOOP); 7751 movdqu(vec3, Address(result, 0)); 7752 pcmpeqw(vec3, vec1); 7753 ptest(vec2, vec3); 7754 jcc(Assembler::carryClear, FOUND_CHAR); 7755 addptr(result, 16); 7756 subl(tmp, stride); 7757 jccb(Assembler::notZero, SCAN_TO_8_CHAR_LOOP); 7758 bind(SCAN_TO_CHAR); 7759 testl(cnt1, cnt1); 7760 jcc(Assembler::zero, RET_NOT_FOUND); 7761 bind(SCAN_TO_CHAR_LOOP); 7762 load_unsigned_short(tmp, Address(result, 0)); 7763 cmpl(ch, tmp); 7764 jccb(Assembler::equal, FOUND_SEQ_CHAR); 7765 addptr(result, 2); 7766 subl(cnt1, 1); 7767 jccb(Assembler::zero, RET_NOT_FOUND); 7768 jmp(SCAN_TO_CHAR_LOOP); 7769 7770 bind(RET_NOT_FOUND); 7771 movl(result, -1); 7772 jmpb(DONE_LABEL); 7773 7774 bind(FOUND_CHAR); 7775 if (UseAVX >= 2) { 7776 vpmovmskb(tmp, vec3); 7777 } else { 7778 pmovmskb(tmp, vec3); 7779 } 7780 bsfl(ch, tmp); 7781 addl(result, ch); 7782 7783 bind(FOUND_SEQ_CHAR); 7784 subptr(result, str1); 7785 shrl(result, 1); 7786 7787 bind(DONE_LABEL); 7788 } // string_indexof_char 7789 7790 // helper function for string_compare 7791 void MacroAssembler::load_next_elements(Register elem1, Register elem2, Register str1, Register str2, 7792 Address::ScaleFactor scale, Address::ScaleFactor scale1, 7793 Address::ScaleFactor scale2, Register index, int ae) { 7794 if (ae == StrIntrinsicNode::LL) { 7795 load_unsigned_byte(elem1, Address(str1, index, scale, 0)); 7796 load_unsigned_byte(elem2, Address(str2, index, scale, 0)); 7797 } else if (ae == StrIntrinsicNode::UU) { 7798 load_unsigned_short(elem1, Address(str1, index, scale, 0)); 7799 load_unsigned_short(elem2, Address(str2, index, scale, 0)); 7800 } else { 7801 load_unsigned_byte(elem1, Address(str1, index, scale1, 0)); 7802 load_unsigned_short(elem2, Address(str2, index, scale2, 0)); 7803 } 7804 } 7805 7806 // Compare strings, used for char[] and byte[]. 7807 void MacroAssembler::string_compare(Register str1, Register str2, 7808 Register cnt1, Register cnt2, Register result, 7809 XMMRegister vec1, int ae) { 7810 ShortBranchVerifier sbv(this); 7811 Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL; 7812 Label COMPARE_WIDE_VECTORS_LOOP_FAILED; // used only _LP64 && AVX3 7813 int stride, stride2, adr_stride, adr_stride1, adr_stride2; 7814 int stride2x2 = 0x40; 7815 Address::ScaleFactor scale = Address::no_scale; 7816 Address::ScaleFactor scale1 = Address::no_scale; 7817 Address::ScaleFactor scale2 = Address::no_scale; 7818 7819 if (ae != StrIntrinsicNode::LL) { 7820 stride2x2 = 0x20; 7821 } 7822 7823 if (ae == StrIntrinsicNode::LU || ae == StrIntrinsicNode::UL) { 7824 shrl(cnt2, 1); 7825 } 7826 // Compute the minimum of the string lengths and the 7827 // difference of the string lengths (stack). 7828 // Do the conditional move stuff 7829 movl(result, cnt1); 7830 subl(cnt1, cnt2); 7831 push(cnt1); 7832 cmov32(Assembler::lessEqual, cnt2, result); // cnt2 = min(cnt1, cnt2) 7833 7834 // Is the minimum length zero? 7835 testl(cnt2, cnt2); 7836 jcc(Assembler::zero, LENGTH_DIFF_LABEL); 7837 if (ae == StrIntrinsicNode::LL) { 7838 // Load first bytes 7839 load_unsigned_byte(result, Address(str1, 0)); // result = str1[0] 7840 load_unsigned_byte(cnt1, Address(str2, 0)); // cnt1 = str2[0] 7841 } else if (ae == StrIntrinsicNode::UU) { 7842 // Load first characters 7843 load_unsigned_short(result, Address(str1, 0)); 7844 load_unsigned_short(cnt1, Address(str2, 0)); 7845 } else { 7846 load_unsigned_byte(result, Address(str1, 0)); 7847 load_unsigned_short(cnt1, Address(str2, 0)); 7848 } 7849 subl(result, cnt1); 7850 jcc(Assembler::notZero, POP_LABEL); 7851 7852 if (ae == StrIntrinsicNode::UU) { 7853 // Divide length by 2 to get number of chars 7854 shrl(cnt2, 1); 7855 } 7856 cmpl(cnt2, 1); 7857 jcc(Assembler::equal, LENGTH_DIFF_LABEL); 7858 7859 // Check if the strings start at the same location and setup scale and stride 7860 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7861 cmpptr(str1, str2); 7862 jcc(Assembler::equal, LENGTH_DIFF_LABEL); 7863 if (ae == StrIntrinsicNode::LL) { 7864 scale = Address::times_1; 7865 stride = 16; 7866 } else { 7867 scale = Address::times_2; 7868 stride = 8; 7869 } 7870 } else { 7871 scale1 = Address::times_1; 7872 scale2 = Address::times_2; 7873 // scale not used 7874 stride = 8; 7875 } 7876 7877 if (UseAVX >= 2 && UseSSE42Intrinsics) { 7878 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_WIDE_TAIL, COMPARE_SMALL_STR; 7879 Label COMPARE_WIDE_VECTORS_LOOP, COMPARE_16_CHARS, COMPARE_INDEX_CHAR; 7880 Label COMPARE_WIDE_VECTORS_LOOP_AVX2; 7881 Label COMPARE_TAIL_LONG; 7882 Label COMPARE_WIDE_VECTORS_LOOP_AVX3; // used only _LP64 && AVX3 7883 7884 int pcmpmask = 0x19; 7885 if (ae == StrIntrinsicNode::LL) { 7886 pcmpmask &= ~0x01; 7887 } 7888 7889 // Setup to compare 16-chars (32-bytes) vectors, 7890 // start from first character again because it has aligned address. 7891 if (ae == StrIntrinsicNode::LL) { 7892 stride2 = 32; 7893 } else { 7894 stride2 = 16; 7895 } 7896 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7897 adr_stride = stride << scale; 7898 } else { 7899 adr_stride1 = 8; //stride << scale1; 7900 adr_stride2 = 16; //stride << scale2; 7901 } 7902 7903 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri"); 7904 // rax and rdx are used by pcmpestri as elements counters 7905 movl(result, cnt2); 7906 andl(cnt2, ~(stride2-1)); // cnt2 holds the vector count 7907 jcc(Assembler::zero, COMPARE_TAIL_LONG); 7908 7909 // fast path : compare first 2 8-char vectors. 7910 bind(COMPARE_16_CHARS); 7911 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7912 movdqu(vec1, Address(str1, 0)); 7913 } else { 7914 pmovzxbw(vec1, Address(str1, 0)); 7915 } 7916 pcmpestri(vec1, Address(str2, 0), pcmpmask); 7917 jccb(Assembler::below, COMPARE_INDEX_CHAR); 7918 7919 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7920 movdqu(vec1, Address(str1, adr_stride)); 7921 pcmpestri(vec1, Address(str2, adr_stride), pcmpmask); 7922 } else { 7923 pmovzxbw(vec1, Address(str1, adr_stride1)); 7924 pcmpestri(vec1, Address(str2, adr_stride2), pcmpmask); 7925 } 7926 jccb(Assembler::aboveEqual, COMPARE_WIDE_VECTORS); 7927 addl(cnt1, stride); 7928 7929 // Compare the characters at index in cnt1 7930 bind(COMPARE_INDEX_CHAR); // cnt1 has the offset of the mismatching character 7931 load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae); 7932 subl(result, cnt2); 7933 jmp(POP_LABEL); 7934 7935 // Setup the registers to start vector comparison loop 7936 bind(COMPARE_WIDE_VECTORS); 7937 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7938 lea(str1, Address(str1, result, scale)); 7939 lea(str2, Address(str2, result, scale)); 7940 } else { 7941 lea(str1, Address(str1, result, scale1)); 7942 lea(str2, Address(str2, result, scale2)); 7943 } 7944 subl(result, stride2); 7945 subl(cnt2, stride2); 7946 jcc(Assembler::zero, COMPARE_WIDE_TAIL); 7947 negptr(result); 7948 7949 // In a loop, compare 16-chars (32-bytes) at once using (vpxor+vptest) 7950 bind(COMPARE_WIDE_VECTORS_LOOP); 7951 7952 #ifdef _LP64 7953 if (VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop 7954 cmpl(cnt2, stride2x2); 7955 jccb(Assembler::below, COMPARE_WIDE_VECTORS_LOOP_AVX2); 7956 testl(cnt2, stride2x2-1); // cnt2 holds the vector count 7957 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX2); // means we cannot subtract by 0x40 7958 7959 bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop 7960 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7961 evmovdquq(vec1, Address(str1, result, scale), Assembler::AVX_512bit); 7962 evpcmpeqb(k7, vec1, Address(str2, result, scale), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0 7963 } else { 7964 vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_512bit); 7965 evpcmpeqb(k7, vec1, Address(str2, result, scale2), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0 7966 } 7967 kortestql(k7, k7); 7968 jcc(Assembler::aboveEqual, COMPARE_WIDE_VECTORS_LOOP_FAILED); // miscompare 7969 addptr(result, stride2x2); // update since we already compared at this addr 7970 subl(cnt2, stride2x2); // and sub the size too 7971 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX3); 7972 7973 vpxor(vec1, vec1); 7974 jmpb(COMPARE_WIDE_TAIL); 7975 }//if (VM_Version::supports_avx512vlbw()) 7976 #endif // _LP64 7977 7978 7979 bind(COMPARE_WIDE_VECTORS_LOOP_AVX2); 7980 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7981 vmovdqu(vec1, Address(str1, result, scale)); 7982 vpxor(vec1, Address(str2, result, scale)); 7983 } else { 7984 vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_256bit); 7985 vpxor(vec1, Address(str2, result, scale2)); 7986 } 7987 vptest(vec1, vec1); 7988 jcc(Assembler::notZero, VECTOR_NOT_EQUAL); 7989 addptr(result, stride2); 7990 subl(cnt2, stride2); 7991 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP); 7992 // clean upper bits of YMM registers 7993 vpxor(vec1, vec1); 7994 7995 // compare wide vectors tail 7996 bind(COMPARE_WIDE_TAIL); 7997 testptr(result, result); 7998 jcc(Assembler::zero, LENGTH_DIFF_LABEL); 7999 8000 movl(result, stride2); 8001 movl(cnt2, result); 8002 negptr(result); 8003 jmp(COMPARE_WIDE_VECTORS_LOOP_AVX2); 8004 8005 // Identifies the mismatching (higher or lower)16-bytes in the 32-byte vectors. 8006 bind(VECTOR_NOT_EQUAL); 8007 // clean upper bits of YMM registers 8008 vpxor(vec1, vec1); 8009 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 8010 lea(str1, Address(str1, result, scale)); 8011 lea(str2, Address(str2, result, scale)); 8012 } else { 8013 lea(str1, Address(str1, result, scale1)); 8014 lea(str2, Address(str2, result, scale2)); 8015 } 8016 jmp(COMPARE_16_CHARS); 8017 8018 // Compare tail chars, length between 1 to 15 chars 8019 bind(COMPARE_TAIL_LONG); 8020 movl(cnt2, result); 8021 cmpl(cnt2, stride); 8022 jcc(Assembler::less, COMPARE_SMALL_STR); 8023 8024 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 8025 movdqu(vec1, Address(str1, 0)); 8026 } else { 8027 pmovzxbw(vec1, Address(str1, 0)); 8028 } 8029 pcmpestri(vec1, Address(str2, 0), pcmpmask); 8030 jcc(Assembler::below, COMPARE_INDEX_CHAR); 8031 subptr(cnt2, stride); 8032 jcc(Assembler::zero, LENGTH_DIFF_LABEL); 8033 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 8034 lea(str1, Address(str1, result, scale)); 8035 lea(str2, Address(str2, result, scale)); 8036 } else { 8037 lea(str1, Address(str1, result, scale1)); 8038 lea(str2, Address(str2, result, scale2)); 8039 } 8040 negptr(cnt2); 8041 jmpb(WHILE_HEAD_LABEL); 8042 8043 bind(COMPARE_SMALL_STR); 8044 } else if (UseSSE42Intrinsics) { 8045 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL; 8046 int pcmpmask = 0x19; 8047 // Setup to compare 8-char (16-byte) vectors, 8048 // start from first character again because it has aligned address. 8049 movl(result, cnt2); 8050 andl(cnt2, ~(stride - 1)); // cnt2 holds the vector count 8051 if (ae == StrIntrinsicNode::LL) { 8052 pcmpmask &= ~0x01; 8053 } 8054 jcc(Assembler::zero, COMPARE_TAIL); 8055 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 8056 lea(str1, Address(str1, result, scale)); 8057 lea(str2, Address(str2, result, scale)); 8058 } else { 8059 lea(str1, Address(str1, result, scale1)); 8060 lea(str2, Address(str2, result, scale2)); 8061 } 8062 negptr(result); 8063 8064 // pcmpestri 8065 // inputs: 8066 // vec1- substring 8067 // rax - negative string length (elements count) 8068 // mem - scanned string 8069 // rdx - string length (elements count) 8070 // pcmpmask - cmp mode: 11000 (string compare with negated result) 8071 // + 00 (unsigned bytes) or + 01 (unsigned shorts) 8072 // outputs: 8073 // rcx - first mismatched element index 8074 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri"); 8075 8076 bind(COMPARE_WIDE_VECTORS); 8077 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 8078 movdqu(vec1, Address(str1, result, scale)); 8079 pcmpestri(vec1, Address(str2, result, scale), pcmpmask); 8080 } else { 8081 pmovzxbw(vec1, Address(str1, result, scale1)); 8082 pcmpestri(vec1, Address(str2, result, scale2), pcmpmask); 8083 } 8084 // After pcmpestri cnt1(rcx) contains mismatched element index 8085 8086 jccb(Assembler::below, VECTOR_NOT_EQUAL); // CF==1 8087 addptr(result, stride); 8088 subptr(cnt2, stride); 8089 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS); 8090 8091 // compare wide vectors tail 8092 testptr(result, result); 8093 jcc(Assembler::zero, LENGTH_DIFF_LABEL); 8094 8095 movl(cnt2, stride); 8096 movl(result, stride); 8097 negptr(result); 8098 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 8099 movdqu(vec1, Address(str1, result, scale)); 8100 pcmpestri(vec1, Address(str2, result, scale), pcmpmask); 8101 } else { 8102 pmovzxbw(vec1, Address(str1, result, scale1)); 8103 pcmpestri(vec1, Address(str2, result, scale2), pcmpmask); 8104 } 8105 jccb(Assembler::aboveEqual, LENGTH_DIFF_LABEL); 8106 8107 // Mismatched characters in the vectors 8108 bind(VECTOR_NOT_EQUAL); 8109 addptr(cnt1, result); 8110 load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae); 8111 subl(result, cnt2); 8112 jmpb(POP_LABEL); 8113 8114 bind(COMPARE_TAIL); // limit is zero 8115 movl(cnt2, result); 8116 // Fallthru to tail compare 8117 } 8118 // Shift str2 and str1 to the end of the arrays, negate min 8119 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 8120 lea(str1, Address(str1, cnt2, scale)); 8121 lea(str2, Address(str2, cnt2, scale)); 8122 } else { 8123 lea(str1, Address(str1, cnt2, scale1)); 8124 lea(str2, Address(str2, cnt2, scale2)); 8125 } 8126 decrementl(cnt2); // first character was compared already 8127 negptr(cnt2); 8128 8129 // Compare the rest of the elements 8130 bind(WHILE_HEAD_LABEL); 8131 load_next_elements(result, cnt1, str1, str2, scale, scale1, scale2, cnt2, ae); 8132 subl(result, cnt1); 8133 jccb(Assembler::notZero, POP_LABEL); 8134 increment(cnt2); 8135 jccb(Assembler::notZero, WHILE_HEAD_LABEL); 8136 8137 // Strings are equal up to min length. Return the length difference. 8138 bind(LENGTH_DIFF_LABEL); 8139 pop(result); 8140 if (ae == StrIntrinsicNode::UU) { 8141 // Divide diff by 2 to get number of chars 8142 sarl(result, 1); 8143 } 8144 jmpb(DONE_LABEL); 8145 8146 #ifdef _LP64 8147 if (VM_Version::supports_avx512vlbw()) { 8148 8149 bind(COMPARE_WIDE_VECTORS_LOOP_FAILED); 8150 8151 kmovql(cnt1, k7); 8152 notq(cnt1); 8153 bsfq(cnt2, cnt1); 8154 if (ae != StrIntrinsicNode::LL) { 8155 // Divide diff by 2 to get number of chars 8156 sarl(cnt2, 1); 8157 } 8158 addq(result, cnt2); 8159 if (ae == StrIntrinsicNode::LL) { 8160 load_unsigned_byte(cnt1, Address(str2, result)); 8161 load_unsigned_byte(result, Address(str1, result)); 8162 } else if (ae == StrIntrinsicNode::UU) { 8163 load_unsigned_short(cnt1, Address(str2, result, scale)); 8164 load_unsigned_short(result, Address(str1, result, scale)); 8165 } else { 8166 load_unsigned_short(cnt1, Address(str2, result, scale2)); 8167 load_unsigned_byte(result, Address(str1, result, scale1)); 8168 } 8169 subl(result, cnt1); 8170 jmpb(POP_LABEL); 8171 }//if (VM_Version::supports_avx512vlbw()) 8172 #endif // _LP64 8173 8174 // Discard the stored length difference 8175 bind(POP_LABEL); 8176 pop(cnt1); 8177 8178 // That's it 8179 bind(DONE_LABEL); 8180 if(ae == StrIntrinsicNode::UL) { 8181 negl(result); 8182 } 8183 8184 } 8185 8186 // Search for Non-ASCII character (Negative byte value) in a byte array, 8187 // return true if it has any and false otherwise. 8188 // ..\jdk\src\java.base\share\classes\java\lang\StringCoding.java 8189 // @HotSpotIntrinsicCandidate 8190 // private static boolean hasNegatives(byte[] ba, int off, int len) { 8191 // for (int i = off; i < off + len; i++) { 8192 // if (ba[i] < 0) { 8193 // return true; 8194 // } 8195 // } 8196 // return false; 8197 // } 8198 void MacroAssembler::has_negatives(Register ary1, Register len, 8199 Register result, Register tmp1, 8200 XMMRegister vec1, XMMRegister vec2) { 8201 // rsi: byte array 8202 // rcx: len 8203 // rax: result 8204 ShortBranchVerifier sbv(this); 8205 assert_different_registers(ary1, len, result, tmp1); 8206 assert_different_registers(vec1, vec2); 8207 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_CHAR, COMPARE_VECTORS, COMPARE_BYTE; 8208 8209 // len == 0 8210 testl(len, len); 8211 jcc(Assembler::zero, FALSE_LABEL); 8212 8213 if ((UseAVX > 2) && // AVX512 8214 VM_Version::supports_avx512vlbw() && 8215 VM_Version::supports_bmi2()) { 8216 8217 set_vector_masking(); // opening of the stub context for programming mask registers 8218 8219 Label test_64_loop, test_tail; 8220 Register tmp3_aliased = len; 8221 8222 movl(tmp1, len); 8223 vpxor(vec2, vec2, vec2, Assembler::AVX_512bit); 8224 8225 andl(tmp1, 64 - 1); // tail count (in chars) 0x3F 8226 andl(len, ~(64 - 1)); // vector count (in chars) 8227 jccb(Assembler::zero, test_tail); 8228 8229 lea(ary1, Address(ary1, len, Address::times_1)); 8230 negptr(len); 8231 8232 bind(test_64_loop); 8233 // Check whether our 64 elements of size byte contain negatives 8234 evpcmpgtb(k2, vec2, Address(ary1, len, Address::times_1), Assembler::AVX_512bit); 8235 kortestql(k2, k2); 8236 jcc(Assembler::notZero, TRUE_LABEL); 8237 8238 addptr(len, 64); 8239 jccb(Assembler::notZero, test_64_loop); 8240 8241 8242 bind(test_tail); 8243 // bail out when there is nothing to be done 8244 testl(tmp1, -1); 8245 jcc(Assembler::zero, FALSE_LABEL); 8246 8247 // Save k1 8248 kmovql(k3, k1); 8249 8250 // ~(~0 << len) applied up to two times (for 32-bit scenario) 8251 #ifdef _LP64 8252 mov64(tmp3_aliased, 0xFFFFFFFFFFFFFFFF); 8253 shlxq(tmp3_aliased, tmp3_aliased, tmp1); 8254 notq(tmp3_aliased); 8255 kmovql(k1, tmp3_aliased); 8256 #else 8257 Label k_init; 8258 jmp(k_init); 8259 8260 // We could not read 64-bits from a general purpose register thus we move 8261 // data required to compose 64 1's to the instruction stream 8262 // We emit 64 byte wide series of elements from 0..63 which later on would 8263 // be used as a compare targets with tail count contained in tmp1 register. 8264 // Result would be a k1 register having tmp1 consecutive number or 1 8265 // counting from least significant bit. 8266 address tmp = pc(); 8267 emit_int64(0x0706050403020100); 8268 emit_int64(0x0F0E0D0C0B0A0908); 8269 emit_int64(0x1716151413121110); 8270 emit_int64(0x1F1E1D1C1B1A1918); 8271 emit_int64(0x2726252423222120); 8272 emit_int64(0x2F2E2D2C2B2A2928); 8273 emit_int64(0x3736353433323130); 8274 emit_int64(0x3F3E3D3C3B3A3938); 8275 8276 bind(k_init); 8277 lea(len, InternalAddress(tmp)); 8278 // create mask to test for negative byte inside a vector 8279 evpbroadcastb(vec1, tmp1, Assembler::AVX_512bit); 8280 evpcmpgtb(k1, vec1, Address(len, 0), Assembler::AVX_512bit); 8281 8282 #endif 8283 evpcmpgtb(k2, k1, vec2, Address(ary1, 0), Assembler::AVX_512bit); 8284 ktestq(k2, k1); 8285 // Restore k1 8286 kmovql(k1, k3); 8287 jcc(Assembler::notZero, TRUE_LABEL); 8288 8289 jmp(FALSE_LABEL); 8290 8291 clear_vector_masking(); // closing of the stub context for programming mask registers 8292 } else { 8293 movl(result, len); // copy 8294 8295 if (UseAVX == 2 && UseSSE >= 2) { 8296 // With AVX2, use 32-byte vector compare 8297 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL; 8298 8299 // Compare 32-byte vectors 8300 andl(result, 0x0000001f); // tail count (in bytes) 8301 andl(len, 0xffffffe0); // vector count (in bytes) 8302 jccb(Assembler::zero, COMPARE_TAIL); 8303 8304 lea(ary1, Address(ary1, len, Address::times_1)); 8305 negptr(len); 8306 8307 movl(tmp1, 0x80808080); // create mask to test for Unicode chars in vector 8308 movdl(vec2, tmp1); 8309 vpbroadcastd(vec2, vec2); 8310 8311 bind(COMPARE_WIDE_VECTORS); 8312 vmovdqu(vec1, Address(ary1, len, Address::times_1)); 8313 vptest(vec1, vec2); 8314 jccb(Assembler::notZero, TRUE_LABEL); 8315 addptr(len, 32); 8316 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS); 8317 8318 testl(result, result); 8319 jccb(Assembler::zero, FALSE_LABEL); 8320 8321 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32)); 8322 vptest(vec1, vec2); 8323 jccb(Assembler::notZero, TRUE_LABEL); 8324 jmpb(FALSE_LABEL); 8325 8326 bind(COMPARE_TAIL); // len is zero 8327 movl(len, result); 8328 // Fallthru to tail compare 8329 } else if (UseSSE42Intrinsics) { 8330 // With SSE4.2, use double quad vector compare 8331 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL; 8332 8333 // Compare 16-byte vectors 8334 andl(result, 0x0000000f); // tail count (in bytes) 8335 andl(len, 0xfffffff0); // vector count (in bytes) 8336 jccb(Assembler::zero, COMPARE_TAIL); 8337 8338 lea(ary1, Address(ary1, len, Address::times_1)); 8339 negptr(len); 8340 8341 movl(tmp1, 0x80808080); 8342 movdl(vec2, tmp1); 8343 pshufd(vec2, vec2, 0); 8344 8345 bind(COMPARE_WIDE_VECTORS); 8346 movdqu(vec1, Address(ary1, len, Address::times_1)); 8347 ptest(vec1, vec2); 8348 jccb(Assembler::notZero, TRUE_LABEL); 8349 addptr(len, 16); 8350 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS); 8351 8352 testl(result, result); 8353 jccb(Assembler::zero, FALSE_LABEL); 8354 8355 movdqu(vec1, Address(ary1, result, Address::times_1, -16)); 8356 ptest(vec1, vec2); 8357 jccb(Assembler::notZero, TRUE_LABEL); 8358 jmpb(FALSE_LABEL); 8359 8360 bind(COMPARE_TAIL); // len is zero 8361 movl(len, result); 8362 // Fallthru to tail compare 8363 } 8364 } 8365 // Compare 4-byte vectors 8366 andl(len, 0xfffffffc); // vector count (in bytes) 8367 jccb(Assembler::zero, COMPARE_CHAR); 8368 8369 lea(ary1, Address(ary1, len, Address::times_1)); 8370 negptr(len); 8371 8372 bind(COMPARE_VECTORS); 8373 movl(tmp1, Address(ary1, len, Address::times_1)); 8374 andl(tmp1, 0x80808080); 8375 jccb(Assembler::notZero, TRUE_LABEL); 8376 addptr(len, 4); 8377 jcc(Assembler::notZero, COMPARE_VECTORS); 8378 8379 // Compare trailing char (final 2 bytes), if any 8380 bind(COMPARE_CHAR); 8381 testl(result, 0x2); // tail char 8382 jccb(Assembler::zero, COMPARE_BYTE); 8383 load_unsigned_short(tmp1, Address(ary1, 0)); 8384 andl(tmp1, 0x00008080); 8385 jccb(Assembler::notZero, TRUE_LABEL); 8386 subptr(result, 2); 8387 lea(ary1, Address(ary1, 2)); 8388 8389 bind(COMPARE_BYTE); 8390 testl(result, 0x1); // tail byte 8391 jccb(Assembler::zero, FALSE_LABEL); 8392 load_unsigned_byte(tmp1, Address(ary1, 0)); 8393 andl(tmp1, 0x00000080); 8394 jccb(Assembler::notEqual, TRUE_LABEL); 8395 jmpb(FALSE_LABEL); 8396 8397 bind(TRUE_LABEL); 8398 movl(result, 1); // return true 8399 jmpb(DONE); 8400 8401 bind(FALSE_LABEL); 8402 xorl(result, result); // return false 8403 8404 // That's it 8405 bind(DONE); 8406 if (UseAVX >= 2 && UseSSE >= 2) { 8407 // clean upper bits of YMM registers 8408 vpxor(vec1, vec1); 8409 vpxor(vec2, vec2); 8410 } 8411 } 8412 // Compare char[] or byte[] arrays aligned to 4 bytes or substrings. 8413 void MacroAssembler::arrays_equals(bool is_array_equ, Register ary1, Register ary2, 8414 Register limit, Register result, Register chr, 8415 XMMRegister vec1, XMMRegister vec2, bool is_char) { 8416 ShortBranchVerifier sbv(this); 8417 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR, COMPARE_BYTE; 8418 8419 int length_offset = arrayOopDesc::length_offset_in_bytes(); 8420 int base_offset = arrayOopDesc::base_offset_in_bytes(is_char ? T_CHAR : T_BYTE); 8421 8422 if (is_array_equ) { 8423 // Check the input args 8424 cmpoop(ary1, ary2); 8425 jcc(Assembler::equal, TRUE_LABEL); 8426 8427 // Need additional checks for arrays_equals. 8428 testptr(ary1, ary1); 8429 jcc(Assembler::zero, FALSE_LABEL); 8430 testptr(ary2, ary2); 8431 jcc(Assembler::zero, FALSE_LABEL); 8432 8433 // Check the lengths 8434 movl(limit, Address(ary1, length_offset)); 8435 cmpl(limit, Address(ary2, length_offset)); 8436 jcc(Assembler::notEqual, FALSE_LABEL); 8437 } 8438 8439 // count == 0 8440 testl(limit, limit); 8441 jcc(Assembler::zero, TRUE_LABEL); 8442 8443 if (is_array_equ) { 8444 // Load array address 8445 lea(ary1, Address(ary1, base_offset)); 8446 lea(ary2, Address(ary2, base_offset)); 8447 } 8448 8449 if (is_array_equ && is_char) { 8450 // arrays_equals when used for char[]. 8451 shll(limit, 1); // byte count != 0 8452 } 8453 movl(result, limit); // copy 8454 8455 if (UseAVX >= 2) { 8456 // With AVX2, use 32-byte vector compare 8457 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL; 8458 8459 // Compare 32-byte vectors 8460 andl(result, 0x0000001f); // tail count (in bytes) 8461 andl(limit, 0xffffffe0); // vector count (in bytes) 8462 jcc(Assembler::zero, COMPARE_TAIL); 8463 8464 lea(ary1, Address(ary1, limit, Address::times_1)); 8465 lea(ary2, Address(ary2, limit, Address::times_1)); 8466 negptr(limit); 8467 8468 bind(COMPARE_WIDE_VECTORS); 8469 8470 #ifdef _LP64 8471 if (VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop 8472 Label COMPARE_WIDE_VECTORS_LOOP_AVX2, COMPARE_WIDE_VECTORS_LOOP_AVX3; 8473 8474 cmpl(limit, -64); 8475 jccb(Assembler::greater, COMPARE_WIDE_VECTORS_LOOP_AVX2); 8476 8477 bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop 8478 8479 evmovdquq(vec1, Address(ary1, limit, Address::times_1), Assembler::AVX_512bit); 8480 evpcmpeqb(k7, vec1, Address(ary2, limit, Address::times_1), Assembler::AVX_512bit); 8481 kortestql(k7, k7); 8482 jcc(Assembler::aboveEqual, FALSE_LABEL); // miscompare 8483 addptr(limit, 64); // update since we already compared at this addr 8484 cmpl(limit, -64); 8485 jccb(Assembler::lessEqual, COMPARE_WIDE_VECTORS_LOOP_AVX3); 8486 8487 // At this point we may still need to compare -limit+result bytes. 8488 // We could execute the next two instruction and just continue via non-wide path: 8489 // cmpl(limit, 0); 8490 // jcc(Assembler::equal, COMPARE_TAIL); // true 8491 // But since we stopped at the points ary{1,2}+limit which are 8492 // not farther than 64 bytes from the ends of arrays ary{1,2}+result 8493 // (|limit| <= 32 and result < 32), 8494 // we may just compare the last 64 bytes. 8495 // 8496 addptr(result, -64); // it is safe, bc we just came from this area 8497 evmovdquq(vec1, Address(ary1, result, Address::times_1), Assembler::AVX_512bit); 8498 evpcmpeqb(k7, vec1, Address(ary2, result, Address::times_1), Assembler::AVX_512bit); 8499 kortestql(k7, k7); 8500 jcc(Assembler::aboveEqual, FALSE_LABEL); // miscompare 8501 8502 jmp(TRUE_LABEL); 8503 8504 bind(COMPARE_WIDE_VECTORS_LOOP_AVX2); 8505 8506 }//if (VM_Version::supports_avx512vlbw()) 8507 #endif //_LP64 8508 8509 vmovdqu(vec1, Address(ary1, limit, Address::times_1)); 8510 vmovdqu(vec2, Address(ary2, limit, Address::times_1)); 8511 vpxor(vec1, vec2); 8512 8513 vptest(vec1, vec1); 8514 jcc(Assembler::notZero, FALSE_LABEL); 8515 addptr(limit, 32); 8516 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS); 8517 8518 testl(result, result); 8519 jcc(Assembler::zero, TRUE_LABEL); 8520 8521 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32)); 8522 vmovdqu(vec2, Address(ary2, result, Address::times_1, -32)); 8523 vpxor(vec1, vec2); 8524 8525 vptest(vec1, vec1); 8526 jccb(Assembler::notZero, FALSE_LABEL); 8527 jmpb(TRUE_LABEL); 8528 8529 bind(COMPARE_TAIL); // limit is zero 8530 movl(limit, result); 8531 // Fallthru to tail compare 8532 } else if (UseSSE42Intrinsics) { 8533 // With SSE4.2, use double quad vector compare 8534 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL; 8535 8536 // Compare 16-byte vectors 8537 andl(result, 0x0000000f); // tail count (in bytes) 8538 andl(limit, 0xfffffff0); // vector count (in bytes) 8539 jcc(Assembler::zero, COMPARE_TAIL); 8540 8541 lea(ary1, Address(ary1, limit, Address::times_1)); 8542 lea(ary2, Address(ary2, limit, Address::times_1)); 8543 negptr(limit); 8544 8545 bind(COMPARE_WIDE_VECTORS); 8546 movdqu(vec1, Address(ary1, limit, Address::times_1)); 8547 movdqu(vec2, Address(ary2, limit, Address::times_1)); 8548 pxor(vec1, vec2); 8549 8550 ptest(vec1, vec1); 8551 jcc(Assembler::notZero, FALSE_LABEL); 8552 addptr(limit, 16); 8553 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS); 8554 8555 testl(result, result); 8556 jcc(Assembler::zero, TRUE_LABEL); 8557 8558 movdqu(vec1, Address(ary1, result, Address::times_1, -16)); 8559 movdqu(vec2, Address(ary2, result, Address::times_1, -16)); 8560 pxor(vec1, vec2); 8561 8562 ptest(vec1, vec1); 8563 jccb(Assembler::notZero, FALSE_LABEL); 8564 jmpb(TRUE_LABEL); 8565 8566 bind(COMPARE_TAIL); // limit is zero 8567 movl(limit, result); 8568 // Fallthru to tail compare 8569 } 8570 8571 // Compare 4-byte vectors 8572 andl(limit, 0xfffffffc); // vector count (in bytes) 8573 jccb(Assembler::zero, COMPARE_CHAR); 8574 8575 lea(ary1, Address(ary1, limit, Address::times_1)); 8576 lea(ary2, Address(ary2, limit, Address::times_1)); 8577 negptr(limit); 8578 8579 bind(COMPARE_VECTORS); 8580 movl(chr, Address(ary1, limit, Address::times_1)); 8581 cmpl(chr, Address(ary2, limit, Address::times_1)); 8582 jccb(Assembler::notEqual, FALSE_LABEL); 8583 addptr(limit, 4); 8584 jcc(Assembler::notZero, COMPARE_VECTORS); 8585 8586 // Compare trailing char (final 2 bytes), if any 8587 bind(COMPARE_CHAR); 8588 testl(result, 0x2); // tail char 8589 jccb(Assembler::zero, COMPARE_BYTE); 8590 load_unsigned_short(chr, Address(ary1, 0)); 8591 load_unsigned_short(limit, Address(ary2, 0)); 8592 cmpl(chr, limit); 8593 jccb(Assembler::notEqual, FALSE_LABEL); 8594 8595 if (is_array_equ && is_char) { 8596 bind(COMPARE_BYTE); 8597 } else { 8598 lea(ary1, Address(ary1, 2)); 8599 lea(ary2, Address(ary2, 2)); 8600 8601 bind(COMPARE_BYTE); 8602 testl(result, 0x1); // tail byte 8603 jccb(Assembler::zero, TRUE_LABEL); 8604 load_unsigned_byte(chr, Address(ary1, 0)); 8605 load_unsigned_byte(limit, Address(ary2, 0)); 8606 cmpl(chr, limit); 8607 jccb(Assembler::notEqual, FALSE_LABEL); 8608 } 8609 bind(TRUE_LABEL); 8610 movl(result, 1); // return true 8611 jmpb(DONE); 8612 8613 bind(FALSE_LABEL); 8614 xorl(result, result); // return false 8615 8616 // That's it 8617 bind(DONE); 8618 if (UseAVX >= 2) { 8619 // clean upper bits of YMM registers 8620 vpxor(vec1, vec1); 8621 vpxor(vec2, vec2); 8622 } 8623 } 8624 8625 #endif 8626 8627 void MacroAssembler::generate_fill(BasicType t, bool aligned, 8628 Register to, Register value, Register count, 8629 Register rtmp, XMMRegister xtmp) { 8630 ShortBranchVerifier sbv(this); 8631 assert_different_registers(to, value, count, rtmp); 8632 Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte; 8633 Label L_fill_2_bytes, L_fill_4_bytes; 8634 8635 int shift = -1; 8636 switch (t) { 8637 case T_BYTE: 8638 shift = 2; 8639 break; 8640 case T_SHORT: 8641 shift = 1; 8642 break; 8643 case T_INT: 8644 shift = 0; 8645 break; 8646 default: ShouldNotReachHere(); 8647 } 8648 8649 if (t == T_BYTE) { 8650 andl(value, 0xff); 8651 movl(rtmp, value); 8652 shll(rtmp, 8); 8653 orl(value, rtmp); 8654 } 8655 if (t == T_SHORT) { 8656 andl(value, 0xffff); 8657 } 8658 if (t == T_BYTE || t == T_SHORT) { 8659 movl(rtmp, value); 8660 shll(rtmp, 16); 8661 orl(value, rtmp); 8662 } 8663 8664 cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element 8665 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp 8666 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) { 8667 // align source address at 4 bytes address boundary 8668 if (t == T_BYTE) { 8669 // One byte misalignment happens only for byte arrays 8670 testptr(to, 1); 8671 jccb(Assembler::zero, L_skip_align1); 8672 movb(Address(to, 0), value); 8673 increment(to); 8674 decrement(count); 8675 BIND(L_skip_align1); 8676 } 8677 // Two bytes misalignment happens only for byte and short (char) arrays 8678 testptr(to, 2); 8679 jccb(Assembler::zero, L_skip_align2); 8680 movw(Address(to, 0), value); 8681 addptr(to, 2); 8682 subl(count, 1<<(shift-1)); 8683 BIND(L_skip_align2); 8684 } 8685 if (UseSSE < 2) { 8686 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes; 8687 // Fill 32-byte chunks 8688 subl(count, 8 << shift); 8689 jcc(Assembler::less, L_check_fill_8_bytes); 8690 align(16); 8691 8692 BIND(L_fill_32_bytes_loop); 8693 8694 for (int i = 0; i < 32; i += 4) { 8695 movl(Address(to, i), value); 8696 } 8697 8698 addptr(to, 32); 8699 subl(count, 8 << shift); 8700 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop); 8701 BIND(L_check_fill_8_bytes); 8702 addl(count, 8 << shift); 8703 jccb(Assembler::zero, L_exit); 8704 jmpb(L_fill_8_bytes); 8705 8706 // 8707 // length is too short, just fill qwords 8708 // 8709 BIND(L_fill_8_bytes_loop); 8710 movl(Address(to, 0), value); 8711 movl(Address(to, 4), value); 8712 addptr(to, 8); 8713 BIND(L_fill_8_bytes); 8714 subl(count, 1 << (shift + 1)); 8715 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop); 8716 // fall through to fill 4 bytes 8717 } else { 8718 Label L_fill_32_bytes; 8719 if (!UseUnalignedLoadStores) { 8720 // align to 8 bytes, we know we are 4 byte aligned to start 8721 testptr(to, 4); 8722 jccb(Assembler::zero, L_fill_32_bytes); 8723 movl(Address(to, 0), value); 8724 addptr(to, 4); 8725 subl(count, 1<<shift); 8726 } 8727 BIND(L_fill_32_bytes); 8728 { 8729 assert( UseSSE >= 2, "supported cpu only" ); 8730 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes; 8731 if (UseAVX > 2) { 8732 movl(rtmp, 0xffff); 8733 kmovwl(k1, rtmp); 8734 } 8735 movdl(xtmp, value); 8736 if (UseAVX > 2 && UseUnalignedLoadStores) { 8737 // Fill 64-byte chunks 8738 Label L_fill_64_bytes_loop, L_check_fill_32_bytes; 8739 evpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit); 8740 8741 subl(count, 16 << shift); 8742 jcc(Assembler::less, L_check_fill_32_bytes); 8743 align(16); 8744 8745 BIND(L_fill_64_bytes_loop); 8746 evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit); 8747 addptr(to, 64); 8748 subl(count, 16 << shift); 8749 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop); 8750 8751 BIND(L_check_fill_32_bytes); 8752 addl(count, 8 << shift); 8753 jccb(Assembler::less, L_check_fill_8_bytes); 8754 vmovdqu(Address(to, 0), xtmp); 8755 addptr(to, 32); 8756 subl(count, 8 << shift); 8757 8758 BIND(L_check_fill_8_bytes); 8759 } else if (UseAVX == 2 && UseUnalignedLoadStores) { 8760 // Fill 64-byte chunks 8761 Label L_fill_64_bytes_loop, L_check_fill_32_bytes; 8762 vpbroadcastd(xtmp, xtmp); 8763 8764 subl(count, 16 << shift); 8765 jcc(Assembler::less, L_check_fill_32_bytes); 8766 align(16); 8767 8768 BIND(L_fill_64_bytes_loop); 8769 vmovdqu(Address(to, 0), xtmp); 8770 vmovdqu(Address(to, 32), xtmp); 8771 addptr(to, 64); 8772 subl(count, 16 << shift); 8773 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop); 8774 8775 BIND(L_check_fill_32_bytes); 8776 addl(count, 8 << shift); 8777 jccb(Assembler::less, L_check_fill_8_bytes); 8778 vmovdqu(Address(to, 0), xtmp); 8779 addptr(to, 32); 8780 subl(count, 8 << shift); 8781 8782 BIND(L_check_fill_8_bytes); 8783 // clean upper bits of YMM registers 8784 movdl(xtmp, value); 8785 pshufd(xtmp, xtmp, 0); 8786 } else { 8787 // Fill 32-byte chunks 8788 pshufd(xtmp, xtmp, 0); 8789 8790 subl(count, 8 << shift); 8791 jcc(Assembler::less, L_check_fill_8_bytes); 8792 align(16); 8793 8794 BIND(L_fill_32_bytes_loop); 8795 8796 if (UseUnalignedLoadStores) { 8797 movdqu(Address(to, 0), xtmp); 8798 movdqu(Address(to, 16), xtmp); 8799 } else { 8800 movq(Address(to, 0), xtmp); 8801 movq(Address(to, 8), xtmp); 8802 movq(Address(to, 16), xtmp); 8803 movq(Address(to, 24), xtmp); 8804 } 8805 8806 addptr(to, 32); 8807 subl(count, 8 << shift); 8808 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop); 8809 8810 BIND(L_check_fill_8_bytes); 8811 } 8812 addl(count, 8 << shift); 8813 jccb(Assembler::zero, L_exit); 8814 jmpb(L_fill_8_bytes); 8815 8816 // 8817 // length is too short, just fill qwords 8818 // 8819 BIND(L_fill_8_bytes_loop); 8820 movq(Address(to, 0), xtmp); 8821 addptr(to, 8); 8822 BIND(L_fill_8_bytes); 8823 subl(count, 1 << (shift + 1)); 8824 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop); 8825 } 8826 } 8827 // fill trailing 4 bytes 8828 BIND(L_fill_4_bytes); 8829 testl(count, 1<<shift); 8830 jccb(Assembler::zero, L_fill_2_bytes); 8831 movl(Address(to, 0), value); 8832 if (t == T_BYTE || t == T_SHORT) { 8833 addptr(to, 4); 8834 BIND(L_fill_2_bytes); 8835 // fill trailing 2 bytes 8836 testl(count, 1<<(shift-1)); 8837 jccb(Assembler::zero, L_fill_byte); 8838 movw(Address(to, 0), value); 8839 if (t == T_BYTE) { 8840 addptr(to, 2); 8841 BIND(L_fill_byte); 8842 // fill trailing byte 8843 testl(count, 1); 8844 jccb(Assembler::zero, L_exit); 8845 movb(Address(to, 0), value); 8846 } else { 8847 BIND(L_fill_byte); 8848 } 8849 } else { 8850 BIND(L_fill_2_bytes); 8851 } 8852 BIND(L_exit); 8853 } 8854 8855 // encode char[] to byte[] in ISO_8859_1 8856 //@HotSpotIntrinsicCandidate 8857 //private static int implEncodeISOArray(byte[] sa, int sp, 8858 //byte[] da, int dp, int len) { 8859 // int i = 0; 8860 // for (; i < len; i++) { 8861 // char c = StringUTF16.getChar(sa, sp++); 8862 // if (c > '\u00FF') 8863 // break; 8864 // da[dp++] = (byte)c; 8865 // } 8866 // return i; 8867 //} 8868 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len, 8869 XMMRegister tmp1Reg, XMMRegister tmp2Reg, 8870 XMMRegister tmp3Reg, XMMRegister tmp4Reg, 8871 Register tmp5, Register result) { 8872 8873 // rsi: src 8874 // rdi: dst 8875 // rdx: len 8876 // rcx: tmp5 8877 // rax: result 8878 ShortBranchVerifier sbv(this); 8879 assert_different_registers(src, dst, len, tmp5, result); 8880 Label L_done, L_copy_1_char, L_copy_1_char_exit; 8881 8882 // set result 8883 xorl(result, result); 8884 // check for zero length 8885 testl(len, len); 8886 jcc(Assembler::zero, L_done); 8887 8888 movl(result, len); 8889 8890 // Setup pointers 8891 lea(src, Address(src, len, Address::times_2)); // char[] 8892 lea(dst, Address(dst, len, Address::times_1)); // byte[] 8893 negptr(len); 8894 8895 if (UseSSE42Intrinsics || UseAVX >= 2) { 8896 Label L_chars_8_check, L_copy_8_chars, L_copy_8_chars_exit; 8897 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit; 8898 8899 if (UseAVX >= 2) { 8900 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit; 8901 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector 8902 movdl(tmp1Reg, tmp5); 8903 vpbroadcastd(tmp1Reg, tmp1Reg); 8904 jmp(L_chars_32_check); 8905 8906 bind(L_copy_32_chars); 8907 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64)); 8908 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32)); 8909 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1); 8910 vptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector 8911 jccb(Assembler::notZero, L_copy_32_chars_exit); 8912 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1); 8913 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1); 8914 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg); 8915 8916 bind(L_chars_32_check); 8917 addptr(len, 32); 8918 jcc(Assembler::lessEqual, L_copy_32_chars); 8919 8920 bind(L_copy_32_chars_exit); 8921 subptr(len, 16); 8922 jccb(Assembler::greater, L_copy_16_chars_exit); 8923 8924 } else if (UseSSE42Intrinsics) { 8925 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector 8926 movdl(tmp1Reg, tmp5); 8927 pshufd(tmp1Reg, tmp1Reg, 0); 8928 jmpb(L_chars_16_check); 8929 } 8930 8931 bind(L_copy_16_chars); 8932 if (UseAVX >= 2) { 8933 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32)); 8934 vptest(tmp2Reg, tmp1Reg); 8935 jcc(Assembler::notZero, L_copy_16_chars_exit); 8936 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1); 8937 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1); 8938 } else { 8939 if (UseAVX > 0) { 8940 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32)); 8941 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16)); 8942 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0); 8943 } else { 8944 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32)); 8945 por(tmp2Reg, tmp3Reg); 8946 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16)); 8947 por(tmp2Reg, tmp4Reg); 8948 } 8949 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector 8950 jccb(Assembler::notZero, L_copy_16_chars_exit); 8951 packuswb(tmp3Reg, tmp4Reg); 8952 } 8953 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg); 8954 8955 bind(L_chars_16_check); 8956 addptr(len, 16); 8957 jcc(Assembler::lessEqual, L_copy_16_chars); 8958 8959 bind(L_copy_16_chars_exit); 8960 if (UseAVX >= 2) { 8961 // clean upper bits of YMM registers 8962 vpxor(tmp2Reg, tmp2Reg); 8963 vpxor(tmp3Reg, tmp3Reg); 8964 vpxor(tmp4Reg, tmp4Reg); 8965 movdl(tmp1Reg, tmp5); 8966 pshufd(tmp1Reg, tmp1Reg, 0); 8967 } 8968 subptr(len, 8); 8969 jccb(Assembler::greater, L_copy_8_chars_exit); 8970 8971 bind(L_copy_8_chars); 8972 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16)); 8973 ptest(tmp3Reg, tmp1Reg); 8974 jccb(Assembler::notZero, L_copy_8_chars_exit); 8975 packuswb(tmp3Reg, tmp1Reg); 8976 movq(Address(dst, len, Address::times_1, -8), tmp3Reg); 8977 addptr(len, 8); 8978 jccb(Assembler::lessEqual, L_copy_8_chars); 8979 8980 bind(L_copy_8_chars_exit); 8981 subptr(len, 8); 8982 jccb(Assembler::zero, L_done); 8983 } 8984 8985 bind(L_copy_1_char); 8986 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0)); 8987 testl(tmp5, 0xff00); // check if Unicode char 8988 jccb(Assembler::notZero, L_copy_1_char_exit); 8989 movb(Address(dst, len, Address::times_1, 0), tmp5); 8990 addptr(len, 1); 8991 jccb(Assembler::less, L_copy_1_char); 8992 8993 bind(L_copy_1_char_exit); 8994 addptr(result, len); // len is negative count of not processed elements 8995 8996 bind(L_done); 8997 } 8998 8999 #ifdef _LP64 9000 /** 9001 * Helper for multiply_to_len(). 9002 */ 9003 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) { 9004 addq(dest_lo, src1); 9005 adcq(dest_hi, 0); 9006 addq(dest_lo, src2); 9007 adcq(dest_hi, 0); 9008 } 9009 9010 /** 9011 * Multiply 64 bit by 64 bit first loop. 9012 */ 9013 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart, 9014 Register y, Register y_idx, Register z, 9015 Register carry, Register product, 9016 Register idx, Register kdx) { 9017 // 9018 // jlong carry, x[], y[], z[]; 9019 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) { 9020 // huge_128 product = y[idx] * x[xstart] + carry; 9021 // z[kdx] = (jlong)product; 9022 // carry = (jlong)(product >>> 64); 9023 // } 9024 // z[xstart] = carry; 9025 // 9026 9027 Label L_first_loop, L_first_loop_exit; 9028 Label L_one_x, L_one_y, L_multiply; 9029 9030 decrementl(xstart); 9031 jcc(Assembler::negative, L_one_x); 9032 9033 movq(x_xstart, Address(x, xstart, Address::times_4, 0)); 9034 rorq(x_xstart, 32); // convert big-endian to little-endian 9035 9036 bind(L_first_loop); 9037 decrementl(idx); 9038 jcc(Assembler::negative, L_first_loop_exit); 9039 decrementl(idx); 9040 jcc(Assembler::negative, L_one_y); 9041 movq(y_idx, Address(y, idx, Address::times_4, 0)); 9042 rorq(y_idx, 32); // convert big-endian to little-endian 9043 bind(L_multiply); 9044 movq(product, x_xstart); 9045 mulq(y_idx); // product(rax) * y_idx -> rdx:rax 9046 addq(product, carry); 9047 adcq(rdx, 0); 9048 subl(kdx, 2); 9049 movl(Address(z, kdx, Address::times_4, 4), product); 9050 shrq(product, 32); 9051 movl(Address(z, kdx, Address::times_4, 0), product); 9052 movq(carry, rdx); 9053 jmp(L_first_loop); 9054 9055 bind(L_one_y); 9056 movl(y_idx, Address(y, 0)); 9057 jmp(L_multiply); 9058 9059 bind(L_one_x); 9060 movl(x_xstart, Address(x, 0)); 9061 jmp(L_first_loop); 9062 9063 bind(L_first_loop_exit); 9064 } 9065 9066 /** 9067 * Multiply 64 bit by 64 bit and add 128 bit. 9068 */ 9069 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z, 9070 Register yz_idx, Register idx, 9071 Register carry, Register product, int offset) { 9072 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry; 9073 // z[kdx] = (jlong)product; 9074 9075 movq(yz_idx, Address(y, idx, Address::times_4, offset)); 9076 rorq(yz_idx, 32); // convert big-endian to little-endian 9077 movq(product, x_xstart); 9078 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax) 9079 movq(yz_idx, Address(z, idx, Address::times_4, offset)); 9080 rorq(yz_idx, 32); // convert big-endian to little-endian 9081 9082 add2_with_carry(rdx, product, carry, yz_idx); 9083 9084 movl(Address(z, idx, Address::times_4, offset+4), product); 9085 shrq(product, 32); 9086 movl(Address(z, idx, Address::times_4, offset), product); 9087 9088 } 9089 9090 /** 9091 * Multiply 128 bit by 128 bit. Unrolled inner loop. 9092 */ 9093 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z, 9094 Register yz_idx, Register idx, Register jdx, 9095 Register carry, Register product, 9096 Register carry2) { 9097 // jlong carry, x[], y[], z[]; 9098 // int kdx = ystart+1; 9099 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop 9100 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry; 9101 // z[kdx+idx+1] = (jlong)product; 9102 // jlong carry2 = (jlong)(product >>> 64); 9103 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2; 9104 // z[kdx+idx] = (jlong)product; 9105 // carry = (jlong)(product >>> 64); 9106 // } 9107 // idx += 2; 9108 // if (idx > 0) { 9109 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry; 9110 // z[kdx+idx] = (jlong)product; 9111 // carry = (jlong)(product >>> 64); 9112 // } 9113 // 9114 9115 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done; 9116 9117 movl(jdx, idx); 9118 andl(jdx, 0xFFFFFFFC); 9119 shrl(jdx, 2); 9120 9121 bind(L_third_loop); 9122 subl(jdx, 1); 9123 jcc(Assembler::negative, L_third_loop_exit); 9124 subl(idx, 4); 9125 9126 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8); 9127 movq(carry2, rdx); 9128 9129 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0); 9130 movq(carry, rdx); 9131 jmp(L_third_loop); 9132 9133 bind (L_third_loop_exit); 9134 9135 andl (idx, 0x3); 9136 jcc(Assembler::zero, L_post_third_loop_done); 9137 9138 Label L_check_1; 9139 subl(idx, 2); 9140 jcc(Assembler::negative, L_check_1); 9141 9142 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0); 9143 movq(carry, rdx); 9144 9145 bind (L_check_1); 9146 addl (idx, 0x2); 9147 andl (idx, 0x1); 9148 subl(idx, 1); 9149 jcc(Assembler::negative, L_post_third_loop_done); 9150 9151 movl(yz_idx, Address(y, idx, Address::times_4, 0)); 9152 movq(product, x_xstart); 9153 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax) 9154 movl(yz_idx, Address(z, idx, Address::times_4, 0)); 9155 9156 add2_with_carry(rdx, product, yz_idx, carry); 9157 9158 movl(Address(z, idx, Address::times_4, 0), product); 9159 shrq(product, 32); 9160 9161 shlq(rdx, 32); 9162 orq(product, rdx); 9163 movq(carry, product); 9164 9165 bind(L_post_third_loop_done); 9166 } 9167 9168 /** 9169 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop. 9170 * 9171 */ 9172 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z, 9173 Register carry, Register carry2, 9174 Register idx, Register jdx, 9175 Register yz_idx1, Register yz_idx2, 9176 Register tmp, Register tmp3, Register tmp4) { 9177 assert(UseBMI2Instructions, "should be used only when BMI2 is available"); 9178 9179 // jlong carry, x[], y[], z[]; 9180 // int kdx = ystart+1; 9181 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop 9182 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry; 9183 // jlong carry2 = (jlong)(tmp3 >>> 64); 9184 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2; 9185 // carry = (jlong)(tmp4 >>> 64); 9186 // z[kdx+idx+1] = (jlong)tmp3; 9187 // z[kdx+idx] = (jlong)tmp4; 9188 // } 9189 // idx += 2; 9190 // if (idx > 0) { 9191 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry; 9192 // z[kdx+idx] = (jlong)yz_idx1; 9193 // carry = (jlong)(yz_idx1 >>> 64); 9194 // } 9195 // 9196 9197 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done; 9198 9199 movl(jdx, idx); 9200 andl(jdx, 0xFFFFFFFC); 9201 shrl(jdx, 2); 9202 9203 bind(L_third_loop); 9204 subl(jdx, 1); 9205 jcc(Assembler::negative, L_third_loop_exit); 9206 subl(idx, 4); 9207 9208 movq(yz_idx1, Address(y, idx, Address::times_4, 8)); 9209 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian 9210 movq(yz_idx2, Address(y, idx, Address::times_4, 0)); 9211 rorxq(yz_idx2, yz_idx2, 32); 9212 9213 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3 9214 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp 9215 9216 movq(yz_idx1, Address(z, idx, Address::times_4, 8)); 9217 rorxq(yz_idx1, yz_idx1, 32); 9218 movq(yz_idx2, Address(z, idx, Address::times_4, 0)); 9219 rorxq(yz_idx2, yz_idx2, 32); 9220 9221 if (VM_Version::supports_adx()) { 9222 adcxq(tmp3, carry); 9223 adoxq(tmp3, yz_idx1); 9224 9225 adcxq(tmp4, tmp); 9226 adoxq(tmp4, yz_idx2); 9227 9228 movl(carry, 0); // does not affect flags 9229 adcxq(carry2, carry); 9230 adoxq(carry2, carry); 9231 } else { 9232 add2_with_carry(tmp4, tmp3, carry, yz_idx1); 9233 add2_with_carry(carry2, tmp4, tmp, yz_idx2); 9234 } 9235 movq(carry, carry2); 9236 9237 movl(Address(z, idx, Address::times_4, 12), tmp3); 9238 shrq(tmp3, 32); 9239 movl(Address(z, idx, Address::times_4, 8), tmp3); 9240 9241 movl(Address(z, idx, Address::times_4, 4), tmp4); 9242 shrq(tmp4, 32); 9243 movl(Address(z, idx, Address::times_4, 0), tmp4); 9244 9245 jmp(L_third_loop); 9246 9247 bind (L_third_loop_exit); 9248 9249 andl (idx, 0x3); 9250 jcc(Assembler::zero, L_post_third_loop_done); 9251 9252 Label L_check_1; 9253 subl(idx, 2); 9254 jcc(Assembler::negative, L_check_1); 9255 9256 movq(yz_idx1, Address(y, idx, Address::times_4, 0)); 9257 rorxq(yz_idx1, yz_idx1, 32); 9258 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3 9259 movq(yz_idx2, Address(z, idx, Address::times_4, 0)); 9260 rorxq(yz_idx2, yz_idx2, 32); 9261 9262 add2_with_carry(tmp4, tmp3, carry, yz_idx2); 9263 9264 movl(Address(z, idx, Address::times_4, 4), tmp3); 9265 shrq(tmp3, 32); 9266 movl(Address(z, idx, Address::times_4, 0), tmp3); 9267 movq(carry, tmp4); 9268 9269 bind (L_check_1); 9270 addl (idx, 0x2); 9271 andl (idx, 0x1); 9272 subl(idx, 1); 9273 jcc(Assembler::negative, L_post_third_loop_done); 9274 movl(tmp4, Address(y, idx, Address::times_4, 0)); 9275 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3 9276 movl(tmp4, Address(z, idx, Address::times_4, 0)); 9277 9278 add2_with_carry(carry2, tmp3, tmp4, carry); 9279 9280 movl(Address(z, idx, Address::times_4, 0), tmp3); 9281 shrq(tmp3, 32); 9282 9283 shlq(carry2, 32); 9284 orq(tmp3, carry2); 9285 movq(carry, tmp3); 9286 9287 bind(L_post_third_loop_done); 9288 } 9289 9290 /** 9291 * Code for BigInteger::multiplyToLen() instrinsic. 9292 * 9293 * rdi: x 9294 * rax: xlen 9295 * rsi: y 9296 * rcx: ylen 9297 * r8: z 9298 * r11: zlen 9299 * r12: tmp1 9300 * r13: tmp2 9301 * r14: tmp3 9302 * r15: tmp4 9303 * rbx: tmp5 9304 * 9305 */ 9306 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen, 9307 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) { 9308 ShortBranchVerifier sbv(this); 9309 assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, rdx); 9310 9311 push(tmp1); 9312 push(tmp2); 9313 push(tmp3); 9314 push(tmp4); 9315 push(tmp5); 9316 9317 push(xlen); 9318 push(zlen); 9319 9320 const Register idx = tmp1; 9321 const Register kdx = tmp2; 9322 const Register xstart = tmp3; 9323 9324 const Register y_idx = tmp4; 9325 const Register carry = tmp5; 9326 const Register product = xlen; 9327 const Register x_xstart = zlen; // reuse register 9328 9329 // First Loop. 9330 // 9331 // final static long LONG_MASK = 0xffffffffL; 9332 // int xstart = xlen - 1; 9333 // int ystart = ylen - 1; 9334 // long carry = 0; 9335 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) { 9336 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry; 9337 // z[kdx] = (int)product; 9338 // carry = product >>> 32; 9339 // } 9340 // z[xstart] = (int)carry; 9341 // 9342 9343 movl(idx, ylen); // idx = ylen; 9344 movl(kdx, zlen); // kdx = xlen+ylen; 9345 xorq(carry, carry); // carry = 0; 9346 9347 Label L_done; 9348 9349 movl(xstart, xlen); 9350 decrementl(xstart); 9351 jcc(Assembler::negative, L_done); 9352 9353 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx); 9354 9355 Label L_second_loop; 9356 testl(kdx, kdx); 9357 jcc(Assembler::zero, L_second_loop); 9358 9359 Label L_carry; 9360 subl(kdx, 1); 9361 jcc(Assembler::zero, L_carry); 9362 9363 movl(Address(z, kdx, Address::times_4, 0), carry); 9364 shrq(carry, 32); 9365 subl(kdx, 1); 9366 9367 bind(L_carry); 9368 movl(Address(z, kdx, Address::times_4, 0), carry); 9369 9370 // Second and third (nested) loops. 9371 // 9372 // for (int i = xstart-1; i >= 0; i--) { // Second loop 9373 // carry = 0; 9374 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop 9375 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) + 9376 // (z[k] & LONG_MASK) + carry; 9377 // z[k] = (int)product; 9378 // carry = product >>> 32; 9379 // } 9380 // z[i] = (int)carry; 9381 // } 9382 // 9383 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx 9384 9385 const Register jdx = tmp1; 9386 9387 bind(L_second_loop); 9388 xorl(carry, carry); // carry = 0; 9389 movl(jdx, ylen); // j = ystart+1 9390 9391 subl(xstart, 1); // i = xstart-1; 9392 jcc(Assembler::negative, L_done); 9393 9394 push (z); 9395 9396 Label L_last_x; 9397 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j 9398 subl(xstart, 1); // i = xstart-1; 9399 jcc(Assembler::negative, L_last_x); 9400 9401 if (UseBMI2Instructions) { 9402 movq(rdx, Address(x, xstart, Address::times_4, 0)); 9403 rorxq(rdx, rdx, 32); // convert big-endian to little-endian 9404 } else { 9405 movq(x_xstart, Address(x, xstart, Address::times_4, 0)); 9406 rorq(x_xstart, 32); // convert big-endian to little-endian 9407 } 9408 9409 Label L_third_loop_prologue; 9410 bind(L_third_loop_prologue); 9411 9412 push (x); 9413 push (xstart); 9414 push (ylen); 9415 9416 9417 if (UseBMI2Instructions) { 9418 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4); 9419 } else { // !UseBMI2Instructions 9420 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x); 9421 } 9422 9423 pop(ylen); 9424 pop(xlen); 9425 pop(x); 9426 pop(z); 9427 9428 movl(tmp3, xlen); 9429 addl(tmp3, 1); 9430 movl(Address(z, tmp3, Address::times_4, 0), carry); 9431 subl(tmp3, 1); 9432 jccb(Assembler::negative, L_done); 9433 9434 shrq(carry, 32); 9435 movl(Address(z, tmp3, Address::times_4, 0), carry); 9436 jmp(L_second_loop); 9437 9438 // Next infrequent code is moved outside loops. 9439 bind(L_last_x); 9440 if (UseBMI2Instructions) { 9441 movl(rdx, Address(x, 0)); 9442 } else { 9443 movl(x_xstart, Address(x, 0)); 9444 } 9445 jmp(L_third_loop_prologue); 9446 9447 bind(L_done); 9448 9449 pop(zlen); 9450 pop(xlen); 9451 9452 pop(tmp5); 9453 pop(tmp4); 9454 pop(tmp3); 9455 pop(tmp2); 9456 pop(tmp1); 9457 } 9458 9459 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale, 9460 Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){ 9461 assert(UseSSE42Intrinsics, "SSE4.2 must be enabled."); 9462 Label VECTOR64_LOOP, VECTOR64_TAIL, VECTOR64_NOT_EQUAL, VECTOR32_TAIL; 9463 Label VECTOR32_LOOP, VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP; 9464 Label VECTOR16_TAIL, VECTOR8_TAIL, VECTOR4_TAIL; 9465 Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL; 9466 Label SAME_TILL_END, DONE; 9467 Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL; 9468 9469 //scale is in rcx in both Win64 and Unix 9470 ShortBranchVerifier sbv(this); 9471 9472 shlq(length); 9473 xorq(result, result); 9474 9475 if ((UseAVX > 2) && 9476 VM_Version::supports_avx512vlbw()) { 9477 set_vector_masking(); // opening of the stub context for programming mask registers 9478 cmpq(length, 64); 9479 jcc(Assembler::less, VECTOR32_TAIL); 9480 movq(tmp1, length); 9481 andq(tmp1, 0x3F); // tail count 9482 andq(length, ~(0x3F)); //vector count 9483 9484 bind(VECTOR64_LOOP); 9485 // AVX512 code to compare 64 byte vectors. 9486 evmovdqub(rymm0, Address(obja, result), Assembler::AVX_512bit); 9487 evpcmpeqb(k7, rymm0, Address(objb, result), Assembler::AVX_512bit); 9488 kortestql(k7, k7); 9489 jcc(Assembler::aboveEqual, VECTOR64_NOT_EQUAL); // mismatch 9490 addq(result, 64); 9491 subq(length, 64); 9492 jccb(Assembler::notZero, VECTOR64_LOOP); 9493 9494 //bind(VECTOR64_TAIL); 9495 testq(tmp1, tmp1); 9496 jcc(Assembler::zero, SAME_TILL_END); 9497 9498 bind(VECTOR64_TAIL); 9499 // AVX512 code to compare upto 63 byte vectors. 9500 // Save k1 9501 kmovql(k3, k1); 9502 mov64(tmp2, 0xFFFFFFFFFFFFFFFF); 9503 shlxq(tmp2, tmp2, tmp1); 9504 notq(tmp2); 9505 kmovql(k1, tmp2); 9506 9507 evmovdqub(rymm0, k1, Address(obja, result), Assembler::AVX_512bit); 9508 evpcmpeqb(k7, k1, rymm0, Address(objb, result), Assembler::AVX_512bit); 9509 9510 ktestql(k7, k1); 9511 // Restore k1 9512 kmovql(k1, k3); 9513 jcc(Assembler::below, SAME_TILL_END); // not mismatch 9514 9515 bind(VECTOR64_NOT_EQUAL); 9516 kmovql(tmp1, k7); 9517 notq(tmp1); 9518 tzcntq(tmp1, tmp1); 9519 addq(result, tmp1); 9520 shrq(result); 9521 jmp(DONE); 9522 bind(VECTOR32_TAIL); 9523 clear_vector_masking(); // closing of the stub context for programming mask registers 9524 } 9525 9526 cmpq(length, 8); 9527 jcc(Assembler::equal, VECTOR8_LOOP); 9528 jcc(Assembler::less, VECTOR4_TAIL); 9529 9530 if (UseAVX >= 2) { 9531 9532 cmpq(length, 16); 9533 jcc(Assembler::equal, VECTOR16_LOOP); 9534 jcc(Assembler::less, VECTOR8_LOOP); 9535 9536 cmpq(length, 32); 9537 jccb(Assembler::less, VECTOR16_TAIL); 9538 9539 subq(length, 32); 9540 bind(VECTOR32_LOOP); 9541 vmovdqu(rymm0, Address(obja, result)); 9542 vmovdqu(rymm1, Address(objb, result)); 9543 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit); 9544 vptest(rymm2, rymm2); 9545 jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found 9546 addq(result, 32); 9547 subq(length, 32); 9548 jccb(Assembler::greaterEqual, VECTOR32_LOOP); 9549 addq(length, 32); 9550 jcc(Assembler::equal, SAME_TILL_END); 9551 //falling through if less than 32 bytes left //close the branch here. 9552 9553 bind(VECTOR16_TAIL); 9554 cmpq(length, 16); 9555 jccb(Assembler::less, VECTOR8_TAIL); 9556 bind(VECTOR16_LOOP); 9557 movdqu(rymm0, Address(obja, result)); 9558 movdqu(rymm1, Address(objb, result)); 9559 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit); 9560 ptest(rymm2, rymm2); 9561 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found 9562 addq(result, 16); 9563 subq(length, 16); 9564 jcc(Assembler::equal, SAME_TILL_END); 9565 //falling through if less than 16 bytes left 9566 } else {//regular intrinsics 9567 9568 cmpq(length, 16); 9569 jccb(Assembler::less, VECTOR8_TAIL); 9570 9571 subq(length, 16); 9572 bind(VECTOR16_LOOP); 9573 movdqu(rymm0, Address(obja, result)); 9574 movdqu(rymm1, Address(objb, result)); 9575 pxor(rymm0, rymm1); 9576 ptest(rymm0, rymm0); 9577 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found 9578 addq(result, 16); 9579 subq(length, 16); 9580 jccb(Assembler::greaterEqual, VECTOR16_LOOP); 9581 addq(length, 16); 9582 jcc(Assembler::equal, SAME_TILL_END); 9583 //falling through if less than 16 bytes left 9584 } 9585 9586 bind(VECTOR8_TAIL); 9587 cmpq(length, 8); 9588 jccb(Assembler::less, VECTOR4_TAIL); 9589 bind(VECTOR8_LOOP); 9590 movq(tmp1, Address(obja, result)); 9591 movq(tmp2, Address(objb, result)); 9592 xorq(tmp1, tmp2); 9593 testq(tmp1, tmp1); 9594 jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found 9595 addq(result, 8); 9596 subq(length, 8); 9597 jcc(Assembler::equal, SAME_TILL_END); 9598 //falling through if less than 8 bytes left 9599 9600 bind(VECTOR4_TAIL); 9601 cmpq(length, 4); 9602 jccb(Assembler::less, BYTES_TAIL); 9603 bind(VECTOR4_LOOP); 9604 movl(tmp1, Address(obja, result)); 9605 xorl(tmp1, Address(objb, result)); 9606 testl(tmp1, tmp1); 9607 jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found 9608 addq(result, 4); 9609 subq(length, 4); 9610 jcc(Assembler::equal, SAME_TILL_END); 9611 //falling through if less than 4 bytes left 9612 9613 bind(BYTES_TAIL); 9614 bind(BYTES_LOOP); 9615 load_unsigned_byte(tmp1, Address(obja, result)); 9616 load_unsigned_byte(tmp2, Address(objb, result)); 9617 xorl(tmp1, tmp2); 9618 testl(tmp1, tmp1); 9619 jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found 9620 decq(length); 9621 jccb(Assembler::zero, SAME_TILL_END); 9622 incq(result); 9623 load_unsigned_byte(tmp1, Address(obja, result)); 9624 load_unsigned_byte(tmp2, Address(objb, result)); 9625 xorl(tmp1, tmp2); 9626 testl(tmp1, tmp1); 9627 jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found 9628 decq(length); 9629 jccb(Assembler::zero, SAME_TILL_END); 9630 incq(result); 9631 load_unsigned_byte(tmp1, Address(obja, result)); 9632 load_unsigned_byte(tmp2, Address(objb, result)); 9633 xorl(tmp1, tmp2); 9634 testl(tmp1, tmp1); 9635 jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found 9636 jmpb(SAME_TILL_END); 9637 9638 if (UseAVX >= 2) { 9639 bind(VECTOR32_NOT_EQUAL); 9640 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit); 9641 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit); 9642 vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit); 9643 vpmovmskb(tmp1, rymm0); 9644 bsfq(tmp1, tmp1); 9645 addq(result, tmp1); 9646 shrq(result); 9647 jmpb(DONE); 9648 } 9649 9650 bind(VECTOR16_NOT_EQUAL); 9651 if (UseAVX >= 2) { 9652 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit); 9653 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit); 9654 pxor(rymm0, rymm2); 9655 } else { 9656 pcmpeqb(rymm2, rymm2); 9657 pxor(rymm0, rymm1); 9658 pcmpeqb(rymm0, rymm1); 9659 pxor(rymm0, rymm2); 9660 } 9661 pmovmskb(tmp1, rymm0); 9662 bsfq(tmp1, tmp1); 9663 addq(result, tmp1); 9664 shrq(result); 9665 jmpb(DONE); 9666 9667 bind(VECTOR8_NOT_EQUAL); 9668 bind(VECTOR4_NOT_EQUAL); 9669 bsfq(tmp1, tmp1); 9670 shrq(tmp1, 3); 9671 addq(result, tmp1); 9672 bind(BYTES_NOT_EQUAL); 9673 shrq(result); 9674 jmpb(DONE); 9675 9676 bind(SAME_TILL_END); 9677 mov64(result, -1); 9678 9679 bind(DONE); 9680 } 9681 9682 //Helper functions for square_to_len() 9683 9684 /** 9685 * Store the squares of x[], right shifted one bit (divided by 2) into z[] 9686 * Preserves x and z and modifies rest of the registers. 9687 */ 9688 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) { 9689 // Perform square and right shift by 1 9690 // Handle odd xlen case first, then for even xlen do the following 9691 // jlong carry = 0; 9692 // for (int j=0, i=0; j < xlen; j+=2, i+=4) { 9693 // huge_128 product = x[j:j+1] * x[j:j+1]; 9694 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65); 9695 // z[i+2:i+3] = (jlong)(product >>> 1); 9696 // carry = (jlong)product; 9697 // } 9698 9699 xorq(tmp5, tmp5); // carry 9700 xorq(rdxReg, rdxReg); 9701 xorl(tmp1, tmp1); // index for x 9702 xorl(tmp4, tmp4); // index for z 9703 9704 Label L_first_loop, L_first_loop_exit; 9705 9706 testl(xlen, 1); 9707 jccb(Assembler::zero, L_first_loop); //jump if xlen is even 9708 9709 // Square and right shift by 1 the odd element using 32 bit multiply 9710 movl(raxReg, Address(x, tmp1, Address::times_4, 0)); 9711 imulq(raxReg, raxReg); 9712 shrq(raxReg, 1); 9713 adcq(tmp5, 0); 9714 movq(Address(z, tmp4, Address::times_4, 0), raxReg); 9715 incrementl(tmp1); 9716 addl(tmp4, 2); 9717 9718 // Square and right shift by 1 the rest using 64 bit multiply 9719 bind(L_first_loop); 9720 cmpptr(tmp1, xlen); 9721 jccb(Assembler::equal, L_first_loop_exit); 9722 9723 // Square 9724 movq(raxReg, Address(x, tmp1, Address::times_4, 0)); 9725 rorq(raxReg, 32); // convert big-endian to little-endian 9726 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax 9727 9728 // Right shift by 1 and save carry 9729 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1 9730 rcrq(rdxReg, 1); 9731 rcrq(raxReg, 1); 9732 adcq(tmp5, 0); 9733 9734 // Store result in z 9735 movq(Address(z, tmp4, Address::times_4, 0), rdxReg); 9736 movq(Address(z, tmp4, Address::times_4, 8), raxReg); 9737 9738 // Update indices for x and z 9739 addl(tmp1, 2); 9740 addl(tmp4, 4); 9741 jmp(L_first_loop); 9742 9743 bind(L_first_loop_exit); 9744 } 9745 9746 9747 /** 9748 * Perform the following multiply add operation using BMI2 instructions 9749 * carry:sum = sum + op1*op2 + carry 9750 * op2 should be in rdx 9751 * op2 is preserved, all other registers are modified 9752 */ 9753 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) { 9754 // assert op2 is rdx 9755 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1 9756 addq(sum, carry); 9757 adcq(tmp2, 0); 9758 addq(sum, op1); 9759 adcq(tmp2, 0); 9760 movq(carry, tmp2); 9761 } 9762 9763 /** 9764 * Perform the following multiply add operation: 9765 * carry:sum = sum + op1*op2 + carry 9766 * Preserves op1, op2 and modifies rest of registers 9767 */ 9768 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) { 9769 // rdx:rax = op1 * op2 9770 movq(raxReg, op2); 9771 mulq(op1); 9772 9773 // rdx:rax = sum + carry + rdx:rax 9774 addq(sum, carry); 9775 adcq(rdxReg, 0); 9776 addq(sum, raxReg); 9777 adcq(rdxReg, 0); 9778 9779 // carry:sum = rdx:sum 9780 movq(carry, rdxReg); 9781 } 9782 9783 /** 9784 * Add 64 bit long carry into z[] with carry propogation. 9785 * Preserves z and carry register values and modifies rest of registers. 9786 * 9787 */ 9788 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) { 9789 Label L_fourth_loop, L_fourth_loop_exit; 9790 9791 movl(tmp1, 1); 9792 subl(zlen, 2); 9793 addq(Address(z, zlen, Address::times_4, 0), carry); 9794 9795 bind(L_fourth_loop); 9796 jccb(Assembler::carryClear, L_fourth_loop_exit); 9797 subl(zlen, 2); 9798 jccb(Assembler::negative, L_fourth_loop_exit); 9799 addq(Address(z, zlen, Address::times_4, 0), tmp1); 9800 jmp(L_fourth_loop); 9801 bind(L_fourth_loop_exit); 9802 } 9803 9804 /** 9805 * Shift z[] left by 1 bit. 9806 * Preserves x, len, z and zlen registers and modifies rest of the registers. 9807 * 9808 */ 9809 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) { 9810 9811 Label L_fifth_loop, L_fifth_loop_exit; 9812 9813 // Fifth loop 9814 // Perform primitiveLeftShift(z, zlen, 1) 9815 9816 const Register prev_carry = tmp1; 9817 const Register new_carry = tmp4; 9818 const Register value = tmp2; 9819 const Register zidx = tmp3; 9820 9821 // int zidx, carry; 9822 // long value; 9823 // carry = 0; 9824 // for (zidx = zlen-2; zidx >=0; zidx -= 2) { 9825 // (carry:value) = (z[i] << 1) | carry ; 9826 // z[i] = value; 9827 // } 9828 9829 movl(zidx, zlen); 9830 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register 9831 9832 bind(L_fifth_loop); 9833 decl(zidx); // Use decl to preserve carry flag 9834 decl(zidx); 9835 jccb(Assembler::negative, L_fifth_loop_exit); 9836 9837 if (UseBMI2Instructions) { 9838 movq(value, Address(z, zidx, Address::times_4, 0)); 9839 rclq(value, 1); 9840 rorxq(value, value, 32); 9841 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form 9842 } 9843 else { 9844 // clear new_carry 9845 xorl(new_carry, new_carry); 9846 9847 // Shift z[i] by 1, or in previous carry and save new carry 9848 movq(value, Address(z, zidx, Address::times_4, 0)); 9849 shlq(value, 1); 9850 adcl(new_carry, 0); 9851 9852 orq(value, prev_carry); 9853 rorq(value, 0x20); 9854 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form 9855 9856 // Set previous carry = new carry 9857 movl(prev_carry, new_carry); 9858 } 9859 jmp(L_fifth_loop); 9860 9861 bind(L_fifth_loop_exit); 9862 } 9863 9864 9865 /** 9866 * Code for BigInteger::squareToLen() intrinsic 9867 * 9868 * rdi: x 9869 * rsi: len 9870 * r8: z 9871 * rcx: zlen 9872 * r12: tmp1 9873 * r13: tmp2 9874 * r14: tmp3 9875 * r15: tmp4 9876 * rbx: tmp5 9877 * 9878 */ 9879 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) { 9880 9881 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, fifth_loop, fifth_loop_exit, L_last_x, L_multiply; 9882 push(tmp1); 9883 push(tmp2); 9884 push(tmp3); 9885 push(tmp4); 9886 push(tmp5); 9887 9888 // First loop 9889 // Store the squares, right shifted one bit (i.e., divided by 2). 9890 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg); 9891 9892 // Add in off-diagonal sums. 9893 // 9894 // Second, third (nested) and fourth loops. 9895 // zlen +=2; 9896 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) { 9897 // carry = 0; 9898 // long op2 = x[xidx:xidx+1]; 9899 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) { 9900 // k -= 2; 9901 // long op1 = x[j:j+1]; 9902 // long sum = z[k:k+1]; 9903 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs); 9904 // z[k:k+1] = sum; 9905 // } 9906 // add_one_64(z, k, carry, tmp_regs); 9907 // } 9908 9909 const Register carry = tmp5; 9910 const Register sum = tmp3; 9911 const Register op1 = tmp4; 9912 Register op2 = tmp2; 9913 9914 push(zlen); 9915 push(len); 9916 addl(zlen,2); 9917 bind(L_second_loop); 9918 xorq(carry, carry); 9919 subl(zlen, 4); 9920 subl(len, 2); 9921 push(zlen); 9922 push(len); 9923 cmpl(len, 0); 9924 jccb(Assembler::lessEqual, L_second_loop_exit); 9925 9926 // Multiply an array by one 64 bit long. 9927 if (UseBMI2Instructions) { 9928 op2 = rdxReg; 9929 movq(op2, Address(x, len, Address::times_4, 0)); 9930 rorxq(op2, op2, 32); 9931 } 9932 else { 9933 movq(op2, Address(x, len, Address::times_4, 0)); 9934 rorq(op2, 32); 9935 } 9936 9937 bind(L_third_loop); 9938 decrementl(len); 9939 jccb(Assembler::negative, L_third_loop_exit); 9940 decrementl(len); 9941 jccb(Assembler::negative, L_last_x); 9942 9943 movq(op1, Address(x, len, Address::times_4, 0)); 9944 rorq(op1, 32); 9945 9946 bind(L_multiply); 9947 subl(zlen, 2); 9948 movq(sum, Address(z, zlen, Address::times_4, 0)); 9949 9950 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry. 9951 if (UseBMI2Instructions) { 9952 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2); 9953 } 9954 else { 9955 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg); 9956 } 9957 9958 movq(Address(z, zlen, Address::times_4, 0), sum); 9959 9960 jmp(L_third_loop); 9961 bind(L_third_loop_exit); 9962 9963 // Fourth loop 9964 // Add 64 bit long carry into z with carry propogation. 9965 // Uses offsetted zlen. 9966 add_one_64(z, zlen, carry, tmp1); 9967 9968 pop(len); 9969 pop(zlen); 9970 jmp(L_second_loop); 9971 9972 // Next infrequent code is moved outside loops. 9973 bind(L_last_x); 9974 movl(op1, Address(x, 0)); 9975 jmp(L_multiply); 9976 9977 bind(L_second_loop_exit); 9978 pop(len); 9979 pop(zlen); 9980 pop(len); 9981 pop(zlen); 9982 9983 // Fifth loop 9984 // Shift z left 1 bit. 9985 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4); 9986 9987 // z[zlen-1] |= x[len-1] & 1; 9988 movl(tmp3, Address(x, len, Address::times_4, -4)); 9989 andl(tmp3, 1); 9990 orl(Address(z, zlen, Address::times_4, -4), tmp3); 9991 9992 pop(tmp5); 9993 pop(tmp4); 9994 pop(tmp3); 9995 pop(tmp2); 9996 pop(tmp1); 9997 } 9998 9999 /** 10000 * Helper function for mul_add() 10001 * Multiply the in[] by int k and add to out[] starting at offset offs using 10002 * 128 bit by 32 bit multiply and return the carry in tmp5. 10003 * Only quad int aligned length of in[] is operated on in this function. 10004 * k is in rdxReg for BMI2Instructions, for others it is in tmp2. 10005 * This function preserves out, in and k registers. 10006 * len and offset point to the appropriate index in "in" & "out" correspondingly 10007 * tmp5 has the carry. 10008 * other registers are temporary and are modified. 10009 * 10010 */ 10011 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in, 10012 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3, 10013 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) { 10014 10015 Label L_first_loop, L_first_loop_exit; 10016 10017 movl(tmp1, len); 10018 shrl(tmp1, 2); 10019 10020 bind(L_first_loop); 10021 subl(tmp1, 1); 10022 jccb(Assembler::negative, L_first_loop_exit); 10023 10024 subl(len, 4); 10025 subl(offset, 4); 10026 10027 Register op2 = tmp2; 10028 const Register sum = tmp3; 10029 const Register op1 = tmp4; 10030 const Register carry = tmp5; 10031 10032 if (UseBMI2Instructions) { 10033 op2 = rdxReg; 10034 } 10035 10036 movq(op1, Address(in, len, Address::times_4, 8)); 10037 rorq(op1, 32); 10038 movq(sum, Address(out, offset, Address::times_4, 8)); 10039 rorq(sum, 32); 10040 if (UseBMI2Instructions) { 10041 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg); 10042 } 10043 else { 10044 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg); 10045 } 10046 // Store back in big endian from little endian 10047 rorq(sum, 0x20); 10048 movq(Address(out, offset, Address::times_4, 8), sum); 10049 10050 movq(op1, Address(in, len, Address::times_4, 0)); 10051 rorq(op1, 32); 10052 movq(sum, Address(out, offset, Address::times_4, 0)); 10053 rorq(sum, 32); 10054 if (UseBMI2Instructions) { 10055 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg); 10056 } 10057 else { 10058 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg); 10059 } 10060 // Store back in big endian from little endian 10061 rorq(sum, 0x20); 10062 movq(Address(out, offset, Address::times_4, 0), sum); 10063 10064 jmp(L_first_loop); 10065 bind(L_first_loop_exit); 10066 } 10067 10068 /** 10069 * Code for BigInteger::mulAdd() intrinsic 10070 * 10071 * rdi: out 10072 * rsi: in 10073 * r11: offs (out.length - offset) 10074 * rcx: len 10075 * r8: k 10076 * r12: tmp1 10077 * r13: tmp2 10078 * r14: tmp3 10079 * r15: tmp4 10080 * rbx: tmp5 10081 * Multiply the in[] by word k and add to out[], return the carry in rax 10082 */ 10083 void MacroAssembler::mul_add(Register out, Register in, Register offs, 10084 Register len, Register k, Register tmp1, Register tmp2, Register tmp3, 10085 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) { 10086 10087 Label L_carry, L_last_in, L_done; 10088 10089 // carry = 0; 10090 // for (int j=len-1; j >= 0; j--) { 10091 // long product = (in[j] & LONG_MASK) * kLong + 10092 // (out[offs] & LONG_MASK) + carry; 10093 // out[offs--] = (int)product; 10094 // carry = product >>> 32; 10095 // } 10096 // 10097 push(tmp1); 10098 push(tmp2); 10099 push(tmp3); 10100 push(tmp4); 10101 push(tmp5); 10102 10103 Register op2 = tmp2; 10104 const Register sum = tmp3; 10105 const Register op1 = tmp4; 10106 const Register carry = tmp5; 10107 10108 if (UseBMI2Instructions) { 10109 op2 = rdxReg; 10110 movl(op2, k); 10111 } 10112 else { 10113 movl(op2, k); 10114 } 10115 10116 xorq(carry, carry); 10117 10118 //First loop 10119 10120 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply 10121 //The carry is in tmp5 10122 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg); 10123 10124 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any 10125 decrementl(len); 10126 jccb(Assembler::negative, L_carry); 10127 decrementl(len); 10128 jccb(Assembler::negative, L_last_in); 10129 10130 movq(op1, Address(in, len, Address::times_4, 0)); 10131 rorq(op1, 32); 10132 10133 subl(offs, 2); 10134 movq(sum, Address(out, offs, Address::times_4, 0)); 10135 rorq(sum, 32); 10136 10137 if (UseBMI2Instructions) { 10138 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg); 10139 } 10140 else { 10141 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg); 10142 } 10143 10144 // Store back in big endian from little endian 10145 rorq(sum, 0x20); 10146 movq(Address(out, offs, Address::times_4, 0), sum); 10147 10148 testl(len, len); 10149 jccb(Assembler::zero, L_carry); 10150 10151 //Multiply the last in[] entry, if any 10152 bind(L_last_in); 10153 movl(op1, Address(in, 0)); 10154 movl(sum, Address(out, offs, Address::times_4, -4)); 10155 10156 movl(raxReg, k); 10157 mull(op1); //tmp4 * eax -> edx:eax 10158 addl(sum, carry); 10159 adcl(rdxReg, 0); 10160 addl(sum, raxReg); 10161 adcl(rdxReg, 0); 10162 movl(carry, rdxReg); 10163 10164 movl(Address(out, offs, Address::times_4, -4), sum); 10165 10166 bind(L_carry); 10167 //return tmp5/carry as carry in rax 10168 movl(rax, carry); 10169 10170 bind(L_done); 10171 pop(tmp5); 10172 pop(tmp4); 10173 pop(tmp3); 10174 pop(tmp2); 10175 pop(tmp1); 10176 } 10177 #endif 10178 10179 /** 10180 * Emits code to update CRC-32 with a byte value according to constants in table 10181 * 10182 * @param [in,out]crc Register containing the crc. 10183 * @param [in]val Register containing the byte to fold into the CRC. 10184 * @param [in]table Register containing the table of crc constants. 10185 * 10186 * uint32_t crc; 10187 * val = crc_table[(val ^ crc) & 0xFF]; 10188 * crc = val ^ (crc >> 8); 10189 * 10190 */ 10191 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) { 10192 xorl(val, crc); 10193 andl(val, 0xFF); 10194 shrl(crc, 8); // unsigned shift 10195 xorl(crc, Address(table, val, Address::times_4, 0)); 10196 } 10197 10198 /** 10199 * Fold 128-bit data chunk 10200 */ 10201 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) { 10202 if (UseAVX > 0) { 10203 vpclmulhdq(xtmp, xK, xcrc); // [123:64] 10204 vpclmulldq(xcrc, xK, xcrc); // [63:0] 10205 vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */); 10206 pxor(xcrc, xtmp); 10207 } else { 10208 movdqa(xtmp, xcrc); 10209 pclmulhdq(xtmp, xK); // [123:64] 10210 pclmulldq(xcrc, xK); // [63:0] 10211 pxor(xcrc, xtmp); 10212 movdqu(xtmp, Address(buf, offset)); 10213 pxor(xcrc, xtmp); 10214 } 10215 } 10216 10217 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) { 10218 if (UseAVX > 0) { 10219 vpclmulhdq(xtmp, xK, xcrc); 10220 vpclmulldq(xcrc, xK, xcrc); 10221 pxor(xcrc, xbuf); 10222 pxor(xcrc, xtmp); 10223 } else { 10224 movdqa(xtmp, xcrc); 10225 pclmulhdq(xtmp, xK); 10226 pclmulldq(xcrc, xK); 10227 pxor(xcrc, xbuf); 10228 pxor(xcrc, xtmp); 10229 } 10230 } 10231 10232 /** 10233 * 8-bit folds to compute 32-bit CRC 10234 * 10235 * uint64_t xcrc; 10236 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8); 10237 */ 10238 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) { 10239 movdl(tmp, xcrc); 10240 andl(tmp, 0xFF); 10241 movdl(xtmp, Address(table, tmp, Address::times_4, 0)); 10242 psrldq(xcrc, 1); // unsigned shift one byte 10243 pxor(xcrc, xtmp); 10244 } 10245 10246 /** 10247 * uint32_t crc; 10248 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8); 10249 */ 10250 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) { 10251 movl(tmp, crc); 10252 andl(tmp, 0xFF); 10253 shrl(crc, 8); 10254 xorl(crc, Address(table, tmp, Address::times_4, 0)); 10255 } 10256 10257 /** 10258 * @param crc register containing existing CRC (32-bit) 10259 * @param buf register pointing to input byte buffer (byte*) 10260 * @param len register containing number of bytes 10261 * @param table register that will contain address of CRC table 10262 * @param tmp scratch register 10263 */ 10264 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) { 10265 assert_different_registers(crc, buf, len, table, tmp, rax); 10266 10267 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned; 10268 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop; 10269 10270 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge 10271 // context for the registers used, where all instructions below are using 128-bit mode 10272 // On EVEX without VL and BW, these instructions will all be AVX. 10273 if (VM_Version::supports_avx512vlbw()) { 10274 movl(tmp, 0xffff); 10275 kmovwl(k1, tmp); 10276 } 10277 10278 lea(table, ExternalAddress(StubRoutines::crc_table_addr())); 10279 notl(crc); // ~crc 10280 cmpl(len, 16); 10281 jcc(Assembler::less, L_tail); 10282 10283 // Align buffer to 16 bytes 10284 movl(tmp, buf); 10285 andl(tmp, 0xF); 10286 jccb(Assembler::zero, L_aligned); 10287 subl(tmp, 16); 10288 addl(len, tmp); 10289 10290 align(4); 10291 BIND(L_align_loop); 10292 movsbl(rax, Address(buf, 0)); // load byte with sign extension 10293 update_byte_crc32(crc, rax, table); 10294 increment(buf); 10295 incrementl(tmp); 10296 jccb(Assembler::less, L_align_loop); 10297 10298 BIND(L_aligned); 10299 movl(tmp, len); // save 10300 shrl(len, 4); 10301 jcc(Assembler::zero, L_tail_restore); 10302 10303 // Fold crc into first bytes of vector 10304 movdqa(xmm1, Address(buf, 0)); 10305 movdl(rax, xmm1); 10306 xorl(crc, rax); 10307 if (VM_Version::supports_sse4_1()) { 10308 pinsrd(xmm1, crc, 0); 10309 } else { 10310 pinsrw(xmm1, crc, 0); 10311 shrl(crc, 16); 10312 pinsrw(xmm1, crc, 1); 10313 } 10314 addptr(buf, 16); 10315 subl(len, 4); // len > 0 10316 jcc(Assembler::less, L_fold_tail); 10317 10318 movdqa(xmm2, Address(buf, 0)); 10319 movdqa(xmm3, Address(buf, 16)); 10320 movdqa(xmm4, Address(buf, 32)); 10321 addptr(buf, 48); 10322 subl(len, 3); 10323 jcc(Assembler::lessEqual, L_fold_512b); 10324 10325 // Fold total 512 bits of polynomial on each iteration, 10326 // 128 bits per each of 4 parallel streams. 10327 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32)); 10328 10329 align(32); 10330 BIND(L_fold_512b_loop); 10331 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0); 10332 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16); 10333 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32); 10334 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48); 10335 addptr(buf, 64); 10336 subl(len, 4); 10337 jcc(Assembler::greater, L_fold_512b_loop); 10338 10339 // Fold 512 bits to 128 bits. 10340 BIND(L_fold_512b); 10341 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16)); 10342 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2); 10343 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3); 10344 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4); 10345 10346 // Fold the rest of 128 bits data chunks 10347 BIND(L_fold_tail); 10348 addl(len, 3); 10349 jccb(Assembler::lessEqual, L_fold_128b); 10350 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16)); 10351 10352 BIND(L_fold_tail_loop); 10353 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0); 10354 addptr(buf, 16); 10355 decrementl(len); 10356 jccb(Assembler::greater, L_fold_tail_loop); 10357 10358 // Fold 128 bits in xmm1 down into 32 bits in crc register. 10359 BIND(L_fold_128b); 10360 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr())); 10361 if (UseAVX > 0) { 10362 vpclmulqdq(xmm2, xmm0, xmm1, 0x1); 10363 vpand(xmm3, xmm0, xmm2, 0 /* vector_len */); 10364 vpclmulqdq(xmm0, xmm0, xmm3, 0x1); 10365 } else { 10366 movdqa(xmm2, xmm0); 10367 pclmulqdq(xmm2, xmm1, 0x1); 10368 movdqa(xmm3, xmm0); 10369 pand(xmm3, xmm2); 10370 pclmulqdq(xmm0, xmm3, 0x1); 10371 } 10372 psrldq(xmm1, 8); 10373 psrldq(xmm2, 4); 10374 pxor(xmm0, xmm1); 10375 pxor(xmm0, xmm2); 10376 10377 // 8 8-bit folds to compute 32-bit CRC. 10378 for (int j = 0; j < 4; j++) { 10379 fold_8bit_crc32(xmm0, table, xmm1, rax); 10380 } 10381 movdl(crc, xmm0); // mov 32 bits to general register 10382 for (int j = 0; j < 4; j++) { 10383 fold_8bit_crc32(crc, table, rax); 10384 } 10385 10386 BIND(L_tail_restore); 10387 movl(len, tmp); // restore 10388 BIND(L_tail); 10389 andl(len, 0xf); 10390 jccb(Assembler::zero, L_exit); 10391 10392 // Fold the rest of bytes 10393 align(4); 10394 BIND(L_tail_loop); 10395 movsbl(rax, Address(buf, 0)); // load byte with sign extension 10396 update_byte_crc32(crc, rax, table); 10397 increment(buf); 10398 decrementl(len); 10399 jccb(Assembler::greater, L_tail_loop); 10400 10401 BIND(L_exit); 10402 notl(crc); // ~c 10403 } 10404 10405 #ifdef _LP64 10406 // S. Gueron / Information Processing Letters 112 (2012) 184 10407 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table. 10408 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0]. 10409 // Output: the 64-bit carry-less product of B * CONST 10410 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n, 10411 Register tmp1, Register tmp2, Register tmp3) { 10412 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr())); 10413 if (n > 0) { 10414 addq(tmp3, n * 256 * 8); 10415 } 10416 // Q1 = TABLEExt[n][B & 0xFF]; 10417 movl(tmp1, in); 10418 andl(tmp1, 0x000000FF); 10419 shll(tmp1, 3); 10420 addq(tmp1, tmp3); 10421 movq(tmp1, Address(tmp1, 0)); 10422 10423 // Q2 = TABLEExt[n][B >> 8 & 0xFF]; 10424 movl(tmp2, in); 10425 shrl(tmp2, 8); 10426 andl(tmp2, 0x000000FF); 10427 shll(tmp2, 3); 10428 addq(tmp2, tmp3); 10429 movq(tmp2, Address(tmp2, 0)); 10430 10431 shlq(tmp2, 8); 10432 xorq(tmp1, tmp2); 10433 10434 // Q3 = TABLEExt[n][B >> 16 & 0xFF]; 10435 movl(tmp2, in); 10436 shrl(tmp2, 16); 10437 andl(tmp2, 0x000000FF); 10438 shll(tmp2, 3); 10439 addq(tmp2, tmp3); 10440 movq(tmp2, Address(tmp2, 0)); 10441 10442 shlq(tmp2, 16); 10443 xorq(tmp1, tmp2); 10444 10445 // Q4 = TABLEExt[n][B >> 24 & 0xFF]; 10446 shrl(in, 24); 10447 andl(in, 0x000000FF); 10448 shll(in, 3); 10449 addq(in, tmp3); 10450 movq(in, Address(in, 0)); 10451 10452 shlq(in, 24); 10453 xorq(in, tmp1); 10454 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24; 10455 } 10456 10457 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1, 10458 Register in_out, 10459 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported, 10460 XMMRegister w_xtmp2, 10461 Register tmp1, 10462 Register n_tmp2, Register n_tmp3) { 10463 if (is_pclmulqdq_supported) { 10464 movdl(w_xtmp1, in_out); // modified blindly 10465 10466 movl(tmp1, const_or_pre_comp_const_index); 10467 movdl(w_xtmp2, tmp1); 10468 pclmulqdq(w_xtmp1, w_xtmp2, 0); 10469 10470 movdq(in_out, w_xtmp1); 10471 } else { 10472 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3); 10473 } 10474 } 10475 10476 // Recombination Alternative 2: No bit-reflections 10477 // T1 = (CRC_A * U1) << 1 10478 // T2 = (CRC_B * U2) << 1 10479 // C1 = T1 >> 32 10480 // C2 = T2 >> 32 10481 // T1 = T1 & 0xFFFFFFFF 10482 // T2 = T2 & 0xFFFFFFFF 10483 // T1 = CRC32(0, T1) 10484 // T2 = CRC32(0, T2) 10485 // C1 = C1 ^ T1 10486 // C2 = C2 ^ T2 10487 // CRC = C1 ^ C2 ^ CRC_C 10488 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2, 10489 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 10490 Register tmp1, Register tmp2, 10491 Register n_tmp3) { 10492 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3); 10493 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3); 10494 shlq(in_out, 1); 10495 movl(tmp1, in_out); 10496 shrq(in_out, 32); 10497 xorl(tmp2, tmp2); 10498 crc32(tmp2, tmp1, 4); 10499 xorl(in_out, tmp2); // we don't care about upper 32 bit contents here 10500 shlq(in1, 1); 10501 movl(tmp1, in1); 10502 shrq(in1, 32); 10503 xorl(tmp2, tmp2); 10504 crc32(tmp2, tmp1, 4); 10505 xorl(in1, tmp2); 10506 xorl(in_out, in1); 10507 xorl(in_out, in2); 10508 } 10509 10510 // Set N to predefined value 10511 // Subtract from a lenght of a buffer 10512 // execute in a loop: 10513 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0 10514 // for i = 1 to N do 10515 // CRC_A = CRC32(CRC_A, A[i]) 10516 // CRC_B = CRC32(CRC_B, B[i]) 10517 // CRC_C = CRC32(CRC_C, C[i]) 10518 // end for 10519 // Recombine 10520 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, 10521 Register in_out1, Register in_out2, Register in_out3, 10522 Register tmp1, Register tmp2, Register tmp3, 10523 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 10524 Register tmp4, Register tmp5, 10525 Register n_tmp6) { 10526 Label L_processPartitions; 10527 Label L_processPartition; 10528 Label L_exit; 10529 10530 bind(L_processPartitions); 10531 cmpl(in_out1, 3 * size); 10532 jcc(Assembler::less, L_exit); 10533 xorl(tmp1, tmp1); 10534 xorl(tmp2, tmp2); 10535 movq(tmp3, in_out2); 10536 addq(tmp3, size); 10537 10538 bind(L_processPartition); 10539 crc32(in_out3, Address(in_out2, 0), 8); 10540 crc32(tmp1, Address(in_out2, size), 8); 10541 crc32(tmp2, Address(in_out2, size * 2), 8); 10542 addq(in_out2, 8); 10543 cmpq(in_out2, tmp3); 10544 jcc(Assembler::less, L_processPartition); 10545 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2, 10546 w_xtmp1, w_xtmp2, w_xtmp3, 10547 tmp4, tmp5, 10548 n_tmp6); 10549 addq(in_out2, 2 * size); 10550 subl(in_out1, 3 * size); 10551 jmp(L_processPartitions); 10552 10553 bind(L_exit); 10554 } 10555 #else 10556 void MacroAssembler::crc32c_ipl_alg4(Register in_out, uint32_t n, 10557 Register tmp1, Register tmp2, Register tmp3, 10558 XMMRegister xtmp1, XMMRegister xtmp2) { 10559 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr())); 10560 if (n > 0) { 10561 addl(tmp3, n * 256 * 8); 10562 } 10563 // Q1 = TABLEExt[n][B & 0xFF]; 10564 movl(tmp1, in_out); 10565 andl(tmp1, 0x000000FF); 10566 shll(tmp1, 3); 10567 addl(tmp1, tmp3); 10568 movq(xtmp1, Address(tmp1, 0)); 10569 10570 // Q2 = TABLEExt[n][B >> 8 & 0xFF]; 10571 movl(tmp2, in_out); 10572 shrl(tmp2, 8); 10573 andl(tmp2, 0x000000FF); 10574 shll(tmp2, 3); 10575 addl(tmp2, tmp3); 10576 movq(xtmp2, Address(tmp2, 0)); 10577 10578 psllq(xtmp2, 8); 10579 pxor(xtmp1, xtmp2); 10580 10581 // Q3 = TABLEExt[n][B >> 16 & 0xFF]; 10582 movl(tmp2, in_out); 10583 shrl(tmp2, 16); 10584 andl(tmp2, 0x000000FF); 10585 shll(tmp2, 3); 10586 addl(tmp2, tmp3); 10587 movq(xtmp2, Address(tmp2, 0)); 10588 10589 psllq(xtmp2, 16); 10590 pxor(xtmp1, xtmp2); 10591 10592 // Q4 = TABLEExt[n][B >> 24 & 0xFF]; 10593 shrl(in_out, 24); 10594 andl(in_out, 0x000000FF); 10595 shll(in_out, 3); 10596 addl(in_out, tmp3); 10597 movq(xtmp2, Address(in_out, 0)); 10598 10599 psllq(xtmp2, 24); 10600 pxor(xtmp1, xtmp2); // Result in CXMM 10601 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24; 10602 } 10603 10604 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1, 10605 Register in_out, 10606 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported, 10607 XMMRegister w_xtmp2, 10608 Register tmp1, 10609 Register n_tmp2, Register n_tmp3) { 10610 if (is_pclmulqdq_supported) { 10611 movdl(w_xtmp1, in_out); 10612 10613 movl(tmp1, const_or_pre_comp_const_index); 10614 movdl(w_xtmp2, tmp1); 10615 pclmulqdq(w_xtmp1, w_xtmp2, 0); 10616 // Keep result in XMM since GPR is 32 bit in length 10617 } else { 10618 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3, w_xtmp1, w_xtmp2); 10619 } 10620 } 10621 10622 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2, 10623 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 10624 Register tmp1, Register tmp2, 10625 Register n_tmp3) { 10626 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3); 10627 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3); 10628 10629 psllq(w_xtmp1, 1); 10630 movdl(tmp1, w_xtmp1); 10631 psrlq(w_xtmp1, 32); 10632 movdl(in_out, w_xtmp1); 10633 10634 xorl(tmp2, tmp2); 10635 crc32(tmp2, tmp1, 4); 10636 xorl(in_out, tmp2); 10637 10638 psllq(w_xtmp2, 1); 10639 movdl(tmp1, w_xtmp2); 10640 psrlq(w_xtmp2, 32); 10641 movdl(in1, w_xtmp2); 10642 10643 xorl(tmp2, tmp2); 10644 crc32(tmp2, tmp1, 4); 10645 xorl(in1, tmp2); 10646 xorl(in_out, in1); 10647 xorl(in_out, in2); 10648 } 10649 10650 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, 10651 Register in_out1, Register in_out2, Register in_out3, 10652 Register tmp1, Register tmp2, Register tmp3, 10653 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 10654 Register tmp4, Register tmp5, 10655 Register n_tmp6) { 10656 Label L_processPartitions; 10657 Label L_processPartition; 10658 Label L_exit; 10659 10660 bind(L_processPartitions); 10661 cmpl(in_out1, 3 * size); 10662 jcc(Assembler::less, L_exit); 10663 xorl(tmp1, tmp1); 10664 xorl(tmp2, tmp2); 10665 movl(tmp3, in_out2); 10666 addl(tmp3, size); 10667 10668 bind(L_processPartition); 10669 crc32(in_out3, Address(in_out2, 0), 4); 10670 crc32(tmp1, Address(in_out2, size), 4); 10671 crc32(tmp2, Address(in_out2, size*2), 4); 10672 crc32(in_out3, Address(in_out2, 0+4), 4); 10673 crc32(tmp1, Address(in_out2, size+4), 4); 10674 crc32(tmp2, Address(in_out2, size*2+4), 4); 10675 addl(in_out2, 8); 10676 cmpl(in_out2, tmp3); 10677 jcc(Assembler::less, L_processPartition); 10678 10679 push(tmp3); 10680 push(in_out1); 10681 push(in_out2); 10682 tmp4 = tmp3; 10683 tmp5 = in_out1; 10684 n_tmp6 = in_out2; 10685 10686 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2, 10687 w_xtmp1, w_xtmp2, w_xtmp3, 10688 tmp4, tmp5, 10689 n_tmp6); 10690 10691 pop(in_out2); 10692 pop(in_out1); 10693 pop(tmp3); 10694 10695 addl(in_out2, 2 * size); 10696 subl(in_out1, 3 * size); 10697 jmp(L_processPartitions); 10698 10699 bind(L_exit); 10700 } 10701 #endif //LP64 10702 10703 #ifdef _LP64 10704 // Algorithm 2: Pipelined usage of the CRC32 instruction. 10705 // Input: A buffer I of L bytes. 10706 // Output: the CRC32C value of the buffer. 10707 // Notations: 10708 // Write L = 24N + r, with N = floor (L/24). 10709 // r = L mod 24 (0 <= r < 24). 10710 // Consider I as the concatenation of A|B|C|R, where A, B, C, each, 10711 // N quadwords, and R consists of r bytes. 10712 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1 10713 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1 10714 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1 10715 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1 10716 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2, 10717 Register tmp1, Register tmp2, Register tmp3, 10718 Register tmp4, Register tmp5, Register tmp6, 10719 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 10720 bool is_pclmulqdq_supported) { 10721 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS]; 10722 Label L_wordByWord; 10723 Label L_byteByByteProlog; 10724 Label L_byteByByte; 10725 Label L_exit; 10726 10727 if (is_pclmulqdq_supported ) { 10728 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr; 10729 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr+1); 10730 10731 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2); 10732 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3); 10733 10734 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4); 10735 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5); 10736 assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\""); 10737 } else { 10738 const_or_pre_comp_const_index[0] = 1; 10739 const_or_pre_comp_const_index[1] = 0; 10740 10741 const_or_pre_comp_const_index[2] = 3; 10742 const_or_pre_comp_const_index[3] = 2; 10743 10744 const_or_pre_comp_const_index[4] = 5; 10745 const_or_pre_comp_const_index[5] = 4; 10746 } 10747 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported, 10748 in2, in1, in_out, 10749 tmp1, tmp2, tmp3, 10750 w_xtmp1, w_xtmp2, w_xtmp3, 10751 tmp4, tmp5, 10752 tmp6); 10753 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported, 10754 in2, in1, in_out, 10755 tmp1, tmp2, tmp3, 10756 w_xtmp1, w_xtmp2, w_xtmp3, 10757 tmp4, tmp5, 10758 tmp6); 10759 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported, 10760 in2, in1, in_out, 10761 tmp1, tmp2, tmp3, 10762 w_xtmp1, w_xtmp2, w_xtmp3, 10763 tmp4, tmp5, 10764 tmp6); 10765 movl(tmp1, in2); 10766 andl(tmp1, 0x00000007); 10767 negl(tmp1); 10768 addl(tmp1, in2); 10769 addq(tmp1, in1); 10770 10771 BIND(L_wordByWord); 10772 cmpq(in1, tmp1); 10773 jcc(Assembler::greaterEqual, L_byteByByteProlog); 10774 crc32(in_out, Address(in1, 0), 4); 10775 addq(in1, 4); 10776 jmp(L_wordByWord); 10777 10778 BIND(L_byteByByteProlog); 10779 andl(in2, 0x00000007); 10780 movl(tmp2, 1); 10781 10782 BIND(L_byteByByte); 10783 cmpl(tmp2, in2); 10784 jccb(Assembler::greater, L_exit); 10785 crc32(in_out, Address(in1, 0), 1); 10786 incq(in1); 10787 incl(tmp2); 10788 jmp(L_byteByByte); 10789 10790 BIND(L_exit); 10791 } 10792 #else 10793 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2, 10794 Register tmp1, Register tmp2, Register tmp3, 10795 Register tmp4, Register tmp5, Register tmp6, 10796 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 10797 bool is_pclmulqdq_supported) { 10798 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS]; 10799 Label L_wordByWord; 10800 Label L_byteByByteProlog; 10801 Label L_byteByByte; 10802 Label L_exit; 10803 10804 if (is_pclmulqdq_supported) { 10805 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr; 10806 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 1); 10807 10808 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2); 10809 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3); 10810 10811 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4); 10812 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5); 10813 } else { 10814 const_or_pre_comp_const_index[0] = 1; 10815 const_or_pre_comp_const_index[1] = 0; 10816 10817 const_or_pre_comp_const_index[2] = 3; 10818 const_or_pre_comp_const_index[3] = 2; 10819 10820 const_or_pre_comp_const_index[4] = 5; 10821 const_or_pre_comp_const_index[5] = 4; 10822 } 10823 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported, 10824 in2, in1, in_out, 10825 tmp1, tmp2, tmp3, 10826 w_xtmp1, w_xtmp2, w_xtmp3, 10827 tmp4, tmp5, 10828 tmp6); 10829 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported, 10830 in2, in1, in_out, 10831 tmp1, tmp2, tmp3, 10832 w_xtmp1, w_xtmp2, w_xtmp3, 10833 tmp4, tmp5, 10834 tmp6); 10835 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported, 10836 in2, in1, in_out, 10837 tmp1, tmp2, tmp3, 10838 w_xtmp1, w_xtmp2, w_xtmp3, 10839 tmp4, tmp5, 10840 tmp6); 10841 movl(tmp1, in2); 10842 andl(tmp1, 0x00000007); 10843 negl(tmp1); 10844 addl(tmp1, in2); 10845 addl(tmp1, in1); 10846 10847 BIND(L_wordByWord); 10848 cmpl(in1, tmp1); 10849 jcc(Assembler::greaterEqual, L_byteByByteProlog); 10850 crc32(in_out, Address(in1,0), 4); 10851 addl(in1, 4); 10852 jmp(L_wordByWord); 10853 10854 BIND(L_byteByByteProlog); 10855 andl(in2, 0x00000007); 10856 movl(tmp2, 1); 10857 10858 BIND(L_byteByByte); 10859 cmpl(tmp2, in2); 10860 jccb(Assembler::greater, L_exit); 10861 movb(tmp1, Address(in1, 0)); 10862 crc32(in_out, tmp1, 1); 10863 incl(in1); 10864 incl(tmp2); 10865 jmp(L_byteByByte); 10866 10867 BIND(L_exit); 10868 } 10869 #endif // LP64 10870 #undef BIND 10871 #undef BLOCK_COMMENT 10872 10873 // Compress char[] array to byte[]. 10874 // ..\jdk\src\java.base\share\classes\java\lang\StringUTF16.java 10875 // @HotSpotIntrinsicCandidate 10876 // private static int compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) { 10877 // for (int i = 0; i < len; i++) { 10878 // int c = src[srcOff++]; 10879 // if (c >>> 8 != 0) { 10880 // return 0; 10881 // } 10882 // dst[dstOff++] = (byte)c; 10883 // } 10884 // return len; 10885 // } 10886 void MacroAssembler::char_array_compress(Register src, Register dst, Register len, 10887 XMMRegister tmp1Reg, XMMRegister tmp2Reg, 10888 XMMRegister tmp3Reg, XMMRegister tmp4Reg, 10889 Register tmp5, Register result) { 10890 Label copy_chars_loop, return_length, return_zero, done, below_threshold; 10891 10892 // rsi: src 10893 // rdi: dst 10894 // rdx: len 10895 // rcx: tmp5 10896 // rax: result 10897 10898 // rsi holds start addr of source char[] to be compressed 10899 // rdi holds start addr of destination byte[] 10900 // rdx holds length 10901 10902 assert(len != result, ""); 10903 10904 // save length for return 10905 push(len); 10906 10907 if ((UseAVX > 2) && // AVX512 10908 VM_Version::supports_avx512vlbw() && 10909 VM_Version::supports_bmi2()) { 10910 10911 set_vector_masking(); // opening of the stub context for programming mask registers 10912 10913 Label copy_32_loop, copy_loop_tail, restore_k1_return_zero; 10914 10915 // alignement 10916 Label post_alignement; 10917 10918 // if length of the string is less than 16, handle it in an old fashioned 10919 // way 10920 testl(len, -32); 10921 jcc(Assembler::zero, below_threshold); 10922 10923 // First check whether a character is compressable ( <= 0xFF). 10924 // Create mask to test for Unicode chars inside zmm vector 10925 movl(result, 0x00FF); 10926 evpbroadcastw(tmp2Reg, result, Assembler::AVX_512bit); 10927 10928 // Save k1 10929 kmovql(k3, k1); 10930 10931 testl(len, -64); 10932 jcc(Assembler::zero, post_alignement); 10933 10934 movl(tmp5, dst); 10935 andl(tmp5, (32 - 1)); 10936 negl(tmp5); 10937 andl(tmp5, (32 - 1)); 10938 10939 // bail out when there is nothing to be done 10940 testl(tmp5, 0xFFFFFFFF); 10941 jcc(Assembler::zero, post_alignement); 10942 10943 // ~(~0 << len), where len is the # of remaining elements to process 10944 movl(result, 0xFFFFFFFF); 10945 shlxl(result, result, tmp5); 10946 notl(result); 10947 kmovdl(k1, result); 10948 10949 evmovdquw(tmp1Reg, k1, Address(src, 0), Assembler::AVX_512bit); 10950 evpcmpuw(k2, k1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit); 10951 ktestd(k2, k1); 10952 jcc(Assembler::carryClear, restore_k1_return_zero); 10953 10954 evpmovwb(Address(dst, 0), k1, tmp1Reg, Assembler::AVX_512bit); 10955 10956 addptr(src, tmp5); 10957 addptr(src, tmp5); 10958 addptr(dst, tmp5); 10959 subl(len, tmp5); 10960 10961 bind(post_alignement); 10962 // end of alignement 10963 10964 movl(tmp5, len); 10965 andl(tmp5, (32 - 1)); // tail count (in chars) 10966 andl(len, ~(32 - 1)); // vector count (in chars) 10967 jcc(Assembler::zero, copy_loop_tail); 10968 10969 lea(src, Address(src, len, Address::times_2)); 10970 lea(dst, Address(dst, len, Address::times_1)); 10971 negptr(len); 10972 10973 bind(copy_32_loop); 10974 evmovdquw(tmp1Reg, Address(src, len, Address::times_2), Assembler::AVX_512bit); 10975 evpcmpuw(k2, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit); 10976 kortestdl(k2, k2); 10977 jcc(Assembler::carryClear, restore_k1_return_zero); 10978 10979 // All elements in current processed chunk are valid candidates for 10980 // compression. Write a truncated byte elements to the memory. 10981 evpmovwb(Address(dst, len, Address::times_1), tmp1Reg, Assembler::AVX_512bit); 10982 addptr(len, 32); 10983 jcc(Assembler::notZero, copy_32_loop); 10984 10985 bind(copy_loop_tail); 10986 // bail out when there is nothing to be done 10987 testl(tmp5, 0xFFFFFFFF); 10988 // Restore k1 10989 kmovql(k1, k3); 10990 jcc(Assembler::zero, return_length); 10991 10992 movl(len, tmp5); 10993 10994 // ~(~0 << len), where len is the # of remaining elements to process 10995 movl(result, 0xFFFFFFFF); 10996 shlxl(result, result, len); 10997 notl(result); 10998 10999 kmovdl(k1, result); 11000 11001 evmovdquw(tmp1Reg, k1, Address(src, 0), Assembler::AVX_512bit); 11002 evpcmpuw(k2, k1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit); 11003 ktestd(k2, k1); 11004 jcc(Assembler::carryClear, restore_k1_return_zero); 11005 11006 evpmovwb(Address(dst, 0), k1, tmp1Reg, Assembler::AVX_512bit); 11007 // Restore k1 11008 kmovql(k1, k3); 11009 jmp(return_length); 11010 11011 bind(restore_k1_return_zero); 11012 // Restore k1 11013 kmovql(k1, k3); 11014 jmp(return_zero); 11015 11016 clear_vector_masking(); // closing of the stub context for programming mask registers 11017 } 11018 if (UseSSE42Intrinsics) { 11019 Label copy_32_loop, copy_16, copy_tail; 11020 11021 bind(below_threshold); 11022 11023 movl(result, len); 11024 11025 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vectors 11026 11027 // vectored compression 11028 andl(len, 0xfffffff0); // vector count (in chars) 11029 andl(result, 0x0000000f); // tail count (in chars) 11030 testl(len, len); 11031 jccb(Assembler::zero, copy_16); 11032 11033 // compress 16 chars per iter 11034 movdl(tmp1Reg, tmp5); 11035 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg 11036 pxor(tmp4Reg, tmp4Reg); 11037 11038 lea(src, Address(src, len, Address::times_2)); 11039 lea(dst, Address(dst, len, Address::times_1)); 11040 negptr(len); 11041 11042 bind(copy_32_loop); 11043 movdqu(tmp2Reg, Address(src, len, Address::times_2)); // load 1st 8 characters 11044 por(tmp4Reg, tmp2Reg); 11045 movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters 11046 por(tmp4Reg, tmp3Reg); 11047 ptest(tmp4Reg, tmp1Reg); // check for Unicode chars in next vector 11048 jcc(Assembler::notZero, return_zero); 11049 packuswb(tmp2Reg, tmp3Reg); // only ASCII chars; compress each to 1 byte 11050 movdqu(Address(dst, len, Address::times_1), tmp2Reg); 11051 addptr(len, 16); 11052 jcc(Assembler::notZero, copy_32_loop); 11053 11054 // compress next vector of 8 chars (if any) 11055 bind(copy_16); 11056 movl(len, result); 11057 andl(len, 0xfffffff8); // vector count (in chars) 11058 andl(result, 0x00000007); // tail count (in chars) 11059 testl(len, len); 11060 jccb(Assembler::zero, copy_tail); 11061 11062 movdl(tmp1Reg, tmp5); 11063 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg 11064 pxor(tmp3Reg, tmp3Reg); 11065 11066 movdqu(tmp2Reg, Address(src, 0)); 11067 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector 11068 jccb(Assembler::notZero, return_zero); 11069 packuswb(tmp2Reg, tmp3Reg); // only LATIN1 chars; compress each to 1 byte 11070 movq(Address(dst, 0), tmp2Reg); 11071 addptr(src, 16); 11072 addptr(dst, 8); 11073 11074 bind(copy_tail); 11075 movl(len, result); 11076 } 11077 // compress 1 char per iter 11078 testl(len, len); 11079 jccb(Assembler::zero, return_length); 11080 lea(src, Address(src, len, Address::times_2)); 11081 lea(dst, Address(dst, len, Address::times_1)); 11082 negptr(len); 11083 11084 bind(copy_chars_loop); 11085 load_unsigned_short(result, Address(src, len, Address::times_2)); 11086 testl(result, 0xff00); // check if Unicode char 11087 jccb(Assembler::notZero, return_zero); 11088 movb(Address(dst, len, Address::times_1), result); // ASCII char; compress to 1 byte 11089 increment(len); 11090 jcc(Assembler::notZero, copy_chars_loop); 11091 11092 // if compression succeeded, return length 11093 bind(return_length); 11094 pop(result); 11095 jmpb(done); 11096 11097 // if compression failed, return 0 11098 bind(return_zero); 11099 xorl(result, result); 11100 addptr(rsp, wordSize); 11101 11102 bind(done); 11103 } 11104 11105 // Inflate byte[] array to char[]. 11106 // ..\jdk\src\java.base\share\classes\java\lang\StringLatin1.java 11107 // @HotSpotIntrinsicCandidate 11108 // private static void inflate(byte[] src, int srcOff, char[] dst, int dstOff, int len) { 11109 // for (int i = 0; i < len; i++) { 11110 // dst[dstOff++] = (char)(src[srcOff++] & 0xff); 11111 // } 11112 // } 11113 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len, 11114 XMMRegister tmp1, Register tmp2) { 11115 Label copy_chars_loop, done, below_threshold; 11116 // rsi: src 11117 // rdi: dst 11118 // rdx: len 11119 // rcx: tmp2 11120 11121 // rsi holds start addr of source byte[] to be inflated 11122 // rdi holds start addr of destination char[] 11123 // rdx holds length 11124 assert_different_registers(src, dst, len, tmp2); 11125 11126 if ((UseAVX > 2) && // AVX512 11127 VM_Version::supports_avx512vlbw() && 11128 VM_Version::supports_bmi2()) { 11129 11130 set_vector_masking(); // opening of the stub context for programming mask registers 11131 11132 Label copy_32_loop, copy_tail; 11133 Register tmp3_aliased = len; 11134 11135 // if length of the string is less than 16, handle it in an old fashioned 11136 // way 11137 testl(len, -16); 11138 jcc(Assembler::zero, below_threshold); 11139 11140 // In order to use only one arithmetic operation for the main loop we use 11141 // this pre-calculation 11142 movl(tmp2, len); 11143 andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop 11144 andl(len, -32); // vector count 11145 jccb(Assembler::zero, copy_tail); 11146 11147 lea(src, Address(src, len, Address::times_1)); 11148 lea(dst, Address(dst, len, Address::times_2)); 11149 negptr(len); 11150 11151 11152 // inflate 32 chars per iter 11153 bind(copy_32_loop); 11154 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_512bit); 11155 evmovdquw(Address(dst, len, Address::times_2), tmp1, Assembler::AVX_512bit); 11156 addptr(len, 32); 11157 jcc(Assembler::notZero, copy_32_loop); 11158 11159 bind(copy_tail); 11160 // bail out when there is nothing to be done 11161 testl(tmp2, -1); // we don't destroy the contents of tmp2 here 11162 jcc(Assembler::zero, done); 11163 11164 // Save k1 11165 kmovql(k2, k1); 11166 11167 // ~(~0 << length), where length is the # of remaining elements to process 11168 movl(tmp3_aliased, -1); 11169 shlxl(tmp3_aliased, tmp3_aliased, tmp2); 11170 notl(tmp3_aliased); 11171 kmovdl(k1, tmp3_aliased); 11172 evpmovzxbw(tmp1, k1, Address(src, 0), Assembler::AVX_512bit); 11173 evmovdquw(Address(dst, 0), k1, tmp1, Assembler::AVX_512bit); 11174 11175 // Restore k1 11176 kmovql(k1, k2); 11177 jmp(done); 11178 11179 clear_vector_masking(); // closing of the stub context for programming mask registers 11180 } 11181 if (UseSSE42Intrinsics) { 11182 Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail; 11183 11184 movl(tmp2, len); 11185 11186 if (UseAVX > 1) { 11187 andl(tmp2, (16 - 1)); 11188 andl(len, -16); 11189 jccb(Assembler::zero, copy_new_tail); 11190 } else { 11191 andl(tmp2, 0x00000007); // tail count (in chars) 11192 andl(len, 0xfffffff8); // vector count (in chars) 11193 jccb(Assembler::zero, copy_tail); 11194 } 11195 11196 // vectored inflation 11197 lea(src, Address(src, len, Address::times_1)); 11198 lea(dst, Address(dst, len, Address::times_2)); 11199 negptr(len); 11200 11201 if (UseAVX > 1) { 11202 bind(copy_16_loop); 11203 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_256bit); 11204 vmovdqu(Address(dst, len, Address::times_2), tmp1); 11205 addptr(len, 16); 11206 jcc(Assembler::notZero, copy_16_loop); 11207 11208 bind(below_threshold); 11209 bind(copy_new_tail); 11210 if ((UseAVX > 2) && 11211 VM_Version::supports_avx512vlbw() && 11212 VM_Version::supports_bmi2()) { 11213 movl(tmp2, len); 11214 } else { 11215 movl(len, tmp2); 11216 } 11217 andl(tmp2, 0x00000007); 11218 andl(len, 0xFFFFFFF8); 11219 jccb(Assembler::zero, copy_tail); 11220 11221 pmovzxbw(tmp1, Address(src, 0)); 11222 movdqu(Address(dst, 0), tmp1); 11223 addptr(src, 8); 11224 addptr(dst, 2 * 8); 11225 11226 jmp(copy_tail, true); 11227 } 11228 11229 // inflate 8 chars per iter 11230 bind(copy_8_loop); 11231 pmovzxbw(tmp1, Address(src, len, Address::times_1)); // unpack to 8 words 11232 movdqu(Address(dst, len, Address::times_2), tmp1); 11233 addptr(len, 8); 11234 jcc(Assembler::notZero, copy_8_loop); 11235 11236 bind(copy_tail); 11237 movl(len, tmp2); 11238 11239 cmpl(len, 4); 11240 jccb(Assembler::less, copy_bytes); 11241 11242 movdl(tmp1, Address(src, 0)); // load 4 byte chars 11243 pmovzxbw(tmp1, tmp1); 11244 movq(Address(dst, 0), tmp1); 11245 subptr(len, 4); 11246 addptr(src, 4); 11247 addptr(dst, 8); 11248 11249 bind(copy_bytes); 11250 } 11251 testl(len, len); 11252 jccb(Assembler::zero, done); 11253 lea(src, Address(src, len, Address::times_1)); 11254 lea(dst, Address(dst, len, Address::times_2)); 11255 negptr(len); 11256 11257 // inflate 1 char per iter 11258 bind(copy_chars_loop); 11259 load_unsigned_byte(tmp2, Address(src, len, Address::times_1)); // load byte char 11260 movw(Address(dst, len, Address::times_2), tmp2); // inflate byte char to word 11261 increment(len); 11262 jcc(Assembler::notZero, copy_chars_loop); 11263 11264 bind(done); 11265 } 11266 11267 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) { 11268 switch (cond) { 11269 // Note some conditions are synonyms for others 11270 case Assembler::zero: return Assembler::notZero; 11271 case Assembler::notZero: return Assembler::zero; 11272 case Assembler::less: return Assembler::greaterEqual; 11273 case Assembler::lessEqual: return Assembler::greater; 11274 case Assembler::greater: return Assembler::lessEqual; 11275 case Assembler::greaterEqual: return Assembler::less; 11276 case Assembler::below: return Assembler::aboveEqual; 11277 case Assembler::belowEqual: return Assembler::above; 11278 case Assembler::above: return Assembler::belowEqual; 11279 case Assembler::aboveEqual: return Assembler::below; 11280 case Assembler::overflow: return Assembler::noOverflow; 11281 case Assembler::noOverflow: return Assembler::overflow; 11282 case Assembler::negative: return Assembler::positive; 11283 case Assembler::positive: return Assembler::negative; 11284 case Assembler::parity: return Assembler::noParity; 11285 case Assembler::noParity: return Assembler::parity; 11286 } 11287 ShouldNotReachHere(); return Assembler::overflow; 11288 } 11289 11290 SkipIfEqual::SkipIfEqual( 11291 MacroAssembler* masm, const bool* flag_addr, bool value) { 11292 _masm = masm; 11293 _masm->cmp8(ExternalAddress((address)flag_addr), value); 11294 _masm->jcc(Assembler::equal, _label); 11295 } 11296 11297 SkipIfEqual::~SkipIfEqual() { 11298 _masm->bind(_label); 11299 } 11300 11301 // 32-bit Windows has its own fast-path implementation 11302 // of get_thread 11303 #if !defined(WIN32) || defined(_LP64) 11304 11305 // This is simply a call to Thread::current() 11306 void MacroAssembler::get_thread(Register thread) { 11307 if (thread != rax) { 11308 push(rax); 11309 } 11310 LP64_ONLY(push(rdi);) 11311 LP64_ONLY(push(rsi);) 11312 push(rdx); 11313 push(rcx); 11314 #ifdef _LP64 11315 push(r8); 11316 push(r9); 11317 push(r10); 11318 push(r11); 11319 #endif 11320 11321 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0); 11322 11323 #ifdef _LP64 11324 pop(r11); 11325 pop(r10); 11326 pop(r9); 11327 pop(r8); 11328 #endif 11329 pop(rcx); 11330 pop(rdx); 11331 LP64_ONLY(pop(rsi);) 11332 LP64_ONLY(pop(rdi);) 11333 if (thread != rax) { 11334 mov(thread, rax); 11335 pop(rax); 11336 } 11337 } 11338 11339 #endif