1 //
2 // Copyright (c) 2003, 2018, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // AMD64 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when
64 // used as byte registers)
65
66 // Previously set RBX, RSI, and RDI as save-on-entry for java code
67 // Turn off SOE in java-code due to frequent use of uncommon-traps.
68 // Now that allocator is better, turn on RSI and RDI as SOE registers.
69
70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg());
71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next());
72
73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next());
75
76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next());
78
79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next());
81
82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg());
83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next());
84
85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code
86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg());
87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next());
88
89 #ifdef _WIN64
90
91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next());
93
94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next());
96
97 #else
98
99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg());
100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next());
101
102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg());
103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next());
104
105 #endif
106
107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg());
108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next());
109
110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg());
111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next());
112
113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg());
114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
115
116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg());
117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
118
119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg());
120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next());
121
122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg());
123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next());
124
125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg());
126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next());
127
128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg());
129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next());
130
131
132 // Floating Point Registers
133
134 // Specify priority of register selection within phases of register
135 // allocation. Highest priority is first. A useful heuristic is to
136 // give registers a low priority when they are required by machine
137 // instructions, like EAX and EDX on I486, and choose no-save registers
138 // before save-on-call, & save-on-call before save-on-entry. Registers
139 // which participate in fixed calling sequences should come last.
140 // Registers which are used as pairs must fall on an even boundary.
141
142 alloc_class chunk0(R10, R10_H,
143 R11, R11_H,
144 R8, R8_H,
145 R9, R9_H,
146 R12, R12_H,
147 RCX, RCX_H,
148 RBX, RBX_H,
149 RDI, RDI_H,
150 RDX, RDX_H,
151 RSI, RSI_H,
152 RAX, RAX_H,
153 RBP, RBP_H,
154 R13, R13_H,
155 R14, R14_H,
156 R15, R15_H,
157 RSP, RSP_H);
158
159
160 //----------Architecture Description Register Classes--------------------------
161 // Several register classes are automatically defined based upon information in
162 // this architecture description.
163 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
164 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
165 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
166 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
167 //
168
169 // Empty register class.
170 reg_class no_reg();
171
172 // Class for all pointer registers (including RSP and RBP)
173 reg_class any_reg_with_rbp(RAX, RAX_H,
174 RDX, RDX_H,
175 RBP, RBP_H,
176 RDI, RDI_H,
177 RSI, RSI_H,
178 RCX, RCX_H,
179 RBX, RBX_H,
180 RSP, RSP_H,
181 R8, R8_H,
182 R9, R9_H,
183 R10, R10_H,
184 R11, R11_H,
185 R12, R12_H,
186 R13, R13_H,
187 R14, R14_H,
188 R15, R15_H);
189
190 // Class for all pointer registers (including RSP, but excluding RBP)
191 reg_class any_reg_no_rbp(RAX, RAX_H,
192 RDX, RDX_H,
193 RDI, RDI_H,
194 RSI, RSI_H,
195 RCX, RCX_H,
196 RBX, RBX_H,
197 RSP, RSP_H,
198 R8, R8_H,
199 R9, R9_H,
200 R10, R10_H,
201 R11, R11_H,
202 R12, R12_H,
203 R13, R13_H,
204 R14, R14_H,
205 R15, R15_H);
206
207 // Dynamic register class that selects at runtime between register classes
208 // any_reg_no_rbp and any_reg_with_rbp (depending on the value of the flag PreserveFramePointer).
209 // Equivalent to: return PreserveFramePointer ? any_reg_no_rbp : any_reg_with_rbp;
210 reg_class_dynamic any_reg(any_reg_no_rbp, any_reg_with_rbp, %{ PreserveFramePointer %});
211
212 // Class for all pointer registers (excluding RSP)
213 reg_class ptr_reg_with_rbp(RAX, RAX_H,
214 RDX, RDX_H,
215 RBP, RBP_H,
216 RDI, RDI_H,
217 RSI, RSI_H,
218 RCX, RCX_H,
219 RBX, RBX_H,
220 R8, R8_H,
221 R9, R9_H,
222 R10, R10_H,
223 R11, R11_H,
224 R13, R13_H,
225 R14, R14_H);
226
227 // Class for all pointer registers (excluding RSP and RBP)
228 reg_class ptr_reg_no_rbp(RAX, RAX_H,
229 RDX, RDX_H,
230 RDI, RDI_H,
231 RSI, RSI_H,
232 RCX, RCX_H,
233 RBX, RBX_H,
234 R8, R8_H,
235 R9, R9_H,
236 R10, R10_H,
237 R11, R11_H,
238 R13, R13_H,
239 R14, R14_H);
240
241 // Dynamic register class that selects between ptr_reg_no_rbp and ptr_reg_with_rbp.
242 reg_class_dynamic ptr_reg(ptr_reg_no_rbp, ptr_reg_with_rbp, %{ PreserveFramePointer %});
243
244 // Class for all pointer registers (excluding RAX and RSP)
245 reg_class ptr_no_rax_reg_with_rbp(RDX, RDX_H,
246 RBP, RBP_H,
247 RDI, RDI_H,
248 RSI, RSI_H,
249 RCX, RCX_H,
250 RBX, RBX_H,
251 R8, R8_H,
252 R9, R9_H,
253 R10, R10_H,
254 R11, R11_H,
255 R13, R13_H,
256 R14, R14_H);
257
258 // Class for all pointer registers (excluding RAX, RSP, and RBP)
259 reg_class ptr_no_rax_reg_no_rbp(RDX, RDX_H,
260 RDI, RDI_H,
261 RSI, RSI_H,
262 RCX, RCX_H,
263 RBX, RBX_H,
264 R8, R8_H,
265 R9, R9_H,
266 R10, R10_H,
267 R11, R11_H,
268 R13, R13_H,
269 R14, R14_H);
270
271 // Dynamic register class that selects between ptr_no_rax_reg_no_rbp and ptr_no_rax_reg_with_rbp.
272 reg_class_dynamic ptr_no_rax_reg(ptr_no_rax_reg_no_rbp, ptr_no_rax_reg_with_rbp, %{ PreserveFramePointer %});
273
274 // Class for all pointer registers (excluding RAX, RBX, and RSP)
275 reg_class ptr_no_rax_rbx_reg_with_rbp(RDX, RDX_H,
276 RBP, RBP_H,
277 RDI, RDI_H,
278 RSI, RSI_H,
279 RCX, RCX_H,
280 R8, R8_H,
281 R9, R9_H,
282 R10, R10_H,
283 R11, R11_H,
284 R13, R13_H,
285 R14, R14_H);
286
287 // Class for all pointer registers (excluding RAX, RBX, RSP, and RBP)
288 reg_class ptr_no_rax_rbx_reg_no_rbp(RDX, RDX_H,
289 RDI, RDI_H,
290 RSI, RSI_H,
291 RCX, RCX_H,
292 R8, R8_H,
293 R9, R9_H,
294 R10, R10_H,
295 R11, R11_H,
296 R13, R13_H,
297 R14, R14_H);
298
299 // Dynamic register class that selects between ptr_no_rax_rbx_reg_no_rbp and ptr_no_rax_rbx_reg_with_rbp.
300 reg_class_dynamic ptr_no_rax_rbx_reg(ptr_no_rax_rbx_reg_no_rbp, ptr_no_rax_rbx_reg_with_rbp, %{ PreserveFramePointer %});
301
302 // Singleton class for RAX pointer register
303 reg_class ptr_rax_reg(RAX, RAX_H);
304
305 // Singleton class for RBX pointer register
306 reg_class ptr_rbx_reg(RBX, RBX_H);
307
308 // Singleton class for RSI pointer register
309 reg_class ptr_rsi_reg(RSI, RSI_H);
310
311 // Singleton class for RDI pointer register
312 reg_class ptr_rdi_reg(RDI, RDI_H);
313
314 // Singleton class for stack pointer
315 reg_class ptr_rsp_reg(RSP, RSP_H);
316
317 // Singleton class for TLS pointer
318 reg_class ptr_r15_reg(R15, R15_H);
319
320 // Class for all long registers (excluding RSP)
321 reg_class long_reg_with_rbp(RAX, RAX_H,
322 RDX, RDX_H,
323 RBP, RBP_H,
324 RDI, RDI_H,
325 RSI, RSI_H,
326 RCX, RCX_H,
327 RBX, RBX_H,
328 R8, R8_H,
329 R9, R9_H,
330 R10, R10_H,
331 R11, R11_H,
332 R13, R13_H,
333 R14, R14_H);
334
335 // Class for all long registers (excluding RSP and RBP)
336 reg_class long_reg_no_rbp(RAX, RAX_H,
337 RDX, RDX_H,
338 RDI, RDI_H,
339 RSI, RSI_H,
340 RCX, RCX_H,
341 RBX, RBX_H,
342 R8, R8_H,
343 R9, R9_H,
344 R10, R10_H,
345 R11, R11_H,
346 R13, R13_H,
347 R14, R14_H);
348
349 // Dynamic register class that selects between long_reg_no_rbp and long_reg_with_rbp.
350 reg_class_dynamic long_reg(long_reg_no_rbp, long_reg_with_rbp, %{ PreserveFramePointer %});
351
352 // Class for all long registers (excluding RAX, RDX and RSP)
353 reg_class long_no_rax_rdx_reg_with_rbp(RBP, RBP_H,
354 RDI, RDI_H,
355 RSI, RSI_H,
356 RCX, RCX_H,
357 RBX, RBX_H,
358 R8, R8_H,
359 R9, R9_H,
360 R10, R10_H,
361 R11, R11_H,
362 R13, R13_H,
363 R14, R14_H);
364
365 // Class for all long registers (excluding RAX, RDX, RSP, and RBP)
366 reg_class long_no_rax_rdx_reg_no_rbp(RDI, RDI_H,
367 RSI, RSI_H,
368 RCX, RCX_H,
369 RBX, RBX_H,
370 R8, R8_H,
371 R9, R9_H,
372 R10, R10_H,
373 R11, R11_H,
374 R13, R13_H,
375 R14, R14_H);
376
377 // Dynamic register class that selects between long_no_rax_rdx_reg_no_rbp and long_no_rax_rdx_reg_with_rbp.
378 reg_class_dynamic long_no_rax_rdx_reg(long_no_rax_rdx_reg_no_rbp, long_no_rax_rdx_reg_with_rbp, %{ PreserveFramePointer %});
379
380 // Class for all long registers (excluding RCX and RSP)
381 reg_class long_no_rcx_reg_with_rbp(RBP, RBP_H,
382 RDI, RDI_H,
383 RSI, RSI_H,
384 RAX, RAX_H,
385 RDX, RDX_H,
386 RBX, RBX_H,
387 R8, R8_H,
388 R9, R9_H,
389 R10, R10_H,
390 R11, R11_H,
391 R13, R13_H,
392 R14, R14_H);
393
394 // Class for all long registers (excluding RCX, RSP, and RBP)
395 reg_class long_no_rcx_reg_no_rbp(RDI, RDI_H,
396 RSI, RSI_H,
397 RAX, RAX_H,
398 RDX, RDX_H,
399 RBX, RBX_H,
400 R8, R8_H,
401 R9, R9_H,
402 R10, R10_H,
403 R11, R11_H,
404 R13, R13_H,
405 R14, R14_H);
406
407 // Dynamic register class that selects between long_no_rcx_reg_no_rbp and long_no_rcx_reg_with_rbp.
408 reg_class_dynamic long_no_rcx_reg(long_no_rcx_reg_no_rbp, long_no_rcx_reg_with_rbp, %{ PreserveFramePointer %});
409
410 // Singleton class for RAX long register
411 reg_class long_rax_reg(RAX, RAX_H);
412
413 // Singleton class for RCX long register
414 reg_class long_rcx_reg(RCX, RCX_H);
415
416 // Singleton class for RDX long register
417 reg_class long_rdx_reg(RDX, RDX_H);
418
419 // Class for all int registers (excluding RSP)
420 reg_class int_reg_with_rbp(RAX,
421 RDX,
422 RBP,
423 RDI,
424 RSI,
425 RCX,
426 RBX,
427 R8,
428 R9,
429 R10,
430 R11,
431 R13,
432 R14);
433
434 // Class for all int registers (excluding RSP and RBP)
435 reg_class int_reg_no_rbp(RAX,
436 RDX,
437 RDI,
438 RSI,
439 RCX,
440 RBX,
441 R8,
442 R9,
443 R10,
444 R11,
445 R13,
446 R14);
447
448 // Dynamic register class that selects between int_reg_no_rbp and int_reg_with_rbp.
449 reg_class_dynamic int_reg(int_reg_no_rbp, int_reg_with_rbp, %{ PreserveFramePointer %});
450
451 // Class for all int registers (excluding RCX and RSP)
452 reg_class int_no_rcx_reg_with_rbp(RAX,
453 RDX,
454 RBP,
455 RDI,
456 RSI,
457 RBX,
458 R8,
459 R9,
460 R10,
461 R11,
462 R13,
463 R14);
464
465 // Class for all int registers (excluding RCX, RSP, and RBP)
466 reg_class int_no_rcx_reg_no_rbp(RAX,
467 RDX,
468 RDI,
469 RSI,
470 RBX,
471 R8,
472 R9,
473 R10,
474 R11,
475 R13,
476 R14);
477
478 // Dynamic register class that selects between int_no_rcx_reg_no_rbp and int_no_rcx_reg_with_rbp.
479 reg_class_dynamic int_no_rcx_reg(int_no_rcx_reg_no_rbp, int_no_rcx_reg_with_rbp, %{ PreserveFramePointer %});
480
481 // Class for all int registers (excluding RAX, RDX, and RSP)
482 reg_class int_no_rax_rdx_reg_with_rbp(RBP,
483 RDI,
484 RSI,
485 RCX,
486 RBX,
487 R8,
488 R9,
489 R10,
490 R11,
491 R13,
492 R14);
493
494 // Class for all int registers (excluding RAX, RDX, RSP, and RBP)
495 reg_class int_no_rax_rdx_reg_no_rbp(RDI,
496 RSI,
497 RCX,
498 RBX,
499 R8,
500 R9,
501 R10,
502 R11,
503 R13,
504 R14);
505
506 // Dynamic register class that selects between int_no_rax_rdx_reg_no_rbp and int_no_rax_rdx_reg_with_rbp.
507 reg_class_dynamic int_no_rax_rdx_reg(int_no_rax_rdx_reg_no_rbp, int_no_rax_rdx_reg_with_rbp, %{ PreserveFramePointer %});
508
509 // Singleton class for RAX int register
510 reg_class int_rax_reg(RAX);
511
512 // Singleton class for RBX int register
513 reg_class int_rbx_reg(RBX);
514
515 // Singleton class for RCX int register
516 reg_class int_rcx_reg(RCX);
517
518 // Singleton class for RCX int register
519 reg_class int_rdx_reg(RDX);
520
521 // Singleton class for RCX int register
522 reg_class int_rdi_reg(RDI);
523
524 // Singleton class for instruction pointer
525 // reg_class ip_reg(RIP);
526
527 %}
528
529 source_hpp %{
530 #if INCLUDE_ZGC
531 #include "gc/z/zBarrierSetAssembler.hpp"
532 #endif
533 %}
534
535 //----------SOURCE BLOCK-------------------------------------------------------
536 // This is a block of C++ code which provides values, functions, and
537 // definitions necessary in the rest of the architecture description
538 source %{
539 #define RELOC_IMM64 Assembler::imm_operand
540 #define RELOC_DISP32 Assembler::disp32_operand
541
542 #define __ _masm.
543
544 static bool generate_vzeroupper(Compile* C) {
545 return (VM_Version::supports_vzeroupper() && (C->max_vector_size() > 16 || C->clear_upper_avx() == true)) ? true: false; // Generate vzeroupper
546 }
547
548 static int clear_avx_size() {
549 return generate_vzeroupper(Compile::current()) ? 3: 0; // vzeroupper
550 }
551
552 // !!!!! Special hack to get all types of calls to specify the byte offset
553 // from the start of the call to the point where the return address
554 // will point.
555 int MachCallStaticJavaNode::ret_addr_offset()
556 {
557 int offset = 5; // 5 bytes from start of call to where return address points
558 offset += clear_avx_size();
559 return offset;
560 }
561
562 int MachCallDynamicJavaNode::ret_addr_offset()
563 {
564 int offset = 15; // 15 bytes from start of call to where return address points
565 offset += clear_avx_size();
566 return offset;
567 }
568
569 int MachCallRuntimeNode::ret_addr_offset() {
570 int offset = 13; // movq r10,#addr; callq (r10)
571 offset += clear_avx_size();
572 return offset;
573 }
574
575 // Indicate if the safepoint node needs the polling page as an input,
576 // it does if the polling page is more than disp32 away.
577 bool SafePointNode::needs_polling_address_input()
578 {
579 return SafepointMechanism::uses_thread_local_poll() || Assembler::is_polling_page_far();
580 }
581
582 //
583 // Compute padding required for nodes which need alignment
584 //
585
586 // The address of the call instruction needs to be 4-byte aligned to
587 // ensure that it does not span a cache line so that it can be patched.
588 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
589 {
590 current_offset += clear_avx_size(); // skip vzeroupper
591 current_offset += 1; // skip call opcode byte
592 return align_up(current_offset, alignment_required()) - current_offset;
593 }
594
595 // The address of the call instruction needs to be 4-byte aligned to
596 // ensure that it does not span a cache line so that it can be patched.
597 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
598 {
599 current_offset += clear_avx_size(); // skip vzeroupper
600 current_offset += 11; // skip movq instruction + call opcode byte
601 return align_up(current_offset, alignment_required()) - current_offset;
602 }
603
604 // EMIT_RM()
605 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
606 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);
607 cbuf.insts()->emit_int8(c);
608 }
609
610 // EMIT_CC()
611 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
612 unsigned char c = (unsigned char) (f1 | f2);
613 cbuf.insts()->emit_int8(c);
614 }
615
616 // EMIT_OPCODE()
617 void emit_opcode(CodeBuffer &cbuf, int code) {
618 cbuf.insts()->emit_int8((unsigned char) code);
619 }
620
621 // EMIT_OPCODE() w/ relocation information
622 void emit_opcode(CodeBuffer &cbuf,
623 int code, relocInfo::relocType reloc, int offset, int format)
624 {
625 cbuf.relocate(cbuf.insts_mark() + offset, reloc, format);
626 emit_opcode(cbuf, code);
627 }
628
629 // EMIT_D8()
630 void emit_d8(CodeBuffer &cbuf, int d8) {
631 cbuf.insts()->emit_int8((unsigned char) d8);
632 }
633
634 // EMIT_D16()
635 void emit_d16(CodeBuffer &cbuf, int d16) {
636 cbuf.insts()->emit_int16(d16);
637 }
638
639 // EMIT_D32()
640 void emit_d32(CodeBuffer &cbuf, int d32) {
641 cbuf.insts()->emit_int32(d32);
642 }
643
644 // EMIT_D64()
645 void emit_d64(CodeBuffer &cbuf, int64_t d64) {
646 cbuf.insts()->emit_int64(d64);
647 }
648
649 // emit 32 bit value and construct relocation entry from relocInfo::relocType
650 void emit_d32_reloc(CodeBuffer& cbuf,
651 int d32,
652 relocInfo::relocType reloc,
653 int format)
654 {
655 assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc");
656 cbuf.relocate(cbuf.insts_mark(), reloc, format);
657 cbuf.insts()->emit_int32(d32);
658 }
659
660 // emit 32 bit value and construct relocation entry from RelocationHolder
661 void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) {
662 #ifdef ASSERT
663 if (rspec.reloc()->type() == relocInfo::oop_type &&
664 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) {
665 assert(Universe::heap()->is_in_reserved((address)(intptr_t)d32), "should be real oop");
666 assert(oopDesc::is_oop(cast_to_oop((intptr_t)d32)) && (ScavengeRootsInCode || !Universe::heap()->is_scavengable(cast_to_oop((intptr_t)d32))), "cannot embed scavengable oops in code");
667 }
668 #endif
669 cbuf.relocate(cbuf.insts_mark(), rspec, format);
670 cbuf.insts()->emit_int32(d32);
671 }
672
673 void emit_d32_reloc(CodeBuffer& cbuf, address addr) {
674 address next_ip = cbuf.insts_end() + 4;
675 emit_d32_reloc(cbuf, (int) (addr - next_ip),
676 external_word_Relocation::spec(addr),
677 RELOC_DISP32);
678 }
679
680
681 // emit 64 bit value and construct relocation entry from relocInfo::relocType
682 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, relocInfo::relocType reloc, int format) {
683 cbuf.relocate(cbuf.insts_mark(), reloc, format);
684 cbuf.insts()->emit_int64(d64);
685 }
686
687 // emit 64 bit value and construct relocation entry from RelocationHolder
688 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) {
689 #ifdef ASSERT
690 if (rspec.reloc()->type() == relocInfo::oop_type &&
691 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) {
692 assert(Universe::heap()->is_in_reserved((address)d64), "should be real oop");
693 assert(oopDesc::is_oop(cast_to_oop(d64)) && (ScavengeRootsInCode || !Universe::heap()->is_scavengable(cast_to_oop(d64))),
694 "cannot embed scavengable oops in code");
695 }
696 #endif
697 cbuf.relocate(cbuf.insts_mark(), rspec, format);
698 cbuf.insts()->emit_int64(d64);
699 }
700
701 // Access stack slot for load or store
702 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp)
703 {
704 emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src])
705 if (-0x80 <= disp && disp < 0x80) {
706 emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte
707 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
708 emit_d8(cbuf, disp); // Displacement // R/M byte
709 } else {
710 emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte
711 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
712 emit_d32(cbuf, disp); // Displacement // R/M byte
713 }
714 }
715
716 // rRegI ereg, memory mem) %{ // emit_reg_mem
717 void encode_RegMem(CodeBuffer &cbuf,
718 int reg,
719 int base, int index, int scale, int disp, relocInfo::relocType disp_reloc)
720 {
721 assert(disp_reloc == relocInfo::none, "cannot have disp");
722 int regenc = reg & 7;
723 int baseenc = base & 7;
724 int indexenc = index & 7;
725
726 // There is no index & no scale, use form without SIB byte
727 if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) {
728 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
729 if (disp == 0 && base != RBP_enc && base != R13_enc) {
730 emit_rm(cbuf, 0x0, regenc, baseenc); // *
731 } else if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
732 // If 8-bit displacement, mode 0x1
733 emit_rm(cbuf, 0x1, regenc, baseenc); // *
734 emit_d8(cbuf, disp);
735 } else {
736 // If 32-bit displacement
737 if (base == -1) { // Special flag for absolute address
738 emit_rm(cbuf, 0x0, regenc, 0x5); // *
739 if (disp_reloc != relocInfo::none) {
740 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
741 } else {
742 emit_d32(cbuf, disp);
743 }
744 } else {
745 // Normal base + offset
746 emit_rm(cbuf, 0x2, regenc, baseenc); // *
747 if (disp_reloc != relocInfo::none) {
748 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
749 } else {
750 emit_d32(cbuf, disp);
751 }
752 }
753 }
754 } else {
755 // Else, encode with the SIB byte
756 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
757 if (disp == 0 && base != RBP_enc && base != R13_enc) {
758 // If no displacement
759 emit_rm(cbuf, 0x0, regenc, 0x4); // *
760 emit_rm(cbuf, scale, indexenc, baseenc);
761 } else {
762 if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
763 // If 8-bit displacement, mode 0x1
764 emit_rm(cbuf, 0x1, regenc, 0x4); // *
765 emit_rm(cbuf, scale, indexenc, baseenc);
766 emit_d8(cbuf, disp);
767 } else {
768 // If 32-bit displacement
769 if (base == 0x04 ) {
770 emit_rm(cbuf, 0x2, regenc, 0x4);
771 emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid???
772 } else {
773 emit_rm(cbuf, 0x2, regenc, 0x4);
774 emit_rm(cbuf, scale, indexenc, baseenc); // *
775 }
776 if (disp_reloc != relocInfo::none) {
777 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
778 } else {
779 emit_d32(cbuf, disp);
780 }
781 }
782 }
783 }
784 }
785
786 // This could be in MacroAssembler but it's fairly C2 specific
787 void emit_cmpfp_fixup(MacroAssembler& _masm) {
788 Label exit;
789 __ jccb(Assembler::noParity, exit);
790 __ pushf();
791 //
792 // comiss/ucomiss instructions set ZF,PF,CF flags and
793 // zero OF,AF,SF for NaN values.
794 // Fixup flags by zeroing ZF,PF so that compare of NaN
795 // values returns 'less than' result (CF is set).
796 // Leave the rest of flags unchanged.
797 //
798 // 7 6 5 4 3 2 1 0
799 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
800 // 0 0 1 0 1 0 1 1 (0x2B)
801 //
802 __ andq(Address(rsp, 0), 0xffffff2b);
803 __ popf();
804 __ bind(exit);
805 }
806
807 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
808 Label done;
809 __ movl(dst, -1);
810 __ jcc(Assembler::parity, done);
811 __ jcc(Assembler::below, done);
812 __ setb(Assembler::notEqual, dst);
813 __ movzbl(dst, dst);
814 __ bind(done);
815 }
816
817
818 //=============================================================================
819 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
820
821 int Compile::ConstantTable::calculate_table_base_offset() const {
822 return 0; // absolute addressing, no offset
823 }
824
825 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
826 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
827 ShouldNotReachHere();
828 }
829
830 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
831 // Empty encoding
832 }
833
834 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
835 return 0;
836 }
837
838 #ifndef PRODUCT
839 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
840 st->print("# MachConstantBaseNode (empty encoding)");
841 }
842 #endif
843
844
845 //=============================================================================
846 #ifndef PRODUCT
847 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
848 Compile* C = ra_->C;
849
850 int framesize = C->frame_size_in_bytes();
851 int bangsize = C->bang_size_in_bytes();
852 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
853 // Remove wordSize for return addr which is already pushed.
854 framesize -= wordSize;
855
856 if (C->need_stack_bang(bangsize)) {
857 framesize -= wordSize;
858 st->print("# stack bang (%d bytes)", bangsize);
859 st->print("\n\t");
860 st->print("pushq rbp\t# Save rbp");
861 if (PreserveFramePointer) {
862 st->print("\n\t");
863 st->print("movq rbp, rsp\t# Save the caller's SP into rbp");
864 }
865 if (framesize) {
866 st->print("\n\t");
867 st->print("subq rsp, #%d\t# Create frame",framesize);
868 }
869 } else {
870 st->print("subq rsp, #%d\t# Create frame",framesize);
871 st->print("\n\t");
872 framesize -= wordSize;
873 st->print("movq [rsp + #%d], rbp\t# Save rbp",framesize);
874 if (PreserveFramePointer) {
875 st->print("\n\t");
876 st->print("movq rbp, rsp\t# Save the caller's SP into rbp");
877 if (framesize > 0) {
878 st->print("\n\t");
879 st->print("addq rbp, #%d", framesize);
880 }
881 }
882 }
883
884 if (VerifyStackAtCalls) {
885 st->print("\n\t");
886 framesize -= wordSize;
887 st->print("movq [rsp + #%d], 0xbadb100d\t# Majik cookie for stack depth check",framesize);
888 #ifdef ASSERT
889 st->print("\n\t");
890 st->print("# stack alignment check");
891 #endif
892 }
893 if (C->stub_function() != NULL && BarrierSet::barrier_set()->barrier_set_nmethod() != NULL) {
894 st->print("\n\t");
895 st->print("cmpl [r15_thread + #disarmed_offset], #disarmed_value\t");
896 st->print("\n\t");
897 st->print("je fast_entry\t");
898 st->print("\n\t");
899 st->print("call #nmethod_entry_barrier_stub\t");
900 st->print("\n\tfast_entry:");
901 }
902 st->cr();
903 }
904 #endif
905
906 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
907 Compile* C = ra_->C;
908 MacroAssembler _masm(&cbuf);
909
910 int framesize = C->frame_size_in_bytes();
911 int bangsize = C->bang_size_in_bytes();
912
913 __ verified_entry(framesize, C->need_stack_bang(bangsize)?bangsize:0, false, C->stub_function() != NULL);
914
915 C->set_frame_complete(cbuf.insts_size());
916
917 if (C->has_mach_constant_base_node()) {
918 // NOTE: We set the table base offset here because users might be
919 // emitted before MachConstantBaseNode.
920 Compile::ConstantTable& constant_table = C->constant_table();
921 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
922 }
923 }
924
925 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
926 {
927 return MachNode::size(ra_); // too many variables; just compute it
928 // the hard way
929 }
930
931 int MachPrologNode::reloc() const
932 {
933 return 0; // a large enough number
934 }
935
936 //=============================================================================
937 #ifndef PRODUCT
938 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const
939 {
940 Compile* C = ra_->C;
941 if (generate_vzeroupper(C)) {
942 st->print("vzeroupper");
943 st->cr(); st->print("\t");
944 }
945
946 int framesize = C->frame_size_in_bytes();
947 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
948 // Remove word for return adr already pushed
949 // and RBP
950 framesize -= 2*wordSize;
951
952 if (framesize) {
953 st->print_cr("addq rsp, %d\t# Destroy frame", framesize);
954 st->print("\t");
955 }
956
957 st->print_cr("popq rbp");
958 if (do_polling() && C->is_method_compilation()) {
959 st->print("\t");
960 if (SafepointMechanism::uses_thread_local_poll()) {
961 st->print_cr("movq rscratch1, poll_offset[r15_thread] #polling_page_address\n\t"
962 "testl rax, [rscratch1]\t"
963 "# Safepoint: poll for GC");
964 } else if (Assembler::is_polling_page_far()) {
965 st->print_cr("movq rscratch1, #polling_page_address\n\t"
966 "testl rax, [rscratch1]\t"
967 "# Safepoint: poll for GC");
968 } else {
969 st->print_cr("testl rax, [rip + #offset_to_poll_page]\t"
970 "# Safepoint: poll for GC");
971 }
972 }
973 }
974 #endif
975
976 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
977 {
978 Compile* C = ra_->C;
979 MacroAssembler _masm(&cbuf);
980
981 if (generate_vzeroupper(C)) {
982 // Clear upper bits of YMM registers when current compiled code uses
983 // wide vectors to avoid AVX <-> SSE transition penalty during call.
984 __ vzeroupper();
985 }
986
987 int framesize = C->frame_size_in_bytes();
988 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
989 // Remove word for return adr already pushed
990 // and RBP
991 framesize -= 2*wordSize;
992
993 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
994
995 if (framesize) {
996 emit_opcode(cbuf, Assembler::REX_W);
997 if (framesize < 0x80) {
998 emit_opcode(cbuf, 0x83); // addq rsp, #framesize
999 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
1000 emit_d8(cbuf, framesize);
1001 } else {
1002 emit_opcode(cbuf, 0x81); // addq rsp, #framesize
1003 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
1004 emit_d32(cbuf, framesize);
1005 }
1006 }
1007
1008 // popq rbp
1009 emit_opcode(cbuf, 0x58 | RBP_enc);
1010
1011 if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
1012 __ reserved_stack_check();
1013 }
1014
1015 if (do_polling() && C->is_method_compilation()) {
1016 MacroAssembler _masm(&cbuf);
1017 if (SafepointMechanism::uses_thread_local_poll()) {
1018 __ movq(rscratch1, Address(r15_thread, Thread::polling_page_offset()));
1019 __ relocate(relocInfo::poll_return_type);
1020 __ testl(rax, Address(rscratch1, 0));
1021 } else {
1022 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);
1023 if (Assembler::is_polling_page_far()) {
1024 __ lea(rscratch1, polling_page);
1025 __ relocate(relocInfo::poll_return_type);
1026 __ testl(rax, Address(rscratch1, 0));
1027 } else {
1028 __ testl(rax, polling_page);
1029 }
1030 }
1031 }
1032 }
1033
1034 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const
1035 {
1036 return MachNode::size(ra_); // too many variables; just compute it
1037 // the hard way
1038 }
1039
1040 int MachEpilogNode::reloc() const
1041 {
1042 return 2; // a large enough number
1043 }
1044
1045 const Pipeline* MachEpilogNode::pipeline() const
1046 {
1047 return MachNode::pipeline_class();
1048 }
1049
1050 int MachEpilogNode::safepoint_offset() const
1051 {
1052 return 0;
1053 }
1054
1055 //=============================================================================
1056
1057 enum RC {
1058 rc_bad,
1059 rc_int,
1060 rc_float,
1061 rc_stack
1062 };
1063
1064 static enum RC rc_class(OptoReg::Name reg)
1065 {
1066 if( !OptoReg::is_valid(reg) ) return rc_bad;
1067
1068 if (OptoReg::is_stack(reg)) return rc_stack;
1069
1070 VMReg r = OptoReg::as_VMReg(reg);
1071
1072 if (r->is_Register()) return rc_int;
1073
1074 assert(r->is_XMMRegister(), "must be");
1075 return rc_float;
1076 }
1077
1078 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
1079 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
1080 int src_hi, int dst_hi, uint ireg, outputStream* st);
1081
1082 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
1083 int stack_offset, int reg, uint ireg, outputStream* st);
1084
1085 static void vec_stack_to_stack_helper(CodeBuffer *cbuf, int src_offset,
1086 int dst_offset, uint ireg, outputStream* st) {
1087 if (cbuf) {
1088 MacroAssembler _masm(cbuf);
1089 switch (ireg) {
1090 case Op_VecS:
1091 __ movq(Address(rsp, -8), rax);
1092 __ movl(rax, Address(rsp, src_offset));
1093 __ movl(Address(rsp, dst_offset), rax);
1094 __ movq(rax, Address(rsp, -8));
1095 break;
1096 case Op_VecD:
1097 __ pushq(Address(rsp, src_offset));
1098 __ popq (Address(rsp, dst_offset));
1099 break;
1100 case Op_VecX:
1101 __ pushq(Address(rsp, src_offset));
1102 __ popq (Address(rsp, dst_offset));
1103 __ pushq(Address(rsp, src_offset+8));
1104 __ popq (Address(rsp, dst_offset+8));
1105 break;
1106 case Op_VecY:
1107 __ vmovdqu(Address(rsp, -32), xmm0);
1108 __ vmovdqu(xmm0, Address(rsp, src_offset));
1109 __ vmovdqu(Address(rsp, dst_offset), xmm0);
1110 __ vmovdqu(xmm0, Address(rsp, -32));
1111 break;
1112 case Op_VecZ:
1113 __ evmovdquq(Address(rsp, -64), xmm0, 2);
1114 __ evmovdquq(xmm0, Address(rsp, src_offset), 2);
1115 __ evmovdquq(Address(rsp, dst_offset), xmm0, 2);
1116 __ evmovdquq(xmm0, Address(rsp, -64), 2);
1117 break;
1118 default:
1119 ShouldNotReachHere();
1120 }
1121 #ifndef PRODUCT
1122 } else {
1123 switch (ireg) {
1124 case Op_VecS:
1125 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1126 "movl rax, [rsp + #%d]\n\t"
1127 "movl [rsp + #%d], rax\n\t"
1128 "movq rax, [rsp - #8]",
1129 src_offset, dst_offset);
1130 break;
1131 case Op_VecD:
1132 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1133 "popq [rsp + #%d]",
1134 src_offset, dst_offset);
1135 break;
1136 case Op_VecX:
1137 st->print("pushq [rsp + #%d]\t# 128-bit mem-mem spill\n\t"
1138 "popq [rsp + #%d]\n\t"
1139 "pushq [rsp + #%d]\n\t"
1140 "popq [rsp + #%d]",
1141 src_offset, dst_offset, src_offset+8, dst_offset+8);
1142 break;
1143 case Op_VecY:
1144 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
1145 "vmovdqu xmm0, [rsp + #%d]\n\t"
1146 "vmovdqu [rsp + #%d], xmm0\n\t"
1147 "vmovdqu xmm0, [rsp - #32]",
1148 src_offset, dst_offset);
1149 break;
1150 case Op_VecZ:
1151 st->print("vmovdqu [rsp - #64], xmm0\t# 512-bit mem-mem spill\n\t"
1152 "vmovdqu xmm0, [rsp + #%d]\n\t"
1153 "vmovdqu [rsp + #%d], xmm0\n\t"
1154 "vmovdqu xmm0, [rsp - #64]",
1155 src_offset, dst_offset);
1156 break;
1157 default:
1158 ShouldNotReachHere();
1159 }
1160 #endif
1161 }
1162 }
1163
1164 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf,
1165 PhaseRegAlloc* ra_,
1166 bool do_size,
1167 outputStream* st) const {
1168 assert(cbuf != NULL || st != NULL, "sanity");
1169 // Get registers to move
1170 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1171 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1172 OptoReg::Name dst_second = ra_->get_reg_second(this);
1173 OptoReg::Name dst_first = ra_->get_reg_first(this);
1174
1175 enum RC src_second_rc = rc_class(src_second);
1176 enum RC src_first_rc = rc_class(src_first);
1177 enum RC dst_second_rc = rc_class(dst_second);
1178 enum RC dst_first_rc = rc_class(dst_first);
1179
1180 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first),
1181 "must move at least 1 register" );
1182
1183 if (src_first == dst_first && src_second == dst_second) {
1184 // Self copy, no move
1185 return 0;
1186 }
1187 if (bottom_type()->isa_vect() != NULL) {
1188 uint ireg = ideal_reg();
1189 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
1190 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY || ireg == Op_VecZ ), "sanity");
1191 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1192 // mem -> mem
1193 int src_offset = ra_->reg2offset(src_first);
1194 int dst_offset = ra_->reg2offset(dst_first);
1195 vec_stack_to_stack_helper(cbuf, src_offset, dst_offset, ireg, st);
1196 } else if (src_first_rc == rc_float && dst_first_rc == rc_float ) {
1197 vec_mov_helper(cbuf, false, src_first, dst_first, src_second, dst_second, ireg, st);
1198 } else if (src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1199 int stack_offset = ra_->reg2offset(dst_first);
1200 vec_spill_helper(cbuf, false, false, stack_offset, src_first, ireg, st);
1201 } else if (src_first_rc == rc_stack && dst_first_rc == rc_float ) {
1202 int stack_offset = ra_->reg2offset(src_first);
1203 vec_spill_helper(cbuf, false, true, stack_offset, dst_first, ireg, st);
1204 } else {
1205 ShouldNotReachHere();
1206 }
1207 return 0;
1208 }
1209 if (src_first_rc == rc_stack) {
1210 // mem ->
1211 if (dst_first_rc == rc_stack) {
1212 // mem -> mem
1213 assert(src_second != dst_first, "overlap");
1214 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1215 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1216 // 64-bit
1217 int src_offset = ra_->reg2offset(src_first);
1218 int dst_offset = ra_->reg2offset(dst_first);
1219 if (cbuf) {
1220 MacroAssembler _masm(cbuf);
1221 __ pushq(Address(rsp, src_offset));
1222 __ popq (Address(rsp, dst_offset));
1223 #ifndef PRODUCT
1224 } else {
1225 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1226 "popq [rsp + #%d]",
1227 src_offset, dst_offset);
1228 #endif
1229 }
1230 } else {
1231 // 32-bit
1232 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1233 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1234 // No pushl/popl, so:
1235 int src_offset = ra_->reg2offset(src_first);
1236 int dst_offset = ra_->reg2offset(dst_first);
1237 if (cbuf) {
1238 MacroAssembler _masm(cbuf);
1239 __ movq(Address(rsp, -8), rax);
1240 __ movl(rax, Address(rsp, src_offset));
1241 __ movl(Address(rsp, dst_offset), rax);
1242 __ movq(rax, Address(rsp, -8));
1243 #ifndef PRODUCT
1244 } else {
1245 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1246 "movl rax, [rsp + #%d]\n\t"
1247 "movl [rsp + #%d], rax\n\t"
1248 "movq rax, [rsp - #8]",
1249 src_offset, dst_offset);
1250 #endif
1251 }
1252 }
1253 return 0;
1254 } else if (dst_first_rc == rc_int) {
1255 // mem -> gpr
1256 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1257 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1258 // 64-bit
1259 int offset = ra_->reg2offset(src_first);
1260 if (cbuf) {
1261 MacroAssembler _masm(cbuf);
1262 __ movq(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1263 #ifndef PRODUCT
1264 } else {
1265 st->print("movq %s, [rsp + #%d]\t# spill",
1266 Matcher::regName[dst_first],
1267 offset);
1268 #endif
1269 }
1270 } else {
1271 // 32-bit
1272 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1273 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1274 int offset = ra_->reg2offset(src_first);
1275 if (cbuf) {
1276 MacroAssembler _masm(cbuf);
1277 __ movl(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1278 #ifndef PRODUCT
1279 } else {
1280 st->print("movl %s, [rsp + #%d]\t# spill",
1281 Matcher::regName[dst_first],
1282 offset);
1283 #endif
1284 }
1285 }
1286 return 0;
1287 } else if (dst_first_rc == rc_float) {
1288 // mem-> xmm
1289 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1290 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1291 // 64-bit
1292 int offset = ra_->reg2offset(src_first);
1293 if (cbuf) {
1294 MacroAssembler _masm(cbuf);
1295 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1296 #ifndef PRODUCT
1297 } else {
1298 st->print("%s %s, [rsp + #%d]\t# spill",
1299 UseXmmLoadAndClearUpper ? "movsd " : "movlpd",
1300 Matcher::regName[dst_first],
1301 offset);
1302 #endif
1303 }
1304 } else {
1305 // 32-bit
1306 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1307 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1308 int offset = ra_->reg2offset(src_first);
1309 if (cbuf) {
1310 MacroAssembler _masm(cbuf);
1311 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1312 #ifndef PRODUCT
1313 } else {
1314 st->print("movss %s, [rsp + #%d]\t# spill",
1315 Matcher::regName[dst_first],
1316 offset);
1317 #endif
1318 }
1319 }
1320 return 0;
1321 }
1322 } else if (src_first_rc == rc_int) {
1323 // gpr ->
1324 if (dst_first_rc == rc_stack) {
1325 // gpr -> mem
1326 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1327 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1328 // 64-bit
1329 int offset = ra_->reg2offset(dst_first);
1330 if (cbuf) {
1331 MacroAssembler _masm(cbuf);
1332 __ movq(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1333 #ifndef PRODUCT
1334 } else {
1335 st->print("movq [rsp + #%d], %s\t# spill",
1336 offset,
1337 Matcher::regName[src_first]);
1338 #endif
1339 }
1340 } else {
1341 // 32-bit
1342 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1343 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1344 int offset = ra_->reg2offset(dst_first);
1345 if (cbuf) {
1346 MacroAssembler _masm(cbuf);
1347 __ movl(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1348 #ifndef PRODUCT
1349 } else {
1350 st->print("movl [rsp + #%d], %s\t# spill",
1351 offset,
1352 Matcher::regName[src_first]);
1353 #endif
1354 }
1355 }
1356 return 0;
1357 } else if (dst_first_rc == rc_int) {
1358 // gpr -> gpr
1359 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1360 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1361 // 64-bit
1362 if (cbuf) {
1363 MacroAssembler _masm(cbuf);
1364 __ movq(as_Register(Matcher::_regEncode[dst_first]),
1365 as_Register(Matcher::_regEncode[src_first]));
1366 #ifndef PRODUCT
1367 } else {
1368 st->print("movq %s, %s\t# spill",
1369 Matcher::regName[dst_first],
1370 Matcher::regName[src_first]);
1371 #endif
1372 }
1373 return 0;
1374 } else {
1375 // 32-bit
1376 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1377 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1378 if (cbuf) {
1379 MacroAssembler _masm(cbuf);
1380 __ movl(as_Register(Matcher::_regEncode[dst_first]),
1381 as_Register(Matcher::_regEncode[src_first]));
1382 #ifndef PRODUCT
1383 } else {
1384 st->print("movl %s, %s\t# spill",
1385 Matcher::regName[dst_first],
1386 Matcher::regName[src_first]);
1387 #endif
1388 }
1389 return 0;
1390 }
1391 } else if (dst_first_rc == rc_float) {
1392 // gpr -> xmm
1393 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1394 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1395 // 64-bit
1396 if (cbuf) {
1397 MacroAssembler _masm(cbuf);
1398 __ movdq( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1399 #ifndef PRODUCT
1400 } else {
1401 st->print("movdq %s, %s\t# spill",
1402 Matcher::regName[dst_first],
1403 Matcher::regName[src_first]);
1404 #endif
1405 }
1406 } else {
1407 // 32-bit
1408 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1409 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1410 if (cbuf) {
1411 MacroAssembler _masm(cbuf);
1412 __ movdl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1413 #ifndef PRODUCT
1414 } else {
1415 st->print("movdl %s, %s\t# spill",
1416 Matcher::regName[dst_first],
1417 Matcher::regName[src_first]);
1418 #endif
1419 }
1420 }
1421 return 0;
1422 }
1423 } else if (src_first_rc == rc_float) {
1424 // xmm ->
1425 if (dst_first_rc == rc_stack) {
1426 // xmm -> mem
1427 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1428 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1429 // 64-bit
1430 int offset = ra_->reg2offset(dst_first);
1431 if (cbuf) {
1432 MacroAssembler _masm(cbuf);
1433 __ movdbl( Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1434 #ifndef PRODUCT
1435 } else {
1436 st->print("movsd [rsp + #%d], %s\t# spill",
1437 offset,
1438 Matcher::regName[src_first]);
1439 #endif
1440 }
1441 } else {
1442 // 32-bit
1443 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1444 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1445 int offset = ra_->reg2offset(dst_first);
1446 if (cbuf) {
1447 MacroAssembler _masm(cbuf);
1448 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1449 #ifndef PRODUCT
1450 } else {
1451 st->print("movss [rsp + #%d], %s\t# spill",
1452 offset,
1453 Matcher::regName[src_first]);
1454 #endif
1455 }
1456 }
1457 return 0;
1458 } else if (dst_first_rc == rc_int) {
1459 // xmm -> gpr
1460 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1461 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1462 // 64-bit
1463 if (cbuf) {
1464 MacroAssembler _masm(cbuf);
1465 __ movdq( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1466 #ifndef PRODUCT
1467 } else {
1468 st->print("movdq %s, %s\t# spill",
1469 Matcher::regName[dst_first],
1470 Matcher::regName[src_first]);
1471 #endif
1472 }
1473 } else {
1474 // 32-bit
1475 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1476 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1477 if (cbuf) {
1478 MacroAssembler _masm(cbuf);
1479 __ movdl( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1480 #ifndef PRODUCT
1481 } else {
1482 st->print("movdl %s, %s\t# spill",
1483 Matcher::regName[dst_first],
1484 Matcher::regName[src_first]);
1485 #endif
1486 }
1487 }
1488 return 0;
1489 } else if (dst_first_rc == rc_float) {
1490 // xmm -> xmm
1491 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1492 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1493 // 64-bit
1494 if (cbuf) {
1495 MacroAssembler _masm(cbuf);
1496 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1497 #ifndef PRODUCT
1498 } else {
1499 st->print("%s %s, %s\t# spill",
1500 UseXmmRegToRegMoveAll ? "movapd" : "movsd ",
1501 Matcher::regName[dst_first],
1502 Matcher::regName[src_first]);
1503 #endif
1504 }
1505 } else {
1506 // 32-bit
1507 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1508 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1509 if (cbuf) {
1510 MacroAssembler _masm(cbuf);
1511 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1512 #ifndef PRODUCT
1513 } else {
1514 st->print("%s %s, %s\t# spill",
1515 UseXmmRegToRegMoveAll ? "movaps" : "movss ",
1516 Matcher::regName[dst_first],
1517 Matcher::regName[src_first]);
1518 #endif
1519 }
1520 }
1521 return 0;
1522 }
1523 }
1524
1525 assert(0," foo ");
1526 Unimplemented();
1527 return 0;
1528 }
1529
1530 #ifndef PRODUCT
1531 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1532 implementation(NULL, ra_, false, st);
1533 }
1534 #endif
1535
1536 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1537 implementation(&cbuf, ra_, false, NULL);
1538 }
1539
1540 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1541 return MachNode::size(ra_);
1542 }
1543
1544 //=============================================================================
1545 #ifndef PRODUCT
1546 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1547 {
1548 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1549 int reg = ra_->get_reg_first(this);
1550 st->print("leaq %s, [rsp + #%d]\t# box lock",
1551 Matcher::regName[reg], offset);
1552 }
1553 #endif
1554
1555 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1556 {
1557 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1558 int reg = ra_->get_encode(this);
1559 if (offset >= 0x80) {
1560 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1561 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1562 emit_rm(cbuf, 0x2, reg & 7, 0x04);
1563 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1564 emit_d32(cbuf, offset);
1565 } else {
1566 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1567 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1568 emit_rm(cbuf, 0x1, reg & 7, 0x04);
1569 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1570 emit_d8(cbuf, offset);
1571 }
1572 }
1573
1574 uint BoxLockNode::size(PhaseRegAlloc *ra_) const
1575 {
1576 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1577 return (offset < 0x80) ? 5 : 8; // REX
1578 }
1579
1580 //=============================================================================
1581 #ifndef PRODUCT
1582 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1583 {
1584 if (UseCompressedClassPointers) {
1585 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1586 st->print_cr("\tdecode_klass_not_null rscratch1, rscratch1");
1587 st->print_cr("\tcmpq rax, rscratch1\t # Inline cache check");
1588 } else {
1589 st->print_cr("\tcmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t"
1590 "# Inline cache check");
1591 }
1592 st->print_cr("\tjne SharedRuntime::_ic_miss_stub");
1593 st->print_cr("\tnop\t# nops to align entry point");
1594 }
1595 #endif
1596
1597 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1598 {
1599 MacroAssembler masm(&cbuf);
1600 uint insts_size = cbuf.insts_size();
1601 if (UseCompressedClassPointers) {
1602 masm.load_klass(rscratch1, j_rarg0);
1603 masm.cmpptr(rax, rscratch1);
1604 } else {
1605 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes()));
1606 }
1607
1608 masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1609
1610 /* WARNING these NOPs are critical so that verified entry point is properly
1611 4 bytes aligned for patching by NativeJump::patch_verified_entry() */
1612 int nops_cnt = 4 - ((cbuf.insts_size() - insts_size) & 0x3);
1613 if (OptoBreakpoint) {
1614 // Leave space for int3
1615 nops_cnt -= 1;
1616 }
1617 nops_cnt &= 0x3; // Do not add nops if code is aligned.
1618 if (nops_cnt > 0)
1619 masm.nop(nops_cnt);
1620 }
1621
1622 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
1623 {
1624 return MachNode::size(ra_); // too many variables; just compute it
1625 // the hard way
1626 }
1627
1628
1629 //=============================================================================
1630
1631 int Matcher::regnum_to_fpu_offset(int regnum)
1632 {
1633 return regnum - 32; // The FP registers are in the second chunk
1634 }
1635
1636 // This is UltraSparc specific, true just means we have fast l2f conversion
1637 const bool Matcher::convL2FSupported(void) {
1638 return true;
1639 }
1640
1641 // Is this branch offset short enough that a short branch can be used?
1642 //
1643 // NOTE: If the platform does not provide any short branch variants, then
1644 // this method should return false for offset 0.
1645 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1646 // The passed offset is relative to address of the branch.
1647 // On 86 a branch displacement is calculated relative to address
1648 // of a next instruction.
1649 offset -= br_size;
1650
1651 // the short version of jmpConUCF2 contains multiple branches,
1652 // making the reach slightly less
1653 if (rule == jmpConUCF2_rule)
1654 return (-126 <= offset && offset <= 125);
1655 return (-128 <= offset && offset <= 127);
1656 }
1657
1658 const bool Matcher::isSimpleConstant64(jlong value) {
1659 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1660 //return value == (int) value; // Cf. storeImmL and immL32.
1661
1662 // Probably always true, even if a temp register is required.
1663 return true;
1664 }
1665
1666 // The ecx parameter to rep stosq for the ClearArray node is in words.
1667 const bool Matcher::init_array_count_is_in_bytes = false;
1668
1669 // No additional cost for CMOVL.
1670 const int Matcher::long_cmove_cost() { return 0; }
1671
1672 // No CMOVF/CMOVD with SSE2
1673 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
1674
1675 // Does the CPU require late expand (see block.cpp for description of late expand)?
1676 const bool Matcher::require_postalloc_expand = false;
1677
1678 // Do we need to mask the count passed to shift instructions or does
1679 // the cpu only look at the lower 5/6 bits anyway?
1680 const bool Matcher::need_masked_shift_count = false;
1681
1682 bool Matcher::narrow_oop_use_complex_address() {
1683 assert(UseCompressedOops, "only for compressed oops code");
1684 return (LogMinObjAlignmentInBytes <= 3);
1685 }
1686
1687 bool Matcher::narrow_klass_use_complex_address() {
1688 assert(UseCompressedClassPointers, "only for compressed klass code");
1689 return (LogKlassAlignmentInBytes <= 3);
1690 }
1691
1692 bool Matcher::const_oop_prefer_decode() {
1693 // Prefer ConN+DecodeN over ConP.
1694 return true;
1695 }
1696
1697 bool Matcher::const_klass_prefer_decode() {
1698 // TODO: Either support matching DecodeNKlass (heap-based) in operand
1699 // or condisider the following:
1700 // Prefer ConNKlass+DecodeNKlass over ConP in simple compressed klass mode.
1701 //return Universe::narrow_klass_base() == NULL;
1702 return true;
1703 }
1704
1705 // Is it better to copy float constants, or load them directly from
1706 // memory? Intel can load a float constant from a direct address,
1707 // requiring no extra registers. Most RISCs will have to materialize
1708 // an address into a register first, so they would do better to copy
1709 // the constant from stack.
1710 const bool Matcher::rematerialize_float_constants = true; // XXX
1711
1712 // If CPU can load and store mis-aligned doubles directly then no
1713 // fixup is needed. Else we split the double into 2 integer pieces
1714 // and move it piece-by-piece. Only happens when passing doubles into
1715 // C code as the Java calling convention forces doubles to be aligned.
1716 const bool Matcher::misaligned_doubles_ok = true;
1717
1718 // No-op on amd64
1719 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {}
1720
1721 // Advertise here if the CPU requires explicit rounding operations to
1722 // implement the UseStrictFP mode.
1723 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1724
1725 // Are floats conerted to double when stored to stack during deoptimization?
1726 // On x64 it is stored without convertion so we can use normal access.
1727 bool Matcher::float_in_double() { return false; }
1728
1729 // Do ints take an entire long register or just half?
1730 const bool Matcher::int_in_long = true;
1731
1732 // Return whether or not this register is ever used as an argument.
1733 // This function is used on startup to build the trampoline stubs in
1734 // generateOptoStub. Registers not mentioned will be killed by the VM
1735 // call in the trampoline, and arguments in those registers not be
1736 // available to the callee.
1737 bool Matcher::can_be_java_arg(int reg)
1738 {
1739 return
1740 reg == RDI_num || reg == RDI_H_num ||
1741 reg == RSI_num || reg == RSI_H_num ||
1742 reg == RDX_num || reg == RDX_H_num ||
1743 reg == RCX_num || reg == RCX_H_num ||
1744 reg == R8_num || reg == R8_H_num ||
1745 reg == R9_num || reg == R9_H_num ||
1746 reg == R12_num || reg == R12_H_num ||
1747 reg == XMM0_num || reg == XMM0b_num ||
1748 reg == XMM1_num || reg == XMM1b_num ||
1749 reg == XMM2_num || reg == XMM2b_num ||
1750 reg == XMM3_num || reg == XMM3b_num ||
1751 reg == XMM4_num || reg == XMM4b_num ||
1752 reg == XMM5_num || reg == XMM5b_num ||
1753 reg == XMM6_num || reg == XMM6b_num ||
1754 reg == XMM7_num || reg == XMM7b_num;
1755 }
1756
1757 bool Matcher::is_spillable_arg(int reg)
1758 {
1759 return can_be_java_arg(reg);
1760 }
1761
1762 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1763 // In 64 bit mode a code which use multiply when
1764 // devisor is constant is faster than hardware
1765 // DIV instruction (it uses MulHiL).
1766 return false;
1767 }
1768
1769 // Register for DIVI projection of divmodI
1770 RegMask Matcher::divI_proj_mask() {
1771 return INT_RAX_REG_mask();
1772 }
1773
1774 // Register for MODI projection of divmodI
1775 RegMask Matcher::modI_proj_mask() {
1776 return INT_RDX_REG_mask();
1777 }
1778
1779 // Register for DIVL projection of divmodL
1780 RegMask Matcher::divL_proj_mask() {
1781 return LONG_RAX_REG_mask();
1782 }
1783
1784 // Register for MODL projection of divmodL
1785 RegMask Matcher::modL_proj_mask() {
1786 return LONG_RDX_REG_mask();
1787 }
1788
1789 // Register for saving SP into on method handle invokes. Not used on x86_64.
1790 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1791 return NO_REG_mask();
1792 }
1793
1794 %}
1795
1796 //----------ENCODING BLOCK-----------------------------------------------------
1797 // This block specifies the encoding classes used by the compiler to
1798 // output byte streams. Encoding classes are parameterized macros
1799 // used by Machine Instruction Nodes in order to generate the bit
1800 // encoding of the instruction. Operands specify their base encoding
1801 // interface with the interface keyword. There are currently
1802 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
1803 // COND_INTER. REG_INTER causes an operand to generate a function
1804 // which returns its register number when queried. CONST_INTER causes
1805 // an operand to generate a function which returns the value of the
1806 // constant when queried. MEMORY_INTER causes an operand to generate
1807 // four functions which return the Base Register, the Index Register,
1808 // the Scale Value, and the Offset Value of the operand when queried.
1809 // COND_INTER causes an operand to generate six functions which return
1810 // the encoding code (ie - encoding bits for the instruction)
1811 // associated with each basic boolean condition for a conditional
1812 // instruction.
1813 //
1814 // Instructions specify two basic values for encoding. Again, a
1815 // function is available to check if the constant displacement is an
1816 // oop. They use the ins_encode keyword to specify their encoding
1817 // classes (which must be a sequence of enc_class names, and their
1818 // parameters, specified in the encoding block), and they use the
1819 // opcode keyword to specify, in order, their primary, secondary, and
1820 // tertiary opcode. Only the opcode sections which a particular
1821 // instruction needs for encoding need to be specified.
1822 encode %{
1823 // Build emit functions for each basic byte or larger field in the
1824 // intel encoding scheme (opcode, rm, sib, immediate), and call them
1825 // from C++ code in the enc_class source block. Emit functions will
1826 // live in the main source block for now. In future, we can
1827 // generalize this by adding a syntax that specifies the sizes of
1828 // fields in an order, so that the adlc can build the emit functions
1829 // automagically
1830
1831 // Emit primary opcode
1832 enc_class OpcP
1833 %{
1834 emit_opcode(cbuf, $primary);
1835 %}
1836
1837 // Emit secondary opcode
1838 enc_class OpcS
1839 %{
1840 emit_opcode(cbuf, $secondary);
1841 %}
1842
1843 // Emit tertiary opcode
1844 enc_class OpcT
1845 %{
1846 emit_opcode(cbuf, $tertiary);
1847 %}
1848
1849 // Emit opcode directly
1850 enc_class Opcode(immI d8)
1851 %{
1852 emit_opcode(cbuf, $d8$$constant);
1853 %}
1854
1855 // Emit size prefix
1856 enc_class SizePrefix
1857 %{
1858 emit_opcode(cbuf, 0x66);
1859 %}
1860
1861 enc_class reg(rRegI reg)
1862 %{
1863 emit_rm(cbuf, 0x3, 0, $reg$$reg & 7);
1864 %}
1865
1866 enc_class reg_reg(rRegI dst, rRegI src)
1867 %{
1868 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1869 %}
1870
1871 enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src)
1872 %{
1873 emit_opcode(cbuf, $opcode$$constant);
1874 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1875 %}
1876
1877 enc_class cdql_enc(no_rax_rdx_RegI div)
1878 %{
1879 // Full implementation of Java idiv and irem; checks for
1880 // special case as described in JVM spec., p.243 & p.271.
1881 //
1882 // normal case special case
1883 //
1884 // input : rax: dividend min_int
1885 // reg: divisor -1
1886 //
1887 // output: rax: quotient (= rax idiv reg) min_int
1888 // rdx: remainder (= rax irem reg) 0
1889 //
1890 // Code sequnce:
1891 //
1892 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax
1893 // 5: 75 07/08 jne e <normal>
1894 // 7: 33 d2 xor %edx,%edx
1895 // [div >= 8 -> offset + 1]
1896 // [REX_B]
1897 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div
1898 // c: 74 03/04 je 11 <done>
1899 // 000000000000000e <normal>:
1900 // e: 99 cltd
1901 // [div >= 8 -> offset + 1]
1902 // [REX_B]
1903 // f: f7 f9 idiv $div
1904 // 0000000000000011 <done>:
1905
1906 // cmp $0x80000000,%eax
1907 emit_opcode(cbuf, 0x3d);
1908 emit_d8(cbuf, 0x00);
1909 emit_d8(cbuf, 0x00);
1910 emit_d8(cbuf, 0x00);
1911 emit_d8(cbuf, 0x80);
1912
1913 // jne e <normal>
1914 emit_opcode(cbuf, 0x75);
1915 emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08);
1916
1917 // xor %edx,%edx
1918 emit_opcode(cbuf, 0x33);
1919 emit_d8(cbuf, 0xD2);
1920
1921 // cmp $0xffffffffffffffff,%ecx
1922 if ($div$$reg >= 8) {
1923 emit_opcode(cbuf, Assembler::REX_B);
1924 }
1925 emit_opcode(cbuf, 0x83);
1926 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
1927 emit_d8(cbuf, 0xFF);
1928
1929 // je 11 <done>
1930 emit_opcode(cbuf, 0x74);
1931 emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04);
1932
1933 // <normal>
1934 // cltd
1935 emit_opcode(cbuf, 0x99);
1936
1937 // idivl (note: must be emitted by the user of this rule)
1938 // <done>
1939 %}
1940
1941 enc_class cdqq_enc(no_rax_rdx_RegL div)
1942 %{
1943 // Full implementation of Java ldiv and lrem; checks for
1944 // special case as described in JVM spec., p.243 & p.271.
1945 //
1946 // normal case special case
1947 //
1948 // input : rax: dividend min_long
1949 // reg: divisor -1
1950 //
1951 // output: rax: quotient (= rax idiv reg) min_long
1952 // rdx: remainder (= rax irem reg) 0
1953 //
1954 // Code sequnce:
1955 //
1956 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx
1957 // 7: 00 00 80
1958 // a: 48 39 d0 cmp %rdx,%rax
1959 // d: 75 08 jne 17 <normal>
1960 // f: 33 d2 xor %edx,%edx
1961 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div
1962 // 15: 74 05 je 1c <done>
1963 // 0000000000000017 <normal>:
1964 // 17: 48 99 cqto
1965 // 19: 48 f7 f9 idiv $div
1966 // 000000000000001c <done>:
1967
1968 // mov $0x8000000000000000,%rdx
1969 emit_opcode(cbuf, Assembler::REX_W);
1970 emit_opcode(cbuf, 0xBA);
1971 emit_d8(cbuf, 0x00);
1972 emit_d8(cbuf, 0x00);
1973 emit_d8(cbuf, 0x00);
1974 emit_d8(cbuf, 0x00);
1975 emit_d8(cbuf, 0x00);
1976 emit_d8(cbuf, 0x00);
1977 emit_d8(cbuf, 0x00);
1978 emit_d8(cbuf, 0x80);
1979
1980 // cmp %rdx,%rax
1981 emit_opcode(cbuf, Assembler::REX_W);
1982 emit_opcode(cbuf, 0x39);
1983 emit_d8(cbuf, 0xD0);
1984
1985 // jne 17 <normal>
1986 emit_opcode(cbuf, 0x75);
1987 emit_d8(cbuf, 0x08);
1988
1989 // xor %edx,%edx
1990 emit_opcode(cbuf, 0x33);
1991 emit_d8(cbuf, 0xD2);
1992
1993 // cmp $0xffffffffffffffff,$div
1994 emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB);
1995 emit_opcode(cbuf, 0x83);
1996 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
1997 emit_d8(cbuf, 0xFF);
1998
1999 // je 1e <done>
2000 emit_opcode(cbuf, 0x74);
2001 emit_d8(cbuf, 0x05);
2002
2003 // <normal>
2004 // cqto
2005 emit_opcode(cbuf, Assembler::REX_W);
2006 emit_opcode(cbuf, 0x99);
2007
2008 // idivq (note: must be emitted by the user of this rule)
2009 // <done>
2010 %}
2011
2012 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
2013 enc_class OpcSE(immI imm)
2014 %{
2015 // Emit primary opcode and set sign-extend bit
2016 // Check for 8-bit immediate, and set sign extend bit in opcode
2017 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2018 emit_opcode(cbuf, $primary | 0x02);
2019 } else {
2020 // 32-bit immediate
2021 emit_opcode(cbuf, $primary);
2022 }
2023 %}
2024
2025 enc_class OpcSErm(rRegI dst, immI imm)
2026 %{
2027 // OpcSEr/m
2028 int dstenc = $dst$$reg;
2029 if (dstenc >= 8) {
2030 emit_opcode(cbuf, Assembler::REX_B);
2031 dstenc -= 8;
2032 }
2033 // Emit primary opcode and set sign-extend bit
2034 // Check for 8-bit immediate, and set sign extend bit in opcode
2035 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2036 emit_opcode(cbuf, $primary | 0x02);
2037 } else {
2038 // 32-bit immediate
2039 emit_opcode(cbuf, $primary);
2040 }
2041 // Emit r/m byte with secondary opcode, after primary opcode.
2042 emit_rm(cbuf, 0x3, $secondary, dstenc);
2043 %}
2044
2045 enc_class OpcSErm_wide(rRegL dst, immI imm)
2046 %{
2047 // OpcSEr/m
2048 int dstenc = $dst$$reg;
2049 if (dstenc < 8) {
2050 emit_opcode(cbuf, Assembler::REX_W);
2051 } else {
2052 emit_opcode(cbuf, Assembler::REX_WB);
2053 dstenc -= 8;
2054 }
2055 // Emit primary opcode and set sign-extend bit
2056 // Check for 8-bit immediate, and set sign extend bit in opcode
2057 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2058 emit_opcode(cbuf, $primary | 0x02);
2059 } else {
2060 // 32-bit immediate
2061 emit_opcode(cbuf, $primary);
2062 }
2063 // Emit r/m byte with secondary opcode, after primary opcode.
2064 emit_rm(cbuf, 0x3, $secondary, dstenc);
2065 %}
2066
2067 enc_class Con8or32(immI imm)
2068 %{
2069 // Check for 8-bit immediate, and set sign extend bit in opcode
2070 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2071 $$$emit8$imm$$constant;
2072 } else {
2073 // 32-bit immediate
2074 $$$emit32$imm$$constant;
2075 }
2076 %}
2077
2078 enc_class opc2_reg(rRegI dst)
2079 %{
2080 // BSWAP
2081 emit_cc(cbuf, $secondary, $dst$$reg);
2082 %}
2083
2084 enc_class opc3_reg(rRegI dst)
2085 %{
2086 // BSWAP
2087 emit_cc(cbuf, $tertiary, $dst$$reg);
2088 %}
2089
2090 enc_class reg_opc(rRegI div)
2091 %{
2092 // INC, DEC, IDIV, IMOD, JMP indirect, ...
2093 emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7);
2094 %}
2095
2096 enc_class enc_cmov(cmpOp cop)
2097 %{
2098 // CMOV
2099 $$$emit8$primary;
2100 emit_cc(cbuf, $secondary, $cop$$cmpcode);
2101 %}
2102
2103 enc_class enc_PartialSubtypeCheck()
2104 %{
2105 Register Rrdi = as_Register(RDI_enc); // result register
2106 Register Rrax = as_Register(RAX_enc); // super class
2107 Register Rrcx = as_Register(RCX_enc); // killed
2108 Register Rrsi = as_Register(RSI_enc); // sub class
2109 Label miss;
2110 const bool set_cond_codes = true;
2111
2112 MacroAssembler _masm(&cbuf);
2113 __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi,
2114 NULL, &miss,
2115 /*set_cond_codes:*/ true);
2116 if ($primary) {
2117 __ xorptr(Rrdi, Rrdi);
2118 }
2119 __ bind(miss);
2120 %}
2121
2122 enc_class clear_avx %{
2123 debug_only(int off0 = cbuf.insts_size());
2124 if (generate_vzeroupper(Compile::current())) {
2125 // Clear upper bits of YMM registers to avoid AVX <-> SSE transition penalty
2126 // Clear upper bits of YMM registers when current compiled code uses
2127 // wide vectors to avoid AVX <-> SSE transition penalty during call.
2128 MacroAssembler _masm(&cbuf);
2129 __ vzeroupper();
2130 }
2131 debug_only(int off1 = cbuf.insts_size());
2132 assert(off1 - off0 == clear_avx_size(), "correct size prediction");
2133 %}
2134
2135 enc_class Java_To_Runtime(method meth) %{
2136 // No relocation needed
2137 MacroAssembler _masm(&cbuf);
2138 __ mov64(r10, (int64_t) $meth$$method);
2139 __ call(r10);
2140 %}
2141
2142 enc_class Java_To_Interpreter(method meth)
2143 %{
2144 // CALL Java_To_Interpreter
2145 // This is the instruction starting address for relocation info.
2146 cbuf.set_insts_mark();
2147 $$$emit8$primary;
2148 // CALL directly to the runtime
2149 emit_d32_reloc(cbuf,
2150 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2151 runtime_call_Relocation::spec(),
2152 RELOC_DISP32);
2153 %}
2154
2155 enc_class Java_Static_Call(method meth)
2156 %{
2157 // JAVA STATIC CALL
2158 // CALL to fixup routine. Fixup routine uses ScopeDesc info to
2159 // determine who we intended to call.
2160 cbuf.set_insts_mark();
2161 $$$emit8$primary;
2162
2163 if (!_method) {
2164 emit_d32_reloc(cbuf, (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2165 runtime_call_Relocation::spec(),
2166 RELOC_DISP32);
2167 } else {
2168 int method_index = resolved_method_index(cbuf);
2169 RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
2170 : static_call_Relocation::spec(method_index);
2171 emit_d32_reloc(cbuf, (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2172 rspec, RELOC_DISP32);
2173 // Emit stubs for static call.
2174 address mark = cbuf.insts_mark();
2175 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf, mark);
2176 if (stub == NULL) {
2177 ciEnv::current()->record_failure("CodeCache is full");
2178 return;
2179 }
2180 #if INCLUDE_AOT
2181 CompiledStaticCall::emit_to_aot_stub(cbuf, mark);
2182 #endif
2183 }
2184 %}
2185
2186 enc_class Java_Dynamic_Call(method meth) %{
2187 MacroAssembler _masm(&cbuf);
2188 __ ic_call((address)$meth$$method, resolved_method_index(cbuf));
2189 %}
2190
2191 enc_class Java_Compiled_Call(method meth)
2192 %{
2193 // JAVA COMPILED CALL
2194 int disp = in_bytes(Method:: from_compiled_offset());
2195
2196 // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!!
2197 // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small");
2198
2199 // callq *disp(%rax)
2200 cbuf.set_insts_mark();
2201 $$$emit8$primary;
2202 if (disp < 0x80) {
2203 emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte
2204 emit_d8(cbuf, disp); // Displacement
2205 } else {
2206 emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte
2207 emit_d32(cbuf, disp); // Displacement
2208 }
2209 %}
2210
2211 enc_class reg_opc_imm(rRegI dst, immI8 shift)
2212 %{
2213 // SAL, SAR, SHR
2214 int dstenc = $dst$$reg;
2215 if (dstenc >= 8) {
2216 emit_opcode(cbuf, Assembler::REX_B);
2217 dstenc -= 8;
2218 }
2219 $$$emit8$primary;
2220 emit_rm(cbuf, 0x3, $secondary, dstenc);
2221 $$$emit8$shift$$constant;
2222 %}
2223
2224 enc_class reg_opc_imm_wide(rRegL dst, immI8 shift)
2225 %{
2226 // SAL, SAR, SHR
2227 int dstenc = $dst$$reg;
2228 if (dstenc < 8) {
2229 emit_opcode(cbuf, Assembler::REX_W);
2230 } else {
2231 emit_opcode(cbuf, Assembler::REX_WB);
2232 dstenc -= 8;
2233 }
2234 $$$emit8$primary;
2235 emit_rm(cbuf, 0x3, $secondary, dstenc);
2236 $$$emit8$shift$$constant;
2237 %}
2238
2239 enc_class load_immI(rRegI dst, immI src)
2240 %{
2241 int dstenc = $dst$$reg;
2242 if (dstenc >= 8) {
2243 emit_opcode(cbuf, Assembler::REX_B);
2244 dstenc -= 8;
2245 }
2246 emit_opcode(cbuf, 0xB8 | dstenc);
2247 $$$emit32$src$$constant;
2248 %}
2249
2250 enc_class load_immL(rRegL dst, immL src)
2251 %{
2252 int dstenc = $dst$$reg;
2253 if (dstenc < 8) {
2254 emit_opcode(cbuf, Assembler::REX_W);
2255 } else {
2256 emit_opcode(cbuf, Assembler::REX_WB);
2257 dstenc -= 8;
2258 }
2259 emit_opcode(cbuf, 0xB8 | dstenc);
2260 emit_d64(cbuf, $src$$constant);
2261 %}
2262
2263 enc_class load_immUL32(rRegL dst, immUL32 src)
2264 %{
2265 // same as load_immI, but this time we care about zeroes in the high word
2266 int dstenc = $dst$$reg;
2267 if (dstenc >= 8) {
2268 emit_opcode(cbuf, Assembler::REX_B);
2269 dstenc -= 8;
2270 }
2271 emit_opcode(cbuf, 0xB8 | dstenc);
2272 $$$emit32$src$$constant;
2273 %}
2274
2275 enc_class load_immL32(rRegL dst, immL32 src)
2276 %{
2277 int dstenc = $dst$$reg;
2278 if (dstenc < 8) {
2279 emit_opcode(cbuf, Assembler::REX_W);
2280 } else {
2281 emit_opcode(cbuf, Assembler::REX_WB);
2282 dstenc -= 8;
2283 }
2284 emit_opcode(cbuf, 0xC7);
2285 emit_rm(cbuf, 0x03, 0x00, dstenc);
2286 $$$emit32$src$$constant;
2287 %}
2288
2289 enc_class load_immP31(rRegP dst, immP32 src)
2290 %{
2291 // same as load_immI, but this time we care about zeroes in the high word
2292 int dstenc = $dst$$reg;
2293 if (dstenc >= 8) {
2294 emit_opcode(cbuf, Assembler::REX_B);
2295 dstenc -= 8;
2296 }
2297 emit_opcode(cbuf, 0xB8 | dstenc);
2298 $$$emit32$src$$constant;
2299 %}
2300
2301 enc_class load_immP(rRegP dst, immP src)
2302 %{
2303 int dstenc = $dst$$reg;
2304 if (dstenc < 8) {
2305 emit_opcode(cbuf, Assembler::REX_W);
2306 } else {
2307 emit_opcode(cbuf, Assembler::REX_WB);
2308 dstenc -= 8;
2309 }
2310 emit_opcode(cbuf, 0xB8 | dstenc);
2311 // This next line should be generated from ADLC
2312 if ($src->constant_reloc() != relocInfo::none) {
2313 emit_d64_reloc(cbuf, $src$$constant, $src->constant_reloc(), RELOC_IMM64);
2314 } else {
2315 emit_d64(cbuf, $src$$constant);
2316 }
2317 %}
2318
2319 enc_class Con32(immI src)
2320 %{
2321 // Output immediate
2322 $$$emit32$src$$constant;
2323 %}
2324
2325 enc_class Con32F_as_bits(immF src)
2326 %{
2327 // Output Float immediate bits
2328 jfloat jf = $src$$constant;
2329 jint jf_as_bits = jint_cast(jf);
2330 emit_d32(cbuf, jf_as_bits);
2331 %}
2332
2333 enc_class Con16(immI src)
2334 %{
2335 // Output immediate
2336 $$$emit16$src$$constant;
2337 %}
2338
2339 // How is this different from Con32??? XXX
2340 enc_class Con_d32(immI src)
2341 %{
2342 emit_d32(cbuf,$src$$constant);
2343 %}
2344
2345 enc_class conmemref (rRegP t1) %{ // Con32(storeImmI)
2346 // Output immediate memory reference
2347 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2348 emit_d32(cbuf, 0x00);
2349 %}
2350
2351 enc_class lock_prefix()
2352 %{
2353 emit_opcode(cbuf, 0xF0); // lock
2354 %}
2355
2356 enc_class REX_mem(memory mem)
2357 %{
2358 if ($mem$$base >= 8) {
2359 if ($mem$$index < 8) {
2360 emit_opcode(cbuf, Assembler::REX_B);
2361 } else {
2362 emit_opcode(cbuf, Assembler::REX_XB);
2363 }
2364 } else {
2365 if ($mem$$index >= 8) {
2366 emit_opcode(cbuf, Assembler::REX_X);
2367 }
2368 }
2369 %}
2370
2371 enc_class REX_mem_wide(memory mem)
2372 %{
2373 if ($mem$$base >= 8) {
2374 if ($mem$$index < 8) {
2375 emit_opcode(cbuf, Assembler::REX_WB);
2376 } else {
2377 emit_opcode(cbuf, Assembler::REX_WXB);
2378 }
2379 } else {
2380 if ($mem$$index < 8) {
2381 emit_opcode(cbuf, Assembler::REX_W);
2382 } else {
2383 emit_opcode(cbuf, Assembler::REX_WX);
2384 }
2385 }
2386 %}
2387
2388 // for byte regs
2389 enc_class REX_breg(rRegI reg)
2390 %{
2391 if ($reg$$reg >= 4) {
2392 emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2393 }
2394 %}
2395
2396 // for byte regs
2397 enc_class REX_reg_breg(rRegI dst, rRegI src)
2398 %{
2399 if ($dst$$reg < 8) {
2400 if ($src$$reg >= 4) {
2401 emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2402 }
2403 } else {
2404 if ($src$$reg < 8) {
2405 emit_opcode(cbuf, Assembler::REX_R);
2406 } else {
2407 emit_opcode(cbuf, Assembler::REX_RB);
2408 }
2409 }
2410 %}
2411
2412 // for byte regs
2413 enc_class REX_breg_mem(rRegI reg, memory mem)
2414 %{
2415 if ($reg$$reg < 8) {
2416 if ($mem$$base < 8) {
2417 if ($mem$$index >= 8) {
2418 emit_opcode(cbuf, Assembler::REX_X);
2419 } else if ($reg$$reg >= 4) {
2420 emit_opcode(cbuf, Assembler::REX);
2421 }
2422 } else {
2423 if ($mem$$index < 8) {
2424 emit_opcode(cbuf, Assembler::REX_B);
2425 } else {
2426 emit_opcode(cbuf, Assembler::REX_XB);
2427 }
2428 }
2429 } else {
2430 if ($mem$$base < 8) {
2431 if ($mem$$index < 8) {
2432 emit_opcode(cbuf, Assembler::REX_R);
2433 } else {
2434 emit_opcode(cbuf, Assembler::REX_RX);
2435 }
2436 } else {
2437 if ($mem$$index < 8) {
2438 emit_opcode(cbuf, Assembler::REX_RB);
2439 } else {
2440 emit_opcode(cbuf, Assembler::REX_RXB);
2441 }
2442 }
2443 }
2444 %}
2445
2446 enc_class REX_reg(rRegI reg)
2447 %{
2448 if ($reg$$reg >= 8) {
2449 emit_opcode(cbuf, Assembler::REX_B);
2450 }
2451 %}
2452
2453 enc_class REX_reg_wide(rRegI reg)
2454 %{
2455 if ($reg$$reg < 8) {
2456 emit_opcode(cbuf, Assembler::REX_W);
2457 } else {
2458 emit_opcode(cbuf, Assembler::REX_WB);
2459 }
2460 %}
2461
2462 enc_class REX_reg_reg(rRegI dst, rRegI src)
2463 %{
2464 if ($dst$$reg < 8) {
2465 if ($src$$reg >= 8) {
2466 emit_opcode(cbuf, Assembler::REX_B);
2467 }
2468 } else {
2469 if ($src$$reg < 8) {
2470 emit_opcode(cbuf, Assembler::REX_R);
2471 } else {
2472 emit_opcode(cbuf, Assembler::REX_RB);
2473 }
2474 }
2475 %}
2476
2477 enc_class REX_reg_reg_wide(rRegI dst, rRegI src)
2478 %{
2479 if ($dst$$reg < 8) {
2480 if ($src$$reg < 8) {
2481 emit_opcode(cbuf, Assembler::REX_W);
2482 } else {
2483 emit_opcode(cbuf, Assembler::REX_WB);
2484 }
2485 } else {
2486 if ($src$$reg < 8) {
2487 emit_opcode(cbuf, Assembler::REX_WR);
2488 } else {
2489 emit_opcode(cbuf, Assembler::REX_WRB);
2490 }
2491 }
2492 %}
2493
2494 enc_class REX_reg_mem(rRegI reg, memory mem)
2495 %{
2496 if ($reg$$reg < 8) {
2497 if ($mem$$base < 8) {
2498 if ($mem$$index >= 8) {
2499 emit_opcode(cbuf, Assembler::REX_X);
2500 }
2501 } else {
2502 if ($mem$$index < 8) {
2503 emit_opcode(cbuf, Assembler::REX_B);
2504 } else {
2505 emit_opcode(cbuf, Assembler::REX_XB);
2506 }
2507 }
2508 } else {
2509 if ($mem$$base < 8) {
2510 if ($mem$$index < 8) {
2511 emit_opcode(cbuf, Assembler::REX_R);
2512 } else {
2513 emit_opcode(cbuf, Assembler::REX_RX);
2514 }
2515 } else {
2516 if ($mem$$index < 8) {
2517 emit_opcode(cbuf, Assembler::REX_RB);
2518 } else {
2519 emit_opcode(cbuf, Assembler::REX_RXB);
2520 }
2521 }
2522 }
2523 %}
2524
2525 enc_class REX_reg_mem_wide(rRegL reg, memory mem)
2526 %{
2527 if ($reg$$reg < 8) {
2528 if ($mem$$base < 8) {
2529 if ($mem$$index < 8) {
2530 emit_opcode(cbuf, Assembler::REX_W);
2531 } else {
2532 emit_opcode(cbuf, Assembler::REX_WX);
2533 }
2534 } else {
2535 if ($mem$$index < 8) {
2536 emit_opcode(cbuf, Assembler::REX_WB);
2537 } else {
2538 emit_opcode(cbuf, Assembler::REX_WXB);
2539 }
2540 }
2541 } else {
2542 if ($mem$$base < 8) {
2543 if ($mem$$index < 8) {
2544 emit_opcode(cbuf, Assembler::REX_WR);
2545 } else {
2546 emit_opcode(cbuf, Assembler::REX_WRX);
2547 }
2548 } else {
2549 if ($mem$$index < 8) {
2550 emit_opcode(cbuf, Assembler::REX_WRB);
2551 } else {
2552 emit_opcode(cbuf, Assembler::REX_WRXB);
2553 }
2554 }
2555 }
2556 %}
2557
2558 enc_class reg_mem(rRegI ereg, memory mem)
2559 %{
2560 // High registers handle in encode_RegMem
2561 int reg = $ereg$$reg;
2562 int base = $mem$$base;
2563 int index = $mem$$index;
2564 int scale = $mem$$scale;
2565 int disp = $mem$$disp;
2566 relocInfo::relocType disp_reloc = $mem->disp_reloc();
2567
2568 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
2569 %}
2570
2571 enc_class RM_opc_mem(immI rm_opcode, memory mem)
2572 %{
2573 int rm_byte_opcode = $rm_opcode$$constant;
2574
2575 // High registers handle in encode_RegMem
2576 int base = $mem$$base;
2577 int index = $mem$$index;
2578 int scale = $mem$$scale;
2579 int displace = $mem$$disp;
2580
2581 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when
2582 // working with static
2583 // globals
2584 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
2585 disp_reloc);
2586 %}
2587
2588 enc_class reg_lea(rRegI dst, rRegI src0, immI src1)
2589 %{
2590 int reg_encoding = $dst$$reg;
2591 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2592 int index = 0x04; // 0x04 indicates no index
2593 int scale = 0x00; // 0x00 indicates no scale
2594 int displace = $src1$$constant; // 0x00 indicates no displacement
2595 relocInfo::relocType disp_reloc = relocInfo::none;
2596 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace,
2597 disp_reloc);
2598 %}
2599
2600 enc_class neg_reg(rRegI dst)
2601 %{
2602 int dstenc = $dst$$reg;
2603 if (dstenc >= 8) {
2604 emit_opcode(cbuf, Assembler::REX_B);
2605 dstenc -= 8;
2606 }
2607 // NEG $dst
2608 emit_opcode(cbuf, 0xF7);
2609 emit_rm(cbuf, 0x3, 0x03, dstenc);
2610 %}
2611
2612 enc_class neg_reg_wide(rRegI dst)
2613 %{
2614 int dstenc = $dst$$reg;
2615 if (dstenc < 8) {
2616 emit_opcode(cbuf, Assembler::REX_W);
2617 } else {
2618 emit_opcode(cbuf, Assembler::REX_WB);
2619 dstenc -= 8;
2620 }
2621 // NEG $dst
2622 emit_opcode(cbuf, 0xF7);
2623 emit_rm(cbuf, 0x3, 0x03, dstenc);
2624 %}
2625
2626 enc_class setLT_reg(rRegI dst)
2627 %{
2628 int dstenc = $dst$$reg;
2629 if (dstenc >= 8) {
2630 emit_opcode(cbuf, Assembler::REX_B);
2631 dstenc -= 8;
2632 } else if (dstenc >= 4) {
2633 emit_opcode(cbuf, Assembler::REX);
2634 }
2635 // SETLT $dst
2636 emit_opcode(cbuf, 0x0F);
2637 emit_opcode(cbuf, 0x9C);
2638 emit_rm(cbuf, 0x3, 0x0, dstenc);
2639 %}
2640
2641 enc_class setNZ_reg(rRegI dst)
2642 %{
2643 int dstenc = $dst$$reg;
2644 if (dstenc >= 8) {
2645 emit_opcode(cbuf, Assembler::REX_B);
2646 dstenc -= 8;
2647 } else if (dstenc >= 4) {
2648 emit_opcode(cbuf, Assembler::REX);
2649 }
2650 // SETNZ $dst
2651 emit_opcode(cbuf, 0x0F);
2652 emit_opcode(cbuf, 0x95);
2653 emit_rm(cbuf, 0x3, 0x0, dstenc);
2654 %}
2655
2656
2657 // Compare the lonogs and set -1, 0, or 1 into dst
2658 enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst)
2659 %{
2660 int src1enc = $src1$$reg;
2661 int src2enc = $src2$$reg;
2662 int dstenc = $dst$$reg;
2663
2664 // cmpq $src1, $src2
2665 if (src1enc < 8) {
2666 if (src2enc < 8) {
2667 emit_opcode(cbuf, Assembler::REX_W);
2668 } else {
2669 emit_opcode(cbuf, Assembler::REX_WB);
2670 }
2671 } else {
2672 if (src2enc < 8) {
2673 emit_opcode(cbuf, Assembler::REX_WR);
2674 } else {
2675 emit_opcode(cbuf, Assembler::REX_WRB);
2676 }
2677 }
2678 emit_opcode(cbuf, 0x3B);
2679 emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7);
2680
2681 // movl $dst, -1
2682 if (dstenc >= 8) {
2683 emit_opcode(cbuf, Assembler::REX_B);
2684 }
2685 emit_opcode(cbuf, 0xB8 | (dstenc & 7));
2686 emit_d32(cbuf, -1);
2687
2688 // jl,s done
2689 emit_opcode(cbuf, 0x7C);
2690 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
2691
2692 // setne $dst
2693 if (dstenc >= 4) {
2694 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
2695 }
2696 emit_opcode(cbuf, 0x0F);
2697 emit_opcode(cbuf, 0x95);
2698 emit_opcode(cbuf, 0xC0 | (dstenc & 7));
2699
2700 // movzbl $dst, $dst
2701 if (dstenc >= 4) {
2702 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
2703 }
2704 emit_opcode(cbuf, 0x0F);
2705 emit_opcode(cbuf, 0xB6);
2706 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
2707 %}
2708
2709 enc_class Push_ResultXD(regD dst) %{
2710 MacroAssembler _masm(&cbuf);
2711 __ fstp_d(Address(rsp, 0));
2712 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2713 __ addptr(rsp, 8);
2714 %}
2715
2716 enc_class Push_SrcXD(regD src) %{
2717 MacroAssembler _masm(&cbuf);
2718 __ subptr(rsp, 8);
2719 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2720 __ fld_d(Address(rsp, 0));
2721 %}
2722
2723
2724 enc_class enc_rethrow()
2725 %{
2726 cbuf.set_insts_mark();
2727 emit_opcode(cbuf, 0xE9); // jmp entry
2728 emit_d32_reloc(cbuf,
2729 (int) (OptoRuntime::rethrow_stub() - cbuf.insts_end() - 4),
2730 runtime_call_Relocation::spec(),
2731 RELOC_DISP32);
2732 %}
2733
2734 %}
2735
2736
2737
2738 //----------FRAME--------------------------------------------------------------
2739 // Definition of frame structure and management information.
2740 //
2741 // S T A C K L A Y O U T Allocators stack-slot number
2742 // | (to get allocators register number
2743 // G Owned by | | v add OptoReg::stack0())
2744 // r CALLER | |
2745 // o | +--------+ pad to even-align allocators stack-slot
2746 // w V | pad0 | numbers; owned by CALLER
2747 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
2748 // h ^ | in | 5
2749 // | | args | 4 Holes in incoming args owned by SELF
2750 // | | | | 3
2751 // | | +--------+
2752 // V | | old out| Empty on Intel, window on Sparc
2753 // | old |preserve| Must be even aligned.
2754 // | SP-+--------+----> Matcher::_old_SP, even aligned
2755 // | | in | 3 area for Intel ret address
2756 // Owned by |preserve| Empty on Sparc.
2757 // SELF +--------+
2758 // | | pad2 | 2 pad to align old SP
2759 // | +--------+ 1
2760 // | | locks | 0
2761 // | +--------+----> OptoReg::stack0(), even aligned
2762 // | | pad1 | 11 pad to align new SP
2763 // | +--------+
2764 // | | | 10
2765 // | | spills | 9 spills
2766 // V | | 8 (pad0 slot for callee)
2767 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
2768 // ^ | out | 7
2769 // | | args | 6 Holes in outgoing args owned by CALLEE
2770 // Owned by +--------+
2771 // CALLEE | new out| 6 Empty on Intel, window on Sparc
2772 // | new |preserve| Must be even-aligned.
2773 // | SP-+--------+----> Matcher::_new_SP, even aligned
2774 // | | |
2775 //
2776 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
2777 // known from SELF's arguments and the Java calling convention.
2778 // Region 6-7 is determined per call site.
2779 // Note 2: If the calling convention leaves holes in the incoming argument
2780 // area, those holes are owned by SELF. Holes in the outgoing area
2781 // are owned by the CALLEE. Holes should not be nessecary in the
2782 // incoming area, as the Java calling convention is completely under
2783 // the control of the AD file. Doubles can be sorted and packed to
2784 // avoid holes. Holes in the outgoing arguments may be nessecary for
2785 // varargs C calling conventions.
2786 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
2787 // even aligned with pad0 as needed.
2788 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
2789 // region 6-11 is even aligned; it may be padded out more so that
2790 // the region from SP to FP meets the minimum stack alignment.
2791 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
2792 // alignment. Region 11, pad1, may be dynamically extended so that
2793 // SP meets the minimum alignment.
2794
2795 frame
2796 %{
2797 // What direction does stack grow in (assumed to be same for C & Java)
2798 stack_direction(TOWARDS_LOW);
2799
2800 // These three registers define part of the calling convention
2801 // between compiled code and the interpreter.
2802 inline_cache_reg(RAX); // Inline Cache Register
2803 interpreter_method_oop_reg(RBX); // Method Oop Register when
2804 // calling interpreter
2805
2806 // Optional: name the operand used by cisc-spilling to access
2807 // [stack_pointer + offset]
2808 cisc_spilling_operand_name(indOffset32);
2809
2810 // Number of stack slots consumed by locking an object
2811 sync_stack_slots(2);
2812
2813 // Compiled code's Frame Pointer
2814 frame_pointer(RSP);
2815
2816 // Interpreter stores its frame pointer in a register which is
2817 // stored to the stack by I2CAdaptors.
2818 // I2CAdaptors convert from interpreted java to compiled java.
2819 interpreter_frame_pointer(RBP);
2820
2821 // Stack alignment requirement
2822 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
2823
2824 // Number of stack slots between incoming argument block and the start of
2825 // a new frame. The PROLOG must add this many slots to the stack. The
2826 // EPILOG must remove this many slots. amd64 needs two slots for
2827 // return address.
2828 in_preserve_stack_slots(4 + 2 * VerifyStackAtCalls);
2829
2830 // Number of outgoing stack slots killed above the out_preserve_stack_slots
2831 // for calls to C. Supports the var-args backing area for register parms.
2832 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt);
2833
2834 // The after-PROLOG location of the return address. Location of
2835 // return address specifies a type (REG or STACK) and a number
2836 // representing the register number (i.e. - use a register name) or
2837 // stack slot.
2838 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
2839 // Otherwise, it is above the locks and verification slot and alignment word
2840 return_addr(STACK - 2 +
2841 align_up((Compile::current()->in_preserve_stack_slots() +
2842 Compile::current()->fixed_slots()),
2843 stack_alignment_in_slots()));
2844
2845 // Body of function which returns an integer array locating
2846 // arguments either in registers or in stack slots. Passed an array
2847 // of ideal registers called "sig" and a "length" count. Stack-slot
2848 // offsets are based on outgoing arguments, i.e. a CALLER setting up
2849 // arguments for a CALLEE. Incoming stack arguments are
2850 // automatically biased by the preserve_stack_slots field above.
2851
2852 calling_convention
2853 %{
2854 // No difference between ingoing/outgoing just pass false
2855 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
2856 %}
2857
2858 c_calling_convention
2859 %{
2860 // This is obviously always outgoing
2861 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
2862 %}
2863
2864 // Location of compiled Java return values. Same as C for now.
2865 return_value
2866 %{
2867 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
2868 "only return normal values");
2869
2870 static const int lo[Op_RegL + 1] = {
2871 0,
2872 0,
2873 RAX_num, // Op_RegN
2874 RAX_num, // Op_RegI
2875 RAX_num, // Op_RegP
2876 XMM0_num, // Op_RegF
2877 XMM0_num, // Op_RegD
2878 RAX_num // Op_RegL
2879 };
2880 static const int hi[Op_RegL + 1] = {
2881 0,
2882 0,
2883 OptoReg::Bad, // Op_RegN
2884 OptoReg::Bad, // Op_RegI
2885 RAX_H_num, // Op_RegP
2886 OptoReg::Bad, // Op_RegF
2887 XMM0b_num, // Op_RegD
2888 RAX_H_num // Op_RegL
2889 };
2890 // Excluded flags and vector registers.
2891 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 6, "missing type");
2892 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
2893 %}
2894 %}
2895
2896 //----------ATTRIBUTES---------------------------------------------------------
2897 //----------Operand Attributes-------------------------------------------------
2898 op_attrib op_cost(0); // Required cost attribute
2899
2900 //----------Instruction Attributes---------------------------------------------
2901 ins_attrib ins_cost(100); // Required cost attribute
2902 ins_attrib ins_size(8); // Required size attribute (in bits)
2903 ins_attrib ins_short_branch(0); // Required flag: is this instruction
2904 // a non-matching short branch variant
2905 // of some long branch?
2906 ins_attrib ins_alignment(1); // Required alignment attribute (must
2907 // be a power of 2) specifies the
2908 // alignment that some part of the
2909 // instruction (not necessarily the
2910 // start) requires. If > 1, a
2911 // compute_padding() function must be
2912 // provided for the instruction
2913
2914 //----------OPERANDS-----------------------------------------------------------
2915 // Operand definitions must precede instruction definitions for correct parsing
2916 // in the ADLC because operands constitute user defined types which are used in
2917 // instruction definitions.
2918
2919 //----------Simple Operands----------------------------------------------------
2920 // Immediate Operands
2921 // Integer Immediate
2922 operand immI()
2923 %{
2924 match(ConI);
2925
2926 op_cost(10);
2927 format %{ %}
2928 interface(CONST_INTER);
2929 %}
2930
2931 // Constant for test vs zero
2932 operand immI0()
2933 %{
2934 predicate(n->get_int() == 0);
2935 match(ConI);
2936
2937 op_cost(0);
2938 format %{ %}
2939 interface(CONST_INTER);
2940 %}
2941
2942 // Constant for increment
2943 operand immI1()
2944 %{
2945 predicate(n->get_int() == 1);
2946 match(ConI);
2947
2948 op_cost(0);
2949 format %{ %}
2950 interface(CONST_INTER);
2951 %}
2952
2953 // Constant for decrement
2954 operand immI_M1()
2955 %{
2956 predicate(n->get_int() == -1);
2957 match(ConI);
2958
2959 op_cost(0);
2960 format %{ %}
2961 interface(CONST_INTER);
2962 %}
2963
2964 // Valid scale values for addressing modes
2965 operand immI2()
2966 %{
2967 predicate(0 <= n->get_int() && (n->get_int() <= 3));
2968 match(ConI);
2969
2970 format %{ %}
2971 interface(CONST_INTER);
2972 %}
2973
2974 operand immI8()
2975 %{
2976 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80));
2977 match(ConI);
2978
2979 op_cost(5);
2980 format %{ %}
2981 interface(CONST_INTER);
2982 %}
2983
2984 operand immU8()
2985 %{
2986 predicate((0 <= n->get_int()) && (n->get_int() <= 255));
2987 match(ConI);
2988
2989 op_cost(5);
2990 format %{ %}
2991 interface(CONST_INTER);
2992 %}
2993
2994 operand immI16()
2995 %{
2996 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
2997 match(ConI);
2998
2999 op_cost(10);
3000 format %{ %}
3001 interface(CONST_INTER);
3002 %}
3003
3004 // Int Immediate non-negative
3005 operand immU31()
3006 %{
3007 predicate(n->get_int() >= 0);
3008 match(ConI);
3009
3010 op_cost(0);
3011 format %{ %}
3012 interface(CONST_INTER);
3013 %}
3014
3015 // Constant for long shifts
3016 operand immI_32()
3017 %{
3018 predicate( n->get_int() == 32 );
3019 match(ConI);
3020
3021 op_cost(0);
3022 format %{ %}
3023 interface(CONST_INTER);
3024 %}
3025
3026 // Constant for long shifts
3027 operand immI_64()
3028 %{
3029 predicate( n->get_int() == 64 );
3030 match(ConI);
3031
3032 op_cost(0);
3033 format %{ %}
3034 interface(CONST_INTER);
3035 %}
3036
3037 // Pointer Immediate
3038 operand immP()
3039 %{
3040 match(ConP);
3041
3042 op_cost(10);
3043 format %{ %}
3044 interface(CONST_INTER);
3045 %}
3046
3047 // NULL Pointer Immediate
3048 operand immP0()
3049 %{
3050 predicate(n->get_ptr() == 0);
3051 match(ConP);
3052
3053 op_cost(5);
3054 format %{ %}
3055 interface(CONST_INTER);
3056 %}
3057
3058 // Pointer Immediate
3059 operand immN() %{
3060 match(ConN);
3061
3062 op_cost(10);
3063 format %{ %}
3064 interface(CONST_INTER);
3065 %}
3066
3067 operand immNKlass() %{
3068 match(ConNKlass);
3069
3070 op_cost(10);
3071 format %{ %}
3072 interface(CONST_INTER);
3073 %}
3074
3075 // NULL Pointer Immediate
3076 operand immN0() %{
3077 predicate(n->get_narrowcon() == 0);
3078 match(ConN);
3079
3080 op_cost(5);
3081 format %{ %}
3082 interface(CONST_INTER);
3083 %}
3084
3085 operand immP31()
3086 %{
3087 predicate(n->as_Type()->type()->reloc() == relocInfo::none
3088 && (n->get_ptr() >> 31) == 0);
3089 match(ConP);
3090
3091 op_cost(5);
3092 format %{ %}
3093 interface(CONST_INTER);
3094 %}
3095
3096
3097 // Long Immediate
3098 operand immL()
3099 %{
3100 match(ConL);
3101
3102 op_cost(20);
3103 format %{ %}
3104 interface(CONST_INTER);
3105 %}
3106
3107 // Long Immediate 8-bit
3108 operand immL8()
3109 %{
3110 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L);
3111 match(ConL);
3112
3113 op_cost(5);
3114 format %{ %}
3115 interface(CONST_INTER);
3116 %}
3117
3118 // Long Immediate 32-bit unsigned
3119 operand immUL32()
3120 %{
3121 predicate(n->get_long() == (unsigned int) (n->get_long()));
3122 match(ConL);
3123
3124 op_cost(10);
3125 format %{ %}
3126 interface(CONST_INTER);
3127 %}
3128
3129 // Long Immediate 32-bit signed
3130 operand immL32()
3131 %{
3132 predicate(n->get_long() == (int) (n->get_long()));
3133 match(ConL);
3134
3135 op_cost(15);
3136 format %{ %}
3137 interface(CONST_INTER);
3138 %}
3139
3140 // Long Immediate zero
3141 operand immL0()
3142 %{
3143 predicate(n->get_long() == 0L);
3144 match(ConL);
3145
3146 op_cost(10);
3147 format %{ %}
3148 interface(CONST_INTER);
3149 %}
3150
3151 // Constant for increment
3152 operand immL1()
3153 %{
3154 predicate(n->get_long() == 1);
3155 match(ConL);
3156
3157 format %{ %}
3158 interface(CONST_INTER);
3159 %}
3160
3161 // Constant for decrement
3162 operand immL_M1()
3163 %{
3164 predicate(n->get_long() == -1);
3165 match(ConL);
3166
3167 format %{ %}
3168 interface(CONST_INTER);
3169 %}
3170
3171 // Long Immediate: the value 10
3172 operand immL10()
3173 %{
3174 predicate(n->get_long() == 10);
3175 match(ConL);
3176
3177 format %{ %}
3178 interface(CONST_INTER);
3179 %}
3180
3181 // Long immediate from 0 to 127.
3182 // Used for a shorter form of long mul by 10.
3183 operand immL_127()
3184 %{
3185 predicate(0 <= n->get_long() && n->get_long() < 0x80);
3186 match(ConL);
3187
3188 op_cost(10);
3189 format %{ %}
3190 interface(CONST_INTER);
3191 %}
3192
3193 // Long Immediate: low 32-bit mask
3194 operand immL_32bits()
3195 %{
3196 predicate(n->get_long() == 0xFFFFFFFFL);
3197 match(ConL);
3198 op_cost(20);
3199
3200 format %{ %}
3201 interface(CONST_INTER);
3202 %}
3203
3204 // Float Immediate zero
3205 operand immF0()
3206 %{
3207 predicate(jint_cast(n->getf()) == 0);
3208 match(ConF);
3209
3210 op_cost(5);
3211 format %{ %}
3212 interface(CONST_INTER);
3213 %}
3214
3215 // Float Immediate
3216 operand immF()
3217 %{
3218 match(ConF);
3219
3220 op_cost(15);
3221 format %{ %}
3222 interface(CONST_INTER);
3223 %}
3224
3225 // Double Immediate zero
3226 operand immD0()
3227 %{
3228 predicate(jlong_cast(n->getd()) == 0);
3229 match(ConD);
3230
3231 op_cost(5);
3232 format %{ %}
3233 interface(CONST_INTER);
3234 %}
3235
3236 // Double Immediate
3237 operand immD()
3238 %{
3239 match(ConD);
3240
3241 op_cost(15);
3242 format %{ %}
3243 interface(CONST_INTER);
3244 %}
3245
3246 // Immediates for special shifts (sign extend)
3247
3248 // Constants for increment
3249 operand immI_16()
3250 %{
3251 predicate(n->get_int() == 16);
3252 match(ConI);
3253
3254 format %{ %}
3255 interface(CONST_INTER);
3256 %}
3257
3258 operand immI_24()
3259 %{
3260 predicate(n->get_int() == 24);
3261 match(ConI);
3262
3263 format %{ %}
3264 interface(CONST_INTER);
3265 %}
3266
3267 // Constant for byte-wide masking
3268 operand immI_255()
3269 %{
3270 predicate(n->get_int() == 255);
3271 match(ConI);
3272
3273 format %{ %}
3274 interface(CONST_INTER);
3275 %}
3276
3277 // Constant for short-wide masking
3278 operand immI_65535()
3279 %{
3280 predicate(n->get_int() == 65535);
3281 match(ConI);
3282
3283 format %{ %}
3284 interface(CONST_INTER);
3285 %}
3286
3287 // Constant for byte-wide masking
3288 operand immL_255()
3289 %{
3290 predicate(n->get_long() == 255);
3291 match(ConL);
3292
3293 format %{ %}
3294 interface(CONST_INTER);
3295 %}
3296
3297 // Constant for short-wide masking
3298 operand immL_65535()
3299 %{
3300 predicate(n->get_long() == 65535);
3301 match(ConL);
3302
3303 format %{ %}
3304 interface(CONST_INTER);
3305 %}
3306
3307 // Register Operands
3308 // Integer Register
3309 operand rRegI()
3310 %{
3311 constraint(ALLOC_IN_RC(int_reg));
3312 match(RegI);
3313
3314 match(rax_RegI);
3315 match(rbx_RegI);
3316 match(rcx_RegI);
3317 match(rdx_RegI);
3318 match(rdi_RegI);
3319
3320 format %{ %}
3321 interface(REG_INTER);
3322 %}
3323
3324 // Special Registers
3325 operand rax_RegI()
3326 %{
3327 constraint(ALLOC_IN_RC(int_rax_reg));
3328 match(RegI);
3329 match(rRegI);
3330
3331 format %{ "RAX" %}
3332 interface(REG_INTER);
3333 %}
3334
3335 // Special Registers
3336 operand rbx_RegI()
3337 %{
3338 constraint(ALLOC_IN_RC(int_rbx_reg));
3339 match(RegI);
3340 match(rRegI);
3341
3342 format %{ "RBX" %}
3343 interface(REG_INTER);
3344 %}
3345
3346 operand rcx_RegI()
3347 %{
3348 constraint(ALLOC_IN_RC(int_rcx_reg));
3349 match(RegI);
3350 match(rRegI);
3351
3352 format %{ "RCX" %}
3353 interface(REG_INTER);
3354 %}
3355
3356 operand rdx_RegI()
3357 %{
3358 constraint(ALLOC_IN_RC(int_rdx_reg));
3359 match(RegI);
3360 match(rRegI);
3361
3362 format %{ "RDX" %}
3363 interface(REG_INTER);
3364 %}
3365
3366 operand rdi_RegI()
3367 %{
3368 constraint(ALLOC_IN_RC(int_rdi_reg));
3369 match(RegI);
3370 match(rRegI);
3371
3372 format %{ "RDI" %}
3373 interface(REG_INTER);
3374 %}
3375
3376 operand no_rcx_RegI()
3377 %{
3378 constraint(ALLOC_IN_RC(int_no_rcx_reg));
3379 match(RegI);
3380 match(rax_RegI);
3381 match(rbx_RegI);
3382 match(rdx_RegI);
3383 match(rdi_RegI);
3384
3385 format %{ %}
3386 interface(REG_INTER);
3387 %}
3388
3389 operand no_rax_rdx_RegI()
3390 %{
3391 constraint(ALLOC_IN_RC(int_no_rax_rdx_reg));
3392 match(RegI);
3393 match(rbx_RegI);
3394 match(rcx_RegI);
3395 match(rdi_RegI);
3396
3397 format %{ %}
3398 interface(REG_INTER);
3399 %}
3400
3401 // Pointer Register
3402 operand any_RegP()
3403 %{
3404 constraint(ALLOC_IN_RC(any_reg));
3405 match(RegP);
3406 match(rax_RegP);
3407 match(rbx_RegP);
3408 match(rdi_RegP);
3409 match(rsi_RegP);
3410 match(rbp_RegP);
3411 match(r15_RegP);
3412 match(rRegP);
3413
3414 format %{ %}
3415 interface(REG_INTER);
3416 %}
3417
3418 operand rRegP()
3419 %{
3420 constraint(ALLOC_IN_RC(ptr_reg));
3421 match(RegP);
3422 match(rax_RegP);
3423 match(rbx_RegP);
3424 match(rdi_RegP);
3425 match(rsi_RegP);
3426 match(rbp_RegP); // See Q&A below about
3427 match(r15_RegP); // r15_RegP and rbp_RegP.
3428
3429 format %{ %}
3430 interface(REG_INTER);
3431 %}
3432
3433 operand rRegN() %{
3434 constraint(ALLOC_IN_RC(int_reg));
3435 match(RegN);
3436
3437 format %{ %}
3438 interface(REG_INTER);
3439 %}
3440
3441 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP?
3442 // Answer: Operand match rules govern the DFA as it processes instruction inputs.
3443 // It's fine for an instruction input that expects rRegP to match a r15_RegP.
3444 // The output of an instruction is controlled by the allocator, which respects
3445 // register class masks, not match rules. Unless an instruction mentions
3446 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered
3447 // by the allocator as an input.
3448 // The same logic applies to rbp_RegP being a match for rRegP: If PreserveFramePointer==true,
3449 // the RBP is used as a proper frame pointer and is not included in ptr_reg. As a
3450 // result, RBP is not included in the output of the instruction either.
3451
3452 operand no_rax_RegP()
3453 %{
3454 constraint(ALLOC_IN_RC(ptr_no_rax_reg));
3455 match(RegP);
3456 match(rbx_RegP);
3457 match(rsi_RegP);
3458 match(rdi_RegP);
3459
3460 format %{ %}
3461 interface(REG_INTER);
3462 %}
3463
3464 // This operand is not allowed to use RBP even if
3465 // RBP is not used to hold the frame pointer.
3466 operand no_rbp_RegP()
3467 %{
3468 constraint(ALLOC_IN_RC(ptr_reg_no_rbp));
3469 match(RegP);
3470 match(rbx_RegP);
3471 match(rsi_RegP);
3472 match(rdi_RegP);
3473
3474 format %{ %}
3475 interface(REG_INTER);
3476 %}
3477
3478 operand no_rax_rbx_RegP()
3479 %{
3480 constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg));
3481 match(RegP);
3482 match(rsi_RegP);
3483 match(rdi_RegP);
3484
3485 format %{ %}
3486 interface(REG_INTER);
3487 %}
3488
3489 // Special Registers
3490 // Return a pointer value
3491 operand rax_RegP()
3492 %{
3493 constraint(ALLOC_IN_RC(ptr_rax_reg));
3494 match(RegP);
3495 match(rRegP);
3496
3497 format %{ %}
3498 interface(REG_INTER);
3499 %}
3500
3501 // Special Registers
3502 // Return a compressed pointer value
3503 operand rax_RegN()
3504 %{
3505 constraint(ALLOC_IN_RC(int_rax_reg));
3506 match(RegN);
3507 match(rRegN);
3508
3509 format %{ %}
3510 interface(REG_INTER);
3511 %}
3512
3513 // Used in AtomicAdd
3514 operand rbx_RegP()
3515 %{
3516 constraint(ALLOC_IN_RC(ptr_rbx_reg));
3517 match(RegP);
3518 match(rRegP);
3519
3520 format %{ %}
3521 interface(REG_INTER);
3522 %}
3523
3524 operand rsi_RegP()
3525 %{
3526 constraint(ALLOC_IN_RC(ptr_rsi_reg));
3527 match(RegP);
3528 match(rRegP);
3529
3530 format %{ %}
3531 interface(REG_INTER);
3532 %}
3533
3534 // Used in rep stosq
3535 operand rdi_RegP()
3536 %{
3537 constraint(ALLOC_IN_RC(ptr_rdi_reg));
3538 match(RegP);
3539 match(rRegP);
3540
3541 format %{ %}
3542 interface(REG_INTER);
3543 %}
3544
3545 operand r15_RegP()
3546 %{
3547 constraint(ALLOC_IN_RC(ptr_r15_reg));
3548 match(RegP);
3549 match(rRegP);
3550
3551 format %{ %}
3552 interface(REG_INTER);
3553 %}
3554
3555 operand rRegL()
3556 %{
3557 constraint(ALLOC_IN_RC(long_reg));
3558 match(RegL);
3559 match(rax_RegL);
3560 match(rdx_RegL);
3561
3562 format %{ %}
3563 interface(REG_INTER);
3564 %}
3565
3566 // Special Registers
3567 operand no_rax_rdx_RegL()
3568 %{
3569 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3570 match(RegL);
3571 match(rRegL);
3572
3573 format %{ %}
3574 interface(REG_INTER);
3575 %}
3576
3577 operand no_rax_RegL()
3578 %{
3579 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3580 match(RegL);
3581 match(rRegL);
3582 match(rdx_RegL);
3583
3584 format %{ %}
3585 interface(REG_INTER);
3586 %}
3587
3588 operand no_rcx_RegL()
3589 %{
3590 constraint(ALLOC_IN_RC(long_no_rcx_reg));
3591 match(RegL);
3592 match(rRegL);
3593
3594 format %{ %}
3595 interface(REG_INTER);
3596 %}
3597
3598 operand rax_RegL()
3599 %{
3600 constraint(ALLOC_IN_RC(long_rax_reg));
3601 match(RegL);
3602 match(rRegL);
3603
3604 format %{ "RAX" %}
3605 interface(REG_INTER);
3606 %}
3607
3608 operand rcx_RegL()
3609 %{
3610 constraint(ALLOC_IN_RC(long_rcx_reg));
3611 match(RegL);
3612 match(rRegL);
3613
3614 format %{ %}
3615 interface(REG_INTER);
3616 %}
3617
3618 operand rdx_RegL()
3619 %{
3620 constraint(ALLOC_IN_RC(long_rdx_reg));
3621 match(RegL);
3622 match(rRegL);
3623
3624 format %{ %}
3625 interface(REG_INTER);
3626 %}
3627
3628 // Flags register, used as output of compare instructions
3629 operand rFlagsReg()
3630 %{
3631 constraint(ALLOC_IN_RC(int_flags));
3632 match(RegFlags);
3633
3634 format %{ "RFLAGS" %}
3635 interface(REG_INTER);
3636 %}
3637
3638 // Flags register, used as output of FLOATING POINT compare instructions
3639 operand rFlagsRegU()
3640 %{
3641 constraint(ALLOC_IN_RC(int_flags));
3642 match(RegFlags);
3643
3644 format %{ "RFLAGS_U" %}
3645 interface(REG_INTER);
3646 %}
3647
3648 operand rFlagsRegUCF() %{
3649 constraint(ALLOC_IN_RC(int_flags));
3650 match(RegFlags);
3651 predicate(false);
3652
3653 format %{ "RFLAGS_U_CF" %}
3654 interface(REG_INTER);
3655 %}
3656
3657 // Float register operands
3658 operand regF() %{
3659 constraint(ALLOC_IN_RC(float_reg));
3660 match(RegF);
3661
3662 format %{ %}
3663 interface(REG_INTER);
3664 %}
3665
3666 // Float register operands
3667 operand vlRegF() %{
3668 constraint(ALLOC_IN_RC(float_reg_vl));
3669 match(RegF);
3670
3671 format %{ %}
3672 interface(REG_INTER);
3673 %}
3674
3675 // Double register operands
3676 operand regD() %{
3677 constraint(ALLOC_IN_RC(double_reg));
3678 match(RegD);
3679
3680 format %{ %}
3681 interface(REG_INTER);
3682 %}
3683
3684 // Double register operands
3685 operand vlRegD() %{
3686 constraint(ALLOC_IN_RC(double_reg_vl));
3687 match(RegD);
3688
3689 format %{ %}
3690 interface(REG_INTER);
3691 %}
3692
3693 // Vectors
3694 operand vecS() %{
3695 constraint(ALLOC_IN_RC(vectors_reg_vlbwdq));
3696 match(VecS);
3697
3698 format %{ %}
3699 interface(REG_INTER);
3700 %}
3701
3702 // Vectors
3703 operand legVecS() %{
3704 constraint(ALLOC_IN_RC(vectors_reg_legacy));
3705 match(VecS);
3706
3707 format %{ %}
3708 interface(REG_INTER);
3709 %}
3710
3711 operand vecD() %{
3712 constraint(ALLOC_IN_RC(vectord_reg_vlbwdq));
3713 match(VecD);
3714
3715 format %{ %}
3716 interface(REG_INTER);
3717 %}
3718
3719 operand legVecD() %{
3720 constraint(ALLOC_IN_RC(vectord_reg_legacy));
3721 match(VecD);
3722
3723 format %{ %}
3724 interface(REG_INTER);
3725 %}
3726
3727 operand vecX() %{
3728 constraint(ALLOC_IN_RC(vectorx_reg_vlbwdq));
3729 match(VecX);
3730
3731 format %{ %}
3732 interface(REG_INTER);
3733 %}
3734
3735 operand legVecX() %{
3736 constraint(ALLOC_IN_RC(vectorx_reg_legacy));
3737 match(VecX);
3738
3739 format %{ %}
3740 interface(REG_INTER);
3741 %}
3742
3743 operand vecY() %{
3744 constraint(ALLOC_IN_RC(vectory_reg_vlbwdq));
3745 match(VecY);
3746
3747 format %{ %}
3748 interface(REG_INTER);
3749 %}
3750
3751 operand legVecY() %{
3752 constraint(ALLOC_IN_RC(vectory_reg_legacy));
3753 match(VecY);
3754
3755 format %{ %}
3756 interface(REG_INTER);
3757 %}
3758
3759 //----------Memory Operands----------------------------------------------------
3760 // Direct Memory Operand
3761 // operand direct(immP addr)
3762 // %{
3763 // match(addr);
3764
3765 // format %{ "[$addr]" %}
3766 // interface(MEMORY_INTER) %{
3767 // base(0xFFFFFFFF);
3768 // index(0x4);
3769 // scale(0x0);
3770 // disp($addr);
3771 // %}
3772 // %}
3773
3774 // Indirect Memory Operand
3775 operand indirect(any_RegP reg)
3776 %{
3777 constraint(ALLOC_IN_RC(ptr_reg));
3778 match(reg);
3779
3780 format %{ "[$reg]" %}
3781 interface(MEMORY_INTER) %{
3782 base($reg);
3783 index(0x4);
3784 scale(0x0);
3785 disp(0x0);
3786 %}
3787 %}
3788
3789 // Indirect Memory Plus Short Offset Operand
3790 operand indOffset8(any_RegP reg, immL8 off)
3791 %{
3792 constraint(ALLOC_IN_RC(ptr_reg));
3793 match(AddP reg off);
3794
3795 format %{ "[$reg + $off (8-bit)]" %}
3796 interface(MEMORY_INTER) %{
3797 base($reg);
3798 index(0x4);
3799 scale(0x0);
3800 disp($off);
3801 %}
3802 %}
3803
3804 // Indirect Memory Plus Long Offset Operand
3805 operand indOffset32(any_RegP reg, immL32 off)
3806 %{
3807 constraint(ALLOC_IN_RC(ptr_reg));
3808 match(AddP reg off);
3809
3810 format %{ "[$reg + $off (32-bit)]" %}
3811 interface(MEMORY_INTER) %{
3812 base($reg);
3813 index(0x4);
3814 scale(0x0);
3815 disp($off);
3816 %}
3817 %}
3818
3819 // Indirect Memory Plus Index Register Plus Offset Operand
3820 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off)
3821 %{
3822 constraint(ALLOC_IN_RC(ptr_reg));
3823 match(AddP (AddP reg lreg) off);
3824
3825 op_cost(10);
3826 format %{"[$reg + $off + $lreg]" %}
3827 interface(MEMORY_INTER) %{
3828 base($reg);
3829 index($lreg);
3830 scale(0x0);
3831 disp($off);
3832 %}
3833 %}
3834
3835 // Indirect Memory Plus Index Register Plus Offset Operand
3836 operand indIndex(any_RegP reg, rRegL lreg)
3837 %{
3838 constraint(ALLOC_IN_RC(ptr_reg));
3839 match(AddP reg lreg);
3840
3841 op_cost(10);
3842 format %{"[$reg + $lreg]" %}
3843 interface(MEMORY_INTER) %{
3844 base($reg);
3845 index($lreg);
3846 scale(0x0);
3847 disp(0x0);
3848 %}
3849 %}
3850
3851 // Indirect Memory Times Scale Plus Index Register
3852 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale)
3853 %{
3854 constraint(ALLOC_IN_RC(ptr_reg));
3855 match(AddP reg (LShiftL lreg scale));
3856
3857 op_cost(10);
3858 format %{"[$reg + $lreg << $scale]" %}
3859 interface(MEMORY_INTER) %{
3860 base($reg);
3861 index($lreg);
3862 scale($scale);
3863 disp(0x0);
3864 %}
3865 %}
3866
3867 operand indPosIndexScale(any_RegP reg, rRegI idx, immI2 scale)
3868 %{
3869 constraint(ALLOC_IN_RC(ptr_reg));
3870 predicate(n->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3871 match(AddP reg (LShiftL (ConvI2L idx) scale));
3872
3873 op_cost(10);
3874 format %{"[$reg + pos $idx << $scale]" %}
3875 interface(MEMORY_INTER) %{
3876 base($reg);
3877 index($idx);
3878 scale($scale);
3879 disp(0x0);
3880 %}
3881 %}
3882
3883 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
3884 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale)
3885 %{
3886 constraint(ALLOC_IN_RC(ptr_reg));
3887 match(AddP (AddP reg (LShiftL lreg scale)) off);
3888
3889 op_cost(10);
3890 format %{"[$reg + $off + $lreg << $scale]" %}
3891 interface(MEMORY_INTER) %{
3892 base($reg);
3893 index($lreg);
3894 scale($scale);
3895 disp($off);
3896 %}
3897 %}
3898
3899 // Indirect Memory Plus Positive Index Register Plus Offset Operand
3900 operand indPosIndexOffset(any_RegP reg, immL32 off, rRegI idx)
3901 %{
3902 constraint(ALLOC_IN_RC(ptr_reg));
3903 predicate(n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
3904 match(AddP (AddP reg (ConvI2L idx)) off);
3905
3906 op_cost(10);
3907 format %{"[$reg + $off + $idx]" %}
3908 interface(MEMORY_INTER) %{
3909 base($reg);
3910 index($idx);
3911 scale(0x0);
3912 disp($off);
3913 %}
3914 %}
3915
3916 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
3917 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale)
3918 %{
3919 constraint(ALLOC_IN_RC(ptr_reg));
3920 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3921 match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off);
3922
3923 op_cost(10);
3924 format %{"[$reg + $off + $idx << $scale]" %}
3925 interface(MEMORY_INTER) %{
3926 base($reg);
3927 index($idx);
3928 scale($scale);
3929 disp($off);
3930 %}
3931 %}
3932
3933 // Indirect Narrow Oop Plus Offset Operand
3934 // Note: x86 architecture doesn't support "scale * index + offset" without a base
3935 // we can't free r12 even with Universe::narrow_oop_base() == NULL.
3936 operand indCompressedOopOffset(rRegN reg, immL32 off) %{
3937 predicate(UseCompressedOops && (Universe::narrow_oop_shift() == Address::times_8));
3938 constraint(ALLOC_IN_RC(ptr_reg));
3939 match(AddP (DecodeN reg) off);
3940
3941 op_cost(10);
3942 format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %}
3943 interface(MEMORY_INTER) %{
3944 base(0xc); // R12
3945 index($reg);
3946 scale(0x3);
3947 disp($off);
3948 %}
3949 %}
3950
3951 // Indirect Memory Operand
3952 operand indirectNarrow(rRegN reg)
3953 %{
3954 predicate(Universe::narrow_oop_shift() == 0);
3955 constraint(ALLOC_IN_RC(ptr_reg));
3956 match(DecodeN reg);
3957
3958 format %{ "[$reg]" %}
3959 interface(MEMORY_INTER) %{
3960 base($reg);
3961 index(0x4);
3962 scale(0x0);
3963 disp(0x0);
3964 %}
3965 %}
3966
3967 // Indirect Memory Plus Short Offset Operand
3968 operand indOffset8Narrow(rRegN reg, immL8 off)
3969 %{
3970 predicate(Universe::narrow_oop_shift() == 0);
3971 constraint(ALLOC_IN_RC(ptr_reg));
3972 match(AddP (DecodeN reg) off);
3973
3974 format %{ "[$reg + $off (8-bit)]" %}
3975 interface(MEMORY_INTER) %{
3976 base($reg);
3977 index(0x4);
3978 scale(0x0);
3979 disp($off);
3980 %}
3981 %}
3982
3983 // Indirect Memory Plus Long Offset Operand
3984 operand indOffset32Narrow(rRegN reg, immL32 off)
3985 %{
3986 predicate(Universe::narrow_oop_shift() == 0);
3987 constraint(ALLOC_IN_RC(ptr_reg));
3988 match(AddP (DecodeN reg) off);
3989
3990 format %{ "[$reg + $off (32-bit)]" %}
3991 interface(MEMORY_INTER) %{
3992 base($reg);
3993 index(0x4);
3994 scale(0x0);
3995 disp($off);
3996 %}
3997 %}
3998
3999 // Indirect Memory Plus Index Register Plus Offset Operand
4000 operand indIndexOffsetNarrow(rRegN reg, rRegL lreg, immL32 off)
4001 %{
4002 predicate(Universe::narrow_oop_shift() == 0);
4003 constraint(ALLOC_IN_RC(ptr_reg));
4004 match(AddP (AddP (DecodeN reg) lreg) off);
4005
4006 op_cost(10);
4007 format %{"[$reg + $off + $lreg]" %}
4008 interface(MEMORY_INTER) %{
4009 base($reg);
4010 index($lreg);
4011 scale(0x0);
4012 disp($off);
4013 %}
4014 %}
4015
4016 // Indirect Memory Plus Index Register Plus Offset Operand
4017 operand indIndexNarrow(rRegN reg, rRegL lreg)
4018 %{
4019 predicate(Universe::narrow_oop_shift() == 0);
4020 constraint(ALLOC_IN_RC(ptr_reg));
4021 match(AddP (DecodeN reg) lreg);
4022
4023 op_cost(10);
4024 format %{"[$reg + $lreg]" %}
4025 interface(MEMORY_INTER) %{
4026 base($reg);
4027 index($lreg);
4028 scale(0x0);
4029 disp(0x0);
4030 %}
4031 %}
4032
4033 // Indirect Memory Times Scale Plus Index Register
4034 operand indIndexScaleNarrow(rRegN reg, rRegL lreg, immI2 scale)
4035 %{
4036 predicate(Universe::narrow_oop_shift() == 0);
4037 constraint(ALLOC_IN_RC(ptr_reg));
4038 match(AddP (DecodeN reg) (LShiftL lreg scale));
4039
4040 op_cost(10);
4041 format %{"[$reg + $lreg << $scale]" %}
4042 interface(MEMORY_INTER) %{
4043 base($reg);
4044 index($lreg);
4045 scale($scale);
4046 disp(0x0);
4047 %}
4048 %}
4049
4050 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4051 operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale)
4052 %{
4053 predicate(Universe::narrow_oop_shift() == 0);
4054 constraint(ALLOC_IN_RC(ptr_reg));
4055 match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off);
4056
4057 op_cost(10);
4058 format %{"[$reg + $off + $lreg << $scale]" %}
4059 interface(MEMORY_INTER) %{
4060 base($reg);
4061 index($lreg);
4062 scale($scale);
4063 disp($off);
4064 %}
4065 %}
4066
4067 // Indirect Memory Times Plus Positive Index Register Plus Offset Operand
4068 operand indPosIndexOffsetNarrow(rRegN reg, immL32 off, rRegI idx)
4069 %{
4070 constraint(ALLOC_IN_RC(ptr_reg));
4071 predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
4072 match(AddP (AddP (DecodeN reg) (ConvI2L idx)) off);
4073
4074 op_cost(10);
4075 format %{"[$reg + $off + $idx]" %}
4076 interface(MEMORY_INTER) %{
4077 base($reg);
4078 index($idx);
4079 scale(0x0);
4080 disp($off);
4081 %}
4082 %}
4083
4084 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
4085 operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale)
4086 %{
4087 constraint(ALLOC_IN_RC(ptr_reg));
4088 predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
4089 match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off);
4090
4091 op_cost(10);
4092 format %{"[$reg + $off + $idx << $scale]" %}
4093 interface(MEMORY_INTER) %{
4094 base($reg);
4095 index($idx);
4096 scale($scale);
4097 disp($off);
4098 %}
4099 %}
4100
4101 //----------Special Memory Operands--------------------------------------------
4102 // Stack Slot Operand - This operand is used for loading and storing temporary
4103 // values on the stack where a match requires a value to
4104 // flow through memory.
4105 operand stackSlotP(sRegP reg)
4106 %{
4107 constraint(ALLOC_IN_RC(stack_slots));
4108 // No match rule because this operand is only generated in matching
4109
4110 format %{ "[$reg]" %}
4111 interface(MEMORY_INTER) %{
4112 base(0x4); // RSP
4113 index(0x4); // No Index
4114 scale(0x0); // No Scale
4115 disp($reg); // Stack Offset
4116 %}
4117 %}
4118
4119 operand stackSlotI(sRegI reg)
4120 %{
4121 constraint(ALLOC_IN_RC(stack_slots));
4122 // No match rule because this operand is only generated in matching
4123
4124 format %{ "[$reg]" %}
4125 interface(MEMORY_INTER) %{
4126 base(0x4); // RSP
4127 index(0x4); // No Index
4128 scale(0x0); // No Scale
4129 disp($reg); // Stack Offset
4130 %}
4131 %}
4132
4133 operand stackSlotF(sRegF reg)
4134 %{
4135 constraint(ALLOC_IN_RC(stack_slots));
4136 // No match rule because this operand is only generated in matching
4137
4138 format %{ "[$reg]" %}
4139 interface(MEMORY_INTER) %{
4140 base(0x4); // RSP
4141 index(0x4); // No Index
4142 scale(0x0); // No Scale
4143 disp($reg); // Stack Offset
4144 %}
4145 %}
4146
4147 operand stackSlotD(sRegD reg)
4148 %{
4149 constraint(ALLOC_IN_RC(stack_slots));
4150 // No match rule because this operand is only generated in matching
4151
4152 format %{ "[$reg]" %}
4153 interface(MEMORY_INTER) %{
4154 base(0x4); // RSP
4155 index(0x4); // No Index
4156 scale(0x0); // No Scale
4157 disp($reg); // Stack Offset
4158 %}
4159 %}
4160 operand stackSlotL(sRegL reg)
4161 %{
4162 constraint(ALLOC_IN_RC(stack_slots));
4163 // No match rule because this operand is only generated in matching
4164
4165 format %{ "[$reg]" %}
4166 interface(MEMORY_INTER) %{
4167 base(0x4); // RSP
4168 index(0x4); // No Index
4169 scale(0x0); // No Scale
4170 disp($reg); // Stack Offset
4171 %}
4172 %}
4173
4174 //----------Conditional Branch Operands----------------------------------------
4175 // Comparison Op - This is the operation of the comparison, and is limited to
4176 // the following set of codes:
4177 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4178 //
4179 // Other attributes of the comparison, such as unsignedness, are specified
4180 // by the comparison instruction that sets a condition code flags register.
4181 // That result is represented by a flags operand whose subtype is appropriate
4182 // to the unsignedness (etc.) of the comparison.
4183 //
4184 // Later, the instruction which matches both the Comparison Op (a Bool) and
4185 // the flags (produced by the Cmp) specifies the coding of the comparison op
4186 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4187
4188 // Comparision Code
4189 operand cmpOp()
4190 %{
4191 match(Bool);
4192
4193 format %{ "" %}
4194 interface(COND_INTER) %{
4195 equal(0x4, "e");
4196 not_equal(0x5, "ne");
4197 less(0xC, "l");
4198 greater_equal(0xD, "ge");
4199 less_equal(0xE, "le");
4200 greater(0xF, "g");
4201 overflow(0x0, "o");
4202 no_overflow(0x1, "no");
4203 %}
4204 %}
4205
4206 // Comparison Code, unsigned compare. Used by FP also, with
4207 // C2 (unordered) turned into GT or LT already. The other bits
4208 // C0 and C3 are turned into Carry & Zero flags.
4209 operand cmpOpU()
4210 %{
4211 match(Bool);
4212
4213 format %{ "" %}
4214 interface(COND_INTER) %{
4215 equal(0x4, "e");
4216 not_equal(0x5, "ne");
4217 less(0x2, "b");
4218 greater_equal(0x3, "nb");
4219 less_equal(0x6, "be");
4220 greater(0x7, "nbe");
4221 overflow(0x0, "o");
4222 no_overflow(0x1, "no");
4223 %}
4224 %}
4225
4226
4227 // Floating comparisons that don't require any fixup for the unordered case
4228 operand cmpOpUCF() %{
4229 match(Bool);
4230 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
4231 n->as_Bool()->_test._test == BoolTest::ge ||
4232 n->as_Bool()->_test._test == BoolTest::le ||
4233 n->as_Bool()->_test._test == BoolTest::gt);
4234 format %{ "" %}
4235 interface(COND_INTER) %{
4236 equal(0x4, "e");
4237 not_equal(0x5, "ne");
4238 less(0x2, "b");
4239 greater_equal(0x3, "nb");
4240 less_equal(0x6, "be");
4241 greater(0x7, "nbe");
4242 overflow(0x0, "o");
4243 no_overflow(0x1, "no");
4244 %}
4245 %}
4246
4247
4248 // Floating comparisons that can be fixed up with extra conditional jumps
4249 operand cmpOpUCF2() %{
4250 match(Bool);
4251 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
4252 n->as_Bool()->_test._test == BoolTest::eq);
4253 format %{ "" %}
4254 interface(COND_INTER) %{
4255 equal(0x4, "e");
4256 not_equal(0x5, "ne");
4257 less(0x2, "b");
4258 greater_equal(0x3, "nb");
4259 less_equal(0x6, "be");
4260 greater(0x7, "nbe");
4261 overflow(0x0, "o");
4262 no_overflow(0x1, "no");
4263 %}
4264 %}
4265
4266 // Operands for bound floating pointer register arguments
4267 operand rxmm0() %{
4268 constraint(ALLOC_IN_RC(xmm0_reg)); match(VecX);
4269 predicate((UseSSE > 0) && (UseAVX<= 2)); format%{%} interface(REG_INTER);
4270 %}
4271 operand rxmm1() %{
4272 constraint(ALLOC_IN_RC(xmm1_reg)); match(VecX);
4273 predicate((UseSSE > 0) && (UseAVX <= 2)); format%{%} interface(REG_INTER);
4274 %}
4275 operand rxmm2() %{
4276 constraint(ALLOC_IN_RC(xmm2_reg)); match(VecX);
4277 predicate((UseSSE > 0) && (UseAVX <= 2)); format%{%} interface(REG_INTER);
4278 %}
4279 operand rxmm3() %{
4280 constraint(ALLOC_IN_RC(xmm3_reg)); match(VecX);
4281 predicate((UseSSE > 0) && (UseAVX <= 2)); format%{%} interface(REG_INTER);
4282 %}
4283 operand rxmm4() %{
4284 constraint(ALLOC_IN_RC(xmm4_reg)); match(VecX);
4285 predicate((UseSSE > 0) && (UseAVX <= 2)); format%{%} interface(REG_INTER);
4286 %}
4287 operand rxmm5() %{
4288 constraint(ALLOC_IN_RC(xmm5_reg)); match(VecX);
4289 predicate((UseSSE > 0) && (UseAVX <= 2)); format%{%} interface(REG_INTER);
4290 %}
4291 operand rxmm6() %{
4292 constraint(ALLOC_IN_RC(xmm6_reg)); match(VecX);
4293 predicate((UseSSE > 0) && (UseAVX <= 2)); format%{%} interface(REG_INTER);
4294 %}
4295 operand rxmm7() %{
4296 constraint(ALLOC_IN_RC(xmm7_reg)); match(VecX);
4297 predicate((UseSSE > 0) && (UseAVX <= 2)); format%{%} interface(REG_INTER);
4298 %}
4299 operand rxmm8() %{
4300 constraint(ALLOC_IN_RC(xmm8_reg)); match(VecX);
4301 predicate((UseSSE > 0) && (UseAVX <= 2)); format%{%} interface(REG_INTER);
4302 %}
4303 operand rxmm9() %{
4304 constraint(ALLOC_IN_RC(xmm9_reg)); match(VecX);
4305 predicate((UseSSE > 0) && (UseAVX <= 2)); format%{%} interface(REG_INTER);
4306 %}
4307 operand rxmm10() %{
4308 constraint(ALLOC_IN_RC(xmm10_reg)); match(VecX);
4309 predicate((UseSSE > 0) && (UseAVX <= 2)); format%{%} interface(REG_INTER);
4310 %}
4311 operand rxmm11() %{
4312 constraint(ALLOC_IN_RC(xmm11_reg)); match(VecX);
4313 predicate((UseSSE > 0) && (UseAVX <= 2)); format%{%} interface(REG_INTER);
4314 %}
4315 operand rxmm12() %{
4316 constraint(ALLOC_IN_RC(xmm12_reg)); match(VecX);
4317 predicate((UseSSE > 0) && (UseAVX <= 2)); format%{%} interface(REG_INTER);
4318 %}
4319 operand rxmm13() %{
4320 constraint(ALLOC_IN_RC(xmm13_reg)); match(VecX);
4321 predicate((UseSSE > 0) && (UseAVX <= 2)); format%{%} interface(REG_INTER);
4322 %}
4323 operand rxmm14() %{
4324 constraint(ALLOC_IN_RC(xmm14_reg)); match(VecX);
4325 predicate((UseSSE > 0) && (UseAVX <= 2)); format%{%} interface(REG_INTER);
4326 %}
4327 operand rxmm15() %{
4328 constraint(ALLOC_IN_RC(xmm15_reg)); match(VecX);
4329 predicate((UseSSE > 0) && (UseAVX <= 2)); format%{%} interface(REG_INTER);
4330 %}
4331 operand rxmm16() %{
4332 constraint(ALLOC_IN_RC(xmm16_reg)); match(VecX);
4333 predicate(UseAVX == 3); format%{%} interface(REG_INTER);
4334 %}
4335 operand rxmm17() %{
4336 constraint(ALLOC_IN_RC(xmm17_reg)); match(VecX);
4337 predicate(UseAVX == 3); format%{%} interface(REG_INTER);
4338 %}
4339 operand rxmm18() %{
4340 constraint(ALLOC_IN_RC(xmm18_reg)); match(VecX);
4341 predicate(UseAVX == 3); format%{%} interface(REG_INTER);
4342 %}
4343 operand rxmm19() %{
4344 constraint(ALLOC_IN_RC(xmm19_reg)); match(VecX);
4345 predicate(UseAVX == 3); format%{%} interface(REG_INTER);
4346 %}
4347 operand rxmm20() %{
4348 constraint(ALLOC_IN_RC(xmm20_reg)); match(VecX);
4349 predicate(UseAVX == 3); format%{%} interface(REG_INTER);
4350 %}
4351 operand rxmm21() %{
4352 constraint(ALLOC_IN_RC(xmm21_reg)); match(VecX);
4353 predicate(UseAVX == 3); format%{%} interface(REG_INTER);
4354 %}
4355 operand rxmm22() %{
4356 constraint(ALLOC_IN_RC(xmm22_reg)); match(VecX);
4357 predicate(UseAVX == 3); format%{%} interface(REG_INTER);
4358 %}
4359 operand rxmm23() %{
4360 constraint(ALLOC_IN_RC(xmm23_reg)); match(VecX);
4361 predicate(UseAVX == 3); format%{%} interface(REG_INTER);
4362 %}
4363 operand rxmm24() %{
4364 constraint(ALLOC_IN_RC(xmm24_reg)); match(VecX);
4365 predicate(UseAVX == 3); format%{%} interface(REG_INTER);
4366 %}
4367 operand rxmm25() %{
4368 constraint(ALLOC_IN_RC(xmm25_reg)); match(VecX);
4369 predicate(UseAVX == 3); format%{%} interface(REG_INTER);
4370 %}
4371 operand rxmm26() %{
4372 constraint(ALLOC_IN_RC(xmm26_reg)); match(VecX);
4373 predicate(UseAVX == 3); format%{%} interface(REG_INTER);
4374 %}
4375 operand rxmm27() %{
4376 constraint(ALLOC_IN_RC(xmm27_reg)); match(VecX);
4377 predicate(UseAVX == 3); format%{%} interface(REG_INTER);
4378 %}
4379 operand rxmm28() %{
4380 constraint(ALLOC_IN_RC(xmm28_reg)); match(VecX);
4381 predicate(UseAVX == 3); format%{%} interface(REG_INTER);
4382 %}
4383 operand rxmm29() %{
4384 constraint(ALLOC_IN_RC(xmm29_reg)); match(VecX);
4385 predicate(UseAVX == 3); format%{%} interface(REG_INTER);
4386 %}
4387 operand rxmm30() %{
4388 constraint(ALLOC_IN_RC(xmm30_reg)); match(VecX);
4389 predicate(UseAVX == 3); format%{%} interface(REG_INTER);
4390 %}
4391 operand rxmm31() %{
4392 constraint(ALLOC_IN_RC(xmm31_reg)); match(VecX);
4393 predicate(UseAVX == 3); format%{%} interface(REG_INTER);
4394 %}
4395
4396 //----------OPERAND CLASSES----------------------------------------------------
4397 // Operand Classes are groups of operands that are used as to simplify
4398 // instruction definitions by not requiring the AD writer to specify separate
4399 // instructions for every form of operand when the instruction accepts
4400 // multiple operand types with the same basic encoding and format. The classic
4401 // case of this is memory operands.
4402
4403 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex,
4404 indIndexScale, indPosIndexScale, indIndexScaleOffset, indPosIndexOffset, indPosIndexScaleOffset,
4405 indCompressedOopOffset,
4406 indirectNarrow, indOffset8Narrow, indOffset32Narrow,
4407 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow,
4408 indIndexScaleOffsetNarrow, indPosIndexOffsetNarrow, indPosIndexScaleOffsetNarrow);
4409
4410 //----------PIPELINE-----------------------------------------------------------
4411 // Rules which define the behavior of the target architectures pipeline.
4412 pipeline %{
4413
4414 //----------ATTRIBUTES---------------------------------------------------------
4415 attributes %{
4416 variable_size_instructions; // Fixed size instructions
4417 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
4418 instruction_unit_size = 1; // An instruction is 1 bytes long
4419 instruction_fetch_unit_size = 16; // The processor fetches one line
4420 instruction_fetch_units = 1; // of 16 bytes
4421
4422 // List of nop instructions
4423 nops( MachNop );
4424 %}
4425
4426 //----------RESOURCES----------------------------------------------------------
4427 // Resources are the functional units available to the machine
4428
4429 // Generic P2/P3 pipeline
4430 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
4431 // 3 instructions decoded per cycle.
4432 // 2 load/store ops per cycle, 1 branch, 1 FPU,
4433 // 3 ALU op, only ALU0 handles mul instructions.
4434 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
4435 MS0, MS1, MS2, MEM = MS0 | MS1 | MS2,
4436 BR, FPU,
4437 ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2);
4438
4439 //----------PIPELINE DESCRIPTION-----------------------------------------------
4440 // Pipeline Description specifies the stages in the machine's pipeline
4441
4442 // Generic P2/P3 pipeline
4443 pipe_desc(S0, S1, S2, S3, S4, S5);
4444
4445 //----------PIPELINE CLASSES---------------------------------------------------
4446 // Pipeline Classes describe the stages in which input and output are
4447 // referenced by the hardware pipeline.
4448
4449 // Naming convention: ialu or fpu
4450 // Then: _reg
4451 // Then: _reg if there is a 2nd register
4452 // Then: _long if it's a pair of instructions implementing a long
4453 // Then: _fat if it requires the big decoder
4454 // Or: _mem if it requires the big decoder and a memory unit.
4455
4456 // Integer ALU reg operation
4457 pipe_class ialu_reg(rRegI dst)
4458 %{
4459 single_instruction;
4460 dst : S4(write);
4461 dst : S3(read);
4462 DECODE : S0; // any decoder
4463 ALU : S3; // any alu
4464 %}
4465
4466 // Long ALU reg operation
4467 pipe_class ialu_reg_long(rRegL dst)
4468 %{
4469 instruction_count(2);
4470 dst : S4(write);
4471 dst : S3(read);
4472 DECODE : S0(2); // any 2 decoders
4473 ALU : S3(2); // both alus
4474 %}
4475
4476 // Integer ALU reg operation using big decoder
4477 pipe_class ialu_reg_fat(rRegI dst)
4478 %{
4479 single_instruction;
4480 dst : S4(write);
4481 dst : S3(read);
4482 D0 : S0; // big decoder only
4483 ALU : S3; // any alu
4484 %}
4485
4486 // Long ALU reg operation using big decoder
4487 pipe_class ialu_reg_long_fat(rRegL dst)
4488 %{
4489 instruction_count(2);
4490 dst : S4(write);
4491 dst : S3(read);
4492 D0 : S0(2); // big decoder only; twice
4493 ALU : S3(2); // any 2 alus
4494 %}
4495
4496 // Integer ALU reg-reg operation
4497 pipe_class ialu_reg_reg(rRegI dst, rRegI src)
4498 %{
4499 single_instruction;
4500 dst : S4(write);
4501 src : S3(read);
4502 DECODE : S0; // any decoder
4503 ALU : S3; // any alu
4504 %}
4505
4506 // Long ALU reg-reg operation
4507 pipe_class ialu_reg_reg_long(rRegL dst, rRegL src)
4508 %{
4509 instruction_count(2);
4510 dst : S4(write);
4511 src : S3(read);
4512 DECODE : S0(2); // any 2 decoders
4513 ALU : S3(2); // both alus
4514 %}
4515
4516 // Integer ALU reg-reg operation
4517 pipe_class ialu_reg_reg_fat(rRegI dst, memory src)
4518 %{
4519 single_instruction;
4520 dst : S4(write);
4521 src : S3(read);
4522 D0 : S0; // big decoder only
4523 ALU : S3; // any alu
4524 %}
4525
4526 // Long ALU reg-reg operation
4527 pipe_class ialu_reg_reg_long_fat(rRegL dst, rRegL src)
4528 %{
4529 instruction_count(2);
4530 dst : S4(write);
4531 src : S3(read);
4532 D0 : S0(2); // big decoder only; twice
4533 ALU : S3(2); // both alus
4534 %}
4535
4536 // Integer ALU reg-mem operation
4537 pipe_class ialu_reg_mem(rRegI dst, memory mem)
4538 %{
4539 single_instruction;
4540 dst : S5(write);
4541 mem : S3(read);
4542 D0 : S0; // big decoder only
4543 ALU : S4; // any alu
4544 MEM : S3; // any mem
4545 %}
4546
4547 // Integer mem operation (prefetch)
4548 pipe_class ialu_mem(memory mem)
4549 %{
4550 single_instruction;
4551 mem : S3(read);
4552 D0 : S0; // big decoder only
4553 MEM : S3; // any mem
4554 %}
4555
4556 // Integer Store to Memory
4557 pipe_class ialu_mem_reg(memory mem, rRegI src)
4558 %{
4559 single_instruction;
4560 mem : S3(read);
4561 src : S5(read);
4562 D0 : S0; // big decoder only
4563 ALU : S4; // any alu
4564 MEM : S3;
4565 %}
4566
4567 // // Long Store to Memory
4568 // pipe_class ialu_mem_long_reg(memory mem, rRegL src)
4569 // %{
4570 // instruction_count(2);
4571 // mem : S3(read);
4572 // src : S5(read);
4573 // D0 : S0(2); // big decoder only; twice
4574 // ALU : S4(2); // any 2 alus
4575 // MEM : S3(2); // Both mems
4576 // %}
4577
4578 // Integer Store to Memory
4579 pipe_class ialu_mem_imm(memory mem)
4580 %{
4581 single_instruction;
4582 mem : S3(read);
4583 D0 : S0; // big decoder only
4584 ALU : S4; // any alu
4585 MEM : S3;
4586 %}
4587
4588 // Integer ALU0 reg-reg operation
4589 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src)
4590 %{
4591 single_instruction;
4592 dst : S4(write);
4593 src : S3(read);
4594 D0 : S0; // Big decoder only
4595 ALU0 : S3; // only alu0
4596 %}
4597
4598 // Integer ALU0 reg-mem operation
4599 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem)
4600 %{
4601 single_instruction;
4602 dst : S5(write);
4603 mem : S3(read);
4604 D0 : S0; // big decoder only
4605 ALU0 : S4; // ALU0 only
4606 MEM : S3; // any mem
4607 %}
4608
4609 // Integer ALU reg-reg operation
4610 pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2)
4611 %{
4612 single_instruction;
4613 cr : S4(write);
4614 src1 : S3(read);
4615 src2 : S3(read);
4616 DECODE : S0; // any decoder
4617 ALU : S3; // any alu
4618 %}
4619
4620 // Integer ALU reg-imm operation
4621 pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1)
4622 %{
4623 single_instruction;
4624 cr : S4(write);
4625 src1 : S3(read);
4626 DECODE : S0; // any decoder
4627 ALU : S3; // any alu
4628 %}
4629
4630 // Integer ALU reg-mem operation
4631 pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2)
4632 %{
4633 single_instruction;
4634 cr : S4(write);
4635 src1 : S3(read);
4636 src2 : S3(read);
4637 D0 : S0; // big decoder only
4638 ALU : S4; // any alu
4639 MEM : S3;
4640 %}
4641
4642 // Conditional move reg-reg
4643 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y)
4644 %{
4645 instruction_count(4);
4646 y : S4(read);
4647 q : S3(read);
4648 p : S3(read);
4649 DECODE : S0(4); // any decoder
4650 %}
4651
4652 // Conditional move reg-reg
4653 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr)
4654 %{
4655 single_instruction;
4656 dst : S4(write);
4657 src : S3(read);
4658 cr : S3(read);
4659 DECODE : S0; // any decoder
4660 %}
4661
4662 // Conditional move reg-mem
4663 pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src)
4664 %{
4665 single_instruction;
4666 dst : S4(write);
4667 src : S3(read);
4668 cr : S3(read);
4669 DECODE : S0; // any decoder
4670 MEM : S3;
4671 %}
4672
4673 // Conditional move reg-reg long
4674 pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src)
4675 %{
4676 single_instruction;
4677 dst : S4(write);
4678 src : S3(read);
4679 cr : S3(read);
4680 DECODE : S0(2); // any 2 decoders
4681 %}
4682
4683 // XXX
4684 // // Conditional move double reg-reg
4685 // pipe_class pipe_cmovD_reg( rFlagsReg cr, regDPR1 dst, regD src)
4686 // %{
4687 // single_instruction;
4688 // dst : S4(write);
4689 // src : S3(read);
4690 // cr : S3(read);
4691 // DECODE : S0; // any decoder
4692 // %}
4693
4694 // Float reg-reg operation
4695 pipe_class fpu_reg(regD dst)
4696 %{
4697 instruction_count(2);
4698 dst : S3(read);
4699 DECODE : S0(2); // any 2 decoders
4700 FPU : S3;
4701 %}
4702
4703 // Float reg-reg operation
4704 pipe_class fpu_reg_reg(regD dst, regD src)
4705 %{
4706 instruction_count(2);
4707 dst : S4(write);
4708 src : S3(read);
4709 DECODE : S0(2); // any 2 decoders
4710 FPU : S3;
4711 %}
4712
4713 // Float reg-reg operation
4714 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2)
4715 %{
4716 instruction_count(3);
4717 dst : S4(write);
4718 src1 : S3(read);
4719 src2 : S3(read);
4720 DECODE : S0(3); // any 3 decoders
4721 FPU : S3(2);
4722 %}
4723
4724 // Float reg-reg operation
4725 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3)
4726 %{
4727 instruction_count(4);
4728 dst : S4(write);
4729 src1 : S3(read);
4730 src2 : S3(read);
4731 src3 : S3(read);
4732 DECODE : S0(4); // any 3 decoders
4733 FPU : S3(2);
4734 %}
4735
4736 // Float reg-reg operation
4737 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3)
4738 %{
4739 instruction_count(4);
4740 dst : S4(write);
4741 src1 : S3(read);
4742 src2 : S3(read);
4743 src3 : S3(read);
4744 DECODE : S1(3); // any 3 decoders
4745 D0 : S0; // Big decoder only
4746 FPU : S3(2);
4747 MEM : S3;
4748 %}
4749
4750 // Float reg-mem operation
4751 pipe_class fpu_reg_mem(regD dst, memory mem)
4752 %{
4753 instruction_count(2);
4754 dst : S5(write);
4755 mem : S3(read);
4756 D0 : S0; // big decoder only
4757 DECODE : S1; // any decoder for FPU POP
4758 FPU : S4;
4759 MEM : S3; // any mem
4760 %}
4761
4762 // Float reg-mem operation
4763 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem)
4764 %{
4765 instruction_count(3);
4766 dst : S5(write);
4767 src1 : S3(read);
4768 mem : S3(read);
4769 D0 : S0; // big decoder only
4770 DECODE : S1(2); // any decoder for FPU POP
4771 FPU : S4;
4772 MEM : S3; // any mem
4773 %}
4774
4775 // Float mem-reg operation
4776 pipe_class fpu_mem_reg(memory mem, regD src)
4777 %{
4778 instruction_count(2);
4779 src : S5(read);
4780 mem : S3(read);
4781 DECODE : S0; // any decoder for FPU PUSH
4782 D0 : S1; // big decoder only
4783 FPU : S4;
4784 MEM : S3; // any mem
4785 %}
4786
4787 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2)
4788 %{
4789 instruction_count(3);
4790 src1 : S3(read);
4791 src2 : S3(read);
4792 mem : S3(read);
4793 DECODE : S0(2); // any decoder for FPU PUSH
4794 D0 : S1; // big decoder only
4795 FPU : S4;
4796 MEM : S3; // any mem
4797 %}
4798
4799 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2)
4800 %{
4801 instruction_count(3);
4802 src1 : S3(read);
4803 src2 : S3(read);
4804 mem : S4(read);
4805 DECODE : S0; // any decoder for FPU PUSH
4806 D0 : S0(2); // big decoder only
4807 FPU : S4;
4808 MEM : S3(2); // any mem
4809 %}
4810
4811 pipe_class fpu_mem_mem(memory dst, memory src1)
4812 %{
4813 instruction_count(2);
4814 src1 : S3(read);
4815 dst : S4(read);
4816 D0 : S0(2); // big decoder only
4817 MEM : S3(2); // any mem
4818 %}
4819
4820 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2)
4821 %{
4822 instruction_count(3);
4823 src1 : S3(read);
4824 src2 : S3(read);
4825 dst : S4(read);
4826 D0 : S0(3); // big decoder only
4827 FPU : S4;
4828 MEM : S3(3); // any mem
4829 %}
4830
4831 pipe_class fpu_mem_reg_con(memory mem, regD src1)
4832 %{
4833 instruction_count(3);
4834 src1 : S4(read);
4835 mem : S4(read);
4836 DECODE : S0; // any decoder for FPU PUSH
4837 D0 : S0(2); // big decoder only
4838 FPU : S4;
4839 MEM : S3(2); // any mem
4840 %}
4841
4842 // Float load constant
4843 pipe_class fpu_reg_con(regD dst)
4844 %{
4845 instruction_count(2);
4846 dst : S5(write);
4847 D0 : S0; // big decoder only for the load
4848 DECODE : S1; // any decoder for FPU POP
4849 FPU : S4;
4850 MEM : S3; // any mem
4851 %}
4852
4853 // Float load constant
4854 pipe_class fpu_reg_reg_con(regD dst, regD src)
4855 %{
4856 instruction_count(3);
4857 dst : S5(write);
4858 src : S3(read);
4859 D0 : S0; // big decoder only for the load
4860 DECODE : S1(2); // any decoder for FPU POP
4861 FPU : S4;
4862 MEM : S3; // any mem
4863 %}
4864
4865 // UnConditional branch
4866 pipe_class pipe_jmp(label labl)
4867 %{
4868 single_instruction;
4869 BR : S3;
4870 %}
4871
4872 // Conditional branch
4873 pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl)
4874 %{
4875 single_instruction;
4876 cr : S1(read);
4877 BR : S3;
4878 %}
4879
4880 // Allocation idiom
4881 pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr)
4882 %{
4883 instruction_count(1); force_serialization;
4884 fixed_latency(6);
4885 heap_ptr : S3(read);
4886 DECODE : S0(3);
4887 D0 : S2;
4888 MEM : S3;
4889 ALU : S3(2);
4890 dst : S5(write);
4891 BR : S5;
4892 %}
4893
4894 // Generic big/slow expanded idiom
4895 pipe_class pipe_slow()
4896 %{
4897 instruction_count(10); multiple_bundles; force_serialization;
4898 fixed_latency(100);
4899 D0 : S0(2);
4900 MEM : S3(2);
4901 %}
4902
4903 // The real do-nothing guy
4904 pipe_class empty()
4905 %{
4906 instruction_count(0);
4907 %}
4908
4909 // Define the class for the Nop node
4910 define
4911 %{
4912 MachNop = empty;
4913 %}
4914
4915 %}
4916
4917 //----------INSTRUCTIONS-------------------------------------------------------
4918 //
4919 // match -- States which machine-independent subtree may be replaced
4920 // by this instruction.
4921 // ins_cost -- The estimated cost of this instruction is used by instruction
4922 // selection to identify a minimum cost tree of machine
4923 // instructions that matches a tree of machine-independent
4924 // instructions.
4925 // format -- A string providing the disassembly for this instruction.
4926 // The value of an instruction's operand may be inserted
4927 // by referring to it with a '$' prefix.
4928 // opcode -- Three instruction opcodes may be provided. These are referred
4929 // to within an encode class as $primary, $secondary, and $tertiary
4930 // rrspectively. The primary opcode is commonly used to
4931 // indicate the type of machine instruction, while secondary
4932 // and tertiary are often used for prefix options or addressing
4933 // modes.
4934 // ins_encode -- A list of encode classes with parameters. The encode class
4935 // name must have been defined in an 'enc_class' specification
4936 // in the encode section of the architecture description.
4937
4938
4939 //----------Load/Store/Move Instructions---------------------------------------
4940 //----------Load Instructions--------------------------------------------------
4941
4942 // Load Byte (8 bit signed)
4943 instruct loadB(rRegI dst, memory mem)
4944 %{
4945 match(Set dst (LoadB mem));
4946
4947 ins_cost(125);
4948 format %{ "movsbl $dst, $mem\t# byte" %}
4949
4950 ins_encode %{
4951 __ movsbl($dst$$Register, $mem$$Address);
4952 %}
4953
4954 ins_pipe(ialu_reg_mem);
4955 %}
4956
4957 // Load Byte (8 bit signed) into Long Register
4958 instruct loadB2L(rRegL dst, memory mem)
4959 %{
4960 match(Set dst (ConvI2L (LoadB mem)));
4961
4962 ins_cost(125);
4963 format %{ "movsbq $dst, $mem\t# byte -> long" %}
4964
4965 ins_encode %{
4966 __ movsbq($dst$$Register, $mem$$Address);
4967 %}
4968
4969 ins_pipe(ialu_reg_mem);
4970 %}
4971
4972 // Load Unsigned Byte (8 bit UNsigned)
4973 instruct loadUB(rRegI dst, memory mem)
4974 %{
4975 match(Set dst (LoadUB mem));
4976
4977 ins_cost(125);
4978 format %{ "movzbl $dst, $mem\t# ubyte" %}
4979
4980 ins_encode %{
4981 __ movzbl($dst$$Register, $mem$$Address);
4982 %}
4983
4984 ins_pipe(ialu_reg_mem);
4985 %}
4986
4987 // Load Unsigned Byte (8 bit UNsigned) into Long Register
4988 instruct loadUB2L(rRegL dst, memory mem)
4989 %{
4990 match(Set dst (ConvI2L (LoadUB mem)));
4991
4992 ins_cost(125);
4993 format %{ "movzbq $dst, $mem\t# ubyte -> long" %}
4994
4995 ins_encode %{
4996 __ movzbq($dst$$Register, $mem$$Address);
4997 %}
4998
4999 ins_pipe(ialu_reg_mem);
5000 %}
5001
5002 // Load Unsigned Byte (8 bit UNsigned) with 32-bit mask into Long Register
5003 instruct loadUB2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
5004 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5005 effect(KILL cr);
5006
5007 format %{ "movzbq $dst, $mem\t# ubyte & 32-bit mask -> long\n\t"
5008 "andl $dst, right_n_bits($mask, 8)" %}
5009 ins_encode %{
5010 Register Rdst = $dst$$Register;
5011 __ movzbq(Rdst, $mem$$Address);
5012 __ andl(Rdst, $mask$$constant & right_n_bits(8));
5013 %}
5014 ins_pipe(ialu_reg_mem);
5015 %}
5016
5017 // Load Short (16 bit signed)
5018 instruct loadS(rRegI dst, memory mem)
5019 %{
5020 match(Set dst (LoadS mem));
5021
5022 ins_cost(125);
5023 format %{ "movswl $dst, $mem\t# short" %}
5024
5025 ins_encode %{
5026 __ movswl($dst$$Register, $mem$$Address);
5027 %}
5028
5029 ins_pipe(ialu_reg_mem);
5030 %}
5031
5032 // Load Short (16 bit signed) to Byte (8 bit signed)
5033 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5034 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5035
5036 ins_cost(125);
5037 format %{ "movsbl $dst, $mem\t# short -> byte" %}
5038 ins_encode %{
5039 __ movsbl($dst$$Register, $mem$$Address);
5040 %}
5041 ins_pipe(ialu_reg_mem);
5042 %}
5043
5044 // Load Short (16 bit signed) into Long Register
5045 instruct loadS2L(rRegL dst, memory mem)
5046 %{
5047 match(Set dst (ConvI2L (LoadS mem)));
5048
5049 ins_cost(125);
5050 format %{ "movswq $dst, $mem\t# short -> long" %}
5051
5052 ins_encode %{
5053 __ movswq($dst$$Register, $mem$$Address);
5054 %}
5055
5056 ins_pipe(ialu_reg_mem);
5057 %}
5058
5059 // Load Unsigned Short/Char (16 bit UNsigned)
5060 instruct loadUS(rRegI dst, memory mem)
5061 %{
5062 match(Set dst (LoadUS mem));
5063
5064 ins_cost(125);
5065 format %{ "movzwl $dst, $mem\t# ushort/char" %}
5066
5067 ins_encode %{
5068 __ movzwl($dst$$Register, $mem$$Address);
5069 %}
5070
5071 ins_pipe(ialu_reg_mem);
5072 %}
5073
5074 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5075 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5076 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5077
5078 ins_cost(125);
5079 format %{ "movsbl $dst, $mem\t# ushort -> byte" %}
5080 ins_encode %{
5081 __ movsbl($dst$$Register, $mem$$Address);
5082 %}
5083 ins_pipe(ialu_reg_mem);
5084 %}
5085
5086 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
5087 instruct loadUS2L(rRegL dst, memory mem)
5088 %{
5089 match(Set dst (ConvI2L (LoadUS mem)));
5090
5091 ins_cost(125);
5092 format %{ "movzwq $dst, $mem\t# ushort/char -> long" %}
5093
5094 ins_encode %{
5095 __ movzwq($dst$$Register, $mem$$Address);
5096 %}
5097
5098 ins_pipe(ialu_reg_mem);
5099 %}
5100
5101 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
5102 instruct loadUS2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
5103 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5104
5105 format %{ "movzbq $dst, $mem\t# ushort/char & 0xFF -> long" %}
5106 ins_encode %{
5107 __ movzbq($dst$$Register, $mem$$Address);
5108 %}
5109 ins_pipe(ialu_reg_mem);
5110 %}
5111
5112 // Load Unsigned Short/Char (16 bit UNsigned) with 32-bit mask into Long Register
5113 instruct loadUS2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
5114 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5115 effect(KILL cr);
5116
5117 format %{ "movzwq $dst, $mem\t# ushort/char & 32-bit mask -> long\n\t"
5118 "andl $dst, right_n_bits($mask, 16)" %}
5119 ins_encode %{
5120 Register Rdst = $dst$$Register;
5121 __ movzwq(Rdst, $mem$$Address);
5122 __ andl(Rdst, $mask$$constant & right_n_bits(16));
5123 %}
5124 ins_pipe(ialu_reg_mem);
5125 %}
5126
5127 // Load Integer
5128 instruct loadI(rRegI dst, memory mem)
5129 %{
5130 match(Set dst (LoadI mem));
5131
5132 ins_cost(125);
5133 format %{ "movl $dst, $mem\t# int" %}
5134
5135 ins_encode %{
5136 __ movl($dst$$Register, $mem$$Address);
5137 %}
5138
5139 ins_pipe(ialu_reg_mem);
5140 %}
5141
5142 // Load Integer (32 bit signed) to Byte (8 bit signed)
5143 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5144 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5145
5146 ins_cost(125);
5147 format %{ "movsbl $dst, $mem\t# int -> byte" %}
5148 ins_encode %{
5149 __ movsbl($dst$$Register, $mem$$Address);
5150 %}
5151 ins_pipe(ialu_reg_mem);
5152 %}
5153
5154 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
5155 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
5156 match(Set dst (AndI (LoadI mem) mask));
5157
5158 ins_cost(125);
5159 format %{ "movzbl $dst, $mem\t# int -> ubyte" %}
5160 ins_encode %{
5161 __ movzbl($dst$$Register, $mem$$Address);
5162 %}
5163 ins_pipe(ialu_reg_mem);
5164 %}
5165
5166 // Load Integer (32 bit signed) to Short (16 bit signed)
5167 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
5168 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5169
5170 ins_cost(125);
5171 format %{ "movswl $dst, $mem\t# int -> short" %}
5172 ins_encode %{
5173 __ movswl($dst$$Register, $mem$$Address);
5174 %}
5175 ins_pipe(ialu_reg_mem);
5176 %}
5177
5178 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
5179 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
5180 match(Set dst (AndI (LoadI mem) mask));
5181
5182 ins_cost(125);
5183 format %{ "movzwl $dst, $mem\t# int -> ushort/char" %}
5184 ins_encode %{
5185 __ movzwl($dst$$Register, $mem$$Address);
5186 %}
5187 ins_pipe(ialu_reg_mem);
5188 %}
5189
5190 // Load Integer into Long Register
5191 instruct loadI2L(rRegL dst, memory mem)
5192 %{
5193 match(Set dst (ConvI2L (LoadI mem)));
5194
5195 ins_cost(125);
5196 format %{ "movslq $dst, $mem\t# int -> long" %}
5197
5198 ins_encode %{
5199 __ movslq($dst$$Register, $mem$$Address);
5200 %}
5201
5202 ins_pipe(ialu_reg_mem);
5203 %}
5204
5205 // Load Integer with mask 0xFF into Long Register
5206 instruct loadI2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
5207 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5208
5209 format %{ "movzbq $dst, $mem\t# int & 0xFF -> long" %}
5210 ins_encode %{
5211 __ movzbq($dst$$Register, $mem$$Address);
5212 %}
5213 ins_pipe(ialu_reg_mem);
5214 %}
5215
5216 // Load Integer with mask 0xFFFF into Long Register
5217 instruct loadI2L_immI_65535(rRegL dst, memory mem, immI_65535 mask) %{
5218 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5219
5220 format %{ "movzwq $dst, $mem\t# int & 0xFFFF -> long" %}
5221 ins_encode %{
5222 __ movzwq($dst$$Register, $mem$$Address);
5223 %}
5224 ins_pipe(ialu_reg_mem);
5225 %}
5226
5227 // Load Integer with a 31-bit mask into Long Register
5228 instruct loadI2L_immU31(rRegL dst, memory mem, immU31 mask, rFlagsReg cr) %{
5229 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5230 effect(KILL cr);
5231
5232 format %{ "movl $dst, $mem\t# int & 31-bit mask -> long\n\t"
5233 "andl $dst, $mask" %}
5234 ins_encode %{
5235 Register Rdst = $dst$$Register;
5236 __ movl(Rdst, $mem$$Address);
5237 __ andl(Rdst, $mask$$constant);
5238 %}
5239 ins_pipe(ialu_reg_mem);
5240 %}
5241
5242 // Load Unsigned Integer into Long Register
5243 instruct loadUI2L(rRegL dst, memory mem, immL_32bits mask)
5244 %{
5245 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5246
5247 ins_cost(125);
5248 format %{ "movl $dst, $mem\t# uint -> long" %}
5249
5250 ins_encode %{
5251 __ movl($dst$$Register, $mem$$Address);
5252 %}
5253
5254 ins_pipe(ialu_reg_mem);
5255 %}
5256
5257 // Load Long
5258 instruct loadL(rRegL dst, memory mem)
5259 %{
5260 match(Set dst (LoadL mem));
5261
5262 ins_cost(125);
5263 format %{ "movq $dst, $mem\t# long" %}
5264
5265 ins_encode %{
5266 __ movq($dst$$Register, $mem$$Address);
5267 %}
5268
5269 ins_pipe(ialu_reg_mem); // XXX
5270 %}
5271
5272 // Load Range
5273 instruct loadRange(rRegI dst, memory mem)
5274 %{
5275 match(Set dst (LoadRange mem));
5276
5277 ins_cost(125); // XXX
5278 format %{ "movl $dst, $mem\t# range" %}
5279 opcode(0x8B);
5280 ins_encode(REX_reg_mem(dst, mem), OpcP, reg_mem(dst, mem));
5281 ins_pipe(ialu_reg_mem);
5282 %}
5283
5284 // Load Pointer
5285 instruct loadP(rRegP dst, memory mem)
5286 %{
5287 match(Set dst (LoadP mem));
5288
5289 ins_cost(125); // XXX
5290 format %{ "movq $dst, $mem\t# ptr" %}
5291 opcode(0x8B);
5292 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5293 ins_pipe(ialu_reg_mem); // XXX
5294 %}
5295
5296 // Load Compressed Pointer
5297 instruct loadN(rRegN dst, memory mem)
5298 %{
5299 match(Set dst (LoadN mem));
5300
5301 ins_cost(125); // XXX
5302 format %{ "movl $dst, $mem\t# compressed ptr" %}
5303 ins_encode %{
5304 __ movl($dst$$Register, $mem$$Address);
5305 %}
5306 ins_pipe(ialu_reg_mem); // XXX
5307 %}
5308
5309
5310 // Load Klass Pointer
5311 instruct loadKlass(rRegP dst, memory mem)
5312 %{
5313 match(Set dst (LoadKlass mem));
5314
5315 ins_cost(125); // XXX
5316 format %{ "movq $dst, $mem\t# class" %}
5317 opcode(0x8B);
5318 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5319 ins_pipe(ialu_reg_mem); // XXX
5320 %}
5321
5322 // Load narrow Klass Pointer
5323 instruct loadNKlass(rRegN dst, memory mem)
5324 %{
5325 match(Set dst (LoadNKlass mem));
5326
5327 ins_cost(125); // XXX
5328 format %{ "movl $dst, $mem\t# compressed klass ptr" %}
5329 ins_encode %{
5330 __ movl($dst$$Register, $mem$$Address);
5331 %}
5332 ins_pipe(ialu_reg_mem); // XXX
5333 %}
5334
5335 // Load Float
5336 instruct loadF(regF dst, memory mem)
5337 %{
5338 match(Set dst (LoadF mem));
5339
5340 ins_cost(145); // XXX
5341 format %{ "movss $dst, $mem\t# float" %}
5342 ins_encode %{
5343 __ movflt($dst$$XMMRegister, $mem$$Address);
5344 %}
5345 ins_pipe(pipe_slow); // XXX
5346 %}
5347
5348 // Load Float
5349 instruct MoveF2VL(vlRegF dst, regF src) %{
5350 match(Set dst src);
5351 format %{ "movss $dst,$src\t! load float (4 bytes)" %}
5352 ins_encode %{
5353 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
5354 %}
5355 ins_pipe( fpu_reg_reg );
5356 %}
5357
5358 // Load Float
5359 instruct MoveVL2F(regF dst, vlRegF src) %{
5360 match(Set dst src);
5361 format %{ "movss $dst,$src\t! load float (4 bytes)" %}
5362 ins_encode %{
5363 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
5364 %}
5365 ins_pipe( fpu_reg_reg );
5366 %}
5367
5368 // Load Double
5369 instruct loadD_partial(regD dst, memory mem)
5370 %{
5371 predicate(!UseXmmLoadAndClearUpper);
5372 match(Set dst (LoadD mem));
5373
5374 ins_cost(145); // XXX
5375 format %{ "movlpd $dst, $mem\t# double" %}
5376 ins_encode %{
5377 __ movdbl($dst$$XMMRegister, $mem$$Address);
5378 %}
5379 ins_pipe(pipe_slow); // XXX
5380 %}
5381
5382 instruct loadD(regD dst, memory mem)
5383 %{
5384 predicate(UseXmmLoadAndClearUpper);
5385 match(Set dst (LoadD mem));
5386
5387 ins_cost(145); // XXX
5388 format %{ "movsd $dst, $mem\t# double" %}
5389 ins_encode %{
5390 __ movdbl($dst$$XMMRegister, $mem$$Address);
5391 %}
5392 ins_pipe(pipe_slow); // XXX
5393 %}
5394
5395 // Load Double
5396 instruct MoveD2VL(vlRegD dst, regD src) %{
5397 match(Set dst src);
5398 format %{ "movsd $dst,$src\t! load double (8 bytes)" %}
5399 ins_encode %{
5400 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
5401 %}
5402 ins_pipe( fpu_reg_reg );
5403 %}
5404
5405 // Load Double
5406 instruct MoveVL2D(regD dst, vlRegD src) %{
5407 match(Set dst src);
5408 format %{ "movsd $dst,$src\t! load double (8 bytes)" %}
5409 ins_encode %{
5410 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
5411 %}
5412 ins_pipe( fpu_reg_reg );
5413 %}
5414
5415 // Load Effective Address
5416 instruct leaP8(rRegP dst, indOffset8 mem)
5417 %{
5418 match(Set dst mem);
5419
5420 ins_cost(110); // XXX
5421 format %{ "leaq $dst, $mem\t# ptr 8" %}
5422 opcode(0x8D);
5423 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5424 ins_pipe(ialu_reg_reg_fat);
5425 %}
5426
5427 instruct leaP32(rRegP dst, indOffset32 mem)
5428 %{
5429 match(Set dst mem);
5430
5431 ins_cost(110);
5432 format %{ "leaq $dst, $mem\t# ptr 32" %}
5433 opcode(0x8D);
5434 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5435 ins_pipe(ialu_reg_reg_fat);
5436 %}
5437
5438 // instruct leaPIdx(rRegP dst, indIndex mem)
5439 // %{
5440 // match(Set dst mem);
5441
5442 // ins_cost(110);
5443 // format %{ "leaq $dst, $mem\t# ptr idx" %}
5444 // opcode(0x8D);
5445 // ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5446 // ins_pipe(ialu_reg_reg_fat);
5447 // %}
5448
5449 instruct leaPIdxOff(rRegP dst, indIndexOffset mem)
5450 %{
5451 match(Set dst mem);
5452
5453 ins_cost(110);
5454 format %{ "leaq $dst, $mem\t# ptr idxoff" %}
5455 opcode(0x8D);
5456 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5457 ins_pipe(ialu_reg_reg_fat);
5458 %}
5459
5460 instruct leaPIdxScale(rRegP dst, indIndexScale mem)
5461 %{
5462 match(Set dst mem);
5463
5464 ins_cost(110);
5465 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
5466 opcode(0x8D);
5467 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5468 ins_pipe(ialu_reg_reg_fat);
5469 %}
5470
5471 instruct leaPPosIdxScale(rRegP dst, indPosIndexScale mem)
5472 %{
5473 match(Set dst mem);
5474
5475 ins_cost(110);
5476 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
5477 opcode(0x8D);
5478 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5479 ins_pipe(ialu_reg_reg_fat);
5480 %}
5481
5482 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem)
5483 %{
5484 match(Set dst mem);
5485
5486 ins_cost(110);
5487 format %{ "leaq $dst, $mem\t# ptr idxscaleoff" %}
5488 opcode(0x8D);
5489 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5490 ins_pipe(ialu_reg_reg_fat);
5491 %}
5492
5493 instruct leaPPosIdxOff(rRegP dst, indPosIndexOffset mem)
5494 %{
5495 match(Set dst mem);
5496
5497 ins_cost(110);
5498 format %{ "leaq $dst, $mem\t# ptr posidxoff" %}
5499 opcode(0x8D);
5500 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5501 ins_pipe(ialu_reg_reg_fat);
5502 %}
5503
5504 instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem)
5505 %{
5506 match(Set dst mem);
5507
5508 ins_cost(110);
5509 format %{ "leaq $dst, $mem\t# ptr posidxscaleoff" %}
5510 opcode(0x8D);
5511 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5512 ins_pipe(ialu_reg_reg_fat);
5513 %}
5514
5515 // Load Effective Address which uses Narrow (32-bits) oop
5516 instruct leaPCompressedOopOffset(rRegP dst, indCompressedOopOffset mem)
5517 %{
5518 predicate(UseCompressedOops && (Universe::narrow_oop_shift() != 0));
5519 match(Set dst mem);
5520
5521 ins_cost(110);
5522 format %{ "leaq $dst, $mem\t# ptr compressedoopoff32" %}
5523 opcode(0x8D);
5524 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5525 ins_pipe(ialu_reg_reg_fat);
5526 %}
5527
5528 instruct leaP8Narrow(rRegP dst, indOffset8Narrow mem)
5529 %{
5530 predicate(Universe::narrow_oop_shift() == 0);
5531 match(Set dst mem);
5532
5533 ins_cost(110); // XXX
5534 format %{ "leaq $dst, $mem\t# ptr off8narrow" %}
5535 opcode(0x8D);
5536 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5537 ins_pipe(ialu_reg_reg_fat);
5538 %}
5539
5540 instruct leaP32Narrow(rRegP dst, indOffset32Narrow mem)
5541 %{
5542 predicate(Universe::narrow_oop_shift() == 0);
5543 match(Set dst mem);
5544
5545 ins_cost(110);
5546 format %{ "leaq $dst, $mem\t# ptr off32narrow" %}
5547 opcode(0x8D);
5548 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5549 ins_pipe(ialu_reg_reg_fat);
5550 %}
5551
5552 instruct leaPIdxOffNarrow(rRegP dst, indIndexOffsetNarrow mem)
5553 %{
5554 predicate(Universe::narrow_oop_shift() == 0);
5555 match(Set dst mem);
5556
5557 ins_cost(110);
5558 format %{ "leaq $dst, $mem\t# ptr idxoffnarrow" %}
5559 opcode(0x8D);
5560 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5561 ins_pipe(ialu_reg_reg_fat);
5562 %}
5563
5564 instruct leaPIdxScaleNarrow(rRegP dst, indIndexScaleNarrow mem)
5565 %{
5566 predicate(Universe::narrow_oop_shift() == 0);
5567 match(Set dst mem);
5568
5569 ins_cost(110);
5570 format %{ "leaq $dst, $mem\t# ptr idxscalenarrow" %}
5571 opcode(0x8D);
5572 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5573 ins_pipe(ialu_reg_reg_fat);
5574 %}
5575
5576 instruct leaPIdxScaleOffNarrow(rRegP dst, indIndexScaleOffsetNarrow mem)
5577 %{
5578 predicate(Universe::narrow_oop_shift() == 0);
5579 match(Set dst mem);
5580
5581 ins_cost(110);
5582 format %{ "leaq $dst, $mem\t# ptr idxscaleoffnarrow" %}
5583 opcode(0x8D);
5584 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5585 ins_pipe(ialu_reg_reg_fat);
5586 %}
5587
5588 instruct leaPPosIdxOffNarrow(rRegP dst, indPosIndexOffsetNarrow mem)
5589 %{
5590 predicate(Universe::narrow_oop_shift() == 0);
5591 match(Set dst mem);
5592
5593 ins_cost(110);
5594 format %{ "leaq $dst, $mem\t# ptr posidxoffnarrow" %}
5595 opcode(0x8D);
5596 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5597 ins_pipe(ialu_reg_reg_fat);
5598 %}
5599
5600 instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem)
5601 %{
5602 predicate(Universe::narrow_oop_shift() == 0);
5603 match(Set dst mem);
5604
5605 ins_cost(110);
5606 format %{ "leaq $dst, $mem\t# ptr posidxscaleoffnarrow" %}
5607 opcode(0x8D);
5608 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5609 ins_pipe(ialu_reg_reg_fat);
5610 %}
5611
5612 instruct loadConI(rRegI dst, immI src)
5613 %{
5614 match(Set dst src);
5615
5616 format %{ "movl $dst, $src\t# int" %}
5617 ins_encode(load_immI(dst, src));
5618 ins_pipe(ialu_reg_fat); // XXX
5619 %}
5620
5621 instruct loadConI0(rRegI dst, immI0 src, rFlagsReg cr)
5622 %{
5623 match(Set dst src);
5624 effect(KILL cr);
5625
5626 ins_cost(50);
5627 format %{ "xorl $dst, $dst\t# int" %}
5628 opcode(0x33); /* + rd */
5629 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5630 ins_pipe(ialu_reg);
5631 %}
5632
5633 instruct loadConL(rRegL dst, immL src)
5634 %{
5635 match(Set dst src);
5636
5637 ins_cost(150);
5638 format %{ "movq $dst, $src\t# long" %}
5639 ins_encode(load_immL(dst, src));
5640 ins_pipe(ialu_reg);
5641 %}
5642
5643 instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr)
5644 %{
5645 match(Set dst src);
5646 effect(KILL cr);
5647
5648 ins_cost(50);
5649 format %{ "xorl $dst, $dst\t# long" %}
5650 opcode(0x33); /* + rd */
5651 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5652 ins_pipe(ialu_reg); // XXX
5653 %}
5654
5655 instruct loadConUL32(rRegL dst, immUL32 src)
5656 %{
5657 match(Set dst src);
5658
5659 ins_cost(60);
5660 format %{ "movl $dst, $src\t# long (unsigned 32-bit)" %}
5661 ins_encode(load_immUL32(dst, src));
5662 ins_pipe(ialu_reg);
5663 %}
5664
5665 instruct loadConL32(rRegL dst, immL32 src)
5666 %{
5667 match(Set dst src);
5668
5669 ins_cost(70);
5670 format %{ "movq $dst, $src\t# long (32-bit)" %}
5671 ins_encode(load_immL32(dst, src));
5672 ins_pipe(ialu_reg);
5673 %}
5674
5675 instruct loadConP(rRegP dst, immP con) %{
5676 match(Set dst con);
5677
5678 format %{ "movq $dst, $con\t# ptr" %}
5679 ins_encode(load_immP(dst, con));
5680 ins_pipe(ialu_reg_fat); // XXX
5681 %}
5682
5683 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr)
5684 %{
5685 match(Set dst src);
5686 effect(KILL cr);
5687
5688 ins_cost(50);
5689 format %{ "xorl $dst, $dst\t# ptr" %}
5690 opcode(0x33); /* + rd */
5691 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5692 ins_pipe(ialu_reg);
5693 %}
5694
5695 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr)
5696 %{
5697 match(Set dst src);
5698 effect(KILL cr);
5699
5700 ins_cost(60);
5701 format %{ "movl $dst, $src\t# ptr (positive 32-bit)" %}
5702 ins_encode(load_immP31(dst, src));
5703 ins_pipe(ialu_reg);
5704 %}
5705
5706 instruct loadConF(regF dst, immF con) %{
5707 match(Set dst con);
5708 ins_cost(125);
5709 format %{ "movss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
5710 ins_encode %{
5711 __ movflt($dst$$XMMRegister, $constantaddress($con));
5712 %}
5713 ins_pipe(pipe_slow);
5714 %}
5715
5716 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{
5717 match(Set dst src);
5718 effect(KILL cr);
5719 format %{ "xorq $dst, $src\t# compressed NULL ptr" %}
5720 ins_encode %{
5721 __ xorq($dst$$Register, $dst$$Register);
5722 %}
5723 ins_pipe(ialu_reg);
5724 %}
5725
5726 instruct loadConN(rRegN dst, immN src) %{
5727 match(Set dst src);
5728
5729 ins_cost(125);
5730 format %{ "movl $dst, $src\t# compressed ptr" %}
5731 ins_encode %{
5732 address con = (address)$src$$constant;
5733 if (con == NULL) {
5734 ShouldNotReachHere();
5735 } else {
5736 __ set_narrow_oop($dst$$Register, (jobject)$src$$constant);
5737 }
5738 %}
5739 ins_pipe(ialu_reg_fat); // XXX
5740 %}
5741
5742 instruct loadConNKlass(rRegN dst, immNKlass src) %{
5743 match(Set dst src);
5744
5745 ins_cost(125);
5746 format %{ "movl $dst, $src\t# compressed klass ptr" %}
5747 ins_encode %{
5748 address con = (address)$src$$constant;
5749 if (con == NULL) {
5750 ShouldNotReachHere();
5751 } else {
5752 __ set_narrow_klass($dst$$Register, (Klass*)$src$$constant);
5753 }
5754 %}
5755 ins_pipe(ialu_reg_fat); // XXX
5756 %}
5757
5758 instruct loadConF0(regF dst, immF0 src)
5759 %{
5760 match(Set dst src);
5761 ins_cost(100);
5762
5763 format %{ "xorps $dst, $dst\t# float 0.0" %}
5764 ins_encode %{
5765 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
5766 %}
5767 ins_pipe(pipe_slow);
5768 %}
5769
5770 // Use the same format since predicate() can not be used here.
5771 instruct loadConD(regD dst, immD con) %{
5772 match(Set dst con);
5773 ins_cost(125);
5774 format %{ "movsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
5775 ins_encode %{
5776 __ movdbl($dst$$XMMRegister, $constantaddress($con));
5777 %}
5778 ins_pipe(pipe_slow);
5779 %}
5780
5781 instruct loadConD0(regD dst, immD0 src)
5782 %{
5783 match(Set dst src);
5784 ins_cost(100);
5785
5786 format %{ "xorpd $dst, $dst\t# double 0.0" %}
5787 ins_encode %{
5788 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
5789 %}
5790 ins_pipe(pipe_slow);
5791 %}
5792
5793 instruct loadSSI(rRegI dst, stackSlotI src)
5794 %{
5795 match(Set dst src);
5796
5797 ins_cost(125);
5798 format %{ "movl $dst, $src\t# int stk" %}
5799 opcode(0x8B);
5800 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
5801 ins_pipe(ialu_reg_mem);
5802 %}
5803
5804 instruct loadSSL(rRegL dst, stackSlotL src)
5805 %{
5806 match(Set dst src);
5807
5808 ins_cost(125);
5809 format %{ "movq $dst, $src\t# long stk" %}
5810 opcode(0x8B);
5811 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
5812 ins_pipe(ialu_reg_mem);
5813 %}
5814
5815 instruct loadSSP(rRegP dst, stackSlotP src)
5816 %{
5817 match(Set dst src);
5818
5819 ins_cost(125);
5820 format %{ "movq $dst, $src\t# ptr stk" %}
5821 opcode(0x8B);
5822 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
5823 ins_pipe(ialu_reg_mem);
5824 %}
5825
5826 instruct loadSSF(regF dst, stackSlotF src)
5827 %{
5828 match(Set dst src);
5829
5830 ins_cost(125);
5831 format %{ "movss $dst, $src\t# float stk" %}
5832 ins_encode %{
5833 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
5834 %}
5835 ins_pipe(pipe_slow); // XXX
5836 %}
5837
5838 // Use the same format since predicate() can not be used here.
5839 instruct loadSSD(regD dst, stackSlotD src)
5840 %{
5841 match(Set dst src);
5842
5843 ins_cost(125);
5844 format %{ "movsd $dst, $src\t# double stk" %}
5845 ins_encode %{
5846 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
5847 %}
5848 ins_pipe(pipe_slow); // XXX
5849 %}
5850
5851 // Prefetch instructions for allocation.
5852 // Must be safe to execute with invalid address (cannot fault).
5853
5854 instruct prefetchAlloc( memory mem ) %{
5855 predicate(AllocatePrefetchInstr==3);
5856 match(PrefetchAllocation mem);
5857 ins_cost(125);
5858
5859 format %{ "PREFETCHW $mem\t# Prefetch allocation into level 1 cache and mark modified" %}
5860 ins_encode %{
5861 __ prefetchw($mem$$Address);
5862 %}
5863 ins_pipe(ialu_mem);
5864 %}
5865
5866 instruct prefetchAllocNTA( memory mem ) %{
5867 predicate(AllocatePrefetchInstr==0);
5868 match(PrefetchAllocation mem);
5869 ins_cost(125);
5870
5871 format %{ "PREFETCHNTA $mem\t# Prefetch allocation to non-temporal cache for write" %}
5872 ins_encode %{
5873 __ prefetchnta($mem$$Address);
5874 %}
5875 ins_pipe(ialu_mem);
5876 %}
5877
5878 instruct prefetchAllocT0( memory mem ) %{
5879 predicate(AllocatePrefetchInstr==1);
5880 match(PrefetchAllocation mem);
5881 ins_cost(125);
5882
5883 format %{ "PREFETCHT0 $mem\t# Prefetch allocation to level 1 and 2 caches for write" %}
5884 ins_encode %{
5885 __ prefetcht0($mem$$Address);
5886 %}
5887 ins_pipe(ialu_mem);
5888 %}
5889
5890 instruct prefetchAllocT2( memory mem ) %{
5891 predicate(AllocatePrefetchInstr==2);
5892 match(PrefetchAllocation mem);
5893 ins_cost(125);
5894
5895 format %{ "PREFETCHT2 $mem\t# Prefetch allocation to level 2 cache for write" %}
5896 ins_encode %{
5897 __ prefetcht2($mem$$Address);
5898 %}
5899 ins_pipe(ialu_mem);
5900 %}
5901
5902 //----------Store Instructions-------------------------------------------------
5903
5904 // Store Byte
5905 instruct storeB(memory mem, rRegI src)
5906 %{
5907 match(Set mem (StoreB mem src));
5908
5909 ins_cost(125); // XXX
5910 format %{ "movb $mem, $src\t# byte" %}
5911 opcode(0x88);
5912 ins_encode(REX_breg_mem(src, mem), OpcP, reg_mem(src, mem));
5913 ins_pipe(ialu_mem_reg);
5914 %}
5915
5916 // Store Char/Short
5917 instruct storeC(memory mem, rRegI src)
5918 %{
5919 match(Set mem (StoreC mem src));
5920
5921 ins_cost(125); // XXX
5922 format %{ "movw $mem, $src\t# char/short" %}
5923 opcode(0x89);
5924 ins_encode(SizePrefix, REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
5925 ins_pipe(ialu_mem_reg);
5926 %}
5927
5928 // Store Integer
5929 instruct storeI(memory mem, rRegI src)
5930 %{
5931 match(Set mem (StoreI mem src));
5932
5933 ins_cost(125); // XXX
5934 format %{ "movl $mem, $src\t# int" %}
5935 opcode(0x89);
5936 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
5937 ins_pipe(ialu_mem_reg);
5938 %}
5939
5940 // Store Long
5941 instruct storeL(memory mem, rRegL src)
5942 %{
5943 match(Set mem (StoreL mem src));
5944
5945 ins_cost(125); // XXX
5946 format %{ "movq $mem, $src\t# long" %}
5947 opcode(0x89);
5948 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
5949 ins_pipe(ialu_mem_reg); // XXX
5950 %}
5951
5952 // Store Pointer
5953 instruct storeP(memory mem, any_RegP src)
5954 %{
5955 match(Set mem (StoreP mem src));
5956
5957 ins_cost(125); // XXX
5958 format %{ "movq $mem, $src\t# ptr" %}
5959 opcode(0x89);
5960 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
5961 ins_pipe(ialu_mem_reg);
5962 %}
5963
5964 instruct storeImmP0(memory mem, immP0 zero)
5965 %{
5966 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5967 match(Set mem (StoreP mem zero));
5968
5969 ins_cost(125); // XXX
5970 format %{ "movq $mem, R12\t# ptr (R12_heapbase==0)" %}
5971 ins_encode %{
5972 __ movq($mem$$Address, r12);
5973 %}
5974 ins_pipe(ialu_mem_reg);
5975 %}
5976
5977 // Store NULL Pointer, mark word, or other simple pointer constant.
5978 instruct storeImmP(memory mem, immP31 src)
5979 %{
5980 match(Set mem (StoreP mem src));
5981
5982 ins_cost(150); // XXX
5983 format %{ "movq $mem, $src\t# ptr" %}
5984 opcode(0xC7); /* C7 /0 */
5985 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
5986 ins_pipe(ialu_mem_imm);
5987 %}
5988
5989 // Store Compressed Pointer
5990 instruct storeN(memory mem, rRegN src)
5991 %{
5992 match(Set mem (StoreN mem src));
5993
5994 ins_cost(125); // XXX
5995 format %{ "movl $mem, $src\t# compressed ptr" %}
5996 ins_encode %{
5997 __ movl($mem$$Address, $src$$Register);
5998 %}
5999 ins_pipe(ialu_mem_reg);
6000 %}
6001
6002 instruct storeNKlass(memory mem, rRegN src)
6003 %{
6004 match(Set mem (StoreNKlass mem src));
6005
6006 ins_cost(125); // XXX
6007 format %{ "movl $mem, $src\t# compressed klass ptr" %}
6008 ins_encode %{
6009 __ movl($mem$$Address, $src$$Register);
6010 %}
6011 ins_pipe(ialu_mem_reg);
6012 %}
6013
6014 instruct storeImmN0(memory mem, immN0 zero)
6015 %{
6016 predicate(Universe::narrow_oop_base() == NULL && Universe::narrow_klass_base() == NULL);
6017 match(Set mem (StoreN mem zero));
6018
6019 ins_cost(125); // XXX
6020 format %{ "movl $mem, R12\t# compressed ptr (R12_heapbase==0)" %}
6021 ins_encode %{
6022 __ movl($mem$$Address, r12);
6023 %}
6024 ins_pipe(ialu_mem_reg);
6025 %}
6026
6027 instruct storeImmN(memory mem, immN src)
6028 %{
6029 match(Set mem (StoreN mem src));
6030
6031 ins_cost(150); // XXX
6032 format %{ "movl $mem, $src\t# compressed ptr" %}
6033 ins_encode %{
6034 address con = (address)$src$$constant;
6035 if (con == NULL) {
6036 __ movl($mem$$Address, (int32_t)0);
6037 } else {
6038 __ set_narrow_oop($mem$$Address, (jobject)$src$$constant);
6039 }
6040 %}
6041 ins_pipe(ialu_mem_imm);
6042 %}
6043
6044 instruct storeImmNKlass(memory mem, immNKlass src)
6045 %{
6046 match(Set mem (StoreNKlass mem src));
6047
6048 ins_cost(150); // XXX
6049 format %{ "movl $mem, $src\t# compressed klass ptr" %}
6050 ins_encode %{
6051 __ set_narrow_klass($mem$$Address, (Klass*)$src$$constant);
6052 %}
6053 ins_pipe(ialu_mem_imm);
6054 %}
6055
6056 // Store Integer Immediate
6057 instruct storeImmI0(memory mem, immI0 zero)
6058 %{
6059 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6060 match(Set mem (StoreI mem zero));
6061
6062 ins_cost(125); // XXX
6063 format %{ "movl $mem, R12\t# int (R12_heapbase==0)" %}
6064 ins_encode %{
6065 __ movl($mem$$Address, r12);
6066 %}
6067 ins_pipe(ialu_mem_reg);
6068 %}
6069
6070 instruct storeImmI(memory mem, immI src)
6071 %{
6072 match(Set mem (StoreI mem src));
6073
6074 ins_cost(150);
6075 format %{ "movl $mem, $src\t# int" %}
6076 opcode(0xC7); /* C7 /0 */
6077 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
6078 ins_pipe(ialu_mem_imm);
6079 %}
6080
6081 // Store Long Immediate
6082 instruct storeImmL0(memory mem, immL0 zero)
6083 %{
6084 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6085 match(Set mem (StoreL mem zero));
6086
6087 ins_cost(125); // XXX
6088 format %{ "movq $mem, R12\t# long (R12_heapbase==0)" %}
6089 ins_encode %{
6090 __ movq($mem$$Address, r12);
6091 %}
6092 ins_pipe(ialu_mem_reg);
6093 %}
6094
6095 instruct storeImmL(memory mem, immL32 src)
6096 %{
6097 match(Set mem (StoreL mem src));
6098
6099 ins_cost(150);
6100 format %{ "movq $mem, $src\t# long" %}
6101 opcode(0xC7); /* C7 /0 */
6102 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
6103 ins_pipe(ialu_mem_imm);
6104 %}
6105
6106 // Store Short/Char Immediate
6107 instruct storeImmC0(memory mem, immI0 zero)
6108 %{
6109 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6110 match(Set mem (StoreC mem zero));
6111
6112 ins_cost(125); // XXX
6113 format %{ "movw $mem, R12\t# short/char (R12_heapbase==0)" %}
6114 ins_encode %{
6115 __ movw($mem$$Address, r12);
6116 %}
6117 ins_pipe(ialu_mem_reg);
6118 %}
6119
6120 instruct storeImmI16(memory mem, immI16 src)
6121 %{
6122 predicate(UseStoreImmI16);
6123 match(Set mem (StoreC mem src));
6124
6125 ins_cost(150);
6126 format %{ "movw $mem, $src\t# short/char" %}
6127 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
6128 ins_encode(SizePrefix, REX_mem(mem), OpcP, RM_opc_mem(0x00, mem),Con16(src));
6129 ins_pipe(ialu_mem_imm);
6130 %}
6131
6132 // Store Byte Immediate
6133 instruct storeImmB0(memory mem, immI0 zero)
6134 %{
6135 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6136 match(Set mem (StoreB mem zero));
6137
6138 ins_cost(125); // XXX
6139 format %{ "movb $mem, R12\t# short/char (R12_heapbase==0)" %}
6140 ins_encode %{
6141 __ movb($mem$$Address, r12);
6142 %}
6143 ins_pipe(ialu_mem_reg);
6144 %}
6145
6146 instruct storeImmB(memory mem, immI8 src)
6147 %{
6148 match(Set mem (StoreB mem src));
6149
6150 ins_cost(150); // XXX
6151 format %{ "movb $mem, $src\t# byte" %}
6152 opcode(0xC6); /* C6 /0 */
6153 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
6154 ins_pipe(ialu_mem_imm);
6155 %}
6156
6157 // Store CMS card-mark Immediate
6158 instruct storeImmCM0_reg(memory mem, immI0 zero)
6159 %{
6160 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6161 match(Set mem (StoreCM mem zero));
6162
6163 ins_cost(125); // XXX
6164 format %{ "movb $mem, R12\t# CMS card-mark byte 0 (R12_heapbase==0)" %}
6165 ins_encode %{
6166 __ movb($mem$$Address, r12);
6167 %}
6168 ins_pipe(ialu_mem_reg);
6169 %}
6170
6171 instruct storeImmCM0(memory mem, immI0 src)
6172 %{
6173 match(Set mem (StoreCM mem src));
6174
6175 ins_cost(150); // XXX
6176 format %{ "movb $mem, $src\t# CMS card-mark byte 0" %}
6177 opcode(0xC6); /* C6 /0 */
6178 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
6179 ins_pipe(ialu_mem_imm);
6180 %}
6181
6182 // Store Float
6183 instruct storeF(memory mem, regF src)
6184 %{
6185 match(Set mem (StoreF mem src));
6186
6187 ins_cost(95); // XXX
6188 format %{ "movss $mem, $src\t# float" %}
6189 ins_encode %{
6190 __ movflt($mem$$Address, $src$$XMMRegister);
6191 %}
6192 ins_pipe(pipe_slow); // XXX
6193 %}
6194
6195 // Store immediate Float value (it is faster than store from XMM register)
6196 instruct storeF0(memory mem, immF0 zero)
6197 %{
6198 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6199 match(Set mem (StoreF mem zero));
6200
6201 ins_cost(25); // XXX
6202 format %{ "movl $mem, R12\t# float 0. (R12_heapbase==0)" %}
6203 ins_encode %{
6204 __ movl($mem$$Address, r12);
6205 %}
6206 ins_pipe(ialu_mem_reg);
6207 %}
6208
6209 instruct storeF_imm(memory mem, immF src)
6210 %{
6211 match(Set mem (StoreF mem src));
6212
6213 ins_cost(50);
6214 format %{ "movl $mem, $src\t# float" %}
6215 opcode(0xC7); /* C7 /0 */
6216 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
6217 ins_pipe(ialu_mem_imm);
6218 %}
6219
6220 // Store Double
6221 instruct storeD(memory mem, regD src)
6222 %{
6223 match(Set mem (StoreD mem src));
6224
6225 ins_cost(95); // XXX
6226 format %{ "movsd $mem, $src\t# double" %}
6227 ins_encode %{
6228 __ movdbl($mem$$Address, $src$$XMMRegister);
6229 %}
6230 ins_pipe(pipe_slow); // XXX
6231 %}
6232
6233 // Store immediate double 0.0 (it is faster than store from XMM register)
6234 instruct storeD0_imm(memory mem, immD0 src)
6235 %{
6236 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
6237 match(Set mem (StoreD mem src));
6238
6239 ins_cost(50);
6240 format %{ "movq $mem, $src\t# double 0." %}
6241 opcode(0xC7); /* C7 /0 */
6242 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
6243 ins_pipe(ialu_mem_imm);
6244 %}
6245
6246 instruct storeD0(memory mem, immD0 zero)
6247 %{
6248 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6249 match(Set mem (StoreD mem zero));
6250
6251 ins_cost(25); // XXX
6252 format %{ "movq $mem, R12\t# double 0. (R12_heapbase==0)" %}
6253 ins_encode %{
6254 __ movq($mem$$Address, r12);
6255 %}
6256 ins_pipe(ialu_mem_reg);
6257 %}
6258
6259 instruct storeSSI(stackSlotI dst, rRegI src)
6260 %{
6261 match(Set dst src);
6262
6263 ins_cost(100);
6264 format %{ "movl $dst, $src\t# int stk" %}
6265 opcode(0x89);
6266 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
6267 ins_pipe( ialu_mem_reg );
6268 %}
6269
6270 instruct storeSSL(stackSlotL dst, rRegL src)
6271 %{
6272 match(Set dst src);
6273
6274 ins_cost(100);
6275 format %{ "movq $dst, $src\t# long stk" %}
6276 opcode(0x89);
6277 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6278 ins_pipe(ialu_mem_reg);
6279 %}
6280
6281 instruct storeSSP(stackSlotP dst, rRegP src)
6282 %{
6283 match(Set dst src);
6284
6285 ins_cost(100);
6286 format %{ "movq $dst, $src\t# ptr stk" %}
6287 opcode(0x89);
6288 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6289 ins_pipe(ialu_mem_reg);
6290 %}
6291
6292 instruct storeSSF(stackSlotF dst, regF src)
6293 %{
6294 match(Set dst src);
6295
6296 ins_cost(95); // XXX
6297 format %{ "movss $dst, $src\t# float stk" %}
6298 ins_encode %{
6299 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
6300 %}
6301 ins_pipe(pipe_slow); // XXX
6302 %}
6303
6304 instruct storeSSD(stackSlotD dst, regD src)
6305 %{
6306 match(Set dst src);
6307
6308 ins_cost(95); // XXX
6309 format %{ "movsd $dst, $src\t# double stk" %}
6310 ins_encode %{
6311 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
6312 %}
6313 ins_pipe(pipe_slow); // XXX
6314 %}
6315
6316 //----------BSWAP Instructions-------------------------------------------------
6317 instruct bytes_reverse_int(rRegI dst) %{
6318 match(Set dst (ReverseBytesI dst));
6319
6320 format %{ "bswapl $dst" %}
6321 opcode(0x0F, 0xC8); /*Opcode 0F /C8 */
6322 ins_encode( REX_reg(dst), OpcP, opc2_reg(dst) );
6323 ins_pipe( ialu_reg );
6324 %}
6325
6326 instruct bytes_reverse_long(rRegL dst) %{
6327 match(Set dst (ReverseBytesL dst));
6328
6329 format %{ "bswapq $dst" %}
6330 opcode(0x0F, 0xC8); /* Opcode 0F /C8 */
6331 ins_encode( REX_reg_wide(dst), OpcP, opc2_reg(dst) );
6332 ins_pipe( ialu_reg);
6333 %}
6334
6335 instruct bytes_reverse_unsigned_short(rRegI dst, rFlagsReg cr) %{
6336 match(Set dst (ReverseBytesUS dst));
6337 effect(KILL cr);
6338
6339 format %{ "bswapl $dst\n\t"
6340 "shrl $dst,16\n\t" %}
6341 ins_encode %{
6342 __ bswapl($dst$$Register);
6343 __ shrl($dst$$Register, 16);
6344 %}
6345 ins_pipe( ialu_reg );
6346 %}
6347
6348 instruct bytes_reverse_short(rRegI dst, rFlagsReg cr) %{
6349 match(Set dst (ReverseBytesS dst));
6350 effect(KILL cr);
6351
6352 format %{ "bswapl $dst\n\t"
6353 "sar $dst,16\n\t" %}
6354 ins_encode %{
6355 __ bswapl($dst$$Register);
6356 __ sarl($dst$$Register, 16);
6357 %}
6358 ins_pipe( ialu_reg );
6359 %}
6360
6361 //---------- Zeros Count Instructions ------------------------------------------
6362
6363 instruct countLeadingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6364 predicate(UseCountLeadingZerosInstruction);
6365 match(Set dst (CountLeadingZerosI src));
6366 effect(KILL cr);
6367
6368 format %{ "lzcntl $dst, $src\t# count leading zeros (int)" %}
6369 ins_encode %{
6370 __ lzcntl($dst$$Register, $src$$Register);
6371 %}
6372 ins_pipe(ialu_reg);
6373 %}
6374
6375 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, rFlagsReg cr) %{
6376 predicate(!UseCountLeadingZerosInstruction);
6377 match(Set dst (CountLeadingZerosI src));
6378 effect(KILL cr);
6379
6380 format %{ "bsrl $dst, $src\t# count leading zeros (int)\n\t"
6381 "jnz skip\n\t"
6382 "movl $dst, -1\n"
6383 "skip:\n\t"
6384 "negl $dst\n\t"
6385 "addl $dst, 31" %}
6386 ins_encode %{
6387 Register Rdst = $dst$$Register;
6388 Register Rsrc = $src$$Register;
6389 Label skip;
6390 __ bsrl(Rdst, Rsrc);
6391 __ jccb(Assembler::notZero, skip);
6392 __ movl(Rdst, -1);
6393 __ bind(skip);
6394 __ negl(Rdst);
6395 __ addl(Rdst, BitsPerInt - 1);
6396 %}
6397 ins_pipe(ialu_reg);
6398 %}
6399
6400 instruct countLeadingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6401 predicate(UseCountLeadingZerosInstruction);
6402 match(Set dst (CountLeadingZerosL src));
6403 effect(KILL cr);
6404
6405 format %{ "lzcntq $dst, $src\t# count leading zeros (long)" %}
6406 ins_encode %{
6407 __ lzcntq($dst$$Register, $src$$Register);
6408 %}
6409 ins_pipe(ialu_reg);
6410 %}
6411
6412 instruct countLeadingZerosL_bsr(rRegI dst, rRegL src, rFlagsReg cr) %{
6413 predicate(!UseCountLeadingZerosInstruction);
6414 match(Set dst (CountLeadingZerosL src));
6415 effect(KILL cr);
6416
6417 format %{ "bsrq $dst, $src\t# count leading zeros (long)\n\t"
6418 "jnz skip\n\t"
6419 "movl $dst, -1\n"
6420 "skip:\n\t"
6421 "negl $dst\n\t"
6422 "addl $dst, 63" %}
6423 ins_encode %{
6424 Register Rdst = $dst$$Register;
6425 Register Rsrc = $src$$Register;
6426 Label skip;
6427 __ bsrq(Rdst, Rsrc);
6428 __ jccb(Assembler::notZero, skip);
6429 __ movl(Rdst, -1);
6430 __ bind(skip);
6431 __ negl(Rdst);
6432 __ addl(Rdst, BitsPerLong - 1);
6433 %}
6434 ins_pipe(ialu_reg);
6435 %}
6436
6437 instruct countTrailingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6438 predicate(UseCountTrailingZerosInstruction);
6439 match(Set dst (CountTrailingZerosI src));
6440 effect(KILL cr);
6441
6442 format %{ "tzcntl $dst, $src\t# count trailing zeros (int)" %}
6443 ins_encode %{
6444 __ tzcntl($dst$$Register, $src$$Register);
6445 %}
6446 ins_pipe(ialu_reg);
6447 %}
6448
6449 instruct countTrailingZerosI_bsf(rRegI dst, rRegI src, rFlagsReg cr) %{
6450 predicate(!UseCountTrailingZerosInstruction);
6451 match(Set dst (CountTrailingZerosI src));
6452 effect(KILL cr);
6453
6454 format %{ "bsfl $dst, $src\t# count trailing zeros (int)\n\t"
6455 "jnz done\n\t"
6456 "movl $dst, 32\n"
6457 "done:" %}
6458 ins_encode %{
6459 Register Rdst = $dst$$Register;
6460 Label done;
6461 __ bsfl(Rdst, $src$$Register);
6462 __ jccb(Assembler::notZero, done);
6463 __ movl(Rdst, BitsPerInt);
6464 __ bind(done);
6465 %}
6466 ins_pipe(ialu_reg);
6467 %}
6468
6469 instruct countTrailingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6470 predicate(UseCountTrailingZerosInstruction);
6471 match(Set dst (CountTrailingZerosL src));
6472 effect(KILL cr);
6473
6474 format %{ "tzcntq $dst, $src\t# count trailing zeros (long)" %}
6475 ins_encode %{
6476 __ tzcntq($dst$$Register, $src$$Register);
6477 %}
6478 ins_pipe(ialu_reg);
6479 %}
6480
6481 instruct countTrailingZerosL_bsf(rRegI dst, rRegL src, rFlagsReg cr) %{
6482 predicate(!UseCountTrailingZerosInstruction);
6483 match(Set dst (CountTrailingZerosL src));
6484 effect(KILL cr);
6485
6486 format %{ "bsfq $dst, $src\t# count trailing zeros (long)\n\t"
6487 "jnz done\n\t"
6488 "movl $dst, 64\n"
6489 "done:" %}
6490 ins_encode %{
6491 Register Rdst = $dst$$Register;
6492 Label done;
6493 __ bsfq(Rdst, $src$$Register);
6494 __ jccb(Assembler::notZero, done);
6495 __ movl(Rdst, BitsPerLong);
6496 __ bind(done);
6497 %}
6498 ins_pipe(ialu_reg);
6499 %}
6500
6501
6502 //---------- Population Count Instructions -------------------------------------
6503
6504 instruct popCountI(rRegI dst, rRegI src, rFlagsReg cr) %{
6505 predicate(UsePopCountInstruction);
6506 match(Set dst (PopCountI src));
6507 effect(KILL cr);
6508
6509 format %{ "popcnt $dst, $src" %}
6510 ins_encode %{
6511 __ popcntl($dst$$Register, $src$$Register);
6512 %}
6513 ins_pipe(ialu_reg);
6514 %}
6515
6516 instruct popCountI_mem(rRegI dst, memory mem, rFlagsReg cr) %{
6517 predicate(UsePopCountInstruction);
6518 match(Set dst (PopCountI (LoadI mem)));
6519 effect(KILL cr);
6520
6521 format %{ "popcnt $dst, $mem" %}
6522 ins_encode %{
6523 __ popcntl($dst$$Register, $mem$$Address);
6524 %}
6525 ins_pipe(ialu_reg);
6526 %}
6527
6528 // Note: Long.bitCount(long) returns an int.
6529 instruct popCountL(rRegI dst, rRegL src, rFlagsReg cr) %{
6530 predicate(UsePopCountInstruction);
6531 match(Set dst (PopCountL src));
6532 effect(KILL cr);
6533
6534 format %{ "popcnt $dst, $src" %}
6535 ins_encode %{
6536 __ popcntq($dst$$Register, $src$$Register);
6537 %}
6538 ins_pipe(ialu_reg);
6539 %}
6540
6541 // Note: Long.bitCount(long) returns an int.
6542 instruct popCountL_mem(rRegI dst, memory mem, rFlagsReg cr) %{
6543 predicate(UsePopCountInstruction);
6544 match(Set dst (PopCountL (LoadL mem)));
6545 effect(KILL cr);
6546
6547 format %{ "popcnt $dst, $mem" %}
6548 ins_encode %{
6549 __ popcntq($dst$$Register, $mem$$Address);
6550 %}
6551 ins_pipe(ialu_reg);
6552 %}
6553
6554
6555 //----------MemBar Instructions-----------------------------------------------
6556 // Memory barrier flavors
6557
6558 instruct membar_acquire()
6559 %{
6560 match(MemBarAcquire);
6561 match(LoadFence);
6562 ins_cost(0);
6563
6564 size(0);
6565 format %{ "MEMBAR-acquire ! (empty encoding)" %}
6566 ins_encode();
6567 ins_pipe(empty);
6568 %}
6569
6570 instruct membar_acquire_lock()
6571 %{
6572 match(MemBarAcquireLock);
6573 ins_cost(0);
6574
6575 size(0);
6576 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
6577 ins_encode();
6578 ins_pipe(empty);
6579 %}
6580
6581 instruct membar_release()
6582 %{
6583 match(MemBarRelease);
6584 match(StoreFence);
6585 ins_cost(0);
6586
6587 size(0);
6588 format %{ "MEMBAR-release ! (empty encoding)" %}
6589 ins_encode();
6590 ins_pipe(empty);
6591 %}
6592
6593 instruct membar_release_lock()
6594 %{
6595 match(MemBarReleaseLock);
6596 ins_cost(0);
6597
6598 size(0);
6599 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
6600 ins_encode();
6601 ins_pipe(empty);
6602 %}
6603
6604 instruct membar_volatile(rFlagsReg cr) %{
6605 match(MemBarVolatile);
6606 effect(KILL cr);
6607 ins_cost(400);
6608
6609 format %{
6610 $$template
6611 $$emit$$"lock addl [rsp + #0], 0\t! membar_volatile"
6612 %}
6613 ins_encode %{
6614 __ membar(Assembler::StoreLoad);
6615 %}
6616 ins_pipe(pipe_slow);
6617 %}
6618
6619 instruct unnecessary_membar_volatile()
6620 %{
6621 match(MemBarVolatile);
6622 predicate(Matcher::post_store_load_barrier(n));
6623 ins_cost(0);
6624
6625 size(0);
6626 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
6627 ins_encode();
6628 ins_pipe(empty);
6629 %}
6630
6631 instruct membar_storestore() %{
6632 match(MemBarStoreStore);
6633 ins_cost(0);
6634
6635 size(0);
6636 format %{ "MEMBAR-storestore (empty encoding)" %}
6637 ins_encode( );
6638 ins_pipe(empty);
6639 %}
6640
6641 //----------Move Instructions--------------------------------------------------
6642
6643 instruct castX2P(rRegP dst, rRegL src)
6644 %{
6645 match(Set dst (CastX2P src));
6646
6647 format %{ "movq $dst, $src\t# long->ptr" %}
6648 ins_encode %{
6649 if ($dst$$reg != $src$$reg) {
6650 __ movptr($dst$$Register, $src$$Register);
6651 }
6652 %}
6653 ins_pipe(ialu_reg_reg); // XXX
6654 %}
6655
6656 instruct castP2X(rRegL dst, rRegP src)
6657 %{
6658 match(Set dst (CastP2X src));
6659
6660 format %{ "movq $dst, $src\t# ptr -> long" %}
6661 ins_encode %{
6662 if ($dst$$reg != $src$$reg) {
6663 __ movptr($dst$$Register, $src$$Register);
6664 }
6665 %}
6666 ins_pipe(ialu_reg_reg); // XXX
6667 %}
6668
6669 // Convert oop into int for vectors alignment masking
6670 instruct convP2I(rRegI dst, rRegP src)
6671 %{
6672 match(Set dst (ConvL2I (CastP2X src)));
6673
6674 format %{ "movl $dst, $src\t# ptr -> int" %}
6675 ins_encode %{
6676 __ movl($dst$$Register, $src$$Register);
6677 %}
6678 ins_pipe(ialu_reg_reg); // XXX
6679 %}
6680
6681 // Convert compressed oop into int for vectors alignment masking
6682 // in case of 32bit oops (heap < 4Gb).
6683 instruct convN2I(rRegI dst, rRegN src)
6684 %{
6685 predicate(Universe::narrow_oop_shift() == 0);
6686 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
6687
6688 format %{ "movl $dst, $src\t# compressed ptr -> int" %}
6689 ins_encode %{
6690 __ movl($dst$$Register, $src$$Register);
6691 %}
6692 ins_pipe(ialu_reg_reg); // XXX
6693 %}
6694
6695 // Convert oop pointer into compressed form
6696 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{
6697 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6698 match(Set dst (EncodeP src));
6699 effect(KILL cr);
6700 format %{ "encode_heap_oop $dst,$src" %}
6701 ins_encode %{
6702 Register s = $src$$Register;
6703 Register d = $dst$$Register;
6704 if (s != d) {
6705 __ movq(d, s);
6706 }
6707 __ encode_heap_oop(d);
6708 %}
6709 ins_pipe(ialu_reg_long);
6710 %}
6711
6712 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6713 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6714 match(Set dst (EncodeP src));
6715 effect(KILL cr);
6716 format %{ "encode_heap_oop_not_null $dst,$src" %}
6717 ins_encode %{
6718 __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
6719 %}
6720 ins_pipe(ialu_reg_long);
6721 %}
6722
6723 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{
6724 predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
6725 n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
6726 match(Set dst (DecodeN src));
6727 effect(KILL cr);
6728 format %{ "decode_heap_oop $dst,$src" %}
6729 ins_encode %{
6730 Register s = $src$$Register;
6731 Register d = $dst$$Register;
6732 if (s != d) {
6733 __ movq(d, s);
6734 }
6735 __ decode_heap_oop(d);
6736 %}
6737 ins_pipe(ialu_reg_long);
6738 %}
6739
6740 instruct decodeHeapOop_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6741 predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
6742 n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
6743 match(Set dst (DecodeN src));
6744 effect(KILL cr);
6745 format %{ "decode_heap_oop_not_null $dst,$src" %}
6746 ins_encode %{
6747 Register s = $src$$Register;
6748 Register d = $dst$$Register;
6749 if (s != d) {
6750 __ decode_heap_oop_not_null(d, s);
6751 } else {
6752 __ decode_heap_oop_not_null(d);
6753 }
6754 %}
6755 ins_pipe(ialu_reg_long);
6756 %}
6757
6758 instruct encodeKlass_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6759 match(Set dst (EncodePKlass src));
6760 effect(KILL cr);
6761 format %{ "encode_klass_not_null $dst,$src" %}
6762 ins_encode %{
6763 __ encode_klass_not_null($dst$$Register, $src$$Register);
6764 %}
6765 ins_pipe(ialu_reg_long);
6766 %}
6767
6768 instruct decodeKlass_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6769 match(Set dst (DecodeNKlass src));
6770 effect(KILL cr);
6771 format %{ "decode_klass_not_null $dst,$src" %}
6772 ins_encode %{
6773 Register s = $src$$Register;
6774 Register d = $dst$$Register;
6775 if (s != d) {
6776 __ decode_klass_not_null(d, s);
6777 } else {
6778 __ decode_klass_not_null(d);
6779 }
6780 %}
6781 ins_pipe(ialu_reg_long);
6782 %}
6783
6784
6785 //----------Conditional Move---------------------------------------------------
6786 // Jump
6787 // dummy instruction for generating temp registers
6788 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{
6789 match(Jump (LShiftL switch_val shift));
6790 ins_cost(350);
6791 predicate(false);
6792 effect(TEMP dest);
6793
6794 format %{ "leaq $dest, [$constantaddress]\n\t"
6795 "jmp [$dest + $switch_val << $shift]\n\t" %}
6796 ins_encode %{
6797 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6798 // to do that and the compiler is using that register as one it can allocate.
6799 // So we build it all by hand.
6800 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant);
6801 // ArrayAddress dispatch(table, index);
6802 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant);
6803 __ lea($dest$$Register, $constantaddress);
6804 __ jmp(dispatch);
6805 %}
6806 ins_pipe(pipe_jmp);
6807 %}
6808
6809 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{
6810 match(Jump (AddL (LShiftL switch_val shift) offset));
6811 ins_cost(350);
6812 effect(TEMP dest);
6813
6814 format %{ "leaq $dest, [$constantaddress]\n\t"
6815 "jmp [$dest + $switch_val << $shift + $offset]\n\t" %}
6816 ins_encode %{
6817 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6818 // to do that and the compiler is using that register as one it can allocate.
6819 // So we build it all by hand.
6820 // Address index(noreg, switch_reg, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6821 // ArrayAddress dispatch(table, index);
6822 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6823 __ lea($dest$$Register, $constantaddress);
6824 __ jmp(dispatch);
6825 %}
6826 ins_pipe(pipe_jmp);
6827 %}
6828
6829 instruct jumpXtnd(rRegL switch_val, rRegI dest) %{
6830 match(Jump switch_val);
6831 ins_cost(350);
6832 effect(TEMP dest);
6833
6834 format %{ "leaq $dest, [$constantaddress]\n\t"
6835 "jmp [$dest + $switch_val]\n\t" %}
6836 ins_encode %{
6837 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6838 // to do that and the compiler is using that register as one it can allocate.
6839 // So we build it all by hand.
6840 // Address index(noreg, switch_reg, Address::times_1);
6841 // ArrayAddress dispatch(table, index);
6842 Address dispatch($dest$$Register, $switch_val$$Register, Address::times_1);
6843 __ lea($dest$$Register, $constantaddress);
6844 __ jmp(dispatch);
6845 %}
6846 ins_pipe(pipe_jmp);
6847 %}
6848
6849 // Conditional move
6850 instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop)
6851 %{
6852 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6853
6854 ins_cost(200); // XXX
6855 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6856 opcode(0x0F, 0x40);
6857 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6858 ins_pipe(pipe_cmov_reg);
6859 %}
6860
6861 instruct cmovI_regU(cmpOpU cop, rFlagsRegU cr, rRegI dst, rRegI src) %{
6862 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6863
6864 ins_cost(200); // XXX
6865 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
6866 opcode(0x0F, 0x40);
6867 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6868 ins_pipe(pipe_cmov_reg);
6869 %}
6870
6871 instruct cmovI_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{
6872 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6873 ins_cost(200);
6874 expand %{
6875 cmovI_regU(cop, cr, dst, src);
6876 %}
6877 %}
6878
6879 // Conditional move
6880 instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) %{
6881 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6882
6883 ins_cost(250); // XXX
6884 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6885 opcode(0x0F, 0x40);
6886 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
6887 ins_pipe(pipe_cmov_mem);
6888 %}
6889
6890 // Conditional move
6891 instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src)
6892 %{
6893 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6894
6895 ins_cost(250); // XXX
6896 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
6897 opcode(0x0F, 0x40);
6898 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
6899 ins_pipe(pipe_cmov_mem);
6900 %}
6901
6902 instruct cmovI_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, memory src) %{
6903 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6904 ins_cost(250);
6905 expand %{
6906 cmovI_memU(cop, cr, dst, src);
6907 %}
6908 %}
6909
6910 // Conditional move
6911 instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop)
6912 %{
6913 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6914
6915 ins_cost(200); // XXX
6916 format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %}
6917 opcode(0x0F, 0x40);
6918 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6919 ins_pipe(pipe_cmov_reg);
6920 %}
6921
6922 // Conditional move
6923 instruct cmovN_regU(cmpOpU cop, rFlagsRegU cr, rRegN dst, rRegN src)
6924 %{
6925 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6926
6927 ins_cost(200); // XXX
6928 format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %}
6929 opcode(0x0F, 0x40);
6930 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6931 ins_pipe(pipe_cmov_reg);
6932 %}
6933
6934 instruct cmovN_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{
6935 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6936 ins_cost(200);
6937 expand %{
6938 cmovN_regU(cop, cr, dst, src);
6939 %}
6940 %}
6941
6942 // Conditional move
6943 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop)
6944 %{
6945 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6946
6947 ins_cost(200); // XXX
6948 format %{ "cmovq$cop $dst, $src\t# signed, ptr" %}
6949 opcode(0x0F, 0x40);
6950 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6951 ins_pipe(pipe_cmov_reg); // XXX
6952 %}
6953
6954 // Conditional move
6955 instruct cmovP_regU(cmpOpU cop, rFlagsRegU cr, rRegP dst, rRegP src)
6956 %{
6957 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6958
6959 ins_cost(200); // XXX
6960 format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %}
6961 opcode(0x0F, 0x40);
6962 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6963 ins_pipe(pipe_cmov_reg); // XXX
6964 %}
6965
6966 instruct cmovP_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{
6967 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6968 ins_cost(200);
6969 expand %{
6970 cmovP_regU(cop, cr, dst, src);
6971 %}
6972 %}
6973
6974 // DISABLED: Requires the ADLC to emit a bottom_type call that
6975 // correctly meets the two pointer arguments; one is an incoming
6976 // register but the other is a memory operand. ALSO appears to
6977 // be buggy with implicit null checks.
6978 //
6979 //// Conditional move
6980 //instruct cmovP_mem(cmpOp cop, rFlagsReg cr, rRegP dst, memory src)
6981 //%{
6982 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
6983 // ins_cost(250);
6984 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
6985 // opcode(0x0F,0x40);
6986 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
6987 // ins_pipe( pipe_cmov_mem );
6988 //%}
6989 //
6990 //// Conditional move
6991 //instruct cmovP_memU(cmpOpU cop, rFlagsRegU cr, rRegP dst, memory src)
6992 //%{
6993 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
6994 // ins_cost(250);
6995 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
6996 // opcode(0x0F,0x40);
6997 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
6998 // ins_pipe( pipe_cmov_mem );
6999 //%}
7000
7001 instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src)
7002 %{
7003 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7004
7005 ins_cost(200); // XXX
7006 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
7007 opcode(0x0F, 0x40);
7008 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7009 ins_pipe(pipe_cmov_reg); // XXX
7010 %}
7011
7012 instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src)
7013 %{
7014 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
7015
7016 ins_cost(200); // XXX
7017 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
7018 opcode(0x0F, 0x40);
7019 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
7020 ins_pipe(pipe_cmov_mem); // XXX
7021 %}
7022
7023 instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src)
7024 %{
7025 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7026
7027 ins_cost(200); // XXX
7028 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
7029 opcode(0x0F, 0x40);
7030 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7031 ins_pipe(pipe_cmov_reg); // XXX
7032 %}
7033
7034 instruct cmovL_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{
7035 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7036 ins_cost(200);
7037 expand %{
7038 cmovL_regU(cop, cr, dst, src);
7039 %}
7040 %}
7041
7042 instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src)
7043 %{
7044 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
7045
7046 ins_cost(200); // XXX
7047 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
7048 opcode(0x0F, 0x40);
7049 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
7050 ins_pipe(pipe_cmov_mem); // XXX
7051 %}
7052
7053 instruct cmovL_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, memory src) %{
7054 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
7055 ins_cost(200);
7056 expand %{
7057 cmovL_memU(cop, cr, dst, src);
7058 %}
7059 %}
7060
7061 instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src)
7062 %{
7063 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7064
7065 ins_cost(200); // XXX
7066 format %{ "jn$cop skip\t# signed cmove float\n\t"
7067 "movss $dst, $src\n"
7068 "skip:" %}
7069 ins_encode %{
7070 Label Lskip;
7071 // Invert sense of branch from sense of CMOV
7072 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7073 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7074 __ bind(Lskip);
7075 %}
7076 ins_pipe(pipe_slow);
7077 %}
7078
7079 // instruct cmovF_mem(cmpOp cop, rFlagsReg cr, regF dst, memory src)
7080 // %{
7081 // match(Set dst (CMoveF (Binary cop cr) (Binary dst (LoadL src))));
7082
7083 // ins_cost(200); // XXX
7084 // format %{ "jn$cop skip\t# signed cmove float\n\t"
7085 // "movss $dst, $src\n"
7086 // "skip:" %}
7087 // ins_encode(enc_cmovf_mem_branch(cop, dst, src));
7088 // ins_pipe(pipe_slow);
7089 // %}
7090
7091 instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src)
7092 %{
7093 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7094
7095 ins_cost(200); // XXX
7096 format %{ "jn$cop skip\t# unsigned cmove float\n\t"
7097 "movss $dst, $src\n"
7098 "skip:" %}
7099 ins_encode %{
7100 Label Lskip;
7101 // Invert sense of branch from sense of CMOV
7102 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7103 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7104 __ bind(Lskip);
7105 %}
7106 ins_pipe(pipe_slow);
7107 %}
7108
7109 instruct cmovF_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regF dst, regF src) %{
7110 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7111 ins_cost(200);
7112 expand %{
7113 cmovF_regU(cop, cr, dst, src);
7114 %}
7115 %}
7116
7117 instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src)
7118 %{
7119 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7120
7121 ins_cost(200); // XXX
7122 format %{ "jn$cop skip\t# signed cmove double\n\t"
7123 "movsd $dst, $src\n"
7124 "skip:" %}
7125 ins_encode %{
7126 Label Lskip;
7127 // Invert sense of branch from sense of CMOV
7128 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7129 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7130 __ bind(Lskip);
7131 %}
7132 ins_pipe(pipe_slow);
7133 %}
7134
7135 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src)
7136 %{
7137 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7138
7139 ins_cost(200); // XXX
7140 format %{ "jn$cop skip\t# unsigned cmove double\n\t"
7141 "movsd $dst, $src\n"
7142 "skip:" %}
7143 ins_encode %{
7144 Label Lskip;
7145 // Invert sense of branch from sense of CMOV
7146 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7147 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7148 __ bind(Lskip);
7149 %}
7150 ins_pipe(pipe_slow);
7151 %}
7152
7153 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{
7154 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7155 ins_cost(200);
7156 expand %{
7157 cmovD_regU(cop, cr, dst, src);
7158 %}
7159 %}
7160
7161 //----------Arithmetic Instructions--------------------------------------------
7162 //----------Addition Instructions----------------------------------------------
7163
7164 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7165 %{
7166 match(Set dst (AddI dst src));
7167 effect(KILL cr);
7168
7169 format %{ "addl $dst, $src\t# int" %}
7170 opcode(0x03);
7171 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
7172 ins_pipe(ialu_reg_reg);
7173 %}
7174
7175 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
7176 %{
7177 match(Set dst (AddI dst src));
7178 effect(KILL cr);
7179
7180 format %{ "addl $dst, $src\t# int" %}
7181 opcode(0x81, 0x00); /* /0 id */
7182 ins_encode(OpcSErm(dst, src), Con8or32(src));
7183 ins_pipe( ialu_reg );
7184 %}
7185
7186 instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
7187 %{
7188 match(Set dst (AddI dst (LoadI src)));
7189 effect(KILL cr);
7190
7191 ins_cost(125); // XXX
7192 format %{ "addl $dst, $src\t# int" %}
7193 opcode(0x03);
7194 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
7195 ins_pipe(ialu_reg_mem);
7196 %}
7197
7198 instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
7199 %{
7200 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7201 effect(KILL cr);
7202
7203 ins_cost(150); // XXX
7204 format %{ "addl $dst, $src\t# int" %}
7205 opcode(0x01); /* Opcode 01 /r */
7206 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
7207 ins_pipe(ialu_mem_reg);
7208 %}
7209
7210 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr)
7211 %{
7212 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7213 effect(KILL cr);
7214
7215 ins_cost(125); // XXX
7216 format %{ "addl $dst, $src\t# int" %}
7217 opcode(0x81); /* Opcode 81 /0 id */
7218 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
7219 ins_pipe(ialu_mem_imm);
7220 %}
7221
7222 instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
7223 %{
7224 predicate(UseIncDec);
7225 match(Set dst (AddI dst src));
7226 effect(KILL cr);
7227
7228 format %{ "incl $dst\t# int" %}
7229 opcode(0xFF, 0x00); // FF /0
7230 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7231 ins_pipe(ialu_reg);
7232 %}
7233
7234 instruct incI_mem(memory dst, immI1 src, rFlagsReg cr)
7235 %{
7236 predicate(UseIncDec);
7237 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7238 effect(KILL cr);
7239
7240 ins_cost(125); // XXX
7241 format %{ "incl $dst\t# int" %}
7242 opcode(0xFF); /* Opcode FF /0 */
7243 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x00, dst));
7244 ins_pipe(ialu_mem_imm);
7245 %}
7246
7247 // XXX why does that use AddI
7248 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr)
7249 %{
7250 predicate(UseIncDec);
7251 match(Set dst (AddI dst src));
7252 effect(KILL cr);
7253
7254 format %{ "decl $dst\t# int" %}
7255 opcode(0xFF, 0x01); // FF /1
7256 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7257 ins_pipe(ialu_reg);
7258 %}
7259
7260 // XXX why does that use AddI
7261 instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr)
7262 %{
7263 predicate(UseIncDec);
7264 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7265 effect(KILL cr);
7266
7267 ins_cost(125); // XXX
7268 format %{ "decl $dst\t# int" %}
7269 opcode(0xFF); /* Opcode FF /1 */
7270 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x01, dst));
7271 ins_pipe(ialu_mem_imm);
7272 %}
7273
7274 instruct leaI_rReg_immI(rRegI dst, rRegI src0, immI src1)
7275 %{
7276 match(Set dst (AddI src0 src1));
7277
7278 ins_cost(110);
7279 format %{ "addr32 leal $dst, [$src0 + $src1]\t# int" %}
7280 opcode(0x8D); /* 0x8D /r */
7281 ins_encode(Opcode(0x67), REX_reg_reg(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
7282 ins_pipe(ialu_reg_reg);
7283 %}
7284
7285 instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7286 %{
7287 match(Set dst (AddL dst src));
7288 effect(KILL cr);
7289
7290 format %{ "addq $dst, $src\t# long" %}
7291 opcode(0x03);
7292 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7293 ins_pipe(ialu_reg_reg);
7294 %}
7295
7296 instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
7297 %{
7298 match(Set dst (AddL dst src));
7299 effect(KILL cr);
7300
7301 format %{ "addq $dst, $src\t# long" %}
7302 opcode(0x81, 0x00); /* /0 id */
7303 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7304 ins_pipe( ialu_reg );
7305 %}
7306
7307 instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
7308 %{
7309 match(Set dst (AddL dst (LoadL src)));
7310 effect(KILL cr);
7311
7312 ins_cost(125); // XXX
7313 format %{ "addq $dst, $src\t# long" %}
7314 opcode(0x03);
7315 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
7316 ins_pipe(ialu_reg_mem);
7317 %}
7318
7319 instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
7320 %{
7321 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7322 effect(KILL cr);
7323
7324 ins_cost(150); // XXX
7325 format %{ "addq $dst, $src\t# long" %}
7326 opcode(0x01); /* Opcode 01 /r */
7327 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
7328 ins_pipe(ialu_mem_reg);
7329 %}
7330
7331 instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
7332 %{
7333 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7334 effect(KILL cr);
7335
7336 ins_cost(125); // XXX
7337 format %{ "addq $dst, $src\t# long" %}
7338 opcode(0x81); /* Opcode 81 /0 id */
7339 ins_encode(REX_mem_wide(dst),
7340 OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
7341 ins_pipe(ialu_mem_imm);
7342 %}
7343
7344 instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr)
7345 %{
7346 predicate(UseIncDec);
7347 match(Set dst (AddL dst src));
7348 effect(KILL cr);
7349
7350 format %{ "incq $dst\t# long" %}
7351 opcode(0xFF, 0x00); // FF /0
7352 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7353 ins_pipe(ialu_reg);
7354 %}
7355
7356 instruct incL_mem(memory dst, immL1 src, rFlagsReg cr)
7357 %{
7358 predicate(UseIncDec);
7359 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7360 effect(KILL cr);
7361
7362 ins_cost(125); // XXX
7363 format %{ "incq $dst\t# long" %}
7364 opcode(0xFF); /* Opcode FF /0 */
7365 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x00, dst));
7366 ins_pipe(ialu_mem_imm);
7367 %}
7368
7369 // XXX why does that use AddL
7370 instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr)
7371 %{
7372 predicate(UseIncDec);
7373 match(Set dst (AddL dst src));
7374 effect(KILL cr);
7375
7376 format %{ "decq $dst\t# long" %}
7377 opcode(0xFF, 0x01); // FF /1
7378 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7379 ins_pipe(ialu_reg);
7380 %}
7381
7382 // XXX why does that use AddL
7383 instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr)
7384 %{
7385 predicate(UseIncDec);
7386 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7387 effect(KILL cr);
7388
7389 ins_cost(125); // XXX
7390 format %{ "decq $dst\t# long" %}
7391 opcode(0xFF); /* Opcode FF /1 */
7392 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x01, dst));
7393 ins_pipe(ialu_mem_imm);
7394 %}
7395
7396 instruct leaL_rReg_immL(rRegL dst, rRegL src0, immL32 src1)
7397 %{
7398 match(Set dst (AddL src0 src1));
7399
7400 ins_cost(110);
7401 format %{ "leaq $dst, [$src0 + $src1]\t# long" %}
7402 opcode(0x8D); /* 0x8D /r */
7403 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
7404 ins_pipe(ialu_reg_reg);
7405 %}
7406
7407 instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr)
7408 %{
7409 match(Set dst (AddP dst src));
7410 effect(KILL cr);
7411
7412 format %{ "addq $dst, $src\t# ptr" %}
7413 opcode(0x03);
7414 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7415 ins_pipe(ialu_reg_reg);
7416 %}
7417
7418 instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr)
7419 %{
7420 match(Set dst (AddP dst src));
7421 effect(KILL cr);
7422
7423 format %{ "addq $dst, $src\t# ptr" %}
7424 opcode(0x81, 0x00); /* /0 id */
7425 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7426 ins_pipe( ialu_reg );
7427 %}
7428
7429 // XXX addP mem ops ????
7430
7431 instruct leaP_rReg_imm(rRegP dst, rRegP src0, immL32 src1)
7432 %{
7433 match(Set dst (AddP src0 src1));
7434
7435 ins_cost(110);
7436 format %{ "leaq $dst, [$src0 + $src1]\t# ptr" %}
7437 opcode(0x8D); /* 0x8D /r */
7438 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1));// XXX
7439 ins_pipe(ialu_reg_reg);
7440 %}
7441
7442 instruct checkCastPP(rRegP dst)
7443 %{
7444 match(Set dst (CheckCastPP dst));
7445
7446 size(0);
7447 format %{ "# checkcastPP of $dst" %}
7448 ins_encode(/* empty encoding */);
7449 ins_pipe(empty);
7450 %}
7451
7452 instruct castPP(rRegP dst)
7453 %{
7454 match(Set dst (CastPP dst));
7455
7456 size(0);
7457 format %{ "# castPP of $dst" %}
7458 ins_encode(/* empty encoding */);
7459 ins_pipe(empty);
7460 %}
7461
7462 instruct castII(rRegI dst)
7463 %{
7464 match(Set dst (CastII dst));
7465
7466 size(0);
7467 format %{ "# castII of $dst" %}
7468 ins_encode(/* empty encoding */);
7469 ins_cost(0);
7470 ins_pipe(empty);
7471 %}
7472
7473 // LoadP-locked same as a regular LoadP when used with compare-swap
7474 instruct loadPLocked(rRegP dst, memory mem)
7475 %{
7476 match(Set dst (LoadPLocked mem));
7477
7478 ins_cost(125); // XXX
7479 format %{ "movq $dst, $mem\t# ptr locked" %}
7480 opcode(0x8B);
7481 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
7482 ins_pipe(ialu_reg_mem); // XXX
7483 %}
7484
7485 // Conditional-store of the updated heap-top.
7486 // Used during allocation of the shared heap.
7487 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
7488
7489 instruct storePConditional(memory heap_top_ptr,
7490 rax_RegP oldval, rRegP newval,
7491 rFlagsReg cr)
7492 %{
7493 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7494
7495 format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) "
7496 "If rax == $heap_top_ptr then store $newval into $heap_top_ptr" %}
7497 opcode(0x0F, 0xB1);
7498 ins_encode(lock_prefix,
7499 REX_reg_mem_wide(newval, heap_top_ptr),
7500 OpcP, OpcS,
7501 reg_mem(newval, heap_top_ptr));
7502 ins_pipe(pipe_cmpxchg);
7503 %}
7504
7505 // Conditional-store of an int value.
7506 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
7507 instruct storeIConditional(memory mem, rax_RegI oldval, rRegI newval, rFlagsReg cr)
7508 %{
7509 match(Set cr (StoreIConditional mem (Binary oldval newval)));
7510 effect(KILL oldval);
7511
7512 format %{ "cmpxchgl $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7513 opcode(0x0F, 0xB1);
7514 ins_encode(lock_prefix,
7515 REX_reg_mem(newval, mem),
7516 OpcP, OpcS,
7517 reg_mem(newval, mem));
7518 ins_pipe(pipe_cmpxchg);
7519 %}
7520
7521 // Conditional-store of a long value.
7522 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
7523 instruct storeLConditional(memory mem, rax_RegL oldval, rRegL newval, rFlagsReg cr)
7524 %{
7525 match(Set cr (StoreLConditional mem (Binary oldval newval)));
7526 effect(KILL oldval);
7527
7528 format %{ "cmpxchgq $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7529 opcode(0x0F, 0xB1);
7530 ins_encode(lock_prefix,
7531 REX_reg_mem_wide(newval, mem),
7532 OpcP, OpcS,
7533 reg_mem(newval, mem));
7534 ins_pipe(pipe_cmpxchg);
7535 %}
7536
7537
7538 // XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7539 instruct compareAndSwapP(rRegI res,
7540 memory mem_ptr,
7541 rax_RegP oldval, rRegP newval,
7542 rFlagsReg cr)
7543 %{
7544 predicate(VM_Version::supports_cx8());
7545 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7546 match(Set res (WeakCompareAndSwapP mem_ptr (Binary oldval newval)));
7547 effect(KILL cr, KILL oldval);
7548
7549 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7550 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7551 "sete $res\n\t"
7552 "movzbl $res, $res" %}
7553 opcode(0x0F, 0xB1);
7554 ins_encode(lock_prefix,
7555 REX_reg_mem_wide(newval, mem_ptr),
7556 OpcP, OpcS,
7557 reg_mem(newval, mem_ptr),
7558 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7559 REX_reg_breg(res, res), // movzbl
7560 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7561 ins_pipe( pipe_cmpxchg );
7562 %}
7563
7564 instruct compareAndSwapL(rRegI res,
7565 memory mem_ptr,
7566 rax_RegL oldval, rRegL newval,
7567 rFlagsReg cr)
7568 %{
7569 predicate(VM_Version::supports_cx8());
7570 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7571 match(Set res (WeakCompareAndSwapL mem_ptr (Binary oldval newval)));
7572 effect(KILL cr, KILL oldval);
7573
7574 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7575 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7576 "sete $res\n\t"
7577 "movzbl $res, $res" %}
7578 opcode(0x0F, 0xB1);
7579 ins_encode(lock_prefix,
7580 REX_reg_mem_wide(newval, mem_ptr),
7581 OpcP, OpcS,
7582 reg_mem(newval, mem_ptr),
7583 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7584 REX_reg_breg(res, res), // movzbl
7585 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7586 ins_pipe( pipe_cmpxchg );
7587 %}
7588
7589 instruct compareAndSwapI(rRegI res,
7590 memory mem_ptr,
7591 rax_RegI oldval, rRegI newval,
7592 rFlagsReg cr)
7593 %{
7594 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7595 match(Set res (WeakCompareAndSwapI mem_ptr (Binary oldval newval)));
7596 effect(KILL cr, KILL oldval);
7597
7598 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7599 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7600 "sete $res\n\t"
7601 "movzbl $res, $res" %}
7602 opcode(0x0F, 0xB1);
7603 ins_encode(lock_prefix,
7604 REX_reg_mem(newval, mem_ptr),
7605 OpcP, OpcS,
7606 reg_mem(newval, mem_ptr),
7607 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7608 REX_reg_breg(res, res), // movzbl
7609 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7610 ins_pipe( pipe_cmpxchg );
7611 %}
7612
7613 instruct compareAndSwapB(rRegI res,
7614 memory mem_ptr,
7615 rax_RegI oldval, rRegI newval,
7616 rFlagsReg cr)
7617 %{
7618 match(Set res (CompareAndSwapB mem_ptr (Binary oldval newval)));
7619 match(Set res (WeakCompareAndSwapB mem_ptr (Binary oldval newval)));
7620 effect(KILL cr, KILL oldval);
7621
7622 format %{ "cmpxchgb $mem_ptr,$newval\t# "
7623 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7624 "sete $res\n\t"
7625 "movzbl $res, $res" %}
7626 opcode(0x0F, 0xB0);
7627 ins_encode(lock_prefix,
7628 REX_breg_mem(newval, mem_ptr),
7629 OpcP, OpcS,
7630 reg_mem(newval, mem_ptr),
7631 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7632 REX_reg_breg(res, res), // movzbl
7633 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7634 ins_pipe( pipe_cmpxchg );
7635 %}
7636
7637 instruct compareAndSwapS(rRegI res,
7638 memory mem_ptr,
7639 rax_RegI oldval, rRegI newval,
7640 rFlagsReg cr)
7641 %{
7642 match(Set res (CompareAndSwapS mem_ptr (Binary oldval newval)));
7643 match(Set res (WeakCompareAndSwapS mem_ptr (Binary oldval newval)));
7644 effect(KILL cr, KILL oldval);
7645
7646 format %{ "cmpxchgw $mem_ptr,$newval\t# "
7647 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7648 "sete $res\n\t"
7649 "movzbl $res, $res" %}
7650 opcode(0x0F, 0xB1);
7651 ins_encode(lock_prefix,
7652 SizePrefix,
7653 REX_reg_mem(newval, mem_ptr),
7654 OpcP, OpcS,
7655 reg_mem(newval, mem_ptr),
7656 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7657 REX_reg_breg(res, res), // movzbl
7658 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7659 ins_pipe( pipe_cmpxchg );
7660 %}
7661
7662 instruct compareAndSwapN(rRegI res,
7663 memory mem_ptr,
7664 rax_RegN oldval, rRegN newval,
7665 rFlagsReg cr) %{
7666 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7667 match(Set res (WeakCompareAndSwapN mem_ptr (Binary oldval newval)));
7668 effect(KILL cr, KILL oldval);
7669
7670 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7671 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7672 "sete $res\n\t"
7673 "movzbl $res, $res" %}
7674 opcode(0x0F, 0xB1);
7675 ins_encode(lock_prefix,
7676 REX_reg_mem(newval, mem_ptr),
7677 OpcP, OpcS,
7678 reg_mem(newval, mem_ptr),
7679 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7680 REX_reg_breg(res, res), // movzbl
7681 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7682 ins_pipe( pipe_cmpxchg );
7683 %}
7684
7685 instruct compareAndExchangeB(
7686 memory mem_ptr,
7687 rax_RegI oldval, rRegI newval,
7688 rFlagsReg cr)
7689 %{
7690 match(Set oldval (CompareAndExchangeB mem_ptr (Binary oldval newval)));
7691 effect(KILL cr);
7692
7693 format %{ "cmpxchgb $mem_ptr,$newval\t# "
7694 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7695 opcode(0x0F, 0xB0);
7696 ins_encode(lock_prefix,
7697 REX_breg_mem(newval, mem_ptr),
7698 OpcP, OpcS,
7699 reg_mem(newval, mem_ptr) // lock cmpxchg
7700 );
7701 ins_pipe( pipe_cmpxchg );
7702 %}
7703
7704 instruct compareAndExchangeS(
7705 memory mem_ptr,
7706 rax_RegI oldval, rRegI newval,
7707 rFlagsReg cr)
7708 %{
7709 match(Set oldval (CompareAndExchangeS mem_ptr (Binary oldval newval)));
7710 effect(KILL cr);
7711
7712 format %{ "cmpxchgw $mem_ptr,$newval\t# "
7713 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7714 opcode(0x0F, 0xB1);
7715 ins_encode(lock_prefix,
7716 SizePrefix,
7717 REX_reg_mem(newval, mem_ptr),
7718 OpcP, OpcS,
7719 reg_mem(newval, mem_ptr) // lock cmpxchg
7720 );
7721 ins_pipe( pipe_cmpxchg );
7722 %}
7723
7724 instruct compareAndExchangeI(
7725 memory mem_ptr,
7726 rax_RegI oldval, rRegI newval,
7727 rFlagsReg cr)
7728 %{
7729 match(Set oldval (CompareAndExchangeI mem_ptr (Binary oldval newval)));
7730 effect(KILL cr);
7731
7732 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7733 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7734 opcode(0x0F, 0xB1);
7735 ins_encode(lock_prefix,
7736 REX_reg_mem(newval, mem_ptr),
7737 OpcP, OpcS,
7738 reg_mem(newval, mem_ptr) // lock cmpxchg
7739 );
7740 ins_pipe( pipe_cmpxchg );
7741 %}
7742
7743 instruct compareAndExchangeL(
7744 memory mem_ptr,
7745 rax_RegL oldval, rRegL newval,
7746 rFlagsReg cr)
7747 %{
7748 predicate(VM_Version::supports_cx8());
7749 match(Set oldval (CompareAndExchangeL mem_ptr (Binary oldval newval)));
7750 effect(KILL cr);
7751
7752 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7753 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7754 opcode(0x0F, 0xB1);
7755 ins_encode(lock_prefix,
7756 REX_reg_mem_wide(newval, mem_ptr),
7757 OpcP, OpcS,
7758 reg_mem(newval, mem_ptr) // lock cmpxchg
7759 );
7760 ins_pipe( pipe_cmpxchg );
7761 %}
7762
7763 instruct compareAndExchangeN(
7764 memory mem_ptr,
7765 rax_RegN oldval, rRegN newval,
7766 rFlagsReg cr) %{
7767 match(Set oldval (CompareAndExchangeN mem_ptr (Binary oldval newval)));
7768 effect(KILL cr);
7769
7770 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7771 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7772 opcode(0x0F, 0xB1);
7773 ins_encode(lock_prefix,
7774 REX_reg_mem(newval, mem_ptr),
7775 OpcP, OpcS,
7776 reg_mem(newval, mem_ptr) // lock cmpxchg
7777 );
7778 ins_pipe( pipe_cmpxchg );
7779 %}
7780
7781 instruct compareAndExchangeP(
7782 memory mem_ptr,
7783 rax_RegP oldval, rRegP newval,
7784 rFlagsReg cr)
7785 %{
7786 predicate(VM_Version::supports_cx8());
7787 match(Set oldval (CompareAndExchangeP mem_ptr (Binary oldval newval)));
7788 effect(KILL cr);
7789
7790 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7791 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7792 opcode(0x0F, 0xB1);
7793 ins_encode(lock_prefix,
7794 REX_reg_mem_wide(newval, mem_ptr),
7795 OpcP, OpcS,
7796 reg_mem(newval, mem_ptr) // lock cmpxchg
7797 );
7798 ins_pipe( pipe_cmpxchg );
7799 %}
7800
7801 instruct xaddB_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7802 predicate(n->as_LoadStore()->result_not_used());
7803 match(Set dummy (GetAndAddB mem add));
7804 effect(KILL cr);
7805 format %{ "ADDB [$mem],$add" %}
7806 ins_encode %{
7807 __ lock();
7808 __ addb($mem$$Address, $add$$constant);
7809 %}
7810 ins_pipe( pipe_cmpxchg );
7811 %}
7812
7813 instruct xaddB( memory mem, rRegI newval, rFlagsReg cr) %{
7814 match(Set newval (GetAndAddB mem newval));
7815 effect(KILL cr);
7816 format %{ "XADDB [$mem],$newval" %}
7817 ins_encode %{
7818 __ lock();
7819 __ xaddb($mem$$Address, $newval$$Register);
7820 %}
7821 ins_pipe( pipe_cmpxchg );
7822 %}
7823
7824 instruct xaddS_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7825 predicate(n->as_LoadStore()->result_not_used());
7826 match(Set dummy (GetAndAddS mem add));
7827 effect(KILL cr);
7828 format %{ "ADDW [$mem],$add" %}
7829 ins_encode %{
7830 __ lock();
7831 __ addw($mem$$Address, $add$$constant);
7832 %}
7833 ins_pipe( pipe_cmpxchg );
7834 %}
7835
7836 instruct xaddS( memory mem, rRegI newval, rFlagsReg cr) %{
7837 match(Set newval (GetAndAddS mem newval));
7838 effect(KILL cr);
7839 format %{ "XADDW [$mem],$newval" %}
7840 ins_encode %{
7841 __ lock();
7842 __ xaddw($mem$$Address, $newval$$Register);
7843 %}
7844 ins_pipe( pipe_cmpxchg );
7845 %}
7846
7847 instruct xaddI_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7848 predicate(n->as_LoadStore()->result_not_used());
7849 match(Set dummy (GetAndAddI mem add));
7850 effect(KILL cr);
7851 format %{ "ADDL [$mem],$add" %}
7852 ins_encode %{
7853 __ lock();
7854 __ addl($mem$$Address, $add$$constant);
7855 %}
7856 ins_pipe( pipe_cmpxchg );
7857 %}
7858
7859 instruct xaddI( memory mem, rRegI newval, rFlagsReg cr) %{
7860 match(Set newval (GetAndAddI mem newval));
7861 effect(KILL cr);
7862 format %{ "XADDL [$mem],$newval" %}
7863 ins_encode %{
7864 __ lock();
7865 __ xaddl($mem$$Address, $newval$$Register);
7866 %}
7867 ins_pipe( pipe_cmpxchg );
7868 %}
7869
7870 instruct xaddL_no_res( memory mem, Universe dummy, immL32 add, rFlagsReg cr) %{
7871 predicate(n->as_LoadStore()->result_not_used());
7872 match(Set dummy (GetAndAddL mem add));
7873 effect(KILL cr);
7874 format %{ "ADDQ [$mem],$add" %}
7875 ins_encode %{
7876 __ lock();
7877 __ addq($mem$$Address, $add$$constant);
7878 %}
7879 ins_pipe( pipe_cmpxchg );
7880 %}
7881
7882 instruct xaddL( memory mem, rRegL newval, rFlagsReg cr) %{
7883 match(Set newval (GetAndAddL mem newval));
7884 effect(KILL cr);
7885 format %{ "XADDQ [$mem],$newval" %}
7886 ins_encode %{
7887 __ lock();
7888 __ xaddq($mem$$Address, $newval$$Register);
7889 %}
7890 ins_pipe( pipe_cmpxchg );
7891 %}
7892
7893 instruct xchgB( memory mem, rRegI newval) %{
7894 match(Set newval (GetAndSetB mem newval));
7895 format %{ "XCHGB $newval,[$mem]" %}
7896 ins_encode %{
7897 __ xchgb($newval$$Register, $mem$$Address);
7898 %}
7899 ins_pipe( pipe_cmpxchg );
7900 %}
7901
7902 instruct xchgS( memory mem, rRegI newval) %{
7903 match(Set newval (GetAndSetS mem newval));
7904 format %{ "XCHGW $newval,[$mem]" %}
7905 ins_encode %{
7906 __ xchgw($newval$$Register, $mem$$Address);
7907 %}
7908 ins_pipe( pipe_cmpxchg );
7909 %}
7910
7911 instruct xchgI( memory mem, rRegI newval) %{
7912 match(Set newval (GetAndSetI mem newval));
7913 format %{ "XCHGL $newval,[$mem]" %}
7914 ins_encode %{
7915 __ xchgl($newval$$Register, $mem$$Address);
7916 %}
7917 ins_pipe( pipe_cmpxchg );
7918 %}
7919
7920 instruct xchgL( memory mem, rRegL newval) %{
7921 match(Set newval (GetAndSetL mem newval));
7922 format %{ "XCHGL $newval,[$mem]" %}
7923 ins_encode %{
7924 __ xchgq($newval$$Register, $mem$$Address);
7925 %}
7926 ins_pipe( pipe_cmpxchg );
7927 %}
7928
7929 instruct xchgP( memory mem, rRegP newval) %{
7930 match(Set newval (GetAndSetP mem newval));
7931 format %{ "XCHGQ $newval,[$mem]" %}
7932 ins_encode %{
7933 __ xchgq($newval$$Register, $mem$$Address);
7934 %}
7935 ins_pipe( pipe_cmpxchg );
7936 %}
7937
7938 instruct xchgN( memory mem, rRegN newval) %{
7939 match(Set newval (GetAndSetN mem newval));
7940 format %{ "XCHGL $newval,$mem]" %}
7941 ins_encode %{
7942 __ xchgl($newval$$Register, $mem$$Address);
7943 %}
7944 ins_pipe( pipe_cmpxchg );
7945 %}
7946
7947 //----------Subtraction Instructions-------------------------------------------
7948
7949 // Integer Subtraction Instructions
7950 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7951 %{
7952 match(Set dst (SubI dst src));
7953 effect(KILL cr);
7954
7955 format %{ "subl $dst, $src\t# int" %}
7956 opcode(0x2B);
7957 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
7958 ins_pipe(ialu_reg_reg);
7959 %}
7960
7961 instruct subI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
7962 %{
7963 match(Set dst (SubI dst src));
7964 effect(KILL cr);
7965
7966 format %{ "subl $dst, $src\t# int" %}
7967 opcode(0x81, 0x05); /* Opcode 81 /5 */
7968 ins_encode(OpcSErm(dst, src), Con8or32(src));
7969 ins_pipe(ialu_reg);
7970 %}
7971
7972 instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
7973 %{
7974 match(Set dst (SubI dst (LoadI src)));
7975 effect(KILL cr);
7976
7977 ins_cost(125);
7978 format %{ "subl $dst, $src\t# int" %}
7979 opcode(0x2B);
7980 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
7981 ins_pipe(ialu_reg_mem);
7982 %}
7983
7984 instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
7985 %{
7986 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7987 effect(KILL cr);
7988
7989 ins_cost(150);
7990 format %{ "subl $dst, $src\t# int" %}
7991 opcode(0x29); /* Opcode 29 /r */
7992 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
7993 ins_pipe(ialu_mem_reg);
7994 %}
7995
7996 instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr)
7997 %{
7998 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7999 effect(KILL cr);
8000
8001 ins_cost(125); // XXX
8002 format %{ "subl $dst, $src\t# int" %}
8003 opcode(0x81); /* Opcode 81 /5 id */
8004 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
8005 ins_pipe(ialu_mem_imm);
8006 %}
8007
8008 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
8009 %{
8010 match(Set dst (SubL dst src));
8011 effect(KILL cr);
8012
8013 format %{ "subq $dst, $src\t# long" %}
8014 opcode(0x2B);
8015 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
8016 ins_pipe(ialu_reg_reg);
8017 %}
8018
8019 instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr)
8020 %{
8021 match(Set dst (SubL dst src));
8022 effect(KILL cr);
8023
8024 format %{ "subq $dst, $src\t# long" %}
8025 opcode(0x81, 0x05); /* Opcode 81 /5 */
8026 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
8027 ins_pipe(ialu_reg);
8028 %}
8029
8030 instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
8031 %{
8032 match(Set dst (SubL dst (LoadL src)));
8033 effect(KILL cr);
8034
8035 ins_cost(125);
8036 format %{ "subq $dst, $src\t# long" %}
8037 opcode(0x2B);
8038 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
8039 ins_pipe(ialu_reg_mem);
8040 %}
8041
8042 instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
8043 %{
8044 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
8045 effect(KILL cr);
8046
8047 ins_cost(150);
8048 format %{ "subq $dst, $src\t# long" %}
8049 opcode(0x29); /* Opcode 29 /r */
8050 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
8051 ins_pipe(ialu_mem_reg);
8052 %}
8053
8054 instruct subL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
8055 %{
8056 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
8057 effect(KILL cr);
8058
8059 ins_cost(125); // XXX
8060 format %{ "subq $dst, $src\t# long" %}
8061 opcode(0x81); /* Opcode 81 /5 id */
8062 ins_encode(REX_mem_wide(dst),
8063 OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
8064 ins_pipe(ialu_mem_imm);
8065 %}
8066
8067 // Subtract from a pointer
8068 // XXX hmpf???
8069 instruct subP_rReg(rRegP dst, rRegI src, immI0 zero, rFlagsReg cr)
8070 %{
8071 match(Set dst (AddP dst (SubI zero src)));
8072 effect(KILL cr);
8073
8074 format %{ "subq $dst, $src\t# ptr - int" %}
8075 opcode(0x2B);
8076 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
8077 ins_pipe(ialu_reg_reg);
8078 %}
8079
8080 instruct negI_rReg(rRegI dst, immI0 zero, rFlagsReg cr)
8081 %{
8082 match(Set dst (SubI zero dst));
8083 effect(KILL cr);
8084
8085 format %{ "negl $dst\t# int" %}
8086 opcode(0xF7, 0x03); // Opcode F7 /3
8087 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8088 ins_pipe(ialu_reg);
8089 %}
8090
8091 instruct negI_mem(memory dst, immI0 zero, rFlagsReg cr)
8092 %{
8093 match(Set dst (StoreI dst (SubI zero (LoadI dst))));
8094 effect(KILL cr);
8095
8096 format %{ "negl $dst\t# int" %}
8097 opcode(0xF7, 0x03); // Opcode F7 /3
8098 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8099 ins_pipe(ialu_reg);
8100 %}
8101
8102 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr)
8103 %{
8104 match(Set dst (SubL zero dst));
8105 effect(KILL cr);
8106
8107 format %{ "negq $dst\t# long" %}
8108 opcode(0xF7, 0x03); // Opcode F7 /3
8109 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8110 ins_pipe(ialu_reg);
8111 %}
8112
8113 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr)
8114 %{
8115 match(Set dst (StoreL dst (SubL zero (LoadL dst))));
8116 effect(KILL cr);
8117
8118 format %{ "negq $dst\t# long" %}
8119 opcode(0xF7, 0x03); // Opcode F7 /3
8120 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8121 ins_pipe(ialu_reg);
8122 %}
8123
8124 //----------Multiplication/Division Instructions-------------------------------
8125 // Integer Multiplication Instructions
8126 // Multiply Register
8127
8128 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8129 %{
8130 match(Set dst (MulI dst src));
8131 effect(KILL cr);
8132
8133 ins_cost(300);
8134 format %{ "imull $dst, $src\t# int" %}
8135 opcode(0x0F, 0xAF);
8136 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8137 ins_pipe(ialu_reg_reg_alu0);
8138 %}
8139
8140 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr)
8141 %{
8142 match(Set dst (MulI src imm));
8143 effect(KILL cr);
8144
8145 ins_cost(300);
8146 format %{ "imull $dst, $src, $imm\t# int" %}
8147 opcode(0x69); /* 69 /r id */
8148 ins_encode(REX_reg_reg(dst, src),
8149 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
8150 ins_pipe(ialu_reg_reg_alu0);
8151 %}
8152
8153 instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr)
8154 %{
8155 match(Set dst (MulI dst (LoadI src)));
8156 effect(KILL cr);
8157
8158 ins_cost(350);
8159 format %{ "imull $dst, $src\t# int" %}
8160 opcode(0x0F, 0xAF);
8161 ins_encode(REX_reg_mem(dst, src), OpcP, OpcS, reg_mem(dst, src));
8162 ins_pipe(ialu_reg_mem_alu0);
8163 %}
8164
8165 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr)
8166 %{
8167 match(Set dst (MulI (LoadI src) imm));
8168 effect(KILL cr);
8169
8170 ins_cost(300);
8171 format %{ "imull $dst, $src, $imm\t# int" %}
8172 opcode(0x69); /* 69 /r id */
8173 ins_encode(REX_reg_mem(dst, src),
8174 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
8175 ins_pipe(ialu_reg_mem_alu0);
8176 %}
8177
8178 instruct mulAddS2I_rReg(rRegI dst, rRegI src1, rRegI src2, rRegI src3, rFlagsReg cr)
8179 %{
8180 match(Set dst (MulAddS2I (Binary dst src1) (Binary src2 src3)));
8181 effect(KILL cr, KILL src2);
8182
8183 expand %{ mulI_rReg(dst, src1, cr);
8184 mulI_rReg(src2, src3, cr);
8185 addI_rReg(dst, src2, cr); %}
8186 %}
8187
8188 instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
8189 %{
8190 match(Set dst (MulL dst src));
8191 effect(KILL cr);
8192
8193 ins_cost(300);
8194 format %{ "imulq $dst, $src\t# long" %}
8195 opcode(0x0F, 0xAF);
8196 ins_encode(REX_reg_reg_wide(dst, src), OpcP, OpcS, reg_reg(dst, src));
8197 ins_pipe(ialu_reg_reg_alu0);
8198 %}
8199
8200 instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr)
8201 %{
8202 match(Set dst (MulL src imm));
8203 effect(KILL cr);
8204
8205 ins_cost(300);
8206 format %{ "imulq $dst, $src, $imm\t# long" %}
8207 opcode(0x69); /* 69 /r id */
8208 ins_encode(REX_reg_reg_wide(dst, src),
8209 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
8210 ins_pipe(ialu_reg_reg_alu0);
8211 %}
8212
8213 instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr)
8214 %{
8215 match(Set dst (MulL dst (LoadL src)));
8216 effect(KILL cr);
8217
8218 ins_cost(350);
8219 format %{ "imulq $dst, $src\t# long" %}
8220 opcode(0x0F, 0xAF);
8221 ins_encode(REX_reg_mem_wide(dst, src), OpcP, OpcS, reg_mem(dst, src));
8222 ins_pipe(ialu_reg_mem_alu0);
8223 %}
8224
8225 instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr)
8226 %{
8227 match(Set dst (MulL (LoadL src) imm));
8228 effect(KILL cr);
8229
8230 ins_cost(300);
8231 format %{ "imulq $dst, $src, $imm\t# long" %}
8232 opcode(0x69); /* 69 /r id */
8233 ins_encode(REX_reg_mem_wide(dst, src),
8234 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
8235 ins_pipe(ialu_reg_mem_alu0);
8236 %}
8237
8238 instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
8239 %{
8240 match(Set dst (MulHiL src rax));
8241 effect(USE_KILL rax, KILL cr);
8242
8243 ins_cost(300);
8244 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %}
8245 opcode(0xF7, 0x5); /* Opcode F7 /5 */
8246 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
8247 ins_pipe(ialu_reg_reg_alu0);
8248 %}
8249
8250 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
8251 rFlagsReg cr)
8252 %{
8253 match(Set rax (DivI rax div));
8254 effect(KILL rdx, KILL cr);
8255
8256 ins_cost(30*100+10*100); // XXX
8257 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
8258 "jne,s normal\n\t"
8259 "xorl rdx, rdx\n\t"
8260 "cmpl $div, -1\n\t"
8261 "je,s done\n"
8262 "normal: cdql\n\t"
8263 "idivl $div\n"
8264 "done:" %}
8265 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8266 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8267 ins_pipe(ialu_reg_reg_alu0);
8268 %}
8269
8270 instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
8271 rFlagsReg cr)
8272 %{
8273 match(Set rax (DivL rax div));
8274 effect(KILL rdx, KILL cr);
8275
8276 ins_cost(30*100+10*100); // XXX
8277 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
8278 "cmpq rax, rdx\n\t"
8279 "jne,s normal\n\t"
8280 "xorl rdx, rdx\n\t"
8281 "cmpq $div, -1\n\t"
8282 "je,s done\n"
8283 "normal: cdqq\n\t"
8284 "idivq $div\n"
8285 "done:" %}
8286 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8287 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8288 ins_pipe(ialu_reg_reg_alu0);
8289 %}
8290
8291 // Integer DIVMOD with Register, both quotient and mod results
8292 instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
8293 rFlagsReg cr)
8294 %{
8295 match(DivModI rax div);
8296 effect(KILL cr);
8297
8298 ins_cost(30*100+10*100); // XXX
8299 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
8300 "jne,s normal\n\t"
8301 "xorl rdx, rdx\n\t"
8302 "cmpl $div, -1\n\t"
8303 "je,s done\n"
8304 "normal: cdql\n\t"
8305 "idivl $div\n"
8306 "done:" %}
8307 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8308 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8309 ins_pipe(pipe_slow);
8310 %}
8311
8312 // Long DIVMOD with Register, both quotient and mod results
8313 instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
8314 rFlagsReg cr)
8315 %{
8316 match(DivModL rax div);
8317 effect(KILL cr);
8318
8319 ins_cost(30*100+10*100); // XXX
8320 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
8321 "cmpq rax, rdx\n\t"
8322 "jne,s normal\n\t"
8323 "xorl rdx, rdx\n\t"
8324 "cmpq $div, -1\n\t"
8325 "je,s done\n"
8326 "normal: cdqq\n\t"
8327 "idivq $div\n"
8328 "done:" %}
8329 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8330 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8331 ins_pipe(pipe_slow);
8332 %}
8333
8334 //----------- DivL-By-Constant-Expansions--------------------------------------
8335 // DivI cases are handled by the compiler
8336
8337 // Magic constant, reciprocal of 10
8338 instruct loadConL_0x6666666666666667(rRegL dst)
8339 %{
8340 effect(DEF dst);
8341
8342 format %{ "movq $dst, #0x666666666666667\t# Used in div-by-10" %}
8343 ins_encode(load_immL(dst, 0x6666666666666667));
8344 ins_pipe(ialu_reg);
8345 %}
8346
8347 instruct mul_hi(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
8348 %{
8349 effect(DEF dst, USE src, USE_KILL rax, KILL cr);
8350
8351 format %{ "imulq rdx:rax, rax, $src\t# Used in div-by-10" %}
8352 opcode(0xF7, 0x5); /* Opcode F7 /5 */
8353 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
8354 ins_pipe(ialu_reg_reg_alu0);
8355 %}
8356
8357 instruct sarL_rReg_63(rRegL dst, rFlagsReg cr)
8358 %{
8359 effect(USE_DEF dst, KILL cr);
8360
8361 format %{ "sarq $dst, #63\t# Used in div-by-10" %}
8362 opcode(0xC1, 0x7); /* C1 /7 ib */
8363 ins_encode(reg_opc_imm_wide(dst, 0x3F));
8364 ins_pipe(ialu_reg);
8365 %}
8366
8367 instruct sarL_rReg_2(rRegL dst, rFlagsReg cr)
8368 %{
8369 effect(USE_DEF dst, KILL cr);
8370
8371 format %{ "sarq $dst, #2\t# Used in div-by-10" %}
8372 opcode(0xC1, 0x7); /* C1 /7 ib */
8373 ins_encode(reg_opc_imm_wide(dst, 0x2));
8374 ins_pipe(ialu_reg);
8375 %}
8376
8377 instruct divL_10(rdx_RegL dst, no_rax_RegL src, immL10 div)
8378 %{
8379 match(Set dst (DivL src div));
8380
8381 ins_cost((5+8)*100);
8382 expand %{
8383 rax_RegL rax; // Killed temp
8384 rFlagsReg cr; // Killed
8385 loadConL_0x6666666666666667(rax); // movq rax, 0x6666666666666667
8386 mul_hi(dst, src, rax, cr); // mulq rdx:rax <= rax * $src
8387 sarL_rReg_63(src, cr); // sarq src, 63
8388 sarL_rReg_2(dst, cr); // sarq rdx, 2
8389 subL_rReg(dst, src, cr); // subl rdx, src
8390 %}
8391 %}
8392
8393 //-----------------------------------------------------------------------------
8394
8395 instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div,
8396 rFlagsReg cr)
8397 %{
8398 match(Set rdx (ModI rax div));
8399 effect(KILL rax, KILL cr);
8400
8401 ins_cost(300); // XXX
8402 format %{ "cmpl rax, 0x80000000\t# irem\n\t"
8403 "jne,s normal\n\t"
8404 "xorl rdx, rdx\n\t"
8405 "cmpl $div, -1\n\t"
8406 "je,s done\n"
8407 "normal: cdql\n\t"
8408 "idivl $div\n"
8409 "done:" %}
8410 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8411 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8412 ins_pipe(ialu_reg_reg_alu0);
8413 %}
8414
8415 instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div,
8416 rFlagsReg cr)
8417 %{
8418 match(Set rdx (ModL rax div));
8419 effect(KILL rax, KILL cr);
8420
8421 ins_cost(300); // XXX
8422 format %{ "movq rdx, 0x8000000000000000\t# lrem\n\t"
8423 "cmpq rax, rdx\n\t"
8424 "jne,s normal\n\t"
8425 "xorl rdx, rdx\n\t"
8426 "cmpq $div, -1\n\t"
8427 "je,s done\n"
8428 "normal: cdqq\n\t"
8429 "idivq $div\n"
8430 "done:" %}
8431 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8432 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8433 ins_pipe(ialu_reg_reg_alu0);
8434 %}
8435
8436 // Integer Shift Instructions
8437 // Shift Left by one
8438 instruct salI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8439 %{
8440 match(Set dst (LShiftI dst shift));
8441 effect(KILL cr);
8442
8443 format %{ "sall $dst, $shift" %}
8444 opcode(0xD1, 0x4); /* D1 /4 */
8445 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8446 ins_pipe(ialu_reg);
8447 %}
8448
8449 // Shift Left by one
8450 instruct salI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8451 %{
8452 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8453 effect(KILL cr);
8454
8455 format %{ "sall $dst, $shift\t" %}
8456 opcode(0xD1, 0x4); /* D1 /4 */
8457 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8458 ins_pipe(ialu_mem_imm);
8459 %}
8460
8461 // Shift Left by 8-bit immediate
8462 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8463 %{
8464 match(Set dst (LShiftI dst shift));
8465 effect(KILL cr);
8466
8467 format %{ "sall $dst, $shift" %}
8468 opcode(0xC1, 0x4); /* C1 /4 ib */
8469 ins_encode(reg_opc_imm(dst, shift));
8470 ins_pipe(ialu_reg);
8471 %}
8472
8473 // Shift Left by 8-bit immediate
8474 instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8475 %{
8476 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8477 effect(KILL cr);
8478
8479 format %{ "sall $dst, $shift" %}
8480 opcode(0xC1, 0x4); /* C1 /4 ib */
8481 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8482 ins_pipe(ialu_mem_imm);
8483 %}
8484
8485 // Shift Left by variable
8486 instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8487 %{
8488 match(Set dst (LShiftI dst shift));
8489 effect(KILL cr);
8490
8491 format %{ "sall $dst, $shift" %}
8492 opcode(0xD3, 0x4); /* D3 /4 */
8493 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8494 ins_pipe(ialu_reg_reg);
8495 %}
8496
8497 // Shift Left by variable
8498 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8499 %{
8500 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8501 effect(KILL cr);
8502
8503 format %{ "sall $dst, $shift" %}
8504 opcode(0xD3, 0x4); /* D3 /4 */
8505 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8506 ins_pipe(ialu_mem_reg);
8507 %}
8508
8509 // Arithmetic shift right by one
8510 instruct sarI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8511 %{
8512 match(Set dst (RShiftI dst shift));
8513 effect(KILL cr);
8514
8515 format %{ "sarl $dst, $shift" %}
8516 opcode(0xD1, 0x7); /* D1 /7 */
8517 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8518 ins_pipe(ialu_reg);
8519 %}
8520
8521 // Arithmetic shift right by one
8522 instruct sarI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8523 %{
8524 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8525 effect(KILL cr);
8526
8527 format %{ "sarl $dst, $shift" %}
8528 opcode(0xD1, 0x7); /* D1 /7 */
8529 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8530 ins_pipe(ialu_mem_imm);
8531 %}
8532
8533 // Arithmetic Shift Right by 8-bit immediate
8534 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8535 %{
8536 match(Set dst (RShiftI dst shift));
8537 effect(KILL cr);
8538
8539 format %{ "sarl $dst, $shift" %}
8540 opcode(0xC1, 0x7); /* C1 /7 ib */
8541 ins_encode(reg_opc_imm(dst, shift));
8542 ins_pipe(ialu_mem_imm);
8543 %}
8544
8545 // Arithmetic Shift Right by 8-bit immediate
8546 instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8547 %{
8548 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8549 effect(KILL cr);
8550
8551 format %{ "sarl $dst, $shift" %}
8552 opcode(0xC1, 0x7); /* C1 /7 ib */
8553 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8554 ins_pipe(ialu_mem_imm);
8555 %}
8556
8557 // Arithmetic Shift Right by variable
8558 instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8559 %{
8560 match(Set dst (RShiftI dst shift));
8561 effect(KILL cr);
8562
8563 format %{ "sarl $dst, $shift" %}
8564 opcode(0xD3, 0x7); /* D3 /7 */
8565 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8566 ins_pipe(ialu_reg_reg);
8567 %}
8568
8569 // Arithmetic Shift Right by variable
8570 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8571 %{
8572 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8573 effect(KILL cr);
8574
8575 format %{ "sarl $dst, $shift" %}
8576 opcode(0xD3, 0x7); /* D3 /7 */
8577 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8578 ins_pipe(ialu_mem_reg);
8579 %}
8580
8581 // Logical shift right by one
8582 instruct shrI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8583 %{
8584 match(Set dst (URShiftI dst shift));
8585 effect(KILL cr);
8586
8587 format %{ "shrl $dst, $shift" %}
8588 opcode(0xD1, 0x5); /* D1 /5 */
8589 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8590 ins_pipe(ialu_reg);
8591 %}
8592
8593 // Logical shift right by one
8594 instruct shrI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8595 %{
8596 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8597 effect(KILL cr);
8598
8599 format %{ "shrl $dst, $shift" %}
8600 opcode(0xD1, 0x5); /* D1 /5 */
8601 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8602 ins_pipe(ialu_mem_imm);
8603 %}
8604
8605 // Logical Shift Right by 8-bit immediate
8606 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8607 %{
8608 match(Set dst (URShiftI dst shift));
8609 effect(KILL cr);
8610
8611 format %{ "shrl $dst, $shift" %}
8612 opcode(0xC1, 0x5); /* C1 /5 ib */
8613 ins_encode(reg_opc_imm(dst, shift));
8614 ins_pipe(ialu_reg);
8615 %}
8616
8617 // Logical Shift Right by 8-bit immediate
8618 instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8619 %{
8620 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8621 effect(KILL cr);
8622
8623 format %{ "shrl $dst, $shift" %}
8624 opcode(0xC1, 0x5); /* C1 /5 ib */
8625 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8626 ins_pipe(ialu_mem_imm);
8627 %}
8628
8629 // Logical Shift Right by variable
8630 instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8631 %{
8632 match(Set dst (URShiftI dst shift));
8633 effect(KILL cr);
8634
8635 format %{ "shrl $dst, $shift" %}
8636 opcode(0xD3, 0x5); /* D3 /5 */
8637 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8638 ins_pipe(ialu_reg_reg);
8639 %}
8640
8641 // Logical Shift Right by variable
8642 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8643 %{
8644 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8645 effect(KILL cr);
8646
8647 format %{ "shrl $dst, $shift" %}
8648 opcode(0xD3, 0x5); /* D3 /5 */
8649 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8650 ins_pipe(ialu_mem_reg);
8651 %}
8652
8653 // Long Shift Instructions
8654 // Shift Left by one
8655 instruct salL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8656 %{
8657 match(Set dst (LShiftL dst shift));
8658 effect(KILL cr);
8659
8660 format %{ "salq $dst, $shift" %}
8661 opcode(0xD1, 0x4); /* D1 /4 */
8662 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8663 ins_pipe(ialu_reg);
8664 %}
8665
8666 // Shift Left by one
8667 instruct salL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8668 %{
8669 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8670 effect(KILL cr);
8671
8672 format %{ "salq $dst, $shift" %}
8673 opcode(0xD1, 0x4); /* D1 /4 */
8674 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8675 ins_pipe(ialu_mem_imm);
8676 %}
8677
8678 // Shift Left by 8-bit immediate
8679 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8680 %{
8681 match(Set dst (LShiftL dst shift));
8682 effect(KILL cr);
8683
8684 format %{ "salq $dst, $shift" %}
8685 opcode(0xC1, 0x4); /* C1 /4 ib */
8686 ins_encode(reg_opc_imm_wide(dst, shift));
8687 ins_pipe(ialu_reg);
8688 %}
8689
8690 // Shift Left by 8-bit immediate
8691 instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8692 %{
8693 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8694 effect(KILL cr);
8695
8696 format %{ "salq $dst, $shift" %}
8697 opcode(0xC1, 0x4); /* C1 /4 ib */
8698 ins_encode(REX_mem_wide(dst), OpcP,
8699 RM_opc_mem(secondary, dst), Con8or32(shift));
8700 ins_pipe(ialu_mem_imm);
8701 %}
8702
8703 // Shift Left by variable
8704 instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8705 %{
8706 match(Set dst (LShiftL dst shift));
8707 effect(KILL cr);
8708
8709 format %{ "salq $dst, $shift" %}
8710 opcode(0xD3, 0x4); /* D3 /4 */
8711 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8712 ins_pipe(ialu_reg_reg);
8713 %}
8714
8715 // Shift Left by variable
8716 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8717 %{
8718 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8719 effect(KILL cr);
8720
8721 format %{ "salq $dst, $shift" %}
8722 opcode(0xD3, 0x4); /* D3 /4 */
8723 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8724 ins_pipe(ialu_mem_reg);
8725 %}
8726
8727 // Arithmetic shift right by one
8728 instruct sarL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8729 %{
8730 match(Set dst (RShiftL dst shift));
8731 effect(KILL cr);
8732
8733 format %{ "sarq $dst, $shift" %}
8734 opcode(0xD1, 0x7); /* D1 /7 */
8735 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8736 ins_pipe(ialu_reg);
8737 %}
8738
8739 // Arithmetic shift right by one
8740 instruct sarL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8741 %{
8742 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8743 effect(KILL cr);
8744
8745 format %{ "sarq $dst, $shift" %}
8746 opcode(0xD1, 0x7); /* D1 /7 */
8747 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8748 ins_pipe(ialu_mem_imm);
8749 %}
8750
8751 // Arithmetic Shift Right by 8-bit immediate
8752 instruct sarL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8753 %{
8754 match(Set dst (RShiftL dst shift));
8755 effect(KILL cr);
8756
8757 format %{ "sarq $dst, $shift" %}
8758 opcode(0xC1, 0x7); /* C1 /7 ib */
8759 ins_encode(reg_opc_imm_wide(dst, shift));
8760 ins_pipe(ialu_mem_imm);
8761 %}
8762
8763 // Arithmetic Shift Right by 8-bit immediate
8764 instruct sarL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8765 %{
8766 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8767 effect(KILL cr);
8768
8769 format %{ "sarq $dst, $shift" %}
8770 opcode(0xC1, 0x7); /* C1 /7 ib */
8771 ins_encode(REX_mem_wide(dst), OpcP,
8772 RM_opc_mem(secondary, dst), Con8or32(shift));
8773 ins_pipe(ialu_mem_imm);
8774 %}
8775
8776 // Arithmetic Shift Right by variable
8777 instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8778 %{
8779 match(Set dst (RShiftL dst shift));
8780 effect(KILL cr);
8781
8782 format %{ "sarq $dst, $shift" %}
8783 opcode(0xD3, 0x7); /* D3 /7 */
8784 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8785 ins_pipe(ialu_reg_reg);
8786 %}
8787
8788 // Arithmetic Shift Right by variable
8789 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8790 %{
8791 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8792 effect(KILL cr);
8793
8794 format %{ "sarq $dst, $shift" %}
8795 opcode(0xD3, 0x7); /* D3 /7 */
8796 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8797 ins_pipe(ialu_mem_reg);
8798 %}
8799
8800 // Logical shift right by one
8801 instruct shrL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8802 %{
8803 match(Set dst (URShiftL dst shift));
8804 effect(KILL cr);
8805
8806 format %{ "shrq $dst, $shift" %}
8807 opcode(0xD1, 0x5); /* D1 /5 */
8808 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst ));
8809 ins_pipe(ialu_reg);
8810 %}
8811
8812 // Logical shift right by one
8813 instruct shrL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8814 %{
8815 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8816 effect(KILL cr);
8817
8818 format %{ "shrq $dst, $shift" %}
8819 opcode(0xD1, 0x5); /* D1 /5 */
8820 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8821 ins_pipe(ialu_mem_imm);
8822 %}
8823
8824 // Logical Shift Right by 8-bit immediate
8825 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8826 %{
8827 match(Set dst (URShiftL dst shift));
8828 effect(KILL cr);
8829
8830 format %{ "shrq $dst, $shift" %}
8831 opcode(0xC1, 0x5); /* C1 /5 ib */
8832 ins_encode(reg_opc_imm_wide(dst, shift));
8833 ins_pipe(ialu_reg);
8834 %}
8835
8836
8837 // Logical Shift Right by 8-bit immediate
8838 instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8839 %{
8840 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8841 effect(KILL cr);
8842
8843 format %{ "shrq $dst, $shift" %}
8844 opcode(0xC1, 0x5); /* C1 /5 ib */
8845 ins_encode(REX_mem_wide(dst), OpcP,
8846 RM_opc_mem(secondary, dst), Con8or32(shift));
8847 ins_pipe(ialu_mem_imm);
8848 %}
8849
8850 // Logical Shift Right by variable
8851 instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8852 %{
8853 match(Set dst (URShiftL dst shift));
8854 effect(KILL cr);
8855
8856 format %{ "shrq $dst, $shift" %}
8857 opcode(0xD3, 0x5); /* D3 /5 */
8858 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8859 ins_pipe(ialu_reg_reg);
8860 %}
8861
8862 // Logical Shift Right by variable
8863 instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8864 %{
8865 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8866 effect(KILL cr);
8867
8868 format %{ "shrq $dst, $shift" %}
8869 opcode(0xD3, 0x5); /* D3 /5 */
8870 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8871 ins_pipe(ialu_mem_reg);
8872 %}
8873
8874 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
8875 // This idiom is used by the compiler for the i2b bytecode.
8876 instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour)
8877 %{
8878 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
8879
8880 format %{ "movsbl $dst, $src\t# i2b" %}
8881 opcode(0x0F, 0xBE);
8882 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8883 ins_pipe(ialu_reg_reg);
8884 %}
8885
8886 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
8887 // This idiom is used by the compiler the i2s bytecode.
8888 instruct i2s(rRegI dst, rRegI src, immI_16 sixteen)
8889 %{
8890 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
8891
8892 format %{ "movswl $dst, $src\t# i2s" %}
8893 opcode(0x0F, 0xBF);
8894 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8895 ins_pipe(ialu_reg_reg);
8896 %}
8897
8898 // ROL/ROR instructions
8899
8900 // ROL expand
8901 instruct rolI_rReg_imm1(rRegI dst, rFlagsReg cr) %{
8902 effect(KILL cr, USE_DEF dst);
8903
8904 format %{ "roll $dst" %}
8905 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8906 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8907 ins_pipe(ialu_reg);
8908 %}
8909
8910 instruct rolI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) %{
8911 effect(USE_DEF dst, USE shift, KILL cr);
8912
8913 format %{ "roll $dst, $shift" %}
8914 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
8915 ins_encode( reg_opc_imm(dst, shift) );
8916 ins_pipe(ialu_reg);
8917 %}
8918
8919 instruct rolI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
8920 %{
8921 effect(USE_DEF dst, USE shift, KILL cr);
8922
8923 format %{ "roll $dst, $shift" %}
8924 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8925 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8926 ins_pipe(ialu_reg_reg);
8927 %}
8928 // end of ROL expand
8929
8930 // Rotate Left by one
8931 instruct rolI_rReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
8932 %{
8933 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8934
8935 expand %{
8936 rolI_rReg_imm1(dst, cr);
8937 %}
8938 %}
8939
8940 // Rotate Left by 8-bit immediate
8941 instruct rolI_rReg_i8(rRegI dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
8942 %{
8943 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8944 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8945
8946 expand %{
8947 rolI_rReg_imm8(dst, lshift, cr);
8948 %}
8949 %}
8950
8951 // Rotate Left by variable
8952 instruct rolI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8953 %{
8954 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
8955
8956 expand %{
8957 rolI_rReg_CL(dst, shift, cr);
8958 %}
8959 %}
8960
8961 // Rotate Left by variable
8962 instruct rolI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
8963 %{
8964 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
8965
8966 expand %{
8967 rolI_rReg_CL(dst, shift, cr);
8968 %}
8969 %}
8970
8971 // ROR expand
8972 instruct rorI_rReg_imm1(rRegI dst, rFlagsReg cr)
8973 %{
8974 effect(USE_DEF dst, KILL cr);
8975
8976 format %{ "rorl $dst" %}
8977 opcode(0xD1, 0x1); /* D1 /1 */
8978 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8979 ins_pipe(ialu_reg);
8980 %}
8981
8982 instruct rorI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr)
8983 %{
8984 effect(USE_DEF dst, USE shift, KILL cr);
8985
8986 format %{ "rorl $dst, $shift" %}
8987 opcode(0xC1, 0x1); /* C1 /1 ib */
8988 ins_encode(reg_opc_imm(dst, shift));
8989 ins_pipe(ialu_reg);
8990 %}
8991
8992 instruct rorI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
8993 %{
8994 effect(USE_DEF dst, USE shift, KILL cr);
8995
8996 format %{ "rorl $dst, $shift" %}
8997 opcode(0xD3, 0x1); /* D3 /1 */
8998 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8999 ins_pipe(ialu_reg_reg);
9000 %}
9001 // end of ROR expand
9002
9003 // Rotate Right by one
9004 instruct rorI_rReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
9005 %{
9006 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
9007
9008 expand %{
9009 rorI_rReg_imm1(dst, cr);
9010 %}
9011 %}
9012
9013 // Rotate Right by 8-bit immediate
9014 instruct rorI_rReg_i8(rRegI dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
9015 %{
9016 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
9017 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
9018
9019 expand %{
9020 rorI_rReg_imm8(dst, rshift, cr);
9021 %}
9022 %}
9023
9024 // Rotate Right by variable
9025 instruct rorI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
9026 %{
9027 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
9028
9029 expand %{
9030 rorI_rReg_CL(dst, shift, cr);
9031 %}
9032 %}
9033
9034 // Rotate Right by variable
9035 instruct rorI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
9036 %{
9037 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
9038
9039 expand %{
9040 rorI_rReg_CL(dst, shift, cr);
9041 %}
9042 %}
9043
9044 // for long rotate
9045 // ROL expand
9046 instruct rolL_rReg_imm1(rRegL dst, rFlagsReg cr) %{
9047 effect(USE_DEF dst, KILL cr);
9048
9049 format %{ "rolq $dst" %}
9050 opcode(0xD1, 0x0); /* Opcode D1 /0 */
9051 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9052 ins_pipe(ialu_reg);
9053 %}
9054
9055 instruct rolL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) %{
9056 effect(USE_DEF dst, USE shift, KILL cr);
9057
9058 format %{ "rolq $dst, $shift" %}
9059 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
9060 ins_encode( reg_opc_imm_wide(dst, shift) );
9061 ins_pipe(ialu_reg);
9062 %}
9063
9064 instruct rolL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
9065 %{
9066 effect(USE_DEF dst, USE shift, KILL cr);
9067
9068 format %{ "rolq $dst, $shift" %}
9069 opcode(0xD3, 0x0); /* Opcode D3 /0 */
9070 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9071 ins_pipe(ialu_reg_reg);
9072 %}
9073 // end of ROL expand
9074
9075 // Rotate Left by one
9076 instruct rolL_rReg_i1(rRegL dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
9077 %{
9078 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
9079
9080 expand %{
9081 rolL_rReg_imm1(dst, cr);
9082 %}
9083 %}
9084
9085 // Rotate Left by 8-bit immediate
9086 instruct rolL_rReg_i8(rRegL dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
9087 %{
9088 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
9089 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
9090
9091 expand %{
9092 rolL_rReg_imm8(dst, lshift, cr);
9093 %}
9094 %}
9095
9096 // Rotate Left by variable
9097 instruct rolL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
9098 %{
9099 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI zero shift))));
9100
9101 expand %{
9102 rolL_rReg_CL(dst, shift, cr);
9103 %}
9104 %}
9105
9106 // Rotate Left by variable
9107 instruct rolL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
9108 %{
9109 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI c64 shift))));
9110
9111 expand %{
9112 rolL_rReg_CL(dst, shift, cr);
9113 %}
9114 %}
9115
9116 // ROR expand
9117 instruct rorL_rReg_imm1(rRegL dst, rFlagsReg cr)
9118 %{
9119 effect(USE_DEF dst, KILL cr);
9120
9121 format %{ "rorq $dst" %}
9122 opcode(0xD1, 0x1); /* D1 /1 */
9123 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9124 ins_pipe(ialu_reg);
9125 %}
9126
9127 instruct rorL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr)
9128 %{
9129 effect(USE_DEF dst, USE shift, KILL cr);
9130
9131 format %{ "rorq $dst, $shift" %}
9132 opcode(0xC1, 0x1); /* C1 /1 ib */
9133 ins_encode(reg_opc_imm_wide(dst, shift));
9134 ins_pipe(ialu_reg);
9135 %}
9136
9137 instruct rorL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
9138 %{
9139 effect(USE_DEF dst, USE shift, KILL cr);
9140
9141 format %{ "rorq $dst, $shift" %}
9142 opcode(0xD3, 0x1); /* D3 /1 */
9143 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9144 ins_pipe(ialu_reg_reg);
9145 %}
9146 // end of ROR expand
9147
9148 // Rotate Right by one
9149 instruct rorL_rReg_i1(rRegL dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
9150 %{
9151 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
9152
9153 expand %{
9154 rorL_rReg_imm1(dst, cr);
9155 %}
9156 %}
9157
9158 // Rotate Right by 8-bit immediate
9159 instruct rorL_rReg_i8(rRegL dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
9160 %{
9161 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
9162 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
9163
9164 expand %{
9165 rorL_rReg_imm8(dst, rshift, cr);
9166 %}
9167 %}
9168
9169 // Rotate Right by variable
9170 instruct rorL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
9171 %{
9172 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI zero shift))));
9173
9174 expand %{
9175 rorL_rReg_CL(dst, shift, cr);
9176 %}
9177 %}
9178
9179 // Rotate Right by variable
9180 instruct rorL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
9181 %{
9182 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI c64 shift))));
9183
9184 expand %{
9185 rorL_rReg_CL(dst, shift, cr);
9186 %}
9187 %}
9188
9189 // Logical Instructions
9190
9191 // Integer Logical Instructions
9192
9193 // And Instructions
9194 // And Register with Register
9195 instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9196 %{
9197 match(Set dst (AndI dst src));
9198 effect(KILL cr);
9199
9200 format %{ "andl $dst, $src\t# int" %}
9201 opcode(0x23);
9202 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9203 ins_pipe(ialu_reg_reg);
9204 %}
9205
9206 // And Register with Immediate 255
9207 instruct andI_rReg_imm255(rRegI dst, immI_255 src)
9208 %{
9209 match(Set dst (AndI dst src));
9210
9211 format %{ "movzbl $dst, $dst\t# int & 0xFF" %}
9212 opcode(0x0F, 0xB6);
9213 ins_encode(REX_reg_breg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9214 ins_pipe(ialu_reg);
9215 %}
9216
9217 // And Register with Immediate 255 and promote to long
9218 instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask)
9219 %{
9220 match(Set dst (ConvI2L (AndI src mask)));
9221
9222 format %{ "movzbl $dst, $src\t# int & 0xFF -> long" %}
9223 opcode(0x0F, 0xB6);
9224 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9225 ins_pipe(ialu_reg);
9226 %}
9227
9228 // And Register with Immediate 65535
9229 instruct andI_rReg_imm65535(rRegI dst, immI_65535 src)
9230 %{
9231 match(Set dst (AndI dst src));
9232
9233 format %{ "movzwl $dst, $dst\t# int & 0xFFFF" %}
9234 opcode(0x0F, 0xB7);
9235 ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9236 ins_pipe(ialu_reg);
9237 %}
9238
9239 // And Register with Immediate 65535 and promote to long
9240 instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask)
9241 %{
9242 match(Set dst (ConvI2L (AndI src mask)));
9243
9244 format %{ "movzwl $dst, $src\t# int & 0xFFFF -> long" %}
9245 opcode(0x0F, 0xB7);
9246 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9247 ins_pipe(ialu_reg);
9248 %}
9249
9250 // And Register with Immediate
9251 instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9252 %{
9253 match(Set dst (AndI dst src));
9254 effect(KILL cr);
9255
9256 format %{ "andl $dst, $src\t# int" %}
9257 opcode(0x81, 0x04); /* Opcode 81 /4 */
9258 ins_encode(OpcSErm(dst, src), Con8or32(src));
9259 ins_pipe(ialu_reg);
9260 %}
9261
9262 // And Register with Memory
9263 instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9264 %{
9265 match(Set dst (AndI dst (LoadI src)));
9266 effect(KILL cr);
9267
9268 ins_cost(125);
9269 format %{ "andl $dst, $src\t# int" %}
9270 opcode(0x23);
9271 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9272 ins_pipe(ialu_reg_mem);
9273 %}
9274
9275 // And Memory with Register
9276 instruct andB_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9277 %{
9278 match(Set dst (StoreB dst (AndI (LoadB dst) src)));
9279 effect(KILL cr);
9280
9281 ins_cost(150);
9282 format %{ "andb $dst, $src\t# byte" %}
9283 opcode(0x20);
9284 ins_encode(REX_breg_mem(src, dst), OpcP, reg_mem(src, dst));
9285 ins_pipe(ialu_mem_reg);
9286 %}
9287
9288 instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9289 %{
9290 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9291 effect(KILL cr);
9292
9293 ins_cost(150);
9294 format %{ "andl $dst, $src\t# int" %}
9295 opcode(0x21); /* Opcode 21 /r */
9296 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9297 ins_pipe(ialu_mem_reg);
9298 %}
9299
9300 // And Memory with Immediate
9301 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr)
9302 %{
9303 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9304 effect(KILL cr);
9305
9306 ins_cost(125);
9307 format %{ "andl $dst, $src\t# int" %}
9308 opcode(0x81, 0x4); /* Opcode 81 /4 id */
9309 ins_encode(REX_mem(dst), OpcSE(src),
9310 RM_opc_mem(secondary, dst), Con8or32(src));
9311 ins_pipe(ialu_mem_imm);
9312 %}
9313
9314 // BMI1 instructions
9315 instruct andnI_rReg_rReg_mem(rRegI dst, rRegI src1, memory src2, immI_M1 minus_1, rFlagsReg cr) %{
9316 match(Set dst (AndI (XorI src1 minus_1) (LoadI src2)));
9317 predicate(UseBMI1Instructions);
9318 effect(KILL cr);
9319
9320 ins_cost(125);
9321 format %{ "andnl $dst, $src1, $src2" %}
9322
9323 ins_encode %{
9324 __ andnl($dst$$Register, $src1$$Register, $src2$$Address);
9325 %}
9326 ins_pipe(ialu_reg_mem);
9327 %}
9328
9329 instruct andnI_rReg_rReg_rReg(rRegI dst, rRegI src1, rRegI src2, immI_M1 minus_1, rFlagsReg cr) %{
9330 match(Set dst (AndI (XorI src1 minus_1) src2));
9331 predicate(UseBMI1Instructions);
9332 effect(KILL cr);
9333
9334 format %{ "andnl $dst, $src1, $src2" %}
9335
9336 ins_encode %{
9337 __ andnl($dst$$Register, $src1$$Register, $src2$$Register);
9338 %}
9339 ins_pipe(ialu_reg);
9340 %}
9341
9342 instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI0 imm_zero, rFlagsReg cr) %{
9343 match(Set dst (AndI (SubI imm_zero src) src));
9344 predicate(UseBMI1Instructions);
9345 effect(KILL cr);
9346
9347 format %{ "blsil $dst, $src" %}
9348
9349 ins_encode %{
9350 __ blsil($dst$$Register, $src$$Register);
9351 %}
9352 ins_pipe(ialu_reg);
9353 %}
9354
9355 instruct blsiI_rReg_mem(rRegI dst, memory src, immI0 imm_zero, rFlagsReg cr) %{
9356 match(Set dst (AndI (SubI imm_zero (LoadI src) ) (LoadI src) ));
9357 predicate(UseBMI1Instructions);
9358 effect(KILL cr);
9359
9360 ins_cost(125);
9361 format %{ "blsil $dst, $src" %}
9362
9363 ins_encode %{
9364 __ blsil($dst$$Register, $src$$Address);
9365 %}
9366 ins_pipe(ialu_reg_mem);
9367 %}
9368
9369 instruct blsmskI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
9370 %{
9371 match(Set dst (XorI (AddI (LoadI src) minus_1) (LoadI src) ) );
9372 predicate(UseBMI1Instructions);
9373 effect(KILL cr);
9374
9375 ins_cost(125);
9376 format %{ "blsmskl $dst, $src" %}
9377
9378 ins_encode %{
9379 __ blsmskl($dst$$Register, $src$$Address);
9380 %}
9381 ins_pipe(ialu_reg_mem);
9382 %}
9383
9384 instruct blsmskI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
9385 %{
9386 match(Set dst (XorI (AddI src minus_1) src));
9387 predicate(UseBMI1Instructions);
9388 effect(KILL cr);
9389
9390 format %{ "blsmskl $dst, $src" %}
9391
9392 ins_encode %{
9393 __ blsmskl($dst$$Register, $src$$Register);
9394 %}
9395
9396 ins_pipe(ialu_reg);
9397 %}
9398
9399 instruct blsrI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
9400 %{
9401 match(Set dst (AndI (AddI src minus_1) src) );
9402 predicate(UseBMI1Instructions);
9403 effect(KILL cr);
9404
9405 format %{ "blsrl $dst, $src" %}
9406
9407 ins_encode %{
9408 __ blsrl($dst$$Register, $src$$Register);
9409 %}
9410
9411 ins_pipe(ialu_reg_mem);
9412 %}
9413
9414 instruct blsrI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
9415 %{
9416 match(Set dst (AndI (AddI (LoadI src) minus_1) (LoadI src) ) );
9417 predicate(UseBMI1Instructions);
9418 effect(KILL cr);
9419
9420 ins_cost(125);
9421 format %{ "blsrl $dst, $src" %}
9422
9423 ins_encode %{
9424 __ blsrl($dst$$Register, $src$$Address);
9425 %}
9426
9427 ins_pipe(ialu_reg);
9428 %}
9429
9430 // Or Instructions
9431 // Or Register with Register
9432 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9433 %{
9434 match(Set dst (OrI dst src));
9435 effect(KILL cr);
9436
9437 format %{ "orl $dst, $src\t# int" %}
9438 opcode(0x0B);
9439 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9440 ins_pipe(ialu_reg_reg);
9441 %}
9442
9443 // Or Register with Immediate
9444 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9445 %{
9446 match(Set dst (OrI dst src));
9447 effect(KILL cr);
9448
9449 format %{ "orl $dst, $src\t# int" %}
9450 opcode(0x81, 0x01); /* Opcode 81 /1 id */
9451 ins_encode(OpcSErm(dst, src), Con8or32(src));
9452 ins_pipe(ialu_reg);
9453 %}
9454
9455 // Or Register with Memory
9456 instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9457 %{
9458 match(Set dst (OrI dst (LoadI src)));
9459 effect(KILL cr);
9460
9461 ins_cost(125);
9462 format %{ "orl $dst, $src\t# int" %}
9463 opcode(0x0B);
9464 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9465 ins_pipe(ialu_reg_mem);
9466 %}
9467
9468 // Or Memory with Register
9469 instruct orB_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9470 %{
9471 match(Set dst (StoreB dst (OrI (LoadB dst) src)));
9472 effect(KILL cr);
9473
9474 ins_cost(150);
9475 format %{ "orb $dst, $src\t# byte" %}
9476 opcode(0x08);
9477 ins_encode(REX_breg_mem(src, dst), OpcP, reg_mem(src, dst));
9478 ins_pipe(ialu_mem_reg);
9479 %}
9480
9481 instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9482 %{
9483 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9484 effect(KILL cr);
9485
9486 ins_cost(150);
9487 format %{ "orl $dst, $src\t# int" %}
9488 opcode(0x09); /* Opcode 09 /r */
9489 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9490 ins_pipe(ialu_mem_reg);
9491 %}
9492
9493 // Or Memory with Immediate
9494 instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr)
9495 %{
9496 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9497 effect(KILL cr);
9498
9499 ins_cost(125);
9500 format %{ "orl $dst, $src\t# int" %}
9501 opcode(0x81, 0x1); /* Opcode 81 /1 id */
9502 ins_encode(REX_mem(dst), OpcSE(src),
9503 RM_opc_mem(secondary, dst), Con8or32(src));
9504 ins_pipe(ialu_mem_imm);
9505 %}
9506
9507 // Xor Instructions
9508 // Xor Register with Register
9509 instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9510 %{
9511 match(Set dst (XorI dst src));
9512 effect(KILL cr);
9513
9514 format %{ "xorl $dst, $src\t# int" %}
9515 opcode(0x33);
9516 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9517 ins_pipe(ialu_reg_reg);
9518 %}
9519
9520 // Xor Register with Immediate -1
9521 instruct xorI_rReg_im1(rRegI dst, immI_M1 imm) %{
9522 match(Set dst (XorI dst imm));
9523
9524 format %{ "not $dst" %}
9525 ins_encode %{
9526 __ notl($dst$$Register);
9527 %}
9528 ins_pipe(ialu_reg);
9529 %}
9530
9531 // Xor Register with Immediate
9532 instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9533 %{
9534 match(Set dst (XorI dst src));
9535 effect(KILL cr);
9536
9537 format %{ "xorl $dst, $src\t# int" %}
9538 opcode(0x81, 0x06); /* Opcode 81 /6 id */
9539 ins_encode(OpcSErm(dst, src), Con8or32(src));
9540 ins_pipe(ialu_reg);
9541 %}
9542
9543 // Xor Register with Memory
9544 instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9545 %{
9546 match(Set dst (XorI dst (LoadI src)));
9547 effect(KILL cr);
9548
9549 ins_cost(125);
9550 format %{ "xorl $dst, $src\t# int" %}
9551 opcode(0x33);
9552 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9553 ins_pipe(ialu_reg_mem);
9554 %}
9555
9556 // Xor Memory with Register
9557 instruct xorB_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9558 %{
9559 match(Set dst (StoreB dst (XorI (LoadB dst) src)));
9560 effect(KILL cr);
9561
9562 ins_cost(150);
9563 format %{ "xorb $dst, $src\t# byte" %}
9564 opcode(0x30);
9565 ins_encode(REX_breg_mem(src, dst), OpcP, reg_mem(src, dst));
9566 ins_pipe(ialu_mem_reg);
9567 %}
9568
9569 instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9570 %{
9571 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9572 effect(KILL cr);
9573
9574 ins_cost(150);
9575 format %{ "xorl $dst, $src\t# int" %}
9576 opcode(0x31); /* Opcode 31 /r */
9577 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9578 ins_pipe(ialu_mem_reg);
9579 %}
9580
9581 // Xor Memory with Immediate
9582 instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr)
9583 %{
9584 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9585 effect(KILL cr);
9586
9587 ins_cost(125);
9588 format %{ "xorl $dst, $src\t# int" %}
9589 opcode(0x81, 0x6); /* Opcode 81 /6 id */
9590 ins_encode(REX_mem(dst), OpcSE(src),
9591 RM_opc_mem(secondary, dst), Con8or32(src));
9592 ins_pipe(ialu_mem_imm);
9593 %}
9594
9595
9596 // Long Logical Instructions
9597
9598 // And Instructions
9599 // And Register with Register
9600 instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9601 %{
9602 match(Set dst (AndL dst src));
9603 effect(KILL cr);
9604
9605 format %{ "andq $dst, $src\t# long" %}
9606 opcode(0x23);
9607 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9608 ins_pipe(ialu_reg_reg);
9609 %}
9610
9611 // And Register with Immediate 255
9612 instruct andL_rReg_imm255(rRegL dst, immL_255 src)
9613 %{
9614 match(Set dst (AndL dst src));
9615
9616 format %{ "movzbq $dst, $dst\t# long & 0xFF" %}
9617 opcode(0x0F, 0xB6);
9618 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9619 ins_pipe(ialu_reg);
9620 %}
9621
9622 // And Register with Immediate 65535
9623 instruct andL_rReg_imm65535(rRegL dst, immL_65535 src)
9624 %{
9625 match(Set dst (AndL dst src));
9626
9627 format %{ "movzwq $dst, $dst\t# long & 0xFFFF" %}
9628 opcode(0x0F, 0xB7);
9629 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9630 ins_pipe(ialu_reg);
9631 %}
9632
9633 // And Register with Immediate
9634 instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9635 %{
9636 match(Set dst (AndL dst src));
9637 effect(KILL cr);
9638
9639 format %{ "andq $dst, $src\t# long" %}
9640 opcode(0x81, 0x04); /* Opcode 81 /4 */
9641 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9642 ins_pipe(ialu_reg);
9643 %}
9644
9645 // And Register with Memory
9646 instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9647 %{
9648 match(Set dst (AndL dst (LoadL src)));
9649 effect(KILL cr);
9650
9651 ins_cost(125);
9652 format %{ "andq $dst, $src\t# long" %}
9653 opcode(0x23);
9654 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9655 ins_pipe(ialu_reg_mem);
9656 %}
9657
9658 // And Memory with Register
9659 instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9660 %{
9661 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9662 effect(KILL cr);
9663
9664 ins_cost(150);
9665 format %{ "andq $dst, $src\t# long" %}
9666 opcode(0x21); /* Opcode 21 /r */
9667 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9668 ins_pipe(ialu_mem_reg);
9669 %}
9670
9671 // And Memory with Immediate
9672 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9673 %{
9674 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9675 effect(KILL cr);
9676
9677 ins_cost(125);
9678 format %{ "andq $dst, $src\t# long" %}
9679 opcode(0x81, 0x4); /* Opcode 81 /4 id */
9680 ins_encode(REX_mem_wide(dst), OpcSE(src),
9681 RM_opc_mem(secondary, dst), Con8or32(src));
9682 ins_pipe(ialu_mem_imm);
9683 %}
9684
9685 // BMI1 instructions
9686 instruct andnL_rReg_rReg_mem(rRegL dst, rRegL src1, memory src2, immL_M1 minus_1, rFlagsReg cr) %{
9687 match(Set dst (AndL (XorL src1 minus_1) (LoadL src2)));
9688 predicate(UseBMI1Instructions);
9689 effect(KILL cr);
9690
9691 ins_cost(125);
9692 format %{ "andnq $dst, $src1, $src2" %}
9693
9694 ins_encode %{
9695 __ andnq($dst$$Register, $src1$$Register, $src2$$Address);
9696 %}
9697 ins_pipe(ialu_reg_mem);
9698 %}
9699
9700 instruct andnL_rReg_rReg_rReg(rRegL dst, rRegL src1, rRegL src2, immL_M1 minus_1, rFlagsReg cr) %{
9701 match(Set dst (AndL (XorL src1 minus_1) src2));
9702 predicate(UseBMI1Instructions);
9703 effect(KILL cr);
9704
9705 format %{ "andnq $dst, $src1, $src2" %}
9706
9707 ins_encode %{
9708 __ andnq($dst$$Register, $src1$$Register, $src2$$Register);
9709 %}
9710 ins_pipe(ialu_reg_mem);
9711 %}
9712
9713 instruct blsiL_rReg_rReg(rRegL dst, rRegL src, immL0 imm_zero, rFlagsReg cr) %{
9714 match(Set dst (AndL (SubL imm_zero src) src));
9715 predicate(UseBMI1Instructions);
9716 effect(KILL cr);
9717
9718 format %{ "blsiq $dst, $src" %}
9719
9720 ins_encode %{
9721 __ blsiq($dst$$Register, $src$$Register);
9722 %}
9723 ins_pipe(ialu_reg);
9724 %}
9725
9726 instruct blsiL_rReg_mem(rRegL dst, memory src, immL0 imm_zero, rFlagsReg cr) %{
9727 match(Set dst (AndL (SubL imm_zero (LoadL src) ) (LoadL src) ));
9728 predicate(UseBMI1Instructions);
9729 effect(KILL cr);
9730
9731 ins_cost(125);
9732 format %{ "blsiq $dst, $src" %}
9733
9734 ins_encode %{
9735 __ blsiq($dst$$Register, $src$$Address);
9736 %}
9737 ins_pipe(ialu_reg_mem);
9738 %}
9739
9740 instruct blsmskL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
9741 %{
9742 match(Set dst (XorL (AddL (LoadL src) minus_1) (LoadL src) ) );
9743 predicate(UseBMI1Instructions);
9744 effect(KILL cr);
9745
9746 ins_cost(125);
9747 format %{ "blsmskq $dst, $src" %}
9748
9749 ins_encode %{
9750 __ blsmskq($dst$$Register, $src$$Address);
9751 %}
9752 ins_pipe(ialu_reg_mem);
9753 %}
9754
9755 instruct blsmskL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
9756 %{
9757 match(Set dst (XorL (AddL src minus_1) src));
9758 predicate(UseBMI1Instructions);
9759 effect(KILL cr);
9760
9761 format %{ "blsmskq $dst, $src" %}
9762
9763 ins_encode %{
9764 __ blsmskq($dst$$Register, $src$$Register);
9765 %}
9766
9767 ins_pipe(ialu_reg);
9768 %}
9769
9770 instruct blsrL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
9771 %{
9772 match(Set dst (AndL (AddL src minus_1) src) );
9773 predicate(UseBMI1Instructions);
9774 effect(KILL cr);
9775
9776 format %{ "blsrq $dst, $src" %}
9777
9778 ins_encode %{
9779 __ blsrq($dst$$Register, $src$$Register);
9780 %}
9781
9782 ins_pipe(ialu_reg);
9783 %}
9784
9785 instruct blsrL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
9786 %{
9787 match(Set dst (AndL (AddL (LoadL src) minus_1) (LoadL src)) );
9788 predicate(UseBMI1Instructions);
9789 effect(KILL cr);
9790
9791 ins_cost(125);
9792 format %{ "blsrq $dst, $src" %}
9793
9794 ins_encode %{
9795 __ blsrq($dst$$Register, $src$$Address);
9796 %}
9797
9798 ins_pipe(ialu_reg);
9799 %}
9800
9801 // Or Instructions
9802 // Or Register with Register
9803 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9804 %{
9805 match(Set dst (OrL dst src));
9806 effect(KILL cr);
9807
9808 format %{ "orq $dst, $src\t# long" %}
9809 opcode(0x0B);
9810 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9811 ins_pipe(ialu_reg_reg);
9812 %}
9813
9814 // Use any_RegP to match R15 (TLS register) without spilling.
9815 instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{
9816 match(Set dst (OrL dst (CastP2X src)));
9817 effect(KILL cr);
9818
9819 format %{ "orq $dst, $src\t# long" %}
9820 opcode(0x0B);
9821 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9822 ins_pipe(ialu_reg_reg);
9823 %}
9824
9825
9826 // Or Register with Immediate
9827 instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9828 %{
9829 match(Set dst (OrL dst src));
9830 effect(KILL cr);
9831
9832 format %{ "orq $dst, $src\t# long" %}
9833 opcode(0x81, 0x01); /* Opcode 81 /1 id */
9834 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9835 ins_pipe(ialu_reg);
9836 %}
9837
9838 // Or Register with Memory
9839 instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9840 %{
9841 match(Set dst (OrL dst (LoadL src)));
9842 effect(KILL cr);
9843
9844 ins_cost(125);
9845 format %{ "orq $dst, $src\t# long" %}
9846 opcode(0x0B);
9847 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9848 ins_pipe(ialu_reg_mem);
9849 %}
9850
9851 // Or Memory with Register
9852 instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9853 %{
9854 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
9855 effect(KILL cr);
9856
9857 ins_cost(150);
9858 format %{ "orq $dst, $src\t# long" %}
9859 opcode(0x09); /* Opcode 09 /r */
9860 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9861 ins_pipe(ialu_mem_reg);
9862 %}
9863
9864 // Or Memory with Immediate
9865 instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9866 %{
9867 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
9868 effect(KILL cr);
9869
9870 ins_cost(125);
9871 format %{ "orq $dst, $src\t# long" %}
9872 opcode(0x81, 0x1); /* Opcode 81 /1 id */
9873 ins_encode(REX_mem_wide(dst), OpcSE(src),
9874 RM_opc_mem(secondary, dst), Con8or32(src));
9875 ins_pipe(ialu_mem_imm);
9876 %}
9877
9878 // Xor Instructions
9879 // Xor Register with Register
9880 instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9881 %{
9882 match(Set dst (XorL dst src));
9883 effect(KILL cr);
9884
9885 format %{ "xorq $dst, $src\t# long" %}
9886 opcode(0x33);
9887 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9888 ins_pipe(ialu_reg_reg);
9889 %}
9890
9891 // Xor Register with Immediate -1
9892 instruct xorL_rReg_im1(rRegL dst, immL_M1 imm) %{
9893 match(Set dst (XorL dst imm));
9894
9895 format %{ "notq $dst" %}
9896 ins_encode %{
9897 __ notq($dst$$Register);
9898 %}
9899 ins_pipe(ialu_reg);
9900 %}
9901
9902 // Xor Register with Immediate
9903 instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9904 %{
9905 match(Set dst (XorL dst src));
9906 effect(KILL cr);
9907
9908 format %{ "xorq $dst, $src\t# long" %}
9909 opcode(0x81, 0x06); /* Opcode 81 /6 id */
9910 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9911 ins_pipe(ialu_reg);
9912 %}
9913
9914 // Xor Register with Memory
9915 instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9916 %{
9917 match(Set dst (XorL dst (LoadL src)));
9918 effect(KILL cr);
9919
9920 ins_cost(125);
9921 format %{ "xorq $dst, $src\t# long" %}
9922 opcode(0x33);
9923 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9924 ins_pipe(ialu_reg_mem);
9925 %}
9926
9927 // Xor Memory with Register
9928 instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9929 %{
9930 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
9931 effect(KILL cr);
9932
9933 ins_cost(150);
9934 format %{ "xorq $dst, $src\t# long" %}
9935 opcode(0x31); /* Opcode 31 /r */
9936 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9937 ins_pipe(ialu_mem_reg);
9938 %}
9939
9940 // Xor Memory with Immediate
9941 instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9942 %{
9943 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
9944 effect(KILL cr);
9945
9946 ins_cost(125);
9947 format %{ "xorq $dst, $src\t# long" %}
9948 opcode(0x81, 0x6); /* Opcode 81 /6 id */
9949 ins_encode(REX_mem_wide(dst), OpcSE(src),
9950 RM_opc_mem(secondary, dst), Con8or32(src));
9951 ins_pipe(ialu_mem_imm);
9952 %}
9953
9954 // Convert Int to Boolean
9955 instruct convI2B(rRegI dst, rRegI src, rFlagsReg cr)
9956 %{
9957 match(Set dst (Conv2B src));
9958 effect(KILL cr);
9959
9960 format %{ "testl $src, $src\t# ci2b\n\t"
9961 "setnz $dst\n\t"
9962 "movzbl $dst, $dst" %}
9963 ins_encode(REX_reg_reg(src, src), opc_reg_reg(0x85, src, src), // testl
9964 setNZ_reg(dst),
9965 REX_reg_breg(dst, dst), // movzbl
9966 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
9967 ins_pipe(pipe_slow); // XXX
9968 %}
9969
9970 // Convert Pointer to Boolean
9971 instruct convP2B(rRegI dst, rRegP src, rFlagsReg cr)
9972 %{
9973 match(Set dst (Conv2B src));
9974 effect(KILL cr);
9975
9976 format %{ "testq $src, $src\t# cp2b\n\t"
9977 "setnz $dst\n\t"
9978 "movzbl $dst, $dst" %}
9979 ins_encode(REX_reg_reg_wide(src, src), opc_reg_reg(0x85, src, src), // testq
9980 setNZ_reg(dst),
9981 REX_reg_breg(dst, dst), // movzbl
9982 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
9983 ins_pipe(pipe_slow); // XXX
9984 %}
9985
9986 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr)
9987 %{
9988 match(Set dst (CmpLTMask p q));
9989 effect(KILL cr);
9990
9991 ins_cost(400);
9992 format %{ "cmpl $p, $q\t# cmpLTMask\n\t"
9993 "setlt $dst\n\t"
9994 "movzbl $dst, $dst\n\t"
9995 "negl $dst" %}
9996 ins_encode(REX_reg_reg(p, q), opc_reg_reg(0x3B, p, q), // cmpl
9997 setLT_reg(dst),
9998 REX_reg_breg(dst, dst), // movzbl
9999 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst),
10000 neg_reg(dst));
10001 ins_pipe(pipe_slow);
10002 %}
10003
10004 instruct cmpLTMask0(rRegI dst, immI0 zero, rFlagsReg cr)
10005 %{
10006 match(Set dst (CmpLTMask dst zero));
10007 effect(KILL cr);
10008
10009 ins_cost(100);
10010 format %{ "sarl $dst, #31\t# cmpLTMask0" %}
10011 ins_encode %{
10012 __ sarl($dst$$Register, 31);
10013 %}
10014 ins_pipe(ialu_reg);
10015 %}
10016
10017 /* Better to save a register than avoid a branch */
10018 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
10019 %{
10020 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
10021 effect(KILL cr);
10022 ins_cost(300);
10023 format %{ "subl $p,$q\t# cadd_cmpLTMask\n\t"
10024 "jge done\n\t"
10025 "addl $p,$y\n"
10026 "done: " %}
10027 ins_encode %{
10028 Register Rp = $p$$Register;
10029 Register Rq = $q$$Register;
10030 Register Ry = $y$$Register;
10031 Label done;
10032 __ subl(Rp, Rq);
10033 __ jccb(Assembler::greaterEqual, done);
10034 __ addl(Rp, Ry);
10035 __ bind(done);
10036 %}
10037 ins_pipe(pipe_cmplt);
10038 %}
10039
10040 /* Better to save a register than avoid a branch */
10041 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
10042 %{
10043 match(Set y (AndI (CmpLTMask p q) y));
10044 effect(KILL cr);
10045
10046 ins_cost(300);
10047
10048 format %{ "cmpl $p, $q\t# and_cmpLTMask\n\t"
10049 "jlt done\n\t"
10050 "xorl $y, $y\n"
10051 "done: " %}
10052 ins_encode %{
10053 Register Rp = $p$$Register;
10054 Register Rq = $q$$Register;
10055 Register Ry = $y$$Register;
10056 Label done;
10057 __ cmpl(Rp, Rq);
10058 __ jccb(Assembler::less, done);
10059 __ xorl(Ry, Ry);
10060 __ bind(done);
10061 %}
10062 ins_pipe(pipe_cmplt);
10063 %}
10064
10065
10066 //---------- FP Instructions------------------------------------------------
10067
10068 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2)
10069 %{
10070 match(Set cr (CmpF src1 src2));
10071
10072 ins_cost(145);
10073 format %{ "ucomiss $src1, $src2\n\t"
10074 "jnp,s exit\n\t"
10075 "pushfq\t# saw NaN, set CF\n\t"
10076 "andq [rsp], #0xffffff2b\n\t"
10077 "popfq\n"
10078 "exit:" %}
10079 ins_encode %{
10080 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10081 emit_cmpfp_fixup(_masm);
10082 %}
10083 ins_pipe(pipe_slow);
10084 %}
10085
10086 instruct cmpF_cc_reg_CF(rFlagsRegUCF cr, regF src1, regF src2) %{
10087 match(Set cr (CmpF src1 src2));
10088
10089 ins_cost(100);
10090 format %{ "ucomiss $src1, $src2" %}
10091 ins_encode %{
10092 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10093 %}
10094 ins_pipe(pipe_slow);
10095 %}
10096
10097 instruct cmpF_cc_mem(rFlagsRegU cr, regF src1, memory src2)
10098 %{
10099 match(Set cr (CmpF src1 (LoadF src2)));
10100
10101 ins_cost(145);
10102 format %{ "ucomiss $src1, $src2\n\t"
10103 "jnp,s exit\n\t"
10104 "pushfq\t# saw NaN, set CF\n\t"
10105 "andq [rsp], #0xffffff2b\n\t"
10106 "popfq\n"
10107 "exit:" %}
10108 ins_encode %{
10109 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10110 emit_cmpfp_fixup(_masm);
10111 %}
10112 ins_pipe(pipe_slow);
10113 %}
10114
10115 instruct cmpF_cc_memCF(rFlagsRegUCF cr, regF src1, memory src2) %{
10116 match(Set cr (CmpF src1 (LoadF src2)));
10117
10118 ins_cost(100);
10119 format %{ "ucomiss $src1, $src2" %}
10120 ins_encode %{
10121 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10122 %}
10123 ins_pipe(pipe_slow);
10124 %}
10125
10126 instruct cmpF_cc_imm(rFlagsRegU cr, regF src, immF con) %{
10127 match(Set cr (CmpF src con));
10128
10129 ins_cost(145);
10130 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
10131 "jnp,s exit\n\t"
10132 "pushfq\t# saw NaN, set CF\n\t"
10133 "andq [rsp], #0xffffff2b\n\t"
10134 "popfq\n"
10135 "exit:" %}
10136 ins_encode %{
10137 __ ucomiss($src$$XMMRegister, $constantaddress($con));
10138 emit_cmpfp_fixup(_masm);
10139 %}
10140 ins_pipe(pipe_slow);
10141 %}
10142
10143 instruct cmpF_cc_immCF(rFlagsRegUCF cr, regF src, immF con) %{
10144 match(Set cr (CmpF src con));
10145 ins_cost(100);
10146 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con" %}
10147 ins_encode %{
10148 __ ucomiss($src$$XMMRegister, $constantaddress($con));
10149 %}
10150 ins_pipe(pipe_slow);
10151 %}
10152
10153 instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2)
10154 %{
10155 match(Set cr (CmpD src1 src2));
10156
10157 ins_cost(145);
10158 format %{ "ucomisd $src1, $src2\n\t"
10159 "jnp,s exit\n\t"
10160 "pushfq\t# saw NaN, set CF\n\t"
10161 "andq [rsp], #0xffffff2b\n\t"
10162 "popfq\n"
10163 "exit:" %}
10164 ins_encode %{
10165 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
10166 emit_cmpfp_fixup(_masm);
10167 %}
10168 ins_pipe(pipe_slow);
10169 %}
10170
10171 instruct cmpD_cc_reg_CF(rFlagsRegUCF cr, regD src1, regD src2) %{
10172 match(Set cr (CmpD src1 src2));
10173
10174 ins_cost(100);
10175 format %{ "ucomisd $src1, $src2 test" %}
10176 ins_encode %{
10177 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
10178 %}
10179 ins_pipe(pipe_slow);
10180 %}
10181
10182 instruct cmpD_cc_mem(rFlagsRegU cr, regD src1, memory src2)
10183 %{
10184 match(Set cr (CmpD src1 (LoadD src2)));
10185
10186 ins_cost(145);
10187 format %{ "ucomisd $src1, $src2\n\t"
10188 "jnp,s exit\n\t"
10189 "pushfq\t# saw NaN, set CF\n\t"
10190 "andq [rsp], #0xffffff2b\n\t"
10191 "popfq\n"
10192 "exit:" %}
10193 ins_encode %{
10194 __ ucomisd($src1$$XMMRegister, $src2$$Address);
10195 emit_cmpfp_fixup(_masm);
10196 %}
10197 ins_pipe(pipe_slow);
10198 %}
10199
10200 instruct cmpD_cc_memCF(rFlagsRegUCF cr, regD src1, memory src2) %{
10201 match(Set cr (CmpD src1 (LoadD src2)));
10202
10203 ins_cost(100);
10204 format %{ "ucomisd $src1, $src2" %}
10205 ins_encode %{
10206 __ ucomisd($src1$$XMMRegister, $src2$$Address);
10207 %}
10208 ins_pipe(pipe_slow);
10209 %}
10210
10211 instruct cmpD_cc_imm(rFlagsRegU cr, regD src, immD con) %{
10212 match(Set cr (CmpD src con));
10213
10214 ins_cost(145);
10215 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
10216 "jnp,s exit\n\t"
10217 "pushfq\t# saw NaN, set CF\n\t"
10218 "andq [rsp], #0xffffff2b\n\t"
10219 "popfq\n"
10220 "exit:" %}
10221 ins_encode %{
10222 __ ucomisd($src$$XMMRegister, $constantaddress($con));
10223 emit_cmpfp_fixup(_masm);
10224 %}
10225 ins_pipe(pipe_slow);
10226 %}
10227
10228 instruct cmpD_cc_immCF(rFlagsRegUCF cr, regD src, immD con) %{
10229 match(Set cr (CmpD src con));
10230 ins_cost(100);
10231 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con" %}
10232 ins_encode %{
10233 __ ucomisd($src$$XMMRegister, $constantaddress($con));
10234 %}
10235 ins_pipe(pipe_slow);
10236 %}
10237
10238 // Compare into -1,0,1
10239 instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr)
10240 %{
10241 match(Set dst (CmpF3 src1 src2));
10242 effect(KILL cr);
10243
10244 ins_cost(275);
10245 format %{ "ucomiss $src1, $src2\n\t"
10246 "movl $dst, #-1\n\t"
10247 "jp,s done\n\t"
10248 "jb,s done\n\t"
10249 "setne $dst\n\t"
10250 "movzbl $dst, $dst\n"
10251 "done:" %}
10252 ins_encode %{
10253 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10254 emit_cmpfp3(_masm, $dst$$Register);
10255 %}
10256 ins_pipe(pipe_slow);
10257 %}
10258
10259 // Compare into -1,0,1
10260 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr)
10261 %{
10262 match(Set dst (CmpF3 src1 (LoadF src2)));
10263 effect(KILL cr);
10264
10265 ins_cost(275);
10266 format %{ "ucomiss $src1, $src2\n\t"
10267 "movl $dst, #-1\n\t"
10268 "jp,s done\n\t"
10269 "jb,s done\n\t"
10270 "setne $dst\n\t"
10271 "movzbl $dst, $dst\n"
10272 "done:" %}
10273 ins_encode %{
10274 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10275 emit_cmpfp3(_masm, $dst$$Register);
10276 %}
10277 ins_pipe(pipe_slow);
10278 %}
10279
10280 // Compare into -1,0,1
10281 instruct cmpF_imm(rRegI dst, regF src, immF con, rFlagsReg cr) %{
10282 match(Set dst (CmpF3 src con));
10283 effect(KILL cr);
10284
10285 ins_cost(275);
10286 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
10287 "movl $dst, #-1\n\t"
10288 "jp,s done\n\t"
10289 "jb,s done\n\t"
10290 "setne $dst\n\t"
10291 "movzbl $dst, $dst\n"
10292 "done:" %}
10293 ins_encode %{
10294 __ ucomiss($src$$XMMRegister, $constantaddress($con));
10295 emit_cmpfp3(_masm, $dst$$Register);
10296 %}
10297 ins_pipe(pipe_slow);
10298 %}
10299
10300 // Compare into -1,0,1
10301 instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr)
10302 %{
10303 match(Set dst (CmpD3 src1 src2));
10304 effect(KILL cr);
10305
10306 ins_cost(275);
10307 format %{ "ucomisd $src1, $src2\n\t"
10308 "movl $dst, #-1\n\t"
10309 "jp,s done\n\t"
10310 "jb,s done\n\t"
10311 "setne $dst\n\t"
10312 "movzbl $dst, $dst\n"
10313 "done:" %}
10314 ins_encode %{
10315 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
10316 emit_cmpfp3(_masm, $dst$$Register);
10317 %}
10318 ins_pipe(pipe_slow);
10319 %}
10320
10321 // Compare into -1,0,1
10322 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr)
10323 %{
10324 match(Set dst (CmpD3 src1 (LoadD src2)));
10325 effect(KILL cr);
10326
10327 ins_cost(275);
10328 format %{ "ucomisd $src1, $src2\n\t"
10329 "movl $dst, #-1\n\t"
10330 "jp,s done\n\t"
10331 "jb,s done\n\t"
10332 "setne $dst\n\t"
10333 "movzbl $dst, $dst\n"
10334 "done:" %}
10335 ins_encode %{
10336 __ ucomisd($src1$$XMMRegister, $src2$$Address);
10337 emit_cmpfp3(_masm, $dst$$Register);
10338 %}
10339 ins_pipe(pipe_slow);
10340 %}
10341
10342 // Compare into -1,0,1
10343 instruct cmpD_imm(rRegI dst, regD src, immD con, rFlagsReg cr) %{
10344 match(Set dst (CmpD3 src con));
10345 effect(KILL cr);
10346
10347 ins_cost(275);
10348 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
10349 "movl $dst, #-1\n\t"
10350 "jp,s done\n\t"
10351 "jb,s done\n\t"
10352 "setne $dst\n\t"
10353 "movzbl $dst, $dst\n"
10354 "done:" %}
10355 ins_encode %{
10356 __ ucomisd($src$$XMMRegister, $constantaddress($con));
10357 emit_cmpfp3(_masm, $dst$$Register);
10358 %}
10359 ins_pipe(pipe_slow);
10360 %}
10361
10362 //----------Arithmetic Conversion Instructions---------------------------------
10363
10364 instruct roundFloat_nop(regF dst)
10365 %{
10366 match(Set dst (RoundFloat dst));
10367
10368 ins_cost(0);
10369 ins_encode();
10370 ins_pipe(empty);
10371 %}
10372
10373 instruct roundDouble_nop(regD dst)
10374 %{
10375 match(Set dst (RoundDouble dst));
10376
10377 ins_cost(0);
10378 ins_encode();
10379 ins_pipe(empty);
10380 %}
10381
10382 instruct convF2D_reg_reg(regD dst, regF src)
10383 %{
10384 match(Set dst (ConvF2D src));
10385
10386 format %{ "cvtss2sd $dst, $src" %}
10387 ins_encode %{
10388 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
10389 %}
10390 ins_pipe(pipe_slow); // XXX
10391 %}
10392
10393 instruct convF2D_reg_mem(regD dst, memory src)
10394 %{
10395 match(Set dst (ConvF2D (LoadF src)));
10396
10397 format %{ "cvtss2sd $dst, $src" %}
10398 ins_encode %{
10399 __ cvtss2sd ($dst$$XMMRegister, $src$$Address);
10400 %}
10401 ins_pipe(pipe_slow); // XXX
10402 %}
10403
10404 instruct convD2F_reg_reg(regF dst, regD src)
10405 %{
10406 match(Set dst (ConvD2F src));
10407
10408 format %{ "cvtsd2ss $dst, $src" %}
10409 ins_encode %{
10410 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
10411 %}
10412 ins_pipe(pipe_slow); // XXX
10413 %}
10414
10415 instruct convD2F_reg_mem(regF dst, memory src)
10416 %{
10417 match(Set dst (ConvD2F (LoadD src)));
10418
10419 format %{ "cvtsd2ss $dst, $src" %}
10420 ins_encode %{
10421 __ cvtsd2ss ($dst$$XMMRegister, $src$$Address);
10422 %}
10423 ins_pipe(pipe_slow); // XXX
10424 %}
10425
10426 // XXX do mem variants
10427 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr)
10428 %{
10429 match(Set dst (ConvF2I src));
10430 effect(KILL cr);
10431
10432 format %{ "cvttss2sil $dst, $src\t# f2i\n\t"
10433 "cmpl $dst, #0x80000000\n\t"
10434 "jne,s done\n\t"
10435 "subq rsp, #8\n\t"
10436 "movss [rsp], $src\n\t"
10437 "call f2i_fixup\n\t"
10438 "popq $dst\n"
10439 "done: "%}
10440 ins_encode %{
10441 Label done;
10442 __ cvttss2sil($dst$$Register, $src$$XMMRegister);
10443 __ cmpl($dst$$Register, 0x80000000);
10444 __ jccb(Assembler::notEqual, done);
10445 __ subptr(rsp, 8);
10446 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10447 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup())));
10448 __ pop($dst$$Register);
10449 __ bind(done);
10450 %}
10451 ins_pipe(pipe_slow);
10452 %}
10453
10454 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr)
10455 %{
10456 match(Set dst (ConvF2L src));
10457 effect(KILL cr);
10458
10459 format %{ "cvttss2siq $dst, $src\t# f2l\n\t"
10460 "cmpq $dst, [0x8000000000000000]\n\t"
10461 "jne,s done\n\t"
10462 "subq rsp, #8\n\t"
10463 "movss [rsp], $src\n\t"
10464 "call f2l_fixup\n\t"
10465 "popq $dst\n"
10466 "done: "%}
10467 ins_encode %{
10468 Label done;
10469 __ cvttss2siq($dst$$Register, $src$$XMMRegister);
10470 __ cmp64($dst$$Register,
10471 ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10472 __ jccb(Assembler::notEqual, done);
10473 __ subptr(rsp, 8);
10474 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10475 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup())));
10476 __ pop($dst$$Register);
10477 __ bind(done);
10478 %}
10479 ins_pipe(pipe_slow);
10480 %}
10481
10482 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr)
10483 %{
10484 match(Set dst (ConvD2I src));
10485 effect(KILL cr);
10486
10487 format %{ "cvttsd2sil $dst, $src\t# d2i\n\t"
10488 "cmpl $dst, #0x80000000\n\t"
10489 "jne,s done\n\t"
10490 "subq rsp, #8\n\t"
10491 "movsd [rsp], $src\n\t"
10492 "call d2i_fixup\n\t"
10493 "popq $dst\n"
10494 "done: "%}
10495 ins_encode %{
10496 Label done;
10497 __ cvttsd2sil($dst$$Register, $src$$XMMRegister);
10498 __ cmpl($dst$$Register, 0x80000000);
10499 __ jccb(Assembler::notEqual, done);
10500 __ subptr(rsp, 8);
10501 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10502 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup())));
10503 __ pop($dst$$Register);
10504 __ bind(done);
10505 %}
10506 ins_pipe(pipe_slow);
10507 %}
10508
10509 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr)
10510 %{
10511 match(Set dst (ConvD2L src));
10512 effect(KILL cr);
10513
10514 format %{ "cvttsd2siq $dst, $src\t# d2l\n\t"
10515 "cmpq $dst, [0x8000000000000000]\n\t"
10516 "jne,s done\n\t"
10517 "subq rsp, #8\n\t"
10518 "movsd [rsp], $src\n\t"
10519 "call d2l_fixup\n\t"
10520 "popq $dst\n"
10521 "done: "%}
10522 ins_encode %{
10523 Label done;
10524 __ cvttsd2siq($dst$$Register, $src$$XMMRegister);
10525 __ cmp64($dst$$Register,
10526 ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10527 __ jccb(Assembler::notEqual, done);
10528 __ subptr(rsp, 8);
10529 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10530 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
10531 __ pop($dst$$Register);
10532 __ bind(done);
10533 %}
10534 ins_pipe(pipe_slow);
10535 %}
10536
10537 instruct convI2F_reg_reg(regF dst, rRegI src)
10538 %{
10539 predicate(!UseXmmI2F);
10540 match(Set dst (ConvI2F src));
10541
10542 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10543 ins_encode %{
10544 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
10545 %}
10546 ins_pipe(pipe_slow); // XXX
10547 %}
10548
10549 instruct convI2F_reg_mem(regF dst, memory src)
10550 %{
10551 match(Set dst (ConvI2F (LoadI src)));
10552
10553 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10554 ins_encode %{
10555 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Address);
10556 %}
10557 ins_pipe(pipe_slow); // XXX
10558 %}
10559
10560 instruct convI2D_reg_reg(regD dst, rRegI src)
10561 %{
10562 predicate(!UseXmmI2D);
10563 match(Set dst (ConvI2D src));
10564
10565 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10566 ins_encode %{
10567 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
10568 %}
10569 ins_pipe(pipe_slow); // XXX
10570 %}
10571
10572 instruct convI2D_reg_mem(regD dst, memory src)
10573 %{
10574 match(Set dst (ConvI2D (LoadI src)));
10575
10576 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10577 ins_encode %{
10578 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Address);
10579 %}
10580 ins_pipe(pipe_slow); // XXX
10581 %}
10582
10583 instruct convXI2F_reg(regF dst, rRegI src)
10584 %{
10585 predicate(UseXmmI2F);
10586 match(Set dst (ConvI2F src));
10587
10588 format %{ "movdl $dst, $src\n\t"
10589 "cvtdq2psl $dst, $dst\t# i2f" %}
10590 ins_encode %{
10591 __ movdl($dst$$XMMRegister, $src$$Register);
10592 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
10593 %}
10594 ins_pipe(pipe_slow); // XXX
10595 %}
10596
10597 instruct convXI2D_reg(regD dst, rRegI src)
10598 %{
10599 predicate(UseXmmI2D);
10600 match(Set dst (ConvI2D src));
10601
10602 format %{ "movdl $dst, $src\n\t"
10603 "cvtdq2pdl $dst, $dst\t# i2d" %}
10604 ins_encode %{
10605 __ movdl($dst$$XMMRegister, $src$$Register);
10606 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
10607 %}
10608 ins_pipe(pipe_slow); // XXX
10609 %}
10610
10611 instruct convL2F_reg_reg(regF dst, rRegL src)
10612 %{
10613 match(Set dst (ConvL2F src));
10614
10615 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10616 ins_encode %{
10617 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Register);
10618 %}
10619 ins_pipe(pipe_slow); // XXX
10620 %}
10621
10622 instruct convL2F_reg_mem(regF dst, memory src)
10623 %{
10624 match(Set dst (ConvL2F (LoadL src)));
10625
10626 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10627 ins_encode %{
10628 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Address);
10629 %}
10630 ins_pipe(pipe_slow); // XXX
10631 %}
10632
10633 instruct convL2D_reg_reg(regD dst, rRegL src)
10634 %{
10635 match(Set dst (ConvL2D src));
10636
10637 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10638 ins_encode %{
10639 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Register);
10640 %}
10641 ins_pipe(pipe_slow); // XXX
10642 %}
10643
10644 instruct convL2D_reg_mem(regD dst, memory src)
10645 %{
10646 match(Set dst (ConvL2D (LoadL src)));
10647
10648 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10649 ins_encode %{
10650 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Address);
10651 %}
10652 ins_pipe(pipe_slow); // XXX
10653 %}
10654
10655 instruct convI2L_reg_reg(rRegL dst, rRegI src)
10656 %{
10657 match(Set dst (ConvI2L src));
10658
10659 ins_cost(125);
10660 format %{ "movslq $dst, $src\t# i2l" %}
10661 ins_encode %{
10662 __ movslq($dst$$Register, $src$$Register);
10663 %}
10664 ins_pipe(ialu_reg_reg);
10665 %}
10666
10667 // instruct convI2L_reg_reg_foo(rRegL dst, rRegI src)
10668 // %{
10669 // match(Set dst (ConvI2L src));
10670 // // predicate(_kids[0]->_leaf->as_Type()->type()->is_int()->_lo >= 0 &&
10671 // // _kids[0]->_leaf->as_Type()->type()->is_int()->_hi >= 0);
10672 // predicate(((const TypeNode*) n)->type()->is_long()->_hi ==
10673 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_hi &&
10674 // ((const TypeNode*) n)->type()->is_long()->_lo ==
10675 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_lo);
10676
10677 // format %{ "movl $dst, $src\t# unsigned i2l" %}
10678 // ins_encode(enc_copy(dst, src));
10679 // // opcode(0x63); // needs REX.W
10680 // // ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src));
10681 // ins_pipe(ialu_reg_reg);
10682 // %}
10683
10684 // Zero-extend convert int to long
10685 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask)
10686 %{
10687 match(Set dst (AndL (ConvI2L src) mask));
10688
10689 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
10690 ins_encode %{
10691 if ($dst$$reg != $src$$reg) {
10692 __ movl($dst$$Register, $src$$Register);
10693 }
10694 %}
10695 ins_pipe(ialu_reg_reg);
10696 %}
10697
10698 // Zero-extend convert int to long
10699 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask)
10700 %{
10701 match(Set dst (AndL (ConvI2L (LoadI src)) mask));
10702
10703 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
10704 ins_encode %{
10705 __ movl($dst$$Register, $src$$Address);
10706 %}
10707 ins_pipe(ialu_reg_mem);
10708 %}
10709
10710 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask)
10711 %{
10712 match(Set dst (AndL src mask));
10713
10714 format %{ "movl $dst, $src\t# zero-extend long" %}
10715 ins_encode %{
10716 __ movl($dst$$Register, $src$$Register);
10717 %}
10718 ins_pipe(ialu_reg_reg);
10719 %}
10720
10721 instruct convL2I_reg_reg(rRegI dst, rRegL src)
10722 %{
10723 match(Set dst (ConvL2I src));
10724
10725 format %{ "movl $dst, $src\t# l2i" %}
10726 ins_encode %{
10727 __ movl($dst$$Register, $src$$Register);
10728 %}
10729 ins_pipe(ialu_reg_reg);
10730 %}
10731
10732
10733 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
10734 match(Set dst (MoveF2I src));
10735 effect(DEF dst, USE src);
10736
10737 ins_cost(125);
10738 format %{ "movl $dst, $src\t# MoveF2I_stack_reg" %}
10739 ins_encode %{
10740 __ movl($dst$$Register, Address(rsp, $src$$disp));
10741 %}
10742 ins_pipe(ialu_reg_mem);
10743 %}
10744
10745 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
10746 match(Set dst (MoveI2F src));
10747 effect(DEF dst, USE src);
10748
10749 ins_cost(125);
10750 format %{ "movss $dst, $src\t# MoveI2F_stack_reg" %}
10751 ins_encode %{
10752 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
10753 %}
10754 ins_pipe(pipe_slow);
10755 %}
10756
10757 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{
10758 match(Set dst (MoveD2L src));
10759 effect(DEF dst, USE src);
10760
10761 ins_cost(125);
10762 format %{ "movq $dst, $src\t# MoveD2L_stack_reg" %}
10763 ins_encode %{
10764 __ movq($dst$$Register, Address(rsp, $src$$disp));
10765 %}
10766 ins_pipe(ialu_reg_mem);
10767 %}
10768
10769 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{
10770 predicate(!UseXmmLoadAndClearUpper);
10771 match(Set dst (MoveL2D src));
10772 effect(DEF dst, USE src);
10773
10774 ins_cost(125);
10775 format %{ "movlpd $dst, $src\t# MoveL2D_stack_reg" %}
10776 ins_encode %{
10777 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
10778 %}
10779 ins_pipe(pipe_slow);
10780 %}
10781
10782 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
10783 predicate(UseXmmLoadAndClearUpper);
10784 match(Set dst (MoveL2D src));
10785 effect(DEF dst, USE src);
10786
10787 ins_cost(125);
10788 format %{ "movsd $dst, $src\t# MoveL2D_stack_reg" %}
10789 ins_encode %{
10790 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
10791 %}
10792 ins_pipe(pipe_slow);
10793 %}
10794
10795
10796 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
10797 match(Set dst (MoveF2I src));
10798 effect(DEF dst, USE src);
10799
10800 ins_cost(95); // XXX
10801 format %{ "movss $dst, $src\t# MoveF2I_reg_stack" %}
10802 ins_encode %{
10803 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
10804 %}
10805 ins_pipe(pipe_slow);
10806 %}
10807
10808 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
10809 match(Set dst (MoveI2F src));
10810 effect(DEF dst, USE src);
10811
10812 ins_cost(100);
10813 format %{ "movl $dst, $src\t# MoveI2F_reg_stack" %}
10814 ins_encode %{
10815 __ movl(Address(rsp, $dst$$disp), $src$$Register);
10816 %}
10817 ins_pipe( ialu_mem_reg );
10818 %}
10819
10820 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
10821 match(Set dst (MoveD2L src));
10822 effect(DEF dst, USE src);
10823
10824 ins_cost(95); // XXX
10825 format %{ "movsd $dst, $src\t# MoveL2D_reg_stack" %}
10826 ins_encode %{
10827 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
10828 %}
10829 ins_pipe(pipe_slow);
10830 %}
10831
10832 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{
10833 match(Set dst (MoveL2D src));
10834 effect(DEF dst, USE src);
10835
10836 ins_cost(100);
10837 format %{ "movq $dst, $src\t# MoveL2D_reg_stack" %}
10838 ins_encode %{
10839 __ movq(Address(rsp, $dst$$disp), $src$$Register);
10840 %}
10841 ins_pipe(ialu_mem_reg);
10842 %}
10843
10844 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{
10845 match(Set dst (MoveF2I src));
10846 effect(DEF dst, USE src);
10847 ins_cost(85);
10848 format %{ "movd $dst,$src\t# MoveF2I" %}
10849 ins_encode %{
10850 __ movdl($dst$$Register, $src$$XMMRegister);
10851 %}
10852 ins_pipe( pipe_slow );
10853 %}
10854
10855 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{
10856 match(Set dst (MoveD2L src));
10857 effect(DEF dst, USE src);
10858 ins_cost(85);
10859 format %{ "movd $dst,$src\t# MoveD2L" %}
10860 ins_encode %{
10861 __ movdq($dst$$Register, $src$$XMMRegister);
10862 %}
10863 ins_pipe( pipe_slow );
10864 %}
10865
10866 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{
10867 match(Set dst (MoveI2F src));
10868 effect(DEF dst, USE src);
10869 ins_cost(100);
10870 format %{ "movd $dst,$src\t# MoveI2F" %}
10871 ins_encode %{
10872 __ movdl($dst$$XMMRegister, $src$$Register);
10873 %}
10874 ins_pipe( pipe_slow );
10875 %}
10876
10877 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{
10878 match(Set dst (MoveL2D src));
10879 effect(DEF dst, USE src);
10880 ins_cost(100);
10881 format %{ "movd $dst,$src\t# MoveL2D" %}
10882 ins_encode %{
10883 __ movdq($dst$$XMMRegister, $src$$Register);
10884 %}
10885 ins_pipe( pipe_slow );
10886 %}
10887
10888
10889 // =======================================================================
10890 // fast clearing of an array
10891 instruct rep_stos(rcx_RegL cnt, rdi_RegP base, regD tmp, rax_RegI zero,
10892 Universe dummy, rFlagsReg cr)
10893 %{
10894 predicate(!((ClearArrayNode*)n)->is_large());
10895 match(Set dummy (ClearArray cnt base));
10896 effect(USE_KILL cnt, USE_KILL base, TEMP tmp, KILL zero, KILL cr);
10897
10898 format %{ $$template
10899 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
10900 $$emit$$"cmp InitArrayShortSize,rcx\n\t"
10901 $$emit$$"jg LARGE\n\t"
10902 $$emit$$"dec rcx\n\t"
10903 $$emit$$"js DONE\t# Zero length\n\t"
10904 $$emit$$"mov rax,(rdi,rcx,8)\t# LOOP\n\t"
10905 $$emit$$"dec rcx\n\t"
10906 $$emit$$"jge LOOP\n\t"
10907 $$emit$$"jmp DONE\n\t"
10908 $$emit$$"# LARGE:\n\t"
10909 if (UseFastStosb) {
10910 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t"
10911 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--\n\t"
10912 } else if (UseXMMForObjInit) {
10913 $$emit$$"mov rdi,rax\n\t"
10914 $$emit$$"vpxor ymm0,ymm0,ymm0\n\t"
10915 $$emit$$"jmpq L_zero_64_bytes\n\t"
10916 $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
10917 $$emit$$"vmovdqu ymm0,(rax)\n\t"
10918 $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
10919 $$emit$$"add 0x40,rax\n\t"
10920 $$emit$$"# L_zero_64_bytes:\n\t"
10921 $$emit$$"sub 0x8,rcx\n\t"
10922 $$emit$$"jge L_loop\n\t"
10923 $$emit$$"add 0x4,rcx\n\t"
10924 $$emit$$"jl L_tail\n\t"
10925 $$emit$$"vmovdqu ymm0,(rax)\n\t"
10926 $$emit$$"add 0x20,rax\n\t"
10927 $$emit$$"sub 0x4,rcx\n\t"
10928 $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
10929 $$emit$$"add 0x4,rcx\n\t"
10930 $$emit$$"jle L_end\n\t"
10931 $$emit$$"dec rcx\n\t"
10932 $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
10933 $$emit$$"vmovq xmm0,(rax)\n\t"
10934 $$emit$$"add 0x8,rax\n\t"
10935 $$emit$$"dec rcx\n\t"
10936 $$emit$$"jge L_sloop\n\t"
10937 $$emit$$"# L_end:\n\t"
10938 } else {
10939 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--\n\t"
10940 }
10941 $$emit$$"# DONE"
10942 %}
10943 ins_encode %{
10944 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register,
10945 $tmp$$XMMRegister, false);
10946 %}
10947 ins_pipe(pipe_slow);
10948 %}
10949
10950 instruct rep_stos_large(rcx_RegL cnt, rdi_RegP base, regD tmp, rax_RegI zero,
10951 Universe dummy, rFlagsReg cr)
10952 %{
10953 predicate(((ClearArrayNode*)n)->is_large());
10954 match(Set dummy (ClearArray cnt base));
10955 effect(USE_KILL cnt, USE_KILL base, TEMP tmp, KILL zero, KILL cr);
10956
10957 format %{ $$template
10958 if (UseFastStosb) {
10959 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
10960 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t"
10961 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--"
10962 } else if (UseXMMForObjInit) {
10963 $$emit$$"mov rdi,rax\t# ClearArray:\n\t"
10964 $$emit$$"vpxor ymm0,ymm0,ymm0\n\t"
10965 $$emit$$"jmpq L_zero_64_bytes\n\t"
10966 $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
10967 $$emit$$"vmovdqu ymm0,(rax)\n\t"
10968 $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
10969 $$emit$$"add 0x40,rax\n\t"
10970 $$emit$$"# L_zero_64_bytes:\n\t"
10971 $$emit$$"sub 0x8,rcx\n\t"
10972 $$emit$$"jge L_loop\n\t"
10973 $$emit$$"add 0x4,rcx\n\t"
10974 $$emit$$"jl L_tail\n\t"
10975 $$emit$$"vmovdqu ymm0,(rax)\n\t"
10976 $$emit$$"add 0x20,rax\n\t"
10977 $$emit$$"sub 0x4,rcx\n\t"
10978 $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
10979 $$emit$$"add 0x4,rcx\n\t"
10980 $$emit$$"jle L_end\n\t"
10981 $$emit$$"dec rcx\n\t"
10982 $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
10983 $$emit$$"vmovq xmm0,(rax)\n\t"
10984 $$emit$$"add 0x8,rax\n\t"
10985 $$emit$$"dec rcx\n\t"
10986 $$emit$$"jge L_sloop\n\t"
10987 $$emit$$"# L_end:\n\t"
10988 } else {
10989 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
10990 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--"
10991 }
10992 %}
10993 ins_encode %{
10994 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register,
10995 $tmp$$XMMRegister, true);
10996 %}
10997 ins_pipe(pipe_slow);
10998 %}
10999
11000 instruct string_compareL(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11001 rax_RegI result, legVecS tmp1, rFlagsReg cr)
11002 %{
11003 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
11004 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11005 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11006
11007 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11008 ins_encode %{
11009 __ string_compare($str1$$Register, $str2$$Register,
11010 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11011 $tmp1$$XMMRegister, StrIntrinsicNode::LL);
11012 %}
11013 ins_pipe( pipe_slow );
11014 %}
11015
11016 instruct string_compareU(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11017 rax_RegI result, legVecS tmp1, rFlagsReg cr)
11018 %{
11019 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU);
11020 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11021 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11022
11023 format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11024 ins_encode %{
11025 __ string_compare($str1$$Register, $str2$$Register,
11026 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11027 $tmp1$$XMMRegister, StrIntrinsicNode::UU);
11028 %}
11029 ins_pipe( pipe_slow );
11030 %}
11031
11032 instruct string_compareLU(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11033 rax_RegI result, legVecS tmp1, rFlagsReg cr)
11034 %{
11035 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
11036 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11037 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11038
11039 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11040 ins_encode %{
11041 __ string_compare($str1$$Register, $str2$$Register,
11042 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11043 $tmp1$$XMMRegister, StrIntrinsicNode::LU);
11044 %}
11045 ins_pipe( pipe_slow );
11046 %}
11047
11048 instruct string_compareUL(rsi_RegP str1, rdx_RegI cnt1, rdi_RegP str2, rcx_RegI cnt2,
11049 rax_RegI result, legVecS tmp1, rFlagsReg cr)
11050 %{
11051 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
11052 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11053 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11054
11055 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11056 ins_encode %{
11057 __ string_compare($str2$$Register, $str1$$Register,
11058 $cnt2$$Register, $cnt1$$Register, $result$$Register,
11059 $tmp1$$XMMRegister, StrIntrinsicNode::UL);
11060 %}
11061 ins_pipe( pipe_slow );
11062 %}
11063
11064 // fast search of substring with known size.
11065 instruct string_indexof_conL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
11066 rbx_RegI result, legVecS vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
11067 %{
11068 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL));
11069 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11070 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11071
11072 format %{ "String IndexOf byte[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
11073 ins_encode %{
11074 int icnt2 = (int)$int_cnt2$$constant;
11075 if (icnt2 >= 16) {
11076 // IndexOf for constant substrings with size >= 16 elements
11077 // which don't need to be loaded through stack.
11078 __ string_indexofC8($str1$$Register, $str2$$Register,
11079 $cnt1$$Register, $cnt2$$Register,
11080 icnt2, $result$$Register,
11081 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
11082 } else {
11083 // Small strings are loaded through stack if they cross page boundary.
11084 __ string_indexof($str1$$Register, $str2$$Register,
11085 $cnt1$$Register, $cnt2$$Register,
11086 icnt2, $result$$Register,
11087 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
11088 }
11089 %}
11090 ins_pipe( pipe_slow );
11091 %}
11092
11093 // fast search of substring with known size.
11094 instruct string_indexof_conU(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
11095 rbx_RegI result, legVecS vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
11096 %{
11097 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU));
11098 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11099 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11100
11101 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
11102 ins_encode %{
11103 int icnt2 = (int)$int_cnt2$$constant;
11104 if (icnt2 >= 8) {
11105 // IndexOf for constant substrings with size >= 8 elements
11106 // which don't need to be loaded through stack.
11107 __ string_indexofC8($str1$$Register, $str2$$Register,
11108 $cnt1$$Register, $cnt2$$Register,
11109 icnt2, $result$$Register,
11110 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
11111 } else {
11112 // Small strings are loaded through stack if they cross page boundary.
11113 __ string_indexof($str1$$Register, $str2$$Register,
11114 $cnt1$$Register, $cnt2$$Register,
11115 icnt2, $result$$Register,
11116 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
11117 }
11118 %}
11119 ins_pipe( pipe_slow );
11120 %}
11121
11122 // fast search of substring with known size.
11123 instruct string_indexof_conUL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
11124 rbx_RegI result, legVecS vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
11125 %{
11126 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL));
11127 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11128 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11129
11130 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
11131 ins_encode %{
11132 int icnt2 = (int)$int_cnt2$$constant;
11133 if (icnt2 >= 8) {
11134 // IndexOf for constant substrings with size >= 8 elements
11135 // which don't need to be loaded through stack.
11136 __ string_indexofC8($str1$$Register, $str2$$Register,
11137 $cnt1$$Register, $cnt2$$Register,
11138 icnt2, $result$$Register,
11139 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
11140 } else {
11141 // Small strings are loaded through stack if they cross page boundary.
11142 __ string_indexof($str1$$Register, $str2$$Register,
11143 $cnt1$$Register, $cnt2$$Register,
11144 icnt2, $result$$Register,
11145 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
11146 }
11147 %}
11148 ins_pipe( pipe_slow );
11149 %}
11150
11151 instruct string_indexofL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
11152 rbx_RegI result, legVecS vec, rcx_RegI tmp, rFlagsReg cr)
11153 %{
11154 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL));
11155 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11156 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11157
11158 format %{ "String IndexOf byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
11159 ins_encode %{
11160 __ string_indexof($str1$$Register, $str2$$Register,
11161 $cnt1$$Register, $cnt2$$Register,
11162 (-1), $result$$Register,
11163 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
11164 %}
11165 ins_pipe( pipe_slow );
11166 %}
11167
11168 instruct string_indexofU(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
11169 rbx_RegI result, legVecS vec, rcx_RegI tmp, rFlagsReg cr)
11170 %{
11171 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU));
11172 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11173 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11174
11175 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
11176 ins_encode %{
11177 __ string_indexof($str1$$Register, $str2$$Register,
11178 $cnt1$$Register, $cnt2$$Register,
11179 (-1), $result$$Register,
11180 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
11181 %}
11182 ins_pipe( pipe_slow );
11183 %}
11184
11185 instruct string_indexofUL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
11186 rbx_RegI result, legVecS vec, rcx_RegI tmp, rFlagsReg cr)
11187 %{
11188 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL));
11189 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11190 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11191
11192 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
11193 ins_encode %{
11194 __ string_indexof($str1$$Register, $str2$$Register,
11195 $cnt1$$Register, $cnt2$$Register,
11196 (-1), $result$$Register,
11197 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
11198 %}
11199 ins_pipe( pipe_slow );
11200 %}
11201
11202 instruct string_indexofU_char(rdi_RegP str1, rdx_RegI cnt1, rax_RegI ch,
11203 rbx_RegI result, legVecS vec1, legVecS vec2, legVecS vec3, rcx_RegI tmp, rFlagsReg cr)
11204 %{
11205 predicate(UseSSE42Intrinsics);
11206 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
11207 effect(TEMP vec1, TEMP vec2, TEMP vec3, USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP tmp, KILL cr);
11208 format %{ "String IndexOf char[] $str1,$cnt1,$ch -> $result // KILL all" %}
11209 ins_encode %{
11210 __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register, $result$$Register,
11211 $vec1$$XMMRegister, $vec2$$XMMRegister, $vec3$$XMMRegister, $tmp$$Register);
11212 %}
11213 ins_pipe( pipe_slow );
11214 %}
11215
11216 // fast string equals
11217 instruct string_equals(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result,
11218 legVecS tmp1, legVecS tmp2, rbx_RegI tmp3, rFlagsReg cr)
11219 %{
11220 match(Set result (StrEquals (Binary str1 str2) cnt));
11221 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
11222
11223 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
11224 ins_encode %{
11225 __ arrays_equals(false, $str1$$Register, $str2$$Register,
11226 $cnt$$Register, $result$$Register, $tmp3$$Register,
11227 $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */);
11228 %}
11229 ins_pipe( pipe_slow );
11230 %}
11231
11232 // fast array equals
11233 instruct array_equalsB(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
11234 legVecS tmp1, legVecS tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
11235 %{
11236 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
11237 match(Set result (AryEq ary1 ary2));
11238 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11239
11240 format %{ "Array Equals byte[] $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11241 ins_encode %{
11242 __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
11243 $tmp3$$Register, $result$$Register, $tmp4$$Register,
11244 $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */);
11245 %}
11246 ins_pipe( pipe_slow );
11247 %}
11248
11249 instruct array_equalsC(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
11250 legVecS tmp1, legVecS tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
11251 %{
11252 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
11253 match(Set result (AryEq ary1 ary2));
11254 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11255
11256 format %{ "Array Equals char[] $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11257 ins_encode %{
11258 __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
11259 $tmp3$$Register, $result$$Register, $tmp4$$Register,
11260 $tmp1$$XMMRegister, $tmp2$$XMMRegister, true /* char */);
11261 %}
11262 ins_pipe( pipe_slow );
11263 %}
11264
11265 instruct has_negatives(rsi_RegP ary1, rcx_RegI len, rax_RegI result,
11266 legVecS tmp1, legVecS tmp2, rbx_RegI tmp3, rFlagsReg cr)
11267 %{
11268 match(Set result (HasNegatives ary1 len));
11269 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL len, KILL tmp3, KILL cr);
11270
11271 format %{ "has negatives byte[] $ary1,$len -> $result // KILL $tmp1, $tmp2, $tmp3" %}
11272 ins_encode %{
11273 __ has_negatives($ary1$$Register, $len$$Register,
11274 $result$$Register, $tmp3$$Register,
11275 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11276 %}
11277 ins_pipe( pipe_slow );
11278 %}
11279
11280 // fast char[] to byte[] compression
11281 instruct string_compress(rsi_RegP src, rdi_RegP dst, rdx_RegI len, legVecS tmp1, legVecS tmp2, legVecS tmp3, legVecS tmp4,
11282 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
11283 match(Set result (StrCompressedCopy src (Binary dst len)));
11284 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
11285
11286 format %{ "String Compress $src,$dst -> $result // KILL RAX, RCX, RDX" %}
11287 ins_encode %{
11288 __ char_array_compress($src$$Register, $dst$$Register, $len$$Register,
11289 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11290 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
11291 %}
11292 ins_pipe( pipe_slow );
11293 %}
11294
11295 // fast byte[] to char[] inflation
11296 instruct string_inflate(Universe dummy, rsi_RegP src, rdi_RegP dst, rdx_RegI len,
11297 legVecS tmp1, rcx_RegI tmp2, rFlagsReg cr) %{
11298 match(Set dummy (StrInflatedCopy src (Binary dst len)));
11299 effect(TEMP tmp1, TEMP tmp2, USE_KILL src, USE_KILL dst, USE_KILL len, KILL cr);
11300
11301 format %{ "String Inflate $src,$dst // KILL $tmp1, $tmp2" %}
11302 ins_encode %{
11303 __ byte_array_inflate($src$$Register, $dst$$Register, $len$$Register,
11304 $tmp1$$XMMRegister, $tmp2$$Register);
11305 %}
11306 ins_pipe( pipe_slow );
11307 %}
11308
11309 // encode char[] to byte[] in ISO_8859_1
11310 instruct encode_iso_array(rsi_RegP src, rdi_RegP dst, rdx_RegI len,
11311 legVecS tmp1, legVecS tmp2, legVecS tmp3, legVecS tmp4,
11312 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
11313 match(Set result (EncodeISOArray src (Binary dst len)));
11314 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
11315
11316 format %{ "Encode array $src,$dst,$len -> $result // KILL RCX, RDX, $tmp1, $tmp2, $tmp3, $tmp4, RSI, RDI " %}
11317 ins_encode %{
11318 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
11319 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11320 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
11321 %}
11322 ins_pipe( pipe_slow );
11323 %}
11324
11325 //----------Overflow Math Instructions-----------------------------------------
11326
11327 instruct overflowAddI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
11328 %{
11329 match(Set cr (OverflowAddI op1 op2));
11330 effect(DEF cr, USE_KILL op1, USE op2);
11331
11332 format %{ "addl $op1, $op2\t# overflow check int" %}
11333
11334 ins_encode %{
11335 __ addl($op1$$Register, $op2$$Register);
11336 %}
11337 ins_pipe(ialu_reg_reg);
11338 %}
11339
11340 instruct overflowAddI_rReg_imm(rFlagsReg cr, rax_RegI op1, immI op2)
11341 %{
11342 match(Set cr (OverflowAddI op1 op2));
11343 effect(DEF cr, USE_KILL op1, USE op2);
11344
11345 format %{ "addl $op1, $op2\t# overflow check int" %}
11346
11347 ins_encode %{
11348 __ addl($op1$$Register, $op2$$constant);
11349 %}
11350 ins_pipe(ialu_reg_reg);
11351 %}
11352
11353 instruct overflowAddL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
11354 %{
11355 match(Set cr (OverflowAddL op1 op2));
11356 effect(DEF cr, USE_KILL op1, USE op2);
11357
11358 format %{ "addq $op1, $op2\t# overflow check long" %}
11359 ins_encode %{
11360 __ addq($op1$$Register, $op2$$Register);
11361 %}
11362 ins_pipe(ialu_reg_reg);
11363 %}
11364
11365 instruct overflowAddL_rReg_imm(rFlagsReg cr, rax_RegL op1, immL32 op2)
11366 %{
11367 match(Set cr (OverflowAddL op1 op2));
11368 effect(DEF cr, USE_KILL op1, USE op2);
11369
11370 format %{ "addq $op1, $op2\t# overflow check long" %}
11371 ins_encode %{
11372 __ addq($op1$$Register, $op2$$constant);
11373 %}
11374 ins_pipe(ialu_reg_reg);
11375 %}
11376
11377 instruct overflowSubI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
11378 %{
11379 match(Set cr (OverflowSubI op1 op2));
11380
11381 format %{ "cmpl $op1, $op2\t# overflow check int" %}
11382 ins_encode %{
11383 __ cmpl($op1$$Register, $op2$$Register);
11384 %}
11385 ins_pipe(ialu_reg_reg);
11386 %}
11387
11388 instruct overflowSubI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
11389 %{
11390 match(Set cr (OverflowSubI op1 op2));
11391
11392 format %{ "cmpl $op1, $op2\t# overflow check int" %}
11393 ins_encode %{
11394 __ cmpl($op1$$Register, $op2$$constant);
11395 %}
11396 ins_pipe(ialu_reg_reg);
11397 %}
11398
11399 instruct overflowSubL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
11400 %{
11401 match(Set cr (OverflowSubL op1 op2));
11402
11403 format %{ "cmpq $op1, $op2\t# overflow check long" %}
11404 ins_encode %{
11405 __ cmpq($op1$$Register, $op2$$Register);
11406 %}
11407 ins_pipe(ialu_reg_reg);
11408 %}
11409
11410 instruct overflowSubL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
11411 %{
11412 match(Set cr (OverflowSubL op1 op2));
11413
11414 format %{ "cmpq $op1, $op2\t# overflow check long" %}
11415 ins_encode %{
11416 __ cmpq($op1$$Register, $op2$$constant);
11417 %}
11418 ins_pipe(ialu_reg_reg);
11419 %}
11420
11421 instruct overflowNegI_rReg(rFlagsReg cr, immI0 zero, rax_RegI op2)
11422 %{
11423 match(Set cr (OverflowSubI zero op2));
11424 effect(DEF cr, USE_KILL op2);
11425
11426 format %{ "negl $op2\t# overflow check int" %}
11427 ins_encode %{
11428 __ negl($op2$$Register);
11429 %}
11430 ins_pipe(ialu_reg_reg);
11431 %}
11432
11433 instruct overflowNegL_rReg(rFlagsReg cr, immL0 zero, rax_RegL op2)
11434 %{
11435 match(Set cr (OverflowSubL zero op2));
11436 effect(DEF cr, USE_KILL op2);
11437
11438 format %{ "negq $op2\t# overflow check long" %}
11439 ins_encode %{
11440 __ negq($op2$$Register);
11441 %}
11442 ins_pipe(ialu_reg_reg);
11443 %}
11444
11445 instruct overflowMulI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
11446 %{
11447 match(Set cr (OverflowMulI op1 op2));
11448 effect(DEF cr, USE_KILL op1, USE op2);
11449
11450 format %{ "imull $op1, $op2\t# overflow check int" %}
11451 ins_encode %{
11452 __ imull($op1$$Register, $op2$$Register);
11453 %}
11454 ins_pipe(ialu_reg_reg_alu0);
11455 %}
11456
11457 instruct overflowMulI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2, rRegI tmp)
11458 %{
11459 match(Set cr (OverflowMulI op1 op2));
11460 effect(DEF cr, TEMP tmp, USE op1, USE op2);
11461
11462 format %{ "imull $tmp, $op1, $op2\t# overflow check int" %}
11463 ins_encode %{
11464 __ imull($tmp$$Register, $op1$$Register, $op2$$constant);
11465 %}
11466 ins_pipe(ialu_reg_reg_alu0);
11467 %}
11468
11469 instruct overflowMulL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
11470 %{
11471 match(Set cr (OverflowMulL op1 op2));
11472 effect(DEF cr, USE_KILL op1, USE op2);
11473
11474 format %{ "imulq $op1, $op2\t# overflow check long" %}
11475 ins_encode %{
11476 __ imulq($op1$$Register, $op2$$Register);
11477 %}
11478 ins_pipe(ialu_reg_reg_alu0);
11479 %}
11480
11481 instruct overflowMulL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2, rRegL tmp)
11482 %{
11483 match(Set cr (OverflowMulL op1 op2));
11484 effect(DEF cr, TEMP tmp, USE op1, USE op2);
11485
11486 format %{ "imulq $tmp, $op1, $op2\t# overflow check long" %}
11487 ins_encode %{
11488 __ imulq($tmp$$Register, $op1$$Register, $op2$$constant);
11489 %}
11490 ins_pipe(ialu_reg_reg_alu0);
11491 %}
11492
11493
11494 //----------Control Flow Instructions------------------------------------------
11495 // Signed compare Instructions
11496
11497 // XXX more variants!!
11498 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
11499 %{
11500 match(Set cr (CmpI op1 op2));
11501 effect(DEF cr, USE op1, USE op2);
11502
11503 format %{ "cmpl $op1, $op2" %}
11504 opcode(0x3B); /* Opcode 3B /r */
11505 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
11506 ins_pipe(ialu_cr_reg_reg);
11507 %}
11508
11509 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
11510 %{
11511 match(Set cr (CmpI op1 op2));
11512
11513 format %{ "cmpl $op1, $op2" %}
11514 opcode(0x81, 0x07); /* Opcode 81 /7 */
11515 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
11516 ins_pipe(ialu_cr_reg_imm);
11517 %}
11518
11519 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2)
11520 %{
11521 match(Set cr (CmpI op1 (LoadI op2)));
11522
11523 ins_cost(500); // XXX
11524 format %{ "cmpl $op1, $op2" %}
11525 opcode(0x3B); /* Opcode 3B /r */
11526 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
11527 ins_pipe(ialu_cr_reg_mem);
11528 %}
11529
11530 instruct testI_reg(rFlagsReg cr, rRegI src, immI0 zero)
11531 %{
11532 match(Set cr (CmpI src zero));
11533
11534 format %{ "testl $src, $src" %}
11535 opcode(0x85);
11536 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
11537 ins_pipe(ialu_cr_reg_imm);
11538 %}
11539
11540 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI0 zero)
11541 %{
11542 match(Set cr (CmpI (AndI src con) zero));
11543
11544 format %{ "testl $src, $con" %}
11545 opcode(0xF7, 0x00);
11546 ins_encode(REX_reg(src), OpcP, reg_opc(src), Con32(con));
11547 ins_pipe(ialu_cr_reg_imm);
11548 %}
11549
11550 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI0 zero)
11551 %{
11552 match(Set cr (CmpI (AndI src (LoadI mem)) zero));
11553
11554 format %{ "testl $src, $mem" %}
11555 opcode(0x85);
11556 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
11557 ins_pipe(ialu_cr_reg_mem);
11558 %}
11559
11560 // Unsigned compare Instructions; really, same as signed except they
11561 // produce an rFlagsRegU instead of rFlagsReg.
11562 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2)
11563 %{
11564 match(Set cr (CmpU op1 op2));
11565
11566 format %{ "cmpl $op1, $op2\t# unsigned" %}
11567 opcode(0x3B); /* Opcode 3B /r */
11568 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
11569 ins_pipe(ialu_cr_reg_reg);
11570 %}
11571
11572 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2)
11573 %{
11574 match(Set cr (CmpU op1 op2));
11575
11576 format %{ "cmpl $op1, $op2\t# unsigned" %}
11577 opcode(0x81,0x07); /* Opcode 81 /7 */
11578 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
11579 ins_pipe(ialu_cr_reg_imm);
11580 %}
11581
11582 instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2)
11583 %{
11584 match(Set cr (CmpU op1 (LoadI op2)));
11585
11586 ins_cost(500); // XXX
11587 format %{ "cmpl $op1, $op2\t# unsigned" %}
11588 opcode(0x3B); /* Opcode 3B /r */
11589 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
11590 ins_pipe(ialu_cr_reg_mem);
11591 %}
11592
11593 // // // Cisc-spilled version of cmpU_rReg
11594 // //instruct compU_mem_rReg(rFlagsRegU cr, memory op1, rRegI op2)
11595 // //%{
11596 // // match(Set cr (CmpU (LoadI op1) op2));
11597 // //
11598 // // format %{ "CMPu $op1,$op2" %}
11599 // // ins_cost(500);
11600 // // opcode(0x39); /* Opcode 39 /r */
11601 // // ins_encode( OpcP, reg_mem( op1, op2) );
11602 // //%}
11603
11604 instruct testU_reg(rFlagsRegU cr, rRegI src, immI0 zero)
11605 %{
11606 match(Set cr (CmpU src zero));
11607
11608 format %{ "testl $src, $src\t# unsigned" %}
11609 opcode(0x85);
11610 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
11611 ins_pipe(ialu_cr_reg_imm);
11612 %}
11613
11614 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2)
11615 %{
11616 match(Set cr (CmpP op1 op2));
11617
11618 format %{ "cmpq $op1, $op2\t# ptr" %}
11619 opcode(0x3B); /* Opcode 3B /r */
11620 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
11621 ins_pipe(ialu_cr_reg_reg);
11622 %}
11623
11624 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2)
11625 %{
11626 match(Set cr (CmpP op1 (LoadP op2)));
11627
11628 ins_cost(500); // XXX
11629 format %{ "cmpq $op1, $op2\t# ptr" %}
11630 opcode(0x3B); /* Opcode 3B /r */
11631 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11632 ins_pipe(ialu_cr_reg_mem);
11633 %}
11634
11635 // // // Cisc-spilled version of cmpP_rReg
11636 // //instruct compP_mem_rReg(rFlagsRegU cr, memory op1, rRegP op2)
11637 // //%{
11638 // // match(Set cr (CmpP (LoadP op1) op2));
11639 // //
11640 // // format %{ "CMPu $op1,$op2" %}
11641 // // ins_cost(500);
11642 // // opcode(0x39); /* Opcode 39 /r */
11643 // // ins_encode( OpcP, reg_mem( op1, op2) );
11644 // //%}
11645
11646 // XXX this is generalized by compP_rReg_mem???
11647 // Compare raw pointer (used in out-of-heap check).
11648 // Only works because non-oop pointers must be raw pointers
11649 // and raw pointers have no anti-dependencies.
11650 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2)
11651 %{
11652 predicate(n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none);
11653 match(Set cr (CmpP op1 (LoadP op2)));
11654
11655 format %{ "cmpq $op1, $op2\t# raw ptr" %}
11656 opcode(0x3B); /* Opcode 3B /r */
11657 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11658 ins_pipe(ialu_cr_reg_mem);
11659 %}
11660
11661 // This will generate a signed flags result. This should be OK since
11662 // any compare to a zero should be eq/neq.
11663 instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero)
11664 %{
11665 match(Set cr (CmpP src zero));
11666
11667 format %{ "testq $src, $src\t# ptr" %}
11668 opcode(0x85);
11669 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
11670 ins_pipe(ialu_cr_reg_imm);
11671 %}
11672
11673 // This will generate a signed flags result. This should be OK since
11674 // any compare to a zero should be eq/neq.
11675 instruct testP_mem(rFlagsReg cr, memory op, immP0 zero)
11676 %{
11677 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
11678 match(Set cr (CmpP (LoadP op) zero));
11679
11680 ins_cost(500); // XXX
11681 format %{ "testq $op, 0xffffffffffffffff\t# ptr" %}
11682 opcode(0xF7); /* Opcode F7 /0 */
11683 ins_encode(REX_mem_wide(op),
11684 OpcP, RM_opc_mem(0x00, op), Con_d32(0xFFFFFFFF));
11685 ins_pipe(ialu_cr_reg_imm);
11686 %}
11687
11688 instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero)
11689 %{
11690 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
11691 match(Set cr (CmpP (LoadP mem) zero));
11692
11693 format %{ "cmpq R12, $mem\t# ptr (R12_heapbase==0)" %}
11694 ins_encode %{
11695 __ cmpq(r12, $mem$$Address);
11696 %}
11697 ins_pipe(ialu_cr_reg_mem);
11698 %}
11699
11700 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2)
11701 %{
11702 match(Set cr (CmpN op1 op2));
11703
11704 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
11705 ins_encode %{ __ cmpl($op1$$Register, $op2$$Register); %}
11706 ins_pipe(ialu_cr_reg_reg);
11707 %}
11708
11709 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem)
11710 %{
11711 match(Set cr (CmpN src (LoadN mem)));
11712
11713 format %{ "cmpl $src, $mem\t# compressed ptr" %}
11714 ins_encode %{
11715 __ cmpl($src$$Register, $mem$$Address);
11716 %}
11717 ins_pipe(ialu_cr_reg_mem);
11718 %}
11719
11720 instruct compN_rReg_imm(rFlagsRegU cr, rRegN op1, immN op2) %{
11721 match(Set cr (CmpN op1 op2));
11722
11723 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
11724 ins_encode %{
11725 __ cmp_narrow_oop($op1$$Register, (jobject)$op2$$constant);
11726 %}
11727 ins_pipe(ialu_cr_reg_imm);
11728 %}
11729
11730 instruct compN_mem_imm(rFlagsRegU cr, memory mem, immN src)
11731 %{
11732 match(Set cr (CmpN src (LoadN mem)));
11733
11734 format %{ "cmpl $mem, $src\t# compressed ptr" %}
11735 ins_encode %{
11736 __ cmp_narrow_oop($mem$$Address, (jobject)$src$$constant);
11737 %}
11738 ins_pipe(ialu_cr_reg_mem);
11739 %}
11740
11741 instruct compN_rReg_imm_klass(rFlagsRegU cr, rRegN op1, immNKlass op2) %{
11742 match(Set cr (CmpN op1 op2));
11743
11744 format %{ "cmpl $op1, $op2\t# compressed klass ptr" %}
11745 ins_encode %{
11746 __ cmp_narrow_klass($op1$$Register, (Klass*)$op2$$constant);
11747 %}
11748 ins_pipe(ialu_cr_reg_imm);
11749 %}
11750
11751 instruct compN_mem_imm_klass(rFlagsRegU cr, memory mem, immNKlass src)
11752 %{
11753 match(Set cr (CmpN src (LoadNKlass mem)));
11754
11755 format %{ "cmpl $mem, $src\t# compressed klass ptr" %}
11756 ins_encode %{
11757 __ cmp_narrow_klass($mem$$Address, (Klass*)$src$$constant);
11758 %}
11759 ins_pipe(ialu_cr_reg_mem);
11760 %}
11761
11762 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{
11763 match(Set cr (CmpN src zero));
11764
11765 format %{ "testl $src, $src\t# compressed ptr" %}
11766 ins_encode %{ __ testl($src$$Register, $src$$Register); %}
11767 ins_pipe(ialu_cr_reg_imm);
11768 %}
11769
11770 instruct testN_mem(rFlagsReg cr, memory mem, immN0 zero)
11771 %{
11772 predicate(Universe::narrow_oop_base() != NULL);
11773 match(Set cr (CmpN (LoadN mem) zero));
11774
11775 ins_cost(500); // XXX
11776 format %{ "testl $mem, 0xffffffff\t# compressed ptr" %}
11777 ins_encode %{
11778 __ cmpl($mem$$Address, (int)0xFFFFFFFF);
11779 %}
11780 ins_pipe(ialu_cr_reg_mem);
11781 %}
11782
11783 instruct testN_mem_reg0(rFlagsReg cr, memory mem, immN0 zero)
11784 %{
11785 predicate(Universe::narrow_oop_base() == NULL && (Universe::narrow_klass_base() == NULL));
11786 match(Set cr (CmpN (LoadN mem) zero));
11787
11788 format %{ "cmpl R12, $mem\t# compressed ptr (R12_heapbase==0)" %}
11789 ins_encode %{
11790 __ cmpl(r12, $mem$$Address);
11791 %}
11792 ins_pipe(ialu_cr_reg_mem);
11793 %}
11794
11795 // Yanked all unsigned pointer compare operations.
11796 // Pointer compares are done with CmpP which is already unsigned.
11797
11798 instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
11799 %{
11800 match(Set cr (CmpL op1 op2));
11801
11802 format %{ "cmpq $op1, $op2" %}
11803 opcode(0x3B); /* Opcode 3B /r */
11804 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
11805 ins_pipe(ialu_cr_reg_reg);
11806 %}
11807
11808 instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
11809 %{
11810 match(Set cr (CmpL op1 op2));
11811
11812 format %{ "cmpq $op1, $op2" %}
11813 opcode(0x81, 0x07); /* Opcode 81 /7 */
11814 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2));
11815 ins_pipe(ialu_cr_reg_imm);
11816 %}
11817
11818 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2)
11819 %{
11820 match(Set cr (CmpL op1 (LoadL op2)));
11821
11822 format %{ "cmpq $op1, $op2" %}
11823 opcode(0x3B); /* Opcode 3B /r */
11824 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11825 ins_pipe(ialu_cr_reg_mem);
11826 %}
11827
11828 instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero)
11829 %{
11830 match(Set cr (CmpL src zero));
11831
11832 format %{ "testq $src, $src" %}
11833 opcode(0x85);
11834 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
11835 ins_pipe(ialu_cr_reg_imm);
11836 %}
11837
11838 instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero)
11839 %{
11840 match(Set cr (CmpL (AndL src con) zero));
11841
11842 format %{ "testq $src, $con\t# long" %}
11843 opcode(0xF7, 0x00);
11844 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src), Con32(con));
11845 ins_pipe(ialu_cr_reg_imm);
11846 %}
11847
11848 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero)
11849 %{
11850 match(Set cr (CmpL (AndL src (LoadL mem)) zero));
11851
11852 format %{ "testq $src, $mem" %}
11853 opcode(0x85);
11854 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
11855 ins_pipe(ialu_cr_reg_mem);
11856 %}
11857
11858 instruct testL_reg_mem2(rFlagsReg cr, rRegP src, memory mem, immL0 zero)
11859 %{
11860 match(Set cr (CmpL (AndL (CastP2X src) (LoadL mem)) zero));
11861
11862 format %{ "testq $src, $mem" %}
11863 opcode(0x85);
11864 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
11865 ins_pipe(ialu_cr_reg_mem);
11866 %}
11867
11868 // Manifest a CmpL result in an integer register. Very painful.
11869 // This is the test to avoid.
11870 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags)
11871 %{
11872 match(Set dst (CmpL3 src1 src2));
11873 effect(KILL flags);
11874
11875 ins_cost(275); // XXX
11876 format %{ "cmpq $src1, $src2\t# CmpL3\n\t"
11877 "movl $dst, -1\n\t"
11878 "jl,s done\n\t"
11879 "setne $dst\n\t"
11880 "movzbl $dst, $dst\n\t"
11881 "done:" %}
11882 ins_encode(cmpl3_flag(src1, src2, dst));
11883 ins_pipe(pipe_slow);
11884 %}
11885
11886 // Unsigned long compare Instructions; really, same as signed long except they
11887 // produce an rFlagsRegU instead of rFlagsReg.
11888 instruct compUL_rReg(rFlagsRegU cr, rRegL op1, rRegL op2)
11889 %{
11890 match(Set cr (CmpUL op1 op2));
11891
11892 format %{ "cmpq $op1, $op2\t# unsigned" %}
11893 opcode(0x3B); /* Opcode 3B /r */
11894 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
11895 ins_pipe(ialu_cr_reg_reg);
11896 %}
11897
11898 instruct compUL_rReg_imm(rFlagsRegU cr, rRegL op1, immL32 op2)
11899 %{
11900 match(Set cr (CmpUL op1 op2));
11901
11902 format %{ "cmpq $op1, $op2\t# unsigned" %}
11903 opcode(0x81, 0x07); /* Opcode 81 /7 */
11904 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2));
11905 ins_pipe(ialu_cr_reg_imm);
11906 %}
11907
11908 instruct compUL_rReg_mem(rFlagsRegU cr, rRegL op1, memory op2)
11909 %{
11910 match(Set cr (CmpUL op1 (LoadL op2)));
11911
11912 format %{ "cmpq $op1, $op2\t# unsigned" %}
11913 opcode(0x3B); /* Opcode 3B /r */
11914 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11915 ins_pipe(ialu_cr_reg_mem);
11916 %}
11917
11918 instruct testUL_reg(rFlagsRegU cr, rRegL src, immL0 zero)
11919 %{
11920 match(Set cr (CmpUL src zero));
11921
11922 format %{ "testq $src, $src\t# unsigned" %}
11923 opcode(0x85);
11924 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
11925 ins_pipe(ialu_cr_reg_imm);
11926 %}
11927
11928 instruct compB_mem_imm(rFlagsReg cr, memory mem, immI8 imm)
11929 %{
11930 match(Set cr (CmpI (LoadB mem) imm));
11931
11932 ins_cost(125);
11933 format %{ "cmpb $mem, $imm" %}
11934 ins_encode %{ __ cmpb($mem$$Address, $imm$$constant); %}
11935 ins_pipe(ialu_cr_reg_mem);
11936 %}
11937
11938 instruct testUB_mem_imm(rFlagsReg cr, memory mem, immU8 imm, immI0 zero)
11939 %{
11940 match(Set cr (CmpI (AndI (LoadUB mem) imm) zero));
11941
11942 ins_cost(125);
11943 format %{ "testb $mem, $imm" %}
11944 ins_encode %{ __ testb($mem$$Address, $imm$$constant); %}
11945 ins_pipe(ialu_cr_reg_mem);
11946 %}
11947
11948 //----------Max and Min--------------------------------------------------------
11949 // Min Instructions
11950
11951 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr)
11952 %{
11953 effect(USE_DEF dst, USE src, USE cr);
11954
11955 format %{ "cmovlgt $dst, $src\t# min" %}
11956 opcode(0x0F, 0x4F);
11957 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
11958 ins_pipe(pipe_cmov_reg);
11959 %}
11960
11961
11962 instruct minI_rReg(rRegI dst, rRegI src)
11963 %{
11964 match(Set dst (MinI dst src));
11965
11966 ins_cost(200);
11967 expand %{
11968 rFlagsReg cr;
11969 compI_rReg(cr, dst, src);
11970 cmovI_reg_g(dst, src, cr);
11971 %}
11972 %}
11973
11974 instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr)
11975 %{
11976 effect(USE_DEF dst, USE src, USE cr);
11977
11978 format %{ "cmovllt $dst, $src\t# max" %}
11979 opcode(0x0F, 0x4C);
11980 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
11981 ins_pipe(pipe_cmov_reg);
11982 %}
11983
11984
11985 instruct maxI_rReg(rRegI dst, rRegI src)
11986 %{
11987 match(Set dst (MaxI dst src));
11988
11989 ins_cost(200);
11990 expand %{
11991 rFlagsReg cr;
11992 compI_rReg(cr, dst, src);
11993 cmovI_reg_l(dst, src, cr);
11994 %}
11995 %}
11996
11997 // ============================================================================
11998 // Branch Instructions
11999
12000 // Jump Direct - Label defines a relative address from JMP+1
12001 instruct jmpDir(label labl)
12002 %{
12003 match(Goto);
12004 effect(USE labl);
12005
12006 ins_cost(300);
12007 format %{ "jmp $labl" %}
12008 size(5);
12009 ins_encode %{
12010 Label* L = $labl$$label;
12011 __ jmp(*L, false); // Always long jump
12012 %}
12013 ins_pipe(pipe_jmp);
12014 %}
12015
12016 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12017 instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl)
12018 %{
12019 match(If cop cr);
12020 effect(USE labl);
12021
12022 ins_cost(300);
12023 format %{ "j$cop $labl" %}
12024 size(6);
12025 ins_encode %{
12026 Label* L = $labl$$label;
12027 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12028 %}
12029 ins_pipe(pipe_jcc);
12030 %}
12031
12032 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12033 instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl)
12034 %{
12035 predicate(!n->has_vector_mask_set());
12036 match(CountedLoopEnd cop cr);
12037 effect(USE labl);
12038
12039 ins_cost(300);
12040 format %{ "j$cop $labl\t# loop end" %}
12041 size(6);
12042 ins_encode %{
12043 Label* L = $labl$$label;
12044 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12045 %}
12046 ins_pipe(pipe_jcc);
12047 %}
12048
12049 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12050 instruct jmpLoopEndU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12051 predicate(!n->has_vector_mask_set());
12052 match(CountedLoopEnd cop cmp);
12053 effect(USE labl);
12054
12055 ins_cost(300);
12056 format %{ "j$cop,u $labl\t# loop end" %}
12057 size(6);
12058 ins_encode %{
12059 Label* L = $labl$$label;
12060 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12061 %}
12062 ins_pipe(pipe_jcc);
12063 %}
12064
12065 instruct jmpLoopEndUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12066 predicate(!n->has_vector_mask_set());
12067 match(CountedLoopEnd cop cmp);
12068 effect(USE labl);
12069
12070 ins_cost(200);
12071 format %{ "j$cop,u $labl\t# loop end" %}
12072 size(6);
12073 ins_encode %{
12074 Label* L = $labl$$label;
12075 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12076 %}
12077 ins_pipe(pipe_jcc);
12078 %}
12079
12080 // mask version
12081 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12082 instruct jmpLoopEnd_and_restoreMask(cmpOp cop, rFlagsReg cr, label labl)
12083 %{
12084 predicate(n->has_vector_mask_set());
12085 match(CountedLoopEnd cop cr);
12086 effect(USE labl);
12087
12088 ins_cost(400);
12089 format %{ "j$cop $labl\t# loop end\n\t"
12090 "restorevectmask \t# vector mask restore for loops" %}
12091 size(10);
12092 ins_encode %{
12093 Label* L = $labl$$label;
12094 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12095 __ restorevectmask();
12096 %}
12097 ins_pipe(pipe_jcc);
12098 %}
12099
12100 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12101 instruct jmpLoopEndU_and_restoreMask(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12102 predicate(n->has_vector_mask_set());
12103 match(CountedLoopEnd cop cmp);
12104 effect(USE labl);
12105
12106 ins_cost(400);
12107 format %{ "j$cop,u $labl\t# loop end\n\t"
12108 "restorevectmask \t# vector mask restore for loops" %}
12109 size(10);
12110 ins_encode %{
12111 Label* L = $labl$$label;
12112 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12113 __ restorevectmask();
12114 %}
12115 ins_pipe(pipe_jcc);
12116 %}
12117
12118 instruct jmpLoopEndUCF_and_restoreMask(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12119 predicate(n->has_vector_mask_set());
12120 match(CountedLoopEnd cop cmp);
12121 effect(USE labl);
12122
12123 ins_cost(300);
12124 format %{ "j$cop,u $labl\t# loop end\n\t"
12125 "restorevectmask \t# vector mask restore for loops" %}
12126 size(10);
12127 ins_encode %{
12128 Label* L = $labl$$label;
12129 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12130 __ restorevectmask();
12131 %}
12132 ins_pipe(pipe_jcc);
12133 %}
12134
12135 // Jump Direct Conditional - using unsigned comparison
12136 instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12137 match(If cop cmp);
12138 effect(USE labl);
12139
12140 ins_cost(300);
12141 format %{ "j$cop,u $labl" %}
12142 size(6);
12143 ins_encode %{
12144 Label* L = $labl$$label;
12145 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12146 %}
12147 ins_pipe(pipe_jcc);
12148 %}
12149
12150 instruct jmpConUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12151 match(If cop cmp);
12152 effect(USE labl);
12153
12154 ins_cost(200);
12155 format %{ "j$cop,u $labl" %}
12156 size(6);
12157 ins_encode %{
12158 Label* L = $labl$$label;
12159 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12160 %}
12161 ins_pipe(pipe_jcc);
12162 %}
12163
12164 instruct jmpConUCF2(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
12165 match(If cop cmp);
12166 effect(USE labl);
12167
12168 ins_cost(200);
12169 format %{ $$template
12170 if ($cop$$cmpcode == Assembler::notEqual) {
12171 $$emit$$"jp,u $labl\n\t"
12172 $$emit$$"j$cop,u $labl"
12173 } else {
12174 $$emit$$"jp,u done\n\t"
12175 $$emit$$"j$cop,u $labl\n\t"
12176 $$emit$$"done:"
12177 }
12178 %}
12179 ins_encode %{
12180 Label* l = $labl$$label;
12181 if ($cop$$cmpcode == Assembler::notEqual) {
12182 __ jcc(Assembler::parity, *l, false);
12183 __ jcc(Assembler::notEqual, *l, false);
12184 } else if ($cop$$cmpcode == Assembler::equal) {
12185 Label done;
12186 __ jccb(Assembler::parity, done);
12187 __ jcc(Assembler::equal, *l, false);
12188 __ bind(done);
12189 } else {
12190 ShouldNotReachHere();
12191 }
12192 %}
12193 ins_pipe(pipe_jcc);
12194 %}
12195
12196 // ============================================================================
12197 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary
12198 // superklass array for an instance of the superklass. Set a hidden
12199 // internal cache on a hit (cache is checked with exposed code in
12200 // gen_subtype_check()). Return NZ for a miss or zero for a hit. The
12201 // encoding ALSO sets flags.
12202
12203 instruct partialSubtypeCheck(rdi_RegP result,
12204 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
12205 rFlagsReg cr)
12206 %{
12207 match(Set result (PartialSubtypeCheck sub super));
12208 effect(KILL rcx, KILL cr);
12209
12210 ins_cost(1100); // slightly larger than the next version
12211 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
12212 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
12213 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
12214 "repne scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t"
12215 "jne,s miss\t\t# Missed: rdi not-zero\n\t"
12216 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
12217 "xorq $result, $result\t\t Hit: rdi zero\n\t"
12218 "miss:\t" %}
12219
12220 opcode(0x1); // Force a XOR of RDI
12221 ins_encode(enc_PartialSubtypeCheck());
12222 ins_pipe(pipe_slow);
12223 %}
12224
12225 instruct partialSubtypeCheck_vs_Zero(rFlagsReg cr,
12226 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
12227 immP0 zero,
12228 rdi_RegP result)
12229 %{
12230 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
12231 effect(KILL rcx, KILL result);
12232
12233 ins_cost(1000);
12234 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
12235 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
12236 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
12237 "repne scasq\t# Scan *rdi++ for a match with rax while cx-- != 0\n\t"
12238 "jne,s miss\t\t# Missed: flags nz\n\t"
12239 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
12240 "miss:\t" %}
12241
12242 opcode(0x0); // No need to XOR RDI
12243 ins_encode(enc_PartialSubtypeCheck());
12244 ins_pipe(pipe_slow);
12245 %}
12246
12247 // ============================================================================
12248 // Branch Instructions -- short offset versions
12249 //
12250 // These instructions are used to replace jumps of a long offset (the default
12251 // match) with jumps of a shorter offset. These instructions are all tagged
12252 // with the ins_short_branch attribute, which causes the ADLC to suppress the
12253 // match rules in general matching. Instead, the ADLC generates a conversion
12254 // method in the MachNode which can be used to do in-place replacement of the
12255 // long variant with the shorter variant. The compiler will determine if a
12256 // branch can be taken by the is_short_branch_offset() predicate in the machine
12257 // specific code section of the file.
12258
12259 // Jump Direct - Label defines a relative address from JMP+1
12260 instruct jmpDir_short(label labl) %{
12261 match(Goto);
12262 effect(USE labl);
12263
12264 ins_cost(300);
12265 format %{ "jmp,s $labl" %}
12266 size(2);
12267 ins_encode %{
12268 Label* L = $labl$$label;
12269 __ jmpb(*L);
12270 %}
12271 ins_pipe(pipe_jmp);
12272 ins_short_branch(1);
12273 %}
12274
12275 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12276 instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl) %{
12277 match(If cop cr);
12278 effect(USE labl);
12279
12280 ins_cost(300);
12281 format %{ "j$cop,s $labl" %}
12282 size(2);
12283 ins_encode %{
12284 Label* L = $labl$$label;
12285 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12286 %}
12287 ins_pipe(pipe_jcc);
12288 ins_short_branch(1);
12289 %}
12290
12291 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12292 instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl) %{
12293 match(CountedLoopEnd cop cr);
12294 effect(USE labl);
12295
12296 ins_cost(300);
12297 format %{ "j$cop,s $labl\t# loop end" %}
12298 size(2);
12299 ins_encode %{
12300 Label* L = $labl$$label;
12301 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12302 %}
12303 ins_pipe(pipe_jcc);
12304 ins_short_branch(1);
12305 %}
12306
12307 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12308 instruct jmpLoopEndU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12309 match(CountedLoopEnd cop cmp);
12310 effect(USE labl);
12311
12312 ins_cost(300);
12313 format %{ "j$cop,us $labl\t# loop end" %}
12314 size(2);
12315 ins_encode %{
12316 Label* L = $labl$$label;
12317 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12318 %}
12319 ins_pipe(pipe_jcc);
12320 ins_short_branch(1);
12321 %}
12322
12323 instruct jmpLoopEndUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12324 match(CountedLoopEnd cop cmp);
12325 effect(USE labl);
12326
12327 ins_cost(300);
12328 format %{ "j$cop,us $labl\t# loop end" %}
12329 size(2);
12330 ins_encode %{
12331 Label* L = $labl$$label;
12332 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12333 %}
12334 ins_pipe(pipe_jcc);
12335 ins_short_branch(1);
12336 %}
12337
12338 // Jump Direct Conditional - using unsigned comparison
12339 instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12340 match(If cop cmp);
12341 effect(USE labl);
12342
12343 ins_cost(300);
12344 format %{ "j$cop,us $labl" %}
12345 size(2);
12346 ins_encode %{
12347 Label* L = $labl$$label;
12348 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12349 %}
12350 ins_pipe(pipe_jcc);
12351 ins_short_branch(1);
12352 %}
12353
12354 instruct jmpConUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12355 match(If cop cmp);
12356 effect(USE labl);
12357
12358 ins_cost(300);
12359 format %{ "j$cop,us $labl" %}
12360 size(2);
12361 ins_encode %{
12362 Label* L = $labl$$label;
12363 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12364 %}
12365 ins_pipe(pipe_jcc);
12366 ins_short_branch(1);
12367 %}
12368
12369 instruct jmpConUCF2_short(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
12370 match(If cop cmp);
12371 effect(USE labl);
12372
12373 ins_cost(300);
12374 format %{ $$template
12375 if ($cop$$cmpcode == Assembler::notEqual) {
12376 $$emit$$"jp,u,s $labl\n\t"
12377 $$emit$$"j$cop,u,s $labl"
12378 } else {
12379 $$emit$$"jp,u,s done\n\t"
12380 $$emit$$"j$cop,u,s $labl\n\t"
12381 $$emit$$"done:"
12382 }
12383 %}
12384 size(4);
12385 ins_encode %{
12386 Label* l = $labl$$label;
12387 if ($cop$$cmpcode == Assembler::notEqual) {
12388 __ jccb(Assembler::parity, *l);
12389 __ jccb(Assembler::notEqual, *l);
12390 } else if ($cop$$cmpcode == Assembler::equal) {
12391 Label done;
12392 __ jccb(Assembler::parity, done);
12393 __ jccb(Assembler::equal, *l);
12394 __ bind(done);
12395 } else {
12396 ShouldNotReachHere();
12397 }
12398 %}
12399 ins_pipe(pipe_jcc);
12400 ins_short_branch(1);
12401 %}
12402
12403 // ============================================================================
12404 // inlined locking and unlocking
12405
12406 instruct cmpFastLockRTM(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rdx_RegI scr, rRegI cx1, rRegI cx2) %{
12407 predicate(Compile::current()->use_rtm());
12408 match(Set cr (FastLock object box));
12409 effect(TEMP tmp, TEMP scr, TEMP cx1, TEMP cx2, USE_KILL box);
12410 ins_cost(300);
12411 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr,$cx1,$cx2" %}
12412 ins_encode %{
12413 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
12414 $scr$$Register, $cx1$$Register, $cx2$$Register,
12415 _counters, _rtm_counters, _stack_rtm_counters,
12416 ((Method*)(ra_->C->method()->constant_encoding()))->method_data(),
12417 true, ra_->C->profile_rtm());
12418 %}
12419 ins_pipe(pipe_slow);
12420 %}
12421
12422 instruct cmpFastLock(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rRegP scr) %{
12423 predicate(!Compile::current()->use_rtm());
12424 match(Set cr (FastLock object box));
12425 effect(TEMP tmp, TEMP scr, USE_KILL box);
12426 ins_cost(300);
12427 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr" %}
12428 ins_encode %{
12429 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
12430 $scr$$Register, noreg, noreg, _counters, NULL, NULL, NULL, false, false);
12431 %}
12432 ins_pipe(pipe_slow);
12433 %}
12434
12435 instruct cmpFastUnlock(rFlagsReg cr, rRegP object, rax_RegP box, rRegP tmp) %{
12436 match(Set cr (FastUnlock object box));
12437 effect(TEMP tmp, USE_KILL box);
12438 ins_cost(300);
12439 format %{ "fastunlock $object,$box\t! kills $box,$tmp" %}
12440 ins_encode %{
12441 __ fast_unlock($object$$Register, $box$$Register, $tmp$$Register, ra_->C->use_rtm());
12442 %}
12443 ins_pipe(pipe_slow);
12444 %}
12445
12446
12447 // ============================================================================
12448 // Safepoint Instructions
12449 instruct safePoint_poll(rFlagsReg cr)
12450 %{
12451 predicate(!Assembler::is_polling_page_far() && SafepointMechanism::uses_global_page_poll());
12452 match(SafePoint);
12453 effect(KILL cr);
12454
12455 format %{ "testl rax, [rip + #offset_to_poll_page]\t"
12456 "# Safepoint: poll for GC" %}
12457 ins_cost(125);
12458 ins_encode %{
12459 AddressLiteral addr(os::get_polling_page(), relocInfo::poll_type);
12460 __ testl(rax, addr);
12461 %}
12462 ins_pipe(ialu_reg_mem);
12463 %}
12464
12465 instruct safePoint_poll_far(rFlagsReg cr, rRegP poll)
12466 %{
12467 predicate(Assembler::is_polling_page_far() && SafepointMechanism::uses_global_page_poll());
12468 match(SafePoint poll);
12469 effect(KILL cr, USE poll);
12470
12471 format %{ "testl rax, [$poll]\t"
12472 "# Safepoint: poll for GC" %}
12473 ins_cost(125);
12474 ins_encode %{
12475 __ relocate(relocInfo::poll_type);
12476 __ testl(rax, Address($poll$$Register, 0));
12477 %}
12478 ins_pipe(ialu_reg_mem);
12479 %}
12480
12481 instruct safePoint_poll_tls(rFlagsReg cr, rRegP poll)
12482 %{
12483 predicate(SafepointMechanism::uses_thread_local_poll());
12484 match(SafePoint poll);
12485 effect(KILL cr, USE poll);
12486
12487 format %{ "testl rax, [$poll]\t"
12488 "# Safepoint: poll for GC" %}
12489 ins_cost(125);
12490 size(4); /* setting an explicit size will cause debug builds to assert if size is incorrect */
12491 ins_encode %{
12492 __ relocate(relocInfo::poll_type);
12493 address pre_pc = __ pc();
12494 __ testl(rax, Address($poll$$Register, 0));
12495 assert(nativeInstruction_at(pre_pc)->is_safepoint_poll(), "must emit test %%eax [reg]");
12496 %}
12497 ins_pipe(ialu_reg_mem);
12498 %}
12499
12500 // ============================================================================
12501 // Procedure Call/Return Instructions
12502 // Call Java Static Instruction
12503 // Note: If this code changes, the corresponding ret_addr_offset() and
12504 // compute_padding() functions will have to be adjusted.
12505 instruct CallStaticJavaDirect(method meth) %{
12506 match(CallStaticJava);
12507 effect(USE meth);
12508
12509 ins_cost(300);
12510 format %{ "call,static " %}
12511 opcode(0xE8); /* E8 cd */
12512 ins_encode(clear_avx, Java_Static_Call(meth), call_epilog);
12513 ins_pipe(pipe_slow);
12514 ins_alignment(4);
12515 %}
12516
12517 // Call Java Dynamic Instruction
12518 // Note: If this code changes, the corresponding ret_addr_offset() and
12519 // compute_padding() functions will have to be adjusted.
12520 instruct CallDynamicJavaDirect(method meth)
12521 %{
12522 match(CallDynamicJava);
12523 effect(USE meth);
12524
12525 ins_cost(300);
12526 format %{ "movq rax, #Universe::non_oop_word()\n\t"
12527 "call,dynamic " %}
12528 ins_encode(clear_avx, Java_Dynamic_Call(meth), call_epilog);
12529 ins_pipe(pipe_slow);
12530 ins_alignment(4);
12531 %}
12532
12533 // Call Runtime Instruction
12534 instruct CallRuntimeDirect(method meth)
12535 %{
12536 match(CallRuntime);
12537 effect(USE meth);
12538
12539 ins_cost(300);
12540 format %{ "call,runtime " %}
12541 ins_encode(clear_avx, Java_To_Runtime(meth));
12542 ins_pipe(pipe_slow);
12543 %}
12544
12545 // Call runtime without safepoint
12546 instruct CallLeafDirect(method meth)
12547 %{
12548 match(CallLeaf);
12549 effect(USE meth);
12550
12551 ins_cost(300);
12552 format %{ "call_leaf,runtime " %}
12553 ins_encode(clear_avx, Java_To_Runtime(meth));
12554 ins_pipe(pipe_slow);
12555 %}
12556
12557 // Call runtime without safepoint
12558 instruct CallLeafNoFPDirect(method meth)
12559 %{
12560 match(CallLeafNoFP);
12561 effect(USE meth);
12562
12563 ins_cost(300);
12564 format %{ "call_leaf_nofp,runtime " %}
12565 ins_encode(clear_avx, Java_To_Runtime(meth));
12566 ins_pipe(pipe_slow);
12567 %}
12568
12569 // Return Instruction
12570 // Remove the return address & jump to it.
12571 // Notice: We always emit a nop after a ret to make sure there is room
12572 // for safepoint patching
12573 instruct Ret()
12574 %{
12575 match(Return);
12576
12577 format %{ "ret" %}
12578 opcode(0xC3);
12579 ins_encode(OpcP);
12580 ins_pipe(pipe_jmp);
12581 %}
12582
12583 // Tail Call; Jump from runtime stub to Java code.
12584 // Also known as an 'interprocedural jump'.
12585 // Target of jump will eventually return to caller.
12586 // TailJump below removes the return address.
12587 instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_oop)
12588 %{
12589 match(TailCall jump_target method_oop);
12590
12591 ins_cost(300);
12592 format %{ "jmp $jump_target\t# rbx holds method oop" %}
12593 opcode(0xFF, 0x4); /* Opcode FF /4 */
12594 ins_encode(REX_reg(jump_target), OpcP, reg_opc(jump_target));
12595 ins_pipe(pipe_jmp);
12596 %}
12597
12598 // Tail Jump; remove the return address; jump to target.
12599 // TailCall above leaves the return address around.
12600 instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop)
12601 %{
12602 match(TailJump jump_target ex_oop);
12603
12604 ins_cost(300);
12605 format %{ "popq rdx\t# pop return address\n\t"
12606 "jmp $jump_target" %}
12607 opcode(0xFF, 0x4); /* Opcode FF /4 */
12608 ins_encode(Opcode(0x5a), // popq rdx
12609 REX_reg(jump_target), OpcP, reg_opc(jump_target));
12610 ins_pipe(pipe_jmp);
12611 %}
12612
12613 // Create exception oop: created by stack-crawling runtime code.
12614 // Created exception is now available to this handler, and is setup
12615 // just prior to jumping to this handler. No code emitted.
12616 instruct CreateException(rax_RegP ex_oop)
12617 %{
12618 match(Set ex_oop (CreateEx));
12619
12620 size(0);
12621 // use the following format syntax
12622 format %{ "# exception oop is in rax; no code emitted" %}
12623 ins_encode();
12624 ins_pipe(empty);
12625 %}
12626
12627 // Rethrow exception:
12628 // The exception oop will come in the first argument position.
12629 // Then JUMP (not call) to the rethrow stub code.
12630 instruct RethrowException()
12631 %{
12632 match(Rethrow);
12633
12634 // use the following format syntax
12635 format %{ "jmp rethrow_stub" %}
12636 ins_encode(enc_rethrow);
12637 ins_pipe(pipe_jmp);
12638 %}
12639
12640 //
12641 // Execute ZGC load barrier (strong) slow path
12642 //
12643
12644 // When running without XMM regs
12645 instruct loadBarrierSlowRegNoVec(rRegP dst, memory mem, rFlagsReg cr) %{
12646
12647 match(Set dst (LoadBarrierSlowReg mem));
12648 predicate(MaxVectorSize < 16);
12649
12650 effect(DEF dst, KILL cr);
12651
12652 format %{"LoadBarrierSlowRegNoVec $dst, $mem" %}
12653 ins_encode %{
12654 #if INCLUDE_ZGC
12655 Register d = $dst$$Register;
12656 ZBarrierSetAssembler* bs = (ZBarrierSetAssembler*)BarrierSet::barrier_set()->barrier_set_assembler();
12657
12658 assert(d != r12, "Can't be R12!");
12659 assert(d != r15, "Can't be R15!");
12660 assert(d != rsp, "Can't be RSP!");
12661
12662 __ lea(d, $mem$$Address);
12663 __ call(RuntimeAddress(bs->load_barrier_slow_stub(d)));
12664 #else
12665 ShouldNotReachHere();
12666 #endif
12667 %}
12668 ins_pipe(pipe_slow);
12669 %}
12670
12671 // For XMM and YMM enabled processors
12672 instruct loadBarrierSlowRegXmmAndYmm(rRegP dst, memory mem, rFlagsReg cr,
12673 rxmm0 x0, rxmm1 x1, rxmm2 x2,rxmm3 x3,
12674 rxmm4 x4, rxmm5 x5, rxmm6 x6, rxmm7 x7,
12675 rxmm8 x8, rxmm9 x9, rxmm10 x10, rxmm11 x11,
12676 rxmm12 x12, rxmm13 x13, rxmm14 x14, rxmm15 x15) %{
12677
12678 match(Set dst (LoadBarrierSlowReg mem));
12679 predicate((UseSSE > 0) && (UseAVX <= 2) && (MaxVectorSize >= 16));
12680
12681 effect(DEF dst, KILL cr,
12682 KILL x0, KILL x1, KILL x2, KILL x3,
12683 KILL x4, KILL x5, KILL x6, KILL x7,
12684 KILL x8, KILL x9, KILL x10, KILL x11,
12685 KILL x12, KILL x13, KILL x14, KILL x15);
12686
12687 format %{"LoadBarrierSlowRegXmm $dst, $mem" %}
12688 ins_encode %{
12689 #if INCLUDE_ZGC
12690 Register d = $dst$$Register;
12691 ZBarrierSetAssembler* bs = (ZBarrierSetAssembler*)BarrierSet::barrier_set()->barrier_set_assembler();
12692
12693 assert(d != r12, "Can't be R12!");
12694 assert(d != r15, "Can't be R15!");
12695 assert(d != rsp, "Can't be RSP!");
12696
12697 __ lea(d, $mem$$Address);
12698 __ call(RuntimeAddress(bs->load_barrier_slow_stub(d)));
12699 #else
12700 ShouldNotReachHere();
12701 #endif
12702 %}
12703 ins_pipe(pipe_slow);
12704 %}
12705
12706 // For ZMM enabled processors
12707 instruct loadBarrierSlowRegZmm(rRegP dst, memory mem, rFlagsReg cr,
12708 rxmm0 x0, rxmm1 x1, rxmm2 x2,rxmm3 x3,
12709 rxmm4 x4, rxmm5 x5, rxmm6 x6, rxmm7 x7,
12710 rxmm8 x8, rxmm9 x9, rxmm10 x10, rxmm11 x11,
12711 rxmm12 x12, rxmm13 x13, rxmm14 x14, rxmm15 x15,
12712 rxmm16 x16, rxmm17 x17, rxmm18 x18, rxmm19 x19,
12713 rxmm20 x20, rxmm21 x21, rxmm22 x22, rxmm23 x23,
12714 rxmm24 x24, rxmm25 x25, rxmm26 x26, rxmm27 x27,
12715 rxmm28 x28, rxmm29 x29, rxmm30 x30, rxmm31 x31) %{
12716
12717 match(Set dst (LoadBarrierSlowReg mem));
12718 predicate((UseAVX == 3) && (MaxVectorSize >= 16));
12719
12720 effect(DEF dst, KILL cr,
12721 KILL x0, KILL x1, KILL x2, KILL x3,
12722 KILL x4, KILL x5, KILL x6, KILL x7,
12723 KILL x8, KILL x9, KILL x10, KILL x11,
12724 KILL x12, KILL x13, KILL x14, KILL x15,
12725 KILL x16, KILL x17, KILL x18, KILL x19,
12726 KILL x20, KILL x21, KILL x22, KILL x23,
12727 KILL x24, KILL x25, KILL x26, KILL x27,
12728 KILL x28, KILL x29, KILL x30, KILL x31);
12729
12730 format %{"LoadBarrierSlowRegZmm $dst, $mem" %}
12731 ins_encode %{
12732 #if INCLUDE_ZGC
12733 Register d = $dst$$Register;
12734 ZBarrierSetAssembler* bs = (ZBarrierSetAssembler*)BarrierSet::barrier_set()->barrier_set_assembler();
12735
12736 assert(d != r12, "Can't be R12!");
12737 assert(d != r15, "Can't be R15!");
12738 assert(d != rsp, "Can't be RSP!");
12739
12740 __ lea(d, $mem$$Address);
12741 __ call(RuntimeAddress(bs->load_barrier_slow_stub(d)));
12742 #else
12743 ShouldNotReachHere();
12744 #endif
12745 %}
12746 ins_pipe(pipe_slow);
12747 %}
12748
12749 //
12750 // Execute ZGC load barrier (weak) slow path
12751 //
12752
12753 // When running without XMM regs
12754 instruct loadBarrierWeakSlowRegNoVec(rRegP dst, memory mem, rFlagsReg cr) %{
12755
12756 match(Set dst (LoadBarrierSlowReg mem));
12757 predicate(MaxVectorSize < 16);
12758
12759 effect(DEF dst, KILL cr);
12760
12761 format %{"LoadBarrierSlowRegNoVec $dst, $mem" %}
12762 ins_encode %{
12763 #if INCLUDE_ZGC
12764 Register d = $dst$$Register;
12765 ZBarrierSetAssembler* bs = (ZBarrierSetAssembler*)BarrierSet::barrier_set()->barrier_set_assembler();
12766
12767 assert(d != r12, "Can't be R12!");
12768 assert(d != r15, "Can't be R15!");
12769 assert(d != rsp, "Can't be RSP!");
12770
12771 __ lea(d, $mem$$Address);
12772 __ call(RuntimeAddress(bs->load_barrier_weak_slow_stub(d)));
12773 #else
12774 ShouldNotReachHere();
12775 #endif
12776 %}
12777 ins_pipe(pipe_slow);
12778 %}
12779
12780 // For XMM and YMM enabled processors
12781 instruct loadBarrierWeakSlowRegXmmAndYmm(rRegP dst, memory mem, rFlagsReg cr,
12782 rxmm0 x0, rxmm1 x1, rxmm2 x2,rxmm3 x3,
12783 rxmm4 x4, rxmm5 x5, rxmm6 x6, rxmm7 x7,
12784 rxmm8 x8, rxmm9 x9, rxmm10 x10, rxmm11 x11,
12785 rxmm12 x12, rxmm13 x13, rxmm14 x14, rxmm15 x15) %{
12786
12787 match(Set dst (LoadBarrierWeakSlowReg mem));
12788 predicate((UseSSE > 0) && (UseAVX <= 2) && (MaxVectorSize >= 16));
12789
12790 effect(DEF dst, KILL cr,
12791 KILL x0, KILL x1, KILL x2, KILL x3,
12792 KILL x4, KILL x5, KILL x6, KILL x7,
12793 KILL x8, KILL x9, KILL x10, KILL x11,
12794 KILL x12, KILL x13, KILL x14, KILL x15);
12795
12796 format %{"LoadBarrierWeakSlowRegXmm $dst, $mem" %}
12797 ins_encode %{
12798 #if INCLUDE_ZGC
12799 Register d = $dst$$Register;
12800 ZBarrierSetAssembler* bs = (ZBarrierSetAssembler*)BarrierSet::barrier_set()->barrier_set_assembler();
12801
12802 assert(d != r12, "Can't be R12!");
12803 assert(d != r15, "Can't be R15!");
12804 assert(d != rsp, "Can't be RSP!");
12805
12806 __ lea(d,$mem$$Address);
12807 __ call(RuntimeAddress(bs->load_barrier_weak_slow_stub(d)));
12808 #else
12809 ShouldNotReachHere();
12810 #endif
12811 %}
12812 ins_pipe(pipe_slow);
12813 %}
12814
12815 // For ZMM enabled processors
12816 instruct loadBarrierWeakSlowRegZmm(rRegP dst, memory mem, rFlagsReg cr,
12817 rxmm0 x0, rxmm1 x1, rxmm2 x2,rxmm3 x3,
12818 rxmm4 x4, rxmm5 x5, rxmm6 x6, rxmm7 x7,
12819 rxmm8 x8, rxmm9 x9, rxmm10 x10, rxmm11 x11,
12820 rxmm12 x12, rxmm13 x13, rxmm14 x14, rxmm15 x15,
12821 rxmm16 x16, rxmm17 x17, rxmm18 x18, rxmm19 x19,
12822 rxmm20 x20, rxmm21 x21, rxmm22 x22, rxmm23 x23,
12823 rxmm24 x24, rxmm25 x25, rxmm26 x26, rxmm27 x27,
12824 rxmm28 x28, rxmm29 x29, rxmm30 x30, rxmm31 x31) %{
12825
12826 match(Set dst (LoadBarrierWeakSlowReg mem));
12827 predicate((UseAVX == 3) && (MaxVectorSize >= 16));
12828
12829 effect(DEF dst, KILL cr,
12830 KILL x0, KILL x1, KILL x2, KILL x3,
12831 KILL x4, KILL x5, KILL x6, KILL x7,
12832 KILL x8, KILL x9, KILL x10, KILL x11,
12833 KILL x12, KILL x13, KILL x14, KILL x15,
12834 KILL x16, KILL x17, KILL x18, KILL x19,
12835 KILL x20, KILL x21, KILL x22, KILL x23,
12836 KILL x24, KILL x25, KILL x26, KILL x27,
12837 KILL x28, KILL x29, KILL x30, KILL x31);
12838
12839 format %{"LoadBarrierWeakSlowRegZmm $dst, $mem" %}
12840 ins_encode %{
12841 #if INCLUDE_ZGC
12842 Register d = $dst$$Register;
12843 ZBarrierSetAssembler* bs = (ZBarrierSetAssembler*)BarrierSet::barrier_set()->barrier_set_assembler();
12844
12845 assert(d != r12, "Can't be R12!");
12846 assert(d != r15, "Can't be R15!");
12847 assert(d != rsp, "Can't be RSP!");
12848
12849 __ lea(d,$mem$$Address);
12850 __ call(RuntimeAddress(bs->load_barrier_weak_slow_stub(d)));
12851 #else
12852 ShouldNotReachHere();
12853 #endif
12854 %}
12855 ins_pipe(pipe_slow);
12856 %}
12857
12858 // ============================================================================
12859 // This name is KNOWN by the ADLC and cannot be changed.
12860 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
12861 // for this guy.
12862 instruct tlsLoadP(r15_RegP dst) %{
12863 match(Set dst (ThreadLocal));
12864 effect(DEF dst);
12865
12866 size(0);
12867 format %{ "# TLS is in R15" %}
12868 ins_encode( /*empty encoding*/ );
12869 ins_pipe(ialu_reg_reg);
12870 %}
12871
12872
12873 //----------PEEPHOLE RULES-----------------------------------------------------
12874 // These must follow all instruction definitions as they use the names
12875 // defined in the instructions definitions.
12876 //
12877 // peepmatch ( root_instr_name [preceding_instruction]* );
12878 //
12879 // peepconstraint %{
12880 // (instruction_number.operand_name relational_op instruction_number.operand_name
12881 // [, ...] );
12882 // // instruction numbers are zero-based using left to right order in peepmatch
12883 //
12884 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
12885 // // provide an instruction_number.operand_name for each operand that appears
12886 // // in the replacement instruction's match rule
12887 //
12888 // ---------VM FLAGS---------------------------------------------------------
12889 //
12890 // All peephole optimizations can be turned off using -XX:-OptoPeephole
12891 //
12892 // Each peephole rule is given an identifying number starting with zero and
12893 // increasing by one in the order seen by the parser. An individual peephole
12894 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
12895 // on the command-line.
12896 //
12897 // ---------CURRENT LIMITATIONS----------------------------------------------
12898 //
12899 // Only match adjacent instructions in same basic block
12900 // Only equality constraints
12901 // Only constraints between operands, not (0.dest_reg == RAX_enc)
12902 // Only one replacement instruction
12903 //
12904 // ---------EXAMPLE----------------------------------------------------------
12905 //
12906 // // pertinent parts of existing instructions in architecture description
12907 // instruct movI(rRegI dst, rRegI src)
12908 // %{
12909 // match(Set dst (CopyI src));
12910 // %}
12911 //
12912 // instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
12913 // %{
12914 // match(Set dst (AddI dst src));
12915 // effect(KILL cr);
12916 // %}
12917 //
12918 // // Change (inc mov) to lea
12919 // peephole %{
12920 // // increment preceeded by register-register move
12921 // peepmatch ( incI_rReg movI );
12922 // // require that the destination register of the increment
12923 // // match the destination register of the move
12924 // peepconstraint ( 0.dst == 1.dst );
12925 // // construct a replacement instruction that sets
12926 // // the destination to ( move's source register + one )
12927 // peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) );
12928 // %}
12929 //
12930
12931 // Implementation no longer uses movX instructions since
12932 // machine-independent system no longer uses CopyX nodes.
12933 //
12934 // peephole
12935 // %{
12936 // peepmatch (incI_rReg movI);
12937 // peepconstraint (0.dst == 1.dst);
12938 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
12939 // %}
12940
12941 // peephole
12942 // %{
12943 // peepmatch (decI_rReg movI);
12944 // peepconstraint (0.dst == 1.dst);
12945 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
12946 // %}
12947
12948 // peephole
12949 // %{
12950 // peepmatch (addI_rReg_imm movI);
12951 // peepconstraint (0.dst == 1.dst);
12952 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
12953 // %}
12954
12955 // peephole
12956 // %{
12957 // peepmatch (incL_rReg movL);
12958 // peepconstraint (0.dst == 1.dst);
12959 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
12960 // %}
12961
12962 // peephole
12963 // %{
12964 // peepmatch (decL_rReg movL);
12965 // peepconstraint (0.dst == 1.dst);
12966 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
12967 // %}
12968
12969 // peephole
12970 // %{
12971 // peepmatch (addL_rReg_imm movL);
12972 // peepconstraint (0.dst == 1.dst);
12973 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
12974 // %}
12975
12976 // peephole
12977 // %{
12978 // peepmatch (addP_rReg_imm movP);
12979 // peepconstraint (0.dst == 1.dst);
12980 // peepreplace (leaP_rReg_imm(0.dst 1.src 0.src));
12981 // %}
12982
12983 // // Change load of spilled value to only a spill
12984 // instruct storeI(memory mem, rRegI src)
12985 // %{
12986 // match(Set mem (StoreI mem src));
12987 // %}
12988 //
12989 // instruct loadI(rRegI dst, memory mem)
12990 // %{
12991 // match(Set dst (LoadI mem));
12992 // %}
12993 //
12994
12995 peephole
12996 %{
12997 peepmatch (loadI storeI);
12998 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
12999 peepreplace (storeI(1.mem 1.mem 1.src));
13000 %}
13001
13002 peephole
13003 %{
13004 peepmatch (loadL storeL);
13005 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
13006 peepreplace (storeL(1.mem 1.mem 1.src));
13007 %}
13008
13009 //----------SMARTSPILL RULES---------------------------------------------------
13010 // These must follow all instruction definitions as they use the names
13011 // defined in the instructions definitions.