1 /* 2 * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "memory/allocation.inline.hpp" 27 #include "memory/resourceArea.hpp" 28 #include "opto/ad.hpp" 29 #include "opto/addnode.hpp" 30 #include "opto/callnode.hpp" 31 #include "opto/idealGraphPrinter.hpp" 32 #include "opto/matcher.hpp" 33 #include "opto/memnode.hpp" 34 #include "opto/movenode.hpp" 35 #include "opto/opcodes.hpp" 36 #include "opto/regmask.hpp" 37 #include "opto/rootnode.hpp" 38 #include "opto/runtime.hpp" 39 #include "opto/type.hpp" 40 #include "opto/vectornode.hpp" 41 #include "runtime/os.hpp" 42 #include "runtime/sharedRuntime.hpp" 43 #include "utilities/align.hpp" 44 #if INCLUDE_ZGC 45 #include "gc/z/zBarrierSetRuntime.hpp" 46 #endif // INCLUDE_ZGC 47 48 OptoReg::Name OptoReg::c_frame_pointer; 49 50 const RegMask *Matcher::idealreg2regmask[_last_machine_leaf]; 51 RegMask Matcher::mreg2regmask[_last_Mach_Reg]; 52 RegMask Matcher::STACK_ONLY_mask; 53 RegMask Matcher::c_frame_ptr_mask; 54 const uint Matcher::_begin_rematerialize = _BEGIN_REMATERIALIZE; 55 const uint Matcher::_end_rematerialize = _END_REMATERIALIZE; 56 57 //---------------------------Matcher------------------------------------------- 58 Matcher::Matcher() 59 : PhaseTransform( Phase::Ins_Select ), 60 _states_arena(Chunk::medium_size, mtCompiler), 61 _visited(&_states_arena), 62 _shared(&_states_arena), 63 _dontcare(&_states_arena), 64 _reduceOp(reduceOp), _leftOp(leftOp), _rightOp(rightOp), 65 _swallowed(swallowed), 66 _begin_inst_chain_rule(_BEGIN_INST_CHAIN_RULE), 67 _end_inst_chain_rule(_END_INST_CHAIN_RULE), 68 _must_clone(must_clone), 69 _shared_nodes(C->comp_arena()), 70 #ifdef ASSERT 71 _old2new_map(C->comp_arena()), 72 _new2old_map(C->comp_arena()), 73 #endif 74 _allocation_started(false), 75 _ruleName(ruleName), 76 _register_save_policy(register_save_policy), 77 _c_reg_save_policy(c_reg_save_policy), 78 _register_save_type(register_save_type) { 79 C->set_matcher(this); 80 81 idealreg2spillmask [Op_RegI] = NULL; 82 idealreg2spillmask [Op_RegN] = NULL; 83 idealreg2spillmask [Op_RegL] = NULL; 84 idealreg2spillmask [Op_RegF] = NULL; 85 idealreg2spillmask [Op_RegD] = NULL; 86 idealreg2spillmask [Op_RegP] = NULL; 87 idealreg2spillmask [Op_VecS] = NULL; 88 idealreg2spillmask [Op_VecD] = NULL; 89 idealreg2spillmask [Op_VecX] = NULL; 90 idealreg2spillmask [Op_VecY] = NULL; 91 idealreg2spillmask [Op_VecZ] = NULL; 92 idealreg2spillmask [Op_RegFlags] = NULL; 93 94 idealreg2debugmask [Op_RegI] = NULL; 95 idealreg2debugmask [Op_RegN] = NULL; 96 idealreg2debugmask [Op_RegL] = NULL; 97 idealreg2debugmask [Op_RegF] = NULL; 98 idealreg2debugmask [Op_RegD] = NULL; 99 idealreg2debugmask [Op_RegP] = NULL; 100 idealreg2debugmask [Op_VecS] = NULL; 101 idealreg2debugmask [Op_VecD] = NULL; 102 idealreg2debugmask [Op_VecX] = NULL; 103 idealreg2debugmask [Op_VecY] = NULL; 104 idealreg2debugmask [Op_VecZ] = NULL; 105 idealreg2debugmask [Op_RegFlags] = NULL; 106 107 idealreg2mhdebugmask[Op_RegI] = NULL; 108 idealreg2mhdebugmask[Op_RegN] = NULL; 109 idealreg2mhdebugmask[Op_RegL] = NULL; 110 idealreg2mhdebugmask[Op_RegF] = NULL; 111 idealreg2mhdebugmask[Op_RegD] = NULL; 112 idealreg2mhdebugmask[Op_RegP] = NULL; 113 idealreg2mhdebugmask[Op_VecS] = NULL; 114 idealreg2mhdebugmask[Op_VecD] = NULL; 115 idealreg2mhdebugmask[Op_VecX] = NULL; 116 idealreg2mhdebugmask[Op_VecY] = NULL; 117 idealreg2mhdebugmask[Op_VecZ] = NULL; 118 idealreg2mhdebugmask[Op_RegFlags] = NULL; 119 120 debug_only(_mem_node = NULL;) // Ideal memory node consumed by mach node 121 } 122 123 //------------------------------warp_incoming_stk_arg------------------------ 124 // This warps a VMReg into an OptoReg::Name 125 OptoReg::Name Matcher::warp_incoming_stk_arg( VMReg reg ) { 126 OptoReg::Name warped; 127 if( reg->is_stack() ) { // Stack slot argument? 128 warped = OptoReg::add(_old_SP, reg->reg2stack() ); 129 warped = OptoReg::add(warped, C->out_preserve_stack_slots()); 130 if( warped >= _in_arg_limit ) 131 _in_arg_limit = OptoReg::add(warped, 1); // Bump max stack slot seen 132 if (!RegMask::can_represent_arg(warped)) { 133 // the compiler cannot represent this method's calling sequence 134 C->record_method_not_compilable("unsupported incoming calling sequence"); 135 return OptoReg::Bad; 136 } 137 return warped; 138 } 139 return OptoReg::as_OptoReg(reg); 140 } 141 142 //---------------------------compute_old_SP------------------------------------ 143 OptoReg::Name Compile::compute_old_SP() { 144 int fixed = fixed_slots(); 145 int preserve = in_preserve_stack_slots(); 146 return OptoReg::stack2reg(align_up(fixed + preserve, (int)Matcher::stack_alignment_in_slots())); 147 } 148 149 150 151 #ifdef ASSERT 152 void Matcher::verify_new_nodes_only(Node* xroot) { 153 // Make sure that the new graph only references new nodes 154 ResourceMark rm; 155 Unique_Node_List worklist; 156 VectorSet visited(Thread::current()->resource_area()); 157 worklist.push(xroot); 158 while (worklist.size() > 0) { 159 Node* n = worklist.pop(); 160 visited <<= n->_idx; 161 assert(C->node_arena()->contains(n), "dead node"); 162 for (uint j = 0; j < n->req(); j++) { 163 Node* in = n->in(j); 164 if (in != NULL) { 165 assert(C->node_arena()->contains(in), "dead node"); 166 if (!visited.test(in->_idx)) { 167 worklist.push(in); 168 } 169 } 170 } 171 } 172 } 173 #endif 174 175 176 //---------------------------match--------------------------------------------- 177 void Matcher::match( ) { 178 if( MaxLabelRootDepth < 100 ) { // Too small? 179 assert(false, "invalid MaxLabelRootDepth, increase it to 100 minimum"); 180 MaxLabelRootDepth = 100; 181 } 182 // One-time initialization of some register masks. 183 init_spill_mask( C->root()->in(1) ); 184 _return_addr_mask = return_addr(); 185 #ifdef _LP64 186 // Pointers take 2 slots in 64-bit land 187 _return_addr_mask.Insert(OptoReg::add(return_addr(),1)); 188 #endif 189 190 // Map a Java-signature return type into return register-value 191 // machine registers for 0, 1 and 2 returned values. 192 const TypeTuple *range = C->tf()->range(); 193 if( range->cnt() > TypeFunc::Parms ) { // If not a void function 194 // Get ideal-register return type 195 uint ireg = range->field_at(TypeFunc::Parms)->ideal_reg(); 196 // Get machine return register 197 uint sop = C->start()->Opcode(); 198 OptoRegPair regs = return_value(ireg, false); 199 200 // And mask for same 201 _return_value_mask = RegMask(regs.first()); 202 if( OptoReg::is_valid(regs.second()) ) 203 _return_value_mask.Insert(regs.second()); 204 } 205 206 // --------------- 207 // Frame Layout 208 209 // Need the method signature to determine the incoming argument types, 210 // because the types determine which registers the incoming arguments are 211 // in, and this affects the matched code. 212 const TypeTuple *domain = C->tf()->domain(); 213 uint argcnt = domain->cnt() - TypeFunc::Parms; 214 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt ); 215 VMRegPair *vm_parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt ); 216 _parm_regs = NEW_RESOURCE_ARRAY( OptoRegPair, argcnt ); 217 _calling_convention_mask = NEW_RESOURCE_ARRAY( RegMask, argcnt ); 218 uint i; 219 for( i = 0; i<argcnt; i++ ) { 220 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type(); 221 } 222 223 // Pass array of ideal registers and length to USER code (from the AD file) 224 // that will convert this to an array of register numbers. 225 const StartNode *start = C->start(); 226 start->calling_convention( sig_bt, vm_parm_regs, argcnt ); 227 #ifdef ASSERT 228 // Sanity check users' calling convention. Real handy while trying to 229 // get the initial port correct. 230 { for (uint i = 0; i<argcnt; i++) { 231 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) { 232 assert(domain->field_at(i+TypeFunc::Parms)==Type::HALF, "only allowed on halve" ); 233 _parm_regs[i].set_bad(); 234 continue; 235 } 236 VMReg parm_reg = vm_parm_regs[i].first(); 237 assert(parm_reg->is_valid(), "invalid arg?"); 238 if (parm_reg->is_reg()) { 239 OptoReg::Name opto_parm_reg = OptoReg::as_OptoReg(parm_reg); 240 assert(can_be_java_arg(opto_parm_reg) || 241 C->stub_function() == CAST_FROM_FN_PTR(address, OptoRuntime::rethrow_C) || 242 opto_parm_reg == inline_cache_reg(), 243 "parameters in register must be preserved by runtime stubs"); 244 } 245 for (uint j = 0; j < i; j++) { 246 assert(parm_reg != vm_parm_regs[j].first(), 247 "calling conv. must produce distinct regs"); 248 } 249 } 250 } 251 #endif 252 253 // Do some initial frame layout. 254 255 // Compute the old incoming SP (may be called FP) as 256 // OptoReg::stack0() + locks + in_preserve_stack_slots + pad2. 257 _old_SP = C->compute_old_SP(); 258 assert( is_even(_old_SP), "must be even" ); 259 260 // Compute highest incoming stack argument as 261 // _old_SP + out_preserve_stack_slots + incoming argument size. 262 _in_arg_limit = OptoReg::add(_old_SP, C->out_preserve_stack_slots()); 263 assert( is_even(_in_arg_limit), "out_preserve must be even" ); 264 for( i = 0; i < argcnt; i++ ) { 265 // Permit args to have no register 266 _calling_convention_mask[i].Clear(); 267 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) { 268 continue; 269 } 270 // calling_convention returns stack arguments as a count of 271 // slots beyond OptoReg::stack0()/VMRegImpl::stack0. We need to convert this to 272 // the allocators point of view, taking into account all the 273 // preserve area, locks & pad2. 274 275 OptoReg::Name reg1 = warp_incoming_stk_arg(vm_parm_regs[i].first()); 276 if( OptoReg::is_valid(reg1)) 277 _calling_convention_mask[i].Insert(reg1); 278 279 OptoReg::Name reg2 = warp_incoming_stk_arg(vm_parm_regs[i].second()); 280 if( OptoReg::is_valid(reg2)) 281 _calling_convention_mask[i].Insert(reg2); 282 283 // Saved biased stack-slot register number 284 _parm_regs[i].set_pair(reg2, reg1); 285 } 286 287 // Finally, make sure the incoming arguments take up an even number of 288 // words, in case the arguments or locals need to contain doubleword stack 289 // slots. The rest of the system assumes that stack slot pairs (in 290 // particular, in the spill area) which look aligned will in fact be 291 // aligned relative to the stack pointer in the target machine. Double 292 // stack slots will always be allocated aligned. 293 _new_SP = OptoReg::Name(align_up(_in_arg_limit, (int)RegMask::SlotsPerLong)); 294 295 // Compute highest outgoing stack argument as 296 // _new_SP + out_preserve_stack_slots + max(outgoing argument size). 297 _out_arg_limit = OptoReg::add(_new_SP, C->out_preserve_stack_slots()); 298 assert( is_even(_out_arg_limit), "out_preserve must be even" ); 299 300 if (!RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1))) { 301 // the compiler cannot represent this method's calling sequence 302 C->record_method_not_compilable("must be able to represent all call arguments in reg mask"); 303 } 304 305 if (C->failing()) return; // bailed out on incoming arg failure 306 307 // --------------- 308 // Collect roots of matcher trees. Every node for which 309 // _shared[_idx] is cleared is guaranteed to not be shared, and thus 310 // can be a valid interior of some tree. 311 find_shared( C->root() ); 312 find_shared( C->top() ); 313 314 C->print_method(PHASE_BEFORE_MATCHING); 315 316 // Create new ideal node ConP #NULL even if it does exist in old space 317 // to avoid false sharing if the corresponding mach node is not used. 318 // The corresponding mach node is only used in rare cases for derived 319 // pointers. 320 Node* new_ideal_null = ConNode::make(TypePtr::NULL_PTR); 321 322 // Swap out to old-space; emptying new-space 323 Arena *old = C->node_arena()->move_contents(C->old_arena()); 324 325 // Save debug and profile information for nodes in old space: 326 _old_node_note_array = C->node_note_array(); 327 if (_old_node_note_array != NULL) { 328 C->set_node_note_array(new(C->comp_arena()) GrowableArray<Node_Notes*> 329 (C->comp_arena(), _old_node_note_array->length(), 330 0, NULL)); 331 } 332 333 // Pre-size the new_node table to avoid the need for range checks. 334 grow_new_node_array(C->unique()); 335 336 // Reset node counter so MachNodes start with _idx at 0 337 int live_nodes = C->live_nodes(); 338 C->set_unique(0); 339 C->reset_dead_node_list(); 340 341 // Recursively match trees from old space into new space. 342 // Correct leaves of new-space Nodes; they point to old-space. 343 _visited.Clear(); // Clear visit bits for xform call 344 C->set_cached_top_node(xform( C->top(), live_nodes )); 345 if (!C->failing()) { 346 Node* xroot = xform( C->root(), 1 ); 347 if (xroot == NULL) { 348 Matcher::soft_match_failure(); // recursive matching process failed 349 C->record_method_not_compilable("instruction match failed"); 350 } else { 351 // During matching shared constants were attached to C->root() 352 // because xroot wasn't available yet, so transfer the uses to 353 // the xroot. 354 for( DUIterator_Fast jmax, j = C->root()->fast_outs(jmax); j < jmax; j++ ) { 355 Node* n = C->root()->fast_out(j); 356 if (C->node_arena()->contains(n)) { 357 assert(n->in(0) == C->root(), "should be control user"); 358 n->set_req(0, xroot); 359 --j; 360 --jmax; 361 } 362 } 363 364 // Generate new mach node for ConP #NULL 365 assert(new_ideal_null != NULL, "sanity"); 366 _mach_null = match_tree(new_ideal_null); 367 // Don't set control, it will confuse GCM since there are no uses. 368 // The control will be set when this node is used first time 369 // in find_base_for_derived(). 370 assert(_mach_null != NULL, ""); 371 372 C->set_root(xroot->is_Root() ? xroot->as_Root() : NULL); 373 374 #ifdef ASSERT 375 verify_new_nodes_only(xroot); 376 #endif 377 } 378 } 379 if (C->top() == NULL || C->root() == NULL) { 380 C->record_method_not_compilable("graph lost"); // %%% cannot happen? 381 } 382 if (C->failing()) { 383 // delete old; 384 old->destruct_contents(); 385 return; 386 } 387 assert( C->top(), "" ); 388 assert( C->root(), "" ); 389 validate_null_checks(); 390 391 // Now smoke old-space 392 NOT_DEBUG( old->destruct_contents() ); 393 394 // ------------------------ 395 // Set up save-on-entry registers 396 Fixup_Save_On_Entry( ); 397 } 398 399 400 //------------------------------Fixup_Save_On_Entry---------------------------- 401 // The stated purpose of this routine is to take care of save-on-entry 402 // registers. However, the overall goal of the Match phase is to convert into 403 // machine-specific instructions which have RegMasks to guide allocation. 404 // So what this procedure really does is put a valid RegMask on each input 405 // to the machine-specific variations of all Return, TailCall and Halt 406 // instructions. It also adds edgs to define the save-on-entry values (and of 407 // course gives them a mask). 408 409 static RegMask *init_input_masks( uint size, RegMask &ret_adr, RegMask &fp ) { 410 RegMask *rms = NEW_RESOURCE_ARRAY( RegMask, size ); 411 // Do all the pre-defined register masks 412 rms[TypeFunc::Control ] = RegMask::Empty; 413 rms[TypeFunc::I_O ] = RegMask::Empty; 414 rms[TypeFunc::Memory ] = RegMask::Empty; 415 rms[TypeFunc::ReturnAdr] = ret_adr; 416 rms[TypeFunc::FramePtr ] = fp; 417 return rms; 418 } 419 420 //---------------------------init_first_stack_mask----------------------------- 421 // Create the initial stack mask used by values spilling to the stack. 422 // Disallow any debug info in outgoing argument areas by setting the 423 // initial mask accordingly. 424 void Matcher::init_first_stack_mask() { 425 426 // Allocate storage for spill masks as masks for the appropriate load type. 427 RegMask *rms = (RegMask*)C->comp_arena()->Amalloc_D(sizeof(RegMask) * (3*6+5)); 428 429 idealreg2spillmask [Op_RegN] = &rms[0]; 430 idealreg2spillmask [Op_RegI] = &rms[1]; 431 idealreg2spillmask [Op_RegL] = &rms[2]; 432 idealreg2spillmask [Op_RegF] = &rms[3]; 433 idealreg2spillmask [Op_RegD] = &rms[4]; 434 idealreg2spillmask [Op_RegP] = &rms[5]; 435 436 idealreg2debugmask [Op_RegN] = &rms[6]; 437 idealreg2debugmask [Op_RegI] = &rms[7]; 438 idealreg2debugmask [Op_RegL] = &rms[8]; 439 idealreg2debugmask [Op_RegF] = &rms[9]; 440 idealreg2debugmask [Op_RegD] = &rms[10]; 441 idealreg2debugmask [Op_RegP] = &rms[11]; 442 443 idealreg2mhdebugmask[Op_RegN] = &rms[12]; 444 idealreg2mhdebugmask[Op_RegI] = &rms[13]; 445 idealreg2mhdebugmask[Op_RegL] = &rms[14]; 446 idealreg2mhdebugmask[Op_RegF] = &rms[15]; 447 idealreg2mhdebugmask[Op_RegD] = &rms[16]; 448 idealreg2mhdebugmask[Op_RegP] = &rms[17]; 449 450 idealreg2spillmask [Op_VecS] = &rms[18]; 451 idealreg2spillmask [Op_VecD] = &rms[19]; 452 idealreg2spillmask [Op_VecX] = &rms[20]; 453 idealreg2spillmask [Op_VecY] = &rms[21]; 454 idealreg2spillmask [Op_VecZ] = &rms[22]; 455 456 OptoReg::Name i; 457 458 // At first, start with the empty mask 459 C->FIRST_STACK_mask().Clear(); 460 461 // Add in the incoming argument area 462 OptoReg::Name init_in = OptoReg::add(_old_SP, C->out_preserve_stack_slots()); 463 for (i = init_in; i < _in_arg_limit; i = OptoReg::add(i,1)) { 464 C->FIRST_STACK_mask().Insert(i); 465 } 466 // Add in all bits past the outgoing argument area 467 guarantee(RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1)), 468 "must be able to represent all call arguments in reg mask"); 469 OptoReg::Name init = _out_arg_limit; 470 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1)) { 471 C->FIRST_STACK_mask().Insert(i); 472 } 473 // Finally, set the "infinite stack" bit. 474 C->FIRST_STACK_mask().set_AllStack(); 475 476 // Make spill masks. Registers for their class, plus FIRST_STACK_mask. 477 RegMask aligned_stack_mask = C->FIRST_STACK_mask(); 478 // Keep spill masks aligned. 479 aligned_stack_mask.clear_to_pairs(); 480 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack"); 481 482 *idealreg2spillmask[Op_RegP] = *idealreg2regmask[Op_RegP]; 483 #ifdef _LP64 484 *idealreg2spillmask[Op_RegN] = *idealreg2regmask[Op_RegN]; 485 idealreg2spillmask[Op_RegN]->OR(C->FIRST_STACK_mask()); 486 idealreg2spillmask[Op_RegP]->OR(aligned_stack_mask); 487 #else 488 idealreg2spillmask[Op_RegP]->OR(C->FIRST_STACK_mask()); 489 #endif 490 *idealreg2spillmask[Op_RegI] = *idealreg2regmask[Op_RegI]; 491 idealreg2spillmask[Op_RegI]->OR(C->FIRST_STACK_mask()); 492 *idealreg2spillmask[Op_RegL] = *idealreg2regmask[Op_RegL]; 493 idealreg2spillmask[Op_RegL]->OR(aligned_stack_mask); 494 *idealreg2spillmask[Op_RegF] = *idealreg2regmask[Op_RegF]; 495 idealreg2spillmask[Op_RegF]->OR(C->FIRST_STACK_mask()); 496 *idealreg2spillmask[Op_RegD] = *idealreg2regmask[Op_RegD]; 497 idealreg2spillmask[Op_RegD]->OR(aligned_stack_mask); 498 499 if (Matcher::vector_size_supported(T_BYTE,4)) { 500 *idealreg2spillmask[Op_VecS] = *idealreg2regmask[Op_VecS]; 501 idealreg2spillmask[Op_VecS]->OR(C->FIRST_STACK_mask()); 502 } 503 if (Matcher::vector_size_supported(T_FLOAT,2)) { 504 // For VecD we need dual alignment and 8 bytes (2 slots) for spills. 505 // RA guarantees such alignment since it is needed for Double and Long values. 506 *idealreg2spillmask[Op_VecD] = *idealreg2regmask[Op_VecD]; 507 idealreg2spillmask[Op_VecD]->OR(aligned_stack_mask); 508 } 509 if (Matcher::vector_size_supported(T_FLOAT,4)) { 510 // For VecX we need quadro alignment and 16 bytes (4 slots) for spills. 511 // 512 // RA can use input arguments stack slots for spills but until RA 513 // we don't know frame size and offset of input arg stack slots. 514 // 515 // Exclude last input arg stack slots to avoid spilling vectors there 516 // otherwise vector spills could stomp over stack slots in caller frame. 517 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1); 518 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecX); k++) { 519 aligned_stack_mask.Remove(in); 520 in = OptoReg::add(in, -1); 521 } 522 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecX); 523 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack"); 524 *idealreg2spillmask[Op_VecX] = *idealreg2regmask[Op_VecX]; 525 idealreg2spillmask[Op_VecX]->OR(aligned_stack_mask); 526 } 527 if (Matcher::vector_size_supported(T_FLOAT,8)) { 528 // For VecY we need octo alignment and 32 bytes (8 slots) for spills. 529 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1); 530 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecY); k++) { 531 aligned_stack_mask.Remove(in); 532 in = OptoReg::add(in, -1); 533 } 534 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecY); 535 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack"); 536 *idealreg2spillmask[Op_VecY] = *idealreg2regmask[Op_VecY]; 537 idealreg2spillmask[Op_VecY]->OR(aligned_stack_mask); 538 } 539 if (Matcher::vector_size_supported(T_FLOAT,16)) { 540 // For VecZ we need enough alignment and 64 bytes (16 slots) for spills. 541 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1); 542 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecZ); k++) { 543 aligned_stack_mask.Remove(in); 544 in = OptoReg::add(in, -1); 545 } 546 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecZ); 547 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack"); 548 *idealreg2spillmask[Op_VecZ] = *idealreg2regmask[Op_VecZ]; 549 idealreg2spillmask[Op_VecZ]->OR(aligned_stack_mask); 550 } 551 if (UseFPUForSpilling) { 552 // This mask logic assumes that the spill operations are 553 // symmetric and that the registers involved are the same size. 554 // On sparc for instance we may have to use 64 bit moves will 555 // kill 2 registers when used with F0-F31. 556 idealreg2spillmask[Op_RegI]->OR(*idealreg2regmask[Op_RegF]); 557 idealreg2spillmask[Op_RegF]->OR(*idealreg2regmask[Op_RegI]); 558 #ifdef _LP64 559 idealreg2spillmask[Op_RegN]->OR(*idealreg2regmask[Op_RegF]); 560 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]); 561 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]); 562 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegD]); 563 #else 564 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegF]); 565 #ifdef ARM 566 // ARM has support for moving 64bit values between a pair of 567 // integer registers and a double register 568 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]); 569 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]); 570 #endif 571 #endif 572 } 573 574 // Make up debug masks. Any spill slot plus callee-save registers. 575 // Caller-save registers are assumed to be trashable by the various 576 // inline-cache fixup routines. 577 *idealreg2debugmask [Op_RegN]= *idealreg2spillmask[Op_RegN]; 578 *idealreg2debugmask [Op_RegI]= *idealreg2spillmask[Op_RegI]; 579 *idealreg2debugmask [Op_RegL]= *idealreg2spillmask[Op_RegL]; 580 *idealreg2debugmask [Op_RegF]= *idealreg2spillmask[Op_RegF]; 581 *idealreg2debugmask [Op_RegD]= *idealreg2spillmask[Op_RegD]; 582 *idealreg2debugmask [Op_RegP]= *idealreg2spillmask[Op_RegP]; 583 584 *idealreg2mhdebugmask[Op_RegN]= *idealreg2spillmask[Op_RegN]; 585 *idealreg2mhdebugmask[Op_RegI]= *idealreg2spillmask[Op_RegI]; 586 *idealreg2mhdebugmask[Op_RegL]= *idealreg2spillmask[Op_RegL]; 587 *idealreg2mhdebugmask[Op_RegF]= *idealreg2spillmask[Op_RegF]; 588 *idealreg2mhdebugmask[Op_RegD]= *idealreg2spillmask[Op_RegD]; 589 *idealreg2mhdebugmask[Op_RegP]= *idealreg2spillmask[Op_RegP]; 590 591 // Prevent stub compilations from attempting to reference 592 // callee-saved registers from debug info 593 bool exclude_soe = !Compile::current()->is_method_compilation(); 594 595 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) { 596 // registers the caller has to save do not work 597 if( _register_save_policy[i] == 'C' || 598 _register_save_policy[i] == 'A' || 599 (_register_save_policy[i] == 'E' && exclude_soe) ) { 600 idealreg2debugmask [Op_RegN]->Remove(i); 601 idealreg2debugmask [Op_RegI]->Remove(i); // Exclude save-on-call 602 idealreg2debugmask [Op_RegL]->Remove(i); // registers from debug 603 idealreg2debugmask [Op_RegF]->Remove(i); // masks 604 idealreg2debugmask [Op_RegD]->Remove(i); 605 idealreg2debugmask [Op_RegP]->Remove(i); 606 607 idealreg2mhdebugmask[Op_RegN]->Remove(i); 608 idealreg2mhdebugmask[Op_RegI]->Remove(i); 609 idealreg2mhdebugmask[Op_RegL]->Remove(i); 610 idealreg2mhdebugmask[Op_RegF]->Remove(i); 611 idealreg2mhdebugmask[Op_RegD]->Remove(i); 612 idealreg2mhdebugmask[Op_RegP]->Remove(i); 613 } 614 } 615 616 // Subtract the register we use to save the SP for MethodHandle 617 // invokes to from the debug mask. 618 const RegMask save_mask = method_handle_invoke_SP_save_mask(); 619 idealreg2mhdebugmask[Op_RegN]->SUBTRACT(save_mask); 620 idealreg2mhdebugmask[Op_RegI]->SUBTRACT(save_mask); 621 idealreg2mhdebugmask[Op_RegL]->SUBTRACT(save_mask); 622 idealreg2mhdebugmask[Op_RegF]->SUBTRACT(save_mask); 623 idealreg2mhdebugmask[Op_RegD]->SUBTRACT(save_mask); 624 idealreg2mhdebugmask[Op_RegP]->SUBTRACT(save_mask); 625 } 626 627 //---------------------------is_save_on_entry---------------------------------- 628 bool Matcher::is_save_on_entry( int reg ) { 629 return 630 _register_save_policy[reg] == 'E' || 631 _register_save_policy[reg] == 'A' || // Save-on-entry register? 632 // Also save argument registers in the trampolining stubs 633 (C->save_argument_registers() && is_spillable_arg(reg)); 634 } 635 636 //---------------------------Fixup_Save_On_Entry------------------------------- 637 void Matcher::Fixup_Save_On_Entry( ) { 638 init_first_stack_mask(); 639 640 Node *root = C->root(); // Short name for root 641 // Count number of save-on-entry registers. 642 uint soe_cnt = number_of_saved_registers(); 643 uint i; 644 645 // Find the procedure Start Node 646 StartNode *start = C->start(); 647 assert( start, "Expect a start node" ); 648 649 // Save argument registers in the trampolining stubs 650 if( C->save_argument_registers() ) 651 for( i = 0; i < _last_Mach_Reg; i++ ) 652 if( is_spillable_arg(i) ) 653 soe_cnt++; 654 655 // Input RegMask array shared by all Returns. 656 // The type for doubles and longs has a count of 2, but 657 // there is only 1 returned value 658 uint ret_edge_cnt = TypeFunc::Parms + ((C->tf()->range()->cnt() == TypeFunc::Parms) ? 0 : 1); 659 RegMask *ret_rms = init_input_masks( ret_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask ); 660 // Returns have 0 or 1 returned values depending on call signature. 661 // Return register is specified by return_value in the AD file. 662 if (ret_edge_cnt > TypeFunc::Parms) 663 ret_rms[TypeFunc::Parms+0] = _return_value_mask; 664 665 // Input RegMask array shared by all Rethrows. 666 uint reth_edge_cnt = TypeFunc::Parms+1; 667 RegMask *reth_rms = init_input_masks( reth_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask ); 668 // Rethrow takes exception oop only, but in the argument 0 slot. 669 OptoReg::Name reg = find_receiver(false); 670 if (reg >= 0) { 671 reth_rms[TypeFunc::Parms] = mreg2regmask[reg]; 672 #ifdef _LP64 673 // Need two slots for ptrs in 64-bit land 674 reth_rms[TypeFunc::Parms].Insert(OptoReg::add(OptoReg::Name(reg), 1)); 675 #endif 676 } 677 678 // Input RegMask array shared by all TailCalls 679 uint tail_call_edge_cnt = TypeFunc::Parms+2; 680 RegMask *tail_call_rms = init_input_masks( tail_call_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask ); 681 682 // Input RegMask array shared by all TailJumps 683 uint tail_jump_edge_cnt = TypeFunc::Parms+2; 684 RegMask *tail_jump_rms = init_input_masks( tail_jump_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask ); 685 686 // TailCalls have 2 returned values (target & moop), whose masks come 687 // from the usual MachNode/MachOper mechanism. Find a sample 688 // TailCall to extract these masks and put the correct masks into 689 // the tail_call_rms array. 690 for( i=1; i < root->req(); i++ ) { 691 MachReturnNode *m = root->in(i)->as_MachReturn(); 692 if( m->ideal_Opcode() == Op_TailCall ) { 693 tail_call_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0); 694 tail_call_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1); 695 break; 696 } 697 } 698 699 // TailJumps have 2 returned values (target & ex_oop), whose masks come 700 // from the usual MachNode/MachOper mechanism. Find a sample 701 // TailJump to extract these masks and put the correct masks into 702 // the tail_jump_rms array. 703 for( i=1; i < root->req(); i++ ) { 704 MachReturnNode *m = root->in(i)->as_MachReturn(); 705 if( m->ideal_Opcode() == Op_TailJump ) { 706 tail_jump_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0); 707 tail_jump_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1); 708 break; 709 } 710 } 711 712 // Input RegMask array shared by all Halts 713 uint halt_edge_cnt = TypeFunc::Parms; 714 RegMask *halt_rms = init_input_masks( halt_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask ); 715 716 // Capture the return input masks into each exit flavor 717 for( i=1; i < root->req(); i++ ) { 718 MachReturnNode *exit = root->in(i)->as_MachReturn(); 719 switch( exit->ideal_Opcode() ) { 720 case Op_Return : exit->_in_rms = ret_rms; break; 721 case Op_Rethrow : exit->_in_rms = reth_rms; break; 722 case Op_TailCall : exit->_in_rms = tail_call_rms; break; 723 case Op_TailJump : exit->_in_rms = tail_jump_rms; break; 724 case Op_Halt : exit->_in_rms = halt_rms; break; 725 default : ShouldNotReachHere(); 726 } 727 } 728 729 // Next unused projection number from Start. 730 int proj_cnt = C->tf()->domain()->cnt(); 731 732 // Do all the save-on-entry registers. Make projections from Start for 733 // them, and give them a use at the exit points. To the allocator, they 734 // look like incoming register arguments. 735 for( i = 0; i < _last_Mach_Reg; i++ ) { 736 if( is_save_on_entry(i) ) { 737 738 // Add the save-on-entry to the mask array 739 ret_rms [ ret_edge_cnt] = mreg2regmask[i]; 740 reth_rms [ reth_edge_cnt] = mreg2regmask[i]; 741 tail_call_rms[tail_call_edge_cnt] = mreg2regmask[i]; 742 tail_jump_rms[tail_jump_edge_cnt] = mreg2regmask[i]; 743 // Halts need the SOE registers, but only in the stack as debug info. 744 // A just-prior uncommon-trap or deoptimization will use the SOE regs. 745 halt_rms [ halt_edge_cnt] = *idealreg2spillmask[_register_save_type[i]]; 746 747 Node *mproj; 748 749 // Is this a RegF low half of a RegD? Double up 2 adjacent RegF's 750 // into a single RegD. 751 if( (i&1) == 0 && 752 _register_save_type[i ] == Op_RegF && 753 _register_save_type[i+1] == Op_RegF && 754 is_save_on_entry(i+1) ) { 755 // Add other bit for double 756 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1)); 757 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1)); 758 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1)); 759 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1)); 760 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1)); 761 mproj = new MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegD ); 762 proj_cnt += 2; // Skip 2 for doubles 763 } 764 else if( (i&1) == 1 && // Else check for high half of double 765 _register_save_type[i-1] == Op_RegF && 766 _register_save_type[i ] == Op_RegF && 767 is_save_on_entry(i-1) ) { 768 ret_rms [ ret_edge_cnt] = RegMask::Empty; 769 reth_rms [ reth_edge_cnt] = RegMask::Empty; 770 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty; 771 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty; 772 halt_rms [ halt_edge_cnt] = RegMask::Empty; 773 mproj = C->top(); 774 } 775 // Is this a RegI low half of a RegL? Double up 2 adjacent RegI's 776 // into a single RegL. 777 else if( (i&1) == 0 && 778 _register_save_type[i ] == Op_RegI && 779 _register_save_type[i+1] == Op_RegI && 780 is_save_on_entry(i+1) ) { 781 // Add other bit for long 782 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1)); 783 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1)); 784 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1)); 785 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1)); 786 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1)); 787 mproj = new MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegL ); 788 proj_cnt += 2; // Skip 2 for longs 789 } 790 else if( (i&1) == 1 && // Else check for high half of long 791 _register_save_type[i-1] == Op_RegI && 792 _register_save_type[i ] == Op_RegI && 793 is_save_on_entry(i-1) ) { 794 ret_rms [ ret_edge_cnt] = RegMask::Empty; 795 reth_rms [ reth_edge_cnt] = RegMask::Empty; 796 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty; 797 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty; 798 halt_rms [ halt_edge_cnt] = RegMask::Empty; 799 mproj = C->top(); 800 } else { 801 // Make a projection for it off the Start 802 mproj = new MachProjNode( start, proj_cnt++, ret_rms[ret_edge_cnt], _register_save_type[i] ); 803 } 804 805 ret_edge_cnt ++; 806 reth_edge_cnt ++; 807 tail_call_edge_cnt ++; 808 tail_jump_edge_cnt ++; 809 halt_edge_cnt ++; 810 811 // Add a use of the SOE register to all exit paths 812 for( uint j=1; j < root->req(); j++ ) 813 root->in(j)->add_req(mproj); 814 } // End of if a save-on-entry register 815 } // End of for all machine registers 816 } 817 818 //------------------------------init_spill_mask-------------------------------- 819 void Matcher::init_spill_mask( Node *ret ) { 820 if( idealreg2regmask[Op_RegI] ) return; // One time only init 821 822 OptoReg::c_frame_pointer = c_frame_pointer(); 823 c_frame_ptr_mask = c_frame_pointer(); 824 #ifdef _LP64 825 // pointers are twice as big 826 c_frame_ptr_mask.Insert(OptoReg::add(c_frame_pointer(),1)); 827 #endif 828 829 // Start at OptoReg::stack0() 830 STACK_ONLY_mask.Clear(); 831 OptoReg::Name init = OptoReg::stack2reg(0); 832 // STACK_ONLY_mask is all stack bits 833 OptoReg::Name i; 834 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1)) 835 STACK_ONLY_mask.Insert(i); 836 // Also set the "infinite stack" bit. 837 STACK_ONLY_mask.set_AllStack(); 838 839 // Copy the register names over into the shared world 840 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) { 841 // SharedInfo::regName[i] = regName[i]; 842 // Handy RegMasks per machine register 843 mreg2regmask[i].Insert(i); 844 } 845 846 // Grab the Frame Pointer 847 Node *fp = ret->in(TypeFunc::FramePtr); 848 Node *mem = ret->in(TypeFunc::Memory); 849 const TypePtr* atp = TypePtr::BOTTOM; 850 // Share frame pointer while making spill ops 851 set_shared(fp); 852 853 // Compute generic short-offset Loads 854 #ifdef _LP64 855 MachNode *spillCP = match_tree(new LoadNNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM,MemNode::unordered)); 856 #endif 857 MachNode *spillI = match_tree(new LoadINode(NULL,mem,fp,atp,TypeInt::INT,MemNode::unordered)); 858 MachNode *spillL = match_tree(new LoadLNode(NULL,mem,fp,atp,TypeLong::LONG,MemNode::unordered, LoadNode::DependsOnlyOnTest, false)); 859 MachNode *spillF = match_tree(new LoadFNode(NULL,mem,fp,atp,Type::FLOAT,MemNode::unordered)); 860 MachNode *spillD = match_tree(new LoadDNode(NULL,mem,fp,atp,Type::DOUBLE,MemNode::unordered)); 861 MachNode *spillP = match_tree(new LoadPNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM,MemNode::unordered)); 862 assert(spillI != NULL && spillL != NULL && spillF != NULL && 863 spillD != NULL && spillP != NULL, ""); 864 // Get the ADLC notion of the right regmask, for each basic type. 865 #ifdef _LP64 866 idealreg2regmask[Op_RegN] = &spillCP->out_RegMask(); 867 #endif 868 idealreg2regmask[Op_RegI] = &spillI->out_RegMask(); 869 idealreg2regmask[Op_RegL] = &spillL->out_RegMask(); 870 idealreg2regmask[Op_RegF] = &spillF->out_RegMask(); 871 idealreg2regmask[Op_RegD] = &spillD->out_RegMask(); 872 idealreg2regmask[Op_RegP] = &spillP->out_RegMask(); 873 874 // Vector regmasks. 875 if (Matcher::vector_size_supported(T_BYTE,4)) { 876 TypeVect::VECTS = TypeVect::make(T_BYTE, 4); 877 MachNode *spillVectS = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTS)); 878 idealreg2regmask[Op_VecS] = &spillVectS->out_RegMask(); 879 } 880 if (Matcher::vector_size_supported(T_FLOAT,2)) { 881 MachNode *spillVectD = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTD)); 882 idealreg2regmask[Op_VecD] = &spillVectD->out_RegMask(); 883 } 884 if (Matcher::vector_size_supported(T_FLOAT,4)) { 885 MachNode *spillVectX = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTX)); 886 idealreg2regmask[Op_VecX] = &spillVectX->out_RegMask(); 887 } 888 if (Matcher::vector_size_supported(T_FLOAT,8)) { 889 MachNode *spillVectY = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTY)); 890 idealreg2regmask[Op_VecY] = &spillVectY->out_RegMask(); 891 } 892 if (Matcher::vector_size_supported(T_FLOAT,16)) { 893 MachNode *spillVectZ = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTZ)); 894 idealreg2regmask[Op_VecZ] = &spillVectZ->out_RegMask(); 895 } 896 } 897 898 #ifdef ASSERT 899 static void match_alias_type(Compile* C, Node* n, Node* m) { 900 if (!VerifyAliases) return; // do not go looking for trouble by default 901 const TypePtr* nat = n->adr_type(); 902 const TypePtr* mat = m->adr_type(); 903 int nidx = C->get_alias_index(nat); 904 int midx = C->get_alias_index(mat); 905 // Detune the assert for cases like (AndI 0xFF (LoadB p)). 906 if (nidx == Compile::AliasIdxTop && midx >= Compile::AliasIdxRaw) { 907 for (uint i = 1; i < n->req(); i++) { 908 Node* n1 = n->in(i); 909 const TypePtr* n1at = n1->adr_type(); 910 if (n1at != NULL) { 911 nat = n1at; 912 nidx = C->get_alias_index(n1at); 913 } 914 } 915 } 916 // %%% Kludgery. Instead, fix ideal adr_type methods for all these cases: 917 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxRaw) { 918 switch (n->Opcode()) { 919 case Op_PrefetchAllocation: 920 nidx = Compile::AliasIdxRaw; 921 nat = TypeRawPtr::BOTTOM; 922 break; 923 } 924 } 925 if (nidx == Compile::AliasIdxRaw && midx == Compile::AliasIdxTop) { 926 switch (n->Opcode()) { 927 case Op_ClearArray: 928 midx = Compile::AliasIdxRaw; 929 mat = TypeRawPtr::BOTTOM; 930 break; 931 } 932 } 933 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxBot) { 934 switch (n->Opcode()) { 935 case Op_Return: 936 case Op_Rethrow: 937 case Op_Halt: 938 case Op_TailCall: 939 case Op_TailJump: 940 nidx = Compile::AliasIdxBot; 941 nat = TypePtr::BOTTOM; 942 break; 943 } 944 } 945 if (nidx == Compile::AliasIdxBot && midx == Compile::AliasIdxTop) { 946 switch (n->Opcode()) { 947 case Op_StrComp: 948 case Op_StrEquals: 949 case Op_StrIndexOf: 950 case Op_StrIndexOfChar: 951 case Op_AryEq: 952 case Op_HasNegatives: 953 case Op_MemBarVolatile: 954 case Op_MemBarCPUOrder: // %%% these ideals should have narrower adr_type? 955 case Op_StrInflatedCopy: 956 case Op_StrCompressedCopy: 957 case Op_OnSpinWait: 958 case Op_EncodeISOArray: 959 nidx = Compile::AliasIdxTop; 960 nat = NULL; 961 break; 962 } 963 } 964 if (nidx != midx) { 965 if (PrintOpto || (PrintMiscellaneous && (WizardMode || Verbose))) { 966 tty->print_cr("==== Matcher alias shift %d => %d", nidx, midx); 967 n->dump(); 968 m->dump(); 969 } 970 assert(C->subsume_loads() && C->must_alias(nat, midx), 971 "must not lose alias info when matching"); 972 } 973 } 974 #endif 975 976 //------------------------------xform------------------------------------------ 977 // Given a Node in old-space, Match him (Label/Reduce) to produce a machine 978 // Node in new-space. Given a new-space Node, recursively walk his children. 979 Node *Matcher::transform( Node *n ) { ShouldNotCallThis(); return n; } 980 Node *Matcher::xform( Node *n, int max_stack ) { 981 // Use one stack to keep both: child's node/state and parent's node/index 982 MStack mstack(max_stack * 2 * 2); // usually: C->live_nodes() * 2 * 2 983 mstack.push(n, Visit, NULL, -1); // set NULL as parent to indicate root 984 while (mstack.is_nonempty()) { 985 C->check_node_count(NodeLimitFudgeFactor, "too many nodes matching instructions"); 986 if (C->failing()) return NULL; 987 n = mstack.node(); // Leave node on stack 988 Node_State nstate = mstack.state(); 989 if (nstate == Visit) { 990 mstack.set_state(Post_Visit); 991 Node *oldn = n; 992 // Old-space or new-space check 993 if (!C->node_arena()->contains(n)) { 994 // Old space! 995 Node* m; 996 if (has_new_node(n)) { // Not yet Label/Reduced 997 m = new_node(n); 998 } else { 999 if (!is_dontcare(n)) { // Matcher can match this guy 1000 // Calls match special. They match alone with no children. 1001 // Their children, the incoming arguments, match normally. 1002 m = n->is_SafePoint() ? match_sfpt(n->as_SafePoint()):match_tree(n); 1003 if (C->failing()) return NULL; 1004 if (m == NULL) { Matcher::soft_match_failure(); return NULL; } 1005 if (n->is_MemBar()) { 1006 m->as_MachMemBar()->set_adr_type(n->adr_type()); 1007 } 1008 } else { // Nothing the matcher cares about 1009 if (n->is_Proj() && n->in(0) != NULL && n->in(0)->is_Multi()) { // Projections? 1010 // Convert to machine-dependent projection 1011 m = n->in(0)->as_Multi()->match( n->as_Proj(), this ); 1012 #ifdef ASSERT 1013 _new2old_map.map(m->_idx, n); 1014 #endif 1015 if (m->in(0) != NULL) // m might be top 1016 collect_null_checks(m, n); 1017 } else { // Else just a regular 'ol guy 1018 m = n->clone(); // So just clone into new-space 1019 #ifdef ASSERT 1020 _new2old_map.map(m->_idx, n); 1021 #endif 1022 // Def-Use edges will be added incrementally as Uses 1023 // of this node are matched. 1024 assert(m->outcnt() == 0, "no Uses of this clone yet"); 1025 } 1026 } 1027 1028 set_new_node(n, m); // Map old to new 1029 if (_old_node_note_array != NULL) { 1030 Node_Notes* nn = C->locate_node_notes(_old_node_note_array, 1031 n->_idx); 1032 C->set_node_notes_at(m->_idx, nn); 1033 } 1034 debug_only(match_alias_type(C, n, m)); 1035 } 1036 n = m; // n is now a new-space node 1037 mstack.set_node(n); 1038 } 1039 1040 // New space! 1041 if (_visited.test_set(n->_idx)) continue; // while(mstack.is_nonempty()) 1042 1043 int i; 1044 // Put precedence edges on stack first (match them last). 1045 for (i = oldn->req(); (uint)i < oldn->len(); i++) { 1046 Node *m = oldn->in(i); 1047 if (m == NULL) break; 1048 // set -1 to call add_prec() instead of set_req() during Step1 1049 mstack.push(m, Visit, n, -1); 1050 } 1051 1052 // Handle precedence edges for interior nodes 1053 for (i = n->len()-1; (uint)i >= n->req(); i--) { 1054 Node *m = n->in(i); 1055 if (m == NULL || C->node_arena()->contains(m)) continue; 1056 n->rm_prec(i); 1057 // set -1 to call add_prec() instead of set_req() during Step1 1058 mstack.push(m, Visit, n, -1); 1059 } 1060 1061 // For constant debug info, I'd rather have unmatched constants. 1062 int cnt = n->req(); 1063 JVMState* jvms = n->jvms(); 1064 int debug_cnt = jvms ? jvms->debug_start() : cnt; 1065 1066 // Now do only debug info. Clone constants rather than matching. 1067 // Constants are represented directly in the debug info without 1068 // the need for executable machine instructions. 1069 // Monitor boxes are also represented directly. 1070 for (i = cnt - 1; i >= debug_cnt; --i) { // For all debug inputs do 1071 Node *m = n->in(i); // Get input 1072 int op = m->Opcode(); 1073 assert((op == Op_BoxLock) == jvms->is_monitor_use(i), "boxes only at monitor sites"); 1074 if( op == Op_ConI || op == Op_ConP || op == Op_ConN || op == Op_ConNKlass || 1075 op == Op_ConF || op == Op_ConD || op == Op_ConL 1076 // || op == Op_BoxLock // %%%% enable this and remove (+++) in chaitin.cpp 1077 ) { 1078 m = m->clone(); 1079 #ifdef ASSERT 1080 _new2old_map.map(m->_idx, n); 1081 #endif 1082 mstack.push(m, Post_Visit, n, i); // Don't need to visit 1083 mstack.push(m->in(0), Visit, m, 0); 1084 } else { 1085 mstack.push(m, Visit, n, i); 1086 } 1087 } 1088 1089 // And now walk his children, and convert his inputs to new-space. 1090 for( ; i >= 0; --i ) { // For all normal inputs do 1091 Node *m = n->in(i); // Get input 1092 if(m != NULL) 1093 mstack.push(m, Visit, n, i); 1094 } 1095 1096 } 1097 else if (nstate == Post_Visit) { 1098 // Set xformed input 1099 Node *p = mstack.parent(); 1100 if (p != NULL) { // root doesn't have parent 1101 int i = (int)mstack.index(); 1102 if (i >= 0) 1103 p->set_req(i, n); // required input 1104 else if (i == -1) 1105 p->add_prec(n); // precedence input 1106 else 1107 ShouldNotReachHere(); 1108 } 1109 mstack.pop(); // remove processed node from stack 1110 } 1111 else { 1112 ShouldNotReachHere(); 1113 } 1114 } // while (mstack.is_nonempty()) 1115 return n; // Return new-space Node 1116 } 1117 1118 //------------------------------warp_outgoing_stk_arg------------------------ 1119 OptoReg::Name Matcher::warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call ) { 1120 // Convert outgoing argument location to a pre-biased stack offset 1121 if (reg->is_stack()) { 1122 OptoReg::Name warped = reg->reg2stack(); 1123 // Adjust the stack slot offset to be the register number used 1124 // by the allocator. 1125 warped = OptoReg::add(begin_out_arg_area, warped); 1126 // Keep track of the largest numbered stack slot used for an arg. 1127 // Largest used slot per call-site indicates the amount of stack 1128 // that is killed by the call. 1129 if( warped >= out_arg_limit_per_call ) 1130 out_arg_limit_per_call = OptoReg::add(warped,1); 1131 if (!RegMask::can_represent_arg(warped)) { 1132 C->record_method_not_compilable("unsupported calling sequence"); 1133 return OptoReg::Bad; 1134 } 1135 return warped; 1136 } 1137 return OptoReg::as_OptoReg(reg); 1138 } 1139 1140 1141 //------------------------------match_sfpt------------------------------------- 1142 // Helper function to match call instructions. Calls match special. 1143 // They match alone with no children. Their children, the incoming 1144 // arguments, match normally. 1145 MachNode *Matcher::match_sfpt( SafePointNode *sfpt ) { 1146 MachSafePointNode *msfpt = NULL; 1147 MachCallNode *mcall = NULL; 1148 uint cnt; 1149 // Split out case for SafePoint vs Call 1150 CallNode *call; 1151 const TypeTuple *domain; 1152 ciMethod* method = NULL; 1153 bool is_method_handle_invoke = false; // for special kill effects 1154 if( sfpt->is_Call() ) { 1155 call = sfpt->as_Call(); 1156 domain = call->tf()->domain(); 1157 cnt = domain->cnt(); 1158 1159 // Match just the call, nothing else 1160 MachNode *m = match_tree(call); 1161 if (C->failing()) return NULL; 1162 if( m == NULL ) { Matcher::soft_match_failure(); return NULL; } 1163 1164 // Copy data from the Ideal SafePoint to the machine version 1165 mcall = m->as_MachCall(); 1166 1167 mcall->set_tf( call->tf()); 1168 mcall->set_entry_point(call->entry_point()); 1169 mcall->set_cnt( call->cnt()); 1170 1171 if( mcall->is_MachCallJava() ) { 1172 MachCallJavaNode *mcall_java = mcall->as_MachCallJava(); 1173 const CallJavaNode *call_java = call->as_CallJava(); 1174 method = call_java->method(); 1175 mcall_java->_method = method; 1176 mcall_java->_bci = call_java->_bci; 1177 mcall_java->_optimized_virtual = call_java->is_optimized_virtual(); 1178 is_method_handle_invoke = call_java->is_method_handle_invoke(); 1179 mcall_java->_method_handle_invoke = is_method_handle_invoke; 1180 mcall_java->_override_symbolic_info = call_java->override_symbolic_info(); 1181 if (is_method_handle_invoke) { 1182 C->set_has_method_handle_invokes(true); 1183 } 1184 if( mcall_java->is_MachCallStaticJava() ) 1185 mcall_java->as_MachCallStaticJava()->_name = 1186 call_java->as_CallStaticJava()->_name; 1187 if( mcall_java->is_MachCallDynamicJava() ) 1188 mcall_java->as_MachCallDynamicJava()->_vtable_index = 1189 call_java->as_CallDynamicJava()->_vtable_index; 1190 } 1191 else if( mcall->is_MachCallRuntime() ) { 1192 mcall->as_MachCallRuntime()->_name = call->as_CallRuntime()->_name; 1193 } 1194 msfpt = mcall; 1195 } 1196 // This is a non-call safepoint 1197 else { 1198 call = NULL; 1199 domain = NULL; 1200 MachNode *mn = match_tree(sfpt); 1201 if (C->failing()) return NULL; 1202 msfpt = mn->as_MachSafePoint(); 1203 cnt = TypeFunc::Parms; 1204 } 1205 1206 // Advertise the correct memory effects (for anti-dependence computation). 1207 msfpt->set_adr_type(sfpt->adr_type()); 1208 1209 // Allocate a private array of RegMasks. These RegMasks are not shared. 1210 msfpt->_in_rms = NEW_RESOURCE_ARRAY( RegMask, cnt ); 1211 // Empty them all. 1212 for (uint i = 0; i < cnt; i++) { 1213 msfpt->_in_rms[i] = RegMask(); 1214 } 1215 1216 // Do all the pre-defined non-Empty register masks 1217 msfpt->_in_rms[TypeFunc::ReturnAdr] = _return_addr_mask; 1218 msfpt->_in_rms[TypeFunc::FramePtr ] = c_frame_ptr_mask; 1219 1220 // Place first outgoing argument can possibly be put. 1221 OptoReg::Name begin_out_arg_area = OptoReg::add(_new_SP, C->out_preserve_stack_slots()); 1222 assert( is_even(begin_out_arg_area), "" ); 1223 // Compute max outgoing register number per call site. 1224 OptoReg::Name out_arg_limit_per_call = begin_out_arg_area; 1225 // Calls to C may hammer extra stack slots above and beyond any arguments. 1226 // These are usually backing store for register arguments for varargs. 1227 if( call != NULL && call->is_CallRuntime() ) 1228 out_arg_limit_per_call = OptoReg::add(out_arg_limit_per_call,C->varargs_C_out_slots_killed()); 1229 1230 1231 // Do the normal argument list (parameters) register masks 1232 int argcnt = cnt - TypeFunc::Parms; 1233 if( argcnt > 0 ) { // Skip it all if we have no args 1234 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt ); 1235 VMRegPair *parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt ); 1236 int i; 1237 for( i = 0; i < argcnt; i++ ) { 1238 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type(); 1239 } 1240 // V-call to pick proper calling convention 1241 call->calling_convention( sig_bt, parm_regs, argcnt ); 1242 1243 #ifdef ASSERT 1244 // Sanity check users' calling convention. Really handy during 1245 // the initial porting effort. Fairly expensive otherwise. 1246 { for (int i = 0; i<argcnt; i++) { 1247 if( !parm_regs[i].first()->is_valid() && 1248 !parm_regs[i].second()->is_valid() ) continue; 1249 VMReg reg1 = parm_regs[i].first(); 1250 VMReg reg2 = parm_regs[i].second(); 1251 for (int j = 0; j < i; j++) { 1252 if( !parm_regs[j].first()->is_valid() && 1253 !parm_regs[j].second()->is_valid() ) continue; 1254 VMReg reg3 = parm_regs[j].first(); 1255 VMReg reg4 = parm_regs[j].second(); 1256 if( !reg1->is_valid() ) { 1257 assert( !reg2->is_valid(), "valid halvsies" ); 1258 } else if( !reg3->is_valid() ) { 1259 assert( !reg4->is_valid(), "valid halvsies" ); 1260 } else { 1261 assert( reg1 != reg2, "calling conv. must produce distinct regs"); 1262 assert( reg1 != reg3, "calling conv. must produce distinct regs"); 1263 assert( reg1 != reg4, "calling conv. must produce distinct regs"); 1264 assert( reg2 != reg3, "calling conv. must produce distinct regs"); 1265 assert( reg2 != reg4 || !reg2->is_valid(), "calling conv. must produce distinct regs"); 1266 assert( reg3 != reg4, "calling conv. must produce distinct regs"); 1267 } 1268 } 1269 } 1270 } 1271 #endif 1272 1273 // Visit each argument. Compute its outgoing register mask. 1274 // Return results now can have 2 bits returned. 1275 // Compute max over all outgoing arguments both per call-site 1276 // and over the entire method. 1277 for( i = 0; i < argcnt; i++ ) { 1278 // Address of incoming argument mask to fill in 1279 RegMask *rm = &mcall->_in_rms[i+TypeFunc::Parms]; 1280 if( !parm_regs[i].first()->is_valid() && 1281 !parm_regs[i].second()->is_valid() ) { 1282 continue; // Avoid Halves 1283 } 1284 // Grab first register, adjust stack slots and insert in mask. 1285 OptoReg::Name reg1 = warp_outgoing_stk_arg(parm_regs[i].first(), begin_out_arg_area, out_arg_limit_per_call ); 1286 if (OptoReg::is_valid(reg1)) 1287 rm->Insert( reg1 ); 1288 // Grab second register (if any), adjust stack slots and insert in mask. 1289 OptoReg::Name reg2 = warp_outgoing_stk_arg(parm_regs[i].second(), begin_out_arg_area, out_arg_limit_per_call ); 1290 if (OptoReg::is_valid(reg2)) 1291 rm->Insert( reg2 ); 1292 } // End of for all arguments 1293 1294 // Compute number of stack slots needed to restore stack in case of 1295 // Pascal-style argument popping. 1296 mcall->_argsize = out_arg_limit_per_call - begin_out_arg_area; 1297 } 1298 1299 // Compute the max stack slot killed by any call. These will not be 1300 // available for debug info, and will be used to adjust FIRST_STACK_mask 1301 // after all call sites have been visited. 1302 if( _out_arg_limit < out_arg_limit_per_call) 1303 _out_arg_limit = out_arg_limit_per_call; 1304 1305 if (mcall) { 1306 // Kill the outgoing argument area, including any non-argument holes and 1307 // any legacy C-killed slots. Use Fat-Projections to do the killing. 1308 // Since the max-per-method covers the max-per-call-site and debug info 1309 // is excluded on the max-per-method basis, debug info cannot land in 1310 // this killed area. 1311 uint r_cnt = mcall->tf()->range()->cnt(); 1312 MachProjNode *proj = new MachProjNode( mcall, r_cnt+10000, RegMask::Empty, MachProjNode::fat_proj ); 1313 if (!RegMask::can_represent_arg(OptoReg::Name(out_arg_limit_per_call-1))) { 1314 C->record_method_not_compilable("unsupported outgoing calling sequence"); 1315 } else { 1316 for (int i = begin_out_arg_area; i < out_arg_limit_per_call; i++) 1317 proj->_rout.Insert(OptoReg::Name(i)); 1318 } 1319 if (proj->_rout.is_NotEmpty()) { 1320 push_projection(proj); 1321 } 1322 } 1323 // Transfer the safepoint information from the call to the mcall 1324 // Move the JVMState list 1325 msfpt->set_jvms(sfpt->jvms()); 1326 for (JVMState* jvms = msfpt->jvms(); jvms; jvms = jvms->caller()) { 1327 jvms->set_map(sfpt); 1328 } 1329 1330 // Debug inputs begin just after the last incoming parameter 1331 assert((mcall == NULL) || (mcall->jvms() == NULL) || 1332 (mcall->jvms()->debug_start() + mcall->_jvmadj == mcall->tf()->domain()->cnt()), ""); 1333 1334 // Move the OopMap 1335 msfpt->_oop_map = sfpt->_oop_map; 1336 1337 // Add additional edges. 1338 if (msfpt->mach_constant_base_node_input() != (uint)-1 && !msfpt->is_MachCallLeaf()) { 1339 // For these calls we can not add MachConstantBase in expand(), as the 1340 // ins are not complete then. 1341 msfpt->ins_req(msfpt->mach_constant_base_node_input(), C->mach_constant_base_node()); 1342 if (msfpt->jvms() && 1343 msfpt->mach_constant_base_node_input() <= msfpt->jvms()->debug_start() + msfpt->_jvmadj) { 1344 // We added an edge before jvms, so we must adapt the position of the ins. 1345 msfpt->jvms()->adapt_position(+1); 1346 } 1347 } 1348 1349 // Registers killed by the call are set in the local scheduling pass 1350 // of Global Code Motion. 1351 return msfpt; 1352 } 1353 1354 //---------------------------match_tree---------------------------------------- 1355 // Match a Ideal Node DAG - turn it into a tree; Label & Reduce. Used as part 1356 // of the whole-sale conversion from Ideal to Mach Nodes. Also used for 1357 // making GotoNodes while building the CFG and in init_spill_mask() to identify 1358 // a Load's result RegMask for memoization in idealreg2regmask[] 1359 MachNode *Matcher::match_tree( const Node *n ) { 1360 assert( n->Opcode() != Op_Phi, "cannot match" ); 1361 assert( !n->is_block_start(), "cannot match" ); 1362 // Set the mark for all locally allocated State objects. 1363 // When this call returns, the _states_arena arena will be reset 1364 // freeing all State objects. 1365 ResourceMark rm( &_states_arena ); 1366 1367 LabelRootDepth = 0; 1368 1369 // StoreNodes require their Memory input to match any LoadNodes 1370 Node *mem = n->is_Store() ? n->in(MemNode::Memory) : (Node*)1 ; 1371 #ifdef ASSERT 1372 Node* save_mem_node = _mem_node; 1373 _mem_node = n->is_Store() ? (Node*)n : NULL; 1374 #endif 1375 // State object for root node of match tree 1376 // Allocate it on _states_arena - stack allocation can cause stack overflow. 1377 State *s = new (&_states_arena) State; 1378 s->_kids[0] = NULL; 1379 s->_kids[1] = NULL; 1380 s->_leaf = (Node*)n; 1381 // Label the input tree, allocating labels from top-level arena 1382 Label_Root( n, s, n->in(0), mem ); 1383 if (C->failing()) return NULL; 1384 1385 // The minimum cost match for the whole tree is found at the root State 1386 uint mincost = max_juint; 1387 uint cost = max_juint; 1388 uint i; 1389 for( i = 0; i < NUM_OPERANDS; i++ ) { 1390 if( s->valid(i) && // valid entry and 1391 s->_cost[i] < cost && // low cost and 1392 s->_rule[i] >= NUM_OPERANDS ) // not an operand 1393 cost = s->_cost[mincost=i]; 1394 } 1395 if (mincost == max_juint) { 1396 #ifndef PRODUCT 1397 tty->print("No matching rule for:"); 1398 s->dump(); 1399 #endif 1400 Matcher::soft_match_failure(); 1401 return NULL; 1402 } 1403 // Reduce input tree based upon the state labels to machine Nodes 1404 MachNode *m = ReduceInst( s, s->_rule[mincost], mem ); 1405 #ifdef ASSERT 1406 _old2new_map.map(n->_idx, m); 1407 _new2old_map.map(m->_idx, (Node*)n); 1408 #endif 1409 1410 // Add any Matcher-ignored edges 1411 uint cnt = n->req(); 1412 uint start = 1; 1413 if( mem != (Node*)1 ) start = MemNode::Memory+1; 1414 if( n->is_AddP() ) { 1415 assert( mem == (Node*)1, "" ); 1416 start = AddPNode::Base+1; 1417 } 1418 for( i = start; i < cnt; i++ ) { 1419 if( !n->match_edge(i) ) { 1420 if( i < m->req() ) 1421 m->ins_req( i, n->in(i) ); 1422 else 1423 m->add_req( n->in(i) ); 1424 } 1425 } 1426 1427 debug_only( _mem_node = save_mem_node; ) 1428 return m; 1429 } 1430 1431 1432 //------------------------------match_into_reg--------------------------------- 1433 // Choose to either match this Node in a register or part of the current 1434 // match tree. Return true for requiring a register and false for matching 1435 // as part of the current match tree. 1436 static bool match_into_reg( const Node *n, Node *m, Node *control, int i, bool shared ) { 1437 1438 const Type *t = m->bottom_type(); 1439 1440 if (t->singleton()) { 1441 // Never force constants into registers. Allow them to match as 1442 // constants or registers. Copies of the same value will share 1443 // the same register. See find_shared_node. 1444 return false; 1445 } else { // Not a constant 1446 // Stop recursion if they have different Controls. 1447 Node* m_control = m->in(0); 1448 // Control of load's memory can post-dominates load's control. 1449 // So use it since load can't float above its memory. 1450 Node* mem_control = (m->is_Load()) ? m->in(MemNode::Memory)->in(0) : NULL; 1451 if (control && m_control && control != m_control && control != mem_control) { 1452 1453 // Actually, we can live with the most conservative control we 1454 // find, if it post-dominates the others. This allows us to 1455 // pick up load/op/store trees where the load can float a little 1456 // above the store. 1457 Node *x = control; 1458 const uint max_scan = 6; // Arbitrary scan cutoff 1459 uint j; 1460 for (j=0; j<max_scan; j++) { 1461 if (x->is_Region()) // Bail out at merge points 1462 return true; 1463 x = x->in(0); 1464 if (x == m_control) // Does 'control' post-dominate 1465 break; // m->in(0)? If so, we can use it 1466 if (x == mem_control) // Does 'control' post-dominate 1467 break; // mem_control? If so, we can use it 1468 } 1469 if (j == max_scan) // No post-domination before scan end? 1470 return true; // Then break the match tree up 1471 } 1472 if ((m->is_DecodeN() && Matcher::narrow_oop_use_complex_address()) || 1473 (m->is_DecodeNKlass() && Matcher::narrow_klass_use_complex_address())) { 1474 // These are commonly used in address expressions and can 1475 // efficiently fold into them on X64 in some cases. 1476 return false; 1477 } 1478 } 1479 1480 // Not forceable cloning. If shared, put it into a register. 1481 return shared; 1482 } 1483 1484 1485 //------------------------------Instruction Selection-------------------------- 1486 // Label method walks a "tree" of nodes, using the ADLC generated DFA to match 1487 // ideal nodes to machine instructions. Trees are delimited by shared Nodes, 1488 // things the Matcher does not match (e.g., Memory), and things with different 1489 // Controls (hence forced into different blocks). We pass in the Control 1490 // selected for this entire State tree. 1491 1492 // The Matcher works on Trees, but an Intel add-to-memory requires a DAG: the 1493 // Store and the Load must have identical Memories (as well as identical 1494 // pointers). Since the Matcher does not have anything for Memory (and 1495 // does not handle DAGs), I have to match the Memory input myself. If the 1496 // Tree root is a Store, I require all Loads to have the identical memory. 1497 Node *Matcher::Label_Root( const Node *n, State *svec, Node *control, const Node *mem){ 1498 // Since Label_Root is a recursive function, its possible that we might run 1499 // out of stack space. See bugs 6272980 & 6227033 for more info. 1500 LabelRootDepth++; 1501 if (LabelRootDepth > MaxLabelRootDepth) { 1502 C->record_method_not_compilable("Out of stack space, increase MaxLabelRootDepth"); 1503 return NULL; 1504 } 1505 uint care = 0; // Edges matcher cares about 1506 uint cnt = n->req(); 1507 uint i = 0; 1508 1509 // Examine children for memory state 1510 // Can only subsume a child into your match-tree if that child's memory state 1511 // is not modified along the path to another input. 1512 // It is unsafe even if the other inputs are separate roots. 1513 Node *input_mem = NULL; 1514 for( i = 1; i < cnt; i++ ) { 1515 if( !n->match_edge(i) ) continue; 1516 Node *m = n->in(i); // Get ith input 1517 assert( m, "expect non-null children" ); 1518 if( m->is_Load() ) { 1519 if( input_mem == NULL ) { 1520 input_mem = m->in(MemNode::Memory); 1521 } else if( input_mem != m->in(MemNode::Memory) ) { 1522 input_mem = NodeSentinel; 1523 } 1524 } 1525 } 1526 1527 for( i = 1; i < cnt; i++ ){// For my children 1528 if( !n->match_edge(i) ) continue; 1529 Node *m = n->in(i); // Get ith input 1530 // Allocate states out of a private arena 1531 State *s = new (&_states_arena) State; 1532 svec->_kids[care++] = s; 1533 assert( care <= 2, "binary only for now" ); 1534 1535 // Recursively label the State tree. 1536 s->_kids[0] = NULL; 1537 s->_kids[1] = NULL; 1538 s->_leaf = m; 1539 1540 // Check for leaves of the State Tree; things that cannot be a part of 1541 // the current tree. If it finds any, that value is matched as a 1542 // register operand. If not, then the normal matching is used. 1543 if( match_into_reg(n, m, control, i, is_shared(m)) || 1544 // 1545 // Stop recursion if this is LoadNode and the root of this tree is a 1546 // StoreNode and the load & store have different memories. 1547 ((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) || 1548 // Can NOT include the match of a subtree when its memory state 1549 // is used by any of the other subtrees 1550 (input_mem == NodeSentinel) ) { 1551 // Print when we exclude matching due to different memory states at input-loads 1552 if (PrintOpto && (Verbose && WizardMode) && (input_mem == NodeSentinel) 1553 && !((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem)) { 1554 tty->print_cr("invalid input_mem"); 1555 } 1556 // Switch to a register-only opcode; this value must be in a register 1557 // and cannot be subsumed as part of a larger instruction. 1558 s->DFA( m->ideal_reg(), m ); 1559 1560 } else { 1561 // If match tree has no control and we do, adopt it for entire tree 1562 if( control == NULL && m->in(0) != NULL && m->req() > 1 ) 1563 control = m->in(0); // Pick up control 1564 // Else match as a normal part of the match tree. 1565 control = Label_Root(m,s,control,mem); 1566 if (C->failing()) return NULL; 1567 } 1568 } 1569 1570 1571 // Call DFA to match this node, and return 1572 svec->DFA( n->Opcode(), n ); 1573 1574 #ifdef ASSERT 1575 uint x; 1576 for( x = 0; x < _LAST_MACH_OPER; x++ ) 1577 if( svec->valid(x) ) 1578 break; 1579 1580 if (x >= _LAST_MACH_OPER) { 1581 n->dump(); 1582 svec->dump(); 1583 assert( false, "bad AD file" ); 1584 } 1585 #endif 1586 return control; 1587 } 1588 1589 1590 // Con nodes reduced using the same rule can share their MachNode 1591 // which reduces the number of copies of a constant in the final 1592 // program. The register allocator is free to split uses later to 1593 // split live ranges. 1594 MachNode* Matcher::find_shared_node(Node* leaf, uint rule) { 1595 if (!leaf->is_Con() && !leaf->is_DecodeNarrowPtr()) return NULL; 1596 1597 // See if this Con has already been reduced using this rule. 1598 if (_shared_nodes.Size() <= leaf->_idx) return NULL; 1599 MachNode* last = (MachNode*)_shared_nodes.at(leaf->_idx); 1600 if (last != NULL && rule == last->rule()) { 1601 // Don't expect control change for DecodeN 1602 if (leaf->is_DecodeNarrowPtr()) 1603 return last; 1604 // Get the new space root. 1605 Node* xroot = new_node(C->root()); 1606 if (xroot == NULL) { 1607 // This shouldn't happen give the order of matching. 1608 return NULL; 1609 } 1610 1611 // Shared constants need to have their control be root so they 1612 // can be scheduled properly. 1613 Node* control = last->in(0); 1614 if (control != xroot) { 1615 if (control == NULL || control == C->root()) { 1616 last->set_req(0, xroot); 1617 } else { 1618 assert(false, "unexpected control"); 1619 return NULL; 1620 } 1621 } 1622 return last; 1623 } 1624 return NULL; 1625 } 1626 1627 1628 //------------------------------ReduceInst------------------------------------- 1629 // Reduce a State tree (with given Control) into a tree of MachNodes. 1630 // This routine (and it's cohort ReduceOper) convert Ideal Nodes into 1631 // complicated machine Nodes. Each MachNode covers some tree of Ideal Nodes. 1632 // Each MachNode has a number of complicated MachOper operands; each 1633 // MachOper also covers a further tree of Ideal Nodes. 1634 1635 // The root of the Ideal match tree is always an instruction, so we enter 1636 // the recursion here. After building the MachNode, we need to recurse 1637 // the tree checking for these cases: 1638 // (1) Child is an instruction - 1639 // Build the instruction (recursively), add it as an edge. 1640 // Build a simple operand (register) to hold the result of the instruction. 1641 // (2) Child is an interior part of an instruction - 1642 // Skip over it (do nothing) 1643 // (3) Child is the start of a operand - 1644 // Build the operand, place it inside the instruction 1645 // Call ReduceOper. 1646 MachNode *Matcher::ReduceInst( State *s, int rule, Node *&mem ) { 1647 assert( rule >= NUM_OPERANDS, "called with operand rule" ); 1648 1649 MachNode* shared_node = find_shared_node(s->_leaf, rule); 1650 if (shared_node != NULL) { 1651 return shared_node; 1652 } 1653 1654 // Build the object to represent this state & prepare for recursive calls 1655 MachNode *mach = s->MachNodeGenerator(rule); 1656 guarantee(mach != NULL, "Missing MachNode"); 1657 mach->_opnds[0] = s->MachOperGenerator(_reduceOp[rule]); 1658 assert( mach->_opnds[0] != NULL, "Missing result operand" ); 1659 Node *leaf = s->_leaf; 1660 // Check for instruction or instruction chain rule 1661 if( rule >= _END_INST_CHAIN_RULE || rule < _BEGIN_INST_CHAIN_RULE ) { 1662 assert(C->node_arena()->contains(s->_leaf) || !has_new_node(s->_leaf), 1663 "duplicating node that's already been matched"); 1664 // Instruction 1665 mach->add_req( leaf->in(0) ); // Set initial control 1666 // Reduce interior of complex instruction 1667 ReduceInst_Interior( s, rule, mem, mach, 1 ); 1668 } else { 1669 // Instruction chain rules are data-dependent on their inputs 1670 mach->add_req(0); // Set initial control to none 1671 ReduceInst_Chain_Rule( s, rule, mem, mach ); 1672 } 1673 1674 // If a Memory was used, insert a Memory edge 1675 if( mem != (Node*)1 ) { 1676 mach->ins_req(MemNode::Memory,mem); 1677 #ifdef ASSERT 1678 // Verify adr type after matching memory operation 1679 const MachOper* oper = mach->memory_operand(); 1680 if (oper != NULL && oper != (MachOper*)-1) { 1681 // It has a unique memory operand. Find corresponding ideal mem node. 1682 Node* m = NULL; 1683 if (leaf->is_Mem()) { 1684 m = leaf; 1685 } else { 1686 m = _mem_node; 1687 assert(m != NULL && m->is_Mem(), "expecting memory node"); 1688 } 1689 const Type* mach_at = mach->adr_type(); 1690 // DecodeN node consumed by an address may have different type 1691 // than its input. Don't compare types for such case. 1692 if (m->adr_type() != mach_at && 1693 (m->in(MemNode::Address)->is_DecodeNarrowPtr() || 1694 (m->in(MemNode::Address)->is_AddP() && 1695 m->in(MemNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr()) || 1696 (m->in(MemNode::Address)->is_AddP() && 1697 m->in(MemNode::Address)->in(AddPNode::Address)->is_AddP() && 1698 m->in(MemNode::Address)->in(AddPNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr()))) { 1699 mach_at = m->adr_type(); 1700 } 1701 if (m->adr_type() != mach_at) { 1702 m->dump(); 1703 tty->print_cr("mach:"); 1704 mach->dump(1); 1705 } 1706 assert(m->adr_type() == mach_at, "matcher should not change adr type"); 1707 } 1708 #endif 1709 } 1710 1711 // If the _leaf is an AddP, insert the base edge 1712 if (leaf->is_AddP()) { 1713 mach->ins_req(AddPNode::Base,leaf->in(AddPNode::Base)); 1714 } 1715 1716 uint number_of_projections_prior = number_of_projections(); 1717 1718 // Perform any 1-to-many expansions required 1719 MachNode *ex = mach->Expand(s, _projection_list, mem); 1720 if (ex != mach) { 1721 assert(ex->ideal_reg() == mach->ideal_reg(), "ideal types should match"); 1722 if( ex->in(1)->is_Con() ) 1723 ex->in(1)->set_req(0, C->root()); 1724 // Remove old node from the graph 1725 for( uint i=0; i<mach->req(); i++ ) { 1726 mach->set_req(i,NULL); 1727 } 1728 #ifdef ASSERT 1729 _new2old_map.map(ex->_idx, s->_leaf); 1730 #endif 1731 } 1732 1733 // PhaseChaitin::fixup_spills will sometimes generate spill code 1734 // via the matcher. By the time, nodes have been wired into the CFG, 1735 // and any further nodes generated by expand rules will be left hanging 1736 // in space, and will not get emitted as output code. Catch this. 1737 // Also, catch any new register allocation constraints ("projections") 1738 // generated belatedly during spill code generation. 1739 if (_allocation_started) { 1740 guarantee(ex == mach, "no expand rules during spill generation"); 1741 guarantee(number_of_projections_prior == number_of_projections(), "no allocation during spill generation"); 1742 } 1743 1744 if (leaf->is_Con() || leaf->is_DecodeNarrowPtr()) { 1745 // Record the con for sharing 1746 _shared_nodes.map(leaf->_idx, ex); 1747 } 1748 1749 return ex; 1750 } 1751 1752 void Matcher::handle_precedence_edges(Node* n, MachNode *mach) { 1753 for (uint i = n->req(); i < n->len(); i++) { 1754 if (n->in(i) != NULL) { 1755 mach->add_prec(n->in(i)); 1756 } 1757 } 1758 } 1759 1760 void Matcher::ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach ) { 1761 // 'op' is what I am expecting to receive 1762 int op = _leftOp[rule]; 1763 // Operand type to catch childs result 1764 // This is what my child will give me. 1765 int opnd_class_instance = s->_rule[op]; 1766 // Choose between operand class or not. 1767 // This is what I will receive. 1768 int catch_op = (FIRST_OPERAND_CLASS <= op && op < NUM_OPERANDS) ? opnd_class_instance : op; 1769 // New rule for child. Chase operand classes to get the actual rule. 1770 int newrule = s->_rule[catch_op]; 1771 1772 if( newrule < NUM_OPERANDS ) { 1773 // Chain from operand or operand class, may be output of shared node 1774 assert( 0 <= opnd_class_instance && opnd_class_instance < NUM_OPERANDS, 1775 "Bad AD file: Instruction chain rule must chain from operand"); 1776 // Insert operand into array of operands for this instruction 1777 mach->_opnds[1] = s->MachOperGenerator(opnd_class_instance); 1778 1779 ReduceOper( s, newrule, mem, mach ); 1780 } else { 1781 // Chain from the result of an instruction 1782 assert( newrule >= _LAST_MACH_OPER, "Do NOT chain from internal operand"); 1783 mach->_opnds[1] = s->MachOperGenerator(_reduceOp[catch_op]); 1784 Node *mem1 = (Node*)1; 1785 debug_only(Node *save_mem_node = _mem_node;) 1786 mach->add_req( ReduceInst(s, newrule, mem1) ); 1787 debug_only(_mem_node = save_mem_node;) 1788 } 1789 return; 1790 } 1791 1792 1793 uint Matcher::ReduceInst_Interior( State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds ) { 1794 handle_precedence_edges(s->_leaf, mach); 1795 1796 if( s->_leaf->is_Load() ) { 1797 Node *mem2 = s->_leaf->in(MemNode::Memory); 1798 assert( mem == (Node*)1 || mem == mem2, "multiple Memories being matched at once?" ); 1799 debug_only( if( mem == (Node*)1 ) _mem_node = s->_leaf;) 1800 mem = mem2; 1801 } 1802 if( s->_leaf->in(0) != NULL && s->_leaf->req() > 1) { 1803 if( mach->in(0) == NULL ) 1804 mach->set_req(0, s->_leaf->in(0)); 1805 } 1806 1807 // Now recursively walk the state tree & add operand list. 1808 for( uint i=0; i<2; i++ ) { // binary tree 1809 State *newstate = s->_kids[i]; 1810 if( newstate == NULL ) break; // Might only have 1 child 1811 // 'op' is what I am expecting to receive 1812 int op; 1813 if( i == 0 ) { 1814 op = _leftOp[rule]; 1815 } else { 1816 op = _rightOp[rule]; 1817 } 1818 // Operand type to catch childs result 1819 // This is what my child will give me. 1820 int opnd_class_instance = newstate->_rule[op]; 1821 // Choose between operand class or not. 1822 // This is what I will receive. 1823 int catch_op = (op >= FIRST_OPERAND_CLASS && op < NUM_OPERANDS) ? opnd_class_instance : op; 1824 // New rule for child. Chase operand classes to get the actual rule. 1825 int newrule = newstate->_rule[catch_op]; 1826 1827 if( newrule < NUM_OPERANDS ) { // Operand/operandClass or internalOp/instruction? 1828 // Operand/operandClass 1829 // Insert operand into array of operands for this instruction 1830 mach->_opnds[num_opnds++] = newstate->MachOperGenerator(opnd_class_instance); 1831 ReduceOper( newstate, newrule, mem, mach ); 1832 1833 } else { // Child is internal operand or new instruction 1834 if( newrule < _LAST_MACH_OPER ) { // internal operand or instruction? 1835 // internal operand --> call ReduceInst_Interior 1836 // Interior of complex instruction. Do nothing but recurse. 1837 num_opnds = ReduceInst_Interior( newstate, newrule, mem, mach, num_opnds ); 1838 } else { 1839 // instruction --> call build operand( ) to catch result 1840 // --> ReduceInst( newrule ) 1841 mach->_opnds[num_opnds++] = s->MachOperGenerator(_reduceOp[catch_op]); 1842 Node *mem1 = (Node*)1; 1843 debug_only(Node *save_mem_node = _mem_node;) 1844 mach->add_req( ReduceInst( newstate, newrule, mem1 ) ); 1845 debug_only(_mem_node = save_mem_node;) 1846 } 1847 } 1848 assert( mach->_opnds[num_opnds-1], "" ); 1849 } 1850 return num_opnds; 1851 } 1852 1853 // This routine walks the interior of possible complex operands. 1854 // At each point we check our children in the match tree: 1855 // (1) No children - 1856 // We are a leaf; add _leaf field as an input to the MachNode 1857 // (2) Child is an internal operand - 1858 // Skip over it ( do nothing ) 1859 // (3) Child is an instruction - 1860 // Call ReduceInst recursively and 1861 // and instruction as an input to the MachNode 1862 void Matcher::ReduceOper( State *s, int rule, Node *&mem, MachNode *mach ) { 1863 assert( rule < _LAST_MACH_OPER, "called with operand rule" ); 1864 State *kid = s->_kids[0]; 1865 assert( kid == NULL || s->_leaf->in(0) == NULL, "internal operands have no control" ); 1866 1867 // Leaf? And not subsumed? 1868 if( kid == NULL && !_swallowed[rule] ) { 1869 mach->add_req( s->_leaf ); // Add leaf pointer 1870 return; // Bail out 1871 } 1872 1873 if( s->_leaf->is_Load() ) { 1874 assert( mem == (Node*)1, "multiple Memories being matched at once?" ); 1875 mem = s->_leaf->in(MemNode::Memory); 1876 debug_only(_mem_node = s->_leaf;) 1877 } 1878 1879 handle_precedence_edges(s->_leaf, mach); 1880 1881 if( s->_leaf->in(0) && s->_leaf->req() > 1) { 1882 if( !mach->in(0) ) 1883 mach->set_req(0,s->_leaf->in(0)); 1884 else { 1885 assert( s->_leaf->in(0) == mach->in(0), "same instruction, differing controls?" ); 1886 } 1887 } 1888 1889 for( uint i=0; kid != NULL && i<2; kid = s->_kids[1], i++ ) { // binary tree 1890 int newrule; 1891 if( i == 0) 1892 newrule = kid->_rule[_leftOp[rule]]; 1893 else 1894 newrule = kid->_rule[_rightOp[rule]]; 1895 1896 if( newrule < _LAST_MACH_OPER ) { // Operand or instruction? 1897 // Internal operand; recurse but do nothing else 1898 ReduceOper( kid, newrule, mem, mach ); 1899 1900 } else { // Child is a new instruction 1901 // Reduce the instruction, and add a direct pointer from this 1902 // machine instruction to the newly reduced one. 1903 Node *mem1 = (Node*)1; 1904 debug_only(Node *save_mem_node = _mem_node;) 1905 mach->add_req( ReduceInst( kid, newrule, mem1 ) ); 1906 debug_only(_mem_node = save_mem_node;) 1907 } 1908 } 1909 } 1910 1911 1912 // ------------------------------------------------------------------------- 1913 // Java-Java calling convention 1914 // (what you use when Java calls Java) 1915 1916 //------------------------------find_receiver---------------------------------- 1917 // For a given signature, return the OptoReg for parameter 0. 1918 OptoReg::Name Matcher::find_receiver( bool is_outgoing ) { 1919 VMRegPair regs; 1920 BasicType sig_bt = T_OBJECT; 1921 calling_convention(&sig_bt, ®s, 1, is_outgoing); 1922 // Return argument 0 register. In the LP64 build pointers 1923 // take 2 registers, but the VM wants only the 'main' name. 1924 return OptoReg::as_OptoReg(regs.first()); 1925 } 1926 1927 // This function identifies sub-graphs in which a 'load' node is 1928 // input to two different nodes, and such that it can be matched 1929 // with BMI instructions like blsi, blsr, etc. 1930 // Example : for b = -a[i] & a[i] can be matched to blsi r32, m32. 1931 // The graph is (AndL (SubL Con0 LoadL*) LoadL*), where LoadL* 1932 // refers to the same node. 1933 #ifdef X86 1934 // Match the generic fused operations pattern (op1 (op2 Con{ConType} mop) mop) 1935 // This is a temporary solution until we make DAGs expressible in ADL. 1936 template<typename ConType> 1937 class FusedPatternMatcher { 1938 Node* _op1_node; 1939 Node* _mop_node; 1940 int _con_op; 1941 1942 static int match_next(Node* n, int next_op, int next_op_idx) { 1943 if (n->in(1) == NULL || n->in(2) == NULL) { 1944 return -1; 1945 } 1946 1947 if (next_op_idx == -1) { // n is commutative, try rotations 1948 if (n->in(1)->Opcode() == next_op) { 1949 return 1; 1950 } else if (n->in(2)->Opcode() == next_op) { 1951 return 2; 1952 } 1953 } else { 1954 assert(next_op_idx > 0 && next_op_idx <= 2, "Bad argument index"); 1955 if (n->in(next_op_idx)->Opcode() == next_op) { 1956 return next_op_idx; 1957 } 1958 } 1959 return -1; 1960 } 1961 public: 1962 FusedPatternMatcher(Node* op1_node, Node *mop_node, int con_op) : 1963 _op1_node(op1_node), _mop_node(mop_node), _con_op(con_op) { } 1964 1965 bool match(int op1, int op1_op2_idx, // op1 and the index of the op1->op2 edge, -1 if op1 is commutative 1966 int op2, int op2_con_idx, // op2 and the index of the op2->con edge, -1 if op2 is commutative 1967 typename ConType::NativeType con_value) { 1968 if (_op1_node->Opcode() != op1) { 1969 return false; 1970 } 1971 if (_mop_node->outcnt() > 2) { 1972 return false; 1973 } 1974 op1_op2_idx = match_next(_op1_node, op2, op1_op2_idx); 1975 if (op1_op2_idx == -1) { 1976 return false; 1977 } 1978 // Memory operation must be the other edge 1979 int op1_mop_idx = (op1_op2_idx & 1) + 1; 1980 1981 // Check that the mop node is really what we want 1982 if (_op1_node->in(op1_mop_idx) == _mop_node) { 1983 Node *op2_node = _op1_node->in(op1_op2_idx); 1984 if (op2_node->outcnt() > 1) { 1985 return false; 1986 } 1987 assert(op2_node->Opcode() == op2, "Should be"); 1988 op2_con_idx = match_next(op2_node, _con_op, op2_con_idx); 1989 if (op2_con_idx == -1) { 1990 return false; 1991 } 1992 // Memory operation must be the other edge 1993 int op2_mop_idx = (op2_con_idx & 1) + 1; 1994 // Check that the memory operation is the same node 1995 if (op2_node->in(op2_mop_idx) == _mop_node) { 1996 // Now check the constant 1997 const Type* con_type = op2_node->in(op2_con_idx)->bottom_type(); 1998 if (con_type != Type::TOP && ConType::as_self(con_type)->get_con() == con_value) { 1999 return true; 2000 } 2001 } 2002 } 2003 return false; 2004 } 2005 }; 2006 2007 2008 bool Matcher::is_bmi_pattern(Node *n, Node *m) { 2009 if (n != NULL && m != NULL) { 2010 if (m->Opcode() == Op_LoadI) { 2011 FusedPatternMatcher<TypeInt> bmii(n, m, Op_ConI); 2012 return bmii.match(Op_AndI, -1, Op_SubI, 1, 0) || 2013 bmii.match(Op_AndI, -1, Op_AddI, -1, -1) || 2014 bmii.match(Op_XorI, -1, Op_AddI, -1, -1); 2015 } else if (m->Opcode() == Op_LoadL) { 2016 FusedPatternMatcher<TypeLong> bmil(n, m, Op_ConL); 2017 return bmil.match(Op_AndL, -1, Op_SubL, 1, 0) || 2018 bmil.match(Op_AndL, -1, Op_AddL, -1, -1) || 2019 bmil.match(Op_XorL, -1, Op_AddL, -1, -1); 2020 } 2021 } 2022 return false; 2023 } 2024 #endif // X86 2025 2026 bool Matcher::clone_base_plus_offset_address(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) { 2027 Node *off = m->in(AddPNode::Offset); 2028 if (off->is_Con()) { 2029 address_visited.test_set(m->_idx); // Flag as address_visited 2030 mstack.push(m->in(AddPNode::Address), Pre_Visit); 2031 // Clone X+offset as it also folds into most addressing expressions 2032 mstack.push(off, Visit); 2033 mstack.push(m->in(AddPNode::Base), Pre_Visit); 2034 return true; 2035 } 2036 return false; 2037 } 2038 2039 // A method-klass-holder may be passed in the inline_cache_reg 2040 // and then expanded into the inline_cache_reg and a method_oop register 2041 // defined in ad_<arch>.cpp 2042 2043 //------------------------------find_shared------------------------------------ 2044 // Set bits if Node is shared or otherwise a root 2045 void Matcher::find_shared( Node *n ) { 2046 // Allocate stack of size C->live_nodes() * 2 to avoid frequent realloc 2047 MStack mstack(C->live_nodes() * 2); 2048 // Mark nodes as address_visited if they are inputs to an address expression 2049 VectorSet address_visited(Thread::current()->resource_area()); 2050 mstack.push(n, Visit); // Don't need to pre-visit root node 2051 while (mstack.is_nonempty()) { 2052 n = mstack.node(); // Leave node on stack 2053 Node_State nstate = mstack.state(); 2054 uint nop = n->Opcode(); 2055 if (nstate == Pre_Visit) { 2056 if (address_visited.test(n->_idx)) { // Visited in address already? 2057 // Flag as visited and shared now. 2058 set_visited(n); 2059 } 2060 if (is_visited(n)) { // Visited already? 2061 // Node is shared and has no reason to clone. Flag it as shared. 2062 // This causes it to match into a register for the sharing. 2063 set_shared(n); // Flag as shared and 2064 mstack.pop(); // remove node from stack 2065 continue; 2066 } 2067 nstate = Visit; // Not already visited; so visit now 2068 } 2069 if (nstate == Visit) { 2070 mstack.set_state(Post_Visit); 2071 set_visited(n); // Flag as visited now 2072 bool mem_op = false; 2073 int mem_addr_idx = MemNode::Address; 2074 2075 switch( nop ) { // Handle some opcodes special 2076 case Op_Phi: // Treat Phis as shared roots 2077 case Op_Parm: 2078 case Op_Proj: // All handled specially during matching 2079 case Op_SafePointScalarObject: 2080 set_shared(n); 2081 set_dontcare(n); 2082 break; 2083 case Op_If: 2084 case Op_CountedLoopEnd: 2085 mstack.set_state(Alt_Post_Visit); // Alternative way 2086 // Convert (If (Bool (CmpX A B))) into (If (Bool) (CmpX A B)). Helps 2087 // with matching cmp/branch in 1 instruction. The Matcher needs the 2088 // Bool and CmpX side-by-side, because it can only get at constants 2089 // that are at the leaves of Match trees, and the Bool's condition acts 2090 // as a constant here. 2091 mstack.push(n->in(1), Visit); // Clone the Bool 2092 mstack.push(n->in(0), Pre_Visit); // Visit control input 2093 continue; // while (mstack.is_nonempty()) 2094 case Op_ConvI2D: // These forms efficiently match with a prior 2095 case Op_ConvI2F: // Load but not a following Store 2096 if( n->in(1)->is_Load() && // Prior load 2097 n->outcnt() == 1 && // Not already shared 2098 n->unique_out()->is_Store() ) // Following store 2099 set_shared(n); // Force it to be a root 2100 break; 2101 case Op_ReverseBytesI: 2102 case Op_ReverseBytesL: 2103 if( n->in(1)->is_Load() && // Prior load 2104 n->outcnt() == 1 ) // Not already shared 2105 set_shared(n); // Force it to be a root 2106 break; 2107 case Op_BoxLock: // Cant match until we get stack-regs in ADLC 2108 case Op_IfFalse: 2109 case Op_IfTrue: 2110 case Op_MachProj: 2111 case Op_MergeMem: 2112 case Op_Catch: 2113 case Op_CatchProj: 2114 case Op_CProj: 2115 case Op_JumpProj: 2116 case Op_JProj: 2117 case Op_NeverBranch: 2118 set_dontcare(n); 2119 break; 2120 case Op_Jump: 2121 mstack.push(n->in(1), Pre_Visit); // Switch Value (could be shared) 2122 mstack.push(n->in(0), Pre_Visit); // Visit Control input 2123 continue; // while (mstack.is_nonempty()) 2124 case Op_StrComp: 2125 case Op_StrEquals: 2126 case Op_StrIndexOf: 2127 case Op_StrIndexOfChar: 2128 case Op_AryEq: 2129 case Op_HasNegatives: 2130 case Op_StrInflatedCopy: 2131 case Op_StrCompressedCopy: 2132 case Op_EncodeISOArray: 2133 case Op_FmaD: 2134 case Op_FmaF: 2135 case Op_FmaVD: 2136 case Op_FmaVF: 2137 set_shared(n); // Force result into register (it will be anyways) 2138 break; 2139 case Op_ConP: { // Convert pointers above the centerline to NUL 2140 TypeNode *tn = n->as_Type(); // Constants derive from type nodes 2141 const TypePtr* tp = tn->type()->is_ptr(); 2142 if (tp->_ptr == TypePtr::AnyNull) { 2143 tn->set_type(TypePtr::NULL_PTR); 2144 } 2145 break; 2146 } 2147 case Op_ConN: { // Convert narrow pointers above the centerline to NUL 2148 TypeNode *tn = n->as_Type(); // Constants derive from type nodes 2149 const TypePtr* tp = tn->type()->make_ptr(); 2150 if (tp && tp->_ptr == TypePtr::AnyNull) { 2151 tn->set_type(TypeNarrowOop::NULL_PTR); 2152 } 2153 break; 2154 } 2155 case Op_Binary: // These are introduced in the Post_Visit state. 2156 ShouldNotReachHere(); 2157 break; 2158 case Op_ClearArray: 2159 case Op_SafePoint: 2160 mem_op = true; 2161 break; 2162 #if INCLUDE_ZGC 2163 case Op_CallLeaf: 2164 if (UseZGC) { 2165 if (n->as_Call()->entry_point() == ZBarrierSetRuntime::load_barrier_on_oop_field_preloaded_addr() || 2166 n->as_Call()->entry_point() == ZBarrierSetRuntime::load_barrier_on_weak_oop_field_preloaded_addr()) { 2167 mem_op = true; 2168 mem_addr_idx = TypeFunc::Parms+1; 2169 } 2170 break; 2171 } 2172 #endif 2173 default: 2174 if( n->is_Store() ) { 2175 // Do match stores, despite no ideal reg 2176 mem_op = true; 2177 break; 2178 } 2179 if( n->is_Mem() ) { // Loads and LoadStores 2180 mem_op = true; 2181 // Loads must be root of match tree due to prior load conflict 2182 if( C->subsume_loads() == false ) 2183 set_shared(n); 2184 } 2185 // Fall into default case 2186 if( !n->ideal_reg() ) 2187 set_dontcare(n); // Unmatchable Nodes 2188 } // end_switch 2189 2190 for(int i = n->req() - 1; i >= 0; --i) { // For my children 2191 Node *m = n->in(i); // Get ith input 2192 if (m == NULL) continue; // Ignore NULLs 2193 uint mop = m->Opcode(); 2194 2195 // Must clone all producers of flags, or we will not match correctly. 2196 // Suppose a compare setting int-flags is shared (e.g., a switch-tree) 2197 // then it will match into an ideal Op_RegFlags. Alas, the fp-flags 2198 // are also there, so we may match a float-branch to int-flags and 2199 // expect the allocator to haul the flags from the int-side to the 2200 // fp-side. No can do. 2201 if( _must_clone[mop] ) { 2202 mstack.push(m, Visit); 2203 continue; // for(int i = ...) 2204 } 2205 2206 if( mop == Op_AddP && m->in(AddPNode::Base)->is_DecodeNarrowPtr()) { 2207 // Bases used in addresses must be shared but since 2208 // they are shared through a DecodeN they may appear 2209 // to have a single use so force sharing here. 2210 set_shared(m->in(AddPNode::Base)->in(1)); 2211 } 2212 2213 // if 'n' and 'm' are part of a graph for BMI instruction, clone this node. 2214 #ifdef X86 2215 if (UseBMI1Instructions && is_bmi_pattern(n, m)) { 2216 mstack.push(m, Visit); 2217 continue; 2218 } 2219 #endif 2220 2221 // Clone addressing expressions as they are "free" in memory access instructions 2222 if (mem_op && i == mem_addr_idx && mop == Op_AddP && 2223 // When there are other uses besides address expressions 2224 // put it on stack and mark as shared. 2225 !is_visited(m)) { 2226 // Some inputs for address expression are not put on stack 2227 // to avoid marking them as shared and forcing them into register 2228 // if they are used only in address expressions. 2229 // But they should be marked as shared if there are other uses 2230 // besides address expressions. 2231 2232 if (clone_address_expressions(m->as_AddP(), mstack, address_visited)) { 2233 continue; 2234 } 2235 } // if( mem_op && 2236 mstack.push(m, Pre_Visit); 2237 } // for(int i = ...) 2238 } 2239 else if (nstate == Alt_Post_Visit) { 2240 mstack.pop(); // Remove node from stack 2241 // We cannot remove the Cmp input from the Bool here, as the Bool may be 2242 // shared and all users of the Bool need to move the Cmp in parallel. 2243 // This leaves both the Bool and the If pointing at the Cmp. To 2244 // prevent the Matcher from trying to Match the Cmp along both paths 2245 // BoolNode::match_edge always returns a zero. 2246 2247 // We reorder the Op_If in a pre-order manner, so we can visit without 2248 // accidentally sharing the Cmp (the Bool and the If make 2 users). 2249 n->add_req( n->in(1)->in(1) ); // Add the Cmp next to the Bool 2250 } 2251 else if (nstate == Post_Visit) { 2252 mstack.pop(); // Remove node from stack 2253 2254 // Now hack a few special opcodes 2255 switch( n->Opcode() ) { // Handle some opcodes special 2256 case Op_StorePConditional: 2257 case Op_StoreIConditional: 2258 case Op_StoreLConditional: 2259 case Op_CompareAndExchangeB: 2260 case Op_CompareAndExchangeS: 2261 case Op_CompareAndExchangeI: 2262 case Op_CompareAndExchangeL: 2263 case Op_CompareAndExchangeP: 2264 case Op_CompareAndExchangeN: 2265 case Op_WeakCompareAndSwapB: 2266 case Op_WeakCompareAndSwapS: 2267 case Op_WeakCompareAndSwapI: 2268 case Op_WeakCompareAndSwapL: 2269 case Op_WeakCompareAndSwapP: 2270 case Op_WeakCompareAndSwapN: 2271 case Op_CompareAndSwapB: 2272 case Op_CompareAndSwapS: 2273 case Op_CompareAndSwapI: 2274 case Op_CompareAndSwapL: 2275 case Op_CompareAndSwapP: 2276 case Op_CompareAndSwapN: { // Convert trinary to binary-tree 2277 Node *newval = n->in(MemNode::ValueIn ); 2278 Node *oldval = n->in(LoadStoreConditionalNode::ExpectedIn); 2279 Node *pair = new BinaryNode( oldval, newval ); 2280 n->set_req(MemNode::ValueIn,pair); 2281 n->del_req(LoadStoreConditionalNode::ExpectedIn); 2282 break; 2283 } 2284 case Op_CMoveD: // Convert trinary to binary-tree 2285 case Op_CMoveF: 2286 case Op_CMoveI: 2287 case Op_CMoveL: 2288 case Op_CMoveN: 2289 case Op_CMoveP: 2290 case Op_CMoveVF: 2291 case Op_CMoveVD: { 2292 // Restructure into a binary tree for Matching. It's possible that 2293 // we could move this code up next to the graph reshaping for IfNodes 2294 // or vice-versa, but I do not want to debug this for Ladybird. 2295 // 10/2/2000 CNC. 2296 Node *pair1 = new BinaryNode(n->in(1),n->in(1)->in(1)); 2297 n->set_req(1,pair1); 2298 Node *pair2 = new BinaryNode(n->in(2),n->in(3)); 2299 n->set_req(2,pair2); 2300 n->del_req(3); 2301 break; 2302 } 2303 case Op_LoopLimit: { 2304 Node *pair1 = new BinaryNode(n->in(1),n->in(2)); 2305 n->set_req(1,pair1); 2306 n->set_req(2,n->in(3)); 2307 n->del_req(3); 2308 break; 2309 } 2310 case Op_StrEquals: 2311 case Op_StrIndexOfChar: { 2312 Node *pair1 = new BinaryNode(n->in(2),n->in(3)); 2313 n->set_req(2,pair1); 2314 n->set_req(3,n->in(4)); 2315 n->del_req(4); 2316 break; 2317 } 2318 case Op_StrComp: 2319 case Op_StrIndexOf: { 2320 Node *pair1 = new BinaryNode(n->in(2),n->in(3)); 2321 n->set_req(2,pair1); 2322 Node *pair2 = new BinaryNode(n->in(4),n->in(5)); 2323 n->set_req(3,pair2); 2324 n->del_req(5); 2325 n->del_req(4); 2326 break; 2327 } 2328 case Op_StrCompressedCopy: 2329 case Op_StrInflatedCopy: 2330 case Op_EncodeISOArray: { 2331 // Restructure into a binary tree for Matching. 2332 Node* pair = new BinaryNode(n->in(3), n->in(4)); 2333 n->set_req(3, pair); 2334 n->del_req(4); 2335 break; 2336 } 2337 case Op_FmaD: 2338 case Op_FmaF: 2339 case Op_FmaVD: 2340 case Op_FmaVF: { 2341 // Restructure into a binary tree for Matching. 2342 Node* pair = new BinaryNode(n->in(1), n->in(2)); 2343 n->set_req(2, pair); 2344 n->set_req(1, n->in(3)); 2345 n->del_req(3); 2346 break; 2347 } 2348 case Op_MulAddS2I: { 2349 Node* pair1 = new BinaryNode(n->in(1), n->in(2)); 2350 Node* pair2 = new BinaryNode(n->in(3), n->in(4)); 2351 n->set_req(1, pair1); 2352 n->set_req(2, pair2); 2353 n->del_req(4); 2354 n->del_req(3); 2355 break; 2356 } 2357 default: 2358 break; 2359 } 2360 } 2361 else { 2362 ShouldNotReachHere(); 2363 } 2364 } // end of while (mstack.is_nonempty()) 2365 } 2366 2367 #ifdef ASSERT 2368 // machine-independent root to machine-dependent root 2369 void Matcher::dump_old2new_map() { 2370 _old2new_map.dump(); 2371 } 2372 #endif 2373 2374 //---------------------------collect_null_checks------------------------------- 2375 // Find null checks in the ideal graph; write a machine-specific node for 2376 // it. Used by later implicit-null-check handling. Actually collects 2377 // either an IfTrue or IfFalse for the common NOT-null path, AND the ideal 2378 // value being tested. 2379 void Matcher::collect_null_checks( Node *proj, Node *orig_proj ) { 2380 Node *iff = proj->in(0); 2381 if( iff->Opcode() == Op_If ) { 2382 // During matching If's have Bool & Cmp side-by-side 2383 BoolNode *b = iff->in(1)->as_Bool(); 2384 Node *cmp = iff->in(2); 2385 int opc = cmp->Opcode(); 2386 if (opc != Op_CmpP && opc != Op_CmpN) return; 2387 2388 const Type* ct = cmp->in(2)->bottom_type(); 2389 if (ct == TypePtr::NULL_PTR || 2390 (opc == Op_CmpN && ct == TypeNarrowOop::NULL_PTR)) { 2391 2392 bool push_it = false; 2393 if( proj->Opcode() == Op_IfTrue ) { 2394 #ifndef PRODUCT 2395 extern int all_null_checks_found; 2396 all_null_checks_found++; 2397 #endif 2398 if( b->_test._test == BoolTest::ne ) { 2399 push_it = true; 2400 } 2401 } else { 2402 assert( proj->Opcode() == Op_IfFalse, "" ); 2403 if( b->_test._test == BoolTest::eq ) { 2404 push_it = true; 2405 } 2406 } 2407 if( push_it ) { 2408 _null_check_tests.push(proj); 2409 Node* val = cmp->in(1); 2410 #ifdef _LP64 2411 if (val->bottom_type()->isa_narrowoop() && 2412 !Matcher::narrow_oop_use_complex_address()) { 2413 // 2414 // Look for DecodeN node which should be pinned to orig_proj. 2415 // On platforms (Sparc) which can not handle 2 adds 2416 // in addressing mode we have to keep a DecodeN node and 2417 // use it to do implicit NULL check in address. 2418 // 2419 // DecodeN node was pinned to non-null path (orig_proj) during 2420 // CastPP transformation in final_graph_reshaping_impl(). 2421 // 2422 uint cnt = orig_proj->outcnt(); 2423 for (uint i = 0; i < orig_proj->outcnt(); i++) { 2424 Node* d = orig_proj->raw_out(i); 2425 if (d->is_DecodeN() && d->in(1) == val) { 2426 val = d; 2427 val->set_req(0, NULL); // Unpin now. 2428 // Mark this as special case to distinguish from 2429 // a regular case: CmpP(DecodeN, NULL). 2430 val = (Node*)(((intptr_t)val) | 1); 2431 break; 2432 } 2433 } 2434 } 2435 #endif 2436 _null_check_tests.push(val); 2437 } 2438 } 2439 } 2440 } 2441 2442 //---------------------------validate_null_checks------------------------------ 2443 // Its possible that the value being NULL checked is not the root of a match 2444 // tree. If so, I cannot use the value in an implicit null check. 2445 void Matcher::validate_null_checks( ) { 2446 uint cnt = _null_check_tests.size(); 2447 for( uint i=0; i < cnt; i+=2 ) { 2448 Node *test = _null_check_tests[i]; 2449 Node *val = _null_check_tests[i+1]; 2450 bool is_decoden = ((intptr_t)val) & 1; 2451 val = (Node*)(((intptr_t)val) & ~1); 2452 if (has_new_node(val)) { 2453 Node* new_val = new_node(val); 2454 if (is_decoden) { 2455 assert(val->is_DecodeNarrowPtr() && val->in(0) == NULL, "sanity"); 2456 // Note: new_val may have a control edge if 2457 // the original ideal node DecodeN was matched before 2458 // it was unpinned in Matcher::collect_null_checks(). 2459 // Unpin the mach node and mark it. 2460 new_val->set_req(0, NULL); 2461 new_val = (Node*)(((intptr_t)new_val) | 1); 2462 } 2463 // Is a match-tree root, so replace with the matched value 2464 _null_check_tests.map(i+1, new_val); 2465 } else { 2466 // Yank from candidate list 2467 _null_check_tests.map(i+1,_null_check_tests[--cnt]); 2468 _null_check_tests.map(i,_null_check_tests[--cnt]); 2469 _null_check_tests.pop(); 2470 _null_check_tests.pop(); 2471 i-=2; 2472 } 2473 } 2474 } 2475 2476 // Used by the DFA in dfa_xxx.cpp. Check for a following barrier or 2477 // atomic instruction acting as a store_load barrier without any 2478 // intervening volatile load, and thus we don't need a barrier here. 2479 // We retain the Node to act as a compiler ordering barrier. 2480 bool Matcher::post_store_load_barrier(const Node* vmb) { 2481 Compile* C = Compile::current(); 2482 assert(vmb->is_MemBar(), ""); 2483 assert(vmb->Opcode() != Op_MemBarAcquire && vmb->Opcode() != Op_LoadFence, ""); 2484 const MemBarNode* membar = vmb->as_MemBar(); 2485 2486 // Get the Ideal Proj node, ctrl, that can be used to iterate forward 2487 Node* ctrl = NULL; 2488 for (DUIterator_Fast imax, i = membar->fast_outs(imax); i < imax; i++) { 2489 Node* p = membar->fast_out(i); 2490 assert(p->is_Proj(), "only projections here"); 2491 if ((p->as_Proj()->_con == TypeFunc::Control) && 2492 !C->node_arena()->contains(p)) { // Unmatched old-space only 2493 ctrl = p; 2494 break; 2495 } 2496 } 2497 assert((ctrl != NULL), "missing control projection"); 2498 2499 for (DUIterator_Fast jmax, j = ctrl->fast_outs(jmax); j < jmax; j++) { 2500 Node *x = ctrl->fast_out(j); 2501 int xop = x->Opcode(); 2502 2503 // We don't need current barrier if we see another or a lock 2504 // before seeing volatile load. 2505 // 2506 // Op_Fastunlock previously appeared in the Op_* list below. 2507 // With the advent of 1-0 lock operations we're no longer guaranteed 2508 // that a monitor exit operation contains a serializing instruction. 2509 2510 if (xop == Op_MemBarVolatile || 2511 xop == Op_CompareAndExchangeB || 2512 xop == Op_CompareAndExchangeS || 2513 xop == Op_CompareAndExchangeI || 2514 xop == Op_CompareAndExchangeL || 2515 xop == Op_CompareAndExchangeP || 2516 xop == Op_CompareAndExchangeN || 2517 xop == Op_WeakCompareAndSwapB || 2518 xop == Op_WeakCompareAndSwapS || 2519 xop == Op_WeakCompareAndSwapL || 2520 xop == Op_WeakCompareAndSwapP || 2521 xop == Op_WeakCompareAndSwapN || 2522 xop == Op_WeakCompareAndSwapI || 2523 xop == Op_CompareAndSwapB || 2524 xop == Op_CompareAndSwapS || 2525 xop == Op_CompareAndSwapL || 2526 xop == Op_CompareAndSwapP || 2527 xop == Op_CompareAndSwapN || 2528 xop == Op_CompareAndSwapI) { 2529 return true; 2530 } 2531 2532 // Op_FastLock previously appeared in the Op_* list above. 2533 // With biased locking we're no longer guaranteed that a monitor 2534 // enter operation contains a serializing instruction. 2535 if ((xop == Op_FastLock) && !UseBiasedLocking) { 2536 return true; 2537 } 2538 2539 if (x->is_MemBar()) { 2540 // We must retain this membar if there is an upcoming volatile 2541 // load, which will be followed by acquire membar. 2542 if (xop == Op_MemBarAcquire || xop == Op_LoadFence) { 2543 return false; 2544 } else { 2545 // For other kinds of barriers, check by pretending we 2546 // are them, and seeing if we can be removed. 2547 return post_store_load_barrier(x->as_MemBar()); 2548 } 2549 } 2550 2551 // probably not necessary to check for these 2552 if (x->is_Call() || x->is_SafePoint() || x->is_block_proj()) { 2553 return false; 2554 } 2555 } 2556 return false; 2557 } 2558 2559 // Check whether node n is a branch to an uncommon trap that we could 2560 // optimize as test with very high branch costs in case of going to 2561 // the uncommon trap. The code must be able to be recompiled to use 2562 // a cheaper test. 2563 bool Matcher::branches_to_uncommon_trap(const Node *n) { 2564 // Don't do it for natives, adapters, or runtime stubs 2565 Compile *C = Compile::current(); 2566 if (!C->is_method_compilation()) return false; 2567 2568 assert(n->is_If(), "You should only call this on if nodes."); 2569 IfNode *ifn = n->as_If(); 2570 2571 Node *ifFalse = NULL; 2572 for (DUIterator_Fast imax, i = ifn->fast_outs(imax); i < imax; i++) { 2573 if (ifn->fast_out(i)->is_IfFalse()) { 2574 ifFalse = ifn->fast_out(i); 2575 break; 2576 } 2577 } 2578 assert(ifFalse, "An If should have an ifFalse. Graph is broken."); 2579 2580 Node *reg = ifFalse; 2581 int cnt = 4; // We must protect against cycles. Limit to 4 iterations. 2582 // Alternatively use visited set? Seems too expensive. 2583 while (reg != NULL && cnt > 0) { 2584 CallNode *call = NULL; 2585 RegionNode *nxt_reg = NULL; 2586 for (DUIterator_Fast imax, i = reg->fast_outs(imax); i < imax; i++) { 2587 Node *o = reg->fast_out(i); 2588 if (o->is_Call()) { 2589 call = o->as_Call(); 2590 } 2591 if (o->is_Region()) { 2592 nxt_reg = o->as_Region(); 2593 } 2594 } 2595 2596 if (call && 2597 call->entry_point() == SharedRuntime::uncommon_trap_blob()->entry_point()) { 2598 const Type* trtype = call->in(TypeFunc::Parms)->bottom_type(); 2599 if (trtype->isa_int() && trtype->is_int()->is_con()) { 2600 jint tr_con = trtype->is_int()->get_con(); 2601 Deoptimization::DeoptReason reason = Deoptimization::trap_request_reason(tr_con); 2602 Deoptimization::DeoptAction action = Deoptimization::trap_request_action(tr_con); 2603 assert((int)reason < (int)BitsPerInt, "recode bit map"); 2604 2605 if (is_set_nth_bit(C->allowed_deopt_reasons(), (int)reason) 2606 && action != Deoptimization::Action_none) { 2607 // This uncommon trap is sure to recompile, eventually. 2608 // When that happens, C->too_many_traps will prevent 2609 // this transformation from happening again. 2610 return true; 2611 } 2612 } 2613 } 2614 2615 reg = nxt_reg; 2616 cnt--; 2617 } 2618 2619 return false; 2620 } 2621 2622 //============================================================================= 2623 //---------------------------State--------------------------------------------- 2624 State::State(void) { 2625 #ifdef ASSERT 2626 _id = 0; 2627 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe); 2628 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d); 2629 //memset(_cost, -1, sizeof(_cost)); 2630 //memset(_rule, -1, sizeof(_rule)); 2631 #endif 2632 memset(_valid, 0, sizeof(_valid)); 2633 } 2634 2635 #ifdef ASSERT 2636 State::~State() { 2637 _id = 99; 2638 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe); 2639 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d); 2640 memset(_cost, -3, sizeof(_cost)); 2641 memset(_rule, -3, sizeof(_rule)); 2642 } 2643 #endif 2644 2645 #ifndef PRODUCT 2646 //---------------------------dump---------------------------------------------- 2647 void State::dump() { 2648 tty->print("\n"); 2649 dump(0); 2650 } 2651 2652 void State::dump(int depth) { 2653 for( int j = 0; j < depth; j++ ) 2654 tty->print(" "); 2655 tty->print("--N: "); 2656 _leaf->dump(); 2657 uint i; 2658 for( i = 0; i < _LAST_MACH_OPER; i++ ) 2659 // Check for valid entry 2660 if( valid(i) ) { 2661 for( int j = 0; j < depth; j++ ) 2662 tty->print(" "); 2663 assert(_cost[i] != max_juint, "cost must be a valid value"); 2664 assert(_rule[i] < _last_Mach_Node, "rule[i] must be valid rule"); 2665 tty->print_cr("%s %d %s", 2666 ruleName[i], _cost[i], ruleName[_rule[i]] ); 2667 } 2668 tty->cr(); 2669 2670 for( i=0; i<2; i++ ) 2671 if( _kids[i] ) 2672 _kids[i]->dump(depth+1); 2673 } 2674 #endif