1 /*
2 * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "gc/shared/cardTableBarrierSet.hpp"
29 #include "gc/shared/collectedHeap.inline.hpp"
30 #include "interpreter/interpreter.hpp"
31 #include "memory/resourceArea.hpp"
32 #include "prims/methodHandles.hpp"
33 #include "runtime/biasedLocking.hpp"
34 #include "runtime/objectMonitor.hpp"
35 #include "runtime/os.hpp"
36 #include "runtime/sharedRuntime.hpp"
37 #include "runtime/stubRoutines.hpp"
38 #include "utilities/macros.hpp"
39
40 #ifdef PRODUCT
41 #define BLOCK_COMMENT(str) /* nothing */
42 #define STOP(error) stop(error)
43 #else
44 #define BLOCK_COMMENT(str) block_comment(str)
45 #define STOP(error) block_comment(error); stop(error)
46 #endif
47
48 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
49 // Implementation of AddressLiteral
50
51 // A 2-D table for managing compressed displacement(disp8) on EVEX enabled platforms.
52 unsigned char tuple_table[Assembler::EVEX_ETUP + 1][Assembler::AVX_512bit + 1] = {
53 // -----------------Table 4.5 -------------------- //
54 16, 32, 64, // EVEX_FV(0)
55 4, 4, 4, // EVEX_FV(1) - with Evex.b
56 16, 32, 64, // EVEX_FV(2) - with Evex.w
57 8, 8, 8, // EVEX_FV(3) - with Evex.w and Evex.b
58 8, 16, 32, // EVEX_HV(0)
59 4, 4, 4, // EVEX_HV(1) - with Evex.b
60 // -----------------Table 4.6 -------------------- //
61 16, 32, 64, // EVEX_FVM(0)
62 1, 1, 1, // EVEX_T1S(0)
63 2, 2, 2, // EVEX_T1S(1)
64 4, 4, 4, // EVEX_T1S(2)
65 8, 8, 8, // EVEX_T1S(3)
66 4, 4, 4, // EVEX_T1F(0)
67 8, 8, 8, // EVEX_T1F(1)
68 8, 8, 8, // EVEX_T2(0)
69 0, 16, 16, // EVEX_T2(1)
70 0, 16, 16, // EVEX_T4(0)
71 0, 0, 32, // EVEX_T4(1)
72 0, 0, 32, // EVEX_T8(0)
73 8, 16, 32, // EVEX_HVM(0)
74 4, 8, 16, // EVEX_QVM(0)
75 2, 4, 8, // EVEX_OVM(0)
76 16, 16, 16, // EVEX_M128(0)
77 8, 32, 64, // EVEX_DUP(0)
78 0, 0, 0 // EVEX_NTUP
79 };
80
81 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
82 _is_lval = false;
83 _target = target;
84 switch (rtype) {
85 case relocInfo::oop_type:
86 case relocInfo::metadata_type:
87 // Oops are a special case. Normally they would be their own section
88 // but in cases like icBuffer they are literals in the code stream that
89 // we don't have a section for. We use none so that we get a literal address
90 // which is always patchable.
91 break;
92 case relocInfo::external_word_type:
93 _rspec = external_word_Relocation::spec(target);
94 break;
95 case relocInfo::internal_word_type:
96 _rspec = internal_word_Relocation::spec(target);
97 break;
98 case relocInfo::opt_virtual_call_type:
99 _rspec = opt_virtual_call_Relocation::spec();
100 break;
101 case relocInfo::static_call_type:
102 _rspec = static_call_Relocation::spec();
103 break;
104 case relocInfo::runtime_call_type:
105 _rspec = runtime_call_Relocation::spec();
106 break;
107 case relocInfo::poll_type:
108 case relocInfo::poll_return_type:
109 _rspec = Relocation::spec_simple(rtype);
110 break;
111 case relocInfo::none:
112 break;
113 default:
114 ShouldNotReachHere();
115 break;
116 }
117 }
118
119 // Implementation of Address
120
121 #ifdef _LP64
122
123 Address Address::make_array(ArrayAddress adr) {
124 // Not implementable on 64bit machines
125 // Should have been handled higher up the call chain.
126 ShouldNotReachHere();
127 return Address();
128 }
129
130 // exceedingly dangerous constructor
131 Address::Address(int disp, address loc, relocInfo::relocType rtype) {
132 _base = noreg;
133 _index = noreg;
134 _scale = no_scale;
135 _disp = disp;
136 _xmmindex = xnoreg;
137 _isxmmindex = false;
138 switch (rtype) {
139 case relocInfo::external_word_type:
140 _rspec = external_word_Relocation::spec(loc);
141 break;
142 case relocInfo::internal_word_type:
143 _rspec = internal_word_Relocation::spec(loc);
144 break;
145 case relocInfo::runtime_call_type:
146 // HMM
147 _rspec = runtime_call_Relocation::spec();
148 break;
149 case relocInfo::poll_type:
150 case relocInfo::poll_return_type:
151 _rspec = Relocation::spec_simple(rtype);
152 break;
153 case relocInfo::none:
154 break;
155 default:
156 ShouldNotReachHere();
157 }
158 }
159 #else // LP64
160
161 Address Address::make_array(ArrayAddress adr) {
162 AddressLiteral base = adr.base();
163 Address index = adr.index();
164 assert(index._disp == 0, "must not have disp"); // maybe it can?
165 Address array(index._base, index._index, index._scale, (intptr_t) base.target());
166 array._rspec = base._rspec;
167 return array;
168 }
169
170 // exceedingly dangerous constructor
171 Address::Address(address loc, RelocationHolder spec) {
172 _base = noreg;
173 _index = noreg;
174 _scale = no_scale;
175 _disp = (intptr_t) loc;
176 _rspec = spec;
177 _xmmindex = xnoreg;
178 _isxmmindex = false;
179 }
180
181 #endif // _LP64
182
183
184
185 // Convert the raw encoding form into the form expected by the constructor for
186 // Address. An index of 4 (rsp) corresponds to having no index, so convert
187 // that to noreg for the Address constructor.
188 Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) {
189 RelocationHolder rspec;
190 if (disp_reloc != relocInfo::none) {
191 rspec = Relocation::spec_simple(disp_reloc);
192 }
193 bool valid_index = index != rsp->encoding();
194 if (valid_index) {
195 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));
196 madr._rspec = rspec;
197 return madr;
198 } else {
199 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));
200 madr._rspec = rspec;
201 return madr;
202 }
203 }
204
205 // Implementation of Assembler
206
207 int AbstractAssembler::code_fill_byte() {
208 return (u_char)'\xF4'; // hlt
209 }
210
211 // make this go away someday
212 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) {
213 if (rtype == relocInfo::none)
214 emit_int32(data);
215 else
216 emit_data(data, Relocation::spec_simple(rtype), format);
217 }
218
219 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) {
220 assert(imm_operand == 0, "default format must be immediate in this file");
221 assert(inst_mark() != NULL, "must be inside InstructionMark");
222 if (rspec.type() != relocInfo::none) {
223 #ifdef ASSERT
224 check_relocation(rspec, format);
225 #endif
226 // Do not use AbstractAssembler::relocate, which is not intended for
227 // embedded words. Instead, relocate to the enclosing instruction.
228
229 // hack. call32 is too wide for mask so use disp32
230 if (format == call32_operand)
231 code_section()->relocate(inst_mark(), rspec, disp32_operand);
232 else
233 code_section()->relocate(inst_mark(), rspec, format);
234 }
235 emit_int32(data);
236 }
237
238 static int encode(Register r) {
239 int enc = r->encoding();
240 if (enc >= 8) {
241 enc -= 8;
242 }
243 return enc;
244 }
245
246 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
247 assert(dst->has_byte_register(), "must have byte register");
248 assert(isByte(op1) && isByte(op2), "wrong opcode");
249 assert(isByte(imm8), "not a byte");
250 assert((op1 & 0x01) == 0, "should be 8bit operation");
251 emit_int8(op1);
252 emit_int8(op2 | encode(dst));
253 emit_int8(imm8);
254 }
255
256
257 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) {
258 assert(isByte(op1) && isByte(op2), "wrong opcode");
259 assert((op1 & 0x01) == 1, "should be 32bit operation");
260 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
261 if (is8bit(imm32)) {
262 emit_int8(op1 | 0x02); // set sign bit
263 emit_int8(op2 | encode(dst));
264 emit_int8(imm32 & 0xFF);
265 } else {
266 emit_int8(op1);
267 emit_int8(op2 | encode(dst));
268 emit_int32(imm32);
269 }
270 }
271
272 // Force generation of a 4 byte immediate value even if it fits into 8bit
273 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) {
274 assert(isByte(op1) && isByte(op2), "wrong opcode");
275 assert((op1 & 0x01) == 1, "should be 32bit operation");
276 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
277 emit_int8(op1);
278 emit_int8(op2 | encode(dst));
279 emit_int32(imm32);
280 }
281
282 // immediate-to-memory forms
283 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) {
284 assert((op1 & 0x01) == 1, "should be 32bit operation");
285 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
286 if (is8bit(imm32)) {
287 emit_int8(op1 | 0x02); // set sign bit
288 emit_operand(rm, adr, 1);
289 emit_int8(imm32 & 0xFF);
290 } else {
291 emit_int8(op1);
292 emit_operand(rm, adr, 4);
293 emit_int32(imm32);
294 }
295 }
296
297
298 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
299 assert(isByte(op1) && isByte(op2), "wrong opcode");
300 emit_int8(op1);
301 emit_int8(op2 | encode(dst) << 3 | encode(src));
302 }
303
304
305 bool Assembler::query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len,
306 int cur_tuple_type, int in_size_in_bits, int cur_encoding) {
307 int mod_idx = 0;
308 // We will test if the displacement fits the compressed format and if so
309 // apply the compression to the displacment iff the result is8bit.
310 if (VM_Version::supports_evex() && is_evex_inst) {
311 switch (cur_tuple_type) {
312 case EVEX_FV:
313 if ((cur_encoding & VEX_W) == VEX_W) {
314 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2;
315 } else {
316 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
317 }
318 break;
319
320 case EVEX_HV:
321 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
322 break;
323
324 case EVEX_FVM:
325 break;
326
327 case EVEX_T1S:
328 switch (in_size_in_bits) {
329 case EVEX_8bit:
330 break;
331
332 case EVEX_16bit:
333 mod_idx = 1;
334 break;
335
336 case EVEX_32bit:
337 mod_idx = 2;
338 break;
339
340 case EVEX_64bit:
341 mod_idx = 3;
342 break;
343 }
344 break;
345
346 case EVEX_T1F:
347 case EVEX_T2:
348 case EVEX_T4:
349 mod_idx = (in_size_in_bits == EVEX_64bit) ? 1 : 0;
350 break;
351
352 case EVEX_T8:
353 break;
354
355 case EVEX_HVM:
356 break;
357
358 case EVEX_QVM:
359 break;
360
361 case EVEX_OVM:
362 break;
363
364 case EVEX_M128:
365 break;
366
367 case EVEX_DUP:
368 break;
369
370 default:
371 assert(0, "no valid evex tuple_table entry");
372 break;
373 }
374
375 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
376 int disp_factor = tuple_table[cur_tuple_type + mod_idx][vector_len];
377 if ((disp % disp_factor) == 0) {
378 int new_disp = disp / disp_factor;
379 if ((-0x80 <= new_disp && new_disp < 0x80)) {
380 disp = new_disp;
381 }
382 } else {
383 return false;
384 }
385 }
386 }
387 return (-0x80 <= disp && disp < 0x80);
388 }
389
390
391 bool Assembler::emit_compressed_disp_byte(int &disp) {
392 int mod_idx = 0;
393 // We will test if the displacement fits the compressed format and if so
394 // apply the compression to the displacment iff the result is8bit.
395 if (VM_Version::supports_evex() && _attributes && _attributes->is_evex_instruction()) {
396 int evex_encoding = _attributes->get_evex_encoding();
397 int tuple_type = _attributes->get_tuple_type();
398 switch (tuple_type) {
399 case EVEX_FV:
400 if ((evex_encoding & VEX_W) == VEX_W) {
401 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2;
402 } else {
403 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
404 }
405 break;
406
407 case EVEX_HV:
408 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
409 break;
410
411 case EVEX_FVM:
412 break;
413
414 case EVEX_T1S:
415 switch (_attributes->get_input_size()) {
416 case EVEX_8bit:
417 break;
418
419 case EVEX_16bit:
420 mod_idx = 1;
421 break;
422
423 case EVEX_32bit:
424 mod_idx = 2;
425 break;
426
427 case EVEX_64bit:
428 mod_idx = 3;
429 break;
430 }
431 break;
432
433 case EVEX_T1F:
434 case EVEX_T2:
435 case EVEX_T4:
436 mod_idx = (_attributes->get_input_size() == EVEX_64bit) ? 1 : 0;
437 break;
438
439 case EVEX_T8:
440 break;
441
442 case EVEX_HVM:
443 break;
444
445 case EVEX_QVM:
446 break;
447
448 case EVEX_OVM:
449 break;
450
451 case EVEX_M128:
452 break;
453
454 case EVEX_DUP:
455 break;
456
457 default:
458 assert(0, "no valid evex tuple_table entry");
459 break;
460 }
461
462 int vector_len = _attributes->get_vector_len();
463 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
464 int disp_factor = tuple_table[tuple_type + mod_idx][vector_len];
465 if ((disp % disp_factor) == 0) {
466 int new_disp = disp / disp_factor;
467 if (is8bit(new_disp)) {
468 disp = new_disp;
469 }
470 } else {
471 return false;
472 }
473 }
474 }
475 return is8bit(disp);
476 }
477
478
479 void Assembler::emit_operand(Register reg, Register base, Register index,
480 Address::ScaleFactor scale, int disp,
481 RelocationHolder const& rspec,
482 int rip_relative_correction) {
483 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();
484
485 // Encode the registers as needed in the fields they are used in
486
487 int regenc = encode(reg) << 3;
488 int indexenc = index->is_valid() ? encode(index) << 3 : 0;
489 int baseenc = base->is_valid() ? encode(base) : 0;
490
491 if (base->is_valid()) {
492 if (index->is_valid()) {
493 assert(scale != Address::no_scale, "inconsistent address");
494 // [base + index*scale + disp]
495 if (disp == 0 && rtype == relocInfo::none &&
496 base != rbp LP64_ONLY(&& base != r13)) {
497 // [base + index*scale]
498 // [00 reg 100][ss index base]
499 assert(index != rsp, "illegal addressing mode");
500 emit_int8(0x04 | regenc);
501 emit_int8(scale << 6 | indexenc | baseenc);
502 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
503 // [base + index*scale + imm8]
504 // [01 reg 100][ss index base] imm8
505 assert(index != rsp, "illegal addressing mode");
506 emit_int8(0x44 | regenc);
507 emit_int8(scale << 6 | indexenc | baseenc);
508 emit_int8(disp & 0xFF);
509 } else {
510 // [base + index*scale + disp32]
511 // [10 reg 100][ss index base] disp32
512 assert(index != rsp, "illegal addressing mode");
513 emit_int8(0x84 | regenc);
514 emit_int8(scale << 6 | indexenc | baseenc);
515 emit_data(disp, rspec, disp32_operand);
516 }
517 } else if (base == rsp LP64_ONLY(|| base == r12)) {
518 // [rsp + disp]
519 if (disp == 0 && rtype == relocInfo::none) {
520 // [rsp]
521 // [00 reg 100][00 100 100]
522 emit_int8(0x04 | regenc);
523 emit_int8(0x24);
524 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
525 // [rsp + imm8]
526 // [01 reg 100][00 100 100] disp8
527 emit_int8(0x44 | regenc);
528 emit_int8(0x24);
529 emit_int8(disp & 0xFF);
530 } else {
531 // [rsp + imm32]
532 // [10 reg 100][00 100 100] disp32
533 emit_int8(0x84 | regenc);
534 emit_int8(0x24);
535 emit_data(disp, rspec, disp32_operand);
536 }
537 } else {
538 // [base + disp]
539 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode");
540 if (disp == 0 && rtype == relocInfo::none &&
541 base != rbp LP64_ONLY(&& base != r13)) {
542 // [base]
543 // [00 reg base]
544 emit_int8(0x00 | regenc | baseenc);
545 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
546 // [base + disp8]
547 // [01 reg base] disp8
548 emit_int8(0x40 | regenc | baseenc);
549 emit_int8(disp & 0xFF);
550 } else {
551 // [base + disp32]
552 // [10 reg base] disp32
553 emit_int8(0x80 | regenc | baseenc);
554 emit_data(disp, rspec, disp32_operand);
555 }
556 }
557 } else {
558 if (index->is_valid()) {
559 assert(scale != Address::no_scale, "inconsistent address");
560 // [index*scale + disp]
561 // [00 reg 100][ss index 101] disp32
562 assert(index != rsp, "illegal addressing mode");
563 emit_int8(0x04 | regenc);
564 emit_int8(scale << 6 | indexenc | 0x05);
565 emit_data(disp, rspec, disp32_operand);
566 } else if (rtype != relocInfo::none ) {
567 // [disp] (64bit) RIP-RELATIVE (32bit) abs
568 // [00 000 101] disp32
569
570 emit_int8(0x05 | regenc);
571 // Note that the RIP-rel. correction applies to the generated
572 // disp field, but _not_ to the target address in the rspec.
573
574 // disp was created by converting the target address minus the pc
575 // at the start of the instruction. That needs more correction here.
576 // intptr_t disp = target - next_ip;
577 assert(inst_mark() != NULL, "must be inside InstructionMark");
578 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction;
579 int64_t adjusted = disp;
580 // Do rip-rel adjustment for 64bit
581 LP64_ONLY(adjusted -= (next_ip - inst_mark()));
582 assert(is_simm32(adjusted),
583 "must be 32bit offset (RIP relative address)");
584 emit_data((int32_t) adjusted, rspec, disp32_operand);
585
586 } else {
587 // 32bit never did this, did everything as the rip-rel/disp code above
588 // [disp] ABSOLUTE
589 // [00 reg 100][00 100 101] disp32
590 emit_int8(0x04 | regenc);
591 emit_int8(0x25);
592 emit_data(disp, rspec, disp32_operand);
593 }
594 }
595 }
596
597 void Assembler::emit_operand(XMMRegister reg, Register base, Register index,
598 Address::ScaleFactor scale, int disp,
599 RelocationHolder const& rspec) {
600 if (UseAVX > 2) {
601 int xreg_enc = reg->encoding();
602 if (xreg_enc > 15) {
603 XMMRegister new_reg = as_XMMRegister(xreg_enc & 0xf);
604 emit_operand((Register)new_reg, base, index, scale, disp, rspec);
605 return;
606 }
607 }
608 emit_operand((Register)reg, base, index, scale, disp, rspec);
609 }
610
611 void Assembler::emit_operand(XMMRegister reg, Register base, XMMRegister index,
612 Address::ScaleFactor scale, int disp,
613 RelocationHolder const& rspec) {
614 if (UseAVX > 2) {
615 int xreg_enc = reg->encoding();
616 int xmmindex_enc = index->encoding();
617 XMMRegister new_reg = as_XMMRegister(xreg_enc & 0xf);
618 XMMRegister new_index = as_XMMRegister(xmmindex_enc & 0xf);
619 emit_operand((Register)new_reg, base, (Register)new_index, scale, disp, rspec);
620 } else {
621 emit_operand((Register)reg, base, (Register)index, scale, disp, rspec);
622 }
623 }
624
625
626 // Secret local extension to Assembler::WhichOperand:
627 #define end_pc_operand (_WhichOperand_limit)
628
629 address Assembler::locate_operand(address inst, WhichOperand which) {
630 // Decode the given instruction, and return the address of
631 // an embedded 32-bit operand word.
632
633 // If "which" is disp32_operand, selects the displacement portion
634 // of an effective address specifier.
635 // If "which" is imm64_operand, selects the trailing immediate constant.
636 // If "which" is call32_operand, selects the displacement of a call or jump.
637 // Caller is responsible for ensuring that there is such an operand,
638 // and that it is 32/64 bits wide.
639
640 // If "which" is end_pc_operand, find the end of the instruction.
641
642 address ip = inst;
643 bool is_64bit = false;
644
645 debug_only(bool has_disp32 = false);
646 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn
647
648 again_after_prefix:
649 switch (0xFF & *ip++) {
650
651 // These convenience macros generate groups of "case" labels for the switch.
652 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3
653 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \
654 case (x)+4: case (x)+5: case (x)+6: case (x)+7
655 #define REP16(x) REP8((x)+0): \
656 case REP8((x)+8)
657
658 case CS_segment:
659 case SS_segment:
660 case DS_segment:
661 case ES_segment:
662 case FS_segment:
663 case GS_segment:
664 // Seems dubious
665 LP64_ONLY(assert(false, "shouldn't have that prefix"));
666 assert(ip == inst+1, "only one prefix allowed");
667 goto again_after_prefix;
668
669 case 0x67:
670 case REX:
671 case REX_B:
672 case REX_X:
673 case REX_XB:
674 case REX_R:
675 case REX_RB:
676 case REX_RX:
677 case REX_RXB:
678 NOT_LP64(assert(false, "64bit prefixes"));
679 goto again_after_prefix;
680
681 case REX_W:
682 case REX_WB:
683 case REX_WX:
684 case REX_WXB:
685 case REX_WR:
686 case REX_WRB:
687 case REX_WRX:
688 case REX_WRXB:
689 NOT_LP64(assert(false, "64bit prefixes"));
690 is_64bit = true;
691 goto again_after_prefix;
692
693 case 0xFF: // pushq a; decl a; incl a; call a; jmp a
694 case 0x88: // movb a, r
695 case 0x89: // movl a, r
696 case 0x8A: // movb r, a
697 case 0x8B: // movl r, a
698 case 0x8F: // popl a
699 debug_only(has_disp32 = true);
700 break;
701
702 case 0x68: // pushq #32
703 if (which == end_pc_operand) {
704 return ip + 4;
705 }
706 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate");
707 return ip; // not produced by emit_operand
708
709 case 0x66: // movw ... (size prefix)
710 again_after_size_prefix2:
711 switch (0xFF & *ip++) {
712 case REX:
713 case REX_B:
714 case REX_X:
715 case REX_XB:
716 case REX_R:
717 case REX_RB:
718 case REX_RX:
719 case REX_RXB:
720 case REX_W:
721 case REX_WB:
722 case REX_WX:
723 case REX_WXB:
724 case REX_WR:
725 case REX_WRB:
726 case REX_WRX:
727 case REX_WRXB:
728 NOT_LP64(assert(false, "64bit prefix found"));
729 goto again_after_size_prefix2;
730 case 0x8B: // movw r, a
731 case 0x89: // movw a, r
732 debug_only(has_disp32 = true);
733 break;
734 case 0xC7: // movw a, #16
735 debug_only(has_disp32 = true);
736 tail_size = 2; // the imm16
737 break;
738 case 0x0F: // several SSE/SSE2 variants
739 ip--; // reparse the 0x0F
740 goto again_after_prefix;
741 default:
742 ShouldNotReachHere();
743 }
744 break;
745
746 case REP8(0xB8): // movl/q r, #32/#64(oop?)
747 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4);
748 // these asserts are somewhat nonsensical
749 #ifndef _LP64
750 assert(which == imm_operand || which == disp32_operand,
751 "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip));
752 #else
753 assert((which == call32_operand || which == imm_operand) && is_64bit ||
754 which == narrow_oop_operand && !is_64bit,
755 "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip));
756 #endif // _LP64
757 return ip;
758
759 case 0x69: // imul r, a, #32
760 case 0xC7: // movl a, #32(oop?)
761 tail_size = 4;
762 debug_only(has_disp32 = true); // has both kinds of operands!
763 break;
764
765 case 0x0F: // movx..., etc.
766 switch (0xFF & *ip++) {
767 case 0x3A: // pcmpestri
768 tail_size = 1;
769 case 0x38: // ptest, pmovzxbw
770 ip++; // skip opcode
771 debug_only(has_disp32 = true); // has both kinds of operands!
772 break;
773
774 case 0x70: // pshufd r, r/a, #8
775 debug_only(has_disp32 = true); // has both kinds of operands!
776 case 0x73: // psrldq r, #8
777 tail_size = 1;
778 break;
779
780 case 0x12: // movlps
781 case 0x28: // movaps
782 case 0x2E: // ucomiss
783 case 0x2F: // comiss
784 case 0x54: // andps
785 case 0x55: // andnps
786 case 0x56: // orps
787 case 0x57: // xorps
788 case 0x58: // addpd
789 case 0x59: // mulpd
790 case 0x6E: // movd
791 case 0x7E: // movd
792 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush
793 case 0xFE: // paddd
794 debug_only(has_disp32 = true);
795 break;
796
797 case 0xAD: // shrd r, a, %cl
798 case 0xAF: // imul r, a
799 case 0xBE: // movsbl r, a (movsxb)
800 case 0xBF: // movswl r, a (movsxw)
801 case 0xB6: // movzbl r, a (movzxb)
802 case 0xB7: // movzwl r, a (movzxw)
803 case REP16(0x40): // cmovl cc, r, a
804 case 0xB0: // cmpxchgb
805 case 0xB1: // cmpxchg
806 case 0xC1: // xaddl
807 case 0xC7: // cmpxchg8
808 case REP16(0x90): // setcc a
809 debug_only(has_disp32 = true);
810 // fall out of the switch to decode the address
811 break;
812
813 case 0xC4: // pinsrw r, a, #8
814 debug_only(has_disp32 = true);
815 case 0xC5: // pextrw r, r, #8
816 tail_size = 1; // the imm8
817 break;
818
819 case 0xAC: // shrd r, a, #8
820 debug_only(has_disp32 = true);
821 tail_size = 1; // the imm8
822 break;
823
824 case REP16(0x80): // jcc rdisp32
825 if (which == end_pc_operand) return ip + 4;
826 assert(which == call32_operand, "jcc has no disp32 or imm");
827 return ip;
828 default:
829 ShouldNotReachHere();
830 }
831 break;
832
833 case 0x81: // addl a, #32; addl r, #32
834 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
835 // on 32bit in the case of cmpl, the imm might be an oop
836 tail_size = 4;
837 debug_only(has_disp32 = true); // has both kinds of operands!
838 break;
839
840 case 0x83: // addl a, #8; addl r, #8
841 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
842 debug_only(has_disp32 = true); // has both kinds of operands!
843 tail_size = 1;
844 break;
845
846 case 0x9B:
847 switch (0xFF & *ip++) {
848 case 0xD9: // fnstcw a
849 debug_only(has_disp32 = true);
850 break;
851 default:
852 ShouldNotReachHere();
853 }
854 break;
855
856 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a
857 case REP4(0x10): // adc...
858 case REP4(0x20): // and...
859 case REP4(0x30): // xor...
860 case REP4(0x08): // or...
861 case REP4(0x18): // sbb...
862 case REP4(0x28): // sub...
863 case 0xF7: // mull a
864 case 0x8D: // lea r, a
865 case 0x87: // xchg r, a
866 case REP4(0x38): // cmp...
867 case 0x85: // test r, a
868 debug_only(has_disp32 = true); // has both kinds of operands!
869 break;
870
871 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8
872 case 0xC6: // movb a, #8
873 case 0x80: // cmpb a, #8
874 case 0x6B: // imul r, a, #8
875 debug_only(has_disp32 = true); // has both kinds of operands!
876 tail_size = 1; // the imm8
877 break;
878
879 case 0xC4: // VEX_3bytes
880 case 0xC5: // VEX_2bytes
881 assert((UseAVX > 0), "shouldn't have VEX prefix");
882 assert(ip == inst+1, "no prefixes allowed");
883 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions
884 // but they have prefix 0x0F and processed when 0x0F processed above.
885 //
886 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES
887 // instructions (these instructions are not supported in 64-bit mode).
888 // To distinguish them bits [7:6] are set in the VEX second byte since
889 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set
890 // those VEX bits REX and vvvv bits are inverted.
891 //
892 // Fortunately C2 doesn't generate these instructions so we don't need
893 // to check for them in product version.
894
895 // Check second byte
896 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions"));
897
898 int vex_opcode;
899 // First byte
900 if ((0xFF & *inst) == VEX_3bytes) {
901 vex_opcode = VEX_OPCODE_MASK & *ip;
902 ip++; // third byte
903 is_64bit = ((VEX_W & *ip) == VEX_W);
904 } else {
905 vex_opcode = VEX_OPCODE_0F;
906 }
907 ip++; // opcode
908 // To find the end of instruction (which == end_pc_operand).
909 switch (vex_opcode) {
910 case VEX_OPCODE_0F:
911 switch (0xFF & *ip) {
912 case 0x70: // pshufd r, r/a, #8
913 case 0x71: // ps[rl|ra|ll]w r, #8
914 case 0x72: // ps[rl|ra|ll]d r, #8
915 case 0x73: // ps[rl|ra|ll]q r, #8
916 case 0xC2: // cmp[ps|pd|ss|sd] r, r, r/a, #8
917 case 0xC4: // pinsrw r, r, r/a, #8
918 case 0xC5: // pextrw r/a, r, #8
919 case 0xC6: // shufp[s|d] r, r, r/a, #8
920 tail_size = 1; // the imm8
921 break;
922 }
923 break;
924 case VEX_OPCODE_0F_3A:
925 tail_size = 1;
926 break;
927 }
928 ip++; // skip opcode
929 debug_only(has_disp32 = true); // has both kinds of operands!
930 break;
931
932 case 0x62: // EVEX_4bytes
933 assert(VM_Version::supports_evex(), "shouldn't have EVEX prefix");
934 assert(ip == inst+1, "no prefixes allowed");
935 // no EVEX collisions, all instructions that have 0x62 opcodes
936 // have EVEX versions and are subopcodes of 0x66
937 ip++; // skip P0 and exmaine W in P1
938 is_64bit = ((VEX_W & *ip) == VEX_W);
939 ip++; // move to P2
940 ip++; // skip P2, move to opcode
941 // To find the end of instruction (which == end_pc_operand).
942 switch (0xFF & *ip) {
943 case 0x22: // pinsrd r, r/a, #8
944 case 0x61: // pcmpestri r, r/a, #8
945 case 0x70: // pshufd r, r/a, #8
946 case 0x73: // psrldq r, #8
947 tail_size = 1; // the imm8
948 break;
949 default:
950 break;
951 }
952 ip++; // skip opcode
953 debug_only(has_disp32 = true); // has both kinds of operands!
954 break;
955
956 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
957 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
958 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a
959 case 0xDD: // fld_d a; fst_d a; fstp_d a
960 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a
961 case 0xDF: // fild_d a; fistp_d a
962 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a
963 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a
964 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a
965 debug_only(has_disp32 = true);
966 break;
967
968 case 0xE8: // call rdisp32
969 case 0xE9: // jmp rdisp32
970 if (which == end_pc_operand) return ip + 4;
971 assert(which == call32_operand, "call has no disp32 or imm");
972 return ip;
973
974 case 0xF0: // Lock
975 goto again_after_prefix;
976
977 case 0xF3: // For SSE
978 case 0xF2: // For SSE2
979 switch (0xFF & *ip++) {
980 case REX:
981 case REX_B:
982 case REX_X:
983 case REX_XB:
984 case REX_R:
985 case REX_RB:
986 case REX_RX:
987 case REX_RXB:
988 case REX_W:
989 case REX_WB:
990 case REX_WX:
991 case REX_WXB:
992 case REX_WR:
993 case REX_WRB:
994 case REX_WRX:
995 case REX_WRXB:
996 NOT_LP64(assert(false, "found 64bit prefix"));
997 ip++;
998 default:
999 ip++;
1000 }
1001 debug_only(has_disp32 = true); // has both kinds of operands!
1002 break;
1003
1004 default:
1005 ShouldNotReachHere();
1006
1007 #undef REP8
1008 #undef REP16
1009 }
1010
1011 assert(which != call32_operand, "instruction is not a call, jmp, or jcc");
1012 #ifdef _LP64
1013 assert(which != imm_operand, "instruction is not a movq reg, imm64");
1014 #else
1015 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field");
1016 assert(which != imm_operand || has_disp32, "instruction has no imm32 field");
1017 #endif // LP64
1018 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field");
1019
1020 // parse the output of emit_operand
1021 int op2 = 0xFF & *ip++;
1022 int base = op2 & 0x07;
1023 int op3 = -1;
1024 const int b100 = 4;
1025 const int b101 = 5;
1026 if (base == b100 && (op2 >> 6) != 3) {
1027 op3 = 0xFF & *ip++;
1028 base = op3 & 0x07; // refetch the base
1029 }
1030 // now ip points at the disp (if any)
1031
1032 switch (op2 >> 6) {
1033 case 0:
1034 // [00 reg 100][ss index base]
1035 // [00 reg 100][00 100 esp]
1036 // [00 reg base]
1037 // [00 reg 100][ss index 101][disp32]
1038 // [00 reg 101] [disp32]
1039
1040 if (base == b101) {
1041 if (which == disp32_operand)
1042 return ip; // caller wants the disp32
1043 ip += 4; // skip the disp32
1044 }
1045 break;
1046
1047 case 1:
1048 // [01 reg 100][ss index base][disp8]
1049 // [01 reg 100][00 100 esp][disp8]
1050 // [01 reg base] [disp8]
1051 ip += 1; // skip the disp8
1052 break;
1053
1054 case 2:
1055 // [10 reg 100][ss index base][disp32]
1056 // [10 reg 100][00 100 esp][disp32]
1057 // [10 reg base] [disp32]
1058 if (which == disp32_operand)
1059 return ip; // caller wants the disp32
1060 ip += 4; // skip the disp32
1061 break;
1062
1063 case 3:
1064 // [11 reg base] (not a memory addressing mode)
1065 break;
1066 }
1067
1068 if (which == end_pc_operand) {
1069 return ip + tail_size;
1070 }
1071
1072 #ifdef _LP64
1073 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32");
1074 #else
1075 assert(which == imm_operand, "instruction has only an imm field");
1076 #endif // LP64
1077 return ip;
1078 }
1079
1080 address Assembler::locate_next_instruction(address inst) {
1081 // Secretly share code with locate_operand:
1082 return locate_operand(inst, end_pc_operand);
1083 }
1084
1085
1086 #ifdef ASSERT
1087 void Assembler::check_relocation(RelocationHolder const& rspec, int format) {
1088 address inst = inst_mark();
1089 assert(inst != NULL && inst < pc(), "must point to beginning of instruction");
1090 address opnd;
1091
1092 Relocation* r = rspec.reloc();
1093 if (r->type() == relocInfo::none) {
1094 return;
1095 } else if (r->is_call() || format == call32_operand) {
1096 // assert(format == imm32_operand, "cannot specify a nonzero format");
1097 opnd = locate_operand(inst, call32_operand);
1098 } else if (r->is_data()) {
1099 assert(format == imm_operand || format == disp32_operand
1100 LP64_ONLY(|| format == narrow_oop_operand), "format ok");
1101 opnd = locate_operand(inst, (WhichOperand)format);
1102 } else {
1103 assert(format == imm_operand, "cannot specify a format");
1104 return;
1105 }
1106 assert(opnd == pc(), "must put operand where relocs can find it");
1107 }
1108 #endif // ASSERT
1109
1110 void Assembler::emit_operand32(Register reg, Address adr) {
1111 assert(reg->encoding() < 8, "no extended registers");
1112 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1113 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1114 adr._rspec);
1115 }
1116
1117 void Assembler::emit_operand(Register reg, Address adr,
1118 int rip_relative_correction) {
1119 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1120 adr._rspec,
1121 rip_relative_correction);
1122 }
1123
1124 void Assembler::emit_operand(XMMRegister reg, Address adr) {
1125 if (adr.isxmmindex()) {
1126 emit_operand(reg, adr._base, adr._xmmindex, adr._scale, adr._disp, adr._rspec);
1127 } else {
1128 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1129 adr._rspec);
1130 }
1131 }
1132
1133 // MMX operations
1134 void Assembler::emit_operand(MMXRegister reg, Address adr) {
1135 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1136 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1137 }
1138
1139 // work around gcc (3.2.1-7a) bug
1140 void Assembler::emit_operand(Address adr, MMXRegister reg) {
1141 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1142 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1143 }
1144
1145
1146 void Assembler::emit_farith(int b1, int b2, int i) {
1147 assert(isByte(b1) && isByte(b2), "wrong opcode");
1148 assert(0 <= i && i < 8, "illegal stack offset");
1149 emit_int8(b1);
1150 emit_int8(b2 + i);
1151 }
1152
1153
1154 // Now the Assembler instructions (identical for 32/64 bits)
1155
1156 void Assembler::adcl(Address dst, int32_t imm32) {
1157 InstructionMark im(this);
1158 prefix(dst);
1159 emit_arith_operand(0x81, rdx, dst, imm32);
1160 }
1161
1162 void Assembler::adcl(Address dst, Register src) {
1163 InstructionMark im(this);
1164 prefix(dst, src);
1165 emit_int8(0x11);
1166 emit_operand(src, dst);
1167 }
1168
1169 void Assembler::adcl(Register dst, int32_t imm32) {
1170 prefix(dst);
1171 emit_arith(0x81, 0xD0, dst, imm32);
1172 }
1173
1174 void Assembler::adcl(Register dst, Address src) {
1175 InstructionMark im(this);
1176 prefix(src, dst);
1177 emit_int8(0x13);
1178 emit_operand(dst, src);
1179 }
1180
1181 void Assembler::adcl(Register dst, Register src) {
1182 (void) prefix_and_encode(dst->encoding(), src->encoding());
1183 emit_arith(0x13, 0xC0, dst, src);
1184 }
1185
1186 void Assembler::addl(Address dst, int32_t imm32) {
1187 InstructionMark im(this);
1188 prefix(dst);
1189 emit_arith_operand(0x81, rax, dst, imm32);
1190 }
1191
1192 void Assembler::addb(Address dst, int imm8) {
1193 InstructionMark im(this);
1194 prefix(dst);
1195 emit_int8((unsigned char)0x80);
1196 emit_operand(rax, dst, 1);
1197 emit_int8(imm8);
1198 }
1199
1200 void Assembler::addw(Address dst, int imm16) {
1201 InstructionMark im(this);
1202 emit_int8(0x66);
1203 prefix(dst);
1204 emit_int8((unsigned char)0x81);
1205 emit_operand(rax, dst, 2);
1206 emit_int16(imm16);
1207 }
1208
1209 void Assembler::addl(Address dst, Register src) {
1210 InstructionMark im(this);
1211 prefix(dst, src);
1212 emit_int8(0x01);
1213 emit_operand(src, dst);
1214 }
1215
1216 void Assembler::addl(Register dst, int32_t imm32) {
1217 prefix(dst);
1218 emit_arith(0x81, 0xC0, dst, imm32);
1219 }
1220
1221 void Assembler::addl(Register dst, Address src) {
1222 InstructionMark im(this);
1223 prefix(src, dst);
1224 emit_int8(0x03);
1225 emit_operand(dst, src);
1226 }
1227
1228 void Assembler::addl(Register dst, Register src) {
1229 (void) prefix_and_encode(dst->encoding(), src->encoding());
1230 emit_arith(0x03, 0xC0, dst, src);
1231 }
1232
1233 void Assembler::addr_nop_4() {
1234 assert(UseAddressNop, "no CPU support");
1235 // 4 bytes: NOP DWORD PTR [EAX+0]
1236 emit_int8(0x0F);
1237 emit_int8(0x1F);
1238 emit_int8(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
1239 emit_int8(0); // 8-bits offset (1 byte)
1240 }
1241
1242 void Assembler::addr_nop_5() {
1243 assert(UseAddressNop, "no CPU support");
1244 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
1245 emit_int8(0x0F);
1246 emit_int8(0x1F);
1247 emit_int8(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
1248 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1249 emit_int8(0); // 8-bits offset (1 byte)
1250 }
1251
1252 void Assembler::addr_nop_7() {
1253 assert(UseAddressNop, "no CPU support");
1254 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
1255 emit_int8(0x0F);
1256 emit_int8(0x1F);
1257 emit_int8((unsigned char)0x80);
1258 // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
1259 emit_int32(0); // 32-bits offset (4 bytes)
1260 }
1261
1262 void Assembler::addr_nop_8() {
1263 assert(UseAddressNop, "no CPU support");
1264 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
1265 emit_int8(0x0F);
1266 emit_int8(0x1F);
1267 emit_int8((unsigned char)0x84);
1268 // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
1269 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1270 emit_int32(0); // 32-bits offset (4 bytes)
1271 }
1272
1273 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
1274 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1275 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1276 attributes.set_rex_vex_w_reverted();
1277 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1278 emit_int8(0x58);
1279 emit_int8((unsigned char)(0xC0 | encode));
1280 }
1281
1282 void Assembler::addsd(XMMRegister dst, Address src) {
1283 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1284 InstructionMark im(this);
1285 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1286 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1287 attributes.set_rex_vex_w_reverted();
1288 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1289 emit_int8(0x58);
1290 emit_operand(dst, src);
1291 }
1292
1293 void Assembler::addss(XMMRegister dst, XMMRegister src) {
1294 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1295 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1296 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1297 emit_int8(0x58);
1298 emit_int8((unsigned char)(0xC0 | encode));
1299 }
1300
1301 void Assembler::addss(XMMRegister dst, Address src) {
1302 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1303 InstructionMark im(this);
1304 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1305 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1306 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1307 emit_int8(0x58);
1308 emit_operand(dst, src);
1309 }
1310
1311 void Assembler::aesdec(XMMRegister dst, Address src) {
1312 assert(VM_Version::supports_aes(), "");
1313 InstructionMark im(this);
1314 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1315 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1316 emit_int8((unsigned char)0xDE);
1317 emit_operand(dst, src);
1318 }
1319
1320 void Assembler::aesdec(XMMRegister dst, XMMRegister src) {
1321 assert(VM_Version::supports_aes(), "");
1322 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1323 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1324 emit_int8((unsigned char)0xDE);
1325 emit_int8(0xC0 | encode);
1326 }
1327
1328 void Assembler::vaesdec(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1329 assert(VM_Version::supports_vaes(), "");
1330 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1331 attributes.set_is_evex_instruction();
1332 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1333 emit_int8((unsigned char)0xDE);
1334 emit_int8((unsigned char)(0xC0 | encode));
1335 }
1336
1337
1338 void Assembler::aesdeclast(XMMRegister dst, Address src) {
1339 assert(VM_Version::supports_aes(), "");
1340 InstructionMark im(this);
1341 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1342 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1343 emit_int8((unsigned char)0xDF);
1344 emit_operand(dst, src);
1345 }
1346
1347 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) {
1348 assert(VM_Version::supports_aes(), "");
1349 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1350 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1351 emit_int8((unsigned char)0xDF);
1352 emit_int8((unsigned char)(0xC0 | encode));
1353 }
1354
1355 void Assembler::vaesdeclast(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1356 assert(VM_Version::supports_vaes(), "");
1357 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1358 attributes.set_is_evex_instruction();
1359 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1360 emit_int8((unsigned char)0xDF);
1361 emit_int8((unsigned char)(0xC0 | encode));
1362 }
1363
1364 void Assembler::aesenc(XMMRegister dst, Address src) {
1365 assert(VM_Version::supports_aes(), "");
1366 InstructionMark im(this);
1367 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1368 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1369 emit_int8((unsigned char)0xDC);
1370 emit_operand(dst, src);
1371 }
1372
1373 void Assembler::aesenc(XMMRegister dst, XMMRegister src) {
1374 assert(VM_Version::supports_aes(), "");
1375 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1376 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1377 emit_int8((unsigned char)0xDC);
1378 emit_int8(0xC0 | encode);
1379 }
1380
1381 void Assembler::aesenclast(XMMRegister dst, Address src) {
1382 assert(VM_Version::supports_aes(), "");
1383 InstructionMark im(this);
1384 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1385 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1386 emit_int8((unsigned char)0xDD);
1387 emit_operand(dst, src);
1388 }
1389
1390 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) {
1391 assert(VM_Version::supports_aes(), "");
1392 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1393 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1394 emit_int8((unsigned char)0xDD);
1395 emit_int8((unsigned char)(0xC0 | encode));
1396 }
1397
1398 void Assembler::andl(Address dst, int32_t imm32) {
1399 InstructionMark im(this);
1400 prefix(dst);
1401 emit_int8((unsigned char)0x81);
1402 emit_operand(rsp, dst, 4);
1403 emit_int32(imm32);
1404 }
1405
1406 void Assembler::andl(Register dst, int32_t imm32) {
1407 prefix(dst);
1408 emit_arith(0x81, 0xE0, dst, imm32);
1409 }
1410
1411 void Assembler::andl(Register dst, Address src) {
1412 InstructionMark im(this);
1413 prefix(src, dst);
1414 emit_int8(0x23);
1415 emit_operand(dst, src);
1416 }
1417
1418 void Assembler::andl(Register dst, Register src) {
1419 (void) prefix_and_encode(dst->encoding(), src->encoding());
1420 emit_arith(0x23, 0xC0, dst, src);
1421 }
1422
1423 void Assembler::andnl(Register dst, Register src1, Register src2) {
1424 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1425 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1426 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1427 emit_int8((unsigned char)0xF2);
1428 emit_int8((unsigned char)(0xC0 | encode));
1429 }
1430
1431 void Assembler::andnl(Register dst, Register src1, Address src2) {
1432 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1433 InstructionMark im(this);
1434 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1435 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1436 emit_int8((unsigned char)0xF2);
1437 emit_operand(dst, src2);
1438 }
1439
1440 void Assembler::bsfl(Register dst, Register src) {
1441 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1442 emit_int8(0x0F);
1443 emit_int8((unsigned char)0xBC);
1444 emit_int8((unsigned char)(0xC0 | encode));
1445 }
1446
1447 void Assembler::bsrl(Register dst, Register src) {
1448 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1449 emit_int8(0x0F);
1450 emit_int8((unsigned char)0xBD);
1451 emit_int8((unsigned char)(0xC0 | encode));
1452 }
1453
1454 void Assembler::bswapl(Register reg) { // bswap
1455 int encode = prefix_and_encode(reg->encoding());
1456 emit_int8(0x0F);
1457 emit_int8((unsigned char)(0xC8 | encode));
1458 }
1459
1460 void Assembler::blsil(Register dst, Register src) {
1461 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1462 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1463 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1464 emit_int8((unsigned char)0xF3);
1465 emit_int8((unsigned char)(0xC0 | encode));
1466 }
1467
1468 void Assembler::blsil(Register dst, Address src) {
1469 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1470 InstructionMark im(this);
1471 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1472 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1473 emit_int8((unsigned char)0xF3);
1474 emit_operand(rbx, src);
1475 }
1476
1477 void Assembler::blsmskl(Register dst, Register src) {
1478 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1479 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1480 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1481 emit_int8((unsigned char)0xF3);
1482 emit_int8((unsigned char)(0xC0 | encode));
1483 }
1484
1485 void Assembler::blsmskl(Register dst, Address src) {
1486 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1487 InstructionMark im(this);
1488 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1489 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1490 emit_int8((unsigned char)0xF3);
1491 emit_operand(rdx, src);
1492 }
1493
1494 void Assembler::blsrl(Register dst, Register src) {
1495 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1496 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1497 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1498 emit_int8((unsigned char)0xF3);
1499 emit_int8((unsigned char)(0xC0 | encode));
1500 }
1501
1502 void Assembler::blsrl(Register dst, Address src) {
1503 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1504 InstructionMark im(this);
1505 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1506 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1507 emit_int8((unsigned char)0xF3);
1508 emit_operand(rcx, src);
1509 }
1510
1511 void Assembler::call(Label& L, relocInfo::relocType rtype) {
1512 // suspect disp32 is always good
1513 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
1514
1515 if (L.is_bound()) {
1516 const int long_size = 5;
1517 int offs = (int)( target(L) - pc() );
1518 assert(offs <= 0, "assembler error");
1519 InstructionMark im(this);
1520 // 1110 1000 #32-bit disp
1521 emit_int8((unsigned char)0xE8);
1522 emit_data(offs - long_size, rtype, operand);
1523 } else {
1524 InstructionMark im(this);
1525 // 1110 1000 #32-bit disp
1526 L.add_patch_at(code(), locator());
1527
1528 emit_int8((unsigned char)0xE8);
1529 emit_data(int(0), rtype, operand);
1530 }
1531 }
1532
1533 void Assembler::call(Register dst) {
1534 int encode = prefix_and_encode(dst->encoding());
1535 emit_int8((unsigned char)0xFF);
1536 emit_int8((unsigned char)(0xD0 | encode));
1537 }
1538
1539
1540 void Assembler::call(Address adr) {
1541 InstructionMark im(this);
1542 prefix(adr);
1543 emit_int8((unsigned char)0xFF);
1544 emit_operand(rdx, adr);
1545 }
1546
1547 void Assembler::call_literal(address entry, RelocationHolder const& rspec) {
1548 InstructionMark im(this);
1549 emit_int8((unsigned char)0xE8);
1550 intptr_t disp = entry - (pc() + sizeof(int32_t));
1551 // Entry is NULL in case of a scratch emit.
1552 assert(entry == NULL || is_simm32(disp), "disp=" INTPTR_FORMAT " must be 32bit offset (call2)", disp);
1553 // Technically, should use call32_operand, but this format is
1554 // implied by the fact that we're emitting a call instruction.
1555
1556 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand);
1557 emit_data((int) disp, rspec, operand);
1558 }
1559
1560 void Assembler::cdql() {
1561 emit_int8((unsigned char)0x99);
1562 }
1563
1564 void Assembler::cld() {
1565 emit_int8((unsigned char)0xFC);
1566 }
1567
1568 void Assembler::cmovl(Condition cc, Register dst, Register src) {
1569 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1570 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1571 emit_int8(0x0F);
1572 emit_int8(0x40 | cc);
1573 emit_int8((unsigned char)(0xC0 | encode));
1574 }
1575
1576
1577 void Assembler::cmovl(Condition cc, Register dst, Address src) {
1578 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1579 prefix(src, dst);
1580 emit_int8(0x0F);
1581 emit_int8(0x40 | cc);
1582 emit_operand(dst, src);
1583 }
1584
1585 void Assembler::cmpb(Address dst, int imm8) {
1586 InstructionMark im(this);
1587 prefix(dst);
1588 emit_int8((unsigned char)0x80);
1589 emit_operand(rdi, dst, 1);
1590 emit_int8(imm8);
1591 }
1592
1593 void Assembler::cmpl(Address dst, int32_t imm32) {
1594 InstructionMark im(this);
1595 prefix(dst);
1596 emit_int8((unsigned char)0x81);
1597 emit_operand(rdi, dst, 4);
1598 emit_int32(imm32);
1599 }
1600
1601 void Assembler::cmpl(Register dst, int32_t imm32) {
1602 prefix(dst);
1603 emit_arith(0x81, 0xF8, dst, imm32);
1604 }
1605
1606 void Assembler::cmpl(Register dst, Register src) {
1607 (void) prefix_and_encode(dst->encoding(), src->encoding());
1608 emit_arith(0x3B, 0xC0, dst, src);
1609 }
1610
1611 void Assembler::cmpl(Register dst, Address src) {
1612 InstructionMark im(this);
1613 prefix(src, dst);
1614 emit_int8((unsigned char)0x3B);
1615 emit_operand(dst, src);
1616 }
1617
1618 void Assembler::cmpw(Address dst, int imm16) {
1619 InstructionMark im(this);
1620 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers");
1621 emit_int8(0x66);
1622 emit_int8((unsigned char)0x81);
1623 emit_operand(rdi, dst, 2);
1624 emit_int16(imm16);
1625 }
1626
1627 // The 32-bit cmpxchg compares the value at adr with the contents of rax,
1628 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1629 // The ZF is set if the compared values were equal, and cleared otherwise.
1630 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg
1631 InstructionMark im(this);
1632 prefix(adr, reg);
1633 emit_int8(0x0F);
1634 emit_int8((unsigned char)0xB1);
1635 emit_operand(reg, adr);
1636 }
1637
1638 // The 8-bit cmpxchg compares the value at adr with the contents of rax,
1639 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1640 // The ZF is set if the compared values were equal, and cleared otherwise.
1641 void Assembler::cmpxchgb(Register reg, Address adr) { // cmpxchg
1642 InstructionMark im(this);
1643 prefix(adr, reg, true);
1644 emit_int8(0x0F);
1645 emit_int8((unsigned char)0xB0);
1646 emit_operand(reg, adr);
1647 }
1648
1649 void Assembler::comisd(XMMRegister dst, Address src) {
1650 // NOTE: dbx seems to decode this as comiss even though the
1651 // 0x66 is there. Strangly ucomisd comes out correct
1652 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1653 InstructionMark im(this);
1654 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);;
1655 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1656 attributes.set_rex_vex_w_reverted();
1657 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1658 emit_int8(0x2F);
1659 emit_operand(dst, src);
1660 }
1661
1662 void Assembler::comisd(XMMRegister dst, XMMRegister src) {
1663 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1664 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1665 attributes.set_rex_vex_w_reverted();
1666 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1667 emit_int8(0x2F);
1668 emit_int8((unsigned char)(0xC0 | encode));
1669 }
1670
1671 void Assembler::comiss(XMMRegister dst, Address src) {
1672 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1673 InstructionMark im(this);
1674 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1675 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1676 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1677 emit_int8(0x2F);
1678 emit_operand(dst, src);
1679 }
1680
1681 void Assembler::comiss(XMMRegister dst, XMMRegister src) {
1682 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1683 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1684 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1685 emit_int8(0x2F);
1686 emit_int8((unsigned char)(0xC0 | encode));
1687 }
1688
1689 void Assembler::cpuid() {
1690 emit_int8(0x0F);
1691 emit_int8((unsigned char)0xA2);
1692 }
1693
1694 // Opcode / Instruction Op / En 64 - Bit Mode Compat / Leg Mode Description Implemented
1695 // F2 0F 38 F0 / r CRC32 r32, r / m8 RM Valid Valid Accumulate CRC32 on r / m8. v
1696 // F2 REX 0F 38 F0 / r CRC32 r32, r / m8* RM Valid N.E. Accumulate CRC32 on r / m8. -
1697 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E. Accumulate CRC32 on r / m8. -
1698 //
1699 // F2 0F 38 F1 / r CRC32 r32, r / m16 RM Valid Valid Accumulate CRC32 on r / m16. v
1700 //
1701 // F2 0F 38 F1 / r CRC32 r32, r / m32 RM Valid Valid Accumulate CRC32 on r / m32. v
1702 //
1703 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E. Accumulate CRC32 on r / m64. v
1704 void Assembler::crc32(Register crc, Register v, int8_t sizeInBytes) {
1705 assert(VM_Version::supports_sse4_2(), "");
1706 int8_t w = 0x01;
1707 Prefix p = Prefix_EMPTY;
1708
1709 emit_int8((int8_t)0xF2);
1710 switch (sizeInBytes) {
1711 case 1:
1712 w = 0;
1713 break;
1714 case 2:
1715 case 4:
1716 break;
1717 LP64_ONLY(case 8:)
1718 // This instruction is not valid in 32 bits
1719 // Note:
1720 // http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
1721 //
1722 // Page B - 72 Vol. 2C says
1723 // qwreg2 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : 11 qwreg1 qwreg2
1724 // mem64 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : mod qwreg r / m
1725 // F0!!!
1726 // while 3 - 208 Vol. 2A
1727 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E.Accumulate CRC32 on r / m64.
1728 //
1729 // the 0 on a last bit is reserved for a different flavor of this instruction :
1730 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E.Accumulate CRC32 on r / m8.
1731 p = REX_W;
1732 break;
1733 default:
1734 assert(0, "Unsupported value for a sizeInBytes argument");
1735 break;
1736 }
1737 LP64_ONLY(prefix(crc, v, p);)
1738 emit_int8((int8_t)0x0F);
1739 emit_int8(0x38);
1740 emit_int8((int8_t)(0xF0 | w));
1741 emit_int8(0xC0 | ((crc->encoding() & 0x7) << 3) | (v->encoding() & 7));
1742 }
1743
1744 void Assembler::crc32(Register crc, Address adr, int8_t sizeInBytes) {
1745 assert(VM_Version::supports_sse4_2(), "");
1746 InstructionMark im(this);
1747 int8_t w = 0x01;
1748 Prefix p = Prefix_EMPTY;
1749
1750 emit_int8((int8_t)0xF2);
1751 switch (sizeInBytes) {
1752 case 1:
1753 w = 0;
1754 break;
1755 case 2:
1756 case 4:
1757 break;
1758 LP64_ONLY(case 8:)
1759 // This instruction is not valid in 32 bits
1760 p = REX_W;
1761 break;
1762 default:
1763 assert(0, "Unsupported value for a sizeInBytes argument");
1764 break;
1765 }
1766 LP64_ONLY(prefix(crc, adr, p);)
1767 emit_int8((int8_t)0x0F);
1768 emit_int8(0x38);
1769 emit_int8((int8_t)(0xF0 | w));
1770 emit_operand(crc, adr);
1771 }
1772
1773 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
1774 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1775 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1776 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1777 emit_int8((unsigned char)0xE6);
1778 emit_int8((unsigned char)(0xC0 | encode));
1779 }
1780
1781 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
1782 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1783 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1784 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1785 emit_int8(0x5B);
1786 emit_int8((unsigned char)(0xC0 | encode));
1787 }
1788
1789 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
1790 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1791 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1792 attributes.set_rex_vex_w_reverted();
1793 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1794 emit_int8(0x5A);
1795 emit_int8((unsigned char)(0xC0 | encode));
1796 }
1797
1798 void Assembler::cvtsd2ss(XMMRegister dst, Address src) {
1799 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1800 InstructionMark im(this);
1801 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1802 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1803 attributes.set_rex_vex_w_reverted();
1804 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1805 emit_int8(0x5A);
1806 emit_operand(dst, src);
1807 }
1808
1809 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
1810 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1811 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1812 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1813 emit_int8(0x2A);
1814 emit_int8((unsigned char)(0xC0 | encode));
1815 }
1816
1817 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) {
1818 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1819 InstructionMark im(this);
1820 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1821 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1822 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1823 emit_int8(0x2A);
1824 emit_operand(dst, src);
1825 }
1826
1827 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
1828 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1829 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1830 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1831 emit_int8(0x2A);
1832 emit_int8((unsigned char)(0xC0 | encode));
1833 }
1834
1835 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) {
1836 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1837 InstructionMark im(this);
1838 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1839 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1840 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1841 emit_int8(0x2A);
1842 emit_operand(dst, src);
1843 }
1844
1845 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
1846 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1847 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1848 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1849 emit_int8(0x2A);
1850 emit_int8((unsigned char)(0xC0 | encode));
1851 }
1852
1853 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
1854 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1855 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1856 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1857 emit_int8(0x5A);
1858 emit_int8((unsigned char)(0xC0 | encode));
1859 }
1860
1861 void Assembler::cvtss2sd(XMMRegister dst, Address src) {
1862 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1863 InstructionMark im(this);
1864 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1865 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1866 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1867 emit_int8(0x5A);
1868 emit_operand(dst, src);
1869 }
1870
1871
1872 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
1873 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1874 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1875 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1876 emit_int8(0x2C);
1877 emit_int8((unsigned char)(0xC0 | encode));
1878 }
1879
1880 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
1881 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1882 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1883 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1884 emit_int8(0x2C);
1885 emit_int8((unsigned char)(0xC0 | encode));
1886 }
1887
1888 void Assembler::cvttpd2dq(XMMRegister dst, XMMRegister src) {
1889 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1890 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
1891 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1892 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1893 emit_int8((unsigned char)0xE6);
1894 emit_int8((unsigned char)(0xC0 | encode));
1895 }
1896
1897 void Assembler::decl(Address dst) {
1898 // Don't use it directly. Use MacroAssembler::decrement() instead.
1899 InstructionMark im(this);
1900 prefix(dst);
1901 emit_int8((unsigned char)0xFF);
1902 emit_operand(rcx, dst);
1903 }
1904
1905 void Assembler::divsd(XMMRegister dst, Address src) {
1906 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1907 InstructionMark im(this);
1908 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1909 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1910 attributes.set_rex_vex_w_reverted();
1911 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1912 emit_int8(0x5E);
1913 emit_operand(dst, src);
1914 }
1915
1916 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
1917 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1918 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1919 attributes.set_rex_vex_w_reverted();
1920 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1921 emit_int8(0x5E);
1922 emit_int8((unsigned char)(0xC0 | encode));
1923 }
1924
1925 void Assembler::divss(XMMRegister dst, Address src) {
1926 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1927 InstructionMark im(this);
1928 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1929 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1930 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1931 emit_int8(0x5E);
1932 emit_operand(dst, src);
1933 }
1934
1935 void Assembler::divss(XMMRegister dst, XMMRegister src) {
1936 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1937 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1938 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1939 emit_int8(0x5E);
1940 emit_int8((unsigned char)(0xC0 | encode));
1941 }
1942
1943 void Assembler::emms() {
1944 NOT_LP64(assert(VM_Version::supports_mmx(), ""));
1945 emit_int8(0x0F);
1946 emit_int8(0x77);
1947 }
1948
1949 void Assembler::hlt() {
1950 emit_int8((unsigned char)0xF4);
1951 }
1952
1953 void Assembler::idivl(Register src) {
1954 int encode = prefix_and_encode(src->encoding());
1955 emit_int8((unsigned char)0xF7);
1956 emit_int8((unsigned char)(0xF8 | encode));
1957 }
1958
1959 void Assembler::divl(Register src) { // Unsigned
1960 int encode = prefix_and_encode(src->encoding());
1961 emit_int8((unsigned char)0xF7);
1962 emit_int8((unsigned char)(0xF0 | encode));
1963 }
1964
1965 void Assembler::imull(Register src) {
1966 int encode = prefix_and_encode(src->encoding());
1967 emit_int8((unsigned char)0xF7);
1968 emit_int8((unsigned char)(0xE8 | encode));
1969 }
1970
1971 void Assembler::imull(Register dst, Register src) {
1972 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1973 emit_int8(0x0F);
1974 emit_int8((unsigned char)0xAF);
1975 emit_int8((unsigned char)(0xC0 | encode));
1976 }
1977
1978
1979 void Assembler::imull(Register dst, Register src, int value) {
1980 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1981 if (is8bit(value)) {
1982 emit_int8(0x6B);
1983 emit_int8((unsigned char)(0xC0 | encode));
1984 emit_int8(value & 0xFF);
1985 } else {
1986 emit_int8(0x69);
1987 emit_int8((unsigned char)(0xC0 | encode));
1988 emit_int32(value);
1989 }
1990 }
1991
1992 void Assembler::imull(Register dst, Address src) {
1993 InstructionMark im(this);
1994 prefix(src, dst);
1995 emit_int8(0x0F);
1996 emit_int8((unsigned char) 0xAF);
1997 emit_operand(dst, src);
1998 }
1999
2000
2001 void Assembler::incl(Address dst) {
2002 // Don't use it directly. Use MacroAssembler::increment() instead.
2003 InstructionMark im(this);
2004 prefix(dst);
2005 emit_int8((unsigned char)0xFF);
2006 emit_operand(rax, dst);
2007 }
2008
2009 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) {
2010 InstructionMark im(this);
2011 assert((0 <= cc) && (cc < 16), "illegal cc");
2012 if (L.is_bound()) {
2013 address dst = target(L);
2014 assert(dst != NULL, "jcc most probably wrong");
2015
2016 const int short_size = 2;
2017 const int long_size = 6;
2018 intptr_t offs = (intptr_t)dst - (intptr_t)pc();
2019 if (maybe_short && is8bit(offs - short_size)) {
2020 // 0111 tttn #8-bit disp
2021 emit_int8(0x70 | cc);
2022 emit_int8((offs - short_size) & 0xFF);
2023 } else {
2024 // 0000 1111 1000 tttn #32-bit disp
2025 assert(is_simm32(offs - long_size),
2026 "must be 32bit offset (call4)");
2027 emit_int8(0x0F);
2028 emit_int8((unsigned char)(0x80 | cc));
2029 emit_int32(offs - long_size);
2030 }
2031 } else {
2032 // Note: could eliminate cond. jumps to this jump if condition
2033 // is the same however, seems to be rather unlikely case.
2034 // Note: use jccb() if label to be bound is very close to get
2035 // an 8-bit displacement
2036 L.add_patch_at(code(), locator());
2037 emit_int8(0x0F);
2038 emit_int8((unsigned char)(0x80 | cc));
2039 emit_int32(0);
2040 }
2041 }
2042
2043 void Assembler::jccb_0(Condition cc, Label& L, const char* file, int line) {
2044 if (L.is_bound()) {
2045 const int short_size = 2;
2046 address entry = target(L);
2047 #ifdef ASSERT
2048 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
2049 intptr_t delta = short_branch_delta();
2050 if (delta != 0) {
2051 dist += (dist < 0 ? (-delta) :delta);
2052 }
2053 assert(is8bit(dist), "Dispacement too large for a short jmp at %s:%d", file, line);
2054 #endif
2055 intptr_t offs = (intptr_t)entry - (intptr_t)pc();
2056 // 0111 tttn #8-bit disp
2057 emit_int8(0x70 | cc);
2058 emit_int8((offs - short_size) & 0xFF);
2059 } else {
2060 InstructionMark im(this);
2061 L.add_patch_at(code(), locator(), file, line);
2062 emit_int8(0x70 | cc);
2063 emit_int8(0);
2064 }
2065 }
2066
2067 void Assembler::jmp(Address adr) {
2068 InstructionMark im(this);
2069 prefix(adr);
2070 emit_int8((unsigned char)0xFF);
2071 emit_operand(rsp, adr);
2072 }
2073
2074 void Assembler::jmp(Label& L, bool maybe_short) {
2075 if (L.is_bound()) {
2076 address entry = target(L);
2077 assert(entry != NULL, "jmp most probably wrong");
2078 InstructionMark im(this);
2079 const int short_size = 2;
2080 const int long_size = 5;
2081 intptr_t offs = entry - pc();
2082 if (maybe_short && is8bit(offs - short_size)) {
2083 emit_int8((unsigned char)0xEB);
2084 emit_int8((offs - short_size) & 0xFF);
2085 } else {
2086 emit_int8((unsigned char)0xE9);
2087 emit_int32(offs - long_size);
2088 }
2089 } else {
2090 // By default, forward jumps are always 32-bit displacements, since
2091 // we can't yet know where the label will be bound. If you're sure that
2092 // the forward jump will not run beyond 256 bytes, use jmpb to
2093 // force an 8-bit displacement.
2094 InstructionMark im(this);
2095 L.add_patch_at(code(), locator());
2096 emit_int8((unsigned char)0xE9);
2097 emit_int32(0);
2098 }
2099 }
2100
2101 void Assembler::jmp(Register entry) {
2102 int encode = prefix_and_encode(entry->encoding());
2103 emit_int8((unsigned char)0xFF);
2104 emit_int8((unsigned char)(0xE0 | encode));
2105 }
2106
2107 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
2108 InstructionMark im(this);
2109 emit_int8((unsigned char)0xE9);
2110 assert(dest != NULL, "must have a target");
2111 intptr_t disp = dest - (pc() + sizeof(int32_t));
2112 assert(is_simm32(disp), "must be 32bit offset (jmp)");
2113 emit_data(disp, rspec.reloc(), call32_operand);
2114 }
2115
2116 void Assembler::jmpb_0(Label& L, const char* file, int line) {
2117 if (L.is_bound()) {
2118 const int short_size = 2;
2119 address entry = target(L);
2120 assert(entry != NULL, "jmp most probably wrong");
2121 #ifdef ASSERT
2122 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
2123 intptr_t delta = short_branch_delta();
2124 if (delta != 0) {
2125 dist += (dist < 0 ? (-delta) :delta);
2126 }
2127 assert(is8bit(dist), "Dispacement too large for a short jmp at %s:%d", file, line);
2128 #endif
2129 intptr_t offs = entry - pc();
2130 emit_int8((unsigned char)0xEB);
2131 emit_int8((offs - short_size) & 0xFF);
2132 } else {
2133 InstructionMark im(this);
2134 L.add_patch_at(code(), locator(), file, line);
2135 emit_int8((unsigned char)0xEB);
2136 emit_int8(0);
2137 }
2138 }
2139
2140 void Assembler::ldmxcsr( Address src) {
2141 if (UseAVX > 0 ) {
2142 InstructionMark im(this);
2143 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2144 vex_prefix(src, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2145 emit_int8((unsigned char)0xAE);
2146 emit_operand(as_Register(2), src);
2147 } else {
2148 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2149 InstructionMark im(this);
2150 prefix(src);
2151 emit_int8(0x0F);
2152 emit_int8((unsigned char)0xAE);
2153 emit_operand(as_Register(2), src);
2154 }
2155 }
2156
2157 void Assembler::leal(Register dst, Address src) {
2158 InstructionMark im(this);
2159 #ifdef _LP64
2160 emit_int8(0x67); // addr32
2161 prefix(src, dst);
2162 #endif // LP64
2163 emit_int8((unsigned char)0x8D);
2164 emit_operand(dst, src);
2165 }
2166
2167 void Assembler::lfence() {
2168 emit_int8(0x0F);
2169 emit_int8((unsigned char)0xAE);
2170 emit_int8((unsigned char)0xE8);
2171 }
2172
2173 void Assembler::lock() {
2174 emit_int8((unsigned char)0xF0);
2175 }
2176
2177 void Assembler::lzcntl(Register dst, Register src) {
2178 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
2179 emit_int8((unsigned char)0xF3);
2180 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2181 emit_int8(0x0F);
2182 emit_int8((unsigned char)0xBD);
2183 emit_int8((unsigned char)(0xC0 | encode));
2184 }
2185
2186 // Emit mfence instruction
2187 void Assembler::mfence() {
2188 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
2189 emit_int8(0x0F);
2190 emit_int8((unsigned char)0xAE);
2191 emit_int8((unsigned char)0xF0);
2192 }
2193
2194 void Assembler::mov(Register dst, Register src) {
2195 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2196 }
2197
2198 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
2199 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2200 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2201 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2202 attributes.set_rex_vex_w_reverted();
2203 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2204 emit_int8(0x28);
2205 emit_int8((unsigned char)(0xC0 | encode));
2206 }
2207
2208 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
2209 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2210 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2211 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2212 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2213 emit_int8(0x28);
2214 emit_int8((unsigned char)(0xC0 | encode));
2215 }
2216
2217 void Assembler::movlhps(XMMRegister dst, XMMRegister src) {
2218 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2219 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2220 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2221 emit_int8(0x16);
2222 emit_int8((unsigned char)(0xC0 | encode));
2223 }
2224
2225 void Assembler::movb(Register dst, Address src) {
2226 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
2227 InstructionMark im(this);
2228 prefix(src, dst, true);
2229 emit_int8((unsigned char)0x8A);
2230 emit_operand(dst, src);
2231 }
2232
2233 void Assembler::movddup(XMMRegister dst, XMMRegister src) {
2234 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
2235 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2236 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2237 attributes.set_rex_vex_w_reverted();
2238 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2239 emit_int8(0x12);
2240 emit_int8(0xC0 | encode);
2241 }
2242
2243 void Assembler::kmovbl(KRegister dst, Register src) {
2244 assert(VM_Version::supports_avx512dq(), "");
2245 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2246 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2247 emit_int8((unsigned char)0x92);
2248 emit_int8((unsigned char)(0xC0 | encode));
2249 }
2250
2251 void Assembler::kmovbl(Register dst, KRegister src) {
2252 assert(VM_Version::supports_avx512dq(), "");
2253 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2254 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2255 emit_int8((unsigned char)0x93);
2256 emit_int8((unsigned char)(0xC0 | encode));
2257 }
2258
2259 void Assembler::kmovwl(KRegister dst, Register src) {
2260 assert(VM_Version::supports_evex(), "");
2261 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2262 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2263 emit_int8((unsigned char)0x92);
2264 emit_int8((unsigned char)(0xC0 | encode));
2265 }
2266
2267 void Assembler::kmovwl(Register dst, KRegister src) {
2268 assert(VM_Version::supports_evex(), "");
2269 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2270 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2271 emit_int8((unsigned char)0x93);
2272 emit_int8((unsigned char)(0xC0 | encode));
2273 }
2274
2275 void Assembler::kmovwl(KRegister dst, Address src) {
2276 assert(VM_Version::supports_evex(), "");
2277 InstructionMark im(this);
2278 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2279 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2280 emit_int8((unsigned char)0x90);
2281 emit_operand((Register)dst, src);
2282 }
2283
2284 void Assembler::kmovdl(KRegister dst, Register src) {
2285 assert(VM_Version::supports_avx512bw(), "");
2286 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2287 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2288 emit_int8((unsigned char)0x92);
2289 emit_int8((unsigned char)(0xC0 | encode));
2290 }
2291
2292 void Assembler::kmovdl(Register dst, KRegister src) {
2293 assert(VM_Version::supports_avx512bw(), "");
2294 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2295 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2296 emit_int8((unsigned char)0x93);
2297 emit_int8((unsigned char)(0xC0 | encode));
2298 }
2299
2300 void Assembler::kmovql(KRegister dst, KRegister src) {
2301 assert(VM_Version::supports_avx512bw(), "");
2302 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2303 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2304 emit_int8((unsigned char)0x90);
2305 emit_int8((unsigned char)(0xC0 | encode));
2306 }
2307
2308 void Assembler::kmovql(KRegister dst, Address src) {
2309 assert(VM_Version::supports_avx512bw(), "");
2310 InstructionMark im(this);
2311 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2312 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2313 emit_int8((unsigned char)0x90);
2314 emit_operand((Register)dst, src);
2315 }
2316
2317 void Assembler::kmovql(Address dst, KRegister src) {
2318 assert(VM_Version::supports_avx512bw(), "");
2319 InstructionMark im(this);
2320 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2321 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2322 emit_int8((unsigned char)0x90);
2323 emit_operand((Register)src, dst);
2324 }
2325
2326 void Assembler::kmovql(KRegister dst, Register src) {
2327 assert(VM_Version::supports_avx512bw(), "");
2328 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2329 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2330 emit_int8((unsigned char)0x92);
2331 emit_int8((unsigned char)(0xC0 | encode));
2332 }
2333
2334 void Assembler::kmovql(Register dst, KRegister src) {
2335 assert(VM_Version::supports_avx512bw(), "");
2336 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2337 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2338 emit_int8((unsigned char)0x93);
2339 emit_int8((unsigned char)(0xC0 | encode));
2340 }
2341
2342 void Assembler::knotwl(KRegister dst, KRegister src) {
2343 assert(VM_Version::supports_evex(), "");
2344 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2345 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2346 emit_int8((unsigned char)0x44);
2347 emit_int8((unsigned char)(0xC0 | encode));
2348 }
2349
2350 // This instruction produces ZF or CF flags
2351 void Assembler::kortestbl(KRegister src1, KRegister src2) {
2352 assert(VM_Version::supports_avx512dq(), "");
2353 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2354 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2355 emit_int8((unsigned char)0x98);
2356 emit_int8((unsigned char)(0xC0 | encode));
2357 }
2358
2359 // This instruction produces ZF or CF flags
2360 void Assembler::kortestwl(KRegister src1, KRegister src2) {
2361 assert(VM_Version::supports_evex(), "");
2362 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2363 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2364 emit_int8((unsigned char)0x98);
2365 emit_int8((unsigned char)(0xC0 | encode));
2366 }
2367
2368 // This instruction produces ZF or CF flags
2369 void Assembler::kortestdl(KRegister src1, KRegister src2) {
2370 assert(VM_Version::supports_avx512bw(), "");
2371 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2372 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2373 emit_int8((unsigned char)0x98);
2374 emit_int8((unsigned char)(0xC0 | encode));
2375 }
2376
2377 // This instruction produces ZF or CF flags
2378 void Assembler::kortestql(KRegister src1, KRegister src2) {
2379 assert(VM_Version::supports_avx512bw(), "");
2380 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2381 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2382 emit_int8((unsigned char)0x98);
2383 emit_int8((unsigned char)(0xC0 | encode));
2384 }
2385
2386 // This instruction produces ZF or CF flags
2387 void Assembler::ktestql(KRegister src1, KRegister src2) {
2388 assert(VM_Version::supports_avx512bw(), "");
2389 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2390 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2391 emit_int8((unsigned char)0x99);
2392 emit_int8((unsigned char)(0xC0 | encode));
2393 }
2394
2395 void Assembler::ktestq(KRegister src1, KRegister src2) {
2396 assert(VM_Version::supports_avx512bw(), "");
2397 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2398 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2399 emit_int8((unsigned char)0x99);
2400 emit_int8((unsigned char)(0xC0 | encode));
2401 }
2402
2403 void Assembler::ktestd(KRegister src1, KRegister src2) {
2404 assert(VM_Version::supports_avx512bw(), "");
2405 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2406 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2407 emit_int8((unsigned char)0x99);
2408 emit_int8((unsigned char)(0xC0 | encode));
2409 }
2410
2411 void Assembler::movb(Address dst, int imm8) {
2412 InstructionMark im(this);
2413 prefix(dst);
2414 emit_int8((unsigned char)0xC6);
2415 emit_operand(rax, dst, 1);
2416 emit_int8(imm8);
2417 }
2418
2419
2420 void Assembler::movb(Address dst, Register src) {
2421 assert(src->has_byte_register(), "must have byte register");
2422 InstructionMark im(this);
2423 prefix(dst, src, true);
2424 emit_int8((unsigned char)0x88);
2425 emit_operand(src, dst);
2426 }
2427
2428 void Assembler::movdl(XMMRegister dst, Register src) {
2429 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2430 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2431 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2432 emit_int8(0x6E);
2433 emit_int8((unsigned char)(0xC0 | encode));
2434 }
2435
2436 void Assembler::movdl(Register dst, XMMRegister src) {
2437 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2438 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2439 // swap src/dst to get correct prefix
2440 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2441 emit_int8(0x7E);
2442 emit_int8((unsigned char)(0xC0 | encode));
2443 }
2444
2445 void Assembler::movdl(XMMRegister dst, Address src) {
2446 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2447 InstructionMark im(this);
2448 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2449 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2450 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2451 emit_int8(0x6E);
2452 emit_operand(dst, src);
2453 }
2454
2455 void Assembler::movdl(Address dst, XMMRegister src) {
2456 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2457 InstructionMark im(this);
2458 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2459 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2460 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2461 emit_int8(0x7E);
2462 emit_operand(src, dst);
2463 }
2464
2465 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
2466 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2467 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2468 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2469 emit_int8(0x6F);
2470 emit_int8((unsigned char)(0xC0 | encode));
2471 }
2472
2473 void Assembler::movdqa(XMMRegister dst, Address src) {
2474 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2475 InstructionMark im(this);
2476 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2477 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2478 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2479 emit_int8(0x6F);
2480 emit_operand(dst, src);
2481 }
2482
2483 void Assembler::movdqu(XMMRegister dst, Address src) {
2484 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2485 InstructionMark im(this);
2486 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2487 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2488 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2489 emit_int8(0x6F);
2490 emit_operand(dst, src);
2491 }
2492
2493 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
2494 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2495 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2496 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2497 emit_int8(0x6F);
2498 emit_int8((unsigned char)(0xC0 | encode));
2499 }
2500
2501 void Assembler::movdqu(Address dst, XMMRegister src) {
2502 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2503 InstructionMark im(this);
2504 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2505 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2506 attributes.reset_is_clear_context();
2507 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2508 emit_int8(0x7F);
2509 emit_operand(src, dst);
2510 }
2511
2512 // Move Unaligned 256bit Vector
2513 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2514 assert(UseAVX > 0, "");
2515 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2516 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2517 emit_int8(0x6F);
2518 emit_int8((unsigned char)(0xC0 | encode));
2519 }
2520
2521 void Assembler::vmovdqu(XMMRegister dst, Address src) {
2522 assert(UseAVX > 0, "");
2523 InstructionMark im(this);
2524 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2525 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2526 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2527 emit_int8(0x6F);
2528 emit_operand(dst, src);
2529 }
2530
2531 void Assembler::vmovdqu(Address dst, XMMRegister src) {
2532 assert(UseAVX > 0, "");
2533 InstructionMark im(this);
2534 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2535 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2536 attributes.reset_is_clear_context();
2537 // swap src<->dst for encoding
2538 assert(src != xnoreg, "sanity");
2539 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2540 emit_int8(0x7F);
2541 emit_operand(src, dst);
2542 }
2543
2544 // Move Unaligned EVEX enabled Vector (programmable : 8,16,32,64)
2545 void Assembler::evmovdqub(XMMRegister dst, XMMRegister src, int vector_len) {
2546 assert(VM_Version::supports_evex(), "");
2547 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2548 attributes.set_is_evex_instruction();
2549 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2550 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2551 emit_int8(0x6F);
2552 emit_int8((unsigned char)(0xC0 | encode));
2553 }
2554
2555 void Assembler::evmovdqub(XMMRegister dst, Address src, int vector_len) {
2556 assert(VM_Version::supports_evex(), "");
2557 InstructionMark im(this);
2558 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2559 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2560 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2561 attributes.set_is_evex_instruction();
2562 vex_prefix(src, 0, dst->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2563 emit_int8(0x6F);
2564 emit_operand(dst, src);
2565 }
2566
2567 void Assembler::evmovdqub(Address dst, XMMRegister src, int vector_len) {
2568 assert(VM_Version::supports_evex(), "");
2569 assert(src != xnoreg, "sanity");
2570 InstructionMark im(this);
2571 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2572 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2573 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2574 attributes.set_is_evex_instruction();
2575 vex_prefix(dst, 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2576 emit_int8(0x7F);
2577 emit_operand(src, dst);
2578 }
2579
2580 void Assembler::evmovdqub(XMMRegister dst, KRegister mask, Address src, int vector_len) {
2581 assert(VM_Version::supports_avx512vlbw(), "");
2582 InstructionMark im(this);
2583 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2584 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2585 attributes.set_embedded_opmask_register_specifier(mask);
2586 attributes.set_is_evex_instruction();
2587 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2588 emit_int8(0x6F);
2589 emit_operand(dst, src);
2590 }
2591
2592 void Assembler::evmovdquw(XMMRegister dst, Address src, int vector_len) {
2593 assert(VM_Version::supports_evex(), "");
2594 InstructionMark im(this);
2595 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2596 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2597 attributes.set_is_evex_instruction();
2598 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2599 vex_prefix(src, 0, dst->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2600 emit_int8(0x6F);
2601 emit_operand(dst, src);
2602 }
2603
2604 void Assembler::evmovdquw(XMMRegister dst, KRegister mask, Address src, int vector_len) {
2605 assert(VM_Version::supports_avx512vlbw(), "");
2606 InstructionMark im(this);
2607 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2608 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2609 attributes.set_embedded_opmask_register_specifier(mask);
2610 attributes.set_is_evex_instruction();
2611 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2612 emit_int8(0x6F);
2613 emit_operand(dst, src);
2614 }
2615
2616 void Assembler::evmovdquw(Address dst, XMMRegister src, int vector_len) {
2617 assert(VM_Version::supports_evex(), "");
2618 assert(src != xnoreg, "sanity");
2619 InstructionMark im(this);
2620 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2621 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2622 attributes.set_is_evex_instruction();
2623 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2624 vex_prefix(dst, 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2625 emit_int8(0x7F);
2626 emit_operand(src, dst);
2627 }
2628
2629 void Assembler::evmovdquw(Address dst, KRegister mask, XMMRegister src, int vector_len) {
2630 assert(VM_Version::supports_avx512vlbw(), "");
2631 assert(src != xnoreg, "sanity");
2632 InstructionMark im(this);
2633 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2634 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2635 attributes.reset_is_clear_context();
2636 attributes.set_embedded_opmask_register_specifier(mask);
2637 attributes.set_is_evex_instruction();
2638 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2639 emit_int8(0x7F);
2640 emit_operand(src, dst);
2641 }
2642
2643 void Assembler::evmovdqul(XMMRegister dst, XMMRegister src, int vector_len) {
2644 assert(VM_Version::supports_evex(), "");
2645 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2646 attributes.set_is_evex_instruction();
2647 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2648 emit_int8(0x6F);
2649 emit_int8((unsigned char)(0xC0 | encode));
2650 }
2651
2652 void Assembler::evmovdqul(XMMRegister dst, Address src, int vector_len) {
2653 assert(VM_Version::supports_evex(), "");
2654 InstructionMark im(this);
2655 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true , /* uses_vl */ true);
2656 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2657 attributes.set_is_evex_instruction();
2658 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2659 emit_int8(0x6F);
2660 emit_operand(dst, src);
2661 }
2662
2663 void Assembler::evmovdqul(Address dst, XMMRegister src, int vector_len) {
2664 assert(VM_Version::supports_evex(), "");
2665 assert(src != xnoreg, "sanity");
2666 InstructionMark im(this);
2667 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2668 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2669 attributes.reset_is_clear_context();
2670 attributes.set_is_evex_instruction();
2671 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2672 emit_int8(0x7F);
2673 emit_operand(src, dst);
2674 }
2675
2676 void Assembler::evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) {
2677 assert(VM_Version::supports_evex(), "");
2678 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2679 attributes.set_is_evex_instruction();
2680 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2681 emit_int8(0x6F);
2682 emit_int8((unsigned char)(0xC0 | encode));
2683 }
2684
2685 void Assembler::evmovdquq(XMMRegister dst, Address src, int vector_len) {
2686 assert(VM_Version::supports_evex(), "");
2687 InstructionMark im(this);
2688 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2689 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2690 attributes.set_is_evex_instruction();
2691 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2692 emit_int8(0x6F);
2693 emit_operand(dst, src);
2694 }
2695
2696 void Assembler::evmovdquq(Address dst, XMMRegister src, int vector_len) {
2697 assert(VM_Version::supports_evex(), "");
2698 assert(src != xnoreg, "sanity");
2699 InstructionMark im(this);
2700 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2701 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2702 attributes.reset_is_clear_context();
2703 attributes.set_is_evex_instruction();
2704 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2705 emit_int8(0x7F);
2706 emit_operand(src, dst);
2707 }
2708
2709 // Uses zero extension on 64bit
2710
2711 void Assembler::movl(Register dst, int32_t imm32) {
2712 int encode = prefix_and_encode(dst->encoding());
2713 emit_int8((unsigned char)(0xB8 | encode));
2714 emit_int32(imm32);
2715 }
2716
2717 void Assembler::movl(Register dst, Register src) {
2718 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2719 emit_int8((unsigned char)0x8B);
2720 emit_int8((unsigned char)(0xC0 | encode));
2721 }
2722
2723 void Assembler::movl(Register dst, Address src) {
2724 InstructionMark im(this);
2725 prefix(src, dst);
2726 emit_int8((unsigned char)0x8B);
2727 emit_operand(dst, src);
2728 }
2729
2730 void Assembler::movl(Address dst, int32_t imm32) {
2731 InstructionMark im(this);
2732 prefix(dst);
2733 emit_int8((unsigned char)0xC7);
2734 emit_operand(rax, dst, 4);
2735 emit_int32(imm32);
2736 }
2737
2738 void Assembler::movl(Address dst, Register src) {
2739 InstructionMark im(this);
2740 prefix(dst, src);
2741 emit_int8((unsigned char)0x89);
2742 emit_operand(src, dst);
2743 }
2744
2745 // New cpus require to use movsd and movss to avoid partial register stall
2746 // when loading from memory. But for old Opteron use movlpd instead of movsd.
2747 // The selection is done in MacroAssembler::movdbl() and movflt().
2748 void Assembler::movlpd(XMMRegister dst, Address src) {
2749 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2750 InstructionMark im(this);
2751 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2752 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2753 attributes.set_rex_vex_w_reverted();
2754 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2755 emit_int8(0x12);
2756 emit_operand(dst, src);
2757 }
2758
2759 void Assembler::movq( MMXRegister dst, Address src ) {
2760 assert( VM_Version::supports_mmx(), "" );
2761 emit_int8(0x0F);
2762 emit_int8(0x6F);
2763 emit_operand(dst, src);
2764 }
2765
2766 void Assembler::movq( Address dst, MMXRegister src ) {
2767 assert( VM_Version::supports_mmx(), "" );
2768 emit_int8(0x0F);
2769 emit_int8(0x7F);
2770 // workaround gcc (3.2.1-7a) bug
2771 // In that version of gcc with only an emit_operand(MMX, Address)
2772 // gcc will tail jump and try and reverse the parameters completely
2773 // obliterating dst in the process. By having a version available
2774 // that doesn't need to swap the args at the tail jump the bug is
2775 // avoided.
2776 emit_operand(dst, src);
2777 }
2778
2779 void Assembler::movq(XMMRegister dst, Address src) {
2780 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2781 InstructionMark im(this);
2782 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2783 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2784 attributes.set_rex_vex_w_reverted();
2785 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2786 emit_int8(0x7E);
2787 emit_operand(dst, src);
2788 }
2789
2790 void Assembler::movq(Address dst, XMMRegister src) {
2791 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2792 InstructionMark im(this);
2793 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2794 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2795 attributes.set_rex_vex_w_reverted();
2796 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2797 emit_int8((unsigned char)0xD6);
2798 emit_operand(src, dst);
2799 }
2800
2801 void Assembler::movsbl(Register dst, Address src) { // movsxb
2802 InstructionMark im(this);
2803 prefix(src, dst);
2804 emit_int8(0x0F);
2805 emit_int8((unsigned char)0xBE);
2806 emit_operand(dst, src);
2807 }
2808
2809 void Assembler::movsbl(Register dst, Register src) { // movsxb
2810 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2811 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
2812 emit_int8(0x0F);
2813 emit_int8((unsigned char)0xBE);
2814 emit_int8((unsigned char)(0xC0 | encode));
2815 }
2816
2817 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
2818 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2819 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2820 attributes.set_rex_vex_w_reverted();
2821 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2822 emit_int8(0x10);
2823 emit_int8((unsigned char)(0xC0 | encode));
2824 }
2825
2826 void Assembler::movsd(XMMRegister dst, Address src) {
2827 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2828 InstructionMark im(this);
2829 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2830 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2831 attributes.set_rex_vex_w_reverted();
2832 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2833 emit_int8(0x10);
2834 emit_operand(dst, src);
2835 }
2836
2837 void Assembler::movsd(Address dst, XMMRegister src) {
2838 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2839 InstructionMark im(this);
2840 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2841 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2842 attributes.reset_is_clear_context();
2843 attributes.set_rex_vex_w_reverted();
2844 simd_prefix(src, xnoreg, dst, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2845 emit_int8(0x11);
2846 emit_operand(src, dst);
2847 }
2848
2849 void Assembler::movss(XMMRegister dst, XMMRegister src) {
2850 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2851 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2852 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2853 emit_int8(0x10);
2854 emit_int8((unsigned char)(0xC0 | encode));
2855 }
2856
2857 void Assembler::movss(XMMRegister dst, Address src) {
2858 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2859 InstructionMark im(this);
2860 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2861 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2862 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2863 emit_int8(0x10);
2864 emit_operand(dst, src);
2865 }
2866
2867 void Assembler::movss(Address dst, XMMRegister src) {
2868 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2869 InstructionMark im(this);
2870 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2871 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2872 attributes.reset_is_clear_context();
2873 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2874 emit_int8(0x11);
2875 emit_operand(src, dst);
2876 }
2877
2878 void Assembler::movswl(Register dst, Address src) { // movsxw
2879 InstructionMark im(this);
2880 prefix(src, dst);
2881 emit_int8(0x0F);
2882 emit_int8((unsigned char)0xBF);
2883 emit_operand(dst, src);
2884 }
2885
2886 void Assembler::movswl(Register dst, Register src) { // movsxw
2887 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2888 emit_int8(0x0F);
2889 emit_int8((unsigned char)0xBF);
2890 emit_int8((unsigned char)(0xC0 | encode));
2891 }
2892
2893 void Assembler::movw(Address dst, int imm16) {
2894 InstructionMark im(this);
2895
2896 emit_int8(0x66); // switch to 16-bit mode
2897 prefix(dst);
2898 emit_int8((unsigned char)0xC7);
2899 emit_operand(rax, dst, 2);
2900 emit_int16(imm16);
2901 }
2902
2903 void Assembler::movw(Register dst, Address src) {
2904 InstructionMark im(this);
2905 emit_int8(0x66);
2906 prefix(src, dst);
2907 emit_int8((unsigned char)0x8B);
2908 emit_operand(dst, src);
2909 }
2910
2911 void Assembler::movw(Address dst, Register src) {
2912 InstructionMark im(this);
2913 emit_int8(0x66);
2914 prefix(dst, src);
2915 emit_int8((unsigned char)0x89);
2916 emit_operand(src, dst);
2917 }
2918
2919 void Assembler::movzbl(Register dst, Address src) { // movzxb
2920 InstructionMark im(this);
2921 prefix(src, dst);
2922 emit_int8(0x0F);
2923 emit_int8((unsigned char)0xB6);
2924 emit_operand(dst, src);
2925 }
2926
2927 void Assembler::movzbl(Register dst, Register src) { // movzxb
2928 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2929 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
2930 emit_int8(0x0F);
2931 emit_int8((unsigned char)0xB6);
2932 emit_int8(0xC0 | encode);
2933 }
2934
2935 void Assembler::movzwl(Register dst, Address src) { // movzxw
2936 InstructionMark im(this);
2937 prefix(src, dst);
2938 emit_int8(0x0F);
2939 emit_int8((unsigned char)0xB7);
2940 emit_operand(dst, src);
2941 }
2942
2943 void Assembler::movzwl(Register dst, Register src) { // movzxw
2944 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2945 emit_int8(0x0F);
2946 emit_int8((unsigned char)0xB7);
2947 emit_int8(0xC0 | encode);
2948 }
2949
2950 void Assembler::mull(Address src) {
2951 InstructionMark im(this);
2952 prefix(src);
2953 emit_int8((unsigned char)0xF7);
2954 emit_operand(rsp, src);
2955 }
2956
2957 void Assembler::mull(Register src) {
2958 int encode = prefix_and_encode(src->encoding());
2959 emit_int8((unsigned char)0xF7);
2960 emit_int8((unsigned char)(0xE0 | encode));
2961 }
2962
2963 void Assembler::mulsd(XMMRegister dst, Address src) {
2964 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2965 InstructionMark im(this);
2966 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2967 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2968 attributes.set_rex_vex_w_reverted();
2969 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2970 emit_int8(0x59);
2971 emit_operand(dst, src);
2972 }
2973
2974 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
2975 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2976 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2977 attributes.set_rex_vex_w_reverted();
2978 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2979 emit_int8(0x59);
2980 emit_int8((unsigned char)(0xC0 | encode));
2981 }
2982
2983 void Assembler::mulss(XMMRegister dst, Address src) {
2984 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2985 InstructionMark im(this);
2986 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2987 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2988 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2989 emit_int8(0x59);
2990 emit_operand(dst, src);
2991 }
2992
2993 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
2994 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2995 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2996 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2997 emit_int8(0x59);
2998 emit_int8((unsigned char)(0xC0 | encode));
2999 }
3000
3001 void Assembler::negl(Register dst) {
3002 int encode = prefix_and_encode(dst->encoding());
3003 emit_int8((unsigned char)0xF7);
3004 emit_int8((unsigned char)(0xD8 | encode));
3005 }
3006
3007 void Assembler::nop(int i) {
3008 #ifdef ASSERT
3009 assert(i > 0, " ");
3010 // The fancy nops aren't currently recognized by debuggers making it a
3011 // pain to disassemble code while debugging. If asserts are on clearly
3012 // speed is not an issue so simply use the single byte traditional nop
3013 // to do alignment.
3014
3015 for (; i > 0 ; i--) emit_int8((unsigned char)0x90);
3016 return;
3017
3018 #endif // ASSERT
3019
3020 if (UseAddressNop && VM_Version::is_intel()) {
3021 //
3022 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel
3023 // 1: 0x90
3024 // 2: 0x66 0x90
3025 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
3026 // 4: 0x0F 0x1F 0x40 0x00
3027 // 5: 0x0F 0x1F 0x44 0x00 0x00
3028 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
3029 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3030 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3031 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3032 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3033 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3034
3035 // The rest coding is Intel specific - don't use consecutive address nops
3036
3037 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3038 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3039 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3040 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3041
3042 while(i >= 15) {
3043 // For Intel don't generate consecutive addess nops (mix with regular nops)
3044 i -= 15;
3045 emit_int8(0x66); // size prefix
3046 emit_int8(0x66); // size prefix
3047 emit_int8(0x66); // size prefix
3048 addr_nop_8();
3049 emit_int8(0x66); // size prefix
3050 emit_int8(0x66); // size prefix
3051 emit_int8(0x66); // size prefix
3052 emit_int8((unsigned char)0x90);
3053 // nop
3054 }
3055 switch (i) {
3056 case 14:
3057 emit_int8(0x66); // size prefix
3058 case 13:
3059 emit_int8(0x66); // size prefix
3060 case 12:
3061 addr_nop_8();
3062 emit_int8(0x66); // size prefix
3063 emit_int8(0x66); // size prefix
3064 emit_int8(0x66); // size prefix
3065 emit_int8((unsigned char)0x90);
3066 // nop
3067 break;
3068 case 11:
3069 emit_int8(0x66); // size prefix
3070 case 10:
3071 emit_int8(0x66); // size prefix
3072 case 9:
3073 emit_int8(0x66); // size prefix
3074 case 8:
3075 addr_nop_8();
3076 break;
3077 case 7:
3078 addr_nop_7();
3079 break;
3080 case 6:
3081 emit_int8(0x66); // size prefix
3082 case 5:
3083 addr_nop_5();
3084 break;
3085 case 4:
3086 addr_nop_4();
3087 break;
3088 case 3:
3089 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
3090 emit_int8(0x66); // size prefix
3091 case 2:
3092 emit_int8(0x66); // size prefix
3093 case 1:
3094 emit_int8((unsigned char)0x90);
3095 // nop
3096 break;
3097 default:
3098 assert(i == 0, " ");
3099 }
3100 return;
3101 }
3102 if (UseAddressNop && VM_Version::is_amd()) {
3103 //
3104 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD.
3105 // 1: 0x90
3106 // 2: 0x66 0x90
3107 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
3108 // 4: 0x0F 0x1F 0x40 0x00
3109 // 5: 0x0F 0x1F 0x44 0x00 0x00
3110 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
3111 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3112 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3113 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3114 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3115 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3116
3117 // The rest coding is AMD specific - use consecutive address nops
3118
3119 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
3120 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
3121 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3122 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3123 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3124 // Size prefixes (0x66) are added for larger sizes
3125
3126 while(i >= 22) {
3127 i -= 11;
3128 emit_int8(0x66); // size prefix
3129 emit_int8(0x66); // size prefix
3130 emit_int8(0x66); // size prefix
3131 addr_nop_8();
3132 }
3133 // Generate first nop for size between 21-12
3134 switch (i) {
3135 case 21:
3136 i -= 1;
3137 emit_int8(0x66); // size prefix
3138 case 20:
3139 case 19:
3140 i -= 1;
3141 emit_int8(0x66); // size prefix
3142 case 18:
3143 case 17:
3144 i -= 1;
3145 emit_int8(0x66); // size prefix
3146 case 16:
3147 case 15:
3148 i -= 8;
3149 addr_nop_8();
3150 break;
3151 case 14:
3152 case 13:
3153 i -= 7;
3154 addr_nop_7();
3155 break;
3156 case 12:
3157 i -= 6;
3158 emit_int8(0x66); // size prefix
3159 addr_nop_5();
3160 break;
3161 default:
3162 assert(i < 12, " ");
3163 }
3164
3165 // Generate second nop for size between 11-1
3166 switch (i) {
3167 case 11:
3168 emit_int8(0x66); // size prefix
3169 case 10:
3170 emit_int8(0x66); // size prefix
3171 case 9:
3172 emit_int8(0x66); // size prefix
3173 case 8:
3174 addr_nop_8();
3175 break;
3176 case 7:
3177 addr_nop_7();
3178 break;
3179 case 6:
3180 emit_int8(0x66); // size prefix
3181 case 5:
3182 addr_nop_5();
3183 break;
3184 case 4:
3185 addr_nop_4();
3186 break;
3187 case 3:
3188 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
3189 emit_int8(0x66); // size prefix
3190 case 2:
3191 emit_int8(0x66); // size prefix
3192 case 1:
3193 emit_int8((unsigned char)0x90);
3194 // nop
3195 break;
3196 default:
3197 assert(i == 0, " ");
3198 }
3199 return;
3200 }
3201
3202 if (UseAddressNop && VM_Version::is_zx()) {
3203 //
3204 // Using multi-bytes nops "0x0F 0x1F [address]" for ZX
3205 // 1: 0x90
3206 // 2: 0x66 0x90
3207 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
3208 // 4: 0x0F 0x1F 0x40 0x00
3209 // 5: 0x0F 0x1F 0x44 0x00 0x00
3210 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
3211 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3212 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3213 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3214 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3215 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3216
3217 // The rest coding is ZX specific - don't use consecutive address nops
3218
3219 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3220 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3221 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3222 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3223
3224 while (i >= 15) {
3225 // For ZX don't generate consecutive addess nops (mix with regular nops)
3226 i -= 15;
3227 emit_int8(0x66); // size prefix
3228 emit_int8(0x66); // size prefix
3229 emit_int8(0x66); // size prefix
3230 addr_nop_8();
3231 emit_int8(0x66); // size prefix
3232 emit_int8(0x66); // size prefix
3233 emit_int8(0x66); // size prefix
3234 emit_int8((unsigned char)0x90);
3235 // nop
3236 }
3237 switch (i) {
3238 case 14:
3239 emit_int8(0x66); // size prefix
3240 case 13:
3241 emit_int8(0x66); // size prefix
3242 case 12:
3243 addr_nop_8();
3244 emit_int8(0x66); // size prefix
3245 emit_int8(0x66); // size prefix
3246 emit_int8(0x66); // size prefix
3247 emit_int8((unsigned char)0x90);
3248 // nop
3249 break;
3250 case 11:
3251 emit_int8(0x66); // size prefix
3252 case 10:
3253 emit_int8(0x66); // size prefix
3254 case 9:
3255 emit_int8(0x66); // size prefix
3256 case 8:
3257 addr_nop_8();
3258 break;
3259 case 7:
3260 addr_nop_7();
3261 break;
3262 case 6:
3263 emit_int8(0x66); // size prefix
3264 case 5:
3265 addr_nop_5();
3266 break;
3267 case 4:
3268 addr_nop_4();
3269 break;
3270 case 3:
3271 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
3272 emit_int8(0x66); // size prefix
3273 case 2:
3274 emit_int8(0x66); // size prefix
3275 case 1:
3276 emit_int8((unsigned char)0x90);
3277 // nop
3278 break;
3279 default:
3280 assert(i == 0, " ");
3281 }
3282 return;
3283 }
3284
3285 // Using nops with size prefixes "0x66 0x90".
3286 // From AMD Optimization Guide:
3287 // 1: 0x90
3288 // 2: 0x66 0x90
3289 // 3: 0x66 0x66 0x90
3290 // 4: 0x66 0x66 0x66 0x90
3291 // 5: 0x66 0x66 0x90 0x66 0x90
3292 // 6: 0x66 0x66 0x90 0x66 0x66 0x90
3293 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90
3294 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90
3295 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
3296 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
3297 //
3298 while(i > 12) {
3299 i -= 4;
3300 emit_int8(0x66); // size prefix
3301 emit_int8(0x66);
3302 emit_int8(0x66);
3303 emit_int8((unsigned char)0x90);
3304 // nop
3305 }
3306 // 1 - 12 nops
3307 if(i > 8) {
3308 if(i > 9) {
3309 i -= 1;
3310 emit_int8(0x66);
3311 }
3312 i -= 3;
3313 emit_int8(0x66);
3314 emit_int8(0x66);
3315 emit_int8((unsigned char)0x90);
3316 }
3317 // 1 - 8 nops
3318 if(i > 4) {
3319 if(i > 6) {
3320 i -= 1;
3321 emit_int8(0x66);
3322 }
3323 i -= 3;
3324 emit_int8(0x66);
3325 emit_int8(0x66);
3326 emit_int8((unsigned char)0x90);
3327 }
3328 switch (i) {
3329 case 4:
3330 emit_int8(0x66);
3331 case 3:
3332 emit_int8(0x66);
3333 case 2:
3334 emit_int8(0x66);
3335 case 1:
3336 emit_int8((unsigned char)0x90);
3337 break;
3338 default:
3339 assert(i == 0, " ");
3340 }
3341 }
3342
3343 void Assembler::notl(Register dst) {
3344 int encode = prefix_and_encode(dst->encoding());
3345 emit_int8((unsigned char)0xF7);
3346 emit_int8((unsigned char)(0xD0 | encode));
3347 }
3348
3349 void Assembler::orl(Address dst, int32_t imm32) {
3350 InstructionMark im(this);
3351 prefix(dst);
3352 emit_arith_operand(0x81, rcx, dst, imm32);
3353 }
3354
3355 void Assembler::orl(Register dst, int32_t imm32) {
3356 prefix(dst);
3357 emit_arith(0x81, 0xC8, dst, imm32);
3358 }
3359
3360 void Assembler::orl(Register dst, Address src) {
3361 InstructionMark im(this);
3362 prefix(src, dst);
3363 emit_int8(0x0B);
3364 emit_operand(dst, src);
3365 }
3366
3367 void Assembler::orl(Register dst, Register src) {
3368 (void) prefix_and_encode(dst->encoding(), src->encoding());
3369 emit_arith(0x0B, 0xC0, dst, src);
3370 }
3371
3372 void Assembler::orl(Address dst, Register src) {
3373 InstructionMark im(this);
3374 prefix(dst, src);
3375 emit_int8(0x09);
3376 emit_operand(src, dst);
3377 }
3378
3379 void Assembler::orb(Address dst, int imm8) {
3380 InstructionMark im(this);
3381 prefix(dst);
3382 emit_int8((unsigned char)0x80);
3383 emit_operand(rcx, dst, 1);
3384 emit_int8(imm8);
3385 }
3386
3387 void Assembler::packuswb(XMMRegister dst, Address src) {
3388 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3389 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3390 InstructionMark im(this);
3391 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3392 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3393 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3394 emit_int8(0x67);
3395 emit_operand(dst, src);
3396 }
3397
3398 void Assembler::packuswb(XMMRegister dst, XMMRegister src) {
3399 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3400 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3401 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3402 emit_int8(0x67);
3403 emit_int8((unsigned char)(0xC0 | encode));
3404 }
3405
3406 void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3407 assert(UseAVX > 0, "some form of AVX must be enabled");
3408 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3409 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3410 emit_int8(0x67);
3411 emit_int8((unsigned char)(0xC0 | encode));
3412 }
3413
3414 void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len) {
3415 assert(VM_Version::supports_avx2(), "");
3416 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3417 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3418 emit_int8(0x00);
3419 emit_int8(0xC0 | encode);
3420 emit_int8(imm8);
3421 }
3422
3423 void Assembler::vperm2i128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) {
3424 assert(VM_Version::supports_avx2(), "");
3425 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3426 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3427 emit_int8(0x46);
3428 emit_int8(0xC0 | encode);
3429 emit_int8(imm8);
3430 }
3431
3432 void Assembler::vperm2f128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) {
3433 assert(VM_Version::supports_avx(), "");
3434 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3435 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3436 emit_int8(0x06);
3437 emit_int8(0xC0 | encode);
3438 emit_int8(imm8);
3439 }
3440
3441 void Assembler::evpermi2q(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3442 assert(VM_Version::supports_evex(), "");
3443 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3444 attributes.set_is_evex_instruction();
3445 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3446 emit_int8(0x76);
3447 emit_int8((unsigned char)(0xC0 | encode));
3448 }
3449
3450
3451 void Assembler::pause() {
3452 emit_int8((unsigned char)0xF3);
3453 emit_int8((unsigned char)0x90);
3454 }
3455
3456 void Assembler::ud2() {
3457 emit_int8(0x0F);
3458 emit_int8(0x0B);
3459 }
3460
3461 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3462 assert(VM_Version::supports_sse4_2(), "");
3463 InstructionMark im(this);
3464 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3465 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3466 emit_int8(0x61);
3467 emit_operand(dst, src);
3468 emit_int8(imm8);
3469 }
3470
3471 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3472 assert(VM_Version::supports_sse4_2(), "");
3473 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3474 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3475 emit_int8(0x61);
3476 emit_int8((unsigned char)(0xC0 | encode));
3477 emit_int8(imm8);
3478 }
3479
3480 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3481 void Assembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
3482 assert(VM_Version::supports_sse2(), "");
3483 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3484 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3485 emit_int8(0x74);
3486 emit_int8((unsigned char)(0xC0 | encode));
3487 }
3488
3489 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3490 void Assembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3491 assert(VM_Version::supports_avx(), "");
3492 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3493 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3494 emit_int8(0x74);
3495 emit_int8((unsigned char)(0xC0 | encode));
3496 }
3497
3498 // In this context, kdst is written the mask used to process the equal components
3499 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3500 assert(VM_Version::supports_avx512bw(), "");
3501 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3502 attributes.set_is_evex_instruction();
3503 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3504 emit_int8(0x74);
3505 emit_int8((unsigned char)(0xC0 | encode));
3506 }
3507
3508 void Assembler::evpcmpgtb(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3509 assert(VM_Version::supports_avx512vlbw(), "");
3510 InstructionMark im(this);
3511 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3512 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3513 attributes.set_is_evex_instruction();
3514 int dst_enc = kdst->encoding();
3515 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3516 emit_int8(0x64);
3517 emit_operand(as_Register(dst_enc), src);
3518 }
3519
3520 void Assembler::evpcmpgtb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len) {
3521 assert(VM_Version::supports_avx512vlbw(), "");
3522 InstructionMark im(this);
3523 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3524 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3525 attributes.reset_is_clear_context();
3526 attributes.set_embedded_opmask_register_specifier(mask);
3527 attributes.set_is_evex_instruction();
3528 int dst_enc = kdst->encoding();
3529 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3530 emit_int8(0x64);
3531 emit_operand(as_Register(dst_enc), src);
3532 }
3533
3534 void Assembler::evpcmpuw(KRegister kdst, XMMRegister nds, XMMRegister src, ComparisonPredicate vcc, int vector_len) {
3535 assert(VM_Version::supports_avx512vlbw(), "");
3536 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3537 attributes.set_is_evex_instruction();
3538 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3539 emit_int8(0x3E);
3540 emit_int8((unsigned char)(0xC0 | encode));
3541 emit_int8(vcc);
3542 }
3543
3544 void Assembler::evpcmpuw(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, ComparisonPredicate vcc, int vector_len) {
3545 assert(VM_Version::supports_avx512vlbw(), "");
3546 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3547 attributes.reset_is_clear_context();
3548 attributes.set_embedded_opmask_register_specifier(mask);
3549 attributes.set_is_evex_instruction();
3550 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3551 emit_int8(0x3E);
3552 emit_int8((unsigned char)(0xC0 | encode));
3553 emit_int8(vcc);
3554 }
3555
3556 void Assembler::evpcmpuw(KRegister kdst, XMMRegister nds, Address src, ComparisonPredicate vcc, int vector_len) {
3557 assert(VM_Version::supports_avx512vlbw(), "");
3558 InstructionMark im(this);
3559 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3560 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3561 attributes.set_is_evex_instruction();
3562 int dst_enc = kdst->encoding();
3563 vex_prefix(src, nds->encoding(), kdst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3564 emit_int8(0x3E);
3565 emit_operand(as_Register(dst_enc), src);
3566 emit_int8(vcc);
3567 }
3568
3569 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3570 assert(VM_Version::supports_avx512bw(), "");
3571 InstructionMark im(this);
3572 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3573 attributes.set_is_evex_instruction();
3574 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3575 int dst_enc = kdst->encoding();
3576 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3577 emit_int8(0x74);
3578 emit_operand(as_Register(dst_enc), src);
3579 }
3580
3581 void Assembler::evpcmpeqb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len) {
3582 assert(VM_Version::supports_avx512vlbw(), "");
3583 InstructionMark im(this);
3584 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_reg_mask */ false, /* uses_vl */ true);
3585 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3586 attributes.reset_is_clear_context();
3587 attributes.set_embedded_opmask_register_specifier(mask);
3588 attributes.set_is_evex_instruction();
3589 vex_prefix(src, nds->encoding(), kdst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3590 emit_int8(0x74);
3591 emit_operand(as_Register(kdst->encoding()), src);
3592 }
3593
3594 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3595 void Assembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3596 assert(VM_Version::supports_sse2(), "");
3597 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3598 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3599 emit_int8(0x75);
3600 emit_int8((unsigned char)(0xC0 | encode));
3601 }
3602
3603 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3604 void Assembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3605 assert(VM_Version::supports_avx(), "");
3606 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3607 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3608 emit_int8(0x75);
3609 emit_int8((unsigned char)(0xC0 | encode));
3610 }
3611
3612 // In this context, kdst is written the mask used to process the equal components
3613 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3614 assert(VM_Version::supports_avx512bw(), "");
3615 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3616 attributes.set_is_evex_instruction();
3617 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3618 emit_int8(0x75);
3619 emit_int8((unsigned char)(0xC0 | encode));
3620 }
3621
3622 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3623 assert(VM_Version::supports_avx512bw(), "");
3624 InstructionMark im(this);
3625 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3626 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3627 attributes.set_is_evex_instruction();
3628 int dst_enc = kdst->encoding();
3629 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3630 emit_int8(0x75);
3631 emit_operand(as_Register(dst_enc), src);
3632 }
3633
3634 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3635 void Assembler::pcmpeqd(XMMRegister dst, XMMRegister src) {
3636 assert(VM_Version::supports_sse2(), "");
3637 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3638 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3639 emit_int8(0x76);
3640 emit_int8((unsigned char)(0xC0 | encode));
3641 }
3642
3643 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3644 void Assembler::vpcmpeqd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3645 assert(VM_Version::supports_avx(), "");
3646 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3647 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3648 emit_int8(0x76);
3649 emit_int8((unsigned char)(0xC0 | encode));
3650 }
3651
3652 // In this context, kdst is written the mask used to process the equal components
3653 void Assembler::evpcmpeqd(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3654 assert(VM_Version::supports_evex(), "");
3655 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3656 attributes.set_is_evex_instruction();
3657 attributes.reset_is_clear_context();
3658 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3659 emit_int8(0x76);
3660 emit_int8((unsigned char)(0xC0 | encode));
3661 }
3662
3663 void Assembler::evpcmpeqd(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3664 assert(VM_Version::supports_evex(), "");
3665 InstructionMark im(this);
3666 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3667 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3668 attributes.reset_is_clear_context();
3669 attributes.set_is_evex_instruction();
3670 int dst_enc = kdst->encoding();
3671 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3672 emit_int8(0x76);
3673 emit_operand(as_Register(dst_enc), src);
3674 }
3675
3676 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3677 void Assembler::pcmpeqq(XMMRegister dst, XMMRegister src) {
3678 assert(VM_Version::supports_sse4_1(), "");
3679 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3680 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3681 emit_int8(0x29);
3682 emit_int8((unsigned char)(0xC0 | encode));
3683 }
3684
3685 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3686 void Assembler::vpcmpeqq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3687 assert(VM_Version::supports_avx(), "");
3688 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3689 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3690 emit_int8(0x29);
3691 emit_int8((unsigned char)(0xC0 | encode));
3692 }
3693
3694 // In this context, kdst is written the mask used to process the equal components
3695 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3696 assert(VM_Version::supports_evex(), "");
3697 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3698 attributes.reset_is_clear_context();
3699 attributes.set_is_evex_instruction();
3700 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3701 emit_int8(0x29);
3702 emit_int8((unsigned char)(0xC0 | encode));
3703 }
3704
3705 // In this context, kdst is written the mask used to process the equal components
3706 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3707 assert(VM_Version::supports_evex(), "");
3708 InstructionMark im(this);
3709 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3710 attributes.reset_is_clear_context();
3711 attributes.set_is_evex_instruction();
3712 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
3713 int dst_enc = kdst->encoding();
3714 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3715 emit_int8(0x29);
3716 emit_operand(as_Register(dst_enc), src);
3717 }
3718
3719 void Assembler::pmovmskb(Register dst, XMMRegister src) {
3720 assert(VM_Version::supports_sse2(), "");
3721 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3722 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3723 emit_int8((unsigned char)0xD7);
3724 emit_int8((unsigned char)(0xC0 | encode));
3725 }
3726
3727 void Assembler::vpmovmskb(Register dst, XMMRegister src) {
3728 assert(VM_Version::supports_avx2(), "");
3729 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3730 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3731 emit_int8((unsigned char)0xD7);
3732 emit_int8((unsigned char)(0xC0 | encode));
3733 }
3734
3735 void Assembler::pextrd(Register dst, XMMRegister src, int imm8) {
3736 assert(VM_Version::supports_sse4_1(), "");
3737 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
3738 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3739 emit_int8(0x16);
3740 emit_int8((unsigned char)(0xC0 | encode));
3741 emit_int8(imm8);
3742 }
3743
3744 void Assembler::pextrd(Address dst, XMMRegister src, int imm8) {
3745 assert(VM_Version::supports_sse4_1(), "");
3746 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
3747 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3748 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3749 emit_int8(0x16);
3750 emit_operand(src, dst);
3751 emit_int8(imm8);
3752 }
3753
3754 void Assembler::pextrq(Register dst, XMMRegister src, int imm8) {
3755 assert(VM_Version::supports_sse4_1(), "");
3756 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
3757 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3758 emit_int8(0x16);
3759 emit_int8((unsigned char)(0xC0 | encode));
3760 emit_int8(imm8);
3761 }
3762
3763 void Assembler::pextrq(Address dst, XMMRegister src, int imm8) {
3764 assert(VM_Version::supports_sse4_1(), "");
3765 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
3766 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3767 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3768 emit_int8(0x16);
3769 emit_operand(src, dst);
3770 emit_int8(imm8);
3771 }
3772
3773 void Assembler::pextrw(Register dst, XMMRegister src, int imm8) {
3774 assert(VM_Version::supports_sse2(), "");
3775 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3776 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3777 emit_int8((unsigned char)0xC5);
3778 emit_int8((unsigned char)(0xC0 | encode));
3779 emit_int8(imm8);
3780 }
3781
3782 void Assembler::pextrw(Address dst, XMMRegister src, int imm8) {
3783 assert(VM_Version::supports_sse4_1(), "");
3784 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3785 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
3786 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3787 emit_int8((unsigned char)0x15);
3788 emit_operand(src, dst);
3789 emit_int8(imm8);
3790 }
3791
3792 void Assembler::pextrb(Address dst, XMMRegister src, int imm8) {
3793 assert(VM_Version::supports_sse4_1(), "");
3794 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3795 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
3796 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3797 emit_int8(0x14);
3798 emit_operand(src, dst);
3799 emit_int8(imm8);
3800 }
3801
3802 void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) {
3803 assert(VM_Version::supports_sse4_1(), "");
3804 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
3805 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3806 emit_int8(0x22);
3807 emit_int8((unsigned char)(0xC0 | encode));
3808 emit_int8(imm8);
3809 }
3810
3811 void Assembler::pinsrd(XMMRegister dst, Address src, int imm8) {
3812 assert(VM_Version::supports_sse4_1(), "");
3813 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
3814 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3815 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3816 emit_int8(0x22);
3817 emit_operand(dst,src);
3818 emit_int8(imm8);
3819 }
3820
3821 void Assembler::pinsrq(XMMRegister dst, Register src, int imm8) {
3822 assert(VM_Version::supports_sse4_1(), "");
3823 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
3824 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3825 emit_int8(0x22);
3826 emit_int8((unsigned char)(0xC0 | encode));
3827 emit_int8(imm8);
3828 }
3829
3830 void Assembler::pinsrq(XMMRegister dst, Address src, int imm8) {
3831 assert(VM_Version::supports_sse4_1(), "");
3832 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
3833 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3834 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3835 emit_int8(0x22);
3836 emit_operand(dst, src);
3837 emit_int8(imm8);
3838 }
3839
3840 void Assembler::pinsrw(XMMRegister dst, Register src, int imm8) {
3841 assert(VM_Version::supports_sse2(), "");
3842 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3843 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3844 emit_int8((unsigned char)0xC4);
3845 emit_int8((unsigned char)(0xC0 | encode));
3846 emit_int8(imm8);
3847 }
3848
3849 void Assembler::pinsrw(XMMRegister dst, Address src, int imm8) {
3850 assert(VM_Version::supports_sse2(), "");
3851 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3852 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
3853 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3854 emit_int8((unsigned char)0xC4);
3855 emit_operand(dst, src);
3856 emit_int8(imm8);
3857 }
3858
3859 void Assembler::pinsrb(XMMRegister dst, Address src, int imm8) {
3860 assert(VM_Version::supports_sse4_1(), "");
3861 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3862 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
3863 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3864 emit_int8(0x20);
3865 emit_operand(dst, src);
3866 emit_int8(imm8);
3867 }
3868
3869 void Assembler::pmovzxbw(XMMRegister dst, Address src) {
3870 assert(VM_Version::supports_sse4_1(), "");
3871 InstructionMark im(this);
3872 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3873 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3874 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3875 emit_int8(0x30);
3876 emit_operand(dst, src);
3877 }
3878
3879 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3880 assert(VM_Version::supports_sse4_1(), "");
3881 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3882 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3883 emit_int8(0x30);
3884 emit_int8((unsigned char)(0xC0 | encode));
3885 }
3886
3887 void Assembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
3888 assert(VM_Version::supports_avx(), "");
3889 InstructionMark im(this);
3890 assert(dst != xnoreg, "sanity");
3891 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3892 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3893 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3894 emit_int8(0x30);
3895 emit_operand(dst, src);
3896 }
3897
3898 void Assembler::vpmovzxbw(XMMRegister dst, XMMRegister src, int vector_len) {
3899 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
3900 vector_len == AVX_256bit? VM_Version::supports_avx2() :
3901 vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0, "");
3902 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3903 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3904 emit_int8(0x30);
3905 emit_int8((unsigned char) (0xC0 | encode));
3906 }
3907
3908
3909 void Assembler::evpmovzxbw(XMMRegister dst, KRegister mask, Address src, int vector_len) {
3910 assert(VM_Version::supports_avx512vlbw(), "");
3911 assert(dst != xnoreg, "sanity");
3912 InstructionMark im(this);
3913 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3914 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3915 attributes.set_embedded_opmask_register_specifier(mask);
3916 attributes.set_is_evex_instruction();
3917 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3918 emit_int8(0x30);
3919 emit_operand(dst, src);
3920 }
3921 void Assembler::evpmovwb(Address dst, XMMRegister src, int vector_len) {
3922 assert(VM_Version::supports_avx512vlbw(), "");
3923 assert(src != xnoreg, "sanity");
3924 InstructionMark im(this);
3925 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3926 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3927 attributes.set_is_evex_instruction();
3928 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
3929 emit_int8(0x30);
3930 emit_operand(src, dst);
3931 }
3932
3933 void Assembler::evpmovwb(Address dst, KRegister mask, XMMRegister src, int vector_len) {
3934 assert(VM_Version::supports_avx512vlbw(), "");
3935 assert(src != xnoreg, "sanity");
3936 InstructionMark im(this);
3937 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3938 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3939 attributes.reset_is_clear_context();
3940 attributes.set_embedded_opmask_register_specifier(mask);
3941 attributes.set_is_evex_instruction();
3942 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
3943 emit_int8(0x30);
3944 emit_operand(src, dst);
3945 }
3946
3947 void Assembler::evpmovdb(Address dst, XMMRegister src, int vector_len) {
3948 assert(VM_Version::supports_evex(), "");
3949 assert(src != xnoreg, "sanity");
3950 InstructionMark im(this);
3951 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3952 attributes.set_address_attributes(/* tuple_type */ EVEX_QVM, /* input_size_in_bits */ EVEX_NObit);
3953 attributes.set_is_evex_instruction();
3954 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
3955 emit_int8(0x31);
3956 emit_operand(src, dst);
3957 }
3958
3959 void Assembler::vpmovzxwd(XMMRegister dst, XMMRegister src, int vector_len) {
3960 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
3961 vector_len == AVX_256bit? VM_Version::supports_avx2() :
3962 vector_len == AVX_512bit? VM_Version::supports_evex() : 0, " ");
3963 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3964 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3965 emit_int8(0x33);
3966 emit_int8((unsigned char)(0xC0 | encode));
3967 }
3968
3969 void Assembler::pmaddwd(XMMRegister dst, XMMRegister src) {
3970 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3971 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3972 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3973 emit_int8((unsigned char)0xF5);
3974 emit_int8((unsigned char)(0xC0 | encode));
3975 }
3976
3977 void Assembler::vpmaddwd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3978 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
3979 (vector_len == AVX_256bit ? VM_Version::supports_avx2() :
3980 (vector_len == AVX_512bit ? VM_Version::supports_evex() : 0)), "");
3981 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3982 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3983 emit_int8((unsigned char)0xF5);
3984 emit_int8((unsigned char)(0xC0 | encode));
3985 }
3986
3987 void Assembler::evpdpwssd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3988 assert(VM_Version::supports_evex(), "");
3989 assert(VM_Version::supports_vnni(), "must support vnni");
3990 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3991 attributes.set_is_evex_instruction();
3992 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3993 emit_int8(0x52);
3994 emit_int8((unsigned char)(0xC0 | encode));
3995 }
3996
3997 // generic
3998 void Assembler::pop(Register dst) {
3999 int encode = prefix_and_encode(dst->encoding());
4000 emit_int8(0x58 | encode);
4001 }
4002
4003 void Assembler::popcntl(Register dst, Address src) {
4004 assert(VM_Version::supports_popcnt(), "must support");
4005 InstructionMark im(this);
4006 emit_int8((unsigned char)0xF3);
4007 prefix(src, dst);
4008 emit_int8(0x0F);
4009 emit_int8((unsigned char)0xB8);
4010 emit_operand(dst, src);
4011 }
4012
4013 void Assembler::popcntl(Register dst, Register src) {
4014 assert(VM_Version::supports_popcnt(), "must support");
4015 emit_int8((unsigned char)0xF3);
4016 int encode = prefix_and_encode(dst->encoding(), src->encoding());
4017 emit_int8(0x0F);
4018 emit_int8((unsigned char)0xB8);
4019 emit_int8((unsigned char)(0xC0 | encode));
4020 }
4021
4022 void Assembler::vpopcntd(XMMRegister dst, XMMRegister src, int vector_len) {
4023 assert(VM_Version::supports_vpopcntdq(), "must support vpopcntdq feature");
4024 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4025 attributes.set_is_evex_instruction();
4026 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4027 emit_int8(0x55);
4028 emit_int8((unsigned char)(0xC0 | encode));
4029 }
4030
4031 void Assembler::popf() {
4032 emit_int8((unsigned char)0x9D);
4033 }
4034
4035 #ifndef _LP64 // no 32bit push/pop on amd64
4036 void Assembler::popl(Address dst) {
4037 // NOTE: this will adjust stack by 8byte on 64bits
4038 InstructionMark im(this);
4039 prefix(dst);
4040 emit_int8((unsigned char)0x8F);
4041 emit_operand(rax, dst);
4042 }
4043 #endif
4044
4045 void Assembler::prefetch_prefix(Address src) {
4046 prefix(src);
4047 emit_int8(0x0F);
4048 }
4049
4050 void Assembler::prefetchnta(Address src) {
4051 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
4052 InstructionMark im(this);
4053 prefetch_prefix(src);
4054 emit_int8(0x18);
4055 emit_operand(rax, src); // 0, src
4056 }
4057
4058 void Assembler::prefetchr(Address src) {
4059 assert(VM_Version::supports_3dnow_prefetch(), "must support");
4060 InstructionMark im(this);
4061 prefetch_prefix(src);
4062 emit_int8(0x0D);
4063 emit_operand(rax, src); // 0, src
4064 }
4065
4066 void Assembler::prefetcht0(Address src) {
4067 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
4068 InstructionMark im(this);
4069 prefetch_prefix(src);
4070 emit_int8(0x18);
4071 emit_operand(rcx, src); // 1, src
4072 }
4073
4074 void Assembler::prefetcht1(Address src) {
4075 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
4076 InstructionMark im(this);
4077 prefetch_prefix(src);
4078 emit_int8(0x18);
4079 emit_operand(rdx, src); // 2, src
4080 }
4081
4082 void Assembler::prefetcht2(Address src) {
4083 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
4084 InstructionMark im(this);
4085 prefetch_prefix(src);
4086 emit_int8(0x18);
4087 emit_operand(rbx, src); // 3, src
4088 }
4089
4090 void Assembler::prefetchw(Address src) {
4091 assert(VM_Version::supports_3dnow_prefetch(), "must support");
4092 InstructionMark im(this);
4093 prefetch_prefix(src);
4094 emit_int8(0x0D);
4095 emit_operand(rcx, src); // 1, src
4096 }
4097
4098 void Assembler::prefix(Prefix p) {
4099 emit_int8(p);
4100 }
4101
4102 void Assembler::pshufb(XMMRegister dst, XMMRegister src) {
4103 assert(VM_Version::supports_ssse3(), "");
4104 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4105 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4106 emit_int8(0x00);
4107 emit_int8((unsigned char)(0xC0 | encode));
4108 }
4109
4110 void Assembler::vpshufb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4111 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
4112 vector_len == AVX_256bit? VM_Version::supports_avx2() :
4113 0, "");
4114 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4115 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4116 emit_int8(0x00);
4117 emit_int8((unsigned char)(0xC0 | encode));
4118 }
4119
4120 void Assembler::pshufb(XMMRegister dst, Address src) {
4121 assert(VM_Version::supports_ssse3(), "");
4122 InstructionMark im(this);
4123 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4124 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4125 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4126 emit_int8(0x00);
4127 emit_operand(dst, src);
4128 }
4129
4130 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
4131 assert(isByte(mode), "invalid value");
4132 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4133 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
4134 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4135 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4136 emit_int8(0x70);
4137 emit_int8((unsigned char)(0xC0 | encode));
4138 emit_int8(mode & 0xFF);
4139 }
4140
4141 void Assembler::vpshufd(XMMRegister dst, XMMRegister src, int mode, int vector_len) {
4142 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
4143 vector_len == AVX_256bit? VM_Version::supports_avx2() :
4144 0, "");
4145 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4146 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4147 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4148 emit_int8(0x70);
4149 emit_int8((unsigned char)(0xC0 | encode));
4150 emit_int8(mode & 0xFF);
4151 }
4152
4153 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
4154 assert(isByte(mode), "invalid value");
4155 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4156 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4157 InstructionMark im(this);
4158 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4159 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4160 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4161 emit_int8(0x70);
4162 emit_operand(dst, src);
4163 emit_int8(mode & 0xFF);
4164 }
4165
4166 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
4167 assert(isByte(mode), "invalid value");
4168 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4169 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4170 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4171 emit_int8(0x70);
4172 emit_int8((unsigned char)(0xC0 | encode));
4173 emit_int8(mode & 0xFF);
4174 }
4175
4176 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
4177 assert(isByte(mode), "invalid value");
4178 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4179 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4180 InstructionMark im(this);
4181 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4182 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4183 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4184 emit_int8(0x70);
4185 emit_operand(dst, src);
4186 emit_int8(mode & 0xFF);
4187 }
4188 void Assembler::evshufi64x2(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
4189 assert(VM_Version::supports_evex(), "requires EVEX support");
4190 assert(vector_len == Assembler::AVX_256bit || vector_len == Assembler::AVX_512bit, "");
4191 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4192 attributes.set_is_evex_instruction();
4193 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4194 emit_int8(0x43);
4195 emit_int8((unsigned char)(0xC0 | encode));
4196 emit_int8(imm8 & 0xFF);
4197 }
4198
4199 void Assembler::psrldq(XMMRegister dst, int shift) {
4200 // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
4201 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4202 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4203 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4204 emit_int8(0x73);
4205 emit_int8((unsigned char)(0xC0 | encode));
4206 emit_int8(shift);
4207 }
4208
4209 void Assembler::pslldq(XMMRegister dst, int shift) {
4210 // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
4211 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4212 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4213 // XMM7 is for /7 encoding: 66 0F 73 /7 ib
4214 int encode = simd_prefix_and_encode(xmm7, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4215 emit_int8(0x73);
4216 emit_int8((unsigned char)(0xC0 | encode));
4217 emit_int8(shift);
4218 }
4219
4220 void Assembler::ptest(XMMRegister dst, Address src) {
4221 assert(VM_Version::supports_sse4_1(), "");
4222 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4223 InstructionMark im(this);
4224 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4225 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4226 emit_int8(0x17);
4227 emit_operand(dst, src);
4228 }
4229
4230 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
4231 assert(VM_Version::supports_sse4_1(), "");
4232 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4233 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4234 emit_int8(0x17);
4235 emit_int8((unsigned char)(0xC0 | encode));
4236 }
4237
4238 void Assembler::vptest(XMMRegister dst, Address src) {
4239 assert(VM_Version::supports_avx(), "");
4240 InstructionMark im(this);
4241 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4242 assert(dst != xnoreg, "sanity");
4243 // swap src<->dst for encoding
4244 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4245 emit_int8(0x17);
4246 emit_operand(dst, src);
4247 }
4248
4249 void Assembler::vptest(XMMRegister dst, XMMRegister src) {
4250 assert(VM_Version::supports_avx(), "");
4251 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4252 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4253 emit_int8(0x17);
4254 emit_int8((unsigned char)(0xC0 | encode));
4255 }
4256
4257 void Assembler::punpcklbw(XMMRegister dst, Address src) {
4258 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4259 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4260 InstructionMark im(this);
4261 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ true, /* uses_vl */ true);
4262 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4263 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4264 emit_int8(0x60);
4265 emit_operand(dst, src);
4266 }
4267
4268 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
4269 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4270 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ true, /* uses_vl */ true);
4271 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4272 emit_int8(0x60);
4273 emit_int8((unsigned char)(0xC0 | encode));
4274 }
4275
4276 void Assembler::punpckldq(XMMRegister dst, Address src) {
4277 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4278 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4279 InstructionMark im(this);
4280 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4281 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4282 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4283 emit_int8(0x62);
4284 emit_operand(dst, src);
4285 }
4286
4287 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) {
4288 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4289 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4290 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4291 emit_int8(0x62);
4292 emit_int8((unsigned char)(0xC0 | encode));
4293 }
4294
4295 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) {
4296 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4297 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4298 attributes.set_rex_vex_w_reverted();
4299 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4300 emit_int8(0x6C);
4301 emit_int8((unsigned char)(0xC0 | encode));
4302 }
4303
4304 void Assembler::push(int32_t imm32) {
4305 // in 64bits we push 64bits onto the stack but only
4306 // take a 32bit immediate
4307 emit_int8(0x68);
4308 emit_int32(imm32);
4309 }
4310
4311 void Assembler::push(Register src) {
4312 int encode = prefix_and_encode(src->encoding());
4313
4314 emit_int8(0x50 | encode);
4315 }
4316
4317 void Assembler::pushf() {
4318 emit_int8((unsigned char)0x9C);
4319 }
4320
4321 #ifndef _LP64 // no 32bit push/pop on amd64
4322 void Assembler::pushl(Address src) {
4323 // Note this will push 64bit on 64bit
4324 InstructionMark im(this);
4325 prefix(src);
4326 emit_int8((unsigned char)0xFF);
4327 emit_operand(rsi, src);
4328 }
4329 #endif
4330
4331 void Assembler::rcll(Register dst, int imm8) {
4332 assert(isShiftCount(imm8), "illegal shift count");
4333 int encode = prefix_and_encode(dst->encoding());
4334 if (imm8 == 1) {
4335 emit_int8((unsigned char)0xD1);
4336 emit_int8((unsigned char)(0xD0 | encode));
4337 } else {
4338 emit_int8((unsigned char)0xC1);
4339 emit_int8((unsigned char)0xD0 | encode);
4340 emit_int8(imm8);
4341 }
4342 }
4343
4344 void Assembler::rcpps(XMMRegister dst, XMMRegister src) {
4345 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4346 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4347 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4348 emit_int8(0x53);
4349 emit_int8((unsigned char)(0xC0 | encode));
4350 }
4351
4352 void Assembler::rcpss(XMMRegister dst, XMMRegister src) {
4353 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4354 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4355 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4356 emit_int8(0x53);
4357 emit_int8((unsigned char)(0xC0 | encode));
4358 }
4359
4360 void Assembler::rdtsc() {
4361 emit_int8((unsigned char)0x0F);
4362 emit_int8((unsigned char)0x31);
4363 }
4364
4365 // copies data from [esi] to [edi] using rcx pointer sized words
4366 // generic
4367 void Assembler::rep_mov() {
4368 emit_int8((unsigned char)0xF3);
4369 // MOVSQ
4370 LP64_ONLY(prefix(REX_W));
4371 emit_int8((unsigned char)0xA5);
4372 }
4373
4374 // sets rcx bytes with rax, value at [edi]
4375 void Assembler::rep_stosb() {
4376 emit_int8((unsigned char)0xF3); // REP
4377 LP64_ONLY(prefix(REX_W));
4378 emit_int8((unsigned char)0xAA); // STOSB
4379 }
4380
4381 // sets rcx pointer sized words with rax, value at [edi]
4382 // generic
4383 void Assembler::rep_stos() {
4384 emit_int8((unsigned char)0xF3); // REP
4385 LP64_ONLY(prefix(REX_W)); // LP64:STOSQ, LP32:STOSD
4386 emit_int8((unsigned char)0xAB);
4387 }
4388
4389 // scans rcx pointer sized words at [edi] for occurance of rax,
4390 // generic
4391 void Assembler::repne_scan() { // repne_scan
4392 emit_int8((unsigned char)0xF2);
4393 // SCASQ
4394 LP64_ONLY(prefix(REX_W));
4395 emit_int8((unsigned char)0xAF);
4396 }
4397
4398 #ifdef _LP64
4399 // scans rcx 4 byte words at [edi] for occurance of rax,
4400 // generic
4401 void Assembler::repne_scanl() { // repne_scan
4402 emit_int8((unsigned char)0xF2);
4403 // SCASL
4404 emit_int8((unsigned char)0xAF);
4405 }
4406 #endif
4407
4408 void Assembler::ret(int imm16) {
4409 if (imm16 == 0) {
4410 emit_int8((unsigned char)0xC3);
4411 } else {
4412 emit_int8((unsigned char)0xC2);
4413 emit_int16(imm16);
4414 }
4415 }
4416
4417 void Assembler::sahf() {
4418 #ifdef _LP64
4419 // Not supported in 64bit mode
4420 ShouldNotReachHere();
4421 #endif
4422 emit_int8((unsigned char)0x9E);
4423 }
4424
4425 void Assembler::sarl(Register dst, int imm8) {
4426 int encode = prefix_and_encode(dst->encoding());
4427 assert(isShiftCount(imm8), "illegal shift count");
4428 if (imm8 == 1) {
4429 emit_int8((unsigned char)0xD1);
4430 emit_int8((unsigned char)(0xF8 | encode));
4431 } else {
4432 emit_int8((unsigned char)0xC1);
4433 emit_int8((unsigned char)(0xF8 | encode));
4434 emit_int8(imm8);
4435 }
4436 }
4437
4438 void Assembler::sarl(Register dst) {
4439 int encode = prefix_and_encode(dst->encoding());
4440 emit_int8((unsigned char)0xD3);
4441 emit_int8((unsigned char)(0xF8 | encode));
4442 }
4443
4444 void Assembler::sbbl(Address dst, int32_t imm32) {
4445 InstructionMark im(this);
4446 prefix(dst);
4447 emit_arith_operand(0x81, rbx, dst, imm32);
4448 }
4449
4450 void Assembler::sbbl(Register dst, int32_t imm32) {
4451 prefix(dst);
4452 emit_arith(0x81, 0xD8, dst, imm32);
4453 }
4454
4455
4456 void Assembler::sbbl(Register dst, Address src) {
4457 InstructionMark im(this);
4458 prefix(src, dst);
4459 emit_int8(0x1B);
4460 emit_operand(dst, src);
4461 }
4462
4463 void Assembler::sbbl(Register dst, Register src) {
4464 (void) prefix_and_encode(dst->encoding(), src->encoding());
4465 emit_arith(0x1B, 0xC0, dst, src);
4466 }
4467
4468 void Assembler::setb(Condition cc, Register dst) {
4469 assert(0 <= cc && cc < 16, "illegal cc");
4470 int encode = prefix_and_encode(dst->encoding(), true);
4471 emit_int8(0x0F);
4472 emit_int8((unsigned char)0x90 | cc);
4473 emit_int8((unsigned char)(0xC0 | encode));
4474 }
4475
4476 void Assembler::palignr(XMMRegister dst, XMMRegister src, int imm8) {
4477 assert(VM_Version::supports_ssse3(), "");
4478 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4479 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4480 emit_int8((unsigned char)0x0F);
4481 emit_int8((unsigned char)(0xC0 | encode));
4482 emit_int8(imm8);
4483 }
4484
4485 void Assembler::vpalignr(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
4486 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
4487 vector_len == AVX_256bit? VM_Version::supports_avx2() :
4488 0, "");
4489 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4490 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4491 emit_int8((unsigned char)0x0F);
4492 emit_int8((unsigned char)(0xC0 | encode));
4493 emit_int8(imm8);
4494 }
4495
4496 void Assembler::evalignq(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
4497 assert(VM_Version::supports_evex(), "");
4498 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4499 attributes.set_is_evex_instruction();
4500 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4501 emit_int8(0x3);
4502 emit_int8((unsigned char)(0xC0 | encode));
4503 emit_int8(imm8);
4504 }
4505
4506 void Assembler::pblendw(XMMRegister dst, XMMRegister src, int imm8) {
4507 assert(VM_Version::supports_sse4_1(), "");
4508 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4509 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4510 emit_int8((unsigned char)0x0E);
4511 emit_int8((unsigned char)(0xC0 | encode));
4512 emit_int8(imm8);
4513 }
4514
4515 void Assembler::sha1rnds4(XMMRegister dst, XMMRegister src, int imm8) {
4516 assert(VM_Version::supports_sha(), "");
4517 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3A, /* rex_w */ false);
4518 emit_int8((unsigned char)0xCC);
4519 emit_int8((unsigned char)(0xC0 | encode));
4520 emit_int8((unsigned char)imm8);
4521 }
4522
4523 void Assembler::sha1nexte(XMMRegister dst, XMMRegister src) {
4524 assert(VM_Version::supports_sha(), "");
4525 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4526 emit_int8((unsigned char)0xC8);
4527 emit_int8((unsigned char)(0xC0 | encode));
4528 }
4529
4530 void Assembler::sha1msg1(XMMRegister dst, XMMRegister src) {
4531 assert(VM_Version::supports_sha(), "");
4532 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4533 emit_int8((unsigned char)0xC9);
4534 emit_int8((unsigned char)(0xC0 | encode));
4535 }
4536
4537 void Assembler::sha1msg2(XMMRegister dst, XMMRegister src) {
4538 assert(VM_Version::supports_sha(), "");
4539 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4540 emit_int8((unsigned char)0xCA);
4541 emit_int8((unsigned char)(0xC0 | encode));
4542 }
4543
4544 // xmm0 is implicit additional source to this instruction.
4545 void Assembler::sha256rnds2(XMMRegister dst, XMMRegister src) {
4546 assert(VM_Version::supports_sha(), "");
4547 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4548 emit_int8((unsigned char)0xCB);
4549 emit_int8((unsigned char)(0xC0 | encode));
4550 }
4551
4552 void Assembler::sha256msg1(XMMRegister dst, XMMRegister src) {
4553 assert(VM_Version::supports_sha(), "");
4554 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4555 emit_int8((unsigned char)0xCC);
4556 emit_int8((unsigned char)(0xC0 | encode));
4557 }
4558
4559 void Assembler::sha256msg2(XMMRegister dst, XMMRegister src) {
4560 assert(VM_Version::supports_sha(), "");
4561 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4562 emit_int8((unsigned char)0xCD);
4563 emit_int8((unsigned char)(0xC0 | encode));
4564 }
4565
4566
4567 void Assembler::shll(Register dst, int imm8) {
4568 assert(isShiftCount(imm8), "illegal shift count");
4569 int encode = prefix_and_encode(dst->encoding());
4570 if (imm8 == 1 ) {
4571 emit_int8((unsigned char)0xD1);
4572 emit_int8((unsigned char)(0xE0 | encode));
4573 } else {
4574 emit_int8((unsigned char)0xC1);
4575 emit_int8((unsigned char)(0xE0 | encode));
4576 emit_int8(imm8);
4577 }
4578 }
4579
4580 void Assembler::shll(Register dst) {
4581 int encode = prefix_and_encode(dst->encoding());
4582 emit_int8((unsigned char)0xD3);
4583 emit_int8((unsigned char)(0xE0 | encode));
4584 }
4585
4586 void Assembler::shrl(Register dst, int imm8) {
4587 assert(isShiftCount(imm8), "illegal shift count");
4588 int encode = prefix_and_encode(dst->encoding());
4589 emit_int8((unsigned char)0xC1);
4590 emit_int8((unsigned char)(0xE8 | encode));
4591 emit_int8(imm8);
4592 }
4593
4594 void Assembler::shrl(Register dst) {
4595 int encode = prefix_and_encode(dst->encoding());
4596 emit_int8((unsigned char)0xD3);
4597 emit_int8((unsigned char)(0xE8 | encode));
4598 }
4599
4600 // copies a single word from [esi] to [edi]
4601 void Assembler::smovl() {
4602 emit_int8((unsigned char)0xA5);
4603 }
4604
4605 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
4606 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4607 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4608 attributes.set_rex_vex_w_reverted();
4609 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4610 emit_int8(0x51);
4611 emit_int8((unsigned char)(0xC0 | encode));
4612 }
4613
4614 void Assembler::sqrtsd(XMMRegister dst, Address src) {
4615 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4616 InstructionMark im(this);
4617 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4618 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4619 attributes.set_rex_vex_w_reverted();
4620 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4621 emit_int8(0x51);
4622 emit_operand(dst, src);
4623 }
4624
4625 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
4626 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4627 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4628 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4629 emit_int8(0x51);
4630 emit_int8((unsigned char)(0xC0 | encode));
4631 }
4632
4633 void Assembler::std() {
4634 emit_int8((unsigned char)0xFD);
4635 }
4636
4637 void Assembler::sqrtss(XMMRegister dst, Address src) {
4638 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4639 InstructionMark im(this);
4640 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4641 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4642 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4643 emit_int8(0x51);
4644 emit_operand(dst, src);
4645 }
4646
4647 void Assembler::stmxcsr( Address dst) {
4648 if (UseAVX > 0 ) {
4649 assert(VM_Version::supports_avx(), "");
4650 InstructionMark im(this);
4651 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4652 vex_prefix(dst, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4653 emit_int8((unsigned char)0xAE);
4654 emit_operand(as_Register(3), dst);
4655 } else {
4656 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4657 InstructionMark im(this);
4658 prefix(dst);
4659 emit_int8(0x0F);
4660 emit_int8((unsigned char)0xAE);
4661 emit_operand(as_Register(3), dst);
4662 }
4663 }
4664
4665 void Assembler::subl(Address dst, int32_t imm32) {
4666 InstructionMark im(this);
4667 prefix(dst);
4668 emit_arith_operand(0x81, rbp, dst, imm32);
4669 }
4670
4671 void Assembler::subl(Address dst, Register src) {
4672 InstructionMark im(this);
4673 prefix(dst, src);
4674 emit_int8(0x29);
4675 emit_operand(src, dst);
4676 }
4677
4678 void Assembler::subl(Register dst, int32_t imm32) {
4679 prefix(dst);
4680 emit_arith(0x81, 0xE8, dst, imm32);
4681 }
4682
4683 // Force generation of a 4 byte immediate value even if it fits into 8bit
4684 void Assembler::subl_imm32(Register dst, int32_t imm32) {
4685 prefix(dst);
4686 emit_arith_imm32(0x81, 0xE8, dst, imm32);
4687 }
4688
4689 void Assembler::subl(Register dst, Address src) {
4690 InstructionMark im(this);
4691 prefix(src, dst);
4692 emit_int8(0x2B);
4693 emit_operand(dst, src);
4694 }
4695
4696 void Assembler::subl(Register dst, Register src) {
4697 (void) prefix_and_encode(dst->encoding(), src->encoding());
4698 emit_arith(0x2B, 0xC0, dst, src);
4699 }
4700
4701 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
4702 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4703 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4704 attributes.set_rex_vex_w_reverted();
4705 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4706 emit_int8(0x5C);
4707 emit_int8((unsigned char)(0xC0 | encode));
4708 }
4709
4710 void Assembler::subsd(XMMRegister dst, Address src) {
4711 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4712 InstructionMark im(this);
4713 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4714 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4715 attributes.set_rex_vex_w_reverted();
4716 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4717 emit_int8(0x5C);
4718 emit_operand(dst, src);
4719 }
4720
4721 void Assembler::subss(XMMRegister dst, XMMRegister src) {
4722 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4723 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true , /* uses_vl */ false);
4724 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4725 emit_int8(0x5C);
4726 emit_int8((unsigned char)(0xC0 | encode));
4727 }
4728
4729 void Assembler::subss(XMMRegister dst, Address src) {
4730 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4731 InstructionMark im(this);
4732 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4733 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4734 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4735 emit_int8(0x5C);
4736 emit_operand(dst, src);
4737 }
4738
4739 void Assembler::testb(Register dst, int imm8) {
4740 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
4741 (void) prefix_and_encode(dst->encoding(), true);
4742 emit_arith_b(0xF6, 0xC0, dst, imm8);
4743 }
4744
4745 void Assembler::testb(Address dst, int imm8) {
4746 InstructionMark im(this);
4747 prefix(dst);
4748 emit_int8((unsigned char)0xF6);
4749 emit_operand(rax, dst, 1);
4750 emit_int8(imm8);
4751 }
4752
4753 void Assembler::testl(Register dst, int32_t imm32) {
4754 // not using emit_arith because test
4755 // doesn't support sign-extension of
4756 // 8bit operands
4757 int encode = dst->encoding();
4758 if (encode == 0) {
4759 emit_int8((unsigned char)0xA9);
4760 } else {
4761 encode = prefix_and_encode(encode);
4762 emit_int8((unsigned char)0xF7);
4763 emit_int8((unsigned char)(0xC0 | encode));
4764 }
4765 emit_int32(imm32);
4766 }
4767
4768 void Assembler::testl(Register dst, Register src) {
4769 (void) prefix_and_encode(dst->encoding(), src->encoding());
4770 emit_arith(0x85, 0xC0, dst, src);
4771 }
4772
4773 void Assembler::testl(Register dst, Address src) {
4774 InstructionMark im(this);
4775 prefix(src, dst);
4776 emit_int8((unsigned char)0x85);
4777 emit_operand(dst, src);
4778 }
4779
4780 void Assembler::tzcntl(Register dst, Register src) {
4781 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
4782 emit_int8((unsigned char)0xF3);
4783 int encode = prefix_and_encode(dst->encoding(), src->encoding());
4784 emit_int8(0x0F);
4785 emit_int8((unsigned char)0xBC);
4786 emit_int8((unsigned char)0xC0 | encode);
4787 }
4788
4789 void Assembler::tzcntq(Register dst, Register src) {
4790 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
4791 emit_int8((unsigned char)0xF3);
4792 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4793 emit_int8(0x0F);
4794 emit_int8((unsigned char)0xBC);
4795 emit_int8((unsigned char)(0xC0 | encode));
4796 }
4797
4798 void Assembler::ucomisd(XMMRegister dst, Address src) {
4799 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4800 InstructionMark im(this);
4801 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4802 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4803 attributes.set_rex_vex_w_reverted();
4804 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4805 emit_int8(0x2E);
4806 emit_operand(dst, src);
4807 }
4808
4809 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
4810 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4811 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4812 attributes.set_rex_vex_w_reverted();
4813 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4814 emit_int8(0x2E);
4815 emit_int8((unsigned char)(0xC0 | encode));
4816 }
4817
4818 void Assembler::ucomiss(XMMRegister dst, Address src) {
4819 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4820 InstructionMark im(this);
4821 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4822 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4823 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4824 emit_int8(0x2E);
4825 emit_operand(dst, src);
4826 }
4827
4828 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
4829 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4830 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4831 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4832 emit_int8(0x2E);
4833 emit_int8((unsigned char)(0xC0 | encode));
4834 }
4835
4836 void Assembler::xabort(int8_t imm8) {
4837 emit_int8((unsigned char)0xC6);
4838 emit_int8((unsigned char)0xF8);
4839 emit_int8((unsigned char)(imm8 & 0xFF));
4840 }
4841
4842 void Assembler::xaddb(Address dst, Register src) {
4843 InstructionMark im(this);
4844 prefix(dst, src, true);
4845 emit_int8(0x0F);
4846 emit_int8((unsigned char)0xC0);
4847 emit_operand(src, dst);
4848 }
4849
4850 void Assembler::xaddw(Address dst, Register src) {
4851 InstructionMark im(this);
4852 emit_int8(0x66);
4853 prefix(dst, src);
4854 emit_int8(0x0F);
4855 emit_int8((unsigned char)0xC1);
4856 emit_operand(src, dst);
4857 }
4858
4859 void Assembler::xaddl(Address dst, Register src) {
4860 InstructionMark im(this);
4861 prefix(dst, src);
4862 emit_int8(0x0F);
4863 emit_int8((unsigned char)0xC1);
4864 emit_operand(src, dst);
4865 }
4866
4867 void Assembler::xbegin(Label& abort, relocInfo::relocType rtype) {
4868 InstructionMark im(this);
4869 relocate(rtype);
4870 if (abort.is_bound()) {
4871 address entry = target(abort);
4872 assert(entry != NULL, "abort entry NULL");
4873 intptr_t offset = entry - pc();
4874 emit_int8((unsigned char)0xC7);
4875 emit_int8((unsigned char)0xF8);
4876 emit_int32(offset - 6); // 2 opcode + 4 address
4877 } else {
4878 abort.add_patch_at(code(), locator());
4879 emit_int8((unsigned char)0xC7);
4880 emit_int8((unsigned char)0xF8);
4881 emit_int32(0);
4882 }
4883 }
4884
4885 void Assembler::xchgb(Register dst, Address src) { // xchg
4886 InstructionMark im(this);
4887 prefix(src, dst, true);
4888 emit_int8((unsigned char)0x86);
4889 emit_operand(dst, src);
4890 }
4891
4892 void Assembler::xchgw(Register dst, Address src) { // xchg
4893 InstructionMark im(this);
4894 emit_int8(0x66);
4895 prefix(src, dst);
4896 emit_int8((unsigned char)0x87);
4897 emit_operand(dst, src);
4898 }
4899
4900 void Assembler::xchgl(Register dst, Address src) { // xchg
4901 InstructionMark im(this);
4902 prefix(src, dst);
4903 emit_int8((unsigned char)0x87);
4904 emit_operand(dst, src);
4905 }
4906
4907 void Assembler::xchgl(Register dst, Register src) {
4908 int encode = prefix_and_encode(dst->encoding(), src->encoding());
4909 emit_int8((unsigned char)0x87);
4910 emit_int8((unsigned char)(0xC0 | encode));
4911 }
4912
4913 void Assembler::xend() {
4914 emit_int8((unsigned char)0x0F);
4915 emit_int8((unsigned char)0x01);
4916 emit_int8((unsigned char)0xD5);
4917 }
4918
4919 void Assembler::xgetbv() {
4920 emit_int8(0x0F);
4921 emit_int8(0x01);
4922 emit_int8((unsigned char)0xD0);
4923 }
4924
4925 void Assembler::xorl(Register dst, int32_t imm32) {
4926 prefix(dst);
4927 emit_arith(0x81, 0xF0, dst, imm32);
4928 }
4929
4930 void Assembler::xorl(Register dst, Address src) {
4931 InstructionMark im(this);
4932 prefix(src, dst);
4933 emit_int8(0x33);
4934 emit_operand(dst, src);
4935 }
4936
4937 void Assembler::xorl(Register dst, Register src) {
4938 (void) prefix_and_encode(dst->encoding(), src->encoding());
4939 emit_arith(0x33, 0xC0, dst, src);
4940 }
4941
4942 void Assembler::xorb(Register dst, Address src) {
4943 InstructionMark im(this);
4944 prefix(src, dst);
4945 emit_int8(0x32);
4946 emit_operand(dst, src);
4947 }
4948
4949 // AVX 3-operands scalar float-point arithmetic instructions
4950
4951 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) {
4952 assert(VM_Version::supports_avx(), "");
4953 InstructionMark im(this);
4954 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4955 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4956 attributes.set_rex_vex_w_reverted();
4957 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4958 emit_int8(0x58);
4959 emit_operand(dst, src);
4960 }
4961
4962 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4963 assert(VM_Version::supports_avx(), "");
4964 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4965 attributes.set_rex_vex_w_reverted();
4966 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4967 emit_int8(0x58);
4968 emit_int8((unsigned char)(0xC0 | encode));
4969 }
4970
4971 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) {
4972 assert(VM_Version::supports_avx(), "");
4973 InstructionMark im(this);
4974 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4975 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4976 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4977 emit_int8(0x58);
4978 emit_operand(dst, src);
4979 }
4980
4981 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4982 assert(VM_Version::supports_avx(), "");
4983 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4984 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4985 emit_int8(0x58);
4986 emit_int8((unsigned char)(0xC0 | encode));
4987 }
4988
4989 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) {
4990 assert(VM_Version::supports_avx(), "");
4991 InstructionMark im(this);
4992 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4993 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4994 attributes.set_rex_vex_w_reverted();
4995 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4996 emit_int8(0x5E);
4997 emit_operand(dst, src);
4998 }
4999
5000 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5001 assert(VM_Version::supports_avx(), "");
5002 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5003 attributes.set_rex_vex_w_reverted();
5004 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5005 emit_int8(0x5E);
5006 emit_int8((unsigned char)(0xC0 | encode));
5007 }
5008
5009 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) {
5010 assert(VM_Version::supports_avx(), "");
5011 InstructionMark im(this);
5012 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5013 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
5014 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5015 emit_int8(0x5E);
5016 emit_operand(dst, src);
5017 }
5018
5019 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5020 assert(VM_Version::supports_avx(), "");
5021 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5022 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5023 emit_int8(0x5E);
5024 emit_int8((unsigned char)(0xC0 | encode));
5025 }
5026
5027 void Assembler::vfmadd231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
5028 assert(VM_Version::supports_fma(), "");
5029 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5030 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5031 emit_int8((unsigned char)0xB9);
5032 emit_int8((unsigned char)(0xC0 | encode));
5033 }
5034
5035 void Assembler::vfmadd231ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
5036 assert(VM_Version::supports_fma(), "");
5037 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5038 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5039 emit_int8((unsigned char)0xB9);
5040 emit_int8((unsigned char)(0xC0 | encode));
5041 }
5042
5043 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) {
5044 assert(VM_Version::supports_avx(), "");
5045 InstructionMark im(this);
5046 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5047 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
5048 attributes.set_rex_vex_w_reverted();
5049 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5050 emit_int8(0x59);
5051 emit_operand(dst, src);
5052 }
5053
5054 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5055 assert(VM_Version::supports_avx(), "");
5056 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5057 attributes.set_rex_vex_w_reverted();
5058 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5059 emit_int8(0x59);
5060 emit_int8((unsigned char)(0xC0 | encode));
5061 }
5062
5063 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) {
5064 assert(VM_Version::supports_avx(), "");
5065 InstructionMark im(this);
5066 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5067 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
5068 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5069 emit_int8(0x59);
5070 emit_operand(dst, src);
5071 }
5072
5073 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5074 assert(VM_Version::supports_avx(), "");
5075 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5076 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5077 emit_int8(0x59);
5078 emit_int8((unsigned char)(0xC0 | encode));
5079 }
5080
5081 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) {
5082 assert(VM_Version::supports_avx(), "");
5083 InstructionMark im(this);
5084 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5085 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
5086 attributes.set_rex_vex_w_reverted();
5087 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5088 emit_int8(0x5C);
5089 emit_operand(dst, src);
5090 }
5091
5092 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5093 assert(VM_Version::supports_avx(), "");
5094 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5095 attributes.set_rex_vex_w_reverted();
5096 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5097 emit_int8(0x5C);
5098 emit_int8((unsigned char)(0xC0 | encode));
5099 }
5100
5101 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) {
5102 assert(VM_Version::supports_avx(), "");
5103 InstructionMark im(this);
5104 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5105 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
5106 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5107 emit_int8(0x5C);
5108 emit_operand(dst, src);
5109 }
5110
5111 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5112 assert(VM_Version::supports_avx(), "");
5113 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5114 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5115 emit_int8(0x5C);
5116 emit_int8((unsigned char)(0xC0 | encode));
5117 }
5118
5119 //====================VECTOR ARITHMETIC=====================================
5120
5121 // Float-point vector arithmetic
5122
5123 void Assembler::addpd(XMMRegister dst, XMMRegister src) {
5124 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5125 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5126 attributes.set_rex_vex_w_reverted();
5127 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5128 emit_int8(0x58);
5129 emit_int8((unsigned char)(0xC0 | encode));
5130 }
5131
5132 void Assembler::addpd(XMMRegister dst, Address src) {
5133 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5134 InstructionMark im(this);
5135 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5136 attributes.set_rex_vex_w_reverted();
5137 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5138 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5139 emit_int8(0x58);
5140 emit_operand(dst, src);
5141 }
5142
5143
5144 void Assembler::addps(XMMRegister dst, XMMRegister src) {
5145 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5146 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5147 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5148 emit_int8(0x58);
5149 emit_int8((unsigned char)(0xC0 | encode));
5150 }
5151
5152 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5153 assert(VM_Version::supports_avx(), "");
5154 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5155 attributes.set_rex_vex_w_reverted();
5156 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5157 emit_int8(0x58);
5158 emit_int8((unsigned char)(0xC0 | encode));
5159 }
5160
5161 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5162 assert(VM_Version::supports_avx(), "");
5163 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5164 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5165 emit_int8(0x58);
5166 emit_int8((unsigned char)(0xC0 | encode));
5167 }
5168
5169 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5170 assert(VM_Version::supports_avx(), "");
5171 InstructionMark im(this);
5172 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5173 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5174 attributes.set_rex_vex_w_reverted();
5175 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5176 emit_int8(0x58);
5177 emit_operand(dst, src);
5178 }
5179
5180 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5181 assert(VM_Version::supports_avx(), "");
5182 InstructionMark im(this);
5183 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5184 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5185 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5186 emit_int8(0x58);
5187 emit_operand(dst, src);
5188 }
5189
5190 void Assembler::subpd(XMMRegister dst, XMMRegister src) {
5191 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5192 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5193 attributes.set_rex_vex_w_reverted();
5194 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5195 emit_int8(0x5C);
5196 emit_int8((unsigned char)(0xC0 | encode));
5197 }
5198
5199 void Assembler::subps(XMMRegister dst, XMMRegister src) {
5200 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5201 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5202 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5203 emit_int8(0x5C);
5204 emit_int8((unsigned char)(0xC0 | encode));
5205 }
5206
5207 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5208 assert(VM_Version::supports_avx(), "");
5209 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5210 attributes.set_rex_vex_w_reverted();
5211 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5212 emit_int8(0x5C);
5213 emit_int8((unsigned char)(0xC0 | encode));
5214 }
5215
5216 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5217 assert(VM_Version::supports_avx(), "");
5218 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5219 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5220 emit_int8(0x5C);
5221 emit_int8((unsigned char)(0xC0 | encode));
5222 }
5223
5224 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5225 assert(VM_Version::supports_avx(), "");
5226 InstructionMark im(this);
5227 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5228 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5229 attributes.set_rex_vex_w_reverted();
5230 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5231 emit_int8(0x5C);
5232 emit_operand(dst, src);
5233 }
5234
5235 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5236 assert(VM_Version::supports_avx(), "");
5237 InstructionMark im(this);
5238 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5239 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5240 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5241 emit_int8(0x5C);
5242 emit_operand(dst, src);
5243 }
5244
5245 void Assembler::mulpd(XMMRegister dst, XMMRegister src) {
5246 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5247 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5248 attributes.set_rex_vex_w_reverted();
5249 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5250 emit_int8(0x59);
5251 emit_int8((unsigned char)(0xC0 | encode));
5252 }
5253
5254 void Assembler::mulpd(XMMRegister dst, Address src) {
5255 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5256 InstructionMark im(this);
5257 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5258 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5259 attributes.set_rex_vex_w_reverted();
5260 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5261 emit_int8(0x59);
5262 emit_operand(dst, src);
5263 }
5264
5265 void Assembler::mulps(XMMRegister dst, XMMRegister src) {
5266 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5267 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5268 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5269 emit_int8(0x59);
5270 emit_int8((unsigned char)(0xC0 | encode));
5271 }
5272
5273 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5274 assert(VM_Version::supports_avx(), "");
5275 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5276 attributes.set_rex_vex_w_reverted();
5277 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5278 emit_int8(0x59);
5279 emit_int8((unsigned char)(0xC0 | encode));
5280 }
5281
5282 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5283 assert(VM_Version::supports_avx(), "");
5284 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5285 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5286 emit_int8(0x59);
5287 emit_int8((unsigned char)(0xC0 | encode));
5288 }
5289
5290 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5291 assert(VM_Version::supports_avx(), "");
5292 InstructionMark im(this);
5293 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5294 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5295 attributes.set_rex_vex_w_reverted();
5296 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5297 emit_int8(0x59);
5298 emit_operand(dst, src);
5299 }
5300
5301 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5302 assert(VM_Version::supports_avx(), "");
5303 InstructionMark im(this);
5304 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5305 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5306 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5307 emit_int8(0x59);
5308 emit_operand(dst, src);
5309 }
5310
5311 void Assembler::vfmadd231pd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len) {
5312 assert(VM_Version::supports_fma(), "");
5313 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5314 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5315 emit_int8((unsigned char)0xB8);
5316 emit_int8((unsigned char)(0xC0 | encode));
5317 }
5318
5319 void Assembler::vfmadd231ps(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len) {
5320 assert(VM_Version::supports_fma(), "");
5321 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5322 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5323 emit_int8((unsigned char)0xB8);
5324 emit_int8((unsigned char)(0xC0 | encode));
5325 }
5326
5327 void Assembler::vfmadd231pd(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) {
5328 assert(VM_Version::supports_fma(), "");
5329 InstructionMark im(this);
5330 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5331 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5332 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5333 emit_int8((unsigned char)0xB8);
5334 emit_operand(dst, src2);
5335 }
5336
5337 void Assembler::vfmadd231ps(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) {
5338 assert(VM_Version::supports_fma(), "");
5339 InstructionMark im(this);
5340 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5341 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5342 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5343 emit_int8((unsigned char)0xB8);
5344 emit_operand(dst, src2);
5345 }
5346
5347 void Assembler::divpd(XMMRegister dst, XMMRegister src) {
5348 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5349 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5350 attributes.set_rex_vex_w_reverted();
5351 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5352 emit_int8(0x5E);
5353 emit_int8((unsigned char)(0xC0 | encode));
5354 }
5355
5356 void Assembler::divps(XMMRegister dst, XMMRegister src) {
5357 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5358 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5359 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5360 emit_int8(0x5E);
5361 emit_int8((unsigned char)(0xC0 | encode));
5362 }
5363
5364 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5365 assert(VM_Version::supports_avx(), "");
5366 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5367 attributes.set_rex_vex_w_reverted();
5368 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5369 emit_int8(0x5E);
5370 emit_int8((unsigned char)(0xC0 | encode));
5371 }
5372
5373 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5374 assert(VM_Version::supports_avx(), "");
5375 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5376 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5377 emit_int8(0x5E);
5378 emit_int8((unsigned char)(0xC0 | encode));
5379 }
5380
5381 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5382 assert(VM_Version::supports_avx(), "");
5383 InstructionMark im(this);
5384 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5385 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5386 attributes.set_rex_vex_w_reverted();
5387 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5388 emit_int8(0x5E);
5389 emit_operand(dst, src);
5390 }
5391
5392 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5393 assert(VM_Version::supports_avx(), "");
5394 InstructionMark im(this);
5395 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5396 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5397 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5398 emit_int8(0x5E);
5399 emit_operand(dst, src);
5400 }
5401
5402 void Assembler::vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len) {
5403 assert(VM_Version::supports_avx(), "");
5404 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5405 attributes.set_rex_vex_w_reverted();
5406 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5407 emit_int8(0x51);
5408 emit_int8((unsigned char)(0xC0 | encode));
5409 }
5410
5411 void Assembler::vsqrtpd(XMMRegister dst, Address src, int vector_len) {
5412 assert(VM_Version::supports_avx(), "");
5413 InstructionMark im(this);
5414 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5415 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5416 attributes.set_rex_vex_w_reverted();
5417 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5418 emit_int8(0x51);
5419 emit_operand(dst, src);
5420 }
5421
5422 void Assembler::vsqrtps(XMMRegister dst, XMMRegister src, int vector_len) {
5423 assert(VM_Version::supports_avx(), "");
5424 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5425 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5426 emit_int8(0x51);
5427 emit_int8((unsigned char)(0xC0 | encode));
5428 }
5429
5430 void Assembler::vsqrtps(XMMRegister dst, Address src, int vector_len) {
5431 assert(VM_Version::supports_avx(), "");
5432 InstructionMark im(this);
5433 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5434 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5435 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5436 emit_int8(0x51);
5437 emit_operand(dst, src);
5438 }
5439
5440 void Assembler::andpd(XMMRegister dst, XMMRegister src) {
5441 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5442 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5443 attributes.set_rex_vex_w_reverted();
5444 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5445 emit_int8(0x54);
5446 emit_int8((unsigned char)(0xC0 | encode));
5447 }
5448
5449 void Assembler::andps(XMMRegister dst, XMMRegister src) {
5450 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5451 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5452 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5453 emit_int8(0x54);
5454 emit_int8((unsigned char)(0xC0 | encode));
5455 }
5456
5457 void Assembler::andps(XMMRegister dst, Address src) {
5458 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5459 InstructionMark im(this);
5460 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5461 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5462 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5463 emit_int8(0x54);
5464 emit_operand(dst, src);
5465 }
5466
5467 void Assembler::andpd(XMMRegister dst, Address src) {
5468 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5469 InstructionMark im(this);
5470 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5471 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5472 attributes.set_rex_vex_w_reverted();
5473 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5474 emit_int8(0x54);
5475 emit_operand(dst, src);
5476 }
5477
5478 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5479 assert(VM_Version::supports_avx(), "");
5480 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5481 attributes.set_rex_vex_w_reverted();
5482 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5483 emit_int8(0x54);
5484 emit_int8((unsigned char)(0xC0 | encode));
5485 }
5486
5487 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5488 assert(VM_Version::supports_avx(), "");
5489 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5490 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5491 emit_int8(0x54);
5492 emit_int8((unsigned char)(0xC0 | encode));
5493 }
5494
5495 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5496 assert(VM_Version::supports_avx(), "");
5497 InstructionMark im(this);
5498 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5499 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5500 attributes.set_rex_vex_w_reverted();
5501 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5502 emit_int8(0x54);
5503 emit_operand(dst, src);
5504 }
5505
5506 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5507 assert(VM_Version::supports_avx(), "");
5508 InstructionMark im(this);
5509 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5510 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5511 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5512 emit_int8(0x54);
5513 emit_operand(dst, src);
5514 }
5515
5516 void Assembler::unpckhpd(XMMRegister dst, XMMRegister src) {
5517 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5518 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5519 attributes.set_rex_vex_w_reverted();
5520 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5521 emit_int8(0x15);
5522 emit_int8((unsigned char)(0xC0 | encode));
5523 }
5524
5525 void Assembler::unpcklpd(XMMRegister dst, XMMRegister src) {
5526 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5527 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5528 attributes.set_rex_vex_w_reverted();
5529 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5530 emit_int8(0x14);
5531 emit_int8((unsigned char)(0xC0 | encode));
5532 }
5533
5534 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
5535 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5536 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5537 attributes.set_rex_vex_w_reverted();
5538 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5539 emit_int8(0x57);
5540 emit_int8((unsigned char)(0xC0 | encode));
5541 }
5542
5543 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
5544 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5545 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5546 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5547 emit_int8(0x57);
5548 emit_int8((unsigned char)(0xC0 | encode));
5549 }
5550
5551 void Assembler::xorpd(XMMRegister dst, Address src) {
5552 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5553 InstructionMark im(this);
5554 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5555 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5556 attributes.set_rex_vex_w_reverted();
5557 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5558 emit_int8(0x57);
5559 emit_operand(dst, src);
5560 }
5561
5562 void Assembler::xorps(XMMRegister dst, Address src) {
5563 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5564 InstructionMark im(this);
5565 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5566 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5567 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5568 emit_int8(0x57);
5569 emit_operand(dst, src);
5570 }
5571
5572 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5573 assert(VM_Version::supports_avx(), "");
5574 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5575 attributes.set_rex_vex_w_reverted();
5576 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5577 emit_int8(0x57);
5578 emit_int8((unsigned char)(0xC0 | encode));
5579 }
5580
5581 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5582 assert(VM_Version::supports_avx(), "");
5583 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5584 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5585 emit_int8(0x57);
5586 emit_int8((unsigned char)(0xC0 | encode));
5587 }
5588
5589 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5590 assert(VM_Version::supports_avx(), "");
5591 InstructionMark im(this);
5592 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5593 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5594 attributes.set_rex_vex_w_reverted();
5595 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5596 emit_int8(0x57);
5597 emit_operand(dst, src);
5598 }
5599
5600 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5601 assert(VM_Version::supports_avx(), "");
5602 InstructionMark im(this);
5603 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5604 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5605 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5606 emit_int8(0x57);
5607 emit_operand(dst, src);
5608 }
5609
5610 // Integer vector arithmetic
5611 void Assembler::vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5612 assert(VM_Version::supports_avx() && (vector_len == 0) ||
5613 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
5614 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
5615 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5616 emit_int8(0x01);
5617 emit_int8((unsigned char)(0xC0 | encode));
5618 }
5619
5620 void Assembler::vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5621 assert(VM_Version::supports_avx() && (vector_len == 0) ||
5622 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
5623 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
5624 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5625 emit_int8(0x02);
5626 emit_int8((unsigned char)(0xC0 | encode));
5627 }
5628
5629 void Assembler::paddb(XMMRegister dst, XMMRegister src) {
5630 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5631 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5632 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5633 emit_int8((unsigned char)0xFC);
5634 emit_int8((unsigned char)(0xC0 | encode));
5635 }
5636
5637 void Assembler::paddw(XMMRegister dst, XMMRegister src) {
5638 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5639 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5640 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5641 emit_int8((unsigned char)0xFD);
5642 emit_int8((unsigned char)(0xC0 | encode));
5643 }
5644
5645 void Assembler::paddd(XMMRegister dst, XMMRegister src) {
5646 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5647 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5648 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5649 emit_int8((unsigned char)0xFE);
5650 emit_int8((unsigned char)(0xC0 | encode));
5651 }
5652
5653 void Assembler::paddd(XMMRegister dst, Address src) {
5654 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5655 InstructionMark im(this);
5656 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5657 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5658 emit_int8((unsigned char)0xFE);
5659 emit_operand(dst, src);
5660 }
5661
5662 void Assembler::paddq(XMMRegister dst, XMMRegister src) {
5663 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5664 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5665 attributes.set_rex_vex_w_reverted();
5666 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5667 emit_int8((unsigned char)0xD4);
5668 emit_int8((unsigned char)(0xC0 | encode));
5669 }
5670
5671 void Assembler::phaddw(XMMRegister dst, XMMRegister src) {
5672 assert(VM_Version::supports_sse3(), "");
5673 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
5674 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5675 emit_int8(0x01);
5676 emit_int8((unsigned char)(0xC0 | encode));
5677 }
5678
5679 void Assembler::phaddd(XMMRegister dst, XMMRegister src) {
5680 assert(VM_Version::supports_sse3(), "");
5681 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
5682 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5683 emit_int8(0x02);
5684 emit_int8((unsigned char)(0xC0 | encode));
5685 }
5686
5687 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5688 assert(UseAVX > 0, "requires some form of AVX");
5689 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5690 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5691 emit_int8((unsigned char)0xFC);
5692 emit_int8((unsigned char)(0xC0 | encode));
5693 }
5694
5695 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5696 assert(UseAVX > 0, "requires some form of AVX");
5697 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5698 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5699 emit_int8((unsigned char)0xFD);
5700 emit_int8((unsigned char)(0xC0 | encode));
5701 }
5702
5703 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5704 assert(UseAVX > 0, "requires some form of AVX");
5705 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5706 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5707 emit_int8((unsigned char)0xFE);
5708 emit_int8((unsigned char)(0xC0 | encode));
5709 }
5710
5711 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5712 assert(UseAVX > 0, "requires some form of AVX");
5713 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5714 attributes.set_rex_vex_w_reverted();
5715 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5716 emit_int8((unsigned char)0xD4);
5717 emit_int8((unsigned char)(0xC0 | encode));
5718 }
5719
5720 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5721 assert(UseAVX > 0, "requires some form of AVX");
5722 InstructionMark im(this);
5723 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5724 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5725 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5726 emit_int8((unsigned char)0xFC);
5727 emit_operand(dst, src);
5728 }
5729
5730 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5731 assert(UseAVX > 0, "requires some form of AVX");
5732 InstructionMark im(this);
5733 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5734 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5735 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5736 emit_int8((unsigned char)0xFD);
5737 emit_operand(dst, src);
5738 }
5739
5740 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5741 assert(UseAVX > 0, "requires some form of AVX");
5742 InstructionMark im(this);
5743 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5744 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5745 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5746 emit_int8((unsigned char)0xFE);
5747 emit_operand(dst, src);
5748 }
5749
5750 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5751 assert(UseAVX > 0, "requires some form of AVX");
5752 InstructionMark im(this);
5753 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5754 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5755 attributes.set_rex_vex_w_reverted();
5756 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5757 emit_int8((unsigned char)0xD4);
5758 emit_operand(dst, src);
5759 }
5760
5761 void Assembler::psubb(XMMRegister dst, XMMRegister src) {
5762 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5763 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5764 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5765 emit_int8((unsigned char)0xF8);
5766 emit_int8((unsigned char)(0xC0 | encode));
5767 }
5768
5769 void Assembler::psubw(XMMRegister dst, XMMRegister src) {
5770 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5771 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5772 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5773 emit_int8((unsigned char)0xF9);
5774 emit_int8((unsigned char)(0xC0 | encode));
5775 }
5776
5777 void Assembler::psubd(XMMRegister dst, XMMRegister src) {
5778 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5779 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5780 emit_int8((unsigned char)0xFA);
5781 emit_int8((unsigned char)(0xC0 | encode));
5782 }
5783
5784 void Assembler::psubq(XMMRegister dst, XMMRegister src) {
5785 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5786 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5787 attributes.set_rex_vex_w_reverted();
5788 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5789 emit_int8((unsigned char)0xFB);
5790 emit_int8((unsigned char)(0xC0 | encode));
5791 }
5792
5793 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5794 assert(UseAVX > 0, "requires some form of AVX");
5795 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5796 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5797 emit_int8((unsigned char)0xF8);
5798 emit_int8((unsigned char)(0xC0 | encode));
5799 }
5800
5801 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5802 assert(UseAVX > 0, "requires some form of AVX");
5803 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5804 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5805 emit_int8((unsigned char)0xF9);
5806 emit_int8((unsigned char)(0xC0 | encode));
5807 }
5808
5809 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5810 assert(UseAVX > 0, "requires some form of AVX");
5811 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5812 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5813 emit_int8((unsigned char)0xFA);
5814 emit_int8((unsigned char)(0xC0 | encode));
5815 }
5816
5817 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5818 assert(UseAVX > 0, "requires some form of AVX");
5819 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5820 attributes.set_rex_vex_w_reverted();
5821 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5822 emit_int8((unsigned char)0xFB);
5823 emit_int8((unsigned char)(0xC0 | encode));
5824 }
5825
5826 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5827 assert(UseAVX > 0, "requires some form of AVX");
5828 InstructionMark im(this);
5829 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5830 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5831 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5832 emit_int8((unsigned char)0xF8);
5833 emit_operand(dst, src);
5834 }
5835
5836 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5837 assert(UseAVX > 0, "requires some form of AVX");
5838 InstructionMark im(this);
5839 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5840 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5841 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5842 emit_int8((unsigned char)0xF9);
5843 emit_operand(dst, src);
5844 }
5845
5846 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5847 assert(UseAVX > 0, "requires some form of AVX");
5848 InstructionMark im(this);
5849 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5850 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5851 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5852 emit_int8((unsigned char)0xFA);
5853 emit_operand(dst, src);
5854 }
5855
5856 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5857 assert(UseAVX > 0, "requires some form of AVX");
5858 InstructionMark im(this);
5859 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5860 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5861 attributes.set_rex_vex_w_reverted();
5862 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5863 emit_int8((unsigned char)0xFB);
5864 emit_operand(dst, src);
5865 }
5866
5867 void Assembler::pmullw(XMMRegister dst, XMMRegister src) {
5868 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5869 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5870 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5871 emit_int8((unsigned char)0xD5);
5872 emit_int8((unsigned char)(0xC0 | encode));
5873 }
5874
5875 void Assembler::pmulld(XMMRegister dst, XMMRegister src) {
5876 assert(VM_Version::supports_sse4_1(), "");
5877 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5878 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5879 emit_int8(0x40);
5880 emit_int8((unsigned char)(0xC0 | encode));
5881 }
5882
5883 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5884 assert(UseAVX > 0, "requires some form of AVX");
5885 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5886 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5887 emit_int8((unsigned char)0xD5);
5888 emit_int8((unsigned char)(0xC0 | encode));
5889 }
5890
5891 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5892 assert(UseAVX > 0, "requires some form of AVX");
5893 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5894 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5895 emit_int8(0x40);
5896 emit_int8((unsigned char)(0xC0 | encode));
5897 }
5898
5899 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5900 assert(UseAVX > 2, "requires some form of EVEX");
5901 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5902 attributes.set_is_evex_instruction();
5903 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5904 emit_int8(0x40);
5905 emit_int8((unsigned char)(0xC0 | encode));
5906 }
5907
5908 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5909 assert(UseAVX > 0, "requires some form of AVX");
5910 InstructionMark im(this);
5911 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5912 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5913 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5914 emit_int8((unsigned char)0xD5);
5915 emit_operand(dst, src);
5916 }
5917
5918 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5919 assert(UseAVX > 0, "requires some form of AVX");
5920 InstructionMark im(this);
5921 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5922 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5923 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5924 emit_int8(0x40);
5925 emit_operand(dst, src);
5926 }
5927
5928 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5929 assert(UseAVX > 2, "requires some form of EVEX");
5930 InstructionMark im(this);
5931 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5932 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5933 attributes.set_is_evex_instruction();
5934 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5935 emit_int8(0x40);
5936 emit_operand(dst, src);
5937 }
5938
5939 // Shift packed integers left by specified number of bits.
5940 void Assembler::psllw(XMMRegister dst, int shift) {
5941 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5942 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5943 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
5944 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5945 emit_int8(0x71);
5946 emit_int8((unsigned char)(0xC0 | encode));
5947 emit_int8(shift & 0xFF);
5948 }
5949
5950 void Assembler::pslld(XMMRegister dst, int shift) {
5951 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5952 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5953 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
5954 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5955 emit_int8(0x72);
5956 emit_int8((unsigned char)(0xC0 | encode));
5957 emit_int8(shift & 0xFF);
5958 }
5959
5960 void Assembler::psllq(XMMRegister dst, int shift) {
5961 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5962 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5963 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
5964 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5965 emit_int8(0x73);
5966 emit_int8((unsigned char)(0xC0 | encode));
5967 emit_int8(shift & 0xFF);
5968 }
5969
5970 void Assembler::psllw(XMMRegister dst, XMMRegister shift) {
5971 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5972 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5973 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5974 emit_int8((unsigned char)0xF1);
5975 emit_int8((unsigned char)(0xC0 | encode));
5976 }
5977
5978 void Assembler::pslld(XMMRegister dst, XMMRegister shift) {
5979 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5980 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5981 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5982 emit_int8((unsigned char)0xF2);
5983 emit_int8((unsigned char)(0xC0 | encode));
5984 }
5985
5986 void Assembler::psllq(XMMRegister dst, XMMRegister shift) {
5987 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5988 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5989 attributes.set_rex_vex_w_reverted();
5990 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5991 emit_int8((unsigned char)0xF3);
5992 emit_int8((unsigned char)(0xC0 | encode));
5993 }
5994
5995 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5996 assert(UseAVX > 0, "requires some form of AVX");
5997 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5998 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
5999 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6000 emit_int8(0x71);
6001 emit_int8((unsigned char)(0xC0 | encode));
6002 emit_int8(shift & 0xFF);
6003 }
6004
6005 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6006 assert(UseAVX > 0, "requires some form of AVX");
6007 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6008 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6009 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
6010 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6011 emit_int8(0x72);
6012 emit_int8((unsigned char)(0xC0 | encode));
6013 emit_int8(shift & 0xFF);
6014 }
6015
6016 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6017 assert(UseAVX > 0, "requires some form of AVX");
6018 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6019 attributes.set_rex_vex_w_reverted();
6020 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
6021 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6022 emit_int8(0x73);
6023 emit_int8((unsigned char)(0xC0 | encode));
6024 emit_int8(shift & 0xFF);
6025 }
6026
6027 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6028 assert(UseAVX > 0, "requires some form of AVX");
6029 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6030 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6031 emit_int8((unsigned char)0xF1);
6032 emit_int8((unsigned char)(0xC0 | encode));
6033 }
6034
6035 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6036 assert(UseAVX > 0, "requires some form of AVX");
6037 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6038 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6039 emit_int8((unsigned char)0xF2);
6040 emit_int8((unsigned char)(0xC0 | encode));
6041 }
6042
6043 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6044 assert(UseAVX > 0, "requires some form of AVX");
6045 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6046 attributes.set_rex_vex_w_reverted();
6047 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6048 emit_int8((unsigned char)0xF3);
6049 emit_int8((unsigned char)(0xC0 | encode));
6050 }
6051
6052 // Shift packed integers logically right by specified number of bits.
6053 void Assembler::psrlw(XMMRegister dst, int shift) {
6054 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6055 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6056 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
6057 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6058 emit_int8(0x71);
6059 emit_int8((unsigned char)(0xC0 | encode));
6060 emit_int8(shift & 0xFF);
6061 }
6062
6063 void Assembler::psrld(XMMRegister dst, int shift) {
6064 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6065 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6066 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
6067 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6068 emit_int8(0x72);
6069 emit_int8((unsigned char)(0xC0 | encode));
6070 emit_int8(shift & 0xFF);
6071 }
6072
6073 void Assembler::psrlq(XMMRegister dst, int shift) {
6074 // Do not confuse it with psrldq SSE2 instruction which
6075 // shifts 128 bit value in xmm register by number of bytes.
6076 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6077 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6078 attributes.set_rex_vex_w_reverted();
6079 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
6080 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6081 emit_int8(0x73);
6082 emit_int8((unsigned char)(0xC0 | encode));
6083 emit_int8(shift & 0xFF);
6084 }
6085
6086 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) {
6087 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6088 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6089 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6090 emit_int8((unsigned char)0xD1);
6091 emit_int8((unsigned char)(0xC0 | encode));
6092 }
6093
6094 void Assembler::psrld(XMMRegister dst, XMMRegister shift) {
6095 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6096 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6097 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6098 emit_int8((unsigned char)0xD2);
6099 emit_int8((unsigned char)(0xC0 | encode));
6100 }
6101
6102 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) {
6103 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6104 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6105 attributes.set_rex_vex_w_reverted();
6106 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6107 emit_int8((unsigned char)0xD3);
6108 emit_int8((unsigned char)(0xC0 | encode));
6109 }
6110
6111 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6112 assert(UseAVX > 0, "requires some form of AVX");
6113 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6114 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
6115 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6116 emit_int8(0x71);
6117 emit_int8((unsigned char)(0xC0 | encode));
6118 emit_int8(shift & 0xFF);
6119 }
6120
6121 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6122 assert(UseAVX > 0, "requires some form of AVX");
6123 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6124 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
6125 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6126 emit_int8(0x72);
6127 emit_int8((unsigned char)(0xC0 | encode));
6128 emit_int8(shift & 0xFF);
6129 }
6130
6131 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6132 assert(UseAVX > 0, "requires some form of AVX");
6133 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6134 attributes.set_rex_vex_w_reverted();
6135 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
6136 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6137 emit_int8(0x73);
6138 emit_int8((unsigned char)(0xC0 | encode));
6139 emit_int8(shift & 0xFF);
6140 }
6141
6142 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6143 assert(UseAVX > 0, "requires some form of AVX");
6144 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6145 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6146 emit_int8((unsigned char)0xD1);
6147 emit_int8((unsigned char)(0xC0 | encode));
6148 }
6149
6150 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6151 assert(UseAVX > 0, "requires some form of AVX");
6152 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6153 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6154 emit_int8((unsigned char)0xD2);
6155 emit_int8((unsigned char)(0xC0 | encode));
6156 }
6157
6158 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6159 assert(UseAVX > 0, "requires some form of AVX");
6160 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6161 attributes.set_rex_vex_w_reverted();
6162 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6163 emit_int8((unsigned char)0xD3);
6164 emit_int8((unsigned char)(0xC0 | encode));
6165 }
6166
6167 void Assembler::evpsrlvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6168 assert(VM_Version::supports_avx512bw(), "");
6169 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6170 attributes.set_is_evex_instruction();
6171 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6172 emit_int8(0x10);
6173 emit_int8((unsigned char)(0xC0 | encode));
6174 }
6175
6176 void Assembler::evpsllvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6177 assert(VM_Version::supports_avx512bw(), "");
6178 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6179 attributes.set_is_evex_instruction();
6180 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6181 emit_int8(0x12);
6182 emit_int8((unsigned char)(0xC0 | encode));
6183 }
6184
6185 // Shift packed integers arithmetically right by specified number of bits.
6186 void Assembler::psraw(XMMRegister dst, int shift) {
6187 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6188 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6189 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
6190 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6191 emit_int8(0x71);
6192 emit_int8((unsigned char)(0xC0 | encode));
6193 emit_int8(shift & 0xFF);
6194 }
6195
6196 void Assembler::psrad(XMMRegister dst, int shift) {
6197 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6198 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6199 // XMM4 is for /4 encoding: 66 0F 72 /4 ib
6200 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6201 emit_int8(0x72);
6202 emit_int8((unsigned char)(0xC0 | encode));
6203 emit_int8(shift & 0xFF);
6204 }
6205
6206 void Assembler::psraw(XMMRegister dst, XMMRegister shift) {
6207 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6208 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6209 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6210 emit_int8((unsigned char)0xE1);
6211 emit_int8((unsigned char)(0xC0 | encode));
6212 }
6213
6214 void Assembler::psrad(XMMRegister dst, XMMRegister shift) {
6215 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6216 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6217 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6218 emit_int8((unsigned char)0xE2);
6219 emit_int8((unsigned char)(0xC0 | encode));
6220 }
6221
6222 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6223 assert(UseAVX > 0, "requires some form of AVX");
6224 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6225 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
6226 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6227 emit_int8(0x71);
6228 emit_int8((unsigned char)(0xC0 | encode));
6229 emit_int8(shift & 0xFF);
6230 }
6231
6232 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6233 assert(UseAVX > 0, "requires some form of AVX");
6234 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6235 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
6236 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6237 emit_int8(0x72);
6238 emit_int8((unsigned char)(0xC0 | encode));
6239 emit_int8(shift & 0xFF);
6240 }
6241
6242 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6243 assert(UseAVX > 0, "requires some form of AVX");
6244 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6245 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6246 emit_int8((unsigned char)0xE1);
6247 emit_int8((unsigned char)(0xC0 | encode));
6248 }
6249
6250 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6251 assert(UseAVX > 0, "requires some form of AVX");
6252 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6253 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6254 emit_int8((unsigned char)0xE2);
6255 emit_int8((unsigned char)(0xC0 | encode));
6256 }
6257
6258
6259 // logical operations packed integers
6260 void Assembler::pand(XMMRegister dst, XMMRegister src) {
6261 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6262 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6263 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6264 emit_int8((unsigned char)0xDB);
6265 emit_int8((unsigned char)(0xC0 | encode));
6266 }
6267
6268 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6269 assert(UseAVX > 0, "requires some form of AVX");
6270 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6271 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6272 emit_int8((unsigned char)0xDB);
6273 emit_int8((unsigned char)(0xC0 | encode));
6274 }
6275
6276 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6277 assert(UseAVX > 0, "requires some form of AVX");
6278 InstructionMark im(this);
6279 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6280 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
6281 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6282 emit_int8((unsigned char)0xDB);
6283 emit_operand(dst, src);
6284 }
6285
6286 void Assembler::vpandq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6287 assert(VM_Version::supports_evex(), "");
6288 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6289 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6290 emit_int8((unsigned char)0xDB);
6291 emit_int8((unsigned char)(0xC0 | encode));
6292 }
6293
6294
6295 void Assembler::pandn(XMMRegister dst, XMMRegister src) {
6296 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6297 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6298 attributes.set_rex_vex_w_reverted();
6299 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6300 emit_int8((unsigned char)0xDF);
6301 emit_int8((unsigned char)(0xC0 | encode));
6302 }
6303
6304 void Assembler::vpandn(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6305 assert(UseAVX > 0, "requires some form of AVX");
6306 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6307 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6308 emit_int8((unsigned char)0xDF);
6309 emit_int8((unsigned char)(0xC0 | encode));
6310 }
6311
6312
6313 void Assembler::por(XMMRegister dst, XMMRegister src) {
6314 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6315 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6316 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6317 emit_int8((unsigned char)0xEB);
6318 emit_int8((unsigned char)(0xC0 | encode));
6319 }
6320
6321 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6322 assert(UseAVX > 0, "requires some form of AVX");
6323 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6324 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6325 emit_int8((unsigned char)0xEB);
6326 emit_int8((unsigned char)(0xC0 | encode));
6327 }
6328
6329 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6330 assert(UseAVX > 0, "requires some form of AVX");
6331 InstructionMark im(this);
6332 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6333 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
6334 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6335 emit_int8((unsigned char)0xEB);
6336 emit_operand(dst, src);
6337 }
6338
6339 void Assembler::vporq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6340 assert(VM_Version::supports_evex(), "");
6341 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6342 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6343 emit_int8((unsigned char)0xEB);
6344 emit_int8((unsigned char)(0xC0 | encode));
6345 }
6346
6347
6348 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
6349 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6350 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6351 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6352 emit_int8((unsigned char)0xEF);
6353 emit_int8((unsigned char)(0xC0 | encode));
6354 }
6355
6356 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6357 assert(UseAVX > 0, "requires some form of AVX");
6358 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6359 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6360 emit_int8((unsigned char)0xEF);
6361 emit_int8((unsigned char)(0xC0 | encode));
6362 }
6363
6364 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6365 assert(UseAVX > 0, "requires some form of AVX");
6366 InstructionMark im(this);
6367 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6368 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
6369 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6370 emit_int8((unsigned char)0xEF);
6371 emit_operand(dst, src);
6372 }
6373
6374 void Assembler::evpxorq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6375 assert(VM_Version::supports_evex(), "requires EVEX support");
6376 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6377 attributes.set_is_evex_instruction();
6378 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6379 emit_int8((unsigned char)0xEF);
6380 emit_int8((unsigned char)(0xC0 | encode));
6381 }
6382
6383 void Assembler::evpxorq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6384 assert(VM_Version::supports_evex(), "requires EVEX support");
6385 assert(dst != xnoreg, "sanity");
6386 InstructionMark im(this);
6387 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6388 attributes.set_is_evex_instruction();
6389 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
6390 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6391 emit_int8((unsigned char)0xEF);
6392 emit_operand(dst, src);
6393 }
6394
6395
6396 // vinserti forms
6397
6398 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6399 assert(VM_Version::supports_avx2(), "");
6400 assert(imm8 <= 0x01, "imm8: %u", imm8);
6401 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6402 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6403 emit_int8(0x38);
6404 emit_int8((unsigned char)(0xC0 | encode));
6405 // 0x00 - insert into lower 128 bits
6406 // 0x01 - insert into upper 128 bits
6407 emit_int8(imm8 & 0x01);
6408 }
6409
6410 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6411 assert(VM_Version::supports_avx2(), "");
6412 assert(dst != xnoreg, "sanity");
6413 assert(imm8 <= 0x01, "imm8: %u", imm8);
6414 InstructionMark im(this);
6415 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6416 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6417 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6418 emit_int8(0x38);
6419 emit_operand(dst, src);
6420 // 0x00 - insert into lower 128 bits
6421 // 0x01 - insert into upper 128 bits
6422 emit_int8(imm8 & 0x01);
6423 }
6424
6425 void Assembler::vinserti32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6426 assert(VM_Version::supports_evex(), "");
6427 assert(imm8 <= 0x03, "imm8: %u", imm8);
6428 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6429 attributes.set_is_evex_instruction();
6430 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6431 emit_int8(0x38);
6432 emit_int8((unsigned char)(0xC0 | encode));
6433 // 0x00 - insert into q0 128 bits (0..127)
6434 // 0x01 - insert into q1 128 bits (128..255)
6435 // 0x02 - insert into q2 128 bits (256..383)
6436 // 0x03 - insert into q3 128 bits (384..511)
6437 emit_int8(imm8 & 0x03);
6438 }
6439
6440 void Assembler::vinserti32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6441 assert(VM_Version::supports_avx(), "");
6442 assert(dst != xnoreg, "sanity");
6443 assert(imm8 <= 0x03, "imm8: %u", imm8);
6444 InstructionMark im(this);
6445 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6446 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6447 attributes.set_is_evex_instruction();
6448 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6449 emit_int8(0x18);
6450 emit_operand(dst, src);
6451 // 0x00 - insert into q0 128 bits (0..127)
6452 // 0x01 - insert into q1 128 bits (128..255)
6453 // 0x02 - insert into q2 128 bits (256..383)
6454 // 0x03 - insert into q3 128 bits (384..511)
6455 emit_int8(imm8 & 0x03);
6456 }
6457
6458 void Assembler::vinserti64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6459 assert(VM_Version::supports_evex(), "");
6460 assert(imm8 <= 0x01, "imm8: %u", imm8);
6461 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6462 attributes.set_is_evex_instruction();
6463 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6464 emit_int8(0x3A);
6465 emit_int8((unsigned char)(0xC0 | encode));
6466 // 0x00 - insert into lower 256 bits
6467 // 0x01 - insert into upper 256 bits
6468 emit_int8(imm8 & 0x01);
6469 }
6470
6471
6472 // vinsertf forms
6473
6474 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6475 assert(VM_Version::supports_avx(), "");
6476 assert(imm8 <= 0x01, "imm8: %u", imm8);
6477 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6478 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6479 emit_int8(0x18);
6480 emit_int8((unsigned char)(0xC0 | encode));
6481 // 0x00 - insert into lower 128 bits
6482 // 0x01 - insert into upper 128 bits
6483 emit_int8(imm8 & 0x01);
6484 }
6485
6486 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6487 assert(VM_Version::supports_avx(), "");
6488 assert(dst != xnoreg, "sanity");
6489 assert(imm8 <= 0x01, "imm8: %u", imm8);
6490 InstructionMark im(this);
6491 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6492 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6493 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6494 emit_int8(0x18);
6495 emit_operand(dst, src);
6496 // 0x00 - insert into lower 128 bits
6497 // 0x01 - insert into upper 128 bits
6498 emit_int8(imm8 & 0x01);
6499 }
6500
6501 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6502 assert(VM_Version::supports_avx2(), "");
6503 assert(imm8 <= 0x03, "imm8: %u", imm8);
6504 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6505 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6506 emit_int8(0x18);
6507 emit_int8((unsigned char)(0xC0 | encode));
6508 // 0x00 - insert into q0 128 bits (0..127)
6509 // 0x01 - insert into q1 128 bits (128..255)
6510 // 0x02 - insert into q0 128 bits (256..383)
6511 // 0x03 - insert into q1 128 bits (384..512)
6512 emit_int8(imm8 & 0x03);
6513 }
6514
6515 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6516 assert(VM_Version::supports_avx(), "");
6517 assert(dst != xnoreg, "sanity");
6518 assert(imm8 <= 0x03, "imm8: %u", imm8);
6519 InstructionMark im(this);
6520 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6521 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6522 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6523 emit_int8(0x18);
6524 emit_operand(dst, src);
6525 // 0x00 - insert into q0 128 bits (0..127)
6526 // 0x01 - insert into q1 128 bits (128..255)
6527 // 0x02 - insert into q0 128 bits (256..383)
6528 // 0x03 - insert into q1 128 bits (384..512)
6529 emit_int8(imm8 & 0x03);
6530 }
6531
6532 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6533 assert(VM_Version::supports_evex(), "");
6534 assert(imm8 <= 0x01, "imm8: %u", imm8);
6535 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6536 attributes.set_is_evex_instruction();
6537 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6538 emit_int8(0x1A);
6539 emit_int8((unsigned char)(0xC0 | encode));
6540 // 0x00 - insert into lower 256 bits
6541 // 0x01 - insert into upper 256 bits
6542 emit_int8(imm8 & 0x01);
6543 }
6544
6545 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6546 assert(VM_Version::supports_evex(), "");
6547 assert(dst != xnoreg, "sanity");
6548 assert(imm8 <= 0x01, "imm8: %u", imm8);
6549 InstructionMark im(this);
6550 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6551 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_64bit);
6552 attributes.set_is_evex_instruction();
6553 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6554 emit_int8(0x1A);
6555 emit_operand(dst, src);
6556 // 0x00 - insert into lower 256 bits
6557 // 0x01 - insert into upper 256 bits
6558 emit_int8(imm8 & 0x01);
6559 }
6560
6561
6562 // vextracti forms
6563
6564 void Assembler::vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6565 assert(VM_Version::supports_avx2(), "");
6566 assert(imm8 <= 0x01, "imm8: %u", imm8);
6567 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6568 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6569 emit_int8(0x39);
6570 emit_int8((unsigned char)(0xC0 | encode));
6571 // 0x00 - extract from lower 128 bits
6572 // 0x01 - extract from upper 128 bits
6573 emit_int8(imm8 & 0x01);
6574 }
6575
6576 void Assembler::vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
6577 assert(VM_Version::supports_avx2(), "");
6578 assert(src != xnoreg, "sanity");
6579 assert(imm8 <= 0x01, "imm8: %u", imm8);
6580 InstructionMark im(this);
6581 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6582 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6583 attributes.reset_is_clear_context();
6584 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6585 emit_int8(0x39);
6586 emit_operand(src, dst);
6587 // 0x00 - extract from lower 128 bits
6588 // 0x01 - extract from upper 128 bits
6589 emit_int8(imm8 & 0x01);
6590 }
6591
6592 void Assembler::vextracti32x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6593 assert(VM_Version::supports_evex(), "");
6594 assert(imm8 <= 0x03, "imm8: %u", imm8);
6595 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6596 attributes.set_is_evex_instruction();
6597 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6598 emit_int8(0x39);
6599 emit_int8((unsigned char)(0xC0 | encode));
6600 // 0x00 - extract from bits 127:0
6601 // 0x01 - extract from bits 255:128
6602 // 0x02 - extract from bits 383:256
6603 // 0x03 - extract from bits 511:384
6604 emit_int8(imm8 & 0x03);
6605 }
6606
6607 void Assembler::vextracti32x4(Address dst, XMMRegister src, uint8_t imm8) {
6608 assert(VM_Version::supports_evex(), "");
6609 assert(src != xnoreg, "sanity");
6610 assert(imm8 <= 0x03, "imm8: %u", imm8);
6611 InstructionMark im(this);
6612 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6613 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6614 attributes.reset_is_clear_context();
6615 attributes.set_is_evex_instruction();
6616 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6617 emit_int8(0x39);
6618 emit_operand(src, dst);
6619 // 0x00 - extract from bits 127:0
6620 // 0x01 - extract from bits 255:128
6621 // 0x02 - extract from bits 383:256
6622 // 0x03 - extract from bits 511:384
6623 emit_int8(imm8 & 0x03);
6624 }
6625
6626 void Assembler::vextracti64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6627 assert(VM_Version::supports_avx512dq(), "");
6628 assert(imm8 <= 0x03, "imm8: %u", imm8);
6629 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6630 attributes.set_is_evex_instruction();
6631 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6632 emit_int8(0x39);
6633 emit_int8((unsigned char)(0xC0 | encode));
6634 // 0x00 - extract from bits 127:0
6635 // 0x01 - extract from bits 255:128
6636 // 0x02 - extract from bits 383:256
6637 // 0x03 - extract from bits 511:384
6638 emit_int8(imm8 & 0x03);
6639 }
6640
6641 void Assembler::vextracti64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6642 assert(VM_Version::supports_evex(), "");
6643 assert(imm8 <= 0x01, "imm8: %u", imm8);
6644 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6645 attributes.set_is_evex_instruction();
6646 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6647 emit_int8(0x3B);
6648 emit_int8((unsigned char)(0xC0 | encode));
6649 // 0x00 - extract from lower 256 bits
6650 // 0x01 - extract from upper 256 bits
6651 emit_int8(imm8 & 0x01);
6652 }
6653
6654 void Assembler::vextracti64x4(Address dst, XMMRegister src, uint8_t imm8) {
6655 assert(VM_Version::supports_evex(), "");
6656 assert(src != xnoreg, "sanity");
6657 assert(imm8 <= 0x01, "imm8: %u", imm8);
6658 InstructionMark im(this);
6659 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6660 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_64bit);
6661 attributes.reset_is_clear_context();
6662 attributes.set_is_evex_instruction();
6663 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6664 emit_int8(0x38);
6665 emit_operand(src, dst);
6666 // 0x00 - extract from lower 256 bits
6667 // 0x01 - extract from upper 256 bits
6668 emit_int8(imm8 & 0x01);
6669 }
6670 // vextractf forms
6671
6672 void Assembler::vextractf128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6673 assert(VM_Version::supports_avx(), "");
6674 assert(imm8 <= 0x01, "imm8: %u", imm8);
6675 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6676 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6677 emit_int8(0x19);
6678 emit_int8((unsigned char)(0xC0 | encode));
6679 // 0x00 - extract from lower 128 bits
6680 // 0x01 - extract from upper 128 bits
6681 emit_int8(imm8 & 0x01);
6682 }
6683
6684 void Assembler::vextractf128(Address dst, XMMRegister src, uint8_t imm8) {
6685 assert(VM_Version::supports_avx(), "");
6686 assert(src != xnoreg, "sanity");
6687 assert(imm8 <= 0x01, "imm8: %u", imm8);
6688 InstructionMark im(this);
6689 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6690 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6691 attributes.reset_is_clear_context();
6692 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6693 emit_int8(0x19);
6694 emit_operand(src, dst);
6695 // 0x00 - extract from lower 128 bits
6696 // 0x01 - extract from upper 128 bits
6697 emit_int8(imm8 & 0x01);
6698 }
6699
6700 void Assembler::vextractf32x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6701 assert(VM_Version::supports_evex(), "");
6702 assert(imm8 <= 0x03, "imm8: %u", imm8);
6703 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6704 attributes.set_is_evex_instruction();
6705 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6706 emit_int8(0x19);
6707 emit_int8((unsigned char)(0xC0 | encode));
6708 // 0x00 - extract from bits 127:0
6709 // 0x01 - extract from bits 255:128
6710 // 0x02 - extract from bits 383:256
6711 // 0x03 - extract from bits 511:384
6712 emit_int8(imm8 & 0x03);
6713 }
6714
6715 void Assembler::vextractf32x4(Address dst, XMMRegister src, uint8_t imm8) {
6716 assert(VM_Version::supports_evex(), "");
6717 assert(src != xnoreg, "sanity");
6718 assert(imm8 <= 0x03, "imm8: %u", imm8);
6719 InstructionMark im(this);
6720 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6721 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6722 attributes.reset_is_clear_context();
6723 attributes.set_is_evex_instruction();
6724 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6725 emit_int8(0x19);
6726 emit_operand(src, dst);
6727 // 0x00 - extract from bits 127:0
6728 // 0x01 - extract from bits 255:128
6729 // 0x02 - extract from bits 383:256
6730 // 0x03 - extract from bits 511:384
6731 emit_int8(imm8 & 0x03);
6732 }
6733
6734 void Assembler::vextractf64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6735 assert(VM_Version::supports_avx512dq(), "");
6736 assert(imm8 <= 0x03, "imm8: %u", imm8);
6737 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6738 attributes.set_is_evex_instruction();
6739 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6740 emit_int8(0x19);
6741 emit_int8((unsigned char)(0xC0 | encode));
6742 // 0x00 - extract from bits 127:0
6743 // 0x01 - extract from bits 255:128
6744 // 0x02 - extract from bits 383:256
6745 // 0x03 - extract from bits 511:384
6746 emit_int8(imm8 & 0x03);
6747 }
6748
6749 void Assembler::vextractf64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6750 assert(VM_Version::supports_evex(), "");
6751 assert(imm8 <= 0x01, "imm8: %u", imm8);
6752 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6753 attributes.set_is_evex_instruction();
6754 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6755 emit_int8(0x1B);
6756 emit_int8((unsigned char)(0xC0 | encode));
6757 // 0x00 - extract from lower 256 bits
6758 // 0x01 - extract from upper 256 bits
6759 emit_int8(imm8 & 0x01);
6760 }
6761
6762 void Assembler::vextractf64x4(Address dst, XMMRegister src, uint8_t imm8) {
6763 assert(VM_Version::supports_evex(), "");
6764 assert(src != xnoreg, "sanity");
6765 assert(imm8 <= 0x01, "imm8: %u", imm8);
6766 InstructionMark im(this);
6767 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6768 attributes.set_address_attributes(/* tuple_type */ EVEX_T4,/* input_size_in_bits */ EVEX_64bit);
6769 attributes.reset_is_clear_context();
6770 attributes.set_is_evex_instruction();
6771 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6772 emit_int8(0x1B);
6773 emit_operand(src, dst);
6774 // 0x00 - extract from lower 256 bits
6775 // 0x01 - extract from upper 256 bits
6776 emit_int8(imm8 & 0x01);
6777 }
6778
6779 // duplicate 1-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
6780 void Assembler::vpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len) {
6781 assert(VM_Version::supports_avx2(), "");
6782 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6783 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6784 emit_int8(0x78);
6785 emit_int8((unsigned char)(0xC0 | encode));
6786 }
6787
6788 void Assembler::vpbroadcastb(XMMRegister dst, Address src, int vector_len) {
6789 assert(VM_Version::supports_avx2(), "");
6790 assert(dst != xnoreg, "sanity");
6791 InstructionMark im(this);
6792 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6793 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
6794 // swap src<->dst for encoding
6795 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6796 emit_int8(0x78);
6797 emit_operand(dst, src);
6798 }
6799
6800 // duplicate 2-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
6801 void Assembler::vpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len) {
6802 assert(VM_Version::supports_avx2(), "");
6803 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6804 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6805 emit_int8(0x79);
6806 emit_int8((unsigned char)(0xC0 | encode));
6807 }
6808
6809 void Assembler::vpbroadcastw(XMMRegister dst, Address src, int vector_len) {
6810 assert(VM_Version::supports_avx2(), "");
6811 assert(dst != xnoreg, "sanity");
6812 InstructionMark im(this);
6813 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6814 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
6815 // swap src<->dst for encoding
6816 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6817 emit_int8(0x79);
6818 emit_operand(dst, src);
6819 }
6820
6821 // xmm/mem sourced byte/word/dword/qword replicate
6822
6823 // duplicate 4-byte integer data from src into programmed locations in dest : requires AVX512VL
6824 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len) {
6825 assert(UseAVX >= 2, "");
6826 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6827 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6828 emit_int8(0x58);
6829 emit_int8((unsigned char)(0xC0 | encode));
6830 }
6831
6832 void Assembler::vpbroadcastd(XMMRegister dst, Address src, int vector_len) {
6833 assert(VM_Version::supports_avx2(), "");
6834 assert(dst != xnoreg, "sanity");
6835 InstructionMark im(this);
6836 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6837 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
6838 // swap src<->dst for encoding
6839 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6840 emit_int8(0x58);
6841 emit_operand(dst, src);
6842 }
6843
6844 // duplicate 8-byte integer data from src into programmed locations in dest : requires AVX512VL
6845 void Assembler::vpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len) {
6846 assert(VM_Version::supports_avx2(), "");
6847 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6848 attributes.set_rex_vex_w_reverted();
6849 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6850 emit_int8(0x59);
6851 emit_int8((unsigned char)(0xC0 | encode));
6852 }
6853
6854 void Assembler::vpbroadcastq(XMMRegister dst, Address src, int vector_len) {
6855 assert(VM_Version::supports_avx2(), "");
6856 assert(dst != xnoreg, "sanity");
6857 InstructionMark im(this);
6858 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6859 attributes.set_rex_vex_w_reverted();
6860 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6861 // swap src<->dst for encoding
6862 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6863 emit_int8(0x59);
6864 emit_operand(dst, src);
6865 }
6866 void Assembler::evbroadcasti64x2(XMMRegister dst, XMMRegister src, int vector_len) {
6867 assert(vector_len != Assembler::AVX_128bit, "");
6868 assert(VM_Version::supports_avx512dq(), "");
6869 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6870 attributes.set_rex_vex_w_reverted();
6871 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6872 emit_int8(0x5A);
6873 emit_int8((unsigned char)(0xC0 | encode));
6874 }
6875
6876 void Assembler::evbroadcasti64x2(XMMRegister dst, Address src, int vector_len) {
6877 assert(vector_len != Assembler::AVX_128bit, "");
6878 assert(VM_Version::supports_avx512dq(), "");
6879 assert(dst != xnoreg, "sanity");
6880 InstructionMark im(this);
6881 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6882 attributes.set_rex_vex_w_reverted();
6883 attributes.set_address_attributes(/* tuple_type */ EVEX_T2, /* input_size_in_bits */ EVEX_64bit);
6884 // swap src<->dst for encoding
6885 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6886 emit_int8(0x5A);
6887 emit_operand(dst, src);
6888 }
6889
6890 // scalar single/double precision replicate
6891
6892 // duplicate single precision data from src into programmed locations in dest : requires AVX512VL
6893 void Assembler::vpbroadcastss(XMMRegister dst, XMMRegister src, int vector_len) {
6894 assert(VM_Version::supports_avx(), "");
6895 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6896 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6897 emit_int8(0x18);
6898 emit_int8((unsigned char)(0xC0 | encode));
6899 }
6900
6901 void Assembler::vpbroadcastss(XMMRegister dst, Address src, int vector_len) {
6902 assert(VM_Version::supports_avx(), "");
6903 assert(dst != xnoreg, "sanity");
6904 InstructionMark im(this);
6905 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6906 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
6907 // swap src<->dst for encoding
6908 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6909 emit_int8(0x18);
6910 emit_operand(dst, src);
6911 }
6912
6913 // duplicate double precision data from src into programmed locations in dest : requires AVX512VL
6914 void Assembler::vpbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len) {
6915 assert(VM_Version::supports_avx(), "");
6916 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6917 attributes.set_rex_vex_w_reverted();
6918 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6919 emit_int8(0x19);
6920 emit_int8((unsigned char)(0xC0 | encode));
6921 }
6922
6923 void Assembler::vpbroadcastsd(XMMRegister dst, Address src, int vector_len) {
6924 assert(VM_Version::supports_avx(), "");
6925 assert(dst != xnoreg, "sanity");
6926 InstructionMark im(this);
6927 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6928 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6929 attributes.set_rex_vex_w_reverted();
6930 // swap src<->dst for encoding
6931 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6932 emit_int8(0x19);
6933 emit_operand(dst, src);
6934 }
6935
6936
6937 // gpr source broadcast forms
6938
6939 // duplicate 1-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
6940 void Assembler::evpbroadcastb(XMMRegister dst, Register src, int vector_len) {
6941 assert(VM_Version::supports_avx512bw(), "");
6942 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6943 attributes.set_is_evex_instruction();
6944 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6945 emit_int8(0x7A);
6946 emit_int8((unsigned char)(0xC0 | encode));
6947 }
6948
6949 // duplicate 2-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
6950 void Assembler::evpbroadcastw(XMMRegister dst, Register src, int vector_len) {
6951 assert(VM_Version::supports_avx512bw(), "");
6952 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6953 attributes.set_is_evex_instruction();
6954 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6955 emit_int8(0x7B);
6956 emit_int8((unsigned char)(0xC0 | encode));
6957 }
6958
6959 // duplicate 4-byte integer data from src into programmed locations in dest : requires AVX512VL
6960 void Assembler::evpbroadcastd(XMMRegister dst, Register src, int vector_len) {
6961 assert(VM_Version::supports_evex(), "");
6962 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6963 attributes.set_is_evex_instruction();
6964 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6965 emit_int8(0x7C);
6966 emit_int8((unsigned char)(0xC0 | encode));
6967 }
6968
6969 // duplicate 8-byte integer data from src into programmed locations in dest : requires AVX512VL
6970 void Assembler::evpbroadcastq(XMMRegister dst, Register src, int vector_len) {
6971 assert(VM_Version::supports_evex(), "");
6972 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6973 attributes.set_is_evex_instruction();
6974 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6975 emit_int8(0x7C);
6976 emit_int8((unsigned char)(0xC0 | encode));
6977 }
6978
6979 void Assembler::evpgatherdd(XMMRegister dst, KRegister mask, Address src, int vector_len) {
6980 assert(VM_Version::supports_evex(), "");
6981 assert(dst != xnoreg, "sanity");
6982 InstructionMark im(this);
6983 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6984 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6985 attributes.reset_is_clear_context();
6986 attributes.set_embedded_opmask_register_specifier(mask);
6987 attributes.set_is_evex_instruction();
6988 // swap src<->dst for encoding
6989 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6990 emit_int8((unsigned char)0x90);
6991 emit_operand(dst, src);
6992 }
6993
6994 // Carry-Less Multiplication Quadword
6995 void Assembler::pclmulqdq(XMMRegister dst, XMMRegister src, int mask) {
6996 assert(VM_Version::supports_clmul(), "");
6997 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
6998 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6999 emit_int8(0x44);
7000 emit_int8((unsigned char)(0xC0 | encode));
7001 emit_int8((unsigned char)mask);
7002 }
7003
7004 // Carry-Less Multiplication Quadword
7005 void Assembler::vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask) {
7006 assert(VM_Version::supports_avx() && VM_Version::supports_clmul(), "");
7007 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
7008 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7009 emit_int8(0x44);
7010 emit_int8((unsigned char)(0xC0 | encode));
7011 emit_int8((unsigned char)mask);
7012 }
7013
7014 void Assembler::evpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask, int vector_len) {
7015 assert(VM_Version::supports_vpclmulqdq(), "Requires vector carryless multiplication support");
7016 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7017 attributes.set_is_evex_instruction();
7018 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7019 emit_int8(0x44);
7020 emit_int8((unsigned char)(0xC0 | encode));
7021 emit_int8((unsigned char)mask);
7022 }
7023
7024 void Assembler::vzeroupper() {
7025 if (VM_Version::supports_vzeroupper()) {
7026 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
7027 (void)vex_prefix_and_encode(0, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7028 emit_int8(0x77);
7029 }
7030 }
7031
7032 #ifndef _LP64
7033 // 32bit only pieces of the assembler
7034
7035 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
7036 // NO PREFIX AS NEVER 64BIT
7037 InstructionMark im(this);
7038 emit_int8((unsigned char)0x81);
7039 emit_int8((unsigned char)(0xF8 | src1->encoding()));
7040 emit_data(imm32, rspec, 0);
7041 }
7042
7043 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
7044 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
7045 InstructionMark im(this);
7046 emit_int8((unsigned char)0x81);
7047 emit_operand(rdi, src1);
7048 emit_data(imm32, rspec, 0);
7049 }
7050
7051 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax,
7052 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded
7053 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise.
7054 void Assembler::cmpxchg8(Address adr) {
7055 InstructionMark im(this);
7056 emit_int8(0x0F);
7057 emit_int8((unsigned char)0xC7);
7058 emit_operand(rcx, adr);
7059 }
7060
7061 void Assembler::decl(Register dst) {
7062 // Don't use it directly. Use MacroAssembler::decrementl() instead.
7063 emit_int8(0x48 | dst->encoding());
7064 }
7065
7066 #endif // _LP64
7067
7068 // 64bit typically doesn't use the x87 but needs to for the trig funcs
7069
7070 void Assembler::fabs() {
7071 emit_int8((unsigned char)0xD9);
7072 emit_int8((unsigned char)0xE1);
7073 }
7074
7075 void Assembler::fadd(int i) {
7076 emit_farith(0xD8, 0xC0, i);
7077 }
7078
7079 void Assembler::fadd_d(Address src) {
7080 InstructionMark im(this);
7081 emit_int8((unsigned char)0xDC);
7082 emit_operand32(rax, src);
7083 }
7084
7085 void Assembler::fadd_s(Address src) {
7086 InstructionMark im(this);
7087 emit_int8((unsigned char)0xD8);
7088 emit_operand32(rax, src);
7089 }
7090
7091 void Assembler::fadda(int i) {
7092 emit_farith(0xDC, 0xC0, i);
7093 }
7094
7095 void Assembler::faddp(int i) {
7096 emit_farith(0xDE, 0xC0, i);
7097 }
7098
7099 void Assembler::fchs() {
7100 emit_int8((unsigned char)0xD9);
7101 emit_int8((unsigned char)0xE0);
7102 }
7103
7104 void Assembler::fcom(int i) {
7105 emit_farith(0xD8, 0xD0, i);
7106 }
7107
7108 void Assembler::fcomp(int i) {
7109 emit_farith(0xD8, 0xD8, i);
7110 }
7111
7112 void Assembler::fcomp_d(Address src) {
7113 InstructionMark im(this);
7114 emit_int8((unsigned char)0xDC);
7115 emit_operand32(rbx, src);
7116 }
7117
7118 void Assembler::fcomp_s(Address src) {
7119 InstructionMark im(this);
7120 emit_int8((unsigned char)0xD8);
7121 emit_operand32(rbx, src);
7122 }
7123
7124 void Assembler::fcompp() {
7125 emit_int8((unsigned char)0xDE);
7126 emit_int8((unsigned char)0xD9);
7127 }
7128
7129 void Assembler::fcos() {
7130 emit_int8((unsigned char)0xD9);
7131 emit_int8((unsigned char)0xFF);
7132 }
7133
7134 void Assembler::fdecstp() {
7135 emit_int8((unsigned char)0xD9);
7136 emit_int8((unsigned char)0xF6);
7137 }
7138
7139 void Assembler::fdiv(int i) {
7140 emit_farith(0xD8, 0xF0, i);
7141 }
7142
7143 void Assembler::fdiv_d(Address src) {
7144 InstructionMark im(this);
7145 emit_int8((unsigned char)0xDC);
7146 emit_operand32(rsi, src);
7147 }
7148
7149 void Assembler::fdiv_s(Address src) {
7150 InstructionMark im(this);
7151 emit_int8((unsigned char)0xD8);
7152 emit_operand32(rsi, src);
7153 }
7154
7155 void Assembler::fdiva(int i) {
7156 emit_farith(0xDC, 0xF8, i);
7157 }
7158
7159 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994)
7160 // is erroneous for some of the floating-point instructions below.
7161
7162 void Assembler::fdivp(int i) {
7163 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong)
7164 }
7165
7166 void Assembler::fdivr(int i) {
7167 emit_farith(0xD8, 0xF8, i);
7168 }
7169
7170 void Assembler::fdivr_d(Address src) {
7171 InstructionMark im(this);
7172 emit_int8((unsigned char)0xDC);
7173 emit_operand32(rdi, src);
7174 }
7175
7176 void Assembler::fdivr_s(Address src) {
7177 InstructionMark im(this);
7178 emit_int8((unsigned char)0xD8);
7179 emit_operand32(rdi, src);
7180 }
7181
7182 void Assembler::fdivra(int i) {
7183 emit_farith(0xDC, 0xF0, i);
7184 }
7185
7186 void Assembler::fdivrp(int i) {
7187 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong)
7188 }
7189
7190 void Assembler::ffree(int i) {
7191 emit_farith(0xDD, 0xC0, i);
7192 }
7193
7194 void Assembler::fild_d(Address adr) {
7195 InstructionMark im(this);
7196 emit_int8((unsigned char)0xDF);
7197 emit_operand32(rbp, adr);
7198 }
7199
7200 void Assembler::fild_s(Address adr) {
7201 InstructionMark im(this);
7202 emit_int8((unsigned char)0xDB);
7203 emit_operand32(rax, adr);
7204 }
7205
7206 void Assembler::fincstp() {
7207 emit_int8((unsigned char)0xD9);
7208 emit_int8((unsigned char)0xF7);
7209 }
7210
7211 void Assembler::finit() {
7212 emit_int8((unsigned char)0x9B);
7213 emit_int8((unsigned char)0xDB);
7214 emit_int8((unsigned char)0xE3);
7215 }
7216
7217 void Assembler::fist_s(Address adr) {
7218 InstructionMark im(this);
7219 emit_int8((unsigned char)0xDB);
7220 emit_operand32(rdx, adr);
7221 }
7222
7223 void Assembler::fistp_d(Address adr) {
7224 InstructionMark im(this);
7225 emit_int8((unsigned char)0xDF);
7226 emit_operand32(rdi, adr);
7227 }
7228
7229 void Assembler::fistp_s(Address adr) {
7230 InstructionMark im(this);
7231 emit_int8((unsigned char)0xDB);
7232 emit_operand32(rbx, adr);
7233 }
7234
7235 void Assembler::fld1() {
7236 emit_int8((unsigned char)0xD9);
7237 emit_int8((unsigned char)0xE8);
7238 }
7239
7240 void Assembler::fld_d(Address adr) {
7241 InstructionMark im(this);
7242 emit_int8((unsigned char)0xDD);
7243 emit_operand32(rax, adr);
7244 }
7245
7246 void Assembler::fld_s(Address adr) {
7247 InstructionMark im(this);
7248 emit_int8((unsigned char)0xD9);
7249 emit_operand32(rax, adr);
7250 }
7251
7252
7253 void Assembler::fld_s(int index) {
7254 emit_farith(0xD9, 0xC0, index);
7255 }
7256
7257 void Assembler::fld_x(Address adr) {
7258 InstructionMark im(this);
7259 emit_int8((unsigned char)0xDB);
7260 emit_operand32(rbp, adr);
7261 }
7262
7263 void Assembler::fldcw(Address src) {
7264 InstructionMark im(this);
7265 emit_int8((unsigned char)0xD9);
7266 emit_operand32(rbp, src);
7267 }
7268
7269 void Assembler::fldenv(Address src) {
7270 InstructionMark im(this);
7271 emit_int8((unsigned char)0xD9);
7272 emit_operand32(rsp, src);
7273 }
7274
7275 void Assembler::fldlg2() {
7276 emit_int8((unsigned char)0xD9);
7277 emit_int8((unsigned char)0xEC);
7278 }
7279
7280 void Assembler::fldln2() {
7281 emit_int8((unsigned char)0xD9);
7282 emit_int8((unsigned char)0xED);
7283 }
7284
7285 void Assembler::fldz() {
7286 emit_int8((unsigned char)0xD9);
7287 emit_int8((unsigned char)0xEE);
7288 }
7289
7290 void Assembler::flog() {
7291 fldln2();
7292 fxch();
7293 fyl2x();
7294 }
7295
7296 void Assembler::flog10() {
7297 fldlg2();
7298 fxch();
7299 fyl2x();
7300 }
7301
7302 void Assembler::fmul(int i) {
7303 emit_farith(0xD8, 0xC8, i);
7304 }
7305
7306 void Assembler::fmul_d(Address src) {
7307 InstructionMark im(this);
7308 emit_int8((unsigned char)0xDC);
7309 emit_operand32(rcx, src);
7310 }
7311
7312 void Assembler::fmul_s(Address src) {
7313 InstructionMark im(this);
7314 emit_int8((unsigned char)0xD8);
7315 emit_operand32(rcx, src);
7316 }
7317
7318 void Assembler::fmula(int i) {
7319 emit_farith(0xDC, 0xC8, i);
7320 }
7321
7322 void Assembler::fmulp(int i) {
7323 emit_farith(0xDE, 0xC8, i);
7324 }
7325
7326 void Assembler::fnsave(Address dst) {
7327 InstructionMark im(this);
7328 emit_int8((unsigned char)0xDD);
7329 emit_operand32(rsi, dst);
7330 }
7331
7332 void Assembler::fnstcw(Address src) {
7333 InstructionMark im(this);
7334 emit_int8((unsigned char)0x9B);
7335 emit_int8((unsigned char)0xD9);
7336 emit_operand32(rdi, src);
7337 }
7338
7339 void Assembler::fnstsw_ax() {
7340 emit_int8((unsigned char)0xDF);
7341 emit_int8((unsigned char)0xE0);
7342 }
7343
7344 void Assembler::fprem() {
7345 emit_int8((unsigned char)0xD9);
7346 emit_int8((unsigned char)0xF8);
7347 }
7348
7349 void Assembler::fprem1() {
7350 emit_int8((unsigned char)0xD9);
7351 emit_int8((unsigned char)0xF5);
7352 }
7353
7354 void Assembler::frstor(Address src) {
7355 InstructionMark im(this);
7356 emit_int8((unsigned char)0xDD);
7357 emit_operand32(rsp, src);
7358 }
7359
7360 void Assembler::fsin() {
7361 emit_int8((unsigned char)0xD9);
7362 emit_int8((unsigned char)0xFE);
7363 }
7364
7365 void Assembler::fsqrt() {
7366 emit_int8((unsigned char)0xD9);
7367 emit_int8((unsigned char)0xFA);
7368 }
7369
7370 void Assembler::fst_d(Address adr) {
7371 InstructionMark im(this);
7372 emit_int8((unsigned char)0xDD);
7373 emit_operand32(rdx, adr);
7374 }
7375
7376 void Assembler::fst_s(Address adr) {
7377 InstructionMark im(this);
7378 emit_int8((unsigned char)0xD9);
7379 emit_operand32(rdx, adr);
7380 }
7381
7382 void Assembler::fstp_d(Address adr) {
7383 InstructionMark im(this);
7384 emit_int8((unsigned char)0xDD);
7385 emit_operand32(rbx, adr);
7386 }
7387
7388 void Assembler::fstp_d(int index) {
7389 emit_farith(0xDD, 0xD8, index);
7390 }
7391
7392 void Assembler::fstp_s(Address adr) {
7393 InstructionMark im(this);
7394 emit_int8((unsigned char)0xD9);
7395 emit_operand32(rbx, adr);
7396 }
7397
7398 void Assembler::fstp_x(Address adr) {
7399 InstructionMark im(this);
7400 emit_int8((unsigned char)0xDB);
7401 emit_operand32(rdi, adr);
7402 }
7403
7404 void Assembler::fsub(int i) {
7405 emit_farith(0xD8, 0xE0, i);
7406 }
7407
7408 void Assembler::fsub_d(Address src) {
7409 InstructionMark im(this);
7410 emit_int8((unsigned char)0xDC);
7411 emit_operand32(rsp, src);
7412 }
7413
7414 void Assembler::fsub_s(Address src) {
7415 InstructionMark im(this);
7416 emit_int8((unsigned char)0xD8);
7417 emit_operand32(rsp, src);
7418 }
7419
7420 void Assembler::fsuba(int i) {
7421 emit_farith(0xDC, 0xE8, i);
7422 }
7423
7424 void Assembler::fsubp(int i) {
7425 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong)
7426 }
7427
7428 void Assembler::fsubr(int i) {
7429 emit_farith(0xD8, 0xE8, i);
7430 }
7431
7432 void Assembler::fsubr_d(Address src) {
7433 InstructionMark im(this);
7434 emit_int8((unsigned char)0xDC);
7435 emit_operand32(rbp, src);
7436 }
7437
7438 void Assembler::fsubr_s(Address src) {
7439 InstructionMark im(this);
7440 emit_int8((unsigned char)0xD8);
7441 emit_operand32(rbp, src);
7442 }
7443
7444 void Assembler::fsubra(int i) {
7445 emit_farith(0xDC, 0xE0, i);
7446 }
7447
7448 void Assembler::fsubrp(int i) {
7449 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong)
7450 }
7451
7452 void Assembler::ftan() {
7453 emit_int8((unsigned char)0xD9);
7454 emit_int8((unsigned char)0xF2);
7455 emit_int8((unsigned char)0xDD);
7456 emit_int8((unsigned char)0xD8);
7457 }
7458
7459 void Assembler::ftst() {
7460 emit_int8((unsigned char)0xD9);
7461 emit_int8((unsigned char)0xE4);
7462 }
7463
7464 void Assembler::fucomi(int i) {
7465 // make sure the instruction is supported (introduced for P6, together with cmov)
7466 guarantee(VM_Version::supports_cmov(), "illegal instruction");
7467 emit_farith(0xDB, 0xE8, i);
7468 }
7469
7470 void Assembler::fucomip(int i) {
7471 // make sure the instruction is supported (introduced for P6, together with cmov)
7472 guarantee(VM_Version::supports_cmov(), "illegal instruction");
7473 emit_farith(0xDF, 0xE8, i);
7474 }
7475
7476 void Assembler::fwait() {
7477 emit_int8((unsigned char)0x9B);
7478 }
7479
7480 void Assembler::fxch(int i) {
7481 emit_farith(0xD9, 0xC8, i);
7482 }
7483
7484 void Assembler::fyl2x() {
7485 emit_int8((unsigned char)0xD9);
7486 emit_int8((unsigned char)0xF1);
7487 }
7488
7489 void Assembler::frndint() {
7490 emit_int8((unsigned char)0xD9);
7491 emit_int8((unsigned char)0xFC);
7492 }
7493
7494 void Assembler::f2xm1() {
7495 emit_int8((unsigned char)0xD9);
7496 emit_int8((unsigned char)0xF0);
7497 }
7498
7499 void Assembler::fldl2e() {
7500 emit_int8((unsigned char)0xD9);
7501 emit_int8((unsigned char)0xEA);
7502 }
7503
7504 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding.
7505 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 };
7506 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding.
7507 static int simd_opc[4] = { 0, 0, 0x38, 0x3A };
7508
7509 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding.
7510 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
7511 if (pre > 0) {
7512 emit_int8(simd_pre[pre]);
7513 }
7514 if (rex_w) {
7515 prefixq(adr, xreg);
7516 } else {
7517 prefix(adr, xreg);
7518 }
7519 if (opc > 0) {
7520 emit_int8(0x0F);
7521 int opc2 = simd_opc[opc];
7522 if (opc2 > 0) {
7523 emit_int8(opc2);
7524 }
7525 }
7526 }
7527
7528 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
7529 if (pre > 0) {
7530 emit_int8(simd_pre[pre]);
7531 }
7532 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) : prefix_and_encode(dst_enc, src_enc);
7533 if (opc > 0) {
7534 emit_int8(0x0F);
7535 int opc2 = simd_opc[opc];
7536 if (opc2 > 0) {
7537 emit_int8(opc2);
7538 }
7539 }
7540 return encode;
7541 }
7542
7543
7544 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc) {
7545 int vector_len = _attributes->get_vector_len();
7546 bool vex_w = _attributes->is_rex_vex_w();
7547 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) {
7548 prefix(VEX_3bytes);
7549
7550 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0);
7551 byte1 = (~byte1) & 0xE0;
7552 byte1 |= opc;
7553 emit_int8(byte1);
7554
7555 int byte2 = ((~nds_enc) & 0xf) << 3;
7556 byte2 |= (vex_w ? VEX_W : 0) | ((vector_len > 0) ? 4 : 0) | pre;
7557 emit_int8(byte2);
7558 } else {
7559 prefix(VEX_2bytes);
7560
7561 int byte1 = vex_r ? VEX_R : 0;
7562 byte1 = (~byte1) & 0x80;
7563 byte1 |= ((~nds_enc) & 0xf) << 3;
7564 byte1 |= ((vector_len > 0 ) ? 4 : 0) | pre;
7565 emit_int8(byte1);
7566 }
7567 }
7568
7569 // This is a 4 byte encoding
7570 void Assembler::evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_r, bool evex_v, int nds_enc, VexSimdPrefix pre, VexOpcode opc){
7571 // EVEX 0x62 prefix
7572 prefix(EVEX_4bytes);
7573 bool vex_w = _attributes->is_rex_vex_w();
7574 int evex_encoding = (vex_w ? VEX_W : 0);
7575 // EVEX.b is not currently used for broadcast of single element or data rounding modes
7576 _attributes->set_evex_encoding(evex_encoding);
7577
7578 // P0: byte 2, initialized to RXBR`00mm
7579 // instead of not'd
7580 int byte2 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0) | (evex_r ? EVEX_Rb : 0);
7581 byte2 = (~byte2) & 0xF0;
7582 // confine opc opcode extensions in mm bits to lower two bits
7583 // of form {0F, 0F_38, 0F_3A}
7584 byte2 |= opc;
7585 emit_int8(byte2);
7586
7587 // P1: byte 3 as Wvvvv1pp
7588 int byte3 = ((~nds_enc) & 0xf) << 3;
7589 // p[10] is always 1
7590 byte3 |= EVEX_F;
7591 byte3 |= (vex_w & 1) << 7;
7592 // confine pre opcode extensions in pp bits to lower two bits
7593 // of form {66, F3, F2}
7594 byte3 |= pre;
7595 emit_int8(byte3);
7596
7597 // P2: byte 4 as zL'Lbv'aaa
7598 // kregs are implemented in the low 3 bits as aaa
7599 int byte4 = (_attributes->is_no_reg_mask()) ?
7600 0 :
7601 _attributes->get_embedded_opmask_register_specifier();
7602 // EVEX.v` for extending EVEX.vvvv or VIDX
7603 byte4 |= (evex_v ? 0: EVEX_V);
7604 // third EXEC.b for broadcast actions
7605 byte4 |= (_attributes->is_extended_context() ? EVEX_Rb : 0);
7606 // fourth EVEX.L'L for vector length : 0 is 128, 1 is 256, 2 is 512, currently we do not support 1024
7607 byte4 |= ((_attributes->get_vector_len())& 0x3) << 5;
7608 // last is EVEX.z for zero/merge actions
7609 if (_attributes->is_no_reg_mask() == false) {
7610 byte4 |= (_attributes->is_clear_context() ? EVEX_Z : 0);
7611 }
7612 emit_int8(byte4);
7613 }
7614
7615 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) {
7616 bool vex_r = ((xreg_enc & 8) == 8) ? 1 : 0;
7617 bool vex_b = adr.base_needs_rex();
7618 bool vex_x;
7619 if (adr.isxmmindex()) {
7620 vex_x = adr.xmmindex_needs_rex();
7621 } else {
7622 vex_x = adr.index_needs_rex();
7623 }
7624 set_attributes(attributes);
7625 attributes->set_current_assembler(this);
7626
7627 // For EVEX instruction (which is not marked as pure EVEX instruction) check and see if this instruction
7628 // is allowed in legacy mode and has resources which will fit in it.
7629 // Pure EVEX instructions will have is_evex_instruction set in their definition.
7630 if (!attributes->is_legacy_mode()) {
7631 if (UseAVX > 2 && !attributes->is_evex_instruction() && !_is_managed) {
7632 if ((attributes->get_vector_len() != AVX_512bit) && (nds_enc < 16) && (xreg_enc < 16)) {
7633 attributes->set_is_legacy_mode();
7634 }
7635 }
7636 }
7637
7638 if (UseAVX > 2) {
7639 assert(((!attributes->uses_vl()) ||
7640 (attributes->get_vector_len() == AVX_512bit) ||
7641 (!_legacy_mode_vl) ||
7642 (attributes->is_legacy_mode())),"XMM register should be 0-15");
7643 assert(((nds_enc < 16 && xreg_enc < 16) || (!attributes->is_legacy_mode())),"XMM register should be 0-15");
7644 }
7645
7646 _is_managed = false;
7647 if (UseAVX > 2 && !attributes->is_legacy_mode())
7648 {
7649 bool evex_r = (xreg_enc >= 16);
7650 bool evex_v;
7651 // EVEX.V' is set to true when VSIB is used as we may need to use higher order XMM registers (16-31)
7652 if (adr.isxmmindex()) {
7653 evex_v = ((adr._xmmindex->encoding() > 15) ? true : false);
7654 } else {
7655 evex_v = (nds_enc >= 16);
7656 }
7657 attributes->set_is_evex_instruction();
7658 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc);
7659 } else {
7660 if (UseAVX > 2 && attributes->is_rex_vex_w_reverted()) {
7661 attributes->set_rex_vex_w(false);
7662 }
7663 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc);
7664 }
7665 }
7666
7667 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) {
7668 bool vex_r = ((dst_enc & 8) == 8) ? 1 : 0;
7669 bool vex_b = ((src_enc & 8) == 8) ? 1 : 0;
7670 bool vex_x = false;
7671 set_attributes(attributes);
7672 attributes->set_current_assembler(this);
7673
7674 // For EVEX instruction (which is not marked as pure EVEX instruction) check and see if this instruction
7675 // is allowed in legacy mode and has resources which will fit in it.
7676 // Pure EVEX instructions will have is_evex_instruction set in their definition.
7677 if (!attributes->is_legacy_mode()) {
7678 if (UseAVX > 2 && !attributes->is_evex_instruction() && !_is_managed) {
7679 if ((!attributes->uses_vl() || (attributes->get_vector_len() != AVX_512bit)) &&
7680 (dst_enc < 16) && (nds_enc < 16) && (src_enc < 16)) {
7681 attributes->set_is_legacy_mode();
7682 }
7683 }
7684 }
7685
7686 if (UseAVX > 2) {
7687 // All the scalar fp instructions (with uses_vl as false) can have legacy_mode as false
7688 // Instruction with uses_vl true are vector instructions
7689 // All the vector instructions with AVX_512bit length can have legacy_mode as false
7690 // All the vector instructions with < AVX_512bit length can have legacy_mode as false if AVX512vl() is supported
7691 // Rest all should have legacy_mode set as true
7692 assert(((!attributes->uses_vl()) ||
7693 (attributes->get_vector_len() == AVX_512bit) ||
7694 (!_legacy_mode_vl) ||
7695 (attributes->is_legacy_mode())),"XMM register should be 0-15");
7696 // Instruction with legacy_mode true should have dst, nds and src < 15
7697 assert(((dst_enc < 16 && nds_enc < 16 && src_enc < 16) || (!attributes->is_legacy_mode())),"XMM register should be 0-15");
7698 }
7699
7700 _is_managed = false;
7701 if (UseAVX > 2 && !attributes->is_legacy_mode())
7702 {
7703 bool evex_r = (dst_enc >= 16);
7704 bool evex_v = (nds_enc >= 16);
7705 // can use vex_x as bank extender on rm encoding
7706 vex_x = (src_enc >= 16);
7707 attributes->set_is_evex_instruction();
7708 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc);
7709 } else {
7710 if (UseAVX > 2 && attributes->is_rex_vex_w_reverted()) {
7711 attributes->set_rex_vex_w(false);
7712 }
7713 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc);
7714 }
7715
7716 // return modrm byte components for operands
7717 return (((dst_enc & 7) << 3) | (src_enc & 7));
7718 }
7719
7720
7721 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre,
7722 VexOpcode opc, InstructionAttr *attributes) {
7723 if (UseAVX > 0) {
7724 int xreg_enc = xreg->encoding();
7725 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
7726 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, attributes);
7727 } else {
7728 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding");
7729 rex_prefix(adr, xreg, pre, opc, attributes->is_rex_vex_w());
7730 }
7731 }
7732
7733 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre,
7734 VexOpcode opc, InstructionAttr *attributes) {
7735 int dst_enc = dst->encoding();
7736 int src_enc = src->encoding();
7737 if (UseAVX > 0) {
7738 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
7739 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, attributes);
7740 } else {
7741 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding");
7742 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, attributes->is_rex_vex_w());
7743 }
7744 }
7745
7746 void Assembler::cmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) {
7747 assert(VM_Version::supports_avx(), "");
7748 assert(!VM_Version::supports_evex(), "");
7749 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
7750 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7751 emit_int8((unsigned char)0xC2);
7752 emit_int8((unsigned char)(0xC0 | encode));
7753 emit_int8((unsigned char)(0xF & cop));
7754 }
7755
7756 void Assembler::blendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) {
7757 assert(VM_Version::supports_avx(), "");
7758 assert(!VM_Version::supports_evex(), "");
7759 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
7760 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7761 emit_int8((unsigned char)0x4B);
7762 emit_int8((unsigned char)(0xC0 | encode));
7763 int src2_enc = src2->encoding();
7764 emit_int8((unsigned char)(0xF0 & src2_enc<<4));
7765 }
7766
7767 void Assembler::cmpps(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) {
7768 assert(VM_Version::supports_avx(), "");
7769 assert(!VM_Version::supports_evex(), "");
7770 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
7771 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7772 emit_int8((unsigned char)0xC2);
7773 emit_int8((unsigned char)(0xC0 | encode));
7774 emit_int8((unsigned char)(0xF & cop));
7775 }
7776
7777 void Assembler::blendvps(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) {
7778 assert(VM_Version::supports_avx(), "");
7779 assert(!VM_Version::supports_evex(), "");
7780 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
7781 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7782 emit_int8((unsigned char)0x4A);
7783 emit_int8((unsigned char)(0xC0 | encode));
7784 int src2_enc = src2->encoding();
7785 emit_int8((unsigned char)(0xF0 & src2_enc<<4));
7786 }
7787
7788 void Assembler::vpblendd(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
7789 assert(VM_Version::supports_avx2(), "");
7790 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
7791 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7792 emit_int8((unsigned char)0x02);
7793 emit_int8((unsigned char)(0xC0 | encode));
7794 emit_int8((unsigned char)imm8);
7795 }
7796
7797 void Assembler::shlxl(Register dst, Register src1, Register src2) {
7798 assert(VM_Version::supports_bmi2(), "");
7799 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
7800 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7801 emit_int8((unsigned char)0xF7);
7802 emit_int8((unsigned char)(0xC0 | encode));
7803 }
7804
7805 void Assembler::shlxq(Register dst, Register src1, Register src2) {
7806 assert(VM_Version::supports_bmi2(), "");
7807 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
7808 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7809 emit_int8((unsigned char)0xF7);
7810 emit_int8((unsigned char)(0xC0 | encode));
7811 }
7812
7813 #ifndef _LP64
7814
7815 void Assembler::incl(Register dst) {
7816 // Don't use it directly. Use MacroAssembler::incrementl() instead.
7817 emit_int8(0x40 | dst->encoding());
7818 }
7819
7820 void Assembler::lea(Register dst, Address src) {
7821 leal(dst, src);
7822 }
7823
7824 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
7825 InstructionMark im(this);
7826 emit_int8((unsigned char)0xC7);
7827 emit_operand(rax, dst);
7828 emit_data((int)imm32, rspec, 0);
7829 }
7830
7831 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
7832 InstructionMark im(this);
7833 int encode = prefix_and_encode(dst->encoding());
7834 emit_int8((unsigned char)(0xB8 | encode));
7835 emit_data((int)imm32, rspec, 0);
7836 }
7837
7838 void Assembler::popa() { // 32bit
7839 emit_int8(0x61);
7840 }
7841
7842 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
7843 InstructionMark im(this);
7844 emit_int8(0x68);
7845 emit_data(imm32, rspec, 0);
7846 }
7847
7848 void Assembler::pusha() { // 32bit
7849 emit_int8(0x60);
7850 }
7851
7852 void Assembler::set_byte_if_not_zero(Register dst) {
7853 emit_int8(0x0F);
7854 emit_int8((unsigned char)0x95);
7855 emit_int8((unsigned char)(0xE0 | dst->encoding()));
7856 }
7857
7858 void Assembler::shldl(Register dst, Register src) {
7859 emit_int8(0x0F);
7860 emit_int8((unsigned char)0xA5);
7861 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
7862 }
7863
7864 // 0F A4 / r ib
7865 void Assembler::shldl(Register dst, Register src, int8_t imm8) {
7866 emit_int8(0x0F);
7867 emit_int8((unsigned char)0xA4);
7868 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
7869 emit_int8(imm8);
7870 }
7871
7872 void Assembler::shrdl(Register dst, Register src) {
7873 emit_int8(0x0F);
7874 emit_int8((unsigned char)0xAD);
7875 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
7876 }
7877
7878 #else // LP64
7879
7880 void Assembler::set_byte_if_not_zero(Register dst) {
7881 int enc = prefix_and_encode(dst->encoding(), true);
7882 emit_int8(0x0F);
7883 emit_int8((unsigned char)0x95);
7884 emit_int8((unsigned char)(0xE0 | enc));
7885 }
7886
7887 // 64bit only pieces of the assembler
7888 // This should only be used by 64bit instructions that can use rip-relative
7889 // it cannot be used by instructions that want an immediate value.
7890
7891 bool Assembler::reachable(AddressLiteral adr) {
7892 int64_t disp;
7893 // None will force a 64bit literal to the code stream. Likely a placeholder
7894 // for something that will be patched later and we need to certain it will
7895 // always be reachable.
7896 if (adr.reloc() == relocInfo::none) {
7897 return false;
7898 }
7899 if (adr.reloc() == relocInfo::internal_word_type) {
7900 // This should be rip relative and easily reachable.
7901 return true;
7902 }
7903 if (adr.reloc() == relocInfo::virtual_call_type ||
7904 adr.reloc() == relocInfo::opt_virtual_call_type ||
7905 adr.reloc() == relocInfo::static_call_type ||
7906 adr.reloc() == relocInfo::static_stub_type ) {
7907 // This should be rip relative within the code cache and easily
7908 // reachable until we get huge code caches. (At which point
7909 // ic code is going to have issues).
7910 return true;
7911 }
7912 if (adr.reloc() != relocInfo::external_word_type &&
7913 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special
7914 adr.reloc() != relocInfo::poll_type && // relocs to identify them
7915 adr.reloc() != relocInfo::runtime_call_type ) {
7916 return false;
7917 }
7918
7919 // Stress the correction code
7920 if (ForceUnreachable) {
7921 // Must be runtimecall reloc, see if it is in the codecache
7922 // Flipping stuff in the codecache to be unreachable causes issues
7923 // with things like inline caches where the additional instructions
7924 // are not handled.
7925 if (CodeCache::find_blob(adr._target) == NULL) {
7926 return false;
7927 }
7928 }
7929 // For external_word_type/runtime_call_type if it is reachable from where we
7930 // are now (possibly a temp buffer) and where we might end up
7931 // anywhere in the codeCache then we are always reachable.
7932 // This would have to change if we ever save/restore shared code
7933 // to be more pessimistic.
7934 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int));
7935 if (!is_simm32(disp)) return false;
7936 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int));
7937 if (!is_simm32(disp)) return false;
7938
7939 disp = (int64_t)adr._target - ((int64_t)pc() + sizeof(int));
7940
7941 // Because rip relative is a disp + address_of_next_instruction and we
7942 // don't know the value of address_of_next_instruction we apply a fudge factor
7943 // to make sure we will be ok no matter the size of the instruction we get placed into.
7944 // We don't have to fudge the checks above here because they are already worst case.
7945
7946 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal
7947 // + 4 because better safe than sorry.
7948 const int fudge = 12 + 4;
7949 if (disp < 0) {
7950 disp -= fudge;
7951 } else {
7952 disp += fudge;
7953 }
7954 return is_simm32(disp);
7955 }
7956
7957 // Check if the polling page is not reachable from the code cache using rip-relative
7958 // addressing.
7959 bool Assembler::is_polling_page_far() {
7960 intptr_t addr = (intptr_t)os::get_polling_page();
7961 return ForceUnreachable ||
7962 !is_simm32(addr - (intptr_t)CodeCache::low_bound()) ||
7963 !is_simm32(addr - (intptr_t)CodeCache::high_bound());
7964 }
7965
7966 void Assembler::emit_data64(jlong data,
7967 relocInfo::relocType rtype,
7968 int format) {
7969 if (rtype == relocInfo::none) {
7970 emit_int64(data);
7971 } else {
7972 emit_data64(data, Relocation::spec_simple(rtype), format);
7973 }
7974 }
7975
7976 void Assembler::emit_data64(jlong data,
7977 RelocationHolder const& rspec,
7978 int format) {
7979 assert(imm_operand == 0, "default format must be immediate in this file");
7980 assert(imm_operand == format, "must be immediate");
7981 assert(inst_mark() != NULL, "must be inside InstructionMark");
7982 // Do not use AbstractAssembler::relocate, which is not intended for
7983 // embedded words. Instead, relocate to the enclosing instruction.
7984 code_section()->relocate(inst_mark(), rspec, format);
7985 #ifdef ASSERT
7986 check_relocation(rspec, format);
7987 #endif
7988 emit_int64(data);
7989 }
7990
7991 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) {
7992 if (reg_enc >= 8) {
7993 prefix(REX_B);
7994 reg_enc -= 8;
7995 } else if (byteinst && reg_enc >= 4) {
7996 prefix(REX);
7997 }
7998 return reg_enc;
7999 }
8000
8001 int Assembler::prefixq_and_encode(int reg_enc) {
8002 if (reg_enc < 8) {
8003 prefix(REX_W);
8004 } else {
8005 prefix(REX_WB);
8006 reg_enc -= 8;
8007 }
8008 return reg_enc;
8009 }
8010
8011 int Assembler::prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte) {
8012 if (dst_enc < 8) {
8013 if (src_enc >= 8) {
8014 prefix(REX_B);
8015 src_enc -= 8;
8016 } else if ((src_is_byte && src_enc >= 4) || (dst_is_byte && dst_enc >= 4)) {
8017 prefix(REX);
8018 }
8019 } else {
8020 if (src_enc < 8) {
8021 prefix(REX_R);
8022 } else {
8023 prefix(REX_RB);
8024 src_enc -= 8;
8025 }
8026 dst_enc -= 8;
8027 }
8028 return dst_enc << 3 | src_enc;
8029 }
8030
8031 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) {
8032 if (dst_enc < 8) {
8033 if (src_enc < 8) {
8034 prefix(REX_W);
8035 } else {
8036 prefix(REX_WB);
8037 src_enc -= 8;
8038 }
8039 } else {
8040 if (src_enc < 8) {
8041 prefix(REX_WR);
8042 } else {
8043 prefix(REX_WRB);
8044 src_enc -= 8;
8045 }
8046 dst_enc -= 8;
8047 }
8048 return dst_enc << 3 | src_enc;
8049 }
8050
8051 void Assembler::prefix(Register reg) {
8052 if (reg->encoding() >= 8) {
8053 prefix(REX_B);
8054 }
8055 }
8056
8057 void Assembler::prefix(Register dst, Register src, Prefix p) {
8058 if (src->encoding() >= 8) {
8059 p = (Prefix)(p | REX_B);
8060 }
8061 if (dst->encoding() >= 8) {
8062 p = (Prefix)( p | REX_R);
8063 }
8064 if (p != Prefix_EMPTY) {
8065 // do not generate an empty prefix
8066 prefix(p);
8067 }
8068 }
8069
8070 void Assembler::prefix(Register dst, Address adr, Prefix p) {
8071 if (adr.base_needs_rex()) {
8072 if (adr.index_needs_rex()) {
8073 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X");
8074 } else {
8075 prefix(REX_B);
8076 }
8077 } else {
8078 if (adr.index_needs_rex()) {
8079 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X");
8080 }
8081 }
8082 if (dst->encoding() >= 8) {
8083 p = (Prefix)(p | REX_R);
8084 }
8085 if (p != Prefix_EMPTY) {
8086 // do not generate an empty prefix
8087 prefix(p);
8088 }
8089 }
8090
8091 void Assembler::prefix(Address adr) {
8092 if (adr.base_needs_rex()) {
8093 if (adr.index_needs_rex()) {
8094 prefix(REX_XB);
8095 } else {
8096 prefix(REX_B);
8097 }
8098 } else {
8099 if (adr.index_needs_rex()) {
8100 prefix(REX_X);
8101 }
8102 }
8103 }
8104
8105 void Assembler::prefixq(Address adr) {
8106 if (adr.base_needs_rex()) {
8107 if (adr.index_needs_rex()) {
8108 prefix(REX_WXB);
8109 } else {
8110 prefix(REX_WB);
8111 }
8112 } else {
8113 if (adr.index_needs_rex()) {
8114 prefix(REX_WX);
8115 } else {
8116 prefix(REX_W);
8117 }
8118 }
8119 }
8120
8121
8122 void Assembler::prefix(Address adr, Register reg, bool byteinst) {
8123 if (reg->encoding() < 8) {
8124 if (adr.base_needs_rex()) {
8125 if (adr.index_needs_rex()) {
8126 prefix(REX_XB);
8127 } else {
8128 prefix(REX_B);
8129 }
8130 } else {
8131 if (adr.index_needs_rex()) {
8132 prefix(REX_X);
8133 } else if (byteinst && reg->encoding() >= 4 ) {
8134 prefix(REX);
8135 }
8136 }
8137 } else {
8138 if (adr.base_needs_rex()) {
8139 if (adr.index_needs_rex()) {
8140 prefix(REX_RXB);
8141 } else {
8142 prefix(REX_RB);
8143 }
8144 } else {
8145 if (adr.index_needs_rex()) {
8146 prefix(REX_RX);
8147 } else {
8148 prefix(REX_R);
8149 }
8150 }
8151 }
8152 }
8153
8154 void Assembler::prefixq(Address adr, Register src) {
8155 if (src->encoding() < 8) {
8156 if (adr.base_needs_rex()) {
8157 if (adr.index_needs_rex()) {
8158 prefix(REX_WXB);
8159 } else {
8160 prefix(REX_WB);
8161 }
8162 } else {
8163 if (adr.index_needs_rex()) {
8164 prefix(REX_WX);
8165 } else {
8166 prefix(REX_W);
8167 }
8168 }
8169 } else {
8170 if (adr.base_needs_rex()) {
8171 if (adr.index_needs_rex()) {
8172 prefix(REX_WRXB);
8173 } else {
8174 prefix(REX_WRB);
8175 }
8176 } else {
8177 if (adr.index_needs_rex()) {
8178 prefix(REX_WRX);
8179 } else {
8180 prefix(REX_WR);
8181 }
8182 }
8183 }
8184 }
8185
8186 void Assembler::prefix(Address adr, XMMRegister reg) {
8187 if (reg->encoding() < 8) {
8188 if (adr.base_needs_rex()) {
8189 if (adr.index_needs_rex()) {
8190 prefix(REX_XB);
8191 } else {
8192 prefix(REX_B);
8193 }
8194 } else {
8195 if (adr.index_needs_rex()) {
8196 prefix(REX_X);
8197 }
8198 }
8199 } else {
8200 if (adr.base_needs_rex()) {
8201 if (adr.index_needs_rex()) {
8202 prefix(REX_RXB);
8203 } else {
8204 prefix(REX_RB);
8205 }
8206 } else {
8207 if (adr.index_needs_rex()) {
8208 prefix(REX_RX);
8209 } else {
8210 prefix(REX_R);
8211 }
8212 }
8213 }
8214 }
8215
8216 void Assembler::prefixq(Address adr, XMMRegister src) {
8217 if (src->encoding() < 8) {
8218 if (adr.base_needs_rex()) {
8219 if (adr.index_needs_rex()) {
8220 prefix(REX_WXB);
8221 } else {
8222 prefix(REX_WB);
8223 }
8224 } else {
8225 if (adr.index_needs_rex()) {
8226 prefix(REX_WX);
8227 } else {
8228 prefix(REX_W);
8229 }
8230 }
8231 } else {
8232 if (adr.base_needs_rex()) {
8233 if (adr.index_needs_rex()) {
8234 prefix(REX_WRXB);
8235 } else {
8236 prefix(REX_WRB);
8237 }
8238 } else {
8239 if (adr.index_needs_rex()) {
8240 prefix(REX_WRX);
8241 } else {
8242 prefix(REX_WR);
8243 }
8244 }
8245 }
8246 }
8247
8248 void Assembler::adcq(Register dst, int32_t imm32) {
8249 (void) prefixq_and_encode(dst->encoding());
8250 emit_arith(0x81, 0xD0, dst, imm32);
8251 }
8252
8253 void Assembler::adcq(Register dst, Address src) {
8254 InstructionMark im(this);
8255 prefixq(src, dst);
8256 emit_int8(0x13);
8257 emit_operand(dst, src);
8258 }
8259
8260 void Assembler::adcq(Register dst, Register src) {
8261 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8262 emit_arith(0x13, 0xC0, dst, src);
8263 }
8264
8265 void Assembler::addq(Address dst, int32_t imm32) {
8266 InstructionMark im(this);
8267 prefixq(dst);
8268 emit_arith_operand(0x81, rax, dst,imm32);
8269 }
8270
8271 void Assembler::addq(Address dst, Register src) {
8272 InstructionMark im(this);
8273 prefixq(dst, src);
8274 emit_int8(0x01);
8275 emit_operand(src, dst);
8276 }
8277
8278 void Assembler::addq(Register dst, int32_t imm32) {
8279 (void) prefixq_and_encode(dst->encoding());
8280 emit_arith(0x81, 0xC0, dst, imm32);
8281 }
8282
8283 void Assembler::addq(Register dst, Address src) {
8284 InstructionMark im(this);
8285 prefixq(src, dst);
8286 emit_int8(0x03);
8287 emit_operand(dst, src);
8288 }
8289
8290 void Assembler::addq(Register dst, Register src) {
8291 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8292 emit_arith(0x03, 0xC0, dst, src);
8293 }
8294
8295 void Assembler::adcxq(Register dst, Register src) {
8296 //assert(VM_Version::supports_adx(), "adx instructions not supported");
8297 emit_int8((unsigned char)0x66);
8298 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8299 emit_int8(0x0F);
8300 emit_int8(0x38);
8301 emit_int8((unsigned char)0xF6);
8302 emit_int8((unsigned char)(0xC0 | encode));
8303 }
8304
8305 void Assembler::adoxq(Register dst, Register src) {
8306 //assert(VM_Version::supports_adx(), "adx instructions not supported");
8307 emit_int8((unsigned char)0xF3);
8308 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8309 emit_int8(0x0F);
8310 emit_int8(0x38);
8311 emit_int8((unsigned char)0xF6);
8312 emit_int8((unsigned char)(0xC0 | encode));
8313 }
8314
8315 void Assembler::andq(Address dst, int32_t imm32) {
8316 InstructionMark im(this);
8317 prefixq(dst);
8318 emit_int8((unsigned char)0x81);
8319 emit_operand(rsp, dst, 4);
8320 emit_int32(imm32);
8321 }
8322
8323 void Assembler::andq(Register dst, int32_t imm32) {
8324 (void) prefixq_and_encode(dst->encoding());
8325 emit_arith(0x81, 0xE0, dst, imm32);
8326 }
8327
8328 void Assembler::andq(Register dst, Address src) {
8329 InstructionMark im(this);
8330 prefixq(src, dst);
8331 emit_int8(0x23);
8332 emit_operand(dst, src);
8333 }
8334
8335 void Assembler::andq(Register dst, Register src) {
8336 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8337 emit_arith(0x23, 0xC0, dst, src);
8338 }
8339
8340 void Assembler::andnq(Register dst, Register src1, Register src2) {
8341 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8342 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8343 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8344 emit_int8((unsigned char)0xF2);
8345 emit_int8((unsigned char)(0xC0 | encode));
8346 }
8347
8348 void Assembler::andnq(Register dst, Register src1, Address src2) {
8349 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8350 InstructionMark im(this);
8351 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8352 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8353 emit_int8((unsigned char)0xF2);
8354 emit_operand(dst, src2);
8355 }
8356
8357 void Assembler::bsfq(Register dst, Register src) {
8358 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8359 emit_int8(0x0F);
8360 emit_int8((unsigned char)0xBC);
8361 emit_int8((unsigned char)(0xC0 | encode));
8362 }
8363
8364 void Assembler::bsrq(Register dst, Register src) {
8365 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8366 emit_int8(0x0F);
8367 emit_int8((unsigned char)0xBD);
8368 emit_int8((unsigned char)(0xC0 | encode));
8369 }
8370
8371 void Assembler::bswapq(Register reg) {
8372 int encode = prefixq_and_encode(reg->encoding());
8373 emit_int8(0x0F);
8374 emit_int8((unsigned char)(0xC8 | encode));
8375 }
8376
8377 void Assembler::blsiq(Register dst, Register src) {
8378 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8379 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8380 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8381 emit_int8((unsigned char)0xF3);
8382 emit_int8((unsigned char)(0xC0 | encode));
8383 }
8384
8385 void Assembler::blsiq(Register dst, Address src) {
8386 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8387 InstructionMark im(this);
8388 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8389 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8390 emit_int8((unsigned char)0xF3);
8391 emit_operand(rbx, src);
8392 }
8393
8394 void Assembler::blsmskq(Register dst, Register src) {
8395 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8396 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8397 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8398 emit_int8((unsigned char)0xF3);
8399 emit_int8((unsigned char)(0xC0 | encode));
8400 }
8401
8402 void Assembler::blsmskq(Register dst, Address src) {
8403 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8404 InstructionMark im(this);
8405 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8406 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8407 emit_int8((unsigned char)0xF3);
8408 emit_operand(rdx, src);
8409 }
8410
8411 void Assembler::blsrq(Register dst, Register src) {
8412 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8413 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8414 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8415 emit_int8((unsigned char)0xF3);
8416 emit_int8((unsigned char)(0xC0 | encode));
8417 }
8418
8419 void Assembler::blsrq(Register dst, Address src) {
8420 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8421 InstructionMark im(this);
8422 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8423 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8424 emit_int8((unsigned char)0xF3);
8425 emit_operand(rcx, src);
8426 }
8427
8428 void Assembler::cdqq() {
8429 prefix(REX_W);
8430 emit_int8((unsigned char)0x99);
8431 }
8432
8433 void Assembler::clflush(Address adr) {
8434 prefix(adr);
8435 emit_int8(0x0F);
8436 emit_int8((unsigned char)0xAE);
8437 emit_operand(rdi, adr);
8438 }
8439
8440 void Assembler::cmovq(Condition cc, Register dst, Register src) {
8441 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8442 emit_int8(0x0F);
8443 emit_int8(0x40 | cc);
8444 emit_int8((unsigned char)(0xC0 | encode));
8445 }
8446
8447 void Assembler::cmovq(Condition cc, Register dst, Address src) {
8448 InstructionMark im(this);
8449 prefixq(src, dst);
8450 emit_int8(0x0F);
8451 emit_int8(0x40 | cc);
8452 emit_operand(dst, src);
8453 }
8454
8455 void Assembler::cmpq(Address dst, int32_t imm32) {
8456 InstructionMark im(this);
8457 prefixq(dst);
8458 emit_int8((unsigned char)0x81);
8459 emit_operand(rdi, dst, 4);
8460 emit_int32(imm32);
8461 }
8462
8463 void Assembler::cmpq(Register dst, int32_t imm32) {
8464 (void) prefixq_and_encode(dst->encoding());
8465 emit_arith(0x81, 0xF8, dst, imm32);
8466 }
8467
8468 void Assembler::cmpq(Address dst, Register src) {
8469 InstructionMark im(this);
8470 prefixq(dst, src);
8471 emit_int8(0x3B);
8472 emit_operand(src, dst);
8473 }
8474
8475 void Assembler::cmpq(Register dst, Register src) {
8476 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8477 emit_arith(0x3B, 0xC0, dst, src);
8478 }
8479
8480 void Assembler::cmpq(Register dst, Address src) {
8481 InstructionMark im(this);
8482 prefixq(src, dst);
8483 emit_int8(0x3B);
8484 emit_operand(dst, src);
8485 }
8486
8487 void Assembler::cmpxchgq(Register reg, Address adr) {
8488 InstructionMark im(this);
8489 prefixq(adr, reg);
8490 emit_int8(0x0F);
8491 emit_int8((unsigned char)0xB1);
8492 emit_operand(reg, adr);
8493 }
8494
8495 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
8496 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8497 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8498 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
8499 emit_int8(0x2A);
8500 emit_int8((unsigned char)(0xC0 | encode));
8501 }
8502
8503 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) {
8504 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8505 InstructionMark im(this);
8506 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8507 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
8508 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
8509 emit_int8(0x2A);
8510 emit_operand(dst, src);
8511 }
8512
8513 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) {
8514 NOT_LP64(assert(VM_Version::supports_sse(), ""));
8515 InstructionMark im(this);
8516 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8517 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
8518 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
8519 emit_int8(0x2A);
8520 emit_operand(dst, src);
8521 }
8522
8523 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
8524 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8525 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8526 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
8527 emit_int8(0x2C);
8528 emit_int8((unsigned char)(0xC0 | encode));
8529 }
8530
8531 void Assembler::cvttss2siq(Register dst, XMMRegister src) {
8532 NOT_LP64(assert(VM_Version::supports_sse(), ""));
8533 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8534 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
8535 emit_int8(0x2C);
8536 emit_int8((unsigned char)(0xC0 | encode));
8537 }
8538
8539 void Assembler::decl(Register dst) {
8540 // Don't use it directly. Use MacroAssembler::decrementl() instead.
8541 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
8542 int encode = prefix_and_encode(dst->encoding());
8543 emit_int8((unsigned char)0xFF);
8544 emit_int8((unsigned char)(0xC8 | encode));
8545 }
8546
8547 void Assembler::decq(Register dst) {
8548 // Don't use it directly. Use MacroAssembler::decrementq() instead.
8549 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
8550 int encode = prefixq_and_encode(dst->encoding());
8551 emit_int8((unsigned char)0xFF);
8552 emit_int8(0xC8 | encode);
8553 }
8554
8555 void Assembler::decq(Address dst) {
8556 // Don't use it directly. Use MacroAssembler::decrementq() instead.
8557 InstructionMark im(this);
8558 prefixq(dst);
8559 emit_int8((unsigned char)0xFF);
8560 emit_operand(rcx, dst);
8561 }
8562
8563 void Assembler::fxrstor(Address src) {
8564 prefixq(src);
8565 emit_int8(0x0F);
8566 emit_int8((unsigned char)0xAE);
8567 emit_operand(as_Register(1), src);
8568 }
8569
8570 void Assembler::xrstor(Address src) {
8571 prefixq(src);
8572 emit_int8(0x0F);
8573 emit_int8((unsigned char)0xAE);
8574 emit_operand(as_Register(5), src);
8575 }
8576
8577 void Assembler::fxsave(Address dst) {
8578 prefixq(dst);
8579 emit_int8(0x0F);
8580 emit_int8((unsigned char)0xAE);
8581 emit_operand(as_Register(0), dst);
8582 }
8583
8584 void Assembler::xsave(Address dst) {
8585 prefixq(dst);
8586 emit_int8(0x0F);
8587 emit_int8((unsigned char)0xAE);
8588 emit_operand(as_Register(4), dst);
8589 }
8590
8591 void Assembler::idivq(Register src) {
8592 int encode = prefixq_and_encode(src->encoding());
8593 emit_int8((unsigned char)0xF7);
8594 emit_int8((unsigned char)(0xF8 | encode));
8595 }
8596
8597 void Assembler::imulq(Register dst, Register src) {
8598 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8599 emit_int8(0x0F);
8600 emit_int8((unsigned char)0xAF);
8601 emit_int8((unsigned char)(0xC0 | encode));
8602 }
8603
8604 void Assembler::imulq(Register dst, Register src, int value) {
8605 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8606 if (is8bit(value)) {
8607 emit_int8(0x6B);
8608 emit_int8((unsigned char)(0xC0 | encode));
8609 emit_int8(value & 0xFF);
8610 } else {
8611 emit_int8(0x69);
8612 emit_int8((unsigned char)(0xC0 | encode));
8613 emit_int32(value);
8614 }
8615 }
8616
8617 void Assembler::imulq(Register dst, Address src) {
8618 InstructionMark im(this);
8619 prefixq(src, dst);
8620 emit_int8(0x0F);
8621 emit_int8((unsigned char) 0xAF);
8622 emit_operand(dst, src);
8623 }
8624
8625 void Assembler::incl(Register dst) {
8626 // Don't use it directly. Use MacroAssembler::incrementl() instead.
8627 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
8628 int encode = prefix_and_encode(dst->encoding());
8629 emit_int8((unsigned char)0xFF);
8630 emit_int8((unsigned char)(0xC0 | encode));
8631 }
8632
8633 void Assembler::incq(Register dst) {
8634 // Don't use it directly. Use MacroAssembler::incrementq() instead.
8635 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
8636 int encode = prefixq_and_encode(dst->encoding());
8637 emit_int8((unsigned char)0xFF);
8638 emit_int8((unsigned char)(0xC0 | encode));
8639 }
8640
8641 void Assembler::incq(Address dst) {
8642 // Don't use it directly. Use MacroAssembler::incrementq() instead.
8643 InstructionMark im(this);
8644 prefixq(dst);
8645 emit_int8((unsigned char)0xFF);
8646 emit_operand(rax, dst);
8647 }
8648
8649 void Assembler::lea(Register dst, Address src) {
8650 leaq(dst, src);
8651 }
8652
8653 void Assembler::leaq(Register dst, Address src) {
8654 InstructionMark im(this);
8655 prefixq(src, dst);
8656 emit_int8((unsigned char)0x8D);
8657 emit_operand(dst, src);
8658 }
8659
8660 void Assembler::mov64(Register dst, int64_t imm64) {
8661 InstructionMark im(this);
8662 int encode = prefixq_and_encode(dst->encoding());
8663 emit_int8((unsigned char)(0xB8 | encode));
8664 emit_int64(imm64);
8665 }
8666
8667 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) {
8668 InstructionMark im(this);
8669 int encode = prefixq_and_encode(dst->encoding());
8670 emit_int8(0xB8 | encode);
8671 emit_data64(imm64, rspec);
8672 }
8673
8674 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) {
8675 InstructionMark im(this);
8676 int encode = prefix_and_encode(dst->encoding());
8677 emit_int8((unsigned char)(0xB8 | encode));
8678 emit_data((int)imm32, rspec, narrow_oop_operand);
8679 }
8680
8681 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) {
8682 InstructionMark im(this);
8683 prefix(dst);
8684 emit_int8((unsigned char)0xC7);
8685 emit_operand(rax, dst, 4);
8686 emit_data((int)imm32, rspec, narrow_oop_operand);
8687 }
8688
8689 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) {
8690 InstructionMark im(this);
8691 int encode = prefix_and_encode(src1->encoding());
8692 emit_int8((unsigned char)0x81);
8693 emit_int8((unsigned char)(0xF8 | encode));
8694 emit_data((int)imm32, rspec, narrow_oop_operand);
8695 }
8696
8697 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) {
8698 InstructionMark im(this);
8699 prefix(src1);
8700 emit_int8((unsigned char)0x81);
8701 emit_operand(rax, src1, 4);
8702 emit_data((int)imm32, rspec, narrow_oop_operand);
8703 }
8704
8705 void Assembler::lzcntq(Register dst, Register src) {
8706 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
8707 emit_int8((unsigned char)0xF3);
8708 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8709 emit_int8(0x0F);
8710 emit_int8((unsigned char)0xBD);
8711 emit_int8((unsigned char)(0xC0 | encode));
8712 }
8713
8714 void Assembler::movdq(XMMRegister dst, Register src) {
8715 // table D-1 says MMX/SSE2
8716 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8717 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8718 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8719 emit_int8(0x6E);
8720 emit_int8((unsigned char)(0xC0 | encode));
8721 }
8722
8723 void Assembler::movdq(Register dst, XMMRegister src) {
8724 // table D-1 says MMX/SSE2
8725 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8726 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8727 // swap src/dst to get correct prefix
8728 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8729 emit_int8(0x7E);
8730 emit_int8((unsigned char)(0xC0 | encode));
8731 }
8732
8733 void Assembler::movq(Register dst, Register src) {
8734 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8735 emit_int8((unsigned char)0x8B);
8736 emit_int8((unsigned char)(0xC0 | encode));
8737 }
8738
8739 void Assembler::movq(Register dst, Address src) {
8740 InstructionMark im(this);
8741 prefixq(src, dst);
8742 emit_int8((unsigned char)0x8B);
8743 emit_operand(dst, src);
8744 }
8745
8746 void Assembler::movq(Address dst, Register src) {
8747 InstructionMark im(this);
8748 prefixq(dst, src);
8749 emit_int8((unsigned char)0x89);
8750 emit_operand(src, dst);
8751 }
8752
8753 void Assembler::movsbq(Register dst, Address src) {
8754 InstructionMark im(this);
8755 prefixq(src, dst);
8756 emit_int8(0x0F);
8757 emit_int8((unsigned char)0xBE);
8758 emit_operand(dst, src);
8759 }
8760
8761 void Assembler::movsbq(Register dst, Register src) {
8762 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8763 emit_int8(0x0F);
8764 emit_int8((unsigned char)0xBE);
8765 emit_int8((unsigned char)(0xC0 | encode));
8766 }
8767
8768 void Assembler::movslq(Register dst, int32_t imm32) {
8769 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx)
8770 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx)
8771 // as a result we shouldn't use until tested at runtime...
8772 ShouldNotReachHere();
8773 InstructionMark im(this);
8774 int encode = prefixq_and_encode(dst->encoding());
8775 emit_int8((unsigned char)(0xC7 | encode));
8776 emit_int32(imm32);
8777 }
8778
8779 void Assembler::movslq(Address dst, int32_t imm32) {
8780 assert(is_simm32(imm32), "lost bits");
8781 InstructionMark im(this);
8782 prefixq(dst);
8783 emit_int8((unsigned char)0xC7);
8784 emit_operand(rax, dst, 4);
8785 emit_int32(imm32);
8786 }
8787
8788 void Assembler::movslq(Register dst, Address src) {
8789 InstructionMark im(this);
8790 prefixq(src, dst);
8791 emit_int8(0x63);
8792 emit_operand(dst, src);
8793 }
8794
8795 void Assembler::movslq(Register dst, Register src) {
8796 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8797 emit_int8(0x63);
8798 emit_int8((unsigned char)(0xC0 | encode));
8799 }
8800
8801 void Assembler::movswq(Register dst, Address src) {
8802 InstructionMark im(this);
8803 prefixq(src, dst);
8804 emit_int8(0x0F);
8805 emit_int8((unsigned char)0xBF);
8806 emit_operand(dst, src);
8807 }
8808
8809 void Assembler::movswq(Register dst, Register src) {
8810 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8811 emit_int8((unsigned char)0x0F);
8812 emit_int8((unsigned char)0xBF);
8813 emit_int8((unsigned char)(0xC0 | encode));
8814 }
8815
8816 void Assembler::movzbq(Register dst, Address src) {
8817 InstructionMark im(this);
8818 prefixq(src, dst);
8819 emit_int8((unsigned char)0x0F);
8820 emit_int8((unsigned char)0xB6);
8821 emit_operand(dst, src);
8822 }
8823
8824 void Assembler::movzbq(Register dst, Register src) {
8825 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8826 emit_int8(0x0F);
8827 emit_int8((unsigned char)0xB6);
8828 emit_int8(0xC0 | encode);
8829 }
8830
8831 void Assembler::movzwq(Register dst, Address src) {
8832 InstructionMark im(this);
8833 prefixq(src, dst);
8834 emit_int8((unsigned char)0x0F);
8835 emit_int8((unsigned char)0xB7);
8836 emit_operand(dst, src);
8837 }
8838
8839 void Assembler::movzwq(Register dst, Register src) {
8840 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8841 emit_int8((unsigned char)0x0F);
8842 emit_int8((unsigned char)0xB7);
8843 emit_int8((unsigned char)(0xC0 | encode));
8844 }
8845
8846 void Assembler::mulq(Address src) {
8847 InstructionMark im(this);
8848 prefixq(src);
8849 emit_int8((unsigned char)0xF7);
8850 emit_operand(rsp, src);
8851 }
8852
8853 void Assembler::mulq(Register src) {
8854 int encode = prefixq_and_encode(src->encoding());
8855 emit_int8((unsigned char)0xF7);
8856 emit_int8((unsigned char)(0xE0 | encode));
8857 }
8858
8859 void Assembler::mulxq(Register dst1, Register dst2, Register src) {
8860 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
8861 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8862 int encode = vex_prefix_and_encode(dst1->encoding(), dst2->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
8863 emit_int8((unsigned char)0xF6);
8864 emit_int8((unsigned char)(0xC0 | encode));
8865 }
8866
8867 void Assembler::negq(Register dst) {
8868 int encode = prefixq_and_encode(dst->encoding());
8869 emit_int8((unsigned char)0xF7);
8870 emit_int8((unsigned char)(0xD8 | encode));
8871 }
8872
8873 void Assembler::notq(Register dst) {
8874 int encode = prefixq_and_encode(dst->encoding());
8875 emit_int8((unsigned char)0xF7);
8876 emit_int8((unsigned char)(0xD0 | encode));
8877 }
8878
8879 void Assembler::orq(Address dst, int32_t imm32) {
8880 InstructionMark im(this);
8881 prefixq(dst);
8882 emit_int8((unsigned char)0x81);
8883 emit_operand(rcx, dst, 4);
8884 emit_int32(imm32);
8885 }
8886
8887 void Assembler::orq(Register dst, int32_t imm32) {
8888 (void) prefixq_and_encode(dst->encoding());
8889 emit_arith(0x81, 0xC8, dst, imm32);
8890 }
8891
8892 void Assembler::orq(Register dst, Address src) {
8893 InstructionMark im(this);
8894 prefixq(src, dst);
8895 emit_int8(0x0B);
8896 emit_operand(dst, src);
8897 }
8898
8899 void Assembler::orq(Register dst, Register src) {
8900 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8901 emit_arith(0x0B, 0xC0, dst, src);
8902 }
8903
8904 void Assembler::popa() { // 64bit
8905 movq(r15, Address(rsp, 0));
8906 movq(r14, Address(rsp, wordSize));
8907 movq(r13, Address(rsp, 2 * wordSize));
8908 movq(r12, Address(rsp, 3 * wordSize));
8909 movq(r11, Address(rsp, 4 * wordSize));
8910 movq(r10, Address(rsp, 5 * wordSize));
8911 movq(r9, Address(rsp, 6 * wordSize));
8912 movq(r8, Address(rsp, 7 * wordSize));
8913 movq(rdi, Address(rsp, 8 * wordSize));
8914 movq(rsi, Address(rsp, 9 * wordSize));
8915 movq(rbp, Address(rsp, 10 * wordSize));
8916 // skip rsp
8917 movq(rbx, Address(rsp, 12 * wordSize));
8918 movq(rdx, Address(rsp, 13 * wordSize));
8919 movq(rcx, Address(rsp, 14 * wordSize));
8920 movq(rax, Address(rsp, 15 * wordSize));
8921
8922 addq(rsp, 16 * wordSize);
8923 }
8924
8925 void Assembler::popcntq(Register dst, Address src) {
8926 assert(VM_Version::supports_popcnt(), "must support");
8927 InstructionMark im(this);
8928 emit_int8((unsigned char)0xF3);
8929 prefixq(src, dst);
8930 emit_int8((unsigned char)0x0F);
8931 emit_int8((unsigned char)0xB8);
8932 emit_operand(dst, src);
8933 }
8934
8935 void Assembler::popcntq(Register dst, Register src) {
8936 assert(VM_Version::supports_popcnt(), "must support");
8937 emit_int8((unsigned char)0xF3);
8938 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8939 emit_int8((unsigned char)0x0F);
8940 emit_int8((unsigned char)0xB8);
8941 emit_int8((unsigned char)(0xC0 | encode));
8942 }
8943
8944 void Assembler::popq(Address dst) {
8945 InstructionMark im(this);
8946 prefixq(dst);
8947 emit_int8((unsigned char)0x8F);
8948 emit_operand(rax, dst);
8949 }
8950
8951 void Assembler::pusha() { // 64bit
8952 // we have to store original rsp. ABI says that 128 bytes
8953 // below rsp are local scratch.
8954 movq(Address(rsp, -5 * wordSize), rsp);
8955
8956 subq(rsp, 16 * wordSize);
8957
8958 movq(Address(rsp, 15 * wordSize), rax);
8959 movq(Address(rsp, 14 * wordSize), rcx);
8960 movq(Address(rsp, 13 * wordSize), rdx);
8961 movq(Address(rsp, 12 * wordSize), rbx);
8962 // skip rsp
8963 movq(Address(rsp, 10 * wordSize), rbp);
8964 movq(Address(rsp, 9 * wordSize), rsi);
8965 movq(Address(rsp, 8 * wordSize), rdi);
8966 movq(Address(rsp, 7 * wordSize), r8);
8967 movq(Address(rsp, 6 * wordSize), r9);
8968 movq(Address(rsp, 5 * wordSize), r10);
8969 movq(Address(rsp, 4 * wordSize), r11);
8970 movq(Address(rsp, 3 * wordSize), r12);
8971 movq(Address(rsp, 2 * wordSize), r13);
8972 movq(Address(rsp, wordSize), r14);
8973 movq(Address(rsp, 0), r15);
8974 }
8975
8976 void Assembler::pushq(Address src) {
8977 InstructionMark im(this);
8978 prefixq(src);
8979 emit_int8((unsigned char)0xFF);
8980 emit_operand(rsi, src);
8981 }
8982
8983 void Assembler::rclq(Register dst, int imm8) {
8984 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8985 int encode = prefixq_and_encode(dst->encoding());
8986 if (imm8 == 1) {
8987 emit_int8((unsigned char)0xD1);
8988 emit_int8((unsigned char)(0xD0 | encode));
8989 } else {
8990 emit_int8((unsigned char)0xC1);
8991 emit_int8((unsigned char)(0xD0 | encode));
8992 emit_int8(imm8);
8993 }
8994 }
8995
8996 void Assembler::rcrq(Register dst, int imm8) {
8997 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8998 int encode = prefixq_and_encode(dst->encoding());
8999 if (imm8 == 1) {
9000 emit_int8((unsigned char)0xD1);
9001 emit_int8((unsigned char)(0xD8 | encode));
9002 } else {
9003 emit_int8((unsigned char)0xC1);
9004 emit_int8((unsigned char)(0xD8 | encode));
9005 emit_int8(imm8);
9006 }
9007 }
9008
9009 void Assembler::rorq(Register dst, int imm8) {
9010 assert(isShiftCount(imm8 >> 1), "illegal shift count");
9011 int encode = prefixq_and_encode(dst->encoding());
9012 if (imm8 == 1) {
9013 emit_int8((unsigned char)0xD1);
9014 emit_int8((unsigned char)(0xC8 | encode));
9015 } else {
9016 emit_int8((unsigned char)0xC1);
9017 emit_int8((unsigned char)(0xc8 | encode));
9018 emit_int8(imm8);
9019 }
9020 }
9021
9022 void Assembler::rorxq(Register dst, Register src, int imm8) {
9023 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
9024 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
9025 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes);
9026 emit_int8((unsigned char)0xF0);
9027 emit_int8((unsigned char)(0xC0 | encode));
9028 emit_int8(imm8);
9029 }
9030
9031 void Assembler::rorxd(Register dst, Register src, int imm8) {
9032 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
9033 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
9034 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes);
9035 emit_int8((unsigned char)0xF0);
9036 emit_int8((unsigned char)(0xC0 | encode));
9037 emit_int8(imm8);
9038 }
9039
9040 void Assembler::sarq(Register dst, int imm8) {
9041 assert(isShiftCount(imm8 >> 1), "illegal shift count");
9042 int encode = prefixq_and_encode(dst->encoding());
9043 if (imm8 == 1) {
9044 emit_int8((unsigned char)0xD1);
9045 emit_int8((unsigned char)(0xF8 | encode));
9046 } else {
9047 emit_int8((unsigned char)0xC1);
9048 emit_int8((unsigned char)(0xF8 | encode));
9049 emit_int8(imm8);
9050 }
9051 }
9052
9053 void Assembler::sarq(Register dst) {
9054 int encode = prefixq_and_encode(dst->encoding());
9055 emit_int8((unsigned char)0xD3);
9056 emit_int8((unsigned char)(0xF8 | encode));
9057 }
9058
9059 void Assembler::sbbq(Address dst, int32_t imm32) {
9060 InstructionMark im(this);
9061 prefixq(dst);
9062 emit_arith_operand(0x81, rbx, dst, imm32);
9063 }
9064
9065 void Assembler::sbbq(Register dst, int32_t imm32) {
9066 (void) prefixq_and_encode(dst->encoding());
9067 emit_arith(0x81, 0xD8, dst, imm32);
9068 }
9069
9070 void Assembler::sbbq(Register dst, Address src) {
9071 InstructionMark im(this);
9072 prefixq(src, dst);
9073 emit_int8(0x1B);
9074 emit_operand(dst, src);
9075 }
9076
9077 void Assembler::sbbq(Register dst, Register src) {
9078 (void) prefixq_and_encode(dst->encoding(), src->encoding());
9079 emit_arith(0x1B, 0xC0, dst, src);
9080 }
9081
9082 void Assembler::shlq(Register dst, int imm8) {
9083 assert(isShiftCount(imm8 >> 1), "illegal shift count");
9084 int encode = prefixq_and_encode(dst->encoding());
9085 if (imm8 == 1) {
9086 emit_int8((unsigned char)0xD1);
9087 emit_int8((unsigned char)(0xE0 | encode));
9088 } else {
9089 emit_int8((unsigned char)0xC1);
9090 emit_int8((unsigned char)(0xE0 | encode));
9091 emit_int8(imm8);
9092 }
9093 }
9094
9095 void Assembler::shlq(Register dst) {
9096 int encode = prefixq_and_encode(dst->encoding());
9097 emit_int8((unsigned char)0xD3);
9098 emit_int8((unsigned char)(0xE0 | encode));
9099 }
9100
9101 void Assembler::shrq(Register dst, int imm8) {
9102 assert(isShiftCount(imm8 >> 1), "illegal shift count");
9103 int encode = prefixq_and_encode(dst->encoding());
9104 emit_int8((unsigned char)0xC1);
9105 emit_int8((unsigned char)(0xE8 | encode));
9106 emit_int8(imm8);
9107 }
9108
9109 void Assembler::shrq(Register dst) {
9110 int encode = prefixq_and_encode(dst->encoding());
9111 emit_int8((unsigned char)0xD3);
9112 emit_int8(0xE8 | encode);
9113 }
9114
9115 void Assembler::subq(Address dst, int32_t imm32) {
9116 InstructionMark im(this);
9117 prefixq(dst);
9118 emit_arith_operand(0x81, rbp, dst, imm32);
9119 }
9120
9121 void Assembler::subq(Address dst, Register src) {
9122 InstructionMark im(this);
9123 prefixq(dst, src);
9124 emit_int8(0x29);
9125 emit_operand(src, dst);
9126 }
9127
9128 void Assembler::subq(Register dst, int32_t imm32) {
9129 (void) prefixq_and_encode(dst->encoding());
9130 emit_arith(0x81, 0xE8, dst, imm32);
9131 }
9132
9133 // Force generation of a 4 byte immediate value even if it fits into 8bit
9134 void Assembler::subq_imm32(Register dst, int32_t imm32) {
9135 (void) prefixq_and_encode(dst->encoding());
9136 emit_arith_imm32(0x81, 0xE8, dst, imm32);
9137 }
9138
9139 void Assembler::subq(Register dst, Address src) {
9140 InstructionMark im(this);
9141 prefixq(src, dst);
9142 emit_int8(0x2B);
9143 emit_operand(dst, src);
9144 }
9145
9146 void Assembler::subq(Register dst, Register src) {
9147 (void) prefixq_and_encode(dst->encoding(), src->encoding());
9148 emit_arith(0x2B, 0xC0, dst, src);
9149 }
9150
9151 void Assembler::testq(Register dst, int32_t imm32) {
9152 // not using emit_arith because test
9153 // doesn't support sign-extension of
9154 // 8bit operands
9155 int encode = dst->encoding();
9156 if (encode == 0) {
9157 prefix(REX_W);
9158 emit_int8((unsigned char)0xA9);
9159 } else {
9160 encode = prefixq_and_encode(encode);
9161 emit_int8((unsigned char)0xF7);
9162 emit_int8((unsigned char)(0xC0 | encode));
9163 }
9164 emit_int32(imm32);
9165 }
9166
9167 void Assembler::testq(Register dst, Register src) {
9168 (void) prefixq_and_encode(dst->encoding(), src->encoding());
9169 emit_arith(0x85, 0xC0, dst, src);
9170 }
9171
9172 void Assembler::testq(Register dst, Address src) {
9173 InstructionMark im(this);
9174 prefixq(src, dst);
9175 emit_int8((unsigned char)0x85);
9176 emit_operand(dst, src);
9177 }
9178
9179 void Assembler::xaddq(Address dst, Register src) {
9180 InstructionMark im(this);
9181 prefixq(dst, src);
9182 emit_int8(0x0F);
9183 emit_int8((unsigned char)0xC1);
9184 emit_operand(src, dst);
9185 }
9186
9187 void Assembler::xchgq(Register dst, Address src) {
9188 InstructionMark im(this);
9189 prefixq(src, dst);
9190 emit_int8((unsigned char)0x87);
9191 emit_operand(dst, src);
9192 }
9193
9194 void Assembler::xchgq(Register dst, Register src) {
9195 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
9196 emit_int8((unsigned char)0x87);
9197 emit_int8((unsigned char)(0xc0 | encode));
9198 }
9199
9200 void Assembler::xorq(Register dst, Register src) {
9201 (void) prefixq_and_encode(dst->encoding(), src->encoding());
9202 emit_arith(0x33, 0xC0, dst, src);
9203 }
9204
9205 void Assembler::xorq(Register dst, Address src) {
9206 InstructionMark im(this);
9207 prefixq(src, dst);
9208 emit_int8(0x33);
9209 emit_operand(dst, src);
9210 }
9211
9212 #endif // !LP64