1274 UseXmmRegToRegMoveAll = false;
1275 }
1276 }
1277 if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus
1278 #ifdef COMPILER2
1279 if( FLAG_IS_DEFAULT(MaxLoopPad) ) {
1280 // For new Intel cpus do the next optimization:
1281 // don't align the beginning of a loop if there are enough instructions
1282 // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
1283 // in current fetch line (OptoLoopAlignment) or the padding
1284 // is big (> MaxLoopPad).
1285 // Set MaxLoopPad to 11 for new Intel cpus to reduce number of
1286 // generated NOP instructions. 11 is the largest size of one
1287 // address NOP instruction '0F 1F' (see Assembler::nop(i)).
1288 MaxLoopPad = 11;
1289 }
1290 #endif // COMPILER2
1291 if (FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1292 UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus
1293 }
1294 if (supports_sse4_2() && supports_ht()) { // Newest Intel cpus
1295 if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1296 UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
1297 }
1298 }
1299 if (supports_sse4_2()) {
1300 if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
1301 FLAG_SET_DEFAULT(UseSSE42Intrinsics, true);
1302 }
1303 } else {
1304 if (UseSSE42Intrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
1305 warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled.");
1306 }
1307 FLAG_SET_DEFAULT(UseSSE42Intrinsics, false);
1308 }
1309 }
1310 if (is_atom_family() || is_knights_family()) {
1311 #ifdef COMPILER2
1312 if (FLAG_IS_DEFAULT(OptoScheduling)) {
1313 OptoScheduling = true;
1314 }
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1274 UseXmmRegToRegMoveAll = false;
1275 }
1276 }
1277 if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus
1278 #ifdef COMPILER2
1279 if( FLAG_IS_DEFAULT(MaxLoopPad) ) {
1280 // For new Intel cpus do the next optimization:
1281 // don't align the beginning of a loop if there are enough instructions
1282 // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
1283 // in current fetch line (OptoLoopAlignment) or the padding
1284 // is big (> MaxLoopPad).
1285 // Set MaxLoopPad to 11 for new Intel cpus to reduce number of
1286 // generated NOP instructions. 11 is the largest size of one
1287 // address NOP instruction '0F 1F' (see Assembler::nop(i)).
1288 MaxLoopPad = 11;
1289 }
1290 #endif // COMPILER2
1291 if (FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1292 UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus
1293 }
1294 if ((supports_sse4_2() && supports_ht()) || supports_avx()) { // Newest Intel cpus
1295 if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1296 UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
1297 }
1298 }
1299 if (supports_sse4_2()) {
1300 if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
1301 FLAG_SET_DEFAULT(UseSSE42Intrinsics, true);
1302 }
1303 } else {
1304 if (UseSSE42Intrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
1305 warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled.");
1306 }
1307 FLAG_SET_DEFAULT(UseSSE42Intrinsics, false);
1308 }
1309 }
1310 if (is_atom_family() || is_knights_family()) {
1311 #ifdef COMPILER2
1312 if (FLAG_IS_DEFAULT(OptoScheduling)) {
1313 OptoScheduling = true;
1314 }
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