1 /*
2 * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "gc/shared/cardTableBarrierSet.hpp"
29 #include "gc/shared/collectedHeap.inline.hpp"
30 #include "interpreter/interpreter.hpp"
31 #include "memory/resourceArea.hpp"
32 #include "prims/methodHandles.hpp"
33 #include "runtime/biasedLocking.hpp"
34 #include "runtime/objectMonitor.hpp"
35 #include "runtime/os.hpp"
36 #include "runtime/sharedRuntime.hpp"
37 #include "runtime/stubRoutines.hpp"
38 #include "utilities/macros.hpp"
39
40 #ifdef PRODUCT
41 #define BLOCK_COMMENT(str) /* nothing */
42 #define STOP(error) stop(error)
43 #else
44 #define BLOCK_COMMENT(str) block_comment(str)
45 #define STOP(error) block_comment(error); stop(error)
46 #endif
47
48 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
49 // Implementation of AddressLiteral
50
51 // A 2-D table for managing compressed displacement(disp8) on EVEX enabled platforms.
52 unsigned char tuple_table[Assembler::EVEX_ETUP + 1][Assembler::AVX_512bit + 1] = {
53 // -----------------Table 4.5 -------------------- //
54 16, 32, 64, // EVEX_FV(0)
55 4, 4, 4, // EVEX_FV(1) - with Evex.b
56 16, 32, 64, // EVEX_FV(2) - with Evex.w
57 8, 8, 8, // EVEX_FV(3) - with Evex.w and Evex.b
58 8, 16, 32, // EVEX_HV(0)
59 4, 4, 4, // EVEX_HV(1) - with Evex.b
60 // -----------------Table 4.6 -------------------- //
61 16, 32, 64, // EVEX_FVM(0)
62 1, 1, 1, // EVEX_T1S(0)
63 2, 2, 2, // EVEX_T1S(1)
64 4, 4, 4, // EVEX_T1S(2)
65 8, 8, 8, // EVEX_T1S(3)
66 4, 4, 4, // EVEX_T1F(0)
67 8, 8, 8, // EVEX_T1F(1)
68 8, 8, 8, // EVEX_T2(0)
69 0, 16, 16, // EVEX_T2(1)
70 0, 16, 16, // EVEX_T4(0)
71 0, 0, 32, // EVEX_T4(1)
72 0, 0, 32, // EVEX_T8(0)
73 8, 16, 32, // EVEX_HVM(0)
74 4, 8, 16, // EVEX_QVM(0)
75 2, 4, 8, // EVEX_OVM(0)
76 16, 16, 16, // EVEX_M128(0)
77 8, 32, 64, // EVEX_DUP(0)
78 0, 0, 0 // EVEX_NTUP
79 };
80
81 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
82 _is_lval = false;
83 _target = target;
84 switch (rtype) {
85 case relocInfo::oop_type:
86 case relocInfo::metadata_type:
87 // Oops are a special case. Normally they would be their own section
88 // but in cases like icBuffer they are literals in the code stream that
89 // we don't have a section for. We use none so that we get a literal address
90 // which is always patchable.
91 break;
92 case relocInfo::external_word_type:
93 _rspec = external_word_Relocation::spec(target);
94 break;
95 case relocInfo::internal_word_type:
96 _rspec = internal_word_Relocation::spec(target);
97 break;
98 case relocInfo::opt_virtual_call_type:
99 _rspec = opt_virtual_call_Relocation::spec();
100 break;
101 case relocInfo::static_call_type:
102 _rspec = static_call_Relocation::spec();
103 break;
104 case relocInfo::runtime_call_type:
105 _rspec = runtime_call_Relocation::spec();
106 break;
107 case relocInfo::poll_type:
108 case relocInfo::poll_return_type:
109 _rspec = Relocation::spec_simple(rtype);
110 break;
111 case relocInfo::none:
112 break;
113 default:
114 ShouldNotReachHere();
115 break;
116 }
117 }
118
119 // Implementation of Address
120
121 #ifdef _LP64
122
123 Address Address::make_array(ArrayAddress adr) {
124 // Not implementable on 64bit machines
125 // Should have been handled higher up the call chain.
126 ShouldNotReachHere();
127 return Address();
128 }
129
130 // exceedingly dangerous constructor
131 Address::Address(int disp, address loc, relocInfo::relocType rtype) {
132 _base = noreg;
133 _index = noreg;
134 _scale = no_scale;
135 _disp = disp;
136 _xmmindex = xnoreg;
137 _isxmmindex = false;
138 switch (rtype) {
139 case relocInfo::external_word_type:
140 _rspec = external_word_Relocation::spec(loc);
141 break;
142 case relocInfo::internal_word_type:
143 _rspec = internal_word_Relocation::spec(loc);
144 break;
145 case relocInfo::runtime_call_type:
146 // HMM
147 _rspec = runtime_call_Relocation::spec();
148 break;
149 case relocInfo::poll_type:
150 case relocInfo::poll_return_type:
151 _rspec = Relocation::spec_simple(rtype);
152 break;
153 case relocInfo::none:
154 break;
155 default:
156 ShouldNotReachHere();
157 }
158 }
159 #else // LP64
160
161 Address Address::make_array(ArrayAddress adr) {
162 AddressLiteral base = adr.base();
163 Address index = adr.index();
164 assert(index._disp == 0, "must not have disp"); // maybe it can?
165 Address array(index._base, index._index, index._scale, (intptr_t) base.target());
166 array._rspec = base._rspec;
167 return array;
168 }
169
170 // exceedingly dangerous constructor
171 Address::Address(address loc, RelocationHolder spec) {
172 _base = noreg;
173 _index = noreg;
174 _scale = no_scale;
175 _disp = (intptr_t) loc;
176 _rspec = spec;
177 _xmmindex = xnoreg;
178 _isxmmindex = false;
179 }
180
181 #endif // _LP64
182
183
184
185 // Convert the raw encoding form into the form expected by the constructor for
186 // Address. An index of 4 (rsp) corresponds to having no index, so convert
187 // that to noreg for the Address constructor.
188 Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) {
189 RelocationHolder rspec;
190 if (disp_reloc != relocInfo::none) {
191 rspec = Relocation::spec_simple(disp_reloc);
192 }
193 bool valid_index = index != rsp->encoding();
194 if (valid_index) {
195 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));
196 madr._rspec = rspec;
197 return madr;
198 } else {
199 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));
200 madr._rspec = rspec;
201 return madr;
202 }
203 }
204
205 // Implementation of Assembler
206
207 int AbstractAssembler::code_fill_byte() {
208 return (u_char)'\xF4'; // hlt
209 }
210
211 // make this go away someday
212 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) {
213 if (rtype == relocInfo::none)
214 emit_int32(data);
215 else
216 emit_data(data, Relocation::spec_simple(rtype), format);
217 }
218
219 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) {
220 assert(imm_operand == 0, "default format must be immediate in this file");
221 assert(inst_mark() != NULL, "must be inside InstructionMark");
222 if (rspec.type() != relocInfo::none) {
223 #ifdef ASSERT
224 check_relocation(rspec, format);
225 #endif
226 // Do not use AbstractAssembler::relocate, which is not intended for
227 // embedded words. Instead, relocate to the enclosing instruction.
228
229 // hack. call32 is too wide for mask so use disp32
230 if (format == call32_operand)
231 code_section()->relocate(inst_mark(), rspec, disp32_operand);
232 else
233 code_section()->relocate(inst_mark(), rspec, format);
234 }
235 emit_int32(data);
236 }
237
238 static int encode(Register r) {
239 int enc = r->encoding();
240 if (enc >= 8) {
241 enc -= 8;
242 }
243 return enc;
244 }
245
246 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
247 assert(dst->has_byte_register(), "must have byte register");
248 assert(isByte(op1) && isByte(op2), "wrong opcode");
249 assert(isByte(imm8), "not a byte");
250 assert((op1 & 0x01) == 0, "should be 8bit operation");
251 emit_int8(op1);
252 emit_int8(op2 | encode(dst));
253 emit_int8(imm8);
254 }
255
256
257 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) {
258 assert(isByte(op1) && isByte(op2), "wrong opcode");
259 assert((op1 & 0x01) == 1, "should be 32bit operation");
260 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
261 if (is8bit(imm32)) {
262 emit_int8(op1 | 0x02); // set sign bit
263 emit_int8(op2 | encode(dst));
264 emit_int8(imm32 & 0xFF);
265 } else {
266 emit_int8(op1);
267 emit_int8(op2 | encode(dst));
268 emit_int32(imm32);
269 }
270 }
271
272 // Force generation of a 4 byte immediate value even if it fits into 8bit
273 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) {
274 assert(isByte(op1) && isByte(op2), "wrong opcode");
275 assert((op1 & 0x01) == 1, "should be 32bit operation");
276 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
277 emit_int8(op1);
278 emit_int8(op2 | encode(dst));
279 emit_int32(imm32);
280 }
281
282 // immediate-to-memory forms
283 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) {
284 assert((op1 & 0x01) == 1, "should be 32bit operation");
285 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
286 if (is8bit(imm32)) {
287 emit_int8(op1 | 0x02); // set sign bit
288 emit_operand(rm, adr, 1);
289 emit_int8(imm32 & 0xFF);
290 } else {
291 emit_int8(op1);
292 emit_operand(rm, adr, 4);
293 emit_int32(imm32);
294 }
295 }
296
297
298 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
299 assert(isByte(op1) && isByte(op2), "wrong opcode");
300 emit_int8(op1);
301 emit_int8(op2 | encode(dst) << 3 | encode(src));
302 }
303
304
305 bool Assembler::query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len,
306 int cur_tuple_type, int in_size_in_bits, int cur_encoding) {
307 int mod_idx = 0;
308 // We will test if the displacement fits the compressed format and if so
309 // apply the compression to the displacment iff the result is8bit.
310 if (VM_Version::supports_evex() && is_evex_inst) {
311 switch (cur_tuple_type) {
312 case EVEX_FV:
313 if ((cur_encoding & VEX_W) == VEX_W) {
314 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2;
315 } else {
316 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
317 }
318 break;
319
320 case EVEX_HV:
321 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
322 break;
323
324 case EVEX_FVM:
325 break;
326
327 case EVEX_T1S:
328 switch (in_size_in_bits) {
329 case EVEX_8bit:
330 break;
331
332 case EVEX_16bit:
333 mod_idx = 1;
334 break;
335
336 case EVEX_32bit:
337 mod_idx = 2;
338 break;
339
340 case EVEX_64bit:
341 mod_idx = 3;
342 break;
343 }
344 break;
345
346 case EVEX_T1F:
347 case EVEX_T2:
348 case EVEX_T4:
349 mod_idx = (in_size_in_bits == EVEX_64bit) ? 1 : 0;
350 break;
351
352 case EVEX_T8:
353 break;
354
355 case EVEX_HVM:
356 break;
357
358 case EVEX_QVM:
359 break;
360
361 case EVEX_OVM:
362 break;
363
364 case EVEX_M128:
365 break;
366
367 case EVEX_DUP:
368 break;
369
370 default:
371 assert(0, "no valid evex tuple_table entry");
372 break;
373 }
374
375 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
376 int disp_factor = tuple_table[cur_tuple_type + mod_idx][vector_len];
377 if ((disp % disp_factor) == 0) {
378 int new_disp = disp / disp_factor;
379 if ((-0x80 <= new_disp && new_disp < 0x80)) {
380 disp = new_disp;
381 }
382 } else {
383 return false;
384 }
385 }
386 }
387 return (-0x80 <= disp && disp < 0x80);
388 }
389
390
391 bool Assembler::emit_compressed_disp_byte(int &disp) {
392 int mod_idx = 0;
393 // We will test if the displacement fits the compressed format and if so
394 // apply the compression to the displacment iff the result is8bit.
395 if (VM_Version::supports_evex() && _attributes && _attributes->is_evex_instruction()) {
396 int evex_encoding = _attributes->get_evex_encoding();
397 int tuple_type = _attributes->get_tuple_type();
398 switch (tuple_type) {
399 case EVEX_FV:
400 if ((evex_encoding & VEX_W) == VEX_W) {
401 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2;
402 } else {
403 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
404 }
405 break;
406
407 case EVEX_HV:
408 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
409 break;
410
411 case EVEX_FVM:
412 break;
413
414 case EVEX_T1S:
415 switch (_attributes->get_input_size()) {
416 case EVEX_8bit:
417 break;
418
419 case EVEX_16bit:
420 mod_idx = 1;
421 break;
422
423 case EVEX_32bit:
424 mod_idx = 2;
425 break;
426
427 case EVEX_64bit:
428 mod_idx = 3;
429 break;
430 }
431 break;
432
433 case EVEX_T1F:
434 case EVEX_T2:
435 case EVEX_T4:
436 mod_idx = (_attributes->get_input_size() == EVEX_64bit) ? 1 : 0;
437 break;
438
439 case EVEX_T8:
440 break;
441
442 case EVEX_HVM:
443 break;
444
445 case EVEX_QVM:
446 break;
447
448 case EVEX_OVM:
449 break;
450
451 case EVEX_M128:
452 break;
453
454 case EVEX_DUP:
455 break;
456
457 default:
458 assert(0, "no valid evex tuple_table entry");
459 break;
460 }
461
462 int vector_len = _attributes->get_vector_len();
463 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
464 int disp_factor = tuple_table[tuple_type + mod_idx][vector_len];
465 if ((disp % disp_factor) == 0) {
466 int new_disp = disp / disp_factor;
467 if (is8bit(new_disp)) {
468 disp = new_disp;
469 }
470 } else {
471 return false;
472 }
473 }
474 }
475 return is8bit(disp);
476 }
477
478
479 void Assembler::emit_operand(Register reg, Register base, Register index,
480 Address::ScaleFactor scale, int disp,
481 RelocationHolder const& rspec,
482 int rip_relative_correction) {
483 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();
484
485 // Encode the registers as needed in the fields they are used in
486
487 int regenc = encode(reg) << 3;
488 int indexenc = index->is_valid() ? encode(index) << 3 : 0;
489 int baseenc = base->is_valid() ? encode(base) : 0;
490
491 if (base->is_valid()) {
492 if (index->is_valid()) {
493 assert(scale != Address::no_scale, "inconsistent address");
494 // [base + index*scale + disp]
495 if (disp == 0 && rtype == relocInfo::none &&
496 base != rbp LP64_ONLY(&& base != r13)) {
497 // [base + index*scale]
498 // [00 reg 100][ss index base]
499 assert(index != rsp, "illegal addressing mode");
500 emit_int8(0x04 | regenc);
501 emit_int8(scale << 6 | indexenc | baseenc);
502 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
503 // [base + index*scale + imm8]
504 // [01 reg 100][ss index base] imm8
505 assert(index != rsp, "illegal addressing mode");
506 emit_int8(0x44 | regenc);
507 emit_int8(scale << 6 | indexenc | baseenc);
508 emit_int8(disp & 0xFF);
509 } else {
510 // [base + index*scale + disp32]
511 // [10 reg 100][ss index base] disp32
512 assert(index != rsp, "illegal addressing mode");
513 emit_int8(0x84 | regenc);
514 emit_int8(scale << 6 | indexenc | baseenc);
515 emit_data(disp, rspec, disp32_operand);
516 }
517 } else if (base == rsp LP64_ONLY(|| base == r12)) {
518 // [rsp + disp]
519 if (disp == 0 && rtype == relocInfo::none) {
520 // [rsp]
521 // [00 reg 100][00 100 100]
522 emit_int8(0x04 | regenc);
523 emit_int8(0x24);
524 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
525 // [rsp + imm8]
526 // [01 reg 100][00 100 100] disp8
527 emit_int8(0x44 | regenc);
528 emit_int8(0x24);
529 emit_int8(disp & 0xFF);
530 } else {
531 // [rsp + imm32]
532 // [10 reg 100][00 100 100] disp32
533 emit_int8(0x84 | regenc);
534 emit_int8(0x24);
535 emit_data(disp, rspec, disp32_operand);
536 }
537 } else {
538 // [base + disp]
539 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode");
540 if (disp == 0 && rtype == relocInfo::none &&
541 base != rbp LP64_ONLY(&& base != r13)) {
542 // [base]
543 // [00 reg base]
544 emit_int8(0x00 | regenc | baseenc);
545 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
546 // [base + disp8]
547 // [01 reg base] disp8
548 emit_int8(0x40 | regenc | baseenc);
549 emit_int8(disp & 0xFF);
550 } else {
551 // [base + disp32]
552 // [10 reg base] disp32
553 emit_int8(0x80 | regenc | baseenc);
554 emit_data(disp, rspec, disp32_operand);
555 }
556 }
557 } else {
558 if (index->is_valid()) {
559 assert(scale != Address::no_scale, "inconsistent address");
560 // [index*scale + disp]
561 // [00 reg 100][ss index 101] disp32
562 assert(index != rsp, "illegal addressing mode");
563 emit_int8(0x04 | regenc);
564 emit_int8(scale << 6 | indexenc | 0x05);
565 emit_data(disp, rspec, disp32_operand);
566 } else if (rtype != relocInfo::none ) {
567 // [disp] (64bit) RIP-RELATIVE (32bit) abs
568 // [00 000 101] disp32
569
570 emit_int8(0x05 | regenc);
571 // Note that the RIP-rel. correction applies to the generated
572 // disp field, but _not_ to the target address in the rspec.
573
574 // disp was created by converting the target address minus the pc
575 // at the start of the instruction. That needs more correction here.
576 // intptr_t disp = target - next_ip;
577 assert(inst_mark() != NULL, "must be inside InstructionMark");
578 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction;
579 int64_t adjusted = disp;
580 // Do rip-rel adjustment for 64bit
581 LP64_ONLY(adjusted -= (next_ip - inst_mark()));
582 assert(is_simm32(adjusted),
583 "must be 32bit offset (RIP relative address)");
584 emit_data((int32_t) adjusted, rspec, disp32_operand);
585
586 } else {
587 // 32bit never did this, did everything as the rip-rel/disp code above
588 // [disp] ABSOLUTE
589 // [00 reg 100][00 100 101] disp32
590 emit_int8(0x04 | regenc);
591 emit_int8(0x25);
592 emit_data(disp, rspec, disp32_operand);
593 }
594 }
595 }
596
597 void Assembler::emit_operand(XMMRegister reg, Register base, Register index,
598 Address::ScaleFactor scale, int disp,
599 RelocationHolder const& rspec) {
600 if (UseAVX > 2) {
601 int xreg_enc = reg->encoding();
602 if (xreg_enc > 15) {
603 XMMRegister new_reg = as_XMMRegister(xreg_enc & 0xf);
604 emit_operand((Register)new_reg, base, index, scale, disp, rspec);
605 return;
606 }
607 }
608 emit_operand((Register)reg, base, index, scale, disp, rspec);
609 }
610
611 void Assembler::emit_operand(XMMRegister reg, Register base, XMMRegister index,
612 Address::ScaleFactor scale, int disp,
613 RelocationHolder const& rspec) {
614 if (UseAVX > 2) {
615 int xreg_enc = reg->encoding();
616 int xmmindex_enc = index->encoding();
617 XMMRegister new_reg = as_XMMRegister(xreg_enc & 0xf);
618 XMMRegister new_index = as_XMMRegister(xmmindex_enc & 0xf);
619 emit_operand((Register)new_reg, base, (Register)new_index, scale, disp, rspec);
620 } else {
621 emit_operand((Register)reg, base, (Register)index, scale, disp, rspec);
622 }
623 }
624
625
626 // Secret local extension to Assembler::WhichOperand:
627 #define end_pc_operand (_WhichOperand_limit)
628
629 address Assembler::locate_operand(address inst, WhichOperand which) {
630 // Decode the given instruction, and return the address of
631 // an embedded 32-bit operand word.
632
633 // If "which" is disp32_operand, selects the displacement portion
634 // of an effective address specifier.
635 // If "which" is imm64_operand, selects the trailing immediate constant.
636 // If "which" is call32_operand, selects the displacement of a call or jump.
637 // Caller is responsible for ensuring that there is such an operand,
638 // and that it is 32/64 bits wide.
639
640 // If "which" is end_pc_operand, find the end of the instruction.
641
642 address ip = inst;
643 bool is_64bit = false;
644
645 debug_only(bool has_disp32 = false);
646 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn
647
648 again_after_prefix:
649 switch (0xFF & *ip++) {
650
651 // These convenience macros generate groups of "case" labels for the switch.
652 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3
653 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \
654 case (x)+4: case (x)+5: case (x)+6: case (x)+7
655 #define REP16(x) REP8((x)+0): \
656 case REP8((x)+8)
657
658 case CS_segment:
659 case SS_segment:
660 case DS_segment:
661 case ES_segment:
662 case FS_segment:
663 case GS_segment:
664 // Seems dubious
665 LP64_ONLY(assert(false, "shouldn't have that prefix"));
666 assert(ip == inst+1, "only one prefix allowed");
667 goto again_after_prefix;
668
669 case 0x67:
670 case REX:
671 case REX_B:
672 case REX_X:
673 case REX_XB:
674 case REX_R:
675 case REX_RB:
676 case REX_RX:
677 case REX_RXB:
678 NOT_LP64(assert(false, "64bit prefixes"));
679 goto again_after_prefix;
680
681 case REX_W:
682 case REX_WB:
683 case REX_WX:
684 case REX_WXB:
685 case REX_WR:
686 case REX_WRB:
687 case REX_WRX:
688 case REX_WRXB:
689 NOT_LP64(assert(false, "64bit prefixes"));
690 is_64bit = true;
691 goto again_after_prefix;
692
693 case 0xFF: // pushq a; decl a; incl a; call a; jmp a
694 case 0x88: // movb a, r
695 case 0x89: // movl a, r
696 case 0x8A: // movb r, a
697 case 0x8B: // movl r, a
698 case 0x8F: // popl a
699 debug_only(has_disp32 = true);
700 break;
701
702 case 0x68: // pushq #32
703 if (which == end_pc_operand) {
704 return ip + 4;
705 }
706 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate");
707 return ip; // not produced by emit_operand
708
709 case 0x66: // movw ... (size prefix)
710 again_after_size_prefix2:
711 switch (0xFF & *ip++) {
712 case REX:
713 case REX_B:
714 case REX_X:
715 case REX_XB:
716 case REX_R:
717 case REX_RB:
718 case REX_RX:
719 case REX_RXB:
720 case REX_W:
721 case REX_WB:
722 case REX_WX:
723 case REX_WXB:
724 case REX_WR:
725 case REX_WRB:
726 case REX_WRX:
727 case REX_WRXB:
728 NOT_LP64(assert(false, "64bit prefix found"));
729 goto again_after_size_prefix2;
730 case 0x8B: // movw r, a
731 case 0x89: // movw a, r
732 debug_only(has_disp32 = true);
733 break;
734 case 0xC7: // movw a, #16
735 debug_only(has_disp32 = true);
736 tail_size = 2; // the imm16
737 break;
738 case 0x0F: // several SSE/SSE2 variants
739 ip--; // reparse the 0x0F
740 goto again_after_prefix;
741 default:
742 ShouldNotReachHere();
743 }
744 break;
745
746 case REP8(0xB8): // movl/q r, #32/#64(oop?)
747 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4);
748 // these asserts are somewhat nonsensical
749 #ifndef _LP64
750 assert(which == imm_operand || which == disp32_operand,
751 "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip));
752 #else
753 assert((which == call32_operand || which == imm_operand) && is_64bit ||
754 which == narrow_oop_operand && !is_64bit,
755 "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip));
756 #endif // _LP64
757 return ip;
758
759 case 0x69: // imul r, a, #32
760 case 0xC7: // movl a, #32(oop?)
761 tail_size = 4;
762 debug_only(has_disp32 = true); // has both kinds of operands!
763 break;
764
765 case 0x0F: // movx..., etc.
766 switch (0xFF & *ip++) {
767 case 0x3A: // pcmpestri
768 tail_size = 1;
769 case 0x38: // ptest, pmovzxbw
770 ip++; // skip opcode
771 debug_only(has_disp32 = true); // has both kinds of operands!
772 break;
773
774 case 0x70: // pshufd r, r/a, #8
775 debug_only(has_disp32 = true); // has both kinds of operands!
776 case 0x73: // psrldq r, #8
777 tail_size = 1;
778 break;
779
780 case 0x12: // movlps
781 case 0x28: // movaps
782 case 0x2E: // ucomiss
783 case 0x2F: // comiss
784 case 0x54: // andps
785 case 0x55: // andnps
786 case 0x56: // orps
787 case 0x57: // xorps
788 case 0x58: // addpd
789 case 0x59: // mulpd
790 case 0x6E: // movd
791 case 0x7E: // movd
792 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush
793 case 0xFE: // paddd
794 debug_only(has_disp32 = true);
795 break;
796
797 case 0xAD: // shrd r, a, %cl
798 case 0xAF: // imul r, a
799 case 0xBE: // movsbl r, a (movsxb)
800 case 0xBF: // movswl r, a (movsxw)
801 case 0xB6: // movzbl r, a (movzxb)
802 case 0xB7: // movzwl r, a (movzxw)
803 case REP16(0x40): // cmovl cc, r, a
804 case 0xB0: // cmpxchgb
805 case 0xB1: // cmpxchg
806 case 0xC1: // xaddl
807 case 0xC7: // cmpxchg8
808 case REP16(0x90): // setcc a
809 debug_only(has_disp32 = true);
810 // fall out of the switch to decode the address
811 break;
812
813 case 0xC4: // pinsrw r, a, #8
814 debug_only(has_disp32 = true);
815 case 0xC5: // pextrw r, r, #8
816 tail_size = 1; // the imm8
817 break;
818
819 case 0xAC: // shrd r, a, #8
820 debug_only(has_disp32 = true);
821 tail_size = 1; // the imm8
822 break;
823
824 case REP16(0x80): // jcc rdisp32
825 if (which == end_pc_operand) return ip + 4;
826 assert(which == call32_operand, "jcc has no disp32 or imm");
827 return ip;
828 default:
829 ShouldNotReachHere();
830 }
831 break;
832
833 case 0x81: // addl a, #32; addl r, #32
834 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
835 // on 32bit in the case of cmpl, the imm might be an oop
836 tail_size = 4;
837 debug_only(has_disp32 = true); // has both kinds of operands!
838 break;
839
840 case 0x83: // addl a, #8; addl r, #8
841 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
842 debug_only(has_disp32 = true); // has both kinds of operands!
843 tail_size = 1;
844 break;
845
846 case 0x9B:
847 switch (0xFF & *ip++) {
848 case 0xD9: // fnstcw a
849 debug_only(has_disp32 = true);
850 break;
851 default:
852 ShouldNotReachHere();
853 }
854 break;
855
856 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a
857 case REP4(0x10): // adc...
858 case REP4(0x20): // and...
859 case REP4(0x30): // xor...
860 case REP4(0x08): // or...
861 case REP4(0x18): // sbb...
862 case REP4(0x28): // sub...
863 case 0xF7: // mull a
864 case 0x8D: // lea r, a
865 case 0x87: // xchg r, a
866 case REP4(0x38): // cmp...
867 case 0x85: // test r, a
868 debug_only(has_disp32 = true); // has both kinds of operands!
869 break;
870
871 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8
872 case 0xC6: // movb a, #8
873 case 0x80: // cmpb a, #8
874 case 0x6B: // imul r, a, #8
875 debug_only(has_disp32 = true); // has both kinds of operands!
876 tail_size = 1; // the imm8
877 break;
878
879 case 0xC4: // VEX_3bytes
880 case 0xC5: // VEX_2bytes
881 assert((UseAVX > 0), "shouldn't have VEX prefix");
882 assert(ip == inst+1, "no prefixes allowed");
883 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions
884 // but they have prefix 0x0F and processed when 0x0F processed above.
885 //
886 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES
887 // instructions (these instructions are not supported in 64-bit mode).
888 // To distinguish them bits [7:6] are set in the VEX second byte since
889 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set
890 // those VEX bits REX and vvvv bits are inverted.
891 //
892 // Fortunately C2 doesn't generate these instructions so we don't need
893 // to check for them in product version.
894
895 // Check second byte
896 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions"));
897
898 int vex_opcode;
899 // First byte
900 if ((0xFF & *inst) == VEX_3bytes) {
901 vex_opcode = VEX_OPCODE_MASK & *ip;
902 ip++; // third byte
903 is_64bit = ((VEX_W & *ip) == VEX_W);
904 } else {
905 vex_opcode = VEX_OPCODE_0F;
906 }
907 ip++; // opcode
908 // To find the end of instruction (which == end_pc_operand).
909 switch (vex_opcode) {
910 case VEX_OPCODE_0F:
911 switch (0xFF & *ip) {
912 case 0x70: // pshufd r, r/a, #8
913 case 0x71: // ps[rl|ra|ll]w r, #8
914 case 0x72: // ps[rl|ra|ll]d r, #8
915 case 0x73: // ps[rl|ra|ll]q r, #8
916 case 0xC2: // cmp[ps|pd|ss|sd] r, r, r/a, #8
917 case 0xC4: // pinsrw r, r, r/a, #8
918 case 0xC5: // pextrw r/a, r, #8
919 case 0xC6: // shufp[s|d] r, r, r/a, #8
920 tail_size = 1; // the imm8
921 break;
922 }
923 break;
924 case VEX_OPCODE_0F_3A:
925 tail_size = 1;
926 break;
927 }
928 ip++; // skip opcode
929 debug_only(has_disp32 = true); // has both kinds of operands!
930 break;
931
932 case 0x62: // EVEX_4bytes
933 assert(VM_Version::supports_evex(), "shouldn't have EVEX prefix");
934 assert(ip == inst+1, "no prefixes allowed");
935 // no EVEX collisions, all instructions that have 0x62 opcodes
936 // have EVEX versions and are subopcodes of 0x66
937 ip++; // skip P0 and exmaine W in P1
938 is_64bit = ((VEX_W & *ip) == VEX_W);
939 ip++; // move to P2
940 ip++; // skip P2, move to opcode
941 // To find the end of instruction (which == end_pc_operand).
942 switch (0xFF & *ip) {
943 case 0x22: // pinsrd r, r/a, #8
944 case 0x61: // pcmpestri r, r/a, #8
945 case 0x70: // pshufd r, r/a, #8
946 case 0x73: // psrldq r, #8
947 tail_size = 1; // the imm8
948 break;
949 default:
950 break;
951 }
952 ip++; // skip opcode
953 debug_only(has_disp32 = true); // has both kinds of operands!
954 break;
955
956 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
957 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
958 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a
959 case 0xDD: // fld_d a; fst_d a; fstp_d a
960 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a
961 case 0xDF: // fild_d a; fistp_d a
962 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a
963 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a
964 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a
965 debug_only(has_disp32 = true);
966 break;
967
968 case 0xE8: // call rdisp32
969 case 0xE9: // jmp rdisp32
970 if (which == end_pc_operand) return ip + 4;
971 assert(which == call32_operand, "call has no disp32 or imm");
972 return ip;
973
974 case 0xF0: // Lock
975 goto again_after_prefix;
976
977 case 0xF3: // For SSE
978 case 0xF2: // For SSE2
979 switch (0xFF & *ip++) {
980 case REX:
981 case REX_B:
982 case REX_X:
983 case REX_XB:
984 case REX_R:
985 case REX_RB:
986 case REX_RX:
987 case REX_RXB:
988 case REX_W:
989 case REX_WB:
990 case REX_WX:
991 case REX_WXB:
992 case REX_WR:
993 case REX_WRB:
994 case REX_WRX:
995 case REX_WRXB:
996 NOT_LP64(assert(false, "found 64bit prefix"));
997 ip++;
998 default:
999 ip++;
1000 }
1001 debug_only(has_disp32 = true); // has both kinds of operands!
1002 break;
1003
1004 default:
1005 ShouldNotReachHere();
1006
1007 #undef REP8
1008 #undef REP16
1009 }
1010
1011 assert(which != call32_operand, "instruction is not a call, jmp, or jcc");
1012 #ifdef _LP64
1013 assert(which != imm_operand, "instruction is not a movq reg, imm64");
1014 #else
1015 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field");
1016 assert(which != imm_operand || has_disp32, "instruction has no imm32 field");
1017 #endif // LP64
1018 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field");
1019
1020 // parse the output of emit_operand
1021 int op2 = 0xFF & *ip++;
1022 int base = op2 & 0x07;
1023 int op3 = -1;
1024 const int b100 = 4;
1025 const int b101 = 5;
1026 if (base == b100 && (op2 >> 6) != 3) {
1027 op3 = 0xFF & *ip++;
1028 base = op3 & 0x07; // refetch the base
1029 }
1030 // now ip points at the disp (if any)
1031
1032 switch (op2 >> 6) {
1033 case 0:
1034 // [00 reg 100][ss index base]
1035 // [00 reg 100][00 100 esp]
1036 // [00 reg base]
1037 // [00 reg 100][ss index 101][disp32]
1038 // [00 reg 101] [disp32]
1039
1040 if (base == b101) {
1041 if (which == disp32_operand)
1042 return ip; // caller wants the disp32
1043 ip += 4; // skip the disp32
1044 }
1045 break;
1046
1047 case 1:
1048 // [01 reg 100][ss index base][disp8]
1049 // [01 reg 100][00 100 esp][disp8]
1050 // [01 reg base] [disp8]
1051 ip += 1; // skip the disp8
1052 break;
1053
1054 case 2:
1055 // [10 reg 100][ss index base][disp32]
1056 // [10 reg 100][00 100 esp][disp32]
1057 // [10 reg base] [disp32]
1058 if (which == disp32_operand)
1059 return ip; // caller wants the disp32
1060 ip += 4; // skip the disp32
1061 break;
1062
1063 case 3:
1064 // [11 reg base] (not a memory addressing mode)
1065 break;
1066 }
1067
1068 if (which == end_pc_operand) {
1069 return ip + tail_size;
1070 }
1071
1072 #ifdef _LP64
1073 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32");
1074 #else
1075 assert(which == imm_operand, "instruction has only an imm field");
1076 #endif // LP64
1077 return ip;
1078 }
1079
1080 address Assembler::locate_next_instruction(address inst) {
1081 // Secretly share code with locate_operand:
1082 return locate_operand(inst, end_pc_operand);
1083 }
1084
1085
1086 #ifdef ASSERT
1087 void Assembler::check_relocation(RelocationHolder const& rspec, int format) {
1088 address inst = inst_mark();
1089 assert(inst != NULL && inst < pc(), "must point to beginning of instruction");
1090 address opnd;
1091
1092 Relocation* r = rspec.reloc();
1093 if (r->type() == relocInfo::none) {
1094 return;
1095 } else if (r->is_call() || format == call32_operand) {
1096 // assert(format == imm32_operand, "cannot specify a nonzero format");
1097 opnd = locate_operand(inst, call32_operand);
1098 } else if (r->is_data()) {
1099 assert(format == imm_operand || format == disp32_operand
1100 LP64_ONLY(|| format == narrow_oop_operand), "format ok");
1101 opnd = locate_operand(inst, (WhichOperand)format);
1102 } else {
1103 assert(format == imm_operand, "cannot specify a format");
1104 return;
1105 }
1106 assert(opnd == pc(), "must put operand where relocs can find it");
1107 }
1108 #endif // ASSERT
1109
1110 void Assembler::emit_operand32(Register reg, Address adr) {
1111 assert(reg->encoding() < 8, "no extended registers");
1112 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1113 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1114 adr._rspec);
1115 }
1116
1117 void Assembler::emit_operand(Register reg, Address adr,
1118 int rip_relative_correction) {
1119 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1120 adr._rspec,
1121 rip_relative_correction);
1122 }
1123
1124 void Assembler::emit_operand(XMMRegister reg, Address adr) {
1125 if (adr.isxmmindex()) {
1126 emit_operand(reg, adr._base, adr._xmmindex, adr._scale, adr._disp, adr._rspec);
1127 } else {
1128 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1129 adr._rspec);
1130 }
1131 }
1132
1133 // MMX operations
1134 void Assembler::emit_operand(MMXRegister reg, Address adr) {
1135 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1136 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1137 }
1138
1139 // work around gcc (3.2.1-7a) bug
1140 void Assembler::emit_operand(Address adr, MMXRegister reg) {
1141 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1142 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1143 }
1144
1145
1146 void Assembler::emit_farith(int b1, int b2, int i) {
1147 assert(isByte(b1) && isByte(b2), "wrong opcode");
1148 assert(0 <= i && i < 8, "illegal stack offset");
1149 emit_int8(b1);
1150 emit_int8(b2 + i);
1151 }
1152
1153
1154 // Now the Assembler instructions (identical for 32/64 bits)
1155
1156 void Assembler::adcl(Address dst, int32_t imm32) {
1157 InstructionMark im(this);
1158 prefix(dst);
1159 emit_arith_operand(0x81, rdx, dst, imm32);
1160 }
1161
1162 void Assembler::adcl(Address dst, Register src) {
1163 InstructionMark im(this);
1164 prefix(dst, src);
1165 emit_int8(0x11);
1166 emit_operand(src, dst);
1167 }
1168
1169 void Assembler::adcl(Register dst, int32_t imm32) {
1170 prefix(dst);
1171 emit_arith(0x81, 0xD0, dst, imm32);
1172 }
1173
1174 void Assembler::adcl(Register dst, Address src) {
1175 InstructionMark im(this);
1176 prefix(src, dst);
1177 emit_int8(0x13);
1178 emit_operand(dst, src);
1179 }
1180
1181 void Assembler::adcl(Register dst, Register src) {
1182 (void) prefix_and_encode(dst->encoding(), src->encoding());
1183 emit_arith(0x13, 0xC0, dst, src);
1184 }
1185
1186 void Assembler::addl(Address dst, int32_t imm32) {
1187 InstructionMark im(this);
1188 prefix(dst);
1189 emit_arith_operand(0x81, rax, dst, imm32);
1190 }
1191
1192 void Assembler::addb(Address dst, int imm8) {
1193 InstructionMark im(this);
1194 prefix(dst);
1195 emit_int8((unsigned char)0x80);
1196 emit_operand(rax, dst, 1);
1197 emit_int8(imm8);
1198 }
1199
1200 void Assembler::addw(Address dst, int imm16) {
1201 InstructionMark im(this);
1202 emit_int8(0x66);
1203 prefix(dst);
1204 emit_int8((unsigned char)0x81);
1205 emit_operand(rax, dst, 2);
1206 emit_int16(imm16);
1207 }
1208
1209 void Assembler::addl(Address dst, Register src) {
1210 InstructionMark im(this);
1211 prefix(dst, src);
1212 emit_int8(0x01);
1213 emit_operand(src, dst);
1214 }
1215
1216 void Assembler::addl(Register dst, int32_t imm32) {
1217 prefix(dst);
1218 emit_arith(0x81, 0xC0, dst, imm32);
1219 }
1220
1221 void Assembler::addl(Register dst, Address src) {
1222 InstructionMark im(this);
1223 prefix(src, dst);
1224 emit_int8(0x03);
1225 emit_operand(dst, src);
1226 }
1227
1228 void Assembler::addl(Register dst, Register src) {
1229 (void) prefix_and_encode(dst->encoding(), src->encoding());
1230 emit_arith(0x03, 0xC0, dst, src);
1231 }
1232
1233 void Assembler::addr_nop_4() {
1234 assert(UseAddressNop, "no CPU support");
1235 // 4 bytes: NOP DWORD PTR [EAX+0]
1236 emit_int8(0x0F);
1237 emit_int8(0x1F);
1238 emit_int8(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
1239 emit_int8(0); // 8-bits offset (1 byte)
1240 }
1241
1242 void Assembler::addr_nop_5() {
1243 assert(UseAddressNop, "no CPU support");
1244 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
1245 emit_int8(0x0F);
1246 emit_int8(0x1F);
1247 emit_int8(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
1248 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1249 emit_int8(0); // 8-bits offset (1 byte)
1250 }
1251
1252 void Assembler::addr_nop_7() {
1253 assert(UseAddressNop, "no CPU support");
1254 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
1255 emit_int8(0x0F);
1256 emit_int8(0x1F);
1257 emit_int8((unsigned char)0x80);
1258 // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
1259 emit_int32(0); // 32-bits offset (4 bytes)
1260 }
1261
1262 void Assembler::addr_nop_8() {
1263 assert(UseAddressNop, "no CPU support");
1264 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
1265 emit_int8(0x0F);
1266 emit_int8(0x1F);
1267 emit_int8((unsigned char)0x84);
1268 // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
1269 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1270 emit_int32(0); // 32-bits offset (4 bytes)
1271 }
1272
1273 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
1274 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1275 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1276 attributes.set_rex_vex_w_reverted();
1277 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1278 emit_int8(0x58);
1279 emit_int8((unsigned char)(0xC0 | encode));
1280 }
1281
1282 void Assembler::addsd(XMMRegister dst, Address src) {
1283 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1284 InstructionMark im(this);
1285 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1286 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1287 attributes.set_rex_vex_w_reverted();
1288 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1289 emit_int8(0x58);
1290 emit_operand(dst, src);
1291 }
1292
1293 void Assembler::addss(XMMRegister dst, XMMRegister src) {
1294 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1295 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1296 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1297 emit_int8(0x58);
1298 emit_int8((unsigned char)(0xC0 | encode));
1299 }
1300
1301 void Assembler::addss(XMMRegister dst, Address src) {
1302 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1303 InstructionMark im(this);
1304 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1305 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1306 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1307 emit_int8(0x58);
1308 emit_operand(dst, src);
1309 }
1310
1311 void Assembler::aesdec(XMMRegister dst, Address src) {
1312 assert(VM_Version::supports_aes(), "");
1313 InstructionMark im(this);
1314 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1315 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1316 emit_int8((unsigned char)0xDE);
1317 emit_operand(dst, src);
1318 }
1319
1320 void Assembler::aesdec(XMMRegister dst, XMMRegister src) {
1321 assert(VM_Version::supports_aes(), "");
1322 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1323 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1324 emit_int8((unsigned char)0xDE);
1325 emit_int8(0xC0 | encode);
1326 }
1327
1328 void Assembler::vaesdec(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1329 assert(VM_Version::supports_vaes(), "");
1330 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1331 attributes.set_is_evex_instruction();
1332 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1333 emit_int8((unsigned char)0xDE);
1334 emit_int8((unsigned char)(0xC0 | encode));
1335 }
1336
1337
1338 void Assembler::aesdeclast(XMMRegister dst, Address src) {
1339 assert(VM_Version::supports_aes(), "");
1340 InstructionMark im(this);
1341 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1342 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1343 emit_int8((unsigned char)0xDF);
1344 emit_operand(dst, src);
1345 }
1346
1347 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) {
1348 assert(VM_Version::supports_aes(), "");
1349 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1350 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1351 emit_int8((unsigned char)0xDF);
1352 emit_int8((unsigned char)(0xC0 | encode));
1353 }
1354
1355 void Assembler::vaesdeclast(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1356 assert(VM_Version::supports_vaes(), "");
1357 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1358 attributes.set_is_evex_instruction();
1359 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1360 emit_int8((unsigned char)0xDF);
1361 emit_int8((unsigned char)(0xC0 | encode));
1362 }
1363
1364 void Assembler::aesenc(XMMRegister dst, Address src) {
1365 assert(VM_Version::supports_aes(), "");
1366 InstructionMark im(this);
1367 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1368 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1369 emit_int8((unsigned char)0xDC);
1370 emit_operand(dst, src);
1371 }
1372
1373 void Assembler::aesenc(XMMRegister dst, XMMRegister src) {
1374 assert(VM_Version::supports_aes(), "");
1375 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1376 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1377 emit_int8((unsigned char)0xDC);
1378 emit_int8(0xC0 | encode);
1379 }
1380
1381 void Assembler::aesenclast(XMMRegister dst, Address src) {
1382 assert(VM_Version::supports_aes(), "");
1383 InstructionMark im(this);
1384 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1385 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1386 emit_int8((unsigned char)0xDD);
1387 emit_operand(dst, src);
1388 }
1389
1390 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) {
1391 assert(VM_Version::supports_aes(), "");
1392 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1393 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1394 emit_int8((unsigned char)0xDD);
1395 emit_int8((unsigned char)(0xC0 | encode));
1396 }
1397
1398 void Assembler::andl(Address dst, int32_t imm32) {
1399 InstructionMark im(this);
1400 prefix(dst);
1401 emit_int8((unsigned char)0x81);
1402 emit_operand(rsp, dst, 4);
1403 emit_int32(imm32);
1404 }
1405
1406 void Assembler::andl(Register dst, int32_t imm32) {
1407 prefix(dst);
1408 emit_arith(0x81, 0xE0, dst, imm32);
1409 }
1410
1411 void Assembler::andl(Register dst, Address src) {
1412 InstructionMark im(this);
1413 prefix(src, dst);
1414 emit_int8(0x23);
1415 emit_operand(dst, src);
1416 }
1417
1418 void Assembler::andl(Register dst, Register src) {
1419 (void) prefix_and_encode(dst->encoding(), src->encoding());
1420 emit_arith(0x23, 0xC0, dst, src);
1421 }
1422
1423 void Assembler::andnl(Register dst, Register src1, Register src2) {
1424 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1425 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1426 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1427 emit_int8((unsigned char)0xF2);
1428 emit_int8((unsigned char)(0xC0 | encode));
1429 }
1430
1431 void Assembler::andnl(Register dst, Register src1, Address src2) {
1432 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1433 InstructionMark im(this);
1434 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1435 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1436 emit_int8((unsigned char)0xF2);
1437 emit_operand(dst, src2);
1438 }
1439
1440 void Assembler::bsfl(Register dst, Register src) {
1441 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1442 emit_int8(0x0F);
1443 emit_int8((unsigned char)0xBC);
1444 emit_int8((unsigned char)(0xC0 | encode));
1445 }
1446
1447 void Assembler::bsrl(Register dst, Register src) {
1448 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1449 emit_int8(0x0F);
1450 emit_int8((unsigned char)0xBD);
1451 emit_int8((unsigned char)(0xC0 | encode));
1452 }
1453
1454 void Assembler::bswapl(Register reg) { // bswap
1455 int encode = prefix_and_encode(reg->encoding());
1456 emit_int8(0x0F);
1457 emit_int8((unsigned char)(0xC8 | encode));
1458 }
1459
1460 void Assembler::blsil(Register dst, Register src) {
1461 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1462 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1463 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1464 emit_int8((unsigned char)0xF3);
1465 emit_int8((unsigned char)(0xC0 | encode));
1466 }
1467
1468 void Assembler::blsil(Register dst, Address src) {
1469 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1470 InstructionMark im(this);
1471 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1472 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1473 emit_int8((unsigned char)0xF3);
1474 emit_operand(rbx, src);
1475 }
1476
1477 void Assembler::blsmskl(Register dst, Register src) {
1478 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1479 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1480 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1481 emit_int8((unsigned char)0xF3);
1482 emit_int8((unsigned char)(0xC0 | encode));
1483 }
1484
1485 void Assembler::blsmskl(Register dst, Address src) {
1486 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1487 InstructionMark im(this);
1488 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1489 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1490 emit_int8((unsigned char)0xF3);
1491 emit_operand(rdx, src);
1492 }
1493
1494 void Assembler::blsrl(Register dst, Register src) {
1495 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1496 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1497 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1498 emit_int8((unsigned char)0xF3);
1499 emit_int8((unsigned char)(0xC0 | encode));
1500 }
1501
1502 void Assembler::blsrl(Register dst, Address src) {
1503 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1504 InstructionMark im(this);
1505 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1506 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1507 emit_int8((unsigned char)0xF3);
1508 emit_operand(rcx, src);
1509 }
1510
1511 void Assembler::call(Label& L, relocInfo::relocType rtype) {
1512 // suspect disp32 is always good
1513 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
1514
1515 if (L.is_bound()) {
1516 const int long_size = 5;
1517 int offs = (int)( target(L) - pc() );
1518 assert(offs <= 0, "assembler error");
1519 InstructionMark im(this);
1520 // 1110 1000 #32-bit disp
1521 emit_int8((unsigned char)0xE8);
1522 emit_data(offs - long_size, rtype, operand);
1523 } else {
1524 InstructionMark im(this);
1525 // 1110 1000 #32-bit disp
1526 L.add_patch_at(code(), locator());
1527
1528 emit_int8((unsigned char)0xE8);
1529 emit_data(int(0), rtype, operand);
1530 }
1531 }
1532
1533 void Assembler::call(Register dst) {
1534 int encode = prefix_and_encode(dst->encoding());
1535 emit_int8((unsigned char)0xFF);
1536 emit_int8((unsigned char)(0xD0 | encode));
1537 }
1538
1539
1540 void Assembler::call(Address adr) {
1541 InstructionMark im(this);
1542 prefix(adr);
1543 emit_int8((unsigned char)0xFF);
1544 emit_operand(rdx, adr);
1545 }
1546
1547 void Assembler::call_literal(address entry, RelocationHolder const& rspec) {
1548 InstructionMark im(this);
1549 emit_int8((unsigned char)0xE8);
1550 intptr_t disp = entry - (pc() + sizeof(int32_t));
1551 // Entry is NULL in case of a scratch emit.
1552 assert(entry == NULL || is_simm32(disp), "disp=" INTPTR_FORMAT " must be 32bit offset (call2)", disp);
1553 // Technically, should use call32_operand, but this format is
1554 // implied by the fact that we're emitting a call instruction.
1555
1556 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand);
1557 emit_data((int) disp, rspec, operand);
1558 }
1559
1560 void Assembler::cdql() {
1561 emit_int8((unsigned char)0x99);
1562 }
1563
1564 void Assembler::cld() {
1565 emit_int8((unsigned char)0xFC);
1566 }
1567
1568 void Assembler::cmovl(Condition cc, Register dst, Register src) {
1569 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1570 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1571 emit_int8(0x0F);
1572 emit_int8(0x40 | cc);
1573 emit_int8((unsigned char)(0xC0 | encode));
1574 }
1575
1576
1577 void Assembler::cmovl(Condition cc, Register dst, Address src) {
1578 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1579 prefix(src, dst);
1580 emit_int8(0x0F);
1581 emit_int8(0x40 | cc);
1582 emit_operand(dst, src);
1583 }
1584
1585 void Assembler::cmpb(Address dst, int imm8) {
1586 InstructionMark im(this);
1587 prefix(dst);
1588 emit_int8((unsigned char)0x80);
1589 emit_operand(rdi, dst, 1);
1590 emit_int8(imm8);
1591 }
1592
1593 void Assembler::cmpl(Address dst, int32_t imm32) {
1594 InstructionMark im(this);
1595 prefix(dst);
1596 emit_int8((unsigned char)0x81);
1597 emit_operand(rdi, dst, 4);
1598 emit_int32(imm32);
1599 }
1600
1601 void Assembler::cmpl(Register dst, int32_t imm32) {
1602 prefix(dst);
1603 emit_arith(0x81, 0xF8, dst, imm32);
1604 }
1605
1606 void Assembler::cmpl(Register dst, Register src) {
1607 (void) prefix_and_encode(dst->encoding(), src->encoding());
1608 emit_arith(0x3B, 0xC0, dst, src);
1609 }
1610
1611 void Assembler::cmpl(Register dst, Address src) {
1612 InstructionMark im(this);
1613 prefix(src, dst);
1614 emit_int8((unsigned char)0x3B);
1615 emit_operand(dst, src);
1616 }
1617
1618 void Assembler::cmpw(Address dst, int imm16) {
1619 InstructionMark im(this);
1620 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers");
1621 emit_int8(0x66);
1622 emit_int8((unsigned char)0x81);
1623 emit_operand(rdi, dst, 2);
1624 emit_int16(imm16);
1625 }
1626
1627 // The 32-bit cmpxchg compares the value at adr with the contents of rax,
1628 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1629 // The ZF is set if the compared values were equal, and cleared otherwise.
1630 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg
1631 InstructionMark im(this);
1632 prefix(adr, reg);
1633 emit_int8(0x0F);
1634 emit_int8((unsigned char)0xB1);
1635 emit_operand(reg, adr);
1636 }
1637
1638 // The 8-bit cmpxchg compares the value at adr with the contents of rax,
1639 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1640 // The ZF is set if the compared values were equal, and cleared otherwise.
1641 void Assembler::cmpxchgb(Register reg, Address adr) { // cmpxchg
1642 InstructionMark im(this);
1643 prefix(adr, reg, true);
1644 emit_int8(0x0F);
1645 emit_int8((unsigned char)0xB0);
1646 emit_operand(reg, adr);
1647 }
1648
1649 void Assembler::comisd(XMMRegister dst, Address src) {
1650 // NOTE: dbx seems to decode this as comiss even though the
1651 // 0x66 is there. Strangly ucomisd comes out correct
1652 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1653 InstructionMark im(this);
1654 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);;
1655 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1656 attributes.set_rex_vex_w_reverted();
1657 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1658 emit_int8(0x2F);
1659 emit_operand(dst, src);
1660 }
1661
1662 void Assembler::comisd(XMMRegister dst, XMMRegister src) {
1663 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1664 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1665 attributes.set_rex_vex_w_reverted();
1666 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1667 emit_int8(0x2F);
1668 emit_int8((unsigned char)(0xC0 | encode));
1669 }
1670
1671 void Assembler::comiss(XMMRegister dst, Address src) {
1672 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1673 InstructionMark im(this);
1674 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1675 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1676 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1677 emit_int8(0x2F);
1678 emit_operand(dst, src);
1679 }
1680
1681 void Assembler::comiss(XMMRegister dst, XMMRegister src) {
1682 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1683 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1684 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1685 emit_int8(0x2F);
1686 emit_int8((unsigned char)(0xC0 | encode));
1687 }
1688
1689 void Assembler::cpuid() {
1690 emit_int8(0x0F);
1691 emit_int8((unsigned char)0xA2);
1692 }
1693
1694 // Opcode / Instruction Op / En 64 - Bit Mode Compat / Leg Mode Description Implemented
1695 // F2 0F 38 F0 / r CRC32 r32, r / m8 RM Valid Valid Accumulate CRC32 on r / m8. v
1696 // F2 REX 0F 38 F0 / r CRC32 r32, r / m8* RM Valid N.E. Accumulate CRC32 on r / m8. -
1697 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E. Accumulate CRC32 on r / m8. -
1698 //
1699 // F2 0F 38 F1 / r CRC32 r32, r / m16 RM Valid Valid Accumulate CRC32 on r / m16. v
1700 //
1701 // F2 0F 38 F1 / r CRC32 r32, r / m32 RM Valid Valid Accumulate CRC32 on r / m32. v
1702 //
1703 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E. Accumulate CRC32 on r / m64. v
1704 void Assembler::crc32(Register crc, Register v, int8_t sizeInBytes) {
1705 assert(VM_Version::supports_sse4_2(), "");
1706 int8_t w = 0x01;
1707 Prefix p = Prefix_EMPTY;
1708
1709 emit_int8((int8_t)0xF2);
1710 switch (sizeInBytes) {
1711 case 1:
1712 w = 0;
1713 break;
1714 case 2:
1715 case 4:
1716 break;
1717 LP64_ONLY(case 8:)
1718 // This instruction is not valid in 32 bits
1719 // Note:
1720 // http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
1721 //
1722 // Page B - 72 Vol. 2C says
1723 // qwreg2 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : 11 qwreg1 qwreg2
1724 // mem64 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : mod qwreg r / m
1725 // F0!!!
1726 // while 3 - 208 Vol. 2A
1727 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E.Accumulate CRC32 on r / m64.
1728 //
1729 // the 0 on a last bit is reserved for a different flavor of this instruction :
1730 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E.Accumulate CRC32 on r / m8.
1731 p = REX_W;
1732 break;
1733 default:
1734 assert(0, "Unsupported value for a sizeInBytes argument");
1735 break;
1736 }
1737 LP64_ONLY(prefix(crc, v, p);)
1738 emit_int8((int8_t)0x0F);
1739 emit_int8(0x38);
1740 emit_int8((int8_t)(0xF0 | w));
1741 emit_int8(0xC0 | ((crc->encoding() & 0x7) << 3) | (v->encoding() & 7));
1742 }
1743
1744 void Assembler::crc32(Register crc, Address adr, int8_t sizeInBytes) {
1745 assert(VM_Version::supports_sse4_2(), "");
1746 InstructionMark im(this);
1747 int8_t w = 0x01;
1748 Prefix p = Prefix_EMPTY;
1749
1750 emit_int8((int8_t)0xF2);
1751 switch (sizeInBytes) {
1752 case 1:
1753 w = 0;
1754 break;
1755 case 2:
1756 case 4:
1757 break;
1758 LP64_ONLY(case 8:)
1759 // This instruction is not valid in 32 bits
1760 p = REX_W;
1761 break;
1762 default:
1763 assert(0, "Unsupported value for a sizeInBytes argument");
1764 break;
1765 }
1766 LP64_ONLY(prefix(crc, adr, p);)
1767 emit_int8((int8_t)0x0F);
1768 emit_int8(0x38);
1769 emit_int8((int8_t)(0xF0 | w));
1770 emit_operand(crc, adr);
1771 }
1772
1773 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
1774 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1775 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1776 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1777 emit_int8((unsigned char)0xE6);
1778 emit_int8((unsigned char)(0xC0 | encode));
1779 }
1780
1781 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
1782 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1783 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1784 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1785 emit_int8(0x5B);
1786 emit_int8((unsigned char)(0xC0 | encode));
1787 }
1788
1789 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
1790 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1791 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1792 attributes.set_rex_vex_w_reverted();
1793 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1794 emit_int8(0x5A);
1795 emit_int8((unsigned char)(0xC0 | encode));
1796 }
1797
1798 void Assembler::cvtsd2ss(XMMRegister dst, Address src) {
1799 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1800 InstructionMark im(this);
1801 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1802 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1803 attributes.set_rex_vex_w_reverted();
1804 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1805 emit_int8(0x5A);
1806 emit_operand(dst, src);
1807 }
1808
1809 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
1810 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1811 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1812 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1813 emit_int8(0x2A);
1814 emit_int8((unsigned char)(0xC0 | encode));
1815 }
1816
1817 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) {
1818 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1819 InstructionMark im(this);
1820 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1821 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1822 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1823 emit_int8(0x2A);
1824 emit_operand(dst, src);
1825 }
1826
1827 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
1828 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1829 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1830 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1831 emit_int8(0x2A);
1832 emit_int8((unsigned char)(0xC0 | encode));
1833 }
1834
1835 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) {
1836 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1837 InstructionMark im(this);
1838 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1839 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1840 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1841 emit_int8(0x2A);
1842 emit_operand(dst, src);
1843 }
1844
1845 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
1846 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1847 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1848 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1849 emit_int8(0x2A);
1850 emit_int8((unsigned char)(0xC0 | encode));
1851 }
1852
1853 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
1854 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1855 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1856 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1857 emit_int8(0x5A);
1858 emit_int8((unsigned char)(0xC0 | encode));
1859 }
1860
1861 void Assembler::cvtss2sd(XMMRegister dst, Address src) {
1862 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1863 InstructionMark im(this);
1864 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1865 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1866 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1867 emit_int8(0x5A);
1868 emit_operand(dst, src);
1869 }
1870
1871
1872 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
1873 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1874 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1875 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1876 emit_int8(0x2C);
1877 emit_int8((unsigned char)(0xC0 | encode));
1878 }
1879
1880 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
1881 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1882 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1883 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1884 emit_int8(0x2C);
1885 emit_int8((unsigned char)(0xC0 | encode));
1886 }
1887
1888 void Assembler::cvttpd2dq(XMMRegister dst, XMMRegister src) {
1889 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1890 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
1891 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1892 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1893 emit_int8((unsigned char)0xE6);
1894 emit_int8((unsigned char)(0xC0 | encode));
1895 }
1896
1897 void Assembler::decl(Address dst) {
1898 // Don't use it directly. Use MacroAssembler::decrement() instead.
1899 InstructionMark im(this);
1900 prefix(dst);
1901 emit_int8((unsigned char)0xFF);
1902 emit_operand(rcx, dst);
1903 }
1904
1905 void Assembler::divsd(XMMRegister dst, Address src) {
1906 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1907 InstructionMark im(this);
1908 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1909 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1910 attributes.set_rex_vex_w_reverted();
1911 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1912 emit_int8(0x5E);
1913 emit_operand(dst, src);
1914 }
1915
1916 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
1917 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1918 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1919 attributes.set_rex_vex_w_reverted();
1920 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1921 emit_int8(0x5E);
1922 emit_int8((unsigned char)(0xC0 | encode));
1923 }
1924
1925 void Assembler::divss(XMMRegister dst, Address src) {
1926 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1927 InstructionMark im(this);
1928 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1929 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1930 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1931 emit_int8(0x5E);
1932 emit_operand(dst, src);
1933 }
1934
1935 void Assembler::divss(XMMRegister dst, XMMRegister src) {
1936 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1937 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1938 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1939 emit_int8(0x5E);
1940 emit_int8((unsigned char)(0xC0 | encode));
1941 }
1942
1943 void Assembler::emms() {
1944 NOT_LP64(assert(VM_Version::supports_mmx(), ""));
1945 emit_int8(0x0F);
1946 emit_int8(0x77);
1947 }
1948
1949 void Assembler::hlt() {
1950 emit_int8((unsigned char)0xF4);
1951 }
1952
1953 void Assembler::idivl(Register src) {
1954 int encode = prefix_and_encode(src->encoding());
1955 emit_int8((unsigned char)0xF7);
1956 emit_int8((unsigned char)(0xF8 | encode));
1957 }
1958
1959 void Assembler::divl(Register src) { // Unsigned
1960 int encode = prefix_and_encode(src->encoding());
1961 emit_int8((unsigned char)0xF7);
1962 emit_int8((unsigned char)(0xF0 | encode));
1963 }
1964
1965 void Assembler::imull(Register src) {
1966 int encode = prefix_and_encode(src->encoding());
1967 emit_int8((unsigned char)0xF7);
1968 emit_int8((unsigned char)(0xE8 | encode));
1969 }
1970
1971 void Assembler::imull(Register dst, Register src) {
1972 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1973 emit_int8(0x0F);
1974 emit_int8((unsigned char)0xAF);
1975 emit_int8((unsigned char)(0xC0 | encode));
1976 }
1977
1978
1979 void Assembler::imull(Register dst, Register src, int value) {
1980 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1981 if (is8bit(value)) {
1982 emit_int8(0x6B);
1983 emit_int8((unsigned char)(0xC0 | encode));
1984 emit_int8(value & 0xFF);
1985 } else {
1986 emit_int8(0x69);
1987 emit_int8((unsigned char)(0xC0 | encode));
1988 emit_int32(value);
1989 }
1990 }
1991
1992 void Assembler::imull(Register dst, Address src) {
1993 InstructionMark im(this);
1994 prefix(src, dst);
1995 emit_int8(0x0F);
1996 emit_int8((unsigned char) 0xAF);
1997 emit_operand(dst, src);
1998 }
1999
2000
2001 void Assembler::incl(Address dst) {
2002 // Don't use it directly. Use MacroAssembler::increment() instead.
2003 InstructionMark im(this);
2004 prefix(dst);
2005 emit_int8((unsigned char)0xFF);
2006 emit_operand(rax, dst);
2007 }
2008
2009 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) {
2010 InstructionMark im(this);
2011 assert((0 <= cc) && (cc < 16), "illegal cc");
2012 if (L.is_bound()) {
2013 address dst = target(L);
2014 assert(dst != NULL, "jcc most probably wrong");
2015
2016 const int short_size = 2;
2017 const int long_size = 6;
2018 intptr_t offs = (intptr_t)dst - (intptr_t)pc();
2019 if (maybe_short && is8bit(offs - short_size)) {
2020 // 0111 tttn #8-bit disp
2021 emit_int8(0x70 | cc);
2022 emit_int8((offs - short_size) & 0xFF);
2023 } else {
2024 // 0000 1111 1000 tttn #32-bit disp
2025 assert(is_simm32(offs - long_size),
2026 "must be 32bit offset (call4)");
2027 emit_int8(0x0F);
2028 emit_int8((unsigned char)(0x80 | cc));
2029 emit_int32(offs - long_size);
2030 }
2031 } else {
2032 // Note: could eliminate cond. jumps to this jump if condition
2033 // is the same however, seems to be rather unlikely case.
2034 // Note: use jccb() if label to be bound is very close to get
2035 // an 8-bit displacement
2036 L.add_patch_at(code(), locator());
2037 emit_int8(0x0F);
2038 emit_int8((unsigned char)(0x80 | cc));
2039 emit_int32(0);
2040 }
2041 }
2042
2043 void Assembler::jccb_0(Condition cc, Label& L, const char* file, int line) {
2044 if (L.is_bound()) {
2045 const int short_size = 2;
2046 address entry = target(L);
2047 #ifdef ASSERT
2048 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
2049 intptr_t delta = short_branch_delta();
2050 if (delta != 0) {
2051 dist += (dist < 0 ? (-delta) :delta);
2052 }
2053 assert(is8bit(dist), "Dispacement too large for a short jmp at %s:%d", file, line);
2054 #endif
2055 intptr_t offs = (intptr_t)entry - (intptr_t)pc();
2056 // 0111 tttn #8-bit disp
2057 emit_int8(0x70 | cc);
2058 emit_int8((offs - short_size) & 0xFF);
2059 } else {
2060 InstructionMark im(this);
2061 L.add_patch_at(code(), locator(), file, line);
2062 emit_int8(0x70 | cc);
2063 emit_int8(0);
2064 }
2065 }
2066
2067 void Assembler::jmp(Address adr) {
2068 InstructionMark im(this);
2069 prefix(adr);
2070 emit_int8((unsigned char)0xFF);
2071 emit_operand(rsp, adr);
2072 }
2073
2074 void Assembler::jmp(Label& L, bool maybe_short) {
2075 if (L.is_bound()) {
2076 address entry = target(L);
2077 assert(entry != NULL, "jmp most probably wrong");
2078 InstructionMark im(this);
2079 const int short_size = 2;
2080 const int long_size = 5;
2081 intptr_t offs = entry - pc();
2082 if (maybe_short && is8bit(offs - short_size)) {
2083 emit_int8((unsigned char)0xEB);
2084 emit_int8((offs - short_size) & 0xFF);
2085 } else {
2086 emit_int8((unsigned char)0xE9);
2087 emit_int32(offs - long_size);
2088 }
2089 } else {
2090 // By default, forward jumps are always 32-bit displacements, since
2091 // we can't yet know where the label will be bound. If you're sure that
2092 // the forward jump will not run beyond 256 bytes, use jmpb to
2093 // force an 8-bit displacement.
2094 InstructionMark im(this);
2095 L.add_patch_at(code(), locator());
2096 emit_int8((unsigned char)0xE9);
2097 emit_int32(0);
2098 }
2099 }
2100
2101 void Assembler::jmp(Register entry) {
2102 int encode = prefix_and_encode(entry->encoding());
2103 emit_int8((unsigned char)0xFF);
2104 emit_int8((unsigned char)(0xE0 | encode));
2105 }
2106
2107 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
2108 InstructionMark im(this);
2109 emit_int8((unsigned char)0xE9);
2110 assert(dest != NULL, "must have a target");
2111 intptr_t disp = dest - (pc() + sizeof(int32_t));
2112 assert(is_simm32(disp), "must be 32bit offset (jmp)");
2113 emit_data(disp, rspec.reloc(), call32_operand);
2114 }
2115
2116 void Assembler::jmpb_0(Label& L, const char* file, int line) {
2117 if (L.is_bound()) {
2118 const int short_size = 2;
2119 address entry = target(L);
2120 assert(entry != NULL, "jmp most probably wrong");
2121 #ifdef ASSERT
2122 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
2123 intptr_t delta = short_branch_delta();
2124 if (delta != 0) {
2125 dist += (dist < 0 ? (-delta) :delta);
2126 }
2127 assert(is8bit(dist), "Dispacement too large for a short jmp at %s:%d", file, line);
2128 #endif
2129 intptr_t offs = entry - pc();
2130 emit_int8((unsigned char)0xEB);
2131 emit_int8((offs - short_size) & 0xFF);
2132 } else {
2133 InstructionMark im(this);
2134 L.add_patch_at(code(), locator(), file, line);
2135 emit_int8((unsigned char)0xEB);
2136 emit_int8(0);
2137 }
2138 }
2139
2140 void Assembler::ldmxcsr( Address src) {
2141 if (UseAVX > 0 ) {
2142 InstructionMark im(this);
2143 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2144 vex_prefix(src, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2145 emit_int8((unsigned char)0xAE);
2146 emit_operand(as_Register(2), src);
2147 } else {
2148 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2149 InstructionMark im(this);
2150 prefix(src);
2151 emit_int8(0x0F);
2152 emit_int8((unsigned char)0xAE);
2153 emit_operand(as_Register(2), src);
2154 }
2155 }
2156
2157 void Assembler::leal(Register dst, Address src) {
2158 InstructionMark im(this);
2159 #ifdef _LP64
2160 emit_int8(0x67); // addr32
2161 prefix(src, dst);
2162 #endif // LP64
2163 emit_int8((unsigned char)0x8D);
2164 emit_operand(dst, src);
2165 }
2166
2167 void Assembler::lfence() {
2168 emit_int8(0x0F);
2169 emit_int8((unsigned char)0xAE);
2170 emit_int8((unsigned char)0xE8);
2171 }
2172
2173 void Assembler::lock() {
2174 emit_int8((unsigned char)0xF0);
2175 }
2176
2177 void Assembler::lzcntl(Register dst, Register src) {
2178 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
2179 emit_int8((unsigned char)0xF3);
2180 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2181 emit_int8(0x0F);
2182 emit_int8((unsigned char)0xBD);
2183 emit_int8((unsigned char)(0xC0 | encode));
2184 }
2185
2186 // Emit mfence instruction
2187 void Assembler::mfence() {
2188 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
2189 emit_int8(0x0F);
2190 emit_int8((unsigned char)0xAE);
2191 emit_int8((unsigned char)0xF0);
2192 }
2193
2194 void Assembler::mov(Register dst, Register src) {
2195 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2196 }
2197
2198 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
2199 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2200 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2201 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2202 attributes.set_rex_vex_w_reverted();
2203 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2204 emit_int8(0x28);
2205 emit_int8((unsigned char)(0xC0 | encode));
2206 }
2207
2208 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
2209 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2210 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2211 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2212 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2213 emit_int8(0x28);
2214 emit_int8((unsigned char)(0xC0 | encode));
2215 }
2216
2217 void Assembler::movlhps(XMMRegister dst, XMMRegister src) {
2218 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2219 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2220 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2221 emit_int8(0x16);
2222 emit_int8((unsigned char)(0xC0 | encode));
2223 }
2224
2225 void Assembler::movb(Register dst, Address src) {
2226 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
2227 InstructionMark im(this);
2228 prefix(src, dst, true);
2229 emit_int8((unsigned char)0x8A);
2230 emit_operand(dst, src);
2231 }
2232
2233 void Assembler::movddup(XMMRegister dst, XMMRegister src) {
2234 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
2235 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2236 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2237 attributes.set_rex_vex_w_reverted();
2238 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2239 emit_int8(0x12);
2240 emit_int8(0xC0 | encode);
2241 }
2242
2243 void Assembler::kmovbl(KRegister dst, Register src) {
2244 assert(VM_Version::supports_avx512dq(), "");
2245 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2246 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2247 emit_int8((unsigned char)0x92);
2248 emit_int8((unsigned char)(0xC0 | encode));
2249 }
2250
2251 void Assembler::kmovbl(Register dst, KRegister src) {
2252 assert(VM_Version::supports_avx512dq(), "");
2253 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2254 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2255 emit_int8((unsigned char)0x93);
2256 emit_int8((unsigned char)(0xC0 | encode));
2257 }
2258
2259 void Assembler::kmovwl(KRegister dst, Register src) {
2260 assert(VM_Version::supports_evex(), "");
2261 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2262 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2263 emit_int8((unsigned char)0x92);
2264 emit_int8((unsigned char)(0xC0 | encode));
2265 }
2266
2267 void Assembler::kmovwl(Register dst, KRegister src) {
2268 assert(VM_Version::supports_evex(), "");
2269 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2270 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2271 emit_int8((unsigned char)0x93);
2272 emit_int8((unsigned char)(0xC0 | encode));
2273 }
2274
2275 void Assembler::kmovwl(KRegister dst, Address src) {
2276 assert(VM_Version::supports_evex(), "");
2277 InstructionMark im(this);
2278 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2279 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2280 emit_int8((unsigned char)0x90);
2281 emit_operand((Register)dst, src);
2282 }
2283
2284 void Assembler::kmovdl(KRegister dst, Register src) {
2285 assert(VM_Version::supports_avx512bw(), "");
2286 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2287 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2288 emit_int8((unsigned char)0x92);
2289 emit_int8((unsigned char)(0xC0 | encode));
2290 }
2291
2292 void Assembler::kmovdl(Register dst, KRegister src) {
2293 assert(VM_Version::supports_avx512bw(), "");
2294 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2295 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2296 emit_int8((unsigned char)0x93);
2297 emit_int8((unsigned char)(0xC0 | encode));
2298 }
2299
2300 void Assembler::kmovql(KRegister dst, KRegister src) {
2301 assert(VM_Version::supports_avx512bw(), "");
2302 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2303 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2304 emit_int8((unsigned char)0x90);
2305 emit_int8((unsigned char)(0xC0 | encode));
2306 }
2307
2308 void Assembler::kmovql(KRegister dst, Address src) {
2309 assert(VM_Version::supports_avx512bw(), "");
2310 InstructionMark im(this);
2311 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2312 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2313 emit_int8((unsigned char)0x90);
2314 emit_operand((Register)dst, src);
2315 }
2316
2317 void Assembler::kmovql(Address dst, KRegister src) {
2318 assert(VM_Version::supports_avx512bw(), "");
2319 InstructionMark im(this);
2320 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2321 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2322 emit_int8((unsigned char)0x90);
2323 emit_operand((Register)src, dst);
2324 }
2325
2326 void Assembler::kmovql(KRegister dst, Register src) {
2327 assert(VM_Version::supports_avx512bw(), "");
2328 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2329 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2330 emit_int8((unsigned char)0x92);
2331 emit_int8((unsigned char)(0xC0 | encode));
2332 }
2333
2334 void Assembler::kmovql(Register dst, KRegister src) {
2335 assert(VM_Version::supports_avx512bw(), "");
2336 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2337 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2338 emit_int8((unsigned char)0x93);
2339 emit_int8((unsigned char)(0xC0 | encode));
2340 }
2341
2342 void Assembler::knotwl(KRegister dst, KRegister src) {
2343 assert(VM_Version::supports_evex(), "");
2344 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2345 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2346 emit_int8((unsigned char)0x44);
2347 emit_int8((unsigned char)(0xC0 | encode));
2348 }
2349
2350 // This instruction produces ZF or CF flags
2351 void Assembler::kortestbl(KRegister src1, KRegister src2) {
2352 assert(VM_Version::supports_avx512dq(), "");
2353 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2354 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2355 emit_int8((unsigned char)0x98);
2356 emit_int8((unsigned char)(0xC0 | encode));
2357 }
2358
2359 // This instruction produces ZF or CF flags
2360 void Assembler::kortestwl(KRegister src1, KRegister src2) {
2361 assert(VM_Version::supports_evex(), "");
2362 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2363 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2364 emit_int8((unsigned char)0x98);
2365 emit_int8((unsigned char)(0xC0 | encode));
2366 }
2367
2368 // This instruction produces ZF or CF flags
2369 void Assembler::kortestdl(KRegister src1, KRegister src2) {
2370 assert(VM_Version::supports_avx512bw(), "");
2371 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2372 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2373 emit_int8((unsigned char)0x98);
2374 emit_int8((unsigned char)(0xC0 | encode));
2375 }
2376
2377 // This instruction produces ZF or CF flags
2378 void Assembler::kortestql(KRegister src1, KRegister src2) {
2379 assert(VM_Version::supports_avx512bw(), "");
2380 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2381 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2382 emit_int8((unsigned char)0x98);
2383 emit_int8((unsigned char)(0xC0 | encode));
2384 }
2385
2386 // This instruction produces ZF or CF flags
2387 void Assembler::ktestql(KRegister src1, KRegister src2) {
2388 assert(VM_Version::supports_avx512bw(), "");
2389 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2390 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2391 emit_int8((unsigned char)0x99);
2392 emit_int8((unsigned char)(0xC0 | encode));
2393 }
2394
2395 void Assembler::ktestq(KRegister src1, KRegister src2) {
2396 assert(VM_Version::supports_avx512bw(), "");
2397 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2398 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2399 emit_int8((unsigned char)0x99);
2400 emit_int8((unsigned char)(0xC0 | encode));
2401 }
2402
2403 void Assembler::ktestd(KRegister src1, KRegister src2) {
2404 assert(VM_Version::supports_avx512bw(), "");
2405 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2406 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2407 emit_int8((unsigned char)0x99);
2408 emit_int8((unsigned char)(0xC0 | encode));
2409 }
2410
2411 void Assembler::movb(Address dst, int imm8) {
2412 InstructionMark im(this);
2413 prefix(dst);
2414 emit_int8((unsigned char)0xC6);
2415 emit_operand(rax, dst, 1);
2416 emit_int8(imm8);
2417 }
2418
2419
2420 void Assembler::movb(Address dst, Register src) {
2421 assert(src->has_byte_register(), "must have byte register");
2422 InstructionMark im(this);
2423 prefix(dst, src, true);
2424 emit_int8((unsigned char)0x88);
2425 emit_operand(src, dst);
2426 }
2427
2428 void Assembler::movdl(XMMRegister dst, Register src) {
2429 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2430 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2431 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2432 emit_int8(0x6E);
2433 emit_int8((unsigned char)(0xC0 | encode));
2434 }
2435
2436 void Assembler::movdl(Register dst, XMMRegister src) {
2437 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2438 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2439 // swap src/dst to get correct prefix
2440 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2441 emit_int8(0x7E);
2442 emit_int8((unsigned char)(0xC0 | encode));
2443 }
2444
2445 void Assembler::movdl(XMMRegister dst, Address src) {
2446 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2447 InstructionMark im(this);
2448 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2449 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2450 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2451 emit_int8(0x6E);
2452 emit_operand(dst, src);
2453 }
2454
2455 void Assembler::movdl(Address dst, XMMRegister src) {
2456 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2457 InstructionMark im(this);
2458 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2459 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2460 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2461 emit_int8(0x7E);
2462 emit_operand(src, dst);
2463 }
2464
2465 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
2466 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2467 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2468 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2469 emit_int8(0x6F);
2470 emit_int8((unsigned char)(0xC0 | encode));
2471 }
2472
2473 void Assembler::movdqa(XMMRegister dst, Address src) {
2474 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2475 InstructionMark im(this);
2476 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2477 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2478 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2479 emit_int8(0x6F);
2480 emit_operand(dst, src);
2481 }
2482
2483 void Assembler::movdqu(XMMRegister dst, Address src) {
2484 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2485 InstructionMark im(this);
2486 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2487 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2488 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2489 emit_int8(0x6F);
2490 emit_operand(dst, src);
2491 }
2492
2493 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
2494 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2495 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2496 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2497 emit_int8(0x6F);
2498 emit_int8((unsigned char)(0xC0 | encode));
2499 }
2500
2501 void Assembler::movdqu(Address dst, XMMRegister src) {
2502 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2503 InstructionMark im(this);
2504 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2505 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2506 attributes.reset_is_clear_context();
2507 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2508 emit_int8(0x7F);
2509 emit_operand(src, dst);
2510 }
2511
2512 // Move Unaligned 256bit Vector
2513 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2514 assert(UseAVX > 0, "");
2515 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2516 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2517 emit_int8(0x6F);
2518 emit_int8((unsigned char)(0xC0 | encode));
2519 }
2520
2521 void Assembler::vmovdqu(XMMRegister dst, Address src) {
2522 assert(UseAVX > 0, "");
2523 InstructionMark im(this);
2524 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2525 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2526 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2527 emit_int8(0x6F);
2528 emit_operand(dst, src);
2529 }
2530
2531 void Assembler::vmovdqu(Address dst, XMMRegister src) {
2532 assert(UseAVX > 0, "");
2533 InstructionMark im(this);
2534 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2535 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2536 attributes.reset_is_clear_context();
2537 // swap src<->dst for encoding
2538 assert(src != xnoreg, "sanity");
2539 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2540 emit_int8(0x7F);
2541 emit_operand(src, dst);
2542 }
2543
2544 // Move Unaligned EVEX enabled Vector (programmable : 8,16,32,64)
2545 void Assembler::evmovdqub(XMMRegister dst, XMMRegister src, int vector_len) {
2546 assert(VM_Version::supports_evex(), "");
2547 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2548 attributes.set_is_evex_instruction();
2549 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2550 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2551 emit_int8(0x6F);
2552 emit_int8((unsigned char)(0xC0 | encode));
2553 }
2554
2555 void Assembler::evmovdqub(XMMRegister dst, Address src, int vector_len) {
2556 assert(VM_Version::supports_evex(), "");
2557 InstructionMark im(this);
2558 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2559 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2560 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2561 attributes.set_is_evex_instruction();
2562 vex_prefix(src, 0, dst->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2563 emit_int8(0x6F);
2564 emit_operand(dst, src);
2565 }
2566
2567 void Assembler::evmovdqub(Address dst, XMMRegister src, int vector_len) {
2568 assert(VM_Version::supports_evex(), "");
2569 assert(src != xnoreg, "sanity");
2570 InstructionMark im(this);
2571 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2572 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2573 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2574 attributes.set_is_evex_instruction();
2575 vex_prefix(dst, 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2576 emit_int8(0x7F);
2577 emit_operand(src, dst);
2578 }
2579
2580 void Assembler::evmovdqub(XMMRegister dst, KRegister mask, Address src, int vector_len) {
2581 assert(VM_Version::supports_avx512vlbw(), "");
2582 InstructionMark im(this);
2583 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2584 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2585 attributes.set_embedded_opmask_register_specifier(mask);
2586 attributes.set_is_evex_instruction();
2587 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2588 emit_int8(0x6F);
2589 emit_operand(dst, src);
2590 }
2591
2592 void Assembler::evmovdquw(XMMRegister dst, Address src, int vector_len) {
2593 assert(VM_Version::supports_evex(), "");
2594 InstructionMark im(this);
2595 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2596 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2597 attributes.set_is_evex_instruction();
2598 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2599 vex_prefix(src, 0, dst->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2600 emit_int8(0x6F);
2601 emit_operand(dst, src);
2602 }
2603
2604 void Assembler::evmovdquw(XMMRegister dst, KRegister mask, Address src, int vector_len) {
2605 assert(VM_Version::supports_avx512vlbw(), "");
2606 InstructionMark im(this);
2607 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2608 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2609 attributes.set_embedded_opmask_register_specifier(mask);
2610 attributes.set_is_evex_instruction();
2611 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2612 emit_int8(0x6F);
2613 emit_operand(dst, src);
2614 }
2615
2616 void Assembler::evmovdquw(Address dst, XMMRegister src, int vector_len) {
2617 assert(VM_Version::supports_evex(), "");
2618 assert(src != xnoreg, "sanity");
2619 InstructionMark im(this);
2620 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2621 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2622 attributes.set_is_evex_instruction();
2623 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2624 vex_prefix(dst, 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2625 emit_int8(0x7F);
2626 emit_operand(src, dst);
2627 }
2628
2629 void Assembler::evmovdquw(Address dst, KRegister mask, XMMRegister src, int vector_len) {
2630 assert(VM_Version::supports_avx512vlbw(), "");
2631 assert(src != xnoreg, "sanity");
2632 InstructionMark im(this);
2633 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2634 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2635 attributes.reset_is_clear_context();
2636 attributes.set_embedded_opmask_register_specifier(mask);
2637 attributes.set_is_evex_instruction();
2638 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2639 emit_int8(0x7F);
2640 emit_operand(src, dst);
2641 }
2642
2643 void Assembler::evmovdqul(XMMRegister dst, XMMRegister src, int vector_len) {
2644 assert(VM_Version::supports_evex(), "");
2645 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2646 attributes.set_is_evex_instruction();
2647 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2648 emit_int8(0x6F);
2649 emit_int8((unsigned char)(0xC0 | encode));
2650 }
2651
2652 void Assembler::evmovdqul(XMMRegister dst, Address src, int vector_len) {
2653 assert(VM_Version::supports_evex(), "");
2654 InstructionMark im(this);
2655 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true , /* uses_vl */ true);
2656 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2657 attributes.set_is_evex_instruction();
2658 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2659 emit_int8(0x6F);
2660 emit_operand(dst, src);
2661 }
2662
2663 void Assembler::evmovdqul(Address dst, XMMRegister src, int vector_len) {
2664 assert(VM_Version::supports_evex(), "");
2665 assert(src != xnoreg, "sanity");
2666 InstructionMark im(this);
2667 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2668 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2669 attributes.reset_is_clear_context();
2670 attributes.set_is_evex_instruction();
2671 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2672 emit_int8(0x7F);
2673 emit_operand(src, dst);
2674 }
2675
2676 void Assembler::evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) {
2677 assert(VM_Version::supports_evex(), "");
2678 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2679 attributes.set_is_evex_instruction();
2680 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2681 emit_int8(0x6F);
2682 emit_int8((unsigned char)(0xC0 | encode));
2683 }
2684
2685 void Assembler::evmovdquq(XMMRegister dst, Address src, int vector_len) {
2686 assert(VM_Version::supports_evex(), "");
2687 InstructionMark im(this);
2688 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2689 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2690 attributes.set_is_evex_instruction();
2691 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2692 emit_int8(0x6F);
2693 emit_operand(dst, src);
2694 }
2695
2696 void Assembler::evmovdquq(Address dst, XMMRegister src, int vector_len) {
2697 assert(VM_Version::supports_evex(), "");
2698 assert(src != xnoreg, "sanity");
2699 InstructionMark im(this);
2700 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2701 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2702 attributes.reset_is_clear_context();
2703 attributes.set_is_evex_instruction();
2704 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2705 emit_int8(0x7F);
2706 emit_operand(src, dst);
2707 }
2708
2709 // Uses zero extension on 64bit
2710
2711 void Assembler::movl(Register dst, int32_t imm32) {
2712 int encode = prefix_and_encode(dst->encoding());
2713 emit_int8((unsigned char)(0xB8 | encode));
2714 emit_int32(imm32);
2715 }
2716
2717 void Assembler::movl(Register dst, Register src) {
2718 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2719 emit_int8((unsigned char)0x8B);
2720 emit_int8((unsigned char)(0xC0 | encode));
2721 }
2722
2723 void Assembler::movl(Register dst, Address src) {
2724 InstructionMark im(this);
2725 prefix(src, dst);
2726 emit_int8((unsigned char)0x8B);
2727 emit_operand(dst, src);
2728 }
2729
2730 void Assembler::movl(Address dst, int32_t imm32) {
2731 InstructionMark im(this);
2732 prefix(dst);
2733 emit_int8((unsigned char)0xC7);
2734 emit_operand(rax, dst, 4);
2735 emit_int32(imm32);
2736 }
2737
2738 void Assembler::movl(Address dst, Register src) {
2739 InstructionMark im(this);
2740 prefix(dst, src);
2741 emit_int8((unsigned char)0x89);
2742 emit_operand(src, dst);
2743 }
2744
2745 // New cpus require to use movsd and movss to avoid partial register stall
2746 // when loading from memory. But for old Opteron use movlpd instead of movsd.
2747 // The selection is done in MacroAssembler::movdbl() and movflt().
2748 void Assembler::movlpd(XMMRegister dst, Address src) {
2749 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2750 InstructionMark im(this);
2751 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2752 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2753 attributes.set_rex_vex_w_reverted();
2754 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2755 emit_int8(0x12);
2756 emit_operand(dst, src);
2757 }
2758
2759 void Assembler::movq( MMXRegister dst, Address src ) {
2760 assert( VM_Version::supports_mmx(), "" );
2761 emit_int8(0x0F);
2762 emit_int8(0x6F);
2763 emit_operand(dst, src);
2764 }
2765
2766 void Assembler::movq( Address dst, MMXRegister src ) {
2767 assert( VM_Version::supports_mmx(), "" );
2768 emit_int8(0x0F);
2769 emit_int8(0x7F);
2770 // workaround gcc (3.2.1-7a) bug
2771 // In that version of gcc with only an emit_operand(MMX, Address)
2772 // gcc will tail jump and try and reverse the parameters completely
2773 // obliterating dst in the process. By having a version available
2774 // that doesn't need to swap the args at the tail jump the bug is
2775 // avoided.
2776 emit_operand(dst, src);
2777 }
2778
2779 void Assembler::movq(XMMRegister dst, Address src) {
2780 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2781 InstructionMark im(this);
2782 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2783 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2784 attributes.set_rex_vex_w_reverted();
2785 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2786 emit_int8(0x7E);
2787 emit_operand(dst, src);
2788 }
2789
2790 void Assembler::movq(Address dst, XMMRegister src) {
2791 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2792 InstructionMark im(this);
2793 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2794 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2795 attributes.set_rex_vex_w_reverted();
2796 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2797 emit_int8((unsigned char)0xD6);
2798 emit_operand(src, dst);
2799 }
2800
2801 void Assembler::movsbl(Register dst, Address src) { // movsxb
2802 InstructionMark im(this);
2803 prefix(src, dst);
2804 emit_int8(0x0F);
2805 emit_int8((unsigned char)0xBE);
2806 emit_operand(dst, src);
2807 }
2808
2809 void Assembler::movsbl(Register dst, Register src) { // movsxb
2810 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2811 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
2812 emit_int8(0x0F);
2813 emit_int8((unsigned char)0xBE);
2814 emit_int8((unsigned char)(0xC0 | encode));
2815 }
2816
2817 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
2818 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2819 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2820 attributes.set_rex_vex_w_reverted();
2821 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2822 emit_int8(0x10);
2823 emit_int8((unsigned char)(0xC0 | encode));
2824 }
2825
2826 void Assembler::movsd(XMMRegister dst, Address src) {
2827 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2828 InstructionMark im(this);
2829 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2830 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2831 attributes.set_rex_vex_w_reverted();
2832 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2833 emit_int8(0x10);
2834 emit_operand(dst, src);
2835 }
2836
2837 void Assembler::movsd(Address dst, XMMRegister src) {
2838 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2839 InstructionMark im(this);
2840 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2841 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2842 attributes.reset_is_clear_context();
2843 attributes.set_rex_vex_w_reverted();
2844 simd_prefix(src, xnoreg, dst, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2845 emit_int8(0x11);
2846 emit_operand(src, dst);
2847 }
2848
2849 void Assembler::movss(XMMRegister dst, XMMRegister src) {
2850 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2851 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2852 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2853 emit_int8(0x10);
2854 emit_int8((unsigned char)(0xC0 | encode));
2855 }
2856
2857 void Assembler::movss(XMMRegister dst, Address src) {
2858 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2859 InstructionMark im(this);
2860 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2861 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2862 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2863 emit_int8(0x10);
2864 emit_operand(dst, src);
2865 }
2866
2867 void Assembler::movss(Address dst, XMMRegister src) {
2868 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2869 InstructionMark im(this);
2870 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2871 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2872 attributes.reset_is_clear_context();
2873 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2874 emit_int8(0x11);
2875 emit_operand(src, dst);
2876 }
2877
2878 void Assembler::movswl(Register dst, Address src) { // movsxw
2879 InstructionMark im(this);
2880 prefix(src, dst);
2881 emit_int8(0x0F);
2882 emit_int8((unsigned char)0xBF);
2883 emit_operand(dst, src);
2884 }
2885
2886 void Assembler::movswl(Register dst, Register src) { // movsxw
2887 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2888 emit_int8(0x0F);
2889 emit_int8((unsigned char)0xBF);
2890 emit_int8((unsigned char)(0xC0 | encode));
2891 }
2892
2893 void Assembler::movw(Address dst, int imm16) {
2894 InstructionMark im(this);
2895
2896 emit_int8(0x66); // switch to 16-bit mode
2897 prefix(dst);
2898 emit_int8((unsigned char)0xC7);
2899 emit_operand(rax, dst, 2);
2900 emit_int16(imm16);
2901 }
2902
2903 void Assembler::movw(Register dst, Address src) {
2904 InstructionMark im(this);
2905 emit_int8(0x66);
2906 prefix(src, dst);
2907 emit_int8((unsigned char)0x8B);
2908 emit_operand(dst, src);
2909 }
2910
2911 void Assembler::movw(Address dst, Register src) {
2912 InstructionMark im(this);
2913 emit_int8(0x66);
2914 prefix(dst, src);
2915 emit_int8((unsigned char)0x89);
2916 emit_operand(src, dst);
2917 }
2918
2919 void Assembler::movzbl(Register dst, Address src) { // movzxb
2920 InstructionMark im(this);
2921 prefix(src, dst);
2922 emit_int8(0x0F);
2923 emit_int8((unsigned char)0xB6);
2924 emit_operand(dst, src);
2925 }
2926
2927 void Assembler::movzbl(Register dst, Register src) { // movzxb
2928 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2929 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
2930 emit_int8(0x0F);
2931 emit_int8((unsigned char)0xB6);
2932 emit_int8(0xC0 | encode);
2933 }
2934
2935 void Assembler::movzwl(Register dst, Address src) { // movzxw
2936 InstructionMark im(this);
2937 prefix(src, dst);
2938 emit_int8(0x0F);
2939 emit_int8((unsigned char)0xB7);
2940 emit_operand(dst, src);
2941 }
2942
2943 void Assembler::movzwl(Register dst, Register src) { // movzxw
2944 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2945 emit_int8(0x0F);
2946 emit_int8((unsigned char)0xB7);
2947 emit_int8(0xC0 | encode);
2948 }
2949
2950 void Assembler::mull(Address src) {
2951 InstructionMark im(this);
2952 prefix(src);
2953 emit_int8((unsigned char)0xF7);
2954 emit_operand(rsp, src);
2955 }
2956
2957 void Assembler::mull(Register src) {
2958 int encode = prefix_and_encode(src->encoding());
2959 emit_int8((unsigned char)0xF7);
2960 emit_int8((unsigned char)(0xE0 | encode));
2961 }
2962
2963 void Assembler::mulsd(XMMRegister dst, Address src) {
2964 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2965 InstructionMark im(this);
2966 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2967 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2968 attributes.set_rex_vex_w_reverted();
2969 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2970 emit_int8(0x59);
2971 emit_operand(dst, src);
2972 }
2973
2974 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
2975 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2976 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2977 attributes.set_rex_vex_w_reverted();
2978 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2979 emit_int8(0x59);
2980 emit_int8((unsigned char)(0xC0 | encode));
2981 }
2982
2983 void Assembler::mulss(XMMRegister dst, Address src) {
2984 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2985 InstructionMark im(this);
2986 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2987 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2988 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2989 emit_int8(0x59);
2990 emit_operand(dst, src);
2991 }
2992
2993 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
2994 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2995 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2996 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2997 emit_int8(0x59);
2998 emit_int8((unsigned char)(0xC0 | encode));
2999 }
3000
3001 void Assembler::negl(Register dst) {
3002 int encode = prefix_and_encode(dst->encoding());
3003 emit_int8((unsigned char)0xF7);
3004 emit_int8((unsigned char)(0xD8 | encode));
3005 }
3006
3007 void Assembler::nop(int i) {
3008 #ifdef ASSERT
3009 assert(i > 0, " ");
3010 // The fancy nops aren't currently recognized by debuggers making it a
3011 // pain to disassemble code while debugging. If asserts are on clearly
3012 // speed is not an issue so simply use the single byte traditional nop
3013 // to do alignment.
3014
3015 for (; i > 0 ; i--) emit_int8((unsigned char)0x90);
3016 return;
3017
3018 #endif // ASSERT
3019
3020 if (UseAddressNop && VM_Version::is_intel()) {
3021 //
3022 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel
3023 // 1: 0x90
3024 // 2: 0x66 0x90
3025 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
3026 // 4: 0x0F 0x1F 0x40 0x00
3027 // 5: 0x0F 0x1F 0x44 0x00 0x00
3028 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
3029 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3030 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3031 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3032 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3033 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3034
3035 // The rest coding is Intel specific - don't use consecutive address nops
3036
3037 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3038 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3039 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3040 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3041
3042 while(i >= 15) {
3043 // For Intel don't generate consecutive addess nops (mix with regular nops)
3044 i -= 15;
3045 emit_int8(0x66); // size prefix
3046 emit_int8(0x66); // size prefix
3047 emit_int8(0x66); // size prefix
3048 addr_nop_8();
3049 emit_int8(0x66); // size prefix
3050 emit_int8(0x66); // size prefix
3051 emit_int8(0x66); // size prefix
3052 emit_int8((unsigned char)0x90);
3053 // nop
3054 }
3055 switch (i) {
3056 case 14:
3057 emit_int8(0x66); // size prefix
3058 case 13:
3059 emit_int8(0x66); // size prefix
3060 case 12:
3061 addr_nop_8();
3062 emit_int8(0x66); // size prefix
3063 emit_int8(0x66); // size prefix
3064 emit_int8(0x66); // size prefix
3065 emit_int8((unsigned char)0x90);
3066 // nop
3067 break;
3068 case 11:
3069 emit_int8(0x66); // size prefix
3070 case 10:
3071 emit_int8(0x66); // size prefix
3072 case 9:
3073 emit_int8(0x66); // size prefix
3074 case 8:
3075 addr_nop_8();
3076 break;
3077 case 7:
3078 addr_nop_7();
3079 break;
3080 case 6:
3081 emit_int8(0x66); // size prefix
3082 case 5:
3083 addr_nop_5();
3084 break;
3085 case 4:
3086 addr_nop_4();
3087 break;
3088 case 3:
3089 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
3090 emit_int8(0x66); // size prefix
3091 case 2:
3092 emit_int8(0x66); // size prefix
3093 case 1:
3094 emit_int8((unsigned char)0x90);
3095 // nop
3096 break;
3097 default:
3098 assert(i == 0, " ");
3099 }
3100 return;
3101 }
3102 if (UseAddressNop && VM_Version::is_amd()) {
3103 //
3104 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD.
3105 // 1: 0x90
3106 // 2: 0x66 0x90
3107 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
3108 // 4: 0x0F 0x1F 0x40 0x00
3109 // 5: 0x0F 0x1F 0x44 0x00 0x00
3110 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
3111 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3112 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3113 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3114 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3115 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3116
3117 // The rest coding is AMD specific - use consecutive address nops
3118
3119 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
3120 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
3121 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3122 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3123 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3124 // Size prefixes (0x66) are added for larger sizes
3125
3126 while(i >= 22) {
3127 i -= 11;
3128 emit_int8(0x66); // size prefix
3129 emit_int8(0x66); // size prefix
3130 emit_int8(0x66); // size prefix
3131 addr_nop_8();
3132 }
3133 // Generate first nop for size between 21-12
3134 switch (i) {
3135 case 21:
3136 i -= 1;
3137 emit_int8(0x66); // size prefix
3138 case 20:
3139 case 19:
3140 i -= 1;
3141 emit_int8(0x66); // size prefix
3142 case 18:
3143 case 17:
3144 i -= 1;
3145 emit_int8(0x66); // size prefix
3146 case 16:
3147 case 15:
3148 i -= 8;
3149 addr_nop_8();
3150 break;
3151 case 14:
3152 case 13:
3153 i -= 7;
3154 addr_nop_7();
3155 break;
3156 case 12:
3157 i -= 6;
3158 emit_int8(0x66); // size prefix
3159 addr_nop_5();
3160 break;
3161 default:
3162 assert(i < 12, " ");
3163 }
3164
3165 // Generate second nop for size between 11-1
3166 switch (i) {
3167 case 11:
3168 emit_int8(0x66); // size prefix
3169 case 10:
3170 emit_int8(0x66); // size prefix
3171 case 9:
3172 emit_int8(0x66); // size prefix
3173 case 8:
3174 addr_nop_8();
3175 break;
3176 case 7:
3177 addr_nop_7();
3178 break;
3179 case 6:
3180 emit_int8(0x66); // size prefix
3181 case 5:
3182 addr_nop_5();
3183 break;
3184 case 4:
3185 addr_nop_4();
3186 break;
3187 case 3:
3188 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
3189 emit_int8(0x66); // size prefix
3190 case 2:
3191 emit_int8(0x66); // size prefix
3192 case 1:
3193 emit_int8((unsigned char)0x90);
3194 // nop
3195 break;
3196 default:
3197 assert(i == 0, " ");
3198 }
3199 return;
3200 }
3201
3202 if (UseAddressNop && VM_Version::is_zx()) {
3203 //
3204 // Using multi-bytes nops "0x0F 0x1F [address]" for ZX
3205 // 1: 0x90
3206 // 2: 0x66 0x90
3207 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
3208 // 4: 0x0F 0x1F 0x40 0x00
3209 // 5: 0x0F 0x1F 0x44 0x00 0x00
3210 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
3211 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3212 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3213 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3214 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3215 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3216
3217 // The rest coding is ZX specific - don't use consecutive address nops
3218
3219 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3220 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3221 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3222 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3223
3224 while (i >= 15) {
3225 // For ZX don't generate consecutive addess nops (mix with regular nops)
3226 i -= 15;
3227 emit_int8(0x66); // size prefix
3228 emit_int8(0x66); // size prefix
3229 emit_int8(0x66); // size prefix
3230 addr_nop_8();
3231 emit_int8(0x66); // size prefix
3232 emit_int8(0x66); // size prefix
3233 emit_int8(0x66); // size prefix
3234 emit_int8((unsigned char)0x90);
3235 // nop
3236 }
3237 switch (i) {
3238 case 14:
3239 emit_int8(0x66); // size prefix
3240 case 13:
3241 emit_int8(0x66); // size prefix
3242 case 12:
3243 addr_nop_8();
3244 emit_int8(0x66); // size prefix
3245 emit_int8(0x66); // size prefix
3246 emit_int8(0x66); // size prefix
3247 emit_int8((unsigned char)0x90);
3248 // nop
3249 break;
3250 case 11:
3251 emit_int8(0x66); // size prefix
3252 case 10:
3253 emit_int8(0x66); // size prefix
3254 case 9:
3255 emit_int8(0x66); // size prefix
3256 case 8:
3257 addr_nop_8();
3258 break;
3259 case 7:
3260 addr_nop_7();
3261 break;
3262 case 6:
3263 emit_int8(0x66); // size prefix
3264 case 5:
3265 addr_nop_5();
3266 break;
3267 case 4:
3268 addr_nop_4();
3269 break;
3270 case 3:
3271 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
3272 emit_int8(0x66); // size prefix
3273 case 2:
3274 emit_int8(0x66); // size prefix
3275 case 1:
3276 emit_int8((unsigned char)0x90);
3277 // nop
3278 break;
3279 default:
3280 assert(i == 0, " ");
3281 }
3282 return;
3283 }
3284
3285 // Using nops with size prefixes "0x66 0x90".
3286 // From AMD Optimization Guide:
3287 // 1: 0x90
3288 // 2: 0x66 0x90
3289 // 3: 0x66 0x66 0x90
3290 // 4: 0x66 0x66 0x66 0x90
3291 // 5: 0x66 0x66 0x90 0x66 0x90
3292 // 6: 0x66 0x66 0x90 0x66 0x66 0x90
3293 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90
3294 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90
3295 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
3296 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
3297 //
3298 while(i > 12) {
3299 i -= 4;
3300 emit_int8(0x66); // size prefix
3301 emit_int8(0x66);
3302 emit_int8(0x66);
3303 emit_int8((unsigned char)0x90);
3304 // nop
3305 }
3306 // 1 - 12 nops
3307 if(i > 8) {
3308 if(i > 9) {
3309 i -= 1;
3310 emit_int8(0x66);
3311 }
3312 i -= 3;
3313 emit_int8(0x66);
3314 emit_int8(0x66);
3315 emit_int8((unsigned char)0x90);
3316 }
3317 // 1 - 8 nops
3318 if(i > 4) {
3319 if(i > 6) {
3320 i -= 1;
3321 emit_int8(0x66);
3322 }
3323 i -= 3;
3324 emit_int8(0x66);
3325 emit_int8(0x66);
3326 emit_int8((unsigned char)0x90);
3327 }
3328 switch (i) {
3329 case 4:
3330 emit_int8(0x66);
3331 case 3:
3332 emit_int8(0x66);
3333 case 2:
3334 emit_int8(0x66);
3335 case 1:
3336 emit_int8((unsigned char)0x90);
3337 break;
3338 default:
3339 assert(i == 0, " ");
3340 }
3341 }
3342
3343 void Assembler::notl(Register dst) {
3344 int encode = prefix_and_encode(dst->encoding());
3345 emit_int8((unsigned char)0xF7);
3346 emit_int8((unsigned char)(0xD0 | encode));
3347 }
3348
3349 void Assembler::orl(Address dst, int32_t imm32) {
3350 InstructionMark im(this);
3351 prefix(dst);
3352 emit_arith_operand(0x81, rcx, dst, imm32);
3353 }
3354
3355 void Assembler::orl(Register dst, int32_t imm32) {
3356 prefix(dst);
3357 emit_arith(0x81, 0xC8, dst, imm32);
3358 }
3359
3360 void Assembler::orl(Register dst, Address src) {
3361 InstructionMark im(this);
3362 prefix(src, dst);
3363 emit_int8(0x0B);
3364 emit_operand(dst, src);
3365 }
3366
3367 void Assembler::orl(Register dst, Register src) {
3368 (void) prefix_and_encode(dst->encoding(), src->encoding());
3369 emit_arith(0x0B, 0xC0, dst, src);
3370 }
3371
3372 void Assembler::orl(Address dst, Register src) {
3373 InstructionMark im(this);
3374 prefix(dst, src);
3375 emit_int8(0x09);
3376 emit_operand(src, dst);
3377 }
3378
3379 void Assembler::orb(Address dst, int imm8) {
3380 InstructionMark im(this);
3381 prefix(dst);
3382 emit_int8((unsigned char)0x80);
3383 emit_operand(rcx, dst, 1);
3384 emit_int8(imm8);
3385 }
3386
3387 void Assembler::packuswb(XMMRegister dst, Address src) {
3388 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3389 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3390 InstructionMark im(this);
3391 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3392 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3393 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3394 emit_int8(0x67);
3395 emit_operand(dst, src);
3396 }
3397
3398 void Assembler::packuswb(XMMRegister dst, XMMRegister src) {
3399 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3400 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3401 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3402 emit_int8(0x67);
3403 emit_int8((unsigned char)(0xC0 | encode));
3404 }
3405
3406 void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3407 assert(UseAVX > 0, "some form of AVX must be enabled");
3408 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3409 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3410 emit_int8(0x67);
3411 emit_int8((unsigned char)(0xC0 | encode));
3412 }
3413
3414 void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len) {
3415 assert(VM_Version::supports_avx2(), "");
3416 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3417 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3418 emit_int8(0x00);
3419 emit_int8(0xC0 | encode);
3420 emit_int8(imm8);
3421 }
3422
3423 void Assembler::vperm2i128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) {
3424 assert(VM_Version::supports_avx2(), "");
3425 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3426 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3427 emit_int8(0x46);
3428 emit_int8(0xC0 | encode);
3429 emit_int8(imm8);
3430 }
3431
3432 void Assembler::vperm2f128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) {
3433 assert(VM_Version::supports_avx(), "");
3434 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3435 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3436 emit_int8(0x06);
3437 emit_int8(0xC0 | encode);
3438 emit_int8(imm8);
3439 }
3440
3441 void Assembler::evpermi2q(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3442 assert(VM_Version::supports_evex(), "");
3443 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3444 attributes.set_is_evex_instruction();
3445 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3446 emit_int8(0x76);
3447 emit_int8((unsigned char)(0xC0 | encode));
3448 }
3449
3450
3451 void Assembler::pause() {
3452 emit_int8((unsigned char)0xF3);
3453 emit_int8((unsigned char)0x90);
3454 }
3455
3456 void Assembler::ud2() {
3457 emit_int8(0x0F);
3458 emit_int8(0x0B);
3459 }
3460
3461 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3462 assert(VM_Version::supports_sse4_2(), "");
3463 InstructionMark im(this);
3464 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3465 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3466 emit_int8(0x61);
3467 emit_operand(dst, src);
3468 emit_int8(imm8);
3469 }
3470
3471 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3472 assert(VM_Version::supports_sse4_2(), "");
3473 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3474 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3475 emit_int8(0x61);
3476 emit_int8((unsigned char)(0xC0 | encode));
3477 emit_int8(imm8);
3478 }
3479
3480 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3481 void Assembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
3482 assert(VM_Version::supports_sse2(), "");
3483 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3484 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3485 emit_int8(0x74);
3486 emit_int8((unsigned char)(0xC0 | encode));
3487 }
3488
3489 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3490 void Assembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3491 assert(VM_Version::supports_avx(), "");
3492 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3493 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3494 emit_int8(0x74);
3495 emit_int8((unsigned char)(0xC0 | encode));
3496 }
3497
3498 // In this context, kdst is written the mask used to process the equal components
3499 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3500 assert(VM_Version::supports_avx512bw(), "");
3501 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3502 attributes.set_is_evex_instruction();
3503 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3504 emit_int8(0x74);
3505 emit_int8((unsigned char)(0xC0 | encode));
3506 }
3507
3508 void Assembler::evpcmpgtb(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3509 assert(VM_Version::supports_avx512vlbw(), "");
3510 InstructionMark im(this);
3511 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3512 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3513 attributes.set_is_evex_instruction();
3514 int dst_enc = kdst->encoding();
3515 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3516 emit_int8(0x64);
3517 emit_operand(as_Register(dst_enc), src);
3518 }
3519
3520 void Assembler::evpcmpgtb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len) {
3521 assert(VM_Version::supports_avx512vlbw(), "");
3522 InstructionMark im(this);
3523 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3524 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3525 attributes.reset_is_clear_context();
3526 attributes.set_embedded_opmask_register_specifier(mask);
3527 attributes.set_is_evex_instruction();
3528 int dst_enc = kdst->encoding();
3529 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3530 emit_int8(0x64);
3531 emit_operand(as_Register(dst_enc), src);
3532 }
3533
3534 void Assembler::evpcmpuw(KRegister kdst, XMMRegister nds, XMMRegister src, ComparisonPredicate vcc, int vector_len) {
3535 assert(VM_Version::supports_avx512vlbw(), "");
3536 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3537 attributes.set_is_evex_instruction();
3538 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3539 emit_int8(0x3E);
3540 emit_int8((unsigned char)(0xC0 | encode));
3541 emit_int8(vcc);
3542 }
3543
3544 void Assembler::evpcmpuw(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, ComparisonPredicate vcc, int vector_len) {
3545 assert(VM_Version::supports_avx512vlbw(), "");
3546 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3547 attributes.reset_is_clear_context();
3548 attributes.set_embedded_opmask_register_specifier(mask);
3549 attributes.set_is_evex_instruction();
3550 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3551 emit_int8(0x3E);
3552 emit_int8((unsigned char)(0xC0 | encode));
3553 emit_int8(vcc);
3554 }
3555
3556 void Assembler::evpcmpuw(KRegister kdst, XMMRegister nds, Address src, ComparisonPredicate vcc, int vector_len) {
3557 assert(VM_Version::supports_avx512vlbw(), "");
3558 InstructionMark im(this);
3559 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3560 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3561 attributes.set_is_evex_instruction();
3562 int dst_enc = kdst->encoding();
3563 vex_prefix(src, nds->encoding(), kdst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3564 emit_int8(0x3E);
3565 emit_operand(as_Register(dst_enc), src);
3566 emit_int8(vcc);
3567 }
3568
3569 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3570 assert(VM_Version::supports_avx512bw(), "");
3571 InstructionMark im(this);
3572 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3573 attributes.set_is_evex_instruction();
3574 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3575 int dst_enc = kdst->encoding();
3576 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3577 emit_int8(0x74);
3578 emit_operand(as_Register(dst_enc), src);
3579 }
3580
3581 void Assembler::evpcmpeqb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len) {
3582 assert(VM_Version::supports_avx512vlbw(), "");
3583 InstructionMark im(this);
3584 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_reg_mask */ false, /* uses_vl */ true);
3585 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3586 attributes.reset_is_clear_context();
3587 attributes.set_embedded_opmask_register_specifier(mask);
3588 attributes.set_is_evex_instruction();
3589 vex_prefix(src, nds->encoding(), kdst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3590 emit_int8(0x74);
3591 emit_operand(as_Register(kdst->encoding()), src);
3592 }
3593
3594 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3595 void Assembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3596 assert(VM_Version::supports_sse2(), "");
3597 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3598 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3599 emit_int8(0x75);
3600 emit_int8((unsigned char)(0xC0 | encode));
3601 }
3602
3603 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3604 void Assembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3605 assert(VM_Version::supports_avx(), "");
3606 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3607 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3608 emit_int8(0x75);
3609 emit_int8((unsigned char)(0xC0 | encode));
3610 }
3611
3612 // In this context, kdst is written the mask used to process the equal components
3613 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3614 assert(VM_Version::supports_avx512bw(), "");
3615 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3616 attributes.set_is_evex_instruction();
3617 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3618 emit_int8(0x75);
3619 emit_int8((unsigned char)(0xC0 | encode));
3620 }
3621
3622 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3623 assert(VM_Version::supports_avx512bw(), "");
3624 InstructionMark im(this);
3625 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3626 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3627 attributes.set_is_evex_instruction();
3628 int dst_enc = kdst->encoding();
3629 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3630 emit_int8(0x75);
3631 emit_operand(as_Register(dst_enc), src);
3632 }
3633
3634 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3635 void Assembler::pcmpeqd(XMMRegister dst, XMMRegister src) {
3636 assert(VM_Version::supports_sse2(), "");
3637 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3638 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3639 emit_int8(0x76);
3640 emit_int8((unsigned char)(0xC0 | encode));
3641 }
3642
3643 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3644 void Assembler::vpcmpeqd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3645 assert(VM_Version::supports_avx(), "");
3646 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3647 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3648 emit_int8(0x76);
3649 emit_int8((unsigned char)(0xC0 | encode));
3650 }
3651
3652 // In this context, kdst is written the mask used to process the equal components
3653 void Assembler::evpcmpeqd(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3654 assert(VM_Version::supports_evex(), "");
3655 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3656 attributes.set_is_evex_instruction();
3657 attributes.reset_is_clear_context();
3658 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3659 emit_int8(0x76);
3660 emit_int8((unsigned char)(0xC0 | encode));
3661 }
3662
3663 void Assembler::evpcmpeqd(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3664 assert(VM_Version::supports_evex(), "");
3665 InstructionMark im(this);
3666 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3667 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3668 attributes.reset_is_clear_context();
3669 attributes.set_is_evex_instruction();
3670 int dst_enc = kdst->encoding();
3671 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3672 emit_int8(0x76);
3673 emit_operand(as_Register(dst_enc), src);
3674 }
3675
3676 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3677 void Assembler::pcmpeqq(XMMRegister dst, XMMRegister src) {
3678 assert(VM_Version::supports_sse4_1(), "");
3679 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3680 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3681 emit_int8(0x29);
3682 emit_int8((unsigned char)(0xC0 | encode));
3683 }
3684
3685 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3686 void Assembler::vpcmpeqq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3687 assert(VM_Version::supports_avx(), "");
3688 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3689 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3690 emit_int8(0x29);
3691 emit_int8((unsigned char)(0xC0 | encode));
3692 }
3693
3694 // In this context, kdst is written the mask used to process the equal components
3695 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3696 assert(VM_Version::supports_evex(), "");
3697 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3698 attributes.reset_is_clear_context();
3699 attributes.set_is_evex_instruction();
3700 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3701 emit_int8(0x29);
3702 emit_int8((unsigned char)(0xC0 | encode));
3703 }
3704
3705 // In this context, kdst is written the mask used to process the equal components
3706 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3707 assert(VM_Version::supports_evex(), "");
3708 InstructionMark im(this);
3709 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3710 attributes.reset_is_clear_context();
3711 attributes.set_is_evex_instruction();
3712 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
3713 int dst_enc = kdst->encoding();
3714 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3715 emit_int8(0x29);
3716 emit_operand(as_Register(dst_enc), src);
3717 }
3718
3719 void Assembler::pmovmskb(Register dst, XMMRegister src) {
3720 assert(VM_Version::supports_sse2(), "");
3721 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3722 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3723 emit_int8((unsigned char)0xD7);
3724 emit_int8((unsigned char)(0xC0 | encode));
3725 }
3726
3727 void Assembler::vpmovmskb(Register dst, XMMRegister src) {
3728 assert(VM_Version::supports_avx2(), "");
3729 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3730 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3731 emit_int8((unsigned char)0xD7);
3732 emit_int8((unsigned char)(0xC0 | encode));
3733 }
3734
3735 void Assembler::pextrd(Register dst, XMMRegister src, int imm8) {
3736 assert(VM_Version::supports_sse4_1(), "");
3737 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
3738 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3739 emit_int8(0x16);
3740 emit_int8((unsigned char)(0xC0 | encode));
3741 emit_int8(imm8);
3742 }
3743
3744 void Assembler::pextrd(Address dst, XMMRegister src, int imm8) {
3745 assert(VM_Version::supports_sse4_1(), "");
3746 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
3747 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3748 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3749 emit_int8(0x16);
3750 emit_operand(src, dst);
3751 emit_int8(imm8);
3752 }
3753
3754 void Assembler::pextrq(Register dst, XMMRegister src, int imm8) {
3755 assert(VM_Version::supports_sse4_1(), "");
3756 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
3757 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3758 emit_int8(0x16);
3759 emit_int8((unsigned char)(0xC0 | encode));
3760 emit_int8(imm8);
3761 }
3762
3763 void Assembler::pextrq(Address dst, XMMRegister src, int imm8) {
3764 assert(VM_Version::supports_sse4_1(), "");
3765 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
3766 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3767 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3768 emit_int8(0x16);
3769 emit_operand(src, dst);
3770 emit_int8(imm8);
3771 }
3772
3773 void Assembler::pextrw(Register dst, XMMRegister src, int imm8) {
3774 assert(VM_Version::supports_sse2(), "");
3775 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3776 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3777 emit_int8((unsigned char)0xC5);
3778 emit_int8((unsigned char)(0xC0 | encode));
3779 emit_int8(imm8);
3780 }
3781
3782 void Assembler::pextrw(Address dst, XMMRegister src, int imm8) {
3783 assert(VM_Version::supports_sse4_1(), "");
3784 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3785 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
3786 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3787 emit_int8((unsigned char)0x15);
3788 emit_operand(src, dst);
3789 emit_int8(imm8);
3790 }
3791
3792 void Assembler::pextrb(Address dst, XMMRegister src, int imm8) {
3793 assert(VM_Version::supports_sse4_1(), "");
3794 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3795 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
3796 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3797 emit_int8(0x14);
3798 emit_operand(src, dst);
3799 emit_int8(imm8);
3800 }
3801
3802 void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) {
3803 assert(VM_Version::supports_sse4_1(), "");
3804 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
3805 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3806 emit_int8(0x22);
3807 emit_int8((unsigned char)(0xC0 | encode));
3808 emit_int8(imm8);
3809 }
3810
3811 void Assembler::pinsrd(XMMRegister dst, Address src, int imm8) {
3812 assert(VM_Version::supports_sse4_1(), "");
3813 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
3814 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3815 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3816 emit_int8(0x22);
3817 emit_operand(dst,src);
3818 emit_int8(imm8);
3819 }
3820
3821 void Assembler::pinsrq(XMMRegister dst, Register src, int imm8) {
3822 assert(VM_Version::supports_sse4_1(), "");
3823 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
3824 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3825 emit_int8(0x22);
3826 emit_int8((unsigned char)(0xC0 | encode));
3827 emit_int8(imm8);
3828 }
3829
3830 void Assembler::pinsrq(XMMRegister dst, Address src, int imm8) {
3831 assert(VM_Version::supports_sse4_1(), "");
3832 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
3833 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3834 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3835 emit_int8(0x22);
3836 emit_operand(dst, src);
3837 emit_int8(imm8);
3838 }
3839
3840 void Assembler::pinsrw(XMMRegister dst, Register src, int imm8) {
3841 assert(VM_Version::supports_sse2(), "");
3842 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3843 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3844 emit_int8((unsigned char)0xC4);
3845 emit_int8((unsigned char)(0xC0 | encode));
3846 emit_int8(imm8);
3847 }
3848
3849 void Assembler::pinsrw(XMMRegister dst, Address src, int imm8) {
3850 assert(VM_Version::supports_sse2(), "");
3851 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3852 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
3853 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3854 emit_int8((unsigned char)0xC4);
3855 emit_operand(dst, src);
3856 emit_int8(imm8);
3857 }
3858
3859 void Assembler::pinsrb(XMMRegister dst, Address src, int imm8) {
3860 assert(VM_Version::supports_sse4_1(), "");
3861 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3862 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
3863 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3864 emit_int8(0x20);
3865 emit_operand(dst, src);
3866 emit_int8(imm8);
3867 }
3868
3869 void Assembler::pmovzxbw(XMMRegister dst, Address src) {
3870 assert(VM_Version::supports_sse4_1(), "");
3871 InstructionMark im(this);
3872 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3873 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3874 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3875 emit_int8(0x30);
3876 emit_operand(dst, src);
3877 }
3878
3879 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3880 assert(VM_Version::supports_sse4_1(), "");
3881 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3882 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3883 emit_int8(0x30);
3884 emit_int8((unsigned char)(0xC0 | encode));
3885 }
3886
3887 void Assembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
3888 assert(VM_Version::supports_avx(), "");
3889 InstructionMark im(this);
3890 assert(dst != xnoreg, "sanity");
3891 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3892 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3893 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3894 emit_int8(0x30);
3895 emit_operand(dst, src);
3896 }
3897
3898 void Assembler::vpmovzxbw(XMMRegister dst, XMMRegister src, int vector_len) {
3899 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
3900 vector_len == AVX_256bit? VM_Version::supports_avx2() :
3901 vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0, "");
3902 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3903 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3904 emit_int8(0x30);
3905 emit_int8((unsigned char) (0xC0 | encode));
3906 }
3907
3908
3909 void Assembler::evpmovzxbw(XMMRegister dst, KRegister mask, Address src, int vector_len) {
3910 assert(VM_Version::supports_avx512vlbw(), "");
3911 assert(dst != xnoreg, "sanity");
3912 InstructionMark im(this);
3913 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3914 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3915 attributes.set_embedded_opmask_register_specifier(mask);
3916 attributes.set_is_evex_instruction();
3917 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3918 emit_int8(0x30);
3919 emit_operand(dst, src);
3920 }
3921 void Assembler::evpmovwb(Address dst, XMMRegister src, int vector_len) {
3922 assert(VM_Version::supports_avx512vlbw(), "");
3923 assert(src != xnoreg, "sanity");
3924 InstructionMark im(this);
3925 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3926 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3927 attributes.set_is_evex_instruction();
3928 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
3929 emit_int8(0x30);
3930 emit_operand(src, dst);
3931 }
3932
3933 void Assembler::evpmovwb(Address dst, KRegister mask, XMMRegister src, int vector_len) {
3934 assert(VM_Version::supports_avx512vlbw(), "");
3935 assert(src != xnoreg, "sanity");
3936 InstructionMark im(this);
3937 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3938 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3939 attributes.reset_is_clear_context();
3940 attributes.set_embedded_opmask_register_specifier(mask);
3941 attributes.set_is_evex_instruction();
3942 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
3943 emit_int8(0x30);
3944 emit_operand(src, dst);
3945 }
3946
3947 void Assembler::evpmovdb(Address dst, XMMRegister src, int vector_len) {
3948 assert(VM_Version::supports_evex(), "");
3949 assert(src != xnoreg, "sanity");
3950 InstructionMark im(this);
3951 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3952 attributes.set_address_attributes(/* tuple_type */ EVEX_QVM, /* input_size_in_bits */ EVEX_NObit);
3953 attributes.set_is_evex_instruction();
3954 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
3955 emit_int8(0x31);
3956 emit_operand(src, dst);
3957 }
3958
3959 void Assembler::vpmovzxwd(XMMRegister dst, XMMRegister src, int vector_len) {
3960 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
3961 vector_len == AVX_256bit? VM_Version::supports_avx2() :
3962 vector_len == AVX_512bit? VM_Version::supports_evex() : 0, " ");
3963 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3964 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3965 emit_int8(0x33);
3966 emit_int8((unsigned char)(0xC0 | encode));
3967 }
3968
3969 // generic
3970 void Assembler::pop(Register dst) {
3971 int encode = prefix_and_encode(dst->encoding());
3972 emit_int8(0x58 | encode);
3973 }
3974
3975 void Assembler::popcntl(Register dst, Address src) {
3976 assert(VM_Version::supports_popcnt(), "must support");
3977 InstructionMark im(this);
3978 emit_int8((unsigned char)0xF3);
3979 prefix(src, dst);
3980 emit_int8(0x0F);
3981 emit_int8((unsigned char)0xB8);
3982 emit_operand(dst, src);
3983 }
3984
3985 void Assembler::popcntl(Register dst, Register src) {
3986 assert(VM_Version::supports_popcnt(), "must support");
3987 emit_int8((unsigned char)0xF3);
3988 int encode = prefix_and_encode(dst->encoding(), src->encoding());
3989 emit_int8(0x0F);
3990 emit_int8((unsigned char)0xB8);
3991 emit_int8((unsigned char)(0xC0 | encode));
3992 }
3993
3994 void Assembler::vpopcntd(XMMRegister dst, XMMRegister src, int vector_len) {
3995 assert(VM_Version::supports_vpopcntdq(), "must support vpopcntdq feature");
3996 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3997 attributes.set_is_evex_instruction();
3998 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3999 emit_int8(0x55);
4000 emit_int8((unsigned char)(0xC0 | encode));
4001 }
4002
4003 void Assembler::popf() {
4004 emit_int8((unsigned char)0x9D);
4005 }
4006
4007 #ifndef _LP64 // no 32bit push/pop on amd64
4008 void Assembler::popl(Address dst) {
4009 // NOTE: this will adjust stack by 8byte on 64bits
4010 InstructionMark im(this);
4011 prefix(dst);
4012 emit_int8((unsigned char)0x8F);
4013 emit_operand(rax, dst);
4014 }
4015 #endif
4016
4017 void Assembler::prefetch_prefix(Address src) {
4018 prefix(src);
4019 emit_int8(0x0F);
4020 }
4021
4022 void Assembler::prefetchnta(Address src) {
4023 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
4024 InstructionMark im(this);
4025 prefetch_prefix(src);
4026 emit_int8(0x18);
4027 emit_operand(rax, src); // 0, src
4028 }
4029
4030 void Assembler::prefetchr(Address src) {
4031 assert(VM_Version::supports_3dnow_prefetch(), "must support");
4032 InstructionMark im(this);
4033 prefetch_prefix(src);
4034 emit_int8(0x0D);
4035 emit_operand(rax, src); // 0, src
4036 }
4037
4038 void Assembler::prefetcht0(Address src) {
4039 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
4040 InstructionMark im(this);
4041 prefetch_prefix(src);
4042 emit_int8(0x18);
4043 emit_operand(rcx, src); // 1, src
4044 }
4045
4046 void Assembler::prefetcht1(Address src) {
4047 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
4048 InstructionMark im(this);
4049 prefetch_prefix(src);
4050 emit_int8(0x18);
4051 emit_operand(rdx, src); // 2, src
4052 }
4053
4054 void Assembler::prefetcht2(Address src) {
4055 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
4056 InstructionMark im(this);
4057 prefetch_prefix(src);
4058 emit_int8(0x18);
4059 emit_operand(rbx, src); // 3, src
4060 }
4061
4062 void Assembler::prefetchw(Address src) {
4063 assert(VM_Version::supports_3dnow_prefetch(), "must support");
4064 InstructionMark im(this);
4065 prefetch_prefix(src);
4066 emit_int8(0x0D);
4067 emit_operand(rcx, src); // 1, src
4068 }
4069
4070 void Assembler::prefix(Prefix p) {
4071 emit_int8(p);
4072 }
4073
4074 void Assembler::pshufb(XMMRegister dst, XMMRegister src) {
4075 assert(VM_Version::supports_ssse3(), "");
4076 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4077 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4078 emit_int8(0x00);
4079 emit_int8((unsigned char)(0xC0 | encode));
4080 }
4081
4082 void Assembler::vpshufb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4083 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
4084 vector_len == AVX_256bit? VM_Version::supports_avx2() :
4085 0, "");
4086 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4087 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4088 emit_int8(0x00);
4089 emit_int8((unsigned char)(0xC0 | encode));
4090 }
4091
4092 void Assembler::pshufb(XMMRegister dst, Address src) {
4093 assert(VM_Version::supports_ssse3(), "");
4094 InstructionMark im(this);
4095 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4096 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4097 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4098 emit_int8(0x00);
4099 emit_operand(dst, src);
4100 }
4101
4102 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
4103 assert(isByte(mode), "invalid value");
4104 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4105 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
4106 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4107 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4108 emit_int8(0x70);
4109 emit_int8((unsigned char)(0xC0 | encode));
4110 emit_int8(mode & 0xFF);
4111 }
4112
4113 void Assembler::vpshufd(XMMRegister dst, XMMRegister src, int mode, int vector_len) {
4114 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
4115 vector_len == AVX_256bit? VM_Version::supports_avx2() :
4116 0, "");
4117 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4118 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4119 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4120 emit_int8(0x70);
4121 emit_int8((unsigned char)(0xC0 | encode));
4122 emit_int8(mode & 0xFF);
4123 }
4124
4125 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
4126 assert(isByte(mode), "invalid value");
4127 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4128 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4129 InstructionMark im(this);
4130 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4131 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4132 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4133 emit_int8(0x70);
4134 emit_operand(dst, src);
4135 emit_int8(mode & 0xFF);
4136 }
4137
4138 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
4139 assert(isByte(mode), "invalid value");
4140 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4141 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4142 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4143 emit_int8(0x70);
4144 emit_int8((unsigned char)(0xC0 | encode));
4145 emit_int8(mode & 0xFF);
4146 }
4147
4148 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
4149 assert(isByte(mode), "invalid value");
4150 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4151 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4152 InstructionMark im(this);
4153 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4154 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4155 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4156 emit_int8(0x70);
4157 emit_operand(dst, src);
4158 emit_int8(mode & 0xFF);
4159 }
4160 void Assembler::evshufi64x2(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
4161 assert(VM_Version::supports_evex(), "requires EVEX support");
4162 assert(vector_len == Assembler::AVX_256bit || vector_len == Assembler::AVX_512bit, "");
4163 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4164 attributes.set_is_evex_instruction();
4165 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4166 emit_int8(0x43);
4167 emit_int8((unsigned char)(0xC0 | encode));
4168 emit_int8(imm8 & 0xFF);
4169 }
4170
4171 void Assembler::psrldq(XMMRegister dst, int shift) {
4172 // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
4173 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4174 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4175 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4176 emit_int8(0x73);
4177 emit_int8((unsigned char)(0xC0 | encode));
4178 emit_int8(shift);
4179 }
4180
4181 void Assembler::pslldq(XMMRegister dst, int shift) {
4182 // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
4183 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4184 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4185 // XMM7 is for /7 encoding: 66 0F 73 /7 ib
4186 int encode = simd_prefix_and_encode(xmm7, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4187 emit_int8(0x73);
4188 emit_int8((unsigned char)(0xC0 | encode));
4189 emit_int8(shift);
4190 }
4191
4192 void Assembler::ptest(XMMRegister dst, Address src) {
4193 assert(VM_Version::supports_sse4_1(), "");
4194 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4195 InstructionMark im(this);
4196 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4197 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4198 emit_int8(0x17);
4199 emit_operand(dst, src);
4200 }
4201
4202 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
4203 assert(VM_Version::supports_sse4_1(), "");
4204 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4205 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4206 emit_int8(0x17);
4207 emit_int8((unsigned char)(0xC0 | encode));
4208 }
4209
4210 void Assembler::vptest(XMMRegister dst, Address src) {
4211 assert(VM_Version::supports_avx(), "");
4212 InstructionMark im(this);
4213 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4214 assert(dst != xnoreg, "sanity");
4215 // swap src<->dst for encoding
4216 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4217 emit_int8(0x17);
4218 emit_operand(dst, src);
4219 }
4220
4221 void Assembler::vptest(XMMRegister dst, XMMRegister src) {
4222 assert(VM_Version::supports_avx(), "");
4223 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4224 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4225 emit_int8(0x17);
4226 emit_int8((unsigned char)(0xC0 | encode));
4227 }
4228
4229 void Assembler::punpcklbw(XMMRegister dst, Address src) {
4230 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4231 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4232 InstructionMark im(this);
4233 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ true, /* uses_vl */ true);
4234 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4235 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4236 emit_int8(0x60);
4237 emit_operand(dst, src);
4238 }
4239
4240 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
4241 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4242 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ true, /* uses_vl */ true);
4243 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4244 emit_int8(0x60);
4245 emit_int8((unsigned char)(0xC0 | encode));
4246 }
4247
4248 void Assembler::punpckldq(XMMRegister dst, Address src) {
4249 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4250 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4251 InstructionMark im(this);
4252 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4253 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4254 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4255 emit_int8(0x62);
4256 emit_operand(dst, src);
4257 }
4258
4259 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) {
4260 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4261 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4262 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4263 emit_int8(0x62);
4264 emit_int8((unsigned char)(0xC0 | encode));
4265 }
4266
4267 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) {
4268 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4269 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4270 attributes.set_rex_vex_w_reverted();
4271 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4272 emit_int8(0x6C);
4273 emit_int8((unsigned char)(0xC0 | encode));
4274 }
4275
4276 void Assembler::push(int32_t imm32) {
4277 // in 64bits we push 64bits onto the stack but only
4278 // take a 32bit immediate
4279 emit_int8(0x68);
4280 emit_int32(imm32);
4281 }
4282
4283 void Assembler::push(Register src) {
4284 int encode = prefix_and_encode(src->encoding());
4285
4286 emit_int8(0x50 | encode);
4287 }
4288
4289 void Assembler::pushf() {
4290 emit_int8((unsigned char)0x9C);
4291 }
4292
4293 #ifndef _LP64 // no 32bit push/pop on amd64
4294 void Assembler::pushl(Address src) {
4295 // Note this will push 64bit on 64bit
4296 InstructionMark im(this);
4297 prefix(src);
4298 emit_int8((unsigned char)0xFF);
4299 emit_operand(rsi, src);
4300 }
4301 #endif
4302
4303 void Assembler::rcll(Register dst, int imm8) {
4304 assert(isShiftCount(imm8), "illegal shift count");
4305 int encode = prefix_and_encode(dst->encoding());
4306 if (imm8 == 1) {
4307 emit_int8((unsigned char)0xD1);
4308 emit_int8((unsigned char)(0xD0 | encode));
4309 } else {
4310 emit_int8((unsigned char)0xC1);
4311 emit_int8((unsigned char)0xD0 | encode);
4312 emit_int8(imm8);
4313 }
4314 }
4315
4316 void Assembler::rcpps(XMMRegister dst, XMMRegister src) {
4317 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4318 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4319 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4320 emit_int8(0x53);
4321 emit_int8((unsigned char)(0xC0 | encode));
4322 }
4323
4324 void Assembler::rcpss(XMMRegister dst, XMMRegister src) {
4325 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4326 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4327 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4328 emit_int8(0x53);
4329 emit_int8((unsigned char)(0xC0 | encode));
4330 }
4331
4332 void Assembler::rdtsc() {
4333 emit_int8((unsigned char)0x0F);
4334 emit_int8((unsigned char)0x31);
4335 }
4336
4337 // copies data from [esi] to [edi] using rcx pointer sized words
4338 // generic
4339 void Assembler::rep_mov() {
4340 emit_int8((unsigned char)0xF3);
4341 // MOVSQ
4342 LP64_ONLY(prefix(REX_W));
4343 emit_int8((unsigned char)0xA5);
4344 }
4345
4346 // sets rcx bytes with rax, value at [edi]
4347 void Assembler::rep_stosb() {
4348 emit_int8((unsigned char)0xF3); // REP
4349 LP64_ONLY(prefix(REX_W));
4350 emit_int8((unsigned char)0xAA); // STOSB
4351 }
4352
4353 // sets rcx pointer sized words with rax, value at [edi]
4354 // generic
4355 void Assembler::rep_stos() {
4356 emit_int8((unsigned char)0xF3); // REP
4357 LP64_ONLY(prefix(REX_W)); // LP64:STOSQ, LP32:STOSD
4358 emit_int8((unsigned char)0xAB);
4359 }
4360
4361 // scans rcx pointer sized words at [edi] for occurance of rax,
4362 // generic
4363 void Assembler::repne_scan() { // repne_scan
4364 emit_int8((unsigned char)0xF2);
4365 // SCASQ
4366 LP64_ONLY(prefix(REX_W));
4367 emit_int8((unsigned char)0xAF);
4368 }
4369
4370 #ifdef _LP64
4371 // scans rcx 4 byte words at [edi] for occurance of rax,
4372 // generic
4373 void Assembler::repne_scanl() { // repne_scan
4374 emit_int8((unsigned char)0xF2);
4375 // SCASL
4376 emit_int8((unsigned char)0xAF);
4377 }
4378 #endif
4379
4380 void Assembler::ret(int imm16) {
4381 if (imm16 == 0) {
4382 emit_int8((unsigned char)0xC3);
4383 } else {
4384 emit_int8((unsigned char)0xC2);
4385 emit_int16(imm16);
4386 }
4387 }
4388
4389 void Assembler::sahf() {
4390 #ifdef _LP64
4391 // Not supported in 64bit mode
4392 ShouldNotReachHere();
4393 #endif
4394 emit_int8((unsigned char)0x9E);
4395 }
4396
4397 void Assembler::sarl(Register dst, int imm8) {
4398 int encode = prefix_and_encode(dst->encoding());
4399 assert(isShiftCount(imm8), "illegal shift count");
4400 if (imm8 == 1) {
4401 emit_int8((unsigned char)0xD1);
4402 emit_int8((unsigned char)(0xF8 | encode));
4403 } else {
4404 emit_int8((unsigned char)0xC1);
4405 emit_int8((unsigned char)(0xF8 | encode));
4406 emit_int8(imm8);
4407 }
4408 }
4409
4410 void Assembler::sarl(Register dst) {
4411 int encode = prefix_and_encode(dst->encoding());
4412 emit_int8((unsigned char)0xD3);
4413 emit_int8((unsigned char)(0xF8 | encode));
4414 }
4415
4416 void Assembler::sbbl(Address dst, int32_t imm32) {
4417 InstructionMark im(this);
4418 prefix(dst);
4419 emit_arith_operand(0x81, rbx, dst, imm32);
4420 }
4421
4422 void Assembler::sbbl(Register dst, int32_t imm32) {
4423 prefix(dst);
4424 emit_arith(0x81, 0xD8, dst, imm32);
4425 }
4426
4427
4428 void Assembler::sbbl(Register dst, Address src) {
4429 InstructionMark im(this);
4430 prefix(src, dst);
4431 emit_int8(0x1B);
4432 emit_operand(dst, src);
4433 }
4434
4435 void Assembler::sbbl(Register dst, Register src) {
4436 (void) prefix_and_encode(dst->encoding(), src->encoding());
4437 emit_arith(0x1B, 0xC0, dst, src);
4438 }
4439
4440 void Assembler::setb(Condition cc, Register dst) {
4441 assert(0 <= cc && cc < 16, "illegal cc");
4442 int encode = prefix_and_encode(dst->encoding(), true);
4443 emit_int8(0x0F);
4444 emit_int8((unsigned char)0x90 | cc);
4445 emit_int8((unsigned char)(0xC0 | encode));
4446 }
4447
4448 void Assembler::palignr(XMMRegister dst, XMMRegister src, int imm8) {
4449 assert(VM_Version::supports_ssse3(), "");
4450 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4451 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4452 emit_int8((unsigned char)0x0F);
4453 emit_int8((unsigned char)(0xC0 | encode));
4454 emit_int8(imm8);
4455 }
4456
4457 void Assembler::vpalignr(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
4458 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
4459 vector_len == AVX_256bit? VM_Version::supports_avx2() :
4460 0, "");
4461 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4462 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4463 emit_int8((unsigned char)0x0F);
4464 emit_int8((unsigned char)(0xC0 | encode));
4465 emit_int8(imm8);
4466 }
4467
4468 void Assembler::evalignq(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
4469 assert(VM_Version::supports_evex(), "");
4470 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4471 attributes.set_is_evex_instruction();
4472 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4473 emit_int8(0x3);
4474 emit_int8((unsigned char)(0xC0 | encode));
4475 emit_int8(imm8);
4476 }
4477
4478 void Assembler::pblendw(XMMRegister dst, XMMRegister src, int imm8) {
4479 assert(VM_Version::supports_sse4_1(), "");
4480 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4481 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4482 emit_int8((unsigned char)0x0E);
4483 emit_int8((unsigned char)(0xC0 | encode));
4484 emit_int8(imm8);
4485 }
4486
4487 void Assembler::sha1rnds4(XMMRegister dst, XMMRegister src, int imm8) {
4488 assert(VM_Version::supports_sha(), "");
4489 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3A, /* rex_w */ false);
4490 emit_int8((unsigned char)0xCC);
4491 emit_int8((unsigned char)(0xC0 | encode));
4492 emit_int8((unsigned char)imm8);
4493 }
4494
4495 void Assembler::sha1nexte(XMMRegister dst, XMMRegister src) {
4496 assert(VM_Version::supports_sha(), "");
4497 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4498 emit_int8((unsigned char)0xC8);
4499 emit_int8((unsigned char)(0xC0 | encode));
4500 }
4501
4502 void Assembler::sha1msg1(XMMRegister dst, XMMRegister src) {
4503 assert(VM_Version::supports_sha(), "");
4504 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4505 emit_int8((unsigned char)0xC9);
4506 emit_int8((unsigned char)(0xC0 | encode));
4507 }
4508
4509 void Assembler::sha1msg2(XMMRegister dst, XMMRegister src) {
4510 assert(VM_Version::supports_sha(), "");
4511 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4512 emit_int8((unsigned char)0xCA);
4513 emit_int8((unsigned char)(0xC0 | encode));
4514 }
4515
4516 // xmm0 is implicit additional source to this instruction.
4517 void Assembler::sha256rnds2(XMMRegister dst, XMMRegister src) {
4518 assert(VM_Version::supports_sha(), "");
4519 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4520 emit_int8((unsigned char)0xCB);
4521 emit_int8((unsigned char)(0xC0 | encode));
4522 }
4523
4524 void Assembler::sha256msg1(XMMRegister dst, XMMRegister src) {
4525 assert(VM_Version::supports_sha(), "");
4526 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4527 emit_int8((unsigned char)0xCC);
4528 emit_int8((unsigned char)(0xC0 | encode));
4529 }
4530
4531 void Assembler::sha256msg2(XMMRegister dst, XMMRegister src) {
4532 assert(VM_Version::supports_sha(), "");
4533 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4534 emit_int8((unsigned char)0xCD);
4535 emit_int8((unsigned char)(0xC0 | encode));
4536 }
4537
4538
4539 void Assembler::shll(Register dst, int imm8) {
4540 assert(isShiftCount(imm8), "illegal shift count");
4541 int encode = prefix_and_encode(dst->encoding());
4542 if (imm8 == 1 ) {
4543 emit_int8((unsigned char)0xD1);
4544 emit_int8((unsigned char)(0xE0 | encode));
4545 } else {
4546 emit_int8((unsigned char)0xC1);
4547 emit_int8((unsigned char)(0xE0 | encode));
4548 emit_int8(imm8);
4549 }
4550 }
4551
4552 void Assembler::shll(Register dst) {
4553 int encode = prefix_and_encode(dst->encoding());
4554 emit_int8((unsigned char)0xD3);
4555 emit_int8((unsigned char)(0xE0 | encode));
4556 }
4557
4558 void Assembler::shrl(Register dst, int imm8) {
4559 assert(isShiftCount(imm8), "illegal shift count");
4560 int encode = prefix_and_encode(dst->encoding());
4561 emit_int8((unsigned char)0xC1);
4562 emit_int8((unsigned char)(0xE8 | encode));
4563 emit_int8(imm8);
4564 }
4565
4566 void Assembler::shrl(Register dst) {
4567 int encode = prefix_and_encode(dst->encoding());
4568 emit_int8((unsigned char)0xD3);
4569 emit_int8((unsigned char)(0xE8 | encode));
4570 }
4571
4572 // copies a single word from [esi] to [edi]
4573 void Assembler::smovl() {
4574 emit_int8((unsigned char)0xA5);
4575 }
4576
4577 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
4578 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4579 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4580 attributes.set_rex_vex_w_reverted();
4581 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4582 emit_int8(0x51);
4583 emit_int8((unsigned char)(0xC0 | encode));
4584 }
4585
4586 void Assembler::sqrtsd(XMMRegister dst, Address src) {
4587 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4588 InstructionMark im(this);
4589 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4590 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4591 attributes.set_rex_vex_w_reverted();
4592 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4593 emit_int8(0x51);
4594 emit_operand(dst, src);
4595 }
4596
4597 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
4598 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4599 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4600 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4601 emit_int8(0x51);
4602 emit_int8((unsigned char)(0xC0 | encode));
4603 }
4604
4605 void Assembler::std() {
4606 emit_int8((unsigned char)0xFD);
4607 }
4608
4609 void Assembler::sqrtss(XMMRegister dst, Address src) {
4610 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4611 InstructionMark im(this);
4612 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4613 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4614 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4615 emit_int8(0x51);
4616 emit_operand(dst, src);
4617 }
4618
4619 void Assembler::stmxcsr( Address dst) {
4620 if (UseAVX > 0 ) {
4621 assert(VM_Version::supports_avx(), "");
4622 InstructionMark im(this);
4623 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4624 vex_prefix(dst, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4625 emit_int8((unsigned char)0xAE);
4626 emit_operand(as_Register(3), dst);
4627 } else {
4628 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4629 InstructionMark im(this);
4630 prefix(dst);
4631 emit_int8(0x0F);
4632 emit_int8((unsigned char)0xAE);
4633 emit_operand(as_Register(3), dst);
4634 }
4635 }
4636
4637 void Assembler::subl(Address dst, int32_t imm32) {
4638 InstructionMark im(this);
4639 prefix(dst);
4640 emit_arith_operand(0x81, rbp, dst, imm32);
4641 }
4642
4643 void Assembler::subl(Address dst, Register src) {
4644 InstructionMark im(this);
4645 prefix(dst, src);
4646 emit_int8(0x29);
4647 emit_operand(src, dst);
4648 }
4649
4650 void Assembler::subl(Register dst, int32_t imm32) {
4651 prefix(dst);
4652 emit_arith(0x81, 0xE8, dst, imm32);
4653 }
4654
4655 // Force generation of a 4 byte immediate value even if it fits into 8bit
4656 void Assembler::subl_imm32(Register dst, int32_t imm32) {
4657 prefix(dst);
4658 emit_arith_imm32(0x81, 0xE8, dst, imm32);
4659 }
4660
4661 void Assembler::subl(Register dst, Address src) {
4662 InstructionMark im(this);
4663 prefix(src, dst);
4664 emit_int8(0x2B);
4665 emit_operand(dst, src);
4666 }
4667
4668 void Assembler::subl(Register dst, Register src) {
4669 (void) prefix_and_encode(dst->encoding(), src->encoding());
4670 emit_arith(0x2B, 0xC0, dst, src);
4671 }
4672
4673 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
4674 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4675 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4676 attributes.set_rex_vex_w_reverted();
4677 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4678 emit_int8(0x5C);
4679 emit_int8((unsigned char)(0xC0 | encode));
4680 }
4681
4682 void Assembler::subsd(XMMRegister dst, Address src) {
4683 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4684 InstructionMark im(this);
4685 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4686 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4687 attributes.set_rex_vex_w_reverted();
4688 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4689 emit_int8(0x5C);
4690 emit_operand(dst, src);
4691 }
4692
4693 void Assembler::subss(XMMRegister dst, XMMRegister src) {
4694 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4695 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true , /* uses_vl */ false);
4696 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4697 emit_int8(0x5C);
4698 emit_int8((unsigned char)(0xC0 | encode));
4699 }
4700
4701 void Assembler::subss(XMMRegister dst, Address src) {
4702 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4703 InstructionMark im(this);
4704 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4705 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4706 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4707 emit_int8(0x5C);
4708 emit_operand(dst, src);
4709 }
4710
4711 void Assembler::testb(Register dst, int imm8) {
4712 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
4713 (void) prefix_and_encode(dst->encoding(), true);
4714 emit_arith_b(0xF6, 0xC0, dst, imm8);
4715 }
4716
4717 void Assembler::testb(Address dst, int imm8) {
4718 InstructionMark im(this);
4719 prefix(dst);
4720 emit_int8((unsigned char)0xF6);
4721 emit_operand(rax, dst, 1);
4722 emit_int8(imm8);
4723 }
4724
4725 void Assembler::testl(Register dst, int32_t imm32) {
4726 // not using emit_arith because test
4727 // doesn't support sign-extension of
4728 // 8bit operands
4729 int encode = dst->encoding();
4730 if (encode == 0) {
4731 emit_int8((unsigned char)0xA9);
4732 } else {
4733 encode = prefix_and_encode(encode);
4734 emit_int8((unsigned char)0xF7);
4735 emit_int8((unsigned char)(0xC0 | encode));
4736 }
4737 emit_int32(imm32);
4738 }
4739
4740 void Assembler::testl(Register dst, Register src) {
4741 (void) prefix_and_encode(dst->encoding(), src->encoding());
4742 emit_arith(0x85, 0xC0, dst, src);
4743 }
4744
4745 void Assembler::testl(Register dst, Address src) {
4746 InstructionMark im(this);
4747 prefix(src, dst);
4748 emit_int8((unsigned char)0x85);
4749 emit_operand(dst, src);
4750 }
4751
4752 void Assembler::tzcntl(Register dst, Register src) {
4753 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
4754 emit_int8((unsigned char)0xF3);
4755 int encode = prefix_and_encode(dst->encoding(), src->encoding());
4756 emit_int8(0x0F);
4757 emit_int8((unsigned char)0xBC);
4758 emit_int8((unsigned char)0xC0 | encode);
4759 }
4760
4761 void Assembler::tzcntq(Register dst, Register src) {
4762 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
4763 emit_int8((unsigned char)0xF3);
4764 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4765 emit_int8(0x0F);
4766 emit_int8((unsigned char)0xBC);
4767 emit_int8((unsigned char)(0xC0 | encode));
4768 }
4769
4770 void Assembler::ucomisd(XMMRegister dst, Address src) {
4771 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4772 InstructionMark im(this);
4773 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4774 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4775 attributes.set_rex_vex_w_reverted();
4776 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4777 emit_int8(0x2E);
4778 emit_operand(dst, src);
4779 }
4780
4781 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
4782 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4783 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4784 attributes.set_rex_vex_w_reverted();
4785 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4786 emit_int8(0x2E);
4787 emit_int8((unsigned char)(0xC0 | encode));
4788 }
4789
4790 void Assembler::ucomiss(XMMRegister dst, Address src) {
4791 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4792 InstructionMark im(this);
4793 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4794 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4795 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4796 emit_int8(0x2E);
4797 emit_operand(dst, src);
4798 }
4799
4800 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
4801 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4802 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4803 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4804 emit_int8(0x2E);
4805 emit_int8((unsigned char)(0xC0 | encode));
4806 }
4807
4808 void Assembler::xabort(int8_t imm8) {
4809 emit_int8((unsigned char)0xC6);
4810 emit_int8((unsigned char)0xF8);
4811 emit_int8((unsigned char)(imm8 & 0xFF));
4812 }
4813
4814 void Assembler::xaddb(Address dst, Register src) {
4815 InstructionMark im(this);
4816 prefix(dst, src, true);
4817 emit_int8(0x0F);
4818 emit_int8((unsigned char)0xC0);
4819 emit_operand(src, dst);
4820 }
4821
4822 void Assembler::xaddw(Address dst, Register src) {
4823 InstructionMark im(this);
4824 emit_int8(0x66);
4825 prefix(dst, src);
4826 emit_int8(0x0F);
4827 emit_int8((unsigned char)0xC1);
4828 emit_operand(src, dst);
4829 }
4830
4831 void Assembler::xaddl(Address dst, Register src) {
4832 InstructionMark im(this);
4833 prefix(dst, src);
4834 emit_int8(0x0F);
4835 emit_int8((unsigned char)0xC1);
4836 emit_operand(src, dst);
4837 }
4838
4839 void Assembler::xbegin(Label& abort, relocInfo::relocType rtype) {
4840 InstructionMark im(this);
4841 relocate(rtype);
4842 if (abort.is_bound()) {
4843 address entry = target(abort);
4844 assert(entry != NULL, "abort entry NULL");
4845 intptr_t offset = entry - pc();
4846 emit_int8((unsigned char)0xC7);
4847 emit_int8((unsigned char)0xF8);
4848 emit_int32(offset - 6); // 2 opcode + 4 address
4849 } else {
4850 abort.add_patch_at(code(), locator());
4851 emit_int8((unsigned char)0xC7);
4852 emit_int8((unsigned char)0xF8);
4853 emit_int32(0);
4854 }
4855 }
4856
4857 void Assembler::xchgb(Register dst, Address src) { // xchg
4858 InstructionMark im(this);
4859 prefix(src, dst, true);
4860 emit_int8((unsigned char)0x86);
4861 emit_operand(dst, src);
4862 }
4863
4864 void Assembler::xchgw(Register dst, Address src) { // xchg
4865 InstructionMark im(this);
4866 emit_int8(0x66);
4867 prefix(src, dst);
4868 emit_int8((unsigned char)0x87);
4869 emit_operand(dst, src);
4870 }
4871
4872 void Assembler::xchgl(Register dst, Address src) { // xchg
4873 InstructionMark im(this);
4874 prefix(src, dst);
4875 emit_int8((unsigned char)0x87);
4876 emit_operand(dst, src);
4877 }
4878
4879 void Assembler::xchgl(Register dst, Register src) {
4880 int encode = prefix_and_encode(dst->encoding(), src->encoding());
4881 emit_int8((unsigned char)0x87);
4882 emit_int8((unsigned char)(0xC0 | encode));
4883 }
4884
4885 void Assembler::xend() {
4886 emit_int8((unsigned char)0x0F);
4887 emit_int8((unsigned char)0x01);
4888 emit_int8((unsigned char)0xD5);
4889 }
4890
4891 void Assembler::xgetbv() {
4892 emit_int8(0x0F);
4893 emit_int8(0x01);
4894 emit_int8((unsigned char)0xD0);
4895 }
4896
4897 void Assembler::xorl(Register dst, int32_t imm32) {
4898 prefix(dst);
4899 emit_arith(0x81, 0xF0, dst, imm32);
4900 }
4901
4902 void Assembler::xorl(Register dst, Address src) {
4903 InstructionMark im(this);
4904 prefix(src, dst);
4905 emit_int8(0x33);
4906 emit_operand(dst, src);
4907 }
4908
4909 void Assembler::xorl(Register dst, Register src) {
4910 (void) prefix_and_encode(dst->encoding(), src->encoding());
4911 emit_arith(0x33, 0xC0, dst, src);
4912 }
4913
4914 void Assembler::xorb(Register dst, Address src) {
4915 InstructionMark im(this);
4916 prefix(src, dst);
4917 emit_int8(0x32);
4918 emit_operand(dst, src);
4919 }
4920
4921 // AVX 3-operands scalar float-point arithmetic instructions
4922
4923 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) {
4924 assert(VM_Version::supports_avx(), "");
4925 InstructionMark im(this);
4926 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4927 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4928 attributes.set_rex_vex_w_reverted();
4929 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4930 emit_int8(0x58);
4931 emit_operand(dst, src);
4932 }
4933
4934 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4935 assert(VM_Version::supports_avx(), "");
4936 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4937 attributes.set_rex_vex_w_reverted();
4938 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4939 emit_int8(0x58);
4940 emit_int8((unsigned char)(0xC0 | encode));
4941 }
4942
4943 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) {
4944 assert(VM_Version::supports_avx(), "");
4945 InstructionMark im(this);
4946 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4947 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4948 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4949 emit_int8(0x58);
4950 emit_operand(dst, src);
4951 }
4952
4953 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4954 assert(VM_Version::supports_avx(), "");
4955 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4956 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4957 emit_int8(0x58);
4958 emit_int8((unsigned char)(0xC0 | encode));
4959 }
4960
4961 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) {
4962 assert(VM_Version::supports_avx(), "");
4963 InstructionMark im(this);
4964 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4965 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4966 attributes.set_rex_vex_w_reverted();
4967 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4968 emit_int8(0x5E);
4969 emit_operand(dst, src);
4970 }
4971
4972 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4973 assert(VM_Version::supports_avx(), "");
4974 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4975 attributes.set_rex_vex_w_reverted();
4976 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4977 emit_int8(0x5E);
4978 emit_int8((unsigned char)(0xC0 | encode));
4979 }
4980
4981 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) {
4982 assert(VM_Version::supports_avx(), "");
4983 InstructionMark im(this);
4984 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4985 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4986 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4987 emit_int8(0x5E);
4988 emit_operand(dst, src);
4989 }
4990
4991 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4992 assert(VM_Version::supports_avx(), "");
4993 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4994 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4995 emit_int8(0x5E);
4996 emit_int8((unsigned char)(0xC0 | encode));
4997 }
4998
4999 void Assembler::vfmadd231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
5000 assert(VM_Version::supports_fma(), "");
5001 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5002 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5003 emit_int8((unsigned char)0xB9);
5004 emit_int8((unsigned char)(0xC0 | encode));
5005 }
5006
5007 void Assembler::vfmadd231ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
5008 assert(VM_Version::supports_fma(), "");
5009 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5010 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5011 emit_int8((unsigned char)0xB9);
5012 emit_int8((unsigned char)(0xC0 | encode));
5013 }
5014
5015 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) {
5016 assert(VM_Version::supports_avx(), "");
5017 InstructionMark im(this);
5018 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5019 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
5020 attributes.set_rex_vex_w_reverted();
5021 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5022 emit_int8(0x59);
5023 emit_operand(dst, src);
5024 }
5025
5026 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5027 assert(VM_Version::supports_avx(), "");
5028 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5029 attributes.set_rex_vex_w_reverted();
5030 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5031 emit_int8(0x59);
5032 emit_int8((unsigned char)(0xC0 | encode));
5033 }
5034
5035 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) {
5036 assert(VM_Version::supports_avx(), "");
5037 InstructionMark im(this);
5038 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5039 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
5040 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5041 emit_int8(0x59);
5042 emit_operand(dst, src);
5043 }
5044
5045 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5046 assert(VM_Version::supports_avx(), "");
5047 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5048 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5049 emit_int8(0x59);
5050 emit_int8((unsigned char)(0xC0 | encode));
5051 }
5052
5053 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) {
5054 assert(VM_Version::supports_avx(), "");
5055 InstructionMark im(this);
5056 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5057 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
5058 attributes.set_rex_vex_w_reverted();
5059 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5060 emit_int8(0x5C);
5061 emit_operand(dst, src);
5062 }
5063
5064 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5065 assert(VM_Version::supports_avx(), "");
5066 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5067 attributes.set_rex_vex_w_reverted();
5068 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5069 emit_int8(0x5C);
5070 emit_int8((unsigned char)(0xC0 | encode));
5071 }
5072
5073 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) {
5074 assert(VM_Version::supports_avx(), "");
5075 InstructionMark im(this);
5076 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5077 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
5078 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5079 emit_int8(0x5C);
5080 emit_operand(dst, src);
5081 }
5082
5083 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5084 assert(VM_Version::supports_avx(), "");
5085 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5086 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5087 emit_int8(0x5C);
5088 emit_int8((unsigned char)(0xC0 | encode));
5089 }
5090
5091 //====================VECTOR ARITHMETIC=====================================
5092
5093 // Float-point vector arithmetic
5094
5095 void Assembler::addpd(XMMRegister dst, XMMRegister src) {
5096 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5097 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5098 attributes.set_rex_vex_w_reverted();
5099 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5100 emit_int8(0x58);
5101 emit_int8((unsigned char)(0xC0 | encode));
5102 }
5103
5104 void Assembler::addpd(XMMRegister dst, Address src) {
5105 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5106 InstructionMark im(this);
5107 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5108 attributes.set_rex_vex_w_reverted();
5109 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5110 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5111 emit_int8(0x58);
5112 emit_operand(dst, src);
5113 }
5114
5115
5116 void Assembler::addps(XMMRegister dst, XMMRegister src) {
5117 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5118 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5119 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5120 emit_int8(0x58);
5121 emit_int8((unsigned char)(0xC0 | encode));
5122 }
5123
5124 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5125 assert(VM_Version::supports_avx(), "");
5126 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5127 attributes.set_rex_vex_w_reverted();
5128 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5129 emit_int8(0x58);
5130 emit_int8((unsigned char)(0xC0 | encode));
5131 }
5132
5133 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5134 assert(VM_Version::supports_avx(), "");
5135 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5136 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5137 emit_int8(0x58);
5138 emit_int8((unsigned char)(0xC0 | encode));
5139 }
5140
5141 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5142 assert(VM_Version::supports_avx(), "");
5143 InstructionMark im(this);
5144 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5145 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5146 attributes.set_rex_vex_w_reverted();
5147 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5148 emit_int8(0x58);
5149 emit_operand(dst, src);
5150 }
5151
5152 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5153 assert(VM_Version::supports_avx(), "");
5154 InstructionMark im(this);
5155 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5156 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5157 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5158 emit_int8(0x58);
5159 emit_operand(dst, src);
5160 }
5161
5162 void Assembler::subpd(XMMRegister dst, XMMRegister src) {
5163 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5164 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5165 attributes.set_rex_vex_w_reverted();
5166 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5167 emit_int8(0x5C);
5168 emit_int8((unsigned char)(0xC0 | encode));
5169 }
5170
5171 void Assembler::subps(XMMRegister dst, XMMRegister src) {
5172 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5173 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5174 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5175 emit_int8(0x5C);
5176 emit_int8((unsigned char)(0xC0 | encode));
5177 }
5178
5179 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5180 assert(VM_Version::supports_avx(), "");
5181 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5182 attributes.set_rex_vex_w_reverted();
5183 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5184 emit_int8(0x5C);
5185 emit_int8((unsigned char)(0xC0 | encode));
5186 }
5187
5188 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5189 assert(VM_Version::supports_avx(), "");
5190 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5191 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5192 emit_int8(0x5C);
5193 emit_int8((unsigned char)(0xC0 | encode));
5194 }
5195
5196 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5197 assert(VM_Version::supports_avx(), "");
5198 InstructionMark im(this);
5199 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5200 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5201 attributes.set_rex_vex_w_reverted();
5202 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5203 emit_int8(0x5C);
5204 emit_operand(dst, src);
5205 }
5206
5207 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5208 assert(VM_Version::supports_avx(), "");
5209 InstructionMark im(this);
5210 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5211 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5212 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5213 emit_int8(0x5C);
5214 emit_operand(dst, src);
5215 }
5216
5217 void Assembler::mulpd(XMMRegister dst, XMMRegister src) {
5218 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5219 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5220 attributes.set_rex_vex_w_reverted();
5221 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5222 emit_int8(0x59);
5223 emit_int8((unsigned char)(0xC0 | encode));
5224 }
5225
5226 void Assembler::mulpd(XMMRegister dst, Address src) {
5227 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5228 InstructionMark im(this);
5229 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5230 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5231 attributes.set_rex_vex_w_reverted();
5232 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5233 emit_int8(0x59);
5234 emit_operand(dst, src);
5235 }
5236
5237 void Assembler::mulps(XMMRegister dst, XMMRegister src) {
5238 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5239 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5240 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5241 emit_int8(0x59);
5242 emit_int8((unsigned char)(0xC0 | encode));
5243 }
5244
5245 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5246 assert(VM_Version::supports_avx(), "");
5247 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5248 attributes.set_rex_vex_w_reverted();
5249 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5250 emit_int8(0x59);
5251 emit_int8((unsigned char)(0xC0 | encode));
5252 }
5253
5254 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5255 assert(VM_Version::supports_avx(), "");
5256 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5257 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5258 emit_int8(0x59);
5259 emit_int8((unsigned char)(0xC0 | encode));
5260 }
5261
5262 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5263 assert(VM_Version::supports_avx(), "");
5264 InstructionMark im(this);
5265 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5266 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5267 attributes.set_rex_vex_w_reverted();
5268 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5269 emit_int8(0x59);
5270 emit_operand(dst, src);
5271 }
5272
5273 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5274 assert(VM_Version::supports_avx(), "");
5275 InstructionMark im(this);
5276 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5277 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5278 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5279 emit_int8(0x59);
5280 emit_operand(dst, src);
5281 }
5282
5283 void Assembler::vfmadd231pd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len) {
5284 assert(VM_Version::supports_fma(), "");
5285 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5286 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5287 emit_int8((unsigned char)0xB8);
5288 emit_int8((unsigned char)(0xC0 | encode));
5289 }
5290
5291 void Assembler::vfmadd231ps(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len) {
5292 assert(VM_Version::supports_fma(), "");
5293 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5294 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5295 emit_int8((unsigned char)0xB8);
5296 emit_int8((unsigned char)(0xC0 | encode));
5297 }
5298
5299 void Assembler::vfmadd231pd(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) {
5300 assert(VM_Version::supports_fma(), "");
5301 InstructionMark im(this);
5302 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5303 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5304 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5305 emit_int8((unsigned char)0xB8);
5306 emit_operand(dst, src2);
5307 }
5308
5309 void Assembler::vfmadd231ps(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) {
5310 assert(VM_Version::supports_fma(), "");
5311 InstructionMark im(this);
5312 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5313 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5314 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5315 emit_int8((unsigned char)0xB8);
5316 emit_operand(dst, src2);
5317 }
5318
5319 void Assembler::divpd(XMMRegister dst, XMMRegister src) {
5320 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5321 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5322 attributes.set_rex_vex_w_reverted();
5323 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5324 emit_int8(0x5E);
5325 emit_int8((unsigned char)(0xC0 | encode));
5326 }
5327
5328 void Assembler::divps(XMMRegister dst, XMMRegister src) {
5329 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5330 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5331 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5332 emit_int8(0x5E);
5333 emit_int8((unsigned char)(0xC0 | encode));
5334 }
5335
5336 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5337 assert(VM_Version::supports_avx(), "");
5338 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5339 attributes.set_rex_vex_w_reverted();
5340 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5341 emit_int8(0x5E);
5342 emit_int8((unsigned char)(0xC0 | encode));
5343 }
5344
5345 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5346 assert(VM_Version::supports_avx(), "");
5347 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5348 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5349 emit_int8(0x5E);
5350 emit_int8((unsigned char)(0xC0 | encode));
5351 }
5352
5353 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5354 assert(VM_Version::supports_avx(), "");
5355 InstructionMark im(this);
5356 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5357 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5358 attributes.set_rex_vex_w_reverted();
5359 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5360 emit_int8(0x5E);
5361 emit_operand(dst, src);
5362 }
5363
5364 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5365 assert(VM_Version::supports_avx(), "");
5366 InstructionMark im(this);
5367 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5368 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5369 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5370 emit_int8(0x5E);
5371 emit_operand(dst, src);
5372 }
5373
5374 void Assembler::vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len) {
5375 assert(VM_Version::supports_avx(), "");
5376 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5377 attributes.set_rex_vex_w_reverted();
5378 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5379 emit_int8(0x51);
5380 emit_int8((unsigned char)(0xC0 | encode));
5381 }
5382
5383 void Assembler::vsqrtpd(XMMRegister dst, Address src, int vector_len) {
5384 assert(VM_Version::supports_avx(), "");
5385 InstructionMark im(this);
5386 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5387 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5388 attributes.set_rex_vex_w_reverted();
5389 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5390 emit_int8(0x51);
5391 emit_operand(dst, src);
5392 }
5393
5394 void Assembler::vsqrtps(XMMRegister dst, XMMRegister src, int vector_len) {
5395 assert(VM_Version::supports_avx(), "");
5396 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5397 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5398 emit_int8(0x51);
5399 emit_int8((unsigned char)(0xC0 | encode));
5400 }
5401
5402 void Assembler::vsqrtps(XMMRegister dst, Address src, int vector_len) {
5403 assert(VM_Version::supports_avx(), "");
5404 InstructionMark im(this);
5405 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5406 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5407 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5408 emit_int8(0x51);
5409 emit_operand(dst, src);
5410 }
5411
5412 void Assembler::andpd(XMMRegister dst, XMMRegister src) {
5413 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5414 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5415 attributes.set_rex_vex_w_reverted();
5416 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5417 emit_int8(0x54);
5418 emit_int8((unsigned char)(0xC0 | encode));
5419 }
5420
5421 void Assembler::andps(XMMRegister dst, XMMRegister src) {
5422 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5423 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5424 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5425 emit_int8(0x54);
5426 emit_int8((unsigned char)(0xC0 | encode));
5427 }
5428
5429 void Assembler::andps(XMMRegister dst, Address src) {
5430 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5431 InstructionMark im(this);
5432 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5433 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5434 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5435 emit_int8(0x54);
5436 emit_operand(dst, src);
5437 }
5438
5439 void Assembler::andpd(XMMRegister dst, Address src) {
5440 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5441 InstructionMark im(this);
5442 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5443 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5444 attributes.set_rex_vex_w_reverted();
5445 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5446 emit_int8(0x54);
5447 emit_operand(dst, src);
5448 }
5449
5450 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5451 assert(VM_Version::supports_avx(), "");
5452 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5453 attributes.set_rex_vex_w_reverted();
5454 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5455 emit_int8(0x54);
5456 emit_int8((unsigned char)(0xC0 | encode));
5457 }
5458
5459 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5460 assert(VM_Version::supports_avx(), "");
5461 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5462 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5463 emit_int8(0x54);
5464 emit_int8((unsigned char)(0xC0 | encode));
5465 }
5466
5467 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5468 assert(VM_Version::supports_avx(), "");
5469 InstructionMark im(this);
5470 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5471 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5472 attributes.set_rex_vex_w_reverted();
5473 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5474 emit_int8(0x54);
5475 emit_operand(dst, src);
5476 }
5477
5478 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5479 assert(VM_Version::supports_avx(), "");
5480 InstructionMark im(this);
5481 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5482 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5483 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5484 emit_int8(0x54);
5485 emit_operand(dst, src);
5486 }
5487
5488 void Assembler::unpckhpd(XMMRegister dst, XMMRegister src) {
5489 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5490 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5491 attributes.set_rex_vex_w_reverted();
5492 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5493 emit_int8(0x15);
5494 emit_int8((unsigned char)(0xC0 | encode));
5495 }
5496
5497 void Assembler::unpcklpd(XMMRegister dst, XMMRegister src) {
5498 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5499 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5500 attributes.set_rex_vex_w_reverted();
5501 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5502 emit_int8(0x14);
5503 emit_int8((unsigned char)(0xC0 | encode));
5504 }
5505
5506 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
5507 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5508 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5509 attributes.set_rex_vex_w_reverted();
5510 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5511 emit_int8(0x57);
5512 emit_int8((unsigned char)(0xC0 | encode));
5513 }
5514
5515 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
5516 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5517 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5518 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5519 emit_int8(0x57);
5520 emit_int8((unsigned char)(0xC0 | encode));
5521 }
5522
5523 void Assembler::xorpd(XMMRegister dst, Address src) {
5524 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5525 InstructionMark im(this);
5526 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5527 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5528 attributes.set_rex_vex_w_reverted();
5529 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5530 emit_int8(0x57);
5531 emit_operand(dst, src);
5532 }
5533
5534 void Assembler::xorps(XMMRegister dst, Address src) {
5535 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5536 InstructionMark im(this);
5537 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5538 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5539 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5540 emit_int8(0x57);
5541 emit_operand(dst, src);
5542 }
5543
5544 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5545 assert(VM_Version::supports_avx(), "");
5546 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5547 attributes.set_rex_vex_w_reverted();
5548 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5549 emit_int8(0x57);
5550 emit_int8((unsigned char)(0xC0 | encode));
5551 }
5552
5553 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5554 assert(VM_Version::supports_avx(), "");
5555 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5556 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5557 emit_int8(0x57);
5558 emit_int8((unsigned char)(0xC0 | encode));
5559 }
5560
5561 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5562 assert(VM_Version::supports_avx(), "");
5563 InstructionMark im(this);
5564 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5565 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5566 attributes.set_rex_vex_w_reverted();
5567 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5568 emit_int8(0x57);
5569 emit_operand(dst, src);
5570 }
5571
5572 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5573 assert(VM_Version::supports_avx(), "");
5574 InstructionMark im(this);
5575 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5576 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5577 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5578 emit_int8(0x57);
5579 emit_operand(dst, src);
5580 }
5581
5582 // Integer vector arithmetic
5583 void Assembler::vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5584 assert(VM_Version::supports_avx() && (vector_len == 0) ||
5585 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
5586 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
5587 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5588 emit_int8(0x01);
5589 emit_int8((unsigned char)(0xC0 | encode));
5590 }
5591
5592 void Assembler::vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5593 assert(VM_Version::supports_avx() && (vector_len == 0) ||
5594 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
5595 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
5596 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5597 emit_int8(0x02);
5598 emit_int8((unsigned char)(0xC0 | encode));
5599 }
5600
5601 void Assembler::paddb(XMMRegister dst, XMMRegister src) {
5602 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5603 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5604 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5605 emit_int8((unsigned char)0xFC);
5606 emit_int8((unsigned char)(0xC0 | encode));
5607 }
5608
5609 void Assembler::paddw(XMMRegister dst, XMMRegister src) {
5610 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5611 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5612 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5613 emit_int8((unsigned char)0xFD);
5614 emit_int8((unsigned char)(0xC0 | encode));
5615 }
5616
5617 void Assembler::paddd(XMMRegister dst, XMMRegister src) {
5618 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5619 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5620 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5621 emit_int8((unsigned char)0xFE);
5622 emit_int8((unsigned char)(0xC0 | encode));
5623 }
5624
5625 void Assembler::paddd(XMMRegister dst, Address src) {
5626 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5627 InstructionMark im(this);
5628 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5629 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5630 emit_int8((unsigned char)0xFE);
5631 emit_operand(dst, src);
5632 }
5633
5634 void Assembler::paddq(XMMRegister dst, XMMRegister src) {
5635 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5636 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5637 attributes.set_rex_vex_w_reverted();
5638 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5639 emit_int8((unsigned char)0xD4);
5640 emit_int8((unsigned char)(0xC0 | encode));
5641 }
5642
5643 void Assembler::phaddw(XMMRegister dst, XMMRegister src) {
5644 assert(VM_Version::supports_sse3(), "");
5645 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
5646 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5647 emit_int8(0x01);
5648 emit_int8((unsigned char)(0xC0 | encode));
5649 }
5650
5651 void Assembler::phaddd(XMMRegister dst, XMMRegister src) {
5652 assert(VM_Version::supports_sse3(), "");
5653 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
5654 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5655 emit_int8(0x02);
5656 emit_int8((unsigned char)(0xC0 | encode));
5657 }
5658
5659 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5660 assert(UseAVX > 0, "requires some form of AVX");
5661 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5662 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5663 emit_int8((unsigned char)0xFC);
5664 emit_int8((unsigned char)(0xC0 | encode));
5665 }
5666
5667 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5668 assert(UseAVX > 0, "requires some form of AVX");
5669 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5670 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5671 emit_int8((unsigned char)0xFD);
5672 emit_int8((unsigned char)(0xC0 | encode));
5673 }
5674
5675 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5676 assert(UseAVX > 0, "requires some form of AVX");
5677 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5678 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5679 emit_int8((unsigned char)0xFE);
5680 emit_int8((unsigned char)(0xC0 | encode));
5681 }
5682
5683 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5684 assert(UseAVX > 0, "requires some form of AVX");
5685 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5686 attributes.set_rex_vex_w_reverted();
5687 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5688 emit_int8((unsigned char)0xD4);
5689 emit_int8((unsigned char)(0xC0 | encode));
5690 }
5691
5692 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5693 assert(UseAVX > 0, "requires some form of AVX");
5694 InstructionMark im(this);
5695 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5696 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5697 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5698 emit_int8((unsigned char)0xFC);
5699 emit_operand(dst, src);
5700 }
5701
5702 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5703 assert(UseAVX > 0, "requires some form of AVX");
5704 InstructionMark im(this);
5705 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5706 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5707 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5708 emit_int8((unsigned char)0xFD);
5709 emit_operand(dst, src);
5710 }
5711
5712 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5713 assert(UseAVX > 0, "requires some form of AVX");
5714 InstructionMark im(this);
5715 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5716 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5717 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5718 emit_int8((unsigned char)0xFE);
5719 emit_operand(dst, src);
5720 }
5721
5722 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5723 assert(UseAVX > 0, "requires some form of AVX");
5724 InstructionMark im(this);
5725 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5726 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5727 attributes.set_rex_vex_w_reverted();
5728 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5729 emit_int8((unsigned char)0xD4);
5730 emit_operand(dst, src);
5731 }
5732
5733 void Assembler::psubb(XMMRegister dst, XMMRegister src) {
5734 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5735 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5736 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5737 emit_int8((unsigned char)0xF8);
5738 emit_int8((unsigned char)(0xC0 | encode));
5739 }
5740
5741 void Assembler::psubw(XMMRegister dst, XMMRegister src) {
5742 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5743 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5744 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5745 emit_int8((unsigned char)0xF9);
5746 emit_int8((unsigned char)(0xC0 | encode));
5747 }
5748
5749 void Assembler::psubd(XMMRegister dst, XMMRegister src) {
5750 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5751 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5752 emit_int8((unsigned char)0xFA);
5753 emit_int8((unsigned char)(0xC0 | encode));
5754 }
5755
5756 void Assembler::psubq(XMMRegister dst, XMMRegister src) {
5757 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5758 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5759 attributes.set_rex_vex_w_reverted();
5760 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5761 emit_int8((unsigned char)0xFB);
5762 emit_int8((unsigned char)(0xC0 | encode));
5763 }
5764
5765 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5766 assert(UseAVX > 0, "requires some form of AVX");
5767 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5768 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5769 emit_int8((unsigned char)0xF8);
5770 emit_int8((unsigned char)(0xC0 | encode));
5771 }
5772
5773 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5774 assert(UseAVX > 0, "requires some form of AVX");
5775 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5776 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5777 emit_int8((unsigned char)0xF9);
5778 emit_int8((unsigned char)(0xC0 | encode));
5779 }
5780
5781 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5782 assert(UseAVX > 0, "requires some form of AVX");
5783 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5784 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5785 emit_int8((unsigned char)0xFA);
5786 emit_int8((unsigned char)(0xC0 | encode));
5787 }
5788
5789 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5790 assert(UseAVX > 0, "requires some form of AVX");
5791 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5792 attributes.set_rex_vex_w_reverted();
5793 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5794 emit_int8((unsigned char)0xFB);
5795 emit_int8((unsigned char)(0xC0 | encode));
5796 }
5797
5798 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5799 assert(UseAVX > 0, "requires some form of AVX");
5800 InstructionMark im(this);
5801 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5802 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5803 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5804 emit_int8((unsigned char)0xF8);
5805 emit_operand(dst, src);
5806 }
5807
5808 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5809 assert(UseAVX > 0, "requires some form of AVX");
5810 InstructionMark im(this);
5811 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5812 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5813 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5814 emit_int8((unsigned char)0xF9);
5815 emit_operand(dst, src);
5816 }
5817
5818 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5819 assert(UseAVX > 0, "requires some form of AVX");
5820 InstructionMark im(this);
5821 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5822 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5823 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5824 emit_int8((unsigned char)0xFA);
5825 emit_operand(dst, src);
5826 }
5827
5828 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5829 assert(UseAVX > 0, "requires some form of AVX");
5830 InstructionMark im(this);
5831 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5832 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5833 attributes.set_rex_vex_w_reverted();
5834 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5835 emit_int8((unsigned char)0xFB);
5836 emit_operand(dst, src);
5837 }
5838
5839 void Assembler::pmullw(XMMRegister dst, XMMRegister src) {
5840 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5841 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5842 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5843 emit_int8((unsigned char)0xD5);
5844 emit_int8((unsigned char)(0xC0 | encode));
5845 }
5846
5847 void Assembler::pmulld(XMMRegister dst, XMMRegister src) {
5848 assert(VM_Version::supports_sse4_1(), "");
5849 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5850 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5851 emit_int8(0x40);
5852 emit_int8((unsigned char)(0xC0 | encode));
5853 }
5854
5855 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5856 assert(UseAVX > 0, "requires some form of AVX");
5857 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5858 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5859 emit_int8((unsigned char)0xD5);
5860 emit_int8((unsigned char)(0xC0 | encode));
5861 }
5862
5863 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5864 assert(UseAVX > 0, "requires some form of AVX");
5865 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5866 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5867 emit_int8(0x40);
5868 emit_int8((unsigned char)(0xC0 | encode));
5869 }
5870
5871 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5872 assert(UseAVX > 2, "requires some form of EVEX");
5873 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5874 attributes.set_is_evex_instruction();
5875 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5876 emit_int8(0x40);
5877 emit_int8((unsigned char)(0xC0 | encode));
5878 }
5879
5880 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5881 assert(UseAVX > 0, "requires some form of AVX");
5882 InstructionMark im(this);
5883 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5884 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5885 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5886 emit_int8((unsigned char)0xD5);
5887 emit_operand(dst, src);
5888 }
5889
5890 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5891 assert(UseAVX > 0, "requires some form of AVX");
5892 InstructionMark im(this);
5893 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5894 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5895 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5896 emit_int8(0x40);
5897 emit_operand(dst, src);
5898 }
5899
5900 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5901 assert(UseAVX > 2, "requires some form of EVEX");
5902 InstructionMark im(this);
5903 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5904 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5905 attributes.set_is_evex_instruction();
5906 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5907 emit_int8(0x40);
5908 emit_operand(dst, src);
5909 }
5910
5911 // Shift packed integers left by specified number of bits.
5912 void Assembler::psllw(XMMRegister dst, int shift) {
5913 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5914 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5915 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
5916 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5917 emit_int8(0x71);
5918 emit_int8((unsigned char)(0xC0 | encode));
5919 emit_int8(shift & 0xFF);
5920 }
5921
5922 void Assembler::pslld(XMMRegister dst, int shift) {
5923 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5924 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5925 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
5926 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5927 emit_int8(0x72);
5928 emit_int8((unsigned char)(0xC0 | encode));
5929 emit_int8(shift & 0xFF);
5930 }
5931
5932 void Assembler::psllq(XMMRegister dst, int shift) {
5933 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5934 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5935 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
5936 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5937 emit_int8(0x73);
5938 emit_int8((unsigned char)(0xC0 | encode));
5939 emit_int8(shift & 0xFF);
5940 }
5941
5942 void Assembler::psllw(XMMRegister dst, XMMRegister shift) {
5943 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5944 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5945 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5946 emit_int8((unsigned char)0xF1);
5947 emit_int8((unsigned char)(0xC0 | encode));
5948 }
5949
5950 void Assembler::pslld(XMMRegister dst, XMMRegister shift) {
5951 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5952 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5953 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5954 emit_int8((unsigned char)0xF2);
5955 emit_int8((unsigned char)(0xC0 | encode));
5956 }
5957
5958 void Assembler::psllq(XMMRegister dst, XMMRegister shift) {
5959 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5960 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5961 attributes.set_rex_vex_w_reverted();
5962 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5963 emit_int8((unsigned char)0xF3);
5964 emit_int8((unsigned char)(0xC0 | encode));
5965 }
5966
5967 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5968 assert(UseAVX > 0, "requires some form of AVX");
5969 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5970 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
5971 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5972 emit_int8(0x71);
5973 emit_int8((unsigned char)(0xC0 | encode));
5974 emit_int8(shift & 0xFF);
5975 }
5976
5977 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5978 assert(UseAVX > 0, "requires some form of AVX");
5979 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5980 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5981 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
5982 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5983 emit_int8(0x72);
5984 emit_int8((unsigned char)(0xC0 | encode));
5985 emit_int8(shift & 0xFF);
5986 }
5987
5988 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5989 assert(UseAVX > 0, "requires some form of AVX");
5990 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5991 attributes.set_rex_vex_w_reverted();
5992 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
5993 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5994 emit_int8(0x73);
5995 emit_int8((unsigned char)(0xC0 | encode));
5996 emit_int8(shift & 0xFF);
5997 }
5998
5999 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6000 assert(UseAVX > 0, "requires some form of AVX");
6001 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6002 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6003 emit_int8((unsigned char)0xF1);
6004 emit_int8((unsigned char)(0xC0 | encode));
6005 }
6006
6007 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6008 assert(UseAVX > 0, "requires some form of AVX");
6009 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6010 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6011 emit_int8((unsigned char)0xF2);
6012 emit_int8((unsigned char)(0xC0 | encode));
6013 }
6014
6015 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6016 assert(UseAVX > 0, "requires some form of AVX");
6017 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6018 attributes.set_rex_vex_w_reverted();
6019 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6020 emit_int8((unsigned char)0xF3);
6021 emit_int8((unsigned char)(0xC0 | encode));
6022 }
6023
6024 // Shift packed integers logically right by specified number of bits.
6025 void Assembler::psrlw(XMMRegister dst, int shift) {
6026 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6027 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6028 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
6029 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6030 emit_int8(0x71);
6031 emit_int8((unsigned char)(0xC0 | encode));
6032 emit_int8(shift & 0xFF);
6033 }
6034
6035 void Assembler::psrld(XMMRegister dst, int shift) {
6036 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6037 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6038 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
6039 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6040 emit_int8(0x72);
6041 emit_int8((unsigned char)(0xC0 | encode));
6042 emit_int8(shift & 0xFF);
6043 }
6044
6045 void Assembler::psrlq(XMMRegister dst, int shift) {
6046 // Do not confuse it with psrldq SSE2 instruction which
6047 // shifts 128 bit value in xmm register by number of bytes.
6048 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6049 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6050 attributes.set_rex_vex_w_reverted();
6051 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
6052 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6053 emit_int8(0x73);
6054 emit_int8((unsigned char)(0xC0 | encode));
6055 emit_int8(shift & 0xFF);
6056 }
6057
6058 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) {
6059 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6060 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6061 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6062 emit_int8((unsigned char)0xD1);
6063 emit_int8((unsigned char)(0xC0 | encode));
6064 }
6065
6066 void Assembler::psrld(XMMRegister dst, XMMRegister shift) {
6067 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6068 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6069 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6070 emit_int8((unsigned char)0xD2);
6071 emit_int8((unsigned char)(0xC0 | encode));
6072 }
6073
6074 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) {
6075 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6076 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6077 attributes.set_rex_vex_w_reverted();
6078 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6079 emit_int8((unsigned char)0xD3);
6080 emit_int8((unsigned char)(0xC0 | encode));
6081 }
6082
6083 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6084 assert(UseAVX > 0, "requires some form of AVX");
6085 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6086 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
6087 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6088 emit_int8(0x71);
6089 emit_int8((unsigned char)(0xC0 | encode));
6090 emit_int8(shift & 0xFF);
6091 }
6092
6093 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6094 assert(UseAVX > 0, "requires some form of AVX");
6095 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6096 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
6097 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6098 emit_int8(0x72);
6099 emit_int8((unsigned char)(0xC0 | encode));
6100 emit_int8(shift & 0xFF);
6101 }
6102
6103 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6104 assert(UseAVX > 0, "requires some form of AVX");
6105 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6106 attributes.set_rex_vex_w_reverted();
6107 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
6108 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6109 emit_int8(0x73);
6110 emit_int8((unsigned char)(0xC0 | encode));
6111 emit_int8(shift & 0xFF);
6112 }
6113
6114 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6115 assert(UseAVX > 0, "requires some form of AVX");
6116 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6117 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6118 emit_int8((unsigned char)0xD1);
6119 emit_int8((unsigned char)(0xC0 | encode));
6120 }
6121
6122 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6123 assert(UseAVX > 0, "requires some form of AVX");
6124 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6125 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6126 emit_int8((unsigned char)0xD2);
6127 emit_int8((unsigned char)(0xC0 | encode));
6128 }
6129
6130 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6131 assert(UseAVX > 0, "requires some form of AVX");
6132 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6133 attributes.set_rex_vex_w_reverted();
6134 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6135 emit_int8((unsigned char)0xD3);
6136 emit_int8((unsigned char)(0xC0 | encode));
6137 }
6138
6139 void Assembler::evpsrlvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6140 assert(VM_Version::supports_avx512bw(), "");
6141 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6142 attributes.set_is_evex_instruction();
6143 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6144 emit_int8(0x10);
6145 emit_int8((unsigned char)(0xC0 | encode));
6146 }
6147
6148 void Assembler::evpsllvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6149 assert(VM_Version::supports_avx512bw(), "");
6150 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6151 attributes.set_is_evex_instruction();
6152 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6153 emit_int8(0x12);
6154 emit_int8((unsigned char)(0xC0 | encode));
6155 }
6156
6157 // Shift packed integers arithmetically right by specified number of bits.
6158 void Assembler::psraw(XMMRegister dst, int shift) {
6159 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6160 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6161 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
6162 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6163 emit_int8(0x71);
6164 emit_int8((unsigned char)(0xC0 | encode));
6165 emit_int8(shift & 0xFF);
6166 }
6167
6168 void Assembler::psrad(XMMRegister dst, int shift) {
6169 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6170 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6171 // XMM4 is for /4 encoding: 66 0F 72 /4 ib
6172 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6173 emit_int8(0x72);
6174 emit_int8((unsigned char)(0xC0 | encode));
6175 emit_int8(shift & 0xFF);
6176 }
6177
6178 void Assembler::psraw(XMMRegister dst, XMMRegister shift) {
6179 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6180 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6181 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6182 emit_int8((unsigned char)0xE1);
6183 emit_int8((unsigned char)(0xC0 | encode));
6184 }
6185
6186 void Assembler::psrad(XMMRegister dst, XMMRegister shift) {
6187 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6188 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6189 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6190 emit_int8((unsigned char)0xE2);
6191 emit_int8((unsigned char)(0xC0 | encode));
6192 }
6193
6194 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6195 assert(UseAVX > 0, "requires some form of AVX");
6196 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6197 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
6198 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6199 emit_int8(0x71);
6200 emit_int8((unsigned char)(0xC0 | encode));
6201 emit_int8(shift & 0xFF);
6202 }
6203
6204 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6205 assert(UseAVX > 0, "requires some form of AVX");
6206 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6207 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
6208 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6209 emit_int8(0x72);
6210 emit_int8((unsigned char)(0xC0 | encode));
6211 emit_int8(shift & 0xFF);
6212 }
6213
6214 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6215 assert(UseAVX > 0, "requires some form of AVX");
6216 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6217 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6218 emit_int8((unsigned char)0xE1);
6219 emit_int8((unsigned char)(0xC0 | encode));
6220 }
6221
6222 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6223 assert(UseAVX > 0, "requires some form of AVX");
6224 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6225 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6226 emit_int8((unsigned char)0xE2);
6227 emit_int8((unsigned char)(0xC0 | encode));
6228 }
6229
6230
6231 // logical operations packed integers
6232 void Assembler::pand(XMMRegister dst, XMMRegister src) {
6233 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6234 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6235 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6236 emit_int8((unsigned char)0xDB);
6237 emit_int8((unsigned char)(0xC0 | encode));
6238 }
6239
6240 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6241 assert(UseAVX > 0, "requires some form of AVX");
6242 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6243 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6244 emit_int8((unsigned char)0xDB);
6245 emit_int8((unsigned char)(0xC0 | encode));
6246 }
6247
6248 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6249 assert(UseAVX > 0, "requires some form of AVX");
6250 InstructionMark im(this);
6251 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6252 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
6253 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6254 emit_int8((unsigned char)0xDB);
6255 emit_operand(dst, src);
6256 }
6257
6258 void Assembler::vpandq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6259 assert(VM_Version::supports_evex(), "");
6260 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6261 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6262 emit_int8((unsigned char)0xDB);
6263 emit_int8((unsigned char)(0xC0 | encode));
6264 }
6265
6266
6267 void Assembler::pandn(XMMRegister dst, XMMRegister src) {
6268 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6269 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6270 attributes.set_rex_vex_w_reverted();
6271 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6272 emit_int8((unsigned char)0xDF);
6273 emit_int8((unsigned char)(0xC0 | encode));
6274 }
6275
6276 void Assembler::vpandn(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6277 assert(UseAVX > 0, "requires some form of AVX");
6278 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6279 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6280 emit_int8((unsigned char)0xDF);
6281 emit_int8((unsigned char)(0xC0 | encode));
6282 }
6283
6284
6285 void Assembler::por(XMMRegister dst, XMMRegister src) {
6286 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6287 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6288 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6289 emit_int8((unsigned char)0xEB);
6290 emit_int8((unsigned char)(0xC0 | encode));
6291 }
6292
6293 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6294 assert(UseAVX > 0, "requires some form of AVX");
6295 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6296 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6297 emit_int8((unsigned char)0xEB);
6298 emit_int8((unsigned char)(0xC0 | encode));
6299 }
6300
6301 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6302 assert(UseAVX > 0, "requires some form of AVX");
6303 InstructionMark im(this);
6304 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6305 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
6306 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6307 emit_int8((unsigned char)0xEB);
6308 emit_operand(dst, src);
6309 }
6310
6311 void Assembler::vporq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6312 assert(VM_Version::supports_evex(), "");
6313 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6314 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6315 emit_int8((unsigned char)0xEB);
6316 emit_int8((unsigned char)(0xC0 | encode));
6317 }
6318
6319
6320 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
6321 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6322 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6323 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6324 emit_int8((unsigned char)0xEF);
6325 emit_int8((unsigned char)(0xC0 | encode));
6326 }
6327
6328 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6329 assert(UseAVX > 0, "requires some form of AVX");
6330 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6331 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6332 emit_int8((unsigned char)0xEF);
6333 emit_int8((unsigned char)(0xC0 | encode));
6334 }
6335
6336 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6337 assert(UseAVX > 0, "requires some form of AVX");
6338 InstructionMark im(this);
6339 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6340 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
6341 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6342 emit_int8((unsigned char)0xEF);
6343 emit_operand(dst, src);
6344 }
6345
6346 void Assembler::evpxorq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6347 assert(VM_Version::supports_evex(), "requires EVEX support");
6348 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6349 attributes.set_is_evex_instruction();
6350 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6351 emit_int8((unsigned char)0xEF);
6352 emit_int8((unsigned char)(0xC0 | encode));
6353 }
6354
6355 void Assembler::evpxorq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6356 assert(VM_Version::supports_evex(), "requires EVEX support");
6357 assert(dst != xnoreg, "sanity");
6358 InstructionMark im(this);
6359 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6360 attributes.set_is_evex_instruction();
6361 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
6362 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6363 emit_int8((unsigned char)0xEF);
6364 emit_operand(dst, src);
6365 }
6366
6367
6368 // vinserti forms
6369
6370 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6371 assert(VM_Version::supports_avx2(), "");
6372 assert(imm8 <= 0x01, "imm8: %u", imm8);
6373 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6374 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6375 emit_int8(0x38);
6376 emit_int8((unsigned char)(0xC0 | encode));
6377 // 0x00 - insert into lower 128 bits
6378 // 0x01 - insert into upper 128 bits
6379 emit_int8(imm8 & 0x01);
6380 }
6381
6382 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6383 assert(VM_Version::supports_avx2(), "");
6384 assert(dst != xnoreg, "sanity");
6385 assert(imm8 <= 0x01, "imm8: %u", imm8);
6386 InstructionMark im(this);
6387 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6388 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6389 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6390 emit_int8(0x38);
6391 emit_operand(dst, src);
6392 // 0x00 - insert into lower 128 bits
6393 // 0x01 - insert into upper 128 bits
6394 emit_int8(imm8 & 0x01);
6395 }
6396
6397 void Assembler::vinserti32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6398 assert(VM_Version::supports_evex(), "");
6399 assert(imm8 <= 0x03, "imm8: %u", imm8);
6400 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6401 attributes.set_is_evex_instruction();
6402 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6403 emit_int8(0x38);
6404 emit_int8((unsigned char)(0xC0 | encode));
6405 // 0x00 - insert into q0 128 bits (0..127)
6406 // 0x01 - insert into q1 128 bits (128..255)
6407 // 0x02 - insert into q2 128 bits (256..383)
6408 // 0x03 - insert into q3 128 bits (384..511)
6409 emit_int8(imm8 & 0x03);
6410 }
6411
6412 void Assembler::vinserti32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6413 assert(VM_Version::supports_avx(), "");
6414 assert(dst != xnoreg, "sanity");
6415 assert(imm8 <= 0x03, "imm8: %u", imm8);
6416 InstructionMark im(this);
6417 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6418 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6419 attributes.set_is_evex_instruction();
6420 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6421 emit_int8(0x18);
6422 emit_operand(dst, src);
6423 // 0x00 - insert into q0 128 bits (0..127)
6424 // 0x01 - insert into q1 128 bits (128..255)
6425 // 0x02 - insert into q2 128 bits (256..383)
6426 // 0x03 - insert into q3 128 bits (384..511)
6427 emit_int8(imm8 & 0x03);
6428 }
6429
6430 void Assembler::vinserti64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6431 assert(VM_Version::supports_evex(), "");
6432 assert(imm8 <= 0x01, "imm8: %u", imm8);
6433 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6434 attributes.set_is_evex_instruction();
6435 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6436 emit_int8(0x3A);
6437 emit_int8((unsigned char)(0xC0 | encode));
6438 // 0x00 - insert into lower 256 bits
6439 // 0x01 - insert into upper 256 bits
6440 emit_int8(imm8 & 0x01);
6441 }
6442
6443
6444 // vinsertf forms
6445
6446 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6447 assert(VM_Version::supports_avx(), "");
6448 assert(imm8 <= 0x01, "imm8: %u", imm8);
6449 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6450 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6451 emit_int8(0x18);
6452 emit_int8((unsigned char)(0xC0 | encode));
6453 // 0x00 - insert into lower 128 bits
6454 // 0x01 - insert into upper 128 bits
6455 emit_int8(imm8 & 0x01);
6456 }
6457
6458 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6459 assert(VM_Version::supports_avx(), "");
6460 assert(dst != xnoreg, "sanity");
6461 assert(imm8 <= 0x01, "imm8: %u", imm8);
6462 InstructionMark im(this);
6463 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6464 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6465 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6466 emit_int8(0x18);
6467 emit_operand(dst, src);
6468 // 0x00 - insert into lower 128 bits
6469 // 0x01 - insert into upper 128 bits
6470 emit_int8(imm8 & 0x01);
6471 }
6472
6473 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6474 assert(VM_Version::supports_avx2(), "");
6475 assert(imm8 <= 0x03, "imm8: %u", imm8);
6476 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6477 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6478 emit_int8(0x18);
6479 emit_int8((unsigned char)(0xC0 | encode));
6480 // 0x00 - insert into q0 128 bits (0..127)
6481 // 0x01 - insert into q1 128 bits (128..255)
6482 // 0x02 - insert into q0 128 bits (256..383)
6483 // 0x03 - insert into q1 128 bits (384..512)
6484 emit_int8(imm8 & 0x03);
6485 }
6486
6487 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6488 assert(VM_Version::supports_avx(), "");
6489 assert(dst != xnoreg, "sanity");
6490 assert(imm8 <= 0x03, "imm8: %u", imm8);
6491 InstructionMark im(this);
6492 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6493 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6494 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6495 emit_int8(0x18);
6496 emit_operand(dst, src);
6497 // 0x00 - insert into q0 128 bits (0..127)
6498 // 0x01 - insert into q1 128 bits (128..255)
6499 // 0x02 - insert into q0 128 bits (256..383)
6500 // 0x03 - insert into q1 128 bits (384..512)
6501 emit_int8(imm8 & 0x03);
6502 }
6503
6504 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6505 assert(VM_Version::supports_evex(), "");
6506 assert(imm8 <= 0x01, "imm8: %u", imm8);
6507 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6508 attributes.set_is_evex_instruction();
6509 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6510 emit_int8(0x1A);
6511 emit_int8((unsigned char)(0xC0 | encode));
6512 // 0x00 - insert into lower 256 bits
6513 // 0x01 - insert into upper 256 bits
6514 emit_int8(imm8 & 0x01);
6515 }
6516
6517 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6518 assert(VM_Version::supports_evex(), "");
6519 assert(dst != xnoreg, "sanity");
6520 assert(imm8 <= 0x01, "imm8: %u", imm8);
6521 InstructionMark im(this);
6522 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6523 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_64bit);
6524 attributes.set_is_evex_instruction();
6525 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6526 emit_int8(0x1A);
6527 emit_operand(dst, src);
6528 // 0x00 - insert into lower 256 bits
6529 // 0x01 - insert into upper 256 bits
6530 emit_int8(imm8 & 0x01);
6531 }
6532
6533
6534 // vextracti forms
6535
6536 void Assembler::vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6537 assert(VM_Version::supports_avx2(), "");
6538 assert(imm8 <= 0x01, "imm8: %u", imm8);
6539 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6540 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6541 emit_int8(0x39);
6542 emit_int8((unsigned char)(0xC0 | encode));
6543 // 0x00 - extract from lower 128 bits
6544 // 0x01 - extract from upper 128 bits
6545 emit_int8(imm8 & 0x01);
6546 }
6547
6548 void Assembler::vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
6549 assert(VM_Version::supports_avx2(), "");
6550 assert(src != xnoreg, "sanity");
6551 assert(imm8 <= 0x01, "imm8: %u", imm8);
6552 InstructionMark im(this);
6553 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6554 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6555 attributes.reset_is_clear_context();
6556 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6557 emit_int8(0x39);
6558 emit_operand(src, dst);
6559 // 0x00 - extract from lower 128 bits
6560 // 0x01 - extract from upper 128 bits
6561 emit_int8(imm8 & 0x01);
6562 }
6563
6564 void Assembler::vextracti32x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6565 assert(VM_Version::supports_evex(), "");
6566 assert(imm8 <= 0x03, "imm8: %u", imm8);
6567 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6568 attributes.set_is_evex_instruction();
6569 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6570 emit_int8(0x39);
6571 emit_int8((unsigned char)(0xC0 | encode));
6572 // 0x00 - extract from bits 127:0
6573 // 0x01 - extract from bits 255:128
6574 // 0x02 - extract from bits 383:256
6575 // 0x03 - extract from bits 511:384
6576 emit_int8(imm8 & 0x03);
6577 }
6578
6579 void Assembler::vextracti32x4(Address dst, XMMRegister src, uint8_t imm8) {
6580 assert(VM_Version::supports_evex(), "");
6581 assert(src != xnoreg, "sanity");
6582 assert(imm8 <= 0x03, "imm8: %u", imm8);
6583 InstructionMark im(this);
6584 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6585 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6586 attributes.reset_is_clear_context();
6587 attributes.set_is_evex_instruction();
6588 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6589 emit_int8(0x39);
6590 emit_operand(src, dst);
6591 // 0x00 - extract from bits 127:0
6592 // 0x01 - extract from bits 255:128
6593 // 0x02 - extract from bits 383:256
6594 // 0x03 - extract from bits 511:384
6595 emit_int8(imm8 & 0x03);
6596 }
6597
6598 void Assembler::vextracti64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6599 assert(VM_Version::supports_avx512dq(), "");
6600 assert(imm8 <= 0x03, "imm8: %u", imm8);
6601 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6602 attributes.set_is_evex_instruction();
6603 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6604 emit_int8(0x39);
6605 emit_int8((unsigned char)(0xC0 | encode));
6606 // 0x00 - extract from bits 127:0
6607 // 0x01 - extract from bits 255:128
6608 // 0x02 - extract from bits 383:256
6609 // 0x03 - extract from bits 511:384
6610 emit_int8(imm8 & 0x03);
6611 }
6612
6613 void Assembler::vextracti64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6614 assert(VM_Version::supports_evex(), "");
6615 assert(imm8 <= 0x01, "imm8: %u", imm8);
6616 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6617 attributes.set_is_evex_instruction();
6618 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6619 emit_int8(0x3B);
6620 emit_int8((unsigned char)(0xC0 | encode));
6621 // 0x00 - extract from lower 256 bits
6622 // 0x01 - extract from upper 256 bits
6623 emit_int8(imm8 & 0x01);
6624 }
6625
6626 void Assembler::vextracti64x4(Address dst, XMMRegister src, uint8_t imm8) {
6627 assert(VM_Version::supports_evex(), "");
6628 assert(src != xnoreg, "sanity");
6629 assert(imm8 <= 0x01, "imm8: %u", imm8);
6630 InstructionMark im(this);
6631 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6632 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_64bit);
6633 attributes.reset_is_clear_context();
6634 attributes.set_is_evex_instruction();
6635 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6636 emit_int8(0x38);
6637 emit_operand(src, dst);
6638 // 0x00 - extract from lower 256 bits
6639 // 0x01 - extract from upper 256 bits
6640 emit_int8(imm8 & 0x01);
6641 }
6642 // vextractf forms
6643
6644 void Assembler::vextractf128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6645 assert(VM_Version::supports_avx(), "");
6646 assert(imm8 <= 0x01, "imm8: %u", imm8);
6647 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6648 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6649 emit_int8(0x19);
6650 emit_int8((unsigned char)(0xC0 | encode));
6651 // 0x00 - extract from lower 128 bits
6652 // 0x01 - extract from upper 128 bits
6653 emit_int8(imm8 & 0x01);
6654 }
6655
6656 void Assembler::vextractf128(Address dst, XMMRegister src, uint8_t imm8) {
6657 assert(VM_Version::supports_avx(), "");
6658 assert(src != xnoreg, "sanity");
6659 assert(imm8 <= 0x01, "imm8: %u", imm8);
6660 InstructionMark im(this);
6661 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6662 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6663 attributes.reset_is_clear_context();
6664 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6665 emit_int8(0x19);
6666 emit_operand(src, dst);
6667 // 0x00 - extract from lower 128 bits
6668 // 0x01 - extract from upper 128 bits
6669 emit_int8(imm8 & 0x01);
6670 }
6671
6672 void Assembler::vextractf32x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6673 assert(VM_Version::supports_evex(), "");
6674 assert(imm8 <= 0x03, "imm8: %u", imm8);
6675 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6676 attributes.set_is_evex_instruction();
6677 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6678 emit_int8(0x19);
6679 emit_int8((unsigned char)(0xC0 | encode));
6680 // 0x00 - extract from bits 127:0
6681 // 0x01 - extract from bits 255:128
6682 // 0x02 - extract from bits 383:256
6683 // 0x03 - extract from bits 511:384
6684 emit_int8(imm8 & 0x03);
6685 }
6686
6687 void Assembler::vextractf32x4(Address dst, XMMRegister src, uint8_t imm8) {
6688 assert(VM_Version::supports_evex(), "");
6689 assert(src != xnoreg, "sanity");
6690 assert(imm8 <= 0x03, "imm8: %u", imm8);
6691 InstructionMark im(this);
6692 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6693 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6694 attributes.reset_is_clear_context();
6695 attributes.set_is_evex_instruction();
6696 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6697 emit_int8(0x19);
6698 emit_operand(src, dst);
6699 // 0x00 - extract from bits 127:0
6700 // 0x01 - extract from bits 255:128
6701 // 0x02 - extract from bits 383:256
6702 // 0x03 - extract from bits 511:384
6703 emit_int8(imm8 & 0x03);
6704 }
6705
6706 void Assembler::vextractf64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6707 assert(VM_Version::supports_avx512dq(), "");
6708 assert(imm8 <= 0x03, "imm8: %u", imm8);
6709 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6710 attributes.set_is_evex_instruction();
6711 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6712 emit_int8(0x19);
6713 emit_int8((unsigned char)(0xC0 | encode));
6714 // 0x00 - extract from bits 127:0
6715 // 0x01 - extract from bits 255:128
6716 // 0x02 - extract from bits 383:256
6717 // 0x03 - extract from bits 511:384
6718 emit_int8(imm8 & 0x03);
6719 }
6720
6721 void Assembler::vextractf64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6722 assert(VM_Version::supports_evex(), "");
6723 assert(imm8 <= 0x01, "imm8: %u", imm8);
6724 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6725 attributes.set_is_evex_instruction();
6726 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6727 emit_int8(0x1B);
6728 emit_int8((unsigned char)(0xC0 | encode));
6729 // 0x00 - extract from lower 256 bits
6730 // 0x01 - extract from upper 256 bits
6731 emit_int8(imm8 & 0x01);
6732 }
6733
6734 void Assembler::vextractf64x4(Address dst, XMMRegister src, uint8_t imm8) {
6735 assert(VM_Version::supports_evex(), "");
6736 assert(src != xnoreg, "sanity");
6737 assert(imm8 <= 0x01, "imm8: %u", imm8);
6738 InstructionMark im(this);
6739 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6740 attributes.set_address_attributes(/* tuple_type */ EVEX_T4,/* input_size_in_bits */ EVEX_64bit);
6741 attributes.reset_is_clear_context();
6742 attributes.set_is_evex_instruction();
6743 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6744 emit_int8(0x1B);
6745 emit_operand(src, dst);
6746 // 0x00 - extract from lower 256 bits
6747 // 0x01 - extract from upper 256 bits
6748 emit_int8(imm8 & 0x01);
6749 }
6750
6751 // duplicate 1-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
6752 void Assembler::vpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len) {
6753 assert(VM_Version::supports_avx2(), "");
6754 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6755 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6756 emit_int8(0x78);
6757 emit_int8((unsigned char)(0xC0 | encode));
6758 }
6759
6760 void Assembler::vpbroadcastb(XMMRegister dst, Address src, int vector_len) {
6761 assert(VM_Version::supports_avx2(), "");
6762 assert(dst != xnoreg, "sanity");
6763 InstructionMark im(this);
6764 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6765 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
6766 // swap src<->dst for encoding
6767 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6768 emit_int8(0x78);
6769 emit_operand(dst, src);
6770 }
6771
6772 // duplicate 2-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
6773 void Assembler::vpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len) {
6774 assert(VM_Version::supports_avx2(), "");
6775 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6776 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6777 emit_int8(0x79);
6778 emit_int8((unsigned char)(0xC0 | encode));
6779 }
6780
6781 void Assembler::vpbroadcastw(XMMRegister dst, Address src, int vector_len) {
6782 assert(VM_Version::supports_avx2(), "");
6783 assert(dst != xnoreg, "sanity");
6784 InstructionMark im(this);
6785 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6786 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
6787 // swap src<->dst for encoding
6788 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6789 emit_int8(0x79);
6790 emit_operand(dst, src);
6791 }
6792
6793 // xmm/mem sourced byte/word/dword/qword replicate
6794
6795 // duplicate 4-byte integer data from src into programmed locations in dest : requires AVX512VL
6796 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len) {
6797 assert(UseAVX >= 2, "");
6798 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6799 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6800 emit_int8(0x58);
6801 emit_int8((unsigned char)(0xC0 | encode));
6802 }
6803
6804 void Assembler::vpbroadcastd(XMMRegister dst, Address src, int vector_len) {
6805 assert(VM_Version::supports_avx2(), "");
6806 assert(dst != xnoreg, "sanity");
6807 InstructionMark im(this);
6808 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6809 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
6810 // swap src<->dst for encoding
6811 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6812 emit_int8(0x58);
6813 emit_operand(dst, src);
6814 }
6815
6816 // duplicate 8-byte integer data from src into programmed locations in dest : requires AVX512VL
6817 void Assembler::vpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len) {
6818 assert(VM_Version::supports_avx2(), "");
6819 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6820 attributes.set_rex_vex_w_reverted();
6821 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6822 emit_int8(0x59);
6823 emit_int8((unsigned char)(0xC0 | encode));
6824 }
6825
6826 void Assembler::vpbroadcastq(XMMRegister dst, Address src, int vector_len) {
6827 assert(VM_Version::supports_avx2(), "");
6828 assert(dst != xnoreg, "sanity");
6829 InstructionMark im(this);
6830 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6831 attributes.set_rex_vex_w_reverted();
6832 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6833 // swap src<->dst for encoding
6834 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6835 emit_int8(0x59);
6836 emit_operand(dst, src);
6837 }
6838 void Assembler::evbroadcasti64x2(XMMRegister dst, XMMRegister src, int vector_len) {
6839 assert(vector_len != Assembler::AVX_128bit, "");
6840 assert(VM_Version::supports_avx512dq(), "");
6841 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6842 attributes.set_rex_vex_w_reverted();
6843 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6844 emit_int8(0x5A);
6845 emit_int8((unsigned char)(0xC0 | encode));
6846 }
6847
6848 void Assembler::evbroadcasti64x2(XMMRegister dst, Address src, int vector_len) {
6849 assert(vector_len != Assembler::AVX_128bit, "");
6850 assert(VM_Version::supports_avx512dq(), "");
6851 assert(dst != xnoreg, "sanity");
6852 InstructionMark im(this);
6853 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6854 attributes.set_rex_vex_w_reverted();
6855 attributes.set_address_attributes(/* tuple_type */ EVEX_T2, /* input_size_in_bits */ EVEX_64bit);
6856 // swap src<->dst for encoding
6857 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6858 emit_int8(0x5A);
6859 emit_operand(dst, src);
6860 }
6861
6862 // scalar single/double precision replicate
6863
6864 // duplicate single precision data from src into programmed locations in dest : requires AVX512VL
6865 void Assembler::vpbroadcastss(XMMRegister dst, XMMRegister src, int vector_len) {
6866 assert(VM_Version::supports_avx(), "");
6867 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6868 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6869 emit_int8(0x18);
6870 emit_int8((unsigned char)(0xC0 | encode));
6871 }
6872
6873 void Assembler::vpbroadcastss(XMMRegister dst, Address src, int vector_len) {
6874 assert(VM_Version::supports_avx(), "");
6875 assert(dst != xnoreg, "sanity");
6876 InstructionMark im(this);
6877 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6878 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
6879 // swap src<->dst for encoding
6880 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6881 emit_int8(0x18);
6882 emit_operand(dst, src);
6883 }
6884
6885 // duplicate double precision data from src into programmed locations in dest : requires AVX512VL
6886 void Assembler::vpbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len) {
6887 assert(VM_Version::supports_avx(), "");
6888 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6889 attributes.set_rex_vex_w_reverted();
6890 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6891 emit_int8(0x19);
6892 emit_int8((unsigned char)(0xC0 | encode));
6893 }
6894
6895 void Assembler::vpbroadcastsd(XMMRegister dst, Address src, int vector_len) {
6896 assert(VM_Version::supports_avx(), "");
6897 assert(dst != xnoreg, "sanity");
6898 InstructionMark im(this);
6899 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6900 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6901 attributes.set_rex_vex_w_reverted();
6902 // swap src<->dst for encoding
6903 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6904 emit_int8(0x19);
6905 emit_operand(dst, src);
6906 }
6907
6908
6909 // gpr source broadcast forms
6910
6911 // duplicate 1-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
6912 void Assembler::evpbroadcastb(XMMRegister dst, Register src, int vector_len) {
6913 assert(VM_Version::supports_avx512bw(), "");
6914 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6915 attributes.set_is_evex_instruction();
6916 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6917 emit_int8(0x7A);
6918 emit_int8((unsigned char)(0xC0 | encode));
6919 }
6920
6921 // duplicate 2-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
6922 void Assembler::evpbroadcastw(XMMRegister dst, Register src, int vector_len) {
6923 assert(VM_Version::supports_avx512bw(), "");
6924 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6925 attributes.set_is_evex_instruction();
6926 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6927 emit_int8(0x7B);
6928 emit_int8((unsigned char)(0xC0 | encode));
6929 }
6930
6931 // duplicate 4-byte integer data from src into programmed locations in dest : requires AVX512VL
6932 void Assembler::evpbroadcastd(XMMRegister dst, Register src, int vector_len) {
6933 assert(VM_Version::supports_evex(), "");
6934 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6935 attributes.set_is_evex_instruction();
6936 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6937 emit_int8(0x7C);
6938 emit_int8((unsigned char)(0xC0 | encode));
6939 }
6940
6941 // duplicate 8-byte integer data from src into programmed locations in dest : requires AVX512VL
6942 void Assembler::evpbroadcastq(XMMRegister dst, Register src, int vector_len) {
6943 assert(VM_Version::supports_evex(), "");
6944 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6945 attributes.set_is_evex_instruction();
6946 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6947 emit_int8(0x7C);
6948 emit_int8((unsigned char)(0xC0 | encode));
6949 }
6950
6951 void Assembler::evpgatherdd(XMMRegister dst, KRegister mask, Address src, int vector_len) {
6952 assert(VM_Version::supports_evex(), "");
6953 assert(dst != xnoreg, "sanity");
6954 InstructionMark im(this);
6955 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6956 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6957 attributes.reset_is_clear_context();
6958 attributes.set_embedded_opmask_register_specifier(mask);
6959 attributes.set_is_evex_instruction();
6960 // swap src<->dst for encoding
6961 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6962 emit_int8((unsigned char)0x90);
6963 emit_operand(dst, src);
6964 }
6965
6966 // Carry-Less Multiplication Quadword
6967 void Assembler::pclmulqdq(XMMRegister dst, XMMRegister src, int mask) {
6968 assert(VM_Version::supports_clmul(), "");
6969 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
6970 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6971 emit_int8(0x44);
6972 emit_int8((unsigned char)(0xC0 | encode));
6973 emit_int8((unsigned char)mask);
6974 }
6975
6976 // Carry-Less Multiplication Quadword
6977 void Assembler::vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask) {
6978 assert(VM_Version::supports_avx() && VM_Version::supports_clmul(), "");
6979 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
6980 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6981 emit_int8(0x44);
6982 emit_int8((unsigned char)(0xC0 | encode));
6983 emit_int8((unsigned char)mask);
6984 }
6985
6986 void Assembler::evpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask, int vector_len) {
6987 assert(VM_Version::supports_vpclmulqdq(), "Requires vector carryless multiplication support");
6988 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6989 attributes.set_is_evex_instruction();
6990 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6991 emit_int8(0x44);
6992 emit_int8((unsigned char)(0xC0 | encode));
6993 emit_int8((unsigned char)mask);
6994 }
6995
6996 void Assembler::vzeroupper() {
6997 if (VM_Version::supports_vzeroupper()) {
6998 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
6999 (void)vex_prefix_and_encode(0, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7000 emit_int8(0x77);
7001 }
7002 }
7003
7004 #ifndef _LP64
7005 // 32bit only pieces of the assembler
7006
7007 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
7008 // NO PREFIX AS NEVER 64BIT
7009 InstructionMark im(this);
7010 emit_int8((unsigned char)0x81);
7011 emit_int8((unsigned char)(0xF8 | src1->encoding()));
7012 emit_data(imm32, rspec, 0);
7013 }
7014
7015 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
7016 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
7017 InstructionMark im(this);
7018 emit_int8((unsigned char)0x81);
7019 emit_operand(rdi, src1);
7020 emit_data(imm32, rspec, 0);
7021 }
7022
7023 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax,
7024 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded
7025 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise.
7026 void Assembler::cmpxchg8(Address adr) {
7027 InstructionMark im(this);
7028 emit_int8(0x0F);
7029 emit_int8((unsigned char)0xC7);
7030 emit_operand(rcx, adr);
7031 }
7032
7033 void Assembler::decl(Register dst) {
7034 // Don't use it directly. Use MacroAssembler::decrementl() instead.
7035 emit_int8(0x48 | dst->encoding());
7036 }
7037
7038 #endif // _LP64
7039
7040 // 64bit typically doesn't use the x87 but needs to for the trig funcs
7041
7042 void Assembler::fabs() {
7043 emit_int8((unsigned char)0xD9);
7044 emit_int8((unsigned char)0xE1);
7045 }
7046
7047 void Assembler::fadd(int i) {
7048 emit_farith(0xD8, 0xC0, i);
7049 }
7050
7051 void Assembler::fadd_d(Address src) {
7052 InstructionMark im(this);
7053 emit_int8((unsigned char)0xDC);
7054 emit_operand32(rax, src);
7055 }
7056
7057 void Assembler::fadd_s(Address src) {
7058 InstructionMark im(this);
7059 emit_int8((unsigned char)0xD8);
7060 emit_operand32(rax, src);
7061 }
7062
7063 void Assembler::fadda(int i) {
7064 emit_farith(0xDC, 0xC0, i);
7065 }
7066
7067 void Assembler::faddp(int i) {
7068 emit_farith(0xDE, 0xC0, i);
7069 }
7070
7071 void Assembler::fchs() {
7072 emit_int8((unsigned char)0xD9);
7073 emit_int8((unsigned char)0xE0);
7074 }
7075
7076 void Assembler::fcom(int i) {
7077 emit_farith(0xD8, 0xD0, i);
7078 }
7079
7080 void Assembler::fcomp(int i) {
7081 emit_farith(0xD8, 0xD8, i);
7082 }
7083
7084 void Assembler::fcomp_d(Address src) {
7085 InstructionMark im(this);
7086 emit_int8((unsigned char)0xDC);
7087 emit_operand32(rbx, src);
7088 }
7089
7090 void Assembler::fcomp_s(Address src) {
7091 InstructionMark im(this);
7092 emit_int8((unsigned char)0xD8);
7093 emit_operand32(rbx, src);
7094 }
7095
7096 void Assembler::fcompp() {
7097 emit_int8((unsigned char)0xDE);
7098 emit_int8((unsigned char)0xD9);
7099 }
7100
7101 void Assembler::fcos() {
7102 emit_int8((unsigned char)0xD9);
7103 emit_int8((unsigned char)0xFF);
7104 }
7105
7106 void Assembler::fdecstp() {
7107 emit_int8((unsigned char)0xD9);
7108 emit_int8((unsigned char)0xF6);
7109 }
7110
7111 void Assembler::fdiv(int i) {
7112 emit_farith(0xD8, 0xF0, i);
7113 }
7114
7115 void Assembler::fdiv_d(Address src) {
7116 InstructionMark im(this);
7117 emit_int8((unsigned char)0xDC);
7118 emit_operand32(rsi, src);
7119 }
7120
7121 void Assembler::fdiv_s(Address src) {
7122 InstructionMark im(this);
7123 emit_int8((unsigned char)0xD8);
7124 emit_operand32(rsi, src);
7125 }
7126
7127 void Assembler::fdiva(int i) {
7128 emit_farith(0xDC, 0xF8, i);
7129 }
7130
7131 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994)
7132 // is erroneous for some of the floating-point instructions below.
7133
7134 void Assembler::fdivp(int i) {
7135 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong)
7136 }
7137
7138 void Assembler::fdivr(int i) {
7139 emit_farith(0xD8, 0xF8, i);
7140 }
7141
7142 void Assembler::fdivr_d(Address src) {
7143 InstructionMark im(this);
7144 emit_int8((unsigned char)0xDC);
7145 emit_operand32(rdi, src);
7146 }
7147
7148 void Assembler::fdivr_s(Address src) {
7149 InstructionMark im(this);
7150 emit_int8((unsigned char)0xD8);
7151 emit_operand32(rdi, src);
7152 }
7153
7154 void Assembler::fdivra(int i) {
7155 emit_farith(0xDC, 0xF0, i);
7156 }
7157
7158 void Assembler::fdivrp(int i) {
7159 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong)
7160 }
7161
7162 void Assembler::ffree(int i) {
7163 emit_farith(0xDD, 0xC0, i);
7164 }
7165
7166 void Assembler::fild_d(Address adr) {
7167 InstructionMark im(this);
7168 emit_int8((unsigned char)0xDF);
7169 emit_operand32(rbp, adr);
7170 }
7171
7172 void Assembler::fild_s(Address adr) {
7173 InstructionMark im(this);
7174 emit_int8((unsigned char)0xDB);
7175 emit_operand32(rax, adr);
7176 }
7177
7178 void Assembler::fincstp() {
7179 emit_int8((unsigned char)0xD9);
7180 emit_int8((unsigned char)0xF7);
7181 }
7182
7183 void Assembler::finit() {
7184 emit_int8((unsigned char)0x9B);
7185 emit_int8((unsigned char)0xDB);
7186 emit_int8((unsigned char)0xE3);
7187 }
7188
7189 void Assembler::fist_s(Address adr) {
7190 InstructionMark im(this);
7191 emit_int8((unsigned char)0xDB);
7192 emit_operand32(rdx, adr);
7193 }
7194
7195 void Assembler::fistp_d(Address adr) {
7196 InstructionMark im(this);
7197 emit_int8((unsigned char)0xDF);
7198 emit_operand32(rdi, adr);
7199 }
7200
7201 void Assembler::fistp_s(Address adr) {
7202 InstructionMark im(this);
7203 emit_int8((unsigned char)0xDB);
7204 emit_operand32(rbx, adr);
7205 }
7206
7207 void Assembler::fld1() {
7208 emit_int8((unsigned char)0xD9);
7209 emit_int8((unsigned char)0xE8);
7210 }
7211
7212 void Assembler::fld_d(Address adr) {
7213 InstructionMark im(this);
7214 emit_int8((unsigned char)0xDD);
7215 emit_operand32(rax, adr);
7216 }
7217
7218 void Assembler::fld_s(Address adr) {
7219 InstructionMark im(this);
7220 emit_int8((unsigned char)0xD9);
7221 emit_operand32(rax, adr);
7222 }
7223
7224
7225 void Assembler::fld_s(int index) {
7226 emit_farith(0xD9, 0xC0, index);
7227 }
7228
7229 void Assembler::fld_x(Address adr) {
7230 InstructionMark im(this);
7231 emit_int8((unsigned char)0xDB);
7232 emit_operand32(rbp, adr);
7233 }
7234
7235 void Assembler::fldcw(Address src) {
7236 InstructionMark im(this);
7237 emit_int8((unsigned char)0xD9);
7238 emit_operand32(rbp, src);
7239 }
7240
7241 void Assembler::fldenv(Address src) {
7242 InstructionMark im(this);
7243 emit_int8((unsigned char)0xD9);
7244 emit_operand32(rsp, src);
7245 }
7246
7247 void Assembler::fldlg2() {
7248 emit_int8((unsigned char)0xD9);
7249 emit_int8((unsigned char)0xEC);
7250 }
7251
7252 void Assembler::fldln2() {
7253 emit_int8((unsigned char)0xD9);
7254 emit_int8((unsigned char)0xED);
7255 }
7256
7257 void Assembler::fldz() {
7258 emit_int8((unsigned char)0xD9);
7259 emit_int8((unsigned char)0xEE);
7260 }
7261
7262 void Assembler::flog() {
7263 fldln2();
7264 fxch();
7265 fyl2x();
7266 }
7267
7268 void Assembler::flog10() {
7269 fldlg2();
7270 fxch();
7271 fyl2x();
7272 }
7273
7274 void Assembler::fmul(int i) {
7275 emit_farith(0xD8, 0xC8, i);
7276 }
7277
7278 void Assembler::fmul_d(Address src) {
7279 InstructionMark im(this);
7280 emit_int8((unsigned char)0xDC);
7281 emit_operand32(rcx, src);
7282 }
7283
7284 void Assembler::fmul_s(Address src) {
7285 InstructionMark im(this);
7286 emit_int8((unsigned char)0xD8);
7287 emit_operand32(rcx, src);
7288 }
7289
7290 void Assembler::fmula(int i) {
7291 emit_farith(0xDC, 0xC8, i);
7292 }
7293
7294 void Assembler::fmulp(int i) {
7295 emit_farith(0xDE, 0xC8, i);
7296 }
7297
7298 void Assembler::fnsave(Address dst) {
7299 InstructionMark im(this);
7300 emit_int8((unsigned char)0xDD);
7301 emit_operand32(rsi, dst);
7302 }
7303
7304 void Assembler::fnstcw(Address src) {
7305 InstructionMark im(this);
7306 emit_int8((unsigned char)0x9B);
7307 emit_int8((unsigned char)0xD9);
7308 emit_operand32(rdi, src);
7309 }
7310
7311 void Assembler::fnstsw_ax() {
7312 emit_int8((unsigned char)0xDF);
7313 emit_int8((unsigned char)0xE0);
7314 }
7315
7316 void Assembler::fprem() {
7317 emit_int8((unsigned char)0xD9);
7318 emit_int8((unsigned char)0xF8);
7319 }
7320
7321 void Assembler::fprem1() {
7322 emit_int8((unsigned char)0xD9);
7323 emit_int8((unsigned char)0xF5);
7324 }
7325
7326 void Assembler::frstor(Address src) {
7327 InstructionMark im(this);
7328 emit_int8((unsigned char)0xDD);
7329 emit_operand32(rsp, src);
7330 }
7331
7332 void Assembler::fsin() {
7333 emit_int8((unsigned char)0xD9);
7334 emit_int8((unsigned char)0xFE);
7335 }
7336
7337 void Assembler::fsqrt() {
7338 emit_int8((unsigned char)0xD9);
7339 emit_int8((unsigned char)0xFA);
7340 }
7341
7342 void Assembler::fst_d(Address adr) {
7343 InstructionMark im(this);
7344 emit_int8((unsigned char)0xDD);
7345 emit_operand32(rdx, adr);
7346 }
7347
7348 void Assembler::fst_s(Address adr) {
7349 InstructionMark im(this);
7350 emit_int8((unsigned char)0xD9);
7351 emit_operand32(rdx, adr);
7352 }
7353
7354 void Assembler::fstp_d(Address adr) {
7355 InstructionMark im(this);
7356 emit_int8((unsigned char)0xDD);
7357 emit_operand32(rbx, adr);
7358 }
7359
7360 void Assembler::fstp_d(int index) {
7361 emit_farith(0xDD, 0xD8, index);
7362 }
7363
7364 void Assembler::fstp_s(Address adr) {
7365 InstructionMark im(this);
7366 emit_int8((unsigned char)0xD9);
7367 emit_operand32(rbx, adr);
7368 }
7369
7370 void Assembler::fstp_x(Address adr) {
7371 InstructionMark im(this);
7372 emit_int8((unsigned char)0xDB);
7373 emit_operand32(rdi, adr);
7374 }
7375
7376 void Assembler::fsub(int i) {
7377 emit_farith(0xD8, 0xE0, i);
7378 }
7379
7380 void Assembler::fsub_d(Address src) {
7381 InstructionMark im(this);
7382 emit_int8((unsigned char)0xDC);
7383 emit_operand32(rsp, src);
7384 }
7385
7386 void Assembler::fsub_s(Address src) {
7387 InstructionMark im(this);
7388 emit_int8((unsigned char)0xD8);
7389 emit_operand32(rsp, src);
7390 }
7391
7392 void Assembler::fsuba(int i) {
7393 emit_farith(0xDC, 0xE8, i);
7394 }
7395
7396 void Assembler::fsubp(int i) {
7397 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong)
7398 }
7399
7400 void Assembler::fsubr(int i) {
7401 emit_farith(0xD8, 0xE8, i);
7402 }
7403
7404 void Assembler::fsubr_d(Address src) {
7405 InstructionMark im(this);
7406 emit_int8((unsigned char)0xDC);
7407 emit_operand32(rbp, src);
7408 }
7409
7410 void Assembler::fsubr_s(Address src) {
7411 InstructionMark im(this);
7412 emit_int8((unsigned char)0xD8);
7413 emit_operand32(rbp, src);
7414 }
7415
7416 void Assembler::fsubra(int i) {
7417 emit_farith(0xDC, 0xE0, i);
7418 }
7419
7420 void Assembler::fsubrp(int i) {
7421 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong)
7422 }
7423
7424 void Assembler::ftan() {
7425 emit_int8((unsigned char)0xD9);
7426 emit_int8((unsigned char)0xF2);
7427 emit_int8((unsigned char)0xDD);
7428 emit_int8((unsigned char)0xD8);
7429 }
7430
7431 void Assembler::ftst() {
7432 emit_int8((unsigned char)0xD9);
7433 emit_int8((unsigned char)0xE4);
7434 }
7435
7436 void Assembler::fucomi(int i) {
7437 // make sure the instruction is supported (introduced for P6, together with cmov)
7438 guarantee(VM_Version::supports_cmov(), "illegal instruction");
7439 emit_farith(0xDB, 0xE8, i);
7440 }
7441
7442 void Assembler::fucomip(int i) {
7443 // make sure the instruction is supported (introduced for P6, together with cmov)
7444 guarantee(VM_Version::supports_cmov(), "illegal instruction");
7445 emit_farith(0xDF, 0xE8, i);
7446 }
7447
7448 void Assembler::fwait() {
7449 emit_int8((unsigned char)0x9B);
7450 }
7451
7452 void Assembler::fxch(int i) {
7453 emit_farith(0xD9, 0xC8, i);
7454 }
7455
7456 void Assembler::fyl2x() {
7457 emit_int8((unsigned char)0xD9);
7458 emit_int8((unsigned char)0xF1);
7459 }
7460
7461 void Assembler::frndint() {
7462 emit_int8((unsigned char)0xD9);
7463 emit_int8((unsigned char)0xFC);
7464 }
7465
7466 void Assembler::f2xm1() {
7467 emit_int8((unsigned char)0xD9);
7468 emit_int8((unsigned char)0xF0);
7469 }
7470
7471 void Assembler::fldl2e() {
7472 emit_int8((unsigned char)0xD9);
7473 emit_int8((unsigned char)0xEA);
7474 }
7475
7476 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding.
7477 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 };
7478 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding.
7479 static int simd_opc[4] = { 0, 0, 0x38, 0x3A };
7480
7481 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding.
7482 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
7483 if (pre > 0) {
7484 emit_int8(simd_pre[pre]);
7485 }
7486 if (rex_w) {
7487 prefixq(adr, xreg);
7488 } else {
7489 prefix(adr, xreg);
7490 }
7491 if (opc > 0) {
7492 emit_int8(0x0F);
7493 int opc2 = simd_opc[opc];
7494 if (opc2 > 0) {
7495 emit_int8(opc2);
7496 }
7497 }
7498 }
7499
7500 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
7501 if (pre > 0) {
7502 emit_int8(simd_pre[pre]);
7503 }
7504 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) : prefix_and_encode(dst_enc, src_enc);
7505 if (opc > 0) {
7506 emit_int8(0x0F);
7507 int opc2 = simd_opc[opc];
7508 if (opc2 > 0) {
7509 emit_int8(opc2);
7510 }
7511 }
7512 return encode;
7513 }
7514
7515
7516 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc) {
7517 int vector_len = _attributes->get_vector_len();
7518 bool vex_w = _attributes->is_rex_vex_w();
7519 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) {
7520 prefix(VEX_3bytes);
7521
7522 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0);
7523 byte1 = (~byte1) & 0xE0;
7524 byte1 |= opc;
7525 emit_int8(byte1);
7526
7527 int byte2 = ((~nds_enc) & 0xf) << 3;
7528 byte2 |= (vex_w ? VEX_W : 0) | ((vector_len > 0) ? 4 : 0) | pre;
7529 emit_int8(byte2);
7530 } else {
7531 prefix(VEX_2bytes);
7532
7533 int byte1 = vex_r ? VEX_R : 0;
7534 byte1 = (~byte1) & 0x80;
7535 byte1 |= ((~nds_enc) & 0xf) << 3;
7536 byte1 |= ((vector_len > 0 ) ? 4 : 0) | pre;
7537 emit_int8(byte1);
7538 }
7539 }
7540
7541 // This is a 4 byte encoding
7542 void Assembler::evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_r, bool evex_v, int nds_enc, VexSimdPrefix pre, VexOpcode opc){
7543 // EVEX 0x62 prefix
7544 prefix(EVEX_4bytes);
7545 bool vex_w = _attributes->is_rex_vex_w();
7546 int evex_encoding = (vex_w ? VEX_W : 0);
7547 // EVEX.b is not currently used for broadcast of single element or data rounding modes
7548 _attributes->set_evex_encoding(evex_encoding);
7549
7550 // P0: byte 2, initialized to RXBR`00mm
7551 // instead of not'd
7552 int byte2 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0) | (evex_r ? EVEX_Rb : 0);
7553 byte2 = (~byte2) & 0xF0;
7554 // confine opc opcode extensions in mm bits to lower two bits
7555 // of form {0F, 0F_38, 0F_3A}
7556 byte2 |= opc;
7557 emit_int8(byte2);
7558
7559 // P1: byte 3 as Wvvvv1pp
7560 int byte3 = ((~nds_enc) & 0xf) << 3;
7561 // p[10] is always 1
7562 byte3 |= EVEX_F;
7563 byte3 |= (vex_w & 1) << 7;
7564 // confine pre opcode extensions in pp bits to lower two bits
7565 // of form {66, F3, F2}
7566 byte3 |= pre;
7567 emit_int8(byte3);
7568
7569 // P2: byte 4 as zL'Lbv'aaa
7570 // kregs are implemented in the low 3 bits as aaa
7571 int byte4 = (_attributes->is_no_reg_mask()) ?
7572 0 :
7573 _attributes->get_embedded_opmask_register_specifier();
7574 // EVEX.v` for extending EVEX.vvvv or VIDX
7575 byte4 |= (evex_v ? 0: EVEX_V);
7576 // third EXEC.b for broadcast actions
7577 byte4 |= (_attributes->is_extended_context() ? EVEX_Rb : 0);
7578 // fourth EVEX.L'L for vector length : 0 is 128, 1 is 256, 2 is 512, currently we do not support 1024
7579 byte4 |= ((_attributes->get_vector_len())& 0x3) << 5;
7580 // last is EVEX.z for zero/merge actions
7581 if (_attributes->is_no_reg_mask() == false) {
7582 byte4 |= (_attributes->is_clear_context() ? EVEX_Z : 0);
7583 }
7584 emit_int8(byte4);
7585 }
7586
7587 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) {
7588 bool vex_r = ((xreg_enc & 8) == 8) ? 1 : 0;
7589 bool vex_b = adr.base_needs_rex();
7590 bool vex_x;
7591 if (adr.isxmmindex()) {
7592 vex_x = adr.xmmindex_needs_rex();
7593 } else {
7594 vex_x = adr.index_needs_rex();
7595 }
7596 set_attributes(attributes);
7597 attributes->set_current_assembler(this);
7598
7599 // For EVEX instruction (which is not marked as pure EVEX instruction) check and see if this instruction
7600 // is allowed in legacy mode and has resources which will fit in it.
7601 // Pure EVEX instructions will have is_evex_instruction set in their definition.
7602 if (!attributes->is_legacy_mode()) {
7603 if (UseAVX > 2 && !attributes->is_evex_instruction() && !_is_managed) {
7604 if ((attributes->get_vector_len() != AVX_512bit) && (nds_enc < 16) && (xreg_enc < 16)) {
7605 attributes->set_is_legacy_mode();
7606 }
7607 }
7608 }
7609
7610 if (UseAVX > 2) {
7611 assert(((!attributes->uses_vl()) ||
7612 (attributes->get_vector_len() == AVX_512bit) ||
7613 (!_legacy_mode_vl) ||
7614 (attributes->is_legacy_mode())),"XMM register should be 0-15");
7615 assert(((nds_enc < 16 && xreg_enc < 16) || (!attributes->is_legacy_mode())),"XMM register should be 0-15");
7616 }
7617
7618 _is_managed = false;
7619 if (UseAVX > 2 && !attributes->is_legacy_mode())
7620 {
7621 bool evex_r = (xreg_enc >= 16);
7622 bool evex_v;
7623 // EVEX.V' is set to true when VSIB is used as we may need to use higher order XMM registers (16-31)
7624 if (adr.isxmmindex()) {
7625 evex_v = ((adr._xmmindex->encoding() > 15) ? true : false);
7626 } else {
7627 evex_v = (nds_enc >= 16);
7628 }
7629 attributes->set_is_evex_instruction();
7630 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc);
7631 } else {
7632 if (UseAVX > 2 && attributes->is_rex_vex_w_reverted()) {
7633 attributes->set_rex_vex_w(false);
7634 }
7635 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc);
7636 }
7637 }
7638
7639 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) {
7640 bool vex_r = ((dst_enc & 8) == 8) ? 1 : 0;
7641 bool vex_b = ((src_enc & 8) == 8) ? 1 : 0;
7642 bool vex_x = false;
7643 set_attributes(attributes);
7644 attributes->set_current_assembler(this);
7645
7646 // For EVEX instruction (which is not marked as pure EVEX instruction) check and see if this instruction
7647 // is allowed in legacy mode and has resources which will fit in it.
7648 // Pure EVEX instructions will have is_evex_instruction set in their definition.
7649 if (!attributes->is_legacy_mode()) {
7650 if (UseAVX > 2 && !attributes->is_evex_instruction() && !_is_managed) {
7651 if ((!attributes->uses_vl() || (attributes->get_vector_len() != AVX_512bit)) &&
7652 (dst_enc < 16) && (nds_enc < 16) && (src_enc < 16)) {
7653 attributes->set_is_legacy_mode();
7654 }
7655 }
7656 }
7657
7658 if (UseAVX > 2) {
7659 // All the scalar fp instructions (with uses_vl as false) can have legacy_mode as false
7660 // Instruction with uses_vl true are vector instructions
7661 // All the vector instructions with AVX_512bit length can have legacy_mode as false
7662 // All the vector instructions with < AVX_512bit length can have legacy_mode as false if AVX512vl() is supported
7663 // Rest all should have legacy_mode set as true
7664 assert(((!attributes->uses_vl()) ||
7665 (attributes->get_vector_len() == AVX_512bit) ||
7666 (!_legacy_mode_vl) ||
7667 (attributes->is_legacy_mode())),"XMM register should be 0-15");
7668 // Instruction with legacy_mode true should have dst, nds and src < 15
7669 assert(((dst_enc < 16 && nds_enc < 16 && src_enc < 16) || (!attributes->is_legacy_mode())),"XMM register should be 0-15");
7670 }
7671
7672 _is_managed = false;
7673 if (UseAVX > 2 && !attributes->is_legacy_mode())
7674 {
7675 bool evex_r = (dst_enc >= 16);
7676 bool evex_v = (nds_enc >= 16);
7677 // can use vex_x as bank extender on rm encoding
7678 vex_x = (src_enc >= 16);
7679 attributes->set_is_evex_instruction();
7680 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc);
7681 } else {
7682 if (UseAVX > 2 && attributes->is_rex_vex_w_reverted()) {
7683 attributes->set_rex_vex_w(false);
7684 }
7685 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc);
7686 }
7687
7688 // return modrm byte components for operands
7689 return (((dst_enc & 7) << 3) | (src_enc & 7));
7690 }
7691
7692
7693 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre,
7694 VexOpcode opc, InstructionAttr *attributes) {
7695 if (UseAVX > 0) {
7696 int xreg_enc = xreg->encoding();
7697 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
7698 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, attributes);
7699 } else {
7700 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding");
7701 rex_prefix(adr, xreg, pre, opc, attributes->is_rex_vex_w());
7702 }
7703 }
7704
7705 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre,
7706 VexOpcode opc, InstructionAttr *attributes) {
7707 int dst_enc = dst->encoding();
7708 int src_enc = src->encoding();
7709 if (UseAVX > 0) {
7710 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
7711 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, attributes);
7712 } else {
7713 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding");
7714 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, attributes->is_rex_vex_w());
7715 }
7716 }
7717
7718 void Assembler::cmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) {
7719 assert(VM_Version::supports_avx(), "");
7720 assert(!VM_Version::supports_evex(), "");
7721 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
7722 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7723 emit_int8((unsigned char)0xC2);
7724 emit_int8((unsigned char)(0xC0 | encode));
7725 emit_int8((unsigned char)(0xF & cop));
7726 }
7727
7728 void Assembler::blendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) {
7729 assert(VM_Version::supports_avx(), "");
7730 assert(!VM_Version::supports_evex(), "");
7731 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
7732 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7733 emit_int8((unsigned char)0x4B);
7734 emit_int8((unsigned char)(0xC0 | encode));
7735 int src2_enc = src2->encoding();
7736 emit_int8((unsigned char)(0xF0 & src2_enc<<4));
7737 }
7738
7739 void Assembler::cmpps(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) {
7740 assert(VM_Version::supports_avx(), "");
7741 assert(!VM_Version::supports_evex(), "");
7742 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
7743 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7744 emit_int8((unsigned char)0xC2);
7745 emit_int8((unsigned char)(0xC0 | encode));
7746 emit_int8((unsigned char)(0xF & cop));
7747 }
7748
7749 void Assembler::blendvps(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) {
7750 assert(VM_Version::supports_avx(), "");
7751 assert(!VM_Version::supports_evex(), "");
7752 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
7753 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7754 emit_int8((unsigned char)0x4A);
7755 emit_int8((unsigned char)(0xC0 | encode));
7756 int src2_enc = src2->encoding();
7757 emit_int8((unsigned char)(0xF0 & src2_enc<<4));
7758 }
7759
7760 void Assembler::vpblendd(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
7761 assert(VM_Version::supports_avx2(), "");
7762 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
7763 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7764 emit_int8((unsigned char)0x02);
7765 emit_int8((unsigned char)(0xC0 | encode));
7766 emit_int8((unsigned char)imm8);
7767 }
7768
7769 void Assembler::shlxl(Register dst, Register src1, Register src2) {
7770 assert(VM_Version::supports_bmi2(), "");
7771 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
7772 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7773 emit_int8((unsigned char)0xF7);
7774 emit_int8((unsigned char)(0xC0 | encode));
7775 }
7776
7777 void Assembler::shlxq(Register dst, Register src1, Register src2) {
7778 assert(VM_Version::supports_bmi2(), "");
7779 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
7780 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7781 emit_int8((unsigned char)0xF7);
7782 emit_int8((unsigned char)(0xC0 | encode));
7783 }
7784
7785 #ifndef _LP64
7786
7787 void Assembler::incl(Register dst) {
7788 // Don't use it directly. Use MacroAssembler::incrementl() instead.
7789 emit_int8(0x40 | dst->encoding());
7790 }
7791
7792 void Assembler::lea(Register dst, Address src) {
7793 leal(dst, src);
7794 }
7795
7796 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
7797 InstructionMark im(this);
7798 emit_int8((unsigned char)0xC7);
7799 emit_operand(rax, dst);
7800 emit_data((int)imm32, rspec, 0);
7801 }
7802
7803 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
7804 InstructionMark im(this);
7805 int encode = prefix_and_encode(dst->encoding());
7806 emit_int8((unsigned char)(0xB8 | encode));
7807 emit_data((int)imm32, rspec, 0);
7808 }
7809
7810 void Assembler::popa() { // 32bit
7811 emit_int8(0x61);
7812 }
7813
7814 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
7815 InstructionMark im(this);
7816 emit_int8(0x68);
7817 emit_data(imm32, rspec, 0);
7818 }
7819
7820 void Assembler::pusha() { // 32bit
7821 emit_int8(0x60);
7822 }
7823
7824 void Assembler::set_byte_if_not_zero(Register dst) {
7825 emit_int8(0x0F);
7826 emit_int8((unsigned char)0x95);
7827 emit_int8((unsigned char)(0xE0 | dst->encoding()));
7828 }
7829
7830 void Assembler::shldl(Register dst, Register src) {
7831 emit_int8(0x0F);
7832 emit_int8((unsigned char)0xA5);
7833 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
7834 }
7835
7836 // 0F A4 / r ib
7837 void Assembler::shldl(Register dst, Register src, int8_t imm8) {
7838 emit_int8(0x0F);
7839 emit_int8((unsigned char)0xA4);
7840 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
7841 emit_int8(imm8);
7842 }
7843
7844 void Assembler::shrdl(Register dst, Register src) {
7845 emit_int8(0x0F);
7846 emit_int8((unsigned char)0xAD);
7847 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
7848 }
7849
7850 #else // LP64
7851
7852 void Assembler::set_byte_if_not_zero(Register dst) {
7853 int enc = prefix_and_encode(dst->encoding(), true);
7854 emit_int8(0x0F);
7855 emit_int8((unsigned char)0x95);
7856 emit_int8((unsigned char)(0xE0 | enc));
7857 }
7858
7859 // 64bit only pieces of the assembler
7860 // This should only be used by 64bit instructions that can use rip-relative
7861 // it cannot be used by instructions that want an immediate value.
7862
7863 bool Assembler::reachable(AddressLiteral adr) {
7864 int64_t disp;
7865 // None will force a 64bit literal to the code stream. Likely a placeholder
7866 // for something that will be patched later and we need to certain it will
7867 // always be reachable.
7868 if (adr.reloc() == relocInfo::none) {
7869 return false;
7870 }
7871 if (adr.reloc() == relocInfo::internal_word_type) {
7872 // This should be rip relative and easily reachable.
7873 return true;
7874 }
7875 if (adr.reloc() == relocInfo::virtual_call_type ||
7876 adr.reloc() == relocInfo::opt_virtual_call_type ||
7877 adr.reloc() == relocInfo::static_call_type ||
7878 adr.reloc() == relocInfo::static_stub_type ) {
7879 // This should be rip relative within the code cache and easily
7880 // reachable until we get huge code caches. (At which point
7881 // ic code is going to have issues).
7882 return true;
7883 }
7884 if (adr.reloc() != relocInfo::external_word_type &&
7885 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special
7886 adr.reloc() != relocInfo::poll_type && // relocs to identify them
7887 adr.reloc() != relocInfo::runtime_call_type ) {
7888 return false;
7889 }
7890
7891 // Stress the correction code
7892 if (ForceUnreachable) {
7893 // Must be runtimecall reloc, see if it is in the codecache
7894 // Flipping stuff in the codecache to be unreachable causes issues
7895 // with things like inline caches where the additional instructions
7896 // are not handled.
7897 if (CodeCache::find_blob(adr._target) == NULL) {
7898 return false;
7899 }
7900 }
7901 // For external_word_type/runtime_call_type if it is reachable from where we
7902 // are now (possibly a temp buffer) and where we might end up
7903 // anywhere in the codeCache then we are always reachable.
7904 // This would have to change if we ever save/restore shared code
7905 // to be more pessimistic.
7906 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int));
7907 if (!is_simm32(disp)) return false;
7908 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int));
7909 if (!is_simm32(disp)) return false;
7910
7911 disp = (int64_t)adr._target - ((int64_t)pc() + sizeof(int));
7912
7913 // Because rip relative is a disp + address_of_next_instruction and we
7914 // don't know the value of address_of_next_instruction we apply a fudge factor
7915 // to make sure we will be ok no matter the size of the instruction we get placed into.
7916 // We don't have to fudge the checks above here because they are already worst case.
7917
7918 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal
7919 // + 4 because better safe than sorry.
7920 const int fudge = 12 + 4;
7921 if (disp < 0) {
7922 disp -= fudge;
7923 } else {
7924 disp += fudge;
7925 }
7926 return is_simm32(disp);
7927 }
7928
7929 // Check if the polling page is not reachable from the code cache using rip-relative
7930 // addressing.
7931 bool Assembler::is_polling_page_far() {
7932 intptr_t addr = (intptr_t)os::get_polling_page();
7933 return ForceUnreachable ||
7934 !is_simm32(addr - (intptr_t)CodeCache::low_bound()) ||
7935 !is_simm32(addr - (intptr_t)CodeCache::high_bound());
7936 }
7937
7938 void Assembler::emit_data64(jlong data,
7939 relocInfo::relocType rtype,
7940 int format) {
7941 if (rtype == relocInfo::none) {
7942 emit_int64(data);
7943 } else {
7944 emit_data64(data, Relocation::spec_simple(rtype), format);
7945 }
7946 }
7947
7948 void Assembler::emit_data64(jlong data,
7949 RelocationHolder const& rspec,
7950 int format) {
7951 assert(imm_operand == 0, "default format must be immediate in this file");
7952 assert(imm_operand == format, "must be immediate");
7953 assert(inst_mark() != NULL, "must be inside InstructionMark");
7954 // Do not use AbstractAssembler::relocate, which is not intended for
7955 // embedded words. Instead, relocate to the enclosing instruction.
7956 code_section()->relocate(inst_mark(), rspec, format);
7957 #ifdef ASSERT
7958 check_relocation(rspec, format);
7959 #endif
7960 emit_int64(data);
7961 }
7962
7963 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) {
7964 if (reg_enc >= 8) {
7965 prefix(REX_B);
7966 reg_enc -= 8;
7967 } else if (byteinst && reg_enc >= 4) {
7968 prefix(REX);
7969 }
7970 return reg_enc;
7971 }
7972
7973 int Assembler::prefixq_and_encode(int reg_enc) {
7974 if (reg_enc < 8) {
7975 prefix(REX_W);
7976 } else {
7977 prefix(REX_WB);
7978 reg_enc -= 8;
7979 }
7980 return reg_enc;
7981 }
7982
7983 int Assembler::prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte) {
7984 if (dst_enc < 8) {
7985 if (src_enc >= 8) {
7986 prefix(REX_B);
7987 src_enc -= 8;
7988 } else if ((src_is_byte && src_enc >= 4) || (dst_is_byte && dst_enc >= 4)) {
7989 prefix(REX);
7990 }
7991 } else {
7992 if (src_enc < 8) {
7993 prefix(REX_R);
7994 } else {
7995 prefix(REX_RB);
7996 src_enc -= 8;
7997 }
7998 dst_enc -= 8;
7999 }
8000 return dst_enc << 3 | src_enc;
8001 }
8002
8003 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) {
8004 if (dst_enc < 8) {
8005 if (src_enc < 8) {
8006 prefix(REX_W);
8007 } else {
8008 prefix(REX_WB);
8009 src_enc -= 8;
8010 }
8011 } else {
8012 if (src_enc < 8) {
8013 prefix(REX_WR);
8014 } else {
8015 prefix(REX_WRB);
8016 src_enc -= 8;
8017 }
8018 dst_enc -= 8;
8019 }
8020 return dst_enc << 3 | src_enc;
8021 }
8022
8023 void Assembler::prefix(Register reg) {
8024 if (reg->encoding() >= 8) {
8025 prefix(REX_B);
8026 }
8027 }
8028
8029 void Assembler::prefix(Register dst, Register src, Prefix p) {
8030 if (src->encoding() >= 8) {
8031 p = (Prefix)(p | REX_B);
8032 }
8033 if (dst->encoding() >= 8) {
8034 p = (Prefix)( p | REX_R);
8035 }
8036 if (p != Prefix_EMPTY) {
8037 // do not generate an empty prefix
8038 prefix(p);
8039 }
8040 }
8041
8042 void Assembler::prefix(Register dst, Address adr, Prefix p) {
8043 if (adr.base_needs_rex()) {
8044 if (adr.index_needs_rex()) {
8045 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X");
8046 } else {
8047 prefix(REX_B);
8048 }
8049 } else {
8050 if (adr.index_needs_rex()) {
8051 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X");
8052 }
8053 }
8054 if (dst->encoding() >= 8) {
8055 p = (Prefix)(p | REX_R);
8056 }
8057 if (p != Prefix_EMPTY) {
8058 // do not generate an empty prefix
8059 prefix(p);
8060 }
8061 }
8062
8063 void Assembler::prefix(Address adr) {
8064 if (adr.base_needs_rex()) {
8065 if (adr.index_needs_rex()) {
8066 prefix(REX_XB);
8067 } else {
8068 prefix(REX_B);
8069 }
8070 } else {
8071 if (adr.index_needs_rex()) {
8072 prefix(REX_X);
8073 }
8074 }
8075 }
8076
8077 void Assembler::prefixq(Address adr) {
8078 if (adr.base_needs_rex()) {
8079 if (adr.index_needs_rex()) {
8080 prefix(REX_WXB);
8081 } else {
8082 prefix(REX_WB);
8083 }
8084 } else {
8085 if (adr.index_needs_rex()) {
8086 prefix(REX_WX);
8087 } else {
8088 prefix(REX_W);
8089 }
8090 }
8091 }
8092
8093
8094 void Assembler::prefix(Address adr, Register reg, bool byteinst) {
8095 if (reg->encoding() < 8) {
8096 if (adr.base_needs_rex()) {
8097 if (adr.index_needs_rex()) {
8098 prefix(REX_XB);
8099 } else {
8100 prefix(REX_B);
8101 }
8102 } else {
8103 if (adr.index_needs_rex()) {
8104 prefix(REX_X);
8105 } else if (byteinst && reg->encoding() >= 4 ) {
8106 prefix(REX);
8107 }
8108 }
8109 } else {
8110 if (adr.base_needs_rex()) {
8111 if (adr.index_needs_rex()) {
8112 prefix(REX_RXB);
8113 } else {
8114 prefix(REX_RB);
8115 }
8116 } else {
8117 if (adr.index_needs_rex()) {
8118 prefix(REX_RX);
8119 } else {
8120 prefix(REX_R);
8121 }
8122 }
8123 }
8124 }
8125
8126 void Assembler::prefixq(Address adr, Register src) {
8127 if (src->encoding() < 8) {
8128 if (adr.base_needs_rex()) {
8129 if (adr.index_needs_rex()) {
8130 prefix(REX_WXB);
8131 } else {
8132 prefix(REX_WB);
8133 }
8134 } else {
8135 if (adr.index_needs_rex()) {
8136 prefix(REX_WX);
8137 } else {
8138 prefix(REX_W);
8139 }
8140 }
8141 } else {
8142 if (adr.base_needs_rex()) {
8143 if (adr.index_needs_rex()) {
8144 prefix(REX_WRXB);
8145 } else {
8146 prefix(REX_WRB);
8147 }
8148 } else {
8149 if (adr.index_needs_rex()) {
8150 prefix(REX_WRX);
8151 } else {
8152 prefix(REX_WR);
8153 }
8154 }
8155 }
8156 }
8157
8158 void Assembler::prefix(Address adr, XMMRegister reg) {
8159 if (reg->encoding() < 8) {
8160 if (adr.base_needs_rex()) {
8161 if (adr.index_needs_rex()) {
8162 prefix(REX_XB);
8163 } else {
8164 prefix(REX_B);
8165 }
8166 } else {
8167 if (adr.index_needs_rex()) {
8168 prefix(REX_X);
8169 }
8170 }
8171 } else {
8172 if (adr.base_needs_rex()) {
8173 if (adr.index_needs_rex()) {
8174 prefix(REX_RXB);
8175 } else {
8176 prefix(REX_RB);
8177 }
8178 } else {
8179 if (adr.index_needs_rex()) {
8180 prefix(REX_RX);
8181 } else {
8182 prefix(REX_R);
8183 }
8184 }
8185 }
8186 }
8187
8188 void Assembler::prefixq(Address adr, XMMRegister src) {
8189 if (src->encoding() < 8) {
8190 if (adr.base_needs_rex()) {
8191 if (adr.index_needs_rex()) {
8192 prefix(REX_WXB);
8193 } else {
8194 prefix(REX_WB);
8195 }
8196 } else {
8197 if (adr.index_needs_rex()) {
8198 prefix(REX_WX);
8199 } else {
8200 prefix(REX_W);
8201 }
8202 }
8203 } else {
8204 if (adr.base_needs_rex()) {
8205 if (adr.index_needs_rex()) {
8206 prefix(REX_WRXB);
8207 } else {
8208 prefix(REX_WRB);
8209 }
8210 } else {
8211 if (adr.index_needs_rex()) {
8212 prefix(REX_WRX);
8213 } else {
8214 prefix(REX_WR);
8215 }
8216 }
8217 }
8218 }
8219
8220 void Assembler::adcq(Register dst, int32_t imm32) {
8221 (void) prefixq_and_encode(dst->encoding());
8222 emit_arith(0x81, 0xD0, dst, imm32);
8223 }
8224
8225 void Assembler::adcq(Register dst, Address src) {
8226 InstructionMark im(this);
8227 prefixq(src, dst);
8228 emit_int8(0x13);
8229 emit_operand(dst, src);
8230 }
8231
8232 void Assembler::adcq(Register dst, Register src) {
8233 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8234 emit_arith(0x13, 0xC0, dst, src);
8235 }
8236
8237 void Assembler::addq(Address dst, int32_t imm32) {
8238 InstructionMark im(this);
8239 prefixq(dst);
8240 emit_arith_operand(0x81, rax, dst,imm32);
8241 }
8242
8243 void Assembler::addq(Address dst, Register src) {
8244 InstructionMark im(this);
8245 prefixq(dst, src);
8246 emit_int8(0x01);
8247 emit_operand(src, dst);
8248 }
8249
8250 void Assembler::addq(Register dst, int32_t imm32) {
8251 (void) prefixq_and_encode(dst->encoding());
8252 emit_arith(0x81, 0xC0, dst, imm32);
8253 }
8254
8255 void Assembler::addq(Register dst, Address src) {
8256 InstructionMark im(this);
8257 prefixq(src, dst);
8258 emit_int8(0x03);
8259 emit_operand(dst, src);
8260 }
8261
8262 void Assembler::addq(Register dst, Register src) {
8263 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8264 emit_arith(0x03, 0xC0, dst, src);
8265 }
8266
8267 void Assembler::adcxq(Register dst, Register src) {
8268 //assert(VM_Version::supports_adx(), "adx instructions not supported");
8269 emit_int8((unsigned char)0x66);
8270 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8271 emit_int8(0x0F);
8272 emit_int8(0x38);
8273 emit_int8((unsigned char)0xF6);
8274 emit_int8((unsigned char)(0xC0 | encode));
8275 }
8276
8277 void Assembler::adoxq(Register dst, Register src) {
8278 //assert(VM_Version::supports_adx(), "adx instructions not supported");
8279 emit_int8((unsigned char)0xF3);
8280 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8281 emit_int8(0x0F);
8282 emit_int8(0x38);
8283 emit_int8((unsigned char)0xF6);
8284 emit_int8((unsigned char)(0xC0 | encode));
8285 }
8286
8287 void Assembler::andq(Address dst, int32_t imm32) {
8288 InstructionMark im(this);
8289 prefixq(dst);
8290 emit_int8((unsigned char)0x81);
8291 emit_operand(rsp, dst, 4);
8292 emit_int32(imm32);
8293 }
8294
8295 void Assembler::andq(Register dst, int32_t imm32) {
8296 (void) prefixq_and_encode(dst->encoding());
8297 emit_arith(0x81, 0xE0, dst, imm32);
8298 }
8299
8300 void Assembler::andq(Register dst, Address src) {
8301 InstructionMark im(this);
8302 prefixq(src, dst);
8303 emit_int8(0x23);
8304 emit_operand(dst, src);
8305 }
8306
8307 void Assembler::andq(Register dst, Register src) {
8308 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8309 emit_arith(0x23, 0xC0, dst, src);
8310 }
8311
8312 void Assembler::andnq(Register dst, Register src1, Register src2) {
8313 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8314 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8315 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8316 emit_int8((unsigned char)0xF2);
8317 emit_int8((unsigned char)(0xC0 | encode));
8318 }
8319
8320 void Assembler::andnq(Register dst, Register src1, Address src2) {
8321 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8322 InstructionMark im(this);
8323 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8324 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8325 emit_int8((unsigned char)0xF2);
8326 emit_operand(dst, src2);
8327 }
8328
8329 void Assembler::bsfq(Register dst, Register src) {
8330 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8331 emit_int8(0x0F);
8332 emit_int8((unsigned char)0xBC);
8333 emit_int8((unsigned char)(0xC0 | encode));
8334 }
8335
8336 void Assembler::bsrq(Register dst, Register src) {
8337 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8338 emit_int8(0x0F);
8339 emit_int8((unsigned char)0xBD);
8340 emit_int8((unsigned char)(0xC0 | encode));
8341 }
8342
8343 void Assembler::bswapq(Register reg) {
8344 int encode = prefixq_and_encode(reg->encoding());
8345 emit_int8(0x0F);
8346 emit_int8((unsigned char)(0xC8 | encode));
8347 }
8348
8349 void Assembler::blsiq(Register dst, Register src) {
8350 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8351 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8352 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8353 emit_int8((unsigned char)0xF3);
8354 emit_int8((unsigned char)(0xC0 | encode));
8355 }
8356
8357 void Assembler::blsiq(Register dst, Address src) {
8358 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8359 InstructionMark im(this);
8360 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8361 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8362 emit_int8((unsigned char)0xF3);
8363 emit_operand(rbx, src);
8364 }
8365
8366 void Assembler::blsmskq(Register dst, Register src) {
8367 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8368 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8369 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8370 emit_int8((unsigned char)0xF3);
8371 emit_int8((unsigned char)(0xC0 | encode));
8372 }
8373
8374 void Assembler::blsmskq(Register dst, Address src) {
8375 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8376 InstructionMark im(this);
8377 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8378 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8379 emit_int8((unsigned char)0xF3);
8380 emit_operand(rdx, src);
8381 }
8382
8383 void Assembler::blsrq(Register dst, Register src) {
8384 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8385 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8386 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8387 emit_int8((unsigned char)0xF3);
8388 emit_int8((unsigned char)(0xC0 | encode));
8389 }
8390
8391 void Assembler::blsrq(Register dst, Address src) {
8392 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8393 InstructionMark im(this);
8394 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8395 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8396 emit_int8((unsigned char)0xF3);
8397 emit_operand(rcx, src);
8398 }
8399
8400 void Assembler::cdqq() {
8401 prefix(REX_W);
8402 emit_int8((unsigned char)0x99);
8403 }
8404
8405 void Assembler::clflush(Address adr) {
8406 prefix(adr);
8407 emit_int8(0x0F);
8408 emit_int8((unsigned char)0xAE);
8409 emit_operand(rdi, adr);
8410 }
8411
8412 void Assembler::cmovq(Condition cc, Register dst, Register src) {
8413 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8414 emit_int8(0x0F);
8415 emit_int8(0x40 | cc);
8416 emit_int8((unsigned char)(0xC0 | encode));
8417 }
8418
8419 void Assembler::cmovq(Condition cc, Register dst, Address src) {
8420 InstructionMark im(this);
8421 prefixq(src, dst);
8422 emit_int8(0x0F);
8423 emit_int8(0x40 | cc);
8424 emit_operand(dst, src);
8425 }
8426
8427 void Assembler::cmpq(Address dst, int32_t imm32) {
8428 InstructionMark im(this);
8429 prefixq(dst);
8430 emit_int8((unsigned char)0x81);
8431 emit_operand(rdi, dst, 4);
8432 emit_int32(imm32);
8433 }
8434
8435 void Assembler::cmpq(Register dst, int32_t imm32) {
8436 (void) prefixq_and_encode(dst->encoding());
8437 emit_arith(0x81, 0xF8, dst, imm32);
8438 }
8439
8440 void Assembler::cmpq(Address dst, Register src) {
8441 InstructionMark im(this);
8442 prefixq(dst, src);
8443 emit_int8(0x3B);
8444 emit_operand(src, dst);
8445 }
8446
8447 void Assembler::cmpq(Register dst, Register src) {
8448 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8449 emit_arith(0x3B, 0xC0, dst, src);
8450 }
8451
8452 void Assembler::cmpq(Register dst, Address src) {
8453 InstructionMark im(this);
8454 prefixq(src, dst);
8455 emit_int8(0x3B);
8456 emit_operand(dst, src);
8457 }
8458
8459 void Assembler::cmpxchgq(Register reg, Address adr) {
8460 InstructionMark im(this);
8461 prefixq(adr, reg);
8462 emit_int8(0x0F);
8463 emit_int8((unsigned char)0xB1);
8464 emit_operand(reg, adr);
8465 }
8466
8467 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
8468 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8469 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8470 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
8471 emit_int8(0x2A);
8472 emit_int8((unsigned char)(0xC0 | encode));
8473 }
8474
8475 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) {
8476 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8477 InstructionMark im(this);
8478 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8479 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
8480 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
8481 emit_int8(0x2A);
8482 emit_operand(dst, src);
8483 }
8484
8485 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) {
8486 NOT_LP64(assert(VM_Version::supports_sse(), ""));
8487 InstructionMark im(this);
8488 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8489 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
8490 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
8491 emit_int8(0x2A);
8492 emit_operand(dst, src);
8493 }
8494
8495 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
8496 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8497 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8498 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
8499 emit_int8(0x2C);
8500 emit_int8((unsigned char)(0xC0 | encode));
8501 }
8502
8503 void Assembler::cvttss2siq(Register dst, XMMRegister src) {
8504 NOT_LP64(assert(VM_Version::supports_sse(), ""));
8505 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8506 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
8507 emit_int8(0x2C);
8508 emit_int8((unsigned char)(0xC0 | encode));
8509 }
8510
8511 void Assembler::decl(Register dst) {
8512 // Don't use it directly. Use MacroAssembler::decrementl() instead.
8513 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
8514 int encode = prefix_and_encode(dst->encoding());
8515 emit_int8((unsigned char)0xFF);
8516 emit_int8((unsigned char)(0xC8 | encode));
8517 }
8518
8519 void Assembler::decq(Register dst) {
8520 // Don't use it directly. Use MacroAssembler::decrementq() instead.
8521 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
8522 int encode = prefixq_and_encode(dst->encoding());
8523 emit_int8((unsigned char)0xFF);
8524 emit_int8(0xC8 | encode);
8525 }
8526
8527 void Assembler::decq(Address dst) {
8528 // Don't use it directly. Use MacroAssembler::decrementq() instead.
8529 InstructionMark im(this);
8530 prefixq(dst);
8531 emit_int8((unsigned char)0xFF);
8532 emit_operand(rcx, dst);
8533 }
8534
8535 void Assembler::fxrstor(Address src) {
8536 prefixq(src);
8537 emit_int8(0x0F);
8538 emit_int8((unsigned char)0xAE);
8539 emit_operand(as_Register(1), src);
8540 }
8541
8542 void Assembler::xrstor(Address src) {
8543 prefixq(src);
8544 emit_int8(0x0F);
8545 emit_int8((unsigned char)0xAE);
8546 emit_operand(as_Register(5), src);
8547 }
8548
8549 void Assembler::fxsave(Address dst) {
8550 prefixq(dst);
8551 emit_int8(0x0F);
8552 emit_int8((unsigned char)0xAE);
8553 emit_operand(as_Register(0), dst);
8554 }
8555
8556 void Assembler::xsave(Address dst) {
8557 prefixq(dst);
8558 emit_int8(0x0F);
8559 emit_int8((unsigned char)0xAE);
8560 emit_operand(as_Register(4), dst);
8561 }
8562
8563 void Assembler::idivq(Register src) {
8564 int encode = prefixq_and_encode(src->encoding());
8565 emit_int8((unsigned char)0xF7);
8566 emit_int8((unsigned char)(0xF8 | encode));
8567 }
8568
8569 void Assembler::imulq(Register dst, Register src) {
8570 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8571 emit_int8(0x0F);
8572 emit_int8((unsigned char)0xAF);
8573 emit_int8((unsigned char)(0xC0 | encode));
8574 }
8575
8576 void Assembler::imulq(Register dst, Register src, int value) {
8577 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8578 if (is8bit(value)) {
8579 emit_int8(0x6B);
8580 emit_int8((unsigned char)(0xC0 | encode));
8581 emit_int8(value & 0xFF);
8582 } else {
8583 emit_int8(0x69);
8584 emit_int8((unsigned char)(0xC0 | encode));
8585 emit_int32(value);
8586 }
8587 }
8588
8589 void Assembler::imulq(Register dst, Address src) {
8590 InstructionMark im(this);
8591 prefixq(src, dst);
8592 emit_int8(0x0F);
8593 emit_int8((unsigned char) 0xAF);
8594 emit_operand(dst, src);
8595 }
8596
8597 void Assembler::incl(Register dst) {
8598 // Don't use it directly. Use MacroAssembler::incrementl() instead.
8599 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
8600 int encode = prefix_and_encode(dst->encoding());
8601 emit_int8((unsigned char)0xFF);
8602 emit_int8((unsigned char)(0xC0 | encode));
8603 }
8604
8605 void Assembler::incq(Register dst) {
8606 // Don't use it directly. Use MacroAssembler::incrementq() instead.
8607 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
8608 int encode = prefixq_and_encode(dst->encoding());
8609 emit_int8((unsigned char)0xFF);
8610 emit_int8((unsigned char)(0xC0 | encode));
8611 }
8612
8613 void Assembler::incq(Address dst) {
8614 // Don't use it directly. Use MacroAssembler::incrementq() instead.
8615 InstructionMark im(this);
8616 prefixq(dst);
8617 emit_int8((unsigned char)0xFF);
8618 emit_operand(rax, dst);
8619 }
8620
8621 void Assembler::lea(Register dst, Address src) {
8622 leaq(dst, src);
8623 }
8624
8625 void Assembler::leaq(Register dst, Address src) {
8626 InstructionMark im(this);
8627 prefixq(src, dst);
8628 emit_int8((unsigned char)0x8D);
8629 emit_operand(dst, src);
8630 }
8631
8632 void Assembler::mov64(Register dst, int64_t imm64) {
8633 InstructionMark im(this);
8634 int encode = prefixq_and_encode(dst->encoding());
8635 emit_int8((unsigned char)(0xB8 | encode));
8636 emit_int64(imm64);
8637 }
8638
8639 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) {
8640 InstructionMark im(this);
8641 int encode = prefixq_and_encode(dst->encoding());
8642 emit_int8(0xB8 | encode);
8643 emit_data64(imm64, rspec);
8644 }
8645
8646 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) {
8647 InstructionMark im(this);
8648 int encode = prefix_and_encode(dst->encoding());
8649 emit_int8((unsigned char)(0xB8 | encode));
8650 emit_data((int)imm32, rspec, narrow_oop_operand);
8651 }
8652
8653 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) {
8654 InstructionMark im(this);
8655 prefix(dst);
8656 emit_int8((unsigned char)0xC7);
8657 emit_operand(rax, dst, 4);
8658 emit_data((int)imm32, rspec, narrow_oop_operand);
8659 }
8660
8661 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) {
8662 InstructionMark im(this);
8663 int encode = prefix_and_encode(src1->encoding());
8664 emit_int8((unsigned char)0x81);
8665 emit_int8((unsigned char)(0xF8 | encode));
8666 emit_data((int)imm32, rspec, narrow_oop_operand);
8667 }
8668
8669 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) {
8670 InstructionMark im(this);
8671 prefix(src1);
8672 emit_int8((unsigned char)0x81);
8673 emit_operand(rax, src1, 4);
8674 emit_data((int)imm32, rspec, narrow_oop_operand);
8675 }
8676
8677 void Assembler::lzcntq(Register dst, Register src) {
8678 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
8679 emit_int8((unsigned char)0xF3);
8680 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8681 emit_int8(0x0F);
8682 emit_int8((unsigned char)0xBD);
8683 emit_int8((unsigned char)(0xC0 | encode));
8684 }
8685
8686 void Assembler::movdq(XMMRegister dst, Register src) {
8687 // table D-1 says MMX/SSE2
8688 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8689 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8690 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8691 emit_int8(0x6E);
8692 emit_int8((unsigned char)(0xC0 | encode));
8693 }
8694
8695 void Assembler::movdq(Register dst, XMMRegister src) {
8696 // table D-1 says MMX/SSE2
8697 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8698 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8699 // swap src/dst to get correct prefix
8700 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8701 emit_int8(0x7E);
8702 emit_int8((unsigned char)(0xC0 | encode));
8703 }
8704
8705 void Assembler::movq(Register dst, Register src) {
8706 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8707 emit_int8((unsigned char)0x8B);
8708 emit_int8((unsigned char)(0xC0 | encode));
8709 }
8710
8711 void Assembler::movq(Register dst, Address src) {
8712 InstructionMark im(this);
8713 prefixq(src, dst);
8714 emit_int8((unsigned char)0x8B);
8715 emit_operand(dst, src);
8716 }
8717
8718 void Assembler::movq(Address dst, Register src) {
8719 InstructionMark im(this);
8720 prefixq(dst, src);
8721 emit_int8((unsigned char)0x89);
8722 emit_operand(src, dst);
8723 }
8724
8725 void Assembler::movsbq(Register dst, Address src) {
8726 InstructionMark im(this);
8727 prefixq(src, dst);
8728 emit_int8(0x0F);
8729 emit_int8((unsigned char)0xBE);
8730 emit_operand(dst, src);
8731 }
8732
8733 void Assembler::movsbq(Register dst, Register src) {
8734 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8735 emit_int8(0x0F);
8736 emit_int8((unsigned char)0xBE);
8737 emit_int8((unsigned char)(0xC0 | encode));
8738 }
8739
8740 void Assembler::movslq(Register dst, int32_t imm32) {
8741 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx)
8742 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx)
8743 // as a result we shouldn't use until tested at runtime...
8744 ShouldNotReachHere();
8745 InstructionMark im(this);
8746 int encode = prefixq_and_encode(dst->encoding());
8747 emit_int8((unsigned char)(0xC7 | encode));
8748 emit_int32(imm32);
8749 }
8750
8751 void Assembler::movslq(Address dst, int32_t imm32) {
8752 assert(is_simm32(imm32), "lost bits");
8753 InstructionMark im(this);
8754 prefixq(dst);
8755 emit_int8((unsigned char)0xC7);
8756 emit_operand(rax, dst, 4);
8757 emit_int32(imm32);
8758 }
8759
8760 void Assembler::movslq(Register dst, Address src) {
8761 InstructionMark im(this);
8762 prefixq(src, dst);
8763 emit_int8(0x63);
8764 emit_operand(dst, src);
8765 }
8766
8767 void Assembler::movslq(Register dst, Register src) {
8768 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8769 emit_int8(0x63);
8770 emit_int8((unsigned char)(0xC0 | encode));
8771 }
8772
8773 void Assembler::movswq(Register dst, Address src) {
8774 InstructionMark im(this);
8775 prefixq(src, dst);
8776 emit_int8(0x0F);
8777 emit_int8((unsigned char)0xBF);
8778 emit_operand(dst, src);
8779 }
8780
8781 void Assembler::movswq(Register dst, Register src) {
8782 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8783 emit_int8((unsigned char)0x0F);
8784 emit_int8((unsigned char)0xBF);
8785 emit_int8((unsigned char)(0xC0 | encode));
8786 }
8787
8788 void Assembler::movzbq(Register dst, Address src) {
8789 InstructionMark im(this);
8790 prefixq(src, dst);
8791 emit_int8((unsigned char)0x0F);
8792 emit_int8((unsigned char)0xB6);
8793 emit_operand(dst, src);
8794 }
8795
8796 void Assembler::movzbq(Register dst, Register src) {
8797 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8798 emit_int8(0x0F);
8799 emit_int8((unsigned char)0xB6);
8800 emit_int8(0xC0 | encode);
8801 }
8802
8803 void Assembler::movzwq(Register dst, Address src) {
8804 InstructionMark im(this);
8805 prefixq(src, dst);
8806 emit_int8((unsigned char)0x0F);
8807 emit_int8((unsigned char)0xB7);
8808 emit_operand(dst, src);
8809 }
8810
8811 void Assembler::movzwq(Register dst, Register src) {
8812 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8813 emit_int8((unsigned char)0x0F);
8814 emit_int8((unsigned char)0xB7);
8815 emit_int8((unsigned char)(0xC0 | encode));
8816 }
8817
8818 void Assembler::mulq(Address src) {
8819 InstructionMark im(this);
8820 prefixq(src);
8821 emit_int8((unsigned char)0xF7);
8822 emit_operand(rsp, src);
8823 }
8824
8825 void Assembler::mulq(Register src) {
8826 int encode = prefixq_and_encode(src->encoding());
8827 emit_int8((unsigned char)0xF7);
8828 emit_int8((unsigned char)(0xE0 | encode));
8829 }
8830
8831 void Assembler::mulxq(Register dst1, Register dst2, Register src) {
8832 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
8833 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8834 int encode = vex_prefix_and_encode(dst1->encoding(), dst2->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
8835 emit_int8((unsigned char)0xF6);
8836 emit_int8((unsigned char)(0xC0 | encode));
8837 }
8838
8839 void Assembler::negq(Register dst) {
8840 int encode = prefixq_and_encode(dst->encoding());
8841 emit_int8((unsigned char)0xF7);
8842 emit_int8((unsigned char)(0xD8 | encode));
8843 }
8844
8845 void Assembler::notq(Register dst) {
8846 int encode = prefixq_and_encode(dst->encoding());
8847 emit_int8((unsigned char)0xF7);
8848 emit_int8((unsigned char)(0xD0 | encode));
8849 }
8850
8851 void Assembler::orq(Address dst, int32_t imm32) {
8852 InstructionMark im(this);
8853 prefixq(dst);
8854 emit_int8((unsigned char)0x81);
8855 emit_operand(rcx, dst, 4);
8856 emit_int32(imm32);
8857 }
8858
8859 void Assembler::orq(Register dst, int32_t imm32) {
8860 (void) prefixq_and_encode(dst->encoding());
8861 emit_arith(0x81, 0xC8, dst, imm32);
8862 }
8863
8864 void Assembler::orq(Register dst, Address src) {
8865 InstructionMark im(this);
8866 prefixq(src, dst);
8867 emit_int8(0x0B);
8868 emit_operand(dst, src);
8869 }
8870
8871 void Assembler::orq(Register dst, Register src) {
8872 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8873 emit_arith(0x0B, 0xC0, dst, src);
8874 }
8875
8876 void Assembler::popa() { // 64bit
8877 movq(r15, Address(rsp, 0));
8878 movq(r14, Address(rsp, wordSize));
8879 movq(r13, Address(rsp, 2 * wordSize));
8880 movq(r12, Address(rsp, 3 * wordSize));
8881 movq(r11, Address(rsp, 4 * wordSize));
8882 movq(r10, Address(rsp, 5 * wordSize));
8883 movq(r9, Address(rsp, 6 * wordSize));
8884 movq(r8, Address(rsp, 7 * wordSize));
8885 movq(rdi, Address(rsp, 8 * wordSize));
8886 movq(rsi, Address(rsp, 9 * wordSize));
8887 movq(rbp, Address(rsp, 10 * wordSize));
8888 // skip rsp
8889 movq(rbx, Address(rsp, 12 * wordSize));
8890 movq(rdx, Address(rsp, 13 * wordSize));
8891 movq(rcx, Address(rsp, 14 * wordSize));
8892 movq(rax, Address(rsp, 15 * wordSize));
8893
8894 addq(rsp, 16 * wordSize);
8895 }
8896
8897 void Assembler::popcntq(Register dst, Address src) {
8898 assert(VM_Version::supports_popcnt(), "must support");
8899 InstructionMark im(this);
8900 emit_int8((unsigned char)0xF3);
8901 prefixq(src, dst);
8902 emit_int8((unsigned char)0x0F);
8903 emit_int8((unsigned char)0xB8);
8904 emit_operand(dst, src);
8905 }
8906
8907 void Assembler::popcntq(Register dst, Register src) {
8908 assert(VM_Version::supports_popcnt(), "must support");
8909 emit_int8((unsigned char)0xF3);
8910 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8911 emit_int8((unsigned char)0x0F);
8912 emit_int8((unsigned char)0xB8);
8913 emit_int8((unsigned char)(0xC0 | encode));
8914 }
8915
8916 void Assembler::popq(Address dst) {
8917 InstructionMark im(this);
8918 prefixq(dst);
8919 emit_int8((unsigned char)0x8F);
8920 emit_operand(rax, dst);
8921 }
8922
8923 void Assembler::pusha() { // 64bit
8924 // we have to store original rsp. ABI says that 128 bytes
8925 // below rsp are local scratch.
8926 movq(Address(rsp, -5 * wordSize), rsp);
8927
8928 subq(rsp, 16 * wordSize);
8929
8930 movq(Address(rsp, 15 * wordSize), rax);
8931 movq(Address(rsp, 14 * wordSize), rcx);
8932 movq(Address(rsp, 13 * wordSize), rdx);
8933 movq(Address(rsp, 12 * wordSize), rbx);
8934 // skip rsp
8935 movq(Address(rsp, 10 * wordSize), rbp);
8936 movq(Address(rsp, 9 * wordSize), rsi);
8937 movq(Address(rsp, 8 * wordSize), rdi);
8938 movq(Address(rsp, 7 * wordSize), r8);
8939 movq(Address(rsp, 6 * wordSize), r9);
8940 movq(Address(rsp, 5 * wordSize), r10);
8941 movq(Address(rsp, 4 * wordSize), r11);
8942 movq(Address(rsp, 3 * wordSize), r12);
8943 movq(Address(rsp, 2 * wordSize), r13);
8944 movq(Address(rsp, wordSize), r14);
8945 movq(Address(rsp, 0), r15);
8946 }
8947
8948 void Assembler::pushq(Address src) {
8949 InstructionMark im(this);
8950 prefixq(src);
8951 emit_int8((unsigned char)0xFF);
8952 emit_operand(rsi, src);
8953 }
8954
8955 void Assembler::rclq(Register dst, int imm8) {
8956 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8957 int encode = prefixq_and_encode(dst->encoding());
8958 if (imm8 == 1) {
8959 emit_int8((unsigned char)0xD1);
8960 emit_int8((unsigned char)(0xD0 | encode));
8961 } else {
8962 emit_int8((unsigned char)0xC1);
8963 emit_int8((unsigned char)(0xD0 | encode));
8964 emit_int8(imm8);
8965 }
8966 }
8967
8968 void Assembler::rcrq(Register dst, int imm8) {
8969 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8970 int encode = prefixq_and_encode(dst->encoding());
8971 if (imm8 == 1) {
8972 emit_int8((unsigned char)0xD1);
8973 emit_int8((unsigned char)(0xD8 | encode));
8974 } else {
8975 emit_int8((unsigned char)0xC1);
8976 emit_int8((unsigned char)(0xD8 | encode));
8977 emit_int8(imm8);
8978 }
8979 }
8980
8981 void Assembler::rorq(Register dst, int imm8) {
8982 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8983 int encode = prefixq_and_encode(dst->encoding());
8984 if (imm8 == 1) {
8985 emit_int8((unsigned char)0xD1);
8986 emit_int8((unsigned char)(0xC8 | encode));
8987 } else {
8988 emit_int8((unsigned char)0xC1);
8989 emit_int8((unsigned char)(0xc8 | encode));
8990 emit_int8(imm8);
8991 }
8992 }
8993
8994 void Assembler::rorxq(Register dst, Register src, int imm8) {
8995 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
8996 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8997 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes);
8998 emit_int8((unsigned char)0xF0);
8999 emit_int8((unsigned char)(0xC0 | encode));
9000 emit_int8(imm8);
9001 }
9002
9003 void Assembler::rorxd(Register dst, Register src, int imm8) {
9004 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
9005 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
9006 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes);
9007 emit_int8((unsigned char)0xF0);
9008 emit_int8((unsigned char)(0xC0 | encode));
9009 emit_int8(imm8);
9010 }
9011
9012 void Assembler::sarq(Register dst, int imm8) {
9013 assert(isShiftCount(imm8 >> 1), "illegal shift count");
9014 int encode = prefixq_and_encode(dst->encoding());
9015 if (imm8 == 1) {
9016 emit_int8((unsigned char)0xD1);
9017 emit_int8((unsigned char)(0xF8 | encode));
9018 } else {
9019 emit_int8((unsigned char)0xC1);
9020 emit_int8((unsigned char)(0xF8 | encode));
9021 emit_int8(imm8);
9022 }
9023 }
9024
9025 void Assembler::sarq(Register dst) {
9026 int encode = prefixq_and_encode(dst->encoding());
9027 emit_int8((unsigned char)0xD3);
9028 emit_int8((unsigned char)(0xF8 | encode));
9029 }
9030
9031 void Assembler::sbbq(Address dst, int32_t imm32) {
9032 InstructionMark im(this);
9033 prefixq(dst);
9034 emit_arith_operand(0x81, rbx, dst, imm32);
9035 }
9036
9037 void Assembler::sbbq(Register dst, int32_t imm32) {
9038 (void) prefixq_and_encode(dst->encoding());
9039 emit_arith(0x81, 0xD8, dst, imm32);
9040 }
9041
9042 void Assembler::sbbq(Register dst, Address src) {
9043 InstructionMark im(this);
9044 prefixq(src, dst);
9045 emit_int8(0x1B);
9046 emit_operand(dst, src);
9047 }
9048
9049 void Assembler::sbbq(Register dst, Register src) {
9050 (void) prefixq_and_encode(dst->encoding(), src->encoding());
9051 emit_arith(0x1B, 0xC0, dst, src);
9052 }
9053
9054 void Assembler::shlq(Register dst, int imm8) {
9055 assert(isShiftCount(imm8 >> 1), "illegal shift count");
9056 int encode = prefixq_and_encode(dst->encoding());
9057 if (imm8 == 1) {
9058 emit_int8((unsigned char)0xD1);
9059 emit_int8((unsigned char)(0xE0 | encode));
9060 } else {
9061 emit_int8((unsigned char)0xC1);
9062 emit_int8((unsigned char)(0xE0 | encode));
9063 emit_int8(imm8);
9064 }
9065 }
9066
9067 void Assembler::shlq(Register dst) {
9068 int encode = prefixq_and_encode(dst->encoding());
9069 emit_int8((unsigned char)0xD3);
9070 emit_int8((unsigned char)(0xE0 | encode));
9071 }
9072
9073 void Assembler::shrq(Register dst, int imm8) {
9074 assert(isShiftCount(imm8 >> 1), "illegal shift count");
9075 int encode = prefixq_and_encode(dst->encoding());
9076 emit_int8((unsigned char)0xC1);
9077 emit_int8((unsigned char)(0xE8 | encode));
9078 emit_int8(imm8);
9079 }
9080
9081 void Assembler::shrq(Register dst) {
9082 int encode = prefixq_and_encode(dst->encoding());
9083 emit_int8((unsigned char)0xD3);
9084 emit_int8(0xE8 | encode);
9085 }
9086
9087 void Assembler::subq(Address dst, int32_t imm32) {
9088 InstructionMark im(this);
9089 prefixq(dst);
9090 emit_arith_operand(0x81, rbp, dst, imm32);
9091 }
9092
9093 void Assembler::subq(Address dst, Register src) {
9094 InstructionMark im(this);
9095 prefixq(dst, src);
9096 emit_int8(0x29);
9097 emit_operand(src, dst);
9098 }
9099
9100 void Assembler::subq(Register dst, int32_t imm32) {
9101 (void) prefixq_and_encode(dst->encoding());
9102 emit_arith(0x81, 0xE8, dst, imm32);
9103 }
9104
9105 // Force generation of a 4 byte immediate value even if it fits into 8bit
9106 void Assembler::subq_imm32(Register dst, int32_t imm32) {
9107 (void) prefixq_and_encode(dst->encoding());
9108 emit_arith_imm32(0x81, 0xE8, dst, imm32);
9109 }
9110
9111 void Assembler::subq(Register dst, Address src) {
9112 InstructionMark im(this);
9113 prefixq(src, dst);
9114 emit_int8(0x2B);
9115 emit_operand(dst, src);
9116 }
9117
9118 void Assembler::subq(Register dst, Register src) {
9119 (void) prefixq_and_encode(dst->encoding(), src->encoding());
9120 emit_arith(0x2B, 0xC0, dst, src);
9121 }
9122
9123 void Assembler::testq(Register dst, int32_t imm32) {
9124 // not using emit_arith because test
9125 // doesn't support sign-extension of
9126 // 8bit operands
9127 int encode = dst->encoding();
9128 if (encode == 0) {
9129 prefix(REX_W);
9130 emit_int8((unsigned char)0xA9);
9131 } else {
9132 encode = prefixq_and_encode(encode);
9133 emit_int8((unsigned char)0xF7);
9134 emit_int8((unsigned char)(0xC0 | encode));
9135 }
9136 emit_int32(imm32);
9137 }
9138
9139 void Assembler::testq(Register dst, Register src) {
9140 (void) prefixq_and_encode(dst->encoding(), src->encoding());
9141 emit_arith(0x85, 0xC0, dst, src);
9142 }
9143
9144 void Assembler::testq(Register dst, Address src) {
9145 InstructionMark im(this);
9146 prefixq(src, dst);
9147 emit_int8((unsigned char)0x85);
9148 emit_operand(dst, src);
9149 }
9150
9151 void Assembler::xaddq(Address dst, Register src) {
9152 InstructionMark im(this);
9153 prefixq(dst, src);
9154 emit_int8(0x0F);
9155 emit_int8((unsigned char)0xC1);
9156 emit_operand(src, dst);
9157 }
9158
9159 void Assembler::xchgq(Register dst, Address src) {
9160 InstructionMark im(this);
9161 prefixq(src, dst);
9162 emit_int8((unsigned char)0x87);
9163 emit_operand(dst, src);
9164 }
9165
9166 void Assembler::xchgq(Register dst, Register src) {
9167 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
9168 emit_int8((unsigned char)0x87);
9169 emit_int8((unsigned char)(0xc0 | encode));
9170 }
9171
9172 void Assembler::xorq(Register dst, Register src) {
9173 (void) prefixq_and_encode(dst->encoding(), src->encoding());
9174 emit_arith(0x33, 0xC0, dst, src);
9175 }
9176
9177 void Assembler::xorq(Register dst, Address src) {
9178 InstructionMark im(this);
9179 prefixq(src, dst);
9180 emit_int8(0x33);
9181 emit_operand(dst, src);
9182 }
9183
9184 #endif // !LP64