1 /*
2 * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "jvm.h"
27 #include "asm/assembler.hpp"
28 #include "asm/assembler.inline.hpp"
29 #include "compiler/disassembler.hpp"
30 #include "gc/shared/barrierSet.hpp"
31 #include "gc/shared/barrierSetAssembler.hpp"
32 #include "gc/shared/collectedHeap.inline.hpp"
33 #include "interpreter/interpreter.hpp"
34 #include "memory/resourceArea.hpp"
35 #include "memory/universe.hpp"
36 #include "oops/access.hpp"
37 #include "oops/klass.inline.hpp"
38 #include "prims/methodHandles.hpp"
39 #include "runtime/biasedLocking.hpp"
40 #include "runtime/interfaceSupport.inline.hpp"
41 #include "runtime/objectMonitor.hpp"
42 #include "runtime/os.hpp"
43 #include "runtime/safepoint.hpp"
44 #include "runtime/safepointMechanism.hpp"
45 #include "runtime/sharedRuntime.hpp"
46 #include "runtime/stubRoutines.hpp"
47 #include "runtime/thread.hpp"
48 #include "utilities/macros.hpp"
49 #include "crc32c.h"
50 #ifdef COMPILER2
51 #include "opto/intrinsicnode.hpp"
52 #endif
53
54 #ifdef PRODUCT
55 #define BLOCK_COMMENT(str) /* nothing */
56 #define STOP(error) stop(error)
57 #else
58 #define BLOCK_COMMENT(str) block_comment(str)
59 #define STOP(error) block_comment(error); stop(error)
60 #endif
61
62 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
63
64 #ifdef ASSERT
65 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
66 #endif
67
68 static Assembler::Condition reverse[] = {
69 Assembler::noOverflow /* overflow = 0x0 */ ,
70 Assembler::overflow /* noOverflow = 0x1 */ ,
71 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
72 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
73 Assembler::notZero /* zero = 0x4, equal = 0x4 */ ,
74 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ ,
75 Assembler::above /* belowEqual = 0x6 */ ,
76 Assembler::belowEqual /* above = 0x7 */ ,
77 Assembler::positive /* negative = 0x8 */ ,
78 Assembler::negative /* positive = 0x9 */ ,
79 Assembler::noParity /* parity = 0xa */ ,
80 Assembler::parity /* noParity = 0xb */ ,
81 Assembler::greaterEqual /* less = 0xc */ ,
82 Assembler::less /* greaterEqual = 0xd */ ,
83 Assembler::greater /* lessEqual = 0xe */ ,
84 Assembler::lessEqual /* greater = 0xf, */
85
86 };
87
88
89 // Implementation of MacroAssembler
90
91 // First all the versions that have distinct versions depending on 32/64 bit
92 // Unless the difference is trivial (1 line or so).
93
94 #ifndef _LP64
95
96 // 32bit versions
97
98 Address MacroAssembler::as_Address(AddressLiteral adr) {
99 return Address(adr.target(), adr.rspec());
100 }
101
102 Address MacroAssembler::as_Address(ArrayAddress adr) {
103 return Address::make_array(adr);
104 }
105
106 void MacroAssembler::call_VM_leaf_base(address entry_point,
107 int number_of_arguments) {
108 call(RuntimeAddress(entry_point));
109 increment(rsp, number_of_arguments * wordSize);
110 }
111
112 void MacroAssembler::cmpklass(Address src1, Metadata* obj) {
113 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
114 }
115
116 void MacroAssembler::cmpklass(Register src1, Metadata* obj) {
117 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
118 }
119
120 void MacroAssembler::cmpoop(Address src1, jobject obj) {
121 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
122 }
123
124 void MacroAssembler::cmpoop(Register src1, jobject obj) {
125 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
126 }
127
128 void MacroAssembler::extend_sign(Register hi, Register lo) {
129 // According to Intel Doc. AP-526, "Integer Divide", p.18.
130 if (VM_Version::is_P6() && hi == rdx && lo == rax) {
131 cdql();
132 } else {
133 movl(hi, lo);
134 sarl(hi, 31);
135 }
136 }
137
138 void MacroAssembler::jC2(Register tmp, Label& L) {
139 // set parity bit if FPU flag C2 is set (via rax)
140 save_rax(tmp);
141 fwait(); fnstsw_ax();
142 sahf();
143 restore_rax(tmp);
144 // branch
145 jcc(Assembler::parity, L);
146 }
147
148 void MacroAssembler::jnC2(Register tmp, Label& L) {
149 // set parity bit if FPU flag C2 is set (via rax)
150 save_rax(tmp);
151 fwait(); fnstsw_ax();
152 sahf();
153 restore_rax(tmp);
154 // branch
155 jcc(Assembler::noParity, L);
156 }
157
158 // 32bit can do a case table jump in one instruction but we no longer allow the base
159 // to be installed in the Address class
160 void MacroAssembler::jump(ArrayAddress entry) {
161 jmp(as_Address(entry));
162 }
163
164 // Note: y_lo will be destroyed
165 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
166 // Long compare for Java (semantics as described in JVM spec.)
167 Label high, low, done;
168
169 cmpl(x_hi, y_hi);
170 jcc(Assembler::less, low);
171 jcc(Assembler::greater, high);
172 // x_hi is the return register
173 xorl(x_hi, x_hi);
174 cmpl(x_lo, y_lo);
175 jcc(Assembler::below, low);
176 jcc(Assembler::equal, done);
177
178 bind(high);
179 xorl(x_hi, x_hi);
180 increment(x_hi);
181 jmp(done);
182
183 bind(low);
184 xorl(x_hi, x_hi);
185 decrementl(x_hi);
186
187 bind(done);
188 }
189
190 void MacroAssembler::lea(Register dst, AddressLiteral src) {
191 mov_literal32(dst, (int32_t)src.target(), src.rspec());
192 }
193
194 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
195 // leal(dst, as_Address(adr));
196 // see note in movl as to why we must use a move
197 mov_literal32(dst, (int32_t) adr.target(), adr.rspec());
198 }
199
200 void MacroAssembler::leave() {
201 mov(rsp, rbp);
202 pop(rbp);
203 }
204
205 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
206 // Multiplication of two Java long values stored on the stack
207 // as illustrated below. Result is in rdx:rax.
208 //
209 // rsp ---> [ ?? ] \ \
210 // .... | y_rsp_offset |
211 // [ y_lo ] / (in bytes) | x_rsp_offset
212 // [ y_hi ] | (in bytes)
213 // .... |
214 // [ x_lo ] /
215 // [ x_hi ]
216 // ....
217 //
218 // Basic idea: lo(result) = lo(x_lo * y_lo)
219 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
220 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
221 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
222 Label quick;
223 // load x_hi, y_hi and check if quick
224 // multiplication is possible
225 movl(rbx, x_hi);
226 movl(rcx, y_hi);
227 movl(rax, rbx);
228 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0
229 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply
230 // do full multiplication
231 // 1st step
232 mull(y_lo); // x_hi * y_lo
233 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx,
234 // 2nd step
235 movl(rax, x_lo);
236 mull(rcx); // x_lo * y_hi
237 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx,
238 // 3rd step
239 bind(quick); // note: rbx, = 0 if quick multiply!
240 movl(rax, x_lo);
241 mull(y_lo); // x_lo * y_lo
242 addl(rdx, rbx); // correct hi(x_lo * y_lo)
243 }
244
245 void MacroAssembler::lneg(Register hi, Register lo) {
246 negl(lo);
247 adcl(hi, 0);
248 negl(hi);
249 }
250
251 void MacroAssembler::lshl(Register hi, Register lo) {
252 // Java shift left long support (semantics as described in JVM spec., p.305)
253 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
254 // shift value is in rcx !
255 assert(hi != rcx, "must not use rcx");
256 assert(lo != rcx, "must not use rcx");
257 const Register s = rcx; // shift count
258 const int n = BitsPerWord;
259 Label L;
260 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
261 cmpl(s, n); // if (s < n)
262 jcc(Assembler::less, L); // else (s >= n)
263 movl(hi, lo); // x := x << n
264 xorl(lo, lo);
265 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
266 bind(L); // s (mod n) < n
267 shldl(hi, lo); // x := x << s
268 shll(lo);
269 }
270
271
272 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
273 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
274 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
275 assert(hi != rcx, "must not use rcx");
276 assert(lo != rcx, "must not use rcx");
277 const Register s = rcx; // shift count
278 const int n = BitsPerWord;
279 Label L;
280 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
281 cmpl(s, n); // if (s < n)
282 jcc(Assembler::less, L); // else (s >= n)
283 movl(lo, hi); // x := x >> n
284 if (sign_extension) sarl(hi, 31);
285 else xorl(hi, hi);
286 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
287 bind(L); // s (mod n) < n
288 shrdl(lo, hi); // x := x >> s
289 if (sign_extension) sarl(hi);
290 else shrl(hi);
291 }
292
293 void MacroAssembler::movoop(Register dst, jobject obj) {
294 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
295 }
296
297 void MacroAssembler::movoop(Address dst, jobject obj) {
298 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
299 }
300
301 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
302 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
303 }
304
305 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
306 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
307 }
308
309 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
310 // scratch register is not used,
311 // it is defined to match parameters of 64-bit version of this method.
312 if (src.is_lval()) {
313 mov_literal32(dst, (intptr_t)src.target(), src.rspec());
314 } else {
315 movl(dst, as_Address(src));
316 }
317 }
318
319 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
320 movl(as_Address(dst), src);
321 }
322
323 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
324 movl(dst, as_Address(src));
325 }
326
327 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
328 void MacroAssembler::movptr(Address dst, intptr_t src) {
329 movl(dst, src);
330 }
331
332
333 void MacroAssembler::pop_callee_saved_registers() {
334 pop(rcx);
335 pop(rdx);
336 pop(rdi);
337 pop(rsi);
338 }
339
340 void MacroAssembler::pop_fTOS() {
341 fld_d(Address(rsp, 0));
342 addl(rsp, 2 * wordSize);
343 }
344
345 void MacroAssembler::push_callee_saved_registers() {
346 push(rsi);
347 push(rdi);
348 push(rdx);
349 push(rcx);
350 }
351
352 void MacroAssembler::push_fTOS() {
353 subl(rsp, 2 * wordSize);
354 fstp_d(Address(rsp, 0));
355 }
356
357
358 void MacroAssembler::pushoop(jobject obj) {
359 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
360 }
361
362 void MacroAssembler::pushklass(Metadata* obj) {
363 push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate());
364 }
365
366 void MacroAssembler::pushptr(AddressLiteral src) {
367 if (src.is_lval()) {
368 push_literal32((int32_t)src.target(), src.rspec());
369 } else {
370 pushl(as_Address(src));
371 }
372 }
373
374 void MacroAssembler::set_word_if_not_zero(Register dst) {
375 xorl(dst, dst);
376 set_byte_if_not_zero(dst);
377 }
378
379 static void pass_arg0(MacroAssembler* masm, Register arg) {
380 masm->push(arg);
381 }
382
383 static void pass_arg1(MacroAssembler* masm, Register arg) {
384 masm->push(arg);
385 }
386
387 static void pass_arg2(MacroAssembler* masm, Register arg) {
388 masm->push(arg);
389 }
390
391 static void pass_arg3(MacroAssembler* masm, Register arg) {
392 masm->push(arg);
393 }
394
395 #ifndef PRODUCT
396 extern "C" void findpc(intptr_t x);
397 #endif
398
399 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
400 // In order to get locks to work, we need to fake a in_VM state
401 JavaThread* thread = JavaThread::current();
402 JavaThreadState saved_state = thread->thread_state();
403 thread->set_thread_state(_thread_in_vm);
404 if (ShowMessageBoxOnError) {
405 JavaThread* thread = JavaThread::current();
406 JavaThreadState saved_state = thread->thread_state();
407 thread->set_thread_state(_thread_in_vm);
408 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
409 ttyLocker ttyl;
410 BytecodeCounter::print();
411 }
412 // To see where a verify_oop failed, get $ebx+40/X for this frame.
413 // This is the value of eip which points to where verify_oop will return.
414 if (os::message_box(msg, "Execution stopped, print registers?")) {
415 print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip);
416 BREAKPOINT;
417 }
418 } else {
419 ttyLocker ttyl;
420 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg);
421 }
422 // Don't assert holding the ttyLock
423 assert(false, "DEBUG MESSAGE: %s", msg);
424 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
425 }
426
427 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) {
428 ttyLocker ttyl;
429 FlagSetting fs(Debugging, true);
430 tty->print_cr("eip = 0x%08x", eip);
431 #ifndef PRODUCT
432 if ((WizardMode || Verbose) && PrintMiscellaneous) {
433 tty->cr();
434 findpc(eip);
435 tty->cr();
436 }
437 #endif
438 #define PRINT_REG(rax) \
439 { tty->print("%s = ", #rax); os::print_location(tty, rax); }
440 PRINT_REG(rax);
441 PRINT_REG(rbx);
442 PRINT_REG(rcx);
443 PRINT_REG(rdx);
444 PRINT_REG(rdi);
445 PRINT_REG(rsi);
446 PRINT_REG(rbp);
447 PRINT_REG(rsp);
448 #undef PRINT_REG
449 // Print some words near top of staack.
450 int* dump_sp = (int*) rsp;
451 for (int col1 = 0; col1 < 8; col1++) {
452 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
453 os::print_location(tty, *dump_sp++);
454 }
455 for (int row = 0; row < 16; row++) {
456 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
457 for (int col = 0; col < 8; col++) {
458 tty->print(" 0x%08x", *dump_sp++);
459 }
460 tty->cr();
461 }
462 // Print some instructions around pc:
463 Disassembler::decode((address)eip-64, (address)eip);
464 tty->print_cr("--------");
465 Disassembler::decode((address)eip, (address)eip+32);
466 }
467
468 void MacroAssembler::stop(const char* msg) {
469 ExternalAddress message((address)msg);
470 // push address of message
471 pushptr(message.addr());
472 { Label L; call(L, relocInfo::none); bind(L); } // push eip
473 pusha(); // push registers
474 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
475 hlt();
476 }
477
478 void MacroAssembler::warn(const char* msg) {
479 push_CPU_state();
480
481 ExternalAddress message((address) msg);
482 // push address of message
483 pushptr(message.addr());
484
485 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
486 addl(rsp, wordSize); // discard argument
487 pop_CPU_state();
488 }
489
490 void MacroAssembler::print_state() {
491 { Label L; call(L, relocInfo::none); bind(L); } // push eip
492 pusha(); // push registers
493
494 push_CPU_state();
495 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32)));
496 pop_CPU_state();
497
498 popa();
499 addl(rsp, wordSize);
500 }
501
502 #else // _LP64
503
504 // 64 bit versions
505
506 Address MacroAssembler::as_Address(AddressLiteral adr) {
507 // amd64 always does this as a pc-rel
508 // we can be absolute or disp based on the instruction type
509 // jmp/call are displacements others are absolute
510 assert(!adr.is_lval(), "must be rval");
511 assert(reachable(adr), "must be");
512 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc());
513
514 }
515
516 Address MacroAssembler::as_Address(ArrayAddress adr) {
517 AddressLiteral base = adr.base();
518 lea(rscratch1, base);
519 Address index = adr.index();
520 assert(index._disp == 0, "must not have disp"); // maybe it can?
521 Address array(rscratch1, index._index, index._scale, index._disp);
522 return array;
523 }
524
525 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
526 Label L, E;
527
528 #ifdef _WIN64
529 // Windows always allocates space for it's register args
530 assert(num_args <= 4, "only register arguments supported");
531 subq(rsp, frame::arg_reg_save_area_bytes);
532 #endif
533
534 // Align stack if necessary
535 testl(rsp, 15);
536 jcc(Assembler::zero, L);
537
538 subq(rsp, 8);
539 {
540 call(RuntimeAddress(entry_point));
541 }
542 addq(rsp, 8);
543 jmp(E);
544
545 bind(L);
546 {
547 call(RuntimeAddress(entry_point));
548 }
549
550 bind(E);
551
552 #ifdef _WIN64
553 // restore stack pointer
554 addq(rsp, frame::arg_reg_save_area_bytes);
555 #endif
556
557 }
558
559 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) {
560 assert(!src2.is_lval(), "should use cmpptr");
561
562 if (reachable(src2)) {
563 cmpq(src1, as_Address(src2));
564 } else {
565 lea(rscratch1, src2);
566 Assembler::cmpq(src1, Address(rscratch1, 0));
567 }
568 }
569
570 int MacroAssembler::corrected_idivq(Register reg) {
571 // Full implementation of Java ldiv and lrem; checks for special
572 // case as described in JVM spec., p.243 & p.271. The function
573 // returns the (pc) offset of the idivl instruction - may be needed
574 // for implicit exceptions.
575 //
576 // normal case special case
577 //
578 // input : rax: dividend min_long
579 // reg: divisor (may not be eax/edx) -1
580 //
581 // output: rax: quotient (= rax idiv reg) min_long
582 // rdx: remainder (= rax irem reg) 0
583 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
584 static const int64_t min_long = 0x8000000000000000;
585 Label normal_case, special_case;
586
587 // check for special case
588 cmp64(rax, ExternalAddress((address) &min_long));
589 jcc(Assembler::notEqual, normal_case);
590 xorl(rdx, rdx); // prepare rdx for possible special case (where
591 // remainder = 0)
592 cmpq(reg, -1);
593 jcc(Assembler::equal, special_case);
594
595 // handle normal case
596 bind(normal_case);
597 cdqq();
598 int idivq_offset = offset();
599 idivq(reg);
600
601 // normal and special case exit
602 bind(special_case);
603
604 return idivq_offset;
605 }
606
607 void MacroAssembler::decrementq(Register reg, int value) {
608 if (value == min_jint) { subq(reg, value); return; }
609 if (value < 0) { incrementq(reg, -value); return; }
610 if (value == 0) { ; return; }
611 if (value == 1 && UseIncDec) { decq(reg) ; return; }
612 /* else */ { subq(reg, value) ; return; }
613 }
614
615 void MacroAssembler::decrementq(Address dst, int value) {
616 if (value == min_jint) { subq(dst, value); return; }
617 if (value < 0) { incrementq(dst, -value); return; }
618 if (value == 0) { ; return; }
619 if (value == 1 && UseIncDec) { decq(dst) ; return; }
620 /* else */ { subq(dst, value) ; return; }
621 }
622
623 void MacroAssembler::incrementq(AddressLiteral dst) {
624 if (reachable(dst)) {
625 incrementq(as_Address(dst));
626 } else {
627 lea(rscratch1, dst);
628 incrementq(Address(rscratch1, 0));
629 }
630 }
631
632 void MacroAssembler::incrementq(Register reg, int value) {
633 if (value == min_jint) { addq(reg, value); return; }
634 if (value < 0) { decrementq(reg, -value); return; }
635 if (value == 0) { ; return; }
636 if (value == 1 && UseIncDec) { incq(reg) ; return; }
637 /* else */ { addq(reg, value) ; return; }
638 }
639
640 void MacroAssembler::incrementq(Address dst, int value) {
641 if (value == min_jint) { addq(dst, value); return; }
642 if (value < 0) { decrementq(dst, -value); return; }
643 if (value == 0) { ; return; }
644 if (value == 1 && UseIncDec) { incq(dst) ; return; }
645 /* else */ { addq(dst, value) ; return; }
646 }
647
648 // 32bit can do a case table jump in one instruction but we no longer allow the base
649 // to be installed in the Address class
650 void MacroAssembler::jump(ArrayAddress entry) {
651 lea(rscratch1, entry.base());
652 Address dispatch = entry.index();
653 assert(dispatch._base == noreg, "must be");
654 dispatch._base = rscratch1;
655 jmp(dispatch);
656 }
657
658 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
659 ShouldNotReachHere(); // 64bit doesn't use two regs
660 cmpq(x_lo, y_lo);
661 }
662
663 void MacroAssembler::lea(Register dst, AddressLiteral src) {
664 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
665 }
666
667 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
668 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec());
669 movptr(dst, rscratch1);
670 }
671
672 void MacroAssembler::leave() {
673 // %%% is this really better? Why not on 32bit too?
674 emit_int8((unsigned char)0xC9); // LEAVE
675 }
676
677 void MacroAssembler::lneg(Register hi, Register lo) {
678 ShouldNotReachHere(); // 64bit doesn't use two regs
679 negq(lo);
680 }
681
682 void MacroAssembler::movoop(Register dst, jobject obj) {
683 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
684 }
685
686 void MacroAssembler::movoop(Address dst, jobject obj) {
687 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate());
688 movq(dst, rscratch1);
689 }
690
691 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
692 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
693 }
694
695 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
696 mov_literal64(rscratch1, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
697 movq(dst, rscratch1);
698 }
699
700 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
701 if (src.is_lval()) {
702 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
703 } else {
704 if (reachable(src)) {
705 movq(dst, as_Address(src));
706 } else {
707 lea(scratch, src);
708 movq(dst, Address(scratch, 0));
709 }
710 }
711 }
712
713 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
714 movq(as_Address(dst), src);
715 }
716
717 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
718 movq(dst, as_Address(src));
719 }
720
721 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
722 void MacroAssembler::movptr(Address dst, intptr_t src) {
723 mov64(rscratch1, src);
724 movq(dst, rscratch1);
725 }
726
727 // These are mostly for initializing NULL
728 void MacroAssembler::movptr(Address dst, int32_t src) {
729 movslq(dst, src);
730 }
731
732 void MacroAssembler::movptr(Register dst, int32_t src) {
733 mov64(dst, (intptr_t)src);
734 }
735
736 void MacroAssembler::pushoop(jobject obj) {
737 movoop(rscratch1, obj);
738 push(rscratch1);
739 }
740
741 void MacroAssembler::pushklass(Metadata* obj) {
742 mov_metadata(rscratch1, obj);
743 push(rscratch1);
744 }
745
746 void MacroAssembler::pushptr(AddressLiteral src) {
747 lea(rscratch1, src);
748 if (src.is_lval()) {
749 push(rscratch1);
750 } else {
751 pushq(Address(rscratch1, 0));
752 }
753 }
754
755 void MacroAssembler::reset_last_Java_frame(bool clear_fp) {
756 // we must set sp to zero to clear frame
757 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
758 // must clear fp, so that compiled frames are not confused; it is
759 // possible that we need it only for debugging
760 if (clear_fp) {
761 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
762 }
763
764 // Always clear the pc because it could have been set by make_walkable()
765 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
766 vzeroupper();
767 }
768
769 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
770 Register last_java_fp,
771 address last_java_pc) {
772 vzeroupper();
773 // determine last_java_sp register
774 if (!last_java_sp->is_valid()) {
775 last_java_sp = rsp;
776 }
777
778 // last_java_fp is optional
779 if (last_java_fp->is_valid()) {
780 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()),
781 last_java_fp);
782 }
783
784 // last_java_pc is optional
785 if (last_java_pc != NULL) {
786 Address java_pc(r15_thread,
787 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
788 lea(rscratch1, InternalAddress(last_java_pc));
789 movptr(java_pc, rscratch1);
790 }
791
792 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
793 }
794
795 static void pass_arg0(MacroAssembler* masm, Register arg) {
796 if (c_rarg0 != arg ) {
797 masm->mov(c_rarg0, arg);
798 }
799 }
800
801 static void pass_arg1(MacroAssembler* masm, Register arg) {
802 if (c_rarg1 != arg ) {
803 masm->mov(c_rarg1, arg);
804 }
805 }
806
807 static void pass_arg2(MacroAssembler* masm, Register arg) {
808 if (c_rarg2 != arg ) {
809 masm->mov(c_rarg2, arg);
810 }
811 }
812
813 static void pass_arg3(MacroAssembler* masm, Register arg) {
814 if (c_rarg3 != arg ) {
815 masm->mov(c_rarg3, arg);
816 }
817 }
818
819 void MacroAssembler::stop(const char* msg) {
820 address rip = pc();
821 pusha(); // get regs on stack
822 lea(c_rarg0, ExternalAddress((address) msg));
823 lea(c_rarg1, InternalAddress(rip));
824 movq(c_rarg2, rsp); // pass pointer to regs array
825 andq(rsp, -16); // align stack as required by ABI
826 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
827 hlt();
828 }
829
830 void MacroAssembler::warn(const char* msg) {
831 push(rbp);
832 movq(rbp, rsp);
833 andq(rsp, -16); // align stack as required by push_CPU_state and call
834 push_CPU_state(); // keeps alignment at 16 bytes
835 lea(c_rarg0, ExternalAddress((address) msg));
836 lea(rax, ExternalAddress(CAST_FROM_FN_PTR(address, warning)));
837 call(rax);
838 pop_CPU_state();
839 mov(rsp, rbp);
840 pop(rbp);
841 }
842
843 void MacroAssembler::print_state() {
844 address rip = pc();
845 pusha(); // get regs on stack
846 push(rbp);
847 movq(rbp, rsp);
848 andq(rsp, -16); // align stack as required by push_CPU_state and call
849 push_CPU_state(); // keeps alignment at 16 bytes
850
851 lea(c_rarg0, InternalAddress(rip));
852 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
853 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
854
855 pop_CPU_state();
856 mov(rsp, rbp);
857 pop(rbp);
858 popa();
859 }
860
861 #ifndef PRODUCT
862 extern "C" void findpc(intptr_t x);
863 #endif
864
865 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
866 // In order to get locks to work, we need to fake a in_VM state
867 if (ShowMessageBoxOnError) {
868 JavaThread* thread = JavaThread::current();
869 JavaThreadState saved_state = thread->thread_state();
870 thread->set_thread_state(_thread_in_vm);
871 #ifndef PRODUCT
872 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
873 ttyLocker ttyl;
874 BytecodeCounter::print();
875 }
876 #endif
877 // To see where a verify_oop failed, get $ebx+40/X for this frame.
878 // XXX correct this offset for amd64
879 // This is the value of eip which points to where verify_oop will return.
880 if (os::message_box(msg, "Execution stopped, print registers?")) {
881 print_state64(pc, regs);
882 BREAKPOINT;
883 assert(false, "start up GDB");
884 }
885 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
886 } else {
887 ttyLocker ttyl;
888 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n",
889 msg);
890 assert(false, "DEBUG MESSAGE: %s", msg);
891 }
892 }
893
894 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
895 ttyLocker ttyl;
896 FlagSetting fs(Debugging, true);
897 tty->print_cr("rip = 0x%016lx", (intptr_t)pc);
898 #ifndef PRODUCT
899 tty->cr();
900 findpc(pc);
901 tty->cr();
902 #endif
903 #define PRINT_REG(rax, value) \
904 { tty->print("%s = ", #rax); os::print_location(tty, value); }
905 PRINT_REG(rax, regs[15]);
906 PRINT_REG(rbx, regs[12]);
907 PRINT_REG(rcx, regs[14]);
908 PRINT_REG(rdx, regs[13]);
909 PRINT_REG(rdi, regs[8]);
910 PRINT_REG(rsi, regs[9]);
911 PRINT_REG(rbp, regs[10]);
912 PRINT_REG(rsp, regs[11]);
913 PRINT_REG(r8 , regs[7]);
914 PRINT_REG(r9 , regs[6]);
915 PRINT_REG(r10, regs[5]);
916 PRINT_REG(r11, regs[4]);
917 PRINT_REG(r12, regs[3]);
918 PRINT_REG(r13, regs[2]);
919 PRINT_REG(r14, regs[1]);
920 PRINT_REG(r15, regs[0]);
921 #undef PRINT_REG
922 // Print some words near top of staack.
923 int64_t* rsp = (int64_t*) regs[11];
924 int64_t* dump_sp = rsp;
925 for (int col1 = 0; col1 < 8; col1++) {
926 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
927 os::print_location(tty, *dump_sp++);
928 }
929 for (int row = 0; row < 25; row++) {
930 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
931 for (int col = 0; col < 4; col++) {
932 tty->print(" 0x%016lx", (intptr_t)*dump_sp++);
933 }
934 tty->cr();
935 }
936 // Print some instructions around pc:
937 Disassembler::decode((address)pc-64, (address)pc);
938 tty->print_cr("--------");
939 Disassembler::decode((address)pc, (address)pc+32);
940 }
941
942 #endif // _LP64
943
944 // Now versions that are common to 32/64 bit
945
946 void MacroAssembler::addptr(Register dst, int32_t imm32) {
947 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
948 }
949
950 void MacroAssembler::addptr(Register dst, Register src) {
951 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
952 }
953
954 void MacroAssembler::addptr(Address dst, Register src) {
955 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
956 }
957
958 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) {
959 if (reachable(src)) {
960 Assembler::addsd(dst, as_Address(src));
961 } else {
962 lea(rscratch1, src);
963 Assembler::addsd(dst, Address(rscratch1, 0));
964 }
965 }
966
967 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) {
968 if (reachable(src)) {
969 addss(dst, as_Address(src));
970 } else {
971 lea(rscratch1, src);
972 addss(dst, Address(rscratch1, 0));
973 }
974 }
975
976 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src) {
977 if (reachable(src)) {
978 Assembler::addpd(dst, as_Address(src));
979 } else {
980 lea(rscratch1, src);
981 Assembler::addpd(dst, Address(rscratch1, 0));
982 }
983 }
984
985 void MacroAssembler::align(int modulus) {
986 align(modulus, offset());
987 }
988
989 void MacroAssembler::align(int modulus, int target) {
990 if (target % modulus != 0) {
991 nop(modulus - (target % modulus));
992 }
993 }
994
995 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) {
996 // Used in sign-masking with aligned address.
997 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
998 if (reachable(src)) {
999 Assembler::andpd(dst, as_Address(src));
1000 } else {
1001 lea(rscratch1, src);
1002 Assembler::andpd(dst, Address(rscratch1, 0));
1003 }
1004 }
1005
1006 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src) {
1007 // Used in sign-masking with aligned address.
1008 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1009 if (reachable(src)) {
1010 Assembler::andps(dst, as_Address(src));
1011 } else {
1012 lea(rscratch1, src);
1013 Assembler::andps(dst, Address(rscratch1, 0));
1014 }
1015 }
1016
1017 void MacroAssembler::andptr(Register dst, int32_t imm32) {
1018 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
1019 }
1020
1021 void MacroAssembler::atomic_incl(Address counter_addr) {
1022 if (os::is_MP())
1023 lock();
1024 incrementl(counter_addr);
1025 }
1026
1027 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register scr) {
1028 if (reachable(counter_addr)) {
1029 atomic_incl(as_Address(counter_addr));
1030 } else {
1031 lea(scr, counter_addr);
1032 atomic_incl(Address(scr, 0));
1033 }
1034 }
1035
1036 #ifdef _LP64
1037 void MacroAssembler::atomic_incq(Address counter_addr) {
1038 if (os::is_MP())
1039 lock();
1040 incrementq(counter_addr);
1041 }
1042
1043 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register scr) {
1044 if (reachable(counter_addr)) {
1045 atomic_incq(as_Address(counter_addr));
1046 } else {
1047 lea(scr, counter_addr);
1048 atomic_incq(Address(scr, 0));
1049 }
1050 }
1051 #endif
1052
1053 // Writes to stack successive pages until offset reached to check for
1054 // stack overflow + shadow pages. This clobbers tmp.
1055 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
1056 movptr(tmp, rsp);
1057 // Bang stack for total size given plus shadow page size.
1058 // Bang one page at a time because large size can bang beyond yellow and
1059 // red zones.
1060 Label loop;
1061 bind(loop);
1062 movl(Address(tmp, (-os::vm_page_size())), size );
1063 subptr(tmp, os::vm_page_size());
1064 subl(size, os::vm_page_size());
1065 jcc(Assembler::greater, loop);
1066
1067 // Bang down shadow pages too.
1068 // At this point, (tmp-0) is the last address touched, so don't
1069 // touch it again. (It was touched as (tmp-pagesize) but then tmp
1070 // was post-decremented.) Skip this address by starting at i=1, and
1071 // touch a few more pages below. N.B. It is important to touch all
1072 // the way down including all pages in the shadow zone.
1073 for (int i = 1; i < ((int)JavaThread::stack_shadow_zone_size() / os::vm_page_size()); i++) {
1074 // this could be any sized move but this is can be a debugging crumb
1075 // so the bigger the better.
1076 movptr(Address(tmp, (-i*os::vm_page_size())), size );
1077 }
1078 }
1079
1080 void MacroAssembler::reserved_stack_check() {
1081 // testing if reserved zone needs to be enabled
1082 Label no_reserved_zone_enabling;
1083 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
1084 NOT_LP64(get_thread(rsi);)
1085
1086 cmpptr(rsp, Address(thread, JavaThread::reserved_stack_activation_offset()));
1087 jcc(Assembler::below, no_reserved_zone_enabling);
1088
1089 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), thread);
1090 jump(RuntimeAddress(StubRoutines::throw_delayed_StackOverflowError_entry()));
1091 should_not_reach_here();
1092
1093 bind(no_reserved_zone_enabling);
1094 }
1095
1096 int MacroAssembler::biased_locking_enter(Register lock_reg,
1097 Register obj_reg,
1098 Register swap_reg,
1099 Register tmp_reg,
1100 bool swap_reg_contains_mark,
1101 Label& done,
1102 Label* slow_case,
1103 BiasedLockingCounters* counters) {
1104 assert(UseBiasedLocking, "why call this otherwise?");
1105 assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq");
1106 assert(tmp_reg != noreg, "tmp_reg must be supplied");
1107 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg);
1108 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
1109 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes());
1110 NOT_LP64( Address saved_mark_addr(lock_reg, 0); )
1111
1112 if (PrintBiasedLockingStatistics && counters == NULL) {
1113 counters = BiasedLocking::counters();
1114 }
1115 // Biased locking
1116 // See whether the lock is currently biased toward our thread and
1117 // whether the epoch is still valid
1118 // Note that the runtime guarantees sufficient alignment of JavaThread
1119 // pointers to allow age to be placed into low bits
1120 // First check to see whether biasing is even enabled for this object
1121 Label cas_label;
1122 int null_check_offset = -1;
1123 if (!swap_reg_contains_mark) {
1124 null_check_offset = offset();
1125 movptr(swap_reg, mark_addr);
1126 }
1127 movptr(tmp_reg, swap_reg);
1128 andptr(tmp_reg, markOopDesc::biased_lock_mask_in_place);
1129 cmpptr(tmp_reg, markOopDesc::biased_lock_pattern);
1130 jcc(Assembler::notEqual, cas_label);
1131 // The bias pattern is present in the object's header. Need to check
1132 // whether the bias owner and the epoch are both still current.
1133 #ifndef _LP64
1134 // Note that because there is no current thread register on x86_32 we
1135 // need to store off the mark word we read out of the object to
1136 // avoid reloading it and needing to recheck invariants below. This
1137 // store is unfortunate but it makes the overall code shorter and
1138 // simpler.
1139 movptr(saved_mark_addr, swap_reg);
1140 #endif
1141 if (swap_reg_contains_mark) {
1142 null_check_offset = offset();
1143 }
1144 load_prototype_header(tmp_reg, obj_reg);
1145 #ifdef _LP64
1146 orptr(tmp_reg, r15_thread);
1147 xorptr(tmp_reg, swap_reg);
1148 Register header_reg = tmp_reg;
1149 #else
1150 xorptr(tmp_reg, swap_reg);
1151 get_thread(swap_reg);
1152 xorptr(swap_reg, tmp_reg);
1153 Register header_reg = swap_reg;
1154 #endif
1155 andptr(header_reg, ~((int) markOopDesc::age_mask_in_place));
1156 if (counters != NULL) {
1157 cond_inc32(Assembler::zero,
1158 ExternalAddress((address) counters->biased_lock_entry_count_addr()));
1159 }
1160 jcc(Assembler::equal, done);
1161
1162 Label try_revoke_bias;
1163 Label try_rebias;
1164
1165 // At this point we know that the header has the bias pattern and
1166 // that we are not the bias owner in the current epoch. We need to
1167 // figure out more details about the state of the header in order to
1168 // know what operations can be legally performed on the object's
1169 // header.
1170
1171 // If the low three bits in the xor result aren't clear, that means
1172 // the prototype header is no longer biased and we have to revoke
1173 // the bias on this object.
1174 testptr(header_reg, markOopDesc::biased_lock_mask_in_place);
1175 jccb(Assembler::notZero, try_revoke_bias);
1176
1177 // Biasing is still enabled for this data type. See whether the
1178 // epoch of the current bias is still valid, meaning that the epoch
1179 // bits of the mark word are equal to the epoch bits of the
1180 // prototype header. (Note that the prototype header's epoch bits
1181 // only change at a safepoint.) If not, attempt to rebias the object
1182 // toward the current thread. Note that we must be absolutely sure
1183 // that the current epoch is invalid in order to do this because
1184 // otherwise the manipulations it performs on the mark word are
1185 // illegal.
1186 testptr(header_reg, markOopDesc::epoch_mask_in_place);
1187 jccb(Assembler::notZero, try_rebias);
1188
1189 // The epoch of the current bias is still valid but we know nothing
1190 // about the owner; it might be set or it might be clear. Try to
1191 // acquire the bias of the object using an atomic operation. If this
1192 // fails we will go in to the runtime to revoke the object's bias.
1193 // Note that we first construct the presumed unbiased header so we
1194 // don't accidentally blow away another thread's valid bias.
1195 NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1196 andptr(swap_reg,
1197 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
1198 #ifdef _LP64
1199 movptr(tmp_reg, swap_reg);
1200 orptr(tmp_reg, r15_thread);
1201 #else
1202 get_thread(tmp_reg);
1203 orptr(tmp_reg, swap_reg);
1204 #endif
1205 if (os::is_MP()) {
1206 lock();
1207 }
1208 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1209 // If the biasing toward our thread failed, this means that
1210 // another thread succeeded in biasing it toward itself and we
1211 // need to revoke that bias. The revocation will occur in the
1212 // interpreter runtime in the slow case.
1213 if (counters != NULL) {
1214 cond_inc32(Assembler::zero,
1215 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr()));
1216 }
1217 if (slow_case != NULL) {
1218 jcc(Assembler::notZero, *slow_case);
1219 }
1220 jmp(done);
1221
1222 bind(try_rebias);
1223 // At this point we know the epoch has expired, meaning that the
1224 // current "bias owner", if any, is actually invalid. Under these
1225 // circumstances _only_, we are allowed to use the current header's
1226 // value as the comparison value when doing the cas to acquire the
1227 // bias in the current epoch. In other words, we allow transfer of
1228 // the bias from one thread to another directly in this situation.
1229 //
1230 // FIXME: due to a lack of registers we currently blow away the age
1231 // bits in this situation. Should attempt to preserve them.
1232 load_prototype_header(tmp_reg, obj_reg);
1233 #ifdef _LP64
1234 orptr(tmp_reg, r15_thread);
1235 #else
1236 get_thread(swap_reg);
1237 orptr(tmp_reg, swap_reg);
1238 movptr(swap_reg, saved_mark_addr);
1239 #endif
1240 if (os::is_MP()) {
1241 lock();
1242 }
1243 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1244 // If the biasing toward our thread failed, then another thread
1245 // succeeded in biasing it toward itself and we need to revoke that
1246 // bias. The revocation will occur in the runtime in the slow case.
1247 if (counters != NULL) {
1248 cond_inc32(Assembler::zero,
1249 ExternalAddress((address) counters->rebiased_lock_entry_count_addr()));
1250 }
1251 if (slow_case != NULL) {
1252 jcc(Assembler::notZero, *slow_case);
1253 }
1254 jmp(done);
1255
1256 bind(try_revoke_bias);
1257 // The prototype mark in the klass doesn't have the bias bit set any
1258 // more, indicating that objects of this data type are not supposed
1259 // to be biased any more. We are going to try to reset the mark of
1260 // this object to the prototype value and fall through to the
1261 // CAS-based locking scheme. Note that if our CAS fails, it means
1262 // that another thread raced us for the privilege of revoking the
1263 // bias of this particular object, so it's okay to continue in the
1264 // normal locking code.
1265 //
1266 // FIXME: due to a lack of registers we currently blow away the age
1267 // bits in this situation. Should attempt to preserve them.
1268 NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1269 load_prototype_header(tmp_reg, obj_reg);
1270 if (os::is_MP()) {
1271 lock();
1272 }
1273 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1274 // Fall through to the normal CAS-based lock, because no matter what
1275 // the result of the above CAS, some thread must have succeeded in
1276 // removing the bias bit from the object's header.
1277 if (counters != NULL) {
1278 cond_inc32(Assembler::zero,
1279 ExternalAddress((address) counters->revoked_lock_entry_count_addr()));
1280 }
1281
1282 bind(cas_label);
1283
1284 return null_check_offset;
1285 }
1286
1287 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) {
1288 assert(UseBiasedLocking, "why call this otherwise?");
1289
1290 // Check for biased locking unlock case, which is a no-op
1291 // Note: we do not have to check the thread ID for two reasons.
1292 // First, the interpreter checks for IllegalMonitorStateException at
1293 // a higher level. Second, if the bias was revoked while we held the
1294 // lock, the object could not be rebiased toward another thread, so
1295 // the bias bit would be clear.
1296 movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
1297 andptr(temp_reg, markOopDesc::biased_lock_mask_in_place);
1298 cmpptr(temp_reg, markOopDesc::biased_lock_pattern);
1299 jcc(Assembler::equal, done);
1300 }
1301
1302 #ifdef COMPILER2
1303
1304 #if INCLUDE_RTM_OPT
1305
1306 // Update rtm_counters based on abort status
1307 // input: abort_status
1308 // rtm_counters (RTMLockingCounters*)
1309 // flags are killed
1310 void MacroAssembler::rtm_counters_update(Register abort_status, Register rtm_counters) {
1311
1312 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abort_count_offset()));
1313 if (PrintPreciseRTMLockingStatistics) {
1314 for (int i = 0; i < RTMLockingCounters::ABORT_STATUS_LIMIT; i++) {
1315 Label check_abort;
1316 testl(abort_status, (1<<i));
1317 jccb(Assembler::equal, check_abort);
1318 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abortX_count_offset() + (i * sizeof(uintx))));
1319 bind(check_abort);
1320 }
1321 }
1322 }
1323
1324 // Branch if (random & (count-1) != 0), count is 2^n
1325 // tmp, scr and flags are killed
1326 void MacroAssembler::branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel) {
1327 assert(tmp == rax, "");
1328 assert(scr == rdx, "");
1329 rdtsc(); // modifies EDX:EAX
1330 andptr(tmp, count-1);
1331 jccb(Assembler::notZero, brLabel);
1332 }
1333
1334 // Perform abort ratio calculation, set no_rtm bit if high ratio
1335 // input: rtm_counters_Reg (RTMLockingCounters* address)
1336 // tmpReg, rtm_counters_Reg and flags are killed
1337 void MacroAssembler::rtm_abort_ratio_calculation(Register tmpReg,
1338 Register rtm_counters_Reg,
1339 RTMLockingCounters* rtm_counters,
1340 Metadata* method_data) {
1341 Label L_done, L_check_always_rtm1, L_check_always_rtm2;
1342
1343 if (RTMLockingCalculationDelay > 0) {
1344 // Delay calculation
1345 movptr(tmpReg, ExternalAddress((address) RTMLockingCounters::rtm_calculation_flag_addr()), tmpReg);
1346 testptr(tmpReg, tmpReg);
1347 jccb(Assembler::equal, L_done);
1348 }
1349 // Abort ratio calculation only if abort_count > RTMAbortThreshold
1350 // Aborted transactions = abort_count * 100
1351 // All transactions = total_count * RTMTotalCountIncrRate
1352 // Set no_rtm bit if (Aborted transactions >= All transactions * RTMAbortRatio)
1353
1354 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::abort_count_offset()));
1355 cmpptr(tmpReg, RTMAbortThreshold);
1356 jccb(Assembler::below, L_check_always_rtm2);
1357 imulptr(tmpReg, tmpReg, 100);
1358
1359 Register scrReg = rtm_counters_Reg;
1360 movptr(scrReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1361 imulptr(scrReg, scrReg, RTMTotalCountIncrRate);
1362 imulptr(scrReg, scrReg, RTMAbortRatio);
1363 cmpptr(tmpReg, scrReg);
1364 jccb(Assembler::below, L_check_always_rtm1);
1365 if (method_data != NULL) {
1366 // set rtm_state to "no rtm" in MDO
1367 mov_metadata(tmpReg, method_data);
1368 if (os::is_MP()) {
1369 lock();
1370 }
1371 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), NoRTM);
1372 }
1373 jmpb(L_done);
1374 bind(L_check_always_rtm1);
1375 // Reload RTMLockingCounters* address
1376 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1377 bind(L_check_always_rtm2);
1378 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1379 cmpptr(tmpReg, RTMLockingThreshold / RTMTotalCountIncrRate);
1380 jccb(Assembler::below, L_done);
1381 if (method_data != NULL) {
1382 // set rtm_state to "always rtm" in MDO
1383 mov_metadata(tmpReg, method_data);
1384 if (os::is_MP()) {
1385 lock();
1386 }
1387 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), UseRTM);
1388 }
1389 bind(L_done);
1390 }
1391
1392 // Update counters and perform abort ratio calculation
1393 // input: abort_status_Reg
1394 // rtm_counters_Reg, flags are killed
1395 void MacroAssembler::rtm_profiling(Register abort_status_Reg,
1396 Register rtm_counters_Reg,
1397 RTMLockingCounters* rtm_counters,
1398 Metadata* method_data,
1399 bool profile_rtm) {
1400
1401 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1402 // update rtm counters based on rax value at abort
1403 // reads abort_status_Reg, updates flags
1404 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1405 rtm_counters_update(abort_status_Reg, rtm_counters_Reg);
1406 if (profile_rtm) {
1407 // Save abort status because abort_status_Reg is used by following code.
1408 if (RTMRetryCount > 0) {
1409 push(abort_status_Reg);
1410 }
1411 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1412 rtm_abort_ratio_calculation(abort_status_Reg, rtm_counters_Reg, rtm_counters, method_data);
1413 // restore abort status
1414 if (RTMRetryCount > 0) {
1415 pop(abort_status_Reg);
1416 }
1417 }
1418 }
1419
1420 // Retry on abort if abort's status is 0x6: can retry (0x2) | memory conflict (0x4)
1421 // inputs: retry_count_Reg
1422 // : abort_status_Reg
1423 // output: retry_count_Reg decremented by 1
1424 // flags are killed
1425 void MacroAssembler::rtm_retry_lock_on_abort(Register retry_count_Reg, Register abort_status_Reg, Label& retryLabel) {
1426 Label doneRetry;
1427 assert(abort_status_Reg == rax, "");
1428 // The abort reason bits are in eax (see all states in rtmLocking.hpp)
1429 // 0x6 = conflict on which we can retry (0x2) | memory conflict (0x4)
1430 // if reason is in 0x6 and retry count != 0 then retry
1431 andptr(abort_status_Reg, 0x6);
1432 jccb(Assembler::zero, doneRetry);
1433 testl(retry_count_Reg, retry_count_Reg);
1434 jccb(Assembler::zero, doneRetry);
1435 pause();
1436 decrementl(retry_count_Reg);
1437 jmp(retryLabel);
1438 bind(doneRetry);
1439 }
1440
1441 // Spin and retry if lock is busy,
1442 // inputs: box_Reg (monitor address)
1443 // : retry_count_Reg
1444 // output: retry_count_Reg decremented by 1
1445 // : clear z flag if retry count exceeded
1446 // tmp_Reg, scr_Reg, flags are killed
1447 void MacroAssembler::rtm_retry_lock_on_busy(Register retry_count_Reg, Register box_Reg,
1448 Register tmp_Reg, Register scr_Reg, Label& retryLabel) {
1449 Label SpinLoop, SpinExit, doneRetry;
1450 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1451
1452 testl(retry_count_Reg, retry_count_Reg);
1453 jccb(Assembler::zero, doneRetry);
1454 decrementl(retry_count_Reg);
1455 movptr(scr_Reg, RTMSpinLoopCount);
1456
1457 bind(SpinLoop);
1458 pause();
1459 decrementl(scr_Reg);
1460 jccb(Assembler::lessEqual, SpinExit);
1461 movptr(tmp_Reg, Address(box_Reg, owner_offset));
1462 testptr(tmp_Reg, tmp_Reg);
1463 jccb(Assembler::notZero, SpinLoop);
1464
1465 bind(SpinExit);
1466 jmp(retryLabel);
1467 bind(doneRetry);
1468 incrementl(retry_count_Reg); // clear z flag
1469 }
1470
1471 // Use RTM for normal stack locks
1472 // Input: objReg (object to lock)
1473 void MacroAssembler::rtm_stack_locking(Register objReg, Register tmpReg, Register scrReg,
1474 Register retry_on_abort_count_Reg,
1475 RTMLockingCounters* stack_rtm_counters,
1476 Metadata* method_data, bool profile_rtm,
1477 Label& DONE_LABEL, Label& IsInflated) {
1478 assert(UseRTMForStackLocks, "why call this otherwise?");
1479 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
1480 assert(tmpReg == rax, "");
1481 assert(scrReg == rdx, "");
1482 Label L_rtm_retry, L_decrement_retry, L_on_abort;
1483
1484 if (RTMRetryCount > 0) {
1485 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1486 bind(L_rtm_retry);
1487 }
1488 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes()));
1489 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased
1490 jcc(Assembler::notZero, IsInflated);
1491
1492 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1493 Label L_noincrement;
1494 if (RTMTotalCountIncrRate > 1) {
1495 // tmpReg, scrReg and flags are killed
1496 branch_on_random_using_rdtsc(tmpReg, scrReg, RTMTotalCountIncrRate, L_noincrement);
1497 }
1498 assert(stack_rtm_counters != NULL, "should not be NULL when profiling RTM");
1499 atomic_incptr(ExternalAddress((address)stack_rtm_counters->total_count_addr()), scrReg);
1500 bind(L_noincrement);
1501 }
1502 xbegin(L_on_abort);
1503 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // fetch markword
1504 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
1505 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked
1506 jcc(Assembler::equal, DONE_LABEL); // all done if unlocked
1507
1508 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1509 if (UseRTMXendForLockBusy) {
1510 xend();
1511 movptr(abort_status_Reg, 0x2); // Set the abort status to 2 (so we can retry)
1512 jmp(L_decrement_retry);
1513 }
1514 else {
1515 xabort(0);
1516 }
1517 bind(L_on_abort);
1518 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1519 rtm_profiling(abort_status_Reg, scrReg, stack_rtm_counters, method_data, profile_rtm);
1520 }
1521 bind(L_decrement_retry);
1522 if (RTMRetryCount > 0) {
1523 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1524 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1525 }
1526 }
1527
1528 // Use RTM for inflating locks
1529 // inputs: objReg (object to lock)
1530 // boxReg (on-stack box address (displaced header location) - KILLED)
1531 // tmpReg (ObjectMonitor address + markOopDesc::monitor_value)
1532 void MacroAssembler::rtm_inflated_locking(Register objReg, Register boxReg, Register tmpReg,
1533 Register scrReg, Register retry_on_busy_count_Reg,
1534 Register retry_on_abort_count_Reg,
1535 RTMLockingCounters* rtm_counters,
1536 Metadata* method_data, bool profile_rtm,
1537 Label& DONE_LABEL) {
1538 assert(UseRTMLocking, "why call this otherwise?");
1539 assert(tmpReg == rax, "");
1540 assert(scrReg == rdx, "");
1541 Label L_rtm_retry, L_decrement_retry, L_on_abort;
1542 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1543
1544 // Without cast to int32_t a movptr will destroy r10 which is typically obj
1545 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1546 movptr(boxReg, tmpReg); // Save ObjectMonitor address
1547
1548 if (RTMRetryCount > 0) {
1549 movl(retry_on_busy_count_Reg, RTMRetryCount); // Retry on lock busy
1550 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1551 bind(L_rtm_retry);
1552 }
1553 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1554 Label L_noincrement;
1555 if (RTMTotalCountIncrRate > 1) {
1556 // tmpReg, scrReg and flags are killed
1557 branch_on_random_using_rdtsc(tmpReg, scrReg, RTMTotalCountIncrRate, L_noincrement);
1558 }
1559 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1560 atomic_incptr(ExternalAddress((address)rtm_counters->total_count_addr()), scrReg);
1561 bind(L_noincrement);
1562 }
1563 xbegin(L_on_abort);
1564 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes()));
1565 movptr(tmpReg, Address(tmpReg, owner_offset));
1566 testptr(tmpReg, tmpReg);
1567 jcc(Assembler::zero, DONE_LABEL);
1568 if (UseRTMXendForLockBusy) {
1569 xend();
1570 jmp(L_decrement_retry);
1571 }
1572 else {
1573 xabort(0);
1574 }
1575 bind(L_on_abort);
1576 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1577 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1578 rtm_profiling(abort_status_Reg, scrReg, rtm_counters, method_data, profile_rtm);
1579 }
1580 if (RTMRetryCount > 0) {
1581 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1582 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1583 }
1584
1585 movptr(tmpReg, Address(boxReg, owner_offset)) ;
1586 testptr(tmpReg, tmpReg) ;
1587 jccb(Assembler::notZero, L_decrement_retry) ;
1588
1589 // Appears unlocked - try to swing _owner from null to non-null.
1590 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1591 #ifdef _LP64
1592 Register threadReg = r15_thread;
1593 #else
1594 get_thread(scrReg);
1595 Register threadReg = scrReg;
1596 #endif
1597 if (os::is_MP()) {
1598 lock();
1599 }
1600 cmpxchgptr(threadReg, Address(boxReg, owner_offset)); // Updates tmpReg
1601
1602 if (RTMRetryCount > 0) {
1603 // success done else retry
1604 jccb(Assembler::equal, DONE_LABEL) ;
1605 bind(L_decrement_retry);
1606 // Spin and retry if lock is busy.
1607 rtm_retry_lock_on_busy(retry_on_busy_count_Reg, boxReg, tmpReg, scrReg, L_rtm_retry);
1608 }
1609 else {
1610 bind(L_decrement_retry);
1611 }
1612 }
1613
1614 #endif // INCLUDE_RTM_OPT
1615
1616 // Fast_Lock and Fast_Unlock used by C2
1617
1618 // Because the transitions from emitted code to the runtime
1619 // monitorenter/exit helper stubs are so slow it's critical that
1620 // we inline both the stack-locking fast-path and the inflated fast path.
1621 //
1622 // See also: cmpFastLock and cmpFastUnlock.
1623 //
1624 // What follows is a specialized inline transliteration of the code
1625 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
1626 // another option would be to emit TrySlowEnter and TrySlowExit methods
1627 // at startup-time. These methods would accept arguments as
1628 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
1629 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
1630 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
1631 // In practice, however, the # of lock sites is bounded and is usually small.
1632 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
1633 // if the processor uses simple bimodal branch predictors keyed by EIP
1634 // Since the helper routines would be called from multiple synchronization
1635 // sites.
1636 //
1637 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
1638 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
1639 // to those specialized methods. That'd give us a mostly platform-independent
1640 // implementation that the JITs could optimize and inline at their pleasure.
1641 // Done correctly, the only time we'd need to cross to native could would be
1642 // to park() or unpark() threads. We'd also need a few more unsafe operators
1643 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
1644 // (b) explicit barriers or fence operations.
1645 //
1646 // TODO:
1647 //
1648 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
1649 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
1650 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
1651 // the lock operators would typically be faster than reifying Self.
1652 //
1653 // * Ideally I'd define the primitives as:
1654 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
1655 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
1656 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
1657 // Instead, we're stuck with a rather awkward and brittle register assignments below.
1658 // Furthermore the register assignments are overconstrained, possibly resulting in
1659 // sub-optimal code near the synchronization site.
1660 //
1661 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
1662 // Alternately, use a better sp-proximity test.
1663 //
1664 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
1665 // Either one is sufficient to uniquely identify a thread.
1666 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
1667 //
1668 // * Intrinsify notify() and notifyAll() for the common cases where the
1669 // object is locked by the calling thread but the waitlist is empty.
1670 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
1671 //
1672 // * use jccb and jmpb instead of jcc and jmp to improve code density.
1673 // But beware of excessive branch density on AMD Opterons.
1674 //
1675 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
1676 // or failure of the fast-path. If the fast-path fails then we pass
1677 // control to the slow-path, typically in C. In Fast_Lock and
1678 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
1679 // will emit a conditional branch immediately after the node.
1680 // So we have branches to branches and lots of ICC.ZF games.
1681 // Instead, it might be better to have C2 pass a "FailureLabel"
1682 // into Fast_Lock and Fast_Unlock. In the case of success, control
1683 // will drop through the node. ICC.ZF is undefined at exit.
1684 // In the case of failure, the node will branch directly to the
1685 // FailureLabel
1686
1687
1688 // obj: object to lock
1689 // box: on-stack box address (displaced header location) - KILLED
1690 // rax,: tmp -- KILLED
1691 // scr: tmp -- KILLED
1692 void MacroAssembler::fast_lock(Register objReg, Register boxReg, Register tmpReg,
1693 Register scrReg, Register cx1Reg, Register cx2Reg,
1694 BiasedLockingCounters* counters,
1695 RTMLockingCounters* rtm_counters,
1696 RTMLockingCounters* stack_rtm_counters,
1697 Metadata* method_data,
1698 bool use_rtm, bool profile_rtm) {
1699 // Ensure the register assignments are disjoint
1700 assert(tmpReg == rax, "");
1701
1702 if (use_rtm) {
1703 assert_different_registers(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg);
1704 } else {
1705 assert(cx1Reg == noreg, "");
1706 assert(cx2Reg == noreg, "");
1707 assert_different_registers(objReg, boxReg, tmpReg, scrReg);
1708 }
1709
1710 if (counters != NULL) {
1711 atomic_incl(ExternalAddress((address)counters->total_entry_count_addr()), scrReg);
1712 }
1713 if (EmitSync & 1) {
1714 // set box->dhw = markOopDesc::unused_mark()
1715 // Force all sync thru slow-path: slow_enter() and slow_exit()
1716 movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1717 cmpptr (rsp, (int32_t)NULL_WORD);
1718 } else {
1719 // Possible cases that we'll encounter in fast_lock
1720 // ------------------------------------------------
1721 // * Inflated
1722 // -- unlocked
1723 // -- Locked
1724 // = by self
1725 // = by other
1726 // * biased
1727 // -- by Self
1728 // -- by other
1729 // * neutral
1730 // * stack-locked
1731 // -- by self
1732 // = sp-proximity test hits
1733 // = sp-proximity test generates false-negative
1734 // -- by other
1735 //
1736
1737 Label IsInflated, DONE_LABEL;
1738
1739 // it's stack-locked, biased or neutral
1740 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
1741 // order to reduce the number of conditional branches in the most common cases.
1742 // Beware -- there's a subtle invariant that fetch of the markword
1743 // at [FETCH], below, will never observe a biased encoding (*101b).
1744 // If this invariant is not held we risk exclusion (safety) failure.
1745 if (UseBiasedLocking && !UseOptoBiasInlining) {
1746 biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, counters);
1747 }
1748
1749 #if INCLUDE_RTM_OPT
1750 if (UseRTMForStackLocks && use_rtm) {
1751 rtm_stack_locking(objReg, tmpReg, scrReg, cx2Reg,
1752 stack_rtm_counters, method_data, profile_rtm,
1753 DONE_LABEL, IsInflated);
1754 }
1755 #endif // INCLUDE_RTM_OPT
1756
1757 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // [FETCH]
1758 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased
1759 jccb(Assembler::notZero, IsInflated);
1760
1761 // Attempt stack-locking ...
1762 orptr (tmpReg, markOopDesc::unlocked_value);
1763 movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
1764 if (os::is_MP()) {
1765 lock();
1766 }
1767 cmpxchgptr(boxReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Updates tmpReg
1768 if (counters != NULL) {
1769 cond_inc32(Assembler::equal,
1770 ExternalAddress((address)counters->fast_path_entry_count_addr()));
1771 }
1772 jcc(Assembler::equal, DONE_LABEL); // Success
1773
1774 // Recursive locking.
1775 // The object is stack-locked: markword contains stack pointer to BasicLock.
1776 // Locked by current thread if difference with current SP is less than one page.
1777 subptr(tmpReg, rsp);
1778 // Next instruction set ZFlag == 1 (Success) if difference is less then one page.
1779 andptr(tmpReg, (int32_t) (NOT_LP64(0xFFFFF003) LP64_ONLY(7 - os::vm_page_size())) );
1780 movptr(Address(boxReg, 0), tmpReg);
1781 if (counters != NULL) {
1782 cond_inc32(Assembler::equal,
1783 ExternalAddress((address)counters->fast_path_entry_count_addr()));
1784 }
1785 jmp(DONE_LABEL);
1786
1787 bind(IsInflated);
1788 // The object is inflated. tmpReg contains pointer to ObjectMonitor* + markOopDesc::monitor_value
1789
1790 #if INCLUDE_RTM_OPT
1791 // Use the same RTM locking code in 32- and 64-bit VM.
1792 if (use_rtm) {
1793 rtm_inflated_locking(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg,
1794 rtm_counters, method_data, profile_rtm, DONE_LABEL);
1795 } else {
1796 #endif // INCLUDE_RTM_OPT
1797
1798 #ifndef _LP64
1799 // The object is inflated.
1800
1801 // boxReg refers to the on-stack BasicLock in the current frame.
1802 // We'd like to write:
1803 // set box->_displaced_header = markOopDesc::unused_mark(). Any non-0 value suffices.
1804 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
1805 // additional latency as we have another ST in the store buffer that must drain.
1806
1807 if (EmitSync & 8192) {
1808 movptr(Address(boxReg, 0), 3); // results in ST-before-CAS penalty
1809 get_thread (scrReg);
1810 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
1811 movptr(tmpReg, NULL_WORD); // consider: xor vs mov
1812 if (os::is_MP()) {
1813 lock();
1814 }
1815 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1816 } else
1817 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
1818 // register juggle because we need tmpReg for cmpxchgptr below
1819 movptr(scrReg, boxReg);
1820 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
1821
1822 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
1823 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
1824 // prefetchw [eax + Offset(_owner)-2]
1825 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1826 }
1827
1828 if ((EmitSync & 64) == 0) {
1829 // Optimistic form: consider XORL tmpReg,tmpReg
1830 movptr(tmpReg, NULL_WORD);
1831 } else {
1832 // Can suffer RTS->RTO upgrades on shared or cold $ lines
1833 // Test-And-CAS instead of CAS
1834 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner
1835 testptr(tmpReg, tmpReg); // Locked ?
1836 jccb (Assembler::notZero, DONE_LABEL);
1837 }
1838
1839 // Appears unlocked - try to swing _owner from null to non-null.
1840 // Ideally, I'd manifest "Self" with get_thread and then attempt
1841 // to CAS the register containing Self into m->Owner.
1842 // But we don't have enough registers, so instead we can either try to CAS
1843 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
1844 // we later store "Self" into m->Owner. Transiently storing a stack address
1845 // (rsp or the address of the box) into m->owner is harmless.
1846 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1847 if (os::is_MP()) {
1848 lock();
1849 }
1850 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1851 movptr(Address(scrReg, 0), 3); // box->_displaced_header = 3
1852 // If we weren't able to swing _owner from NULL to the BasicLock
1853 // then take the slow path.
1854 jccb (Assembler::notZero, DONE_LABEL);
1855 // update _owner from BasicLock to thread
1856 get_thread (scrReg); // beware: clobbers ICCs
1857 movptr(Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), scrReg);
1858 xorptr(boxReg, boxReg); // set icc.ZFlag = 1 to indicate success
1859
1860 // If the CAS fails we can either retry or pass control to the slow-path.
1861 // We use the latter tactic.
1862 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1863 // If the CAS was successful ...
1864 // Self has acquired the lock
1865 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1866 // Intentional fall-through into DONE_LABEL ...
1867 } else {
1868 movptr(Address(boxReg, 0), intptr_t(markOopDesc::unused_mark())); // results in ST-before-CAS penalty
1869 movptr(boxReg, tmpReg);
1870
1871 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
1872 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
1873 // prefetchw [eax + Offset(_owner)-2]
1874 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1875 }
1876
1877 if ((EmitSync & 64) == 0) {
1878 // Optimistic form
1879 xorptr (tmpReg, tmpReg);
1880 } else {
1881 // Can suffer RTS->RTO upgrades on shared or cold $ lines
1882 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner
1883 testptr(tmpReg, tmpReg); // Locked ?
1884 jccb (Assembler::notZero, DONE_LABEL);
1885 }
1886
1887 // Appears unlocked - try to swing _owner from null to non-null.
1888 // Use either "Self" (in scr) or rsp as thread identity in _owner.
1889 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1890 get_thread (scrReg);
1891 if (os::is_MP()) {
1892 lock();
1893 }
1894 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1895
1896 // If the CAS fails we can either retry or pass control to the slow-path.
1897 // We use the latter tactic.
1898 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1899 // If the CAS was successful ...
1900 // Self has acquired the lock
1901 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1902 // Intentional fall-through into DONE_LABEL ...
1903 }
1904 #else // _LP64
1905 // It's inflated
1906 movq(scrReg, tmpReg);
1907 xorq(tmpReg, tmpReg);
1908
1909 if (os::is_MP()) {
1910 lock();
1911 }
1912 cmpxchgptr(r15_thread, Address(scrReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1913 // Unconditionally set box->_displaced_header = markOopDesc::unused_mark().
1914 // Without cast to int32_t movptr will destroy r10 which is typically obj.
1915 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1916 // Intentional fall-through into DONE_LABEL ...
1917 // Propagate ICC.ZF from CAS above into DONE_LABEL.
1918 #endif // _LP64
1919 #if INCLUDE_RTM_OPT
1920 } // use_rtm()
1921 #endif
1922 // DONE_LABEL is a hot target - we'd really like to place it at the
1923 // start of cache line by padding with NOPs.
1924 // See the AMD and Intel software optimization manuals for the
1925 // most efficient "long" NOP encodings.
1926 // Unfortunately none of our alignment mechanisms suffice.
1927 bind(DONE_LABEL);
1928
1929 // At DONE_LABEL the icc ZFlag is set as follows ...
1930 // Fast_Unlock uses the same protocol.
1931 // ZFlag == 1 -> Success
1932 // ZFlag == 0 -> Failure - force control through the slow-path
1933 }
1934 }
1935
1936 // obj: object to unlock
1937 // box: box address (displaced header location), killed. Must be EAX.
1938 // tmp: killed, cannot be obj nor box.
1939 //
1940 // Some commentary on balanced locking:
1941 //
1942 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
1943 // Methods that don't have provably balanced locking are forced to run in the
1944 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
1945 // The interpreter provides two properties:
1946 // I1: At return-time the interpreter automatically and quietly unlocks any
1947 // objects acquired the current activation (frame). Recall that the
1948 // interpreter maintains an on-stack list of locks currently held by
1949 // a frame.
1950 // I2: If a method attempts to unlock an object that is not held by the
1951 // the frame the interpreter throws IMSX.
1952 //
1953 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
1954 // B() doesn't have provably balanced locking so it runs in the interpreter.
1955 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
1956 // is still locked by A().
1957 //
1958 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
1959 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
1960 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
1961 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
1962 // Arguably given that the spec legislates the JNI case as undefined our implementation
1963 // could reasonably *avoid* checking owner in Fast_Unlock().
1964 // In the interest of performance we elide m->Owner==Self check in unlock.
1965 // A perfectly viable alternative is to elide the owner check except when
1966 // Xcheck:jni is enabled.
1967
1968 void MacroAssembler::fast_unlock(Register objReg, Register boxReg, Register tmpReg, bool use_rtm) {
1969 assert(boxReg == rax, "");
1970 assert_different_registers(objReg, boxReg, tmpReg);
1971
1972 if (EmitSync & 4) {
1973 // Disable - inhibit all inlining. Force control through the slow-path
1974 cmpptr (rsp, 0);
1975 } else {
1976 Label DONE_LABEL, Stacked, CheckSucc;
1977
1978 // Critically, the biased locking test must have precedence over
1979 // and appear before the (box->dhw == 0) recursive stack-lock test.
1980 if (UseBiasedLocking && !UseOptoBiasInlining) {
1981 biased_locking_exit(objReg, tmpReg, DONE_LABEL);
1982 }
1983
1984 #if INCLUDE_RTM_OPT
1985 if (UseRTMForStackLocks && use_rtm) {
1986 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
1987 Label L_regular_unlock;
1988 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // fetch markword
1989 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
1990 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked
1991 jccb(Assembler::notEqual, L_regular_unlock); // if !HLE RegularLock
1992 xend(); // otherwise end...
1993 jmp(DONE_LABEL); // ... and we're done
1994 bind(L_regular_unlock);
1995 }
1996 #endif
1997
1998 cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD); // Examine the displaced header
1999 jcc (Assembler::zero, DONE_LABEL); // 0 indicates recursive stack-lock
2000 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Examine the object's markword
2001 testptr(tmpReg, markOopDesc::monitor_value); // Inflated?
2002 jccb (Assembler::zero, Stacked);
2003
2004 // It's inflated.
2005 #if INCLUDE_RTM_OPT
2006 if (use_rtm) {
2007 Label L_regular_inflated_unlock;
2008 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
2009 movptr(boxReg, Address(tmpReg, owner_offset));
2010 testptr(boxReg, boxReg);
2011 jccb(Assembler::notZero, L_regular_inflated_unlock);
2012 xend();
2013 jmpb(DONE_LABEL);
2014 bind(L_regular_inflated_unlock);
2015 }
2016 #endif
2017
2018 // Despite our balanced locking property we still check that m->_owner == Self
2019 // as java routines or native JNI code called by this thread might
2020 // have released the lock.
2021 // Refer to the comments in synchronizer.cpp for how we might encode extra
2022 // state in _succ so we can avoid fetching EntryList|cxq.
2023 //
2024 // I'd like to add more cases in fast_lock() and fast_unlock() --
2025 // such as recursive enter and exit -- but we have to be wary of
2026 // I$ bloat, T$ effects and BP$ effects.
2027 //
2028 // If there's no contention try a 1-0 exit. That is, exit without
2029 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
2030 // we detect and recover from the race that the 1-0 exit admits.
2031 //
2032 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
2033 // before it STs null into _owner, releasing the lock. Updates
2034 // to data protected by the critical section must be visible before
2035 // we drop the lock (and thus before any other thread could acquire
2036 // the lock and observe the fields protected by the lock).
2037 // IA32's memory-model is SPO, so STs are ordered with respect to
2038 // each other and there's no need for an explicit barrier (fence).
2039 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
2040 #ifndef _LP64
2041 get_thread (boxReg);
2042 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
2043 // prefetchw [ebx + Offset(_owner)-2]
2044 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2045 }
2046
2047 // Note that we could employ various encoding schemes to reduce
2048 // the number of loads below (currently 4) to just 2 or 3.
2049 // Refer to the comments in synchronizer.cpp.
2050 // In practice the chain of fetches doesn't seem to impact performance, however.
2051 xorptr(boxReg, boxReg);
2052 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
2053 // Attempt to reduce branch density - AMD's branch predictor.
2054 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2055 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2056 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2057 jccb (Assembler::notZero, DONE_LABEL);
2058 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2059 jmpb (DONE_LABEL);
2060 } else {
2061 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2062 jccb (Assembler::notZero, DONE_LABEL);
2063 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2064 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2065 jccb (Assembler::notZero, CheckSucc);
2066 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2067 jmpb (DONE_LABEL);
2068 }
2069
2070 // The Following code fragment (EmitSync & 65536) improves the performance of
2071 // contended applications and contended synchronization microbenchmarks.
2072 // Unfortunately the emission of the code - even though not executed - causes regressions
2073 // in scimark and jetstream, evidently because of $ effects. Replacing the code
2074 // with an equal number of never-executed NOPs results in the same regression.
2075 // We leave it off by default.
2076
2077 if ((EmitSync & 65536) != 0) {
2078 Label LSuccess, LGoSlowPath ;
2079
2080 bind (CheckSucc);
2081
2082 // Optional pre-test ... it's safe to elide this
2083 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2084 jccb(Assembler::zero, LGoSlowPath);
2085
2086 // We have a classic Dekker-style idiom:
2087 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
2088 // There are a number of ways to implement the barrier:
2089 // (1) lock:andl &m->_owner, 0
2090 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
2091 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
2092 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
2093 // (2) If supported, an explicit MFENCE is appealing.
2094 // In older IA32 processors MFENCE is slower than lock:add or xchg
2095 // particularly if the write-buffer is full as might be the case if
2096 // if stores closely precede the fence or fence-equivalent instruction.
2097 // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences
2098 // as the situation has changed with Nehalem and Shanghai.
2099 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
2100 // The $lines underlying the top-of-stack should be in M-state.
2101 // The locked add instruction is serializing, of course.
2102 // (4) Use xchg, which is serializing
2103 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
2104 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
2105 // The integer condition codes will tell us if succ was 0.
2106 // Since _succ and _owner should reside in the same $line and
2107 // we just stored into _owner, it's likely that the $line
2108 // remains in M-state for the lock:orl.
2109 //
2110 // We currently use (3), although it's likely that switching to (2)
2111 // is correct for the future.
2112
2113 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2114 if (os::is_MP()) {
2115 lock(); addptr(Address(rsp, 0), 0);
2116 }
2117 // Ratify _succ remains non-null
2118 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), 0);
2119 jccb (Assembler::notZero, LSuccess);
2120
2121 xorptr(boxReg, boxReg); // box is really EAX
2122 if (os::is_MP()) { lock(); }
2123 cmpxchgptr(rsp, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2124 // There's no successor so we tried to regrab the lock with the
2125 // placeholder value. If that didn't work, then another thread
2126 // grabbed the lock so we're done (and exit was a success).
2127 jccb (Assembler::notEqual, LSuccess);
2128 // Since we're low on registers we installed rsp as a placeholding in _owner.
2129 // Now install Self over rsp. This is safe as we're transitioning from
2130 // non-null to non=null
2131 get_thread (boxReg);
2132 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), boxReg);
2133 // Intentional fall-through into LGoSlowPath ...
2134
2135 bind (LGoSlowPath);
2136 orptr(boxReg, 1); // set ICC.ZF=0 to indicate failure
2137 jmpb (DONE_LABEL);
2138
2139 bind (LSuccess);
2140 xorptr(boxReg, boxReg); // set ICC.ZF=1 to indicate success
2141 jmpb (DONE_LABEL);
2142 }
2143
2144 bind (Stacked);
2145 // It's not inflated and it's not recursively stack-locked and it's not biased.
2146 // It must be stack-locked.
2147 // Try to reset the header to displaced header.
2148 // The "box" value on the stack is stable, so we can reload
2149 // and be assured we observe the same value as above.
2150 movptr(tmpReg, Address(boxReg, 0));
2151 if (os::is_MP()) {
2152 lock();
2153 }
2154 cmpxchgptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Uses RAX which is box
2155 // Intention fall-thru into DONE_LABEL
2156
2157 // DONE_LABEL is a hot target - we'd really like to place it at the
2158 // start of cache line by padding with NOPs.
2159 // See the AMD and Intel software optimization manuals for the
2160 // most efficient "long" NOP encodings.
2161 // Unfortunately none of our alignment mechanisms suffice.
2162 if ((EmitSync & 65536) == 0) {
2163 bind (CheckSucc);
2164 }
2165 #else // _LP64
2166 // It's inflated
2167 if (EmitSync & 1024) {
2168 // Emit code to check that _owner == Self
2169 // We could fold the _owner test into subsequent code more efficiently
2170 // than using a stand-alone check, but since _owner checking is off by
2171 // default we don't bother. We also might consider predicating the
2172 // _owner==Self check on Xcheck:jni or running on a debug build.
2173 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2174 xorptr(boxReg, r15_thread);
2175 } else {
2176 xorptr(boxReg, boxReg);
2177 }
2178 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2179 jccb (Assembler::notZero, DONE_LABEL);
2180 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2181 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2182 jccb (Assembler::notZero, CheckSucc);
2183 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD);
2184 jmpb (DONE_LABEL);
2185
2186 if ((EmitSync & 65536) == 0) {
2187 // Try to avoid passing control into the slow_path ...
2188 Label LSuccess, LGoSlowPath ;
2189 bind (CheckSucc);
2190
2191 // The following optional optimization can be elided if necessary
2192 // Effectively: if (succ == null) goto SlowPath
2193 // The code reduces the window for a race, however,
2194 // and thus benefits performance.
2195 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2196 jccb (Assembler::zero, LGoSlowPath);
2197
2198 xorptr(boxReg, boxReg);
2199 if ((EmitSync & 16) && os::is_MP()) {
2200 xchgptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2201 } else {
2202 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD);
2203 if (os::is_MP()) {
2204 // Memory barrier/fence
2205 // Dekker pivot point -- fulcrum : ST Owner; MEMBAR; LD Succ
2206 // Instead of MFENCE we use a dummy locked add of 0 to the top-of-stack.
2207 // This is faster on Nehalem and AMD Shanghai/Barcelona.
2208 // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences
2209 // We might also restructure (ST Owner=0;barrier;LD _Succ) to
2210 // (mov box,0; xchgq box, &m->Owner; LD _succ) .
2211 lock(); addl(Address(rsp, 0), 0);
2212 }
2213 }
2214 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2215 jccb (Assembler::notZero, LSuccess);
2216
2217 // Rare inopportune interleaving - race.
2218 // The successor vanished in the small window above.
2219 // The lock is contended -- (cxq|EntryList) != null -- and there's no apparent successor.
2220 // We need to ensure progress and succession.
2221 // Try to reacquire the lock.
2222 // If that fails then the new owner is responsible for succession and this
2223 // thread needs to take no further action and can exit via the fast path (success).
2224 // If the re-acquire succeeds then pass control into the slow path.
2225 // As implemented, this latter mode is horrible because we generated more
2226 // coherence traffic on the lock *and* artifically extended the critical section
2227 // length while by virtue of passing control into the slow path.
2228
2229 // box is really RAX -- the following CMPXCHG depends on that binding
2230 // cmpxchg R,[M] is equivalent to rax = CAS(M,rax,R)
2231 if (os::is_MP()) { lock(); }
2232 cmpxchgptr(r15_thread, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2233 // There's no successor so we tried to regrab the lock.
2234 // If that didn't work, then another thread grabbed the
2235 // lock so we're done (and exit was a success).
2236 jccb (Assembler::notEqual, LSuccess);
2237 // Intentional fall-through into slow-path
2238
2239 bind (LGoSlowPath);
2240 orl (boxReg, 1); // set ICC.ZF=0 to indicate failure
2241 jmpb (DONE_LABEL);
2242
2243 bind (LSuccess);
2244 testl (boxReg, 0); // set ICC.ZF=1 to indicate success
2245 jmpb (DONE_LABEL);
2246 }
2247
2248 bind (Stacked);
2249 movptr(tmpReg, Address (boxReg, 0)); // re-fetch
2250 if (os::is_MP()) { lock(); }
2251 cmpxchgptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Uses RAX which is box
2252
2253 if (EmitSync & 65536) {
2254 bind (CheckSucc);
2255 }
2256 #endif
2257 bind(DONE_LABEL);
2258 }
2259 }
2260 #endif // COMPILER2
2261
2262 void MacroAssembler::c2bool(Register x) {
2263 // implements x == 0 ? 0 : 1
2264 // note: must only look at least-significant byte of x
2265 // since C-style booleans are stored in one byte
2266 // only! (was bug)
2267 andl(x, 0xFF);
2268 setb(Assembler::notZero, x);
2269 }
2270
2271 // Wouldn't need if AddressLiteral version had new name
2272 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
2273 Assembler::call(L, rtype);
2274 }
2275
2276 void MacroAssembler::call(Register entry) {
2277 Assembler::call(entry);
2278 }
2279
2280 void MacroAssembler::call(AddressLiteral entry) {
2281 if (reachable(entry)) {
2282 Assembler::call_literal(entry.target(), entry.rspec());
2283 } else {
2284 lea(rscratch1, entry);
2285 Assembler::call(rscratch1);
2286 }
2287 }
2288
2289 void MacroAssembler::ic_call(address entry, jint method_index) {
2290 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
2291 movptr(rax, (intptr_t)Universe::non_oop_word());
2292 call(AddressLiteral(entry, rh));
2293 }
2294
2295 // Implementation of call_VM versions
2296
2297 void MacroAssembler::call_VM(Register oop_result,
2298 address entry_point,
2299 bool check_exceptions) {
2300 Label C, E;
2301 call(C, relocInfo::none);
2302 jmp(E);
2303
2304 bind(C);
2305 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
2306 ret(0);
2307
2308 bind(E);
2309 }
2310
2311 void MacroAssembler::call_VM(Register oop_result,
2312 address entry_point,
2313 Register arg_1,
2314 bool check_exceptions) {
2315 Label C, E;
2316 call(C, relocInfo::none);
2317 jmp(E);
2318
2319 bind(C);
2320 pass_arg1(this, arg_1);
2321 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
2322 ret(0);
2323
2324 bind(E);
2325 }
2326
2327 void MacroAssembler::call_VM(Register oop_result,
2328 address entry_point,
2329 Register arg_1,
2330 Register arg_2,
2331 bool check_exceptions) {
2332 Label C, E;
2333 call(C, relocInfo::none);
2334 jmp(E);
2335
2336 bind(C);
2337
2338 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2339
2340 pass_arg2(this, arg_2);
2341 pass_arg1(this, arg_1);
2342 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
2343 ret(0);
2344
2345 bind(E);
2346 }
2347
2348 void MacroAssembler::call_VM(Register oop_result,
2349 address entry_point,
2350 Register arg_1,
2351 Register arg_2,
2352 Register arg_3,
2353 bool check_exceptions) {
2354 Label C, E;
2355 call(C, relocInfo::none);
2356 jmp(E);
2357
2358 bind(C);
2359
2360 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2361 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2362 pass_arg3(this, arg_3);
2363
2364 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2365 pass_arg2(this, arg_2);
2366
2367 pass_arg1(this, arg_1);
2368 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
2369 ret(0);
2370
2371 bind(E);
2372 }
2373
2374 void MacroAssembler::call_VM(Register oop_result,
2375 Register last_java_sp,
2376 address entry_point,
2377 int number_of_arguments,
2378 bool check_exceptions) {
2379 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2380 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2381 }
2382
2383 void MacroAssembler::call_VM(Register oop_result,
2384 Register last_java_sp,
2385 address entry_point,
2386 Register arg_1,
2387 bool check_exceptions) {
2388 pass_arg1(this, arg_1);
2389 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2390 }
2391
2392 void MacroAssembler::call_VM(Register oop_result,
2393 Register last_java_sp,
2394 address entry_point,
2395 Register arg_1,
2396 Register arg_2,
2397 bool check_exceptions) {
2398
2399 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2400 pass_arg2(this, arg_2);
2401 pass_arg1(this, arg_1);
2402 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2403 }
2404
2405 void MacroAssembler::call_VM(Register oop_result,
2406 Register last_java_sp,
2407 address entry_point,
2408 Register arg_1,
2409 Register arg_2,
2410 Register arg_3,
2411 bool check_exceptions) {
2412 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2413 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2414 pass_arg3(this, arg_3);
2415 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2416 pass_arg2(this, arg_2);
2417 pass_arg1(this, arg_1);
2418 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2419 }
2420
2421 void MacroAssembler::super_call_VM(Register oop_result,
2422 Register last_java_sp,
2423 address entry_point,
2424 int number_of_arguments,
2425 bool check_exceptions) {
2426 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2427 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2428 }
2429
2430 void MacroAssembler::super_call_VM(Register oop_result,
2431 Register last_java_sp,
2432 address entry_point,
2433 Register arg_1,
2434 bool check_exceptions) {
2435 pass_arg1(this, arg_1);
2436 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2437 }
2438
2439 void MacroAssembler::super_call_VM(Register oop_result,
2440 Register last_java_sp,
2441 address entry_point,
2442 Register arg_1,
2443 Register arg_2,
2444 bool check_exceptions) {
2445
2446 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2447 pass_arg2(this, arg_2);
2448 pass_arg1(this, arg_1);
2449 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2450 }
2451
2452 void MacroAssembler::super_call_VM(Register oop_result,
2453 Register last_java_sp,
2454 address entry_point,
2455 Register arg_1,
2456 Register arg_2,
2457 Register arg_3,
2458 bool check_exceptions) {
2459 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2460 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2461 pass_arg3(this, arg_3);
2462 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2463 pass_arg2(this, arg_2);
2464 pass_arg1(this, arg_1);
2465 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2466 }
2467
2468 void MacroAssembler::call_VM_base(Register oop_result,
2469 Register java_thread,
2470 Register last_java_sp,
2471 address entry_point,
2472 int number_of_arguments,
2473 bool check_exceptions) {
2474 // determine java_thread register
2475 if (!java_thread->is_valid()) {
2476 #ifdef _LP64
2477 java_thread = r15_thread;
2478 #else
2479 java_thread = rdi;
2480 get_thread(java_thread);
2481 #endif // LP64
2482 }
2483 // determine last_java_sp register
2484 if (!last_java_sp->is_valid()) {
2485 last_java_sp = rsp;
2486 }
2487 // debugging support
2488 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
2489 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
2490 #ifdef ASSERT
2491 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
2492 // r12 is the heapbase.
2493 LP64_ONLY(if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");)
2494 #endif // ASSERT
2495
2496 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
2497 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
2498
2499 // push java thread (becomes first argument of C function)
2500
2501 NOT_LP64(push(java_thread); number_of_arguments++);
2502 LP64_ONLY(mov(c_rarg0, r15_thread));
2503
2504 // set last Java frame before call
2505 assert(last_java_sp != rbp, "can't use ebp/rbp");
2506
2507 // Only interpreter should have to set fp
2508 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL);
2509
2510 // do the call, remove parameters
2511 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
2512
2513 // restore the thread (cannot use the pushed argument since arguments
2514 // may be overwritten by C code generated by an optimizing compiler);
2515 // however can use the register value directly if it is callee saved.
2516 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
2517 // rdi & rsi (also r15) are callee saved -> nothing to do
2518 #ifdef ASSERT
2519 guarantee(java_thread != rax, "change this code");
2520 push(rax);
2521 { Label L;
2522 get_thread(rax);
2523 cmpptr(java_thread, rax);
2524 jcc(Assembler::equal, L);
2525 STOP("MacroAssembler::call_VM_base: rdi not callee saved?");
2526 bind(L);
2527 }
2528 pop(rax);
2529 #endif
2530 } else {
2531 get_thread(java_thread);
2532 }
2533 // reset last Java frame
2534 // Only interpreter should have to clear fp
2535 reset_last_Java_frame(java_thread, true);
2536
2537 // C++ interp handles this in the interpreter
2538 check_and_handle_popframe(java_thread);
2539 check_and_handle_earlyret(java_thread);
2540
2541 if (check_exceptions) {
2542 // check for pending exceptions (java_thread is set upon return)
2543 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD);
2544 #ifndef _LP64
2545 jump_cc(Assembler::notEqual,
2546 RuntimeAddress(StubRoutines::forward_exception_entry()));
2547 #else
2548 // This used to conditionally jump to forward_exception however it is
2549 // possible if we relocate that the branch will not reach. So we must jump
2550 // around so we can always reach
2551
2552 Label ok;
2553 jcc(Assembler::equal, ok);
2554 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
2555 bind(ok);
2556 #endif // LP64
2557 }
2558
2559 // get oop result if there is one and reset the value in the thread
2560 if (oop_result->is_valid()) {
2561 get_vm_result(oop_result, java_thread);
2562 }
2563 }
2564
2565 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
2566
2567 // Calculate the value for last_Java_sp
2568 // somewhat subtle. call_VM does an intermediate call
2569 // which places a return address on the stack just under the
2570 // stack pointer as the user finsihed with it. This allows
2571 // use to retrieve last_Java_pc from last_Java_sp[-1].
2572 // On 32bit we then have to push additional args on the stack to accomplish
2573 // the actual requested call. On 64bit call_VM only can use register args
2574 // so the only extra space is the return address that call_VM created.
2575 // This hopefully explains the calculations here.
2576
2577 #ifdef _LP64
2578 // We've pushed one address, correct last_Java_sp
2579 lea(rax, Address(rsp, wordSize));
2580 #else
2581 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
2582 #endif // LP64
2583
2584 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
2585
2586 }
2587
2588 // Use this method when MacroAssembler version of call_VM_leaf_base() should be called from Interpreter.
2589 void MacroAssembler::call_VM_leaf0(address entry_point) {
2590 MacroAssembler::call_VM_leaf_base(entry_point, 0);
2591 }
2592
2593 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
2594 call_VM_leaf_base(entry_point, number_of_arguments);
2595 }
2596
2597 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
2598 pass_arg0(this, arg_0);
2599 call_VM_leaf(entry_point, 1);
2600 }
2601
2602 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2603
2604 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2605 pass_arg1(this, arg_1);
2606 pass_arg0(this, arg_0);
2607 call_VM_leaf(entry_point, 2);
2608 }
2609
2610 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2611 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2612 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2613 pass_arg2(this, arg_2);
2614 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2615 pass_arg1(this, arg_1);
2616 pass_arg0(this, arg_0);
2617 call_VM_leaf(entry_point, 3);
2618 }
2619
2620 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
2621 pass_arg0(this, arg_0);
2622 MacroAssembler::call_VM_leaf_base(entry_point, 1);
2623 }
2624
2625 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2626
2627 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2628 pass_arg1(this, arg_1);
2629 pass_arg0(this, arg_0);
2630 MacroAssembler::call_VM_leaf_base(entry_point, 2);
2631 }
2632
2633 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2634 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2635 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2636 pass_arg2(this, arg_2);
2637 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2638 pass_arg1(this, arg_1);
2639 pass_arg0(this, arg_0);
2640 MacroAssembler::call_VM_leaf_base(entry_point, 3);
2641 }
2642
2643 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
2644 LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg"));
2645 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2646 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2647 pass_arg3(this, arg_3);
2648 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2649 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2650 pass_arg2(this, arg_2);
2651 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2652 pass_arg1(this, arg_1);
2653 pass_arg0(this, arg_0);
2654 MacroAssembler::call_VM_leaf_base(entry_point, 4);
2655 }
2656
2657 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
2658 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
2659 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
2660 verify_oop(oop_result, "broken oop in call_VM_base");
2661 }
2662
2663 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
2664 movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
2665 movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD);
2666 }
2667
2668 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
2669 }
2670
2671 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
2672 }
2673
2674 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) {
2675 if (reachable(src1)) {
2676 cmpl(as_Address(src1), imm);
2677 } else {
2678 lea(rscratch1, src1);
2679 cmpl(Address(rscratch1, 0), imm);
2680 }
2681 }
2682
2683 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) {
2684 assert(!src2.is_lval(), "use cmpptr");
2685 if (reachable(src2)) {
2686 cmpl(src1, as_Address(src2));
2687 } else {
2688 lea(rscratch1, src2);
2689 cmpl(src1, Address(rscratch1, 0));
2690 }
2691 }
2692
2693 void MacroAssembler::cmp32(Register src1, int32_t imm) {
2694 Assembler::cmpl(src1, imm);
2695 }
2696
2697 void MacroAssembler::cmp32(Register src1, Address src2) {
2698 Assembler::cmpl(src1, src2);
2699 }
2700
2701 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2702 ucomisd(opr1, opr2);
2703
2704 Label L;
2705 if (unordered_is_less) {
2706 movl(dst, -1);
2707 jcc(Assembler::parity, L);
2708 jcc(Assembler::below , L);
2709 movl(dst, 0);
2710 jcc(Assembler::equal , L);
2711 increment(dst);
2712 } else { // unordered is greater
2713 movl(dst, 1);
2714 jcc(Assembler::parity, L);
2715 jcc(Assembler::above , L);
2716 movl(dst, 0);
2717 jcc(Assembler::equal , L);
2718 decrementl(dst);
2719 }
2720 bind(L);
2721 }
2722
2723 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2724 ucomiss(opr1, opr2);
2725
2726 Label L;
2727 if (unordered_is_less) {
2728 movl(dst, -1);
2729 jcc(Assembler::parity, L);
2730 jcc(Assembler::below , L);
2731 movl(dst, 0);
2732 jcc(Assembler::equal , L);
2733 increment(dst);
2734 } else { // unordered is greater
2735 movl(dst, 1);
2736 jcc(Assembler::parity, L);
2737 jcc(Assembler::above , L);
2738 movl(dst, 0);
2739 jcc(Assembler::equal , L);
2740 decrementl(dst);
2741 }
2742 bind(L);
2743 }
2744
2745
2746 void MacroAssembler::cmp8(AddressLiteral src1, int imm) {
2747 if (reachable(src1)) {
2748 cmpb(as_Address(src1), imm);
2749 } else {
2750 lea(rscratch1, src1);
2751 cmpb(Address(rscratch1, 0), imm);
2752 }
2753 }
2754
2755 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) {
2756 #ifdef _LP64
2757 if (src2.is_lval()) {
2758 movptr(rscratch1, src2);
2759 Assembler::cmpq(src1, rscratch1);
2760 } else if (reachable(src2)) {
2761 cmpq(src1, as_Address(src2));
2762 } else {
2763 lea(rscratch1, src2);
2764 Assembler::cmpq(src1, Address(rscratch1, 0));
2765 }
2766 #else
2767 if (src2.is_lval()) {
2768 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2769 } else {
2770 cmpl(src1, as_Address(src2));
2771 }
2772 #endif // _LP64
2773 }
2774
2775 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) {
2776 assert(src2.is_lval(), "not a mem-mem compare");
2777 #ifdef _LP64
2778 // moves src2's literal address
2779 movptr(rscratch1, src2);
2780 Assembler::cmpq(src1, rscratch1);
2781 #else
2782 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2783 #endif // _LP64
2784 }
2785
2786 void MacroAssembler::cmpoop(Register src1, Register src2) {
2787 cmpptr(src1, src2);
2788 }
2789
2790 void MacroAssembler::cmpoop(Register src1, Address src2) {
2791 cmpptr(src1, src2);
2792 }
2793
2794 #ifdef _LP64
2795 void MacroAssembler::cmpoop(Register src1, jobject src2) {
2796 movoop(rscratch1, src2);
2797 cmpptr(src1, rscratch1);
2798 }
2799 #endif
2800
2801 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) {
2802 if (reachable(adr)) {
2803 if (os::is_MP())
2804 lock();
2805 cmpxchgptr(reg, as_Address(adr));
2806 } else {
2807 lea(rscratch1, adr);
2808 if (os::is_MP())
2809 lock();
2810 cmpxchgptr(reg, Address(rscratch1, 0));
2811 }
2812 }
2813
2814 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
2815 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
2816 }
2817
2818 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) {
2819 if (reachable(src)) {
2820 Assembler::comisd(dst, as_Address(src));
2821 } else {
2822 lea(rscratch1, src);
2823 Assembler::comisd(dst, Address(rscratch1, 0));
2824 }
2825 }
2826
2827 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) {
2828 if (reachable(src)) {
2829 Assembler::comiss(dst, as_Address(src));
2830 } else {
2831 lea(rscratch1, src);
2832 Assembler::comiss(dst, Address(rscratch1, 0));
2833 }
2834 }
2835
2836
2837 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) {
2838 Condition negated_cond = negate_condition(cond);
2839 Label L;
2840 jcc(negated_cond, L);
2841 pushf(); // Preserve flags
2842 atomic_incl(counter_addr);
2843 popf();
2844 bind(L);
2845 }
2846
2847 int MacroAssembler::corrected_idivl(Register reg) {
2848 // Full implementation of Java idiv and irem; checks for
2849 // special case as described in JVM spec., p.243 & p.271.
2850 // The function returns the (pc) offset of the idivl
2851 // instruction - may be needed for implicit exceptions.
2852 //
2853 // normal case special case
2854 //
2855 // input : rax,: dividend min_int
2856 // reg: divisor (may not be rax,/rdx) -1
2857 //
2858 // output: rax,: quotient (= rax, idiv reg) min_int
2859 // rdx: remainder (= rax, irem reg) 0
2860 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
2861 const int min_int = 0x80000000;
2862 Label normal_case, special_case;
2863
2864 // check for special case
2865 cmpl(rax, min_int);
2866 jcc(Assembler::notEqual, normal_case);
2867 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
2868 cmpl(reg, -1);
2869 jcc(Assembler::equal, special_case);
2870
2871 // handle normal case
2872 bind(normal_case);
2873 cdql();
2874 int idivl_offset = offset();
2875 idivl(reg);
2876
2877 // normal and special case exit
2878 bind(special_case);
2879
2880 return idivl_offset;
2881 }
2882
2883
2884
2885 void MacroAssembler::decrementl(Register reg, int value) {
2886 if (value == min_jint) {subl(reg, value) ; return; }
2887 if (value < 0) { incrementl(reg, -value); return; }
2888 if (value == 0) { ; return; }
2889 if (value == 1 && UseIncDec) { decl(reg) ; return; }
2890 /* else */ { subl(reg, value) ; return; }
2891 }
2892
2893 void MacroAssembler::decrementl(Address dst, int value) {
2894 if (value == min_jint) {subl(dst, value) ; return; }
2895 if (value < 0) { incrementl(dst, -value); return; }
2896 if (value == 0) { ; return; }
2897 if (value == 1 && UseIncDec) { decl(dst) ; return; }
2898 /* else */ { subl(dst, value) ; return; }
2899 }
2900
2901 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
2902 assert (shift_value > 0, "illegal shift value");
2903 Label _is_positive;
2904 testl (reg, reg);
2905 jcc (Assembler::positive, _is_positive);
2906 int offset = (1 << shift_value) - 1 ;
2907
2908 if (offset == 1) {
2909 incrementl(reg);
2910 } else {
2911 addl(reg, offset);
2912 }
2913
2914 bind (_is_positive);
2915 sarl(reg, shift_value);
2916 }
2917
2918 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) {
2919 if (reachable(src)) {
2920 Assembler::divsd(dst, as_Address(src));
2921 } else {
2922 lea(rscratch1, src);
2923 Assembler::divsd(dst, Address(rscratch1, 0));
2924 }
2925 }
2926
2927 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) {
2928 if (reachable(src)) {
2929 Assembler::divss(dst, as_Address(src));
2930 } else {
2931 lea(rscratch1, src);
2932 Assembler::divss(dst, Address(rscratch1, 0));
2933 }
2934 }
2935
2936 // !defined(COMPILER2) is because of stupid core builds
2937 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2) || INCLUDE_JVMCI
2938 void MacroAssembler::empty_FPU_stack() {
2939 if (VM_Version::supports_mmx()) {
2940 emms();
2941 } else {
2942 for (int i = 8; i-- > 0; ) ffree(i);
2943 }
2944 }
2945 #endif // !LP64 || C1 || !C2 || INCLUDE_JVMCI
2946
2947
2948 // Defines obj, preserves var_size_in_bytes
2949 void MacroAssembler::eden_allocate(Register obj,
2950 Register var_size_in_bytes,
2951 int con_size_in_bytes,
2952 Register t1,
2953 Label& slow_case) {
2954 assert(obj == rax, "obj must be in rax, for cmpxchg");
2955 assert_different_registers(obj, var_size_in_bytes, t1);
2956 if (!Universe::heap()->supports_inline_contig_alloc()) {
2957 jmp(slow_case);
2958 } else {
2959 Register end = t1;
2960 Label retry;
2961 bind(retry);
2962 ExternalAddress heap_top((address) Universe::heap()->top_addr());
2963 movptr(obj, heap_top);
2964 if (var_size_in_bytes == noreg) {
2965 lea(end, Address(obj, con_size_in_bytes));
2966 } else {
2967 lea(end, Address(obj, var_size_in_bytes, Address::times_1));
2968 }
2969 // if end < obj then we wrapped around => object too long => slow case
2970 cmpptr(end, obj);
2971 jcc(Assembler::below, slow_case);
2972 cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr()));
2973 jcc(Assembler::above, slow_case);
2974 // Compare obj with the top addr, and if still equal, store the new top addr in
2975 // end at the address of the top addr pointer. Sets ZF if was equal, and clears
2976 // it otherwise. Use lock prefix for atomicity on MPs.
2977 locked_cmpxchgptr(end, heap_top);
2978 jcc(Assembler::notEqual, retry);
2979 }
2980 }
2981
2982 void MacroAssembler::enter() {
2983 push(rbp);
2984 mov(rbp, rsp);
2985 }
2986
2987 // A 5 byte nop that is safe for patching (see patch_verified_entry)
2988 void MacroAssembler::fat_nop() {
2989 if (UseAddressNop) {
2990 addr_nop_5();
2991 } else {
2992 emit_int8(0x26); // es:
2993 emit_int8(0x2e); // cs:
2994 emit_int8(0x64); // fs:
2995 emit_int8(0x65); // gs:
2996 emit_int8((unsigned char)0x90);
2997 }
2998 }
2999
3000 void MacroAssembler::fcmp(Register tmp) {
3001 fcmp(tmp, 1, true, true);
3002 }
3003
3004 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
3005 assert(!pop_right || pop_left, "usage error");
3006 if (VM_Version::supports_cmov()) {
3007 assert(tmp == noreg, "unneeded temp");
3008 if (pop_left) {
3009 fucomip(index);
3010 } else {
3011 fucomi(index);
3012 }
3013 if (pop_right) {
3014 fpop();
3015 }
3016 } else {
3017 assert(tmp != noreg, "need temp");
3018 if (pop_left) {
3019 if (pop_right) {
3020 fcompp();
3021 } else {
3022 fcomp(index);
3023 }
3024 } else {
3025 fcom(index);
3026 }
3027 // convert FPU condition into eflags condition via rax,
3028 save_rax(tmp);
3029 fwait(); fnstsw_ax();
3030 sahf();
3031 restore_rax(tmp);
3032 }
3033 // condition codes set as follows:
3034 //
3035 // CF (corresponds to C0) if x < y
3036 // PF (corresponds to C2) if unordered
3037 // ZF (corresponds to C3) if x = y
3038 }
3039
3040 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
3041 fcmp2int(dst, unordered_is_less, 1, true, true);
3042 }
3043
3044 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
3045 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
3046 Label L;
3047 if (unordered_is_less) {
3048 movl(dst, -1);
3049 jcc(Assembler::parity, L);
3050 jcc(Assembler::below , L);
3051 movl(dst, 0);
3052 jcc(Assembler::equal , L);
3053 increment(dst);
3054 } else { // unordered is greater
3055 movl(dst, 1);
3056 jcc(Assembler::parity, L);
3057 jcc(Assembler::above , L);
3058 movl(dst, 0);
3059 jcc(Assembler::equal , L);
3060 decrementl(dst);
3061 }
3062 bind(L);
3063 }
3064
3065 void MacroAssembler::fld_d(AddressLiteral src) {
3066 fld_d(as_Address(src));
3067 }
3068
3069 void MacroAssembler::fld_s(AddressLiteral src) {
3070 fld_s(as_Address(src));
3071 }
3072
3073 void MacroAssembler::fld_x(AddressLiteral src) {
3074 Assembler::fld_x(as_Address(src));
3075 }
3076
3077 void MacroAssembler::fldcw(AddressLiteral src) {
3078 Assembler::fldcw(as_Address(src));
3079 }
3080
3081 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src) {
3082 if (reachable(src)) {
3083 Assembler::mulpd(dst, as_Address(src));
3084 } else {
3085 lea(rscratch1, src);
3086 Assembler::mulpd(dst, Address(rscratch1, 0));
3087 }
3088 }
3089
3090 void MacroAssembler::increase_precision() {
3091 subptr(rsp, BytesPerWord);
3092 fnstcw(Address(rsp, 0));
3093 movl(rax, Address(rsp, 0));
3094 orl(rax, 0x300);
3095 push(rax);
3096 fldcw(Address(rsp, 0));
3097 pop(rax);
3098 }
3099
3100 void MacroAssembler::restore_precision() {
3101 fldcw(Address(rsp, 0));
3102 addptr(rsp, BytesPerWord);
3103 }
3104
3105 void MacroAssembler::fpop() {
3106 ffree();
3107 fincstp();
3108 }
3109
3110 void MacroAssembler::load_float(Address src) {
3111 if (UseSSE >= 1) {
3112 movflt(xmm0, src);
3113 } else {
3114 LP64_ONLY(ShouldNotReachHere());
3115 NOT_LP64(fld_s(src));
3116 }
3117 }
3118
3119 void MacroAssembler::store_float(Address dst) {
3120 if (UseSSE >= 1) {
3121 movflt(dst, xmm0);
3122 } else {
3123 LP64_ONLY(ShouldNotReachHere());
3124 NOT_LP64(fstp_s(dst));
3125 }
3126 }
3127
3128 void MacroAssembler::load_double(Address src) {
3129 if (UseSSE >= 2) {
3130 movdbl(xmm0, src);
3131 } else {
3132 LP64_ONLY(ShouldNotReachHere());
3133 NOT_LP64(fld_d(src));
3134 }
3135 }
3136
3137 void MacroAssembler::store_double(Address dst) {
3138 if (UseSSE >= 2) {
3139 movdbl(dst, xmm0);
3140 } else {
3141 LP64_ONLY(ShouldNotReachHere());
3142 NOT_LP64(fstp_d(dst));
3143 }
3144 }
3145
3146 void MacroAssembler::fremr(Register tmp) {
3147 save_rax(tmp);
3148 { Label L;
3149 bind(L);
3150 fprem();
3151 fwait(); fnstsw_ax();
3152 #ifdef _LP64
3153 testl(rax, 0x400);
3154 jcc(Assembler::notEqual, L);
3155 #else
3156 sahf();
3157 jcc(Assembler::parity, L);
3158 #endif // _LP64
3159 }
3160 restore_rax(tmp);
3161 // Result is in ST0.
3162 // Note: fxch & fpop to get rid of ST1
3163 // (otherwise FPU stack could overflow eventually)
3164 fxch(1);
3165 fpop();
3166 }
3167
3168 // dst = c = a * b + c
3169 void MacroAssembler::fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
3170 Assembler::vfmadd231sd(c, a, b);
3171 if (dst != c) {
3172 movdbl(dst, c);
3173 }
3174 }
3175
3176 // dst = c = a * b + c
3177 void MacroAssembler::fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
3178 Assembler::vfmadd231ss(c, a, b);
3179 if (dst != c) {
3180 movflt(dst, c);
3181 }
3182 }
3183
3184 // dst = c = a * b + c
3185 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
3186 Assembler::vfmadd231pd(c, a, b, vector_len);
3187 if (dst != c) {
3188 vmovdqu(dst, c);
3189 }
3190 }
3191
3192 // dst = c = a * b + c
3193 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
3194 Assembler::vfmadd231ps(c, a, b, vector_len);
3195 if (dst != c) {
3196 vmovdqu(dst, c);
3197 }
3198 }
3199
3200 // dst = c = a * b + c
3201 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
3202 Assembler::vfmadd231pd(c, a, b, vector_len);
3203 if (dst != c) {
3204 vmovdqu(dst, c);
3205 }
3206 }
3207
3208 // dst = c = a * b + c
3209 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
3210 Assembler::vfmadd231ps(c, a, b, vector_len);
3211 if (dst != c) {
3212 vmovdqu(dst, c);
3213 }
3214 }
3215
3216 void MacroAssembler::incrementl(AddressLiteral dst) {
3217 if (reachable(dst)) {
3218 incrementl(as_Address(dst));
3219 } else {
3220 lea(rscratch1, dst);
3221 incrementl(Address(rscratch1, 0));
3222 }
3223 }
3224
3225 void MacroAssembler::incrementl(ArrayAddress dst) {
3226 incrementl(as_Address(dst));
3227 }
3228
3229 void MacroAssembler::incrementl(Register reg, int value) {
3230 if (value == min_jint) {addl(reg, value) ; return; }
3231 if (value < 0) { decrementl(reg, -value); return; }
3232 if (value == 0) { ; return; }
3233 if (value == 1 && UseIncDec) { incl(reg) ; return; }
3234 /* else */ { addl(reg, value) ; return; }
3235 }
3236
3237 void MacroAssembler::incrementl(Address dst, int value) {
3238 if (value == min_jint) {addl(dst, value) ; return; }
3239 if (value < 0) { decrementl(dst, -value); return; }
3240 if (value == 0) { ; return; }
3241 if (value == 1 && UseIncDec) { incl(dst) ; return; }
3242 /* else */ { addl(dst, value) ; return; }
3243 }
3244
3245 void MacroAssembler::jump(AddressLiteral dst) {
3246 if (reachable(dst)) {
3247 jmp_literal(dst.target(), dst.rspec());
3248 } else {
3249 lea(rscratch1, dst);
3250 jmp(rscratch1);
3251 }
3252 }
3253
3254 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) {
3255 if (reachable(dst)) {
3256 InstructionMark im(this);
3257 relocate(dst.reloc());
3258 const int short_size = 2;
3259 const int long_size = 6;
3260 int offs = (intptr_t)dst.target() - ((intptr_t)pc());
3261 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
3262 // 0111 tttn #8-bit disp
3263 emit_int8(0x70 | cc);
3264 emit_int8((offs - short_size) & 0xFF);
3265 } else {
3266 // 0000 1111 1000 tttn #32-bit disp
3267 emit_int8(0x0F);
3268 emit_int8((unsigned char)(0x80 | cc));
3269 emit_int32(offs - long_size);
3270 }
3271 } else {
3272 #ifdef ASSERT
3273 warning("reversing conditional branch");
3274 #endif /* ASSERT */
3275 Label skip;
3276 jccb(reverse[cc], skip);
3277 lea(rscratch1, dst);
3278 Assembler::jmp(rscratch1);
3279 bind(skip);
3280 }
3281 }
3282
3283 void MacroAssembler::ldmxcsr(AddressLiteral src) {
3284 if (reachable(src)) {
3285 Assembler::ldmxcsr(as_Address(src));
3286 } else {
3287 lea(rscratch1, src);
3288 Assembler::ldmxcsr(Address(rscratch1, 0));
3289 }
3290 }
3291
3292 int MacroAssembler::load_signed_byte(Register dst, Address src) {
3293 int off;
3294 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3295 off = offset();
3296 movsbl(dst, src); // movsxb
3297 } else {
3298 off = load_unsigned_byte(dst, src);
3299 shll(dst, 24);
3300 sarl(dst, 24);
3301 }
3302 return off;
3303 }
3304
3305 // Note: load_signed_short used to be called load_signed_word.
3306 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
3307 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
3308 // The term "word" in HotSpot means a 32- or 64-bit machine word.
3309 int MacroAssembler::load_signed_short(Register dst, Address src) {
3310 int off;
3311 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3312 // This is dubious to me since it seems safe to do a signed 16 => 64 bit
3313 // version but this is what 64bit has always done. This seems to imply
3314 // that users are only using 32bits worth.
3315 off = offset();
3316 movswl(dst, src); // movsxw
3317 } else {
3318 off = load_unsigned_short(dst, src);
3319 shll(dst, 16);
3320 sarl(dst, 16);
3321 }
3322 return off;
3323 }
3324
3325 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
3326 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3327 // and "3.9 Partial Register Penalties", p. 22).
3328 int off;
3329 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
3330 off = offset();
3331 movzbl(dst, src); // movzxb
3332 } else {
3333 xorl(dst, dst);
3334 off = offset();
3335 movb(dst, src);
3336 }
3337 return off;
3338 }
3339
3340 // Note: load_unsigned_short used to be called load_unsigned_word.
3341 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
3342 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3343 // and "3.9 Partial Register Penalties", p. 22).
3344 int off;
3345 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
3346 off = offset();
3347 movzwl(dst, src); // movzxw
3348 } else {
3349 xorl(dst, dst);
3350 off = offset();
3351 movw(dst, src);
3352 }
3353 return off;
3354 }
3355
3356 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
3357 switch (size_in_bytes) {
3358 #ifndef _LP64
3359 case 8:
3360 assert(dst2 != noreg, "second dest register required");
3361 movl(dst, src);
3362 movl(dst2, src.plus_disp(BytesPerInt));
3363 break;
3364 #else
3365 case 8: movq(dst, src); break;
3366 #endif
3367 case 4: movl(dst, src); break;
3368 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
3369 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
3370 default: ShouldNotReachHere();
3371 }
3372 }
3373
3374 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
3375 switch (size_in_bytes) {
3376 #ifndef _LP64
3377 case 8:
3378 assert(src2 != noreg, "second source register required");
3379 movl(dst, src);
3380 movl(dst.plus_disp(BytesPerInt), src2);
3381 break;
3382 #else
3383 case 8: movq(dst, src); break;
3384 #endif
3385 case 4: movl(dst, src); break;
3386 case 2: movw(dst, src); break;
3387 case 1: movb(dst, src); break;
3388 default: ShouldNotReachHere();
3389 }
3390 }
3391
3392 void MacroAssembler::mov32(AddressLiteral dst, Register src) {
3393 if (reachable(dst)) {
3394 movl(as_Address(dst), src);
3395 } else {
3396 lea(rscratch1, dst);
3397 movl(Address(rscratch1, 0), src);
3398 }
3399 }
3400
3401 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
3402 if (reachable(src)) {
3403 movl(dst, as_Address(src));
3404 } else {
3405 lea(rscratch1, src);
3406 movl(dst, Address(rscratch1, 0));
3407 }
3408 }
3409
3410 // C++ bool manipulation
3411
3412 void MacroAssembler::movbool(Register dst, Address src) {
3413 if(sizeof(bool) == 1)
3414 movb(dst, src);
3415 else if(sizeof(bool) == 2)
3416 movw(dst, src);
3417 else if(sizeof(bool) == 4)
3418 movl(dst, src);
3419 else
3420 // unsupported
3421 ShouldNotReachHere();
3422 }
3423
3424 void MacroAssembler::movbool(Address dst, bool boolconst) {
3425 if(sizeof(bool) == 1)
3426 movb(dst, (int) boolconst);
3427 else if(sizeof(bool) == 2)
3428 movw(dst, (int) boolconst);
3429 else if(sizeof(bool) == 4)
3430 movl(dst, (int) boolconst);
3431 else
3432 // unsupported
3433 ShouldNotReachHere();
3434 }
3435
3436 void MacroAssembler::movbool(Address dst, Register src) {
3437 if(sizeof(bool) == 1)
3438 movb(dst, src);
3439 else if(sizeof(bool) == 2)
3440 movw(dst, src);
3441 else if(sizeof(bool) == 4)
3442 movl(dst, src);
3443 else
3444 // unsupported
3445 ShouldNotReachHere();
3446 }
3447
3448 void MacroAssembler::movbyte(ArrayAddress dst, int src) {
3449 movb(as_Address(dst), src);
3450 }
3451
3452 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src) {
3453 if (reachable(src)) {
3454 movdl(dst, as_Address(src));
3455 } else {
3456 lea(rscratch1, src);
3457 movdl(dst, Address(rscratch1, 0));
3458 }
3459 }
3460
3461 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src) {
3462 if (reachable(src)) {
3463 movq(dst, as_Address(src));
3464 } else {
3465 lea(rscratch1, src);
3466 movq(dst, Address(rscratch1, 0));
3467 }
3468 }
3469
3470 void MacroAssembler::setvectmask(Register dst, Register src) {
3471 Assembler::movl(dst, 1);
3472 Assembler::shlxl(dst, dst, src);
3473 Assembler::decl(dst);
3474 Assembler::kmovdl(k1, dst);
3475 Assembler::movl(dst, src);
3476 }
3477
3478 void MacroAssembler::restorevectmask() {
3479 Assembler::knotwl(k1, k0);
3480 }
3481
3482 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) {
3483 if (reachable(src)) {
3484 if (UseXmmLoadAndClearUpper) {
3485 movsd (dst, as_Address(src));
3486 } else {
3487 movlpd(dst, as_Address(src));
3488 }
3489 } else {
3490 lea(rscratch1, src);
3491 if (UseXmmLoadAndClearUpper) {
3492 movsd (dst, Address(rscratch1, 0));
3493 } else {
3494 movlpd(dst, Address(rscratch1, 0));
3495 }
3496 }
3497 }
3498
3499 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) {
3500 if (reachable(src)) {
3501 movss(dst, as_Address(src));
3502 } else {
3503 lea(rscratch1, src);
3504 movss(dst, Address(rscratch1, 0));
3505 }
3506 }
3507
3508 void MacroAssembler::movptr(Register dst, Register src) {
3509 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3510 }
3511
3512 void MacroAssembler::movptr(Register dst, Address src) {
3513 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3514 }
3515
3516 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
3517 void MacroAssembler::movptr(Register dst, intptr_t src) {
3518 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src));
3519 }
3520
3521 void MacroAssembler::movptr(Address dst, Register src) {
3522 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3523 }
3524
3525 void MacroAssembler::movdqu(Address dst, XMMRegister src) {
3526 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (src->encoding() > 15)) {
3527 Assembler::vextractf32x4(dst, src, 0);
3528 } else {
3529 Assembler::movdqu(dst, src);
3530 }
3531 }
3532
3533 void MacroAssembler::movdqu(XMMRegister dst, Address src) {
3534 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (dst->encoding() > 15)) {
3535 Assembler::vinsertf32x4(dst, dst, src, 0);
3536 } else {
3537 Assembler::movdqu(dst, src);
3538 }
3539 }
3540
3541 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) {
3542 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3543 Assembler::evmovdqul(dst, src, Assembler::AVX_512bit);
3544 } else {
3545 Assembler::movdqu(dst, src);
3546 }
3547 }
3548
3549 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src, Register scratchReg) {
3550 if (reachable(src)) {
3551 movdqu(dst, as_Address(src));
3552 } else {
3553 lea(scratchReg, src);
3554 movdqu(dst, Address(scratchReg, 0));
3555 }
3556 }
3557
3558 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) {
3559 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (src->encoding() > 15)) {
3560 vextractf64x4_low(dst, src);
3561 } else {
3562 Assembler::vmovdqu(dst, src);
3563 }
3564 }
3565
3566 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) {
3567 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (dst->encoding() > 15)) {
3568 vinsertf64x4_low(dst, src);
3569 } else {
3570 Assembler::vmovdqu(dst, src);
3571 }
3572 }
3573
3574 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) {
3575 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3576 Assembler::evmovdqul(dst, src, Assembler::AVX_512bit);
3577 }
3578 else {
3579 Assembler::vmovdqu(dst, src);
3580 }
3581 }
3582
3583 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src) {
3584 if (reachable(src)) {
3585 vmovdqu(dst, as_Address(src));
3586 }
3587 else {
3588 lea(rscratch1, src);
3589 vmovdqu(dst, Address(rscratch1, 0));
3590 }
3591 }
3592
3593 void MacroAssembler::evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3594 if (reachable(src)) {
3595 Assembler::evmovdquq(dst, as_Address(src), vector_len);
3596 } else {
3597 lea(rscratch, src);
3598 Assembler::evmovdquq(dst, Address(rscratch, 0), vector_len);
3599 }
3600 }
3601
3602 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src) {
3603 if (reachable(src)) {
3604 Assembler::movdqa(dst, as_Address(src));
3605 } else {
3606 lea(rscratch1, src);
3607 Assembler::movdqa(dst, Address(rscratch1, 0));
3608 }
3609 }
3610
3611 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) {
3612 if (reachable(src)) {
3613 Assembler::movsd(dst, as_Address(src));
3614 } else {
3615 lea(rscratch1, src);
3616 Assembler::movsd(dst, Address(rscratch1, 0));
3617 }
3618 }
3619
3620 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) {
3621 if (reachable(src)) {
3622 Assembler::movss(dst, as_Address(src));
3623 } else {
3624 lea(rscratch1, src);
3625 Assembler::movss(dst, Address(rscratch1, 0));
3626 }
3627 }
3628
3629 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) {
3630 if (reachable(src)) {
3631 Assembler::mulsd(dst, as_Address(src));
3632 } else {
3633 lea(rscratch1, src);
3634 Assembler::mulsd(dst, Address(rscratch1, 0));
3635 }
3636 }
3637
3638 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) {
3639 if (reachable(src)) {
3640 Assembler::mulss(dst, as_Address(src));
3641 } else {
3642 lea(rscratch1, src);
3643 Assembler::mulss(dst, Address(rscratch1, 0));
3644 }
3645 }
3646
3647 void MacroAssembler::null_check(Register reg, int offset) {
3648 if (needs_explicit_null_check(offset)) {
3649 // provoke OS NULL exception if reg = NULL by
3650 // accessing M[reg] w/o changing any (non-CC) registers
3651 // NOTE: cmpl is plenty here to provoke a segv
3652 cmpptr(rax, Address(reg, 0));
3653 // Note: should probably use testl(rax, Address(reg, 0));
3654 // may be shorter code (however, this version of
3655 // testl needs to be implemented first)
3656 } else {
3657 // nothing to do, (later) access of M[reg + offset]
3658 // will provoke OS NULL exception if reg = NULL
3659 }
3660 }
3661
3662 void MacroAssembler::os_breakpoint() {
3663 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
3664 // (e.g., MSVC can't call ps() otherwise)
3665 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
3666 }
3667
3668 void MacroAssembler::unimplemented(const char* what) {
3669 const char* buf = NULL;
3670 {
3671 ResourceMark rm;
3672 stringStream ss;
3673 ss.print("unimplemented: %s", what);
3674 buf = code_string(ss.as_string());
3675 }
3676 stop(buf);
3677 }
3678
3679 #ifdef _LP64
3680 #define XSTATE_BV 0x200
3681 #endif
3682
3683 void MacroAssembler::pop_CPU_state() {
3684 pop_FPU_state();
3685 pop_IU_state();
3686 }
3687
3688 void MacroAssembler::pop_FPU_state() {
3689 #ifndef _LP64
3690 frstor(Address(rsp, 0));
3691 #else
3692 fxrstor(Address(rsp, 0));
3693 #endif
3694 addptr(rsp, FPUStateSizeInWords * wordSize);
3695 }
3696
3697 void MacroAssembler::pop_IU_state() {
3698 popa();
3699 LP64_ONLY(addq(rsp, 8));
3700 popf();
3701 }
3702
3703 // Save Integer and Float state
3704 // Warning: Stack must be 16 byte aligned (64bit)
3705 void MacroAssembler::push_CPU_state() {
3706 push_IU_state();
3707 push_FPU_state();
3708 }
3709
3710 void MacroAssembler::push_FPU_state() {
3711 subptr(rsp, FPUStateSizeInWords * wordSize);
3712 #ifndef _LP64
3713 fnsave(Address(rsp, 0));
3714 fwait();
3715 #else
3716 fxsave(Address(rsp, 0));
3717 #endif // LP64
3718 }
3719
3720 void MacroAssembler::push_IU_state() {
3721 // Push flags first because pusha kills them
3722 pushf();
3723 // Make sure rsp stays 16-byte aligned
3724 LP64_ONLY(subq(rsp, 8));
3725 pusha();
3726 }
3727
3728 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp) { // determine java_thread register
3729 if (!java_thread->is_valid()) {
3730 java_thread = rdi;
3731 get_thread(java_thread);
3732 }
3733 // we must set sp to zero to clear frame
3734 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
3735 if (clear_fp) {
3736 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
3737 }
3738
3739 // Always clear the pc because it could have been set by make_walkable()
3740 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
3741
3742 vzeroupper();
3743 }
3744
3745 void MacroAssembler::restore_rax(Register tmp) {
3746 if (tmp == noreg) pop(rax);
3747 else if (tmp != rax) mov(rax, tmp);
3748 }
3749
3750 void MacroAssembler::round_to(Register reg, int modulus) {
3751 addptr(reg, modulus - 1);
3752 andptr(reg, -modulus);
3753 }
3754
3755 void MacroAssembler::save_rax(Register tmp) {
3756 if (tmp == noreg) push(rax);
3757 else if (tmp != rax) mov(tmp, rax);
3758 }
3759
3760 // Write serialization page so VM thread can do a pseudo remote membar.
3761 // We use the current thread pointer to calculate a thread specific
3762 // offset to write to within the page. This minimizes bus traffic
3763 // due to cache line collision.
3764 void MacroAssembler::serialize_memory(Register thread, Register tmp) {
3765 movl(tmp, thread);
3766 shrl(tmp, os::get_serialize_page_shift_count());
3767 andl(tmp, (os::vm_page_size() - sizeof(int)));
3768
3769 Address index(noreg, tmp, Address::times_1);
3770 ExternalAddress page(os::get_memory_serialize_page());
3771
3772 // Size of store must match masking code above
3773 movl(as_Address(ArrayAddress(page, index)), tmp);
3774 }
3775
3776 void MacroAssembler::safepoint_poll(Label& slow_path, Register thread_reg, Register temp_reg) {
3777 if (SafepointMechanism::uses_thread_local_poll()) {
3778 #ifdef _LP64
3779 assert(thread_reg == r15_thread, "should be");
3780 #else
3781 if (thread_reg == noreg) {
3782 thread_reg = temp_reg;
3783 get_thread(thread_reg);
3784 }
3785 #endif
3786 testb(Address(thread_reg, Thread::polling_page_offset()), SafepointMechanism::poll_bit());
3787 jcc(Assembler::notZero, slow_path); // handshake bit set implies poll
3788 } else {
3789 cmp32(ExternalAddress(SafepointSynchronize::address_of_state()),
3790 SafepointSynchronize::_not_synchronized);
3791 jcc(Assembler::notEqual, slow_path);
3792 }
3793 }
3794
3795 // Calls to C land
3796 //
3797 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
3798 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
3799 // has to be reset to 0. This is required to allow proper stack traversal.
3800 void MacroAssembler::set_last_Java_frame(Register java_thread,
3801 Register last_java_sp,
3802 Register last_java_fp,
3803 address last_java_pc) {
3804 vzeroupper();
3805 // determine java_thread register
3806 if (!java_thread->is_valid()) {
3807 java_thread = rdi;
3808 get_thread(java_thread);
3809 }
3810 // determine last_java_sp register
3811 if (!last_java_sp->is_valid()) {
3812 last_java_sp = rsp;
3813 }
3814
3815 // last_java_fp is optional
3816
3817 if (last_java_fp->is_valid()) {
3818 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
3819 }
3820
3821 // last_java_pc is optional
3822
3823 if (last_java_pc != NULL) {
3824 lea(Address(java_thread,
3825 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()),
3826 InternalAddress(last_java_pc));
3827
3828 }
3829 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
3830 }
3831
3832 void MacroAssembler::shlptr(Register dst, int imm8) {
3833 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
3834 }
3835
3836 void MacroAssembler::shrptr(Register dst, int imm8) {
3837 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
3838 }
3839
3840 void MacroAssembler::sign_extend_byte(Register reg) {
3841 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
3842 movsbl(reg, reg); // movsxb
3843 } else {
3844 shll(reg, 24);
3845 sarl(reg, 24);
3846 }
3847 }
3848
3849 void MacroAssembler::sign_extend_short(Register reg) {
3850 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3851 movswl(reg, reg); // movsxw
3852 } else {
3853 shll(reg, 16);
3854 sarl(reg, 16);
3855 }
3856 }
3857
3858 void MacroAssembler::testl(Register dst, AddressLiteral src) {
3859 assert(reachable(src), "Address should be reachable");
3860 testl(dst, as_Address(src));
3861 }
3862
3863 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
3864 int dst_enc = dst->encoding();
3865 int src_enc = src->encoding();
3866 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
3867 Assembler::pcmpeqb(dst, src);
3868 } else if ((dst_enc < 16) && (src_enc < 16)) {
3869 Assembler::pcmpeqb(dst, src);
3870 } else if (src_enc < 16) {
3871 subptr(rsp, 64);
3872 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3873 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3874 Assembler::pcmpeqb(xmm0, src);
3875 movdqu(dst, xmm0);
3876 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3877 addptr(rsp, 64);
3878 } else if (dst_enc < 16) {
3879 subptr(rsp, 64);
3880 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3881 evmovdqul(xmm0, src, Assembler::AVX_512bit);
3882 Assembler::pcmpeqb(dst, xmm0);
3883 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3884 addptr(rsp, 64);
3885 } else {
3886 subptr(rsp, 64);
3887 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3888 subptr(rsp, 64);
3889 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
3890 movdqu(xmm0, src);
3891 movdqu(xmm1, dst);
3892 Assembler::pcmpeqb(xmm1, xmm0);
3893 movdqu(dst, xmm1);
3894 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
3895 addptr(rsp, 64);
3896 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3897 addptr(rsp, 64);
3898 }
3899 }
3900
3901 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3902 int dst_enc = dst->encoding();
3903 int src_enc = src->encoding();
3904 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
3905 Assembler::pcmpeqw(dst, src);
3906 } else if ((dst_enc < 16) && (src_enc < 16)) {
3907 Assembler::pcmpeqw(dst, src);
3908 } else if (src_enc < 16) {
3909 subptr(rsp, 64);
3910 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3911 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3912 Assembler::pcmpeqw(xmm0, src);
3913 movdqu(dst, xmm0);
3914 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3915 addptr(rsp, 64);
3916 } else if (dst_enc < 16) {
3917 subptr(rsp, 64);
3918 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3919 evmovdqul(xmm0, src, Assembler::AVX_512bit);
3920 Assembler::pcmpeqw(dst, xmm0);
3921 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3922 addptr(rsp, 64);
3923 } else {
3924 subptr(rsp, 64);
3925 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3926 subptr(rsp, 64);
3927 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
3928 movdqu(xmm0, src);
3929 movdqu(xmm1, dst);
3930 Assembler::pcmpeqw(xmm1, xmm0);
3931 movdqu(dst, xmm1);
3932 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
3933 addptr(rsp, 64);
3934 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3935 addptr(rsp, 64);
3936 }
3937 }
3938
3939 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3940 int dst_enc = dst->encoding();
3941 if (dst_enc < 16) {
3942 Assembler::pcmpestri(dst, src, imm8);
3943 } else {
3944 subptr(rsp, 64);
3945 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3946 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3947 Assembler::pcmpestri(xmm0, src, imm8);
3948 movdqu(dst, xmm0);
3949 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3950 addptr(rsp, 64);
3951 }
3952 }
3953
3954 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3955 int dst_enc = dst->encoding();
3956 int src_enc = src->encoding();
3957 if ((dst_enc < 16) && (src_enc < 16)) {
3958 Assembler::pcmpestri(dst, src, imm8);
3959 } else if (src_enc < 16) {
3960 subptr(rsp, 64);
3961 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3962 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3963 Assembler::pcmpestri(xmm0, src, imm8);
3964 movdqu(dst, xmm0);
3965 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3966 addptr(rsp, 64);
3967 } else if (dst_enc < 16) {
3968 subptr(rsp, 64);
3969 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3970 evmovdqul(xmm0, src, Assembler::AVX_512bit);
3971 Assembler::pcmpestri(dst, xmm0, imm8);
3972 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3973 addptr(rsp, 64);
3974 } else {
3975 subptr(rsp, 64);
3976 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3977 subptr(rsp, 64);
3978 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
3979 movdqu(xmm0, src);
3980 movdqu(xmm1, dst);
3981 Assembler::pcmpestri(xmm1, xmm0, imm8);
3982 movdqu(dst, xmm1);
3983 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
3984 addptr(rsp, 64);
3985 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3986 addptr(rsp, 64);
3987 }
3988 }
3989
3990 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3991 int dst_enc = dst->encoding();
3992 int src_enc = src->encoding();
3993 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
3994 Assembler::pmovzxbw(dst, src);
3995 } else if ((dst_enc < 16) && (src_enc < 16)) {
3996 Assembler::pmovzxbw(dst, src);
3997 } else if (src_enc < 16) {
3998 subptr(rsp, 64);
3999 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4000 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4001 Assembler::pmovzxbw(xmm0, src);
4002 movdqu(dst, xmm0);
4003 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4004 addptr(rsp, 64);
4005 } else if (dst_enc < 16) {
4006 subptr(rsp, 64);
4007 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4008 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4009 Assembler::pmovzxbw(dst, xmm0);
4010 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4011 addptr(rsp, 64);
4012 } else {
4013 subptr(rsp, 64);
4014 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4015 subptr(rsp, 64);
4016 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4017 movdqu(xmm0, src);
4018 movdqu(xmm1, dst);
4019 Assembler::pmovzxbw(xmm1, xmm0);
4020 movdqu(dst, xmm1);
4021 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4022 addptr(rsp, 64);
4023 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4024 addptr(rsp, 64);
4025 }
4026 }
4027
4028 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) {
4029 int dst_enc = dst->encoding();
4030 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4031 Assembler::pmovzxbw(dst, src);
4032 } else if (dst_enc < 16) {
4033 Assembler::pmovzxbw(dst, src);
4034 } else {
4035 subptr(rsp, 64);
4036 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4037 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4038 Assembler::pmovzxbw(xmm0, src);
4039 movdqu(dst, xmm0);
4040 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4041 addptr(rsp, 64);
4042 }
4043 }
4044
4045 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) {
4046 int src_enc = src->encoding();
4047 if (src_enc < 16) {
4048 Assembler::pmovmskb(dst, src);
4049 } else {
4050 subptr(rsp, 64);
4051 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4052 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4053 Assembler::pmovmskb(dst, xmm0);
4054 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4055 addptr(rsp, 64);
4056 }
4057 }
4058
4059 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) {
4060 int dst_enc = dst->encoding();
4061 int src_enc = src->encoding();
4062 if ((dst_enc < 16) && (src_enc < 16)) {
4063 Assembler::ptest(dst, src);
4064 } else if (src_enc < 16) {
4065 subptr(rsp, 64);
4066 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4067 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4068 Assembler::ptest(xmm0, src);
4069 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4070 addptr(rsp, 64);
4071 } else if (dst_enc < 16) {
4072 subptr(rsp, 64);
4073 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4074 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4075 Assembler::ptest(dst, xmm0);
4076 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4077 addptr(rsp, 64);
4078 } else {
4079 subptr(rsp, 64);
4080 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4081 subptr(rsp, 64);
4082 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4083 movdqu(xmm0, src);
4084 movdqu(xmm1, dst);
4085 Assembler::ptest(xmm1, xmm0);
4086 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4087 addptr(rsp, 64);
4088 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4089 addptr(rsp, 64);
4090 }
4091 }
4092
4093 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) {
4094 if (reachable(src)) {
4095 Assembler::sqrtsd(dst, as_Address(src));
4096 } else {
4097 lea(rscratch1, src);
4098 Assembler::sqrtsd(dst, Address(rscratch1, 0));
4099 }
4100 }
4101
4102 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) {
4103 if (reachable(src)) {
4104 Assembler::sqrtss(dst, as_Address(src));
4105 } else {
4106 lea(rscratch1, src);
4107 Assembler::sqrtss(dst, Address(rscratch1, 0));
4108 }
4109 }
4110
4111 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) {
4112 if (reachable(src)) {
4113 Assembler::subsd(dst, as_Address(src));
4114 } else {
4115 lea(rscratch1, src);
4116 Assembler::subsd(dst, Address(rscratch1, 0));
4117 }
4118 }
4119
4120 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) {
4121 if (reachable(src)) {
4122 Assembler::subss(dst, as_Address(src));
4123 } else {
4124 lea(rscratch1, src);
4125 Assembler::subss(dst, Address(rscratch1, 0));
4126 }
4127 }
4128
4129 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) {
4130 if (reachable(src)) {
4131 Assembler::ucomisd(dst, as_Address(src));
4132 } else {
4133 lea(rscratch1, src);
4134 Assembler::ucomisd(dst, Address(rscratch1, 0));
4135 }
4136 }
4137
4138 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) {
4139 if (reachable(src)) {
4140 Assembler::ucomiss(dst, as_Address(src));
4141 } else {
4142 lea(rscratch1, src);
4143 Assembler::ucomiss(dst, Address(rscratch1, 0));
4144 }
4145 }
4146
4147 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) {
4148 // Used in sign-bit flipping with aligned address.
4149 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
4150 if (reachable(src)) {
4151 Assembler::xorpd(dst, as_Address(src));
4152 } else {
4153 lea(rscratch1, src);
4154 Assembler::xorpd(dst, Address(rscratch1, 0));
4155 }
4156 }
4157
4158 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) {
4159 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
4160 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
4161 }
4162 else {
4163 Assembler::xorpd(dst, src);
4164 }
4165 }
4166
4167 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) {
4168 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
4169 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
4170 } else {
4171 Assembler::xorps(dst, src);
4172 }
4173 }
4174
4175 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) {
4176 // Used in sign-bit flipping with aligned address.
4177 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
4178 if (reachable(src)) {
4179 Assembler::xorps(dst, as_Address(src));
4180 } else {
4181 lea(rscratch1, src);
4182 Assembler::xorps(dst, Address(rscratch1, 0));
4183 }
4184 }
4185
4186 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src) {
4187 // Used in sign-bit flipping with aligned address.
4188 bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
4189 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
4190 if (reachable(src)) {
4191 Assembler::pshufb(dst, as_Address(src));
4192 } else {
4193 lea(rscratch1, src);
4194 Assembler::pshufb(dst, Address(rscratch1, 0));
4195 }
4196 }
4197
4198 // AVX 3-operands instructions
4199
4200 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4201 if (reachable(src)) {
4202 vaddsd(dst, nds, as_Address(src));
4203 } else {
4204 lea(rscratch1, src);
4205 vaddsd(dst, nds, Address(rscratch1, 0));
4206 }
4207 }
4208
4209 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4210 if (reachable(src)) {
4211 vaddss(dst, nds, as_Address(src));
4212 } else {
4213 lea(rscratch1, src);
4214 vaddss(dst, nds, Address(rscratch1, 0));
4215 }
4216 }
4217
4218 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) {
4219 int dst_enc = dst->encoding();
4220 int nds_enc = nds->encoding();
4221 int src_enc = src->encoding();
4222 if ((dst_enc < 16) && (nds_enc < 16)) {
4223 vandps(dst, nds, negate_field, vector_len);
4224 } else if ((src_enc < 16) && (dst_enc < 16)) {
4225 evmovdqul(src, nds, Assembler::AVX_512bit);
4226 vandps(dst, src, negate_field, vector_len);
4227 } else if (src_enc < 16) {
4228 evmovdqul(src, nds, Assembler::AVX_512bit);
4229 vandps(src, src, negate_field, vector_len);
4230 evmovdqul(dst, src, Assembler::AVX_512bit);
4231 } else if (dst_enc < 16) {
4232 evmovdqul(src, xmm0, Assembler::AVX_512bit);
4233 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4234 vandps(dst, xmm0, negate_field, vector_len);
4235 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4236 } else {
4237 if (src_enc != dst_enc) {
4238 evmovdqul(src, xmm0, Assembler::AVX_512bit);
4239 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4240 vandps(xmm0, xmm0, negate_field, vector_len);
4241 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4242 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4243 } else {
4244 subptr(rsp, 64);
4245 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4246 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4247 vandps(xmm0, xmm0, negate_field, vector_len);
4248 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4249 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4250 addptr(rsp, 64);
4251 }
4252 }
4253 }
4254
4255 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) {
4256 int dst_enc = dst->encoding();
4257 int nds_enc = nds->encoding();
4258 int src_enc = src->encoding();
4259 if ((dst_enc < 16) && (nds_enc < 16)) {
4260 vandpd(dst, nds, negate_field, vector_len);
4261 } else if ((src_enc < 16) && (dst_enc < 16)) {
4262 evmovdqul(src, nds, Assembler::AVX_512bit);
4263 vandpd(dst, src, negate_field, vector_len);
4264 } else if (src_enc < 16) {
4265 evmovdqul(src, nds, Assembler::AVX_512bit);
4266 vandpd(src, src, negate_field, vector_len);
4267 evmovdqul(dst, src, Assembler::AVX_512bit);
4268 } else if (dst_enc < 16) {
4269 evmovdqul(src, xmm0, Assembler::AVX_512bit);
4270 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4271 vandpd(dst, xmm0, negate_field, vector_len);
4272 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4273 } else {
4274 if (src_enc != dst_enc) {
4275 evmovdqul(src, xmm0, Assembler::AVX_512bit);
4276 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4277 vandpd(xmm0, xmm0, negate_field, vector_len);
4278 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4279 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4280 } else {
4281 subptr(rsp, 64);
4282 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4283 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4284 vandpd(xmm0, xmm0, negate_field, vector_len);
4285 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4286 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4287 addptr(rsp, 64);
4288 }
4289 }
4290 }
4291
4292 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4293 int dst_enc = dst->encoding();
4294 int nds_enc = nds->encoding();
4295 int src_enc = src->encoding();
4296 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4297 Assembler::vpaddb(dst, nds, src, vector_len);
4298 } else if ((dst_enc < 16) && (src_enc < 16)) {
4299 Assembler::vpaddb(dst, dst, src, vector_len);
4300 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4301 // use nds as scratch for src
4302 evmovdqul(nds, src, Assembler::AVX_512bit);
4303 Assembler::vpaddb(dst, dst, nds, vector_len);
4304 } else if ((src_enc < 16) && (nds_enc < 16)) {
4305 // use nds as scratch for dst
4306 evmovdqul(nds, dst, Assembler::AVX_512bit);
4307 Assembler::vpaddb(nds, nds, src, vector_len);
4308 evmovdqul(dst, nds, Assembler::AVX_512bit);
4309 } else if (dst_enc < 16) {
4310 // use nds as scatch for xmm0 to hold src
4311 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4312 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4313 Assembler::vpaddb(dst, dst, xmm0, vector_len);
4314 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4315 } else {
4316 // worse case scenario, all regs are in the upper bank
4317 subptr(rsp, 64);
4318 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4319 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4320 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4321 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4322 Assembler::vpaddb(xmm0, xmm0, xmm1, vector_len);
4323 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4324 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4325 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4326 addptr(rsp, 64);
4327 }
4328 }
4329
4330 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4331 int dst_enc = dst->encoding();
4332 int nds_enc = nds->encoding();
4333 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4334 Assembler::vpaddb(dst, nds, src, vector_len);
4335 } else if (dst_enc < 16) {
4336 Assembler::vpaddb(dst, dst, src, vector_len);
4337 } else if (nds_enc < 16) {
4338 // implies dst_enc in upper bank with src as scratch
4339 evmovdqul(nds, dst, Assembler::AVX_512bit);
4340 Assembler::vpaddb(nds, nds, src, vector_len);
4341 evmovdqul(dst, nds, Assembler::AVX_512bit);
4342 } else {
4343 // worse case scenario, all regs in upper bank
4344 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4345 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4346 Assembler::vpaddb(xmm0, xmm0, src, vector_len);
4347 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4348 }
4349 }
4350
4351 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4352 int dst_enc = dst->encoding();
4353 int nds_enc = nds->encoding();
4354 int src_enc = src->encoding();
4355 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4356 Assembler::vpaddw(dst, nds, src, vector_len);
4357 } else if ((dst_enc < 16) && (src_enc < 16)) {
4358 Assembler::vpaddw(dst, dst, src, vector_len);
4359 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4360 // use nds as scratch for src
4361 evmovdqul(nds, src, Assembler::AVX_512bit);
4362 Assembler::vpaddw(dst, dst, nds, vector_len);
4363 } else if ((src_enc < 16) && (nds_enc < 16)) {
4364 // use nds as scratch for dst
4365 evmovdqul(nds, dst, Assembler::AVX_512bit);
4366 Assembler::vpaddw(nds, nds, src, vector_len);
4367 evmovdqul(dst, nds, Assembler::AVX_512bit);
4368 } else if (dst_enc < 16) {
4369 // use nds as scatch for xmm0 to hold src
4370 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4371 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4372 Assembler::vpaddw(dst, dst, xmm0, vector_len);
4373 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4374 } else {
4375 // worse case scenario, all regs are in the upper bank
4376 subptr(rsp, 64);
4377 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4378 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4379 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4380 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4381 Assembler::vpaddw(xmm0, xmm0, xmm1, vector_len);
4382 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4383 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4384 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4385 addptr(rsp, 64);
4386 }
4387 }
4388
4389 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4390 int dst_enc = dst->encoding();
4391 int nds_enc = nds->encoding();
4392 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4393 Assembler::vpaddw(dst, nds, src, vector_len);
4394 } else if (dst_enc < 16) {
4395 Assembler::vpaddw(dst, dst, src, vector_len);
4396 } else if (nds_enc < 16) {
4397 // implies dst_enc in upper bank with src as scratch
4398 evmovdqul(nds, dst, Assembler::AVX_512bit);
4399 Assembler::vpaddw(nds, nds, src, vector_len);
4400 evmovdqul(dst, nds, Assembler::AVX_512bit);
4401 } else {
4402 // worse case scenario, all regs in upper bank
4403 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4404 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4405 Assembler::vpaddw(xmm0, xmm0, src, vector_len);
4406 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4407 }
4408 }
4409
4410 void MacroAssembler::vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
4411 if (reachable(src)) {
4412 Assembler::vpand(dst, nds, as_Address(src), vector_len);
4413 } else {
4414 lea(rscratch1, src);
4415 Assembler::vpand(dst, nds, Address(rscratch1, 0), vector_len);
4416 }
4417 }
4418
4419 void MacroAssembler::vpbroadcastw(XMMRegister dst, XMMRegister src) {
4420 int dst_enc = dst->encoding();
4421 int src_enc = src->encoding();
4422 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4423 Assembler::vpbroadcastw(dst, src);
4424 } else if ((dst_enc < 16) && (src_enc < 16)) {
4425 Assembler::vpbroadcastw(dst, src);
4426 } else if (src_enc < 16) {
4427 subptr(rsp, 64);
4428 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4429 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4430 Assembler::vpbroadcastw(xmm0, src);
4431 movdqu(dst, xmm0);
4432 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4433 addptr(rsp, 64);
4434 } else if (dst_enc < 16) {
4435 subptr(rsp, 64);
4436 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4437 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4438 Assembler::vpbroadcastw(dst, xmm0);
4439 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4440 addptr(rsp, 64);
4441 } else {
4442 subptr(rsp, 64);
4443 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4444 subptr(rsp, 64);
4445 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4446 movdqu(xmm0, src);
4447 movdqu(xmm1, dst);
4448 Assembler::vpbroadcastw(xmm1, xmm0);
4449 movdqu(dst, xmm1);
4450 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4451 addptr(rsp, 64);
4452 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4453 addptr(rsp, 64);
4454 }
4455 }
4456
4457 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4458 int dst_enc = dst->encoding();
4459 int nds_enc = nds->encoding();
4460 int src_enc = src->encoding();
4461 assert(dst_enc == nds_enc, "");
4462 if ((dst_enc < 16) && (src_enc < 16)) {
4463 Assembler::vpcmpeqb(dst, nds, src, vector_len);
4464 } else if (src_enc < 16) {
4465 subptr(rsp, 64);
4466 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4467 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4468 Assembler::vpcmpeqb(xmm0, xmm0, src, vector_len);
4469 movdqu(dst, xmm0);
4470 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4471 addptr(rsp, 64);
4472 } else if (dst_enc < 16) {
4473 subptr(rsp, 64);
4474 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4475 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4476 Assembler::vpcmpeqb(dst, dst, xmm0, vector_len);
4477 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4478 addptr(rsp, 64);
4479 } else {
4480 subptr(rsp, 64);
4481 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4482 subptr(rsp, 64);
4483 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4484 movdqu(xmm0, src);
4485 movdqu(xmm1, dst);
4486 Assembler::vpcmpeqb(xmm1, xmm1, xmm0, vector_len);
4487 movdqu(dst, xmm1);
4488 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4489 addptr(rsp, 64);
4490 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4491 addptr(rsp, 64);
4492 }
4493 }
4494
4495 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4496 int dst_enc = dst->encoding();
4497 int nds_enc = nds->encoding();
4498 int src_enc = src->encoding();
4499 assert(dst_enc == nds_enc, "");
4500 if ((dst_enc < 16) && (src_enc < 16)) {
4501 Assembler::vpcmpeqw(dst, nds, src, vector_len);
4502 } else if (src_enc < 16) {
4503 subptr(rsp, 64);
4504 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4505 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4506 Assembler::vpcmpeqw(xmm0, xmm0, src, vector_len);
4507 movdqu(dst, xmm0);
4508 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4509 addptr(rsp, 64);
4510 } else if (dst_enc < 16) {
4511 subptr(rsp, 64);
4512 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4513 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4514 Assembler::vpcmpeqw(dst, dst, xmm0, vector_len);
4515 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4516 addptr(rsp, 64);
4517 } else {
4518 subptr(rsp, 64);
4519 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4520 subptr(rsp, 64);
4521 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4522 movdqu(xmm0, src);
4523 movdqu(xmm1, dst);
4524 Assembler::vpcmpeqw(xmm1, xmm1, xmm0, vector_len);
4525 movdqu(dst, xmm1);
4526 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4527 addptr(rsp, 64);
4528 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4529 addptr(rsp, 64);
4530 }
4531 }
4532
4533 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
4534 int dst_enc = dst->encoding();
4535 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4536 Assembler::vpmovzxbw(dst, src, vector_len);
4537 } else if (dst_enc < 16) {
4538 Assembler::vpmovzxbw(dst, src, vector_len);
4539 } else {
4540 subptr(rsp, 64);
4541 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4542 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4543 Assembler::vpmovzxbw(xmm0, src, vector_len);
4544 movdqu(dst, xmm0);
4545 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4546 addptr(rsp, 64);
4547 }
4548 }
4549
4550 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src) {
4551 int src_enc = src->encoding();
4552 if (src_enc < 16) {
4553 Assembler::vpmovmskb(dst, src);
4554 } else {
4555 subptr(rsp, 64);
4556 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4557 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4558 Assembler::vpmovmskb(dst, xmm0);
4559 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4560 addptr(rsp, 64);
4561 }
4562 }
4563
4564 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4565 int dst_enc = dst->encoding();
4566 int nds_enc = nds->encoding();
4567 int src_enc = src->encoding();
4568 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4569 Assembler::vpmullw(dst, nds, src, vector_len);
4570 } else if ((dst_enc < 16) && (src_enc < 16)) {
4571 Assembler::vpmullw(dst, dst, src, vector_len);
4572 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4573 // use nds as scratch for src
4574 evmovdqul(nds, src, Assembler::AVX_512bit);
4575 Assembler::vpmullw(dst, dst, nds, vector_len);
4576 } else if ((src_enc < 16) && (nds_enc < 16)) {
4577 // use nds as scratch for dst
4578 evmovdqul(nds, dst, Assembler::AVX_512bit);
4579 Assembler::vpmullw(nds, nds, src, vector_len);
4580 evmovdqul(dst, nds, Assembler::AVX_512bit);
4581 } else if (dst_enc < 16) {
4582 // use nds as scatch for xmm0 to hold src
4583 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4584 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4585 Assembler::vpmullw(dst, dst, xmm0, vector_len);
4586 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4587 } else {
4588 // worse case scenario, all regs are in the upper bank
4589 subptr(rsp, 64);
4590 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4591 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4592 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4593 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4594 Assembler::vpmullw(xmm0, xmm0, xmm1, vector_len);
4595 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4596 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4597 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4598 addptr(rsp, 64);
4599 }
4600 }
4601
4602 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4603 int dst_enc = dst->encoding();
4604 int nds_enc = nds->encoding();
4605 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4606 Assembler::vpmullw(dst, nds, src, vector_len);
4607 } else if (dst_enc < 16) {
4608 Assembler::vpmullw(dst, dst, src, vector_len);
4609 } else if (nds_enc < 16) {
4610 // implies dst_enc in upper bank with src as scratch
4611 evmovdqul(nds, dst, Assembler::AVX_512bit);
4612 Assembler::vpmullw(nds, nds, src, vector_len);
4613 evmovdqul(dst, nds, Assembler::AVX_512bit);
4614 } else {
4615 // worse case scenario, all regs in upper bank
4616 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4617 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4618 Assembler::vpmullw(xmm0, xmm0, src, vector_len);
4619 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4620 }
4621 }
4622
4623 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4624 int dst_enc = dst->encoding();
4625 int nds_enc = nds->encoding();
4626 int src_enc = src->encoding();
4627 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4628 Assembler::vpsubb(dst, nds, src, vector_len);
4629 } else if ((dst_enc < 16) && (src_enc < 16)) {
4630 Assembler::vpsubb(dst, dst, src, vector_len);
4631 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4632 // use nds as scratch for src
4633 evmovdqul(nds, src, Assembler::AVX_512bit);
4634 Assembler::vpsubb(dst, dst, nds, vector_len);
4635 } else if ((src_enc < 16) && (nds_enc < 16)) {
4636 // use nds as scratch for dst
4637 evmovdqul(nds, dst, Assembler::AVX_512bit);
4638 Assembler::vpsubb(nds, nds, src, vector_len);
4639 evmovdqul(dst, nds, Assembler::AVX_512bit);
4640 } else if (dst_enc < 16) {
4641 // use nds as scatch for xmm0 to hold src
4642 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4643 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4644 Assembler::vpsubb(dst, dst, xmm0, vector_len);
4645 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4646 } else {
4647 // worse case scenario, all regs are in the upper bank
4648 subptr(rsp, 64);
4649 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4650 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4651 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4652 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4653 Assembler::vpsubb(xmm0, xmm0, xmm1, vector_len);
4654 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4655 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4656 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4657 addptr(rsp, 64);
4658 }
4659 }
4660
4661 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4662 int dst_enc = dst->encoding();
4663 int nds_enc = nds->encoding();
4664 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4665 Assembler::vpsubb(dst, nds, src, vector_len);
4666 } else if (dst_enc < 16) {
4667 Assembler::vpsubb(dst, dst, src, vector_len);
4668 } else if (nds_enc < 16) {
4669 // implies dst_enc in upper bank with src as scratch
4670 evmovdqul(nds, dst, Assembler::AVX_512bit);
4671 Assembler::vpsubb(nds, nds, src, vector_len);
4672 evmovdqul(dst, nds, Assembler::AVX_512bit);
4673 } else {
4674 // worse case scenario, all regs in upper bank
4675 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4676 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4677 Assembler::vpsubw(xmm0, xmm0, src, vector_len);
4678 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4679 }
4680 }
4681
4682 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4683 int dst_enc = dst->encoding();
4684 int nds_enc = nds->encoding();
4685 int src_enc = src->encoding();
4686 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4687 Assembler::vpsubw(dst, nds, src, vector_len);
4688 } else if ((dst_enc < 16) && (src_enc < 16)) {
4689 Assembler::vpsubw(dst, dst, src, vector_len);
4690 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4691 // use nds as scratch for src
4692 evmovdqul(nds, src, Assembler::AVX_512bit);
4693 Assembler::vpsubw(dst, dst, nds, vector_len);
4694 } else if ((src_enc < 16) && (nds_enc < 16)) {
4695 // use nds as scratch for dst
4696 evmovdqul(nds, dst, Assembler::AVX_512bit);
4697 Assembler::vpsubw(nds, nds, src, vector_len);
4698 evmovdqul(dst, nds, Assembler::AVX_512bit);
4699 } else if (dst_enc < 16) {
4700 // use nds as scatch for xmm0 to hold src
4701 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4702 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4703 Assembler::vpsubw(dst, dst, xmm0, vector_len);
4704 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4705 } else {
4706 // worse case scenario, all regs are in the upper bank
4707 subptr(rsp, 64);
4708 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4709 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4710 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4711 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4712 Assembler::vpsubw(xmm0, xmm0, xmm1, vector_len);
4713 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4714 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4715 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4716 addptr(rsp, 64);
4717 }
4718 }
4719
4720 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4721 int dst_enc = dst->encoding();
4722 int nds_enc = nds->encoding();
4723 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4724 Assembler::vpsubw(dst, nds, src, vector_len);
4725 } else if (dst_enc < 16) {
4726 Assembler::vpsubw(dst, dst, src, vector_len);
4727 } else if (nds_enc < 16) {
4728 // implies dst_enc in upper bank with src as scratch
4729 evmovdqul(nds, dst, Assembler::AVX_512bit);
4730 Assembler::vpsubw(nds, nds, src, vector_len);
4731 evmovdqul(dst, nds, Assembler::AVX_512bit);
4732 } else {
4733 // worse case scenario, all regs in upper bank
4734 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4735 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4736 Assembler::vpsubw(xmm0, xmm0, src, vector_len);
4737 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4738 }
4739 }
4740
4741 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
4742 int dst_enc = dst->encoding();
4743 int nds_enc = nds->encoding();
4744 int shift_enc = shift->encoding();
4745 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4746 Assembler::vpsraw(dst, nds, shift, vector_len);
4747 } else if ((dst_enc < 16) && (shift_enc < 16)) {
4748 Assembler::vpsraw(dst, dst, shift, vector_len);
4749 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4750 // use nds_enc as scratch with shift
4751 evmovdqul(nds, shift, Assembler::AVX_512bit);
4752 Assembler::vpsraw(dst, dst, nds, vector_len);
4753 } else if ((shift_enc < 16) && (nds_enc < 16)) {
4754 // use nds as scratch with dst
4755 evmovdqul(nds, dst, Assembler::AVX_512bit);
4756 Assembler::vpsraw(nds, nds, shift, vector_len);
4757 evmovdqul(dst, nds, Assembler::AVX_512bit);
4758 } else if (dst_enc < 16) {
4759 // use nds to save a copy of xmm0 and hold shift
4760 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4761 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4762 Assembler::vpsraw(dst, dst, xmm0, vector_len);
4763 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4764 } else if (nds_enc < 16) {
4765 // use nds as dest as temps
4766 evmovdqul(nds, dst, Assembler::AVX_512bit);
4767 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4768 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4769 Assembler::vpsraw(nds, nds, xmm0, vector_len);
4770 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4771 evmovdqul(dst, nds, Assembler::AVX_512bit);
4772 } else {
4773 // worse case scenario, all regs are in the upper bank
4774 subptr(rsp, 64);
4775 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4776 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4777 evmovdqul(xmm1, shift, Assembler::AVX_512bit);
4778 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4779 Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len);
4780 evmovdqul(xmm1, dst, Assembler::AVX_512bit);
4781 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4782 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4783 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4784 addptr(rsp, 64);
4785 }
4786 }
4787
4788 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
4789 int dst_enc = dst->encoding();
4790 int nds_enc = nds->encoding();
4791 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4792 Assembler::vpsraw(dst, nds, shift, vector_len);
4793 } else if (dst_enc < 16) {
4794 Assembler::vpsraw(dst, dst, shift, vector_len);
4795 } else if (nds_enc < 16) {
4796 // use nds as scratch
4797 evmovdqul(nds, dst, Assembler::AVX_512bit);
4798 Assembler::vpsraw(nds, nds, shift, vector_len);
4799 evmovdqul(dst, nds, Assembler::AVX_512bit);
4800 } else {
4801 // use nds as scratch for xmm0
4802 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4803 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4804 Assembler::vpsraw(xmm0, xmm0, shift, vector_len);
4805 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4806 }
4807 }
4808
4809 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
4810 int dst_enc = dst->encoding();
4811 int nds_enc = nds->encoding();
4812 int shift_enc = shift->encoding();
4813 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4814 Assembler::vpsrlw(dst, nds, shift, vector_len);
4815 } else if ((dst_enc < 16) && (shift_enc < 16)) {
4816 Assembler::vpsrlw(dst, dst, shift, vector_len);
4817 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4818 // use nds_enc as scratch with shift
4819 evmovdqul(nds, shift, Assembler::AVX_512bit);
4820 Assembler::vpsrlw(dst, dst, nds, vector_len);
4821 } else if ((shift_enc < 16) && (nds_enc < 16)) {
4822 // use nds as scratch with dst
4823 evmovdqul(nds, dst, Assembler::AVX_512bit);
4824 Assembler::vpsrlw(nds, nds, shift, vector_len);
4825 evmovdqul(dst, nds, Assembler::AVX_512bit);
4826 } else if (dst_enc < 16) {
4827 // use nds to save a copy of xmm0 and hold shift
4828 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4829 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4830 Assembler::vpsrlw(dst, dst, xmm0, vector_len);
4831 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4832 } else if (nds_enc < 16) {
4833 // use nds as dest as temps
4834 evmovdqul(nds, dst, Assembler::AVX_512bit);
4835 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4836 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4837 Assembler::vpsrlw(nds, nds, xmm0, vector_len);
4838 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4839 evmovdqul(dst, nds, Assembler::AVX_512bit);
4840 } else {
4841 // worse case scenario, all regs are in the upper bank
4842 subptr(rsp, 64);
4843 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4844 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4845 evmovdqul(xmm1, shift, Assembler::AVX_512bit);
4846 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4847 Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len);
4848 evmovdqul(xmm1, dst, Assembler::AVX_512bit);
4849 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4850 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4851 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4852 addptr(rsp, 64);
4853 }
4854 }
4855
4856 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
4857 int dst_enc = dst->encoding();
4858 int nds_enc = nds->encoding();
4859 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4860 Assembler::vpsrlw(dst, nds, shift, vector_len);
4861 } else if (dst_enc < 16) {
4862 Assembler::vpsrlw(dst, dst, shift, vector_len);
4863 } else if (nds_enc < 16) {
4864 // use nds as scratch
4865 evmovdqul(nds, dst, Assembler::AVX_512bit);
4866 Assembler::vpsrlw(nds, nds, shift, vector_len);
4867 evmovdqul(dst, nds, Assembler::AVX_512bit);
4868 } else {
4869 // use nds as scratch for xmm0
4870 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4871 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4872 Assembler::vpsrlw(xmm0, xmm0, shift, vector_len);
4873 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4874 }
4875 }
4876
4877 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
4878 int dst_enc = dst->encoding();
4879 int nds_enc = nds->encoding();
4880 int shift_enc = shift->encoding();
4881 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4882 Assembler::vpsllw(dst, nds, shift, vector_len);
4883 } else if ((dst_enc < 16) && (shift_enc < 16)) {
4884 Assembler::vpsllw(dst, dst, shift, vector_len);
4885 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4886 // use nds_enc as scratch with shift
4887 evmovdqul(nds, shift, Assembler::AVX_512bit);
4888 Assembler::vpsllw(dst, dst, nds, vector_len);
4889 } else if ((shift_enc < 16) && (nds_enc < 16)) {
4890 // use nds as scratch with dst
4891 evmovdqul(nds, dst, Assembler::AVX_512bit);
4892 Assembler::vpsllw(nds, nds, shift, vector_len);
4893 evmovdqul(dst, nds, Assembler::AVX_512bit);
4894 } else if (dst_enc < 16) {
4895 // use nds to save a copy of xmm0 and hold shift
4896 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4897 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4898 Assembler::vpsllw(dst, dst, xmm0, vector_len);
4899 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4900 } else if (nds_enc < 16) {
4901 // use nds as dest as temps
4902 evmovdqul(nds, dst, Assembler::AVX_512bit);
4903 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4904 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4905 Assembler::vpsllw(nds, nds, xmm0, vector_len);
4906 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4907 evmovdqul(dst, nds, Assembler::AVX_512bit);
4908 } else {
4909 // worse case scenario, all regs are in the upper bank
4910 subptr(rsp, 64);
4911 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4912 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4913 evmovdqul(xmm1, shift, Assembler::AVX_512bit);
4914 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4915 Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len);
4916 evmovdqul(xmm1, dst, Assembler::AVX_512bit);
4917 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4918 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4919 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4920 addptr(rsp, 64);
4921 }
4922 }
4923
4924 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
4925 int dst_enc = dst->encoding();
4926 int nds_enc = nds->encoding();
4927 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4928 Assembler::vpsllw(dst, nds, shift, vector_len);
4929 } else if (dst_enc < 16) {
4930 Assembler::vpsllw(dst, dst, shift, vector_len);
4931 } else if (nds_enc < 16) {
4932 // use nds as scratch
4933 evmovdqul(nds, dst, Assembler::AVX_512bit);
4934 Assembler::vpsllw(nds, nds, shift, vector_len);
4935 evmovdqul(dst, nds, Assembler::AVX_512bit);
4936 } else {
4937 // use nds as scratch for xmm0
4938 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4939 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4940 Assembler::vpsllw(xmm0, xmm0, shift, vector_len);
4941 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4942 }
4943 }
4944
4945 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) {
4946 int dst_enc = dst->encoding();
4947 int src_enc = src->encoding();
4948 if ((dst_enc < 16) && (src_enc < 16)) {
4949 Assembler::vptest(dst, src);
4950 } else if (src_enc < 16) {
4951 subptr(rsp, 64);
4952 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4953 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4954 Assembler::vptest(xmm0, src);
4955 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4956 addptr(rsp, 64);
4957 } else if (dst_enc < 16) {
4958 subptr(rsp, 64);
4959 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4960 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4961 Assembler::vptest(dst, xmm0);
4962 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4963 addptr(rsp, 64);
4964 } else {
4965 subptr(rsp, 64);
4966 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4967 subptr(rsp, 64);
4968 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4969 movdqu(xmm0, src);
4970 movdqu(xmm1, dst);
4971 Assembler::vptest(xmm1, xmm0);
4972 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4973 addptr(rsp, 64);
4974 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4975 addptr(rsp, 64);
4976 }
4977 }
4978
4979 // This instruction exists within macros, ergo we cannot control its input
4980 // when emitted through those patterns.
4981 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) {
4982 if (VM_Version::supports_avx512nobw()) {
4983 int dst_enc = dst->encoding();
4984 int src_enc = src->encoding();
4985 if (dst_enc == src_enc) {
4986 if (dst_enc < 16) {
4987 Assembler::punpcklbw(dst, src);
4988 } else {
4989 subptr(rsp, 64);
4990 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4991 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4992 Assembler::punpcklbw(xmm0, xmm0);
4993 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4994 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4995 addptr(rsp, 64);
4996 }
4997 } else {
4998 if ((src_enc < 16) && (dst_enc < 16)) {
4999 Assembler::punpcklbw(dst, src);
5000 } else if (src_enc < 16) {
5001 subptr(rsp, 64);
5002 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
5003 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
5004 Assembler::punpcklbw(xmm0, src);
5005 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
5006 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
5007 addptr(rsp, 64);
5008 } else if (dst_enc < 16) {
5009 subptr(rsp, 64);
5010 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
5011 evmovdqul(xmm0, src, Assembler::AVX_512bit);
5012 Assembler::punpcklbw(dst, xmm0);
5013 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
5014 addptr(rsp, 64);
5015 } else {
5016 subptr(rsp, 64);
5017 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
5018 subptr(rsp, 64);
5019 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
5020 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
5021 evmovdqul(xmm1, src, Assembler::AVX_512bit);
5022 Assembler::punpcklbw(xmm0, xmm1);
5023 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
5024 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
5025 addptr(rsp, 64);
5026 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
5027 addptr(rsp, 64);
5028 }
5029 }
5030 } else {
5031 Assembler::punpcklbw(dst, src);
5032 }
5033 }
5034
5035 void MacroAssembler::pshufd(XMMRegister dst, Address src, int mode) {
5036 if (VM_Version::supports_avx512vl()) {
5037 Assembler::pshufd(dst, src, mode);
5038 } else {
5039 int dst_enc = dst->encoding();
5040 if (dst_enc < 16) {
5041 Assembler::pshufd(dst, src, mode);
5042 } else {
5043 subptr(rsp, 64);
5044 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
5045 Assembler::pshufd(xmm0, src, mode);
5046 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
5047 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
5048 addptr(rsp, 64);
5049 }
5050 }
5051 }
5052
5053 // This instruction exists within macros, ergo we cannot control its input
5054 // when emitted through those patterns.
5055 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
5056 if (VM_Version::supports_avx512nobw()) {
5057 int dst_enc = dst->encoding();
5058 int src_enc = src->encoding();
5059 if (dst_enc == src_enc) {
5060 if (dst_enc < 16) {
5061 Assembler::pshuflw(dst, src, mode);
5062 } else {
5063 subptr(rsp, 64);
5064 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
5065 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
5066 Assembler::pshuflw(xmm0, xmm0, mode);
5067 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
5068 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
5069 addptr(rsp, 64);
5070 }
5071 } else {
5072 if ((src_enc < 16) && (dst_enc < 16)) {
5073 Assembler::pshuflw(dst, src, mode);
5074 } else if (src_enc < 16) {
5075 subptr(rsp, 64);
5076 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
5077 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
5078 Assembler::pshuflw(xmm0, src, mode);
5079 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
5080 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
5081 addptr(rsp, 64);
5082 } else if (dst_enc < 16) {
5083 subptr(rsp, 64);
5084 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
5085 evmovdqul(xmm0, src, Assembler::AVX_512bit);
5086 Assembler::pshuflw(dst, xmm0, mode);
5087 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
5088 addptr(rsp, 64);
5089 } else {
5090 subptr(rsp, 64);
5091 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
5092 subptr(rsp, 64);
5093 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
5094 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
5095 evmovdqul(xmm1, src, Assembler::AVX_512bit);
5096 Assembler::pshuflw(xmm0, xmm1, mode);
5097 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
5098 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
5099 addptr(rsp, 64);
5100 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
5101 addptr(rsp, 64);
5102 }
5103 }
5104 } else {
5105 Assembler::pshuflw(dst, src, mode);
5106 }
5107 }
5108
5109 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
5110 if (reachable(src)) {
5111 vandpd(dst, nds, as_Address(src), vector_len);
5112 } else {
5113 lea(rscratch1, src);
5114 vandpd(dst, nds, Address(rscratch1, 0), vector_len);
5115 }
5116 }
5117
5118 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
5119 if (reachable(src)) {
5120 vandps(dst, nds, as_Address(src), vector_len);
5121 } else {
5122 lea(rscratch1, src);
5123 vandps(dst, nds, Address(rscratch1, 0), vector_len);
5124 }
5125 }
5126
5127 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5128 if (reachable(src)) {
5129 vdivsd(dst, nds, as_Address(src));
5130 } else {
5131 lea(rscratch1, src);
5132 vdivsd(dst, nds, Address(rscratch1, 0));
5133 }
5134 }
5135
5136 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5137 if (reachable(src)) {
5138 vdivss(dst, nds, as_Address(src));
5139 } else {
5140 lea(rscratch1, src);
5141 vdivss(dst, nds, Address(rscratch1, 0));
5142 }
5143 }
5144
5145 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5146 if (reachable(src)) {
5147 vmulsd(dst, nds, as_Address(src));
5148 } else {
5149 lea(rscratch1, src);
5150 vmulsd(dst, nds, Address(rscratch1, 0));
5151 }
5152 }
5153
5154 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5155 if (reachable(src)) {
5156 vmulss(dst, nds, as_Address(src));
5157 } else {
5158 lea(rscratch1, src);
5159 vmulss(dst, nds, Address(rscratch1, 0));
5160 }
5161 }
5162
5163 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5164 if (reachable(src)) {
5165 vsubsd(dst, nds, as_Address(src));
5166 } else {
5167 lea(rscratch1, src);
5168 vsubsd(dst, nds, Address(rscratch1, 0));
5169 }
5170 }
5171
5172 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5173 if (reachable(src)) {
5174 vsubss(dst, nds, as_Address(src));
5175 } else {
5176 lea(rscratch1, src);
5177 vsubss(dst, nds, Address(rscratch1, 0));
5178 }
5179 }
5180
5181 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5182 int nds_enc = nds->encoding();
5183 int dst_enc = dst->encoding();
5184 bool dst_upper_bank = (dst_enc > 15);
5185 bool nds_upper_bank = (nds_enc > 15);
5186 if (VM_Version::supports_avx512novl() &&
5187 (nds_upper_bank || dst_upper_bank)) {
5188 if (dst_upper_bank) {
5189 subptr(rsp, 64);
5190 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
5191 movflt(xmm0, nds);
5192 vxorps(xmm0, xmm0, src, Assembler::AVX_128bit);
5193 movflt(dst, xmm0);
5194 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
5195 addptr(rsp, 64);
5196 } else {
5197 movflt(dst, nds);
5198 vxorps(dst, dst, src, Assembler::AVX_128bit);
5199 }
5200 } else {
5201 vxorps(dst, nds, src, Assembler::AVX_128bit);
5202 }
5203 }
5204
5205 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5206 int nds_enc = nds->encoding();
5207 int dst_enc = dst->encoding();
5208 bool dst_upper_bank = (dst_enc > 15);
5209 bool nds_upper_bank = (nds_enc > 15);
5210 if (VM_Version::supports_avx512novl() &&
5211 (nds_upper_bank || dst_upper_bank)) {
5212 if (dst_upper_bank) {
5213 subptr(rsp, 64);
5214 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
5215 movdbl(xmm0, nds);
5216 vxorpd(xmm0, xmm0, src, Assembler::AVX_128bit);
5217 movdbl(dst, xmm0);
5218 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
5219 addptr(rsp, 64);
5220 } else {
5221 movdbl(dst, nds);
5222 vxorpd(dst, dst, src, Assembler::AVX_128bit);
5223 }
5224 } else {
5225 vxorpd(dst, nds, src, Assembler::AVX_128bit);
5226 }
5227 }
5228
5229 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
5230 if (reachable(src)) {
5231 vxorpd(dst, nds, as_Address(src), vector_len);
5232 } else {
5233 lea(rscratch1, src);
5234 vxorpd(dst, nds, Address(rscratch1, 0), vector_len);
5235 }
5236 }
5237
5238 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
5239 if (reachable(src)) {
5240 vxorps(dst, nds, as_Address(src), vector_len);
5241 } else {
5242 lea(rscratch1, src);
5243 vxorps(dst, nds, Address(rscratch1, 0), vector_len);
5244 }
5245 }
5246
5247 void MacroAssembler::clear_jweak_tag(Register possibly_jweak) {
5248 const int32_t inverted_jweak_mask = ~static_cast<int32_t>(JNIHandles::weak_tag_mask);
5249 STATIC_ASSERT(inverted_jweak_mask == -2); // otherwise check this code
5250 // The inverted mask is sign-extended
5251 andptr(possibly_jweak, inverted_jweak_mask);
5252 }
5253
5254 void MacroAssembler::resolve_jobject(Register value,
5255 Register thread,
5256 Register tmp) {
5257 assert_different_registers(value, thread, tmp);
5258 Label done, not_weak;
5259 testptr(value, value);
5260 jcc(Assembler::zero, done); // Use NULL as-is.
5261 testptr(value, JNIHandles::weak_tag_mask); // Test for jweak tag.
5262 jcc(Assembler::zero, not_weak);
5263 // Resolve jweak.
5264 access_load_at(T_OBJECT, IN_ROOT | ON_PHANTOM_OOP_REF,
5265 value, Address(value, -JNIHandles::weak_tag_value), tmp, thread);
5266 verify_oop(value);
5267 jmp(done);
5268 bind(not_weak);
5269 // Resolve (untagged) jobject.
5270 access_load_at(T_OBJECT, IN_ROOT | IN_CONCURRENT_ROOT,
5271 value, Address(value, 0), tmp, thread);
5272 verify_oop(value);
5273 bind(done);
5274 }
5275
5276 void MacroAssembler::subptr(Register dst, int32_t imm32) {
5277 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
5278 }
5279
5280 // Force generation of a 4 byte immediate value even if it fits into 8bit
5281 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
5282 LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32));
5283 }
5284
5285 void MacroAssembler::subptr(Register dst, Register src) {
5286 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
5287 }
5288
5289 // C++ bool manipulation
5290 void MacroAssembler::testbool(Register dst) {
5291 if(sizeof(bool) == 1)
5292 testb(dst, 0xff);
5293 else if(sizeof(bool) == 2) {
5294 // testw implementation needed for two byte bools
5295 ShouldNotReachHere();
5296 } else if(sizeof(bool) == 4)
5297 testl(dst, dst);
5298 else
5299 // unsupported
5300 ShouldNotReachHere();
5301 }
5302
5303 void MacroAssembler::testptr(Register dst, Register src) {
5304 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
5305 }
5306
5307 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
5308 void MacroAssembler::tlab_allocate(Register obj,
5309 Register var_size_in_bytes,
5310 int con_size_in_bytes,
5311 Register t1,
5312 Register t2,
5313 Label& slow_case) {
5314 assert_different_registers(obj, t1, t2);
5315 assert_different_registers(obj, var_size_in_bytes, t1);
5316 Register end = t2;
5317 Register thread = NOT_LP64(t1) LP64_ONLY(r15_thread);
5318
5319 verify_tlab();
5320
5321 NOT_LP64(get_thread(thread));
5322
5323 movptr(obj, Address(thread, JavaThread::tlab_top_offset()));
5324 if (var_size_in_bytes == noreg) {
5325 lea(end, Address(obj, con_size_in_bytes));
5326 } else {
5327 lea(end, Address(obj, var_size_in_bytes, Address::times_1));
5328 }
5329 cmpptr(end, Address(thread, JavaThread::tlab_end_offset()));
5330 jcc(Assembler::above, slow_case);
5331
5332 // update the tlab top pointer
5333 movptr(Address(thread, JavaThread::tlab_top_offset()), end);
5334
5335 // recover var_size_in_bytes if necessary
5336 if (var_size_in_bytes == end) {
5337 subptr(var_size_in_bytes, obj);
5338 }
5339 verify_tlab();
5340 }
5341
5342 // Preserves the contents of address, destroys the contents length_in_bytes and temp.
5343 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) {
5344 assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different");
5345 assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord");
5346 Label done;
5347
5348 testptr(length_in_bytes, length_in_bytes);
5349 jcc(Assembler::zero, done);
5350
5351 // initialize topmost word, divide index by 2, check if odd and test if zero
5352 // note: for the remaining code to work, index must be a multiple of BytesPerWord
5353 #ifdef ASSERT
5354 {
5355 Label L;
5356 testptr(length_in_bytes, BytesPerWord - 1);
5357 jcc(Assembler::zero, L);
5358 stop("length must be a multiple of BytesPerWord");
5359 bind(L);
5360 }
5361 #endif
5362 Register index = length_in_bytes;
5363 xorptr(temp, temp); // use _zero reg to clear memory (shorter code)
5364 if (UseIncDec) {
5365 shrptr(index, 3); // divide by 8/16 and set carry flag if bit 2 was set
5366 } else {
5367 shrptr(index, 2); // use 2 instructions to avoid partial flag stall
5368 shrptr(index, 1);
5369 }
5370 #ifndef _LP64
5371 // index could have not been a multiple of 8 (i.e., bit 2 was set)
5372 {
5373 Label even;
5374 // note: if index was a multiple of 8, then it cannot
5375 // be 0 now otherwise it must have been 0 before
5376 // => if it is even, we don't need to check for 0 again
5377 jcc(Assembler::carryClear, even);
5378 // clear topmost word (no jump would be needed if conditional assignment worked here)
5379 movptr(Address(address, index, Address::times_8, offset_in_bytes - 0*BytesPerWord), temp);
5380 // index could be 0 now, must check again
5381 jcc(Assembler::zero, done);
5382 bind(even);
5383 }
5384 #endif // !_LP64
5385 // initialize remaining object fields: index is a multiple of 2 now
5386 {
5387 Label loop;
5388 bind(loop);
5389 movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp);
5390 NOT_LP64(movptr(Address(address, index, Address::times_8, offset_in_bytes - 2*BytesPerWord), temp);)
5391 decrement(index);
5392 jcc(Assembler::notZero, loop);
5393 }
5394
5395 bind(done);
5396 }
5397
5398 void MacroAssembler::incr_allocated_bytes(Register thread,
5399 Register var_size_in_bytes,
5400 int con_size_in_bytes,
5401 Register t1) {
5402 if (!thread->is_valid()) {
5403 #ifdef _LP64
5404 thread = r15_thread;
5405 #else
5406 assert(t1->is_valid(), "need temp reg");
5407 thread = t1;
5408 get_thread(thread);
5409 #endif
5410 }
5411
5412 #ifdef _LP64
5413 if (var_size_in_bytes->is_valid()) {
5414 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes);
5415 } else {
5416 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes);
5417 }
5418 #else
5419 if (var_size_in_bytes->is_valid()) {
5420 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes);
5421 } else {
5422 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes);
5423 }
5424 adcl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())+4), 0);
5425 #endif
5426 }
5427
5428 // Look up the method for a megamorphic invokeinterface call.
5429 // The target method is determined by <intf_klass, itable_index>.
5430 // The receiver klass is in recv_klass.
5431 // On success, the result will be in method_result, and execution falls through.
5432 // On failure, execution transfers to the given label.
5433 void MacroAssembler::lookup_interface_method(Register recv_klass,
5434 Register intf_klass,
5435 RegisterOrConstant itable_index,
5436 Register method_result,
5437 Register scan_temp,
5438 Label& L_no_such_interface,
5439 bool return_method) {
5440 assert_different_registers(recv_klass, intf_klass, scan_temp);
5441 assert_different_registers(method_result, intf_klass, scan_temp);
5442 assert(recv_klass != method_result || !return_method,
5443 "recv_klass can be destroyed when method isn't needed");
5444
5445 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
5446 "caller must use same register for non-constant itable index as for method");
5447
5448 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
5449 int vtable_base = in_bytes(Klass::vtable_start_offset());
5450 int itentry_off = itableMethodEntry::method_offset_in_bytes();
5451 int scan_step = itableOffsetEntry::size() * wordSize;
5452 int vte_size = vtableEntry::size_in_bytes();
5453 Address::ScaleFactor times_vte_scale = Address::times_ptr;
5454 assert(vte_size == wordSize, "else adjust times_vte_scale");
5455
5456 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
5457
5458 // %%% Could store the aligned, prescaled offset in the klassoop.
5459 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
5460
5461 if (return_method) {
5462 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
5463 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
5464 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
5465 }
5466
5467 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
5468 // if (scan->interface() == intf) {
5469 // result = (klass + scan->offset() + itable_index);
5470 // }
5471 // }
5472 Label search, found_method;
5473
5474 for (int peel = 1; peel >= 0; peel--) {
5475 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
5476 cmpptr(intf_klass, method_result);
5477
5478 if (peel) {
5479 jccb(Assembler::equal, found_method);
5480 } else {
5481 jccb(Assembler::notEqual, search);
5482 // (invert the test to fall through to found_method...)
5483 }
5484
5485 if (!peel) break;
5486
5487 bind(search);
5488
5489 // Check that the previous entry is non-null. A null entry means that
5490 // the receiver class doesn't implement the interface, and wasn't the
5491 // same as when the caller was compiled.
5492 testptr(method_result, method_result);
5493 jcc(Assembler::zero, L_no_such_interface);
5494 addptr(scan_temp, scan_step);
5495 }
5496
5497 bind(found_method);
5498
5499 if (return_method) {
5500 // Got a hit.
5501 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes()));
5502 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
5503 }
5504 }
5505
5506
5507 // virtual method calling
5508 void MacroAssembler::lookup_virtual_method(Register recv_klass,
5509 RegisterOrConstant vtable_index,
5510 Register method_result) {
5511 const int base = in_bytes(Klass::vtable_start_offset());
5512 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
5513 Address vtable_entry_addr(recv_klass,
5514 vtable_index, Address::times_ptr,
5515 base + vtableEntry::method_offset_in_bytes());
5516 movptr(method_result, vtable_entry_addr);
5517 }
5518
5519
5520 void MacroAssembler::check_klass_subtype(Register sub_klass,
5521 Register super_klass,
5522 Register temp_reg,
5523 Label& L_success) {
5524 Label L_failure;
5525 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL);
5526 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL);
5527 bind(L_failure);
5528 }
5529
5530
5531 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
5532 Register super_klass,
5533 Register temp_reg,
5534 Label* L_success,
5535 Label* L_failure,
5536 Label* L_slow_path,
5537 RegisterOrConstant super_check_offset) {
5538 assert_different_registers(sub_klass, super_klass, temp_reg);
5539 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
5540 if (super_check_offset.is_register()) {
5541 assert_different_registers(sub_klass, super_klass,
5542 super_check_offset.as_register());
5543 } else if (must_load_sco) {
5544 assert(temp_reg != noreg, "supply either a temp or a register offset");
5545 }
5546
5547 Label L_fallthrough;
5548 int label_nulls = 0;
5549 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
5550 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
5551 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
5552 assert(label_nulls <= 1, "at most one NULL in the batch");
5553
5554 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
5555 int sco_offset = in_bytes(Klass::super_check_offset_offset());
5556 Address super_check_offset_addr(super_klass, sco_offset);
5557
5558 // Hacked jcc, which "knows" that L_fallthrough, at least, is in
5559 // range of a jccb. If this routine grows larger, reconsider at
5560 // least some of these.
5561 #define local_jcc(assembler_cond, label) \
5562 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \
5563 else jcc( assembler_cond, label) /*omit semi*/
5564
5565 // Hacked jmp, which may only be used just before L_fallthrough.
5566 #define final_jmp(label) \
5567 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
5568 else jmp(label) /*omit semi*/
5569
5570 // If the pointers are equal, we are done (e.g., String[] elements).
5571 // This self-check enables sharing of secondary supertype arrays among
5572 // non-primary types such as array-of-interface. Otherwise, each such
5573 // type would need its own customized SSA.
5574 // We move this check to the front of the fast path because many
5575 // type checks are in fact trivially successful in this manner,
5576 // so we get a nicely predicted branch right at the start of the check.
5577 cmpptr(sub_klass, super_klass);
5578 local_jcc(Assembler::equal, *L_success);
5579
5580 // Check the supertype display:
5581 if (must_load_sco) {
5582 // Positive movl does right thing on LP64.
5583 movl(temp_reg, super_check_offset_addr);
5584 super_check_offset = RegisterOrConstant(temp_reg);
5585 }
5586 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
5587 cmpptr(super_klass, super_check_addr); // load displayed supertype
5588
5589 // This check has worked decisively for primary supers.
5590 // Secondary supers are sought in the super_cache ('super_cache_addr').
5591 // (Secondary supers are interfaces and very deeply nested subtypes.)
5592 // This works in the same check above because of a tricky aliasing
5593 // between the super_cache and the primary super display elements.
5594 // (The 'super_check_addr' can address either, as the case requires.)
5595 // Note that the cache is updated below if it does not help us find
5596 // what we need immediately.
5597 // So if it was a primary super, we can just fail immediately.
5598 // Otherwise, it's the slow path for us (no success at this point).
5599
5600 if (super_check_offset.is_register()) {
5601 local_jcc(Assembler::equal, *L_success);
5602 cmpl(super_check_offset.as_register(), sc_offset);
5603 if (L_failure == &L_fallthrough) {
5604 local_jcc(Assembler::equal, *L_slow_path);
5605 } else {
5606 local_jcc(Assembler::notEqual, *L_failure);
5607 final_jmp(*L_slow_path);
5608 }
5609 } else if (super_check_offset.as_constant() == sc_offset) {
5610 // Need a slow path; fast failure is impossible.
5611 if (L_slow_path == &L_fallthrough) {
5612 local_jcc(Assembler::equal, *L_success);
5613 } else {
5614 local_jcc(Assembler::notEqual, *L_slow_path);
5615 final_jmp(*L_success);
5616 }
5617 } else {
5618 // No slow path; it's a fast decision.
5619 if (L_failure == &L_fallthrough) {
5620 local_jcc(Assembler::equal, *L_success);
5621 } else {
5622 local_jcc(Assembler::notEqual, *L_failure);
5623 final_jmp(*L_success);
5624 }
5625 }
5626
5627 bind(L_fallthrough);
5628
5629 #undef local_jcc
5630 #undef final_jmp
5631 }
5632
5633
5634 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
5635 Register super_klass,
5636 Register temp_reg,
5637 Register temp2_reg,
5638 Label* L_success,
5639 Label* L_failure,
5640 bool set_cond_codes) {
5641 assert_different_registers(sub_klass, super_klass, temp_reg);
5642 if (temp2_reg != noreg)
5643 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
5644 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
5645
5646 Label L_fallthrough;
5647 int label_nulls = 0;
5648 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
5649 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
5650 assert(label_nulls <= 1, "at most one NULL in the batch");
5651
5652 // a couple of useful fields in sub_klass:
5653 int ss_offset = in_bytes(Klass::secondary_supers_offset());
5654 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
5655 Address secondary_supers_addr(sub_klass, ss_offset);
5656 Address super_cache_addr( sub_klass, sc_offset);
5657
5658 // Do a linear scan of the secondary super-klass chain.
5659 // This code is rarely used, so simplicity is a virtue here.
5660 // The repne_scan instruction uses fixed registers, which we must spill.
5661 // Don't worry too much about pre-existing connections with the input regs.
5662
5663 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
5664 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
5665
5666 // Get super_klass value into rax (even if it was in rdi or rcx).
5667 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
5668 if (super_klass != rax || UseCompressedOops) {
5669 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
5670 mov(rax, super_klass);
5671 }
5672 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
5673 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
5674
5675 #ifndef PRODUCT
5676 int* pst_counter = &SharedRuntime::_partial_subtype_ctr;
5677 ExternalAddress pst_counter_addr((address) pst_counter);
5678 NOT_LP64( incrementl(pst_counter_addr) );
5679 LP64_ONLY( lea(rcx, pst_counter_addr) );
5680 LP64_ONLY( incrementl(Address(rcx, 0)) );
5681 #endif //PRODUCT
5682
5683 // We will consult the secondary-super array.
5684 movptr(rdi, secondary_supers_addr);
5685 // Load the array length. (Positive movl does right thing on LP64.)
5686 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
5687 // Skip to start of data.
5688 addptr(rdi, Array<Klass*>::base_offset_in_bytes());
5689
5690 // Scan RCX words at [RDI] for an occurrence of RAX.
5691 // Set NZ/Z based on last compare.
5692 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
5693 // not change flags (only scas instruction which is repeated sets flags).
5694 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
5695
5696 testptr(rax,rax); // Set Z = 0
5697 repne_scan();
5698
5699 // Unspill the temp. registers:
5700 if (pushed_rdi) pop(rdi);
5701 if (pushed_rcx) pop(rcx);
5702 if (pushed_rax) pop(rax);
5703
5704 if (set_cond_codes) {
5705 // Special hack for the AD files: rdi is guaranteed non-zero.
5706 assert(!pushed_rdi, "rdi must be left non-NULL");
5707 // Also, the condition codes are properly set Z/NZ on succeed/failure.
5708 }
5709
5710 if (L_failure == &L_fallthrough)
5711 jccb(Assembler::notEqual, *L_failure);
5712 else jcc(Assembler::notEqual, *L_failure);
5713
5714 // Success. Cache the super we found and proceed in triumph.
5715 movptr(super_cache_addr, super_klass);
5716
5717 if (L_success != &L_fallthrough) {
5718 jmp(*L_success);
5719 }
5720
5721 #undef IS_A_TEMP
5722
5723 bind(L_fallthrough);
5724 }
5725
5726
5727 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
5728 if (VM_Version::supports_cmov()) {
5729 cmovl(cc, dst, src);
5730 } else {
5731 Label L;
5732 jccb(negate_condition(cc), L);
5733 movl(dst, src);
5734 bind(L);
5735 }
5736 }
5737
5738 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
5739 if (VM_Version::supports_cmov()) {
5740 cmovl(cc, dst, src);
5741 } else {
5742 Label L;
5743 jccb(negate_condition(cc), L);
5744 movl(dst, src);
5745 bind(L);
5746 }
5747 }
5748
5749 void MacroAssembler::verify_oop(Register reg, const char* s) {
5750 if (!VerifyOops) return;
5751
5752 // Pass register number to verify_oop_subroutine
5753 const char* b = NULL;
5754 {
5755 ResourceMark rm;
5756 stringStream ss;
5757 ss.print("verify_oop: %s: %s", reg->name(), s);
5758 b = code_string(ss.as_string());
5759 }
5760 BLOCK_COMMENT("verify_oop {");
5761 #ifdef _LP64
5762 push(rscratch1); // save r10, trashed by movptr()
5763 #endif
5764 push(rax); // save rax,
5765 push(reg); // pass register argument
5766 ExternalAddress buffer((address) b);
5767 // avoid using pushptr, as it modifies scratch registers
5768 // and our contract is not to modify anything
5769 movptr(rax, buffer.addr());
5770 push(rax);
5771 // call indirectly to solve generation ordering problem
5772 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5773 call(rax);
5774 // Caller pops the arguments (oop, message) and restores rax, r10
5775 BLOCK_COMMENT("} verify_oop");
5776 }
5777
5778
5779 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
5780 Register tmp,
5781 int offset) {
5782 intptr_t value = *delayed_value_addr;
5783 if (value != 0)
5784 return RegisterOrConstant(value + offset);
5785
5786 // load indirectly to solve generation ordering problem
5787 movptr(tmp, ExternalAddress((address) delayed_value_addr));
5788
5789 #ifdef ASSERT
5790 { Label L;
5791 testptr(tmp, tmp);
5792 if (WizardMode) {
5793 const char* buf = NULL;
5794 {
5795 ResourceMark rm;
5796 stringStream ss;
5797 ss.print("DelayedValue=" INTPTR_FORMAT, delayed_value_addr[1]);
5798 buf = code_string(ss.as_string());
5799 }
5800 jcc(Assembler::notZero, L);
5801 STOP(buf);
5802 } else {
5803 jccb(Assembler::notZero, L);
5804 hlt();
5805 }
5806 bind(L);
5807 }
5808 #endif
5809
5810 if (offset != 0)
5811 addptr(tmp, offset);
5812
5813 return RegisterOrConstant(tmp);
5814 }
5815
5816
5817 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
5818 int extra_slot_offset) {
5819 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
5820 int stackElementSize = Interpreter::stackElementSize;
5821 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
5822 #ifdef ASSERT
5823 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
5824 assert(offset1 - offset == stackElementSize, "correct arithmetic");
5825 #endif
5826 Register scale_reg = noreg;
5827 Address::ScaleFactor scale_factor = Address::no_scale;
5828 if (arg_slot.is_constant()) {
5829 offset += arg_slot.as_constant() * stackElementSize;
5830 } else {
5831 scale_reg = arg_slot.as_register();
5832 scale_factor = Address::times(stackElementSize);
5833 }
5834 offset += wordSize; // return PC is on stack
5835 return Address(rsp, scale_reg, scale_factor, offset);
5836 }
5837
5838
5839 void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
5840 if (!VerifyOops) return;
5841
5842 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord);
5843 // Pass register number to verify_oop_subroutine
5844 const char* b = NULL;
5845 {
5846 ResourceMark rm;
5847 stringStream ss;
5848 ss.print("verify_oop_addr: %s", s);
5849 b = code_string(ss.as_string());
5850 }
5851 #ifdef _LP64
5852 push(rscratch1); // save r10, trashed by movptr()
5853 #endif
5854 push(rax); // save rax,
5855 // addr may contain rsp so we will have to adjust it based on the push
5856 // we just did (and on 64 bit we do two pushes)
5857 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
5858 // stores rax into addr which is backwards of what was intended.
5859 if (addr.uses(rsp)) {
5860 lea(rax, addr);
5861 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord));
5862 } else {
5863 pushptr(addr);
5864 }
5865
5866 ExternalAddress buffer((address) b);
5867 // pass msg argument
5868 // avoid using pushptr, as it modifies scratch registers
5869 // and our contract is not to modify anything
5870 movptr(rax, buffer.addr());
5871 push(rax);
5872
5873 // call indirectly to solve generation ordering problem
5874 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5875 call(rax);
5876 // Caller pops the arguments (addr, message) and restores rax, r10.
5877 }
5878
5879 void MacroAssembler::verify_tlab() {
5880 #ifdef ASSERT
5881 if (UseTLAB && VerifyOops) {
5882 Label next, ok;
5883 Register t1 = rsi;
5884 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
5885
5886 push(t1);
5887 NOT_LP64(push(thread_reg));
5888 NOT_LP64(get_thread(thread_reg));
5889
5890 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5891 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
5892 jcc(Assembler::aboveEqual, next);
5893 STOP("assert(top >= start)");
5894 should_not_reach_here();
5895
5896 bind(next);
5897 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
5898 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5899 jcc(Assembler::aboveEqual, ok);
5900 STOP("assert(top <= end)");
5901 should_not_reach_here();
5902
5903 bind(ok);
5904 NOT_LP64(pop(thread_reg));
5905 pop(t1);
5906 }
5907 #endif
5908 }
5909
5910 class ControlWord {
5911 public:
5912 int32_t _value;
5913
5914 int rounding_control() const { return (_value >> 10) & 3 ; }
5915 int precision_control() const { return (_value >> 8) & 3 ; }
5916 bool precision() const { return ((_value >> 5) & 1) != 0; }
5917 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5918 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5919 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5920 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5921 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5922
5923 void print() const {
5924 // rounding control
5925 const char* rc;
5926 switch (rounding_control()) {
5927 case 0: rc = "round near"; break;
5928 case 1: rc = "round down"; break;
5929 case 2: rc = "round up "; break;
5930 case 3: rc = "chop "; break;
5931 };
5932 // precision control
5933 const char* pc;
5934 switch (precision_control()) {
5935 case 0: pc = "24 bits "; break;
5936 case 1: pc = "reserved"; break;
5937 case 2: pc = "53 bits "; break;
5938 case 3: pc = "64 bits "; break;
5939 };
5940 // flags
5941 char f[9];
5942 f[0] = ' ';
5943 f[1] = ' ';
5944 f[2] = (precision ()) ? 'P' : 'p';
5945 f[3] = (underflow ()) ? 'U' : 'u';
5946 f[4] = (overflow ()) ? 'O' : 'o';
5947 f[5] = (zero_divide ()) ? 'Z' : 'z';
5948 f[6] = (denormalized()) ? 'D' : 'd';
5949 f[7] = (invalid ()) ? 'I' : 'i';
5950 f[8] = '\x0';
5951 // output
5952 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
5953 }
5954
5955 };
5956
5957 class StatusWord {
5958 public:
5959 int32_t _value;
5960
5961 bool busy() const { return ((_value >> 15) & 1) != 0; }
5962 bool C3() const { return ((_value >> 14) & 1) != 0; }
5963 bool C2() const { return ((_value >> 10) & 1) != 0; }
5964 bool C1() const { return ((_value >> 9) & 1) != 0; }
5965 bool C0() const { return ((_value >> 8) & 1) != 0; }
5966 int top() const { return (_value >> 11) & 7 ; }
5967 bool error_status() const { return ((_value >> 7) & 1) != 0; }
5968 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
5969 bool precision() const { return ((_value >> 5) & 1) != 0; }
5970 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5971 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5972 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5973 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5974 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5975
5976 void print() const {
5977 // condition codes
5978 char c[5];
5979 c[0] = (C3()) ? '3' : '-';
5980 c[1] = (C2()) ? '2' : '-';
5981 c[2] = (C1()) ? '1' : '-';
5982 c[3] = (C0()) ? '0' : '-';
5983 c[4] = '\x0';
5984 // flags
5985 char f[9];
5986 f[0] = (error_status()) ? 'E' : '-';
5987 f[1] = (stack_fault ()) ? 'S' : '-';
5988 f[2] = (precision ()) ? 'P' : '-';
5989 f[3] = (underflow ()) ? 'U' : '-';
5990 f[4] = (overflow ()) ? 'O' : '-';
5991 f[5] = (zero_divide ()) ? 'Z' : '-';
5992 f[6] = (denormalized()) ? 'D' : '-';
5993 f[7] = (invalid ()) ? 'I' : '-';
5994 f[8] = '\x0';
5995 // output
5996 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
5997 }
5998
5999 };
6000
6001 class TagWord {
6002 public:
6003 int32_t _value;
6004
6005 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
6006
6007 void print() const {
6008 printf("%04x", _value & 0xFFFF);
6009 }
6010
6011 };
6012
6013 class FPU_Register {
6014 public:
6015 int32_t _m0;
6016 int32_t _m1;
6017 int16_t _ex;
6018
6019 bool is_indefinite() const {
6020 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
6021 }
6022
6023 void print() const {
6024 char sign = (_ex < 0) ? '-' : '+';
6025 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
6026 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
6027 };
6028
6029 };
6030
6031 class FPU_State {
6032 public:
6033 enum {
6034 register_size = 10,
6035 number_of_registers = 8,
6036 register_mask = 7
6037 };
6038
6039 ControlWord _control_word;
6040 StatusWord _status_word;
6041 TagWord _tag_word;
6042 int32_t _error_offset;
6043 int32_t _error_selector;
6044 int32_t _data_offset;
6045 int32_t _data_selector;
6046 int8_t _register[register_size * number_of_registers];
6047
6048 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
6049 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
6050
6051 const char* tag_as_string(int tag) const {
6052 switch (tag) {
6053 case 0: return "valid";
6054 case 1: return "zero";
6055 case 2: return "special";
6056 case 3: return "empty";
6057 }
6058 ShouldNotReachHere();
6059 return NULL;
6060 }
6061
6062 void print() const {
6063 // print computation registers
6064 { int t = _status_word.top();
6065 for (int i = 0; i < number_of_registers; i++) {
6066 int j = (i - t) & register_mask;
6067 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
6068 st(j)->print();
6069 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
6070 }
6071 }
6072 printf("\n");
6073 // print control registers
6074 printf("ctrl = "); _control_word.print(); printf("\n");
6075 printf("stat = "); _status_word .print(); printf("\n");
6076 printf("tags = "); _tag_word .print(); printf("\n");
6077 }
6078
6079 };
6080
6081 class Flag_Register {
6082 public:
6083 int32_t _value;
6084
6085 bool overflow() const { return ((_value >> 11) & 1) != 0; }
6086 bool direction() const { return ((_value >> 10) & 1) != 0; }
6087 bool sign() const { return ((_value >> 7) & 1) != 0; }
6088 bool zero() const { return ((_value >> 6) & 1) != 0; }
6089 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
6090 bool parity() const { return ((_value >> 2) & 1) != 0; }
6091 bool carry() const { return ((_value >> 0) & 1) != 0; }
6092
6093 void print() const {
6094 // flags
6095 char f[8];
6096 f[0] = (overflow ()) ? 'O' : '-';
6097 f[1] = (direction ()) ? 'D' : '-';
6098 f[2] = (sign ()) ? 'S' : '-';
6099 f[3] = (zero ()) ? 'Z' : '-';
6100 f[4] = (auxiliary_carry()) ? 'A' : '-';
6101 f[5] = (parity ()) ? 'P' : '-';
6102 f[6] = (carry ()) ? 'C' : '-';
6103 f[7] = '\x0';
6104 // output
6105 printf("%08x flags = %s", _value, f);
6106 }
6107
6108 };
6109
6110 class IU_Register {
6111 public:
6112 int32_t _value;
6113
6114 void print() const {
6115 printf("%08x %11d", _value, _value);
6116 }
6117
6118 };
6119
6120 class IU_State {
6121 public:
6122 Flag_Register _eflags;
6123 IU_Register _rdi;
6124 IU_Register _rsi;
6125 IU_Register _rbp;
6126 IU_Register _rsp;
6127 IU_Register _rbx;
6128 IU_Register _rdx;
6129 IU_Register _rcx;
6130 IU_Register _rax;
6131
6132 void print() const {
6133 // computation registers
6134 printf("rax, = "); _rax.print(); printf("\n");
6135 printf("rbx, = "); _rbx.print(); printf("\n");
6136 printf("rcx = "); _rcx.print(); printf("\n");
6137 printf("rdx = "); _rdx.print(); printf("\n");
6138 printf("rdi = "); _rdi.print(); printf("\n");
6139 printf("rsi = "); _rsi.print(); printf("\n");
6140 printf("rbp, = "); _rbp.print(); printf("\n");
6141 printf("rsp = "); _rsp.print(); printf("\n");
6142 printf("\n");
6143 // control registers
6144 printf("flgs = "); _eflags.print(); printf("\n");
6145 }
6146 };
6147
6148
6149 class CPU_State {
6150 public:
6151 FPU_State _fpu_state;
6152 IU_State _iu_state;
6153
6154 void print() const {
6155 printf("--------------------------------------------------\n");
6156 _iu_state .print();
6157 printf("\n");
6158 _fpu_state.print();
6159 printf("--------------------------------------------------\n");
6160 }
6161
6162 };
6163
6164
6165 static void _print_CPU_state(CPU_State* state) {
6166 state->print();
6167 };
6168
6169
6170 void MacroAssembler::print_CPU_state() {
6171 push_CPU_state();
6172 push(rsp); // pass CPU state
6173 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
6174 addptr(rsp, wordSize); // discard argument
6175 pop_CPU_state();
6176 }
6177
6178
6179 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
6180 static int counter = 0;
6181 FPU_State* fs = &state->_fpu_state;
6182 counter++;
6183 // For leaf calls, only verify that the top few elements remain empty.
6184 // We only need 1 empty at the top for C2 code.
6185 if( stack_depth < 0 ) {
6186 if( fs->tag_for_st(7) != 3 ) {
6187 printf("FPR7 not empty\n");
6188 state->print();
6189 assert(false, "error");
6190 return false;
6191 }
6192 return true; // All other stack states do not matter
6193 }
6194
6195 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std,
6196 "bad FPU control word");
6197
6198 // compute stack depth
6199 int i = 0;
6200 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++;
6201 int d = i;
6202 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
6203 // verify findings
6204 if (i != FPU_State::number_of_registers) {
6205 // stack not contiguous
6206 printf("%s: stack not contiguous at ST%d\n", s, i);
6207 state->print();
6208 assert(false, "error");
6209 return false;
6210 }
6211 // check if computed stack depth corresponds to expected stack depth
6212 if (stack_depth < 0) {
6213 // expected stack depth is -stack_depth or less
6214 if (d > -stack_depth) {
6215 // too many elements on the stack
6216 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
6217 state->print();
6218 assert(false, "error");
6219 return false;
6220 }
6221 } else {
6222 // expected stack depth is stack_depth
6223 if (d != stack_depth) {
6224 // wrong stack depth
6225 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
6226 state->print();
6227 assert(false, "error");
6228 return false;
6229 }
6230 }
6231 // everything is cool
6232 return true;
6233 }
6234
6235
6236 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
6237 if (!VerifyFPU) return;
6238 push_CPU_state();
6239 push(rsp); // pass CPU state
6240 ExternalAddress msg((address) s);
6241 // pass message string s
6242 pushptr(msg.addr());
6243 push(stack_depth); // pass stack depth
6244 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
6245 addptr(rsp, 3 * wordSize); // discard arguments
6246 // check for error
6247 { Label L;
6248 testl(rax, rax);
6249 jcc(Assembler::notZero, L);
6250 int3(); // break if error condition
6251 bind(L);
6252 }
6253 pop_CPU_state();
6254 }
6255
6256 void MacroAssembler::restore_cpu_control_state_after_jni() {
6257 // Either restore the MXCSR register after returning from the JNI Call
6258 // or verify that it wasn't changed (with -Xcheck:jni flag).
6259 if (VM_Version::supports_sse()) {
6260 if (RestoreMXCSROnJNICalls) {
6261 ldmxcsr(ExternalAddress(StubRoutines::addr_mxcsr_std()));
6262 } else if (CheckJNICalls) {
6263 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
6264 }
6265 }
6266 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
6267 vzeroupper();
6268 // Reset k1 to 0xffff.
6269 if (VM_Version::supports_evex()) {
6270 push(rcx);
6271 movl(rcx, 0xffff);
6272 kmovwl(k1, rcx);
6273 pop(rcx);
6274 }
6275
6276 #ifndef _LP64
6277 // Either restore the x87 floating pointer control word after returning
6278 // from the JNI call or verify that it wasn't changed.
6279 if (CheckJNICalls) {
6280 call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry()));
6281 }
6282 #endif // _LP64
6283 }
6284
6285 // ((OopHandle)result).resolve();
6286 void MacroAssembler::resolve_oop_handle(Register result) {
6287 // OopHandle::resolve is an indirection.
6288 movptr(result, Address(result, 0));
6289 }
6290
6291 void MacroAssembler::load_mirror(Register mirror, Register method) {
6292 // get mirror
6293 const int mirror_offset = in_bytes(Klass::java_mirror_offset());
6294 movptr(mirror, Address(method, Method::const_offset()));
6295 movptr(mirror, Address(mirror, ConstMethod::constants_offset()));
6296 movptr(mirror, Address(mirror, ConstantPool::pool_holder_offset_in_bytes()));
6297 movptr(mirror, Address(mirror, mirror_offset));
6298 resolve_oop_handle(mirror);
6299 }
6300
6301 void MacroAssembler::load_klass(Register dst, Register src) {
6302 #ifdef _LP64
6303 if (UseCompressedClassPointers) {
6304 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
6305 decode_klass_not_null(dst);
6306 } else
6307 #endif
6308 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
6309 }
6310
6311 void MacroAssembler::load_prototype_header(Register dst, Register src) {
6312 load_klass(dst, src);
6313 movptr(dst, Address(dst, Klass::prototype_header_offset()));
6314 }
6315
6316 void MacroAssembler::store_klass(Register dst, Register src) {
6317 #ifdef _LP64
6318 if (UseCompressedClassPointers) {
6319 encode_klass_not_null(src);
6320 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
6321 } else
6322 #endif
6323 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
6324 }
6325
6326 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
6327 Register tmp1, Register thread_tmp) {
6328 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
6329 bool as_raw = (decorators & AS_RAW) != 0;
6330 if (as_raw) {
6331 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
6332 } else {
6333 bs->load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
6334 }
6335 }
6336
6337 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
6338 Register tmp1, Register tmp2) {
6339 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
6340 bool as_raw = (decorators & AS_RAW) != 0;
6341 if (as_raw) {
6342 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, src, tmp1, tmp2);
6343 } else {
6344 bs->store_at(this, decorators, type, dst, src, tmp1, tmp2);
6345 }
6346 }
6347
6348 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1,
6349 Register thread_tmp, DecoratorSet decorators) {
6350 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, thread_tmp);
6351 }
6352
6353 // Doesn't do verfication, generates fixed size code
6354 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1,
6355 Register thread_tmp, DecoratorSet decorators) {
6356 access_load_at(T_OBJECT, IN_HEAP | OOP_NOT_NULL | decorators, dst, src, tmp1, thread_tmp);
6357 }
6358
6359 void MacroAssembler::store_heap_oop(Address dst, Register src, Register tmp1,
6360 Register tmp2, DecoratorSet decorators) {
6361 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, tmp2);
6362 }
6363
6364 // Used for storing NULLs.
6365 void MacroAssembler::store_heap_oop_null(Address dst) {
6366 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg);
6367 }
6368
6369 #ifdef _LP64
6370 void MacroAssembler::store_klass_gap(Register dst, Register src) {
6371 if (UseCompressedClassPointers) {
6372 // Store to klass gap in destination
6373 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
6374 }
6375 }
6376
6377 #ifdef ASSERT
6378 void MacroAssembler::verify_heapbase(const char* msg) {
6379 assert (UseCompressedOops, "should be compressed");
6380 assert (Universe::heap() != NULL, "java heap should be initialized");
6381 if (CheckCompressedOops) {
6382 Label ok;
6383 push(rscratch1); // cmpptr trashes rscratch1
6384 cmpptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
6385 jcc(Assembler::equal, ok);
6386 STOP(msg);
6387 bind(ok);
6388 pop(rscratch1);
6389 }
6390 }
6391 #endif
6392
6393 // Algorithm must match oop.inline.hpp encode_heap_oop.
6394 void MacroAssembler::encode_heap_oop(Register r) {
6395 #ifdef ASSERT
6396 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
6397 #endif
6398 verify_oop(r, "broken oop in encode_heap_oop");
6399 if (Universe::narrow_oop_base() == NULL) {
6400 if (Universe::narrow_oop_shift() != 0) {
6401 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6402 shrq(r, LogMinObjAlignmentInBytes);
6403 }
6404 return;
6405 }
6406 testq(r, r);
6407 cmovq(Assembler::equal, r, r12_heapbase);
6408 subq(r, r12_heapbase);
6409 shrq(r, LogMinObjAlignmentInBytes);
6410 }
6411
6412 void MacroAssembler::encode_heap_oop_not_null(Register r) {
6413 #ifdef ASSERT
6414 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
6415 if (CheckCompressedOops) {
6416 Label ok;
6417 testq(r, r);
6418 jcc(Assembler::notEqual, ok);
6419 STOP("null oop passed to encode_heap_oop_not_null");
6420 bind(ok);
6421 }
6422 #endif
6423 verify_oop(r, "broken oop in encode_heap_oop_not_null");
6424 if (Universe::narrow_oop_base() != NULL) {
6425 subq(r, r12_heapbase);
6426 }
6427 if (Universe::narrow_oop_shift() != 0) {
6428 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6429 shrq(r, LogMinObjAlignmentInBytes);
6430 }
6431 }
6432
6433 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
6434 #ifdef ASSERT
6435 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
6436 if (CheckCompressedOops) {
6437 Label ok;
6438 testq(src, src);
6439 jcc(Assembler::notEqual, ok);
6440 STOP("null oop passed to encode_heap_oop_not_null2");
6441 bind(ok);
6442 }
6443 #endif
6444 verify_oop(src, "broken oop in encode_heap_oop_not_null2");
6445 if (dst != src) {
6446 movq(dst, src);
6447 }
6448 if (Universe::narrow_oop_base() != NULL) {
6449 subq(dst, r12_heapbase);
6450 }
6451 if (Universe::narrow_oop_shift() != 0) {
6452 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6453 shrq(dst, LogMinObjAlignmentInBytes);
6454 }
6455 }
6456
6457 void MacroAssembler::decode_heap_oop(Register r) {
6458 #ifdef ASSERT
6459 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
6460 #endif
6461 if (Universe::narrow_oop_base() == NULL) {
6462 if (Universe::narrow_oop_shift() != 0) {
6463 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6464 shlq(r, LogMinObjAlignmentInBytes);
6465 }
6466 } else {
6467 Label done;
6468 shlq(r, LogMinObjAlignmentInBytes);
6469 jccb(Assembler::equal, done);
6470 addq(r, r12_heapbase);
6471 bind(done);
6472 }
6473 verify_oop(r, "broken oop in decode_heap_oop");
6474 }
6475
6476 void MacroAssembler::decode_heap_oop_not_null(Register r) {
6477 // Note: it will change flags
6478 assert (UseCompressedOops, "should only be used for compressed headers");
6479 assert (Universe::heap() != NULL, "java heap should be initialized");
6480 // Cannot assert, unverified entry point counts instructions (see .ad file)
6481 // vtableStubs also counts instructions in pd_code_size_limit.
6482 // Also do not verify_oop as this is called by verify_oop.
6483 if (Universe::narrow_oop_shift() != 0) {
6484 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6485 shlq(r, LogMinObjAlignmentInBytes);
6486 if (Universe::narrow_oop_base() != NULL) {
6487 addq(r, r12_heapbase);
6488 }
6489 } else {
6490 assert (Universe::narrow_oop_base() == NULL, "sanity");
6491 }
6492 }
6493
6494 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
6495 // Note: it will change flags
6496 assert (UseCompressedOops, "should only be used for compressed headers");
6497 assert (Universe::heap() != NULL, "java heap should be initialized");
6498 // Cannot assert, unverified entry point counts instructions (see .ad file)
6499 // vtableStubs also counts instructions in pd_code_size_limit.
6500 // Also do not verify_oop as this is called by verify_oop.
6501 if (Universe::narrow_oop_shift() != 0) {
6502 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6503 if (LogMinObjAlignmentInBytes == Address::times_8) {
6504 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
6505 } else {
6506 if (dst != src) {
6507 movq(dst, src);
6508 }
6509 shlq(dst, LogMinObjAlignmentInBytes);
6510 if (Universe::narrow_oop_base() != NULL) {
6511 addq(dst, r12_heapbase);
6512 }
6513 }
6514 } else {
6515 assert (Universe::narrow_oop_base() == NULL, "sanity");
6516 if (dst != src) {
6517 movq(dst, src);
6518 }
6519 }
6520 }
6521
6522 void MacroAssembler::encode_klass_not_null(Register r) {
6523 if (Universe::narrow_klass_base() != NULL) {
6524 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
6525 assert(r != r12_heapbase, "Encoding a klass in r12");
6526 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
6527 subq(r, r12_heapbase);
6528 }
6529 if (Universe::narrow_klass_shift() != 0) {
6530 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6531 shrq(r, LogKlassAlignmentInBytes);
6532 }
6533 if (Universe::narrow_klass_base() != NULL) {
6534 reinit_heapbase();
6535 }
6536 }
6537
6538 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
6539 if (dst == src) {
6540 encode_klass_not_null(src);
6541 } else {
6542 if (Universe::narrow_klass_base() != NULL) {
6543 mov64(dst, (int64_t)Universe::narrow_klass_base());
6544 negq(dst);
6545 addq(dst, src);
6546 } else {
6547 movptr(dst, src);
6548 }
6549 if (Universe::narrow_klass_shift() != 0) {
6550 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6551 shrq(dst, LogKlassAlignmentInBytes);
6552 }
6553 }
6554 }
6555
6556 // Function instr_size_for_decode_klass_not_null() counts the instructions
6557 // generated by decode_klass_not_null(register r) and reinit_heapbase(),
6558 // when (Universe::heap() != NULL). Hence, if the instructions they
6559 // generate change, then this method needs to be updated.
6560 int MacroAssembler::instr_size_for_decode_klass_not_null() {
6561 assert (UseCompressedClassPointers, "only for compressed klass ptrs");
6562 if (Universe::narrow_klass_base() != NULL) {
6563 // mov64 + addq + shlq? + mov64 (for reinit_heapbase()).
6564 return (Universe::narrow_klass_shift() == 0 ? 20 : 24);
6565 } else {
6566 // longest load decode klass function, mov64, leaq
6567 return 16;
6568 }
6569 }
6570
6571 // !!! If the instructions that get generated here change then function
6572 // instr_size_for_decode_klass_not_null() needs to get updated.
6573 void MacroAssembler::decode_klass_not_null(Register r) {
6574 // Note: it will change flags
6575 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6576 assert(r != r12_heapbase, "Decoding a klass in r12");
6577 // Cannot assert, unverified entry point counts instructions (see .ad file)
6578 // vtableStubs also counts instructions in pd_code_size_limit.
6579 // Also do not verify_oop as this is called by verify_oop.
6580 if (Universe::narrow_klass_shift() != 0) {
6581 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6582 shlq(r, LogKlassAlignmentInBytes);
6583 }
6584 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
6585 if (Universe::narrow_klass_base() != NULL) {
6586 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
6587 addq(r, r12_heapbase);
6588 reinit_heapbase();
6589 }
6590 }
6591
6592 void MacroAssembler::decode_klass_not_null(Register dst, Register src) {
6593 // Note: it will change flags
6594 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6595 if (dst == src) {
6596 decode_klass_not_null(dst);
6597 } else {
6598 // Cannot assert, unverified entry point counts instructions (see .ad file)
6599 // vtableStubs also counts instructions in pd_code_size_limit.
6600 // Also do not verify_oop as this is called by verify_oop.
6601 mov64(dst, (int64_t)Universe::narrow_klass_base());
6602 if (Universe::narrow_klass_shift() != 0) {
6603 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6604 assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?");
6605 leaq(dst, Address(dst, src, Address::times_8, 0));
6606 } else {
6607 addq(dst, src);
6608 }
6609 }
6610 }
6611
6612 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
6613 assert (UseCompressedOops, "should only be used for compressed headers");
6614 assert (Universe::heap() != NULL, "java heap should be initialized");
6615 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6616 int oop_index = oop_recorder()->find_index(obj);
6617 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6618 mov_narrow_oop(dst, oop_index, rspec);
6619 }
6620
6621 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
6622 assert (UseCompressedOops, "should only be used for compressed headers");
6623 assert (Universe::heap() != NULL, "java heap should be initialized");
6624 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6625 int oop_index = oop_recorder()->find_index(obj);
6626 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6627 mov_narrow_oop(dst, oop_index, rspec);
6628 }
6629
6630 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
6631 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6632 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6633 int klass_index = oop_recorder()->find_index(k);
6634 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6635 mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
6636 }
6637
6638 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
6639 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6640 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6641 int klass_index = oop_recorder()->find_index(k);
6642 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6643 mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
6644 }
6645
6646 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
6647 assert (UseCompressedOops, "should only be used for compressed headers");
6648 assert (Universe::heap() != NULL, "java heap should be initialized");
6649 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6650 int oop_index = oop_recorder()->find_index(obj);
6651 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6652 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6653 }
6654
6655 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
6656 assert (UseCompressedOops, "should only be used for compressed headers");
6657 assert (Universe::heap() != NULL, "java heap should be initialized");
6658 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6659 int oop_index = oop_recorder()->find_index(obj);
6660 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6661 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6662 }
6663
6664 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
6665 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6666 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6667 int klass_index = oop_recorder()->find_index(k);
6668 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6669 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
6670 }
6671
6672 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
6673 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6674 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6675 int klass_index = oop_recorder()->find_index(k);
6676 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6677 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
6678 }
6679
6680 void MacroAssembler::reinit_heapbase() {
6681 if (UseCompressedOops || UseCompressedClassPointers) {
6682 if (Universe::heap() != NULL) {
6683 if (Universe::narrow_oop_base() == NULL) {
6684 MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
6685 } else {
6686 mov64(r12_heapbase, (int64_t)Universe::narrow_ptrs_base());
6687 }
6688 } else {
6689 movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
6690 }
6691 }
6692 }
6693
6694 #endif // _LP64
6695
6696 // C2 compiled method's prolog code.
6697 void MacroAssembler::verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b) {
6698
6699 // WARNING: Initial instruction MUST be 5 bytes or longer so that
6700 // NativeJump::patch_verified_entry will be able to patch out the entry
6701 // code safely. The push to verify stack depth is ok at 5 bytes,
6702 // the frame allocation can be either 3 or 6 bytes. So if we don't do
6703 // stack bang then we must use the 6 byte frame allocation even if
6704 // we have no frame. :-(
6705 assert(stack_bang_size >= framesize || stack_bang_size <= 0, "stack bang size incorrect");
6706
6707 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
6708 // Remove word for return addr
6709 framesize -= wordSize;
6710 stack_bang_size -= wordSize;
6711
6712 // Calls to C2R adapters often do not accept exceptional returns.
6713 // We require that their callers must bang for them. But be careful, because
6714 // some VM calls (such as call site linkage) can use several kilobytes of
6715 // stack. But the stack safety zone should account for that.
6716 // See bugs 4446381, 4468289, 4497237.
6717 if (stack_bang_size > 0) {
6718 generate_stack_overflow_check(stack_bang_size);
6719
6720 // We always push rbp, so that on return to interpreter rbp, will be
6721 // restored correctly and we can correct the stack.
6722 push(rbp);
6723 // Save caller's stack pointer into RBP if the frame pointer is preserved.
6724 if (PreserveFramePointer) {
6725 mov(rbp, rsp);
6726 }
6727 // Remove word for ebp
6728 framesize -= wordSize;
6729
6730 // Create frame
6731 if (framesize) {
6732 subptr(rsp, framesize);
6733 }
6734 } else {
6735 // Create frame (force generation of a 4 byte immediate value)
6736 subptr_imm32(rsp, framesize);
6737
6738 // Save RBP register now.
6739 framesize -= wordSize;
6740 movptr(Address(rsp, framesize), rbp);
6741 // Save caller's stack pointer into RBP if the frame pointer is preserved.
6742 if (PreserveFramePointer) {
6743 movptr(rbp, rsp);
6744 if (framesize > 0) {
6745 addptr(rbp, framesize);
6746 }
6747 }
6748 }
6749
6750 if (VerifyStackAtCalls) { // Majik cookie to verify stack depth
6751 framesize -= wordSize;
6752 movptr(Address(rsp, framesize), (int32_t)0xbadb100d);
6753 }
6754
6755 #ifndef _LP64
6756 // If method sets FPU control word do it now
6757 if (fp_mode_24b) {
6758 fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
6759 }
6760 if (UseSSE >= 2 && VerifyFPU) {
6761 verify_FPU(0, "FPU stack must be clean on entry");
6762 }
6763 #endif
6764
6765 #ifdef ASSERT
6766 if (VerifyStackAtCalls) {
6767 Label L;
6768 push(rax);
6769 mov(rax, rsp);
6770 andptr(rax, StackAlignmentInBytes-1);
6771 cmpptr(rax, StackAlignmentInBytes-wordSize);
6772 pop(rax);
6773 jcc(Assembler::equal, L);
6774 STOP("Stack is not properly aligned!");
6775 bind(L);
6776 }
6777 #endif
6778
6779 }
6780
6781 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp, bool is_large) {
6782 // cnt - number of qwords (8-byte words).
6783 // base - start address, qword aligned.
6784 // is_large - if optimizers know cnt is larger than InitArrayShortSize
6785 assert(base==rdi, "base register must be edi for rep stos");
6786 assert(tmp==rax, "tmp register must be eax for rep stos");
6787 assert(cnt==rcx, "cnt register must be ecx for rep stos");
6788 assert(InitArrayShortSize % BytesPerLong == 0,
6789 "InitArrayShortSize should be the multiple of BytesPerLong");
6790
6791 Label DONE;
6792
6793 xorptr(tmp, tmp);
6794
6795 if (!is_large) {
6796 Label LOOP, LONG;
6797 cmpptr(cnt, InitArrayShortSize/BytesPerLong);
6798 jccb(Assembler::greater, LONG);
6799
6800 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
6801
6802 decrement(cnt);
6803 jccb(Assembler::negative, DONE); // Zero length
6804
6805 // Use individual pointer-sized stores for small counts:
6806 BIND(LOOP);
6807 movptr(Address(base, cnt, Address::times_ptr), tmp);
6808 decrement(cnt);
6809 jccb(Assembler::greaterEqual, LOOP);
6810 jmpb(DONE);
6811
6812 BIND(LONG);
6813 }
6814
6815 // Use longer rep-prefixed ops for non-small counts:
6816 if (UseFastStosb) {
6817 shlptr(cnt, 3); // convert to number of bytes
6818 rep_stosb();
6819 } else {
6820 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
6821 rep_stos();
6822 }
6823
6824 BIND(DONE);
6825 }
6826
6827 #ifdef COMPILER2
6828
6829 // IndexOf for constant substrings with size >= 8 chars
6830 // which don't need to be loaded through stack.
6831 void MacroAssembler::string_indexofC8(Register str1, Register str2,
6832 Register cnt1, Register cnt2,
6833 int int_cnt2, Register result,
6834 XMMRegister vec, Register tmp,
6835 int ae) {
6836 ShortBranchVerifier sbv(this);
6837 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
6838 assert(ae != StrIntrinsicNode::LU, "Invalid encoding");
6839
6840 // This method uses the pcmpestri instruction with bound registers
6841 // inputs:
6842 // xmm - substring
6843 // rax - substring length (elements count)
6844 // mem - scanned string
6845 // rdx - string length (elements count)
6846 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
6847 // 0xc - mode: 1100 (substring search) + 00 (unsigned bytes)
6848 // outputs:
6849 // rcx - matched index in string
6850 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
6851 int mode = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts
6852 int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8
6853 Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2;
6854 Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1;
6855
6856 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR,
6857 RET_FOUND, RET_NOT_FOUND, EXIT, FOUND_SUBSTR,
6858 MATCH_SUBSTR_HEAD, RELOAD_STR, FOUND_CANDIDATE;
6859
6860 // Note, inline_string_indexOf() generates checks:
6861 // if (substr.count > string.count) return -1;
6862 // if (substr.count == 0) return 0;
6863 assert(int_cnt2 >= stride, "this code is used only for cnt2 >= 8 chars");
6864
6865 // Load substring.
6866 if (ae == StrIntrinsicNode::UL) {
6867 pmovzxbw(vec, Address(str2, 0));
6868 } else {
6869 movdqu(vec, Address(str2, 0));
6870 }
6871 movl(cnt2, int_cnt2);
6872 movptr(result, str1); // string addr
6873
6874 if (int_cnt2 > stride) {
6875 jmpb(SCAN_TO_SUBSTR);
6876
6877 // Reload substr for rescan, this code
6878 // is executed only for large substrings (> 8 chars)
6879 bind(RELOAD_SUBSTR);
6880 if (ae == StrIntrinsicNode::UL) {
6881 pmovzxbw(vec, Address(str2, 0));
6882 } else {
6883 movdqu(vec, Address(str2, 0));
6884 }
6885 negptr(cnt2); // Jumped here with negative cnt2, convert to positive
6886
6887 bind(RELOAD_STR);
6888 // We came here after the beginning of the substring was
6889 // matched but the rest of it was not so we need to search
6890 // again. Start from the next element after the previous match.
6891
6892 // cnt2 is number of substring reminding elements and
6893 // cnt1 is number of string reminding elements when cmp failed.
6894 // Restored cnt1 = cnt1 - cnt2 + int_cnt2
6895 subl(cnt1, cnt2);
6896 addl(cnt1, int_cnt2);
6897 movl(cnt2, int_cnt2); // Now restore cnt2
6898
6899 decrementl(cnt1); // Shift to next element
6900 cmpl(cnt1, cnt2);
6901 jcc(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6902
6903 addptr(result, (1<<scale1));
6904
6905 } // (int_cnt2 > 8)
6906
6907 // Scan string for start of substr in 16-byte vectors
6908 bind(SCAN_TO_SUBSTR);
6909 pcmpestri(vec, Address(result, 0), mode);
6910 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
6911 subl(cnt1, stride);
6912 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
6913 cmpl(cnt1, cnt2);
6914 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6915 addptr(result, 16);
6916 jmpb(SCAN_TO_SUBSTR);
6917
6918 // Found a potential substr
6919 bind(FOUND_CANDIDATE);
6920 // Matched whole vector if first element matched (tmp(rcx) == 0).
6921 if (int_cnt2 == stride) {
6922 jccb(Assembler::overflow, RET_FOUND); // OF == 1
6923 } else { // int_cnt2 > 8
6924 jccb(Assembler::overflow, FOUND_SUBSTR);
6925 }
6926 // After pcmpestri tmp(rcx) contains matched element index
6927 // Compute start addr of substr
6928 lea(result, Address(result, tmp, scale1));
6929
6930 // Make sure string is still long enough
6931 subl(cnt1, tmp);
6932 cmpl(cnt1, cnt2);
6933 if (int_cnt2 == stride) {
6934 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
6935 } else { // int_cnt2 > 8
6936 jccb(Assembler::greaterEqual, MATCH_SUBSTR_HEAD);
6937 }
6938 // Left less then substring.
6939
6940 bind(RET_NOT_FOUND);
6941 movl(result, -1);
6942 jmp(EXIT);
6943
6944 if (int_cnt2 > stride) {
6945 // This code is optimized for the case when whole substring
6946 // is matched if its head is matched.
6947 bind(MATCH_SUBSTR_HEAD);
6948 pcmpestri(vec, Address(result, 0), mode);
6949 // Reload only string if does not match
6950 jcc(Assembler::noOverflow, RELOAD_STR); // OF == 0
6951
6952 Label CONT_SCAN_SUBSTR;
6953 // Compare the rest of substring (> 8 chars).
6954 bind(FOUND_SUBSTR);
6955 // First 8 chars are already matched.
6956 negptr(cnt2);
6957 addptr(cnt2, stride);
6958
6959 bind(SCAN_SUBSTR);
6960 subl(cnt1, stride);
6961 cmpl(cnt2, -stride); // Do not read beyond substring
6962 jccb(Assembler::lessEqual, CONT_SCAN_SUBSTR);
6963 // Back-up strings to avoid reading beyond substring:
6964 // cnt1 = cnt1 - cnt2 + 8
6965 addl(cnt1, cnt2); // cnt2 is negative
6966 addl(cnt1, stride);
6967 movl(cnt2, stride); negptr(cnt2);
6968 bind(CONT_SCAN_SUBSTR);
6969 if (int_cnt2 < (int)G) {
6970 int tail_off1 = int_cnt2<<scale1;
6971 int tail_off2 = int_cnt2<<scale2;
6972 if (ae == StrIntrinsicNode::UL) {
6973 pmovzxbw(vec, Address(str2, cnt2, scale2, tail_off2));
6974 } else {
6975 movdqu(vec, Address(str2, cnt2, scale2, tail_off2));
6976 }
6977 pcmpestri(vec, Address(result, cnt2, scale1, tail_off1), mode);
6978 } else {
6979 // calculate index in register to avoid integer overflow (int_cnt2*2)
6980 movl(tmp, int_cnt2);
6981 addptr(tmp, cnt2);
6982 if (ae == StrIntrinsicNode::UL) {
6983 pmovzxbw(vec, Address(str2, tmp, scale2, 0));
6984 } else {
6985 movdqu(vec, Address(str2, tmp, scale2, 0));
6986 }
6987 pcmpestri(vec, Address(result, tmp, scale1, 0), mode);
6988 }
6989 // Need to reload strings pointers if not matched whole vector
6990 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
6991 addptr(cnt2, stride);
6992 jcc(Assembler::negative, SCAN_SUBSTR);
6993 // Fall through if found full substring
6994
6995 } // (int_cnt2 > 8)
6996
6997 bind(RET_FOUND);
6998 // Found result if we matched full small substring.
6999 // Compute substr offset
7000 subptr(result, str1);
7001 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
7002 shrl(result, 1); // index
7003 }
7004 bind(EXIT);
7005
7006 } // string_indexofC8
7007
7008 // Small strings are loaded through stack if they cross page boundary.
7009 void MacroAssembler::string_indexof(Register str1, Register str2,
7010 Register cnt1, Register cnt2,
7011 int int_cnt2, Register result,
7012 XMMRegister vec, Register tmp,
7013 int ae) {
7014 ShortBranchVerifier sbv(this);
7015 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
7016 assert(ae != StrIntrinsicNode::LU, "Invalid encoding");
7017
7018 //
7019 // int_cnt2 is length of small (< 8 chars) constant substring
7020 // or (-1) for non constant substring in which case its length
7021 // is in cnt2 register.
7022 //
7023 // Note, inline_string_indexOf() generates checks:
7024 // if (substr.count > string.count) return -1;
7025 // if (substr.count == 0) return 0;
7026 //
7027 int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8
7028 assert(int_cnt2 == -1 || (0 < int_cnt2 && int_cnt2 < stride), "should be != 0");
7029 // This method uses the pcmpestri instruction with bound registers
7030 // inputs:
7031 // xmm - substring
7032 // rax - substring length (elements count)
7033 // mem - scanned string
7034 // rdx - string length (elements count)
7035 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
7036 // 0xc - mode: 1100 (substring search) + 00 (unsigned bytes)
7037 // outputs:
7038 // rcx - matched index in string
7039 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
7040 int mode = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts
7041 Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2;
7042 Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1;
7043
7044 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, ADJUST_STR,
7045 RET_FOUND, RET_NOT_FOUND, CLEANUP, FOUND_SUBSTR,
7046 FOUND_CANDIDATE;
7047
7048 { //========================================================
7049 // We don't know where these strings are located
7050 // and we can't read beyond them. Load them through stack.
7051 Label BIG_STRINGS, CHECK_STR, COPY_SUBSTR, COPY_STR;
7052
7053 movptr(tmp, rsp); // save old SP
7054
7055 if (int_cnt2 > 0) { // small (< 8 chars) constant substring
7056 if (int_cnt2 == (1>>scale2)) { // One byte
7057 assert((ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL), "Only possible for latin1 encoding");
7058 load_unsigned_byte(result, Address(str2, 0));
7059 movdl(vec, result); // move 32 bits
7060 } else if (ae == StrIntrinsicNode::LL && int_cnt2 == 3) { // Three bytes
7061 // Not enough header space in 32-bit VM: 12+3 = 15.
7062 movl(result, Address(str2, -1));
7063 shrl(result, 8);
7064 movdl(vec, result); // move 32 bits
7065 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (2>>scale2)) { // One char
7066 load_unsigned_short(result, Address(str2, 0));
7067 movdl(vec, result); // move 32 bits
7068 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (4>>scale2)) { // Two chars
7069 movdl(vec, Address(str2, 0)); // move 32 bits
7070 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (8>>scale2)) { // Four chars
7071 movq(vec, Address(str2, 0)); // move 64 bits
7072 } else { // cnt2 = { 3, 5, 6, 7 } || (ae == StrIntrinsicNode::UL && cnt2 ={2, ..., 7})
7073 // Array header size is 12 bytes in 32-bit VM
7074 // + 6 bytes for 3 chars == 18 bytes,
7075 // enough space to load vec and shift.
7076 assert(HeapWordSize*TypeArrayKlass::header_size() >= 12,"sanity");
7077 if (ae == StrIntrinsicNode::UL) {
7078 int tail_off = int_cnt2-8;
7079 pmovzxbw(vec, Address(str2, tail_off));
7080 psrldq(vec, -2*tail_off);
7081 }
7082 else {
7083 int tail_off = int_cnt2*(1<<scale2);
7084 movdqu(vec, Address(str2, tail_off-16));
7085 psrldq(vec, 16-tail_off);
7086 }
7087 }
7088 } else { // not constant substring
7089 cmpl(cnt2, stride);
7090 jccb(Assembler::aboveEqual, BIG_STRINGS); // Both strings are big enough
7091
7092 // We can read beyond string if srt+16 does not cross page boundary
7093 // since heaps are aligned and mapped by pages.
7094 assert(os::vm_page_size() < (int)G, "default page should be small");
7095 movl(result, str2); // We need only low 32 bits
7096 andl(result, (os::vm_page_size()-1));
7097 cmpl(result, (os::vm_page_size()-16));
7098 jccb(Assembler::belowEqual, CHECK_STR);
7099
7100 // Move small strings to stack to allow load 16 bytes into vec.
7101 subptr(rsp, 16);
7102 int stk_offset = wordSize-(1<<scale2);
7103 push(cnt2);
7104
7105 bind(COPY_SUBSTR);
7106 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL) {
7107 load_unsigned_byte(result, Address(str2, cnt2, scale2, -1));
7108 movb(Address(rsp, cnt2, scale2, stk_offset), result);
7109 } else if (ae == StrIntrinsicNode::UU) {
7110 load_unsigned_short(result, Address(str2, cnt2, scale2, -2));
7111 movw(Address(rsp, cnt2, scale2, stk_offset), result);
7112 }
7113 decrement(cnt2);
7114 jccb(Assembler::notZero, COPY_SUBSTR);
7115
7116 pop(cnt2);
7117 movptr(str2, rsp); // New substring address
7118 } // non constant
7119
7120 bind(CHECK_STR);
7121 cmpl(cnt1, stride);
7122 jccb(Assembler::aboveEqual, BIG_STRINGS);
7123
7124 // Check cross page boundary.
7125 movl(result, str1); // We need only low 32 bits
7126 andl(result, (os::vm_page_size()-1));
7127 cmpl(result, (os::vm_page_size()-16));
7128 jccb(Assembler::belowEqual, BIG_STRINGS);
7129
7130 subptr(rsp, 16);
7131 int stk_offset = -(1<<scale1);
7132 if (int_cnt2 < 0) { // not constant
7133 push(cnt2);
7134 stk_offset += wordSize;
7135 }
7136 movl(cnt2, cnt1);
7137
7138 bind(COPY_STR);
7139 if (ae == StrIntrinsicNode::LL) {
7140 load_unsigned_byte(result, Address(str1, cnt2, scale1, -1));
7141 movb(Address(rsp, cnt2, scale1, stk_offset), result);
7142 } else {
7143 load_unsigned_short(result, Address(str1, cnt2, scale1, -2));
7144 movw(Address(rsp, cnt2, scale1, stk_offset), result);
7145 }
7146 decrement(cnt2);
7147 jccb(Assembler::notZero, COPY_STR);
7148
7149 if (int_cnt2 < 0) { // not constant
7150 pop(cnt2);
7151 }
7152 movptr(str1, rsp); // New string address
7153
7154 bind(BIG_STRINGS);
7155 // Load substring.
7156 if (int_cnt2 < 0) { // -1
7157 if (ae == StrIntrinsicNode::UL) {
7158 pmovzxbw(vec, Address(str2, 0));
7159 } else {
7160 movdqu(vec, Address(str2, 0));
7161 }
7162 push(cnt2); // substr count
7163 push(str2); // substr addr
7164 push(str1); // string addr
7165 } else {
7166 // Small (< 8 chars) constant substrings are loaded already.
7167 movl(cnt2, int_cnt2);
7168 }
7169 push(tmp); // original SP
7170
7171 } // Finished loading
7172
7173 //========================================================
7174 // Start search
7175 //
7176
7177 movptr(result, str1); // string addr
7178
7179 if (int_cnt2 < 0) { // Only for non constant substring
7180 jmpb(SCAN_TO_SUBSTR);
7181
7182 // SP saved at sp+0
7183 // String saved at sp+1*wordSize
7184 // Substr saved at sp+2*wordSize
7185 // Substr count saved at sp+3*wordSize
7186
7187 // Reload substr for rescan, this code
7188 // is executed only for large substrings (> 8 chars)
7189 bind(RELOAD_SUBSTR);
7190 movptr(str2, Address(rsp, 2*wordSize));
7191 movl(cnt2, Address(rsp, 3*wordSize));
7192 if (ae == StrIntrinsicNode::UL) {
7193 pmovzxbw(vec, Address(str2, 0));
7194 } else {
7195 movdqu(vec, Address(str2, 0));
7196 }
7197 // We came here after the beginning of the substring was
7198 // matched but the rest of it was not so we need to search
7199 // again. Start from the next element after the previous match.
7200 subptr(str1, result); // Restore counter
7201 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
7202 shrl(str1, 1);
7203 }
7204 addl(cnt1, str1);
7205 decrementl(cnt1); // Shift to next element
7206 cmpl(cnt1, cnt2);
7207 jcc(Assembler::negative, RET_NOT_FOUND); // Left less then substring
7208
7209 addptr(result, (1<<scale1));
7210 } // non constant
7211
7212 // Scan string for start of substr in 16-byte vectors
7213 bind(SCAN_TO_SUBSTR);
7214 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
7215 pcmpestri(vec, Address(result, 0), mode);
7216 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
7217 subl(cnt1, stride);
7218 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
7219 cmpl(cnt1, cnt2);
7220 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
7221 addptr(result, 16);
7222
7223 bind(ADJUST_STR);
7224 cmpl(cnt1, stride); // Do not read beyond string
7225 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
7226 // Back-up string to avoid reading beyond string.
7227 lea(result, Address(result, cnt1, scale1, -16));
7228 movl(cnt1, stride);
7229 jmpb(SCAN_TO_SUBSTR);
7230
7231 // Found a potential substr
7232 bind(FOUND_CANDIDATE);
7233 // After pcmpestri tmp(rcx) contains matched element index
7234
7235 // Make sure string is still long enough
7236 subl(cnt1, tmp);
7237 cmpl(cnt1, cnt2);
7238 jccb(Assembler::greaterEqual, FOUND_SUBSTR);
7239 // Left less then substring.
7240
7241 bind(RET_NOT_FOUND);
7242 movl(result, -1);
7243 jmpb(CLEANUP);
7244
7245 bind(FOUND_SUBSTR);
7246 // Compute start addr of substr
7247 lea(result, Address(result, tmp, scale1));
7248 if (int_cnt2 > 0) { // Constant substring
7249 // Repeat search for small substring (< 8 chars)
7250 // from new point without reloading substring.
7251 // Have to check that we don't read beyond string.
7252 cmpl(tmp, stride-int_cnt2);
7253 jccb(Assembler::greater, ADJUST_STR);
7254 // Fall through if matched whole substring.
7255 } else { // non constant
7256 assert(int_cnt2 == -1, "should be != 0");
7257
7258 addl(tmp, cnt2);
7259 // Found result if we matched whole substring.
7260 cmpl(tmp, stride);
7261 jccb(Assembler::lessEqual, RET_FOUND);
7262
7263 // Repeat search for small substring (<= 8 chars)
7264 // from new point 'str1' without reloading substring.
7265 cmpl(cnt2, stride);
7266 // Have to check that we don't read beyond string.
7267 jccb(Assembler::lessEqual, ADJUST_STR);
7268
7269 Label CHECK_NEXT, CONT_SCAN_SUBSTR, RET_FOUND_LONG;
7270 // Compare the rest of substring (> 8 chars).
7271 movptr(str1, result);
7272
7273 cmpl(tmp, cnt2);
7274 // First 8 chars are already matched.
7275 jccb(Assembler::equal, CHECK_NEXT);
7276
7277 bind(SCAN_SUBSTR);
7278 pcmpestri(vec, Address(str1, 0), mode);
7279 // Need to reload strings pointers if not matched whole vector
7280 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
7281
7282 bind(CHECK_NEXT);
7283 subl(cnt2, stride);
7284 jccb(Assembler::lessEqual, RET_FOUND_LONG); // Found full substring
7285 addptr(str1, 16);
7286 if (ae == StrIntrinsicNode::UL) {
7287 addptr(str2, 8);
7288 } else {
7289 addptr(str2, 16);
7290 }
7291 subl(cnt1, stride);
7292 cmpl(cnt2, stride); // Do not read beyond substring
7293 jccb(Assembler::greaterEqual, CONT_SCAN_SUBSTR);
7294 // Back-up strings to avoid reading beyond substring.
7295
7296 if (ae == StrIntrinsicNode::UL) {
7297 lea(str2, Address(str2, cnt2, scale2, -8));
7298 lea(str1, Address(str1, cnt2, scale1, -16));
7299 } else {
7300 lea(str2, Address(str2, cnt2, scale2, -16));
7301 lea(str1, Address(str1, cnt2, scale1, -16));
7302 }
7303 subl(cnt1, cnt2);
7304 movl(cnt2, stride);
7305 addl(cnt1, stride);
7306 bind(CONT_SCAN_SUBSTR);
7307 if (ae == StrIntrinsicNode::UL) {
7308 pmovzxbw(vec, Address(str2, 0));
7309 } else {
7310 movdqu(vec, Address(str2, 0));
7311 }
7312 jmp(SCAN_SUBSTR);
7313
7314 bind(RET_FOUND_LONG);
7315 movptr(str1, Address(rsp, wordSize));
7316 } // non constant
7317
7318 bind(RET_FOUND);
7319 // Compute substr offset
7320 subptr(result, str1);
7321 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
7322 shrl(result, 1); // index
7323 }
7324 bind(CLEANUP);
7325 pop(rsp); // restore SP
7326
7327 } // string_indexof
7328
7329 void MacroAssembler::string_indexof_char(Register str1, Register cnt1, Register ch, Register result,
7330 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp) {
7331 ShortBranchVerifier sbv(this);
7332 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
7333
7334 int stride = 8;
7335
7336 Label FOUND_CHAR, SCAN_TO_CHAR, SCAN_TO_CHAR_LOOP,
7337 SCAN_TO_8_CHAR, SCAN_TO_8_CHAR_LOOP, SCAN_TO_16_CHAR_LOOP,
7338 RET_NOT_FOUND, SCAN_TO_8_CHAR_INIT,
7339 FOUND_SEQ_CHAR, DONE_LABEL;
7340
7341 movptr(result, str1);
7342 if (UseAVX >= 2) {
7343 cmpl(cnt1, stride);
7344 jcc(Assembler::less, SCAN_TO_CHAR_LOOP);
7345 cmpl(cnt1, 2*stride);
7346 jcc(Assembler::less, SCAN_TO_8_CHAR_INIT);
7347 movdl(vec1, ch);
7348 vpbroadcastw(vec1, vec1);
7349 vpxor(vec2, vec2);
7350 movl(tmp, cnt1);
7351 andl(tmp, 0xFFFFFFF0); //vector count (in chars)
7352 andl(cnt1,0x0000000F); //tail count (in chars)
7353
7354 bind(SCAN_TO_16_CHAR_LOOP);
7355 vmovdqu(vec3, Address(result, 0));
7356 vpcmpeqw(vec3, vec3, vec1, 1);
7357 vptest(vec2, vec3);
7358 jcc(Assembler::carryClear, FOUND_CHAR);
7359 addptr(result, 32);
7360 subl(tmp, 2*stride);
7361 jccb(Assembler::notZero, SCAN_TO_16_CHAR_LOOP);
7362 jmp(SCAN_TO_8_CHAR);
7363 bind(SCAN_TO_8_CHAR_INIT);
7364 movdl(vec1, ch);
7365 pshuflw(vec1, vec1, 0x00);
7366 pshufd(vec1, vec1, 0);
7367 pxor(vec2, vec2);
7368 }
7369 bind(SCAN_TO_8_CHAR);
7370 cmpl(cnt1, stride);
7371 if (UseAVX >= 2) {
7372 jcc(Assembler::less, SCAN_TO_CHAR);
7373 } else {
7374 jcc(Assembler::less, SCAN_TO_CHAR_LOOP);
7375 movdl(vec1, ch);
7376 pshuflw(vec1, vec1, 0x00);
7377 pshufd(vec1, vec1, 0);
7378 pxor(vec2, vec2);
7379 }
7380 movl(tmp, cnt1);
7381 andl(tmp, 0xFFFFFFF8); //vector count (in chars)
7382 andl(cnt1,0x00000007); //tail count (in chars)
7383
7384 bind(SCAN_TO_8_CHAR_LOOP);
7385 movdqu(vec3, Address(result, 0));
7386 pcmpeqw(vec3, vec1);
7387 ptest(vec2, vec3);
7388 jcc(Assembler::carryClear, FOUND_CHAR);
7389 addptr(result, 16);
7390 subl(tmp, stride);
7391 jccb(Assembler::notZero, SCAN_TO_8_CHAR_LOOP);
7392 bind(SCAN_TO_CHAR);
7393 testl(cnt1, cnt1);
7394 jcc(Assembler::zero, RET_NOT_FOUND);
7395 bind(SCAN_TO_CHAR_LOOP);
7396 load_unsigned_short(tmp, Address(result, 0));
7397 cmpl(ch, tmp);
7398 jccb(Assembler::equal, FOUND_SEQ_CHAR);
7399 addptr(result, 2);
7400 subl(cnt1, 1);
7401 jccb(Assembler::zero, RET_NOT_FOUND);
7402 jmp(SCAN_TO_CHAR_LOOP);
7403
7404 bind(RET_NOT_FOUND);
7405 movl(result, -1);
7406 jmpb(DONE_LABEL);
7407
7408 bind(FOUND_CHAR);
7409 if (UseAVX >= 2) {
7410 vpmovmskb(tmp, vec3);
7411 } else {
7412 pmovmskb(tmp, vec3);
7413 }
7414 bsfl(ch, tmp);
7415 addl(result, ch);
7416
7417 bind(FOUND_SEQ_CHAR);
7418 subptr(result, str1);
7419 shrl(result, 1);
7420
7421 bind(DONE_LABEL);
7422 } // string_indexof_char
7423
7424 // helper function for string_compare
7425 void MacroAssembler::load_next_elements(Register elem1, Register elem2, Register str1, Register str2,
7426 Address::ScaleFactor scale, Address::ScaleFactor scale1,
7427 Address::ScaleFactor scale2, Register index, int ae) {
7428 if (ae == StrIntrinsicNode::LL) {
7429 load_unsigned_byte(elem1, Address(str1, index, scale, 0));
7430 load_unsigned_byte(elem2, Address(str2, index, scale, 0));
7431 } else if (ae == StrIntrinsicNode::UU) {
7432 load_unsigned_short(elem1, Address(str1, index, scale, 0));
7433 load_unsigned_short(elem2, Address(str2, index, scale, 0));
7434 } else {
7435 load_unsigned_byte(elem1, Address(str1, index, scale1, 0));
7436 load_unsigned_short(elem2, Address(str2, index, scale2, 0));
7437 }
7438 }
7439
7440 // Compare strings, used for char[] and byte[].
7441 void MacroAssembler::string_compare(Register str1, Register str2,
7442 Register cnt1, Register cnt2, Register result,
7443 XMMRegister vec1, int ae) {
7444 ShortBranchVerifier sbv(this);
7445 Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL;
7446 Label COMPARE_WIDE_VECTORS_LOOP_FAILED; // used only _LP64 && AVX3
7447 int stride, stride2, adr_stride, adr_stride1, adr_stride2;
7448 int stride2x2 = 0x40;
7449 Address::ScaleFactor scale = Address::no_scale;
7450 Address::ScaleFactor scale1 = Address::no_scale;
7451 Address::ScaleFactor scale2 = Address::no_scale;
7452
7453 if (ae != StrIntrinsicNode::LL) {
7454 stride2x2 = 0x20;
7455 }
7456
7457 if (ae == StrIntrinsicNode::LU || ae == StrIntrinsicNode::UL) {
7458 shrl(cnt2, 1);
7459 }
7460 // Compute the minimum of the string lengths and the
7461 // difference of the string lengths (stack).
7462 // Do the conditional move stuff
7463 movl(result, cnt1);
7464 subl(cnt1, cnt2);
7465 push(cnt1);
7466 cmov32(Assembler::lessEqual, cnt2, result); // cnt2 = min(cnt1, cnt2)
7467
7468 // Is the minimum length zero?
7469 testl(cnt2, cnt2);
7470 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
7471 if (ae == StrIntrinsicNode::LL) {
7472 // Load first bytes
7473 load_unsigned_byte(result, Address(str1, 0)); // result = str1[0]
7474 load_unsigned_byte(cnt1, Address(str2, 0)); // cnt1 = str2[0]
7475 } else if (ae == StrIntrinsicNode::UU) {
7476 // Load first characters
7477 load_unsigned_short(result, Address(str1, 0));
7478 load_unsigned_short(cnt1, Address(str2, 0));
7479 } else {
7480 load_unsigned_byte(result, Address(str1, 0));
7481 load_unsigned_short(cnt1, Address(str2, 0));
7482 }
7483 subl(result, cnt1);
7484 jcc(Assembler::notZero, POP_LABEL);
7485
7486 if (ae == StrIntrinsicNode::UU) {
7487 // Divide length by 2 to get number of chars
7488 shrl(cnt2, 1);
7489 }
7490 cmpl(cnt2, 1);
7491 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
7492
7493 // Check if the strings start at the same location and setup scale and stride
7494 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7495 cmpptr(str1, str2);
7496 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
7497 if (ae == StrIntrinsicNode::LL) {
7498 scale = Address::times_1;
7499 stride = 16;
7500 } else {
7501 scale = Address::times_2;
7502 stride = 8;
7503 }
7504 } else {
7505 scale1 = Address::times_1;
7506 scale2 = Address::times_2;
7507 // scale not used
7508 stride = 8;
7509 }
7510
7511 if (UseAVX >= 2 && UseSSE42Intrinsics) {
7512 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_WIDE_TAIL, COMPARE_SMALL_STR;
7513 Label COMPARE_WIDE_VECTORS_LOOP, COMPARE_16_CHARS, COMPARE_INDEX_CHAR;
7514 Label COMPARE_WIDE_VECTORS_LOOP_AVX2;
7515 Label COMPARE_TAIL_LONG;
7516 Label COMPARE_WIDE_VECTORS_LOOP_AVX3; // used only _LP64 && AVX3
7517
7518 int pcmpmask = 0x19;
7519 if (ae == StrIntrinsicNode::LL) {
7520 pcmpmask &= ~0x01;
7521 }
7522
7523 // Setup to compare 16-chars (32-bytes) vectors,
7524 // start from first character again because it has aligned address.
7525 if (ae == StrIntrinsicNode::LL) {
7526 stride2 = 32;
7527 } else {
7528 stride2 = 16;
7529 }
7530 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7531 adr_stride = stride << scale;
7532 } else {
7533 adr_stride1 = 8; //stride << scale1;
7534 adr_stride2 = 16; //stride << scale2;
7535 }
7536
7537 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
7538 // rax and rdx are used by pcmpestri as elements counters
7539 movl(result, cnt2);
7540 andl(cnt2, ~(stride2-1)); // cnt2 holds the vector count
7541 jcc(Assembler::zero, COMPARE_TAIL_LONG);
7542
7543 // fast path : compare first 2 8-char vectors.
7544 bind(COMPARE_16_CHARS);
7545 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7546 movdqu(vec1, Address(str1, 0));
7547 } else {
7548 pmovzxbw(vec1, Address(str1, 0));
7549 }
7550 pcmpestri(vec1, Address(str2, 0), pcmpmask);
7551 jccb(Assembler::below, COMPARE_INDEX_CHAR);
7552
7553 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7554 movdqu(vec1, Address(str1, adr_stride));
7555 pcmpestri(vec1, Address(str2, adr_stride), pcmpmask);
7556 } else {
7557 pmovzxbw(vec1, Address(str1, adr_stride1));
7558 pcmpestri(vec1, Address(str2, adr_stride2), pcmpmask);
7559 }
7560 jccb(Assembler::aboveEqual, COMPARE_WIDE_VECTORS);
7561 addl(cnt1, stride);
7562
7563 // Compare the characters at index in cnt1
7564 bind(COMPARE_INDEX_CHAR); // cnt1 has the offset of the mismatching character
7565 load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae);
7566 subl(result, cnt2);
7567 jmp(POP_LABEL);
7568
7569 // Setup the registers to start vector comparison loop
7570 bind(COMPARE_WIDE_VECTORS);
7571 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7572 lea(str1, Address(str1, result, scale));
7573 lea(str2, Address(str2, result, scale));
7574 } else {
7575 lea(str1, Address(str1, result, scale1));
7576 lea(str2, Address(str2, result, scale2));
7577 }
7578 subl(result, stride2);
7579 subl(cnt2, stride2);
7580 jcc(Assembler::zero, COMPARE_WIDE_TAIL);
7581 negptr(result);
7582
7583 // In a loop, compare 16-chars (32-bytes) at once using (vpxor+vptest)
7584 bind(COMPARE_WIDE_VECTORS_LOOP);
7585
7586 #ifdef _LP64
7587 if (VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop
7588 cmpl(cnt2, stride2x2);
7589 jccb(Assembler::below, COMPARE_WIDE_VECTORS_LOOP_AVX2);
7590 testl(cnt2, stride2x2-1); // cnt2 holds the vector count
7591 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX2); // means we cannot subtract by 0x40
7592
7593 bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop
7594 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7595 evmovdquq(vec1, Address(str1, result, scale), Assembler::AVX_512bit);
7596 evpcmpeqb(k7, vec1, Address(str2, result, scale), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0
7597 } else {
7598 vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_512bit);
7599 evpcmpeqb(k7, vec1, Address(str2, result, scale2), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0
7600 }
7601 kortestql(k7, k7);
7602 jcc(Assembler::aboveEqual, COMPARE_WIDE_VECTORS_LOOP_FAILED); // miscompare
7603 addptr(result, stride2x2); // update since we already compared at this addr
7604 subl(cnt2, stride2x2); // and sub the size too
7605 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX3);
7606
7607 vpxor(vec1, vec1);
7608 jmpb(COMPARE_WIDE_TAIL);
7609 }//if (VM_Version::supports_avx512vlbw())
7610 #endif // _LP64
7611
7612
7613 bind(COMPARE_WIDE_VECTORS_LOOP_AVX2);
7614 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7615 vmovdqu(vec1, Address(str1, result, scale));
7616 vpxor(vec1, Address(str2, result, scale));
7617 } else {
7618 vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_256bit);
7619 vpxor(vec1, Address(str2, result, scale2));
7620 }
7621 vptest(vec1, vec1);
7622 jcc(Assembler::notZero, VECTOR_NOT_EQUAL);
7623 addptr(result, stride2);
7624 subl(cnt2, stride2);
7625 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP);
7626 // clean upper bits of YMM registers
7627 vpxor(vec1, vec1);
7628
7629 // compare wide vectors tail
7630 bind(COMPARE_WIDE_TAIL);
7631 testptr(result, result);
7632 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
7633
7634 movl(result, stride2);
7635 movl(cnt2, result);
7636 negptr(result);
7637 jmp(COMPARE_WIDE_VECTORS_LOOP_AVX2);
7638
7639 // Identifies the mismatching (higher or lower)16-bytes in the 32-byte vectors.
7640 bind(VECTOR_NOT_EQUAL);
7641 // clean upper bits of YMM registers
7642 vpxor(vec1, vec1);
7643 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7644 lea(str1, Address(str1, result, scale));
7645 lea(str2, Address(str2, result, scale));
7646 } else {
7647 lea(str1, Address(str1, result, scale1));
7648 lea(str2, Address(str2, result, scale2));
7649 }
7650 jmp(COMPARE_16_CHARS);
7651
7652 // Compare tail chars, length between 1 to 15 chars
7653 bind(COMPARE_TAIL_LONG);
7654 movl(cnt2, result);
7655 cmpl(cnt2, stride);
7656 jcc(Assembler::less, COMPARE_SMALL_STR);
7657
7658 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7659 movdqu(vec1, Address(str1, 0));
7660 } else {
7661 pmovzxbw(vec1, Address(str1, 0));
7662 }
7663 pcmpestri(vec1, Address(str2, 0), pcmpmask);
7664 jcc(Assembler::below, COMPARE_INDEX_CHAR);
7665 subptr(cnt2, stride);
7666 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
7667 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7668 lea(str1, Address(str1, result, scale));
7669 lea(str2, Address(str2, result, scale));
7670 } else {
7671 lea(str1, Address(str1, result, scale1));
7672 lea(str2, Address(str2, result, scale2));
7673 }
7674 negptr(cnt2);
7675 jmpb(WHILE_HEAD_LABEL);
7676
7677 bind(COMPARE_SMALL_STR);
7678 } else if (UseSSE42Intrinsics) {
7679 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL;
7680 int pcmpmask = 0x19;
7681 // Setup to compare 8-char (16-byte) vectors,
7682 // start from first character again because it has aligned address.
7683 movl(result, cnt2);
7684 andl(cnt2, ~(stride - 1)); // cnt2 holds the vector count
7685 if (ae == StrIntrinsicNode::LL) {
7686 pcmpmask &= ~0x01;
7687 }
7688 jcc(Assembler::zero, COMPARE_TAIL);
7689 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7690 lea(str1, Address(str1, result, scale));
7691 lea(str2, Address(str2, result, scale));
7692 } else {
7693 lea(str1, Address(str1, result, scale1));
7694 lea(str2, Address(str2, result, scale2));
7695 }
7696 negptr(result);
7697
7698 // pcmpestri
7699 // inputs:
7700 // vec1- substring
7701 // rax - negative string length (elements count)
7702 // mem - scanned string
7703 // rdx - string length (elements count)
7704 // pcmpmask - cmp mode: 11000 (string compare with negated result)
7705 // + 00 (unsigned bytes) or + 01 (unsigned shorts)
7706 // outputs:
7707 // rcx - first mismatched element index
7708 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
7709
7710 bind(COMPARE_WIDE_VECTORS);
7711 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7712 movdqu(vec1, Address(str1, result, scale));
7713 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
7714 } else {
7715 pmovzxbw(vec1, Address(str1, result, scale1));
7716 pcmpestri(vec1, Address(str2, result, scale2), pcmpmask);
7717 }
7718 // After pcmpestri cnt1(rcx) contains mismatched element index
7719
7720 jccb(Assembler::below, VECTOR_NOT_EQUAL); // CF==1
7721 addptr(result, stride);
7722 subptr(cnt2, stride);
7723 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS);
7724
7725 // compare wide vectors tail
7726 testptr(result, result);
7727 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
7728
7729 movl(cnt2, stride);
7730 movl(result, stride);
7731 negptr(result);
7732 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7733 movdqu(vec1, Address(str1, result, scale));
7734 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
7735 } else {
7736 pmovzxbw(vec1, Address(str1, result, scale1));
7737 pcmpestri(vec1, Address(str2, result, scale2), pcmpmask);
7738 }
7739 jccb(Assembler::aboveEqual, LENGTH_DIFF_LABEL);
7740
7741 // Mismatched characters in the vectors
7742 bind(VECTOR_NOT_EQUAL);
7743 addptr(cnt1, result);
7744 load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae);
7745 subl(result, cnt2);
7746 jmpb(POP_LABEL);
7747
7748 bind(COMPARE_TAIL); // limit is zero
7749 movl(cnt2, result);
7750 // Fallthru to tail compare
7751 }
7752 // Shift str2 and str1 to the end of the arrays, negate min
7753 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7754 lea(str1, Address(str1, cnt2, scale));
7755 lea(str2, Address(str2, cnt2, scale));
7756 } else {
7757 lea(str1, Address(str1, cnt2, scale1));
7758 lea(str2, Address(str2, cnt2, scale2));
7759 }
7760 decrementl(cnt2); // first character was compared already
7761 negptr(cnt2);
7762
7763 // Compare the rest of the elements
7764 bind(WHILE_HEAD_LABEL);
7765 load_next_elements(result, cnt1, str1, str2, scale, scale1, scale2, cnt2, ae);
7766 subl(result, cnt1);
7767 jccb(Assembler::notZero, POP_LABEL);
7768 increment(cnt2);
7769 jccb(Assembler::notZero, WHILE_HEAD_LABEL);
7770
7771 // Strings are equal up to min length. Return the length difference.
7772 bind(LENGTH_DIFF_LABEL);
7773 pop(result);
7774 if (ae == StrIntrinsicNode::UU) {
7775 // Divide diff by 2 to get number of chars
7776 sarl(result, 1);
7777 }
7778 jmpb(DONE_LABEL);
7779
7780 #ifdef _LP64
7781 if (VM_Version::supports_avx512vlbw()) {
7782
7783 bind(COMPARE_WIDE_VECTORS_LOOP_FAILED);
7784
7785 kmovql(cnt1, k7);
7786 notq(cnt1);
7787 bsfq(cnt2, cnt1);
7788 if (ae != StrIntrinsicNode::LL) {
7789 // Divide diff by 2 to get number of chars
7790 sarl(cnt2, 1);
7791 }
7792 addq(result, cnt2);
7793 if (ae == StrIntrinsicNode::LL) {
7794 load_unsigned_byte(cnt1, Address(str2, result));
7795 load_unsigned_byte(result, Address(str1, result));
7796 } else if (ae == StrIntrinsicNode::UU) {
7797 load_unsigned_short(cnt1, Address(str2, result, scale));
7798 load_unsigned_short(result, Address(str1, result, scale));
7799 } else {
7800 load_unsigned_short(cnt1, Address(str2, result, scale2));
7801 load_unsigned_byte(result, Address(str1, result, scale1));
7802 }
7803 subl(result, cnt1);
7804 jmpb(POP_LABEL);
7805 }//if (VM_Version::supports_avx512vlbw())
7806 #endif // _LP64
7807
7808 // Discard the stored length difference
7809 bind(POP_LABEL);
7810 pop(cnt1);
7811
7812 // That's it
7813 bind(DONE_LABEL);
7814 if(ae == StrIntrinsicNode::UL) {
7815 negl(result);
7816 }
7817
7818 }
7819
7820 // Search for Non-ASCII character (Negative byte value) in a byte array,
7821 // return true if it has any and false otherwise.
7822 // ..\jdk\src\java.base\share\classes\java\lang\StringCoding.java
7823 // @HotSpotIntrinsicCandidate
7824 // private static boolean hasNegatives(byte[] ba, int off, int len) {
7825 // for (int i = off; i < off + len; i++) {
7826 // if (ba[i] < 0) {
7827 // return true;
7828 // }
7829 // }
7830 // return false;
7831 // }
7832 void MacroAssembler::has_negatives(Register ary1, Register len,
7833 Register result, Register tmp1,
7834 XMMRegister vec1, XMMRegister vec2) {
7835 // rsi: byte array
7836 // rcx: len
7837 // rax: result
7838 ShortBranchVerifier sbv(this);
7839 assert_different_registers(ary1, len, result, tmp1);
7840 assert_different_registers(vec1, vec2);
7841 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_CHAR, COMPARE_VECTORS, COMPARE_BYTE;
7842
7843 // len == 0
7844 testl(len, len);
7845 jcc(Assembler::zero, FALSE_LABEL);
7846
7847 if ((UseAVX > 2) && // AVX512
7848 VM_Version::supports_avx512vlbw() &&
7849 VM_Version::supports_bmi2()) {
7850
7851 set_vector_masking(); // opening of the stub context for programming mask registers
7852
7853 Label test_64_loop, test_tail;
7854 Register tmp3_aliased = len;
7855
7856 movl(tmp1, len);
7857 vpxor(vec2, vec2, vec2, Assembler::AVX_512bit);
7858
7859 andl(tmp1, 64 - 1); // tail count (in chars) 0x3F
7860 andl(len, ~(64 - 1)); // vector count (in chars)
7861 jccb(Assembler::zero, test_tail);
7862
7863 lea(ary1, Address(ary1, len, Address::times_1));
7864 negptr(len);
7865
7866 bind(test_64_loop);
7867 // Check whether our 64 elements of size byte contain negatives
7868 evpcmpgtb(k2, vec2, Address(ary1, len, Address::times_1), Assembler::AVX_512bit);
7869 kortestql(k2, k2);
7870 jcc(Assembler::notZero, TRUE_LABEL);
7871
7872 addptr(len, 64);
7873 jccb(Assembler::notZero, test_64_loop);
7874
7875
7876 bind(test_tail);
7877 // bail out when there is nothing to be done
7878 testl(tmp1, -1);
7879 jcc(Assembler::zero, FALSE_LABEL);
7880
7881 // Save k1
7882 kmovql(k3, k1);
7883
7884 // ~(~0 << len) applied up to two times (for 32-bit scenario)
7885 #ifdef _LP64
7886 mov64(tmp3_aliased, 0xFFFFFFFFFFFFFFFF);
7887 shlxq(tmp3_aliased, tmp3_aliased, tmp1);
7888 notq(tmp3_aliased);
7889 kmovql(k1, tmp3_aliased);
7890 #else
7891 Label k_init;
7892 jmp(k_init);
7893
7894 // We could not read 64-bits from a general purpose register thus we move
7895 // data required to compose 64 1's to the instruction stream
7896 // We emit 64 byte wide series of elements from 0..63 which later on would
7897 // be used as a compare targets with tail count contained in tmp1 register.
7898 // Result would be a k1 register having tmp1 consecutive number or 1
7899 // counting from least significant bit.
7900 address tmp = pc();
7901 emit_int64(0x0706050403020100);
7902 emit_int64(0x0F0E0D0C0B0A0908);
7903 emit_int64(0x1716151413121110);
7904 emit_int64(0x1F1E1D1C1B1A1918);
7905 emit_int64(0x2726252423222120);
7906 emit_int64(0x2F2E2D2C2B2A2928);
7907 emit_int64(0x3736353433323130);
7908 emit_int64(0x3F3E3D3C3B3A3938);
7909
7910 bind(k_init);
7911 lea(len, InternalAddress(tmp));
7912 // create mask to test for negative byte inside a vector
7913 evpbroadcastb(vec1, tmp1, Assembler::AVX_512bit);
7914 evpcmpgtb(k1, vec1, Address(len, 0), Assembler::AVX_512bit);
7915
7916 #endif
7917 evpcmpgtb(k2, k1, vec2, Address(ary1, 0), Assembler::AVX_512bit);
7918 ktestq(k2, k1);
7919 // Restore k1
7920 kmovql(k1, k3);
7921 jcc(Assembler::notZero, TRUE_LABEL);
7922
7923 jmp(FALSE_LABEL);
7924
7925 clear_vector_masking(); // closing of the stub context for programming mask registers
7926 } else {
7927 movl(result, len); // copy
7928
7929 if (UseAVX == 2 && UseSSE >= 2) {
7930 // With AVX2, use 32-byte vector compare
7931 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
7932
7933 // Compare 32-byte vectors
7934 andl(result, 0x0000001f); // tail count (in bytes)
7935 andl(len, 0xffffffe0); // vector count (in bytes)
7936 jccb(Assembler::zero, COMPARE_TAIL);
7937
7938 lea(ary1, Address(ary1, len, Address::times_1));
7939 negptr(len);
7940
7941 movl(tmp1, 0x80808080); // create mask to test for Unicode chars in vector
7942 movdl(vec2, tmp1);
7943 vpbroadcastd(vec2, vec2);
7944
7945 bind(COMPARE_WIDE_VECTORS);
7946 vmovdqu(vec1, Address(ary1, len, Address::times_1));
7947 vptest(vec1, vec2);
7948 jccb(Assembler::notZero, TRUE_LABEL);
7949 addptr(len, 32);
7950 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
7951
7952 testl(result, result);
7953 jccb(Assembler::zero, FALSE_LABEL);
7954
7955 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32));
7956 vptest(vec1, vec2);
7957 jccb(Assembler::notZero, TRUE_LABEL);
7958 jmpb(FALSE_LABEL);
7959
7960 bind(COMPARE_TAIL); // len is zero
7961 movl(len, result);
7962 // Fallthru to tail compare
7963 } else if (UseSSE42Intrinsics) {
7964 // With SSE4.2, use double quad vector compare
7965 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
7966
7967 // Compare 16-byte vectors
7968 andl(result, 0x0000000f); // tail count (in bytes)
7969 andl(len, 0xfffffff0); // vector count (in bytes)
7970 jccb(Assembler::zero, COMPARE_TAIL);
7971
7972 lea(ary1, Address(ary1, len, Address::times_1));
7973 negptr(len);
7974
7975 movl(tmp1, 0x80808080);
7976 movdl(vec2, tmp1);
7977 pshufd(vec2, vec2, 0);
7978
7979 bind(COMPARE_WIDE_VECTORS);
7980 movdqu(vec1, Address(ary1, len, Address::times_1));
7981 ptest(vec1, vec2);
7982 jccb(Assembler::notZero, TRUE_LABEL);
7983 addptr(len, 16);
7984 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
7985
7986 testl(result, result);
7987 jccb(Assembler::zero, FALSE_LABEL);
7988
7989 movdqu(vec1, Address(ary1, result, Address::times_1, -16));
7990 ptest(vec1, vec2);
7991 jccb(Assembler::notZero, TRUE_LABEL);
7992 jmpb(FALSE_LABEL);
7993
7994 bind(COMPARE_TAIL); // len is zero
7995 movl(len, result);
7996 // Fallthru to tail compare
7997 }
7998 }
7999 // Compare 4-byte vectors
8000 andl(len, 0xfffffffc); // vector count (in bytes)
8001 jccb(Assembler::zero, COMPARE_CHAR);
8002
8003 lea(ary1, Address(ary1, len, Address::times_1));
8004 negptr(len);
8005
8006 bind(COMPARE_VECTORS);
8007 movl(tmp1, Address(ary1, len, Address::times_1));
8008 andl(tmp1, 0x80808080);
8009 jccb(Assembler::notZero, TRUE_LABEL);
8010 addptr(len, 4);
8011 jcc(Assembler::notZero, COMPARE_VECTORS);
8012
8013 // Compare trailing char (final 2 bytes), if any
8014 bind(COMPARE_CHAR);
8015 testl(result, 0x2); // tail char
8016 jccb(Assembler::zero, COMPARE_BYTE);
8017 load_unsigned_short(tmp1, Address(ary1, 0));
8018 andl(tmp1, 0x00008080);
8019 jccb(Assembler::notZero, TRUE_LABEL);
8020 subptr(result, 2);
8021 lea(ary1, Address(ary1, 2));
8022
8023 bind(COMPARE_BYTE);
8024 testl(result, 0x1); // tail byte
8025 jccb(Assembler::zero, FALSE_LABEL);
8026 load_unsigned_byte(tmp1, Address(ary1, 0));
8027 andl(tmp1, 0x00000080);
8028 jccb(Assembler::notEqual, TRUE_LABEL);
8029 jmpb(FALSE_LABEL);
8030
8031 bind(TRUE_LABEL);
8032 movl(result, 1); // return true
8033 jmpb(DONE);
8034
8035 bind(FALSE_LABEL);
8036 xorl(result, result); // return false
8037
8038 // That's it
8039 bind(DONE);
8040 if (UseAVX >= 2 && UseSSE >= 2) {
8041 // clean upper bits of YMM registers
8042 vpxor(vec1, vec1);
8043 vpxor(vec2, vec2);
8044 }
8045 }
8046 // Compare char[] or byte[] arrays aligned to 4 bytes or substrings.
8047 void MacroAssembler::arrays_equals(bool is_array_equ, Register ary1, Register ary2,
8048 Register limit, Register result, Register chr,
8049 XMMRegister vec1, XMMRegister vec2, bool is_char) {
8050 ShortBranchVerifier sbv(this);
8051 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR, COMPARE_BYTE;
8052
8053 int length_offset = arrayOopDesc::length_offset_in_bytes();
8054 int base_offset = arrayOopDesc::base_offset_in_bytes(is_char ? T_CHAR : T_BYTE);
8055
8056 if (is_array_equ) {
8057 // Check the input args
8058 cmpoop(ary1, ary2);
8059 jcc(Assembler::equal, TRUE_LABEL);
8060
8061 // Need additional checks for arrays_equals.
8062 testptr(ary1, ary1);
8063 jcc(Assembler::zero, FALSE_LABEL);
8064 testptr(ary2, ary2);
8065 jcc(Assembler::zero, FALSE_LABEL);
8066
8067 // Check the lengths
8068 movl(limit, Address(ary1, length_offset));
8069 cmpl(limit, Address(ary2, length_offset));
8070 jcc(Assembler::notEqual, FALSE_LABEL);
8071 }
8072
8073 // count == 0
8074 testl(limit, limit);
8075 jcc(Assembler::zero, TRUE_LABEL);
8076
8077 if (is_array_equ) {
8078 // Load array address
8079 lea(ary1, Address(ary1, base_offset));
8080 lea(ary2, Address(ary2, base_offset));
8081 }
8082
8083 if (is_array_equ && is_char) {
8084 // arrays_equals when used for char[].
8085 shll(limit, 1); // byte count != 0
8086 }
8087 movl(result, limit); // copy
8088
8089 if (UseAVX >= 2) {
8090 // With AVX2, use 32-byte vector compare
8091 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
8092
8093 // Compare 32-byte vectors
8094 andl(result, 0x0000001f); // tail count (in bytes)
8095 andl(limit, 0xffffffe0); // vector count (in bytes)
8096 jcc(Assembler::zero, COMPARE_TAIL);
8097
8098 lea(ary1, Address(ary1, limit, Address::times_1));
8099 lea(ary2, Address(ary2, limit, Address::times_1));
8100 negptr(limit);
8101
8102 bind(COMPARE_WIDE_VECTORS);
8103
8104 #ifdef _LP64
8105 if (VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop
8106 Label COMPARE_WIDE_VECTORS_LOOP_AVX2, COMPARE_WIDE_VECTORS_LOOP_AVX3;
8107
8108 cmpl(limit, -64);
8109 jccb(Assembler::greater, COMPARE_WIDE_VECTORS_LOOP_AVX2);
8110
8111 bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop
8112
8113 evmovdquq(vec1, Address(ary1, limit, Address::times_1), Assembler::AVX_512bit);
8114 evpcmpeqb(k7, vec1, Address(ary2, limit, Address::times_1), Assembler::AVX_512bit);
8115 kortestql(k7, k7);
8116 jcc(Assembler::aboveEqual, FALSE_LABEL); // miscompare
8117 addptr(limit, 64); // update since we already compared at this addr
8118 cmpl(limit, -64);
8119 jccb(Assembler::lessEqual, COMPARE_WIDE_VECTORS_LOOP_AVX3);
8120
8121 // At this point we may still need to compare -limit+result bytes.
8122 // We could execute the next two instruction and just continue via non-wide path:
8123 // cmpl(limit, 0);
8124 // jcc(Assembler::equal, COMPARE_TAIL); // true
8125 // But since we stopped at the points ary{1,2}+limit which are
8126 // not farther than 64 bytes from the ends of arrays ary{1,2}+result
8127 // (|limit| <= 32 and result < 32),
8128 // we may just compare the last 64 bytes.
8129 //
8130 addptr(result, -64); // it is safe, bc we just came from this area
8131 evmovdquq(vec1, Address(ary1, result, Address::times_1), Assembler::AVX_512bit);
8132 evpcmpeqb(k7, vec1, Address(ary2, result, Address::times_1), Assembler::AVX_512bit);
8133 kortestql(k7, k7);
8134 jcc(Assembler::aboveEqual, FALSE_LABEL); // miscompare
8135
8136 jmp(TRUE_LABEL);
8137
8138 bind(COMPARE_WIDE_VECTORS_LOOP_AVX2);
8139
8140 }//if (VM_Version::supports_avx512vlbw())
8141 #endif //_LP64
8142
8143 vmovdqu(vec1, Address(ary1, limit, Address::times_1));
8144 vmovdqu(vec2, Address(ary2, limit, Address::times_1));
8145 vpxor(vec1, vec2);
8146
8147 vptest(vec1, vec1);
8148 jcc(Assembler::notZero, FALSE_LABEL);
8149 addptr(limit, 32);
8150 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
8151
8152 testl(result, result);
8153 jcc(Assembler::zero, TRUE_LABEL);
8154
8155 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32));
8156 vmovdqu(vec2, Address(ary2, result, Address::times_1, -32));
8157 vpxor(vec1, vec2);
8158
8159 vptest(vec1, vec1);
8160 jccb(Assembler::notZero, FALSE_LABEL);
8161 jmpb(TRUE_LABEL);
8162
8163 bind(COMPARE_TAIL); // limit is zero
8164 movl(limit, result);
8165 // Fallthru to tail compare
8166 } else if (UseSSE42Intrinsics) {
8167 // With SSE4.2, use double quad vector compare
8168 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
8169
8170 // Compare 16-byte vectors
8171 andl(result, 0x0000000f); // tail count (in bytes)
8172 andl(limit, 0xfffffff0); // vector count (in bytes)
8173 jcc(Assembler::zero, COMPARE_TAIL);
8174
8175 lea(ary1, Address(ary1, limit, Address::times_1));
8176 lea(ary2, Address(ary2, limit, Address::times_1));
8177 negptr(limit);
8178
8179 bind(COMPARE_WIDE_VECTORS);
8180 movdqu(vec1, Address(ary1, limit, Address::times_1));
8181 movdqu(vec2, Address(ary2, limit, Address::times_1));
8182 pxor(vec1, vec2);
8183
8184 ptest(vec1, vec1);
8185 jcc(Assembler::notZero, FALSE_LABEL);
8186 addptr(limit, 16);
8187 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
8188
8189 testl(result, result);
8190 jcc(Assembler::zero, TRUE_LABEL);
8191
8192 movdqu(vec1, Address(ary1, result, Address::times_1, -16));
8193 movdqu(vec2, Address(ary2, result, Address::times_1, -16));
8194 pxor(vec1, vec2);
8195
8196 ptest(vec1, vec1);
8197 jccb(Assembler::notZero, FALSE_LABEL);
8198 jmpb(TRUE_LABEL);
8199
8200 bind(COMPARE_TAIL); // limit is zero
8201 movl(limit, result);
8202 // Fallthru to tail compare
8203 }
8204
8205 // Compare 4-byte vectors
8206 andl(limit, 0xfffffffc); // vector count (in bytes)
8207 jccb(Assembler::zero, COMPARE_CHAR);
8208
8209 lea(ary1, Address(ary1, limit, Address::times_1));
8210 lea(ary2, Address(ary2, limit, Address::times_1));
8211 negptr(limit);
8212
8213 bind(COMPARE_VECTORS);
8214 movl(chr, Address(ary1, limit, Address::times_1));
8215 cmpl(chr, Address(ary2, limit, Address::times_1));
8216 jccb(Assembler::notEqual, FALSE_LABEL);
8217 addptr(limit, 4);
8218 jcc(Assembler::notZero, COMPARE_VECTORS);
8219
8220 // Compare trailing char (final 2 bytes), if any
8221 bind(COMPARE_CHAR);
8222 testl(result, 0x2); // tail char
8223 jccb(Assembler::zero, COMPARE_BYTE);
8224 load_unsigned_short(chr, Address(ary1, 0));
8225 load_unsigned_short(limit, Address(ary2, 0));
8226 cmpl(chr, limit);
8227 jccb(Assembler::notEqual, FALSE_LABEL);
8228
8229 if (is_array_equ && is_char) {
8230 bind(COMPARE_BYTE);
8231 } else {
8232 lea(ary1, Address(ary1, 2));
8233 lea(ary2, Address(ary2, 2));
8234
8235 bind(COMPARE_BYTE);
8236 testl(result, 0x1); // tail byte
8237 jccb(Assembler::zero, TRUE_LABEL);
8238 load_unsigned_byte(chr, Address(ary1, 0));
8239 load_unsigned_byte(limit, Address(ary2, 0));
8240 cmpl(chr, limit);
8241 jccb(Assembler::notEqual, FALSE_LABEL);
8242 }
8243 bind(TRUE_LABEL);
8244 movl(result, 1); // return true
8245 jmpb(DONE);
8246
8247 bind(FALSE_LABEL);
8248 xorl(result, result); // return false
8249
8250 // That's it
8251 bind(DONE);
8252 if (UseAVX >= 2) {
8253 // clean upper bits of YMM registers
8254 vpxor(vec1, vec1);
8255 vpxor(vec2, vec2);
8256 }
8257 }
8258
8259 #endif
8260
8261 void MacroAssembler::generate_fill(BasicType t, bool aligned,
8262 Register to, Register value, Register count,
8263 Register rtmp, XMMRegister xtmp) {
8264 ShortBranchVerifier sbv(this);
8265 assert_different_registers(to, value, count, rtmp);
8266 Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte;
8267 Label L_fill_2_bytes, L_fill_4_bytes;
8268
8269 int shift = -1;
8270 switch (t) {
8271 case T_BYTE:
8272 shift = 2;
8273 break;
8274 case T_SHORT:
8275 shift = 1;
8276 break;
8277 case T_INT:
8278 shift = 0;
8279 break;
8280 default: ShouldNotReachHere();
8281 }
8282
8283 if (t == T_BYTE) {
8284 andl(value, 0xff);
8285 movl(rtmp, value);
8286 shll(rtmp, 8);
8287 orl(value, rtmp);
8288 }
8289 if (t == T_SHORT) {
8290 andl(value, 0xffff);
8291 }
8292 if (t == T_BYTE || t == T_SHORT) {
8293 movl(rtmp, value);
8294 shll(rtmp, 16);
8295 orl(value, rtmp);
8296 }
8297
8298 cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element
8299 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
8300 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
8301 // align source address at 4 bytes address boundary
8302 if (t == T_BYTE) {
8303 // One byte misalignment happens only for byte arrays
8304 testptr(to, 1);
8305 jccb(Assembler::zero, L_skip_align1);
8306 movb(Address(to, 0), value);
8307 increment(to);
8308 decrement(count);
8309 BIND(L_skip_align1);
8310 }
8311 // Two bytes misalignment happens only for byte and short (char) arrays
8312 testptr(to, 2);
8313 jccb(Assembler::zero, L_skip_align2);
8314 movw(Address(to, 0), value);
8315 addptr(to, 2);
8316 subl(count, 1<<(shift-1));
8317 BIND(L_skip_align2);
8318 }
8319 if (UseSSE < 2) {
8320 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
8321 // Fill 32-byte chunks
8322 subl(count, 8 << shift);
8323 jcc(Assembler::less, L_check_fill_8_bytes);
8324 align(16);
8325
8326 BIND(L_fill_32_bytes_loop);
8327
8328 for (int i = 0; i < 32; i += 4) {
8329 movl(Address(to, i), value);
8330 }
8331
8332 addptr(to, 32);
8333 subl(count, 8 << shift);
8334 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
8335 BIND(L_check_fill_8_bytes);
8336 addl(count, 8 << shift);
8337 jccb(Assembler::zero, L_exit);
8338 jmpb(L_fill_8_bytes);
8339
8340 //
8341 // length is too short, just fill qwords
8342 //
8343 BIND(L_fill_8_bytes_loop);
8344 movl(Address(to, 0), value);
8345 movl(Address(to, 4), value);
8346 addptr(to, 8);
8347 BIND(L_fill_8_bytes);
8348 subl(count, 1 << (shift + 1));
8349 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
8350 // fall through to fill 4 bytes
8351 } else {
8352 Label L_fill_32_bytes;
8353 if (!UseUnalignedLoadStores) {
8354 // align to 8 bytes, we know we are 4 byte aligned to start
8355 testptr(to, 4);
8356 jccb(Assembler::zero, L_fill_32_bytes);
8357 movl(Address(to, 0), value);
8358 addptr(to, 4);
8359 subl(count, 1<<shift);
8360 }
8361 BIND(L_fill_32_bytes);
8362 {
8363 assert( UseSSE >= 2, "supported cpu only" );
8364 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
8365 if (UseAVX > 2) {
8366 movl(rtmp, 0xffff);
8367 kmovwl(k1, rtmp);
8368 }
8369 movdl(xtmp, value);
8370 if (UseAVX > 2 && UseUnalignedLoadStores) {
8371 // Fill 64-byte chunks
8372 Label L_fill_64_bytes_loop, L_check_fill_32_bytes;
8373 evpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit);
8374
8375 subl(count, 16 << shift);
8376 jcc(Assembler::less, L_check_fill_32_bytes);
8377 align(16);
8378
8379 BIND(L_fill_64_bytes_loop);
8380 evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit);
8381 addptr(to, 64);
8382 subl(count, 16 << shift);
8383 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
8384
8385 BIND(L_check_fill_32_bytes);
8386 addl(count, 8 << shift);
8387 jccb(Assembler::less, L_check_fill_8_bytes);
8388 vmovdqu(Address(to, 0), xtmp);
8389 addptr(to, 32);
8390 subl(count, 8 << shift);
8391
8392 BIND(L_check_fill_8_bytes);
8393 } else if (UseAVX == 2 && UseUnalignedLoadStores) {
8394 // Fill 64-byte chunks
8395 Label L_fill_64_bytes_loop, L_check_fill_32_bytes;
8396 vpbroadcastd(xtmp, xtmp);
8397
8398 subl(count, 16 << shift);
8399 jcc(Assembler::less, L_check_fill_32_bytes);
8400 align(16);
8401
8402 BIND(L_fill_64_bytes_loop);
8403 vmovdqu(Address(to, 0), xtmp);
8404 vmovdqu(Address(to, 32), xtmp);
8405 addptr(to, 64);
8406 subl(count, 16 << shift);
8407 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
8408
8409 BIND(L_check_fill_32_bytes);
8410 addl(count, 8 << shift);
8411 jccb(Assembler::less, L_check_fill_8_bytes);
8412 vmovdqu(Address(to, 0), xtmp);
8413 addptr(to, 32);
8414 subl(count, 8 << shift);
8415
8416 BIND(L_check_fill_8_bytes);
8417 // clean upper bits of YMM registers
8418 movdl(xtmp, value);
8419 pshufd(xtmp, xtmp, 0);
8420 } else {
8421 // Fill 32-byte chunks
8422 pshufd(xtmp, xtmp, 0);
8423
8424 subl(count, 8 << shift);
8425 jcc(Assembler::less, L_check_fill_8_bytes);
8426 align(16);
8427
8428 BIND(L_fill_32_bytes_loop);
8429
8430 if (UseUnalignedLoadStores) {
8431 movdqu(Address(to, 0), xtmp);
8432 movdqu(Address(to, 16), xtmp);
8433 } else {
8434 movq(Address(to, 0), xtmp);
8435 movq(Address(to, 8), xtmp);
8436 movq(Address(to, 16), xtmp);
8437 movq(Address(to, 24), xtmp);
8438 }
8439
8440 addptr(to, 32);
8441 subl(count, 8 << shift);
8442 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
8443
8444 BIND(L_check_fill_8_bytes);
8445 }
8446 addl(count, 8 << shift);
8447 jccb(Assembler::zero, L_exit);
8448 jmpb(L_fill_8_bytes);
8449
8450 //
8451 // length is too short, just fill qwords
8452 //
8453 BIND(L_fill_8_bytes_loop);
8454 movq(Address(to, 0), xtmp);
8455 addptr(to, 8);
8456 BIND(L_fill_8_bytes);
8457 subl(count, 1 << (shift + 1));
8458 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
8459 }
8460 }
8461 // fill trailing 4 bytes
8462 BIND(L_fill_4_bytes);
8463 testl(count, 1<<shift);
8464 jccb(Assembler::zero, L_fill_2_bytes);
8465 movl(Address(to, 0), value);
8466 if (t == T_BYTE || t == T_SHORT) {
8467 addptr(to, 4);
8468 BIND(L_fill_2_bytes);
8469 // fill trailing 2 bytes
8470 testl(count, 1<<(shift-1));
8471 jccb(Assembler::zero, L_fill_byte);
8472 movw(Address(to, 0), value);
8473 if (t == T_BYTE) {
8474 addptr(to, 2);
8475 BIND(L_fill_byte);
8476 // fill trailing byte
8477 testl(count, 1);
8478 jccb(Assembler::zero, L_exit);
8479 movb(Address(to, 0), value);
8480 } else {
8481 BIND(L_fill_byte);
8482 }
8483 } else {
8484 BIND(L_fill_2_bytes);
8485 }
8486 BIND(L_exit);
8487 }
8488
8489 // encode char[] to byte[] in ISO_8859_1
8490 //@HotSpotIntrinsicCandidate
8491 //private static int implEncodeISOArray(byte[] sa, int sp,
8492 //byte[] da, int dp, int len) {
8493 // int i = 0;
8494 // for (; i < len; i++) {
8495 // char c = StringUTF16.getChar(sa, sp++);
8496 // if (c > '\u00FF')
8497 // break;
8498 // da[dp++] = (byte)c;
8499 // }
8500 // return i;
8501 //}
8502 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
8503 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
8504 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
8505 Register tmp5, Register result) {
8506
8507 // rsi: src
8508 // rdi: dst
8509 // rdx: len
8510 // rcx: tmp5
8511 // rax: result
8512 ShortBranchVerifier sbv(this);
8513 assert_different_registers(src, dst, len, tmp5, result);
8514 Label L_done, L_copy_1_char, L_copy_1_char_exit;
8515
8516 // set result
8517 xorl(result, result);
8518 // check for zero length
8519 testl(len, len);
8520 jcc(Assembler::zero, L_done);
8521
8522 movl(result, len);
8523
8524 // Setup pointers
8525 lea(src, Address(src, len, Address::times_2)); // char[]
8526 lea(dst, Address(dst, len, Address::times_1)); // byte[]
8527 negptr(len);
8528
8529 if (UseSSE42Intrinsics || UseAVX >= 2) {
8530 Label L_chars_8_check, L_copy_8_chars, L_copy_8_chars_exit;
8531 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
8532
8533 if (UseAVX >= 2) {
8534 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
8535 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector
8536 movdl(tmp1Reg, tmp5);
8537 vpbroadcastd(tmp1Reg, tmp1Reg);
8538 jmp(L_chars_32_check);
8539
8540 bind(L_copy_32_chars);
8541 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
8542 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
8543 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
8544 vptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
8545 jccb(Assembler::notZero, L_copy_32_chars_exit);
8546 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
8547 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1);
8548 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
8549
8550 bind(L_chars_32_check);
8551 addptr(len, 32);
8552 jcc(Assembler::lessEqual, L_copy_32_chars);
8553
8554 bind(L_copy_32_chars_exit);
8555 subptr(len, 16);
8556 jccb(Assembler::greater, L_copy_16_chars_exit);
8557
8558 } else if (UseSSE42Intrinsics) {
8559 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector
8560 movdl(tmp1Reg, tmp5);
8561 pshufd(tmp1Reg, tmp1Reg, 0);
8562 jmpb(L_chars_16_check);
8563 }
8564
8565 bind(L_copy_16_chars);
8566 if (UseAVX >= 2) {
8567 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
8568 vptest(tmp2Reg, tmp1Reg);
8569 jcc(Assembler::notZero, L_copy_16_chars_exit);
8570 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1);
8571 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1);
8572 } else {
8573 if (UseAVX > 0) {
8574 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
8575 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
8576 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0);
8577 } else {
8578 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
8579 por(tmp2Reg, tmp3Reg);
8580 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
8581 por(tmp2Reg, tmp4Reg);
8582 }
8583 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
8584 jccb(Assembler::notZero, L_copy_16_chars_exit);
8585 packuswb(tmp3Reg, tmp4Reg);
8586 }
8587 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
8588
8589 bind(L_chars_16_check);
8590 addptr(len, 16);
8591 jcc(Assembler::lessEqual, L_copy_16_chars);
8592
8593 bind(L_copy_16_chars_exit);
8594 if (UseAVX >= 2) {
8595 // clean upper bits of YMM registers
8596 vpxor(tmp2Reg, tmp2Reg);
8597 vpxor(tmp3Reg, tmp3Reg);
8598 vpxor(tmp4Reg, tmp4Reg);
8599 movdl(tmp1Reg, tmp5);
8600 pshufd(tmp1Reg, tmp1Reg, 0);
8601 }
8602 subptr(len, 8);
8603 jccb(Assembler::greater, L_copy_8_chars_exit);
8604
8605 bind(L_copy_8_chars);
8606 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
8607 ptest(tmp3Reg, tmp1Reg);
8608 jccb(Assembler::notZero, L_copy_8_chars_exit);
8609 packuswb(tmp3Reg, tmp1Reg);
8610 movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
8611 addptr(len, 8);
8612 jccb(Assembler::lessEqual, L_copy_8_chars);
8613
8614 bind(L_copy_8_chars_exit);
8615 subptr(len, 8);
8616 jccb(Assembler::zero, L_done);
8617 }
8618
8619 bind(L_copy_1_char);
8620 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
8621 testl(tmp5, 0xff00); // check if Unicode char
8622 jccb(Assembler::notZero, L_copy_1_char_exit);
8623 movb(Address(dst, len, Address::times_1, 0), tmp5);
8624 addptr(len, 1);
8625 jccb(Assembler::less, L_copy_1_char);
8626
8627 bind(L_copy_1_char_exit);
8628 addptr(result, len); // len is negative count of not processed elements
8629
8630 bind(L_done);
8631 }
8632
8633 #ifdef _LP64
8634 /**
8635 * Helper for multiply_to_len().
8636 */
8637 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
8638 addq(dest_lo, src1);
8639 adcq(dest_hi, 0);
8640 addq(dest_lo, src2);
8641 adcq(dest_hi, 0);
8642 }
8643
8644 /**
8645 * Multiply 64 bit by 64 bit first loop.
8646 */
8647 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
8648 Register y, Register y_idx, Register z,
8649 Register carry, Register product,
8650 Register idx, Register kdx) {
8651 //
8652 // jlong carry, x[], y[], z[];
8653 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
8654 // huge_128 product = y[idx] * x[xstart] + carry;
8655 // z[kdx] = (jlong)product;
8656 // carry = (jlong)(product >>> 64);
8657 // }
8658 // z[xstart] = carry;
8659 //
8660
8661 Label L_first_loop, L_first_loop_exit;
8662 Label L_one_x, L_one_y, L_multiply;
8663
8664 decrementl(xstart);
8665 jcc(Assembler::negative, L_one_x);
8666
8667 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
8668 rorq(x_xstart, 32); // convert big-endian to little-endian
8669
8670 bind(L_first_loop);
8671 decrementl(idx);
8672 jcc(Assembler::negative, L_first_loop_exit);
8673 decrementl(idx);
8674 jcc(Assembler::negative, L_one_y);
8675 movq(y_idx, Address(y, idx, Address::times_4, 0));
8676 rorq(y_idx, 32); // convert big-endian to little-endian
8677 bind(L_multiply);
8678 movq(product, x_xstart);
8679 mulq(y_idx); // product(rax) * y_idx -> rdx:rax
8680 addq(product, carry);
8681 adcq(rdx, 0);
8682 subl(kdx, 2);
8683 movl(Address(z, kdx, Address::times_4, 4), product);
8684 shrq(product, 32);
8685 movl(Address(z, kdx, Address::times_4, 0), product);
8686 movq(carry, rdx);
8687 jmp(L_first_loop);
8688
8689 bind(L_one_y);
8690 movl(y_idx, Address(y, 0));
8691 jmp(L_multiply);
8692
8693 bind(L_one_x);
8694 movl(x_xstart, Address(x, 0));
8695 jmp(L_first_loop);
8696
8697 bind(L_first_loop_exit);
8698 }
8699
8700 /**
8701 * Multiply 64 bit by 64 bit and add 128 bit.
8702 */
8703 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
8704 Register yz_idx, Register idx,
8705 Register carry, Register product, int offset) {
8706 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
8707 // z[kdx] = (jlong)product;
8708
8709 movq(yz_idx, Address(y, idx, Address::times_4, offset));
8710 rorq(yz_idx, 32); // convert big-endian to little-endian
8711 movq(product, x_xstart);
8712 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
8713 movq(yz_idx, Address(z, idx, Address::times_4, offset));
8714 rorq(yz_idx, 32); // convert big-endian to little-endian
8715
8716 add2_with_carry(rdx, product, carry, yz_idx);
8717
8718 movl(Address(z, idx, Address::times_4, offset+4), product);
8719 shrq(product, 32);
8720 movl(Address(z, idx, Address::times_4, offset), product);
8721
8722 }
8723
8724 /**
8725 * Multiply 128 bit by 128 bit. Unrolled inner loop.
8726 */
8727 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
8728 Register yz_idx, Register idx, Register jdx,
8729 Register carry, Register product,
8730 Register carry2) {
8731 // jlong carry, x[], y[], z[];
8732 // int kdx = ystart+1;
8733 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
8734 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
8735 // z[kdx+idx+1] = (jlong)product;
8736 // jlong carry2 = (jlong)(product >>> 64);
8737 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
8738 // z[kdx+idx] = (jlong)product;
8739 // carry = (jlong)(product >>> 64);
8740 // }
8741 // idx += 2;
8742 // if (idx > 0) {
8743 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
8744 // z[kdx+idx] = (jlong)product;
8745 // carry = (jlong)(product >>> 64);
8746 // }
8747 //
8748
8749 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
8750
8751 movl(jdx, idx);
8752 andl(jdx, 0xFFFFFFFC);
8753 shrl(jdx, 2);
8754
8755 bind(L_third_loop);
8756 subl(jdx, 1);
8757 jcc(Assembler::negative, L_third_loop_exit);
8758 subl(idx, 4);
8759
8760 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
8761 movq(carry2, rdx);
8762
8763 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
8764 movq(carry, rdx);
8765 jmp(L_third_loop);
8766
8767 bind (L_third_loop_exit);
8768
8769 andl (idx, 0x3);
8770 jcc(Assembler::zero, L_post_third_loop_done);
8771
8772 Label L_check_1;
8773 subl(idx, 2);
8774 jcc(Assembler::negative, L_check_1);
8775
8776 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
8777 movq(carry, rdx);
8778
8779 bind (L_check_1);
8780 addl (idx, 0x2);
8781 andl (idx, 0x1);
8782 subl(idx, 1);
8783 jcc(Assembler::negative, L_post_third_loop_done);
8784
8785 movl(yz_idx, Address(y, idx, Address::times_4, 0));
8786 movq(product, x_xstart);
8787 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
8788 movl(yz_idx, Address(z, idx, Address::times_4, 0));
8789
8790 add2_with_carry(rdx, product, yz_idx, carry);
8791
8792 movl(Address(z, idx, Address::times_4, 0), product);
8793 shrq(product, 32);
8794
8795 shlq(rdx, 32);
8796 orq(product, rdx);
8797 movq(carry, product);
8798
8799 bind(L_post_third_loop_done);
8800 }
8801
8802 /**
8803 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
8804 *
8805 */
8806 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
8807 Register carry, Register carry2,
8808 Register idx, Register jdx,
8809 Register yz_idx1, Register yz_idx2,
8810 Register tmp, Register tmp3, Register tmp4) {
8811 assert(UseBMI2Instructions, "should be used only when BMI2 is available");
8812
8813 // jlong carry, x[], y[], z[];
8814 // int kdx = ystart+1;
8815 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
8816 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
8817 // jlong carry2 = (jlong)(tmp3 >>> 64);
8818 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2;
8819 // carry = (jlong)(tmp4 >>> 64);
8820 // z[kdx+idx+1] = (jlong)tmp3;
8821 // z[kdx+idx] = (jlong)tmp4;
8822 // }
8823 // idx += 2;
8824 // if (idx > 0) {
8825 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
8826 // z[kdx+idx] = (jlong)yz_idx1;
8827 // carry = (jlong)(yz_idx1 >>> 64);
8828 // }
8829 //
8830
8831 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
8832
8833 movl(jdx, idx);
8834 andl(jdx, 0xFFFFFFFC);
8835 shrl(jdx, 2);
8836
8837 bind(L_third_loop);
8838 subl(jdx, 1);
8839 jcc(Assembler::negative, L_third_loop_exit);
8840 subl(idx, 4);
8841
8842 movq(yz_idx1, Address(y, idx, Address::times_4, 8));
8843 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
8844 movq(yz_idx2, Address(y, idx, Address::times_4, 0));
8845 rorxq(yz_idx2, yz_idx2, 32);
8846
8847 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
8848 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp
8849
8850 movq(yz_idx1, Address(z, idx, Address::times_4, 8));
8851 rorxq(yz_idx1, yz_idx1, 32);
8852 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
8853 rorxq(yz_idx2, yz_idx2, 32);
8854
8855 if (VM_Version::supports_adx()) {
8856 adcxq(tmp3, carry);
8857 adoxq(tmp3, yz_idx1);
8858
8859 adcxq(tmp4, tmp);
8860 adoxq(tmp4, yz_idx2);
8861
8862 movl(carry, 0); // does not affect flags
8863 adcxq(carry2, carry);
8864 adoxq(carry2, carry);
8865 } else {
8866 add2_with_carry(tmp4, tmp3, carry, yz_idx1);
8867 add2_with_carry(carry2, tmp4, tmp, yz_idx2);
8868 }
8869 movq(carry, carry2);
8870
8871 movl(Address(z, idx, Address::times_4, 12), tmp3);
8872 shrq(tmp3, 32);
8873 movl(Address(z, idx, Address::times_4, 8), tmp3);
8874
8875 movl(Address(z, idx, Address::times_4, 4), tmp4);
8876 shrq(tmp4, 32);
8877 movl(Address(z, idx, Address::times_4, 0), tmp4);
8878
8879 jmp(L_third_loop);
8880
8881 bind (L_third_loop_exit);
8882
8883 andl (idx, 0x3);
8884 jcc(Assembler::zero, L_post_third_loop_done);
8885
8886 Label L_check_1;
8887 subl(idx, 2);
8888 jcc(Assembler::negative, L_check_1);
8889
8890 movq(yz_idx1, Address(y, idx, Address::times_4, 0));
8891 rorxq(yz_idx1, yz_idx1, 32);
8892 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
8893 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
8894 rorxq(yz_idx2, yz_idx2, 32);
8895
8896 add2_with_carry(tmp4, tmp3, carry, yz_idx2);
8897
8898 movl(Address(z, idx, Address::times_4, 4), tmp3);
8899 shrq(tmp3, 32);
8900 movl(Address(z, idx, Address::times_4, 0), tmp3);
8901 movq(carry, tmp4);
8902
8903 bind (L_check_1);
8904 addl (idx, 0x2);
8905 andl (idx, 0x1);
8906 subl(idx, 1);
8907 jcc(Assembler::negative, L_post_third_loop_done);
8908 movl(tmp4, Address(y, idx, Address::times_4, 0));
8909 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3
8910 movl(tmp4, Address(z, idx, Address::times_4, 0));
8911
8912 add2_with_carry(carry2, tmp3, tmp4, carry);
8913
8914 movl(Address(z, idx, Address::times_4, 0), tmp3);
8915 shrq(tmp3, 32);
8916
8917 shlq(carry2, 32);
8918 orq(tmp3, carry2);
8919 movq(carry, tmp3);
8920
8921 bind(L_post_third_loop_done);
8922 }
8923
8924 /**
8925 * Code for BigInteger::multiplyToLen() instrinsic.
8926 *
8927 * rdi: x
8928 * rax: xlen
8929 * rsi: y
8930 * rcx: ylen
8931 * r8: z
8932 * r11: zlen
8933 * r12: tmp1
8934 * r13: tmp2
8935 * r14: tmp3
8936 * r15: tmp4
8937 * rbx: tmp5
8938 *
8939 */
8940 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
8941 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
8942 ShortBranchVerifier sbv(this);
8943 assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
8944
8945 push(tmp1);
8946 push(tmp2);
8947 push(tmp3);
8948 push(tmp4);
8949 push(tmp5);
8950
8951 push(xlen);
8952 push(zlen);
8953
8954 const Register idx = tmp1;
8955 const Register kdx = tmp2;
8956 const Register xstart = tmp3;
8957
8958 const Register y_idx = tmp4;
8959 const Register carry = tmp5;
8960 const Register product = xlen;
8961 const Register x_xstart = zlen; // reuse register
8962
8963 // First Loop.
8964 //
8965 // final static long LONG_MASK = 0xffffffffL;
8966 // int xstart = xlen - 1;
8967 // int ystart = ylen - 1;
8968 // long carry = 0;
8969 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
8970 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
8971 // z[kdx] = (int)product;
8972 // carry = product >>> 32;
8973 // }
8974 // z[xstart] = (int)carry;
8975 //
8976
8977 movl(idx, ylen); // idx = ylen;
8978 movl(kdx, zlen); // kdx = xlen+ylen;
8979 xorq(carry, carry); // carry = 0;
8980
8981 Label L_done;
8982
8983 movl(xstart, xlen);
8984 decrementl(xstart);
8985 jcc(Assembler::negative, L_done);
8986
8987 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
8988
8989 Label L_second_loop;
8990 testl(kdx, kdx);
8991 jcc(Assembler::zero, L_second_loop);
8992
8993 Label L_carry;
8994 subl(kdx, 1);
8995 jcc(Assembler::zero, L_carry);
8996
8997 movl(Address(z, kdx, Address::times_4, 0), carry);
8998 shrq(carry, 32);
8999 subl(kdx, 1);
9000
9001 bind(L_carry);
9002 movl(Address(z, kdx, Address::times_4, 0), carry);
9003
9004 // Second and third (nested) loops.
9005 //
9006 // for (int i = xstart-1; i >= 0; i--) { // Second loop
9007 // carry = 0;
9008 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
9009 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
9010 // (z[k] & LONG_MASK) + carry;
9011 // z[k] = (int)product;
9012 // carry = product >>> 32;
9013 // }
9014 // z[i] = (int)carry;
9015 // }
9016 //
9017 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
9018
9019 const Register jdx = tmp1;
9020
9021 bind(L_second_loop);
9022 xorl(carry, carry); // carry = 0;
9023 movl(jdx, ylen); // j = ystart+1
9024
9025 subl(xstart, 1); // i = xstart-1;
9026 jcc(Assembler::negative, L_done);
9027
9028 push (z);
9029
9030 Label L_last_x;
9031 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
9032 subl(xstart, 1); // i = xstart-1;
9033 jcc(Assembler::negative, L_last_x);
9034
9035 if (UseBMI2Instructions) {
9036 movq(rdx, Address(x, xstart, Address::times_4, 0));
9037 rorxq(rdx, rdx, 32); // convert big-endian to little-endian
9038 } else {
9039 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
9040 rorq(x_xstart, 32); // convert big-endian to little-endian
9041 }
9042
9043 Label L_third_loop_prologue;
9044 bind(L_third_loop_prologue);
9045
9046 push (x);
9047 push (xstart);
9048 push (ylen);
9049
9050
9051 if (UseBMI2Instructions) {
9052 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
9053 } else { // !UseBMI2Instructions
9054 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
9055 }
9056
9057 pop(ylen);
9058 pop(xlen);
9059 pop(x);
9060 pop(z);
9061
9062 movl(tmp3, xlen);
9063 addl(tmp3, 1);
9064 movl(Address(z, tmp3, Address::times_4, 0), carry);
9065 subl(tmp3, 1);
9066 jccb(Assembler::negative, L_done);
9067
9068 shrq(carry, 32);
9069 movl(Address(z, tmp3, Address::times_4, 0), carry);
9070 jmp(L_second_loop);
9071
9072 // Next infrequent code is moved outside loops.
9073 bind(L_last_x);
9074 if (UseBMI2Instructions) {
9075 movl(rdx, Address(x, 0));
9076 } else {
9077 movl(x_xstart, Address(x, 0));
9078 }
9079 jmp(L_third_loop_prologue);
9080
9081 bind(L_done);
9082
9083 pop(zlen);
9084 pop(xlen);
9085
9086 pop(tmp5);
9087 pop(tmp4);
9088 pop(tmp3);
9089 pop(tmp2);
9090 pop(tmp1);
9091 }
9092
9093 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
9094 Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){
9095 assert(UseSSE42Intrinsics, "SSE4.2 must be enabled.");
9096 Label VECTOR64_LOOP, VECTOR64_TAIL, VECTOR64_NOT_EQUAL, VECTOR32_TAIL;
9097 Label VECTOR32_LOOP, VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP;
9098 Label VECTOR16_TAIL, VECTOR8_TAIL, VECTOR4_TAIL;
9099 Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL;
9100 Label SAME_TILL_END, DONE;
9101 Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL;
9102
9103 //scale is in rcx in both Win64 and Unix
9104 ShortBranchVerifier sbv(this);
9105
9106 shlq(length);
9107 xorq(result, result);
9108
9109 if ((UseAVX > 2) &&
9110 VM_Version::supports_avx512vlbw()) {
9111 set_vector_masking(); // opening of the stub context for programming mask registers
9112 cmpq(length, 64);
9113 jcc(Assembler::less, VECTOR32_TAIL);
9114 movq(tmp1, length);
9115 andq(tmp1, 0x3F); // tail count
9116 andq(length, ~(0x3F)); //vector count
9117
9118 bind(VECTOR64_LOOP);
9119 // AVX512 code to compare 64 byte vectors.
9120 evmovdqub(rymm0, Address(obja, result), Assembler::AVX_512bit);
9121 evpcmpeqb(k7, rymm0, Address(objb, result), Assembler::AVX_512bit);
9122 kortestql(k7, k7);
9123 jcc(Assembler::aboveEqual, VECTOR64_NOT_EQUAL); // mismatch
9124 addq(result, 64);
9125 subq(length, 64);
9126 jccb(Assembler::notZero, VECTOR64_LOOP);
9127
9128 //bind(VECTOR64_TAIL);
9129 testq(tmp1, tmp1);
9130 jcc(Assembler::zero, SAME_TILL_END);
9131
9132 bind(VECTOR64_TAIL);
9133 // AVX512 code to compare upto 63 byte vectors.
9134 // Save k1
9135 kmovql(k3, k1);
9136 mov64(tmp2, 0xFFFFFFFFFFFFFFFF);
9137 shlxq(tmp2, tmp2, tmp1);
9138 notq(tmp2);
9139 kmovql(k1, tmp2);
9140
9141 evmovdqub(rymm0, k1, Address(obja, result), Assembler::AVX_512bit);
9142 evpcmpeqb(k7, k1, rymm0, Address(objb, result), Assembler::AVX_512bit);
9143
9144 ktestql(k7, k1);
9145 // Restore k1
9146 kmovql(k1, k3);
9147 jcc(Assembler::below, SAME_TILL_END); // not mismatch
9148
9149 bind(VECTOR64_NOT_EQUAL);
9150 kmovql(tmp1, k7);
9151 notq(tmp1);
9152 tzcntq(tmp1, tmp1);
9153 addq(result, tmp1);
9154 shrq(result);
9155 jmp(DONE);
9156 bind(VECTOR32_TAIL);
9157 clear_vector_masking(); // closing of the stub context for programming mask registers
9158 }
9159
9160 cmpq(length, 8);
9161 jcc(Assembler::equal, VECTOR8_LOOP);
9162 jcc(Assembler::less, VECTOR4_TAIL);
9163
9164 if (UseAVX >= 2) {
9165
9166 cmpq(length, 16);
9167 jcc(Assembler::equal, VECTOR16_LOOP);
9168 jcc(Assembler::less, VECTOR8_LOOP);
9169
9170 cmpq(length, 32);
9171 jccb(Assembler::less, VECTOR16_TAIL);
9172
9173 subq(length, 32);
9174 bind(VECTOR32_LOOP);
9175 vmovdqu(rymm0, Address(obja, result));
9176 vmovdqu(rymm1, Address(objb, result));
9177 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit);
9178 vptest(rymm2, rymm2);
9179 jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found
9180 addq(result, 32);
9181 subq(length, 32);
9182 jccb(Assembler::greaterEqual, VECTOR32_LOOP);
9183 addq(length, 32);
9184 jcc(Assembler::equal, SAME_TILL_END);
9185 //falling through if less than 32 bytes left //close the branch here.
9186
9187 bind(VECTOR16_TAIL);
9188 cmpq(length, 16);
9189 jccb(Assembler::less, VECTOR8_TAIL);
9190 bind(VECTOR16_LOOP);
9191 movdqu(rymm0, Address(obja, result));
9192 movdqu(rymm1, Address(objb, result));
9193 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit);
9194 ptest(rymm2, rymm2);
9195 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
9196 addq(result, 16);
9197 subq(length, 16);
9198 jcc(Assembler::equal, SAME_TILL_END);
9199 //falling through if less than 16 bytes left
9200 } else {//regular intrinsics
9201
9202 cmpq(length, 16);
9203 jccb(Assembler::less, VECTOR8_TAIL);
9204
9205 subq(length, 16);
9206 bind(VECTOR16_LOOP);
9207 movdqu(rymm0, Address(obja, result));
9208 movdqu(rymm1, Address(objb, result));
9209 pxor(rymm0, rymm1);
9210 ptest(rymm0, rymm0);
9211 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
9212 addq(result, 16);
9213 subq(length, 16);
9214 jccb(Assembler::greaterEqual, VECTOR16_LOOP);
9215 addq(length, 16);
9216 jcc(Assembler::equal, SAME_TILL_END);
9217 //falling through if less than 16 bytes left
9218 }
9219
9220 bind(VECTOR8_TAIL);
9221 cmpq(length, 8);
9222 jccb(Assembler::less, VECTOR4_TAIL);
9223 bind(VECTOR8_LOOP);
9224 movq(tmp1, Address(obja, result));
9225 movq(tmp2, Address(objb, result));
9226 xorq(tmp1, tmp2);
9227 testq(tmp1, tmp1);
9228 jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found
9229 addq(result, 8);
9230 subq(length, 8);
9231 jcc(Assembler::equal, SAME_TILL_END);
9232 //falling through if less than 8 bytes left
9233
9234 bind(VECTOR4_TAIL);
9235 cmpq(length, 4);
9236 jccb(Assembler::less, BYTES_TAIL);
9237 bind(VECTOR4_LOOP);
9238 movl(tmp1, Address(obja, result));
9239 xorl(tmp1, Address(objb, result));
9240 testl(tmp1, tmp1);
9241 jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found
9242 addq(result, 4);
9243 subq(length, 4);
9244 jcc(Assembler::equal, SAME_TILL_END);
9245 //falling through if less than 4 bytes left
9246
9247 bind(BYTES_TAIL);
9248 bind(BYTES_LOOP);
9249 load_unsigned_byte(tmp1, Address(obja, result));
9250 load_unsigned_byte(tmp2, Address(objb, result));
9251 xorl(tmp1, tmp2);
9252 testl(tmp1, tmp1);
9253 jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
9254 decq(length);
9255 jccb(Assembler::zero, SAME_TILL_END);
9256 incq(result);
9257 load_unsigned_byte(tmp1, Address(obja, result));
9258 load_unsigned_byte(tmp2, Address(objb, result));
9259 xorl(tmp1, tmp2);
9260 testl(tmp1, tmp1);
9261 jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
9262 decq(length);
9263 jccb(Assembler::zero, SAME_TILL_END);
9264 incq(result);
9265 load_unsigned_byte(tmp1, Address(obja, result));
9266 load_unsigned_byte(tmp2, Address(objb, result));
9267 xorl(tmp1, tmp2);
9268 testl(tmp1, tmp1);
9269 jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
9270 jmpb(SAME_TILL_END);
9271
9272 if (UseAVX >= 2) {
9273 bind(VECTOR32_NOT_EQUAL);
9274 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit);
9275 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit);
9276 vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit);
9277 vpmovmskb(tmp1, rymm0);
9278 bsfq(tmp1, tmp1);
9279 addq(result, tmp1);
9280 shrq(result);
9281 jmpb(DONE);
9282 }
9283
9284 bind(VECTOR16_NOT_EQUAL);
9285 if (UseAVX >= 2) {
9286 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit);
9287 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit);
9288 pxor(rymm0, rymm2);
9289 } else {
9290 pcmpeqb(rymm2, rymm2);
9291 pxor(rymm0, rymm1);
9292 pcmpeqb(rymm0, rymm1);
9293 pxor(rymm0, rymm2);
9294 }
9295 pmovmskb(tmp1, rymm0);
9296 bsfq(tmp1, tmp1);
9297 addq(result, tmp1);
9298 shrq(result);
9299 jmpb(DONE);
9300
9301 bind(VECTOR8_NOT_EQUAL);
9302 bind(VECTOR4_NOT_EQUAL);
9303 bsfq(tmp1, tmp1);
9304 shrq(tmp1, 3);
9305 addq(result, tmp1);
9306 bind(BYTES_NOT_EQUAL);
9307 shrq(result);
9308 jmpb(DONE);
9309
9310 bind(SAME_TILL_END);
9311 mov64(result, -1);
9312
9313 bind(DONE);
9314 }
9315
9316 //Helper functions for square_to_len()
9317
9318 /**
9319 * Store the squares of x[], right shifted one bit (divided by 2) into z[]
9320 * Preserves x and z and modifies rest of the registers.
9321 */
9322 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
9323 // Perform square and right shift by 1
9324 // Handle odd xlen case first, then for even xlen do the following
9325 // jlong carry = 0;
9326 // for (int j=0, i=0; j < xlen; j+=2, i+=4) {
9327 // huge_128 product = x[j:j+1] * x[j:j+1];
9328 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65);
9329 // z[i+2:i+3] = (jlong)(product >>> 1);
9330 // carry = (jlong)product;
9331 // }
9332
9333 xorq(tmp5, tmp5); // carry
9334 xorq(rdxReg, rdxReg);
9335 xorl(tmp1, tmp1); // index for x
9336 xorl(tmp4, tmp4); // index for z
9337
9338 Label L_first_loop, L_first_loop_exit;
9339
9340 testl(xlen, 1);
9341 jccb(Assembler::zero, L_first_loop); //jump if xlen is even
9342
9343 // Square and right shift by 1 the odd element using 32 bit multiply
9344 movl(raxReg, Address(x, tmp1, Address::times_4, 0));
9345 imulq(raxReg, raxReg);
9346 shrq(raxReg, 1);
9347 adcq(tmp5, 0);
9348 movq(Address(z, tmp4, Address::times_4, 0), raxReg);
9349 incrementl(tmp1);
9350 addl(tmp4, 2);
9351
9352 // Square and right shift by 1 the rest using 64 bit multiply
9353 bind(L_first_loop);
9354 cmpptr(tmp1, xlen);
9355 jccb(Assembler::equal, L_first_loop_exit);
9356
9357 // Square
9358 movq(raxReg, Address(x, tmp1, Address::times_4, 0));
9359 rorq(raxReg, 32); // convert big-endian to little-endian
9360 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax
9361
9362 // Right shift by 1 and save carry
9363 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1
9364 rcrq(rdxReg, 1);
9365 rcrq(raxReg, 1);
9366 adcq(tmp5, 0);
9367
9368 // Store result in z
9369 movq(Address(z, tmp4, Address::times_4, 0), rdxReg);
9370 movq(Address(z, tmp4, Address::times_4, 8), raxReg);
9371
9372 // Update indices for x and z
9373 addl(tmp1, 2);
9374 addl(tmp4, 4);
9375 jmp(L_first_loop);
9376
9377 bind(L_first_loop_exit);
9378 }
9379
9380
9381 /**
9382 * Perform the following multiply add operation using BMI2 instructions
9383 * carry:sum = sum + op1*op2 + carry
9384 * op2 should be in rdx
9385 * op2 is preserved, all other registers are modified
9386 */
9387 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) {
9388 // assert op2 is rdx
9389 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1
9390 addq(sum, carry);
9391 adcq(tmp2, 0);
9392 addq(sum, op1);
9393 adcq(tmp2, 0);
9394 movq(carry, tmp2);
9395 }
9396
9397 /**
9398 * Perform the following multiply add operation:
9399 * carry:sum = sum + op1*op2 + carry
9400 * Preserves op1, op2 and modifies rest of registers
9401 */
9402 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) {
9403 // rdx:rax = op1 * op2
9404 movq(raxReg, op2);
9405 mulq(op1);
9406
9407 // rdx:rax = sum + carry + rdx:rax
9408 addq(sum, carry);
9409 adcq(rdxReg, 0);
9410 addq(sum, raxReg);
9411 adcq(rdxReg, 0);
9412
9413 // carry:sum = rdx:sum
9414 movq(carry, rdxReg);
9415 }
9416
9417 /**
9418 * Add 64 bit long carry into z[] with carry propogation.
9419 * Preserves z and carry register values and modifies rest of registers.
9420 *
9421 */
9422 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) {
9423 Label L_fourth_loop, L_fourth_loop_exit;
9424
9425 movl(tmp1, 1);
9426 subl(zlen, 2);
9427 addq(Address(z, zlen, Address::times_4, 0), carry);
9428
9429 bind(L_fourth_loop);
9430 jccb(Assembler::carryClear, L_fourth_loop_exit);
9431 subl(zlen, 2);
9432 jccb(Assembler::negative, L_fourth_loop_exit);
9433 addq(Address(z, zlen, Address::times_4, 0), tmp1);
9434 jmp(L_fourth_loop);
9435 bind(L_fourth_loop_exit);
9436 }
9437
9438 /**
9439 * Shift z[] left by 1 bit.
9440 * Preserves x, len, z and zlen registers and modifies rest of the registers.
9441 *
9442 */
9443 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
9444
9445 Label L_fifth_loop, L_fifth_loop_exit;
9446
9447 // Fifth loop
9448 // Perform primitiveLeftShift(z, zlen, 1)
9449
9450 const Register prev_carry = tmp1;
9451 const Register new_carry = tmp4;
9452 const Register value = tmp2;
9453 const Register zidx = tmp3;
9454
9455 // int zidx, carry;
9456 // long value;
9457 // carry = 0;
9458 // for (zidx = zlen-2; zidx >=0; zidx -= 2) {
9459 // (carry:value) = (z[i] << 1) | carry ;
9460 // z[i] = value;
9461 // }
9462
9463 movl(zidx, zlen);
9464 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register
9465
9466 bind(L_fifth_loop);
9467 decl(zidx); // Use decl to preserve carry flag
9468 decl(zidx);
9469 jccb(Assembler::negative, L_fifth_loop_exit);
9470
9471 if (UseBMI2Instructions) {
9472 movq(value, Address(z, zidx, Address::times_4, 0));
9473 rclq(value, 1);
9474 rorxq(value, value, 32);
9475 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
9476 }
9477 else {
9478 // clear new_carry
9479 xorl(new_carry, new_carry);
9480
9481 // Shift z[i] by 1, or in previous carry and save new carry
9482 movq(value, Address(z, zidx, Address::times_4, 0));
9483 shlq(value, 1);
9484 adcl(new_carry, 0);
9485
9486 orq(value, prev_carry);
9487 rorq(value, 0x20);
9488 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
9489
9490 // Set previous carry = new carry
9491 movl(prev_carry, new_carry);
9492 }
9493 jmp(L_fifth_loop);
9494
9495 bind(L_fifth_loop_exit);
9496 }
9497
9498
9499 /**
9500 * Code for BigInteger::squareToLen() intrinsic
9501 *
9502 * rdi: x
9503 * rsi: len
9504 * r8: z
9505 * rcx: zlen
9506 * r12: tmp1
9507 * r13: tmp2
9508 * r14: tmp3
9509 * r15: tmp4
9510 * rbx: tmp5
9511 *
9512 */
9513 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
9514
9515 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, fifth_loop, fifth_loop_exit, L_last_x, L_multiply;
9516 push(tmp1);
9517 push(tmp2);
9518 push(tmp3);
9519 push(tmp4);
9520 push(tmp5);
9521
9522 // First loop
9523 // Store the squares, right shifted one bit (i.e., divided by 2).
9524 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg);
9525
9526 // Add in off-diagonal sums.
9527 //
9528 // Second, third (nested) and fourth loops.
9529 // zlen +=2;
9530 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) {
9531 // carry = 0;
9532 // long op2 = x[xidx:xidx+1];
9533 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) {
9534 // k -= 2;
9535 // long op1 = x[j:j+1];
9536 // long sum = z[k:k+1];
9537 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs);
9538 // z[k:k+1] = sum;
9539 // }
9540 // add_one_64(z, k, carry, tmp_regs);
9541 // }
9542
9543 const Register carry = tmp5;
9544 const Register sum = tmp3;
9545 const Register op1 = tmp4;
9546 Register op2 = tmp2;
9547
9548 push(zlen);
9549 push(len);
9550 addl(zlen,2);
9551 bind(L_second_loop);
9552 xorq(carry, carry);
9553 subl(zlen, 4);
9554 subl(len, 2);
9555 push(zlen);
9556 push(len);
9557 cmpl(len, 0);
9558 jccb(Assembler::lessEqual, L_second_loop_exit);
9559
9560 // Multiply an array by one 64 bit long.
9561 if (UseBMI2Instructions) {
9562 op2 = rdxReg;
9563 movq(op2, Address(x, len, Address::times_4, 0));
9564 rorxq(op2, op2, 32);
9565 }
9566 else {
9567 movq(op2, Address(x, len, Address::times_4, 0));
9568 rorq(op2, 32);
9569 }
9570
9571 bind(L_third_loop);
9572 decrementl(len);
9573 jccb(Assembler::negative, L_third_loop_exit);
9574 decrementl(len);
9575 jccb(Assembler::negative, L_last_x);
9576
9577 movq(op1, Address(x, len, Address::times_4, 0));
9578 rorq(op1, 32);
9579
9580 bind(L_multiply);
9581 subl(zlen, 2);
9582 movq(sum, Address(z, zlen, Address::times_4, 0));
9583
9584 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry.
9585 if (UseBMI2Instructions) {
9586 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2);
9587 }
9588 else {
9589 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
9590 }
9591
9592 movq(Address(z, zlen, Address::times_4, 0), sum);
9593
9594 jmp(L_third_loop);
9595 bind(L_third_loop_exit);
9596
9597 // Fourth loop
9598 // Add 64 bit long carry into z with carry propogation.
9599 // Uses offsetted zlen.
9600 add_one_64(z, zlen, carry, tmp1);
9601
9602 pop(len);
9603 pop(zlen);
9604 jmp(L_second_loop);
9605
9606 // Next infrequent code is moved outside loops.
9607 bind(L_last_x);
9608 movl(op1, Address(x, 0));
9609 jmp(L_multiply);
9610
9611 bind(L_second_loop_exit);
9612 pop(len);
9613 pop(zlen);
9614 pop(len);
9615 pop(zlen);
9616
9617 // Fifth loop
9618 // Shift z left 1 bit.
9619 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4);
9620
9621 // z[zlen-1] |= x[len-1] & 1;
9622 movl(tmp3, Address(x, len, Address::times_4, -4));
9623 andl(tmp3, 1);
9624 orl(Address(z, zlen, Address::times_4, -4), tmp3);
9625
9626 pop(tmp5);
9627 pop(tmp4);
9628 pop(tmp3);
9629 pop(tmp2);
9630 pop(tmp1);
9631 }
9632
9633 /**
9634 * Helper function for mul_add()
9635 * Multiply the in[] by int k and add to out[] starting at offset offs using
9636 * 128 bit by 32 bit multiply and return the carry in tmp5.
9637 * Only quad int aligned length of in[] is operated on in this function.
9638 * k is in rdxReg for BMI2Instructions, for others it is in tmp2.
9639 * This function preserves out, in and k registers.
9640 * len and offset point to the appropriate index in "in" & "out" correspondingly
9641 * tmp5 has the carry.
9642 * other registers are temporary and are modified.
9643 *
9644 */
9645 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in,
9646 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3,
9647 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
9648
9649 Label L_first_loop, L_first_loop_exit;
9650
9651 movl(tmp1, len);
9652 shrl(tmp1, 2);
9653
9654 bind(L_first_loop);
9655 subl(tmp1, 1);
9656 jccb(Assembler::negative, L_first_loop_exit);
9657
9658 subl(len, 4);
9659 subl(offset, 4);
9660
9661 Register op2 = tmp2;
9662 const Register sum = tmp3;
9663 const Register op1 = tmp4;
9664 const Register carry = tmp5;
9665
9666 if (UseBMI2Instructions) {
9667 op2 = rdxReg;
9668 }
9669
9670 movq(op1, Address(in, len, Address::times_4, 8));
9671 rorq(op1, 32);
9672 movq(sum, Address(out, offset, Address::times_4, 8));
9673 rorq(sum, 32);
9674 if (UseBMI2Instructions) {
9675 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
9676 }
9677 else {
9678 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
9679 }
9680 // Store back in big endian from little endian
9681 rorq(sum, 0x20);
9682 movq(Address(out, offset, Address::times_4, 8), sum);
9683
9684 movq(op1, Address(in, len, Address::times_4, 0));
9685 rorq(op1, 32);
9686 movq(sum, Address(out, offset, Address::times_4, 0));
9687 rorq(sum, 32);
9688 if (UseBMI2Instructions) {
9689 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
9690 }
9691 else {
9692 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
9693 }
9694 // Store back in big endian from little endian
9695 rorq(sum, 0x20);
9696 movq(Address(out, offset, Address::times_4, 0), sum);
9697
9698 jmp(L_first_loop);
9699 bind(L_first_loop_exit);
9700 }
9701
9702 /**
9703 * Code for BigInteger::mulAdd() intrinsic
9704 *
9705 * rdi: out
9706 * rsi: in
9707 * r11: offs (out.length - offset)
9708 * rcx: len
9709 * r8: k
9710 * r12: tmp1
9711 * r13: tmp2
9712 * r14: tmp3
9713 * r15: tmp4
9714 * rbx: tmp5
9715 * Multiply the in[] by word k and add to out[], return the carry in rax
9716 */
9717 void MacroAssembler::mul_add(Register out, Register in, Register offs,
9718 Register len, Register k, Register tmp1, Register tmp2, Register tmp3,
9719 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
9720
9721 Label L_carry, L_last_in, L_done;
9722
9723 // carry = 0;
9724 // for (int j=len-1; j >= 0; j--) {
9725 // long product = (in[j] & LONG_MASK) * kLong +
9726 // (out[offs] & LONG_MASK) + carry;
9727 // out[offs--] = (int)product;
9728 // carry = product >>> 32;
9729 // }
9730 //
9731 push(tmp1);
9732 push(tmp2);
9733 push(tmp3);
9734 push(tmp4);
9735 push(tmp5);
9736
9737 Register op2 = tmp2;
9738 const Register sum = tmp3;
9739 const Register op1 = tmp4;
9740 const Register carry = tmp5;
9741
9742 if (UseBMI2Instructions) {
9743 op2 = rdxReg;
9744 movl(op2, k);
9745 }
9746 else {
9747 movl(op2, k);
9748 }
9749
9750 xorq(carry, carry);
9751
9752 //First loop
9753
9754 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply
9755 //The carry is in tmp5
9756 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg);
9757
9758 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any
9759 decrementl(len);
9760 jccb(Assembler::negative, L_carry);
9761 decrementl(len);
9762 jccb(Assembler::negative, L_last_in);
9763
9764 movq(op1, Address(in, len, Address::times_4, 0));
9765 rorq(op1, 32);
9766
9767 subl(offs, 2);
9768 movq(sum, Address(out, offs, Address::times_4, 0));
9769 rorq(sum, 32);
9770
9771 if (UseBMI2Instructions) {
9772 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
9773 }
9774 else {
9775 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
9776 }
9777
9778 // Store back in big endian from little endian
9779 rorq(sum, 0x20);
9780 movq(Address(out, offs, Address::times_4, 0), sum);
9781
9782 testl(len, len);
9783 jccb(Assembler::zero, L_carry);
9784
9785 //Multiply the last in[] entry, if any
9786 bind(L_last_in);
9787 movl(op1, Address(in, 0));
9788 movl(sum, Address(out, offs, Address::times_4, -4));
9789
9790 movl(raxReg, k);
9791 mull(op1); //tmp4 * eax -> edx:eax
9792 addl(sum, carry);
9793 adcl(rdxReg, 0);
9794 addl(sum, raxReg);
9795 adcl(rdxReg, 0);
9796 movl(carry, rdxReg);
9797
9798 movl(Address(out, offs, Address::times_4, -4), sum);
9799
9800 bind(L_carry);
9801 //return tmp5/carry as carry in rax
9802 movl(rax, carry);
9803
9804 bind(L_done);
9805 pop(tmp5);
9806 pop(tmp4);
9807 pop(tmp3);
9808 pop(tmp2);
9809 pop(tmp1);
9810 }
9811 #endif
9812
9813 /**
9814 * Emits code to update CRC-32 with a byte value according to constants in table
9815 *
9816 * @param [in,out]crc Register containing the crc.
9817 * @param [in]val Register containing the byte to fold into the CRC.
9818 * @param [in]table Register containing the table of crc constants.
9819 *
9820 * uint32_t crc;
9821 * val = crc_table[(val ^ crc) & 0xFF];
9822 * crc = val ^ (crc >> 8);
9823 *
9824 */
9825 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
9826 xorl(val, crc);
9827 andl(val, 0xFF);
9828 shrl(crc, 8); // unsigned shift
9829 xorl(crc, Address(table, val, Address::times_4, 0));
9830 }
9831
9832 /**
9833 * Fold four 128-bit data chunks
9834 */
9835 void MacroAssembler::fold_128bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
9836 evpclmulhdq(xtmp, xK, xcrc, Assembler::AVX_512bit); // [123:64]
9837 evpclmulldq(xcrc, xK, xcrc, Assembler::AVX_512bit); // [63:0]
9838 evpxorq(xcrc, xcrc, Address(buf, offset), Assembler::AVX_512bit /* vector_len */);
9839 evpxorq(xcrc, xcrc, xtmp, Assembler::AVX_512bit /* vector_len */);
9840 }
9841
9842 /**
9843 * Fold 128-bit data chunk
9844 */
9845 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
9846 if (UseAVX > 0) {
9847 vpclmulhdq(xtmp, xK, xcrc); // [123:64]
9848 vpclmulldq(xcrc, xK, xcrc); // [63:0]
9849 vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */);
9850 pxor(xcrc, xtmp);
9851 } else {
9852 movdqa(xtmp, xcrc);
9853 pclmulhdq(xtmp, xK); // [123:64]
9854 pclmulldq(xcrc, xK); // [63:0]
9855 pxor(xcrc, xtmp);
9856 movdqu(xtmp, Address(buf, offset));
9857 pxor(xcrc, xtmp);
9858 }
9859 }
9860
9861 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
9862 if (UseAVX > 0) {
9863 vpclmulhdq(xtmp, xK, xcrc);
9864 vpclmulldq(xcrc, xK, xcrc);
9865 pxor(xcrc, xbuf);
9866 pxor(xcrc, xtmp);
9867 } else {
9868 movdqa(xtmp, xcrc);
9869 pclmulhdq(xtmp, xK);
9870 pclmulldq(xcrc, xK);
9871 pxor(xcrc, xbuf);
9872 pxor(xcrc, xtmp);
9873 }
9874 }
9875
9876 /**
9877 * 8-bit folds to compute 32-bit CRC
9878 *
9879 * uint64_t xcrc;
9880 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
9881 */
9882 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
9883 movdl(tmp, xcrc);
9884 andl(tmp, 0xFF);
9885 movdl(xtmp, Address(table, tmp, Address::times_4, 0));
9886 psrldq(xcrc, 1); // unsigned shift one byte
9887 pxor(xcrc, xtmp);
9888 }
9889
9890 /**
9891 * uint32_t crc;
9892 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
9893 */
9894 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
9895 movl(tmp, crc);
9896 andl(tmp, 0xFF);
9897 shrl(crc, 8);
9898 xorl(crc, Address(table, tmp, Address::times_4, 0));
9899 }
9900
9901 /**
9902 * @param crc register containing existing CRC (32-bit)
9903 * @param buf register pointing to input byte buffer (byte*)
9904 * @param len register containing number of bytes
9905 * @param table register that will contain address of CRC table
9906 * @param tmp scratch register
9907 */
9908 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
9909 assert_different_registers(crc, buf, len, table, tmp, rax);
9910
9911 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
9912 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
9913
9914 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
9915 // context for the registers used, where all instructions below are using 128-bit mode
9916 // On EVEX without VL and BW, these instructions will all be AVX.
9917 if (VM_Version::supports_avx512vlbw()) {
9918 movl(tmp, 0xffff);
9919 kmovwl(k1, tmp);
9920 }
9921
9922 lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
9923 notl(crc); // ~crc
9924 cmpl(len, 16);
9925 jcc(Assembler::less, L_tail);
9926
9927 // Align buffer to 16 bytes
9928 movl(tmp, buf);
9929 andl(tmp, 0xF);
9930 jccb(Assembler::zero, L_aligned);
9931 subl(tmp, 16);
9932 addl(len, tmp);
9933
9934 align(4);
9935 BIND(L_align_loop);
9936 movsbl(rax, Address(buf, 0)); // load byte with sign extension
9937 update_byte_crc32(crc, rax, table);
9938 increment(buf);
9939 incrementl(tmp);
9940 jccb(Assembler::less, L_align_loop);
9941
9942 BIND(L_aligned);
9943 movl(tmp, len); // save
9944 shrl(len, 4);
9945 jcc(Assembler::zero, L_tail_restore);
9946
9947 // Fold total 512 bits of polynomial on each iteration
9948 if (VM_Version::supports_vpclmulqdq()) {
9949 Label Parallel_loop, L_No_Parallel;
9950
9951 cmpl(len, 8);
9952 jccb(Assembler::less, L_No_Parallel);
9953
9954 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32));
9955 evmovdquq(xmm1, Address(buf, 0), Assembler::AVX_512bit);
9956 movdl(xmm5, crc);
9957 evpxorq(xmm1, xmm1, xmm5, Assembler::AVX_512bit);
9958 addptr(buf, 64);
9959 subl(len, 7);
9960 evshufi64x2(xmm0, xmm0, xmm0, 0x00, Assembler::AVX_512bit); //propagate the mask from 128 bits to 512 bits
9961
9962 BIND(Parallel_loop);
9963 fold_128bit_crc32_avx512(xmm1, xmm0, xmm5, buf, 0);
9964 addptr(buf, 64);
9965 subl(len, 4);
9966 jcc(Assembler::greater, Parallel_loop);
9967
9968 vextracti64x2(xmm2, xmm1, 0x01);
9969 vextracti64x2(xmm3, xmm1, 0x02);
9970 vextracti64x2(xmm4, xmm1, 0x03);
9971 jmp(L_fold_512b);
9972
9973 BIND(L_No_Parallel);
9974 }
9975 // Fold crc into first bytes of vector
9976 movdqa(xmm1, Address(buf, 0));
9977 movdl(rax, xmm1);
9978 xorl(crc, rax);
9979 if (VM_Version::supports_sse4_1()) {
9980 pinsrd(xmm1, crc, 0);
9981 } else {
9982 pinsrw(xmm1, crc, 0);
9983 shrl(crc, 16);
9984 pinsrw(xmm1, crc, 1);
9985 }
9986 addptr(buf, 16);
9987 subl(len, 4); // len > 0
9988 jcc(Assembler::less, L_fold_tail);
9989
9990 movdqa(xmm2, Address(buf, 0));
9991 movdqa(xmm3, Address(buf, 16));
9992 movdqa(xmm4, Address(buf, 32));
9993 addptr(buf, 48);
9994 subl(len, 3);
9995 jcc(Assembler::lessEqual, L_fold_512b);
9996
9997 // Fold total 512 bits of polynomial on each iteration,
9998 // 128 bits per each of 4 parallel streams.
9999 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32));
10000
10001 align(32);
10002 BIND(L_fold_512b_loop);
10003 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
10004 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
10005 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
10006 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
10007 addptr(buf, 64);
10008 subl(len, 4);
10009 jcc(Assembler::greater, L_fold_512b_loop);
10010
10011 // Fold 512 bits to 128 bits.
10012 BIND(L_fold_512b);
10013 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
10014 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
10015 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
10016 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
10017
10018 // Fold the rest of 128 bits data chunks
10019 BIND(L_fold_tail);
10020 addl(len, 3);
10021 jccb(Assembler::lessEqual, L_fold_128b);
10022 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
10023
10024 BIND(L_fold_tail_loop);
10025 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
10026 addptr(buf, 16);
10027 decrementl(len);
10028 jccb(Assembler::greater, L_fold_tail_loop);
10029
10030 // Fold 128 bits in xmm1 down into 32 bits in crc register.
10031 BIND(L_fold_128b);
10032 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()));
10033 if (UseAVX > 0) {
10034 vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
10035 vpand(xmm3, xmm0, xmm2, 0 /* vector_len */);
10036 vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
10037 } else {
10038 movdqa(xmm2, xmm0);
10039 pclmulqdq(xmm2, xmm1, 0x1);
10040 movdqa(xmm3, xmm0);
10041 pand(xmm3, xmm2);
10042 pclmulqdq(xmm0, xmm3, 0x1);
10043 }
10044 psrldq(xmm1, 8);
10045 psrldq(xmm2, 4);
10046 pxor(xmm0, xmm1);
10047 pxor(xmm0, xmm2);
10048
10049 // 8 8-bit folds to compute 32-bit CRC.
10050 for (int j = 0; j < 4; j++) {
10051 fold_8bit_crc32(xmm0, table, xmm1, rax);
10052 }
10053 movdl(crc, xmm0); // mov 32 bits to general register
10054 for (int j = 0; j < 4; j++) {
10055 fold_8bit_crc32(crc, table, rax);
10056 }
10057
10058 BIND(L_tail_restore);
10059 movl(len, tmp); // restore
10060 BIND(L_tail);
10061 andl(len, 0xf);
10062 jccb(Assembler::zero, L_exit);
10063
10064 // Fold the rest of bytes
10065 align(4);
10066 BIND(L_tail_loop);
10067 movsbl(rax, Address(buf, 0)); // load byte with sign extension
10068 update_byte_crc32(crc, rax, table);
10069 increment(buf);
10070 decrementl(len);
10071 jccb(Assembler::greater, L_tail_loop);
10072
10073 BIND(L_exit);
10074 notl(crc); // ~c
10075 }
10076
10077 #ifdef _LP64
10078 // S. Gueron / Information Processing Letters 112 (2012) 184
10079 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table.
10080 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0].
10081 // Output: the 64-bit carry-less product of B * CONST
10082 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n,
10083 Register tmp1, Register tmp2, Register tmp3) {
10084 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
10085 if (n > 0) {
10086 addq(tmp3, n * 256 * 8);
10087 }
10088 // Q1 = TABLEExt[n][B & 0xFF];
10089 movl(tmp1, in);
10090 andl(tmp1, 0x000000FF);
10091 shll(tmp1, 3);
10092 addq(tmp1, tmp3);
10093 movq(tmp1, Address(tmp1, 0));
10094
10095 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
10096 movl(tmp2, in);
10097 shrl(tmp2, 8);
10098 andl(tmp2, 0x000000FF);
10099 shll(tmp2, 3);
10100 addq(tmp2, tmp3);
10101 movq(tmp2, Address(tmp2, 0));
10102
10103 shlq(tmp2, 8);
10104 xorq(tmp1, tmp2);
10105
10106 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
10107 movl(tmp2, in);
10108 shrl(tmp2, 16);
10109 andl(tmp2, 0x000000FF);
10110 shll(tmp2, 3);
10111 addq(tmp2, tmp3);
10112 movq(tmp2, Address(tmp2, 0));
10113
10114 shlq(tmp2, 16);
10115 xorq(tmp1, tmp2);
10116
10117 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
10118 shrl(in, 24);
10119 andl(in, 0x000000FF);
10120 shll(in, 3);
10121 addq(in, tmp3);
10122 movq(in, Address(in, 0));
10123
10124 shlq(in, 24);
10125 xorq(in, tmp1);
10126 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
10127 }
10128
10129 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
10130 Register in_out,
10131 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
10132 XMMRegister w_xtmp2,
10133 Register tmp1,
10134 Register n_tmp2, Register n_tmp3) {
10135 if (is_pclmulqdq_supported) {
10136 movdl(w_xtmp1, in_out); // modified blindly
10137
10138 movl(tmp1, const_or_pre_comp_const_index);
10139 movdl(w_xtmp2, tmp1);
10140 pclmulqdq(w_xtmp1, w_xtmp2, 0);
10141
10142 movdq(in_out, w_xtmp1);
10143 } else {
10144 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3);
10145 }
10146 }
10147
10148 // Recombination Alternative 2: No bit-reflections
10149 // T1 = (CRC_A * U1) << 1
10150 // T2 = (CRC_B * U2) << 1
10151 // C1 = T1 >> 32
10152 // C2 = T2 >> 32
10153 // T1 = T1 & 0xFFFFFFFF
10154 // T2 = T2 & 0xFFFFFFFF
10155 // T1 = CRC32(0, T1)
10156 // T2 = CRC32(0, T2)
10157 // C1 = C1 ^ T1
10158 // C2 = C2 ^ T2
10159 // CRC = C1 ^ C2 ^ CRC_C
10160 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
10161 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10162 Register tmp1, Register tmp2,
10163 Register n_tmp3) {
10164 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
10165 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
10166 shlq(in_out, 1);
10167 movl(tmp1, in_out);
10168 shrq(in_out, 32);
10169 xorl(tmp2, tmp2);
10170 crc32(tmp2, tmp1, 4);
10171 xorl(in_out, tmp2); // we don't care about upper 32 bit contents here
10172 shlq(in1, 1);
10173 movl(tmp1, in1);
10174 shrq(in1, 32);
10175 xorl(tmp2, tmp2);
10176 crc32(tmp2, tmp1, 4);
10177 xorl(in1, tmp2);
10178 xorl(in_out, in1);
10179 xorl(in_out, in2);
10180 }
10181
10182 // Set N to predefined value
10183 // Subtract from a lenght of a buffer
10184 // execute in a loop:
10185 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0
10186 // for i = 1 to N do
10187 // CRC_A = CRC32(CRC_A, A[i])
10188 // CRC_B = CRC32(CRC_B, B[i])
10189 // CRC_C = CRC32(CRC_C, C[i])
10190 // end for
10191 // Recombine
10192 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
10193 Register in_out1, Register in_out2, Register in_out3,
10194 Register tmp1, Register tmp2, Register tmp3,
10195 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10196 Register tmp4, Register tmp5,
10197 Register n_tmp6) {
10198 Label L_processPartitions;
10199 Label L_processPartition;
10200 Label L_exit;
10201
10202 bind(L_processPartitions);
10203 cmpl(in_out1, 3 * size);
10204 jcc(Assembler::less, L_exit);
10205 xorl(tmp1, tmp1);
10206 xorl(tmp2, tmp2);
10207 movq(tmp3, in_out2);
10208 addq(tmp3, size);
10209
10210 bind(L_processPartition);
10211 crc32(in_out3, Address(in_out2, 0), 8);
10212 crc32(tmp1, Address(in_out2, size), 8);
10213 crc32(tmp2, Address(in_out2, size * 2), 8);
10214 addq(in_out2, 8);
10215 cmpq(in_out2, tmp3);
10216 jcc(Assembler::less, L_processPartition);
10217 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
10218 w_xtmp1, w_xtmp2, w_xtmp3,
10219 tmp4, tmp5,
10220 n_tmp6);
10221 addq(in_out2, 2 * size);
10222 subl(in_out1, 3 * size);
10223 jmp(L_processPartitions);
10224
10225 bind(L_exit);
10226 }
10227 #else
10228 void MacroAssembler::crc32c_ipl_alg4(Register in_out, uint32_t n,
10229 Register tmp1, Register tmp2, Register tmp3,
10230 XMMRegister xtmp1, XMMRegister xtmp2) {
10231 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
10232 if (n > 0) {
10233 addl(tmp3, n * 256 * 8);
10234 }
10235 // Q1 = TABLEExt[n][B & 0xFF];
10236 movl(tmp1, in_out);
10237 andl(tmp1, 0x000000FF);
10238 shll(tmp1, 3);
10239 addl(tmp1, tmp3);
10240 movq(xtmp1, Address(tmp1, 0));
10241
10242 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
10243 movl(tmp2, in_out);
10244 shrl(tmp2, 8);
10245 andl(tmp2, 0x000000FF);
10246 shll(tmp2, 3);
10247 addl(tmp2, tmp3);
10248 movq(xtmp2, Address(tmp2, 0));
10249
10250 psllq(xtmp2, 8);
10251 pxor(xtmp1, xtmp2);
10252
10253 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
10254 movl(tmp2, in_out);
10255 shrl(tmp2, 16);
10256 andl(tmp2, 0x000000FF);
10257 shll(tmp2, 3);
10258 addl(tmp2, tmp3);
10259 movq(xtmp2, Address(tmp2, 0));
10260
10261 psllq(xtmp2, 16);
10262 pxor(xtmp1, xtmp2);
10263
10264 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
10265 shrl(in_out, 24);
10266 andl(in_out, 0x000000FF);
10267 shll(in_out, 3);
10268 addl(in_out, tmp3);
10269 movq(xtmp2, Address(in_out, 0));
10270
10271 psllq(xtmp2, 24);
10272 pxor(xtmp1, xtmp2); // Result in CXMM
10273 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
10274 }
10275
10276 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
10277 Register in_out,
10278 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
10279 XMMRegister w_xtmp2,
10280 Register tmp1,
10281 Register n_tmp2, Register n_tmp3) {
10282 if (is_pclmulqdq_supported) {
10283 movdl(w_xtmp1, in_out);
10284
10285 movl(tmp1, const_or_pre_comp_const_index);
10286 movdl(w_xtmp2, tmp1);
10287 pclmulqdq(w_xtmp1, w_xtmp2, 0);
10288 // Keep result in XMM since GPR is 32 bit in length
10289 } else {
10290 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3, w_xtmp1, w_xtmp2);
10291 }
10292 }
10293
10294 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
10295 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10296 Register tmp1, Register tmp2,
10297 Register n_tmp3) {
10298 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
10299 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
10300
10301 psllq(w_xtmp1, 1);
10302 movdl(tmp1, w_xtmp1);
10303 psrlq(w_xtmp1, 32);
10304 movdl(in_out, w_xtmp1);
10305
10306 xorl(tmp2, tmp2);
10307 crc32(tmp2, tmp1, 4);
10308 xorl(in_out, tmp2);
10309
10310 psllq(w_xtmp2, 1);
10311 movdl(tmp1, w_xtmp2);
10312 psrlq(w_xtmp2, 32);
10313 movdl(in1, w_xtmp2);
10314
10315 xorl(tmp2, tmp2);
10316 crc32(tmp2, tmp1, 4);
10317 xorl(in1, tmp2);
10318 xorl(in_out, in1);
10319 xorl(in_out, in2);
10320 }
10321
10322 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
10323 Register in_out1, Register in_out2, Register in_out3,
10324 Register tmp1, Register tmp2, Register tmp3,
10325 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10326 Register tmp4, Register tmp5,
10327 Register n_tmp6) {
10328 Label L_processPartitions;
10329 Label L_processPartition;
10330 Label L_exit;
10331
10332 bind(L_processPartitions);
10333 cmpl(in_out1, 3 * size);
10334 jcc(Assembler::less, L_exit);
10335 xorl(tmp1, tmp1);
10336 xorl(tmp2, tmp2);
10337 movl(tmp3, in_out2);
10338 addl(tmp3, size);
10339
10340 bind(L_processPartition);
10341 crc32(in_out3, Address(in_out2, 0), 4);
10342 crc32(tmp1, Address(in_out2, size), 4);
10343 crc32(tmp2, Address(in_out2, size*2), 4);
10344 crc32(in_out3, Address(in_out2, 0+4), 4);
10345 crc32(tmp1, Address(in_out2, size+4), 4);
10346 crc32(tmp2, Address(in_out2, size*2+4), 4);
10347 addl(in_out2, 8);
10348 cmpl(in_out2, tmp3);
10349 jcc(Assembler::less, L_processPartition);
10350
10351 push(tmp3);
10352 push(in_out1);
10353 push(in_out2);
10354 tmp4 = tmp3;
10355 tmp5 = in_out1;
10356 n_tmp6 = in_out2;
10357
10358 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
10359 w_xtmp1, w_xtmp2, w_xtmp3,
10360 tmp4, tmp5,
10361 n_tmp6);
10362
10363 pop(in_out2);
10364 pop(in_out1);
10365 pop(tmp3);
10366
10367 addl(in_out2, 2 * size);
10368 subl(in_out1, 3 * size);
10369 jmp(L_processPartitions);
10370
10371 bind(L_exit);
10372 }
10373 #endif //LP64
10374
10375 #ifdef _LP64
10376 // Algorithm 2: Pipelined usage of the CRC32 instruction.
10377 // Input: A buffer I of L bytes.
10378 // Output: the CRC32C value of the buffer.
10379 // Notations:
10380 // Write L = 24N + r, with N = floor (L/24).
10381 // r = L mod 24 (0 <= r < 24).
10382 // Consider I as the concatenation of A|B|C|R, where A, B, C, each,
10383 // N quadwords, and R consists of r bytes.
10384 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1
10385 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1
10386 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1
10387 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1
10388 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
10389 Register tmp1, Register tmp2, Register tmp3,
10390 Register tmp4, Register tmp5, Register tmp6,
10391 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10392 bool is_pclmulqdq_supported) {
10393 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
10394 Label L_wordByWord;
10395 Label L_byteByByteProlog;
10396 Label L_byteByByte;
10397 Label L_exit;
10398
10399 if (is_pclmulqdq_supported ) {
10400 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
10401 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr+1);
10402
10403 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
10404 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
10405
10406 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
10407 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
10408 assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\"");
10409 } else {
10410 const_or_pre_comp_const_index[0] = 1;
10411 const_or_pre_comp_const_index[1] = 0;
10412
10413 const_or_pre_comp_const_index[2] = 3;
10414 const_or_pre_comp_const_index[3] = 2;
10415
10416 const_or_pre_comp_const_index[4] = 5;
10417 const_or_pre_comp_const_index[5] = 4;
10418 }
10419 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
10420 in2, in1, in_out,
10421 tmp1, tmp2, tmp3,
10422 w_xtmp1, w_xtmp2, w_xtmp3,
10423 tmp4, tmp5,
10424 tmp6);
10425 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
10426 in2, in1, in_out,
10427 tmp1, tmp2, tmp3,
10428 w_xtmp1, w_xtmp2, w_xtmp3,
10429 tmp4, tmp5,
10430 tmp6);
10431 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
10432 in2, in1, in_out,
10433 tmp1, tmp2, tmp3,
10434 w_xtmp1, w_xtmp2, w_xtmp3,
10435 tmp4, tmp5,
10436 tmp6);
10437 movl(tmp1, in2);
10438 andl(tmp1, 0x00000007);
10439 negl(tmp1);
10440 addl(tmp1, in2);
10441 addq(tmp1, in1);
10442
10443 BIND(L_wordByWord);
10444 cmpq(in1, tmp1);
10445 jcc(Assembler::greaterEqual, L_byteByByteProlog);
10446 crc32(in_out, Address(in1, 0), 4);
10447 addq(in1, 4);
10448 jmp(L_wordByWord);
10449
10450 BIND(L_byteByByteProlog);
10451 andl(in2, 0x00000007);
10452 movl(tmp2, 1);
10453
10454 BIND(L_byteByByte);
10455 cmpl(tmp2, in2);
10456 jccb(Assembler::greater, L_exit);
10457 crc32(in_out, Address(in1, 0), 1);
10458 incq(in1);
10459 incl(tmp2);
10460 jmp(L_byteByByte);
10461
10462 BIND(L_exit);
10463 }
10464 #else
10465 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
10466 Register tmp1, Register tmp2, Register tmp3,
10467 Register tmp4, Register tmp5, Register tmp6,
10468 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10469 bool is_pclmulqdq_supported) {
10470 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
10471 Label L_wordByWord;
10472 Label L_byteByByteProlog;
10473 Label L_byteByByte;
10474 Label L_exit;
10475
10476 if (is_pclmulqdq_supported) {
10477 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
10478 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 1);
10479
10480 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
10481 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
10482
10483 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
10484 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
10485 } else {
10486 const_or_pre_comp_const_index[0] = 1;
10487 const_or_pre_comp_const_index[1] = 0;
10488
10489 const_or_pre_comp_const_index[2] = 3;
10490 const_or_pre_comp_const_index[3] = 2;
10491
10492 const_or_pre_comp_const_index[4] = 5;
10493 const_or_pre_comp_const_index[5] = 4;
10494 }
10495 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
10496 in2, in1, in_out,
10497 tmp1, tmp2, tmp3,
10498 w_xtmp1, w_xtmp2, w_xtmp3,
10499 tmp4, tmp5,
10500 tmp6);
10501 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
10502 in2, in1, in_out,
10503 tmp1, tmp2, tmp3,
10504 w_xtmp1, w_xtmp2, w_xtmp3,
10505 tmp4, tmp5,
10506 tmp6);
10507 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
10508 in2, in1, in_out,
10509 tmp1, tmp2, tmp3,
10510 w_xtmp1, w_xtmp2, w_xtmp3,
10511 tmp4, tmp5,
10512 tmp6);
10513 movl(tmp1, in2);
10514 andl(tmp1, 0x00000007);
10515 negl(tmp1);
10516 addl(tmp1, in2);
10517 addl(tmp1, in1);
10518
10519 BIND(L_wordByWord);
10520 cmpl(in1, tmp1);
10521 jcc(Assembler::greaterEqual, L_byteByByteProlog);
10522 crc32(in_out, Address(in1,0), 4);
10523 addl(in1, 4);
10524 jmp(L_wordByWord);
10525
10526 BIND(L_byteByByteProlog);
10527 andl(in2, 0x00000007);
10528 movl(tmp2, 1);
10529
10530 BIND(L_byteByByte);
10531 cmpl(tmp2, in2);
10532 jccb(Assembler::greater, L_exit);
10533 movb(tmp1, Address(in1, 0));
10534 crc32(in_out, tmp1, 1);
10535 incl(in1);
10536 incl(tmp2);
10537 jmp(L_byteByByte);
10538
10539 BIND(L_exit);
10540 }
10541 #endif // LP64
10542 #undef BIND
10543 #undef BLOCK_COMMENT
10544
10545 // Compress char[] array to byte[].
10546 // ..\jdk\src\java.base\share\classes\java\lang\StringUTF16.java
10547 // @HotSpotIntrinsicCandidate
10548 // private static int compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) {
10549 // for (int i = 0; i < len; i++) {
10550 // int c = src[srcOff++];
10551 // if (c >>> 8 != 0) {
10552 // return 0;
10553 // }
10554 // dst[dstOff++] = (byte)c;
10555 // }
10556 // return len;
10557 // }
10558 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
10559 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
10560 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
10561 Register tmp5, Register result) {
10562 Label copy_chars_loop, return_length, return_zero, done, below_threshold;
10563
10564 // rsi: src
10565 // rdi: dst
10566 // rdx: len
10567 // rcx: tmp5
10568 // rax: result
10569
10570 // rsi holds start addr of source char[] to be compressed
10571 // rdi holds start addr of destination byte[]
10572 // rdx holds length
10573
10574 assert(len != result, "");
10575
10576 // save length for return
10577 push(len);
10578
10579 if ((UseAVX > 2) && // AVX512
10580 VM_Version::supports_avx512vlbw() &&
10581 VM_Version::supports_bmi2()) {
10582
10583 set_vector_masking(); // opening of the stub context for programming mask registers
10584
10585 Label copy_32_loop, copy_loop_tail, restore_k1_return_zero;
10586
10587 // alignement
10588 Label post_alignement;
10589
10590 // if length of the string is less than 16, handle it in an old fashioned
10591 // way
10592 testl(len, -32);
10593 jcc(Assembler::zero, below_threshold);
10594
10595 // First check whether a character is compressable ( <= 0xFF).
10596 // Create mask to test for Unicode chars inside zmm vector
10597 movl(result, 0x00FF);
10598 evpbroadcastw(tmp2Reg, result, Assembler::AVX_512bit);
10599
10600 // Save k1
10601 kmovql(k3, k1);
10602
10603 testl(len, -64);
10604 jcc(Assembler::zero, post_alignement);
10605
10606 movl(tmp5, dst);
10607 andl(tmp5, (32 - 1));
10608 negl(tmp5);
10609 andl(tmp5, (32 - 1));
10610
10611 // bail out when there is nothing to be done
10612 testl(tmp5, 0xFFFFFFFF);
10613 jcc(Assembler::zero, post_alignement);
10614
10615 // ~(~0 << len), where len is the # of remaining elements to process
10616 movl(result, 0xFFFFFFFF);
10617 shlxl(result, result, tmp5);
10618 notl(result);
10619 kmovdl(k1, result);
10620
10621 evmovdquw(tmp1Reg, k1, Address(src, 0), Assembler::AVX_512bit);
10622 evpcmpuw(k2, k1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
10623 ktestd(k2, k1);
10624 jcc(Assembler::carryClear, restore_k1_return_zero);
10625
10626 evpmovwb(Address(dst, 0), k1, tmp1Reg, Assembler::AVX_512bit);
10627
10628 addptr(src, tmp5);
10629 addptr(src, tmp5);
10630 addptr(dst, tmp5);
10631 subl(len, tmp5);
10632
10633 bind(post_alignement);
10634 // end of alignement
10635
10636 movl(tmp5, len);
10637 andl(tmp5, (32 - 1)); // tail count (in chars)
10638 andl(len, ~(32 - 1)); // vector count (in chars)
10639 jcc(Assembler::zero, copy_loop_tail);
10640
10641 lea(src, Address(src, len, Address::times_2));
10642 lea(dst, Address(dst, len, Address::times_1));
10643 negptr(len);
10644
10645 bind(copy_32_loop);
10646 evmovdquw(tmp1Reg, Address(src, len, Address::times_2), Assembler::AVX_512bit);
10647 evpcmpuw(k2, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
10648 kortestdl(k2, k2);
10649 jcc(Assembler::carryClear, restore_k1_return_zero);
10650
10651 // All elements in current processed chunk are valid candidates for
10652 // compression. Write a truncated byte elements to the memory.
10653 evpmovwb(Address(dst, len, Address::times_1), tmp1Reg, Assembler::AVX_512bit);
10654 addptr(len, 32);
10655 jcc(Assembler::notZero, copy_32_loop);
10656
10657 bind(copy_loop_tail);
10658 // bail out when there is nothing to be done
10659 testl(tmp5, 0xFFFFFFFF);
10660 // Restore k1
10661 kmovql(k1, k3);
10662 jcc(Assembler::zero, return_length);
10663
10664 movl(len, tmp5);
10665
10666 // ~(~0 << len), where len is the # of remaining elements to process
10667 movl(result, 0xFFFFFFFF);
10668 shlxl(result, result, len);
10669 notl(result);
10670
10671 kmovdl(k1, result);
10672
10673 evmovdquw(tmp1Reg, k1, Address(src, 0), Assembler::AVX_512bit);
10674 evpcmpuw(k2, k1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
10675 ktestd(k2, k1);
10676 jcc(Assembler::carryClear, restore_k1_return_zero);
10677
10678 evpmovwb(Address(dst, 0), k1, tmp1Reg, Assembler::AVX_512bit);
10679 // Restore k1
10680 kmovql(k1, k3);
10681 jmp(return_length);
10682
10683 bind(restore_k1_return_zero);
10684 // Restore k1
10685 kmovql(k1, k3);
10686 jmp(return_zero);
10687
10688 clear_vector_masking(); // closing of the stub context for programming mask registers
10689 }
10690 if (UseSSE42Intrinsics) {
10691 Label copy_32_loop, copy_16, copy_tail;
10692
10693 bind(below_threshold);
10694
10695 movl(result, len);
10696
10697 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vectors
10698
10699 // vectored compression
10700 andl(len, 0xfffffff0); // vector count (in chars)
10701 andl(result, 0x0000000f); // tail count (in chars)
10702 testl(len, len);
10703 jccb(Assembler::zero, copy_16);
10704
10705 // compress 16 chars per iter
10706 movdl(tmp1Reg, tmp5);
10707 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
10708 pxor(tmp4Reg, tmp4Reg);
10709
10710 lea(src, Address(src, len, Address::times_2));
10711 lea(dst, Address(dst, len, Address::times_1));
10712 negptr(len);
10713
10714 bind(copy_32_loop);
10715 movdqu(tmp2Reg, Address(src, len, Address::times_2)); // load 1st 8 characters
10716 por(tmp4Reg, tmp2Reg);
10717 movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters
10718 por(tmp4Reg, tmp3Reg);
10719 ptest(tmp4Reg, tmp1Reg); // check for Unicode chars in next vector
10720 jcc(Assembler::notZero, return_zero);
10721 packuswb(tmp2Reg, tmp3Reg); // only ASCII chars; compress each to 1 byte
10722 movdqu(Address(dst, len, Address::times_1), tmp2Reg);
10723 addptr(len, 16);
10724 jcc(Assembler::notZero, copy_32_loop);
10725
10726 // compress next vector of 8 chars (if any)
10727 bind(copy_16);
10728 movl(len, result);
10729 andl(len, 0xfffffff8); // vector count (in chars)
10730 andl(result, 0x00000007); // tail count (in chars)
10731 testl(len, len);
10732 jccb(Assembler::zero, copy_tail);
10733
10734 movdl(tmp1Reg, tmp5);
10735 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
10736 pxor(tmp3Reg, tmp3Reg);
10737
10738 movdqu(tmp2Reg, Address(src, 0));
10739 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
10740 jccb(Assembler::notZero, return_zero);
10741 packuswb(tmp2Reg, tmp3Reg); // only LATIN1 chars; compress each to 1 byte
10742 movq(Address(dst, 0), tmp2Reg);
10743 addptr(src, 16);
10744 addptr(dst, 8);
10745
10746 bind(copy_tail);
10747 movl(len, result);
10748 }
10749 // compress 1 char per iter
10750 testl(len, len);
10751 jccb(Assembler::zero, return_length);
10752 lea(src, Address(src, len, Address::times_2));
10753 lea(dst, Address(dst, len, Address::times_1));
10754 negptr(len);
10755
10756 bind(copy_chars_loop);
10757 load_unsigned_short(result, Address(src, len, Address::times_2));
10758 testl(result, 0xff00); // check if Unicode char
10759 jccb(Assembler::notZero, return_zero);
10760 movb(Address(dst, len, Address::times_1), result); // ASCII char; compress to 1 byte
10761 increment(len);
10762 jcc(Assembler::notZero, copy_chars_loop);
10763
10764 // if compression succeeded, return length
10765 bind(return_length);
10766 pop(result);
10767 jmpb(done);
10768
10769 // if compression failed, return 0
10770 bind(return_zero);
10771 xorl(result, result);
10772 addptr(rsp, wordSize);
10773
10774 bind(done);
10775 }
10776
10777 // Inflate byte[] array to char[].
10778 // ..\jdk\src\java.base\share\classes\java\lang\StringLatin1.java
10779 // @HotSpotIntrinsicCandidate
10780 // private static void inflate(byte[] src, int srcOff, char[] dst, int dstOff, int len) {
10781 // for (int i = 0; i < len; i++) {
10782 // dst[dstOff++] = (char)(src[srcOff++] & 0xff);
10783 // }
10784 // }
10785 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
10786 XMMRegister tmp1, Register tmp2) {
10787 Label copy_chars_loop, done, below_threshold;
10788 // rsi: src
10789 // rdi: dst
10790 // rdx: len
10791 // rcx: tmp2
10792
10793 // rsi holds start addr of source byte[] to be inflated
10794 // rdi holds start addr of destination char[]
10795 // rdx holds length
10796 assert_different_registers(src, dst, len, tmp2);
10797
10798 if ((UseAVX > 2) && // AVX512
10799 VM_Version::supports_avx512vlbw() &&
10800 VM_Version::supports_bmi2()) {
10801
10802 set_vector_masking(); // opening of the stub context for programming mask registers
10803
10804 Label copy_32_loop, copy_tail;
10805 Register tmp3_aliased = len;
10806
10807 // if length of the string is less than 16, handle it in an old fashioned
10808 // way
10809 testl(len, -16);
10810 jcc(Assembler::zero, below_threshold);
10811
10812 // In order to use only one arithmetic operation for the main loop we use
10813 // this pre-calculation
10814 movl(tmp2, len);
10815 andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop
10816 andl(len, -32); // vector count
10817 jccb(Assembler::zero, copy_tail);
10818
10819 lea(src, Address(src, len, Address::times_1));
10820 lea(dst, Address(dst, len, Address::times_2));
10821 negptr(len);
10822
10823
10824 // inflate 32 chars per iter
10825 bind(copy_32_loop);
10826 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_512bit);
10827 evmovdquw(Address(dst, len, Address::times_2), tmp1, Assembler::AVX_512bit);
10828 addptr(len, 32);
10829 jcc(Assembler::notZero, copy_32_loop);
10830
10831 bind(copy_tail);
10832 // bail out when there is nothing to be done
10833 testl(tmp2, -1); // we don't destroy the contents of tmp2 here
10834 jcc(Assembler::zero, done);
10835
10836 // Save k1
10837 kmovql(k2, k1);
10838
10839 // ~(~0 << length), where length is the # of remaining elements to process
10840 movl(tmp3_aliased, -1);
10841 shlxl(tmp3_aliased, tmp3_aliased, tmp2);
10842 notl(tmp3_aliased);
10843 kmovdl(k1, tmp3_aliased);
10844 evpmovzxbw(tmp1, k1, Address(src, 0), Assembler::AVX_512bit);
10845 evmovdquw(Address(dst, 0), k1, tmp1, Assembler::AVX_512bit);
10846
10847 // Restore k1
10848 kmovql(k1, k2);
10849 jmp(done);
10850
10851 clear_vector_masking(); // closing of the stub context for programming mask registers
10852 }
10853 if (UseSSE42Intrinsics) {
10854 Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail;
10855
10856 movl(tmp2, len);
10857
10858 if (UseAVX > 1) {
10859 andl(tmp2, (16 - 1));
10860 andl(len, -16);
10861 jccb(Assembler::zero, copy_new_tail);
10862 } else {
10863 andl(tmp2, 0x00000007); // tail count (in chars)
10864 andl(len, 0xfffffff8); // vector count (in chars)
10865 jccb(Assembler::zero, copy_tail);
10866 }
10867
10868 // vectored inflation
10869 lea(src, Address(src, len, Address::times_1));
10870 lea(dst, Address(dst, len, Address::times_2));
10871 negptr(len);
10872
10873 if (UseAVX > 1) {
10874 bind(copy_16_loop);
10875 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_256bit);
10876 vmovdqu(Address(dst, len, Address::times_2), tmp1);
10877 addptr(len, 16);
10878 jcc(Assembler::notZero, copy_16_loop);
10879
10880 bind(below_threshold);
10881 bind(copy_new_tail);
10882 if ((UseAVX > 2) &&
10883 VM_Version::supports_avx512vlbw() &&
10884 VM_Version::supports_bmi2()) {
10885 movl(tmp2, len);
10886 } else {
10887 movl(len, tmp2);
10888 }
10889 andl(tmp2, 0x00000007);
10890 andl(len, 0xFFFFFFF8);
10891 jccb(Assembler::zero, copy_tail);
10892
10893 pmovzxbw(tmp1, Address(src, 0));
10894 movdqu(Address(dst, 0), tmp1);
10895 addptr(src, 8);
10896 addptr(dst, 2 * 8);
10897
10898 jmp(copy_tail, true);
10899 }
10900
10901 // inflate 8 chars per iter
10902 bind(copy_8_loop);
10903 pmovzxbw(tmp1, Address(src, len, Address::times_1)); // unpack to 8 words
10904 movdqu(Address(dst, len, Address::times_2), tmp1);
10905 addptr(len, 8);
10906 jcc(Assembler::notZero, copy_8_loop);
10907
10908 bind(copy_tail);
10909 movl(len, tmp2);
10910
10911 cmpl(len, 4);
10912 jccb(Assembler::less, copy_bytes);
10913
10914 movdl(tmp1, Address(src, 0)); // load 4 byte chars
10915 pmovzxbw(tmp1, tmp1);
10916 movq(Address(dst, 0), tmp1);
10917 subptr(len, 4);
10918 addptr(src, 4);
10919 addptr(dst, 8);
10920
10921 bind(copy_bytes);
10922 }
10923 testl(len, len);
10924 jccb(Assembler::zero, done);
10925 lea(src, Address(src, len, Address::times_1));
10926 lea(dst, Address(dst, len, Address::times_2));
10927 negptr(len);
10928
10929 // inflate 1 char per iter
10930 bind(copy_chars_loop);
10931 load_unsigned_byte(tmp2, Address(src, len, Address::times_1)); // load byte char
10932 movw(Address(dst, len, Address::times_2), tmp2); // inflate byte char to word
10933 increment(len);
10934 jcc(Assembler::notZero, copy_chars_loop);
10935
10936 bind(done);
10937 }
10938
10939 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
10940 switch (cond) {
10941 // Note some conditions are synonyms for others
10942 case Assembler::zero: return Assembler::notZero;
10943 case Assembler::notZero: return Assembler::zero;
10944 case Assembler::less: return Assembler::greaterEqual;
10945 case Assembler::lessEqual: return Assembler::greater;
10946 case Assembler::greater: return Assembler::lessEqual;
10947 case Assembler::greaterEqual: return Assembler::less;
10948 case Assembler::below: return Assembler::aboveEqual;
10949 case Assembler::belowEqual: return Assembler::above;
10950 case Assembler::above: return Assembler::belowEqual;
10951 case Assembler::aboveEqual: return Assembler::below;
10952 case Assembler::overflow: return Assembler::noOverflow;
10953 case Assembler::noOverflow: return Assembler::overflow;
10954 case Assembler::negative: return Assembler::positive;
10955 case Assembler::positive: return Assembler::negative;
10956 case Assembler::parity: return Assembler::noParity;
10957 case Assembler::noParity: return Assembler::parity;
10958 }
10959 ShouldNotReachHere(); return Assembler::overflow;
10960 }
10961
10962 SkipIfEqual::SkipIfEqual(
10963 MacroAssembler* masm, const bool* flag_addr, bool value) {
10964 _masm = masm;
10965 _masm->cmp8(ExternalAddress((address)flag_addr), value);
10966 _masm->jcc(Assembler::equal, _label);
10967 }
10968
10969 SkipIfEqual::~SkipIfEqual() {
10970 _masm->bind(_label);
10971 }
10972
10973 // 32-bit Windows has its own fast-path implementation
10974 // of get_thread
10975 #if !defined(WIN32) || defined(_LP64)
10976
10977 // This is simply a call to Thread::current()
10978 void MacroAssembler::get_thread(Register thread) {
10979 if (thread != rax) {
10980 push(rax);
10981 }
10982 LP64_ONLY(push(rdi);)
10983 LP64_ONLY(push(rsi);)
10984 push(rdx);
10985 push(rcx);
10986 #ifdef _LP64
10987 push(r8);
10988 push(r9);
10989 push(r10);
10990 push(r11);
10991 #endif
10992
10993 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0);
10994
10995 #ifdef _LP64
10996 pop(r11);
10997 pop(r10);
10998 pop(r9);
10999 pop(r8);
11000 #endif
11001 pop(rcx);
11002 pop(rdx);
11003 LP64_ONLY(pop(rsi);)
11004 LP64_ONLY(pop(rdi);)
11005 if (thread != rax) {
11006 mov(thread, rax);
11007 pop(rax);
11008 }
11009 }
11010
11011 #endif