1 /*
2 * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
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23 */
24
25 #ifndef CPU_X86_VM_MACROASSEMBLER_X86_HPP
26 #define CPU_X86_VM_MACROASSEMBLER_X86_HPP
27
28 #include "asm/assembler.hpp"
29 #include "utilities/macros.hpp"
30 #include "runtime/rtmLocking.hpp"
31
32 // MacroAssembler extends Assembler by frequently used macros.
33 //
34 // Instructions for which a 'better' code sequence exists depending
35 // on arguments should also go in here.
36
37 class MacroAssembler: public Assembler {
38 friend class LIR_Assembler;
39 friend class Runtime1; // as_Address()
40
41 protected:
42
43 Address as_Address(AddressLiteral adr);
44 Address as_Address(ArrayAddress adr);
45
46 // Support for VM calls
47 //
48 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
49 // may customize this version by overriding it for its purposes (e.g., to save/restore
50 // additional registers when doing a VM call).
51
52 virtual void call_VM_leaf_base(
53 address entry_point, // the entry point
54 int number_of_arguments // the number of arguments to pop after the call
55 );
56
57 // This is the base routine called by the different versions of call_VM. The interpreter
58 // may customize this version by overriding it for its purposes (e.g., to save/restore
59 // additional registers when doing a VM call).
60 //
61 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
62 // returns the register which contains the thread upon return. If a thread register has been
63 // specified, the return value will correspond to that register. If no last_java_sp is specified
64 // (noreg) than rsp will be used instead.
65 virtual void call_VM_base( // returns the register containing the thread upon return
66 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
67 Register java_thread, // the thread if computed before ; use noreg otherwise
68 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
69 address entry_point, // the entry point
70 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
71 bool check_exceptions // whether to check for pending exceptions after return
72 );
73
74 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
75 // The implementation is only non-empty for the InterpreterMacroAssembler,
76 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
77 virtual void check_and_handle_popframe(Register java_thread);
78 virtual void check_and_handle_earlyret(Register java_thread);
79
80 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
81
82 // helpers for FPU flag access
83 // tmp is a temporary register, if none is available use noreg
84 void save_rax (Register tmp);
85 void restore_rax(Register tmp);
86
87 public:
88 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
89
90 // Support for NULL-checks
91 //
92 // Generates code that causes a NULL OS exception if the content of reg is NULL.
93 // If the accessed location is M[reg + offset] and the offset is known, provide the
94 // offset. No explicit code generation is needed if the offset is within a certain
95 // range (0 <= offset <= page_size).
96
97 void null_check(Register reg, int offset = -1);
98 static bool needs_explicit_null_check(intptr_t offset);
99
100 // Required platform-specific helpers for Label::patch_instructions.
101 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
102 void pd_patch_instruction(address branch, address target) {
103 unsigned char op = branch[0];
104 assert(op == 0xE8 /* call */ ||
105 op == 0xE9 /* jmp */ ||
106 op == 0xEB /* short jmp */ ||
107 (op & 0xF0) == 0x70 /* short jcc */ ||
108 op == 0x0F && (branch[1] & 0xF0) == 0x80 /* jcc */ ||
109 op == 0xC7 && branch[1] == 0xF8 /* xbegin */,
110 "Invalid opcode at patch point");
111
112 if (op == 0xEB || (op & 0xF0) == 0x70) {
113 // short offset operators (jmp and jcc)
114 char* disp = (char*) &branch[1];
115 int imm8 = target - (address) &disp[1];
116 guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset");
117 *disp = imm8;
118 } else {
119 int* disp = (int*) &branch[(op == 0x0F || op == 0xC7)? 2: 1];
120 int imm32 = target - (address) &disp[1];
121 *disp = imm32;
122 }
123 }
124
125 // The following 4 methods return the offset of the appropriate move instruction
126
127 // Support for fast byte/short loading with zero extension (depending on particular CPU)
128 int load_unsigned_byte(Register dst, Address src);
129 int load_unsigned_short(Register dst, Address src);
130
131 // Support for fast byte/short loading with sign extension (depending on particular CPU)
132 int load_signed_byte(Register dst, Address src);
133 int load_signed_short(Register dst, Address src);
134
135 // Support for sign-extension (hi:lo = extend_sign(lo))
136 void extend_sign(Register hi, Register lo);
137
138 // Load and store values by size and signed-ness
139 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
140 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
141
142 // Support for inc/dec with optimal instruction selection depending on value
143
144 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
145 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
146
147 void decrementl(Address dst, int value = 1);
148 void decrementl(Register reg, int value = 1);
149
150 void decrementq(Register reg, int value = 1);
151 void decrementq(Address dst, int value = 1);
152
153 void incrementl(Address dst, int value = 1);
154 void incrementl(Register reg, int value = 1);
155
156 void incrementq(Register reg, int value = 1);
157 void incrementq(Address dst, int value = 1);
158
159 // Support optimal SSE move instructions.
160 void movflt(XMMRegister dst, XMMRegister src) {
161 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
162 else { movss (dst, src); return; }
163 }
164 void movflt(XMMRegister dst, Address src) { movss(dst, src); }
165 void movflt(XMMRegister dst, AddressLiteral src);
166 void movflt(Address dst, XMMRegister src) { movss(dst, src); }
167
168 void movdbl(XMMRegister dst, XMMRegister src) {
169 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
170 else { movsd (dst, src); return; }
171 }
172
173 void movdbl(XMMRegister dst, AddressLiteral src);
174
175 void movdbl(XMMRegister dst, Address src) {
176 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
177 else { movlpd(dst, src); return; }
178 }
179 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
180
181 void incrementl(AddressLiteral dst);
182 void incrementl(ArrayAddress dst);
183
184 void incrementq(AddressLiteral dst);
185
186 // Alignment
187 void align(int modulus);
188 void align(int modulus, int target);
189
190 // A 5 byte nop that is safe for patching (see patch_verified_entry)
191 void fat_nop();
192
193 // Stack frame creation/removal
194 void enter();
195 void leave();
196
197 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
198 // The pointer will be loaded into the thread register.
199 void get_thread(Register thread);
200
201
202 // Support for VM calls
203 //
204 // It is imperative that all calls into the VM are handled via the call_VM macros.
205 // They make sure that the stack linkage is setup correctly. call_VM's correspond
206 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
207
208
209 void call_VM(Register oop_result,
210 address entry_point,
211 bool check_exceptions = true);
212 void call_VM(Register oop_result,
213 address entry_point,
214 Register arg_1,
215 bool check_exceptions = true);
216 void call_VM(Register oop_result,
217 address entry_point,
218 Register arg_1, Register arg_2,
219 bool check_exceptions = true);
220 void call_VM(Register oop_result,
221 address entry_point,
222 Register arg_1, Register arg_2, Register arg_3,
223 bool check_exceptions = true);
224
225 // Overloadings with last_Java_sp
226 void call_VM(Register oop_result,
227 Register last_java_sp,
228 address entry_point,
229 int number_of_arguments = 0,
230 bool check_exceptions = true);
231 void call_VM(Register oop_result,
232 Register last_java_sp,
233 address entry_point,
234 Register arg_1, bool
235 check_exceptions = true);
236 void call_VM(Register oop_result,
237 Register last_java_sp,
238 address entry_point,
239 Register arg_1, Register arg_2,
240 bool check_exceptions = true);
241 void call_VM(Register oop_result,
242 Register last_java_sp,
243 address entry_point,
244 Register arg_1, Register arg_2, Register arg_3,
245 bool check_exceptions = true);
246
247 void get_vm_result (Register oop_result, Register thread);
248 void get_vm_result_2(Register metadata_result, Register thread);
249
250 // These always tightly bind to MacroAssembler::call_VM_base
251 // bypassing the virtual implementation
252 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
253 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
254 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
255 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
256 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
257
258 void call_VM_leaf(address entry_point,
259 int number_of_arguments = 0);
260 void call_VM_leaf(address entry_point,
261 Register arg_1);
262 void call_VM_leaf(address entry_point,
263 Register arg_1, Register arg_2);
264 void call_VM_leaf(address entry_point,
265 Register arg_1, Register arg_2, Register arg_3);
266
267 // These always tightly bind to MacroAssembler::call_VM_leaf_base
268 // bypassing the virtual implementation
269 void super_call_VM_leaf(address entry_point);
270 void super_call_VM_leaf(address entry_point, Register arg_1);
271 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
272 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
273 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
274
275 // last Java Frame (fills frame anchor)
276 void set_last_Java_frame(Register thread,
277 Register last_java_sp,
278 Register last_java_fp,
279 address last_java_pc);
280
281 // thread in the default location (r15_thread on 64bit)
282 void set_last_Java_frame(Register last_java_sp,
283 Register last_java_fp,
284 address last_java_pc);
285
286 void reset_last_Java_frame(Register thread, bool clear_fp, bool clear_pc);
287
288 // thread in the default location (r15_thread on 64bit)
289 void reset_last_Java_frame(bool clear_fp, bool clear_pc);
290
291 // Stores
292 void store_check(Register obj); // store check for obj - register is destroyed afterwards
293 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
294
295 #if INCLUDE_ALL_GCS
296
297 void g1_write_barrier_pre(Register obj,
298 Register pre_val,
299 Register thread,
300 Register tmp,
301 bool tosca_live,
302 bool expand_call);
303
304 void g1_write_barrier_post(Register store_addr,
305 Register new_val,
306 Register thread,
307 Register tmp,
308 Register tmp2);
309
310 #endif // INCLUDE_ALL_GCS
311
312 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
313 void c2bool(Register x);
314
315 // C++ bool manipulation
316
317 void movbool(Register dst, Address src);
318 void movbool(Address dst, bool boolconst);
319 void movbool(Address dst, Register src);
320 void testbool(Register dst);
321
322 // oop manipulations
323 void load_klass(Register dst, Register src);
324 void store_klass(Register dst, Register src);
325
326 void load_heap_oop(Register dst, Address src);
327 void load_heap_oop_not_null(Register dst, Address src);
328 void store_heap_oop(Address dst, Register src);
329 void cmp_heap_oop(Register src1, Address src2, Register tmp = noreg);
330
331 // Used for storing NULL. All other oop constants should be
332 // stored using routines that take a jobject.
333 void store_heap_oop_null(Address dst);
334
335 void load_prototype_header(Register dst, Register src);
336
337 #ifdef _LP64
338 void store_klass_gap(Register dst, Register src);
339
340 // This dummy is to prevent a call to store_heap_oop from
341 // converting a zero (like NULL) into a Register by giving
342 // the compiler two choices it can't resolve
343
344 void store_heap_oop(Address dst, void* dummy);
345
346 void encode_heap_oop(Register r);
347 void decode_heap_oop(Register r);
348 void encode_heap_oop_not_null(Register r);
349 void decode_heap_oop_not_null(Register r);
350 void encode_heap_oop_not_null(Register dst, Register src);
351 void decode_heap_oop_not_null(Register dst, Register src);
352
353 void set_narrow_oop(Register dst, jobject obj);
354 void set_narrow_oop(Address dst, jobject obj);
355 void cmp_narrow_oop(Register dst, jobject obj);
356 void cmp_narrow_oop(Address dst, jobject obj);
357
358 void encode_klass_not_null(Register r);
359 void decode_klass_not_null(Register r);
360 void encode_klass_not_null(Register dst, Register src);
361 void decode_klass_not_null(Register dst, Register src);
362 void set_narrow_klass(Register dst, Klass* k);
363 void set_narrow_klass(Address dst, Klass* k);
364 void cmp_narrow_klass(Register dst, Klass* k);
365 void cmp_narrow_klass(Address dst, Klass* k);
366
367 // Returns the byte size of the instructions generated by decode_klass_not_null()
368 // when compressed klass pointers are being used.
369 static int instr_size_for_decode_klass_not_null();
370
371 // if heap base register is used - reinit it with the correct value
372 void reinit_heapbase();
373
374 DEBUG_ONLY(void verify_heapbase(const char* msg);)
375
376 #endif // _LP64
377
378 // Int division/remainder for Java
379 // (as idivl, but checks for special case as described in JVM spec.)
380 // returns idivl instruction offset for implicit exception handling
381 int corrected_idivl(Register reg);
382
383 // Long division/remainder for Java
384 // (as idivq, but checks for special case as described in JVM spec.)
385 // returns idivq instruction offset for implicit exception handling
386 int corrected_idivq(Register reg);
387
388 void int3();
389
390 // Long operation macros for a 32bit cpu
391 // Long negation for Java
392 void lneg(Register hi, Register lo);
393
394 // Long multiplication for Java
395 // (destroys contents of eax, ebx, ecx and edx)
396 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
397
398 // Long shifts for Java
399 // (semantics as described in JVM spec.)
400 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f)
401 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f)
402
403 // Long compare for Java
404 // (semantics as described in JVM spec.)
405 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
406
407
408 // misc
409
410 // Sign extension
411 void sign_extend_short(Register reg);
412 void sign_extend_byte(Register reg);
413
414 // Division by power of 2, rounding towards 0
415 void division_with_shift(Register reg, int shift_value);
416
417 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
418 //
419 // CF (corresponds to C0) if x < y
420 // PF (corresponds to C2) if unordered
421 // ZF (corresponds to C3) if x = y
422 //
423 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
424 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
425 void fcmp(Register tmp);
426 // Variant of the above which allows y to be further down the stack
427 // and which only pops x and y if specified. If pop_right is
428 // specified then pop_left must also be specified.
429 void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
430
431 // Floating-point comparison for Java
432 // Compares the top-most stack entries on the FPU stack and stores the result in dst.
433 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
434 // (semantics as described in JVM spec.)
435 void fcmp2int(Register dst, bool unordered_is_less);
436 // Variant of the above which allows y to be further down the stack
437 // and which only pops x and y if specified. If pop_right is
438 // specified then pop_left must also be specified.
439 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
440
441 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
442 // tmp is a temporary register, if none is available use noreg
443 void fremr(Register tmp);
444
445
446 // same as fcmp2int, but using SSE2
447 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
448 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
449
450 void mathfunc(address runtime_entry);
451
452 // branch to L if FPU flag C2 is set/not set
453 // tmp is a temporary register, if none is available use noreg
454 void jC2 (Register tmp, Label& L);
455 void jnC2(Register tmp, Label& L);
456
457 // Pop ST (ffree & fincstp combined)
458 void fpop();
459
460 // Load float value from 'address'. If UseSSE >= 1, the value is loaded into
461 // register xmm0. Otherwise, the value is loaded onto the FPU stack.
462 void load_float(Address src);
463
464 // Store float value to 'address'. If UseSSE >= 1, the value is stored
465 // from register xmm0. Otherwise, the value is stored from the FPU stack.
466 void store_float(Address dst);
467
468 // Load double value from 'address'. If UseSSE >= 2, the value is loaded into
469 // register xmm0. Otherwise, the value is loaded onto the FPU stack.
470 void load_double(Address src);
471
472 // Store double value to 'address'. If UseSSE >= 2, the value is stored
473 // from register xmm0. Otherwise, the value is stored from the FPU stack.
474 void store_double(Address dst);
475
476 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
477 void push_fTOS();
478
479 // pops double TOS element from CPU stack and pushes on FPU stack
480 void pop_fTOS();
481
482 void empty_FPU_stack();
483
484 void push_IU_state();
485 void pop_IU_state();
486
487 void push_FPU_state();
488 void pop_FPU_state();
489
490 void push_CPU_state();
491 void pop_CPU_state();
492
493 // Round up to a power of two
494 void round_to(Register reg, int modulus);
495
496 // Callee saved registers handling
497 void push_callee_saved_registers();
498 void pop_callee_saved_registers();
499
500 // allocation
501 void eden_allocate(
502 Register obj, // result: pointer to object after successful allocation
503 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
504 int con_size_in_bytes, // object size in bytes if known at compile time
505 Register t1, // temp register
506 Label& slow_case // continuation point if fast allocation fails
507 );
508 void tlab_allocate(
509 Register obj, // result: pointer to object after successful allocation
510 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
511 int con_size_in_bytes, // object size in bytes if known at compile time
512 Register t1, // temp register
513 Register t2, // temp register
514 Label& slow_case // continuation point if fast allocation fails
515 );
516 Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address
517 void zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp);
518
519 void incr_allocated_bytes(Register thread,
520 Register var_size_in_bytes, int con_size_in_bytes,
521 Register t1 = noreg);
522
523 // interface method calling
524 void lookup_interface_method(Register recv_klass,
525 Register intf_klass,
526 RegisterOrConstant itable_index,
527 Register method_result,
528 Register scan_temp,
529 Label& no_such_interface);
530
531 // virtual method calling
532 void lookup_virtual_method(Register recv_klass,
533 RegisterOrConstant vtable_index,
534 Register method_result);
535
536 // Test sub_klass against super_klass, with fast and slow paths.
537
538 // The fast path produces a tri-state answer: yes / no / maybe-slow.
539 // One of the three labels can be NULL, meaning take the fall-through.
540 // If super_check_offset is -1, the value is loaded up from super_klass.
541 // No registers are killed, except temp_reg.
542 void check_klass_subtype_fast_path(Register sub_klass,
543 Register super_klass,
544 Register temp_reg,
545 Label* L_success,
546 Label* L_failure,
547 Label* L_slow_path,
548 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
549
550 // The rest of the type check; must be wired to a corresponding fast path.
551 // It does not repeat the fast path logic, so don't use it standalone.
552 // The temp_reg and temp2_reg can be noreg, if no temps are available.
553 // Updates the sub's secondary super cache as necessary.
554 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
555 void check_klass_subtype_slow_path(Register sub_klass,
556 Register super_klass,
557 Register temp_reg,
558 Register temp2_reg,
559 Label* L_success,
560 Label* L_failure,
561 bool set_cond_codes = false);
562
563 // Simplified, combined version, good for typical uses.
564 // Falls through on failure.
565 void check_klass_subtype(Register sub_klass,
566 Register super_klass,
567 Register temp_reg,
568 Label& L_success);
569
570 // method handles (JSR 292)
571 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
572
573 //----
574 void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
575
576 // Debugging
577
578 // only if +VerifyOops
579 // TODO: Make these macros with file and line like sparc version!
580 void verify_oop(Register reg, const char* s = "broken oop");
581 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
582
583 // TODO: verify method and klass metadata (compare against vptr?)
584 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
585 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
586
587 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
588 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
589
590 // only if +VerifyFPU
591 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
592
593 // Verify or restore cpu control state after JNI call
594 void restore_cpu_control_state_after_jni();
595
596 // prints msg, dumps registers and stops execution
597 void stop(const char* msg);
598
599 // prints msg and continues
600 void warn(const char* msg);
601
602 // dumps registers and other state
603 void print_state();
604
605 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
606 static void debug64(char* msg, int64_t pc, int64_t regs[]);
607 static void print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip);
608 static void print_state64(int64_t pc, int64_t regs[]);
609
610 void os_breakpoint();
611
612 void untested() { stop("untested"); }
613
614 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, 1024, "unimplemented: %s", what); stop(b); }
615
616 void should_not_reach_here() { stop("should not reach here"); }
617
618 void print_CPU_state();
619
620 // Stack overflow checking
621 void bang_stack_with_offset(int offset) {
622 // stack grows down, caller passes positive offset
623 assert(offset > 0, "must bang with negative offset");
624 movl(Address(rsp, (-offset)), rax);
625 }
626
627 // Writes to stack successive pages until offset reached to check for
628 // stack overflow + shadow pages. Also, clobbers tmp
629 void bang_stack_size(Register size, Register tmp);
630
631 // Check for reserved stack access in method being exited (for JIT)
632 void reserved_stack_check();
633
634 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
635 Register tmp,
636 int offset);
637
638 // Support for serializing memory accesses between threads
639 void serialize_memory(Register thread, Register tmp);
640
641 void verify_tlab();
642
643 // Biased locking support
644 // lock_reg and obj_reg must be loaded up with the appropriate values.
645 // swap_reg must be rax, and is killed.
646 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
647 // be killed; if not supplied, push/pop will be used internally to
648 // allocate a temporary (inefficient, avoid if possible).
649 // Optional slow case is for implementations (interpreter and C1) which branch to
650 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
651 // Returns offset of first potentially-faulting instruction for null
652 // check info (currently consumed only by C1). If
653 // swap_reg_contains_mark is true then returns -1 as it is assumed
654 // the calling code has already passed any potential faults.
655 int biased_locking_enter(Register lock_reg, Register obj_reg,
656 Register swap_reg, Register tmp_reg,
657 bool swap_reg_contains_mark,
658 Label& done, Label* slow_case = NULL,
659 BiasedLockingCounters* counters = NULL);
660 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
661 #ifdef COMPILER2
662 // Code used by cmpFastLock and cmpFastUnlock mach instructions in .ad file.
663 // See full desription in macroAssembler_x86.cpp.
664 void fast_lock(Register obj, Register box, Register tmp,
665 Register scr, Register cx1, Register cx2,
666 BiasedLockingCounters* counters,
667 RTMLockingCounters* rtm_counters,
668 RTMLockingCounters* stack_rtm_counters,
669 Metadata* method_data,
670 bool use_rtm, bool profile_rtm);
671 void fast_unlock(Register obj, Register box, Register tmp, bool use_rtm);
672 #if INCLUDE_RTM_OPT
673 void rtm_counters_update(Register abort_status, Register rtm_counters);
674 void branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel);
675 void rtm_abort_ratio_calculation(Register tmp, Register rtm_counters_reg,
676 RTMLockingCounters* rtm_counters,
677 Metadata* method_data);
678 void rtm_profiling(Register abort_status_Reg, Register rtm_counters_Reg,
679 RTMLockingCounters* rtm_counters, Metadata* method_data, bool profile_rtm);
680 void rtm_retry_lock_on_abort(Register retry_count, Register abort_status, Label& retryLabel);
681 void rtm_retry_lock_on_busy(Register retry_count, Register box, Register tmp, Register scr, Label& retryLabel);
682 void rtm_stack_locking(Register obj, Register tmp, Register scr,
683 Register retry_on_abort_count,
684 RTMLockingCounters* stack_rtm_counters,
685 Metadata* method_data, bool profile_rtm,
686 Label& DONE_LABEL, Label& IsInflated);
687 void rtm_inflated_locking(Register obj, Register box, Register tmp,
688 Register scr, Register retry_on_busy_count,
689 Register retry_on_abort_count,
690 RTMLockingCounters* rtm_counters,
691 Metadata* method_data, bool profile_rtm,
692 Label& DONE_LABEL);
693 #endif
694 #endif
695
696 Condition negate_condition(Condition cond);
697
698 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
699 // operands. In general the names are modified to avoid hiding the instruction in Assembler
700 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
701 // here in MacroAssembler. The major exception to this rule is call
702
703 // Arithmetics
704
705
706 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
707 void addptr(Address dst, Register src);
708
709 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
710 void addptr(Register dst, int32_t src);
711 void addptr(Register dst, Register src);
712 void addptr(Register dst, RegisterOrConstant src) {
713 if (src.is_constant()) addptr(dst, (int) src.as_constant());
714 else addptr(dst, src.as_register());
715 }
716
717 void andptr(Register dst, int32_t src);
718 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
719
720 void cmp8(AddressLiteral src1, int imm);
721
722 // renamed to drag out the casting of address to int32_t/intptr_t
723 void cmp32(Register src1, int32_t imm);
724
725 void cmp32(AddressLiteral src1, int32_t imm);
726 // compare reg - mem, or reg - &mem
727 void cmp32(Register src1, AddressLiteral src2);
728
729 void cmp32(Register src1, Address src2);
730
731 #ifndef _LP64
732 void cmpklass(Address dst, Metadata* obj);
733 void cmpklass(Register dst, Metadata* obj);
734 void cmpoop(Address dst, jobject obj);
735 void cmpoop(Register dst, jobject obj);
736 #endif // _LP64
737
738 // NOTE src2 must be the lval. This is NOT an mem-mem compare
739 void cmpptr(Address src1, AddressLiteral src2);
740
741 void cmpptr(Register src1, AddressLiteral src2);
742
743 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
744 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
745 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
746
747 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
748 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
749
750 // cmp64 to avoild hiding cmpq
751 void cmp64(Register src1, AddressLiteral src);
752
753 void cmpxchgptr(Register reg, Address adr);
754
755 void locked_cmpxchgptr(Register reg, AddressLiteral adr);
756
757
758 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
759 void imulptr(Register dst, Register src, int imm32) { LP64_ONLY(imulq(dst, src, imm32)) NOT_LP64(imull(dst, src, imm32)); }
760
761
762 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
763
764 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
765
766 void shlptr(Register dst, int32_t shift);
767 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
768
769 void shrptr(Register dst, int32_t shift);
770 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
771
772 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
773 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
774
775 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
776
777 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
778 void subptr(Register dst, int32_t src);
779 // Force generation of a 4 byte immediate value even if it fits into 8bit
780 void subptr_imm32(Register dst, int32_t src);
781 void subptr(Register dst, Register src);
782 void subptr(Register dst, RegisterOrConstant src) {
783 if (src.is_constant()) subptr(dst, (int) src.as_constant());
784 else subptr(dst, src.as_register());
785 }
786
787 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
788 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
789
790 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
791 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
792
793 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
794
795
796
797 // Helper functions for statistics gathering.
798 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
799 void cond_inc32(Condition cond, AddressLiteral counter_addr);
800 // Unconditional atomic increment.
801 void atomic_incl(Address counter_addr);
802 void atomic_incl(AddressLiteral counter_addr, Register scr = rscratch1);
803 #ifdef _LP64
804 void atomic_incq(Address counter_addr);
805 void atomic_incq(AddressLiteral counter_addr, Register scr = rscratch1);
806 #endif
807 void atomic_incptr(AddressLiteral counter_addr, Register scr = rscratch1) { LP64_ONLY(atomic_incq(counter_addr, scr)) NOT_LP64(atomic_incl(counter_addr, scr)) ; }
808 void atomic_incptr(Address counter_addr) { LP64_ONLY(atomic_incq(counter_addr)) NOT_LP64(atomic_incl(counter_addr)) ; }
809
810 void lea(Register dst, AddressLiteral adr);
811 void lea(Address dst, AddressLiteral adr);
812 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
813
814 void leal32(Register dst, Address src) { leal(dst, src); }
815
816 // Import other testl() methods from the parent class or else
817 // they will be hidden by the following overriding declaration.
818 using Assembler::testl;
819 void testl(Register dst, AddressLiteral src);
820
821 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
822 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
823 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
824 void orptr(Address dst, int32_t imm32) { LP64_ONLY(orq(dst, imm32)) NOT_LP64(orl(dst, imm32)); }
825
826 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
827 void testptr(Register src1, Register src2);
828
829 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
830 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
831
832 // Calls
833
834 void call(Label& L, relocInfo::relocType rtype);
835 void call(Register entry);
836
837 // NOTE: this call tranfers to the effective address of entry NOT
838 // the address contained by entry. This is because this is more natural
839 // for jumps/calls.
840 void call(AddressLiteral entry);
841
842 // Emit the CompiledIC call idiom
843 void ic_call(address entry, jint method_index = 0);
844
845 // Jumps
846
847 // NOTE: these jumps tranfer to the effective address of dst NOT
848 // the address contained by dst. This is because this is more natural
849 // for jumps/calls.
850 void jump(AddressLiteral dst);
851 void jump_cc(Condition cc, AddressLiteral dst);
852
853 // 32bit can do a case table jump in one instruction but we no longer allow the base
854 // to be installed in the Address class. This jump will tranfers to the address
855 // contained in the location described by entry (not the address of entry)
856 void jump(ArrayAddress entry);
857
858 // Floating
859
860 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
861 void andpd(XMMRegister dst, AddressLiteral src);
862 void andpd(XMMRegister dst, XMMRegister src) { Assembler::andpd(dst, src); }
863
864 void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); }
865 void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); }
866 void andps(XMMRegister dst, AddressLiteral src);
867
868 void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); }
869 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
870 void comiss(XMMRegister dst, AddressLiteral src);
871
872 void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); }
873 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
874 void comisd(XMMRegister dst, AddressLiteral src);
875
876 void fadd_s(Address src) { Assembler::fadd_s(src); }
877 void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); }
878
879 void fldcw(Address src) { Assembler::fldcw(src); }
880 void fldcw(AddressLiteral src);
881
882 void fld_s(int index) { Assembler::fld_s(index); }
883 void fld_s(Address src) { Assembler::fld_s(src); }
884 void fld_s(AddressLiteral src);
885
886 void fld_d(Address src) { Assembler::fld_d(src); }
887 void fld_d(AddressLiteral src);
888
889 void fld_x(Address src) { Assembler::fld_x(src); }
890 void fld_x(AddressLiteral src);
891
892 void fmul_s(Address src) { Assembler::fmul_s(src); }
893 void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); }
894
895 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
896 void ldmxcsr(AddressLiteral src);
897
898 void fast_sha1(XMMRegister abcd, XMMRegister e0, XMMRegister e1, XMMRegister msg0,
899 XMMRegister msg1, XMMRegister msg2, XMMRegister msg3, XMMRegister shuf_mask,
900 Register buf, Register state, Register ofs, Register limit, Register rsp,
901 bool multi_block);
902
903 #ifdef _LP64
904 void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
905 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
906 Register buf, Register state, Register ofs, Register limit, Register rsp,
907 bool multi_block, XMMRegister shuf_mask);
908 #else
909 void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
910 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
911 Register buf, Register state, Register ofs, Register limit, Register rsp,
912 bool multi_block);
913 #endif
914
915 void fast_exp(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
916 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
917 Register rax, Register rcx, Register rdx, Register tmp);
918
919 #ifdef _LP64
920 void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
921 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
922 Register rax, Register rcx, Register rdx, Register tmp1, Register tmp2);
923
924 void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
925 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
926 Register rax, Register rcx, Register rdx, Register r11);
927
928 void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
929 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
930 Register rdx, Register tmp1, Register tmp2, Register tmp3, Register tmp4);
931
932 void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
933 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
934 Register rax, Register rbx, Register rcx, Register rdx, Register tmp1, Register tmp2,
935 Register tmp3, Register tmp4);
936
937 void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
938 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
939 Register rax, Register rcx, Register rdx, Register tmp1,
940 Register tmp2, Register tmp3, Register tmp4);
941 void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
942 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
943 Register rax, Register rcx, Register rdx, Register tmp1,
944 Register tmp2, Register tmp3, Register tmp4);
945 #else
946 void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
947 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
948 Register rax, Register rcx, Register rdx, Register tmp1);
949
950 void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
951 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
952 Register rax, Register rcx, Register rdx, Register tmp);
953
954 void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
955 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
956 Register rdx, Register tmp);
957
958 void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
959 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
960 Register rax, Register rbx, Register rdx);
961
962 void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
963 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
964 Register rax, Register rcx, Register rdx, Register tmp);
965
966 void libm_sincos_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
967 Register edx, Register ebx, Register esi, Register edi,
968 Register ebp, Register esp);
969
970 void libm_reduce_pi04l(Register eax, Register ecx, Register edx, Register ebx,
971 Register esi, Register edi, Register ebp, Register esp);
972
973 void libm_tancot_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
974 Register edx, Register ebx, Register esi, Register edi,
975 Register ebp, Register esp);
976
977 void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
978 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
979 Register rax, Register rcx, Register rdx, Register tmp);
980 #endif
981
982 void increase_precision();
983 void restore_precision();
984
985 private:
986
987 // these are private because users should be doing movflt/movdbl
988
989 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); }
990 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
991 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); }
992 void movss(XMMRegister dst, AddressLiteral src);
993
994 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); }
995 void movlpd(XMMRegister dst, AddressLiteral src);
996
997 public:
998
999 void addsd(XMMRegister dst, XMMRegister src) { Assembler::addsd(dst, src); }
1000 void addsd(XMMRegister dst, Address src) { Assembler::addsd(dst, src); }
1001 void addsd(XMMRegister dst, AddressLiteral src);
1002
1003 void addss(XMMRegister dst, XMMRegister src) { Assembler::addss(dst, src); }
1004 void addss(XMMRegister dst, Address src) { Assembler::addss(dst, src); }
1005 void addss(XMMRegister dst, AddressLiteral src);
1006
1007 void addpd(XMMRegister dst, XMMRegister src) { Assembler::addpd(dst, src); }
1008 void addpd(XMMRegister dst, Address src) { Assembler::addpd(dst, src); }
1009 void addpd(XMMRegister dst, AddressLiteral src);
1010
1011 void divsd(XMMRegister dst, XMMRegister src) { Assembler::divsd(dst, src); }
1012 void divsd(XMMRegister dst, Address src) { Assembler::divsd(dst, src); }
1013 void divsd(XMMRegister dst, AddressLiteral src);
1014
1015 void divss(XMMRegister dst, XMMRegister src) { Assembler::divss(dst, src); }
1016 void divss(XMMRegister dst, Address src) { Assembler::divss(dst, src); }
1017 void divss(XMMRegister dst, AddressLiteral src);
1018
1019 // Move Unaligned Double Quadword
1020 void movdqu(Address dst, XMMRegister src);
1021 void movdqu(XMMRegister dst, Address src);
1022 void movdqu(XMMRegister dst, XMMRegister src);
1023 void movdqu(XMMRegister dst, AddressLiteral src);
1024 // AVX Unaligned forms
1025 void vmovdqu(Address dst, XMMRegister src);
1026 void vmovdqu(XMMRegister dst, Address src);
1027 void vmovdqu(XMMRegister dst, XMMRegister src);
1028 void vmovdqu(XMMRegister dst, AddressLiteral src);
1029
1030 // Move Aligned Double Quadword
1031 void movdqa(XMMRegister dst, Address src) { Assembler::movdqa(dst, src); }
1032 void movdqa(XMMRegister dst, XMMRegister src) { Assembler::movdqa(dst, src); }
1033 void movdqa(XMMRegister dst, AddressLiteral src);
1034
1035 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
1036 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); }
1037 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); }
1038 void movsd(XMMRegister dst, AddressLiteral src);
1039
1040 void mulpd(XMMRegister dst, XMMRegister src) { Assembler::mulpd(dst, src); }
1041 void mulpd(XMMRegister dst, Address src) { Assembler::mulpd(dst, src); }
1042 void mulpd(XMMRegister dst, AddressLiteral src);
1043
1044 void mulsd(XMMRegister dst, XMMRegister src) { Assembler::mulsd(dst, src); }
1045 void mulsd(XMMRegister dst, Address src) { Assembler::mulsd(dst, src); }
1046 void mulsd(XMMRegister dst, AddressLiteral src);
1047
1048 void mulss(XMMRegister dst, XMMRegister src) { Assembler::mulss(dst, src); }
1049 void mulss(XMMRegister dst, Address src) { Assembler::mulss(dst, src); }
1050 void mulss(XMMRegister dst, AddressLiteral src);
1051
1052 // Carry-Less Multiplication Quadword
1053 void pclmulldq(XMMRegister dst, XMMRegister src) {
1054 // 0x00 - multiply lower 64 bits [0:63]
1055 Assembler::pclmulqdq(dst, src, 0x00);
1056 }
1057 void pclmulhdq(XMMRegister dst, XMMRegister src) {
1058 // 0x11 - multiply upper 64 bits [64:127]
1059 Assembler::pclmulqdq(dst, src, 0x11);
1060 }
1061
1062 void pcmpeqb(XMMRegister dst, XMMRegister src);
1063 void pcmpeqw(XMMRegister dst, XMMRegister src);
1064
1065 void pcmpestri(XMMRegister dst, Address src, int imm8);
1066 void pcmpestri(XMMRegister dst, XMMRegister src, int imm8);
1067
1068 void pmovzxbw(XMMRegister dst, XMMRegister src);
1069 void pmovzxbw(XMMRegister dst, Address src);
1070
1071 void pmovmskb(Register dst, XMMRegister src);
1072
1073 void ptest(XMMRegister dst, XMMRegister src);
1074
1075 void sqrtsd(XMMRegister dst, XMMRegister src) { Assembler::sqrtsd(dst, src); }
1076 void sqrtsd(XMMRegister dst, Address src) { Assembler::sqrtsd(dst, src); }
1077 void sqrtsd(XMMRegister dst, AddressLiteral src);
1078
1079 void sqrtss(XMMRegister dst, XMMRegister src) { Assembler::sqrtss(dst, src); }
1080 void sqrtss(XMMRegister dst, Address src) { Assembler::sqrtss(dst, src); }
1081 void sqrtss(XMMRegister dst, AddressLiteral src);
1082
1083 void subsd(XMMRegister dst, XMMRegister src) { Assembler::subsd(dst, src); }
1084 void subsd(XMMRegister dst, Address src) { Assembler::subsd(dst, src); }
1085 void subsd(XMMRegister dst, AddressLiteral src);
1086
1087 void subss(XMMRegister dst, XMMRegister src) { Assembler::subss(dst, src); }
1088 void subss(XMMRegister dst, Address src) { Assembler::subss(dst, src); }
1089 void subss(XMMRegister dst, AddressLiteral src);
1090
1091 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
1092 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); }
1093 void ucomiss(XMMRegister dst, AddressLiteral src);
1094
1095 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
1096 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); }
1097 void ucomisd(XMMRegister dst, AddressLiteral src);
1098
1099 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1100 void xorpd(XMMRegister dst, XMMRegister src);
1101 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); }
1102 void xorpd(XMMRegister dst, AddressLiteral src);
1103
1104 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1105 void xorps(XMMRegister dst, XMMRegister src);
1106 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); }
1107 void xorps(XMMRegister dst, AddressLiteral src);
1108
1109 // Shuffle Bytes
1110 void pshufb(XMMRegister dst, XMMRegister src) { Assembler::pshufb(dst, src); }
1111 void pshufb(XMMRegister dst, Address src) { Assembler::pshufb(dst, src); }
1112 void pshufb(XMMRegister dst, AddressLiteral src);
1113 // AVX 3-operands instructions
1114
1115 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); }
1116 void vaddsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddsd(dst, nds, src); }
1117 void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1118
1119 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); }
1120 void vaddss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddss(dst, nds, src); }
1121 void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1122
1123 void vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1124 void vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1125
1126 void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1127 void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1128
1129 void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1130 void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1131
1132 void vpbroadcastw(XMMRegister dst, XMMRegister src);
1133
1134 void vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1135 void vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1136
1137 void vpmovzxbw(XMMRegister dst, Address src, int vector_len);
1138 void vpmovmskb(Register dst, XMMRegister src);
1139
1140 void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1141 void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1142
1143 void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1144 void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1145
1146 void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1147 void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1148
1149 void vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1150 void vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1151
1152 void vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1153 void vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1154
1155 void vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1156 void vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1157
1158 void vptest(XMMRegister dst, XMMRegister src);
1159
1160 void punpcklbw(XMMRegister dst, XMMRegister src);
1161 void punpcklbw(XMMRegister dst, Address src) { Assembler::punpcklbw(dst, src); }
1162
1163 void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1164 void pshuflw(XMMRegister dst, Address src, int mode) { Assembler::pshuflw(dst, src, mode); }
1165
1166 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1167 void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1168 void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1169
1170 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1171 void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1172 void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1173
1174 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); }
1175 void vdivsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivsd(dst, nds, src); }
1176 void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1177
1178 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); }
1179 void vdivss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivss(dst, nds, src); }
1180 void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1181
1182 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); }
1183 void vmulsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulsd(dst, nds, src); }
1184 void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1185
1186 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); }
1187 void vmulss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulss(dst, nds, src); }
1188 void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1189
1190 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); }
1191 void vsubsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubsd(dst, nds, src); }
1192 void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1193
1194 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); }
1195 void vsubss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubss(dst, nds, src); }
1196 void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1197
1198 void vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1199 void vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1200
1201 // AVX Vector instructions
1202
1203 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1204 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1205 void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1206
1207 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1208 void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1209 void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1210
1211 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1212 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1213 Assembler::vpxor(dst, nds, src, vector_len);
1214 else
1215 Assembler::vxorpd(dst, nds, src, vector_len);
1216 }
1217 void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
1218 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1219 Assembler::vpxor(dst, nds, src, vector_len);
1220 else
1221 Assembler::vxorpd(dst, nds, src, vector_len);
1222 }
1223
1224 // Simple version for AVX2 256bit vectors
1225 void vpxor(XMMRegister dst, XMMRegister src) { Assembler::vpxor(dst, dst, src, true); }
1226 void vpxor(XMMRegister dst, Address src) { Assembler::vpxor(dst, dst, src, true); }
1227
1228 void vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
1229 if (UseAVX > 2) {
1230 Assembler::vinserti32x4(dst, dst, src, imm8);
1231 } else if (UseAVX > 1) {
1232 // vinserti128 is available only in AVX2
1233 Assembler::vinserti128(dst, nds, src, imm8);
1234 } else {
1235 Assembler::vinsertf128(dst, nds, src, imm8);
1236 }
1237 }
1238
1239 void vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
1240 if (UseAVX > 2) {
1241 Assembler::vinserti32x4(dst, dst, src, imm8);
1242 } else if (UseAVX > 1) {
1243 // vinserti128 is available only in AVX2
1244 Assembler::vinserti128(dst, nds, src, imm8);
1245 } else {
1246 Assembler::vinsertf128(dst, nds, src, imm8);
1247 }
1248 }
1249
1250 void vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
1251 if (UseAVX > 2) {
1252 Assembler::vextracti32x4(dst, src, imm8);
1253 } else if (UseAVX > 1) {
1254 // vextracti128 is available only in AVX2
1255 Assembler::vextracti128(dst, src, imm8);
1256 } else {
1257 Assembler::vextractf128(dst, src, imm8);
1258 }
1259 }
1260
1261 void vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
1262 if (UseAVX > 2) {
1263 Assembler::vextracti32x4(dst, src, imm8);
1264 } else if (UseAVX > 1) {
1265 // vextracti128 is available only in AVX2
1266 Assembler::vextracti128(dst, src, imm8);
1267 } else {
1268 Assembler::vextractf128(dst, src, imm8);
1269 }
1270 }
1271
1272 // 128bit copy to/from high 128 bits of 256bit (YMM) vector registers
1273 void vinserti128_high(XMMRegister dst, XMMRegister src) {
1274 vinserti128(dst, dst, src, 1);
1275 }
1276 void vinserti128_high(XMMRegister dst, Address src) {
1277 vinserti128(dst, dst, src, 1);
1278 }
1279 void vextracti128_high(XMMRegister dst, XMMRegister src) {
1280 vextracti128(dst, src, 1);
1281 }
1282 void vextracti128_high(Address dst, XMMRegister src) {
1283 vextracti128(dst, src, 1);
1284 }
1285
1286 void vinsertf128_high(XMMRegister dst, XMMRegister src) {
1287 if (UseAVX > 2) {
1288 Assembler::vinsertf32x4(dst, dst, src, 1);
1289 } else {
1290 Assembler::vinsertf128(dst, dst, src, 1);
1291 }
1292 }
1293
1294 void vinsertf128_high(XMMRegister dst, Address src) {
1295 if (UseAVX > 2) {
1296 Assembler::vinsertf32x4(dst, dst, src, 1);
1297 } else {
1298 Assembler::vinsertf128(dst, dst, src, 1);
1299 }
1300 }
1301
1302 void vextractf128_high(XMMRegister dst, XMMRegister src) {
1303 if (UseAVX > 2) {
1304 Assembler::vextractf32x4(dst, src, 1);
1305 } else {
1306 Assembler::vextractf128(dst, src, 1);
1307 }
1308 }
1309
1310 void vextractf128_high(Address dst, XMMRegister src) {
1311 if (UseAVX > 2) {
1312 Assembler::vextractf32x4(dst, src, 1);
1313 } else {
1314 Assembler::vextractf128(dst, src, 1);
1315 }
1316 }
1317
1318 // 256bit copy to/from high 256 bits of 512bit (ZMM) vector registers
1319 void vinserti64x4_high(XMMRegister dst, XMMRegister src) {
1320 Assembler::vinserti64x4(dst, dst, src, 1);
1321 }
1322 void vinsertf64x4_high(XMMRegister dst, XMMRegister src) {
1323 Assembler::vinsertf64x4(dst, dst, src, 1);
1324 }
1325 void vextracti64x4_high(XMMRegister dst, XMMRegister src) {
1326 Assembler::vextracti64x4(dst, src, 1);
1327 }
1328 void vextractf64x4_high(XMMRegister dst, XMMRegister src) {
1329 Assembler::vextractf64x4(dst, src, 1);
1330 }
1331 void vextractf64x4_high(Address dst, XMMRegister src) {
1332 Assembler::vextractf64x4(dst, src, 1);
1333 }
1334 void vinsertf64x4_high(XMMRegister dst, Address src) {
1335 Assembler::vinsertf64x4(dst, dst, src, 1);
1336 }
1337
1338 // 128bit copy to/from low 128 bits of 256bit (YMM) vector registers
1339 void vinserti128_low(XMMRegister dst, XMMRegister src) {
1340 vinserti128(dst, dst, src, 0);
1341 }
1342 void vinserti128_low(XMMRegister dst, Address src) {
1343 vinserti128(dst, dst, src, 0);
1344 }
1345 void vextracti128_low(XMMRegister dst, XMMRegister src) {
1346 vextracti128(dst, src, 0);
1347 }
1348 void vextracti128_low(Address dst, XMMRegister src) {
1349 vextracti128(dst, src, 0);
1350 }
1351
1352 void vinsertf128_low(XMMRegister dst, XMMRegister src) {
1353 if (UseAVX > 2) {
1354 Assembler::vinsertf32x4(dst, dst, src, 0);
1355 } else {
1356 Assembler::vinsertf128(dst, dst, src, 0);
1357 }
1358 }
1359
1360 void vinsertf128_low(XMMRegister dst, Address src) {
1361 if (UseAVX > 2) {
1362 Assembler::vinsertf32x4(dst, dst, src, 0);
1363 } else {
1364 Assembler::vinsertf128(dst, dst, src, 0);
1365 }
1366 }
1367
1368 void vextractf128_low(XMMRegister dst, XMMRegister src) {
1369 if (UseAVX > 2) {
1370 Assembler::vextractf32x4(dst, src, 0);
1371 } else {
1372 Assembler::vextractf128(dst, src, 0);
1373 }
1374 }
1375
1376 void vextractf128_low(Address dst, XMMRegister src) {
1377 if (UseAVX > 2) {
1378 Assembler::vextractf32x4(dst, src, 0);
1379 } else {
1380 Assembler::vextractf128(dst, src, 0);
1381 }
1382 }
1383
1384 // 256bit copy to/from low 256 bits of 512bit (ZMM) vector registers
1385 void vinserti64x4_low(XMMRegister dst, XMMRegister src) {
1386 Assembler::vinserti64x4(dst, dst, src, 0);
1387 }
1388 void vinsertf64x4_low(XMMRegister dst, XMMRegister src) {
1389 Assembler::vinsertf64x4(dst, dst, src, 0);
1390 }
1391 void vextracti64x4_low(XMMRegister dst, XMMRegister src) {
1392 Assembler::vextracti64x4(dst, src, 0);
1393 }
1394 void vextractf64x4_low(XMMRegister dst, XMMRegister src) {
1395 Assembler::vextractf64x4(dst, src, 0);
1396 }
1397 void vextractf64x4_low(Address dst, XMMRegister src) {
1398 Assembler::vextractf64x4(dst, src, 0);
1399 }
1400 void vinsertf64x4_low(XMMRegister dst, Address src) {
1401 Assembler::vinsertf64x4(dst, dst, src, 0);
1402 }
1403
1404 // Carry-Less Multiplication Quadword
1405 void vpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1406 // 0x00 - multiply lower 64 bits [0:63]
1407 Assembler::vpclmulqdq(dst, nds, src, 0x00);
1408 }
1409 void vpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1410 // 0x11 - multiply upper 64 bits [64:127]
1411 Assembler::vpclmulqdq(dst, nds, src, 0x11);
1412 }
1413
1414 // Data
1415
1416 void cmov32( Condition cc, Register dst, Address src);
1417 void cmov32( Condition cc, Register dst, Register src);
1418
1419 void cmov( Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); }
1420
1421 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1422 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1423
1424 void movoop(Register dst, jobject obj);
1425 void movoop(Address dst, jobject obj);
1426
1427 void mov_metadata(Register dst, Metadata* obj);
1428 void mov_metadata(Address dst, Metadata* obj);
1429
1430 void movptr(ArrayAddress dst, Register src);
1431 // can this do an lea?
1432 void movptr(Register dst, ArrayAddress src);
1433
1434 void movptr(Register dst, Address src);
1435
1436 #ifdef _LP64
1437 void movptr(Register dst, AddressLiteral src, Register scratch=rscratch1);
1438 #else
1439 void movptr(Register dst, AddressLiteral src, Register scratch=noreg); // Scratch reg is ignored in 32-bit
1440 #endif
1441
1442 void movptr(Register dst, intptr_t src);
1443 void movptr(Register dst, Register src);
1444 void movptr(Address dst, intptr_t src);
1445
1446 void movptr(Address dst, Register src);
1447
1448 void movptr(Register dst, RegisterOrConstant src) {
1449 if (src.is_constant()) movptr(dst, src.as_constant());
1450 else movptr(dst, src.as_register());
1451 }
1452
1453 #ifdef _LP64
1454 // Generally the next two are only used for moving NULL
1455 // Although there are situations in initializing the mark word where
1456 // they could be used. They are dangerous.
1457
1458 // They only exist on LP64 so that int32_t and intptr_t are not the same
1459 // and we have ambiguous declarations.
1460
1461 void movptr(Address dst, int32_t imm32);
1462 void movptr(Register dst, int32_t imm32);
1463 #endif // _LP64
1464
1465 // to avoid hiding movl
1466 void mov32(AddressLiteral dst, Register src);
1467 void mov32(Register dst, AddressLiteral src);
1468
1469 // to avoid hiding movb
1470 void movbyte(ArrayAddress dst, int src);
1471
1472 // Import other mov() methods from the parent class or else
1473 // they will be hidden by the following overriding declaration.
1474 using Assembler::movdl;
1475 using Assembler::movq;
1476 void movdl(XMMRegister dst, AddressLiteral src);
1477 void movq(XMMRegister dst, AddressLiteral src);
1478
1479 // Can push value or effective address
1480 void pushptr(AddressLiteral src);
1481
1482 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
1483 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
1484
1485 void pushoop(jobject obj);
1486 void pushklass(Metadata* obj);
1487
1488 // sign extend as need a l to ptr sized element
1489 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
1490 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
1491
1492 // C2 compiled method's prolog code.
1493 void verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b);
1494
1495 // clear memory of size 'cnt' qwords, starting at 'base';
1496 // if 'is_large' is set, do not try to produce short loop
1497 void clear_mem(Register base, Register cnt, Register rtmp, bool is_large);
1498
1499 #ifdef COMPILER2
1500 void string_indexof_char(Register str1, Register cnt1, Register ch, Register result,
1501 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp);
1502
1503 // IndexOf strings.
1504 // Small strings are loaded through stack if they cross page boundary.
1505 void string_indexof(Register str1, Register str2,
1506 Register cnt1, Register cnt2,
1507 int int_cnt2, Register result,
1508 XMMRegister vec, Register tmp,
1509 int ae);
1510
1511 // IndexOf for constant substrings with size >= 8 elements
1512 // which don't need to be loaded through stack.
1513 void string_indexofC8(Register str1, Register str2,
1514 Register cnt1, Register cnt2,
1515 int int_cnt2, Register result,
1516 XMMRegister vec, Register tmp,
1517 int ae);
1518
1519 // Smallest code: we don't need to load through stack,
1520 // check string tail.
1521
1522 // helper function for string_compare
1523 void load_next_elements(Register elem1, Register elem2, Register str1, Register str2,
1524 Address::ScaleFactor scale, Address::ScaleFactor scale1,
1525 Address::ScaleFactor scale2, Register index, int ae);
1526 // Compare strings.
1527 void string_compare(Register str1, Register str2,
1528 Register cnt1, Register cnt2, Register result,
1529 XMMRegister vec1, int ae);
1530
1531 // Search for Non-ASCII character (Negative byte value) in a byte array,
1532 // return true if it has any and false otherwise.
1533 void has_negatives(Register ary1, Register len,
1534 Register result, Register tmp1,
1535 XMMRegister vec1, XMMRegister vec2);
1536
1537 // Compare char[] or byte[] arrays.
1538 void arrays_equals(bool is_array_equ, Register ary1, Register ary2,
1539 Register limit, Register result, Register chr,
1540 XMMRegister vec1, XMMRegister vec2, bool is_char);
1541
1542 #endif
1543
1544 // Fill primitive arrays
1545 void generate_fill(BasicType t, bool aligned,
1546 Register to, Register value, Register count,
1547 Register rtmp, XMMRegister xtmp);
1548
1549 void encode_iso_array(Register src, Register dst, Register len,
1550 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1551 XMMRegister tmp4, Register tmp5, Register result);
1552
1553 #ifdef _LP64
1554 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2);
1555 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1556 Register y, Register y_idx, Register z,
1557 Register carry, Register product,
1558 Register idx, Register kdx);
1559 void multiply_add_128_x_128(Register x_xstart, Register y, Register z,
1560 Register yz_idx, Register idx,
1561 Register carry, Register product, int offset);
1562 void multiply_128_x_128_bmi2_loop(Register y, Register z,
1563 Register carry, Register carry2,
1564 Register idx, Register jdx,
1565 Register yz_idx1, Register yz_idx2,
1566 Register tmp, Register tmp3, Register tmp4);
1567 void multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
1568 Register yz_idx, Register idx, Register jdx,
1569 Register carry, Register product,
1570 Register carry2);
1571 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
1572 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5);
1573 void square_rshift(Register x, Register len, Register z, Register tmp1, Register tmp3,
1574 Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1575 void multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry,
1576 Register tmp2);
1577 void multiply_add_64(Register sum, Register op1, Register op2, Register carry,
1578 Register rdxReg, Register raxReg);
1579 void add_one_64(Register z, Register zlen, Register carry, Register tmp1);
1580 void lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1581 Register tmp3, Register tmp4);
1582 void square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1583 Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1584
1585 void mul_add_128_x_32_loop(Register out, Register in, Register offset, Register len, Register tmp1,
1586 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1587 Register raxReg);
1588 void mul_add(Register out, Register in, Register offset, Register len, Register k, Register tmp1,
1589 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1590 Register raxReg);
1591 void vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
1592 Register result, Register tmp1, Register tmp2,
1593 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3);
1594 #endif
1595
1596 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1597 void update_byte_crc32(Register crc, Register val, Register table);
1598 void kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp);
1599 // CRC32C code for java.util.zip.CRC32C::updateBytes() intrinsic
1600 // Note on a naming convention:
1601 // Prefix w = register only used on a Westmere+ architecture
1602 // Prefix n = register only used on a Nehalem architecture
1603 #ifdef _LP64
1604 void crc32c_ipl_alg4(Register in_out, uint32_t n,
1605 Register tmp1, Register tmp2, Register tmp3);
1606 #else
1607 void crc32c_ipl_alg4(Register in_out, uint32_t n,
1608 Register tmp1, Register tmp2, Register tmp3,
1609 XMMRegister xtmp1, XMMRegister xtmp2);
1610 #endif
1611 void crc32c_pclmulqdq(XMMRegister w_xtmp1,
1612 Register in_out,
1613 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
1614 XMMRegister w_xtmp2,
1615 Register tmp1,
1616 Register n_tmp2, Register n_tmp3);
1617 void crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
1618 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1619 Register tmp1, Register tmp2,
1620 Register n_tmp3);
1621 void crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
1622 Register in_out1, Register in_out2, Register in_out3,
1623 Register tmp1, Register tmp2, Register tmp3,
1624 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1625 Register tmp4, Register tmp5,
1626 Register n_tmp6);
1627 void crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
1628 Register tmp1, Register tmp2, Register tmp3,
1629 Register tmp4, Register tmp5, Register tmp6,
1630 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1631 bool is_pclmulqdq_supported);
1632 // Fold 128-bit data chunk
1633 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
1634 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf);
1635 // Fold 8-bit data
1636 void fold_8bit_crc32(Register crc, Register table, Register tmp);
1637 void fold_8bit_crc32(XMMRegister crc, Register table, XMMRegister xtmp, Register tmp);
1638
1639 // Compress char[] array to byte[].
1640 void char_array_compress(Register src, Register dst, Register len,
1641 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1642 XMMRegister tmp4, Register tmp5, Register result);
1643
1644 // Inflate byte[] array to char[].
1645 void byte_array_inflate(Register src, Register dst, Register len,
1646 XMMRegister tmp1, Register tmp2);
1647
1648 };
1649
1650 /**
1651 * class SkipIfEqual:
1652 *
1653 * Instantiating this class will result in assembly code being output that will
1654 * jump around any code emitted between the creation of the instance and it's
1655 * automatic destruction at the end of a scope block, depending on the value of
1656 * the flag passed to the constructor, which will be checked at run-time.
1657 */
1658 class SkipIfEqual {
1659 private:
1660 MacroAssembler* _masm;
1661 Label _label;
1662
1663 public:
1664 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1665 ~SkipIfEqual();
1666 };
1667
1668 #endif // CPU_X86_VM_MACROASSEMBLER_X86_HPP