1 /*
2 * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "compiler/disassembler.hpp"
29 #include "gc/shared/cardTableModRefBS.hpp"
30 #include "gc/shared/collectedHeap.inline.hpp"
31 #include "interpreter/interpreter.hpp"
32 #include "memory/resourceArea.hpp"
33 #include "memory/universe.hpp"
34 #include "oops/klass.inline.hpp"
35 #include "prims/methodHandles.hpp"
36 #include "runtime/biasedLocking.hpp"
37 #include "runtime/interfaceSupport.hpp"
38 #include "runtime/objectMonitor.hpp"
39 #include "runtime/os.hpp"
40 #include "runtime/sharedRuntime.hpp"
41 #include "runtime/stubRoutines.hpp"
42 #include "runtime/thread.hpp"
43 #include "utilities/macros.hpp"
44 #if INCLUDE_ALL_GCS
45 #include "gc/g1/g1CollectedHeap.inline.hpp"
46 #include "gc/g1/g1SATBCardTableModRefBS.hpp"
47 #include "gc/g1/heapRegion.hpp"
48 #endif // INCLUDE_ALL_GCS
49 #include "crc32c.h"
50 #ifdef COMPILER2
51 #include "opto/intrinsicnode.hpp"
52 #endif
53
54 #ifdef PRODUCT
55 #define BLOCK_COMMENT(str) /* nothing */
56 #define STOP(error) stop(error)
57 #else
58 #define BLOCK_COMMENT(str) block_comment(str)
59 #define STOP(error) block_comment(error); stop(error)
60 #endif
61
62 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
63
64 #ifdef ASSERT
65 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
66 #endif
67
68 static Assembler::Condition reverse[] = {
69 Assembler::noOverflow /* overflow = 0x0 */ ,
70 Assembler::overflow /* noOverflow = 0x1 */ ,
71 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
72 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
73 Assembler::notZero /* zero = 0x4, equal = 0x4 */ ,
74 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ ,
75 Assembler::above /* belowEqual = 0x6 */ ,
76 Assembler::belowEqual /* above = 0x7 */ ,
77 Assembler::positive /* negative = 0x8 */ ,
78 Assembler::negative /* positive = 0x9 */ ,
79 Assembler::noParity /* parity = 0xa */ ,
80 Assembler::parity /* noParity = 0xb */ ,
81 Assembler::greaterEqual /* less = 0xc */ ,
82 Assembler::less /* greaterEqual = 0xd */ ,
83 Assembler::greater /* lessEqual = 0xe */ ,
84 Assembler::lessEqual /* greater = 0xf, */
85
86 };
87
88
89 // Implementation of MacroAssembler
90
91 // First all the versions that have distinct versions depending on 32/64 bit
92 // Unless the difference is trivial (1 line or so).
93
94 #ifndef _LP64
95
96 // 32bit versions
97
98 Address MacroAssembler::as_Address(AddressLiteral adr) {
99 return Address(adr.target(), adr.rspec());
100 }
101
102 Address MacroAssembler::as_Address(ArrayAddress adr) {
103 return Address::make_array(adr);
104 }
105
106 void MacroAssembler::call_VM_leaf_base(address entry_point,
107 int number_of_arguments) {
108 call(RuntimeAddress(entry_point));
109 increment(rsp, number_of_arguments * wordSize);
110 }
111
112 void MacroAssembler::cmpklass(Address src1, Metadata* obj) {
113 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
114 }
115
116 void MacroAssembler::cmpklass(Register src1, Metadata* obj) {
117 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
118 }
119
120 void MacroAssembler::cmpoop(Address src1, jobject obj) {
121 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
122 }
123
124 void MacroAssembler::cmpoop(Register src1, jobject obj) {
125 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
126 }
127
128 void MacroAssembler::extend_sign(Register hi, Register lo) {
129 // According to Intel Doc. AP-526, "Integer Divide", p.18.
130 if (VM_Version::is_P6() && hi == rdx && lo == rax) {
131 cdql();
132 } else {
133 movl(hi, lo);
134 sarl(hi, 31);
135 }
136 }
137
138 void MacroAssembler::jC2(Register tmp, Label& L) {
139 // set parity bit if FPU flag C2 is set (via rax)
140 save_rax(tmp);
141 fwait(); fnstsw_ax();
142 sahf();
143 restore_rax(tmp);
144 // branch
145 jcc(Assembler::parity, L);
146 }
147
148 void MacroAssembler::jnC2(Register tmp, Label& L) {
149 // set parity bit if FPU flag C2 is set (via rax)
150 save_rax(tmp);
151 fwait(); fnstsw_ax();
152 sahf();
153 restore_rax(tmp);
154 // branch
155 jcc(Assembler::noParity, L);
156 }
157
158 // 32bit can do a case table jump in one instruction but we no longer allow the base
159 // to be installed in the Address class
160 void MacroAssembler::jump(ArrayAddress entry) {
161 jmp(as_Address(entry));
162 }
163
164 // Note: y_lo will be destroyed
165 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
166 // Long compare for Java (semantics as described in JVM spec.)
167 Label high, low, done;
168
169 cmpl(x_hi, y_hi);
170 jcc(Assembler::less, low);
171 jcc(Assembler::greater, high);
172 // x_hi is the return register
173 xorl(x_hi, x_hi);
174 cmpl(x_lo, y_lo);
175 jcc(Assembler::below, low);
176 jcc(Assembler::equal, done);
177
178 bind(high);
179 xorl(x_hi, x_hi);
180 increment(x_hi);
181 jmp(done);
182
183 bind(low);
184 xorl(x_hi, x_hi);
185 decrementl(x_hi);
186
187 bind(done);
188 }
189
190 void MacroAssembler::lea(Register dst, AddressLiteral src) {
191 mov_literal32(dst, (int32_t)src.target(), src.rspec());
192 }
193
194 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
195 // leal(dst, as_Address(adr));
196 // see note in movl as to why we must use a move
197 mov_literal32(dst, (int32_t) adr.target(), adr.rspec());
198 }
199
200 void MacroAssembler::leave() {
201 mov(rsp, rbp);
202 pop(rbp);
203 }
204
205 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
206 // Multiplication of two Java long values stored on the stack
207 // as illustrated below. Result is in rdx:rax.
208 //
209 // rsp ---> [ ?? ] \ \
210 // .... | y_rsp_offset |
211 // [ y_lo ] / (in bytes) | x_rsp_offset
212 // [ y_hi ] | (in bytes)
213 // .... |
214 // [ x_lo ] /
215 // [ x_hi ]
216 // ....
217 //
218 // Basic idea: lo(result) = lo(x_lo * y_lo)
219 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
220 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
221 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
222 Label quick;
223 // load x_hi, y_hi and check if quick
224 // multiplication is possible
225 movl(rbx, x_hi);
226 movl(rcx, y_hi);
227 movl(rax, rbx);
228 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0
229 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply
230 // do full multiplication
231 // 1st step
232 mull(y_lo); // x_hi * y_lo
233 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx,
234 // 2nd step
235 movl(rax, x_lo);
236 mull(rcx); // x_lo * y_hi
237 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx,
238 // 3rd step
239 bind(quick); // note: rbx, = 0 if quick multiply!
240 movl(rax, x_lo);
241 mull(y_lo); // x_lo * y_lo
242 addl(rdx, rbx); // correct hi(x_lo * y_lo)
243 }
244
245 void MacroAssembler::lneg(Register hi, Register lo) {
246 negl(lo);
247 adcl(hi, 0);
248 negl(hi);
249 }
250
251 void MacroAssembler::lshl(Register hi, Register lo) {
252 // Java shift left long support (semantics as described in JVM spec., p.305)
253 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
254 // shift value is in rcx !
255 assert(hi != rcx, "must not use rcx");
256 assert(lo != rcx, "must not use rcx");
257 const Register s = rcx; // shift count
258 const int n = BitsPerWord;
259 Label L;
260 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
261 cmpl(s, n); // if (s < n)
262 jcc(Assembler::less, L); // else (s >= n)
263 movl(hi, lo); // x := x << n
264 xorl(lo, lo);
265 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
266 bind(L); // s (mod n) < n
267 shldl(hi, lo); // x := x << s
268 shll(lo);
269 }
270
271
272 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
273 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
274 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
275 assert(hi != rcx, "must not use rcx");
276 assert(lo != rcx, "must not use rcx");
277 const Register s = rcx; // shift count
278 const int n = BitsPerWord;
279 Label L;
280 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
281 cmpl(s, n); // if (s < n)
282 jcc(Assembler::less, L); // else (s >= n)
283 movl(lo, hi); // x := x >> n
284 if (sign_extension) sarl(hi, 31);
285 else xorl(hi, hi);
286 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
287 bind(L); // s (mod n) < n
288 shrdl(lo, hi); // x := x >> s
289 if (sign_extension) sarl(hi);
290 else shrl(hi);
291 }
292
293 void MacroAssembler::movoop(Register dst, jobject obj) {
294 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
295 }
296
297 void MacroAssembler::movoop(Address dst, jobject obj) {
298 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
299 }
300
301 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
302 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
303 }
304
305 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
306 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
307 }
308
309 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
310 // scratch register is not used,
311 // it is defined to match parameters of 64-bit version of this method.
312 if (src.is_lval()) {
313 mov_literal32(dst, (intptr_t)src.target(), src.rspec());
314 } else {
315 movl(dst, as_Address(src));
316 }
317 }
318
319 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
320 movl(as_Address(dst), src);
321 }
322
323 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
324 movl(dst, as_Address(src));
325 }
326
327 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
328 void MacroAssembler::movptr(Address dst, intptr_t src) {
329 movl(dst, src);
330 }
331
332
333 void MacroAssembler::pop_callee_saved_registers() {
334 pop(rcx);
335 pop(rdx);
336 pop(rdi);
337 pop(rsi);
338 }
339
340 void MacroAssembler::pop_fTOS() {
341 fld_d(Address(rsp, 0));
342 addl(rsp, 2 * wordSize);
343 }
344
345 void MacroAssembler::push_callee_saved_registers() {
346 push(rsi);
347 push(rdi);
348 push(rdx);
349 push(rcx);
350 }
351
352 void MacroAssembler::push_fTOS() {
353 subl(rsp, 2 * wordSize);
354 fstp_d(Address(rsp, 0));
355 }
356
357
358 void MacroAssembler::pushoop(jobject obj) {
359 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
360 }
361
362 void MacroAssembler::pushklass(Metadata* obj) {
363 push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate());
364 }
365
366 void MacroAssembler::pushptr(AddressLiteral src) {
367 if (src.is_lval()) {
368 push_literal32((int32_t)src.target(), src.rspec());
369 } else {
370 pushl(as_Address(src));
371 }
372 }
373
374 void MacroAssembler::set_word_if_not_zero(Register dst) {
375 xorl(dst, dst);
376 set_byte_if_not_zero(dst);
377 }
378
379 static void pass_arg0(MacroAssembler* masm, Register arg) {
380 masm->push(arg);
381 }
382
383 static void pass_arg1(MacroAssembler* masm, Register arg) {
384 masm->push(arg);
385 }
386
387 static void pass_arg2(MacroAssembler* masm, Register arg) {
388 masm->push(arg);
389 }
390
391 static void pass_arg3(MacroAssembler* masm, Register arg) {
392 masm->push(arg);
393 }
394
395 #ifndef PRODUCT
396 extern "C" void findpc(intptr_t x);
397 #endif
398
399 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
400 // In order to get locks to work, we need to fake a in_VM state
401 JavaThread* thread = JavaThread::current();
402 JavaThreadState saved_state = thread->thread_state();
403 thread->set_thread_state(_thread_in_vm);
404 if (ShowMessageBoxOnError) {
405 JavaThread* thread = JavaThread::current();
406 JavaThreadState saved_state = thread->thread_state();
407 thread->set_thread_state(_thread_in_vm);
408 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
409 ttyLocker ttyl;
410 BytecodeCounter::print();
411 }
412 // To see where a verify_oop failed, get $ebx+40/X for this frame.
413 // This is the value of eip which points to where verify_oop will return.
414 if (os::message_box(msg, "Execution stopped, print registers?")) {
415 print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip);
416 BREAKPOINT;
417 }
418 } else {
419 ttyLocker ttyl;
420 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg);
421 }
422 // Don't assert holding the ttyLock
423 assert(false, "DEBUG MESSAGE: %s", msg);
424 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
425 }
426
427 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) {
428 ttyLocker ttyl;
429 FlagSetting fs(Debugging, true);
430 tty->print_cr("eip = 0x%08x", eip);
431 #ifndef PRODUCT
432 if ((WizardMode || Verbose) && PrintMiscellaneous) {
433 tty->cr();
434 findpc(eip);
435 tty->cr();
436 }
437 #endif
438 #define PRINT_REG(rax) \
439 { tty->print("%s = ", #rax); os::print_location(tty, rax); }
440 PRINT_REG(rax);
441 PRINT_REG(rbx);
442 PRINT_REG(rcx);
443 PRINT_REG(rdx);
444 PRINT_REG(rdi);
445 PRINT_REG(rsi);
446 PRINT_REG(rbp);
447 PRINT_REG(rsp);
448 #undef PRINT_REG
449 // Print some words near top of staack.
450 int* dump_sp = (int*) rsp;
451 for (int col1 = 0; col1 < 8; col1++) {
452 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
453 os::print_location(tty, *dump_sp++);
454 }
455 for (int row = 0; row < 16; row++) {
456 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
457 for (int col = 0; col < 8; col++) {
458 tty->print(" 0x%08x", *dump_sp++);
459 }
460 tty->cr();
461 }
462 // Print some instructions around pc:
463 Disassembler::decode((address)eip-64, (address)eip);
464 tty->print_cr("--------");
465 Disassembler::decode((address)eip, (address)eip+32);
466 }
467
468 void MacroAssembler::stop(const char* msg) {
469 ExternalAddress message((address)msg);
470 // push address of message
471 pushptr(message.addr());
472 { Label L; call(L, relocInfo::none); bind(L); } // push eip
473 pusha(); // push registers
474 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
475 hlt();
476 }
477
478 void MacroAssembler::warn(const char* msg) {
479 push_CPU_state();
480
481 ExternalAddress message((address) msg);
482 // push address of message
483 pushptr(message.addr());
484
485 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
486 addl(rsp, wordSize); // discard argument
487 pop_CPU_state();
488 }
489
490 void MacroAssembler::print_state() {
491 { Label L; call(L, relocInfo::none); bind(L); } // push eip
492 pusha(); // push registers
493
494 push_CPU_state();
495 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32)));
496 pop_CPU_state();
497
498 popa();
499 addl(rsp, wordSize);
500 }
501
502 #else // _LP64
503
504 // 64 bit versions
505
506 Address MacroAssembler::as_Address(AddressLiteral adr) {
507 // amd64 always does this as a pc-rel
508 // we can be absolute or disp based on the instruction type
509 // jmp/call are displacements others are absolute
510 assert(!adr.is_lval(), "must be rval");
511 assert(reachable(adr), "must be");
512 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc());
513
514 }
515
516 Address MacroAssembler::as_Address(ArrayAddress adr) {
517 AddressLiteral base = adr.base();
518 lea(rscratch1, base);
519 Address index = adr.index();
520 assert(index._disp == 0, "must not have disp"); // maybe it can?
521 Address array(rscratch1, index._index, index._scale, index._disp);
522 return array;
523 }
524
525 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
526 Label L, E;
527
528 #ifdef _WIN64
529 // Windows always allocates space for it's register args
530 assert(num_args <= 4, "only register arguments supported");
531 subq(rsp, frame::arg_reg_save_area_bytes);
532 #endif
533
534 // Align stack if necessary
535 testl(rsp, 15);
536 jcc(Assembler::zero, L);
537
538 subq(rsp, 8);
539 {
540 call(RuntimeAddress(entry_point));
541 }
542 addq(rsp, 8);
543 jmp(E);
544
545 bind(L);
546 {
547 call(RuntimeAddress(entry_point));
548 }
549
550 bind(E);
551
552 #ifdef _WIN64
553 // restore stack pointer
554 addq(rsp, frame::arg_reg_save_area_bytes);
555 #endif
556
557 }
558
559 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) {
560 assert(!src2.is_lval(), "should use cmpptr");
561
562 if (reachable(src2)) {
563 cmpq(src1, as_Address(src2));
564 } else {
565 lea(rscratch1, src2);
566 Assembler::cmpq(src1, Address(rscratch1, 0));
567 }
568 }
569
570 int MacroAssembler::corrected_idivq(Register reg) {
571 // Full implementation of Java ldiv and lrem; checks for special
572 // case as described in JVM spec., p.243 & p.271. The function
573 // returns the (pc) offset of the idivl instruction - may be needed
574 // for implicit exceptions.
575 //
576 // normal case special case
577 //
578 // input : rax: dividend min_long
579 // reg: divisor (may not be eax/edx) -1
580 //
581 // output: rax: quotient (= rax idiv reg) min_long
582 // rdx: remainder (= rax irem reg) 0
583 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
584 static const int64_t min_long = 0x8000000000000000;
585 Label normal_case, special_case;
586
587 // check for special case
588 cmp64(rax, ExternalAddress((address) &min_long));
589 jcc(Assembler::notEqual, normal_case);
590 xorl(rdx, rdx); // prepare rdx for possible special case (where
591 // remainder = 0)
592 cmpq(reg, -1);
593 jcc(Assembler::equal, special_case);
594
595 // handle normal case
596 bind(normal_case);
597 cdqq();
598 int idivq_offset = offset();
599 idivq(reg);
600
601 // normal and special case exit
602 bind(special_case);
603
604 return idivq_offset;
605 }
606
607 void MacroAssembler::decrementq(Register reg, int value) {
608 if (value == min_jint) { subq(reg, value); return; }
609 if (value < 0) { incrementq(reg, -value); return; }
610 if (value == 0) { ; return; }
611 if (value == 1 && UseIncDec) { decq(reg) ; return; }
612 /* else */ { subq(reg, value) ; return; }
613 }
614
615 void MacroAssembler::decrementq(Address dst, int value) {
616 if (value == min_jint) { subq(dst, value); return; }
617 if (value < 0) { incrementq(dst, -value); return; }
618 if (value == 0) { ; return; }
619 if (value == 1 && UseIncDec) { decq(dst) ; return; }
620 /* else */ { subq(dst, value) ; return; }
621 }
622
623 void MacroAssembler::incrementq(AddressLiteral dst) {
624 if (reachable(dst)) {
625 incrementq(as_Address(dst));
626 } else {
627 lea(rscratch1, dst);
628 incrementq(Address(rscratch1, 0));
629 }
630 }
631
632 void MacroAssembler::incrementq(Register reg, int value) {
633 if (value == min_jint) { addq(reg, value); return; }
634 if (value < 0) { decrementq(reg, -value); return; }
635 if (value == 0) { ; return; }
636 if (value == 1 && UseIncDec) { incq(reg) ; return; }
637 /* else */ { addq(reg, value) ; return; }
638 }
639
640 void MacroAssembler::incrementq(Address dst, int value) {
641 if (value == min_jint) { addq(dst, value); return; }
642 if (value < 0) { decrementq(dst, -value); return; }
643 if (value == 0) { ; return; }
644 if (value == 1 && UseIncDec) { incq(dst) ; return; }
645 /* else */ { addq(dst, value) ; return; }
646 }
647
648 // 32bit can do a case table jump in one instruction but we no longer allow the base
649 // to be installed in the Address class
650 void MacroAssembler::jump(ArrayAddress entry) {
651 lea(rscratch1, entry.base());
652 Address dispatch = entry.index();
653 assert(dispatch._base == noreg, "must be");
654 dispatch._base = rscratch1;
655 jmp(dispatch);
656 }
657
658 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
659 ShouldNotReachHere(); // 64bit doesn't use two regs
660 cmpq(x_lo, y_lo);
661 }
662
663 void MacroAssembler::lea(Register dst, AddressLiteral src) {
664 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
665 }
666
667 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
668 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec());
669 movptr(dst, rscratch1);
670 }
671
672 void MacroAssembler::leave() {
673 // %%% is this really better? Why not on 32bit too?
674 emit_int8((unsigned char)0xC9); // LEAVE
675 }
676
677 void MacroAssembler::lneg(Register hi, Register lo) {
678 ShouldNotReachHere(); // 64bit doesn't use two regs
679 negq(lo);
680 }
681
682 void MacroAssembler::movoop(Register dst, jobject obj) {
683 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
684 }
685
686 void MacroAssembler::movoop(Address dst, jobject obj) {
687 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate());
688 movq(dst, rscratch1);
689 }
690
691 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
692 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
693 }
694
695 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
696 mov_literal64(rscratch1, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
697 movq(dst, rscratch1);
698 }
699
700 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
701 if (src.is_lval()) {
702 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
703 } else {
704 if (reachable(src)) {
705 movq(dst, as_Address(src));
706 } else {
707 lea(scratch, src);
708 movq(dst, Address(scratch, 0));
709 }
710 }
711 }
712
713 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
714 movq(as_Address(dst), src);
715 }
716
717 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
718 movq(dst, as_Address(src));
719 }
720
721 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
722 void MacroAssembler::movptr(Address dst, intptr_t src) {
723 mov64(rscratch1, src);
724 movq(dst, rscratch1);
725 }
726
727 // These are mostly for initializing NULL
728 void MacroAssembler::movptr(Address dst, int32_t src) {
729 movslq(dst, src);
730 }
731
732 void MacroAssembler::movptr(Register dst, int32_t src) {
733 mov64(dst, (intptr_t)src);
734 }
735
736 void MacroAssembler::pushoop(jobject obj) {
737 movoop(rscratch1, obj);
738 push(rscratch1);
739 }
740
741 void MacroAssembler::pushklass(Metadata* obj) {
742 mov_metadata(rscratch1, obj);
743 push(rscratch1);
744 }
745
746 void MacroAssembler::pushptr(AddressLiteral src) {
747 lea(rscratch1, src);
748 if (src.is_lval()) {
749 push(rscratch1);
750 } else {
751 pushq(Address(rscratch1, 0));
752 }
753 }
754
755 void MacroAssembler::reset_last_Java_frame(bool clear_fp,
756 bool clear_pc) {
757 // we must set sp to zero to clear frame
758 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
759 // must clear fp, so that compiled frames are not confused; it is
760 // possible that we need it only for debugging
761 if (clear_fp) {
762 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
763 }
764
765 if (clear_pc) {
766 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
767 }
768 }
769
770 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
771 Register last_java_fp,
772 address last_java_pc) {
773 // determine last_java_sp register
774 if (!last_java_sp->is_valid()) {
775 last_java_sp = rsp;
776 }
777
778 // last_java_fp is optional
779 if (last_java_fp->is_valid()) {
780 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()),
781 last_java_fp);
782 }
783
784 // last_java_pc is optional
785 if (last_java_pc != NULL) {
786 Address java_pc(r15_thread,
787 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
788 lea(rscratch1, InternalAddress(last_java_pc));
789 movptr(java_pc, rscratch1);
790 }
791
792 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
793 }
794
795 static void pass_arg0(MacroAssembler* masm, Register arg) {
796 if (c_rarg0 != arg ) {
797 masm->mov(c_rarg0, arg);
798 }
799 }
800
801 static void pass_arg1(MacroAssembler* masm, Register arg) {
802 if (c_rarg1 != arg ) {
803 masm->mov(c_rarg1, arg);
804 }
805 }
806
807 static void pass_arg2(MacroAssembler* masm, Register arg) {
808 if (c_rarg2 != arg ) {
809 masm->mov(c_rarg2, arg);
810 }
811 }
812
813 static void pass_arg3(MacroAssembler* masm, Register arg) {
814 if (c_rarg3 != arg ) {
815 masm->mov(c_rarg3, arg);
816 }
817 }
818
819 void MacroAssembler::stop(const char* msg) {
820 address rip = pc();
821 pusha(); // get regs on stack
822 lea(c_rarg0, ExternalAddress((address) msg));
823 lea(c_rarg1, InternalAddress(rip));
824 movq(c_rarg2, rsp); // pass pointer to regs array
825 andq(rsp, -16); // align stack as required by ABI
826 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
827 hlt();
828 }
829
830 void MacroAssembler::warn(const char* msg) {
831 push(rbp);
832 movq(rbp, rsp);
833 andq(rsp, -16); // align stack as required by push_CPU_state and call
834 push_CPU_state(); // keeps alignment at 16 bytes
835 lea(c_rarg0, ExternalAddress((address) msg));
836 call_VM_leaf(CAST_FROM_FN_PTR(address, warning), c_rarg0);
837 pop_CPU_state();
838 mov(rsp, rbp);
839 pop(rbp);
840 }
841
842 void MacroAssembler::print_state() {
843 address rip = pc();
844 pusha(); // get regs on stack
845 push(rbp);
846 movq(rbp, rsp);
847 andq(rsp, -16); // align stack as required by push_CPU_state and call
848 push_CPU_state(); // keeps alignment at 16 bytes
849
850 lea(c_rarg0, InternalAddress(rip));
851 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
852 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
853
854 pop_CPU_state();
855 mov(rsp, rbp);
856 pop(rbp);
857 popa();
858 }
859
860 #ifndef PRODUCT
861 extern "C" void findpc(intptr_t x);
862 #endif
863
864 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
865 // In order to get locks to work, we need to fake a in_VM state
866 if (ShowMessageBoxOnError) {
867 JavaThread* thread = JavaThread::current();
868 JavaThreadState saved_state = thread->thread_state();
869 thread->set_thread_state(_thread_in_vm);
870 #ifndef PRODUCT
871 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
872 ttyLocker ttyl;
873 BytecodeCounter::print();
874 }
875 #endif
876 // To see where a verify_oop failed, get $ebx+40/X for this frame.
877 // XXX correct this offset for amd64
878 // This is the value of eip which points to where verify_oop will return.
879 if (os::message_box(msg, "Execution stopped, print registers?")) {
880 print_state64(pc, regs);
881 BREAKPOINT;
882 assert(false, "start up GDB");
883 }
884 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
885 } else {
886 ttyLocker ttyl;
887 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n",
888 msg);
889 assert(false, "DEBUG MESSAGE: %s", msg);
890 }
891 }
892
893 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
894 ttyLocker ttyl;
895 FlagSetting fs(Debugging, true);
896 tty->print_cr("rip = 0x%016lx", pc);
897 #ifndef PRODUCT
898 tty->cr();
899 findpc(pc);
900 tty->cr();
901 #endif
902 #define PRINT_REG(rax, value) \
903 { tty->print("%s = ", #rax); os::print_location(tty, value); }
904 PRINT_REG(rax, regs[15]);
905 PRINT_REG(rbx, regs[12]);
906 PRINT_REG(rcx, regs[14]);
907 PRINT_REG(rdx, regs[13]);
908 PRINT_REG(rdi, regs[8]);
909 PRINT_REG(rsi, regs[9]);
910 PRINT_REG(rbp, regs[10]);
911 PRINT_REG(rsp, regs[11]);
912 PRINT_REG(r8 , regs[7]);
913 PRINT_REG(r9 , regs[6]);
914 PRINT_REG(r10, regs[5]);
915 PRINT_REG(r11, regs[4]);
916 PRINT_REG(r12, regs[3]);
917 PRINT_REG(r13, regs[2]);
918 PRINT_REG(r14, regs[1]);
919 PRINT_REG(r15, regs[0]);
920 #undef PRINT_REG
921 // Print some words near top of staack.
922 int64_t* rsp = (int64_t*) regs[11];
923 int64_t* dump_sp = rsp;
924 for (int col1 = 0; col1 < 8; col1++) {
925 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp);
926 os::print_location(tty, *dump_sp++);
927 }
928 for (int row = 0; row < 25; row++) {
929 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp);
930 for (int col = 0; col < 4; col++) {
931 tty->print(" 0x%016lx", *dump_sp++);
932 }
933 tty->cr();
934 }
935 // Print some instructions around pc:
936 Disassembler::decode((address)pc-64, (address)pc);
937 tty->print_cr("--------");
938 Disassembler::decode((address)pc, (address)pc+32);
939 }
940
941 #endif // _LP64
942
943 // Now versions that are common to 32/64 bit
944
945 void MacroAssembler::addptr(Register dst, int32_t imm32) {
946 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
947 }
948
949 void MacroAssembler::addptr(Register dst, Register src) {
950 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
951 }
952
953 void MacroAssembler::addptr(Address dst, Register src) {
954 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
955 }
956
957 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) {
958 if (reachable(src)) {
959 Assembler::addsd(dst, as_Address(src));
960 } else {
961 lea(rscratch1, src);
962 Assembler::addsd(dst, Address(rscratch1, 0));
963 }
964 }
965
966 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) {
967 if (reachable(src)) {
968 addss(dst, as_Address(src));
969 } else {
970 lea(rscratch1, src);
971 addss(dst, Address(rscratch1, 0));
972 }
973 }
974
975 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src) {
976 if (reachable(src)) {
977 Assembler::addpd(dst, as_Address(src));
978 } else {
979 lea(rscratch1, src);
980 Assembler::addpd(dst, Address(rscratch1, 0));
981 }
982 }
983
984 void MacroAssembler::align(int modulus) {
985 align(modulus, offset());
986 }
987
988 void MacroAssembler::align(int modulus, int target) {
989 if (target % modulus != 0) {
990 nop(modulus - (target % modulus));
991 }
992 }
993
994 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) {
995 // Used in sign-masking with aligned address.
996 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
997 if (reachable(src)) {
998 Assembler::andpd(dst, as_Address(src));
999 } else {
1000 lea(rscratch1, src);
1001 Assembler::andpd(dst, Address(rscratch1, 0));
1002 }
1003 }
1004
1005 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src) {
1006 // Used in sign-masking with aligned address.
1007 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1008 if (reachable(src)) {
1009 Assembler::andps(dst, as_Address(src));
1010 } else {
1011 lea(rscratch1, src);
1012 Assembler::andps(dst, Address(rscratch1, 0));
1013 }
1014 }
1015
1016 void MacroAssembler::andptr(Register dst, int32_t imm32) {
1017 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
1018 }
1019
1020 void MacroAssembler::atomic_incl(Address counter_addr) {
1021 if (os::is_MP())
1022 lock();
1023 incrementl(counter_addr);
1024 }
1025
1026 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register scr) {
1027 if (reachable(counter_addr)) {
1028 atomic_incl(as_Address(counter_addr));
1029 } else {
1030 lea(scr, counter_addr);
1031 atomic_incl(Address(scr, 0));
1032 }
1033 }
1034
1035 #ifdef _LP64
1036 void MacroAssembler::atomic_incq(Address counter_addr) {
1037 if (os::is_MP())
1038 lock();
1039 incrementq(counter_addr);
1040 }
1041
1042 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register scr) {
1043 if (reachable(counter_addr)) {
1044 atomic_incq(as_Address(counter_addr));
1045 } else {
1046 lea(scr, counter_addr);
1047 atomic_incq(Address(scr, 0));
1048 }
1049 }
1050 #endif
1051
1052 // Writes to stack successive pages until offset reached to check for
1053 // stack overflow + shadow pages. This clobbers tmp.
1054 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
1055 movptr(tmp, rsp);
1056 // Bang stack for total size given plus shadow page size.
1057 // Bang one page at a time because large size can bang beyond yellow and
1058 // red zones.
1059 Label loop;
1060 bind(loop);
1061 movl(Address(tmp, (-os::vm_page_size())), size );
1062 subptr(tmp, os::vm_page_size());
1063 subl(size, os::vm_page_size());
1064 jcc(Assembler::greater, loop);
1065
1066 // Bang down shadow pages too.
1067 // At this point, (tmp-0) is the last address touched, so don't
1068 // touch it again. (It was touched as (tmp-pagesize) but then tmp
1069 // was post-decremented.) Skip this address by starting at i=1, and
1070 // touch a few more pages below. N.B. It is important to touch all
1071 // the way down including all pages in the shadow zone.
1072 for (int i = 1; i < ((int)JavaThread::stack_shadow_zone_size() / os::vm_page_size()); i++) {
1073 // this could be any sized move but this is can be a debugging crumb
1074 // so the bigger the better.
1075 movptr(Address(tmp, (-i*os::vm_page_size())), size );
1076 }
1077 }
1078
1079 void MacroAssembler::reserved_stack_check() {
1080 // testing if reserved zone needs to be enabled
1081 Label no_reserved_zone_enabling;
1082 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
1083 NOT_LP64(get_thread(rsi);)
1084
1085 cmpptr(rsp, Address(thread, JavaThread::reserved_stack_activation_offset()));
1086 jcc(Assembler::below, no_reserved_zone_enabling);
1087
1088 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), thread);
1089 jump(RuntimeAddress(StubRoutines::throw_delayed_StackOverflowError_entry()));
1090 should_not_reach_here();
1091
1092 bind(no_reserved_zone_enabling);
1093 }
1094
1095 int MacroAssembler::biased_locking_enter(Register lock_reg,
1096 Register obj_reg,
1097 Register swap_reg,
1098 Register tmp_reg,
1099 bool swap_reg_contains_mark,
1100 Label& done,
1101 Label* slow_case,
1102 BiasedLockingCounters* counters) {
1103 assert(UseBiasedLocking, "why call this otherwise?");
1104 assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq");
1105 assert(tmp_reg != noreg, "tmp_reg must be supplied");
1106 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg);
1107 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
1108 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes());
1109 NOT_LP64( Address saved_mark_addr(lock_reg, 0); )
1110
1111 if (PrintBiasedLockingStatistics && counters == NULL) {
1112 counters = BiasedLocking::counters();
1113 }
1114 // Biased locking
1115 // See whether the lock is currently biased toward our thread and
1116 // whether the epoch is still valid
1117 // Note that the runtime guarantees sufficient alignment of JavaThread
1118 // pointers to allow age to be placed into low bits
1119 // First check to see whether biasing is even enabled for this object
1120 Label cas_label;
1121 int null_check_offset = -1;
1122 if (!swap_reg_contains_mark) {
1123 null_check_offset = offset();
1124 movptr(swap_reg, mark_addr);
1125 }
1126 movptr(tmp_reg, swap_reg);
1127 andptr(tmp_reg, markOopDesc::biased_lock_mask_in_place);
1128 cmpptr(tmp_reg, markOopDesc::biased_lock_pattern);
1129 jcc(Assembler::notEqual, cas_label);
1130 // The bias pattern is present in the object's header. Need to check
1131 // whether the bias owner and the epoch are both still current.
1132 #ifndef _LP64
1133 // Note that because there is no current thread register on x86_32 we
1134 // need to store off the mark word we read out of the object to
1135 // avoid reloading it and needing to recheck invariants below. This
1136 // store is unfortunate but it makes the overall code shorter and
1137 // simpler.
1138 movptr(saved_mark_addr, swap_reg);
1139 #endif
1140 if (swap_reg_contains_mark) {
1141 null_check_offset = offset();
1142 }
1143 load_prototype_header(tmp_reg, obj_reg);
1144 #ifdef _LP64
1145 orptr(tmp_reg, r15_thread);
1146 xorptr(tmp_reg, swap_reg);
1147 Register header_reg = tmp_reg;
1148 #else
1149 xorptr(tmp_reg, swap_reg);
1150 get_thread(swap_reg);
1151 xorptr(swap_reg, tmp_reg);
1152 Register header_reg = swap_reg;
1153 #endif
1154 andptr(header_reg, ~((int) markOopDesc::age_mask_in_place));
1155 if (counters != NULL) {
1156 cond_inc32(Assembler::zero,
1157 ExternalAddress((address) counters->biased_lock_entry_count_addr()));
1158 }
1159 jcc(Assembler::equal, done);
1160
1161 Label try_revoke_bias;
1162 Label try_rebias;
1163
1164 // At this point we know that the header has the bias pattern and
1165 // that we are not the bias owner in the current epoch. We need to
1166 // figure out more details about the state of the header in order to
1167 // know what operations can be legally performed on the object's
1168 // header.
1169
1170 // If the low three bits in the xor result aren't clear, that means
1171 // the prototype header is no longer biased and we have to revoke
1172 // the bias on this object.
1173 testptr(header_reg, markOopDesc::biased_lock_mask_in_place);
1174 jccb(Assembler::notZero, try_revoke_bias);
1175
1176 // Biasing is still enabled for this data type. See whether the
1177 // epoch of the current bias is still valid, meaning that the epoch
1178 // bits of the mark word are equal to the epoch bits of the
1179 // prototype header. (Note that the prototype header's epoch bits
1180 // only change at a safepoint.) If not, attempt to rebias the object
1181 // toward the current thread. Note that we must be absolutely sure
1182 // that the current epoch is invalid in order to do this because
1183 // otherwise the manipulations it performs on the mark word are
1184 // illegal.
1185 testptr(header_reg, markOopDesc::epoch_mask_in_place);
1186 jccb(Assembler::notZero, try_rebias);
1187
1188 // The epoch of the current bias is still valid but we know nothing
1189 // about the owner; it might be set or it might be clear. Try to
1190 // acquire the bias of the object using an atomic operation. If this
1191 // fails we will go in to the runtime to revoke the object's bias.
1192 // Note that we first construct the presumed unbiased header so we
1193 // don't accidentally blow away another thread's valid bias.
1194 NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1195 andptr(swap_reg,
1196 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
1197 #ifdef _LP64
1198 movptr(tmp_reg, swap_reg);
1199 orptr(tmp_reg, r15_thread);
1200 #else
1201 get_thread(tmp_reg);
1202 orptr(tmp_reg, swap_reg);
1203 #endif
1204 if (os::is_MP()) {
1205 lock();
1206 }
1207 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1208 // If the biasing toward our thread failed, this means that
1209 // another thread succeeded in biasing it toward itself and we
1210 // need to revoke that bias. The revocation will occur in the
1211 // interpreter runtime in the slow case.
1212 if (counters != NULL) {
1213 cond_inc32(Assembler::zero,
1214 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr()));
1215 }
1216 if (slow_case != NULL) {
1217 jcc(Assembler::notZero, *slow_case);
1218 }
1219 jmp(done);
1220
1221 bind(try_rebias);
1222 // At this point we know the epoch has expired, meaning that the
1223 // current "bias owner", if any, is actually invalid. Under these
1224 // circumstances _only_, we are allowed to use the current header's
1225 // value as the comparison value when doing the cas to acquire the
1226 // bias in the current epoch. In other words, we allow transfer of
1227 // the bias from one thread to another directly in this situation.
1228 //
1229 // FIXME: due to a lack of registers we currently blow away the age
1230 // bits in this situation. Should attempt to preserve them.
1231 load_prototype_header(tmp_reg, obj_reg);
1232 #ifdef _LP64
1233 orptr(tmp_reg, r15_thread);
1234 #else
1235 get_thread(swap_reg);
1236 orptr(tmp_reg, swap_reg);
1237 movptr(swap_reg, saved_mark_addr);
1238 #endif
1239 if (os::is_MP()) {
1240 lock();
1241 }
1242 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1243 // If the biasing toward our thread failed, then another thread
1244 // succeeded in biasing it toward itself and we need to revoke that
1245 // bias. The revocation will occur in the runtime in the slow case.
1246 if (counters != NULL) {
1247 cond_inc32(Assembler::zero,
1248 ExternalAddress((address) counters->rebiased_lock_entry_count_addr()));
1249 }
1250 if (slow_case != NULL) {
1251 jcc(Assembler::notZero, *slow_case);
1252 }
1253 jmp(done);
1254
1255 bind(try_revoke_bias);
1256 // The prototype mark in the klass doesn't have the bias bit set any
1257 // more, indicating that objects of this data type are not supposed
1258 // to be biased any more. We are going to try to reset the mark of
1259 // this object to the prototype value and fall through to the
1260 // CAS-based locking scheme. Note that if our CAS fails, it means
1261 // that another thread raced us for the privilege of revoking the
1262 // bias of this particular object, so it's okay to continue in the
1263 // normal locking code.
1264 //
1265 // FIXME: due to a lack of registers we currently blow away the age
1266 // bits in this situation. Should attempt to preserve them.
1267 NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1268 load_prototype_header(tmp_reg, obj_reg);
1269 if (os::is_MP()) {
1270 lock();
1271 }
1272 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1273 // Fall through to the normal CAS-based lock, because no matter what
1274 // the result of the above CAS, some thread must have succeeded in
1275 // removing the bias bit from the object's header.
1276 if (counters != NULL) {
1277 cond_inc32(Assembler::zero,
1278 ExternalAddress((address) counters->revoked_lock_entry_count_addr()));
1279 }
1280
1281 bind(cas_label);
1282
1283 return null_check_offset;
1284 }
1285
1286 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) {
1287 assert(UseBiasedLocking, "why call this otherwise?");
1288
1289 // Check for biased locking unlock case, which is a no-op
1290 // Note: we do not have to check the thread ID for two reasons.
1291 // First, the interpreter checks for IllegalMonitorStateException at
1292 // a higher level. Second, if the bias was revoked while we held the
1293 // lock, the object could not be rebiased toward another thread, so
1294 // the bias bit would be clear.
1295 movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
1296 andptr(temp_reg, markOopDesc::biased_lock_mask_in_place);
1297 cmpptr(temp_reg, markOopDesc::biased_lock_pattern);
1298 jcc(Assembler::equal, done);
1299 }
1300
1301 #ifdef COMPILER2
1302
1303 #if INCLUDE_RTM_OPT
1304
1305 // Update rtm_counters based on abort status
1306 // input: abort_status
1307 // rtm_counters (RTMLockingCounters*)
1308 // flags are killed
1309 void MacroAssembler::rtm_counters_update(Register abort_status, Register rtm_counters) {
1310
1311 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abort_count_offset()));
1312 if (PrintPreciseRTMLockingStatistics) {
1313 for (int i = 0; i < RTMLockingCounters::ABORT_STATUS_LIMIT; i++) {
1314 Label check_abort;
1315 testl(abort_status, (1<<i));
1316 jccb(Assembler::equal, check_abort);
1317 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abortX_count_offset() + (i * sizeof(uintx))));
1318 bind(check_abort);
1319 }
1320 }
1321 }
1322
1323 // Branch if (random & (count-1) != 0), count is 2^n
1324 // tmp, scr and flags are killed
1325 void MacroAssembler::branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel) {
1326 assert(tmp == rax, "");
1327 assert(scr == rdx, "");
1328 rdtsc(); // modifies EDX:EAX
1329 andptr(tmp, count-1);
1330 jccb(Assembler::notZero, brLabel);
1331 }
1332
1333 // Perform abort ratio calculation, set no_rtm bit if high ratio
1334 // input: rtm_counters_Reg (RTMLockingCounters* address)
1335 // tmpReg, rtm_counters_Reg and flags are killed
1336 void MacroAssembler::rtm_abort_ratio_calculation(Register tmpReg,
1337 Register rtm_counters_Reg,
1338 RTMLockingCounters* rtm_counters,
1339 Metadata* method_data) {
1340 Label L_done, L_check_always_rtm1, L_check_always_rtm2;
1341
1342 if (RTMLockingCalculationDelay > 0) {
1343 // Delay calculation
1344 movptr(tmpReg, ExternalAddress((address) RTMLockingCounters::rtm_calculation_flag_addr()), tmpReg);
1345 testptr(tmpReg, tmpReg);
1346 jccb(Assembler::equal, L_done);
1347 }
1348 // Abort ratio calculation only if abort_count > RTMAbortThreshold
1349 // Aborted transactions = abort_count * 100
1350 // All transactions = total_count * RTMTotalCountIncrRate
1351 // Set no_rtm bit if (Aborted transactions >= All transactions * RTMAbortRatio)
1352
1353 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::abort_count_offset()));
1354 cmpptr(tmpReg, RTMAbortThreshold);
1355 jccb(Assembler::below, L_check_always_rtm2);
1356 imulptr(tmpReg, tmpReg, 100);
1357
1358 Register scrReg = rtm_counters_Reg;
1359 movptr(scrReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1360 imulptr(scrReg, scrReg, RTMTotalCountIncrRate);
1361 imulptr(scrReg, scrReg, RTMAbortRatio);
1362 cmpptr(tmpReg, scrReg);
1363 jccb(Assembler::below, L_check_always_rtm1);
1364 if (method_data != NULL) {
1365 // set rtm_state to "no rtm" in MDO
1366 mov_metadata(tmpReg, method_data);
1367 if (os::is_MP()) {
1368 lock();
1369 }
1370 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), NoRTM);
1371 }
1372 jmpb(L_done);
1373 bind(L_check_always_rtm1);
1374 // Reload RTMLockingCounters* address
1375 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1376 bind(L_check_always_rtm2);
1377 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1378 cmpptr(tmpReg, RTMLockingThreshold / RTMTotalCountIncrRate);
1379 jccb(Assembler::below, L_done);
1380 if (method_data != NULL) {
1381 // set rtm_state to "always rtm" in MDO
1382 mov_metadata(tmpReg, method_data);
1383 if (os::is_MP()) {
1384 lock();
1385 }
1386 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), UseRTM);
1387 }
1388 bind(L_done);
1389 }
1390
1391 // Update counters and perform abort ratio calculation
1392 // input: abort_status_Reg
1393 // rtm_counters_Reg, flags are killed
1394 void MacroAssembler::rtm_profiling(Register abort_status_Reg,
1395 Register rtm_counters_Reg,
1396 RTMLockingCounters* rtm_counters,
1397 Metadata* method_data,
1398 bool profile_rtm) {
1399
1400 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1401 // update rtm counters based on rax value at abort
1402 // reads abort_status_Reg, updates flags
1403 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1404 rtm_counters_update(abort_status_Reg, rtm_counters_Reg);
1405 if (profile_rtm) {
1406 // Save abort status because abort_status_Reg is used by following code.
1407 if (RTMRetryCount > 0) {
1408 push(abort_status_Reg);
1409 }
1410 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1411 rtm_abort_ratio_calculation(abort_status_Reg, rtm_counters_Reg, rtm_counters, method_data);
1412 // restore abort status
1413 if (RTMRetryCount > 0) {
1414 pop(abort_status_Reg);
1415 }
1416 }
1417 }
1418
1419 // Retry on abort if abort's status is 0x6: can retry (0x2) | memory conflict (0x4)
1420 // inputs: retry_count_Reg
1421 // : abort_status_Reg
1422 // output: retry_count_Reg decremented by 1
1423 // flags are killed
1424 void MacroAssembler::rtm_retry_lock_on_abort(Register retry_count_Reg, Register abort_status_Reg, Label& retryLabel) {
1425 Label doneRetry;
1426 assert(abort_status_Reg == rax, "");
1427 // The abort reason bits are in eax (see all states in rtmLocking.hpp)
1428 // 0x6 = conflict on which we can retry (0x2) | memory conflict (0x4)
1429 // if reason is in 0x6 and retry count != 0 then retry
1430 andptr(abort_status_Reg, 0x6);
1431 jccb(Assembler::zero, doneRetry);
1432 testl(retry_count_Reg, retry_count_Reg);
1433 jccb(Assembler::zero, doneRetry);
1434 pause();
1435 decrementl(retry_count_Reg);
1436 jmp(retryLabel);
1437 bind(doneRetry);
1438 }
1439
1440 // Spin and retry if lock is busy,
1441 // inputs: box_Reg (monitor address)
1442 // : retry_count_Reg
1443 // output: retry_count_Reg decremented by 1
1444 // : clear z flag if retry count exceeded
1445 // tmp_Reg, scr_Reg, flags are killed
1446 void MacroAssembler::rtm_retry_lock_on_busy(Register retry_count_Reg, Register box_Reg,
1447 Register tmp_Reg, Register scr_Reg, Label& retryLabel) {
1448 Label SpinLoop, SpinExit, doneRetry;
1449 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1450
1451 testl(retry_count_Reg, retry_count_Reg);
1452 jccb(Assembler::zero, doneRetry);
1453 decrementl(retry_count_Reg);
1454 movptr(scr_Reg, RTMSpinLoopCount);
1455
1456 bind(SpinLoop);
1457 pause();
1458 decrementl(scr_Reg);
1459 jccb(Assembler::lessEqual, SpinExit);
1460 movptr(tmp_Reg, Address(box_Reg, owner_offset));
1461 testptr(tmp_Reg, tmp_Reg);
1462 jccb(Assembler::notZero, SpinLoop);
1463
1464 bind(SpinExit);
1465 jmp(retryLabel);
1466 bind(doneRetry);
1467 incrementl(retry_count_Reg); // clear z flag
1468 }
1469
1470 // Use RTM for normal stack locks
1471 // Input: objReg (object to lock)
1472 void MacroAssembler::rtm_stack_locking(Register objReg, Register tmpReg, Register scrReg,
1473 Register retry_on_abort_count_Reg,
1474 RTMLockingCounters* stack_rtm_counters,
1475 Metadata* method_data, bool profile_rtm,
1476 Label& DONE_LABEL, Label& IsInflated) {
1477 assert(UseRTMForStackLocks, "why call this otherwise?");
1478 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
1479 assert(tmpReg == rax, "");
1480 assert(scrReg == rdx, "");
1481 Label L_rtm_retry, L_decrement_retry, L_on_abort;
1482
1483 if (RTMRetryCount > 0) {
1484 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1485 bind(L_rtm_retry);
1486 }
1487 movptr(tmpReg, Address(objReg, 0));
1488 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased
1489 jcc(Assembler::notZero, IsInflated);
1490
1491 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1492 Label L_noincrement;
1493 if (RTMTotalCountIncrRate > 1) {
1494 // tmpReg, scrReg and flags are killed
1495 branch_on_random_using_rdtsc(tmpReg, scrReg, (int)RTMTotalCountIncrRate, L_noincrement);
1496 }
1497 assert(stack_rtm_counters != NULL, "should not be NULL when profiling RTM");
1498 atomic_incptr(ExternalAddress((address)stack_rtm_counters->total_count_addr()), scrReg);
1499 bind(L_noincrement);
1500 }
1501 xbegin(L_on_abort);
1502 movptr(tmpReg, Address(objReg, 0)); // fetch markword
1503 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
1504 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked
1505 jcc(Assembler::equal, DONE_LABEL); // all done if unlocked
1506
1507 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1508 if (UseRTMXendForLockBusy) {
1509 xend();
1510 movptr(abort_status_Reg, 0x2); // Set the abort status to 2 (so we can retry)
1511 jmp(L_decrement_retry);
1512 }
1513 else {
1514 xabort(0);
1515 }
1516 bind(L_on_abort);
1517 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1518 rtm_profiling(abort_status_Reg, scrReg, stack_rtm_counters, method_data, profile_rtm);
1519 }
1520 bind(L_decrement_retry);
1521 if (RTMRetryCount > 0) {
1522 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1523 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1524 }
1525 }
1526
1527 // Use RTM for inflating locks
1528 // inputs: objReg (object to lock)
1529 // boxReg (on-stack box address (displaced header location) - KILLED)
1530 // tmpReg (ObjectMonitor address + markOopDesc::monitor_value)
1531 void MacroAssembler::rtm_inflated_locking(Register objReg, Register boxReg, Register tmpReg,
1532 Register scrReg, Register retry_on_busy_count_Reg,
1533 Register retry_on_abort_count_Reg,
1534 RTMLockingCounters* rtm_counters,
1535 Metadata* method_data, bool profile_rtm,
1536 Label& DONE_LABEL) {
1537 assert(UseRTMLocking, "why call this otherwise?");
1538 assert(tmpReg == rax, "");
1539 assert(scrReg == rdx, "");
1540 Label L_rtm_retry, L_decrement_retry, L_on_abort;
1541 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1542
1543 // Without cast to int32_t a movptr will destroy r10 which is typically obj
1544 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1545 movptr(boxReg, tmpReg); // Save ObjectMonitor address
1546
1547 if (RTMRetryCount > 0) {
1548 movl(retry_on_busy_count_Reg, RTMRetryCount); // Retry on lock busy
1549 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1550 bind(L_rtm_retry);
1551 }
1552 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1553 Label L_noincrement;
1554 if (RTMTotalCountIncrRate > 1) {
1555 // tmpReg, scrReg and flags are killed
1556 branch_on_random_using_rdtsc(tmpReg, scrReg, (int)RTMTotalCountIncrRate, L_noincrement);
1557 }
1558 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1559 atomic_incptr(ExternalAddress((address)rtm_counters->total_count_addr()), scrReg);
1560 bind(L_noincrement);
1561 }
1562 xbegin(L_on_abort);
1563 movptr(tmpReg, Address(objReg, 0));
1564 movptr(tmpReg, Address(tmpReg, owner_offset));
1565 testptr(tmpReg, tmpReg);
1566 jcc(Assembler::zero, DONE_LABEL);
1567 if (UseRTMXendForLockBusy) {
1568 xend();
1569 jmp(L_decrement_retry);
1570 }
1571 else {
1572 xabort(0);
1573 }
1574 bind(L_on_abort);
1575 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1576 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1577 rtm_profiling(abort_status_Reg, scrReg, rtm_counters, method_data, profile_rtm);
1578 }
1579 if (RTMRetryCount > 0) {
1580 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1581 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1582 }
1583
1584 movptr(tmpReg, Address(boxReg, owner_offset)) ;
1585 testptr(tmpReg, tmpReg) ;
1586 jccb(Assembler::notZero, L_decrement_retry) ;
1587
1588 // Appears unlocked - try to swing _owner from null to non-null.
1589 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1590 #ifdef _LP64
1591 Register threadReg = r15_thread;
1592 #else
1593 get_thread(scrReg);
1594 Register threadReg = scrReg;
1595 #endif
1596 if (os::is_MP()) {
1597 lock();
1598 }
1599 cmpxchgptr(threadReg, Address(boxReg, owner_offset)); // Updates tmpReg
1600
1601 if (RTMRetryCount > 0) {
1602 // success done else retry
1603 jccb(Assembler::equal, DONE_LABEL) ;
1604 bind(L_decrement_retry);
1605 // Spin and retry if lock is busy.
1606 rtm_retry_lock_on_busy(retry_on_busy_count_Reg, boxReg, tmpReg, scrReg, L_rtm_retry);
1607 }
1608 else {
1609 bind(L_decrement_retry);
1610 }
1611 }
1612
1613 #endif // INCLUDE_RTM_OPT
1614
1615 // Fast_Lock and Fast_Unlock used by C2
1616
1617 // Because the transitions from emitted code to the runtime
1618 // monitorenter/exit helper stubs are so slow it's critical that
1619 // we inline both the stack-locking fast-path and the inflated fast path.
1620 //
1621 // See also: cmpFastLock and cmpFastUnlock.
1622 //
1623 // What follows is a specialized inline transliteration of the code
1624 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
1625 // another option would be to emit TrySlowEnter and TrySlowExit methods
1626 // at startup-time. These methods would accept arguments as
1627 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
1628 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
1629 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
1630 // In practice, however, the # of lock sites is bounded and is usually small.
1631 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
1632 // if the processor uses simple bimodal branch predictors keyed by EIP
1633 // Since the helper routines would be called from multiple synchronization
1634 // sites.
1635 //
1636 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
1637 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
1638 // to those specialized methods. That'd give us a mostly platform-independent
1639 // implementation that the JITs could optimize and inline at their pleasure.
1640 // Done correctly, the only time we'd need to cross to native could would be
1641 // to park() or unpark() threads. We'd also need a few more unsafe operators
1642 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
1643 // (b) explicit barriers or fence operations.
1644 //
1645 // TODO:
1646 //
1647 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
1648 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
1649 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
1650 // the lock operators would typically be faster than reifying Self.
1651 //
1652 // * Ideally I'd define the primitives as:
1653 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
1654 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
1655 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
1656 // Instead, we're stuck with a rather awkward and brittle register assignments below.
1657 // Furthermore the register assignments are overconstrained, possibly resulting in
1658 // sub-optimal code near the synchronization site.
1659 //
1660 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
1661 // Alternately, use a better sp-proximity test.
1662 //
1663 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
1664 // Either one is sufficient to uniquely identify a thread.
1665 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
1666 //
1667 // * Intrinsify notify() and notifyAll() for the common cases where the
1668 // object is locked by the calling thread but the waitlist is empty.
1669 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
1670 //
1671 // * use jccb and jmpb instead of jcc and jmp to improve code density.
1672 // But beware of excessive branch density on AMD Opterons.
1673 //
1674 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
1675 // or failure of the fast-path. If the fast-path fails then we pass
1676 // control to the slow-path, typically in C. In Fast_Lock and
1677 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
1678 // will emit a conditional branch immediately after the node.
1679 // So we have branches to branches and lots of ICC.ZF games.
1680 // Instead, it might be better to have C2 pass a "FailureLabel"
1681 // into Fast_Lock and Fast_Unlock. In the case of success, control
1682 // will drop through the node. ICC.ZF is undefined at exit.
1683 // In the case of failure, the node will branch directly to the
1684 // FailureLabel
1685
1686
1687 // obj: object to lock
1688 // box: on-stack box address (displaced header location) - KILLED
1689 // rax,: tmp -- KILLED
1690 // scr: tmp -- KILLED
1691 void MacroAssembler::fast_lock(Register objReg, Register boxReg, Register tmpReg,
1692 Register scrReg, Register cx1Reg, Register cx2Reg,
1693 BiasedLockingCounters* counters,
1694 RTMLockingCounters* rtm_counters,
1695 RTMLockingCounters* stack_rtm_counters,
1696 Metadata* method_data,
1697 bool use_rtm, bool profile_rtm) {
1698 // Ensure the register assignments are disjoint
1699 assert(tmpReg == rax, "");
1700
1701 if (use_rtm) {
1702 assert_different_registers(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg);
1703 } else {
1704 assert(cx1Reg == noreg, "");
1705 assert(cx2Reg == noreg, "");
1706 assert_different_registers(objReg, boxReg, tmpReg, scrReg);
1707 }
1708
1709 if (counters != NULL) {
1710 atomic_incl(ExternalAddress((address)counters->total_entry_count_addr()), scrReg);
1711 }
1712 if (EmitSync & 1) {
1713 // set box->dhw = markOopDesc::unused_mark()
1714 // Force all sync thru slow-path: slow_enter() and slow_exit()
1715 movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1716 cmpptr (rsp, (int32_t)NULL_WORD);
1717 } else {
1718 // Possible cases that we'll encounter in fast_lock
1719 // ------------------------------------------------
1720 // * Inflated
1721 // -- unlocked
1722 // -- Locked
1723 // = by self
1724 // = by other
1725 // * biased
1726 // -- by Self
1727 // -- by other
1728 // * neutral
1729 // * stack-locked
1730 // -- by self
1731 // = sp-proximity test hits
1732 // = sp-proximity test generates false-negative
1733 // -- by other
1734 //
1735
1736 Label IsInflated, DONE_LABEL;
1737
1738 // it's stack-locked, biased or neutral
1739 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
1740 // order to reduce the number of conditional branches in the most common cases.
1741 // Beware -- there's a subtle invariant that fetch of the markword
1742 // at [FETCH], below, will never observe a biased encoding (*101b).
1743 // If this invariant is not held we risk exclusion (safety) failure.
1744 if (UseBiasedLocking && !UseOptoBiasInlining) {
1745 biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, counters);
1746 }
1747
1748 #if INCLUDE_RTM_OPT
1749 if (UseRTMForStackLocks && use_rtm) {
1750 rtm_stack_locking(objReg, tmpReg, scrReg, cx2Reg,
1751 stack_rtm_counters, method_data, profile_rtm,
1752 DONE_LABEL, IsInflated);
1753 }
1754 #endif // INCLUDE_RTM_OPT
1755
1756 movptr(tmpReg, Address(objReg, 0)); // [FETCH]
1757 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased
1758 jccb(Assembler::notZero, IsInflated);
1759
1760 // Attempt stack-locking ...
1761 orptr (tmpReg, markOopDesc::unlocked_value);
1762 movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
1763 if (os::is_MP()) {
1764 lock();
1765 }
1766 cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
1767 if (counters != NULL) {
1768 cond_inc32(Assembler::equal,
1769 ExternalAddress((address)counters->fast_path_entry_count_addr()));
1770 }
1771 jcc(Assembler::equal, DONE_LABEL); // Success
1772
1773 // Recursive locking.
1774 // The object is stack-locked: markword contains stack pointer to BasicLock.
1775 // Locked by current thread if difference with current SP is less than one page.
1776 subptr(tmpReg, rsp);
1777 // Next instruction set ZFlag == 1 (Success) if difference is less then one page.
1778 andptr(tmpReg, (int32_t) (NOT_LP64(0xFFFFF003) LP64_ONLY(7 - os::vm_page_size())) );
1779 movptr(Address(boxReg, 0), tmpReg);
1780 if (counters != NULL) {
1781 cond_inc32(Assembler::equal,
1782 ExternalAddress((address)counters->fast_path_entry_count_addr()));
1783 }
1784 jmp(DONE_LABEL);
1785
1786 bind(IsInflated);
1787 // The object is inflated. tmpReg contains pointer to ObjectMonitor* + markOopDesc::monitor_value
1788
1789 #if INCLUDE_RTM_OPT
1790 // Use the same RTM locking code in 32- and 64-bit VM.
1791 if (use_rtm) {
1792 rtm_inflated_locking(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg,
1793 rtm_counters, method_data, profile_rtm, DONE_LABEL);
1794 } else {
1795 #endif // INCLUDE_RTM_OPT
1796
1797 #ifndef _LP64
1798 // The object is inflated.
1799
1800 // boxReg refers to the on-stack BasicLock in the current frame.
1801 // We'd like to write:
1802 // set box->_displaced_header = markOopDesc::unused_mark(). Any non-0 value suffices.
1803 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
1804 // additional latency as we have another ST in the store buffer that must drain.
1805
1806 if (EmitSync & 8192) {
1807 movptr(Address(boxReg, 0), 3); // results in ST-before-CAS penalty
1808 get_thread (scrReg);
1809 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
1810 movptr(tmpReg, NULL_WORD); // consider: xor vs mov
1811 if (os::is_MP()) {
1812 lock();
1813 }
1814 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1815 } else
1816 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
1817 // register juggle because we need tmpReg for cmpxchgptr below
1818 movptr(scrReg, boxReg);
1819 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
1820
1821 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
1822 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
1823 // prefetchw [eax + Offset(_owner)-2]
1824 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1825 }
1826
1827 if ((EmitSync & 64) == 0) {
1828 // Optimistic form: consider XORL tmpReg,tmpReg
1829 movptr(tmpReg, NULL_WORD);
1830 } else {
1831 // Can suffer RTS->RTO upgrades on shared or cold $ lines
1832 // Test-And-CAS instead of CAS
1833 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner
1834 testptr(tmpReg, tmpReg); // Locked ?
1835 jccb (Assembler::notZero, DONE_LABEL);
1836 }
1837
1838 // Appears unlocked - try to swing _owner from null to non-null.
1839 // Ideally, I'd manifest "Self" with get_thread and then attempt
1840 // to CAS the register containing Self into m->Owner.
1841 // But we don't have enough registers, so instead we can either try to CAS
1842 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
1843 // we later store "Self" into m->Owner. Transiently storing a stack address
1844 // (rsp or the address of the box) into m->owner is harmless.
1845 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1846 if (os::is_MP()) {
1847 lock();
1848 }
1849 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1850 movptr(Address(scrReg, 0), 3); // box->_displaced_header = 3
1851 // If we weren't able to swing _owner from NULL to the BasicLock
1852 // then take the slow path.
1853 jccb (Assembler::notZero, DONE_LABEL);
1854 // update _owner from BasicLock to thread
1855 get_thread (scrReg); // beware: clobbers ICCs
1856 movptr(Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), scrReg);
1857 xorptr(boxReg, boxReg); // set icc.ZFlag = 1 to indicate success
1858
1859 // If the CAS fails we can either retry or pass control to the slow-path.
1860 // We use the latter tactic.
1861 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1862 // If the CAS was successful ...
1863 // Self has acquired the lock
1864 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1865 // Intentional fall-through into DONE_LABEL ...
1866 } else {
1867 movptr(Address(boxReg, 0), intptr_t(markOopDesc::unused_mark())); // results in ST-before-CAS penalty
1868 movptr(boxReg, tmpReg);
1869
1870 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
1871 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
1872 // prefetchw [eax + Offset(_owner)-2]
1873 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1874 }
1875
1876 if ((EmitSync & 64) == 0) {
1877 // Optimistic form
1878 xorptr (tmpReg, tmpReg);
1879 } else {
1880 // Can suffer RTS->RTO upgrades on shared or cold $ lines
1881 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner
1882 testptr(tmpReg, tmpReg); // Locked ?
1883 jccb (Assembler::notZero, DONE_LABEL);
1884 }
1885
1886 // Appears unlocked - try to swing _owner from null to non-null.
1887 // Use either "Self" (in scr) or rsp as thread identity in _owner.
1888 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1889 get_thread (scrReg);
1890 if (os::is_MP()) {
1891 lock();
1892 }
1893 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1894
1895 // If the CAS fails we can either retry or pass control to the slow-path.
1896 // We use the latter tactic.
1897 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1898 // If the CAS was successful ...
1899 // Self has acquired the lock
1900 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1901 // Intentional fall-through into DONE_LABEL ...
1902 }
1903 #else // _LP64
1904 // It's inflated
1905 movq(scrReg, tmpReg);
1906 xorq(tmpReg, tmpReg);
1907
1908 if (os::is_MP()) {
1909 lock();
1910 }
1911 cmpxchgptr(r15_thread, Address(scrReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1912 // Unconditionally set box->_displaced_header = markOopDesc::unused_mark().
1913 // Without cast to int32_t movptr will destroy r10 which is typically obj.
1914 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1915 // Intentional fall-through into DONE_LABEL ...
1916 // Propagate ICC.ZF from CAS above into DONE_LABEL.
1917 #endif // _LP64
1918 #if INCLUDE_RTM_OPT
1919 } // use_rtm()
1920 #endif
1921 // DONE_LABEL is a hot target - we'd really like to place it at the
1922 // start of cache line by padding with NOPs.
1923 // See the AMD and Intel software optimization manuals for the
1924 // most efficient "long" NOP encodings.
1925 // Unfortunately none of our alignment mechanisms suffice.
1926 bind(DONE_LABEL);
1927
1928 // At DONE_LABEL the icc ZFlag is set as follows ...
1929 // Fast_Unlock uses the same protocol.
1930 // ZFlag == 1 -> Success
1931 // ZFlag == 0 -> Failure - force control through the slow-path
1932 }
1933 }
1934
1935 // obj: object to unlock
1936 // box: box address (displaced header location), killed. Must be EAX.
1937 // tmp: killed, cannot be obj nor box.
1938 //
1939 // Some commentary on balanced locking:
1940 //
1941 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
1942 // Methods that don't have provably balanced locking are forced to run in the
1943 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
1944 // The interpreter provides two properties:
1945 // I1: At return-time the interpreter automatically and quietly unlocks any
1946 // objects acquired the current activation (frame). Recall that the
1947 // interpreter maintains an on-stack list of locks currently held by
1948 // a frame.
1949 // I2: If a method attempts to unlock an object that is not held by the
1950 // the frame the interpreter throws IMSX.
1951 //
1952 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
1953 // B() doesn't have provably balanced locking so it runs in the interpreter.
1954 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
1955 // is still locked by A().
1956 //
1957 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
1958 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
1959 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
1960 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
1961 // Arguably given that the spec legislates the JNI case as undefined our implementation
1962 // could reasonably *avoid* checking owner in Fast_Unlock().
1963 // In the interest of performance we elide m->Owner==Self check in unlock.
1964 // A perfectly viable alternative is to elide the owner check except when
1965 // Xcheck:jni is enabled.
1966
1967 void MacroAssembler::fast_unlock(Register objReg, Register boxReg, Register tmpReg, bool use_rtm) {
1968 assert(boxReg == rax, "");
1969 assert_different_registers(objReg, boxReg, tmpReg);
1970
1971 if (EmitSync & 4) {
1972 // Disable - inhibit all inlining. Force control through the slow-path
1973 cmpptr (rsp, 0);
1974 } else {
1975 Label DONE_LABEL, Stacked, CheckSucc;
1976
1977 // Critically, the biased locking test must have precedence over
1978 // and appear before the (box->dhw == 0) recursive stack-lock test.
1979 if (UseBiasedLocking && !UseOptoBiasInlining) {
1980 biased_locking_exit(objReg, tmpReg, DONE_LABEL);
1981 }
1982
1983 #if INCLUDE_RTM_OPT
1984 if (UseRTMForStackLocks && use_rtm) {
1985 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
1986 Label L_regular_unlock;
1987 movptr(tmpReg, Address(objReg, 0)); // fetch markword
1988 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
1989 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked
1990 jccb(Assembler::notEqual, L_regular_unlock); // if !HLE RegularLock
1991 xend(); // otherwise end...
1992 jmp(DONE_LABEL); // ... and we're done
1993 bind(L_regular_unlock);
1994 }
1995 #endif
1996
1997 cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD); // Examine the displaced header
1998 jcc (Assembler::zero, DONE_LABEL); // 0 indicates recursive stack-lock
1999 movptr(tmpReg, Address(objReg, 0)); // Examine the object's markword
2000 testptr(tmpReg, markOopDesc::monitor_value); // Inflated?
2001 jccb (Assembler::zero, Stacked);
2002
2003 // It's inflated.
2004 #if INCLUDE_RTM_OPT
2005 if (use_rtm) {
2006 Label L_regular_inflated_unlock;
2007 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
2008 movptr(boxReg, Address(tmpReg, owner_offset));
2009 testptr(boxReg, boxReg);
2010 jccb(Assembler::notZero, L_regular_inflated_unlock);
2011 xend();
2012 jmpb(DONE_LABEL);
2013 bind(L_regular_inflated_unlock);
2014 }
2015 #endif
2016
2017 // Despite our balanced locking property we still check that m->_owner == Self
2018 // as java routines or native JNI code called by this thread might
2019 // have released the lock.
2020 // Refer to the comments in synchronizer.cpp for how we might encode extra
2021 // state in _succ so we can avoid fetching EntryList|cxq.
2022 //
2023 // I'd like to add more cases in fast_lock() and fast_unlock() --
2024 // such as recursive enter and exit -- but we have to be wary of
2025 // I$ bloat, T$ effects and BP$ effects.
2026 //
2027 // If there's no contention try a 1-0 exit. That is, exit without
2028 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
2029 // we detect and recover from the race that the 1-0 exit admits.
2030 //
2031 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
2032 // before it STs null into _owner, releasing the lock. Updates
2033 // to data protected by the critical section must be visible before
2034 // we drop the lock (and thus before any other thread could acquire
2035 // the lock and observe the fields protected by the lock).
2036 // IA32's memory-model is SPO, so STs are ordered with respect to
2037 // each other and there's no need for an explicit barrier (fence).
2038 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
2039 #ifndef _LP64
2040 get_thread (boxReg);
2041 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
2042 // prefetchw [ebx + Offset(_owner)-2]
2043 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2044 }
2045
2046 // Note that we could employ various encoding schemes to reduce
2047 // the number of loads below (currently 4) to just 2 or 3.
2048 // Refer to the comments in synchronizer.cpp.
2049 // In practice the chain of fetches doesn't seem to impact performance, however.
2050 xorptr(boxReg, boxReg);
2051 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
2052 // Attempt to reduce branch density - AMD's branch predictor.
2053 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2054 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2055 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2056 jccb (Assembler::notZero, DONE_LABEL);
2057 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2058 jmpb (DONE_LABEL);
2059 } else {
2060 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2061 jccb (Assembler::notZero, DONE_LABEL);
2062 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2063 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2064 jccb (Assembler::notZero, CheckSucc);
2065 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2066 jmpb (DONE_LABEL);
2067 }
2068
2069 // The Following code fragment (EmitSync & 65536) improves the performance of
2070 // contended applications and contended synchronization microbenchmarks.
2071 // Unfortunately the emission of the code - even though not executed - causes regressions
2072 // in scimark and jetstream, evidently because of $ effects. Replacing the code
2073 // with an equal number of never-executed NOPs results in the same regression.
2074 // We leave it off by default.
2075
2076 if ((EmitSync & 65536) != 0) {
2077 Label LSuccess, LGoSlowPath ;
2078
2079 bind (CheckSucc);
2080
2081 // Optional pre-test ... it's safe to elide this
2082 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2083 jccb(Assembler::zero, LGoSlowPath);
2084
2085 // We have a classic Dekker-style idiom:
2086 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
2087 // There are a number of ways to implement the barrier:
2088 // (1) lock:andl &m->_owner, 0
2089 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
2090 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
2091 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
2092 // (2) If supported, an explicit MFENCE is appealing.
2093 // In older IA32 processors MFENCE is slower than lock:add or xchg
2094 // particularly if the write-buffer is full as might be the case if
2095 // if stores closely precede the fence or fence-equivalent instruction.
2096 // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences
2097 // as the situation has changed with Nehalem and Shanghai.
2098 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
2099 // The $lines underlying the top-of-stack should be in M-state.
2100 // The locked add instruction is serializing, of course.
2101 // (4) Use xchg, which is serializing
2102 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
2103 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
2104 // The integer condition codes will tell us if succ was 0.
2105 // Since _succ and _owner should reside in the same $line and
2106 // we just stored into _owner, it's likely that the $line
2107 // remains in M-state for the lock:orl.
2108 //
2109 // We currently use (3), although it's likely that switching to (2)
2110 // is correct for the future.
2111
2112 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2113 if (os::is_MP()) {
2114 lock(); addptr(Address(rsp, 0), 0);
2115 }
2116 // Ratify _succ remains non-null
2117 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), 0);
2118 jccb (Assembler::notZero, LSuccess);
2119
2120 xorptr(boxReg, boxReg); // box is really EAX
2121 if (os::is_MP()) { lock(); }
2122 cmpxchgptr(rsp, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2123 // There's no successor so we tried to regrab the lock with the
2124 // placeholder value. If that didn't work, then another thread
2125 // grabbed the lock so we're done (and exit was a success).
2126 jccb (Assembler::notEqual, LSuccess);
2127 // Since we're low on registers we installed rsp as a placeholding in _owner.
2128 // Now install Self over rsp. This is safe as we're transitioning from
2129 // non-null to non=null
2130 get_thread (boxReg);
2131 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), boxReg);
2132 // Intentional fall-through into LGoSlowPath ...
2133
2134 bind (LGoSlowPath);
2135 orptr(boxReg, 1); // set ICC.ZF=0 to indicate failure
2136 jmpb (DONE_LABEL);
2137
2138 bind (LSuccess);
2139 xorptr(boxReg, boxReg); // set ICC.ZF=1 to indicate success
2140 jmpb (DONE_LABEL);
2141 }
2142
2143 bind (Stacked);
2144 // It's not inflated and it's not recursively stack-locked and it's not biased.
2145 // It must be stack-locked.
2146 // Try to reset the header to displaced header.
2147 // The "box" value on the stack is stable, so we can reload
2148 // and be assured we observe the same value as above.
2149 movptr(tmpReg, Address(boxReg, 0));
2150 if (os::is_MP()) {
2151 lock();
2152 }
2153 cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
2154 // Intention fall-thru into DONE_LABEL
2155
2156 // DONE_LABEL is a hot target - we'd really like to place it at the
2157 // start of cache line by padding with NOPs.
2158 // See the AMD and Intel software optimization manuals for the
2159 // most efficient "long" NOP encodings.
2160 // Unfortunately none of our alignment mechanisms suffice.
2161 if ((EmitSync & 65536) == 0) {
2162 bind (CheckSucc);
2163 }
2164 #else // _LP64
2165 // It's inflated
2166 if (EmitSync & 1024) {
2167 // Emit code to check that _owner == Self
2168 // We could fold the _owner test into subsequent code more efficiently
2169 // than using a stand-alone check, but since _owner checking is off by
2170 // default we don't bother. We also might consider predicating the
2171 // _owner==Self check on Xcheck:jni or running on a debug build.
2172 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2173 xorptr(boxReg, r15_thread);
2174 } else {
2175 xorptr(boxReg, boxReg);
2176 }
2177 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2178 jccb (Assembler::notZero, DONE_LABEL);
2179 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2180 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2181 jccb (Assembler::notZero, CheckSucc);
2182 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD);
2183 jmpb (DONE_LABEL);
2184
2185 if ((EmitSync & 65536) == 0) {
2186 // Try to avoid passing control into the slow_path ...
2187 Label LSuccess, LGoSlowPath ;
2188 bind (CheckSucc);
2189
2190 // The following optional optimization can be elided if necessary
2191 // Effectively: if (succ == null) goto SlowPath
2192 // The code reduces the window for a race, however,
2193 // and thus benefits performance.
2194 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2195 jccb (Assembler::zero, LGoSlowPath);
2196
2197 xorptr(boxReg, boxReg);
2198 if ((EmitSync & 16) && os::is_MP()) {
2199 xchgptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2200 } else {
2201 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD);
2202 if (os::is_MP()) {
2203 // Memory barrier/fence
2204 // Dekker pivot point -- fulcrum : ST Owner; MEMBAR; LD Succ
2205 // Instead of MFENCE we use a dummy locked add of 0 to the top-of-stack.
2206 // This is faster on Nehalem and AMD Shanghai/Barcelona.
2207 // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences
2208 // We might also restructure (ST Owner=0;barrier;LD _Succ) to
2209 // (mov box,0; xchgq box, &m->Owner; LD _succ) .
2210 lock(); addl(Address(rsp, 0), 0);
2211 }
2212 }
2213 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2214 jccb (Assembler::notZero, LSuccess);
2215
2216 // Rare inopportune interleaving - race.
2217 // The successor vanished in the small window above.
2218 // The lock is contended -- (cxq|EntryList) != null -- and there's no apparent successor.
2219 // We need to ensure progress and succession.
2220 // Try to reacquire the lock.
2221 // If that fails then the new owner is responsible for succession and this
2222 // thread needs to take no further action and can exit via the fast path (success).
2223 // If the re-acquire succeeds then pass control into the slow path.
2224 // As implemented, this latter mode is horrible because we generated more
2225 // coherence traffic on the lock *and* artifically extended the critical section
2226 // length while by virtue of passing control into the slow path.
2227
2228 // box is really RAX -- the following CMPXCHG depends on that binding
2229 // cmpxchg R,[M] is equivalent to rax = CAS(M,rax,R)
2230 if (os::is_MP()) { lock(); }
2231 cmpxchgptr(r15_thread, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2232 // There's no successor so we tried to regrab the lock.
2233 // If that didn't work, then another thread grabbed the
2234 // lock so we're done (and exit was a success).
2235 jccb (Assembler::notEqual, LSuccess);
2236 // Intentional fall-through into slow-path
2237
2238 bind (LGoSlowPath);
2239 orl (boxReg, 1); // set ICC.ZF=0 to indicate failure
2240 jmpb (DONE_LABEL);
2241
2242 bind (LSuccess);
2243 testl (boxReg, 0); // set ICC.ZF=1 to indicate success
2244 jmpb (DONE_LABEL);
2245 }
2246
2247 bind (Stacked);
2248 movptr(tmpReg, Address (boxReg, 0)); // re-fetch
2249 if (os::is_MP()) { lock(); }
2250 cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
2251
2252 if (EmitSync & 65536) {
2253 bind (CheckSucc);
2254 }
2255 #endif
2256 bind(DONE_LABEL);
2257 }
2258 }
2259 #endif // COMPILER2
2260
2261 void MacroAssembler::c2bool(Register x) {
2262 // implements x == 0 ? 0 : 1
2263 // note: must only look at least-significant byte of x
2264 // since C-style booleans are stored in one byte
2265 // only! (was bug)
2266 andl(x, 0xFF);
2267 setb(Assembler::notZero, x);
2268 }
2269
2270 // Wouldn't need if AddressLiteral version had new name
2271 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
2272 Assembler::call(L, rtype);
2273 }
2274
2275 void MacroAssembler::call(Register entry) {
2276 Assembler::call(entry);
2277 }
2278
2279 void MacroAssembler::call(AddressLiteral entry) {
2280 if (reachable(entry)) {
2281 Assembler::call_literal(entry.target(), entry.rspec());
2282 } else {
2283 lea(rscratch1, entry);
2284 Assembler::call(rscratch1);
2285 }
2286 }
2287
2288 void MacroAssembler::ic_call(address entry, jint method_index) {
2289 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
2290 movptr(rax, (intptr_t)Universe::non_oop_word());
2291 call(AddressLiteral(entry, rh));
2292 }
2293
2294 // Implementation of call_VM versions
2295
2296 void MacroAssembler::call_VM(Register oop_result,
2297 address entry_point,
2298 bool check_exceptions) {
2299 Label C, E;
2300 call(C, relocInfo::none);
2301 jmp(E);
2302
2303 bind(C);
2304 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
2305 ret(0);
2306
2307 bind(E);
2308 }
2309
2310 void MacroAssembler::call_VM(Register oop_result,
2311 address entry_point,
2312 Register arg_1,
2313 bool check_exceptions) {
2314 Label C, E;
2315 call(C, relocInfo::none);
2316 jmp(E);
2317
2318 bind(C);
2319 pass_arg1(this, arg_1);
2320 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
2321 ret(0);
2322
2323 bind(E);
2324 }
2325
2326 void MacroAssembler::call_VM(Register oop_result,
2327 address entry_point,
2328 Register arg_1,
2329 Register arg_2,
2330 bool check_exceptions) {
2331 Label C, E;
2332 call(C, relocInfo::none);
2333 jmp(E);
2334
2335 bind(C);
2336
2337 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2338
2339 pass_arg2(this, arg_2);
2340 pass_arg1(this, arg_1);
2341 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
2342 ret(0);
2343
2344 bind(E);
2345 }
2346
2347 void MacroAssembler::call_VM(Register oop_result,
2348 address entry_point,
2349 Register arg_1,
2350 Register arg_2,
2351 Register arg_3,
2352 bool check_exceptions) {
2353 Label C, E;
2354 call(C, relocInfo::none);
2355 jmp(E);
2356
2357 bind(C);
2358
2359 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2360 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2361 pass_arg3(this, arg_3);
2362
2363 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2364 pass_arg2(this, arg_2);
2365
2366 pass_arg1(this, arg_1);
2367 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
2368 ret(0);
2369
2370 bind(E);
2371 }
2372
2373 void MacroAssembler::call_VM(Register oop_result,
2374 Register last_java_sp,
2375 address entry_point,
2376 int number_of_arguments,
2377 bool check_exceptions) {
2378 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2379 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2380 }
2381
2382 void MacroAssembler::call_VM(Register oop_result,
2383 Register last_java_sp,
2384 address entry_point,
2385 Register arg_1,
2386 bool check_exceptions) {
2387 pass_arg1(this, arg_1);
2388 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2389 }
2390
2391 void MacroAssembler::call_VM(Register oop_result,
2392 Register last_java_sp,
2393 address entry_point,
2394 Register arg_1,
2395 Register arg_2,
2396 bool check_exceptions) {
2397
2398 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2399 pass_arg2(this, arg_2);
2400 pass_arg1(this, arg_1);
2401 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2402 }
2403
2404 void MacroAssembler::call_VM(Register oop_result,
2405 Register last_java_sp,
2406 address entry_point,
2407 Register arg_1,
2408 Register arg_2,
2409 Register arg_3,
2410 bool check_exceptions) {
2411 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2412 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2413 pass_arg3(this, arg_3);
2414 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2415 pass_arg2(this, arg_2);
2416 pass_arg1(this, arg_1);
2417 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2418 }
2419
2420 void MacroAssembler::super_call_VM(Register oop_result,
2421 Register last_java_sp,
2422 address entry_point,
2423 int number_of_arguments,
2424 bool check_exceptions) {
2425 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2426 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2427 }
2428
2429 void MacroAssembler::super_call_VM(Register oop_result,
2430 Register last_java_sp,
2431 address entry_point,
2432 Register arg_1,
2433 bool check_exceptions) {
2434 pass_arg1(this, arg_1);
2435 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2436 }
2437
2438 void MacroAssembler::super_call_VM(Register oop_result,
2439 Register last_java_sp,
2440 address entry_point,
2441 Register arg_1,
2442 Register arg_2,
2443 bool check_exceptions) {
2444
2445 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2446 pass_arg2(this, arg_2);
2447 pass_arg1(this, arg_1);
2448 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2449 }
2450
2451 void MacroAssembler::super_call_VM(Register oop_result,
2452 Register last_java_sp,
2453 address entry_point,
2454 Register arg_1,
2455 Register arg_2,
2456 Register arg_3,
2457 bool check_exceptions) {
2458 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2459 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2460 pass_arg3(this, arg_3);
2461 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2462 pass_arg2(this, arg_2);
2463 pass_arg1(this, arg_1);
2464 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2465 }
2466
2467 void MacroAssembler::call_VM_base(Register oop_result,
2468 Register java_thread,
2469 Register last_java_sp,
2470 address entry_point,
2471 int number_of_arguments,
2472 bool check_exceptions) {
2473 // determine java_thread register
2474 if (!java_thread->is_valid()) {
2475 #ifdef _LP64
2476 java_thread = r15_thread;
2477 #else
2478 java_thread = rdi;
2479 get_thread(java_thread);
2480 #endif // LP64
2481 }
2482 // determine last_java_sp register
2483 if (!last_java_sp->is_valid()) {
2484 last_java_sp = rsp;
2485 }
2486 // debugging support
2487 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
2488 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
2489 #ifdef ASSERT
2490 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
2491 // r12 is the heapbase.
2492 LP64_ONLY(if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");)
2493 #endif // ASSERT
2494
2495 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
2496 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
2497
2498 // push java thread (becomes first argument of C function)
2499
2500 NOT_LP64(push(java_thread); number_of_arguments++);
2501 LP64_ONLY(mov(c_rarg0, r15_thread));
2502
2503 // set last Java frame before call
2504 assert(last_java_sp != rbp, "can't use ebp/rbp");
2505
2506 // Only interpreter should have to set fp
2507 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL);
2508
2509 // do the call, remove parameters
2510 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
2511
2512 // restore the thread (cannot use the pushed argument since arguments
2513 // may be overwritten by C code generated by an optimizing compiler);
2514 // however can use the register value directly if it is callee saved.
2515 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
2516 // rdi & rsi (also r15) are callee saved -> nothing to do
2517 #ifdef ASSERT
2518 guarantee(java_thread != rax, "change this code");
2519 push(rax);
2520 { Label L;
2521 get_thread(rax);
2522 cmpptr(java_thread, rax);
2523 jcc(Assembler::equal, L);
2524 STOP("MacroAssembler::call_VM_base: rdi not callee saved?");
2525 bind(L);
2526 }
2527 pop(rax);
2528 #endif
2529 } else {
2530 get_thread(java_thread);
2531 }
2532 // reset last Java frame
2533 // Only interpreter should have to clear fp
2534 reset_last_Java_frame(java_thread, true, false);
2535
2536 // C++ interp handles this in the interpreter
2537 check_and_handle_popframe(java_thread);
2538 check_and_handle_earlyret(java_thread);
2539
2540 if (check_exceptions) {
2541 // check for pending exceptions (java_thread is set upon return)
2542 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD);
2543 #ifndef _LP64
2544 jump_cc(Assembler::notEqual,
2545 RuntimeAddress(StubRoutines::forward_exception_entry()));
2546 #else
2547 // This used to conditionally jump to forward_exception however it is
2548 // possible if we relocate that the branch will not reach. So we must jump
2549 // around so we can always reach
2550
2551 Label ok;
2552 jcc(Assembler::equal, ok);
2553 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
2554 bind(ok);
2555 #endif // LP64
2556 }
2557
2558 // get oop result if there is one and reset the value in the thread
2559 if (oop_result->is_valid()) {
2560 get_vm_result(oop_result, java_thread);
2561 }
2562 }
2563
2564 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
2565
2566 // Calculate the value for last_Java_sp
2567 // somewhat subtle. call_VM does an intermediate call
2568 // which places a return address on the stack just under the
2569 // stack pointer as the user finsihed with it. This allows
2570 // use to retrieve last_Java_pc from last_Java_sp[-1].
2571 // On 32bit we then have to push additional args on the stack to accomplish
2572 // the actual requested call. On 64bit call_VM only can use register args
2573 // so the only extra space is the return address that call_VM created.
2574 // This hopefully explains the calculations here.
2575
2576 #ifdef _LP64
2577 // We've pushed one address, correct last_Java_sp
2578 lea(rax, Address(rsp, wordSize));
2579 #else
2580 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
2581 #endif // LP64
2582
2583 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
2584
2585 }
2586
2587 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
2588 call_VM_leaf_base(entry_point, number_of_arguments);
2589 }
2590
2591 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
2592 pass_arg0(this, arg_0);
2593 call_VM_leaf(entry_point, 1);
2594 }
2595
2596 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2597
2598 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2599 pass_arg1(this, arg_1);
2600 pass_arg0(this, arg_0);
2601 call_VM_leaf(entry_point, 2);
2602 }
2603
2604 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2605 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2606 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2607 pass_arg2(this, arg_2);
2608 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2609 pass_arg1(this, arg_1);
2610 pass_arg0(this, arg_0);
2611 call_VM_leaf(entry_point, 3);
2612 }
2613
2614 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
2615 pass_arg0(this, arg_0);
2616 MacroAssembler::call_VM_leaf_base(entry_point, 1);
2617 }
2618
2619 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2620
2621 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2622 pass_arg1(this, arg_1);
2623 pass_arg0(this, arg_0);
2624 MacroAssembler::call_VM_leaf_base(entry_point, 2);
2625 }
2626
2627 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2628 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2629 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2630 pass_arg2(this, arg_2);
2631 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2632 pass_arg1(this, arg_1);
2633 pass_arg0(this, arg_0);
2634 MacroAssembler::call_VM_leaf_base(entry_point, 3);
2635 }
2636
2637 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
2638 LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg"));
2639 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2640 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2641 pass_arg3(this, arg_3);
2642 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2643 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2644 pass_arg2(this, arg_2);
2645 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2646 pass_arg1(this, arg_1);
2647 pass_arg0(this, arg_0);
2648 MacroAssembler::call_VM_leaf_base(entry_point, 4);
2649 }
2650
2651 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
2652 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
2653 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
2654 verify_oop(oop_result, "broken oop in call_VM_base");
2655 }
2656
2657 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
2658 movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
2659 movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD);
2660 }
2661
2662 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
2663 }
2664
2665 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
2666 }
2667
2668 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) {
2669 if (reachable(src1)) {
2670 cmpl(as_Address(src1), imm);
2671 } else {
2672 lea(rscratch1, src1);
2673 cmpl(Address(rscratch1, 0), imm);
2674 }
2675 }
2676
2677 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) {
2678 assert(!src2.is_lval(), "use cmpptr");
2679 if (reachable(src2)) {
2680 cmpl(src1, as_Address(src2));
2681 } else {
2682 lea(rscratch1, src2);
2683 cmpl(src1, Address(rscratch1, 0));
2684 }
2685 }
2686
2687 void MacroAssembler::cmp32(Register src1, int32_t imm) {
2688 Assembler::cmpl(src1, imm);
2689 }
2690
2691 void MacroAssembler::cmp32(Register src1, Address src2) {
2692 Assembler::cmpl(src1, src2);
2693 }
2694
2695 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2696 ucomisd(opr1, opr2);
2697
2698 Label L;
2699 if (unordered_is_less) {
2700 movl(dst, -1);
2701 jcc(Assembler::parity, L);
2702 jcc(Assembler::below , L);
2703 movl(dst, 0);
2704 jcc(Assembler::equal , L);
2705 increment(dst);
2706 } else { // unordered is greater
2707 movl(dst, 1);
2708 jcc(Assembler::parity, L);
2709 jcc(Assembler::above , L);
2710 movl(dst, 0);
2711 jcc(Assembler::equal , L);
2712 decrementl(dst);
2713 }
2714 bind(L);
2715 }
2716
2717 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2718 ucomiss(opr1, opr2);
2719
2720 Label L;
2721 if (unordered_is_less) {
2722 movl(dst, -1);
2723 jcc(Assembler::parity, L);
2724 jcc(Assembler::below , L);
2725 movl(dst, 0);
2726 jcc(Assembler::equal , L);
2727 increment(dst);
2728 } else { // unordered is greater
2729 movl(dst, 1);
2730 jcc(Assembler::parity, L);
2731 jcc(Assembler::above , L);
2732 movl(dst, 0);
2733 jcc(Assembler::equal , L);
2734 decrementl(dst);
2735 }
2736 bind(L);
2737 }
2738
2739
2740 void MacroAssembler::cmp8(AddressLiteral src1, int imm) {
2741 if (reachable(src1)) {
2742 cmpb(as_Address(src1), imm);
2743 } else {
2744 lea(rscratch1, src1);
2745 cmpb(Address(rscratch1, 0), imm);
2746 }
2747 }
2748
2749 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) {
2750 #ifdef _LP64
2751 if (src2.is_lval()) {
2752 movptr(rscratch1, src2);
2753 Assembler::cmpq(src1, rscratch1);
2754 } else if (reachable(src2)) {
2755 cmpq(src1, as_Address(src2));
2756 } else {
2757 lea(rscratch1, src2);
2758 Assembler::cmpq(src1, Address(rscratch1, 0));
2759 }
2760 #else
2761 if (src2.is_lval()) {
2762 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2763 } else {
2764 cmpl(src1, as_Address(src2));
2765 }
2766 #endif // _LP64
2767 }
2768
2769 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) {
2770 assert(src2.is_lval(), "not a mem-mem compare");
2771 #ifdef _LP64
2772 // moves src2's literal address
2773 movptr(rscratch1, src2);
2774 Assembler::cmpq(src1, rscratch1);
2775 #else
2776 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2777 #endif // _LP64
2778 }
2779
2780 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) {
2781 if (reachable(adr)) {
2782 if (os::is_MP())
2783 lock();
2784 cmpxchgptr(reg, as_Address(adr));
2785 } else {
2786 lea(rscratch1, adr);
2787 if (os::is_MP())
2788 lock();
2789 cmpxchgptr(reg, Address(rscratch1, 0));
2790 }
2791 }
2792
2793 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
2794 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
2795 }
2796
2797 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) {
2798 if (reachable(src)) {
2799 Assembler::comisd(dst, as_Address(src));
2800 } else {
2801 lea(rscratch1, src);
2802 Assembler::comisd(dst, Address(rscratch1, 0));
2803 }
2804 }
2805
2806 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) {
2807 if (reachable(src)) {
2808 Assembler::comiss(dst, as_Address(src));
2809 } else {
2810 lea(rscratch1, src);
2811 Assembler::comiss(dst, Address(rscratch1, 0));
2812 }
2813 }
2814
2815
2816 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) {
2817 Condition negated_cond = negate_condition(cond);
2818 Label L;
2819 jcc(negated_cond, L);
2820 pushf(); // Preserve flags
2821 atomic_incl(counter_addr);
2822 popf();
2823 bind(L);
2824 }
2825
2826 int MacroAssembler::corrected_idivl(Register reg) {
2827 // Full implementation of Java idiv and irem; checks for
2828 // special case as described in JVM spec., p.243 & p.271.
2829 // The function returns the (pc) offset of the idivl
2830 // instruction - may be needed for implicit exceptions.
2831 //
2832 // normal case special case
2833 //
2834 // input : rax,: dividend min_int
2835 // reg: divisor (may not be rax,/rdx) -1
2836 //
2837 // output: rax,: quotient (= rax, idiv reg) min_int
2838 // rdx: remainder (= rax, irem reg) 0
2839 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
2840 const int min_int = 0x80000000;
2841 Label normal_case, special_case;
2842
2843 // check for special case
2844 cmpl(rax, min_int);
2845 jcc(Assembler::notEqual, normal_case);
2846 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
2847 cmpl(reg, -1);
2848 jcc(Assembler::equal, special_case);
2849
2850 // handle normal case
2851 bind(normal_case);
2852 cdql();
2853 int idivl_offset = offset();
2854 idivl(reg);
2855
2856 // normal and special case exit
2857 bind(special_case);
2858
2859 return idivl_offset;
2860 }
2861
2862
2863
2864 void MacroAssembler::decrementl(Register reg, int value) {
2865 if (value == min_jint) {subl(reg, value) ; return; }
2866 if (value < 0) { incrementl(reg, -value); return; }
2867 if (value == 0) { ; return; }
2868 if (value == 1 && UseIncDec) { decl(reg) ; return; }
2869 /* else */ { subl(reg, value) ; return; }
2870 }
2871
2872 void MacroAssembler::decrementl(Address dst, int value) {
2873 if (value == min_jint) {subl(dst, value) ; return; }
2874 if (value < 0) { incrementl(dst, -value); return; }
2875 if (value == 0) { ; return; }
2876 if (value == 1 && UseIncDec) { decl(dst) ; return; }
2877 /* else */ { subl(dst, value) ; return; }
2878 }
2879
2880 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
2881 assert (shift_value > 0, "illegal shift value");
2882 Label _is_positive;
2883 testl (reg, reg);
2884 jcc (Assembler::positive, _is_positive);
2885 int offset = (1 << shift_value) - 1 ;
2886
2887 if (offset == 1) {
2888 incrementl(reg);
2889 } else {
2890 addl(reg, offset);
2891 }
2892
2893 bind (_is_positive);
2894 sarl(reg, shift_value);
2895 }
2896
2897 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) {
2898 if (reachable(src)) {
2899 Assembler::divsd(dst, as_Address(src));
2900 } else {
2901 lea(rscratch1, src);
2902 Assembler::divsd(dst, Address(rscratch1, 0));
2903 }
2904 }
2905
2906 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) {
2907 if (reachable(src)) {
2908 Assembler::divss(dst, as_Address(src));
2909 } else {
2910 lea(rscratch1, src);
2911 Assembler::divss(dst, Address(rscratch1, 0));
2912 }
2913 }
2914
2915 // !defined(COMPILER2) is because of stupid core builds
2916 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2) || INCLUDE_JVMCI
2917 void MacroAssembler::empty_FPU_stack() {
2918 if (VM_Version::supports_mmx()) {
2919 emms();
2920 } else {
2921 for (int i = 8; i-- > 0; ) ffree(i);
2922 }
2923 }
2924 #endif // !LP64 || C1 || !C2 || INCLUDE_JVMCI
2925
2926
2927 // Defines obj, preserves var_size_in_bytes
2928 void MacroAssembler::eden_allocate(Register obj,
2929 Register var_size_in_bytes,
2930 int con_size_in_bytes,
2931 Register t1,
2932 Label& slow_case) {
2933 assert(obj == rax, "obj must be in rax, for cmpxchg");
2934 assert_different_registers(obj, var_size_in_bytes, t1);
2935 if (!Universe::heap()->supports_inline_contig_alloc()) {
2936 jmp(slow_case);
2937 } else {
2938 Register end = t1;
2939 Label retry;
2940 bind(retry);
2941 ExternalAddress heap_top((address) Universe::heap()->top_addr());
2942 movptr(obj, heap_top);
2943 if (var_size_in_bytes == noreg) {
2944 lea(end, Address(obj, con_size_in_bytes));
2945 } else {
2946 lea(end, Address(obj, var_size_in_bytes, Address::times_1));
2947 }
2948 // if end < obj then we wrapped around => object too long => slow case
2949 cmpptr(end, obj);
2950 jcc(Assembler::below, slow_case);
2951 cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr()));
2952 jcc(Assembler::above, slow_case);
2953 // Compare obj with the top addr, and if still equal, store the new top addr in
2954 // end at the address of the top addr pointer. Sets ZF if was equal, and clears
2955 // it otherwise. Use lock prefix for atomicity on MPs.
2956 locked_cmpxchgptr(end, heap_top);
2957 jcc(Assembler::notEqual, retry);
2958 }
2959 }
2960
2961 void MacroAssembler::enter() {
2962 push(rbp);
2963 mov(rbp, rsp);
2964 }
2965
2966 // A 5 byte nop that is safe for patching (see patch_verified_entry)
2967 void MacroAssembler::fat_nop() {
2968 if (UseAddressNop) {
2969 addr_nop_5();
2970 } else {
2971 emit_int8(0x26); // es:
2972 emit_int8(0x2e); // cs:
2973 emit_int8(0x64); // fs:
2974 emit_int8(0x65); // gs:
2975 emit_int8((unsigned char)0x90);
2976 }
2977 }
2978
2979 void MacroAssembler::fcmp(Register tmp) {
2980 fcmp(tmp, 1, true, true);
2981 }
2982
2983 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
2984 assert(!pop_right || pop_left, "usage error");
2985 if (VM_Version::supports_cmov()) {
2986 assert(tmp == noreg, "unneeded temp");
2987 if (pop_left) {
2988 fucomip(index);
2989 } else {
2990 fucomi(index);
2991 }
2992 if (pop_right) {
2993 fpop();
2994 }
2995 } else {
2996 assert(tmp != noreg, "need temp");
2997 if (pop_left) {
2998 if (pop_right) {
2999 fcompp();
3000 } else {
3001 fcomp(index);
3002 }
3003 } else {
3004 fcom(index);
3005 }
3006 // convert FPU condition into eflags condition via rax,
3007 save_rax(tmp);
3008 fwait(); fnstsw_ax();
3009 sahf();
3010 restore_rax(tmp);
3011 }
3012 // condition codes set as follows:
3013 //
3014 // CF (corresponds to C0) if x < y
3015 // PF (corresponds to C2) if unordered
3016 // ZF (corresponds to C3) if x = y
3017 }
3018
3019 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
3020 fcmp2int(dst, unordered_is_less, 1, true, true);
3021 }
3022
3023 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
3024 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
3025 Label L;
3026 if (unordered_is_less) {
3027 movl(dst, -1);
3028 jcc(Assembler::parity, L);
3029 jcc(Assembler::below , L);
3030 movl(dst, 0);
3031 jcc(Assembler::equal , L);
3032 increment(dst);
3033 } else { // unordered is greater
3034 movl(dst, 1);
3035 jcc(Assembler::parity, L);
3036 jcc(Assembler::above , L);
3037 movl(dst, 0);
3038 jcc(Assembler::equal , L);
3039 decrementl(dst);
3040 }
3041 bind(L);
3042 }
3043
3044 void MacroAssembler::fld_d(AddressLiteral src) {
3045 fld_d(as_Address(src));
3046 }
3047
3048 void MacroAssembler::fld_s(AddressLiteral src) {
3049 fld_s(as_Address(src));
3050 }
3051
3052 void MacroAssembler::fld_x(AddressLiteral src) {
3053 Assembler::fld_x(as_Address(src));
3054 }
3055
3056 void MacroAssembler::fldcw(AddressLiteral src) {
3057 Assembler::fldcw(as_Address(src));
3058 }
3059
3060 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src) {
3061 if (reachable(src)) {
3062 Assembler::mulpd(dst, as_Address(src));
3063 } else {
3064 lea(rscratch1, src);
3065 Assembler::mulpd(dst, Address(rscratch1, 0));
3066 }
3067 }
3068
3069 void MacroAssembler::increase_precision() {
3070 subptr(rsp, BytesPerWord);
3071 fnstcw(Address(rsp, 0));
3072 movl(rax, Address(rsp, 0));
3073 orl(rax, 0x300);
3074 push(rax);
3075 fldcw(Address(rsp, 0));
3076 pop(rax);
3077 }
3078
3079 void MacroAssembler::restore_precision() {
3080 fldcw(Address(rsp, 0));
3081 addptr(rsp, BytesPerWord);
3082 }
3083
3084 void MacroAssembler::fpop() {
3085 ffree();
3086 fincstp();
3087 }
3088
3089 void MacroAssembler::load_float(Address src) {
3090 if (UseSSE >= 1) {
3091 movflt(xmm0, src);
3092 } else {
3093 LP64_ONLY(ShouldNotReachHere());
3094 NOT_LP64(fld_s(src));
3095 }
3096 }
3097
3098 void MacroAssembler::store_float(Address dst) {
3099 if (UseSSE >= 1) {
3100 movflt(dst, xmm0);
3101 } else {
3102 LP64_ONLY(ShouldNotReachHere());
3103 NOT_LP64(fstp_s(dst));
3104 }
3105 }
3106
3107 void MacroAssembler::load_double(Address src) {
3108 if (UseSSE >= 2) {
3109 movdbl(xmm0, src);
3110 } else {
3111 LP64_ONLY(ShouldNotReachHere());
3112 NOT_LP64(fld_d(src));
3113 }
3114 }
3115
3116 void MacroAssembler::store_double(Address dst) {
3117 if (UseSSE >= 2) {
3118 movdbl(dst, xmm0);
3119 } else {
3120 LP64_ONLY(ShouldNotReachHere());
3121 NOT_LP64(fstp_d(dst));
3122 }
3123 }
3124
3125 void MacroAssembler::fremr(Register tmp) {
3126 save_rax(tmp);
3127 { Label L;
3128 bind(L);
3129 fprem();
3130 fwait(); fnstsw_ax();
3131 #ifdef _LP64
3132 testl(rax, 0x400);
3133 jcc(Assembler::notEqual, L);
3134 #else
3135 sahf();
3136 jcc(Assembler::parity, L);
3137 #endif // _LP64
3138 }
3139 restore_rax(tmp);
3140 // Result is in ST0.
3141 // Note: fxch & fpop to get rid of ST1
3142 // (otherwise FPU stack could overflow eventually)
3143 fxch(1);
3144 fpop();
3145 }
3146
3147
3148 void MacroAssembler::incrementl(AddressLiteral dst) {
3149 if (reachable(dst)) {
3150 incrementl(as_Address(dst));
3151 } else {
3152 lea(rscratch1, dst);
3153 incrementl(Address(rscratch1, 0));
3154 }
3155 }
3156
3157 void MacroAssembler::incrementl(ArrayAddress dst) {
3158 incrementl(as_Address(dst));
3159 }
3160
3161 void MacroAssembler::incrementl(Register reg, int value) {
3162 if (value == min_jint) {addl(reg, value) ; return; }
3163 if (value < 0) { decrementl(reg, -value); return; }
3164 if (value == 0) { ; return; }
3165 if (value == 1 && UseIncDec) { incl(reg) ; return; }
3166 /* else */ { addl(reg, value) ; return; }
3167 }
3168
3169 void MacroAssembler::incrementl(Address dst, int value) {
3170 if (value == min_jint) {addl(dst, value) ; return; }
3171 if (value < 0) { decrementl(dst, -value); return; }
3172 if (value == 0) { ; return; }
3173 if (value == 1 && UseIncDec) { incl(dst) ; return; }
3174 /* else */ { addl(dst, value) ; return; }
3175 }
3176
3177 void MacroAssembler::jump(AddressLiteral dst) {
3178 if (reachable(dst)) {
3179 jmp_literal(dst.target(), dst.rspec());
3180 } else {
3181 lea(rscratch1, dst);
3182 jmp(rscratch1);
3183 }
3184 }
3185
3186 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) {
3187 if (reachable(dst)) {
3188 InstructionMark im(this);
3189 relocate(dst.reloc());
3190 const int short_size = 2;
3191 const int long_size = 6;
3192 int offs = (intptr_t)dst.target() - ((intptr_t)pc());
3193 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
3194 // 0111 tttn #8-bit disp
3195 emit_int8(0x70 | cc);
3196 emit_int8((offs - short_size) & 0xFF);
3197 } else {
3198 // 0000 1111 1000 tttn #32-bit disp
3199 emit_int8(0x0F);
3200 emit_int8((unsigned char)(0x80 | cc));
3201 emit_int32(offs - long_size);
3202 }
3203 } else {
3204 #ifdef ASSERT
3205 warning("reversing conditional branch");
3206 #endif /* ASSERT */
3207 Label skip;
3208 jccb(reverse[cc], skip);
3209 lea(rscratch1, dst);
3210 Assembler::jmp(rscratch1);
3211 bind(skip);
3212 }
3213 }
3214
3215 void MacroAssembler::ldmxcsr(AddressLiteral src) {
3216 if (reachable(src)) {
3217 Assembler::ldmxcsr(as_Address(src));
3218 } else {
3219 lea(rscratch1, src);
3220 Assembler::ldmxcsr(Address(rscratch1, 0));
3221 }
3222 }
3223
3224 int MacroAssembler::load_signed_byte(Register dst, Address src) {
3225 int off;
3226 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3227 off = offset();
3228 movsbl(dst, src); // movsxb
3229 } else {
3230 off = load_unsigned_byte(dst, src);
3231 shll(dst, 24);
3232 sarl(dst, 24);
3233 }
3234 return off;
3235 }
3236
3237 // Note: load_signed_short used to be called load_signed_word.
3238 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
3239 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
3240 // The term "word" in HotSpot means a 32- or 64-bit machine word.
3241 int MacroAssembler::load_signed_short(Register dst, Address src) {
3242 int off;
3243 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3244 // This is dubious to me since it seems safe to do a signed 16 => 64 bit
3245 // version but this is what 64bit has always done. This seems to imply
3246 // that users are only using 32bits worth.
3247 off = offset();
3248 movswl(dst, src); // movsxw
3249 } else {
3250 off = load_unsigned_short(dst, src);
3251 shll(dst, 16);
3252 sarl(dst, 16);
3253 }
3254 return off;
3255 }
3256
3257 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
3258 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3259 // and "3.9 Partial Register Penalties", p. 22).
3260 int off;
3261 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
3262 off = offset();
3263 movzbl(dst, src); // movzxb
3264 } else {
3265 xorl(dst, dst);
3266 off = offset();
3267 movb(dst, src);
3268 }
3269 return off;
3270 }
3271
3272 // Note: load_unsigned_short used to be called load_unsigned_word.
3273 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
3274 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3275 // and "3.9 Partial Register Penalties", p. 22).
3276 int off;
3277 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
3278 off = offset();
3279 movzwl(dst, src); // movzxw
3280 } else {
3281 xorl(dst, dst);
3282 off = offset();
3283 movw(dst, src);
3284 }
3285 return off;
3286 }
3287
3288 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
3289 switch (size_in_bytes) {
3290 #ifndef _LP64
3291 case 8:
3292 assert(dst2 != noreg, "second dest register required");
3293 movl(dst, src);
3294 movl(dst2, src.plus_disp(BytesPerInt));
3295 break;
3296 #else
3297 case 8: movq(dst, src); break;
3298 #endif
3299 case 4: movl(dst, src); break;
3300 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
3301 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
3302 default: ShouldNotReachHere();
3303 }
3304 }
3305
3306 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
3307 switch (size_in_bytes) {
3308 #ifndef _LP64
3309 case 8:
3310 assert(src2 != noreg, "second source register required");
3311 movl(dst, src);
3312 movl(dst.plus_disp(BytesPerInt), src2);
3313 break;
3314 #else
3315 case 8: movq(dst, src); break;
3316 #endif
3317 case 4: movl(dst, src); break;
3318 case 2: movw(dst, src); break;
3319 case 1: movb(dst, src); break;
3320 default: ShouldNotReachHere();
3321 }
3322 }
3323
3324 void MacroAssembler::mov32(AddressLiteral dst, Register src) {
3325 if (reachable(dst)) {
3326 movl(as_Address(dst), src);
3327 } else {
3328 lea(rscratch1, dst);
3329 movl(Address(rscratch1, 0), src);
3330 }
3331 }
3332
3333 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
3334 if (reachable(src)) {
3335 movl(dst, as_Address(src));
3336 } else {
3337 lea(rscratch1, src);
3338 movl(dst, Address(rscratch1, 0));
3339 }
3340 }
3341
3342 // C++ bool manipulation
3343
3344 void MacroAssembler::movbool(Register dst, Address src) {
3345 if(sizeof(bool) == 1)
3346 movb(dst, src);
3347 else if(sizeof(bool) == 2)
3348 movw(dst, src);
3349 else if(sizeof(bool) == 4)
3350 movl(dst, src);
3351 else
3352 // unsupported
3353 ShouldNotReachHere();
3354 }
3355
3356 void MacroAssembler::movbool(Address dst, bool boolconst) {
3357 if(sizeof(bool) == 1)
3358 movb(dst, (int) boolconst);
3359 else if(sizeof(bool) == 2)
3360 movw(dst, (int) boolconst);
3361 else if(sizeof(bool) == 4)
3362 movl(dst, (int) boolconst);
3363 else
3364 // unsupported
3365 ShouldNotReachHere();
3366 }
3367
3368 void MacroAssembler::movbool(Address dst, Register src) {
3369 if(sizeof(bool) == 1)
3370 movb(dst, src);
3371 else if(sizeof(bool) == 2)
3372 movw(dst, src);
3373 else if(sizeof(bool) == 4)
3374 movl(dst, src);
3375 else
3376 // unsupported
3377 ShouldNotReachHere();
3378 }
3379
3380 void MacroAssembler::movbyte(ArrayAddress dst, int src) {
3381 movb(as_Address(dst), src);
3382 }
3383
3384 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src) {
3385 if (reachable(src)) {
3386 movdl(dst, as_Address(src));
3387 } else {
3388 lea(rscratch1, src);
3389 movdl(dst, Address(rscratch1, 0));
3390 }
3391 }
3392
3393 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src) {
3394 if (reachable(src)) {
3395 movq(dst, as_Address(src));
3396 } else {
3397 lea(rscratch1, src);
3398 movq(dst, Address(rscratch1, 0));
3399 }
3400 }
3401
3402 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) {
3403 if (reachable(src)) {
3404 if (UseXmmLoadAndClearUpper) {
3405 movsd (dst, as_Address(src));
3406 } else {
3407 movlpd(dst, as_Address(src));
3408 }
3409 } else {
3410 lea(rscratch1, src);
3411 if (UseXmmLoadAndClearUpper) {
3412 movsd (dst, Address(rscratch1, 0));
3413 } else {
3414 movlpd(dst, Address(rscratch1, 0));
3415 }
3416 }
3417 }
3418
3419 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) {
3420 if (reachable(src)) {
3421 movss(dst, as_Address(src));
3422 } else {
3423 lea(rscratch1, src);
3424 movss(dst, Address(rscratch1, 0));
3425 }
3426 }
3427
3428 void MacroAssembler::movptr(Register dst, Register src) {
3429 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3430 }
3431
3432 void MacroAssembler::movptr(Register dst, Address src) {
3433 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3434 }
3435
3436 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
3437 void MacroAssembler::movptr(Register dst, intptr_t src) {
3438 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src));
3439 }
3440
3441 void MacroAssembler::movptr(Address dst, Register src) {
3442 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3443 }
3444
3445 void MacroAssembler::movdqu(Address dst, XMMRegister src) {
3446 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (src->encoding() > 15)) {
3447 Assembler::vextractf32x4(dst, src, 0);
3448 } else {
3449 Assembler::movdqu(dst, src);
3450 }
3451 }
3452
3453 void MacroAssembler::movdqu(XMMRegister dst, Address src) {
3454 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (dst->encoding() > 15)) {
3455 Assembler::vinsertf32x4(dst, dst, src, 0);
3456 } else {
3457 Assembler::movdqu(dst, src);
3458 }
3459 }
3460
3461 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) {
3462 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3463 Assembler::evmovdqul(dst, src, Assembler::AVX_512bit);
3464 } else {
3465 Assembler::movdqu(dst, src);
3466 }
3467 }
3468
3469 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src) {
3470 if (reachable(src)) {
3471 movdqu(dst, as_Address(src));
3472 } else {
3473 lea(rscratch1, src);
3474 movdqu(dst, Address(rscratch1, 0));
3475 }
3476 }
3477
3478 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) {
3479 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (src->encoding() > 15)) {
3480 vextractf64x4_low(dst, src);
3481 } else {
3482 Assembler::vmovdqu(dst, src);
3483 }
3484 }
3485
3486 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) {
3487 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (dst->encoding() > 15)) {
3488 vinsertf64x4_low(dst, src);
3489 } else {
3490 Assembler::vmovdqu(dst, src);
3491 }
3492 }
3493
3494 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) {
3495 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3496 Assembler::evmovdqul(dst, src, Assembler::AVX_512bit);
3497 }
3498 else {
3499 Assembler::vmovdqu(dst, src);
3500 }
3501 }
3502
3503 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src) {
3504 if (reachable(src)) {
3505 vmovdqu(dst, as_Address(src));
3506 }
3507 else {
3508 lea(rscratch1, src);
3509 vmovdqu(dst, Address(rscratch1, 0));
3510 }
3511 }
3512
3513 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src) {
3514 if (reachable(src)) {
3515 Assembler::movdqa(dst, as_Address(src));
3516 } else {
3517 lea(rscratch1, src);
3518 Assembler::movdqa(dst, Address(rscratch1, 0));
3519 }
3520 }
3521
3522 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) {
3523 if (reachable(src)) {
3524 Assembler::movsd(dst, as_Address(src));
3525 } else {
3526 lea(rscratch1, src);
3527 Assembler::movsd(dst, Address(rscratch1, 0));
3528 }
3529 }
3530
3531 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) {
3532 if (reachable(src)) {
3533 Assembler::movss(dst, as_Address(src));
3534 } else {
3535 lea(rscratch1, src);
3536 Assembler::movss(dst, Address(rscratch1, 0));
3537 }
3538 }
3539
3540 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) {
3541 if (reachable(src)) {
3542 Assembler::mulsd(dst, as_Address(src));
3543 } else {
3544 lea(rscratch1, src);
3545 Assembler::mulsd(dst, Address(rscratch1, 0));
3546 }
3547 }
3548
3549 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) {
3550 if (reachable(src)) {
3551 Assembler::mulss(dst, as_Address(src));
3552 } else {
3553 lea(rscratch1, src);
3554 Assembler::mulss(dst, Address(rscratch1, 0));
3555 }
3556 }
3557
3558 void MacroAssembler::null_check(Register reg, int offset) {
3559 if (needs_explicit_null_check(offset)) {
3560 // provoke OS NULL exception if reg = NULL by
3561 // accessing M[reg] w/o changing any (non-CC) registers
3562 // NOTE: cmpl is plenty here to provoke a segv
3563 cmpptr(rax, Address(reg, 0));
3564 // Note: should probably use testl(rax, Address(reg, 0));
3565 // may be shorter code (however, this version of
3566 // testl needs to be implemented first)
3567 } else {
3568 // nothing to do, (later) access of M[reg + offset]
3569 // will provoke OS NULL exception if reg = NULL
3570 }
3571 }
3572
3573 void MacroAssembler::os_breakpoint() {
3574 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
3575 // (e.g., MSVC can't call ps() otherwise)
3576 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
3577 }
3578
3579 #ifdef _LP64
3580 #define XSTATE_BV 0x200
3581 #endif
3582
3583 void MacroAssembler::pop_CPU_state() {
3584 pop_FPU_state();
3585 pop_IU_state();
3586 }
3587
3588 void MacroAssembler::pop_FPU_state() {
3589 #ifndef _LP64
3590 frstor(Address(rsp, 0));
3591 #else
3592 fxrstor(Address(rsp, 0));
3593 #endif
3594 addptr(rsp, FPUStateSizeInWords * wordSize);
3595 }
3596
3597 void MacroAssembler::pop_IU_state() {
3598 popa();
3599 LP64_ONLY(addq(rsp, 8));
3600 popf();
3601 }
3602
3603 // Save Integer and Float state
3604 // Warning: Stack must be 16 byte aligned (64bit)
3605 void MacroAssembler::push_CPU_state() {
3606 push_IU_state();
3607 push_FPU_state();
3608 }
3609
3610 void MacroAssembler::push_FPU_state() {
3611 subptr(rsp, FPUStateSizeInWords * wordSize);
3612 #ifndef _LP64
3613 fnsave(Address(rsp, 0));
3614 fwait();
3615 #else
3616 fxsave(Address(rsp, 0));
3617 #endif // LP64
3618 }
3619
3620 void MacroAssembler::push_IU_state() {
3621 // Push flags first because pusha kills them
3622 pushf();
3623 // Make sure rsp stays 16-byte aligned
3624 LP64_ONLY(subq(rsp, 8));
3625 pusha();
3626 }
3627
3628 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp, bool clear_pc) {
3629 // determine java_thread register
3630 if (!java_thread->is_valid()) {
3631 java_thread = rdi;
3632 get_thread(java_thread);
3633 }
3634 // we must set sp to zero to clear frame
3635 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
3636 if (clear_fp) {
3637 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
3638 }
3639
3640 if (clear_pc)
3641 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
3642
3643 }
3644
3645 void MacroAssembler::restore_rax(Register tmp) {
3646 if (tmp == noreg) pop(rax);
3647 else if (tmp != rax) mov(rax, tmp);
3648 }
3649
3650 void MacroAssembler::round_to(Register reg, int modulus) {
3651 addptr(reg, modulus - 1);
3652 andptr(reg, -modulus);
3653 }
3654
3655 void MacroAssembler::save_rax(Register tmp) {
3656 if (tmp == noreg) push(rax);
3657 else if (tmp != rax) mov(tmp, rax);
3658 }
3659
3660 // Write serialization page so VM thread can do a pseudo remote membar.
3661 // We use the current thread pointer to calculate a thread specific
3662 // offset to write to within the page. This minimizes bus traffic
3663 // due to cache line collision.
3664 void MacroAssembler::serialize_memory(Register thread, Register tmp) {
3665 movl(tmp, thread);
3666 shrl(tmp, os::get_serialize_page_shift_count());
3667 andl(tmp, (os::vm_page_size() - sizeof(int)));
3668
3669 Address index(noreg, tmp, Address::times_1);
3670 ExternalAddress page(os::get_memory_serialize_page());
3671
3672 // Size of store must match masking code above
3673 movl(as_Address(ArrayAddress(page, index)), tmp);
3674 }
3675
3676 // Calls to C land
3677 //
3678 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
3679 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
3680 // has to be reset to 0. This is required to allow proper stack traversal.
3681 void MacroAssembler::set_last_Java_frame(Register java_thread,
3682 Register last_java_sp,
3683 Register last_java_fp,
3684 address last_java_pc) {
3685 // determine java_thread register
3686 if (!java_thread->is_valid()) {
3687 java_thread = rdi;
3688 get_thread(java_thread);
3689 }
3690 // determine last_java_sp register
3691 if (!last_java_sp->is_valid()) {
3692 last_java_sp = rsp;
3693 }
3694
3695 // last_java_fp is optional
3696
3697 if (last_java_fp->is_valid()) {
3698 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
3699 }
3700
3701 // last_java_pc is optional
3702
3703 if (last_java_pc != NULL) {
3704 lea(Address(java_thread,
3705 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()),
3706 InternalAddress(last_java_pc));
3707
3708 }
3709 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
3710 }
3711
3712 void MacroAssembler::shlptr(Register dst, int imm8) {
3713 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
3714 }
3715
3716 void MacroAssembler::shrptr(Register dst, int imm8) {
3717 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
3718 }
3719
3720 void MacroAssembler::sign_extend_byte(Register reg) {
3721 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
3722 movsbl(reg, reg); // movsxb
3723 } else {
3724 shll(reg, 24);
3725 sarl(reg, 24);
3726 }
3727 }
3728
3729 void MacroAssembler::sign_extend_short(Register reg) {
3730 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3731 movswl(reg, reg); // movsxw
3732 } else {
3733 shll(reg, 16);
3734 sarl(reg, 16);
3735 }
3736 }
3737
3738 void MacroAssembler::testl(Register dst, AddressLiteral src) {
3739 assert(reachable(src), "Address should be reachable");
3740 testl(dst, as_Address(src));
3741 }
3742
3743 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
3744 int dst_enc = dst->encoding();
3745 int src_enc = src->encoding();
3746 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
3747 Assembler::pcmpeqb(dst, src);
3748 } else if ((dst_enc < 16) && (src_enc < 16)) {
3749 Assembler::pcmpeqb(dst, src);
3750 } else if (src_enc < 16) {
3751 subptr(rsp, 64);
3752 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3753 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3754 Assembler::pcmpeqb(xmm0, src);
3755 movdqu(dst, xmm0);
3756 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3757 addptr(rsp, 64);
3758 } else if (dst_enc < 16) {
3759 subptr(rsp, 64);
3760 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3761 evmovdqul(xmm0, src, Assembler::AVX_512bit);
3762 Assembler::pcmpeqb(dst, xmm0);
3763 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3764 addptr(rsp, 64);
3765 } else {
3766 subptr(rsp, 64);
3767 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3768 subptr(rsp, 64);
3769 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
3770 movdqu(xmm0, src);
3771 movdqu(xmm1, dst);
3772 Assembler::pcmpeqb(xmm1, xmm0);
3773 movdqu(dst, xmm1);
3774 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
3775 addptr(rsp, 64);
3776 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3777 addptr(rsp, 64);
3778 }
3779 }
3780
3781 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3782 int dst_enc = dst->encoding();
3783 int src_enc = src->encoding();
3784 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
3785 Assembler::pcmpeqw(dst, src);
3786 } else if ((dst_enc < 16) && (src_enc < 16)) {
3787 Assembler::pcmpeqw(dst, src);
3788 } else if (src_enc < 16) {
3789 subptr(rsp, 64);
3790 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3791 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3792 Assembler::pcmpeqw(xmm0, src);
3793 movdqu(dst, xmm0);
3794 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3795 addptr(rsp, 64);
3796 } else if (dst_enc < 16) {
3797 subptr(rsp, 64);
3798 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3799 evmovdqul(xmm0, src, Assembler::AVX_512bit);
3800 Assembler::pcmpeqw(dst, xmm0);
3801 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3802 addptr(rsp, 64);
3803 } else {
3804 subptr(rsp, 64);
3805 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3806 subptr(rsp, 64);
3807 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
3808 movdqu(xmm0, src);
3809 movdqu(xmm1, dst);
3810 Assembler::pcmpeqw(xmm1, xmm0);
3811 movdqu(dst, xmm1);
3812 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
3813 addptr(rsp, 64);
3814 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3815 addptr(rsp, 64);
3816 }
3817 }
3818
3819 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3820 int dst_enc = dst->encoding();
3821 if (dst_enc < 16) {
3822 Assembler::pcmpestri(dst, src, imm8);
3823 } else {
3824 subptr(rsp, 64);
3825 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3826 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3827 Assembler::pcmpestri(xmm0, src, imm8);
3828 movdqu(dst, xmm0);
3829 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3830 addptr(rsp, 64);
3831 }
3832 }
3833
3834 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3835 int dst_enc = dst->encoding();
3836 int src_enc = src->encoding();
3837 if ((dst_enc < 16) && (src_enc < 16)) {
3838 Assembler::pcmpestri(dst, src, imm8);
3839 } else if (src_enc < 16) {
3840 subptr(rsp, 64);
3841 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3842 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3843 Assembler::pcmpestri(xmm0, src, imm8);
3844 movdqu(dst, xmm0);
3845 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3846 addptr(rsp, 64);
3847 } else if (dst_enc < 16) {
3848 subptr(rsp, 64);
3849 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3850 evmovdqul(xmm0, src, Assembler::AVX_512bit);
3851 Assembler::pcmpestri(dst, xmm0, imm8);
3852 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3853 addptr(rsp, 64);
3854 } else {
3855 subptr(rsp, 64);
3856 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3857 subptr(rsp, 64);
3858 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
3859 movdqu(xmm0, src);
3860 movdqu(xmm1, dst);
3861 Assembler::pcmpestri(xmm1, xmm0, imm8);
3862 movdqu(dst, xmm1);
3863 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
3864 addptr(rsp, 64);
3865 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3866 addptr(rsp, 64);
3867 }
3868 }
3869
3870 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3871 int dst_enc = dst->encoding();
3872 int src_enc = src->encoding();
3873 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
3874 Assembler::pmovzxbw(dst, src);
3875 } else if ((dst_enc < 16) && (src_enc < 16)) {
3876 Assembler::pmovzxbw(dst, src);
3877 } else if (src_enc < 16) {
3878 subptr(rsp, 64);
3879 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3880 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3881 Assembler::pmovzxbw(xmm0, src);
3882 movdqu(dst, xmm0);
3883 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3884 addptr(rsp, 64);
3885 } else if (dst_enc < 16) {
3886 subptr(rsp, 64);
3887 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3888 evmovdqul(xmm0, src, Assembler::AVX_512bit);
3889 Assembler::pmovzxbw(dst, xmm0);
3890 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3891 addptr(rsp, 64);
3892 } else {
3893 subptr(rsp, 64);
3894 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3895 subptr(rsp, 64);
3896 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
3897 movdqu(xmm0, src);
3898 movdqu(xmm1, dst);
3899 Assembler::pmovzxbw(xmm1, xmm0);
3900 movdqu(dst, xmm1);
3901 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
3902 addptr(rsp, 64);
3903 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3904 addptr(rsp, 64);
3905 }
3906 }
3907
3908 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) {
3909 int dst_enc = dst->encoding();
3910 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
3911 Assembler::pmovzxbw(dst, src);
3912 } else if (dst_enc < 16) {
3913 Assembler::pmovzxbw(dst, src);
3914 } else {
3915 subptr(rsp, 64);
3916 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3917 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3918 Assembler::pmovzxbw(xmm0, src);
3919 movdqu(dst, xmm0);
3920 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3921 addptr(rsp, 64);
3922 }
3923 }
3924
3925 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) {
3926 int src_enc = src->encoding();
3927 if (src_enc < 16) {
3928 Assembler::pmovmskb(dst, src);
3929 } else {
3930 subptr(rsp, 64);
3931 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3932 evmovdqul(xmm0, src, Assembler::AVX_512bit);
3933 Assembler::pmovmskb(dst, xmm0);
3934 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3935 addptr(rsp, 64);
3936 }
3937 }
3938
3939 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) {
3940 int dst_enc = dst->encoding();
3941 int src_enc = src->encoding();
3942 if ((dst_enc < 16) && (src_enc < 16)) {
3943 Assembler::ptest(dst, src);
3944 } else if (src_enc < 16) {
3945 subptr(rsp, 64);
3946 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3947 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3948 Assembler::ptest(xmm0, src);
3949 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3950 addptr(rsp, 64);
3951 } else if (dst_enc < 16) {
3952 subptr(rsp, 64);
3953 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3954 evmovdqul(xmm0, src, Assembler::AVX_512bit);
3955 Assembler::ptest(dst, xmm0);
3956 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3957 addptr(rsp, 64);
3958 } else {
3959 subptr(rsp, 64);
3960 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3961 subptr(rsp, 64);
3962 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
3963 movdqu(xmm0, src);
3964 movdqu(xmm1, dst);
3965 Assembler::ptest(xmm1, xmm0);
3966 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
3967 addptr(rsp, 64);
3968 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3969 addptr(rsp, 64);
3970 }
3971 }
3972
3973 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) {
3974 if (reachable(src)) {
3975 Assembler::sqrtsd(dst, as_Address(src));
3976 } else {
3977 lea(rscratch1, src);
3978 Assembler::sqrtsd(dst, Address(rscratch1, 0));
3979 }
3980 }
3981
3982 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) {
3983 if (reachable(src)) {
3984 Assembler::sqrtss(dst, as_Address(src));
3985 } else {
3986 lea(rscratch1, src);
3987 Assembler::sqrtss(dst, Address(rscratch1, 0));
3988 }
3989 }
3990
3991 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) {
3992 if (reachable(src)) {
3993 Assembler::subsd(dst, as_Address(src));
3994 } else {
3995 lea(rscratch1, src);
3996 Assembler::subsd(dst, Address(rscratch1, 0));
3997 }
3998 }
3999
4000 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) {
4001 if (reachable(src)) {
4002 Assembler::subss(dst, as_Address(src));
4003 } else {
4004 lea(rscratch1, src);
4005 Assembler::subss(dst, Address(rscratch1, 0));
4006 }
4007 }
4008
4009 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) {
4010 if (reachable(src)) {
4011 Assembler::ucomisd(dst, as_Address(src));
4012 } else {
4013 lea(rscratch1, src);
4014 Assembler::ucomisd(dst, Address(rscratch1, 0));
4015 }
4016 }
4017
4018 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) {
4019 if (reachable(src)) {
4020 Assembler::ucomiss(dst, as_Address(src));
4021 } else {
4022 lea(rscratch1, src);
4023 Assembler::ucomiss(dst, Address(rscratch1, 0));
4024 }
4025 }
4026
4027 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) {
4028 // Used in sign-bit flipping with aligned address.
4029 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
4030 if (reachable(src)) {
4031 Assembler::xorpd(dst, as_Address(src));
4032 } else {
4033 lea(rscratch1, src);
4034 Assembler::xorpd(dst, Address(rscratch1, 0));
4035 }
4036 }
4037
4038 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) {
4039 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
4040 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
4041 }
4042 else {
4043 Assembler::xorpd(dst, src);
4044 }
4045 }
4046
4047 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) {
4048 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
4049 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
4050 } else {
4051 Assembler::xorps(dst, src);
4052 }
4053 }
4054
4055 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) {
4056 // Used in sign-bit flipping with aligned address.
4057 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
4058 if (reachable(src)) {
4059 Assembler::xorps(dst, as_Address(src));
4060 } else {
4061 lea(rscratch1, src);
4062 Assembler::xorps(dst, Address(rscratch1, 0));
4063 }
4064 }
4065
4066 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src) {
4067 // Used in sign-bit flipping with aligned address.
4068 bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
4069 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
4070 if (reachable(src)) {
4071 Assembler::pshufb(dst, as_Address(src));
4072 } else {
4073 lea(rscratch1, src);
4074 Assembler::pshufb(dst, Address(rscratch1, 0));
4075 }
4076 }
4077
4078 // AVX 3-operands instructions
4079
4080 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4081 if (reachable(src)) {
4082 vaddsd(dst, nds, as_Address(src));
4083 } else {
4084 lea(rscratch1, src);
4085 vaddsd(dst, nds, Address(rscratch1, 0));
4086 }
4087 }
4088
4089 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4090 if (reachable(src)) {
4091 vaddss(dst, nds, as_Address(src));
4092 } else {
4093 lea(rscratch1, src);
4094 vaddss(dst, nds, Address(rscratch1, 0));
4095 }
4096 }
4097
4098 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) {
4099 int dst_enc = dst->encoding();
4100 int nds_enc = nds->encoding();
4101 int src_enc = src->encoding();
4102 if ((dst_enc < 16) && (nds_enc < 16)) {
4103 vandps(dst, nds, negate_field, vector_len);
4104 } else if ((src_enc < 16) && (dst_enc < 16)) {
4105 movss(src, nds);
4106 vandps(dst, src, negate_field, vector_len);
4107 } else if (src_enc < 16) {
4108 movss(src, nds);
4109 vandps(src, src, negate_field, vector_len);
4110 movss(dst, src);
4111 } else if (dst_enc < 16) {
4112 movdqu(src, xmm0);
4113 movss(xmm0, nds);
4114 vandps(dst, xmm0, negate_field, vector_len);
4115 movdqu(xmm0, src);
4116 } else if (nds_enc < 16) {
4117 movdqu(src, xmm0);
4118 vandps(xmm0, nds, negate_field, vector_len);
4119 movss(dst, xmm0);
4120 movdqu(xmm0, src);
4121 } else {
4122 movdqu(src, xmm0);
4123 movss(xmm0, nds);
4124 vandps(xmm0, xmm0, negate_field, vector_len);
4125 movss(dst, xmm0);
4126 movdqu(xmm0, src);
4127 }
4128 }
4129
4130 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) {
4131 int dst_enc = dst->encoding();
4132 int nds_enc = nds->encoding();
4133 int src_enc = src->encoding();
4134 if ((dst_enc < 16) && (nds_enc < 16)) {
4135 vandpd(dst, nds, negate_field, vector_len);
4136 } else if ((src_enc < 16) && (dst_enc < 16)) {
4137 movsd(src, nds);
4138 vandpd(dst, src, negate_field, vector_len);
4139 } else if (src_enc < 16) {
4140 movsd(src, nds);
4141 vandpd(src, src, negate_field, vector_len);
4142 movsd(dst, src);
4143 } else if (dst_enc < 16) {
4144 movdqu(src, xmm0);
4145 movsd(xmm0, nds);
4146 vandpd(dst, xmm0, negate_field, vector_len);
4147 movdqu(xmm0, src);
4148 } else if (nds_enc < 16) {
4149 movdqu(src, xmm0);
4150 vandpd(xmm0, nds, negate_field, vector_len);
4151 movsd(dst, xmm0);
4152 movdqu(xmm0, src);
4153 } else {
4154 movdqu(src, xmm0);
4155 movsd(xmm0, nds);
4156 vandpd(xmm0, xmm0, negate_field, vector_len);
4157 movsd(dst, xmm0);
4158 movdqu(xmm0, src);
4159 }
4160 }
4161
4162 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4163 int dst_enc = dst->encoding();
4164 int nds_enc = nds->encoding();
4165 int src_enc = src->encoding();
4166 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4167 Assembler::vpaddb(dst, nds, src, vector_len);
4168 } else if ((dst_enc < 16) && (src_enc < 16)) {
4169 Assembler::vpaddb(dst, dst, src, vector_len);
4170 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4171 // use nds as scratch for src
4172 evmovdqul(nds, src, Assembler::AVX_512bit);
4173 Assembler::vpaddb(dst, dst, nds, vector_len);
4174 } else if ((src_enc < 16) && (nds_enc < 16)) {
4175 // use nds as scratch for dst
4176 evmovdqul(nds, dst, Assembler::AVX_512bit);
4177 Assembler::vpaddb(nds, nds, src, vector_len);
4178 evmovdqul(dst, nds, Assembler::AVX_512bit);
4179 } else if (dst_enc < 16) {
4180 // use nds as scatch for xmm0 to hold src
4181 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4182 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4183 Assembler::vpaddb(dst, dst, xmm0, vector_len);
4184 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4185 } else {
4186 // worse case scenario, all regs are in the upper bank
4187 subptr(rsp, 64);
4188 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4189 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4190 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4191 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4192 Assembler::vpaddb(xmm0, xmm0, xmm1, vector_len);
4193 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4194 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4195 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4196 addptr(rsp, 64);
4197 }
4198 }
4199
4200 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4201 int dst_enc = dst->encoding();
4202 int nds_enc = nds->encoding();
4203 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4204 Assembler::vpaddb(dst, nds, src, vector_len);
4205 } else if (dst_enc < 16) {
4206 Assembler::vpaddb(dst, dst, src, vector_len);
4207 } else if (nds_enc < 16) {
4208 // implies dst_enc in upper bank with src as scratch
4209 evmovdqul(nds, dst, Assembler::AVX_512bit);
4210 Assembler::vpaddb(nds, nds, src, vector_len);
4211 evmovdqul(dst, nds, Assembler::AVX_512bit);
4212 } else {
4213 // worse case scenario, all regs in upper bank
4214 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4215 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4216 Assembler::vpaddb(xmm0, xmm0, src, vector_len);
4217 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4218 }
4219 }
4220
4221 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4222 int dst_enc = dst->encoding();
4223 int nds_enc = nds->encoding();
4224 int src_enc = src->encoding();
4225 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4226 Assembler::vpaddw(dst, nds, src, vector_len);
4227 } else if ((dst_enc < 16) && (src_enc < 16)) {
4228 Assembler::vpaddw(dst, dst, src, vector_len);
4229 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4230 // use nds as scratch for src
4231 evmovdqul(nds, src, Assembler::AVX_512bit);
4232 Assembler::vpaddw(dst, dst, nds, vector_len);
4233 } else if ((src_enc < 16) && (nds_enc < 16)) {
4234 // use nds as scratch for dst
4235 evmovdqul(nds, dst, Assembler::AVX_512bit);
4236 Assembler::vpaddw(nds, nds, src, vector_len);
4237 evmovdqul(dst, nds, Assembler::AVX_512bit);
4238 } else if (dst_enc < 16) {
4239 // use nds as scatch for xmm0 to hold src
4240 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4241 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4242 Assembler::vpaddw(dst, dst, xmm0, vector_len);
4243 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4244 } else {
4245 // worse case scenario, all regs are in the upper bank
4246 subptr(rsp, 64);
4247 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4248 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4249 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4250 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4251 Assembler::vpaddw(xmm0, xmm0, xmm1, vector_len);
4252 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4253 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4254 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4255 addptr(rsp, 64);
4256 }
4257 }
4258
4259 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4260 int dst_enc = dst->encoding();
4261 int nds_enc = nds->encoding();
4262 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4263 Assembler::vpaddw(dst, nds, src, vector_len);
4264 } else if (dst_enc < 16) {
4265 Assembler::vpaddw(dst, dst, src, vector_len);
4266 } else if (nds_enc < 16) {
4267 // implies dst_enc in upper bank with src as scratch
4268 evmovdqul(nds, dst, Assembler::AVX_512bit);
4269 Assembler::vpaddw(nds, nds, src, vector_len);
4270 evmovdqul(dst, nds, Assembler::AVX_512bit);
4271 } else {
4272 // worse case scenario, all regs in upper bank
4273 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4274 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4275 Assembler::vpaddw(xmm0, xmm0, src, vector_len);
4276 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4277 }
4278 }
4279
4280 void MacroAssembler::vpbroadcastw(XMMRegister dst, XMMRegister src) {
4281 int dst_enc = dst->encoding();
4282 int src_enc = src->encoding();
4283 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4284 Assembler::vpbroadcastw(dst, src);
4285 } else if ((dst_enc < 16) && (src_enc < 16)) {
4286 Assembler::vpbroadcastw(dst, src);
4287 } else if (src_enc < 16) {
4288 subptr(rsp, 64);
4289 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4290 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4291 Assembler::vpbroadcastw(xmm0, src);
4292 movdqu(dst, xmm0);
4293 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4294 addptr(rsp, 64);
4295 } else if (dst_enc < 16) {
4296 subptr(rsp, 64);
4297 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4298 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4299 Assembler::vpbroadcastw(dst, xmm0);
4300 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4301 addptr(rsp, 64);
4302 } else {
4303 subptr(rsp, 64);
4304 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4305 subptr(rsp, 64);
4306 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4307 movdqu(xmm0, src);
4308 movdqu(xmm1, dst);
4309 Assembler::vpbroadcastw(xmm1, xmm0);
4310 movdqu(dst, xmm1);
4311 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4312 addptr(rsp, 64);
4313 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4314 addptr(rsp, 64);
4315 }
4316 }
4317
4318 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4319 int dst_enc = dst->encoding();
4320 int nds_enc = nds->encoding();
4321 int src_enc = src->encoding();
4322 assert(dst_enc == nds_enc, "");
4323 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4324 Assembler::vpcmpeqb(dst, nds, src, vector_len);
4325 } else if ((dst_enc < 16) && (src_enc < 16)) {
4326 Assembler::vpcmpeqb(dst, nds, src, vector_len);
4327 } else if (src_enc < 16) {
4328 subptr(rsp, 64);
4329 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4330 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4331 Assembler::vpcmpeqb(xmm0, xmm0, src, vector_len);
4332 movdqu(dst, xmm0);
4333 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4334 addptr(rsp, 64);
4335 } else if (dst_enc < 16) {
4336 subptr(rsp, 64);
4337 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4338 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4339 Assembler::vpcmpeqb(dst, dst, xmm0, vector_len);
4340 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4341 addptr(rsp, 64);
4342 } else {
4343 subptr(rsp, 64);
4344 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4345 subptr(rsp, 64);
4346 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4347 movdqu(xmm0, src);
4348 movdqu(xmm1, dst);
4349 Assembler::vpcmpeqb(xmm1, xmm1, xmm0, vector_len);
4350 movdqu(dst, xmm1);
4351 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4352 addptr(rsp, 64);
4353 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4354 addptr(rsp, 64);
4355 }
4356 }
4357
4358 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4359 int dst_enc = dst->encoding();
4360 int nds_enc = nds->encoding();
4361 int src_enc = src->encoding();
4362 assert(dst_enc == nds_enc, "");
4363 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4364 Assembler::vpcmpeqw(dst, nds, src, vector_len);
4365 } else if ((dst_enc < 16) && (src_enc < 16)) {
4366 Assembler::vpcmpeqw(dst, nds, src, vector_len);
4367 } else if (src_enc < 16) {
4368 subptr(rsp, 64);
4369 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4370 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4371 Assembler::vpcmpeqw(xmm0, xmm0, src, vector_len);
4372 movdqu(dst, xmm0);
4373 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4374 addptr(rsp, 64);
4375 } else if (dst_enc < 16) {
4376 subptr(rsp, 64);
4377 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4378 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4379 Assembler::vpcmpeqw(dst, dst, xmm0, vector_len);
4380 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4381 addptr(rsp, 64);
4382 } else {
4383 subptr(rsp, 64);
4384 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4385 subptr(rsp, 64);
4386 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4387 movdqu(xmm0, src);
4388 movdqu(xmm1, dst);
4389 Assembler::vpcmpeqw(xmm1, xmm1, xmm0, vector_len);
4390 movdqu(dst, xmm1);
4391 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4392 addptr(rsp, 64);
4393 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4394 addptr(rsp, 64);
4395 }
4396 }
4397
4398 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
4399 int dst_enc = dst->encoding();
4400 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4401 Assembler::vpmovzxbw(dst, src, vector_len);
4402 } else if (dst_enc < 16) {
4403 Assembler::vpmovzxbw(dst, src, vector_len);
4404 } else {
4405 subptr(rsp, 64);
4406 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4407 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4408 Assembler::vpmovzxbw(xmm0, src, vector_len);
4409 movdqu(dst, xmm0);
4410 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4411 addptr(rsp, 64);
4412 }
4413 }
4414
4415 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src) {
4416 int src_enc = src->encoding();
4417 if (src_enc < 16) {
4418 Assembler::vpmovmskb(dst, src);
4419 } else {
4420 subptr(rsp, 64);
4421 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4422 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4423 Assembler::vpmovmskb(dst, xmm0);
4424 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4425 addptr(rsp, 64);
4426 }
4427 }
4428
4429 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4430 int dst_enc = dst->encoding();
4431 int nds_enc = nds->encoding();
4432 int src_enc = src->encoding();
4433 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4434 Assembler::vpmullw(dst, nds, src, vector_len);
4435 } else if ((dst_enc < 16) && (src_enc < 16)) {
4436 Assembler::vpmullw(dst, dst, src, vector_len);
4437 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4438 // use nds as scratch for src
4439 evmovdqul(nds, src, Assembler::AVX_512bit);
4440 Assembler::vpmullw(dst, dst, nds, vector_len);
4441 } else if ((src_enc < 16) && (nds_enc < 16)) {
4442 // use nds as scratch for dst
4443 evmovdqul(nds, dst, Assembler::AVX_512bit);
4444 Assembler::vpmullw(nds, nds, src, vector_len);
4445 evmovdqul(dst, nds, Assembler::AVX_512bit);
4446 } else if (dst_enc < 16) {
4447 // use nds as scatch for xmm0 to hold src
4448 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4449 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4450 Assembler::vpmullw(dst, dst, xmm0, vector_len);
4451 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4452 } else {
4453 // worse case scenario, all regs are in the upper bank
4454 subptr(rsp, 64);
4455 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4456 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4457 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4458 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4459 Assembler::vpmullw(xmm0, xmm0, xmm1, vector_len);
4460 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4461 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4462 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4463 addptr(rsp, 64);
4464 }
4465 }
4466
4467 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4468 int dst_enc = dst->encoding();
4469 int nds_enc = nds->encoding();
4470 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4471 Assembler::vpmullw(dst, nds, src, vector_len);
4472 } else if (dst_enc < 16) {
4473 Assembler::vpmullw(dst, dst, src, vector_len);
4474 } else if (nds_enc < 16) {
4475 // implies dst_enc in upper bank with src as scratch
4476 evmovdqul(nds, dst, Assembler::AVX_512bit);
4477 Assembler::vpmullw(nds, nds, src, vector_len);
4478 evmovdqul(dst, nds, Assembler::AVX_512bit);
4479 } else {
4480 // worse case scenario, all regs in upper bank
4481 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4482 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4483 Assembler::vpmullw(xmm0, xmm0, src, vector_len);
4484 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4485 }
4486 }
4487
4488 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4489 int dst_enc = dst->encoding();
4490 int nds_enc = nds->encoding();
4491 int src_enc = src->encoding();
4492 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4493 Assembler::vpsubb(dst, nds, src, vector_len);
4494 } else if ((dst_enc < 16) && (src_enc < 16)) {
4495 Assembler::vpsubb(dst, dst, src, vector_len);
4496 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4497 // use nds as scratch for src
4498 evmovdqul(nds, src, Assembler::AVX_512bit);
4499 Assembler::vpsubb(dst, dst, nds, vector_len);
4500 } else if ((src_enc < 16) && (nds_enc < 16)) {
4501 // use nds as scratch for dst
4502 evmovdqul(nds, dst, Assembler::AVX_512bit);
4503 Assembler::vpsubb(nds, nds, src, vector_len);
4504 evmovdqul(dst, nds, Assembler::AVX_512bit);
4505 } else if (dst_enc < 16) {
4506 // use nds as scatch for xmm0 to hold src
4507 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4508 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4509 Assembler::vpsubb(dst, dst, xmm0, vector_len);
4510 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4511 } else {
4512 // worse case scenario, all regs are in the upper bank
4513 subptr(rsp, 64);
4514 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4515 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4516 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4517 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4518 Assembler::vpsubb(xmm0, xmm0, xmm1, vector_len);
4519 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4520 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4521 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4522 addptr(rsp, 64);
4523 }
4524 }
4525
4526 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4527 int dst_enc = dst->encoding();
4528 int nds_enc = nds->encoding();
4529 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4530 Assembler::vpsubb(dst, nds, src, vector_len);
4531 } else if (dst_enc < 16) {
4532 Assembler::vpsubb(dst, dst, src, vector_len);
4533 } else if (nds_enc < 16) {
4534 // implies dst_enc in upper bank with src as scratch
4535 evmovdqul(nds, dst, Assembler::AVX_512bit);
4536 Assembler::vpsubb(nds, nds, src, vector_len);
4537 evmovdqul(dst, nds, Assembler::AVX_512bit);
4538 } else {
4539 // worse case scenario, all regs in upper bank
4540 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4541 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4542 Assembler::vpsubw(xmm0, xmm0, src, vector_len);
4543 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4544 }
4545 }
4546
4547 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4548 int dst_enc = dst->encoding();
4549 int nds_enc = nds->encoding();
4550 int src_enc = src->encoding();
4551 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4552 Assembler::vpsubw(dst, nds, src, vector_len);
4553 } else if ((dst_enc < 16) && (src_enc < 16)) {
4554 Assembler::vpsubw(dst, dst, src, vector_len);
4555 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4556 // use nds as scratch for src
4557 evmovdqul(nds, src, Assembler::AVX_512bit);
4558 Assembler::vpsubw(dst, dst, nds, vector_len);
4559 } else if ((src_enc < 16) && (nds_enc < 16)) {
4560 // use nds as scratch for dst
4561 evmovdqul(nds, dst, Assembler::AVX_512bit);
4562 Assembler::vpsubw(nds, nds, src, vector_len);
4563 evmovdqul(dst, nds, Assembler::AVX_512bit);
4564 } else if (dst_enc < 16) {
4565 // use nds as scatch for xmm0 to hold src
4566 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4567 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4568 Assembler::vpsubw(dst, dst, xmm0, vector_len);
4569 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4570 } else {
4571 // worse case scenario, all regs are in the upper bank
4572 subptr(rsp, 64);
4573 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4574 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4575 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4576 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4577 Assembler::vpsubw(xmm0, xmm0, xmm1, vector_len);
4578 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4579 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4580 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4581 addptr(rsp, 64);
4582 }
4583 }
4584
4585 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4586 int dst_enc = dst->encoding();
4587 int nds_enc = nds->encoding();
4588 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4589 Assembler::vpsubw(dst, nds, src, vector_len);
4590 } else if (dst_enc < 16) {
4591 Assembler::vpsubw(dst, dst, src, vector_len);
4592 } else if (nds_enc < 16) {
4593 // implies dst_enc in upper bank with src as scratch
4594 evmovdqul(nds, dst, Assembler::AVX_512bit);
4595 Assembler::vpsubw(nds, nds, src, vector_len);
4596 evmovdqul(dst, nds, Assembler::AVX_512bit);
4597 } else {
4598 // worse case scenario, all regs in upper bank
4599 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4600 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4601 Assembler::vpsubw(xmm0, xmm0, src, vector_len);
4602 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4603 }
4604 }
4605
4606 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
4607 int dst_enc = dst->encoding();
4608 int nds_enc = nds->encoding();
4609 int shift_enc = shift->encoding();
4610 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4611 Assembler::vpsraw(dst, nds, shift, vector_len);
4612 } else if ((dst_enc < 16) && (shift_enc < 16)) {
4613 Assembler::vpsraw(dst, dst, shift, vector_len);
4614 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4615 // use nds_enc as scratch with shift
4616 evmovdqul(nds, shift, Assembler::AVX_512bit);
4617 Assembler::vpsraw(dst, dst, nds, vector_len);
4618 } else if ((shift_enc < 16) && (nds_enc < 16)) {
4619 // use nds as scratch with dst
4620 evmovdqul(nds, dst, Assembler::AVX_512bit);
4621 Assembler::vpsraw(nds, nds, shift, vector_len);
4622 evmovdqul(dst, nds, Assembler::AVX_512bit);
4623 } else if (dst_enc < 16) {
4624 // use nds to save a copy of xmm0 and hold shift
4625 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4626 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4627 Assembler::vpsraw(dst, dst, xmm0, vector_len);
4628 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4629 } else if (nds_enc < 16) {
4630 // use nds as dest as temps
4631 evmovdqul(nds, dst, Assembler::AVX_512bit);
4632 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4633 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4634 Assembler::vpsraw(nds, nds, xmm0, vector_len);
4635 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4636 evmovdqul(dst, nds, Assembler::AVX_512bit);
4637 } else {
4638 // worse case scenario, all regs are in the upper bank
4639 subptr(rsp, 64);
4640 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4641 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4642 evmovdqul(xmm1, shift, Assembler::AVX_512bit);
4643 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4644 Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len);
4645 evmovdqul(xmm1, dst, Assembler::AVX_512bit);
4646 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4647 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4648 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4649 addptr(rsp, 64);
4650 }
4651 }
4652
4653 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
4654 int dst_enc = dst->encoding();
4655 int nds_enc = nds->encoding();
4656 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4657 Assembler::vpsraw(dst, nds, shift, vector_len);
4658 } else if (dst_enc < 16) {
4659 Assembler::vpsraw(dst, dst, shift, vector_len);
4660 } else if (nds_enc < 16) {
4661 // use nds as scratch
4662 evmovdqul(nds, dst, Assembler::AVX_512bit);
4663 Assembler::vpsraw(nds, nds, shift, vector_len);
4664 evmovdqul(dst, nds, Assembler::AVX_512bit);
4665 } else {
4666 // use nds as scratch for xmm0
4667 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4668 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4669 Assembler::vpsraw(xmm0, xmm0, shift, vector_len);
4670 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4671 }
4672 }
4673
4674 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
4675 int dst_enc = dst->encoding();
4676 int nds_enc = nds->encoding();
4677 int shift_enc = shift->encoding();
4678 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4679 Assembler::vpsrlw(dst, nds, shift, vector_len);
4680 } else if ((dst_enc < 16) && (shift_enc < 16)) {
4681 Assembler::vpsrlw(dst, dst, shift, vector_len);
4682 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4683 // use nds_enc as scratch with shift
4684 evmovdqul(nds, shift, Assembler::AVX_512bit);
4685 Assembler::vpsrlw(dst, dst, nds, vector_len);
4686 } else if ((shift_enc < 16) && (nds_enc < 16)) {
4687 // use nds as scratch with dst
4688 evmovdqul(nds, dst, Assembler::AVX_512bit);
4689 Assembler::vpsrlw(nds, nds, shift, vector_len);
4690 evmovdqul(dst, nds, Assembler::AVX_512bit);
4691 } else if (dst_enc < 16) {
4692 // use nds to save a copy of xmm0 and hold shift
4693 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4694 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4695 Assembler::vpsrlw(dst, dst, xmm0, vector_len);
4696 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4697 } else if (nds_enc < 16) {
4698 // use nds as dest as temps
4699 evmovdqul(nds, dst, Assembler::AVX_512bit);
4700 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4701 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4702 Assembler::vpsrlw(nds, nds, xmm0, vector_len);
4703 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4704 evmovdqul(dst, nds, Assembler::AVX_512bit);
4705 } else {
4706 // worse case scenario, all regs are in the upper bank
4707 subptr(rsp, 64);
4708 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4709 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4710 evmovdqul(xmm1, shift, Assembler::AVX_512bit);
4711 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4712 Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len);
4713 evmovdqul(xmm1, dst, Assembler::AVX_512bit);
4714 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4715 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4716 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4717 addptr(rsp, 64);
4718 }
4719 }
4720
4721 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
4722 int dst_enc = dst->encoding();
4723 int nds_enc = nds->encoding();
4724 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4725 Assembler::vpsrlw(dst, nds, shift, vector_len);
4726 } else if (dst_enc < 16) {
4727 Assembler::vpsrlw(dst, dst, shift, vector_len);
4728 } else if (nds_enc < 16) {
4729 // use nds as scratch
4730 evmovdqul(nds, dst, Assembler::AVX_512bit);
4731 Assembler::vpsrlw(nds, nds, shift, vector_len);
4732 evmovdqul(dst, nds, Assembler::AVX_512bit);
4733 } else {
4734 // use nds as scratch for xmm0
4735 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4736 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4737 Assembler::vpsrlw(xmm0, xmm0, shift, vector_len);
4738 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4739 }
4740 }
4741
4742 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
4743 int dst_enc = dst->encoding();
4744 int nds_enc = nds->encoding();
4745 int shift_enc = shift->encoding();
4746 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4747 Assembler::vpsllw(dst, nds, shift, vector_len);
4748 } else if ((dst_enc < 16) && (shift_enc < 16)) {
4749 Assembler::vpsllw(dst, dst, shift, vector_len);
4750 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4751 // use nds_enc as scratch with shift
4752 evmovdqul(nds, shift, Assembler::AVX_512bit);
4753 Assembler::vpsllw(dst, dst, nds, vector_len);
4754 } else if ((shift_enc < 16) && (nds_enc < 16)) {
4755 // use nds as scratch with dst
4756 evmovdqul(nds, dst, Assembler::AVX_512bit);
4757 Assembler::vpsllw(nds, nds, shift, vector_len);
4758 evmovdqul(dst, nds, Assembler::AVX_512bit);
4759 } else if (dst_enc < 16) {
4760 // use nds to save a copy of xmm0 and hold shift
4761 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4762 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4763 Assembler::vpsllw(dst, dst, xmm0, vector_len);
4764 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4765 } else if (nds_enc < 16) {
4766 // use nds as dest as temps
4767 evmovdqul(nds, dst, Assembler::AVX_512bit);
4768 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4769 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4770 Assembler::vpsllw(nds, nds, xmm0, vector_len);
4771 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4772 evmovdqul(dst, nds, Assembler::AVX_512bit);
4773 } else {
4774 // worse case scenario, all regs are in the upper bank
4775 subptr(rsp, 64);
4776 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4777 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4778 evmovdqul(xmm1, shift, Assembler::AVX_512bit);
4779 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4780 Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len);
4781 evmovdqul(xmm1, dst, Assembler::AVX_512bit);
4782 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4783 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4784 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4785 addptr(rsp, 64);
4786 }
4787 }
4788
4789 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
4790 int dst_enc = dst->encoding();
4791 int nds_enc = nds->encoding();
4792 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4793 Assembler::vpsllw(dst, nds, shift, vector_len);
4794 } else if (dst_enc < 16) {
4795 Assembler::vpsllw(dst, dst, shift, vector_len);
4796 } else if (nds_enc < 16) {
4797 // use nds as scratch
4798 evmovdqul(nds, dst, Assembler::AVX_512bit);
4799 Assembler::vpsllw(nds, nds, shift, vector_len);
4800 evmovdqul(dst, nds, Assembler::AVX_512bit);
4801 } else {
4802 // use nds as scratch for xmm0
4803 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4804 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4805 Assembler::vpsllw(xmm0, xmm0, shift, vector_len);
4806 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4807 }
4808 }
4809
4810 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) {
4811 int dst_enc = dst->encoding();
4812 int src_enc = src->encoding();
4813 if ((dst_enc < 16) && (src_enc < 16)) {
4814 Assembler::vptest(dst, src);
4815 } else if (src_enc < 16) {
4816 subptr(rsp, 64);
4817 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4818 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4819 Assembler::vptest(xmm0, src);
4820 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4821 addptr(rsp, 64);
4822 } else if (dst_enc < 16) {
4823 subptr(rsp, 64);
4824 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4825 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4826 Assembler::vptest(dst, xmm0);
4827 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4828 addptr(rsp, 64);
4829 } else {
4830 subptr(rsp, 64);
4831 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4832 subptr(rsp, 64);
4833 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4834 movdqu(xmm0, src);
4835 movdqu(xmm1, dst);
4836 Assembler::vptest(xmm1, xmm0);
4837 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4838 addptr(rsp, 64);
4839 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4840 addptr(rsp, 64);
4841 }
4842 }
4843
4844 // This instruction exists within macros, ergo we cannot control its input
4845 // when emitted through those patterns.
4846 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) {
4847 if (VM_Version::supports_avx512nobw()) {
4848 int dst_enc = dst->encoding();
4849 int src_enc = src->encoding();
4850 if (dst_enc == src_enc) {
4851 if (dst_enc < 16) {
4852 Assembler::punpcklbw(dst, src);
4853 } else {
4854 subptr(rsp, 64);
4855 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4856 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4857 Assembler::punpcklbw(xmm0, xmm0);
4858 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4859 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4860 addptr(rsp, 64);
4861 }
4862 } else {
4863 if ((src_enc < 16) && (dst_enc < 16)) {
4864 Assembler::punpcklbw(dst, src);
4865 } else if (src_enc < 16) {
4866 subptr(rsp, 64);
4867 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4868 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4869 Assembler::punpcklbw(xmm0, src);
4870 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4871 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4872 addptr(rsp, 64);
4873 } else if (dst_enc < 16) {
4874 subptr(rsp, 64);
4875 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4876 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4877 Assembler::punpcklbw(dst, xmm0);
4878 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4879 addptr(rsp, 64);
4880 } else {
4881 subptr(rsp, 64);
4882 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4883 subptr(rsp, 64);
4884 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4885 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4886 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4887 Assembler::punpcklbw(xmm0, xmm1);
4888 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4889 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4890 addptr(rsp, 64);
4891 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4892 addptr(rsp, 64);
4893 }
4894 }
4895 } else {
4896 Assembler::punpcklbw(dst, src);
4897 }
4898 }
4899
4900 // This instruction exists within macros, ergo we cannot control its input
4901 // when emitted through those patterns.
4902 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
4903 if (VM_Version::supports_avx512nobw()) {
4904 int dst_enc = dst->encoding();
4905 int src_enc = src->encoding();
4906 if (dst_enc == src_enc) {
4907 if (dst_enc < 16) {
4908 Assembler::pshuflw(dst, src, mode);
4909 } else {
4910 subptr(rsp, 64);
4911 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4912 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4913 Assembler::pshuflw(xmm0, xmm0, mode);
4914 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4915 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4916 addptr(rsp, 64);
4917 }
4918 } else {
4919 if ((src_enc < 16) && (dst_enc < 16)) {
4920 Assembler::pshuflw(dst, src, mode);
4921 } else if (src_enc < 16) {
4922 subptr(rsp, 64);
4923 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4924 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4925 Assembler::pshuflw(xmm0, src, mode);
4926 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4927 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4928 addptr(rsp, 64);
4929 } else if (dst_enc < 16) {
4930 subptr(rsp, 64);
4931 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4932 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4933 Assembler::pshuflw(dst, xmm0, mode);
4934 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4935 addptr(rsp, 64);
4936 } else {
4937 subptr(rsp, 64);
4938 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4939 subptr(rsp, 64);
4940 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4941 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4942 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4943 Assembler::pshuflw(xmm0, xmm1, mode);
4944 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4945 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4946 addptr(rsp, 64);
4947 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4948 addptr(rsp, 64);
4949 }
4950 }
4951 } else {
4952 Assembler::pshuflw(dst, src, mode);
4953 }
4954 }
4955
4956 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
4957 if (reachable(src)) {
4958 vandpd(dst, nds, as_Address(src), vector_len);
4959 } else {
4960 lea(rscratch1, src);
4961 vandpd(dst, nds, Address(rscratch1, 0), vector_len);
4962 }
4963 }
4964
4965 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
4966 if (reachable(src)) {
4967 vandps(dst, nds, as_Address(src), vector_len);
4968 } else {
4969 lea(rscratch1, src);
4970 vandps(dst, nds, Address(rscratch1, 0), vector_len);
4971 }
4972 }
4973
4974 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4975 if (reachable(src)) {
4976 vdivsd(dst, nds, as_Address(src));
4977 } else {
4978 lea(rscratch1, src);
4979 vdivsd(dst, nds, Address(rscratch1, 0));
4980 }
4981 }
4982
4983 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4984 if (reachable(src)) {
4985 vdivss(dst, nds, as_Address(src));
4986 } else {
4987 lea(rscratch1, src);
4988 vdivss(dst, nds, Address(rscratch1, 0));
4989 }
4990 }
4991
4992 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4993 if (reachable(src)) {
4994 vmulsd(dst, nds, as_Address(src));
4995 } else {
4996 lea(rscratch1, src);
4997 vmulsd(dst, nds, Address(rscratch1, 0));
4998 }
4999 }
5000
5001 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5002 if (reachable(src)) {
5003 vmulss(dst, nds, as_Address(src));
5004 } else {
5005 lea(rscratch1, src);
5006 vmulss(dst, nds, Address(rscratch1, 0));
5007 }
5008 }
5009
5010 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5011 if (reachable(src)) {
5012 vsubsd(dst, nds, as_Address(src));
5013 } else {
5014 lea(rscratch1, src);
5015 vsubsd(dst, nds, Address(rscratch1, 0));
5016 }
5017 }
5018
5019 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5020 if (reachable(src)) {
5021 vsubss(dst, nds, as_Address(src));
5022 } else {
5023 lea(rscratch1, src);
5024 vsubss(dst, nds, Address(rscratch1, 0));
5025 }
5026 }
5027
5028 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5029 int nds_enc = nds->encoding();
5030 int dst_enc = dst->encoding();
5031 bool dst_upper_bank = (dst_enc > 15);
5032 bool nds_upper_bank = (nds_enc > 15);
5033 if (VM_Version::supports_avx512novl() &&
5034 (nds_upper_bank || dst_upper_bank)) {
5035 if (dst_upper_bank) {
5036 subptr(rsp, 64);
5037 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
5038 movflt(xmm0, nds);
5039 vxorps(xmm0, xmm0, src, Assembler::AVX_128bit);
5040 movflt(dst, xmm0);
5041 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
5042 addptr(rsp, 64);
5043 } else {
5044 movflt(dst, nds);
5045 vxorps(dst, dst, src, Assembler::AVX_128bit);
5046 }
5047 } else {
5048 vxorps(dst, nds, src, Assembler::AVX_128bit);
5049 }
5050 }
5051
5052 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5053 int nds_enc = nds->encoding();
5054 int dst_enc = dst->encoding();
5055 bool dst_upper_bank = (dst_enc > 15);
5056 bool nds_upper_bank = (nds_enc > 15);
5057 if (VM_Version::supports_avx512novl() &&
5058 (nds_upper_bank || dst_upper_bank)) {
5059 if (dst_upper_bank) {
5060 subptr(rsp, 64);
5061 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
5062 movdbl(xmm0, nds);
5063 vxorpd(xmm0, xmm0, src, Assembler::AVX_128bit);
5064 movdbl(dst, xmm0);
5065 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
5066 addptr(rsp, 64);
5067 } else {
5068 movdbl(dst, nds);
5069 vxorpd(dst, dst, src, Assembler::AVX_128bit);
5070 }
5071 } else {
5072 vxorpd(dst, nds, src, Assembler::AVX_128bit);
5073 }
5074 }
5075
5076 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
5077 if (reachable(src)) {
5078 vxorpd(dst, nds, as_Address(src), vector_len);
5079 } else {
5080 lea(rscratch1, src);
5081 vxorpd(dst, nds, Address(rscratch1, 0), vector_len);
5082 }
5083 }
5084
5085 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
5086 if (reachable(src)) {
5087 vxorps(dst, nds, as_Address(src), vector_len);
5088 } else {
5089 lea(rscratch1, src);
5090 vxorps(dst, nds, Address(rscratch1, 0), vector_len);
5091 }
5092 }
5093
5094
5095 //////////////////////////////////////////////////////////////////////////////////
5096 #if INCLUDE_ALL_GCS
5097
5098 void MacroAssembler::g1_write_barrier_pre(Register obj,
5099 Register pre_val,
5100 Register thread,
5101 Register tmp,
5102 bool tosca_live,
5103 bool expand_call) {
5104
5105 // If expand_call is true then we expand the call_VM_leaf macro
5106 // directly to skip generating the check by
5107 // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp.
5108
5109 #ifdef _LP64
5110 assert(thread == r15_thread, "must be");
5111 #endif // _LP64
5112
5113 Label done;
5114 Label runtime;
5115
5116 assert(pre_val != noreg, "check this code");
5117
5118 if (obj != noreg) {
5119 assert_different_registers(obj, pre_val, tmp);
5120 assert(pre_val != rax, "check this code");
5121 }
5122
5123 Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
5124 SATBMarkQueue::byte_offset_of_active()));
5125 Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
5126 SATBMarkQueue::byte_offset_of_index()));
5127 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
5128 SATBMarkQueue::byte_offset_of_buf()));
5129
5130
5131 // Is marking active?
5132 if (in_bytes(SATBMarkQueue::byte_width_of_active()) == 4) {
5133 cmpl(in_progress, 0);
5134 } else {
5135 assert(in_bytes(SATBMarkQueue::byte_width_of_active()) == 1, "Assumption");
5136 cmpb(in_progress, 0);
5137 }
5138 jcc(Assembler::equal, done);
5139
5140 // Do we need to load the previous value?
5141 if (obj != noreg) {
5142 load_heap_oop(pre_val, Address(obj, 0));
5143 }
5144
5145 // Is the previous value null?
5146 cmpptr(pre_val, (int32_t) NULL_WORD);
5147 jcc(Assembler::equal, done);
5148
5149 // Can we store original value in the thread's buffer?
5150 // Is index == 0?
5151 // (The index field is typed as size_t.)
5152
5153 movptr(tmp, index); // tmp := *index_adr
5154 cmpptr(tmp, 0); // tmp == 0?
5155 jcc(Assembler::equal, runtime); // If yes, goto runtime
5156
5157 subptr(tmp, wordSize); // tmp := tmp - wordSize
5158 movptr(index, tmp); // *index_adr := tmp
5159 addptr(tmp, buffer); // tmp := tmp + *buffer_adr
5160
5161 // Record the previous value
5162 movptr(Address(tmp, 0), pre_val);
5163 jmp(done);
5164
5165 bind(runtime);
5166 // save the live input values
5167 if(tosca_live) push(rax);
5168
5169 if (obj != noreg && obj != rax)
5170 push(obj);
5171
5172 if (pre_val != rax)
5173 push(pre_val);
5174
5175 // Calling the runtime using the regular call_VM_leaf mechanism generates
5176 // code (generated by InterpreterMacroAssember::call_VM_leaf_base)
5177 // that checks that the *(ebp+frame::interpreter_frame_last_sp) == NULL.
5178 //
5179 // If we care generating the pre-barrier without a frame (e.g. in the
5180 // intrinsified Reference.get() routine) then ebp might be pointing to
5181 // the caller frame and so this check will most likely fail at runtime.
5182 //
5183 // Expanding the call directly bypasses the generation of the check.
5184 // So when we do not have have a full interpreter frame on the stack
5185 // expand_call should be passed true.
5186
5187 NOT_LP64( push(thread); )
5188
5189 if (expand_call) {
5190 LP64_ONLY( assert(pre_val != c_rarg1, "smashed arg"); )
5191 pass_arg1(this, thread);
5192 pass_arg0(this, pre_val);
5193 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), 2);
5194 } else {
5195 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), pre_val, thread);
5196 }
5197
5198 NOT_LP64( pop(thread); )
5199
5200 // save the live input values
5201 if (pre_val != rax)
5202 pop(pre_val);
5203
5204 if (obj != noreg && obj != rax)
5205 pop(obj);
5206
5207 if(tosca_live) pop(rax);
5208
5209 bind(done);
5210 }
5211
5212 void MacroAssembler::g1_write_barrier_post(Register store_addr,
5213 Register new_val,
5214 Register thread,
5215 Register tmp,
5216 Register tmp2) {
5217 #ifdef _LP64
5218 assert(thread == r15_thread, "must be");
5219 #endif // _LP64
5220
5221 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
5222 DirtyCardQueue::byte_offset_of_index()));
5223 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
5224 DirtyCardQueue::byte_offset_of_buf()));
5225
5226 CardTableModRefBS* ct =
5227 barrier_set_cast<CardTableModRefBS>(Universe::heap()->barrier_set());
5228 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
5229
5230 Label done;
5231 Label runtime;
5232
5233 // Does store cross heap regions?
5234
5235 movptr(tmp, store_addr);
5236 xorptr(tmp, new_val);
5237 shrptr(tmp, HeapRegion::LogOfHRGrainBytes);
5238 jcc(Assembler::equal, done);
5239
5240 // crosses regions, storing NULL?
5241
5242 cmpptr(new_val, (int32_t) NULL_WORD);
5243 jcc(Assembler::equal, done);
5244
5245 // storing region crossing non-NULL, is card already dirty?
5246
5247 const Register card_addr = tmp;
5248 const Register cardtable = tmp2;
5249
5250 movptr(card_addr, store_addr);
5251 shrptr(card_addr, CardTableModRefBS::card_shift);
5252 // Do not use ExternalAddress to load 'byte_map_base', since 'byte_map_base' is NOT
5253 // a valid address and therefore is not properly handled by the relocation code.
5254 movptr(cardtable, (intptr_t)ct->byte_map_base);
5255 addptr(card_addr, cardtable);
5256
5257 cmpb(Address(card_addr, 0), (int)G1SATBCardTableModRefBS::g1_young_card_val());
5258 jcc(Assembler::equal, done);
5259
5260 membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
5261 cmpb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val());
5262 jcc(Assembler::equal, done);
5263
5264
5265 // storing a region crossing, non-NULL oop, card is clean.
5266 // dirty card and log.
5267
5268 movb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val());
5269
5270 cmpl(queue_index, 0);
5271 jcc(Assembler::equal, runtime);
5272 subl(queue_index, wordSize);
5273 movptr(tmp2, buffer);
5274 #ifdef _LP64
5275 movslq(rscratch1, queue_index);
5276 addq(tmp2, rscratch1);
5277 movq(Address(tmp2, 0), card_addr);
5278 #else
5279 addl(tmp2, queue_index);
5280 movl(Address(tmp2, 0), card_addr);
5281 #endif
5282 jmp(done);
5283
5284 bind(runtime);
5285 // save the live input values
5286 push(store_addr);
5287 push(new_val);
5288 #ifdef _LP64
5289 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, r15_thread);
5290 #else
5291 push(thread);
5292 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread);
5293 pop(thread);
5294 #endif
5295 pop(new_val);
5296 pop(store_addr);
5297
5298 bind(done);
5299 }
5300
5301 #endif // INCLUDE_ALL_GCS
5302 //////////////////////////////////////////////////////////////////////////////////
5303
5304
5305 void MacroAssembler::store_check(Register obj, Address dst) {
5306 store_check(obj);
5307 }
5308
5309 void MacroAssembler::store_check(Register obj) {
5310 // Does a store check for the oop in register obj. The content of
5311 // register obj is destroyed afterwards.
5312 BarrierSet* bs = Universe::heap()->barrier_set();
5313 assert(bs->kind() == BarrierSet::CardTableForRS ||
5314 bs->kind() == BarrierSet::CardTableExtension,
5315 "Wrong barrier set kind");
5316
5317 CardTableModRefBS* ct = barrier_set_cast<CardTableModRefBS>(bs);
5318 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
5319
5320 shrptr(obj, CardTableModRefBS::card_shift);
5321
5322 Address card_addr;
5323
5324 // The calculation for byte_map_base is as follows:
5325 // byte_map_base = _byte_map - (uintptr_t(low_bound) >> card_shift);
5326 // So this essentially converts an address to a displacement and it will
5327 // never need to be relocated. On 64bit however the value may be too
5328 // large for a 32bit displacement.
5329 intptr_t disp = (intptr_t) ct->byte_map_base;
5330 if (is_simm32(disp)) {
5331 card_addr = Address(noreg, obj, Address::times_1, disp);
5332 } else {
5333 // By doing it as an ExternalAddress 'disp' could be converted to a rip-relative
5334 // displacement and done in a single instruction given favorable mapping and a
5335 // smarter version of as_Address. However, 'ExternalAddress' generates a relocation
5336 // entry and that entry is not properly handled by the relocation code.
5337 AddressLiteral cardtable((address)ct->byte_map_base, relocInfo::none);
5338 Address index(noreg, obj, Address::times_1);
5339 card_addr = as_Address(ArrayAddress(cardtable, index));
5340 }
5341
5342 int dirty = CardTableModRefBS::dirty_card_val();
5343 if (UseCondCardMark) {
5344 Label L_already_dirty;
5345 if (UseConcMarkSweepGC) {
5346 membar(Assembler::StoreLoad);
5347 }
5348 cmpb(card_addr, dirty);
5349 jcc(Assembler::equal, L_already_dirty);
5350 movb(card_addr, dirty);
5351 bind(L_already_dirty);
5352 } else {
5353 movb(card_addr, dirty);
5354 }
5355 }
5356
5357 void MacroAssembler::subptr(Register dst, int32_t imm32) {
5358 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
5359 }
5360
5361 // Force generation of a 4 byte immediate value even if it fits into 8bit
5362 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
5363 LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32));
5364 }
5365
5366 void MacroAssembler::subptr(Register dst, Register src) {
5367 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
5368 }
5369
5370 // C++ bool manipulation
5371 void MacroAssembler::testbool(Register dst) {
5372 if(sizeof(bool) == 1)
5373 testb(dst, 0xff);
5374 else if(sizeof(bool) == 2) {
5375 // testw implementation needed for two byte bools
5376 ShouldNotReachHere();
5377 } else if(sizeof(bool) == 4)
5378 testl(dst, dst);
5379 else
5380 // unsupported
5381 ShouldNotReachHere();
5382 }
5383
5384 void MacroAssembler::testptr(Register dst, Register src) {
5385 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
5386 }
5387
5388 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
5389 void MacroAssembler::tlab_allocate(Register obj,
5390 Register var_size_in_bytes,
5391 int con_size_in_bytes,
5392 Register t1,
5393 Register t2,
5394 Label& slow_case) {
5395 assert_different_registers(obj, t1, t2);
5396 assert_different_registers(obj, var_size_in_bytes, t1);
5397 Register end = t2;
5398 Register thread = NOT_LP64(t1) LP64_ONLY(r15_thread);
5399
5400 verify_tlab();
5401
5402 NOT_LP64(get_thread(thread));
5403
5404 movptr(obj, Address(thread, JavaThread::tlab_top_offset()));
5405 if (var_size_in_bytes == noreg) {
5406 lea(end, Address(obj, con_size_in_bytes));
5407 } else {
5408 lea(end, Address(obj, var_size_in_bytes, Address::times_1));
5409 }
5410 cmpptr(end, Address(thread, JavaThread::tlab_end_offset()));
5411 jcc(Assembler::above, slow_case);
5412
5413 // update the tlab top pointer
5414 movptr(Address(thread, JavaThread::tlab_top_offset()), end);
5415
5416 // recover var_size_in_bytes if necessary
5417 if (var_size_in_bytes == end) {
5418 subptr(var_size_in_bytes, obj);
5419 }
5420 verify_tlab();
5421 }
5422
5423 // Preserves rbx, and rdx.
5424 Register MacroAssembler::tlab_refill(Label& retry,
5425 Label& try_eden,
5426 Label& slow_case) {
5427 Register top = rax;
5428 Register t1 = rcx; // object size
5429 Register t2 = rsi;
5430 Register thread_reg = NOT_LP64(rdi) LP64_ONLY(r15_thread);
5431 assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ rbx, rdx);
5432 Label do_refill, discard_tlab;
5433
5434 if (!Universe::heap()->supports_inline_contig_alloc()) {
5435 // No allocation in the shared eden.
5436 jmp(slow_case);
5437 }
5438
5439 NOT_LP64(get_thread(thread_reg));
5440
5441 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5442 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
5443
5444 // calculate amount of free space
5445 subptr(t1, top);
5446 shrptr(t1, LogHeapWordSize);
5447
5448 // Retain tlab and allocate object in shared space if
5449 // the amount free in the tlab is too large to discard.
5450 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())));
5451 jcc(Assembler::lessEqual, discard_tlab);
5452
5453 // Retain
5454 // %%% yuck as movptr...
5455 movptr(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment());
5456 addptr(Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())), t2);
5457 if (TLABStats) {
5458 // increment number of slow_allocations
5459 addl(Address(thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())), 1);
5460 }
5461 jmp(try_eden);
5462
5463 bind(discard_tlab);
5464 if (TLABStats) {
5465 // increment number of refills
5466 addl(Address(thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1);
5467 // accumulate wastage -- t1 is amount free in tlab
5468 addl(Address(thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1);
5469 }
5470
5471 // if tlab is currently allocated (top or end != null) then
5472 // fill [top, end + alignment_reserve) with array object
5473 testptr(top, top);
5474 jcc(Assembler::zero, do_refill);
5475
5476 // set up the mark word
5477 movptr(Address(top, oopDesc::mark_offset_in_bytes()), (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2));
5478 // set the length to the remaining space
5479 subptr(t1, typeArrayOopDesc::header_size(T_INT));
5480 addptr(t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve());
5481 shlptr(t1, log2_intptr(HeapWordSize/sizeof(jint)));
5482 movl(Address(top, arrayOopDesc::length_offset_in_bytes()), t1);
5483 // set klass to intArrayKlass
5484 // dubious reloc why not an oop reloc?
5485 movptr(t1, ExternalAddress((address)Universe::intArrayKlassObj_addr()));
5486 // store klass last. concurrent gcs assumes klass length is valid if
5487 // klass field is not null.
5488 store_klass(top, t1);
5489
5490 movptr(t1, top);
5491 subptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
5492 incr_allocated_bytes(thread_reg, t1, 0);
5493
5494 // refill the tlab with an eden allocation
5495 bind(do_refill);
5496 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
5497 shlptr(t1, LogHeapWordSize);
5498 // allocate new tlab, address returned in top
5499 eden_allocate(top, t1, 0, t2, slow_case);
5500
5501 // Check that t1 was preserved in eden_allocate.
5502 #ifdef ASSERT
5503 if (UseTLAB) {
5504 Label ok;
5505 Register tsize = rsi;
5506 assert_different_registers(tsize, thread_reg, t1);
5507 push(tsize);
5508 movptr(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
5509 shlptr(tsize, LogHeapWordSize);
5510 cmpptr(t1, tsize);
5511 jcc(Assembler::equal, ok);
5512 STOP("assert(t1 != tlab size)");
5513 should_not_reach_here();
5514
5515 bind(ok);
5516 pop(tsize);
5517 }
5518 #endif
5519 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top);
5520 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top);
5521 addptr(top, t1);
5522 subptr(top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes());
5523 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top);
5524
5525 if (ZeroTLAB) {
5526 // This is a fast TLAB refill, therefore the GC is not notified of it.
5527 // So compiled code must fill the new TLAB with zeroes.
5528 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
5529 zero_memory(top, t1, 0, t2);
5530 }
5531
5532 verify_tlab();
5533 jmp(retry);
5534
5535 return thread_reg; // for use by caller
5536 }
5537
5538 // Preserves the contents of address, destroys the contents length_in_bytes and temp.
5539 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) {
5540 assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different");
5541 assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord");
5542 Label done;
5543
5544 testptr(length_in_bytes, length_in_bytes);
5545 jcc(Assembler::zero, done);
5546
5547 // initialize topmost word, divide index by 2, check if odd and test if zero
5548 // note: for the remaining code to work, index must be a multiple of BytesPerWord
5549 #ifdef ASSERT
5550 {
5551 Label L;
5552 testptr(length_in_bytes, BytesPerWord - 1);
5553 jcc(Assembler::zero, L);
5554 stop("length must be a multiple of BytesPerWord");
5555 bind(L);
5556 }
5557 #endif
5558 Register index = length_in_bytes;
5559 xorptr(temp, temp); // use _zero reg to clear memory (shorter code)
5560 if (UseIncDec) {
5561 shrptr(index, 3); // divide by 8/16 and set carry flag if bit 2 was set
5562 } else {
5563 shrptr(index, 2); // use 2 instructions to avoid partial flag stall
5564 shrptr(index, 1);
5565 }
5566 #ifndef _LP64
5567 // index could have not been a multiple of 8 (i.e., bit 2 was set)
5568 {
5569 Label even;
5570 // note: if index was a multiple of 8, then it cannot
5571 // be 0 now otherwise it must have been 0 before
5572 // => if it is even, we don't need to check for 0 again
5573 jcc(Assembler::carryClear, even);
5574 // clear topmost word (no jump would be needed if conditional assignment worked here)
5575 movptr(Address(address, index, Address::times_8, offset_in_bytes - 0*BytesPerWord), temp);
5576 // index could be 0 now, must check again
5577 jcc(Assembler::zero, done);
5578 bind(even);
5579 }
5580 #endif // !_LP64
5581 // initialize remaining object fields: index is a multiple of 2 now
5582 {
5583 Label loop;
5584 bind(loop);
5585 movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp);
5586 NOT_LP64(movptr(Address(address, index, Address::times_8, offset_in_bytes - 2*BytesPerWord), temp);)
5587 decrement(index);
5588 jcc(Assembler::notZero, loop);
5589 }
5590
5591 bind(done);
5592 }
5593
5594 void MacroAssembler::incr_allocated_bytes(Register thread,
5595 Register var_size_in_bytes,
5596 int con_size_in_bytes,
5597 Register t1) {
5598 if (!thread->is_valid()) {
5599 #ifdef _LP64
5600 thread = r15_thread;
5601 #else
5602 assert(t1->is_valid(), "need temp reg");
5603 thread = t1;
5604 get_thread(thread);
5605 #endif
5606 }
5607
5608 #ifdef _LP64
5609 if (var_size_in_bytes->is_valid()) {
5610 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes);
5611 } else {
5612 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes);
5613 }
5614 #else
5615 if (var_size_in_bytes->is_valid()) {
5616 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes);
5617 } else {
5618 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes);
5619 }
5620 adcl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())+4), 0);
5621 #endif
5622 }
5623
5624 void MacroAssembler::fp_runtime_fallback(address runtime_entry, int nb_args, int num_fpu_regs_in_use) {
5625 pusha();
5626
5627 // if we are coming from c1, xmm registers may be live
5628 int num_xmm_regs = LP64_ONLY(16) NOT_LP64(8);
5629 if (UseAVX > 2) {
5630 num_xmm_regs = LP64_ONLY(32) NOT_LP64(8);
5631 }
5632
5633 if (UseSSE == 1) {
5634 subptr(rsp, sizeof(jdouble)*8);
5635 for (int n = 0; n < 8; n++) {
5636 movflt(Address(rsp, n*sizeof(jdouble)), as_XMMRegister(n));
5637 }
5638 } else if (UseSSE >= 2) {
5639 if (UseAVX > 2) {
5640 push(rbx);
5641 movl(rbx, 0xffff);
5642 kmovwl(k1, rbx);
5643 pop(rbx);
5644 }
5645 #ifdef COMPILER2
5646 if (MaxVectorSize > 16) {
5647 if(UseAVX > 2) {
5648 // Save upper half of ZMM registers
5649 subptr(rsp, 32*num_xmm_regs);
5650 for (int n = 0; n < num_xmm_regs; n++) {
5651 vextractf64x4_high(Address(rsp, n*32), as_XMMRegister(n));
5652 }
5653 }
5654 assert(UseAVX > 0, "256 bit vectors are supported only with AVX");
5655 // Save upper half of YMM registers
5656 subptr(rsp, 16*num_xmm_regs);
5657 for (int n = 0; n < num_xmm_regs; n++) {
5658 vextractf128_high(Address(rsp, n*16), as_XMMRegister(n));
5659 }
5660 }
5661 #endif
5662 // Save whole 128bit (16 bytes) XMM registers
5663 subptr(rsp, 16*num_xmm_regs);
5664 #ifdef _LP64
5665 if (VM_Version::supports_evex()) {
5666 for (int n = 0; n < num_xmm_regs; n++) {
5667 vextractf32x4(Address(rsp, n*16), as_XMMRegister(n), 0);
5668 }
5669 } else {
5670 for (int n = 0; n < num_xmm_regs; n++) {
5671 movdqu(Address(rsp, n*16), as_XMMRegister(n));
5672 }
5673 }
5674 #else
5675 for (int n = 0; n < num_xmm_regs; n++) {
5676 movdqu(Address(rsp, n*16), as_XMMRegister(n));
5677 }
5678 #endif
5679 }
5680
5681 // Preserve registers across runtime call
5682 int incoming_argument_and_return_value_offset = -1;
5683 if (num_fpu_regs_in_use > 1) {
5684 // Must preserve all other FPU regs (could alternatively convert
5685 // SharedRuntime::dsin, dcos etc. into assembly routines known not to trash
5686 // FPU state, but can not trust C compiler)
5687 NEEDS_CLEANUP;
5688 // NOTE that in this case we also push the incoming argument(s) to
5689 // the stack and restore it later; we also use this stack slot to
5690 // hold the return value from dsin, dcos etc.
5691 for (int i = 0; i < num_fpu_regs_in_use; i++) {
5692 subptr(rsp, sizeof(jdouble));
5693 fstp_d(Address(rsp, 0));
5694 }
5695 incoming_argument_and_return_value_offset = sizeof(jdouble)*(num_fpu_regs_in_use-1);
5696 for (int i = nb_args-1; i >= 0; i--) {
5697 fld_d(Address(rsp, incoming_argument_and_return_value_offset-i*sizeof(jdouble)));
5698 }
5699 }
5700
5701 subptr(rsp, nb_args*sizeof(jdouble));
5702 for (int i = 0; i < nb_args; i++) {
5703 fstp_d(Address(rsp, i*sizeof(jdouble)));
5704 }
5705
5706 #ifdef _LP64
5707 if (nb_args > 0) {
5708 movdbl(xmm0, Address(rsp, 0));
5709 }
5710 if (nb_args > 1) {
5711 movdbl(xmm1, Address(rsp, sizeof(jdouble)));
5712 }
5713 assert(nb_args <= 2, "unsupported number of args");
5714 #endif // _LP64
5715
5716 // NOTE: we must not use call_VM_leaf here because that requires a
5717 // complete interpreter frame in debug mode -- same bug as 4387334
5718 // MacroAssembler::call_VM_leaf_base is perfectly safe and will
5719 // do proper 64bit abi
5720
5721 NEEDS_CLEANUP;
5722 // Need to add stack banging before this runtime call if it needs to
5723 // be taken; however, there is no generic stack banging routine at
5724 // the MacroAssembler level
5725
5726 MacroAssembler::call_VM_leaf_base(runtime_entry, 0);
5727
5728 #ifdef _LP64
5729 movsd(Address(rsp, 0), xmm0);
5730 fld_d(Address(rsp, 0));
5731 #endif // _LP64
5732 addptr(rsp, sizeof(jdouble)*nb_args);
5733 if (num_fpu_regs_in_use > 1) {
5734 // Must save return value to stack and then restore entire FPU
5735 // stack except incoming arguments
5736 fstp_d(Address(rsp, incoming_argument_and_return_value_offset));
5737 for (int i = 0; i < num_fpu_regs_in_use - nb_args; i++) {
5738 fld_d(Address(rsp, 0));
5739 addptr(rsp, sizeof(jdouble));
5740 }
5741 fld_d(Address(rsp, (nb_args-1)*sizeof(jdouble)));
5742 addptr(rsp, sizeof(jdouble)*nb_args);
5743 }
5744
5745 if (UseSSE == 1) {
5746 for (int n = 0; n < 8; n++) {
5747 movflt(as_XMMRegister(n), Address(rsp, n*sizeof(jdouble)));
5748 }
5749 addptr(rsp, sizeof(jdouble)*8);
5750 } else if (UseSSE >= 2) {
5751 // Restore whole 128bit (16 bytes) XMM registers
5752 #ifdef _LP64
5753 if (VM_Version::supports_evex()) {
5754 for (int n = 0; n < num_xmm_regs; n++) {
5755 vinsertf32x4(as_XMMRegister(n), as_XMMRegister(n), Address(rsp, n*16), 0);
5756 }
5757 } else {
5758 for (int n = 0; n < num_xmm_regs; n++) {
5759 movdqu(as_XMMRegister(n), Address(rsp, n*16));
5760 }
5761 }
5762 #else
5763 for (int n = 0; n < num_xmm_regs; n++) {
5764 movdqu(as_XMMRegister(n), Address(rsp, n*16));
5765 }
5766 #endif
5767 addptr(rsp, 16*num_xmm_regs);
5768
5769 #ifdef COMPILER2
5770 if (MaxVectorSize > 16) {
5771 // Restore upper half of YMM registers.
5772 for (int n = 0; n < num_xmm_regs; n++) {
5773 vinsertf128_high(as_XMMRegister(n), Address(rsp, n*16));
5774 }
5775 addptr(rsp, 16*num_xmm_regs);
5776 if(UseAVX > 2) {
5777 for (int n = 0; n < num_xmm_regs; n++) {
5778 vinsertf64x4_high(as_XMMRegister(n), Address(rsp, n*32));
5779 }
5780 addptr(rsp, 32*num_xmm_regs);
5781 }
5782 }
5783 #endif
5784 }
5785 popa();
5786 }
5787
5788 static const double pi_4 = 0.7853981633974483;
5789
5790 void MacroAssembler::trigfunc(char trig, int num_fpu_regs_in_use) {
5791 // A hand-coded argument reduction for values in fabs(pi/4, pi/2)
5792 // was attempted in this code; unfortunately it appears that the
5793 // switch to 80-bit precision and back causes this to be
5794 // unprofitable compared with simply performing a runtime call if
5795 // the argument is out of the (-pi/4, pi/4) range.
5796
5797 Register tmp = noreg;
5798 if (!VM_Version::supports_cmov()) {
5799 // fcmp needs a temporary so preserve rbx,
5800 tmp = rbx;
5801 push(tmp);
5802 }
5803
5804 Label slow_case, done;
5805 if (trig == 't') {
5806 ExternalAddress pi4_adr = (address)&pi_4;
5807 if (reachable(pi4_adr)) {
5808 // x ?<= pi/4
5809 fld_d(pi4_adr);
5810 fld_s(1); // Stack: X PI/4 X
5811 fabs(); // Stack: |X| PI/4 X
5812 fcmp(tmp);
5813 jcc(Assembler::above, slow_case);
5814
5815 // fastest case: -pi/4 <= x <= pi/4
5816 ftan();
5817
5818 jmp(done);
5819 }
5820 }
5821 // slow case: runtime call
5822 bind(slow_case);
5823
5824 switch(trig) {
5825 case 's':
5826 {
5827 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dsin), 1, num_fpu_regs_in_use);
5828 }
5829 break;
5830 case 'c':
5831 {
5832 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dcos), 1, num_fpu_regs_in_use);
5833 }
5834 break;
5835 case 't':
5836 {
5837 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dtan), 1, num_fpu_regs_in_use);
5838 }
5839 break;
5840 default:
5841 assert(false, "bad intrinsic");
5842 break;
5843 }
5844
5845 // Come here with result in F-TOS
5846 bind(done);
5847
5848 if (tmp != noreg) {
5849 pop(tmp);
5850 }
5851 }
5852
5853 // Look up the method for a megamorphic invokeinterface call.
5854 // The target method is determined by <intf_klass, itable_index>.
5855 // The receiver klass is in recv_klass.
5856 // On success, the result will be in method_result, and execution falls through.
5857 // On failure, execution transfers to the given label.
5858 void MacroAssembler::lookup_interface_method(Register recv_klass,
5859 Register intf_klass,
5860 RegisterOrConstant itable_index,
5861 Register method_result,
5862 Register scan_temp,
5863 Label& L_no_such_interface) {
5864 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp);
5865 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
5866 "caller must use same register for non-constant itable index as for method");
5867
5868 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
5869 int vtable_base = in_bytes(Klass::vtable_start_offset());
5870 int itentry_off = itableMethodEntry::method_offset_in_bytes();
5871 int scan_step = itableOffsetEntry::size() * wordSize;
5872 int vte_size = vtableEntry::size_in_bytes();
5873 Address::ScaleFactor times_vte_scale = Address::times_ptr;
5874 assert(vte_size == wordSize, "else adjust times_vte_scale");
5875
5876 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
5877
5878 // %%% Could store the aligned, prescaled offset in the klassoop.
5879 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
5880
5881 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
5882 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
5883 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
5884
5885 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
5886 // if (scan->interface() == intf) {
5887 // result = (klass + scan->offset() + itable_index);
5888 // }
5889 // }
5890 Label search, found_method;
5891
5892 for (int peel = 1; peel >= 0; peel--) {
5893 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
5894 cmpptr(intf_klass, method_result);
5895
5896 if (peel) {
5897 jccb(Assembler::equal, found_method);
5898 } else {
5899 jccb(Assembler::notEqual, search);
5900 // (invert the test to fall through to found_method...)
5901 }
5902
5903 if (!peel) break;
5904
5905 bind(search);
5906
5907 // Check that the previous entry is non-null. A null entry means that
5908 // the receiver class doesn't implement the interface, and wasn't the
5909 // same as when the caller was compiled.
5910 testptr(method_result, method_result);
5911 jcc(Assembler::zero, L_no_such_interface);
5912 addptr(scan_temp, scan_step);
5913 }
5914
5915 bind(found_method);
5916
5917 // Got a hit.
5918 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes()));
5919 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
5920 }
5921
5922
5923 // virtual method calling
5924 void MacroAssembler::lookup_virtual_method(Register recv_klass,
5925 RegisterOrConstant vtable_index,
5926 Register method_result) {
5927 const int base = in_bytes(Klass::vtable_start_offset());
5928 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
5929 Address vtable_entry_addr(recv_klass,
5930 vtable_index, Address::times_ptr,
5931 base + vtableEntry::method_offset_in_bytes());
5932 movptr(method_result, vtable_entry_addr);
5933 }
5934
5935
5936 void MacroAssembler::check_klass_subtype(Register sub_klass,
5937 Register super_klass,
5938 Register temp_reg,
5939 Label& L_success) {
5940 Label L_failure;
5941 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL);
5942 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL);
5943 bind(L_failure);
5944 }
5945
5946
5947 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
5948 Register super_klass,
5949 Register temp_reg,
5950 Label* L_success,
5951 Label* L_failure,
5952 Label* L_slow_path,
5953 RegisterOrConstant super_check_offset) {
5954 assert_different_registers(sub_klass, super_klass, temp_reg);
5955 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
5956 if (super_check_offset.is_register()) {
5957 assert_different_registers(sub_klass, super_klass,
5958 super_check_offset.as_register());
5959 } else if (must_load_sco) {
5960 assert(temp_reg != noreg, "supply either a temp or a register offset");
5961 }
5962
5963 Label L_fallthrough;
5964 int label_nulls = 0;
5965 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
5966 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
5967 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
5968 assert(label_nulls <= 1, "at most one NULL in the batch");
5969
5970 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
5971 int sco_offset = in_bytes(Klass::super_check_offset_offset());
5972 Address super_check_offset_addr(super_klass, sco_offset);
5973
5974 // Hacked jcc, which "knows" that L_fallthrough, at least, is in
5975 // range of a jccb. If this routine grows larger, reconsider at
5976 // least some of these.
5977 #define local_jcc(assembler_cond, label) \
5978 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \
5979 else jcc( assembler_cond, label) /*omit semi*/
5980
5981 // Hacked jmp, which may only be used just before L_fallthrough.
5982 #define final_jmp(label) \
5983 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
5984 else jmp(label) /*omit semi*/
5985
5986 // If the pointers are equal, we are done (e.g., String[] elements).
5987 // This self-check enables sharing of secondary supertype arrays among
5988 // non-primary types such as array-of-interface. Otherwise, each such
5989 // type would need its own customized SSA.
5990 // We move this check to the front of the fast path because many
5991 // type checks are in fact trivially successful in this manner,
5992 // so we get a nicely predicted branch right at the start of the check.
5993 cmpptr(sub_klass, super_klass);
5994 local_jcc(Assembler::equal, *L_success);
5995
5996 // Check the supertype display:
5997 if (must_load_sco) {
5998 // Positive movl does right thing on LP64.
5999 movl(temp_reg, super_check_offset_addr);
6000 super_check_offset = RegisterOrConstant(temp_reg);
6001 }
6002 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
6003 cmpptr(super_klass, super_check_addr); // load displayed supertype
6004
6005 // This check has worked decisively for primary supers.
6006 // Secondary supers are sought in the super_cache ('super_cache_addr').
6007 // (Secondary supers are interfaces and very deeply nested subtypes.)
6008 // This works in the same check above because of a tricky aliasing
6009 // between the super_cache and the primary super display elements.
6010 // (The 'super_check_addr' can address either, as the case requires.)
6011 // Note that the cache is updated below if it does not help us find
6012 // what we need immediately.
6013 // So if it was a primary super, we can just fail immediately.
6014 // Otherwise, it's the slow path for us (no success at this point).
6015
6016 if (super_check_offset.is_register()) {
6017 local_jcc(Assembler::equal, *L_success);
6018 cmpl(super_check_offset.as_register(), sc_offset);
6019 if (L_failure == &L_fallthrough) {
6020 local_jcc(Assembler::equal, *L_slow_path);
6021 } else {
6022 local_jcc(Assembler::notEqual, *L_failure);
6023 final_jmp(*L_slow_path);
6024 }
6025 } else if (super_check_offset.as_constant() == sc_offset) {
6026 // Need a slow path; fast failure is impossible.
6027 if (L_slow_path == &L_fallthrough) {
6028 local_jcc(Assembler::equal, *L_success);
6029 } else {
6030 local_jcc(Assembler::notEqual, *L_slow_path);
6031 final_jmp(*L_success);
6032 }
6033 } else {
6034 // No slow path; it's a fast decision.
6035 if (L_failure == &L_fallthrough) {
6036 local_jcc(Assembler::equal, *L_success);
6037 } else {
6038 local_jcc(Assembler::notEqual, *L_failure);
6039 final_jmp(*L_success);
6040 }
6041 }
6042
6043 bind(L_fallthrough);
6044
6045 #undef local_jcc
6046 #undef final_jmp
6047 }
6048
6049
6050 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
6051 Register super_klass,
6052 Register temp_reg,
6053 Register temp2_reg,
6054 Label* L_success,
6055 Label* L_failure,
6056 bool set_cond_codes) {
6057 assert_different_registers(sub_klass, super_klass, temp_reg);
6058 if (temp2_reg != noreg)
6059 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
6060 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
6061
6062 Label L_fallthrough;
6063 int label_nulls = 0;
6064 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
6065 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
6066 assert(label_nulls <= 1, "at most one NULL in the batch");
6067
6068 // a couple of useful fields in sub_klass:
6069 int ss_offset = in_bytes(Klass::secondary_supers_offset());
6070 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
6071 Address secondary_supers_addr(sub_klass, ss_offset);
6072 Address super_cache_addr( sub_klass, sc_offset);
6073
6074 // Do a linear scan of the secondary super-klass chain.
6075 // This code is rarely used, so simplicity is a virtue here.
6076 // The repne_scan instruction uses fixed registers, which we must spill.
6077 // Don't worry too much about pre-existing connections with the input regs.
6078
6079 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
6080 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
6081
6082 // Get super_klass value into rax (even if it was in rdi or rcx).
6083 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
6084 if (super_klass != rax || UseCompressedOops) {
6085 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
6086 mov(rax, super_klass);
6087 }
6088 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
6089 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
6090
6091 #ifndef PRODUCT
6092 int* pst_counter = &SharedRuntime::_partial_subtype_ctr;
6093 ExternalAddress pst_counter_addr((address) pst_counter);
6094 NOT_LP64( incrementl(pst_counter_addr) );
6095 LP64_ONLY( lea(rcx, pst_counter_addr) );
6096 LP64_ONLY( incrementl(Address(rcx, 0)) );
6097 #endif //PRODUCT
6098
6099 // We will consult the secondary-super array.
6100 movptr(rdi, secondary_supers_addr);
6101 // Load the array length. (Positive movl does right thing on LP64.)
6102 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
6103 // Skip to start of data.
6104 addptr(rdi, Array<Klass*>::base_offset_in_bytes());
6105
6106 // Scan RCX words at [RDI] for an occurrence of RAX.
6107 // Set NZ/Z based on last compare.
6108 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
6109 // not change flags (only scas instruction which is repeated sets flags).
6110 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
6111
6112 testptr(rax,rax); // Set Z = 0
6113 repne_scan();
6114
6115 // Unspill the temp. registers:
6116 if (pushed_rdi) pop(rdi);
6117 if (pushed_rcx) pop(rcx);
6118 if (pushed_rax) pop(rax);
6119
6120 if (set_cond_codes) {
6121 // Special hack for the AD files: rdi is guaranteed non-zero.
6122 assert(!pushed_rdi, "rdi must be left non-NULL");
6123 // Also, the condition codes are properly set Z/NZ on succeed/failure.
6124 }
6125
6126 if (L_failure == &L_fallthrough)
6127 jccb(Assembler::notEqual, *L_failure);
6128 else jcc(Assembler::notEqual, *L_failure);
6129
6130 // Success. Cache the super we found and proceed in triumph.
6131 movptr(super_cache_addr, super_klass);
6132
6133 if (L_success != &L_fallthrough) {
6134 jmp(*L_success);
6135 }
6136
6137 #undef IS_A_TEMP
6138
6139 bind(L_fallthrough);
6140 }
6141
6142
6143 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
6144 if (VM_Version::supports_cmov()) {
6145 cmovl(cc, dst, src);
6146 } else {
6147 Label L;
6148 jccb(negate_condition(cc), L);
6149 movl(dst, src);
6150 bind(L);
6151 }
6152 }
6153
6154 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
6155 if (VM_Version::supports_cmov()) {
6156 cmovl(cc, dst, src);
6157 } else {
6158 Label L;
6159 jccb(negate_condition(cc), L);
6160 movl(dst, src);
6161 bind(L);
6162 }
6163 }
6164
6165 void MacroAssembler::verify_oop(Register reg, const char* s) {
6166 if (!VerifyOops) return;
6167
6168 // Pass register number to verify_oop_subroutine
6169 const char* b = NULL;
6170 {
6171 ResourceMark rm;
6172 stringStream ss;
6173 ss.print("verify_oop: %s: %s", reg->name(), s);
6174 b = code_string(ss.as_string());
6175 }
6176 BLOCK_COMMENT("verify_oop {");
6177 #ifdef _LP64
6178 push(rscratch1); // save r10, trashed by movptr()
6179 #endif
6180 push(rax); // save rax,
6181 push(reg); // pass register argument
6182 ExternalAddress buffer((address) b);
6183 // avoid using pushptr, as it modifies scratch registers
6184 // and our contract is not to modify anything
6185 movptr(rax, buffer.addr());
6186 push(rax);
6187 // call indirectly to solve generation ordering problem
6188 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
6189 call(rax);
6190 // Caller pops the arguments (oop, message) and restores rax, r10
6191 BLOCK_COMMENT("} verify_oop");
6192 }
6193
6194
6195 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
6196 Register tmp,
6197 int offset) {
6198 intptr_t value = *delayed_value_addr;
6199 if (value != 0)
6200 return RegisterOrConstant(value + offset);
6201
6202 // load indirectly to solve generation ordering problem
6203 movptr(tmp, ExternalAddress((address) delayed_value_addr));
6204
6205 #ifdef ASSERT
6206 { Label L;
6207 testptr(tmp, tmp);
6208 if (WizardMode) {
6209 const char* buf = NULL;
6210 {
6211 ResourceMark rm;
6212 stringStream ss;
6213 ss.print("DelayedValue=" INTPTR_FORMAT, delayed_value_addr[1]);
6214 buf = code_string(ss.as_string());
6215 }
6216 jcc(Assembler::notZero, L);
6217 STOP(buf);
6218 } else {
6219 jccb(Assembler::notZero, L);
6220 hlt();
6221 }
6222 bind(L);
6223 }
6224 #endif
6225
6226 if (offset != 0)
6227 addptr(tmp, offset);
6228
6229 return RegisterOrConstant(tmp);
6230 }
6231
6232
6233 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
6234 int extra_slot_offset) {
6235 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
6236 int stackElementSize = Interpreter::stackElementSize;
6237 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
6238 #ifdef ASSERT
6239 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
6240 assert(offset1 - offset == stackElementSize, "correct arithmetic");
6241 #endif
6242 Register scale_reg = noreg;
6243 Address::ScaleFactor scale_factor = Address::no_scale;
6244 if (arg_slot.is_constant()) {
6245 offset += arg_slot.as_constant() * stackElementSize;
6246 } else {
6247 scale_reg = arg_slot.as_register();
6248 scale_factor = Address::times(stackElementSize);
6249 }
6250 offset += wordSize; // return PC is on stack
6251 return Address(rsp, scale_reg, scale_factor, offset);
6252 }
6253
6254
6255 void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
6256 if (!VerifyOops) return;
6257
6258 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord);
6259 // Pass register number to verify_oop_subroutine
6260 const char* b = NULL;
6261 {
6262 ResourceMark rm;
6263 stringStream ss;
6264 ss.print("verify_oop_addr: %s", s);
6265 b = code_string(ss.as_string());
6266 }
6267 #ifdef _LP64
6268 push(rscratch1); // save r10, trashed by movptr()
6269 #endif
6270 push(rax); // save rax,
6271 // addr may contain rsp so we will have to adjust it based on the push
6272 // we just did (and on 64 bit we do two pushes)
6273 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
6274 // stores rax into addr which is backwards of what was intended.
6275 if (addr.uses(rsp)) {
6276 lea(rax, addr);
6277 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord));
6278 } else {
6279 pushptr(addr);
6280 }
6281
6282 ExternalAddress buffer((address) b);
6283 // pass msg argument
6284 // avoid using pushptr, as it modifies scratch registers
6285 // and our contract is not to modify anything
6286 movptr(rax, buffer.addr());
6287 push(rax);
6288
6289 // call indirectly to solve generation ordering problem
6290 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
6291 call(rax);
6292 // Caller pops the arguments (addr, message) and restores rax, r10.
6293 }
6294
6295 void MacroAssembler::verify_tlab() {
6296 #ifdef ASSERT
6297 if (UseTLAB && VerifyOops) {
6298 Label next, ok;
6299 Register t1 = rsi;
6300 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
6301
6302 push(t1);
6303 NOT_LP64(push(thread_reg));
6304 NOT_LP64(get_thread(thread_reg));
6305
6306 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
6307 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
6308 jcc(Assembler::aboveEqual, next);
6309 STOP("assert(top >= start)");
6310 should_not_reach_here();
6311
6312 bind(next);
6313 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
6314 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
6315 jcc(Assembler::aboveEqual, ok);
6316 STOP("assert(top <= end)");
6317 should_not_reach_here();
6318
6319 bind(ok);
6320 NOT_LP64(pop(thread_reg));
6321 pop(t1);
6322 }
6323 #endif
6324 }
6325
6326 class ControlWord {
6327 public:
6328 int32_t _value;
6329
6330 int rounding_control() const { return (_value >> 10) & 3 ; }
6331 int precision_control() const { return (_value >> 8) & 3 ; }
6332 bool precision() const { return ((_value >> 5) & 1) != 0; }
6333 bool underflow() const { return ((_value >> 4) & 1) != 0; }
6334 bool overflow() const { return ((_value >> 3) & 1) != 0; }
6335 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
6336 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
6337 bool invalid() const { return ((_value >> 0) & 1) != 0; }
6338
6339 void print() const {
6340 // rounding control
6341 const char* rc;
6342 switch (rounding_control()) {
6343 case 0: rc = "round near"; break;
6344 case 1: rc = "round down"; break;
6345 case 2: rc = "round up "; break;
6346 case 3: rc = "chop "; break;
6347 };
6348 // precision control
6349 const char* pc;
6350 switch (precision_control()) {
6351 case 0: pc = "24 bits "; break;
6352 case 1: pc = "reserved"; break;
6353 case 2: pc = "53 bits "; break;
6354 case 3: pc = "64 bits "; break;
6355 };
6356 // flags
6357 char f[9];
6358 f[0] = ' ';
6359 f[1] = ' ';
6360 f[2] = (precision ()) ? 'P' : 'p';
6361 f[3] = (underflow ()) ? 'U' : 'u';
6362 f[4] = (overflow ()) ? 'O' : 'o';
6363 f[5] = (zero_divide ()) ? 'Z' : 'z';
6364 f[6] = (denormalized()) ? 'D' : 'd';
6365 f[7] = (invalid ()) ? 'I' : 'i';
6366 f[8] = '\x0';
6367 // output
6368 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
6369 }
6370
6371 };
6372
6373 class StatusWord {
6374 public:
6375 int32_t _value;
6376
6377 bool busy() const { return ((_value >> 15) & 1) != 0; }
6378 bool C3() const { return ((_value >> 14) & 1) != 0; }
6379 bool C2() const { return ((_value >> 10) & 1) != 0; }
6380 bool C1() const { return ((_value >> 9) & 1) != 0; }
6381 bool C0() const { return ((_value >> 8) & 1) != 0; }
6382 int top() const { return (_value >> 11) & 7 ; }
6383 bool error_status() const { return ((_value >> 7) & 1) != 0; }
6384 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
6385 bool precision() const { return ((_value >> 5) & 1) != 0; }
6386 bool underflow() const { return ((_value >> 4) & 1) != 0; }
6387 bool overflow() const { return ((_value >> 3) & 1) != 0; }
6388 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
6389 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
6390 bool invalid() const { return ((_value >> 0) & 1) != 0; }
6391
6392 void print() const {
6393 // condition codes
6394 char c[5];
6395 c[0] = (C3()) ? '3' : '-';
6396 c[1] = (C2()) ? '2' : '-';
6397 c[2] = (C1()) ? '1' : '-';
6398 c[3] = (C0()) ? '0' : '-';
6399 c[4] = '\x0';
6400 // flags
6401 char f[9];
6402 f[0] = (error_status()) ? 'E' : '-';
6403 f[1] = (stack_fault ()) ? 'S' : '-';
6404 f[2] = (precision ()) ? 'P' : '-';
6405 f[3] = (underflow ()) ? 'U' : '-';
6406 f[4] = (overflow ()) ? 'O' : '-';
6407 f[5] = (zero_divide ()) ? 'Z' : '-';
6408 f[6] = (denormalized()) ? 'D' : '-';
6409 f[7] = (invalid ()) ? 'I' : '-';
6410 f[8] = '\x0';
6411 // output
6412 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
6413 }
6414
6415 };
6416
6417 class TagWord {
6418 public:
6419 int32_t _value;
6420
6421 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
6422
6423 void print() const {
6424 printf("%04x", _value & 0xFFFF);
6425 }
6426
6427 };
6428
6429 class FPU_Register {
6430 public:
6431 int32_t _m0;
6432 int32_t _m1;
6433 int16_t _ex;
6434
6435 bool is_indefinite() const {
6436 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
6437 }
6438
6439 void print() const {
6440 char sign = (_ex < 0) ? '-' : '+';
6441 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
6442 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
6443 };
6444
6445 };
6446
6447 class FPU_State {
6448 public:
6449 enum {
6450 register_size = 10,
6451 number_of_registers = 8,
6452 register_mask = 7
6453 };
6454
6455 ControlWord _control_word;
6456 StatusWord _status_word;
6457 TagWord _tag_word;
6458 int32_t _error_offset;
6459 int32_t _error_selector;
6460 int32_t _data_offset;
6461 int32_t _data_selector;
6462 int8_t _register[register_size * number_of_registers];
6463
6464 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
6465 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
6466
6467 const char* tag_as_string(int tag) const {
6468 switch (tag) {
6469 case 0: return "valid";
6470 case 1: return "zero";
6471 case 2: return "special";
6472 case 3: return "empty";
6473 }
6474 ShouldNotReachHere();
6475 return NULL;
6476 }
6477
6478 void print() const {
6479 // print computation registers
6480 { int t = _status_word.top();
6481 for (int i = 0; i < number_of_registers; i++) {
6482 int j = (i - t) & register_mask;
6483 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
6484 st(j)->print();
6485 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
6486 }
6487 }
6488 printf("\n");
6489 // print control registers
6490 printf("ctrl = "); _control_word.print(); printf("\n");
6491 printf("stat = "); _status_word .print(); printf("\n");
6492 printf("tags = "); _tag_word .print(); printf("\n");
6493 }
6494
6495 };
6496
6497 class Flag_Register {
6498 public:
6499 int32_t _value;
6500
6501 bool overflow() const { return ((_value >> 11) & 1) != 0; }
6502 bool direction() const { return ((_value >> 10) & 1) != 0; }
6503 bool sign() const { return ((_value >> 7) & 1) != 0; }
6504 bool zero() const { return ((_value >> 6) & 1) != 0; }
6505 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
6506 bool parity() const { return ((_value >> 2) & 1) != 0; }
6507 bool carry() const { return ((_value >> 0) & 1) != 0; }
6508
6509 void print() const {
6510 // flags
6511 char f[8];
6512 f[0] = (overflow ()) ? 'O' : '-';
6513 f[1] = (direction ()) ? 'D' : '-';
6514 f[2] = (sign ()) ? 'S' : '-';
6515 f[3] = (zero ()) ? 'Z' : '-';
6516 f[4] = (auxiliary_carry()) ? 'A' : '-';
6517 f[5] = (parity ()) ? 'P' : '-';
6518 f[6] = (carry ()) ? 'C' : '-';
6519 f[7] = '\x0';
6520 // output
6521 printf("%08x flags = %s", _value, f);
6522 }
6523
6524 };
6525
6526 class IU_Register {
6527 public:
6528 int32_t _value;
6529
6530 void print() const {
6531 printf("%08x %11d", _value, _value);
6532 }
6533
6534 };
6535
6536 class IU_State {
6537 public:
6538 Flag_Register _eflags;
6539 IU_Register _rdi;
6540 IU_Register _rsi;
6541 IU_Register _rbp;
6542 IU_Register _rsp;
6543 IU_Register _rbx;
6544 IU_Register _rdx;
6545 IU_Register _rcx;
6546 IU_Register _rax;
6547
6548 void print() const {
6549 // computation registers
6550 printf("rax, = "); _rax.print(); printf("\n");
6551 printf("rbx, = "); _rbx.print(); printf("\n");
6552 printf("rcx = "); _rcx.print(); printf("\n");
6553 printf("rdx = "); _rdx.print(); printf("\n");
6554 printf("rdi = "); _rdi.print(); printf("\n");
6555 printf("rsi = "); _rsi.print(); printf("\n");
6556 printf("rbp, = "); _rbp.print(); printf("\n");
6557 printf("rsp = "); _rsp.print(); printf("\n");
6558 printf("\n");
6559 // control registers
6560 printf("flgs = "); _eflags.print(); printf("\n");
6561 }
6562 };
6563
6564
6565 class CPU_State {
6566 public:
6567 FPU_State _fpu_state;
6568 IU_State _iu_state;
6569
6570 void print() const {
6571 printf("--------------------------------------------------\n");
6572 _iu_state .print();
6573 printf("\n");
6574 _fpu_state.print();
6575 printf("--------------------------------------------------\n");
6576 }
6577
6578 };
6579
6580
6581 static void _print_CPU_state(CPU_State* state) {
6582 state->print();
6583 };
6584
6585
6586 void MacroAssembler::print_CPU_state() {
6587 push_CPU_state();
6588 push(rsp); // pass CPU state
6589 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
6590 addptr(rsp, wordSize); // discard argument
6591 pop_CPU_state();
6592 }
6593
6594
6595 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
6596 static int counter = 0;
6597 FPU_State* fs = &state->_fpu_state;
6598 counter++;
6599 // For leaf calls, only verify that the top few elements remain empty.
6600 // We only need 1 empty at the top for C2 code.
6601 if( stack_depth < 0 ) {
6602 if( fs->tag_for_st(7) != 3 ) {
6603 printf("FPR7 not empty\n");
6604 state->print();
6605 assert(false, "error");
6606 return false;
6607 }
6608 return true; // All other stack states do not matter
6609 }
6610
6611 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std,
6612 "bad FPU control word");
6613
6614 // compute stack depth
6615 int i = 0;
6616 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++;
6617 int d = i;
6618 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
6619 // verify findings
6620 if (i != FPU_State::number_of_registers) {
6621 // stack not contiguous
6622 printf("%s: stack not contiguous at ST%d\n", s, i);
6623 state->print();
6624 assert(false, "error");
6625 return false;
6626 }
6627 // check if computed stack depth corresponds to expected stack depth
6628 if (stack_depth < 0) {
6629 // expected stack depth is -stack_depth or less
6630 if (d > -stack_depth) {
6631 // too many elements on the stack
6632 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
6633 state->print();
6634 assert(false, "error");
6635 return false;
6636 }
6637 } else {
6638 // expected stack depth is stack_depth
6639 if (d != stack_depth) {
6640 // wrong stack depth
6641 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
6642 state->print();
6643 assert(false, "error");
6644 return false;
6645 }
6646 }
6647 // everything is cool
6648 return true;
6649 }
6650
6651
6652 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
6653 if (!VerifyFPU) return;
6654 push_CPU_state();
6655 push(rsp); // pass CPU state
6656 ExternalAddress msg((address) s);
6657 // pass message string s
6658 pushptr(msg.addr());
6659 push(stack_depth); // pass stack depth
6660 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
6661 addptr(rsp, 3 * wordSize); // discard arguments
6662 // check for error
6663 { Label L;
6664 testl(rax, rax);
6665 jcc(Assembler::notZero, L);
6666 int3(); // break if error condition
6667 bind(L);
6668 }
6669 pop_CPU_state();
6670 }
6671
6672 void MacroAssembler::restore_cpu_control_state_after_jni() {
6673 // Either restore the MXCSR register after returning from the JNI Call
6674 // or verify that it wasn't changed (with -Xcheck:jni flag).
6675 if (VM_Version::supports_sse()) {
6676 if (RestoreMXCSROnJNICalls) {
6677 ldmxcsr(ExternalAddress(StubRoutines::addr_mxcsr_std()));
6678 } else if (CheckJNICalls) {
6679 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
6680 }
6681 }
6682 if (VM_Version::supports_avx()) {
6683 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
6684 vzeroupper();
6685 }
6686
6687 #ifndef _LP64
6688 // Either restore the x87 floating pointer control word after returning
6689 // from the JNI call or verify that it wasn't changed.
6690 if (CheckJNICalls) {
6691 call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry()));
6692 }
6693 #endif // _LP64
6694 }
6695
6696
6697 void MacroAssembler::load_klass(Register dst, Register src) {
6698 #ifdef _LP64
6699 if (UseCompressedClassPointers) {
6700 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
6701 decode_klass_not_null(dst);
6702 } else
6703 #endif
6704 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
6705 }
6706
6707 void MacroAssembler::load_prototype_header(Register dst, Register src) {
6708 load_klass(dst, src);
6709 movptr(dst, Address(dst, Klass::prototype_header_offset()));
6710 }
6711
6712 void MacroAssembler::store_klass(Register dst, Register src) {
6713 #ifdef _LP64
6714 if (UseCompressedClassPointers) {
6715 encode_klass_not_null(src);
6716 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
6717 } else
6718 #endif
6719 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
6720 }
6721
6722 void MacroAssembler::load_heap_oop(Register dst, Address src) {
6723 #ifdef _LP64
6724 // FIXME: Must change all places where we try to load the klass.
6725 if (UseCompressedOops) {
6726 movl(dst, src);
6727 decode_heap_oop(dst);
6728 } else
6729 #endif
6730 movptr(dst, src);
6731 }
6732
6733 // Doesn't do verfication, generates fixed size code
6734 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src) {
6735 #ifdef _LP64
6736 if (UseCompressedOops) {
6737 movl(dst, src);
6738 decode_heap_oop_not_null(dst);
6739 } else
6740 #endif
6741 movptr(dst, src);
6742 }
6743
6744 void MacroAssembler::store_heap_oop(Address dst, Register src) {
6745 #ifdef _LP64
6746 if (UseCompressedOops) {
6747 assert(!dst.uses(src), "not enough registers");
6748 encode_heap_oop(src);
6749 movl(dst, src);
6750 } else
6751 #endif
6752 movptr(dst, src);
6753 }
6754
6755 void MacroAssembler::cmp_heap_oop(Register src1, Address src2, Register tmp) {
6756 assert_different_registers(src1, tmp);
6757 #ifdef _LP64
6758 if (UseCompressedOops) {
6759 bool did_push = false;
6760 if (tmp == noreg) {
6761 tmp = rax;
6762 push(tmp);
6763 did_push = true;
6764 assert(!src2.uses(rsp), "can't push");
6765 }
6766 load_heap_oop(tmp, src2);
6767 cmpptr(src1, tmp);
6768 if (did_push) pop(tmp);
6769 } else
6770 #endif
6771 cmpptr(src1, src2);
6772 }
6773
6774 // Used for storing NULLs.
6775 void MacroAssembler::store_heap_oop_null(Address dst) {
6776 #ifdef _LP64
6777 if (UseCompressedOops) {
6778 movl(dst, (int32_t)NULL_WORD);
6779 } else {
6780 movslq(dst, (int32_t)NULL_WORD);
6781 }
6782 #else
6783 movl(dst, (int32_t)NULL_WORD);
6784 #endif
6785 }
6786
6787 #ifdef _LP64
6788 void MacroAssembler::store_klass_gap(Register dst, Register src) {
6789 if (UseCompressedClassPointers) {
6790 // Store to klass gap in destination
6791 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
6792 }
6793 }
6794
6795 #ifdef ASSERT
6796 void MacroAssembler::verify_heapbase(const char* msg) {
6797 assert (UseCompressedOops, "should be compressed");
6798 assert (Universe::heap() != NULL, "java heap should be initialized");
6799 if (CheckCompressedOops) {
6800 Label ok;
6801 push(rscratch1); // cmpptr trashes rscratch1
6802 cmpptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
6803 jcc(Assembler::equal, ok);
6804 STOP(msg);
6805 bind(ok);
6806 pop(rscratch1);
6807 }
6808 }
6809 #endif
6810
6811 // Algorithm must match oop.inline.hpp encode_heap_oop.
6812 void MacroAssembler::encode_heap_oop(Register r) {
6813 #ifdef ASSERT
6814 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
6815 #endif
6816 verify_oop(r, "broken oop in encode_heap_oop");
6817 if (Universe::narrow_oop_base() == NULL) {
6818 if (Universe::narrow_oop_shift() != 0) {
6819 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6820 shrq(r, LogMinObjAlignmentInBytes);
6821 }
6822 return;
6823 }
6824 testq(r, r);
6825 cmovq(Assembler::equal, r, r12_heapbase);
6826 subq(r, r12_heapbase);
6827 shrq(r, LogMinObjAlignmentInBytes);
6828 }
6829
6830 void MacroAssembler::encode_heap_oop_not_null(Register r) {
6831 #ifdef ASSERT
6832 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
6833 if (CheckCompressedOops) {
6834 Label ok;
6835 testq(r, r);
6836 jcc(Assembler::notEqual, ok);
6837 STOP("null oop passed to encode_heap_oop_not_null");
6838 bind(ok);
6839 }
6840 #endif
6841 verify_oop(r, "broken oop in encode_heap_oop_not_null");
6842 if (Universe::narrow_oop_base() != NULL) {
6843 subq(r, r12_heapbase);
6844 }
6845 if (Universe::narrow_oop_shift() != 0) {
6846 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6847 shrq(r, LogMinObjAlignmentInBytes);
6848 }
6849 }
6850
6851 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
6852 #ifdef ASSERT
6853 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
6854 if (CheckCompressedOops) {
6855 Label ok;
6856 testq(src, src);
6857 jcc(Assembler::notEqual, ok);
6858 STOP("null oop passed to encode_heap_oop_not_null2");
6859 bind(ok);
6860 }
6861 #endif
6862 verify_oop(src, "broken oop in encode_heap_oop_not_null2");
6863 if (dst != src) {
6864 movq(dst, src);
6865 }
6866 if (Universe::narrow_oop_base() != NULL) {
6867 subq(dst, r12_heapbase);
6868 }
6869 if (Universe::narrow_oop_shift() != 0) {
6870 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6871 shrq(dst, LogMinObjAlignmentInBytes);
6872 }
6873 }
6874
6875 void MacroAssembler::decode_heap_oop(Register r) {
6876 #ifdef ASSERT
6877 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
6878 #endif
6879 if (Universe::narrow_oop_base() == NULL) {
6880 if (Universe::narrow_oop_shift() != 0) {
6881 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6882 shlq(r, LogMinObjAlignmentInBytes);
6883 }
6884 } else {
6885 Label done;
6886 shlq(r, LogMinObjAlignmentInBytes);
6887 jccb(Assembler::equal, done);
6888 addq(r, r12_heapbase);
6889 bind(done);
6890 }
6891 verify_oop(r, "broken oop in decode_heap_oop");
6892 }
6893
6894 void MacroAssembler::decode_heap_oop_not_null(Register r) {
6895 // Note: it will change flags
6896 assert (UseCompressedOops, "should only be used for compressed headers");
6897 assert (Universe::heap() != NULL, "java heap should be initialized");
6898 // Cannot assert, unverified entry point counts instructions (see .ad file)
6899 // vtableStubs also counts instructions in pd_code_size_limit.
6900 // Also do not verify_oop as this is called by verify_oop.
6901 if (Universe::narrow_oop_shift() != 0) {
6902 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6903 shlq(r, LogMinObjAlignmentInBytes);
6904 if (Universe::narrow_oop_base() != NULL) {
6905 addq(r, r12_heapbase);
6906 }
6907 } else {
6908 assert (Universe::narrow_oop_base() == NULL, "sanity");
6909 }
6910 }
6911
6912 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
6913 // Note: it will change flags
6914 assert (UseCompressedOops, "should only be used for compressed headers");
6915 assert (Universe::heap() != NULL, "java heap should be initialized");
6916 // Cannot assert, unverified entry point counts instructions (see .ad file)
6917 // vtableStubs also counts instructions in pd_code_size_limit.
6918 // Also do not verify_oop as this is called by verify_oop.
6919 if (Universe::narrow_oop_shift() != 0) {
6920 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6921 if (LogMinObjAlignmentInBytes == Address::times_8) {
6922 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
6923 } else {
6924 if (dst != src) {
6925 movq(dst, src);
6926 }
6927 shlq(dst, LogMinObjAlignmentInBytes);
6928 if (Universe::narrow_oop_base() != NULL) {
6929 addq(dst, r12_heapbase);
6930 }
6931 }
6932 } else {
6933 assert (Universe::narrow_oop_base() == NULL, "sanity");
6934 if (dst != src) {
6935 movq(dst, src);
6936 }
6937 }
6938 }
6939
6940 void MacroAssembler::encode_klass_not_null(Register r) {
6941 if (Universe::narrow_klass_base() != NULL) {
6942 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
6943 assert(r != r12_heapbase, "Encoding a klass in r12");
6944 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
6945 subq(r, r12_heapbase);
6946 }
6947 if (Universe::narrow_klass_shift() != 0) {
6948 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6949 shrq(r, LogKlassAlignmentInBytes);
6950 }
6951 if (Universe::narrow_klass_base() != NULL) {
6952 reinit_heapbase();
6953 }
6954 }
6955
6956 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
6957 if (dst == src) {
6958 encode_klass_not_null(src);
6959 } else {
6960 if (Universe::narrow_klass_base() != NULL) {
6961 mov64(dst, (int64_t)Universe::narrow_klass_base());
6962 negq(dst);
6963 addq(dst, src);
6964 } else {
6965 movptr(dst, src);
6966 }
6967 if (Universe::narrow_klass_shift() != 0) {
6968 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6969 shrq(dst, LogKlassAlignmentInBytes);
6970 }
6971 }
6972 }
6973
6974 // Function instr_size_for_decode_klass_not_null() counts the instructions
6975 // generated by decode_klass_not_null(register r) and reinit_heapbase(),
6976 // when (Universe::heap() != NULL). Hence, if the instructions they
6977 // generate change, then this method needs to be updated.
6978 int MacroAssembler::instr_size_for_decode_klass_not_null() {
6979 assert (UseCompressedClassPointers, "only for compressed klass ptrs");
6980 if (Universe::narrow_klass_base() != NULL) {
6981 // mov64 + addq + shlq? + mov64 (for reinit_heapbase()).
6982 return (Universe::narrow_klass_shift() == 0 ? 20 : 24);
6983 } else {
6984 // longest load decode klass function, mov64, leaq
6985 return 16;
6986 }
6987 }
6988
6989 // !!! If the instructions that get generated here change then function
6990 // instr_size_for_decode_klass_not_null() needs to get updated.
6991 void MacroAssembler::decode_klass_not_null(Register r) {
6992 // Note: it will change flags
6993 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6994 assert(r != r12_heapbase, "Decoding a klass in r12");
6995 // Cannot assert, unverified entry point counts instructions (see .ad file)
6996 // vtableStubs also counts instructions in pd_code_size_limit.
6997 // Also do not verify_oop as this is called by verify_oop.
6998 if (Universe::narrow_klass_shift() != 0) {
6999 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
7000 shlq(r, LogKlassAlignmentInBytes);
7001 }
7002 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
7003 if (Universe::narrow_klass_base() != NULL) {
7004 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
7005 addq(r, r12_heapbase);
7006 reinit_heapbase();
7007 }
7008 }
7009
7010 void MacroAssembler::decode_klass_not_null(Register dst, Register src) {
7011 // Note: it will change flags
7012 assert (UseCompressedClassPointers, "should only be used for compressed headers");
7013 if (dst == src) {
7014 decode_klass_not_null(dst);
7015 } else {
7016 // Cannot assert, unverified entry point counts instructions (see .ad file)
7017 // vtableStubs also counts instructions in pd_code_size_limit.
7018 // Also do not verify_oop as this is called by verify_oop.
7019 mov64(dst, (int64_t)Universe::narrow_klass_base());
7020 if (Universe::narrow_klass_shift() != 0) {
7021 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
7022 assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?");
7023 leaq(dst, Address(dst, src, Address::times_8, 0));
7024 } else {
7025 addq(dst, src);
7026 }
7027 }
7028 }
7029
7030 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
7031 assert (UseCompressedOops, "should only be used for compressed headers");
7032 assert (Universe::heap() != NULL, "java heap should be initialized");
7033 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
7034 int oop_index = oop_recorder()->find_index(obj);
7035 RelocationHolder rspec = oop_Relocation::spec(oop_index);
7036 mov_narrow_oop(dst, oop_index, rspec);
7037 }
7038
7039 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
7040 assert (UseCompressedOops, "should only be used for compressed headers");
7041 assert (Universe::heap() != NULL, "java heap should be initialized");
7042 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
7043 int oop_index = oop_recorder()->find_index(obj);
7044 RelocationHolder rspec = oop_Relocation::spec(oop_index);
7045 mov_narrow_oop(dst, oop_index, rspec);
7046 }
7047
7048 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
7049 assert (UseCompressedClassPointers, "should only be used for compressed headers");
7050 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
7051 int klass_index = oop_recorder()->find_index(k);
7052 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
7053 mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
7054 }
7055
7056 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
7057 assert (UseCompressedClassPointers, "should only be used for compressed headers");
7058 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
7059 int klass_index = oop_recorder()->find_index(k);
7060 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
7061 mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
7062 }
7063
7064 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
7065 assert (UseCompressedOops, "should only be used for compressed headers");
7066 assert (Universe::heap() != NULL, "java heap should be initialized");
7067 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
7068 int oop_index = oop_recorder()->find_index(obj);
7069 RelocationHolder rspec = oop_Relocation::spec(oop_index);
7070 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
7071 }
7072
7073 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
7074 assert (UseCompressedOops, "should only be used for compressed headers");
7075 assert (Universe::heap() != NULL, "java heap should be initialized");
7076 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
7077 int oop_index = oop_recorder()->find_index(obj);
7078 RelocationHolder rspec = oop_Relocation::spec(oop_index);
7079 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
7080 }
7081
7082 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
7083 assert (UseCompressedClassPointers, "should only be used for compressed headers");
7084 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
7085 int klass_index = oop_recorder()->find_index(k);
7086 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
7087 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
7088 }
7089
7090 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
7091 assert (UseCompressedClassPointers, "should only be used for compressed headers");
7092 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
7093 int klass_index = oop_recorder()->find_index(k);
7094 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
7095 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
7096 }
7097
7098 void MacroAssembler::reinit_heapbase() {
7099 if (UseCompressedOops || UseCompressedClassPointers) {
7100 if (Universe::heap() != NULL) {
7101 if (Universe::narrow_oop_base() == NULL) {
7102 MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
7103 } else {
7104 mov64(r12_heapbase, (int64_t)Universe::narrow_ptrs_base());
7105 }
7106 } else {
7107 movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
7108 }
7109 }
7110 }
7111
7112 #endif // _LP64
7113
7114
7115 // C2 compiled method's prolog code.
7116 void MacroAssembler::verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b) {
7117
7118 // WARNING: Initial instruction MUST be 5 bytes or longer so that
7119 // NativeJump::patch_verified_entry will be able to patch out the entry
7120 // code safely. The push to verify stack depth is ok at 5 bytes,
7121 // the frame allocation can be either 3 or 6 bytes. So if we don't do
7122 // stack bang then we must use the 6 byte frame allocation even if
7123 // we have no frame. :-(
7124 assert(stack_bang_size >= framesize || stack_bang_size <= 0, "stack bang size incorrect");
7125
7126 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
7127 // Remove word for return addr
7128 framesize -= wordSize;
7129 stack_bang_size -= wordSize;
7130
7131 // Calls to C2R adapters often do not accept exceptional returns.
7132 // We require that their callers must bang for them. But be careful, because
7133 // some VM calls (such as call site linkage) can use several kilobytes of
7134 // stack. But the stack safety zone should account for that.
7135 // See bugs 4446381, 4468289, 4497237.
7136 if (stack_bang_size > 0) {
7137 generate_stack_overflow_check(stack_bang_size);
7138
7139 // We always push rbp, so that on return to interpreter rbp, will be
7140 // restored correctly and we can correct the stack.
7141 push(rbp);
7142 // Save caller's stack pointer into RBP if the frame pointer is preserved.
7143 if (PreserveFramePointer) {
7144 mov(rbp, rsp);
7145 }
7146 // Remove word for ebp
7147 framesize -= wordSize;
7148
7149 // Create frame
7150 if (framesize) {
7151 subptr(rsp, framesize);
7152 }
7153 } else {
7154 // Create frame (force generation of a 4 byte immediate value)
7155 subptr_imm32(rsp, framesize);
7156
7157 // Save RBP register now.
7158 framesize -= wordSize;
7159 movptr(Address(rsp, framesize), rbp);
7160 // Save caller's stack pointer into RBP if the frame pointer is preserved.
7161 if (PreserveFramePointer) {
7162 movptr(rbp, rsp);
7163 if (framesize > 0) {
7164 addptr(rbp, framesize);
7165 }
7166 }
7167 }
7168
7169 if (VerifyStackAtCalls) { // Majik cookie to verify stack depth
7170 framesize -= wordSize;
7171 movptr(Address(rsp, framesize), (int32_t)0xbadb100d);
7172 }
7173
7174 #ifndef _LP64
7175 // If method sets FPU control word do it now
7176 if (fp_mode_24b) {
7177 fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
7178 }
7179 if (UseSSE >= 2 && VerifyFPU) {
7180 verify_FPU(0, "FPU stack must be clean on entry");
7181 }
7182 #endif
7183
7184 #ifdef ASSERT
7185 if (VerifyStackAtCalls) {
7186 Label L;
7187 push(rax);
7188 mov(rax, rsp);
7189 andptr(rax, StackAlignmentInBytes-1);
7190 cmpptr(rax, StackAlignmentInBytes-wordSize);
7191 pop(rax);
7192 jcc(Assembler::equal, L);
7193 STOP("Stack is not properly aligned!");
7194 bind(L);
7195 }
7196 #endif
7197
7198 }
7199
7200 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp, bool is_large) {
7201 // cnt - number of qwords (8-byte words).
7202 // base - start address, qword aligned.
7203 // is_large - if optimizers know cnt is larger than InitArrayShortSize
7204 assert(base==rdi, "base register must be edi for rep stos");
7205 assert(tmp==rax, "tmp register must be eax for rep stos");
7206 assert(cnt==rcx, "cnt register must be ecx for rep stos");
7207 assert(InitArrayShortSize % BytesPerLong == 0,
7208 "InitArrayShortSize should be the multiple of BytesPerLong");
7209
7210 Label DONE;
7211
7212 xorptr(tmp, tmp);
7213
7214 if (!is_large) {
7215 Label LOOP, LONG;
7216 cmpptr(cnt, InitArrayShortSize/BytesPerLong);
7217 jccb(Assembler::greater, LONG);
7218
7219 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
7220
7221 decrement(cnt);
7222 jccb(Assembler::negative, DONE); // Zero length
7223
7224 // Use individual pointer-sized stores for small counts:
7225 BIND(LOOP);
7226 movptr(Address(base, cnt, Address::times_ptr), tmp);
7227 decrement(cnt);
7228 jccb(Assembler::greaterEqual, LOOP);
7229 jmpb(DONE);
7230
7231 BIND(LONG);
7232 }
7233
7234 // Use longer rep-prefixed ops for non-small counts:
7235 if (UseFastStosb) {
7236 shlptr(cnt, 3); // convert to number of bytes
7237 rep_stosb();
7238 } else {
7239 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
7240 rep_stos();
7241 }
7242
7243 BIND(DONE);
7244 }
7245
7246 #ifdef COMPILER2
7247
7248 // IndexOf for constant substrings with size >= 8 chars
7249 // which don't need to be loaded through stack.
7250 void MacroAssembler::string_indexofC8(Register str1, Register str2,
7251 Register cnt1, Register cnt2,
7252 int int_cnt2, Register result,
7253 XMMRegister vec, Register tmp,
7254 int ae) {
7255 ShortBranchVerifier sbv(this);
7256 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
7257 assert(UseSSE >= 4, "SSE4 must be enabled for SSE4.2 intrinsics to be available");
7258 assert(ae != StrIntrinsicNode::LU, "Invalid encoding");
7259
7260 // This method uses the pcmpestri instruction with bound registers
7261 // inputs:
7262 // xmm - substring
7263 // rax - substring length (elements count)
7264 // mem - scanned string
7265 // rdx - string length (elements count)
7266 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
7267 // 0xc - mode: 1100 (substring search) + 00 (unsigned bytes)
7268 // outputs:
7269 // rcx - matched index in string
7270 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
7271 int mode = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts
7272 int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8
7273 Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2;
7274 Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1;
7275
7276 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR,
7277 RET_FOUND, RET_NOT_FOUND, EXIT, FOUND_SUBSTR,
7278 MATCH_SUBSTR_HEAD, RELOAD_STR, FOUND_CANDIDATE;
7279
7280 // Note, inline_string_indexOf() generates checks:
7281 // if (substr.count > string.count) return -1;
7282 // if (substr.count == 0) return 0;
7283 assert(int_cnt2 >= stride, "this code is used only for cnt2 >= 8 chars");
7284
7285 // Load substring.
7286 if (ae == StrIntrinsicNode::UL) {
7287 pmovzxbw(vec, Address(str2, 0));
7288 } else {
7289 movdqu(vec, Address(str2, 0));
7290 }
7291 movl(cnt2, int_cnt2);
7292 movptr(result, str1); // string addr
7293
7294 if (int_cnt2 > stride) {
7295 jmpb(SCAN_TO_SUBSTR);
7296
7297 // Reload substr for rescan, this code
7298 // is executed only for large substrings (> 8 chars)
7299 bind(RELOAD_SUBSTR);
7300 if (ae == StrIntrinsicNode::UL) {
7301 pmovzxbw(vec, Address(str2, 0));
7302 } else {
7303 movdqu(vec, Address(str2, 0));
7304 }
7305 negptr(cnt2); // Jumped here with negative cnt2, convert to positive
7306
7307 bind(RELOAD_STR);
7308 // We came here after the beginning of the substring was
7309 // matched but the rest of it was not so we need to search
7310 // again. Start from the next element after the previous match.
7311
7312 // cnt2 is number of substring reminding elements and
7313 // cnt1 is number of string reminding elements when cmp failed.
7314 // Restored cnt1 = cnt1 - cnt2 + int_cnt2
7315 subl(cnt1, cnt2);
7316 addl(cnt1, int_cnt2);
7317 movl(cnt2, int_cnt2); // Now restore cnt2
7318
7319 decrementl(cnt1); // Shift to next element
7320 cmpl(cnt1, cnt2);
7321 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
7322
7323 addptr(result, (1<<scale1));
7324
7325 } // (int_cnt2 > 8)
7326
7327 // Scan string for start of substr in 16-byte vectors
7328 bind(SCAN_TO_SUBSTR);
7329 pcmpestri(vec, Address(result, 0), mode);
7330 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
7331 subl(cnt1, stride);
7332 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
7333 cmpl(cnt1, cnt2);
7334 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
7335 addptr(result, 16);
7336 jmpb(SCAN_TO_SUBSTR);
7337
7338 // Found a potential substr
7339 bind(FOUND_CANDIDATE);
7340 // Matched whole vector if first element matched (tmp(rcx) == 0).
7341 if (int_cnt2 == stride) {
7342 jccb(Assembler::overflow, RET_FOUND); // OF == 1
7343 } else { // int_cnt2 > 8
7344 jccb(Assembler::overflow, FOUND_SUBSTR);
7345 }
7346 // After pcmpestri tmp(rcx) contains matched element index
7347 // Compute start addr of substr
7348 lea(result, Address(result, tmp, scale1));
7349
7350 // Make sure string is still long enough
7351 subl(cnt1, tmp);
7352 cmpl(cnt1, cnt2);
7353 if (int_cnt2 == stride) {
7354 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
7355 } else { // int_cnt2 > 8
7356 jccb(Assembler::greaterEqual, MATCH_SUBSTR_HEAD);
7357 }
7358 // Left less then substring.
7359
7360 bind(RET_NOT_FOUND);
7361 movl(result, -1);
7362 jmpb(EXIT);
7363
7364 if (int_cnt2 > stride) {
7365 // This code is optimized for the case when whole substring
7366 // is matched if its head is matched.
7367 bind(MATCH_SUBSTR_HEAD);
7368 pcmpestri(vec, Address(result, 0), mode);
7369 // Reload only string if does not match
7370 jccb(Assembler::noOverflow, RELOAD_STR); // OF == 0
7371
7372 Label CONT_SCAN_SUBSTR;
7373 // Compare the rest of substring (> 8 chars).
7374 bind(FOUND_SUBSTR);
7375 // First 8 chars are already matched.
7376 negptr(cnt2);
7377 addptr(cnt2, stride);
7378
7379 bind(SCAN_SUBSTR);
7380 subl(cnt1, stride);
7381 cmpl(cnt2, -stride); // Do not read beyond substring
7382 jccb(Assembler::lessEqual, CONT_SCAN_SUBSTR);
7383 // Back-up strings to avoid reading beyond substring:
7384 // cnt1 = cnt1 - cnt2 + 8
7385 addl(cnt1, cnt2); // cnt2 is negative
7386 addl(cnt1, stride);
7387 movl(cnt2, stride); negptr(cnt2);
7388 bind(CONT_SCAN_SUBSTR);
7389 if (int_cnt2 < (int)G) {
7390 int tail_off1 = int_cnt2<<scale1;
7391 int tail_off2 = int_cnt2<<scale2;
7392 if (ae == StrIntrinsicNode::UL) {
7393 pmovzxbw(vec, Address(str2, cnt2, scale2, tail_off2));
7394 } else {
7395 movdqu(vec, Address(str2, cnt2, scale2, tail_off2));
7396 }
7397 pcmpestri(vec, Address(result, cnt2, scale1, tail_off1), mode);
7398 } else {
7399 // calculate index in register to avoid integer overflow (int_cnt2*2)
7400 movl(tmp, int_cnt2);
7401 addptr(tmp, cnt2);
7402 if (ae == StrIntrinsicNode::UL) {
7403 pmovzxbw(vec, Address(str2, tmp, scale2, 0));
7404 } else {
7405 movdqu(vec, Address(str2, tmp, scale2, 0));
7406 }
7407 pcmpestri(vec, Address(result, tmp, scale1, 0), mode);
7408 }
7409 // Need to reload strings pointers if not matched whole vector
7410 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
7411 addptr(cnt2, stride);
7412 jcc(Assembler::negative, SCAN_SUBSTR);
7413 // Fall through if found full substring
7414
7415 } // (int_cnt2 > 8)
7416
7417 bind(RET_FOUND);
7418 // Found result if we matched full small substring.
7419 // Compute substr offset
7420 subptr(result, str1);
7421 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
7422 shrl(result, 1); // index
7423 }
7424 bind(EXIT);
7425
7426 } // string_indexofC8
7427
7428 // Small strings are loaded through stack if they cross page boundary.
7429 void MacroAssembler::string_indexof(Register str1, Register str2,
7430 Register cnt1, Register cnt2,
7431 int int_cnt2, Register result,
7432 XMMRegister vec, Register tmp,
7433 int ae) {
7434 ShortBranchVerifier sbv(this);
7435 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
7436 assert(UseSSE >= 4, "SSE4 must be enabled for SSE4.2 intrinsics to be available");
7437 assert(ae != StrIntrinsicNode::LU, "Invalid encoding");
7438
7439 //
7440 // int_cnt2 is length of small (< 8 chars) constant substring
7441 // or (-1) for non constant substring in which case its length
7442 // is in cnt2 register.
7443 //
7444 // Note, inline_string_indexOf() generates checks:
7445 // if (substr.count > string.count) return -1;
7446 // if (substr.count == 0) return 0;
7447 //
7448 int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8
7449 assert(int_cnt2 == -1 || (0 < int_cnt2 && int_cnt2 < stride), "should be != 0");
7450 // This method uses the pcmpestri instruction with bound registers
7451 // inputs:
7452 // xmm - substring
7453 // rax - substring length (elements count)
7454 // mem - scanned string
7455 // rdx - string length (elements count)
7456 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
7457 // 0xc - mode: 1100 (substring search) + 00 (unsigned bytes)
7458 // outputs:
7459 // rcx - matched index in string
7460 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
7461 int mode = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts
7462 Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2;
7463 Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1;
7464
7465 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, ADJUST_STR,
7466 RET_FOUND, RET_NOT_FOUND, CLEANUP, FOUND_SUBSTR,
7467 FOUND_CANDIDATE;
7468
7469 { //========================================================
7470 // We don't know where these strings are located
7471 // and we can't read beyond them. Load them through stack.
7472 Label BIG_STRINGS, CHECK_STR, COPY_SUBSTR, COPY_STR;
7473
7474 movptr(tmp, rsp); // save old SP
7475
7476 if (int_cnt2 > 0) { // small (< 8 chars) constant substring
7477 if (int_cnt2 == (1>>scale2)) { // One byte
7478 assert((ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL), "Only possible for latin1 encoding");
7479 load_unsigned_byte(result, Address(str2, 0));
7480 movdl(vec, result); // move 32 bits
7481 } else if (ae == StrIntrinsicNode::LL && int_cnt2 == 3) { // Three bytes
7482 // Not enough header space in 32-bit VM: 12+3 = 15.
7483 movl(result, Address(str2, -1));
7484 shrl(result, 8);
7485 movdl(vec, result); // move 32 bits
7486 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (2>>scale2)) { // One char
7487 load_unsigned_short(result, Address(str2, 0));
7488 movdl(vec, result); // move 32 bits
7489 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (4>>scale2)) { // Two chars
7490 movdl(vec, Address(str2, 0)); // move 32 bits
7491 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (8>>scale2)) { // Four chars
7492 movq(vec, Address(str2, 0)); // move 64 bits
7493 } else { // cnt2 = { 3, 5, 6, 7 } || (ae == StrIntrinsicNode::UL && cnt2 ={2, ..., 7})
7494 // Array header size is 12 bytes in 32-bit VM
7495 // + 6 bytes for 3 chars == 18 bytes,
7496 // enough space to load vec and shift.
7497 assert(HeapWordSize*TypeArrayKlass::header_size() >= 12,"sanity");
7498 if (ae == StrIntrinsicNode::UL) {
7499 int tail_off = int_cnt2-8;
7500 pmovzxbw(vec, Address(str2, tail_off));
7501 psrldq(vec, -2*tail_off);
7502 }
7503 else {
7504 int tail_off = int_cnt2*(1<<scale2);
7505 movdqu(vec, Address(str2, tail_off-16));
7506 psrldq(vec, 16-tail_off);
7507 }
7508 }
7509 } else { // not constant substring
7510 cmpl(cnt2, stride);
7511 jccb(Assembler::aboveEqual, BIG_STRINGS); // Both strings are big enough
7512
7513 // We can read beyond string if srt+16 does not cross page boundary
7514 // since heaps are aligned and mapped by pages.
7515 assert(os::vm_page_size() < (int)G, "default page should be small");
7516 movl(result, str2); // We need only low 32 bits
7517 andl(result, (os::vm_page_size()-1));
7518 cmpl(result, (os::vm_page_size()-16));
7519 jccb(Assembler::belowEqual, CHECK_STR);
7520
7521 // Move small strings to stack to allow load 16 bytes into vec.
7522 subptr(rsp, 16);
7523 int stk_offset = wordSize-(1<<scale2);
7524 push(cnt2);
7525
7526 bind(COPY_SUBSTR);
7527 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL) {
7528 load_unsigned_byte(result, Address(str2, cnt2, scale2, -1));
7529 movb(Address(rsp, cnt2, scale2, stk_offset), result);
7530 } else if (ae == StrIntrinsicNode::UU) {
7531 load_unsigned_short(result, Address(str2, cnt2, scale2, -2));
7532 movw(Address(rsp, cnt2, scale2, stk_offset), result);
7533 }
7534 decrement(cnt2);
7535 jccb(Assembler::notZero, COPY_SUBSTR);
7536
7537 pop(cnt2);
7538 movptr(str2, rsp); // New substring address
7539 } // non constant
7540
7541 bind(CHECK_STR);
7542 cmpl(cnt1, stride);
7543 jccb(Assembler::aboveEqual, BIG_STRINGS);
7544
7545 // Check cross page boundary.
7546 movl(result, str1); // We need only low 32 bits
7547 andl(result, (os::vm_page_size()-1));
7548 cmpl(result, (os::vm_page_size()-16));
7549 jccb(Assembler::belowEqual, BIG_STRINGS);
7550
7551 subptr(rsp, 16);
7552 int stk_offset = -(1<<scale1);
7553 if (int_cnt2 < 0) { // not constant
7554 push(cnt2);
7555 stk_offset += wordSize;
7556 }
7557 movl(cnt2, cnt1);
7558
7559 bind(COPY_STR);
7560 if (ae == StrIntrinsicNode::LL) {
7561 load_unsigned_byte(result, Address(str1, cnt2, scale1, -1));
7562 movb(Address(rsp, cnt2, scale1, stk_offset), result);
7563 } else {
7564 load_unsigned_short(result, Address(str1, cnt2, scale1, -2));
7565 movw(Address(rsp, cnt2, scale1, stk_offset), result);
7566 }
7567 decrement(cnt2);
7568 jccb(Assembler::notZero, COPY_STR);
7569
7570 if (int_cnt2 < 0) { // not constant
7571 pop(cnt2);
7572 }
7573 movptr(str1, rsp); // New string address
7574
7575 bind(BIG_STRINGS);
7576 // Load substring.
7577 if (int_cnt2 < 0) { // -1
7578 if (ae == StrIntrinsicNode::UL) {
7579 pmovzxbw(vec, Address(str2, 0));
7580 } else {
7581 movdqu(vec, Address(str2, 0));
7582 }
7583 push(cnt2); // substr count
7584 push(str2); // substr addr
7585 push(str1); // string addr
7586 } else {
7587 // Small (< 8 chars) constant substrings are loaded already.
7588 movl(cnt2, int_cnt2);
7589 }
7590 push(tmp); // original SP
7591
7592 } // Finished loading
7593
7594 //========================================================
7595 // Start search
7596 //
7597
7598 movptr(result, str1); // string addr
7599
7600 if (int_cnt2 < 0) { // Only for non constant substring
7601 jmpb(SCAN_TO_SUBSTR);
7602
7603 // SP saved at sp+0
7604 // String saved at sp+1*wordSize
7605 // Substr saved at sp+2*wordSize
7606 // Substr count saved at sp+3*wordSize
7607
7608 // Reload substr for rescan, this code
7609 // is executed only for large substrings (> 8 chars)
7610 bind(RELOAD_SUBSTR);
7611 movptr(str2, Address(rsp, 2*wordSize));
7612 movl(cnt2, Address(rsp, 3*wordSize));
7613 if (ae == StrIntrinsicNode::UL) {
7614 pmovzxbw(vec, Address(str2, 0));
7615 } else {
7616 movdqu(vec, Address(str2, 0));
7617 }
7618 // We came here after the beginning of the substring was
7619 // matched but the rest of it was not so we need to search
7620 // again. Start from the next element after the previous match.
7621 subptr(str1, result); // Restore counter
7622 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
7623 shrl(str1, 1);
7624 }
7625 addl(cnt1, str1);
7626 decrementl(cnt1); // Shift to next element
7627 cmpl(cnt1, cnt2);
7628 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
7629
7630 addptr(result, (1<<scale1));
7631 } // non constant
7632
7633 // Scan string for start of substr in 16-byte vectors
7634 bind(SCAN_TO_SUBSTR);
7635 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
7636 pcmpestri(vec, Address(result, 0), mode);
7637 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
7638 subl(cnt1, stride);
7639 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
7640 cmpl(cnt1, cnt2);
7641 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
7642 addptr(result, 16);
7643
7644 bind(ADJUST_STR);
7645 cmpl(cnt1, stride); // Do not read beyond string
7646 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
7647 // Back-up string to avoid reading beyond string.
7648 lea(result, Address(result, cnt1, scale1, -16));
7649 movl(cnt1, stride);
7650 jmpb(SCAN_TO_SUBSTR);
7651
7652 // Found a potential substr
7653 bind(FOUND_CANDIDATE);
7654 // After pcmpestri tmp(rcx) contains matched element index
7655
7656 // Make sure string is still long enough
7657 subl(cnt1, tmp);
7658 cmpl(cnt1, cnt2);
7659 jccb(Assembler::greaterEqual, FOUND_SUBSTR);
7660 // Left less then substring.
7661
7662 bind(RET_NOT_FOUND);
7663 movl(result, -1);
7664 jmpb(CLEANUP);
7665
7666 bind(FOUND_SUBSTR);
7667 // Compute start addr of substr
7668 lea(result, Address(result, tmp, scale1));
7669 if (int_cnt2 > 0) { // Constant substring
7670 // Repeat search for small substring (< 8 chars)
7671 // from new point without reloading substring.
7672 // Have to check that we don't read beyond string.
7673 cmpl(tmp, stride-int_cnt2);
7674 jccb(Assembler::greater, ADJUST_STR);
7675 // Fall through if matched whole substring.
7676 } else { // non constant
7677 assert(int_cnt2 == -1, "should be != 0");
7678
7679 addl(tmp, cnt2);
7680 // Found result if we matched whole substring.
7681 cmpl(tmp, stride);
7682 jccb(Assembler::lessEqual, RET_FOUND);
7683
7684 // Repeat search for small substring (<= 8 chars)
7685 // from new point 'str1' without reloading substring.
7686 cmpl(cnt2, stride);
7687 // Have to check that we don't read beyond string.
7688 jccb(Assembler::lessEqual, ADJUST_STR);
7689
7690 Label CHECK_NEXT, CONT_SCAN_SUBSTR, RET_FOUND_LONG;
7691 // Compare the rest of substring (> 8 chars).
7692 movptr(str1, result);
7693
7694 cmpl(tmp, cnt2);
7695 // First 8 chars are already matched.
7696 jccb(Assembler::equal, CHECK_NEXT);
7697
7698 bind(SCAN_SUBSTR);
7699 pcmpestri(vec, Address(str1, 0), mode);
7700 // Need to reload strings pointers if not matched whole vector
7701 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
7702
7703 bind(CHECK_NEXT);
7704 subl(cnt2, stride);
7705 jccb(Assembler::lessEqual, RET_FOUND_LONG); // Found full substring
7706 addptr(str1, 16);
7707 if (ae == StrIntrinsicNode::UL) {
7708 addptr(str2, 8);
7709 } else {
7710 addptr(str2, 16);
7711 }
7712 subl(cnt1, stride);
7713 cmpl(cnt2, stride); // Do not read beyond substring
7714 jccb(Assembler::greaterEqual, CONT_SCAN_SUBSTR);
7715 // Back-up strings to avoid reading beyond substring.
7716
7717 if (ae == StrIntrinsicNode::UL) {
7718 lea(str2, Address(str2, cnt2, scale2, -8));
7719 lea(str1, Address(str1, cnt2, scale1, -16));
7720 } else {
7721 lea(str2, Address(str2, cnt2, scale2, -16));
7722 lea(str1, Address(str1, cnt2, scale1, -16));
7723 }
7724 subl(cnt1, cnt2);
7725 movl(cnt2, stride);
7726 addl(cnt1, stride);
7727 bind(CONT_SCAN_SUBSTR);
7728 if (ae == StrIntrinsicNode::UL) {
7729 pmovzxbw(vec, Address(str2, 0));
7730 } else {
7731 movdqu(vec, Address(str2, 0));
7732 }
7733 jmpb(SCAN_SUBSTR);
7734
7735 bind(RET_FOUND_LONG);
7736 movptr(str1, Address(rsp, wordSize));
7737 } // non constant
7738
7739 bind(RET_FOUND);
7740 // Compute substr offset
7741 subptr(result, str1);
7742 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
7743 shrl(result, 1); // index
7744 }
7745 bind(CLEANUP);
7746 pop(rsp); // restore SP
7747
7748 } // string_indexof
7749
7750 void MacroAssembler::string_indexof_char(Register str1, Register cnt1, Register ch, Register result,
7751 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp) {
7752 ShortBranchVerifier sbv(this);
7753 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
7754 assert(UseSSE >= 4, "SSE4 must be enabled for SSE4.2 intrinsics to be available");
7755
7756 int stride = 8;
7757
7758 Label FOUND_CHAR, SCAN_TO_CHAR, SCAN_TO_CHAR_LOOP,
7759 SCAN_TO_8_CHAR, SCAN_TO_8_CHAR_LOOP, SCAN_TO_16_CHAR_LOOP,
7760 RET_NOT_FOUND, SCAN_TO_8_CHAR_INIT,
7761 FOUND_SEQ_CHAR, DONE_LABEL;
7762
7763 movptr(result, str1);
7764 if (UseAVX >= 2) {
7765 cmpl(cnt1, stride);
7766 jccb(Assembler::less, SCAN_TO_CHAR_LOOP);
7767 cmpl(cnt1, 2*stride);
7768 jccb(Assembler::less, SCAN_TO_8_CHAR_INIT);
7769 movdl(vec1, ch);
7770 vpbroadcastw(vec1, vec1);
7771 vpxor(vec2, vec2);
7772 movl(tmp, cnt1);
7773 andl(tmp, 0xFFFFFFF0); //vector count (in chars)
7774 andl(cnt1,0x0000000F); //tail count (in chars)
7775
7776 bind(SCAN_TO_16_CHAR_LOOP);
7777 vmovdqu(vec3, Address(result, 0));
7778 vpcmpeqw(vec3, vec3, vec1, 1);
7779 vptest(vec2, vec3);
7780 jcc(Assembler::carryClear, FOUND_CHAR);
7781 addptr(result, 32);
7782 subl(tmp, 2*stride);
7783 jccb(Assembler::notZero, SCAN_TO_16_CHAR_LOOP);
7784 jmp(SCAN_TO_8_CHAR);
7785 bind(SCAN_TO_8_CHAR_INIT);
7786 movdl(vec1, ch);
7787 pshuflw(vec1, vec1, 0x00);
7788 pshufd(vec1, vec1, 0);
7789 pxor(vec2, vec2);
7790 }
7791 bind(SCAN_TO_8_CHAR);
7792 cmpl(cnt1, stride);
7793 if (UseAVX >= 2) {
7794 jccb(Assembler::less, SCAN_TO_CHAR);
7795 } else {
7796 jccb(Assembler::less, SCAN_TO_CHAR_LOOP);
7797 movdl(vec1, ch);
7798 pshuflw(vec1, vec1, 0x00);
7799 pshufd(vec1, vec1, 0);
7800 pxor(vec2, vec2);
7801 }
7802 movl(tmp, cnt1);
7803 andl(tmp, 0xFFFFFFF8); //vector count (in chars)
7804 andl(cnt1,0x00000007); //tail count (in chars)
7805
7806 bind(SCAN_TO_8_CHAR_LOOP);
7807 movdqu(vec3, Address(result, 0));
7808 pcmpeqw(vec3, vec1);
7809 ptest(vec2, vec3);
7810 jcc(Assembler::carryClear, FOUND_CHAR);
7811 addptr(result, 16);
7812 subl(tmp, stride);
7813 jccb(Assembler::notZero, SCAN_TO_8_CHAR_LOOP);
7814 bind(SCAN_TO_CHAR);
7815 testl(cnt1, cnt1);
7816 jcc(Assembler::zero, RET_NOT_FOUND);
7817 bind(SCAN_TO_CHAR_LOOP);
7818 load_unsigned_short(tmp, Address(result, 0));
7819 cmpl(ch, tmp);
7820 jccb(Assembler::equal, FOUND_SEQ_CHAR);
7821 addptr(result, 2);
7822 subl(cnt1, 1);
7823 jccb(Assembler::zero, RET_NOT_FOUND);
7824 jmp(SCAN_TO_CHAR_LOOP);
7825
7826 bind(RET_NOT_FOUND);
7827 movl(result, -1);
7828 jmpb(DONE_LABEL);
7829
7830 bind(FOUND_CHAR);
7831 if (UseAVX >= 2) {
7832 vpmovmskb(tmp, vec3);
7833 } else {
7834 pmovmskb(tmp, vec3);
7835 }
7836 bsfl(ch, tmp);
7837 addl(result, ch);
7838
7839 bind(FOUND_SEQ_CHAR);
7840 subptr(result, str1);
7841 shrl(result, 1);
7842
7843 bind(DONE_LABEL);
7844 } // string_indexof_char
7845
7846 // helper function for string_compare
7847 void MacroAssembler::load_next_elements(Register elem1, Register elem2, Register str1, Register str2,
7848 Address::ScaleFactor scale, Address::ScaleFactor scale1,
7849 Address::ScaleFactor scale2, Register index, int ae) {
7850 if (ae == StrIntrinsicNode::LL) {
7851 load_unsigned_byte(elem1, Address(str1, index, scale, 0));
7852 load_unsigned_byte(elem2, Address(str2, index, scale, 0));
7853 } else if (ae == StrIntrinsicNode::UU) {
7854 load_unsigned_short(elem1, Address(str1, index, scale, 0));
7855 load_unsigned_short(elem2, Address(str2, index, scale, 0));
7856 } else {
7857 load_unsigned_byte(elem1, Address(str1, index, scale1, 0));
7858 load_unsigned_short(elem2, Address(str2, index, scale2, 0));
7859 }
7860 }
7861
7862 // Compare strings, used for char[] and byte[].
7863 void MacroAssembler::string_compare(Register str1, Register str2,
7864 Register cnt1, Register cnt2, Register result,
7865 XMMRegister vec1, int ae) {
7866 ShortBranchVerifier sbv(this);
7867 Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL;
7868 Label COMPARE_WIDE_VECTORS_LOOP_FAILED; // used only _LP64 && AVX3
7869 int stride, stride2, adr_stride, adr_stride1, adr_stride2;
7870 int stride2x2 = 0x40;
7871 Address::ScaleFactor scale = Address::no_scale;
7872 Address::ScaleFactor scale1 = Address::no_scale;
7873 Address::ScaleFactor scale2 = Address::no_scale;
7874
7875 if (ae != StrIntrinsicNode::LL) {
7876 stride2x2 = 0x20;
7877 }
7878
7879 if (ae == StrIntrinsicNode::LU || ae == StrIntrinsicNode::UL) {
7880 shrl(cnt2, 1);
7881 }
7882 // Compute the minimum of the string lengths and the
7883 // difference of the string lengths (stack).
7884 // Do the conditional move stuff
7885 movl(result, cnt1);
7886 subl(cnt1, cnt2);
7887 push(cnt1);
7888 cmov32(Assembler::lessEqual, cnt2, result); // cnt2 = min(cnt1, cnt2)
7889
7890 // Is the minimum length zero?
7891 testl(cnt2, cnt2);
7892 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
7893 if (ae == StrIntrinsicNode::LL) {
7894 // Load first bytes
7895 load_unsigned_byte(result, Address(str1, 0)); // result = str1[0]
7896 load_unsigned_byte(cnt1, Address(str2, 0)); // cnt1 = str2[0]
7897 } else if (ae == StrIntrinsicNode::UU) {
7898 // Load first characters
7899 load_unsigned_short(result, Address(str1, 0));
7900 load_unsigned_short(cnt1, Address(str2, 0));
7901 } else {
7902 load_unsigned_byte(result, Address(str1, 0));
7903 load_unsigned_short(cnt1, Address(str2, 0));
7904 }
7905 subl(result, cnt1);
7906 jcc(Assembler::notZero, POP_LABEL);
7907
7908 if (ae == StrIntrinsicNode::UU) {
7909 // Divide length by 2 to get number of chars
7910 shrl(cnt2, 1);
7911 }
7912 cmpl(cnt2, 1);
7913 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
7914
7915 // Check if the strings start at the same location and setup scale and stride
7916 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7917 cmpptr(str1, str2);
7918 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
7919 if (ae == StrIntrinsicNode::LL) {
7920 scale = Address::times_1;
7921 stride = 16;
7922 } else {
7923 scale = Address::times_2;
7924 stride = 8;
7925 }
7926 } else {
7927 scale1 = Address::times_1;
7928 scale2 = Address::times_2;
7929 // scale not used
7930 stride = 8;
7931 }
7932
7933 if (UseAVX >= 2 && UseSSE42Intrinsics) {
7934 assert(UseSSE >= 4, "SSE4 must be enabled for SSE4.2 intrinsics to be available");
7935 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_WIDE_TAIL, COMPARE_SMALL_STR;
7936 Label COMPARE_WIDE_VECTORS_LOOP, COMPARE_16_CHARS, COMPARE_INDEX_CHAR;
7937 Label COMPARE_WIDE_VECTORS_LOOP_AVX2;
7938 Label COMPARE_TAIL_LONG;
7939 Label COMPARE_WIDE_VECTORS_LOOP_AVX3; // used only _LP64 && AVX3
7940
7941 int pcmpmask = 0x19;
7942 if (ae == StrIntrinsicNode::LL) {
7943 pcmpmask &= ~0x01;
7944 }
7945
7946 // Setup to compare 16-chars (32-bytes) vectors,
7947 // start from first character again because it has aligned address.
7948 if (ae == StrIntrinsicNode::LL) {
7949 stride2 = 32;
7950 } else {
7951 stride2 = 16;
7952 }
7953 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7954 adr_stride = stride << scale;
7955 } else {
7956 adr_stride1 = 8; //stride << scale1;
7957 adr_stride2 = 16; //stride << scale2;
7958 }
7959
7960 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
7961 // rax and rdx are used by pcmpestri as elements counters
7962 movl(result, cnt2);
7963 andl(cnt2, ~(stride2-1)); // cnt2 holds the vector count
7964 jcc(Assembler::zero, COMPARE_TAIL_LONG);
7965
7966 // fast path : compare first 2 8-char vectors.
7967 bind(COMPARE_16_CHARS);
7968 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7969 movdqu(vec1, Address(str1, 0));
7970 } else {
7971 pmovzxbw(vec1, Address(str1, 0));
7972 }
7973 pcmpestri(vec1, Address(str2, 0), pcmpmask);
7974 jccb(Assembler::below, COMPARE_INDEX_CHAR);
7975
7976 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7977 movdqu(vec1, Address(str1, adr_stride));
7978 pcmpestri(vec1, Address(str2, adr_stride), pcmpmask);
7979 } else {
7980 pmovzxbw(vec1, Address(str1, adr_stride1));
7981 pcmpestri(vec1, Address(str2, adr_stride2), pcmpmask);
7982 }
7983 jccb(Assembler::aboveEqual, COMPARE_WIDE_VECTORS);
7984 addl(cnt1, stride);
7985
7986 // Compare the characters at index in cnt1
7987 bind(COMPARE_INDEX_CHAR); // cnt1 has the offset of the mismatching character
7988 load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae);
7989 subl(result, cnt2);
7990 jmp(POP_LABEL);
7991
7992 // Setup the registers to start vector comparison loop
7993 bind(COMPARE_WIDE_VECTORS);
7994 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7995 lea(str1, Address(str1, result, scale));
7996 lea(str2, Address(str2, result, scale));
7997 } else {
7998 lea(str1, Address(str1, result, scale1));
7999 lea(str2, Address(str2, result, scale2));
8000 }
8001 subl(result, stride2);
8002 subl(cnt2, stride2);
8003 jcc(Assembler::zero, COMPARE_WIDE_TAIL);
8004 negptr(result);
8005
8006 // In a loop, compare 16-chars (32-bytes) at once using (vpxor+vptest)
8007 bind(COMPARE_WIDE_VECTORS_LOOP);
8008
8009 #ifdef _LP64
8010 if (VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop
8011 cmpl(cnt2, stride2x2);
8012 jccb(Assembler::below, COMPARE_WIDE_VECTORS_LOOP_AVX2);
8013 testl(cnt2, stride2x2-1); // cnt2 holds the vector count
8014 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX2); // means we cannot subtract by 0x40
8015
8016 bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop
8017 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
8018 evmovdquq(vec1, Address(str1, result, scale), Assembler::AVX_512bit);
8019 evpcmpeqb(k7, vec1, Address(str2, result, scale), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0
8020 } else {
8021 vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_512bit);
8022 evpcmpeqb(k7, vec1, Address(str2, result, scale2), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0
8023 }
8024 kortestql(k7, k7);
8025 jcc(Assembler::aboveEqual, COMPARE_WIDE_VECTORS_LOOP_FAILED); // miscompare
8026 addptr(result, stride2x2); // update since we already compared at this addr
8027 subl(cnt2, stride2x2); // and sub the size too
8028 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX3);
8029
8030 vpxor(vec1, vec1);
8031 jmpb(COMPARE_WIDE_TAIL);
8032 }//if (VM_Version::supports_avx512vlbw())
8033 #endif // _LP64
8034
8035
8036 bind(COMPARE_WIDE_VECTORS_LOOP_AVX2);
8037 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
8038 vmovdqu(vec1, Address(str1, result, scale));
8039 vpxor(vec1, Address(str2, result, scale));
8040 } else {
8041 vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_256bit);
8042 vpxor(vec1, Address(str2, result, scale2));
8043 }
8044 vptest(vec1, vec1);
8045 jcc(Assembler::notZero, VECTOR_NOT_EQUAL);
8046 addptr(result, stride2);
8047 subl(cnt2, stride2);
8048 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP);
8049 // clean upper bits of YMM registers
8050 vpxor(vec1, vec1);
8051
8052 // compare wide vectors tail
8053 bind(COMPARE_WIDE_TAIL);
8054 testptr(result, result);
8055 jccb(Assembler::zero, LENGTH_DIFF_LABEL);
8056
8057 movl(result, stride2);
8058 movl(cnt2, result);
8059 negptr(result);
8060 jmp(COMPARE_WIDE_VECTORS_LOOP_AVX2);
8061
8062 // Identifies the mismatching (higher or lower)16-bytes in the 32-byte vectors.
8063 bind(VECTOR_NOT_EQUAL);
8064 // clean upper bits of YMM registers
8065 vpxor(vec1, vec1);
8066 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
8067 lea(str1, Address(str1, result, scale));
8068 lea(str2, Address(str2, result, scale));
8069 } else {
8070 lea(str1, Address(str1, result, scale1));
8071 lea(str2, Address(str2, result, scale2));
8072 }
8073 jmp(COMPARE_16_CHARS);
8074
8075 // Compare tail chars, length between 1 to 15 chars
8076 bind(COMPARE_TAIL_LONG);
8077 movl(cnt2, result);
8078 cmpl(cnt2, stride);
8079 jccb(Assembler::less, COMPARE_SMALL_STR);
8080
8081 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
8082 movdqu(vec1, Address(str1, 0));
8083 } else {
8084 pmovzxbw(vec1, Address(str1, 0));
8085 }
8086 pcmpestri(vec1, Address(str2, 0), pcmpmask);
8087 jcc(Assembler::below, COMPARE_INDEX_CHAR);
8088 subptr(cnt2, stride);
8089 jccb(Assembler::zero, LENGTH_DIFF_LABEL);
8090 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
8091 lea(str1, Address(str1, result, scale));
8092 lea(str2, Address(str2, result, scale));
8093 } else {
8094 lea(str1, Address(str1, result, scale1));
8095 lea(str2, Address(str2, result, scale2));
8096 }
8097 negptr(cnt2);
8098 jmpb(WHILE_HEAD_LABEL);
8099
8100 bind(COMPARE_SMALL_STR);
8101 } else if (UseSSE42Intrinsics) {
8102 assert(UseSSE >= 4, "SSE4 must be enabled for SSE4.2 intrinsics to be available");
8103 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL;
8104 int pcmpmask = 0x19;
8105 // Setup to compare 8-char (16-byte) vectors,
8106 // start from first character again because it has aligned address.
8107 movl(result, cnt2);
8108 andl(cnt2, ~(stride - 1)); // cnt2 holds the vector count
8109 if (ae == StrIntrinsicNode::LL) {
8110 pcmpmask &= ~0x01;
8111 }
8112 jccb(Assembler::zero, COMPARE_TAIL);
8113 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
8114 lea(str1, Address(str1, result, scale));
8115 lea(str2, Address(str2, result, scale));
8116 } else {
8117 lea(str1, Address(str1, result, scale1));
8118 lea(str2, Address(str2, result, scale2));
8119 }
8120 negptr(result);
8121
8122 // pcmpestri
8123 // inputs:
8124 // vec1- substring
8125 // rax - negative string length (elements count)
8126 // mem - scanned string
8127 // rdx - string length (elements count)
8128 // pcmpmask - cmp mode: 11000 (string compare with negated result)
8129 // + 00 (unsigned bytes) or + 01 (unsigned shorts)
8130 // outputs:
8131 // rcx - first mismatched element index
8132 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
8133
8134 bind(COMPARE_WIDE_VECTORS);
8135 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
8136 movdqu(vec1, Address(str1, result, scale));
8137 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
8138 } else {
8139 pmovzxbw(vec1, Address(str1, result, scale1));
8140 pcmpestri(vec1, Address(str2, result, scale2), pcmpmask);
8141 }
8142 // After pcmpestri cnt1(rcx) contains mismatched element index
8143
8144 jccb(Assembler::below, VECTOR_NOT_EQUAL); // CF==1
8145 addptr(result, stride);
8146 subptr(cnt2, stride);
8147 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS);
8148
8149 // compare wide vectors tail
8150 testptr(result, result);
8151 jccb(Assembler::zero, LENGTH_DIFF_LABEL);
8152
8153 movl(cnt2, stride);
8154 movl(result, stride);
8155 negptr(result);
8156 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
8157 movdqu(vec1, Address(str1, result, scale));
8158 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
8159 } else {
8160 pmovzxbw(vec1, Address(str1, result, scale1));
8161 pcmpestri(vec1, Address(str2, result, scale2), pcmpmask);
8162 }
8163 jccb(Assembler::aboveEqual, LENGTH_DIFF_LABEL);
8164
8165 // Mismatched characters in the vectors
8166 bind(VECTOR_NOT_EQUAL);
8167 addptr(cnt1, result);
8168 load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae);
8169 subl(result, cnt2);
8170 jmpb(POP_LABEL);
8171
8172 bind(COMPARE_TAIL); // limit is zero
8173 movl(cnt2, result);
8174 // Fallthru to tail compare
8175 }
8176 // Shift str2 and str1 to the end of the arrays, negate min
8177 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
8178 lea(str1, Address(str1, cnt2, scale));
8179 lea(str2, Address(str2, cnt2, scale));
8180 } else {
8181 lea(str1, Address(str1, cnt2, scale1));
8182 lea(str2, Address(str2, cnt2, scale2));
8183 }
8184 decrementl(cnt2); // first character was compared already
8185 negptr(cnt2);
8186
8187 // Compare the rest of the elements
8188 bind(WHILE_HEAD_LABEL);
8189 load_next_elements(result, cnt1, str1, str2, scale, scale1, scale2, cnt2, ae);
8190 subl(result, cnt1);
8191 jccb(Assembler::notZero, POP_LABEL);
8192 increment(cnt2);
8193 jccb(Assembler::notZero, WHILE_HEAD_LABEL);
8194
8195 // Strings are equal up to min length. Return the length difference.
8196 bind(LENGTH_DIFF_LABEL);
8197 pop(result);
8198 if (ae == StrIntrinsicNode::UU) {
8199 // Divide diff by 2 to get number of chars
8200 sarl(result, 1);
8201 }
8202 jmpb(DONE_LABEL);
8203
8204 #ifdef _LP64
8205 if (VM_Version::supports_avx512vlbw()) {
8206
8207 bind(COMPARE_WIDE_VECTORS_LOOP_FAILED);
8208
8209 kmovql(cnt1, k7);
8210 notq(cnt1);
8211 bsfq(cnt2, cnt1);
8212 if (ae != StrIntrinsicNode::LL) {
8213 // Divide diff by 2 to get number of chars
8214 sarl(cnt2, 1);
8215 }
8216 addq(result, cnt2);
8217 if (ae == StrIntrinsicNode::LL) {
8218 load_unsigned_byte(cnt1, Address(str2, result));
8219 load_unsigned_byte(result, Address(str1, result));
8220 } else if (ae == StrIntrinsicNode::UU) {
8221 load_unsigned_short(cnt1, Address(str2, result, scale));
8222 load_unsigned_short(result, Address(str1, result, scale));
8223 } else {
8224 load_unsigned_short(cnt1, Address(str2, result, scale2));
8225 load_unsigned_byte(result, Address(str1, result, scale1));
8226 }
8227 subl(result, cnt1);
8228 jmpb(POP_LABEL);
8229 }//if (VM_Version::supports_avx512vlbw())
8230 #endif // _LP64
8231
8232 // Discard the stored length difference
8233 bind(POP_LABEL);
8234 pop(cnt1);
8235
8236 // That's it
8237 bind(DONE_LABEL);
8238 if(ae == StrIntrinsicNode::UL) {
8239 negl(result);
8240 }
8241
8242 }
8243
8244 // Search for Non-ASCII character (Negative byte value) in a byte array,
8245 // return true if it has any and false otherwise.
8246 void MacroAssembler::has_negatives(Register ary1, Register len,
8247 Register result, Register tmp1,
8248 XMMRegister vec1, XMMRegister vec2) {
8249
8250 // rsi: byte array
8251 // rcx: len
8252 // rax: result
8253 ShortBranchVerifier sbv(this);
8254 assert_different_registers(ary1, len, result, tmp1);
8255 assert_different_registers(vec1, vec2);
8256 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_CHAR, COMPARE_VECTORS, COMPARE_BYTE;
8257
8258 // len == 0
8259 testl(len, len);
8260 jcc(Assembler::zero, FALSE_LABEL);
8261
8262 movl(result, len); // copy
8263
8264 if (UseAVX >= 2 && UseSSE >= 2) {
8265 // With AVX2, use 32-byte vector compare
8266 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
8267
8268 // Compare 32-byte vectors
8269 andl(result, 0x0000001f); // tail count (in bytes)
8270 andl(len, 0xffffffe0); // vector count (in bytes)
8271 jccb(Assembler::zero, COMPARE_TAIL);
8272
8273 lea(ary1, Address(ary1, len, Address::times_1));
8274 negptr(len);
8275
8276 movl(tmp1, 0x80808080); // create mask to test for Unicode chars in vector
8277 movdl(vec2, tmp1);
8278 vpbroadcastd(vec2, vec2);
8279
8280 bind(COMPARE_WIDE_VECTORS);
8281 vmovdqu(vec1, Address(ary1, len, Address::times_1));
8282 vptest(vec1, vec2);
8283 jccb(Assembler::notZero, TRUE_LABEL);
8284 addptr(len, 32);
8285 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
8286
8287 testl(result, result);
8288 jccb(Assembler::zero, FALSE_LABEL);
8289
8290 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32));
8291 vptest(vec1, vec2);
8292 jccb(Assembler::notZero, TRUE_LABEL);
8293 jmpb(FALSE_LABEL);
8294
8295 bind(COMPARE_TAIL); // len is zero
8296 movl(len, result);
8297 // Fallthru to tail compare
8298 } else if (UseSSE42Intrinsics) {
8299 assert(UseSSE >= 4, "SSE4 must be for SSE4.2 intrinsics to be available");
8300 // With SSE4.2, use double quad vector compare
8301 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
8302
8303 // Compare 16-byte vectors
8304 andl(result, 0x0000000f); // tail count (in bytes)
8305 andl(len, 0xfffffff0); // vector count (in bytes)
8306 jccb(Assembler::zero, COMPARE_TAIL);
8307
8308 lea(ary1, Address(ary1, len, Address::times_1));
8309 negptr(len);
8310
8311 movl(tmp1, 0x80808080);
8312 movdl(vec2, tmp1);
8313 pshufd(vec2, vec2, 0);
8314
8315 bind(COMPARE_WIDE_VECTORS);
8316 movdqu(vec1, Address(ary1, len, Address::times_1));
8317 ptest(vec1, vec2);
8318 jccb(Assembler::notZero, TRUE_LABEL);
8319 addptr(len, 16);
8320 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
8321
8322 testl(result, result);
8323 jccb(Assembler::zero, FALSE_LABEL);
8324
8325 movdqu(vec1, Address(ary1, result, Address::times_1, -16));
8326 ptest(vec1, vec2);
8327 jccb(Assembler::notZero, TRUE_LABEL);
8328 jmpb(FALSE_LABEL);
8329
8330 bind(COMPARE_TAIL); // len is zero
8331 movl(len, result);
8332 // Fallthru to tail compare
8333 }
8334
8335 // Compare 4-byte vectors
8336 andl(len, 0xfffffffc); // vector count (in bytes)
8337 jccb(Assembler::zero, COMPARE_CHAR);
8338
8339 lea(ary1, Address(ary1, len, Address::times_1));
8340 negptr(len);
8341
8342 bind(COMPARE_VECTORS);
8343 movl(tmp1, Address(ary1, len, Address::times_1));
8344 andl(tmp1, 0x80808080);
8345 jccb(Assembler::notZero, TRUE_LABEL);
8346 addptr(len, 4);
8347 jcc(Assembler::notZero, COMPARE_VECTORS);
8348
8349 // Compare trailing char (final 2 bytes), if any
8350 bind(COMPARE_CHAR);
8351 testl(result, 0x2); // tail char
8352 jccb(Assembler::zero, COMPARE_BYTE);
8353 load_unsigned_short(tmp1, Address(ary1, 0));
8354 andl(tmp1, 0x00008080);
8355 jccb(Assembler::notZero, TRUE_LABEL);
8356 subptr(result, 2);
8357 lea(ary1, Address(ary1, 2));
8358
8359 bind(COMPARE_BYTE);
8360 testl(result, 0x1); // tail byte
8361 jccb(Assembler::zero, FALSE_LABEL);
8362 load_unsigned_byte(tmp1, Address(ary1, 0));
8363 andl(tmp1, 0x00000080);
8364 jccb(Assembler::notEqual, TRUE_LABEL);
8365 jmpb(FALSE_LABEL);
8366
8367 bind(TRUE_LABEL);
8368 movl(result, 1); // return true
8369 jmpb(DONE);
8370
8371 bind(FALSE_LABEL);
8372 xorl(result, result); // return false
8373
8374 // That's it
8375 bind(DONE);
8376 if (UseAVX >= 2 && UseSSE >= 2) {
8377 // clean upper bits of YMM registers
8378 vpxor(vec1, vec1);
8379 vpxor(vec2, vec2);
8380 }
8381 }
8382
8383 // Compare char[] or byte[] arrays aligned to 4 bytes or substrings.
8384 void MacroAssembler::arrays_equals(bool is_array_equ, Register ary1, Register ary2,
8385 Register limit, Register result, Register chr,
8386 XMMRegister vec1, XMMRegister vec2, bool is_char) {
8387 ShortBranchVerifier sbv(this);
8388 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR, COMPARE_BYTE;
8389
8390 int length_offset = arrayOopDesc::length_offset_in_bytes();
8391 int base_offset = arrayOopDesc::base_offset_in_bytes(is_char ? T_CHAR : T_BYTE);
8392
8393 if (is_array_equ) {
8394 // Check the input args
8395 cmpptr(ary1, ary2);
8396 jcc(Assembler::equal, TRUE_LABEL);
8397
8398 // Need additional checks for arrays_equals.
8399 testptr(ary1, ary1);
8400 jcc(Assembler::zero, FALSE_LABEL);
8401 testptr(ary2, ary2);
8402 jcc(Assembler::zero, FALSE_LABEL);
8403
8404 // Check the lengths
8405 movl(limit, Address(ary1, length_offset));
8406 cmpl(limit, Address(ary2, length_offset));
8407 jcc(Assembler::notEqual, FALSE_LABEL);
8408 }
8409
8410 // count == 0
8411 testl(limit, limit);
8412 jcc(Assembler::zero, TRUE_LABEL);
8413
8414 if (is_array_equ) {
8415 // Load array address
8416 lea(ary1, Address(ary1, base_offset));
8417 lea(ary2, Address(ary2, base_offset));
8418 }
8419
8420 if (is_array_equ && is_char) {
8421 // arrays_equals when used for char[].
8422 shll(limit, 1); // byte count != 0
8423 }
8424 movl(result, limit); // copy
8425
8426 if (UseAVX >= 2) {
8427 // With AVX2, use 32-byte vector compare
8428 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
8429
8430 // Compare 32-byte vectors
8431 andl(result, 0x0000001f); // tail count (in bytes)
8432 andl(limit, 0xffffffe0); // vector count (in bytes)
8433 jcc(Assembler::zero, COMPARE_TAIL);
8434
8435 lea(ary1, Address(ary1, limit, Address::times_1));
8436 lea(ary2, Address(ary2, limit, Address::times_1));
8437 negptr(limit);
8438
8439 bind(COMPARE_WIDE_VECTORS);
8440
8441 #ifdef _LP64
8442 if (VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop
8443 Label COMPARE_WIDE_VECTORS_LOOP_AVX2, COMPARE_WIDE_VECTORS_LOOP_AVX3;
8444
8445 cmpl(limit, -64);
8446 jccb(Assembler::greater, COMPARE_WIDE_VECTORS_LOOP_AVX2);
8447
8448 bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop
8449
8450 evmovdquq(vec1, Address(ary1, limit, Address::times_1), Assembler::AVX_512bit);
8451 evpcmpeqb(k7, vec1, Address(ary2, limit, Address::times_1), Assembler::AVX_512bit);
8452 kortestql(k7, k7);
8453 jcc(Assembler::aboveEqual, FALSE_LABEL); // miscompare
8454 addptr(limit, 64); // update since we already compared at this addr
8455 cmpl(limit, -64);
8456 jccb(Assembler::lessEqual, COMPARE_WIDE_VECTORS_LOOP_AVX3);
8457
8458 // At this point we may still need to compare -limit+result bytes.
8459 // We could execute the next two instruction and just continue via non-wide path:
8460 // cmpl(limit, 0);
8461 // jcc(Assembler::equal, COMPARE_TAIL); // true
8462 // But since we stopped at the points ary{1,2}+limit which are
8463 // not farther than 64 bytes from the ends of arrays ary{1,2}+result
8464 // (|limit| <= 32 and result < 32),
8465 // we may just compare the last 64 bytes.
8466 //
8467 addptr(result, -64); // it is safe, bc we just came from this area
8468 evmovdquq(vec1, Address(ary1, result, Address::times_1), Assembler::AVX_512bit);
8469 evpcmpeqb(k7, vec1, Address(ary2, result, Address::times_1), Assembler::AVX_512bit);
8470 kortestql(k7, k7);
8471 jcc(Assembler::aboveEqual, FALSE_LABEL); // miscompare
8472
8473 jmp(TRUE_LABEL);
8474
8475 bind(COMPARE_WIDE_VECTORS_LOOP_AVX2);
8476
8477 }//if (VM_Version::supports_avx512vlbw())
8478 #endif //_LP64
8479
8480 vmovdqu(vec1, Address(ary1, limit, Address::times_1));
8481 vmovdqu(vec2, Address(ary2, limit, Address::times_1));
8482 vpxor(vec1, vec2);
8483
8484 vptest(vec1, vec1);
8485 jccb(Assembler::notZero, FALSE_LABEL);
8486 addptr(limit, 32);
8487 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
8488
8489 testl(result, result);
8490 jccb(Assembler::zero, TRUE_LABEL);
8491
8492 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32));
8493 vmovdqu(vec2, Address(ary2, result, Address::times_1, -32));
8494 vpxor(vec1, vec2);
8495
8496 vptest(vec1, vec1);
8497 jccb(Assembler::notZero, FALSE_LABEL);
8498 jmpb(TRUE_LABEL);
8499
8500 bind(COMPARE_TAIL); // limit is zero
8501 movl(limit, result);
8502 // Fallthru to tail compare
8503 } else if (UseSSE42Intrinsics) {
8504 assert(UseSSE >= 4, "SSE4 must be enabled for SSE4.2 intrinsics to be available");
8505 // With SSE4.2, use double quad vector compare
8506 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
8507
8508 // Compare 16-byte vectors
8509 andl(result, 0x0000000f); // tail count (in bytes)
8510 andl(limit, 0xfffffff0); // vector count (in bytes)
8511 jccb(Assembler::zero, COMPARE_TAIL);
8512
8513 lea(ary1, Address(ary1, limit, Address::times_1));
8514 lea(ary2, Address(ary2, limit, Address::times_1));
8515 negptr(limit);
8516
8517 bind(COMPARE_WIDE_VECTORS);
8518 movdqu(vec1, Address(ary1, limit, Address::times_1));
8519 movdqu(vec2, Address(ary2, limit, Address::times_1));
8520 pxor(vec1, vec2);
8521
8522 ptest(vec1, vec1);
8523 jccb(Assembler::notZero, FALSE_LABEL);
8524 addptr(limit, 16);
8525 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
8526
8527 testl(result, result);
8528 jccb(Assembler::zero, TRUE_LABEL);
8529
8530 movdqu(vec1, Address(ary1, result, Address::times_1, -16));
8531 movdqu(vec2, Address(ary2, result, Address::times_1, -16));
8532 pxor(vec1, vec2);
8533
8534 ptest(vec1, vec1);
8535 jccb(Assembler::notZero, FALSE_LABEL);
8536 jmpb(TRUE_LABEL);
8537
8538 bind(COMPARE_TAIL); // limit is zero
8539 movl(limit, result);
8540 // Fallthru to tail compare
8541 }
8542
8543 // Compare 4-byte vectors
8544 andl(limit, 0xfffffffc); // vector count (in bytes)
8545 jccb(Assembler::zero, COMPARE_CHAR);
8546
8547 lea(ary1, Address(ary1, limit, Address::times_1));
8548 lea(ary2, Address(ary2, limit, Address::times_1));
8549 negptr(limit);
8550
8551 bind(COMPARE_VECTORS);
8552 movl(chr, Address(ary1, limit, Address::times_1));
8553 cmpl(chr, Address(ary2, limit, Address::times_1));
8554 jccb(Assembler::notEqual, FALSE_LABEL);
8555 addptr(limit, 4);
8556 jcc(Assembler::notZero, COMPARE_VECTORS);
8557
8558 // Compare trailing char (final 2 bytes), if any
8559 bind(COMPARE_CHAR);
8560 testl(result, 0x2); // tail char
8561 jccb(Assembler::zero, COMPARE_BYTE);
8562 load_unsigned_short(chr, Address(ary1, 0));
8563 load_unsigned_short(limit, Address(ary2, 0));
8564 cmpl(chr, limit);
8565 jccb(Assembler::notEqual, FALSE_LABEL);
8566
8567 if (is_array_equ && is_char) {
8568 bind(COMPARE_BYTE);
8569 } else {
8570 lea(ary1, Address(ary1, 2));
8571 lea(ary2, Address(ary2, 2));
8572
8573 bind(COMPARE_BYTE);
8574 testl(result, 0x1); // tail byte
8575 jccb(Assembler::zero, TRUE_LABEL);
8576 load_unsigned_byte(chr, Address(ary1, 0));
8577 load_unsigned_byte(limit, Address(ary2, 0));
8578 cmpl(chr, limit);
8579 jccb(Assembler::notEqual, FALSE_LABEL);
8580 }
8581 bind(TRUE_LABEL);
8582 movl(result, 1); // return true
8583 jmpb(DONE);
8584
8585 bind(FALSE_LABEL);
8586 xorl(result, result); // return false
8587
8588 // That's it
8589 bind(DONE);
8590 if (UseAVX >= 2) {
8591 // clean upper bits of YMM registers
8592 vpxor(vec1, vec1);
8593 vpxor(vec2, vec2);
8594 }
8595 }
8596
8597 #endif
8598
8599 void MacroAssembler::generate_fill(BasicType t, bool aligned,
8600 Register to, Register value, Register count,
8601 Register rtmp, XMMRegister xtmp) {
8602 ShortBranchVerifier sbv(this);
8603 assert_different_registers(to, value, count, rtmp);
8604 Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte;
8605 Label L_fill_2_bytes, L_fill_4_bytes;
8606
8607 int shift = -1;
8608 switch (t) {
8609 case T_BYTE:
8610 shift = 2;
8611 break;
8612 case T_SHORT:
8613 shift = 1;
8614 break;
8615 case T_INT:
8616 shift = 0;
8617 break;
8618 default: ShouldNotReachHere();
8619 }
8620
8621 if (t == T_BYTE) {
8622 andl(value, 0xff);
8623 movl(rtmp, value);
8624 shll(rtmp, 8);
8625 orl(value, rtmp);
8626 }
8627 if (t == T_SHORT) {
8628 andl(value, 0xffff);
8629 }
8630 if (t == T_BYTE || t == T_SHORT) {
8631 movl(rtmp, value);
8632 shll(rtmp, 16);
8633 orl(value, rtmp);
8634 }
8635
8636 cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element
8637 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
8638 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
8639 // align source address at 4 bytes address boundary
8640 if (t == T_BYTE) {
8641 // One byte misalignment happens only for byte arrays
8642 testptr(to, 1);
8643 jccb(Assembler::zero, L_skip_align1);
8644 movb(Address(to, 0), value);
8645 increment(to);
8646 decrement(count);
8647 BIND(L_skip_align1);
8648 }
8649 // Two bytes misalignment happens only for byte and short (char) arrays
8650 testptr(to, 2);
8651 jccb(Assembler::zero, L_skip_align2);
8652 movw(Address(to, 0), value);
8653 addptr(to, 2);
8654 subl(count, 1<<(shift-1));
8655 BIND(L_skip_align2);
8656 }
8657 if (UseSSE < 2) {
8658 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
8659 // Fill 32-byte chunks
8660 subl(count, 8 << shift);
8661 jcc(Assembler::less, L_check_fill_8_bytes);
8662 align(16);
8663
8664 BIND(L_fill_32_bytes_loop);
8665
8666 for (int i = 0; i < 32; i += 4) {
8667 movl(Address(to, i), value);
8668 }
8669
8670 addptr(to, 32);
8671 subl(count, 8 << shift);
8672 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
8673 BIND(L_check_fill_8_bytes);
8674 addl(count, 8 << shift);
8675 jccb(Assembler::zero, L_exit);
8676 jmpb(L_fill_8_bytes);
8677
8678 //
8679 // length is too short, just fill qwords
8680 //
8681 BIND(L_fill_8_bytes_loop);
8682 movl(Address(to, 0), value);
8683 movl(Address(to, 4), value);
8684 addptr(to, 8);
8685 BIND(L_fill_8_bytes);
8686 subl(count, 1 << (shift + 1));
8687 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
8688 // fall through to fill 4 bytes
8689 } else {
8690 Label L_fill_32_bytes;
8691 if (!UseUnalignedLoadStores) {
8692 // align to 8 bytes, we know we are 4 byte aligned to start
8693 testptr(to, 4);
8694 jccb(Assembler::zero, L_fill_32_bytes);
8695 movl(Address(to, 0), value);
8696 addptr(to, 4);
8697 subl(count, 1<<shift);
8698 }
8699 BIND(L_fill_32_bytes);
8700 {
8701 assert( UseSSE >= 2, "supported cpu only" );
8702 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
8703 if (UseAVX > 2) {
8704 movl(rtmp, 0xffff);
8705 kmovwl(k1, rtmp);
8706 }
8707 movdl(xtmp, value);
8708 if (UseAVX > 2 && UseUnalignedLoadStores) {
8709 // Fill 64-byte chunks
8710 Label L_fill_64_bytes_loop, L_check_fill_32_bytes;
8711 evpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit);
8712
8713 subl(count, 16 << shift);
8714 jcc(Assembler::less, L_check_fill_32_bytes);
8715 align(16);
8716
8717 BIND(L_fill_64_bytes_loop);
8718 evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit);
8719 addptr(to, 64);
8720 subl(count, 16 << shift);
8721 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
8722
8723 BIND(L_check_fill_32_bytes);
8724 addl(count, 8 << shift);
8725 jccb(Assembler::less, L_check_fill_8_bytes);
8726 vmovdqu(Address(to, 0), xtmp);
8727 addptr(to, 32);
8728 subl(count, 8 << shift);
8729
8730 BIND(L_check_fill_8_bytes);
8731 } else if (UseAVX == 2 && UseUnalignedLoadStores) {
8732 // Fill 64-byte chunks
8733 Label L_fill_64_bytes_loop, L_check_fill_32_bytes;
8734 vpbroadcastd(xtmp, xtmp);
8735
8736 subl(count, 16 << shift);
8737 jcc(Assembler::less, L_check_fill_32_bytes);
8738 align(16);
8739
8740 BIND(L_fill_64_bytes_loop);
8741 vmovdqu(Address(to, 0), xtmp);
8742 vmovdqu(Address(to, 32), xtmp);
8743 addptr(to, 64);
8744 subl(count, 16 << shift);
8745 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
8746
8747 BIND(L_check_fill_32_bytes);
8748 addl(count, 8 << shift);
8749 jccb(Assembler::less, L_check_fill_8_bytes);
8750 vmovdqu(Address(to, 0), xtmp);
8751 addptr(to, 32);
8752 subl(count, 8 << shift);
8753
8754 BIND(L_check_fill_8_bytes);
8755 // clean upper bits of YMM registers
8756 movdl(xtmp, value);
8757 pshufd(xtmp, xtmp, 0);
8758 } else {
8759 // Fill 32-byte chunks
8760 pshufd(xtmp, xtmp, 0);
8761
8762 subl(count, 8 << shift);
8763 jcc(Assembler::less, L_check_fill_8_bytes);
8764 align(16);
8765
8766 BIND(L_fill_32_bytes_loop);
8767
8768 if (UseUnalignedLoadStores) {
8769 movdqu(Address(to, 0), xtmp);
8770 movdqu(Address(to, 16), xtmp);
8771 } else {
8772 movq(Address(to, 0), xtmp);
8773 movq(Address(to, 8), xtmp);
8774 movq(Address(to, 16), xtmp);
8775 movq(Address(to, 24), xtmp);
8776 }
8777
8778 addptr(to, 32);
8779 subl(count, 8 << shift);
8780 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
8781
8782 BIND(L_check_fill_8_bytes);
8783 }
8784 addl(count, 8 << shift);
8785 jccb(Assembler::zero, L_exit);
8786 jmpb(L_fill_8_bytes);
8787
8788 //
8789 // length is too short, just fill qwords
8790 //
8791 BIND(L_fill_8_bytes_loop);
8792 movq(Address(to, 0), xtmp);
8793 addptr(to, 8);
8794 BIND(L_fill_8_bytes);
8795 subl(count, 1 << (shift + 1));
8796 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
8797 }
8798 }
8799 // fill trailing 4 bytes
8800 BIND(L_fill_4_bytes);
8801 testl(count, 1<<shift);
8802 jccb(Assembler::zero, L_fill_2_bytes);
8803 movl(Address(to, 0), value);
8804 if (t == T_BYTE || t == T_SHORT) {
8805 addptr(to, 4);
8806 BIND(L_fill_2_bytes);
8807 // fill trailing 2 bytes
8808 testl(count, 1<<(shift-1));
8809 jccb(Assembler::zero, L_fill_byte);
8810 movw(Address(to, 0), value);
8811 if (t == T_BYTE) {
8812 addptr(to, 2);
8813 BIND(L_fill_byte);
8814 // fill trailing byte
8815 testl(count, 1);
8816 jccb(Assembler::zero, L_exit);
8817 movb(Address(to, 0), value);
8818 } else {
8819 BIND(L_fill_byte);
8820 }
8821 } else {
8822 BIND(L_fill_2_bytes);
8823 }
8824 BIND(L_exit);
8825 }
8826
8827 // encode char[] to byte[] in ISO_8859_1
8828 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
8829 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
8830 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
8831 Register tmp5, Register result) {
8832 // rsi: src
8833 // rdi: dst
8834 // rdx: len
8835 // rcx: tmp5
8836 // rax: result
8837 ShortBranchVerifier sbv(this);
8838 assert_different_registers(src, dst, len, tmp5, result);
8839 Label L_done, L_copy_1_char, L_copy_1_char_exit;
8840
8841 // set result
8842 xorl(result, result);
8843 // check for zero length
8844 testl(len, len);
8845 jcc(Assembler::zero, L_done);
8846 movl(result, len);
8847
8848 // Setup pointers
8849 lea(src, Address(src, len, Address::times_2)); // char[]
8850 lea(dst, Address(dst, len, Address::times_1)); // byte[]
8851 negptr(len);
8852
8853 if (UseSSE42Intrinsics || UseAVX >= 2) {
8854 assert(UseSSE42Intrinsics ? UseSSE >= 4 : true, "SSE4 must be enabled for SSE4.2 intrinsics to be available");
8855 Label L_chars_8_check, L_copy_8_chars, L_copy_8_chars_exit;
8856 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
8857
8858 if (UseAVX >= 2) {
8859 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
8860 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector
8861 movdl(tmp1Reg, tmp5);
8862 vpbroadcastd(tmp1Reg, tmp1Reg);
8863 jmpb(L_chars_32_check);
8864
8865 bind(L_copy_32_chars);
8866 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
8867 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
8868 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
8869 vptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
8870 jccb(Assembler::notZero, L_copy_32_chars_exit);
8871 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
8872 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1);
8873 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
8874
8875 bind(L_chars_32_check);
8876 addptr(len, 32);
8877 jccb(Assembler::lessEqual, L_copy_32_chars);
8878
8879 bind(L_copy_32_chars_exit);
8880 subptr(len, 16);
8881 jccb(Assembler::greater, L_copy_16_chars_exit);
8882
8883 } else if (UseSSE42Intrinsics) {
8884 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector
8885 movdl(tmp1Reg, tmp5);
8886 pshufd(tmp1Reg, tmp1Reg, 0);
8887 jmpb(L_chars_16_check);
8888 }
8889
8890 bind(L_copy_16_chars);
8891 if (UseAVX >= 2) {
8892 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
8893 vptest(tmp2Reg, tmp1Reg);
8894 jccb(Assembler::notZero, L_copy_16_chars_exit);
8895 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1);
8896 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1);
8897 } else {
8898 if (UseAVX > 0) {
8899 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
8900 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
8901 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0);
8902 } else {
8903 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
8904 por(tmp2Reg, tmp3Reg);
8905 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
8906 por(tmp2Reg, tmp4Reg);
8907 }
8908 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
8909 jccb(Assembler::notZero, L_copy_16_chars_exit);
8910 packuswb(tmp3Reg, tmp4Reg);
8911 }
8912 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
8913
8914 bind(L_chars_16_check);
8915 addptr(len, 16);
8916 jccb(Assembler::lessEqual, L_copy_16_chars);
8917
8918 bind(L_copy_16_chars_exit);
8919 if (UseAVX >= 2) {
8920 // clean upper bits of YMM registers
8921 vpxor(tmp2Reg, tmp2Reg);
8922 vpxor(tmp3Reg, tmp3Reg);
8923 vpxor(tmp4Reg, tmp4Reg);
8924 movdl(tmp1Reg, tmp5);
8925 pshufd(tmp1Reg, tmp1Reg, 0);
8926 }
8927 subptr(len, 8);
8928 jccb(Assembler::greater, L_copy_8_chars_exit);
8929
8930 bind(L_copy_8_chars);
8931 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
8932 ptest(tmp3Reg, tmp1Reg);
8933 jccb(Assembler::notZero, L_copy_8_chars_exit);
8934 packuswb(tmp3Reg, tmp1Reg);
8935 movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
8936 addptr(len, 8);
8937 jccb(Assembler::lessEqual, L_copy_8_chars);
8938
8939 bind(L_copy_8_chars_exit);
8940 subptr(len, 8);
8941 jccb(Assembler::zero, L_done);
8942 }
8943
8944 bind(L_copy_1_char);
8945 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
8946 testl(tmp5, 0xff00); // check if Unicode char
8947 jccb(Assembler::notZero, L_copy_1_char_exit);
8948 movb(Address(dst, len, Address::times_1, 0), tmp5);
8949 addptr(len, 1);
8950 jccb(Assembler::less, L_copy_1_char);
8951
8952 bind(L_copy_1_char_exit);
8953 addptr(result, len); // len is negative count of not processed elements
8954 bind(L_done);
8955 }
8956
8957 #ifdef _LP64
8958 /**
8959 * Helper for multiply_to_len().
8960 */
8961 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
8962 addq(dest_lo, src1);
8963 adcq(dest_hi, 0);
8964 addq(dest_lo, src2);
8965 adcq(dest_hi, 0);
8966 }
8967
8968 /**
8969 * Multiply 64 bit by 64 bit first loop.
8970 */
8971 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
8972 Register y, Register y_idx, Register z,
8973 Register carry, Register product,
8974 Register idx, Register kdx) {
8975 //
8976 // jlong carry, x[], y[], z[];
8977 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
8978 // huge_128 product = y[idx] * x[xstart] + carry;
8979 // z[kdx] = (jlong)product;
8980 // carry = (jlong)(product >>> 64);
8981 // }
8982 // z[xstart] = carry;
8983 //
8984
8985 Label L_first_loop, L_first_loop_exit;
8986 Label L_one_x, L_one_y, L_multiply;
8987
8988 decrementl(xstart);
8989 jcc(Assembler::negative, L_one_x);
8990
8991 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
8992 rorq(x_xstart, 32); // convert big-endian to little-endian
8993
8994 bind(L_first_loop);
8995 decrementl(idx);
8996 jcc(Assembler::negative, L_first_loop_exit);
8997 decrementl(idx);
8998 jcc(Assembler::negative, L_one_y);
8999 movq(y_idx, Address(y, idx, Address::times_4, 0));
9000 rorq(y_idx, 32); // convert big-endian to little-endian
9001 bind(L_multiply);
9002 movq(product, x_xstart);
9003 mulq(y_idx); // product(rax) * y_idx -> rdx:rax
9004 addq(product, carry);
9005 adcq(rdx, 0);
9006 subl(kdx, 2);
9007 movl(Address(z, kdx, Address::times_4, 4), product);
9008 shrq(product, 32);
9009 movl(Address(z, kdx, Address::times_4, 0), product);
9010 movq(carry, rdx);
9011 jmp(L_first_loop);
9012
9013 bind(L_one_y);
9014 movl(y_idx, Address(y, 0));
9015 jmp(L_multiply);
9016
9017 bind(L_one_x);
9018 movl(x_xstart, Address(x, 0));
9019 jmp(L_first_loop);
9020
9021 bind(L_first_loop_exit);
9022 }
9023
9024 /**
9025 * Multiply 64 bit by 64 bit and add 128 bit.
9026 */
9027 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
9028 Register yz_idx, Register idx,
9029 Register carry, Register product, int offset) {
9030 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
9031 // z[kdx] = (jlong)product;
9032
9033 movq(yz_idx, Address(y, idx, Address::times_4, offset));
9034 rorq(yz_idx, 32); // convert big-endian to little-endian
9035 movq(product, x_xstart);
9036 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
9037 movq(yz_idx, Address(z, idx, Address::times_4, offset));
9038 rorq(yz_idx, 32); // convert big-endian to little-endian
9039
9040 add2_with_carry(rdx, product, carry, yz_idx);
9041
9042 movl(Address(z, idx, Address::times_4, offset+4), product);
9043 shrq(product, 32);
9044 movl(Address(z, idx, Address::times_4, offset), product);
9045
9046 }
9047
9048 /**
9049 * Multiply 128 bit by 128 bit. Unrolled inner loop.
9050 */
9051 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
9052 Register yz_idx, Register idx, Register jdx,
9053 Register carry, Register product,
9054 Register carry2) {
9055 // jlong carry, x[], y[], z[];
9056 // int kdx = ystart+1;
9057 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
9058 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
9059 // z[kdx+idx+1] = (jlong)product;
9060 // jlong carry2 = (jlong)(product >>> 64);
9061 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
9062 // z[kdx+idx] = (jlong)product;
9063 // carry = (jlong)(product >>> 64);
9064 // }
9065 // idx += 2;
9066 // if (idx > 0) {
9067 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
9068 // z[kdx+idx] = (jlong)product;
9069 // carry = (jlong)(product >>> 64);
9070 // }
9071 //
9072
9073 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
9074
9075 movl(jdx, idx);
9076 andl(jdx, 0xFFFFFFFC);
9077 shrl(jdx, 2);
9078
9079 bind(L_third_loop);
9080 subl(jdx, 1);
9081 jcc(Assembler::negative, L_third_loop_exit);
9082 subl(idx, 4);
9083
9084 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
9085 movq(carry2, rdx);
9086
9087 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
9088 movq(carry, rdx);
9089 jmp(L_third_loop);
9090
9091 bind (L_third_loop_exit);
9092
9093 andl (idx, 0x3);
9094 jcc(Assembler::zero, L_post_third_loop_done);
9095
9096 Label L_check_1;
9097 subl(idx, 2);
9098 jcc(Assembler::negative, L_check_1);
9099
9100 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
9101 movq(carry, rdx);
9102
9103 bind (L_check_1);
9104 addl (idx, 0x2);
9105 andl (idx, 0x1);
9106 subl(idx, 1);
9107 jcc(Assembler::negative, L_post_third_loop_done);
9108
9109 movl(yz_idx, Address(y, idx, Address::times_4, 0));
9110 movq(product, x_xstart);
9111 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
9112 movl(yz_idx, Address(z, idx, Address::times_4, 0));
9113
9114 add2_with_carry(rdx, product, yz_idx, carry);
9115
9116 movl(Address(z, idx, Address::times_4, 0), product);
9117 shrq(product, 32);
9118
9119 shlq(rdx, 32);
9120 orq(product, rdx);
9121 movq(carry, product);
9122
9123 bind(L_post_third_loop_done);
9124 }
9125
9126 /**
9127 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
9128 *
9129 */
9130 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
9131 Register carry, Register carry2,
9132 Register idx, Register jdx,
9133 Register yz_idx1, Register yz_idx2,
9134 Register tmp, Register tmp3, Register tmp4) {
9135 assert(UseBMI2Instructions, "should be used only when BMI2 is available");
9136
9137 // jlong carry, x[], y[], z[];
9138 // int kdx = ystart+1;
9139 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
9140 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
9141 // jlong carry2 = (jlong)(tmp3 >>> 64);
9142 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2;
9143 // carry = (jlong)(tmp4 >>> 64);
9144 // z[kdx+idx+1] = (jlong)tmp3;
9145 // z[kdx+idx] = (jlong)tmp4;
9146 // }
9147 // idx += 2;
9148 // if (idx > 0) {
9149 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
9150 // z[kdx+idx] = (jlong)yz_idx1;
9151 // carry = (jlong)(yz_idx1 >>> 64);
9152 // }
9153 //
9154
9155 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
9156
9157 movl(jdx, idx);
9158 andl(jdx, 0xFFFFFFFC);
9159 shrl(jdx, 2);
9160
9161 bind(L_third_loop);
9162 subl(jdx, 1);
9163 jcc(Assembler::negative, L_third_loop_exit);
9164 subl(idx, 4);
9165
9166 movq(yz_idx1, Address(y, idx, Address::times_4, 8));
9167 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
9168 movq(yz_idx2, Address(y, idx, Address::times_4, 0));
9169 rorxq(yz_idx2, yz_idx2, 32);
9170
9171 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
9172 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp
9173
9174 movq(yz_idx1, Address(z, idx, Address::times_4, 8));
9175 rorxq(yz_idx1, yz_idx1, 32);
9176 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
9177 rorxq(yz_idx2, yz_idx2, 32);
9178
9179 if (VM_Version::supports_adx()) {
9180 adcxq(tmp3, carry);
9181 adoxq(tmp3, yz_idx1);
9182
9183 adcxq(tmp4, tmp);
9184 adoxq(tmp4, yz_idx2);
9185
9186 movl(carry, 0); // does not affect flags
9187 adcxq(carry2, carry);
9188 adoxq(carry2, carry);
9189 } else {
9190 add2_with_carry(tmp4, tmp3, carry, yz_idx1);
9191 add2_with_carry(carry2, tmp4, tmp, yz_idx2);
9192 }
9193 movq(carry, carry2);
9194
9195 movl(Address(z, idx, Address::times_4, 12), tmp3);
9196 shrq(tmp3, 32);
9197 movl(Address(z, idx, Address::times_4, 8), tmp3);
9198
9199 movl(Address(z, idx, Address::times_4, 4), tmp4);
9200 shrq(tmp4, 32);
9201 movl(Address(z, idx, Address::times_4, 0), tmp4);
9202
9203 jmp(L_third_loop);
9204
9205 bind (L_third_loop_exit);
9206
9207 andl (idx, 0x3);
9208 jcc(Assembler::zero, L_post_third_loop_done);
9209
9210 Label L_check_1;
9211 subl(idx, 2);
9212 jcc(Assembler::negative, L_check_1);
9213
9214 movq(yz_idx1, Address(y, idx, Address::times_4, 0));
9215 rorxq(yz_idx1, yz_idx1, 32);
9216 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
9217 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
9218 rorxq(yz_idx2, yz_idx2, 32);
9219
9220 add2_with_carry(tmp4, tmp3, carry, yz_idx2);
9221
9222 movl(Address(z, idx, Address::times_4, 4), tmp3);
9223 shrq(tmp3, 32);
9224 movl(Address(z, idx, Address::times_4, 0), tmp3);
9225 movq(carry, tmp4);
9226
9227 bind (L_check_1);
9228 addl (idx, 0x2);
9229 andl (idx, 0x1);
9230 subl(idx, 1);
9231 jcc(Assembler::negative, L_post_third_loop_done);
9232 movl(tmp4, Address(y, idx, Address::times_4, 0));
9233 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3
9234 movl(tmp4, Address(z, idx, Address::times_4, 0));
9235
9236 add2_with_carry(carry2, tmp3, tmp4, carry);
9237
9238 movl(Address(z, idx, Address::times_4, 0), tmp3);
9239 shrq(tmp3, 32);
9240
9241 shlq(carry2, 32);
9242 orq(tmp3, carry2);
9243 movq(carry, tmp3);
9244
9245 bind(L_post_third_loop_done);
9246 }
9247
9248 /**
9249 * Code for BigInteger::multiplyToLen() instrinsic.
9250 *
9251 * rdi: x
9252 * rax: xlen
9253 * rsi: y
9254 * rcx: ylen
9255 * r8: z
9256 * r11: zlen
9257 * r12: tmp1
9258 * r13: tmp2
9259 * r14: tmp3
9260 * r15: tmp4
9261 * rbx: tmp5
9262 *
9263 */
9264 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
9265 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
9266 ShortBranchVerifier sbv(this);
9267 assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
9268
9269 push(tmp1);
9270 push(tmp2);
9271 push(tmp3);
9272 push(tmp4);
9273 push(tmp5);
9274
9275 push(xlen);
9276 push(zlen);
9277
9278 const Register idx = tmp1;
9279 const Register kdx = tmp2;
9280 const Register xstart = tmp3;
9281
9282 const Register y_idx = tmp4;
9283 const Register carry = tmp5;
9284 const Register product = xlen;
9285 const Register x_xstart = zlen; // reuse register
9286
9287 // First Loop.
9288 //
9289 // final static long LONG_MASK = 0xffffffffL;
9290 // int xstart = xlen - 1;
9291 // int ystart = ylen - 1;
9292 // long carry = 0;
9293 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
9294 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
9295 // z[kdx] = (int)product;
9296 // carry = product >>> 32;
9297 // }
9298 // z[xstart] = (int)carry;
9299 //
9300
9301 movl(idx, ylen); // idx = ylen;
9302 movl(kdx, zlen); // kdx = xlen+ylen;
9303 xorq(carry, carry); // carry = 0;
9304
9305 Label L_done;
9306
9307 movl(xstart, xlen);
9308 decrementl(xstart);
9309 jcc(Assembler::negative, L_done);
9310
9311 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
9312
9313 Label L_second_loop;
9314 testl(kdx, kdx);
9315 jcc(Assembler::zero, L_second_loop);
9316
9317 Label L_carry;
9318 subl(kdx, 1);
9319 jcc(Assembler::zero, L_carry);
9320
9321 movl(Address(z, kdx, Address::times_4, 0), carry);
9322 shrq(carry, 32);
9323 subl(kdx, 1);
9324
9325 bind(L_carry);
9326 movl(Address(z, kdx, Address::times_4, 0), carry);
9327
9328 // Second and third (nested) loops.
9329 //
9330 // for (int i = xstart-1; i >= 0; i--) { // Second loop
9331 // carry = 0;
9332 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
9333 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
9334 // (z[k] & LONG_MASK) + carry;
9335 // z[k] = (int)product;
9336 // carry = product >>> 32;
9337 // }
9338 // z[i] = (int)carry;
9339 // }
9340 //
9341 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
9342
9343 const Register jdx = tmp1;
9344
9345 bind(L_second_loop);
9346 xorl(carry, carry); // carry = 0;
9347 movl(jdx, ylen); // j = ystart+1
9348
9349 subl(xstart, 1); // i = xstart-1;
9350 jcc(Assembler::negative, L_done);
9351
9352 push (z);
9353
9354 Label L_last_x;
9355 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
9356 subl(xstart, 1); // i = xstart-1;
9357 jcc(Assembler::negative, L_last_x);
9358
9359 if (UseBMI2Instructions) {
9360 movq(rdx, Address(x, xstart, Address::times_4, 0));
9361 rorxq(rdx, rdx, 32); // convert big-endian to little-endian
9362 } else {
9363 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
9364 rorq(x_xstart, 32); // convert big-endian to little-endian
9365 }
9366
9367 Label L_third_loop_prologue;
9368 bind(L_third_loop_prologue);
9369
9370 push (x);
9371 push (xstart);
9372 push (ylen);
9373
9374
9375 if (UseBMI2Instructions) {
9376 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
9377 } else { // !UseBMI2Instructions
9378 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
9379 }
9380
9381 pop(ylen);
9382 pop(xlen);
9383 pop(x);
9384 pop(z);
9385
9386 movl(tmp3, xlen);
9387 addl(tmp3, 1);
9388 movl(Address(z, tmp3, Address::times_4, 0), carry);
9389 subl(tmp3, 1);
9390 jccb(Assembler::negative, L_done);
9391
9392 shrq(carry, 32);
9393 movl(Address(z, tmp3, Address::times_4, 0), carry);
9394 jmp(L_second_loop);
9395
9396 // Next infrequent code is moved outside loops.
9397 bind(L_last_x);
9398 if (UseBMI2Instructions) {
9399 movl(rdx, Address(x, 0));
9400 } else {
9401 movl(x_xstart, Address(x, 0));
9402 }
9403 jmp(L_third_loop_prologue);
9404
9405 bind(L_done);
9406
9407 pop(zlen);
9408 pop(xlen);
9409
9410 pop(tmp5);
9411 pop(tmp4);
9412 pop(tmp3);
9413 pop(tmp2);
9414 pop(tmp1);
9415 }
9416
9417 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
9418 Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){
9419 assert(UseSSE42Intrinsics, "SSE4.2 must be enabled.");
9420 Label VECTOR32_LOOP, VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP;
9421 Label VECTOR16_TAIL, VECTOR8_TAIL, VECTOR4_TAIL;
9422 Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL;
9423 Label SAME_TILL_END, DONE;
9424 Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL;
9425
9426 //scale is in rcx in both Win64 and Unix
9427 ShortBranchVerifier sbv(this);
9428
9429 shlq(length);
9430 xorq(result, result);
9431
9432 cmpq(length, 8);
9433 jcc(Assembler::equal, VECTOR8_LOOP);
9434 jcc(Assembler::less, VECTOR4_TAIL);
9435
9436 if (UseAVX >= 2){
9437
9438 cmpq(length, 16);
9439 jcc(Assembler::equal, VECTOR16_LOOP);
9440 jcc(Assembler::less, VECTOR8_LOOP);
9441
9442 cmpq(length, 32);
9443 jccb(Assembler::less, VECTOR16_TAIL);
9444
9445 subq(length, 32);
9446 bind(VECTOR32_LOOP);
9447 vmovdqu(rymm0, Address(obja, result));
9448 vmovdqu(rymm1, Address(objb, result));
9449 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit);
9450 vptest(rymm2, rymm2);
9451 jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found
9452 addq(result, 32);
9453 subq(length, 32);
9454 jccb(Assembler::greaterEqual, VECTOR32_LOOP);
9455 addq(length, 32);
9456 jcc(Assembler::equal, SAME_TILL_END);
9457 //falling through if less than 32 bytes left //close the branch here.
9458
9459 bind(VECTOR16_TAIL);
9460 cmpq(length, 16);
9461 jccb(Assembler::less, VECTOR8_TAIL);
9462 bind(VECTOR16_LOOP);
9463 movdqu(rymm0, Address(obja, result));
9464 movdqu(rymm1, Address(objb, result));
9465 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit);
9466 ptest(rymm2, rymm2);
9467 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
9468 addq(result, 16);
9469 subq(length, 16);
9470 jcc(Assembler::equal, SAME_TILL_END);
9471 //falling through if less than 16 bytes left
9472 } else {//regular intrinsics
9473
9474 cmpq(length, 16);
9475 jccb(Assembler::less, VECTOR8_TAIL);
9476
9477 subq(length, 16);
9478 bind(VECTOR16_LOOP);
9479 movdqu(rymm0, Address(obja, result));
9480 movdqu(rymm1, Address(objb, result));
9481 pxor(rymm0, rymm1);
9482 ptest(rymm0, rymm0);
9483 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
9484 addq(result, 16);
9485 subq(length, 16);
9486 jccb(Assembler::greaterEqual, VECTOR16_LOOP);
9487 addq(length, 16);
9488 jcc(Assembler::equal, SAME_TILL_END);
9489 //falling through if less than 16 bytes left
9490 }
9491
9492 bind(VECTOR8_TAIL);
9493 cmpq(length, 8);
9494 jccb(Assembler::less, VECTOR4_TAIL);
9495 bind(VECTOR8_LOOP);
9496 movq(tmp1, Address(obja, result));
9497 movq(tmp2, Address(objb, result));
9498 xorq(tmp1, tmp2);
9499 testq(tmp1, tmp1);
9500 jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found
9501 addq(result, 8);
9502 subq(length, 8);
9503 jcc(Assembler::equal, SAME_TILL_END);
9504 //falling through if less than 8 bytes left
9505
9506 bind(VECTOR4_TAIL);
9507 cmpq(length, 4);
9508 jccb(Assembler::less, BYTES_TAIL);
9509 bind(VECTOR4_LOOP);
9510 movl(tmp1, Address(obja, result));
9511 xorl(tmp1, Address(objb, result));
9512 testl(tmp1, tmp1);
9513 jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found
9514 addq(result, 4);
9515 subq(length, 4);
9516 jcc(Assembler::equal, SAME_TILL_END);
9517 //falling through if less than 4 bytes left
9518
9519 bind(BYTES_TAIL);
9520 bind(BYTES_LOOP);
9521 load_unsigned_byte(tmp1, Address(obja, result));
9522 load_unsigned_byte(tmp2, Address(objb, result));
9523 xorl(tmp1, tmp2);
9524 testl(tmp1, tmp1);
9525 jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
9526 decq(length);
9527 jccb(Assembler::zero, SAME_TILL_END);
9528 incq(result);
9529 load_unsigned_byte(tmp1, Address(obja, result));
9530 load_unsigned_byte(tmp2, Address(objb, result));
9531 xorl(tmp1, tmp2);
9532 testl(tmp1, tmp1);
9533 jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
9534 decq(length);
9535 jccb(Assembler::zero, SAME_TILL_END);
9536 incq(result);
9537 load_unsigned_byte(tmp1, Address(obja, result));
9538 load_unsigned_byte(tmp2, Address(objb, result));
9539 xorl(tmp1, tmp2);
9540 testl(tmp1, tmp1);
9541 jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
9542 jmpb(SAME_TILL_END);
9543
9544 if (UseAVX >= 2){
9545 bind(VECTOR32_NOT_EQUAL);
9546 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit);
9547 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit);
9548 vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit);
9549 vpmovmskb(tmp1, rymm0);
9550 bsfq(tmp1, tmp1);
9551 addq(result, tmp1);
9552 shrq(result);
9553 jmpb(DONE);
9554 }
9555
9556 bind(VECTOR16_NOT_EQUAL);
9557 if (UseAVX >= 2){
9558 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit);
9559 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit);
9560 pxor(rymm0, rymm2);
9561 } else {
9562 pcmpeqb(rymm2, rymm2);
9563 pxor(rymm0, rymm1);
9564 pcmpeqb(rymm0, rymm1);
9565 pxor(rymm0, rymm2);
9566 }
9567 pmovmskb(tmp1, rymm0);
9568 bsfq(tmp1, tmp1);
9569 addq(result, tmp1);
9570 shrq(result);
9571 jmpb(DONE);
9572
9573 bind(VECTOR8_NOT_EQUAL);
9574 bind(VECTOR4_NOT_EQUAL);
9575 bsfq(tmp1, tmp1);
9576 shrq(tmp1, 3);
9577 addq(result, tmp1);
9578 bind(BYTES_NOT_EQUAL);
9579 shrq(result);
9580 jmpb(DONE);
9581
9582 bind(SAME_TILL_END);
9583 mov64(result, -1);
9584
9585 bind(DONE);
9586 }
9587
9588
9589 //Helper functions for square_to_len()
9590
9591 /**
9592 * Store the squares of x[], right shifted one bit (divided by 2) into z[]
9593 * Preserves x and z and modifies rest of the registers.
9594 */
9595 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
9596 // Perform square and right shift by 1
9597 // Handle odd xlen case first, then for even xlen do the following
9598 // jlong carry = 0;
9599 // for (int j=0, i=0; j < xlen; j+=2, i+=4) {
9600 // huge_128 product = x[j:j+1] * x[j:j+1];
9601 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65);
9602 // z[i+2:i+3] = (jlong)(product >>> 1);
9603 // carry = (jlong)product;
9604 // }
9605
9606 xorq(tmp5, tmp5); // carry
9607 xorq(rdxReg, rdxReg);
9608 xorl(tmp1, tmp1); // index for x
9609 xorl(tmp4, tmp4); // index for z
9610
9611 Label L_first_loop, L_first_loop_exit;
9612
9613 testl(xlen, 1);
9614 jccb(Assembler::zero, L_first_loop); //jump if xlen is even
9615
9616 // Square and right shift by 1 the odd element using 32 bit multiply
9617 movl(raxReg, Address(x, tmp1, Address::times_4, 0));
9618 imulq(raxReg, raxReg);
9619 shrq(raxReg, 1);
9620 adcq(tmp5, 0);
9621 movq(Address(z, tmp4, Address::times_4, 0), raxReg);
9622 incrementl(tmp1);
9623 addl(tmp4, 2);
9624
9625 // Square and right shift by 1 the rest using 64 bit multiply
9626 bind(L_first_loop);
9627 cmpptr(tmp1, xlen);
9628 jccb(Assembler::equal, L_first_loop_exit);
9629
9630 // Square
9631 movq(raxReg, Address(x, tmp1, Address::times_4, 0));
9632 rorq(raxReg, 32); // convert big-endian to little-endian
9633 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax
9634
9635 // Right shift by 1 and save carry
9636 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1
9637 rcrq(rdxReg, 1);
9638 rcrq(raxReg, 1);
9639 adcq(tmp5, 0);
9640
9641 // Store result in z
9642 movq(Address(z, tmp4, Address::times_4, 0), rdxReg);
9643 movq(Address(z, tmp4, Address::times_4, 8), raxReg);
9644
9645 // Update indices for x and z
9646 addl(tmp1, 2);
9647 addl(tmp4, 4);
9648 jmp(L_first_loop);
9649
9650 bind(L_first_loop_exit);
9651 }
9652
9653
9654 /**
9655 * Perform the following multiply add operation using BMI2 instructions
9656 * carry:sum = sum + op1*op2 + carry
9657 * op2 should be in rdx
9658 * op2 is preserved, all other registers are modified
9659 */
9660 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) {
9661 // assert op2 is rdx
9662 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1
9663 addq(sum, carry);
9664 adcq(tmp2, 0);
9665 addq(sum, op1);
9666 adcq(tmp2, 0);
9667 movq(carry, tmp2);
9668 }
9669
9670 /**
9671 * Perform the following multiply add operation:
9672 * carry:sum = sum + op1*op2 + carry
9673 * Preserves op1, op2 and modifies rest of registers
9674 */
9675 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) {
9676 // rdx:rax = op1 * op2
9677 movq(raxReg, op2);
9678 mulq(op1);
9679
9680 // rdx:rax = sum + carry + rdx:rax
9681 addq(sum, carry);
9682 adcq(rdxReg, 0);
9683 addq(sum, raxReg);
9684 adcq(rdxReg, 0);
9685
9686 // carry:sum = rdx:sum
9687 movq(carry, rdxReg);
9688 }
9689
9690 /**
9691 * Add 64 bit long carry into z[] with carry propogation.
9692 * Preserves z and carry register values and modifies rest of registers.
9693 *
9694 */
9695 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) {
9696 Label L_fourth_loop, L_fourth_loop_exit;
9697
9698 movl(tmp1, 1);
9699 subl(zlen, 2);
9700 addq(Address(z, zlen, Address::times_4, 0), carry);
9701
9702 bind(L_fourth_loop);
9703 jccb(Assembler::carryClear, L_fourth_loop_exit);
9704 subl(zlen, 2);
9705 jccb(Assembler::negative, L_fourth_loop_exit);
9706 addq(Address(z, zlen, Address::times_4, 0), tmp1);
9707 jmp(L_fourth_loop);
9708 bind(L_fourth_loop_exit);
9709 }
9710
9711 /**
9712 * Shift z[] left by 1 bit.
9713 * Preserves x, len, z and zlen registers and modifies rest of the registers.
9714 *
9715 */
9716 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
9717
9718 Label L_fifth_loop, L_fifth_loop_exit;
9719
9720 // Fifth loop
9721 // Perform primitiveLeftShift(z, zlen, 1)
9722
9723 const Register prev_carry = tmp1;
9724 const Register new_carry = tmp4;
9725 const Register value = tmp2;
9726 const Register zidx = tmp3;
9727
9728 // int zidx, carry;
9729 // long value;
9730 // carry = 0;
9731 // for (zidx = zlen-2; zidx >=0; zidx -= 2) {
9732 // (carry:value) = (z[i] << 1) | carry ;
9733 // z[i] = value;
9734 // }
9735
9736 movl(zidx, zlen);
9737 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register
9738
9739 bind(L_fifth_loop);
9740 decl(zidx); // Use decl to preserve carry flag
9741 decl(zidx);
9742 jccb(Assembler::negative, L_fifth_loop_exit);
9743
9744 if (UseBMI2Instructions) {
9745 movq(value, Address(z, zidx, Address::times_4, 0));
9746 rclq(value, 1);
9747 rorxq(value, value, 32);
9748 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
9749 }
9750 else {
9751 // clear new_carry
9752 xorl(new_carry, new_carry);
9753
9754 // Shift z[i] by 1, or in previous carry and save new carry
9755 movq(value, Address(z, zidx, Address::times_4, 0));
9756 shlq(value, 1);
9757 adcl(new_carry, 0);
9758
9759 orq(value, prev_carry);
9760 rorq(value, 0x20);
9761 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
9762
9763 // Set previous carry = new carry
9764 movl(prev_carry, new_carry);
9765 }
9766 jmp(L_fifth_loop);
9767
9768 bind(L_fifth_loop_exit);
9769 }
9770
9771
9772 /**
9773 * Code for BigInteger::squareToLen() intrinsic
9774 *
9775 * rdi: x
9776 * rsi: len
9777 * r8: z
9778 * rcx: zlen
9779 * r12: tmp1
9780 * r13: tmp2
9781 * r14: tmp3
9782 * r15: tmp4
9783 * rbx: tmp5
9784 *
9785 */
9786 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
9787
9788 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, fifth_loop, fifth_loop_exit, L_last_x, L_multiply;
9789 push(tmp1);
9790 push(tmp2);
9791 push(tmp3);
9792 push(tmp4);
9793 push(tmp5);
9794
9795 // First loop
9796 // Store the squares, right shifted one bit (i.e., divided by 2).
9797 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg);
9798
9799 // Add in off-diagonal sums.
9800 //
9801 // Second, third (nested) and fourth loops.
9802 // zlen +=2;
9803 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) {
9804 // carry = 0;
9805 // long op2 = x[xidx:xidx+1];
9806 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) {
9807 // k -= 2;
9808 // long op1 = x[j:j+1];
9809 // long sum = z[k:k+1];
9810 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs);
9811 // z[k:k+1] = sum;
9812 // }
9813 // add_one_64(z, k, carry, tmp_regs);
9814 // }
9815
9816 const Register carry = tmp5;
9817 const Register sum = tmp3;
9818 const Register op1 = tmp4;
9819 Register op2 = tmp2;
9820
9821 push(zlen);
9822 push(len);
9823 addl(zlen,2);
9824 bind(L_second_loop);
9825 xorq(carry, carry);
9826 subl(zlen, 4);
9827 subl(len, 2);
9828 push(zlen);
9829 push(len);
9830 cmpl(len, 0);
9831 jccb(Assembler::lessEqual, L_second_loop_exit);
9832
9833 // Multiply an array by one 64 bit long.
9834 if (UseBMI2Instructions) {
9835 op2 = rdxReg;
9836 movq(op2, Address(x, len, Address::times_4, 0));
9837 rorxq(op2, op2, 32);
9838 }
9839 else {
9840 movq(op2, Address(x, len, Address::times_4, 0));
9841 rorq(op2, 32);
9842 }
9843
9844 bind(L_third_loop);
9845 decrementl(len);
9846 jccb(Assembler::negative, L_third_loop_exit);
9847 decrementl(len);
9848 jccb(Assembler::negative, L_last_x);
9849
9850 movq(op1, Address(x, len, Address::times_4, 0));
9851 rorq(op1, 32);
9852
9853 bind(L_multiply);
9854 subl(zlen, 2);
9855 movq(sum, Address(z, zlen, Address::times_4, 0));
9856
9857 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry.
9858 if (UseBMI2Instructions) {
9859 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2);
9860 }
9861 else {
9862 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
9863 }
9864
9865 movq(Address(z, zlen, Address::times_4, 0), sum);
9866
9867 jmp(L_third_loop);
9868 bind(L_third_loop_exit);
9869
9870 // Fourth loop
9871 // Add 64 bit long carry into z with carry propogation.
9872 // Uses offsetted zlen.
9873 add_one_64(z, zlen, carry, tmp1);
9874
9875 pop(len);
9876 pop(zlen);
9877 jmp(L_second_loop);
9878
9879 // Next infrequent code is moved outside loops.
9880 bind(L_last_x);
9881 movl(op1, Address(x, 0));
9882 jmp(L_multiply);
9883
9884 bind(L_second_loop_exit);
9885 pop(len);
9886 pop(zlen);
9887 pop(len);
9888 pop(zlen);
9889
9890 // Fifth loop
9891 // Shift z left 1 bit.
9892 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4);
9893
9894 // z[zlen-1] |= x[len-1] & 1;
9895 movl(tmp3, Address(x, len, Address::times_4, -4));
9896 andl(tmp3, 1);
9897 orl(Address(z, zlen, Address::times_4, -4), tmp3);
9898
9899 pop(tmp5);
9900 pop(tmp4);
9901 pop(tmp3);
9902 pop(tmp2);
9903 pop(tmp1);
9904 }
9905
9906 /**
9907 * Helper function for mul_add()
9908 * Multiply the in[] by int k and add to out[] starting at offset offs using
9909 * 128 bit by 32 bit multiply and return the carry in tmp5.
9910 * Only quad int aligned length of in[] is operated on in this function.
9911 * k is in rdxReg for BMI2Instructions, for others it is in tmp2.
9912 * This function preserves out, in and k registers.
9913 * len and offset point to the appropriate index in "in" & "out" correspondingly
9914 * tmp5 has the carry.
9915 * other registers are temporary and are modified.
9916 *
9917 */
9918 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in,
9919 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3,
9920 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
9921
9922 Label L_first_loop, L_first_loop_exit;
9923
9924 movl(tmp1, len);
9925 shrl(tmp1, 2);
9926
9927 bind(L_first_loop);
9928 subl(tmp1, 1);
9929 jccb(Assembler::negative, L_first_loop_exit);
9930
9931 subl(len, 4);
9932 subl(offset, 4);
9933
9934 Register op2 = tmp2;
9935 const Register sum = tmp3;
9936 const Register op1 = tmp4;
9937 const Register carry = tmp5;
9938
9939 if (UseBMI2Instructions) {
9940 op2 = rdxReg;
9941 }
9942
9943 movq(op1, Address(in, len, Address::times_4, 8));
9944 rorq(op1, 32);
9945 movq(sum, Address(out, offset, Address::times_4, 8));
9946 rorq(sum, 32);
9947 if (UseBMI2Instructions) {
9948 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
9949 }
9950 else {
9951 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
9952 }
9953 // Store back in big endian from little endian
9954 rorq(sum, 0x20);
9955 movq(Address(out, offset, Address::times_4, 8), sum);
9956
9957 movq(op1, Address(in, len, Address::times_4, 0));
9958 rorq(op1, 32);
9959 movq(sum, Address(out, offset, Address::times_4, 0));
9960 rorq(sum, 32);
9961 if (UseBMI2Instructions) {
9962 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
9963 }
9964 else {
9965 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
9966 }
9967 // Store back in big endian from little endian
9968 rorq(sum, 0x20);
9969 movq(Address(out, offset, Address::times_4, 0), sum);
9970
9971 jmp(L_first_loop);
9972 bind(L_first_loop_exit);
9973 }
9974
9975 /**
9976 * Code for BigInteger::mulAdd() intrinsic
9977 *
9978 * rdi: out
9979 * rsi: in
9980 * r11: offs (out.length - offset)
9981 * rcx: len
9982 * r8: k
9983 * r12: tmp1
9984 * r13: tmp2
9985 * r14: tmp3
9986 * r15: tmp4
9987 * rbx: tmp5
9988 * Multiply the in[] by word k and add to out[], return the carry in rax
9989 */
9990 void MacroAssembler::mul_add(Register out, Register in, Register offs,
9991 Register len, Register k, Register tmp1, Register tmp2, Register tmp3,
9992 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
9993
9994 Label L_carry, L_last_in, L_done;
9995
9996 // carry = 0;
9997 // for (int j=len-1; j >= 0; j--) {
9998 // long product = (in[j] & LONG_MASK) * kLong +
9999 // (out[offs] & LONG_MASK) + carry;
10000 // out[offs--] = (int)product;
10001 // carry = product >>> 32;
10002 // }
10003 //
10004 push(tmp1);
10005 push(tmp2);
10006 push(tmp3);
10007 push(tmp4);
10008 push(tmp5);
10009
10010 Register op2 = tmp2;
10011 const Register sum = tmp3;
10012 const Register op1 = tmp4;
10013 const Register carry = tmp5;
10014
10015 if (UseBMI2Instructions) {
10016 op2 = rdxReg;
10017 movl(op2, k);
10018 }
10019 else {
10020 movl(op2, k);
10021 }
10022
10023 xorq(carry, carry);
10024
10025 //First loop
10026
10027 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply
10028 //The carry is in tmp5
10029 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg);
10030
10031 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any
10032 decrementl(len);
10033 jccb(Assembler::negative, L_carry);
10034 decrementl(len);
10035 jccb(Assembler::negative, L_last_in);
10036
10037 movq(op1, Address(in, len, Address::times_4, 0));
10038 rorq(op1, 32);
10039
10040 subl(offs, 2);
10041 movq(sum, Address(out, offs, Address::times_4, 0));
10042 rorq(sum, 32);
10043
10044 if (UseBMI2Instructions) {
10045 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
10046 }
10047 else {
10048 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
10049 }
10050
10051 // Store back in big endian from little endian
10052 rorq(sum, 0x20);
10053 movq(Address(out, offs, Address::times_4, 0), sum);
10054
10055 testl(len, len);
10056 jccb(Assembler::zero, L_carry);
10057
10058 //Multiply the last in[] entry, if any
10059 bind(L_last_in);
10060 movl(op1, Address(in, 0));
10061 movl(sum, Address(out, offs, Address::times_4, -4));
10062
10063 movl(raxReg, k);
10064 mull(op1); //tmp4 * eax -> edx:eax
10065 addl(sum, carry);
10066 adcl(rdxReg, 0);
10067 addl(sum, raxReg);
10068 adcl(rdxReg, 0);
10069 movl(carry, rdxReg);
10070
10071 movl(Address(out, offs, Address::times_4, -4), sum);
10072
10073 bind(L_carry);
10074 //return tmp5/carry as carry in rax
10075 movl(rax, carry);
10076
10077 bind(L_done);
10078 pop(tmp5);
10079 pop(tmp4);
10080 pop(tmp3);
10081 pop(tmp2);
10082 pop(tmp1);
10083 }
10084 #endif
10085
10086 /**
10087 * Emits code to update CRC-32 with a byte value according to constants in table
10088 *
10089 * @param [in,out]crc Register containing the crc.
10090 * @param [in]val Register containing the byte to fold into the CRC.
10091 * @param [in]table Register containing the table of crc constants.
10092 *
10093 * uint32_t crc;
10094 * val = crc_table[(val ^ crc) & 0xFF];
10095 * crc = val ^ (crc >> 8);
10096 *
10097 */
10098 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
10099 xorl(val, crc);
10100 andl(val, 0xFF);
10101 shrl(crc, 8); // unsigned shift
10102 xorl(crc, Address(table, val, Address::times_4, 0));
10103 }
10104
10105 /**
10106 * Fold 128-bit data chunk
10107 */
10108 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
10109 if (UseAVX > 0) {
10110 vpclmulhdq(xtmp, xK, xcrc); // [123:64]
10111 vpclmulldq(xcrc, xK, xcrc); // [63:0]
10112 vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */);
10113 pxor(xcrc, xtmp);
10114 } else {
10115 movdqa(xtmp, xcrc);
10116 pclmulhdq(xtmp, xK); // [123:64]
10117 pclmulldq(xcrc, xK); // [63:0]
10118 pxor(xcrc, xtmp);
10119 movdqu(xtmp, Address(buf, offset));
10120 pxor(xcrc, xtmp);
10121 }
10122 }
10123
10124 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
10125 if (UseAVX > 0) {
10126 vpclmulhdq(xtmp, xK, xcrc);
10127 vpclmulldq(xcrc, xK, xcrc);
10128 pxor(xcrc, xbuf);
10129 pxor(xcrc, xtmp);
10130 } else {
10131 movdqa(xtmp, xcrc);
10132 pclmulhdq(xtmp, xK);
10133 pclmulldq(xcrc, xK);
10134 pxor(xcrc, xbuf);
10135 pxor(xcrc, xtmp);
10136 }
10137 }
10138
10139 /**
10140 * 8-bit folds to compute 32-bit CRC
10141 *
10142 * uint64_t xcrc;
10143 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
10144 */
10145 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
10146 movdl(tmp, xcrc);
10147 andl(tmp, 0xFF);
10148 movdl(xtmp, Address(table, tmp, Address::times_4, 0));
10149 psrldq(xcrc, 1); // unsigned shift one byte
10150 pxor(xcrc, xtmp);
10151 }
10152
10153 /**
10154 * uint32_t crc;
10155 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
10156 */
10157 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
10158 movl(tmp, crc);
10159 andl(tmp, 0xFF);
10160 shrl(crc, 8);
10161 xorl(crc, Address(table, tmp, Address::times_4, 0));
10162 }
10163
10164 /**
10165 * @param crc register containing existing CRC (32-bit)
10166 * @param buf register pointing to input byte buffer (byte*)
10167 * @param len register containing number of bytes
10168 * @param table register that will contain address of CRC table
10169 * @param tmp scratch register
10170 */
10171 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
10172 assert_different_registers(crc, buf, len, table, tmp, rax);
10173
10174 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
10175 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
10176
10177 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
10178 // context for the registers used, where all instructions below are using 128-bit mode
10179 // On EVEX without VL and BW, these instructions will all be AVX.
10180 if (VM_Version::supports_avx512vlbw()) {
10181 movl(tmp, 0xffff);
10182 kmovwl(k1, tmp);
10183 }
10184
10185 lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
10186 notl(crc); // ~crc
10187 cmpl(len, 16);
10188 jcc(Assembler::less, L_tail);
10189
10190 // Align buffer to 16 bytes
10191 movl(tmp, buf);
10192 andl(tmp, 0xF);
10193 jccb(Assembler::zero, L_aligned);
10194 subl(tmp, 16);
10195 addl(len, tmp);
10196
10197 align(4);
10198 BIND(L_align_loop);
10199 movsbl(rax, Address(buf, 0)); // load byte with sign extension
10200 update_byte_crc32(crc, rax, table);
10201 increment(buf);
10202 incrementl(tmp);
10203 jccb(Assembler::less, L_align_loop);
10204
10205 BIND(L_aligned);
10206 movl(tmp, len); // save
10207 shrl(len, 4);
10208 jcc(Assembler::zero, L_tail_restore);
10209
10210 // Fold crc into first bytes of vector
10211 movdqa(xmm1, Address(buf, 0));
10212 movdl(rax, xmm1);
10213 xorl(crc, rax);
10214 pinsrd(xmm1, crc, 0);
10215 addptr(buf, 16);
10216 subl(len, 4); // len > 0
10217 jcc(Assembler::less, L_fold_tail);
10218
10219 movdqa(xmm2, Address(buf, 0));
10220 movdqa(xmm3, Address(buf, 16));
10221 movdqa(xmm4, Address(buf, 32));
10222 addptr(buf, 48);
10223 subl(len, 3);
10224 jcc(Assembler::lessEqual, L_fold_512b);
10225
10226 // Fold total 512 bits of polynomial on each iteration,
10227 // 128 bits per each of 4 parallel streams.
10228 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32));
10229
10230 align(32);
10231 BIND(L_fold_512b_loop);
10232 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
10233 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
10234 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
10235 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
10236 addptr(buf, 64);
10237 subl(len, 4);
10238 jcc(Assembler::greater, L_fold_512b_loop);
10239
10240 // Fold 512 bits to 128 bits.
10241 BIND(L_fold_512b);
10242 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
10243 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
10244 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
10245 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
10246
10247 // Fold the rest of 128 bits data chunks
10248 BIND(L_fold_tail);
10249 addl(len, 3);
10250 jccb(Assembler::lessEqual, L_fold_128b);
10251 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
10252
10253 BIND(L_fold_tail_loop);
10254 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
10255 addptr(buf, 16);
10256 decrementl(len);
10257 jccb(Assembler::greater, L_fold_tail_loop);
10258
10259 // Fold 128 bits in xmm1 down into 32 bits in crc register.
10260 BIND(L_fold_128b);
10261 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()));
10262 if (UseAVX > 0) {
10263 vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
10264 vpand(xmm3, xmm0, xmm2, 0 /* vector_len */);
10265 vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
10266 } else {
10267 movdqa(xmm2, xmm0);
10268 pclmulqdq(xmm2, xmm1, 0x1);
10269 movdqa(xmm3, xmm0);
10270 pand(xmm3, xmm2);
10271 pclmulqdq(xmm0, xmm3, 0x1);
10272 }
10273 psrldq(xmm1, 8);
10274 psrldq(xmm2, 4);
10275 pxor(xmm0, xmm1);
10276 pxor(xmm0, xmm2);
10277
10278 // 8 8-bit folds to compute 32-bit CRC.
10279 for (int j = 0; j < 4; j++) {
10280 fold_8bit_crc32(xmm0, table, xmm1, rax);
10281 }
10282 movdl(crc, xmm0); // mov 32 bits to general register
10283 for (int j = 0; j < 4; j++) {
10284 fold_8bit_crc32(crc, table, rax);
10285 }
10286
10287 BIND(L_tail_restore);
10288 movl(len, tmp); // restore
10289 BIND(L_tail);
10290 andl(len, 0xf);
10291 jccb(Assembler::zero, L_exit);
10292
10293 // Fold the rest of bytes
10294 align(4);
10295 BIND(L_tail_loop);
10296 movsbl(rax, Address(buf, 0)); // load byte with sign extension
10297 update_byte_crc32(crc, rax, table);
10298 increment(buf);
10299 decrementl(len);
10300 jccb(Assembler::greater, L_tail_loop);
10301
10302 BIND(L_exit);
10303 notl(crc); // ~c
10304 }
10305
10306 #ifdef _LP64
10307 // S. Gueron / Information Processing Letters 112 (2012) 184
10308 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table.
10309 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0].
10310 // Output: the 64-bit carry-less product of B * CONST
10311 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n,
10312 Register tmp1, Register tmp2, Register tmp3) {
10313 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
10314 if (n > 0) {
10315 addq(tmp3, n * 256 * 8);
10316 }
10317 // Q1 = TABLEExt[n][B & 0xFF];
10318 movl(tmp1, in);
10319 andl(tmp1, 0x000000FF);
10320 shll(tmp1, 3);
10321 addq(tmp1, tmp3);
10322 movq(tmp1, Address(tmp1, 0));
10323
10324 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
10325 movl(tmp2, in);
10326 shrl(tmp2, 8);
10327 andl(tmp2, 0x000000FF);
10328 shll(tmp2, 3);
10329 addq(tmp2, tmp3);
10330 movq(tmp2, Address(tmp2, 0));
10331
10332 shlq(tmp2, 8);
10333 xorq(tmp1, tmp2);
10334
10335 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
10336 movl(tmp2, in);
10337 shrl(tmp2, 16);
10338 andl(tmp2, 0x000000FF);
10339 shll(tmp2, 3);
10340 addq(tmp2, tmp3);
10341 movq(tmp2, Address(tmp2, 0));
10342
10343 shlq(tmp2, 16);
10344 xorq(tmp1, tmp2);
10345
10346 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
10347 shrl(in, 24);
10348 andl(in, 0x000000FF);
10349 shll(in, 3);
10350 addq(in, tmp3);
10351 movq(in, Address(in, 0));
10352
10353 shlq(in, 24);
10354 xorq(in, tmp1);
10355 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
10356 }
10357
10358 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
10359 Register in_out,
10360 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
10361 XMMRegister w_xtmp2,
10362 Register tmp1,
10363 Register n_tmp2, Register n_tmp3) {
10364 if (is_pclmulqdq_supported) {
10365 movdl(w_xtmp1, in_out); // modified blindly
10366
10367 movl(tmp1, const_or_pre_comp_const_index);
10368 movdl(w_xtmp2, tmp1);
10369 pclmulqdq(w_xtmp1, w_xtmp2, 0);
10370
10371 movdq(in_out, w_xtmp1);
10372 } else {
10373 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3);
10374 }
10375 }
10376
10377 // Recombination Alternative 2: No bit-reflections
10378 // T1 = (CRC_A * U1) << 1
10379 // T2 = (CRC_B * U2) << 1
10380 // C1 = T1 >> 32
10381 // C2 = T2 >> 32
10382 // T1 = T1 & 0xFFFFFFFF
10383 // T2 = T2 & 0xFFFFFFFF
10384 // T1 = CRC32(0, T1)
10385 // T2 = CRC32(0, T2)
10386 // C1 = C1 ^ T1
10387 // C2 = C2 ^ T2
10388 // CRC = C1 ^ C2 ^ CRC_C
10389 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
10390 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10391 Register tmp1, Register tmp2,
10392 Register n_tmp3) {
10393 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
10394 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
10395 shlq(in_out, 1);
10396 movl(tmp1, in_out);
10397 shrq(in_out, 32);
10398 xorl(tmp2, tmp2);
10399 crc32(tmp2, tmp1, 4);
10400 xorl(in_out, tmp2); // we don't care about upper 32 bit contents here
10401 shlq(in1, 1);
10402 movl(tmp1, in1);
10403 shrq(in1, 32);
10404 xorl(tmp2, tmp2);
10405 crc32(tmp2, tmp1, 4);
10406 xorl(in1, tmp2);
10407 xorl(in_out, in1);
10408 xorl(in_out, in2);
10409 }
10410
10411 // Set N to predefined value
10412 // Subtract from a lenght of a buffer
10413 // execute in a loop:
10414 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0
10415 // for i = 1 to N do
10416 // CRC_A = CRC32(CRC_A, A[i])
10417 // CRC_B = CRC32(CRC_B, B[i])
10418 // CRC_C = CRC32(CRC_C, C[i])
10419 // end for
10420 // Recombine
10421 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
10422 Register in_out1, Register in_out2, Register in_out3,
10423 Register tmp1, Register tmp2, Register tmp3,
10424 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10425 Register tmp4, Register tmp5,
10426 Register n_tmp6) {
10427 Label L_processPartitions;
10428 Label L_processPartition;
10429 Label L_exit;
10430
10431 bind(L_processPartitions);
10432 cmpl(in_out1, 3 * size);
10433 jcc(Assembler::less, L_exit);
10434 xorl(tmp1, tmp1);
10435 xorl(tmp2, tmp2);
10436 movq(tmp3, in_out2);
10437 addq(tmp3, size);
10438
10439 bind(L_processPartition);
10440 crc32(in_out3, Address(in_out2, 0), 8);
10441 crc32(tmp1, Address(in_out2, size), 8);
10442 crc32(tmp2, Address(in_out2, size * 2), 8);
10443 addq(in_out2, 8);
10444 cmpq(in_out2, tmp3);
10445 jcc(Assembler::less, L_processPartition);
10446 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
10447 w_xtmp1, w_xtmp2, w_xtmp3,
10448 tmp4, tmp5,
10449 n_tmp6);
10450 addq(in_out2, 2 * size);
10451 subl(in_out1, 3 * size);
10452 jmp(L_processPartitions);
10453
10454 bind(L_exit);
10455 }
10456 #else
10457 void MacroAssembler::crc32c_ipl_alg4(Register in_out, uint32_t n,
10458 Register tmp1, Register tmp2, Register tmp3,
10459 XMMRegister xtmp1, XMMRegister xtmp2) {
10460 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
10461 if (n > 0) {
10462 addl(tmp3, n * 256 * 8);
10463 }
10464 // Q1 = TABLEExt[n][B & 0xFF];
10465 movl(tmp1, in_out);
10466 andl(tmp1, 0x000000FF);
10467 shll(tmp1, 3);
10468 addl(tmp1, tmp3);
10469 movq(xtmp1, Address(tmp1, 0));
10470
10471 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
10472 movl(tmp2, in_out);
10473 shrl(tmp2, 8);
10474 andl(tmp2, 0x000000FF);
10475 shll(tmp2, 3);
10476 addl(tmp2, tmp3);
10477 movq(xtmp2, Address(tmp2, 0));
10478
10479 psllq(xtmp2, 8);
10480 pxor(xtmp1, xtmp2);
10481
10482 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
10483 movl(tmp2, in_out);
10484 shrl(tmp2, 16);
10485 andl(tmp2, 0x000000FF);
10486 shll(tmp2, 3);
10487 addl(tmp2, tmp3);
10488 movq(xtmp2, Address(tmp2, 0));
10489
10490 psllq(xtmp2, 16);
10491 pxor(xtmp1, xtmp2);
10492
10493 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
10494 shrl(in_out, 24);
10495 andl(in_out, 0x000000FF);
10496 shll(in_out, 3);
10497 addl(in_out, tmp3);
10498 movq(xtmp2, Address(in_out, 0));
10499
10500 psllq(xtmp2, 24);
10501 pxor(xtmp1, xtmp2); // Result in CXMM
10502 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
10503 }
10504
10505 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
10506 Register in_out,
10507 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
10508 XMMRegister w_xtmp2,
10509 Register tmp1,
10510 Register n_tmp2, Register n_tmp3) {
10511 if (is_pclmulqdq_supported) {
10512 movdl(w_xtmp1, in_out);
10513
10514 movl(tmp1, const_or_pre_comp_const_index);
10515 movdl(w_xtmp2, tmp1);
10516 pclmulqdq(w_xtmp1, w_xtmp2, 0);
10517 // Keep result in XMM since GPR is 32 bit in length
10518 } else {
10519 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3, w_xtmp1, w_xtmp2);
10520 }
10521 }
10522
10523 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
10524 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10525 Register tmp1, Register tmp2,
10526 Register n_tmp3) {
10527 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
10528 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
10529
10530 psllq(w_xtmp1, 1);
10531 movdl(tmp1, w_xtmp1);
10532 psrlq(w_xtmp1, 32);
10533 movdl(in_out, w_xtmp1);
10534
10535 xorl(tmp2, tmp2);
10536 crc32(tmp2, tmp1, 4);
10537 xorl(in_out, tmp2);
10538
10539 psllq(w_xtmp2, 1);
10540 movdl(tmp1, w_xtmp2);
10541 psrlq(w_xtmp2, 32);
10542 movdl(in1, w_xtmp2);
10543
10544 xorl(tmp2, tmp2);
10545 crc32(tmp2, tmp1, 4);
10546 xorl(in1, tmp2);
10547 xorl(in_out, in1);
10548 xorl(in_out, in2);
10549 }
10550
10551 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
10552 Register in_out1, Register in_out2, Register in_out3,
10553 Register tmp1, Register tmp2, Register tmp3,
10554 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10555 Register tmp4, Register tmp5,
10556 Register n_tmp6) {
10557 Label L_processPartitions;
10558 Label L_processPartition;
10559 Label L_exit;
10560
10561 bind(L_processPartitions);
10562 cmpl(in_out1, 3 * size);
10563 jcc(Assembler::less, L_exit);
10564 xorl(tmp1, tmp1);
10565 xorl(tmp2, tmp2);
10566 movl(tmp3, in_out2);
10567 addl(tmp3, size);
10568
10569 bind(L_processPartition);
10570 crc32(in_out3, Address(in_out2, 0), 4);
10571 crc32(tmp1, Address(in_out2, size), 4);
10572 crc32(tmp2, Address(in_out2, size*2), 4);
10573 crc32(in_out3, Address(in_out2, 0+4), 4);
10574 crc32(tmp1, Address(in_out2, size+4), 4);
10575 crc32(tmp2, Address(in_out2, size*2+4), 4);
10576 addl(in_out2, 8);
10577 cmpl(in_out2, tmp3);
10578 jcc(Assembler::less, L_processPartition);
10579
10580 push(tmp3);
10581 push(in_out1);
10582 push(in_out2);
10583 tmp4 = tmp3;
10584 tmp5 = in_out1;
10585 n_tmp6 = in_out2;
10586
10587 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
10588 w_xtmp1, w_xtmp2, w_xtmp3,
10589 tmp4, tmp5,
10590 n_tmp6);
10591
10592 pop(in_out2);
10593 pop(in_out1);
10594 pop(tmp3);
10595
10596 addl(in_out2, 2 * size);
10597 subl(in_out1, 3 * size);
10598 jmp(L_processPartitions);
10599
10600 bind(L_exit);
10601 }
10602 #endif //LP64
10603
10604 #ifdef _LP64
10605 // Algorithm 2: Pipelined usage of the CRC32 instruction.
10606 // Input: A buffer I of L bytes.
10607 // Output: the CRC32C value of the buffer.
10608 // Notations:
10609 // Write L = 24N + r, with N = floor (L/24).
10610 // r = L mod 24 (0 <= r < 24).
10611 // Consider I as the concatenation of A|B|C|R, where A, B, C, each,
10612 // N quadwords, and R consists of r bytes.
10613 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1
10614 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1
10615 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1
10616 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1
10617 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
10618 Register tmp1, Register tmp2, Register tmp3,
10619 Register tmp4, Register tmp5, Register tmp6,
10620 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10621 bool is_pclmulqdq_supported) {
10622 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
10623 Label L_wordByWord;
10624 Label L_byteByByteProlog;
10625 Label L_byteByByte;
10626 Label L_exit;
10627
10628 if (is_pclmulqdq_supported ) {
10629 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
10630 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr+1);
10631
10632 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
10633 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
10634
10635 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
10636 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
10637 assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\"");
10638 } else {
10639 const_or_pre_comp_const_index[0] = 1;
10640 const_or_pre_comp_const_index[1] = 0;
10641
10642 const_or_pre_comp_const_index[2] = 3;
10643 const_or_pre_comp_const_index[3] = 2;
10644
10645 const_or_pre_comp_const_index[4] = 5;
10646 const_or_pre_comp_const_index[5] = 4;
10647 }
10648 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
10649 in2, in1, in_out,
10650 tmp1, tmp2, tmp3,
10651 w_xtmp1, w_xtmp2, w_xtmp3,
10652 tmp4, tmp5,
10653 tmp6);
10654 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
10655 in2, in1, in_out,
10656 tmp1, tmp2, tmp3,
10657 w_xtmp1, w_xtmp2, w_xtmp3,
10658 tmp4, tmp5,
10659 tmp6);
10660 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
10661 in2, in1, in_out,
10662 tmp1, tmp2, tmp3,
10663 w_xtmp1, w_xtmp2, w_xtmp3,
10664 tmp4, tmp5,
10665 tmp6);
10666 movl(tmp1, in2);
10667 andl(tmp1, 0x00000007);
10668 negl(tmp1);
10669 addl(tmp1, in2);
10670 addq(tmp1, in1);
10671
10672 BIND(L_wordByWord);
10673 cmpq(in1, tmp1);
10674 jcc(Assembler::greaterEqual, L_byteByByteProlog);
10675 crc32(in_out, Address(in1, 0), 4);
10676 addq(in1, 4);
10677 jmp(L_wordByWord);
10678
10679 BIND(L_byteByByteProlog);
10680 andl(in2, 0x00000007);
10681 movl(tmp2, 1);
10682
10683 BIND(L_byteByByte);
10684 cmpl(tmp2, in2);
10685 jccb(Assembler::greater, L_exit);
10686 crc32(in_out, Address(in1, 0), 1);
10687 incq(in1);
10688 incl(tmp2);
10689 jmp(L_byteByByte);
10690
10691 BIND(L_exit);
10692 }
10693 #else
10694 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
10695 Register tmp1, Register tmp2, Register tmp3,
10696 Register tmp4, Register tmp5, Register tmp6,
10697 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10698 bool is_pclmulqdq_supported) {
10699 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
10700 Label L_wordByWord;
10701 Label L_byteByByteProlog;
10702 Label L_byteByByte;
10703 Label L_exit;
10704
10705 if (is_pclmulqdq_supported) {
10706 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
10707 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 1);
10708
10709 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
10710 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
10711
10712 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
10713 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
10714 } else {
10715 const_or_pre_comp_const_index[0] = 1;
10716 const_or_pre_comp_const_index[1] = 0;
10717
10718 const_or_pre_comp_const_index[2] = 3;
10719 const_or_pre_comp_const_index[3] = 2;
10720
10721 const_or_pre_comp_const_index[4] = 5;
10722 const_or_pre_comp_const_index[5] = 4;
10723 }
10724 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
10725 in2, in1, in_out,
10726 tmp1, tmp2, tmp3,
10727 w_xtmp1, w_xtmp2, w_xtmp3,
10728 tmp4, tmp5,
10729 tmp6);
10730 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
10731 in2, in1, in_out,
10732 tmp1, tmp2, tmp3,
10733 w_xtmp1, w_xtmp2, w_xtmp3,
10734 tmp4, tmp5,
10735 tmp6);
10736 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
10737 in2, in1, in_out,
10738 tmp1, tmp2, tmp3,
10739 w_xtmp1, w_xtmp2, w_xtmp3,
10740 tmp4, tmp5,
10741 tmp6);
10742 movl(tmp1, in2);
10743 andl(tmp1, 0x00000007);
10744 negl(tmp1);
10745 addl(tmp1, in2);
10746 addl(tmp1, in1);
10747
10748 BIND(L_wordByWord);
10749 cmpl(in1, tmp1);
10750 jcc(Assembler::greaterEqual, L_byteByByteProlog);
10751 crc32(in_out, Address(in1,0), 4);
10752 addl(in1, 4);
10753 jmp(L_wordByWord);
10754
10755 BIND(L_byteByByteProlog);
10756 andl(in2, 0x00000007);
10757 movl(tmp2, 1);
10758
10759 BIND(L_byteByByte);
10760 cmpl(tmp2, in2);
10761 jccb(Assembler::greater, L_exit);
10762 movb(tmp1, Address(in1, 0));
10763 crc32(in_out, tmp1, 1);
10764 incl(in1);
10765 incl(tmp2);
10766 jmp(L_byteByByte);
10767
10768 BIND(L_exit);
10769 }
10770 #endif // LP64
10771 #undef BIND
10772 #undef BLOCK_COMMENT
10773
10774
10775 // Compress char[] array to byte[].
10776 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
10777 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
10778 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
10779 Register tmp5, Register result) {
10780 Label copy_chars_loop, return_length, return_zero, done;
10781
10782 // rsi: src
10783 // rdi: dst
10784 // rdx: len
10785 // rcx: tmp5
10786 // rax: result
10787
10788 // rsi holds start addr of source char[] to be compressed
10789 // rdi holds start addr of destination byte[]
10790 // rdx holds length
10791
10792 assert(len != result, "");
10793
10794 // save length for return
10795 push(len);
10796
10797 if (UseSSE42Intrinsics) {
10798 assert(UseSSE >= 4, "SSE4 must be enabled for SSE4.2 intrinsics to be available");
10799 Label copy_32_loop, copy_16, copy_tail;
10800
10801 movl(result, len);
10802 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vectors
10803
10804 // vectored compression
10805 andl(len, 0xfffffff0); // vector count (in chars)
10806 andl(result, 0x0000000f); // tail count (in chars)
10807 testl(len, len);
10808 jccb(Assembler::zero, copy_16);
10809
10810 // compress 16 chars per iter
10811 movdl(tmp1Reg, tmp5);
10812 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
10813 pxor(tmp4Reg, tmp4Reg);
10814
10815 lea(src, Address(src, len, Address::times_2));
10816 lea(dst, Address(dst, len, Address::times_1));
10817 negptr(len);
10818
10819 bind(copy_32_loop);
10820 movdqu(tmp2Reg, Address(src, len, Address::times_2)); // load 1st 8 characters
10821 por(tmp4Reg, tmp2Reg);
10822 movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters
10823 por(tmp4Reg, tmp3Reg);
10824 ptest(tmp4Reg, tmp1Reg); // check for Unicode chars in next vector
10825 jcc(Assembler::notZero, return_zero);
10826 packuswb(tmp2Reg, tmp3Reg); // only ASCII chars; compress each to 1 byte
10827 movdqu(Address(dst, len, Address::times_1), tmp2Reg);
10828 addptr(len, 16);
10829 jcc(Assembler::notZero, copy_32_loop);
10830
10831 // compress next vector of 8 chars (if any)
10832 bind(copy_16);
10833 movl(len, result);
10834 andl(len, 0xfffffff8); // vector count (in chars)
10835 andl(result, 0x00000007); // tail count (in chars)
10836 testl(len, len);
10837 jccb(Assembler::zero, copy_tail);
10838
10839 movdl(tmp1Reg, tmp5);
10840 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
10841 pxor(tmp3Reg, tmp3Reg);
10842
10843 movdqu(tmp2Reg, Address(src, 0));
10844 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
10845 jccb(Assembler::notZero, return_zero);
10846 packuswb(tmp2Reg, tmp3Reg); // only LATIN1 chars; compress each to 1 byte
10847 movq(Address(dst, 0), tmp2Reg);
10848 addptr(src, 16);
10849 addptr(dst, 8);
10850
10851 bind(copy_tail);
10852 movl(len, result);
10853 }
10854 // compress 1 char per iter
10855 testl(len, len);
10856 jccb(Assembler::zero, return_length);
10857 lea(src, Address(src, len, Address::times_2));
10858 lea(dst, Address(dst, len, Address::times_1));
10859 negptr(len);
10860
10861 bind(copy_chars_loop);
10862 load_unsigned_short(result, Address(src, len, Address::times_2));
10863 testl(result, 0xff00); // check if Unicode char
10864 jccb(Assembler::notZero, return_zero);
10865 movb(Address(dst, len, Address::times_1), result); // ASCII char; compress to 1 byte
10866 increment(len);
10867 jcc(Assembler::notZero, copy_chars_loop);
10868
10869 // if compression succeeded, return length
10870 bind(return_length);
10871 pop(result);
10872 jmpb(done);
10873
10874 // if compression failed, return 0
10875 bind(return_zero);
10876 xorl(result, result);
10877 addptr(rsp, wordSize);
10878
10879 bind(done);
10880 }
10881
10882 // Inflate byte[] array to char[].
10883 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
10884 XMMRegister tmp1, Register tmp2) {
10885 Label copy_chars_loop, done;
10886
10887 // rsi: src
10888 // rdi: dst
10889 // rdx: len
10890 // rcx: tmp2
10891
10892 // rsi holds start addr of source byte[] to be inflated
10893 // rdi holds start addr of destination char[]
10894 // rdx holds length
10895 assert_different_registers(src, dst, len, tmp2);
10896
10897 if (UseSSE42Intrinsics) {
10898 assert(UseSSE >= 4, "SSE4 must be enabled for SSE4.2 intrinsics to be available");
10899 Label copy_8_loop, copy_bytes, copy_tail;
10900
10901 movl(tmp2, len);
10902 andl(tmp2, 0x00000007); // tail count (in chars)
10903 andl(len, 0xfffffff8); // vector count (in chars)
10904 jccb(Assembler::zero, copy_tail);
10905
10906 // vectored inflation
10907 lea(src, Address(src, len, Address::times_1));
10908 lea(dst, Address(dst, len, Address::times_2));
10909 negptr(len);
10910
10911 // inflate 8 chars per iter
10912 bind(copy_8_loop);
10913 pmovzxbw(tmp1, Address(src, len, Address::times_1)); // unpack to 8 words
10914 movdqu(Address(dst, len, Address::times_2), tmp1);
10915 addptr(len, 8);
10916 jcc(Assembler::notZero, copy_8_loop);
10917
10918 bind(copy_tail);
10919 movl(len, tmp2);
10920
10921 cmpl(len, 4);
10922 jccb(Assembler::less, copy_bytes);
10923
10924 movdl(tmp1, Address(src, 0)); // load 4 byte chars
10925 pmovzxbw(tmp1, tmp1);
10926 movq(Address(dst, 0), tmp1);
10927 subptr(len, 4);
10928 addptr(src, 4);
10929 addptr(dst, 8);
10930
10931 bind(copy_bytes);
10932 }
10933 testl(len, len);
10934 jccb(Assembler::zero, done);
10935 lea(src, Address(src, len, Address::times_1));
10936 lea(dst, Address(dst, len, Address::times_2));
10937 negptr(len);
10938
10939 // inflate 1 char per iter
10940 bind(copy_chars_loop);
10941 load_unsigned_byte(tmp2, Address(src, len, Address::times_1)); // load byte char
10942 movw(Address(dst, len, Address::times_2), tmp2); // inflate byte char to word
10943 increment(len);
10944 jcc(Assembler::notZero, copy_chars_loop);
10945
10946 bind(done);
10947 }
10948
10949
10950 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
10951 switch (cond) {
10952 // Note some conditions are synonyms for others
10953 case Assembler::zero: return Assembler::notZero;
10954 case Assembler::notZero: return Assembler::zero;
10955 case Assembler::less: return Assembler::greaterEqual;
10956 case Assembler::lessEqual: return Assembler::greater;
10957 case Assembler::greater: return Assembler::lessEqual;
10958 case Assembler::greaterEqual: return Assembler::less;
10959 case Assembler::below: return Assembler::aboveEqual;
10960 case Assembler::belowEqual: return Assembler::above;
10961 case Assembler::above: return Assembler::belowEqual;
10962 case Assembler::aboveEqual: return Assembler::below;
10963 case Assembler::overflow: return Assembler::noOverflow;
10964 case Assembler::noOverflow: return Assembler::overflow;
10965 case Assembler::negative: return Assembler::positive;
10966 case Assembler::positive: return Assembler::negative;
10967 case Assembler::parity: return Assembler::noParity;
10968 case Assembler::noParity: return Assembler::parity;
10969 }
10970 ShouldNotReachHere(); return Assembler::overflow;
10971 }
10972
10973 SkipIfEqual::SkipIfEqual(
10974 MacroAssembler* masm, const bool* flag_addr, bool value) {
10975 _masm = masm;
10976 _masm->cmp8(ExternalAddress((address)flag_addr), value);
10977 _masm->jcc(Assembler::equal, _label);
10978 }
10979
10980 SkipIfEqual::~SkipIfEqual() {
10981 _masm->bind(_label);
10982 }
10983
10984 // 32-bit Windows has its own fast-path implementation
10985 // of get_thread
10986 #if !defined(WIN32) || defined(_LP64)
10987
10988 // This is simply a call to Thread::current()
10989 void MacroAssembler::get_thread(Register thread) {
10990 if (thread != rax) {
10991 push(rax);
10992 }
10993 LP64_ONLY(push(rdi);)
10994 LP64_ONLY(push(rsi);)
10995 push(rdx);
10996 push(rcx);
10997 #ifdef _LP64
10998 push(r8);
10999 push(r9);
11000 push(r10);
11001 push(r11);
11002 #endif
11003
11004 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0);
11005
11006 #ifdef _LP64
11007 pop(r11);
11008 pop(r10);
11009 pop(r9);
11010 pop(r8);
11011 #endif
11012 pop(rcx);
11013 pop(rdx);
11014 LP64_ONLY(pop(rsi);)
11015 LP64_ONLY(pop(rdi);)
11016 if (thread != rax) {
11017 mov(thread, rax);
11018 pop(rax);
11019 }
11020 }
11021
11022 #endif