1 /*
2 * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "compiler/disassembler.hpp"
29 #include "gc/shared/cardTableModRefBS.hpp"
30 #include "gc/shared/collectedHeap.inline.hpp"
31 #include "interpreter/interpreter.hpp"
32 #include "memory/resourceArea.hpp"
33 #include "memory/universe.hpp"
34 #include "oops/klass.inline.hpp"
35 #include "prims/methodHandles.hpp"
36 #include "runtime/biasedLocking.hpp"
37 #include "runtime/interfaceSupport.hpp"
38 #include "runtime/objectMonitor.hpp"
39 #include "runtime/os.hpp"
40 #include "runtime/sharedRuntime.hpp"
41 #include "runtime/stubRoutines.hpp"
42 #include "runtime/thread.hpp"
43 #include "utilities/macros.hpp"
44 #if INCLUDE_ALL_GCS
45 #include "gc/g1/g1CollectedHeap.inline.hpp"
46 #include "gc/g1/g1SATBCardTableModRefBS.hpp"
47 #include "gc/g1/heapRegion.hpp"
48 #endif // INCLUDE_ALL_GCS
49 #include "crc32c.h"
50 #ifdef COMPILER2
51 #include "opto/intrinsicnode.hpp"
52 #endif
53
54 #ifdef PRODUCT
55 #define BLOCK_COMMENT(str) /* nothing */
56 #define STOP(error) stop(error)
57 #else
58 #define BLOCK_COMMENT(str) block_comment(str)
59 #define STOP(error) block_comment(error); stop(error)
60 #endif
61
62 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
63
64 #ifdef ASSERT
65 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
66 #endif
67
68 static Assembler::Condition reverse[] = {
69 Assembler::noOverflow /* overflow = 0x0 */ ,
70 Assembler::overflow /* noOverflow = 0x1 */ ,
71 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
72 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
73 Assembler::notZero /* zero = 0x4, equal = 0x4 */ ,
74 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ ,
75 Assembler::above /* belowEqual = 0x6 */ ,
76 Assembler::belowEqual /* above = 0x7 */ ,
77 Assembler::positive /* negative = 0x8 */ ,
78 Assembler::negative /* positive = 0x9 */ ,
79 Assembler::noParity /* parity = 0xa */ ,
80 Assembler::parity /* noParity = 0xb */ ,
81 Assembler::greaterEqual /* less = 0xc */ ,
82 Assembler::less /* greaterEqual = 0xd */ ,
83 Assembler::greater /* lessEqual = 0xe */ ,
84 Assembler::lessEqual /* greater = 0xf, */
85
86 };
87
88
89 // Implementation of MacroAssembler
90
91 // First all the versions that have distinct versions depending on 32/64 bit
92 // Unless the difference is trivial (1 line or so).
93
94 #ifndef _LP64
95
96 // 32bit versions
97
98 Address MacroAssembler::as_Address(AddressLiteral adr) {
99 return Address(adr.target(), adr.rspec());
100 }
101
102 Address MacroAssembler::as_Address(ArrayAddress adr) {
103 return Address::make_array(adr);
104 }
105
106 void MacroAssembler::call_VM_leaf_base(address entry_point,
107 int number_of_arguments) {
108 call(RuntimeAddress(entry_point));
109 increment(rsp, number_of_arguments * wordSize);
110 }
111
112 void MacroAssembler::cmpklass(Address src1, Metadata* obj) {
113 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
114 }
115
116 void MacroAssembler::cmpklass(Register src1, Metadata* obj) {
117 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
118 }
119
120 void MacroAssembler::cmpoop(Address src1, jobject obj) {
121 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
122 }
123
124 void MacroAssembler::cmpoop(Register src1, jobject obj) {
125 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
126 }
127
128 void MacroAssembler::extend_sign(Register hi, Register lo) {
129 // According to Intel Doc. AP-526, "Integer Divide", p.18.
130 if (VM_Version::is_P6() && hi == rdx && lo == rax) {
131 cdql();
132 } else {
133 movl(hi, lo);
134 sarl(hi, 31);
135 }
136 }
137
138 void MacroAssembler::jC2(Register tmp, Label& L) {
139 // set parity bit if FPU flag C2 is set (via rax)
140 save_rax(tmp);
141 fwait(); fnstsw_ax();
142 sahf();
143 restore_rax(tmp);
144 // branch
145 jcc(Assembler::parity, L);
146 }
147
148 void MacroAssembler::jnC2(Register tmp, Label& L) {
149 // set parity bit if FPU flag C2 is set (via rax)
150 save_rax(tmp);
151 fwait(); fnstsw_ax();
152 sahf();
153 restore_rax(tmp);
154 // branch
155 jcc(Assembler::noParity, L);
156 }
157
158 // 32bit can do a case table jump in one instruction but we no longer allow the base
159 // to be installed in the Address class
160 void MacroAssembler::jump(ArrayAddress entry) {
161 jmp(as_Address(entry));
162 }
163
164 // Note: y_lo will be destroyed
165 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
166 // Long compare for Java (semantics as described in JVM spec.)
167 Label high, low, done;
168
169 cmpl(x_hi, y_hi);
170 jcc(Assembler::less, low);
171 jcc(Assembler::greater, high);
172 // x_hi is the return register
173 xorl(x_hi, x_hi);
174 cmpl(x_lo, y_lo);
175 jcc(Assembler::below, low);
176 jcc(Assembler::equal, done);
177
178 bind(high);
179 xorl(x_hi, x_hi);
180 increment(x_hi);
181 jmp(done);
182
183 bind(low);
184 xorl(x_hi, x_hi);
185 decrementl(x_hi);
186
187 bind(done);
188 }
189
190 void MacroAssembler::lea(Register dst, AddressLiteral src) {
191 mov_literal32(dst, (int32_t)src.target(), src.rspec());
192 }
193
194 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
195 // leal(dst, as_Address(adr));
196 // see note in movl as to why we must use a move
197 mov_literal32(dst, (int32_t) adr.target(), adr.rspec());
198 }
199
200 void MacroAssembler::leave() {
201 mov(rsp, rbp);
202 pop(rbp);
203 }
204
205 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
206 // Multiplication of two Java long values stored on the stack
207 // as illustrated below. Result is in rdx:rax.
208 //
209 // rsp ---> [ ?? ] \ \
210 // .... | y_rsp_offset |
211 // [ y_lo ] / (in bytes) | x_rsp_offset
212 // [ y_hi ] | (in bytes)
213 // .... |
214 // [ x_lo ] /
215 // [ x_hi ]
216 // ....
217 //
218 // Basic idea: lo(result) = lo(x_lo * y_lo)
219 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
220 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
221 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
222 Label quick;
223 // load x_hi, y_hi and check if quick
224 // multiplication is possible
225 movl(rbx, x_hi);
226 movl(rcx, y_hi);
227 movl(rax, rbx);
228 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0
229 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply
230 // do full multiplication
231 // 1st step
232 mull(y_lo); // x_hi * y_lo
233 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx,
234 // 2nd step
235 movl(rax, x_lo);
236 mull(rcx); // x_lo * y_hi
237 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx,
238 // 3rd step
239 bind(quick); // note: rbx, = 0 if quick multiply!
240 movl(rax, x_lo);
241 mull(y_lo); // x_lo * y_lo
242 addl(rdx, rbx); // correct hi(x_lo * y_lo)
243 }
244
245 void MacroAssembler::lneg(Register hi, Register lo) {
246 negl(lo);
247 adcl(hi, 0);
248 negl(hi);
249 }
250
251 void MacroAssembler::lshl(Register hi, Register lo) {
252 // Java shift left long support (semantics as described in JVM spec., p.305)
253 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
254 // shift value is in rcx !
255 assert(hi != rcx, "must not use rcx");
256 assert(lo != rcx, "must not use rcx");
257 const Register s = rcx; // shift count
258 const int n = BitsPerWord;
259 Label L;
260 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
261 cmpl(s, n); // if (s < n)
262 jcc(Assembler::less, L); // else (s >= n)
263 movl(hi, lo); // x := x << n
264 xorl(lo, lo);
265 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
266 bind(L); // s (mod n) < n
267 shldl(hi, lo); // x := x << s
268 shll(lo);
269 }
270
271
272 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
273 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
274 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
275 assert(hi != rcx, "must not use rcx");
276 assert(lo != rcx, "must not use rcx");
277 const Register s = rcx; // shift count
278 const int n = BitsPerWord;
279 Label L;
280 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
281 cmpl(s, n); // if (s < n)
282 jcc(Assembler::less, L); // else (s >= n)
283 movl(lo, hi); // x := x >> n
284 if (sign_extension) sarl(hi, 31);
285 else xorl(hi, hi);
286 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
287 bind(L); // s (mod n) < n
288 shrdl(lo, hi); // x := x >> s
289 if (sign_extension) sarl(hi);
290 else shrl(hi);
291 }
292
293 void MacroAssembler::movoop(Register dst, jobject obj) {
294 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
295 }
296
297 void MacroAssembler::movoop(Address dst, jobject obj) {
298 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
299 }
300
301 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
302 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
303 }
304
305 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
306 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
307 }
308
309 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
310 // scratch register is not used,
311 // it is defined to match parameters of 64-bit version of this method.
312 if (src.is_lval()) {
313 mov_literal32(dst, (intptr_t)src.target(), src.rspec());
314 } else {
315 movl(dst, as_Address(src));
316 }
317 }
318
319 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
320 movl(as_Address(dst), src);
321 }
322
323 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
324 movl(dst, as_Address(src));
325 }
326
327 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
328 void MacroAssembler::movptr(Address dst, intptr_t src) {
329 movl(dst, src);
330 }
331
332
333 void MacroAssembler::pop_callee_saved_registers() {
334 pop(rcx);
335 pop(rdx);
336 pop(rdi);
337 pop(rsi);
338 }
339
340 void MacroAssembler::pop_fTOS() {
341 fld_d(Address(rsp, 0));
342 addl(rsp, 2 * wordSize);
343 }
344
345 void MacroAssembler::push_callee_saved_registers() {
346 push(rsi);
347 push(rdi);
348 push(rdx);
349 push(rcx);
350 }
351
352 void MacroAssembler::push_fTOS() {
353 subl(rsp, 2 * wordSize);
354 fstp_d(Address(rsp, 0));
355 }
356
357
358 void MacroAssembler::pushoop(jobject obj) {
359 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
360 }
361
362 void MacroAssembler::pushklass(Metadata* obj) {
363 push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate());
364 }
365
366 void MacroAssembler::pushptr(AddressLiteral src) {
367 if (src.is_lval()) {
368 push_literal32((int32_t)src.target(), src.rspec());
369 } else {
370 pushl(as_Address(src));
371 }
372 }
373
374 void MacroAssembler::set_word_if_not_zero(Register dst) {
375 xorl(dst, dst);
376 set_byte_if_not_zero(dst);
377 }
378
379 static void pass_arg0(MacroAssembler* masm, Register arg) {
380 masm->push(arg);
381 }
382
383 static void pass_arg1(MacroAssembler* masm, Register arg) {
384 masm->push(arg);
385 }
386
387 static void pass_arg2(MacroAssembler* masm, Register arg) {
388 masm->push(arg);
389 }
390
391 static void pass_arg3(MacroAssembler* masm, Register arg) {
392 masm->push(arg);
393 }
394
395 #ifndef PRODUCT
396 extern "C" void findpc(intptr_t x);
397 #endif
398
399 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
400 // In order to get locks to work, we need to fake a in_VM state
401 JavaThread* thread = JavaThread::current();
402 JavaThreadState saved_state = thread->thread_state();
403 thread->set_thread_state(_thread_in_vm);
404 if (ShowMessageBoxOnError) {
405 JavaThread* thread = JavaThread::current();
406 JavaThreadState saved_state = thread->thread_state();
407 thread->set_thread_state(_thread_in_vm);
408 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
409 ttyLocker ttyl;
410 BytecodeCounter::print();
411 }
412 // To see where a verify_oop failed, get $ebx+40/X for this frame.
413 // This is the value of eip which points to where verify_oop will return.
414 if (os::message_box(msg, "Execution stopped, print registers?")) {
415 print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip);
416 BREAKPOINT;
417 }
418 } else {
419 ttyLocker ttyl;
420 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg);
421 }
422 // Don't assert holding the ttyLock
423 assert(false, "DEBUG MESSAGE: %s", msg);
424 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
425 }
426
427 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) {
428 ttyLocker ttyl;
429 FlagSetting fs(Debugging, true);
430 tty->print_cr("eip = 0x%08x", eip);
431 #ifndef PRODUCT
432 if ((WizardMode || Verbose) && PrintMiscellaneous) {
433 tty->cr();
434 findpc(eip);
435 tty->cr();
436 }
437 #endif
438 #define PRINT_REG(rax) \
439 { tty->print("%s = ", #rax); os::print_location(tty, rax); }
440 PRINT_REG(rax);
441 PRINT_REG(rbx);
442 PRINT_REG(rcx);
443 PRINT_REG(rdx);
444 PRINT_REG(rdi);
445 PRINT_REG(rsi);
446 PRINT_REG(rbp);
447 PRINT_REG(rsp);
448 #undef PRINT_REG
449 // Print some words near top of staack.
450 int* dump_sp = (int*) rsp;
451 for (int col1 = 0; col1 < 8; col1++) {
452 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
453 os::print_location(tty, *dump_sp++);
454 }
455 for (int row = 0; row < 16; row++) {
456 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
457 for (int col = 0; col < 8; col++) {
458 tty->print(" 0x%08x", *dump_sp++);
459 }
460 tty->cr();
461 }
462 // Print some instructions around pc:
463 Disassembler::decode((address)eip-64, (address)eip);
464 tty->print_cr("--------");
465 Disassembler::decode((address)eip, (address)eip+32);
466 }
467
468 void MacroAssembler::stop(const char* msg) {
469 ExternalAddress message((address)msg);
470 // push address of message
471 pushptr(message.addr());
472 { Label L; call(L, relocInfo::none); bind(L); } // push eip
473 pusha(); // push registers
474 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
475 hlt();
476 }
477
478 void MacroAssembler::warn(const char* msg) {
479 push_CPU_state();
480
481 ExternalAddress message((address) msg);
482 // push address of message
483 pushptr(message.addr());
484
485 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
486 addl(rsp, wordSize); // discard argument
487 pop_CPU_state();
488 }
489
490 void MacroAssembler::print_state() {
491 { Label L; call(L, relocInfo::none); bind(L); } // push eip
492 pusha(); // push registers
493
494 push_CPU_state();
495 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32)));
496 pop_CPU_state();
497
498 popa();
499 addl(rsp, wordSize);
500 }
501
502 #else // _LP64
503
504 // 64 bit versions
505
506 Address MacroAssembler::as_Address(AddressLiteral adr) {
507 // amd64 always does this as a pc-rel
508 // we can be absolute or disp based on the instruction type
509 // jmp/call are displacements others are absolute
510 assert(!adr.is_lval(), "must be rval");
511 assert(reachable(adr), "must be");
512 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc());
513
514 }
515
516 Address MacroAssembler::as_Address(ArrayAddress adr) {
517 AddressLiteral base = adr.base();
518 lea(rscratch1, base);
519 Address index = adr.index();
520 assert(index._disp == 0, "must not have disp"); // maybe it can?
521 Address array(rscratch1, index._index, index._scale, index._disp);
522 return array;
523 }
524
525 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
526 Label L, E;
527
528 #ifdef _WIN64
529 // Windows always allocates space for it's register args
530 assert(num_args <= 4, "only register arguments supported");
531 subq(rsp, frame::arg_reg_save_area_bytes);
532 #endif
533
534 // Align stack if necessary
535 testl(rsp, 15);
536 jcc(Assembler::zero, L);
537
538 subq(rsp, 8);
539 {
540 call(RuntimeAddress(entry_point));
541 }
542 addq(rsp, 8);
543 jmp(E);
544
545 bind(L);
546 {
547 call(RuntimeAddress(entry_point));
548 }
549
550 bind(E);
551
552 #ifdef _WIN64
553 // restore stack pointer
554 addq(rsp, frame::arg_reg_save_area_bytes);
555 #endif
556
557 }
558
559 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) {
560 assert(!src2.is_lval(), "should use cmpptr");
561
562 if (reachable(src2)) {
563 cmpq(src1, as_Address(src2));
564 } else {
565 lea(rscratch1, src2);
566 Assembler::cmpq(src1, Address(rscratch1, 0));
567 }
568 }
569
570 int MacroAssembler::corrected_idivq(Register reg) {
571 // Full implementation of Java ldiv and lrem; checks for special
572 // case as described in JVM spec., p.243 & p.271. The function
573 // returns the (pc) offset of the idivl instruction - may be needed
574 // for implicit exceptions.
575 //
576 // normal case special case
577 //
578 // input : rax: dividend min_long
579 // reg: divisor (may not be eax/edx) -1
580 //
581 // output: rax: quotient (= rax idiv reg) min_long
582 // rdx: remainder (= rax irem reg) 0
583 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
584 static const int64_t min_long = 0x8000000000000000;
585 Label normal_case, special_case;
586
587 // check for special case
588 cmp64(rax, ExternalAddress((address) &min_long));
589 jcc(Assembler::notEqual, normal_case);
590 xorl(rdx, rdx); // prepare rdx for possible special case (where
591 // remainder = 0)
592 cmpq(reg, -1);
593 jcc(Assembler::equal, special_case);
594
595 // handle normal case
596 bind(normal_case);
597 cdqq();
598 int idivq_offset = offset();
599 idivq(reg);
600
601 // normal and special case exit
602 bind(special_case);
603
604 return idivq_offset;
605 }
606
607 void MacroAssembler::decrementq(Register reg, int value) {
608 if (value == min_jint) { subq(reg, value); return; }
609 if (value < 0) { incrementq(reg, -value); return; }
610 if (value == 0) { ; return; }
611 if (value == 1 && UseIncDec) { decq(reg) ; return; }
612 /* else */ { subq(reg, value) ; return; }
613 }
614
615 void MacroAssembler::decrementq(Address dst, int value) {
616 if (value == min_jint) { subq(dst, value); return; }
617 if (value < 0) { incrementq(dst, -value); return; }
618 if (value == 0) { ; return; }
619 if (value == 1 && UseIncDec) { decq(dst) ; return; }
620 /* else */ { subq(dst, value) ; return; }
621 }
622
623 void MacroAssembler::incrementq(AddressLiteral dst) {
624 if (reachable(dst)) {
625 incrementq(as_Address(dst));
626 } else {
627 lea(rscratch1, dst);
628 incrementq(Address(rscratch1, 0));
629 }
630 }
631
632 void MacroAssembler::incrementq(Register reg, int value) {
633 if (value == min_jint) { addq(reg, value); return; }
634 if (value < 0) { decrementq(reg, -value); return; }
635 if (value == 0) { ; return; }
636 if (value == 1 && UseIncDec) { incq(reg) ; return; }
637 /* else */ { addq(reg, value) ; return; }
638 }
639
640 void MacroAssembler::incrementq(Address dst, int value) {
641 if (value == min_jint) { addq(dst, value); return; }
642 if (value < 0) { decrementq(dst, -value); return; }
643 if (value == 0) { ; return; }
644 if (value == 1 && UseIncDec) { incq(dst) ; return; }
645 /* else */ { addq(dst, value) ; return; }
646 }
647
648 // 32bit can do a case table jump in one instruction but we no longer allow the base
649 // to be installed in the Address class
650 void MacroAssembler::jump(ArrayAddress entry) {
651 lea(rscratch1, entry.base());
652 Address dispatch = entry.index();
653 assert(dispatch._base == noreg, "must be");
654 dispatch._base = rscratch1;
655 jmp(dispatch);
656 }
657
658 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
659 ShouldNotReachHere(); // 64bit doesn't use two regs
660 cmpq(x_lo, y_lo);
661 }
662
663 void MacroAssembler::lea(Register dst, AddressLiteral src) {
664 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
665 }
666
667 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
668 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec());
669 movptr(dst, rscratch1);
670 }
671
672 void MacroAssembler::leave() {
673 // %%% is this really better? Why not on 32bit too?
674 emit_int8((unsigned char)0xC9); // LEAVE
675 }
676
677 void MacroAssembler::lneg(Register hi, Register lo) {
678 ShouldNotReachHere(); // 64bit doesn't use two regs
679 negq(lo);
680 }
681
682 void MacroAssembler::movoop(Register dst, jobject obj) {
683 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
684 }
685
686 void MacroAssembler::movoop(Address dst, jobject obj) {
687 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate());
688 movq(dst, rscratch1);
689 }
690
691 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
692 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
693 }
694
695 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
696 mov_literal64(rscratch1, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
697 movq(dst, rscratch1);
698 }
699
700 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
701 if (src.is_lval()) {
702 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
703 } else {
704 if (reachable(src)) {
705 movq(dst, as_Address(src));
706 } else {
707 lea(scratch, src);
708 movq(dst, Address(scratch, 0));
709 }
710 }
711 }
712
713 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
714 movq(as_Address(dst), src);
715 }
716
717 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
718 movq(dst, as_Address(src));
719 }
720
721 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
722 void MacroAssembler::movptr(Address dst, intptr_t src) {
723 mov64(rscratch1, src);
724 movq(dst, rscratch1);
725 }
726
727 // These are mostly for initializing NULL
728 void MacroAssembler::movptr(Address dst, int32_t src) {
729 movslq(dst, src);
730 }
731
732 void MacroAssembler::movptr(Register dst, int32_t src) {
733 mov64(dst, (intptr_t)src);
734 }
735
736 void MacroAssembler::pushoop(jobject obj) {
737 movoop(rscratch1, obj);
738 push(rscratch1);
739 }
740
741 void MacroAssembler::pushklass(Metadata* obj) {
742 mov_metadata(rscratch1, obj);
743 push(rscratch1);
744 }
745
746 void MacroAssembler::pushptr(AddressLiteral src) {
747 lea(rscratch1, src);
748 if (src.is_lval()) {
749 push(rscratch1);
750 } else {
751 pushq(Address(rscratch1, 0));
752 }
753 }
754
755 void MacroAssembler::reset_last_Java_frame(bool clear_fp,
756 bool clear_pc) {
757 // we must set sp to zero to clear frame
758 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
759 // must clear fp, so that compiled frames are not confused; it is
760 // possible that we need it only for debugging
761 if (clear_fp) {
762 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
763 }
764
765 if (clear_pc) {
766 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
767 }
768 }
769
770 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
771 Register last_java_fp,
772 address last_java_pc) {
773 // determine last_java_sp register
774 if (!last_java_sp->is_valid()) {
775 last_java_sp = rsp;
776 }
777
778 // last_java_fp is optional
779 if (last_java_fp->is_valid()) {
780 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()),
781 last_java_fp);
782 }
783
784 // last_java_pc is optional
785 if (last_java_pc != NULL) {
786 Address java_pc(r15_thread,
787 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
788 lea(rscratch1, InternalAddress(last_java_pc));
789 movptr(java_pc, rscratch1);
790 }
791
792 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
793 }
794
795 static void pass_arg0(MacroAssembler* masm, Register arg) {
796 if (c_rarg0 != arg ) {
797 masm->mov(c_rarg0, arg);
798 }
799 }
800
801 static void pass_arg1(MacroAssembler* masm, Register arg) {
802 if (c_rarg1 != arg ) {
803 masm->mov(c_rarg1, arg);
804 }
805 }
806
807 static void pass_arg2(MacroAssembler* masm, Register arg) {
808 if (c_rarg2 != arg ) {
809 masm->mov(c_rarg2, arg);
810 }
811 }
812
813 static void pass_arg3(MacroAssembler* masm, Register arg) {
814 if (c_rarg3 != arg ) {
815 masm->mov(c_rarg3, arg);
816 }
817 }
818
819 void MacroAssembler::stop(const char* msg) {
820 address rip = pc();
821 pusha(); // get regs on stack
822 lea(c_rarg0, ExternalAddress((address) msg));
823 lea(c_rarg1, InternalAddress(rip));
824 movq(c_rarg2, rsp); // pass pointer to regs array
825 andq(rsp, -16); // align stack as required by ABI
826 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
827 hlt();
828 }
829
830 void MacroAssembler::warn(const char* msg) {
831 push(rbp);
832 movq(rbp, rsp);
833 andq(rsp, -16); // align stack as required by push_CPU_state and call
834 push_CPU_state(); // keeps alignment at 16 bytes
835 lea(c_rarg0, ExternalAddress((address) msg));
836 call_VM_leaf(CAST_FROM_FN_PTR(address, warning), c_rarg0);
837 pop_CPU_state();
838 mov(rsp, rbp);
839 pop(rbp);
840 }
841
842 void MacroAssembler::print_state() {
843 address rip = pc();
844 pusha(); // get regs on stack
845 push(rbp);
846 movq(rbp, rsp);
847 andq(rsp, -16); // align stack as required by push_CPU_state and call
848 push_CPU_state(); // keeps alignment at 16 bytes
849
850 lea(c_rarg0, InternalAddress(rip));
851 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
852 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
853
854 pop_CPU_state();
855 mov(rsp, rbp);
856 pop(rbp);
857 popa();
858 }
859
860 #ifndef PRODUCT
861 extern "C" void findpc(intptr_t x);
862 #endif
863
864 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
865 // In order to get locks to work, we need to fake a in_VM state
866 if (ShowMessageBoxOnError) {
867 JavaThread* thread = JavaThread::current();
868 JavaThreadState saved_state = thread->thread_state();
869 thread->set_thread_state(_thread_in_vm);
870 #ifndef PRODUCT
871 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
872 ttyLocker ttyl;
873 BytecodeCounter::print();
874 }
875 #endif
876 // To see where a verify_oop failed, get $ebx+40/X for this frame.
877 // XXX correct this offset for amd64
878 // This is the value of eip which points to where verify_oop will return.
879 if (os::message_box(msg, "Execution stopped, print registers?")) {
880 print_state64(pc, regs);
881 BREAKPOINT;
882 assert(false, "start up GDB");
883 }
884 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
885 } else {
886 ttyLocker ttyl;
887 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n",
888 msg);
889 assert(false, "DEBUG MESSAGE: %s", msg);
890 }
891 }
892
893 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
894 ttyLocker ttyl;
895 FlagSetting fs(Debugging, true);
896 tty->print_cr("rip = 0x%016lx", pc);
897 #ifndef PRODUCT
898 tty->cr();
899 findpc(pc);
900 tty->cr();
901 #endif
902 #define PRINT_REG(rax, value) \
903 { tty->print("%s = ", #rax); os::print_location(tty, value); }
904 PRINT_REG(rax, regs[15]);
905 PRINT_REG(rbx, regs[12]);
906 PRINT_REG(rcx, regs[14]);
907 PRINT_REG(rdx, regs[13]);
908 PRINT_REG(rdi, regs[8]);
909 PRINT_REG(rsi, regs[9]);
910 PRINT_REG(rbp, regs[10]);
911 PRINT_REG(rsp, regs[11]);
912 PRINT_REG(r8 , regs[7]);
913 PRINT_REG(r9 , regs[6]);
914 PRINT_REG(r10, regs[5]);
915 PRINT_REG(r11, regs[4]);
916 PRINT_REG(r12, regs[3]);
917 PRINT_REG(r13, regs[2]);
918 PRINT_REG(r14, regs[1]);
919 PRINT_REG(r15, regs[0]);
920 #undef PRINT_REG
921 // Print some words near top of staack.
922 int64_t* rsp = (int64_t*) regs[11];
923 int64_t* dump_sp = rsp;
924 for (int col1 = 0; col1 < 8; col1++) {
925 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp);
926 os::print_location(tty, *dump_sp++);
927 }
928 for (int row = 0; row < 25; row++) {
929 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp);
930 for (int col = 0; col < 4; col++) {
931 tty->print(" 0x%016lx", *dump_sp++);
932 }
933 tty->cr();
934 }
935 // Print some instructions around pc:
936 Disassembler::decode((address)pc-64, (address)pc);
937 tty->print_cr("--------");
938 Disassembler::decode((address)pc, (address)pc+32);
939 }
940
941 #endif // _LP64
942
943 // Now versions that are common to 32/64 bit
944
945 void MacroAssembler::addptr(Register dst, int32_t imm32) {
946 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
947 }
948
949 void MacroAssembler::addptr(Register dst, Register src) {
950 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
951 }
952
953 void MacroAssembler::addptr(Address dst, Register src) {
954 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
955 }
956
957 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) {
958 if (reachable(src)) {
959 Assembler::addsd(dst, as_Address(src));
960 } else {
961 lea(rscratch1, src);
962 Assembler::addsd(dst, Address(rscratch1, 0));
963 }
964 }
965
966 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) {
967 if (reachable(src)) {
968 addss(dst, as_Address(src));
969 } else {
970 lea(rscratch1, src);
971 addss(dst, Address(rscratch1, 0));
972 }
973 }
974
975 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src) {
976 if (reachable(src)) {
977 Assembler::addpd(dst, as_Address(src));
978 } else {
979 lea(rscratch1, src);
980 Assembler::addpd(dst, Address(rscratch1, 0));
981 }
982 }
983
984 void MacroAssembler::align(int modulus) {
985 align(modulus, offset());
986 }
987
988 void MacroAssembler::align(int modulus, int target) {
989 if (target % modulus != 0) {
990 nop(modulus - (target % modulus));
991 }
992 }
993
994 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) {
995 // Used in sign-masking with aligned address.
996 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
997 if (reachable(src)) {
998 Assembler::andpd(dst, as_Address(src));
999 } else {
1000 lea(rscratch1, src);
1001 Assembler::andpd(dst, Address(rscratch1, 0));
1002 }
1003 }
1004
1005 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src) {
1006 // Used in sign-masking with aligned address.
1007 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1008 if (reachable(src)) {
1009 Assembler::andps(dst, as_Address(src));
1010 } else {
1011 lea(rscratch1, src);
1012 Assembler::andps(dst, Address(rscratch1, 0));
1013 }
1014 }
1015
1016 void MacroAssembler::andptr(Register dst, int32_t imm32) {
1017 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
1018 }
1019
1020 void MacroAssembler::atomic_incl(Address counter_addr) {
1021 if (os::is_MP())
1022 lock();
1023 incrementl(counter_addr);
1024 }
1025
1026 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register scr) {
1027 if (reachable(counter_addr)) {
1028 atomic_incl(as_Address(counter_addr));
1029 } else {
1030 lea(scr, counter_addr);
1031 atomic_incl(Address(scr, 0));
1032 }
1033 }
1034
1035 #ifdef _LP64
1036 void MacroAssembler::atomic_incq(Address counter_addr) {
1037 if (os::is_MP())
1038 lock();
1039 incrementq(counter_addr);
1040 }
1041
1042 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register scr) {
1043 if (reachable(counter_addr)) {
1044 atomic_incq(as_Address(counter_addr));
1045 } else {
1046 lea(scr, counter_addr);
1047 atomic_incq(Address(scr, 0));
1048 }
1049 }
1050 #endif
1051
1052 // Writes to stack successive pages until offset reached to check for
1053 // stack overflow + shadow pages. This clobbers tmp.
1054 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
1055 movptr(tmp, rsp);
1056 // Bang stack for total size given plus shadow page size.
1057 // Bang one page at a time because large size can bang beyond yellow and
1058 // red zones.
1059 Label loop;
1060 bind(loop);
1061 movl(Address(tmp, (-os::vm_page_size())), size );
1062 subptr(tmp, os::vm_page_size());
1063 subl(size, os::vm_page_size());
1064 jcc(Assembler::greater, loop);
1065
1066 // Bang down shadow pages too.
1067 // At this point, (tmp-0) is the last address touched, so don't
1068 // touch it again. (It was touched as (tmp-pagesize) but then tmp
1069 // was post-decremented.) Skip this address by starting at i=1, and
1070 // touch a few more pages below. N.B. It is important to touch all
1071 // the way down including all pages in the shadow zone.
1072 for (int i = 1; i < ((int)JavaThread::stack_shadow_zone_size() / os::vm_page_size()); i++) {
1073 // this could be any sized move but this is can be a debugging crumb
1074 // so the bigger the better.
1075 movptr(Address(tmp, (-i*os::vm_page_size())), size );
1076 }
1077 }
1078
1079 void MacroAssembler::reserved_stack_check() {
1080 // testing if reserved zone needs to be enabled
1081 Label no_reserved_zone_enabling;
1082 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
1083 NOT_LP64(get_thread(rsi);)
1084
1085 cmpptr(rsp, Address(thread, JavaThread::reserved_stack_activation_offset()));
1086 jcc(Assembler::below, no_reserved_zone_enabling);
1087
1088 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), thread);
1089 jump(RuntimeAddress(StubRoutines::throw_delayed_StackOverflowError_entry()));
1090 should_not_reach_here();
1091
1092 bind(no_reserved_zone_enabling);
1093 }
1094
1095 int MacroAssembler::biased_locking_enter(Register lock_reg,
1096 Register obj_reg,
1097 Register swap_reg,
1098 Register tmp_reg,
1099 bool swap_reg_contains_mark,
1100 Label& done,
1101 Label* slow_case,
1102 BiasedLockingCounters* counters) {
1103 assert(UseBiasedLocking, "why call this otherwise?");
1104 assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq");
1105 assert(tmp_reg != noreg, "tmp_reg must be supplied");
1106 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg);
1107 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
1108 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes());
1109 NOT_LP64( Address saved_mark_addr(lock_reg, 0); )
1110
1111 if (PrintBiasedLockingStatistics && counters == NULL) {
1112 counters = BiasedLocking::counters();
1113 }
1114 // Biased locking
1115 // See whether the lock is currently biased toward our thread and
1116 // whether the epoch is still valid
1117 // Note that the runtime guarantees sufficient alignment of JavaThread
1118 // pointers to allow age to be placed into low bits
1119 // First check to see whether biasing is even enabled for this object
1120 Label cas_label;
1121 int null_check_offset = -1;
1122 if (!swap_reg_contains_mark) {
1123 null_check_offset = offset();
1124 movptr(swap_reg, mark_addr);
1125 }
1126 movptr(tmp_reg, swap_reg);
1127 andptr(tmp_reg, markOopDesc::biased_lock_mask_in_place);
1128 cmpptr(tmp_reg, markOopDesc::biased_lock_pattern);
1129 jcc(Assembler::notEqual, cas_label);
1130 // The bias pattern is present in the object's header. Need to check
1131 // whether the bias owner and the epoch are both still current.
1132 #ifndef _LP64
1133 // Note that because there is no current thread register on x86_32 we
1134 // need to store off the mark word we read out of the object to
1135 // avoid reloading it and needing to recheck invariants below. This
1136 // store is unfortunate but it makes the overall code shorter and
1137 // simpler.
1138 movptr(saved_mark_addr, swap_reg);
1139 #endif
1140 if (swap_reg_contains_mark) {
1141 null_check_offset = offset();
1142 }
1143 load_prototype_header(tmp_reg, obj_reg);
1144 #ifdef _LP64
1145 orptr(tmp_reg, r15_thread);
1146 xorptr(tmp_reg, swap_reg);
1147 Register header_reg = tmp_reg;
1148 #else
1149 xorptr(tmp_reg, swap_reg);
1150 get_thread(swap_reg);
1151 xorptr(swap_reg, tmp_reg);
1152 Register header_reg = swap_reg;
1153 #endif
1154 andptr(header_reg, ~((int) markOopDesc::age_mask_in_place));
1155 if (counters != NULL) {
1156 cond_inc32(Assembler::zero,
1157 ExternalAddress((address) counters->biased_lock_entry_count_addr()));
1158 }
1159 jcc(Assembler::equal, done);
1160
1161 Label try_revoke_bias;
1162 Label try_rebias;
1163
1164 // At this point we know that the header has the bias pattern and
1165 // that we are not the bias owner in the current epoch. We need to
1166 // figure out more details about the state of the header in order to
1167 // know what operations can be legally performed on the object's
1168 // header.
1169
1170 // If the low three bits in the xor result aren't clear, that means
1171 // the prototype header is no longer biased and we have to revoke
1172 // the bias on this object.
1173 testptr(header_reg, markOopDesc::biased_lock_mask_in_place);
1174 jccb(Assembler::notZero, try_revoke_bias);
1175
1176 // Biasing is still enabled for this data type. See whether the
1177 // epoch of the current bias is still valid, meaning that the epoch
1178 // bits of the mark word are equal to the epoch bits of the
1179 // prototype header. (Note that the prototype header's epoch bits
1180 // only change at a safepoint.) If not, attempt to rebias the object
1181 // toward the current thread. Note that we must be absolutely sure
1182 // that the current epoch is invalid in order to do this because
1183 // otherwise the manipulations it performs on the mark word are
1184 // illegal.
1185 testptr(header_reg, markOopDesc::epoch_mask_in_place);
1186 jccb(Assembler::notZero, try_rebias);
1187
1188 // The epoch of the current bias is still valid but we know nothing
1189 // about the owner; it might be set or it might be clear. Try to
1190 // acquire the bias of the object using an atomic operation. If this
1191 // fails we will go in to the runtime to revoke the object's bias.
1192 // Note that we first construct the presumed unbiased header so we
1193 // don't accidentally blow away another thread's valid bias.
1194 NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1195 andptr(swap_reg,
1196 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
1197 #ifdef _LP64
1198 movptr(tmp_reg, swap_reg);
1199 orptr(tmp_reg, r15_thread);
1200 #else
1201 get_thread(tmp_reg);
1202 orptr(tmp_reg, swap_reg);
1203 #endif
1204 if (os::is_MP()) {
1205 lock();
1206 }
1207 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1208 // If the biasing toward our thread failed, this means that
1209 // another thread succeeded in biasing it toward itself and we
1210 // need to revoke that bias. The revocation will occur in the
1211 // interpreter runtime in the slow case.
1212 if (counters != NULL) {
1213 cond_inc32(Assembler::zero,
1214 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr()));
1215 }
1216 if (slow_case != NULL) {
1217 jcc(Assembler::notZero, *slow_case);
1218 }
1219 jmp(done);
1220
1221 bind(try_rebias);
1222 // At this point we know the epoch has expired, meaning that the
1223 // current "bias owner", if any, is actually invalid. Under these
1224 // circumstances _only_, we are allowed to use the current header's
1225 // value as the comparison value when doing the cas to acquire the
1226 // bias in the current epoch. In other words, we allow transfer of
1227 // the bias from one thread to another directly in this situation.
1228 //
1229 // FIXME: due to a lack of registers we currently blow away the age
1230 // bits in this situation. Should attempt to preserve them.
1231 load_prototype_header(tmp_reg, obj_reg);
1232 #ifdef _LP64
1233 orptr(tmp_reg, r15_thread);
1234 #else
1235 get_thread(swap_reg);
1236 orptr(tmp_reg, swap_reg);
1237 movptr(swap_reg, saved_mark_addr);
1238 #endif
1239 if (os::is_MP()) {
1240 lock();
1241 }
1242 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1243 // If the biasing toward our thread failed, then another thread
1244 // succeeded in biasing it toward itself and we need to revoke that
1245 // bias. The revocation will occur in the runtime in the slow case.
1246 if (counters != NULL) {
1247 cond_inc32(Assembler::zero,
1248 ExternalAddress((address) counters->rebiased_lock_entry_count_addr()));
1249 }
1250 if (slow_case != NULL) {
1251 jcc(Assembler::notZero, *slow_case);
1252 }
1253 jmp(done);
1254
1255 bind(try_revoke_bias);
1256 // The prototype mark in the klass doesn't have the bias bit set any
1257 // more, indicating that objects of this data type are not supposed
1258 // to be biased any more. We are going to try to reset the mark of
1259 // this object to the prototype value and fall through to the
1260 // CAS-based locking scheme. Note that if our CAS fails, it means
1261 // that another thread raced us for the privilege of revoking the
1262 // bias of this particular object, so it's okay to continue in the
1263 // normal locking code.
1264 //
1265 // FIXME: due to a lack of registers we currently blow away the age
1266 // bits in this situation. Should attempt to preserve them.
1267 NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1268 load_prototype_header(tmp_reg, obj_reg);
1269 if (os::is_MP()) {
1270 lock();
1271 }
1272 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1273 // Fall through to the normal CAS-based lock, because no matter what
1274 // the result of the above CAS, some thread must have succeeded in
1275 // removing the bias bit from the object's header.
1276 if (counters != NULL) {
1277 cond_inc32(Assembler::zero,
1278 ExternalAddress((address) counters->revoked_lock_entry_count_addr()));
1279 }
1280
1281 bind(cas_label);
1282
1283 return null_check_offset;
1284 }
1285
1286 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) {
1287 assert(UseBiasedLocking, "why call this otherwise?");
1288
1289 // Check for biased locking unlock case, which is a no-op
1290 // Note: we do not have to check the thread ID for two reasons.
1291 // First, the interpreter checks for IllegalMonitorStateException at
1292 // a higher level. Second, if the bias was revoked while we held the
1293 // lock, the object could not be rebiased toward another thread, so
1294 // the bias bit would be clear.
1295 movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
1296 andptr(temp_reg, markOopDesc::biased_lock_mask_in_place);
1297 cmpptr(temp_reg, markOopDesc::biased_lock_pattern);
1298 jcc(Assembler::equal, done);
1299 }
1300
1301 #ifdef COMPILER2
1302
1303 #if INCLUDE_RTM_OPT
1304
1305 // Update rtm_counters based on abort status
1306 // input: abort_status
1307 // rtm_counters (RTMLockingCounters*)
1308 // flags are killed
1309 void MacroAssembler::rtm_counters_update(Register abort_status, Register rtm_counters) {
1310
1311 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abort_count_offset()));
1312 if (PrintPreciseRTMLockingStatistics) {
1313 for (int i = 0; i < RTMLockingCounters::ABORT_STATUS_LIMIT; i++) {
1314 Label check_abort;
1315 testl(abort_status, (1<<i));
1316 jccb(Assembler::equal, check_abort);
1317 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abortX_count_offset() + (i * sizeof(uintx))));
1318 bind(check_abort);
1319 }
1320 }
1321 }
1322
1323 // Branch if (random & (count-1) != 0), count is 2^n
1324 // tmp, scr and flags are killed
1325 void MacroAssembler::branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel) {
1326 assert(tmp == rax, "");
1327 assert(scr == rdx, "");
1328 rdtsc(); // modifies EDX:EAX
1329 andptr(tmp, count-1);
1330 jccb(Assembler::notZero, brLabel);
1331 }
1332
1333 // Perform abort ratio calculation, set no_rtm bit if high ratio
1334 // input: rtm_counters_Reg (RTMLockingCounters* address)
1335 // tmpReg, rtm_counters_Reg and flags are killed
1336 void MacroAssembler::rtm_abort_ratio_calculation(Register tmpReg,
1337 Register rtm_counters_Reg,
1338 RTMLockingCounters* rtm_counters,
1339 Metadata* method_data) {
1340 Label L_done, L_check_always_rtm1, L_check_always_rtm2;
1341
1342 if (RTMLockingCalculationDelay > 0) {
1343 // Delay calculation
1344 movptr(tmpReg, ExternalAddress((address) RTMLockingCounters::rtm_calculation_flag_addr()), tmpReg);
1345 testptr(tmpReg, tmpReg);
1346 jccb(Assembler::equal, L_done);
1347 }
1348 // Abort ratio calculation only if abort_count > RTMAbortThreshold
1349 // Aborted transactions = abort_count * 100
1350 // All transactions = total_count * RTMTotalCountIncrRate
1351 // Set no_rtm bit if (Aborted transactions >= All transactions * RTMAbortRatio)
1352
1353 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::abort_count_offset()));
1354 cmpptr(tmpReg, RTMAbortThreshold);
1355 jccb(Assembler::below, L_check_always_rtm2);
1356 imulptr(tmpReg, tmpReg, 100);
1357
1358 Register scrReg = rtm_counters_Reg;
1359 movptr(scrReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1360 imulptr(scrReg, scrReg, RTMTotalCountIncrRate);
1361 imulptr(scrReg, scrReg, RTMAbortRatio);
1362 cmpptr(tmpReg, scrReg);
1363 jccb(Assembler::below, L_check_always_rtm1);
1364 if (method_data != NULL) {
1365 // set rtm_state to "no rtm" in MDO
1366 mov_metadata(tmpReg, method_data);
1367 if (os::is_MP()) {
1368 lock();
1369 }
1370 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), NoRTM);
1371 }
1372 jmpb(L_done);
1373 bind(L_check_always_rtm1);
1374 // Reload RTMLockingCounters* address
1375 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1376 bind(L_check_always_rtm2);
1377 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1378 cmpptr(tmpReg, RTMLockingThreshold / RTMTotalCountIncrRate);
1379 jccb(Assembler::below, L_done);
1380 if (method_data != NULL) {
1381 // set rtm_state to "always rtm" in MDO
1382 mov_metadata(tmpReg, method_data);
1383 if (os::is_MP()) {
1384 lock();
1385 }
1386 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), UseRTM);
1387 }
1388 bind(L_done);
1389 }
1390
1391 // Update counters and perform abort ratio calculation
1392 // input: abort_status_Reg
1393 // rtm_counters_Reg, flags are killed
1394 void MacroAssembler::rtm_profiling(Register abort_status_Reg,
1395 Register rtm_counters_Reg,
1396 RTMLockingCounters* rtm_counters,
1397 Metadata* method_data,
1398 bool profile_rtm) {
1399
1400 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1401 // update rtm counters based on rax value at abort
1402 // reads abort_status_Reg, updates flags
1403 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1404 rtm_counters_update(abort_status_Reg, rtm_counters_Reg);
1405 if (profile_rtm) {
1406 // Save abort status because abort_status_Reg is used by following code.
1407 if (RTMRetryCount > 0) {
1408 push(abort_status_Reg);
1409 }
1410 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1411 rtm_abort_ratio_calculation(abort_status_Reg, rtm_counters_Reg, rtm_counters, method_data);
1412 // restore abort status
1413 if (RTMRetryCount > 0) {
1414 pop(abort_status_Reg);
1415 }
1416 }
1417 }
1418
1419 // Retry on abort if abort's status is 0x6: can retry (0x2) | memory conflict (0x4)
1420 // inputs: retry_count_Reg
1421 // : abort_status_Reg
1422 // output: retry_count_Reg decremented by 1
1423 // flags are killed
1424 void MacroAssembler::rtm_retry_lock_on_abort(Register retry_count_Reg, Register abort_status_Reg, Label& retryLabel) {
1425 Label doneRetry;
1426 assert(abort_status_Reg == rax, "");
1427 // The abort reason bits are in eax (see all states in rtmLocking.hpp)
1428 // 0x6 = conflict on which we can retry (0x2) | memory conflict (0x4)
1429 // if reason is in 0x6 and retry count != 0 then retry
1430 andptr(abort_status_Reg, 0x6);
1431 jccb(Assembler::zero, doneRetry);
1432 testl(retry_count_Reg, retry_count_Reg);
1433 jccb(Assembler::zero, doneRetry);
1434 pause();
1435 decrementl(retry_count_Reg);
1436 jmp(retryLabel);
1437 bind(doneRetry);
1438 }
1439
1440 // Spin and retry if lock is busy,
1441 // inputs: box_Reg (monitor address)
1442 // : retry_count_Reg
1443 // output: retry_count_Reg decremented by 1
1444 // : clear z flag if retry count exceeded
1445 // tmp_Reg, scr_Reg, flags are killed
1446 void MacroAssembler::rtm_retry_lock_on_busy(Register retry_count_Reg, Register box_Reg,
1447 Register tmp_Reg, Register scr_Reg, Label& retryLabel) {
1448 Label SpinLoop, SpinExit, doneRetry;
1449 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1450
1451 testl(retry_count_Reg, retry_count_Reg);
1452 jccb(Assembler::zero, doneRetry);
1453 decrementl(retry_count_Reg);
1454 movptr(scr_Reg, RTMSpinLoopCount);
1455
1456 bind(SpinLoop);
1457 pause();
1458 decrementl(scr_Reg);
1459 jccb(Assembler::lessEqual, SpinExit);
1460 movptr(tmp_Reg, Address(box_Reg, owner_offset));
1461 testptr(tmp_Reg, tmp_Reg);
1462 jccb(Assembler::notZero, SpinLoop);
1463
1464 bind(SpinExit);
1465 jmp(retryLabel);
1466 bind(doneRetry);
1467 incrementl(retry_count_Reg); // clear z flag
1468 }
1469
1470 // Use RTM for normal stack locks
1471 // Input: objReg (object to lock)
1472 void MacroAssembler::rtm_stack_locking(Register objReg, Register tmpReg, Register scrReg,
1473 Register retry_on_abort_count_Reg,
1474 RTMLockingCounters* stack_rtm_counters,
1475 Metadata* method_data, bool profile_rtm,
1476 Label& DONE_LABEL, Label& IsInflated) {
1477 assert(UseRTMForStackLocks, "why call this otherwise?");
1478 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
1479 assert(tmpReg == rax, "");
1480 assert(scrReg == rdx, "");
1481 Label L_rtm_retry, L_decrement_retry, L_on_abort;
1482
1483 if (RTMRetryCount > 0) {
1484 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1485 bind(L_rtm_retry);
1486 }
1487 movptr(tmpReg, Address(objReg, 0));
1488 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased
1489 jcc(Assembler::notZero, IsInflated);
1490
1491 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1492 Label L_noincrement;
1493 if (RTMTotalCountIncrRate > 1) {
1494 // tmpReg, scrReg and flags are killed
1495 branch_on_random_using_rdtsc(tmpReg, scrReg, (int)RTMTotalCountIncrRate, L_noincrement);
1496 }
1497 assert(stack_rtm_counters != NULL, "should not be NULL when profiling RTM");
1498 atomic_incptr(ExternalAddress((address)stack_rtm_counters->total_count_addr()), scrReg);
1499 bind(L_noincrement);
1500 }
1501 xbegin(L_on_abort);
1502 movptr(tmpReg, Address(objReg, 0)); // fetch markword
1503 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
1504 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked
1505 jcc(Assembler::equal, DONE_LABEL); // all done if unlocked
1506
1507 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1508 if (UseRTMXendForLockBusy) {
1509 xend();
1510 movptr(abort_status_Reg, 0x2); // Set the abort status to 2 (so we can retry)
1511 jmp(L_decrement_retry);
1512 }
1513 else {
1514 xabort(0);
1515 }
1516 bind(L_on_abort);
1517 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1518 rtm_profiling(abort_status_Reg, scrReg, stack_rtm_counters, method_data, profile_rtm);
1519 }
1520 bind(L_decrement_retry);
1521 if (RTMRetryCount > 0) {
1522 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1523 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1524 }
1525 }
1526
1527 // Use RTM for inflating locks
1528 // inputs: objReg (object to lock)
1529 // boxReg (on-stack box address (displaced header location) - KILLED)
1530 // tmpReg (ObjectMonitor address + markOopDesc::monitor_value)
1531 void MacroAssembler::rtm_inflated_locking(Register objReg, Register boxReg, Register tmpReg,
1532 Register scrReg, Register retry_on_busy_count_Reg,
1533 Register retry_on_abort_count_Reg,
1534 RTMLockingCounters* rtm_counters,
1535 Metadata* method_data, bool profile_rtm,
1536 Label& DONE_LABEL) {
1537 assert(UseRTMLocking, "why call this otherwise?");
1538 assert(tmpReg == rax, "");
1539 assert(scrReg == rdx, "");
1540 Label L_rtm_retry, L_decrement_retry, L_on_abort;
1541 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1542
1543 // Without cast to int32_t a movptr will destroy r10 which is typically obj
1544 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1545 movptr(boxReg, tmpReg); // Save ObjectMonitor address
1546
1547 if (RTMRetryCount > 0) {
1548 movl(retry_on_busy_count_Reg, RTMRetryCount); // Retry on lock busy
1549 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1550 bind(L_rtm_retry);
1551 }
1552 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1553 Label L_noincrement;
1554 if (RTMTotalCountIncrRate > 1) {
1555 // tmpReg, scrReg and flags are killed
1556 branch_on_random_using_rdtsc(tmpReg, scrReg, (int)RTMTotalCountIncrRate, L_noincrement);
1557 }
1558 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1559 atomic_incptr(ExternalAddress((address)rtm_counters->total_count_addr()), scrReg);
1560 bind(L_noincrement);
1561 }
1562 xbegin(L_on_abort);
1563 movptr(tmpReg, Address(objReg, 0));
1564 movptr(tmpReg, Address(tmpReg, owner_offset));
1565 testptr(tmpReg, tmpReg);
1566 jcc(Assembler::zero, DONE_LABEL);
1567 if (UseRTMXendForLockBusy) {
1568 xend();
1569 jmp(L_decrement_retry);
1570 }
1571 else {
1572 xabort(0);
1573 }
1574 bind(L_on_abort);
1575 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1576 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1577 rtm_profiling(abort_status_Reg, scrReg, rtm_counters, method_data, profile_rtm);
1578 }
1579 if (RTMRetryCount > 0) {
1580 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1581 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1582 }
1583
1584 movptr(tmpReg, Address(boxReg, owner_offset)) ;
1585 testptr(tmpReg, tmpReg) ;
1586 jccb(Assembler::notZero, L_decrement_retry) ;
1587
1588 // Appears unlocked - try to swing _owner from null to non-null.
1589 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1590 #ifdef _LP64
1591 Register threadReg = r15_thread;
1592 #else
1593 get_thread(scrReg);
1594 Register threadReg = scrReg;
1595 #endif
1596 if (os::is_MP()) {
1597 lock();
1598 }
1599 cmpxchgptr(threadReg, Address(boxReg, owner_offset)); // Updates tmpReg
1600
1601 if (RTMRetryCount > 0) {
1602 // success done else retry
1603 jccb(Assembler::equal, DONE_LABEL) ;
1604 bind(L_decrement_retry);
1605 // Spin and retry if lock is busy.
1606 rtm_retry_lock_on_busy(retry_on_busy_count_Reg, boxReg, tmpReg, scrReg, L_rtm_retry);
1607 }
1608 else {
1609 bind(L_decrement_retry);
1610 }
1611 }
1612
1613 #endif // INCLUDE_RTM_OPT
1614
1615 // Fast_Lock and Fast_Unlock used by C2
1616
1617 // Because the transitions from emitted code to the runtime
1618 // monitorenter/exit helper stubs are so slow it's critical that
1619 // we inline both the stack-locking fast-path and the inflated fast path.
1620 //
1621 // See also: cmpFastLock and cmpFastUnlock.
1622 //
1623 // What follows is a specialized inline transliteration of the code
1624 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
1625 // another option would be to emit TrySlowEnter and TrySlowExit methods
1626 // at startup-time. These methods would accept arguments as
1627 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
1628 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
1629 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
1630 // In practice, however, the # of lock sites is bounded and is usually small.
1631 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
1632 // if the processor uses simple bimodal branch predictors keyed by EIP
1633 // Since the helper routines would be called from multiple synchronization
1634 // sites.
1635 //
1636 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
1637 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
1638 // to those specialized methods. That'd give us a mostly platform-independent
1639 // implementation that the JITs could optimize and inline at their pleasure.
1640 // Done correctly, the only time we'd need to cross to native could would be
1641 // to park() or unpark() threads. We'd also need a few more unsafe operators
1642 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
1643 // (b) explicit barriers or fence operations.
1644 //
1645 // TODO:
1646 //
1647 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
1648 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
1649 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
1650 // the lock operators would typically be faster than reifying Self.
1651 //
1652 // * Ideally I'd define the primitives as:
1653 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
1654 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
1655 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
1656 // Instead, we're stuck with a rather awkward and brittle register assignments below.
1657 // Furthermore the register assignments are overconstrained, possibly resulting in
1658 // sub-optimal code near the synchronization site.
1659 //
1660 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
1661 // Alternately, use a better sp-proximity test.
1662 //
1663 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
1664 // Either one is sufficient to uniquely identify a thread.
1665 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
1666 //
1667 // * Intrinsify notify() and notifyAll() for the common cases where the
1668 // object is locked by the calling thread but the waitlist is empty.
1669 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
1670 //
1671 // * use jccb and jmpb instead of jcc and jmp to improve code density.
1672 // But beware of excessive branch density on AMD Opterons.
1673 //
1674 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
1675 // or failure of the fast-path. If the fast-path fails then we pass
1676 // control to the slow-path, typically in C. In Fast_Lock and
1677 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
1678 // will emit a conditional branch immediately after the node.
1679 // So we have branches to branches and lots of ICC.ZF games.
1680 // Instead, it might be better to have C2 pass a "FailureLabel"
1681 // into Fast_Lock and Fast_Unlock. In the case of success, control
1682 // will drop through the node. ICC.ZF is undefined at exit.
1683 // In the case of failure, the node will branch directly to the
1684 // FailureLabel
1685
1686
1687 // obj: object to lock
1688 // box: on-stack box address (displaced header location) - KILLED
1689 // rax,: tmp -- KILLED
1690 // scr: tmp -- KILLED
1691 void MacroAssembler::fast_lock(Register objReg, Register boxReg, Register tmpReg,
1692 Register scrReg, Register cx1Reg, Register cx2Reg,
1693 BiasedLockingCounters* counters,
1694 RTMLockingCounters* rtm_counters,
1695 RTMLockingCounters* stack_rtm_counters,
1696 Metadata* method_data,
1697 bool use_rtm, bool profile_rtm) {
1698 // Ensure the register assignments are disjoint
1699 assert(tmpReg == rax, "");
1700
1701 if (use_rtm) {
1702 assert_different_registers(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg);
1703 } else {
1704 assert(cx1Reg == noreg, "");
1705 assert(cx2Reg == noreg, "");
1706 assert_different_registers(objReg, boxReg, tmpReg, scrReg);
1707 }
1708
1709 if (counters != NULL) {
1710 atomic_incl(ExternalAddress((address)counters->total_entry_count_addr()), scrReg);
1711 }
1712 if (EmitSync & 1) {
1713 // set box->dhw = markOopDesc::unused_mark()
1714 // Force all sync thru slow-path: slow_enter() and slow_exit()
1715 movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1716 cmpptr (rsp, (int32_t)NULL_WORD);
1717 } else {
1718 // Possible cases that we'll encounter in fast_lock
1719 // ------------------------------------------------
1720 // * Inflated
1721 // -- unlocked
1722 // -- Locked
1723 // = by self
1724 // = by other
1725 // * biased
1726 // -- by Self
1727 // -- by other
1728 // * neutral
1729 // * stack-locked
1730 // -- by self
1731 // = sp-proximity test hits
1732 // = sp-proximity test generates false-negative
1733 // -- by other
1734 //
1735
1736 Label IsInflated, DONE_LABEL;
1737
1738 // it's stack-locked, biased or neutral
1739 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
1740 // order to reduce the number of conditional branches in the most common cases.
1741 // Beware -- there's a subtle invariant that fetch of the markword
1742 // at [FETCH], below, will never observe a biased encoding (*101b).
1743 // If this invariant is not held we risk exclusion (safety) failure.
1744 if (UseBiasedLocking && !UseOptoBiasInlining) {
1745 biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, counters);
1746 }
1747
1748 #if INCLUDE_RTM_OPT
1749 if (UseRTMForStackLocks && use_rtm) {
1750 rtm_stack_locking(objReg, tmpReg, scrReg, cx2Reg,
1751 stack_rtm_counters, method_data, profile_rtm,
1752 DONE_LABEL, IsInflated);
1753 }
1754 #endif // INCLUDE_RTM_OPT
1755
1756 movptr(tmpReg, Address(objReg, 0)); // [FETCH]
1757 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased
1758 jccb(Assembler::notZero, IsInflated);
1759
1760 // Attempt stack-locking ...
1761 orptr (tmpReg, markOopDesc::unlocked_value);
1762 movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
1763 if (os::is_MP()) {
1764 lock();
1765 }
1766 cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
1767 if (counters != NULL) {
1768 cond_inc32(Assembler::equal,
1769 ExternalAddress((address)counters->fast_path_entry_count_addr()));
1770 }
1771 jcc(Assembler::equal, DONE_LABEL); // Success
1772
1773 // Recursive locking.
1774 // The object is stack-locked: markword contains stack pointer to BasicLock.
1775 // Locked by current thread if difference with current SP is less than one page.
1776 subptr(tmpReg, rsp);
1777 // Next instruction set ZFlag == 1 (Success) if difference is less then one page.
1778 andptr(tmpReg, (int32_t) (NOT_LP64(0xFFFFF003) LP64_ONLY(7 - os::vm_page_size())) );
1779 movptr(Address(boxReg, 0), tmpReg);
1780 if (counters != NULL) {
1781 cond_inc32(Assembler::equal,
1782 ExternalAddress((address)counters->fast_path_entry_count_addr()));
1783 }
1784 jmp(DONE_LABEL);
1785
1786 bind(IsInflated);
1787 // The object is inflated. tmpReg contains pointer to ObjectMonitor* + markOopDesc::monitor_value
1788
1789 #if INCLUDE_RTM_OPT
1790 // Use the same RTM locking code in 32- and 64-bit VM.
1791 if (use_rtm) {
1792 rtm_inflated_locking(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg,
1793 rtm_counters, method_data, profile_rtm, DONE_LABEL);
1794 } else {
1795 #endif // INCLUDE_RTM_OPT
1796
1797 #ifndef _LP64
1798 // The object is inflated.
1799
1800 // boxReg refers to the on-stack BasicLock in the current frame.
1801 // We'd like to write:
1802 // set box->_displaced_header = markOopDesc::unused_mark(). Any non-0 value suffices.
1803 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
1804 // additional latency as we have another ST in the store buffer that must drain.
1805
1806 if (EmitSync & 8192) {
1807 movptr(Address(boxReg, 0), 3); // results in ST-before-CAS penalty
1808 get_thread (scrReg);
1809 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
1810 movptr(tmpReg, NULL_WORD); // consider: xor vs mov
1811 if (os::is_MP()) {
1812 lock();
1813 }
1814 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1815 } else
1816 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
1817 // register juggle because we need tmpReg for cmpxchgptr below
1818 movptr(scrReg, boxReg);
1819 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
1820
1821 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
1822 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
1823 // prefetchw [eax + Offset(_owner)-2]
1824 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1825 }
1826
1827 if ((EmitSync & 64) == 0) {
1828 // Optimistic form: consider XORL tmpReg,tmpReg
1829 movptr(tmpReg, NULL_WORD);
1830 } else {
1831 // Can suffer RTS->RTO upgrades on shared or cold $ lines
1832 // Test-And-CAS instead of CAS
1833 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner
1834 testptr(tmpReg, tmpReg); // Locked ?
1835 jccb (Assembler::notZero, DONE_LABEL);
1836 }
1837
1838 // Appears unlocked - try to swing _owner from null to non-null.
1839 // Ideally, I'd manifest "Self" with get_thread and then attempt
1840 // to CAS the register containing Self into m->Owner.
1841 // But we don't have enough registers, so instead we can either try to CAS
1842 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
1843 // we later store "Self" into m->Owner. Transiently storing a stack address
1844 // (rsp or the address of the box) into m->owner is harmless.
1845 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1846 if (os::is_MP()) {
1847 lock();
1848 }
1849 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1850 movptr(Address(scrReg, 0), 3); // box->_displaced_header = 3
1851 // If we weren't able to swing _owner from NULL to the BasicLock
1852 // then take the slow path.
1853 jccb (Assembler::notZero, DONE_LABEL);
1854 // update _owner from BasicLock to thread
1855 get_thread (scrReg); // beware: clobbers ICCs
1856 movptr(Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), scrReg);
1857 xorptr(boxReg, boxReg); // set icc.ZFlag = 1 to indicate success
1858
1859 // If the CAS fails we can either retry or pass control to the slow-path.
1860 // We use the latter tactic.
1861 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1862 // If the CAS was successful ...
1863 // Self has acquired the lock
1864 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1865 // Intentional fall-through into DONE_LABEL ...
1866 } else {
1867 movptr(Address(boxReg, 0), intptr_t(markOopDesc::unused_mark())); // results in ST-before-CAS penalty
1868 movptr(boxReg, tmpReg);
1869
1870 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
1871 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
1872 // prefetchw [eax + Offset(_owner)-2]
1873 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1874 }
1875
1876 if ((EmitSync & 64) == 0) {
1877 // Optimistic form
1878 xorptr (tmpReg, tmpReg);
1879 } else {
1880 // Can suffer RTS->RTO upgrades on shared or cold $ lines
1881 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner
1882 testptr(tmpReg, tmpReg); // Locked ?
1883 jccb (Assembler::notZero, DONE_LABEL);
1884 }
1885
1886 // Appears unlocked - try to swing _owner from null to non-null.
1887 // Use either "Self" (in scr) or rsp as thread identity in _owner.
1888 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1889 get_thread (scrReg);
1890 if (os::is_MP()) {
1891 lock();
1892 }
1893 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1894
1895 // If the CAS fails we can either retry or pass control to the slow-path.
1896 // We use the latter tactic.
1897 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1898 // If the CAS was successful ...
1899 // Self has acquired the lock
1900 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1901 // Intentional fall-through into DONE_LABEL ...
1902 }
1903 #else // _LP64
1904 // It's inflated
1905 movq(scrReg, tmpReg);
1906 xorq(tmpReg, tmpReg);
1907
1908 if (os::is_MP()) {
1909 lock();
1910 }
1911 cmpxchgptr(r15_thread, Address(scrReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1912 // Unconditionally set box->_displaced_header = markOopDesc::unused_mark().
1913 // Without cast to int32_t movptr will destroy r10 which is typically obj.
1914 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1915 // Intentional fall-through into DONE_LABEL ...
1916 // Propagate ICC.ZF from CAS above into DONE_LABEL.
1917 #endif // _LP64
1918 #if INCLUDE_RTM_OPT
1919 } // use_rtm()
1920 #endif
1921 // DONE_LABEL is a hot target - we'd really like to place it at the
1922 // start of cache line by padding with NOPs.
1923 // See the AMD and Intel software optimization manuals for the
1924 // most efficient "long" NOP encodings.
1925 // Unfortunately none of our alignment mechanisms suffice.
1926 bind(DONE_LABEL);
1927
1928 // At DONE_LABEL the icc ZFlag is set as follows ...
1929 // Fast_Unlock uses the same protocol.
1930 // ZFlag == 1 -> Success
1931 // ZFlag == 0 -> Failure - force control through the slow-path
1932 }
1933 }
1934
1935 // obj: object to unlock
1936 // box: box address (displaced header location), killed. Must be EAX.
1937 // tmp: killed, cannot be obj nor box.
1938 //
1939 // Some commentary on balanced locking:
1940 //
1941 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
1942 // Methods that don't have provably balanced locking are forced to run in the
1943 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
1944 // The interpreter provides two properties:
1945 // I1: At return-time the interpreter automatically and quietly unlocks any
1946 // objects acquired the current activation (frame). Recall that the
1947 // interpreter maintains an on-stack list of locks currently held by
1948 // a frame.
1949 // I2: If a method attempts to unlock an object that is not held by the
1950 // the frame the interpreter throws IMSX.
1951 //
1952 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
1953 // B() doesn't have provably balanced locking so it runs in the interpreter.
1954 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
1955 // is still locked by A().
1956 //
1957 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
1958 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
1959 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
1960 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
1961 // Arguably given that the spec legislates the JNI case as undefined our implementation
1962 // could reasonably *avoid* checking owner in Fast_Unlock().
1963 // In the interest of performance we elide m->Owner==Self check in unlock.
1964 // A perfectly viable alternative is to elide the owner check except when
1965 // Xcheck:jni is enabled.
1966
1967 void MacroAssembler::fast_unlock(Register objReg, Register boxReg, Register tmpReg, bool use_rtm) {
1968 assert(boxReg == rax, "");
1969 assert_different_registers(objReg, boxReg, tmpReg);
1970
1971 if (EmitSync & 4) {
1972 // Disable - inhibit all inlining. Force control through the slow-path
1973 cmpptr (rsp, 0);
1974 } else {
1975 Label DONE_LABEL, Stacked, CheckSucc;
1976
1977 // Critically, the biased locking test must have precedence over
1978 // and appear before the (box->dhw == 0) recursive stack-lock test.
1979 if (UseBiasedLocking && !UseOptoBiasInlining) {
1980 biased_locking_exit(objReg, tmpReg, DONE_LABEL);
1981 }
1982
1983 #if INCLUDE_RTM_OPT
1984 if (UseRTMForStackLocks && use_rtm) {
1985 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
1986 Label L_regular_unlock;
1987 movptr(tmpReg, Address(objReg, 0)); // fetch markword
1988 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
1989 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked
1990 jccb(Assembler::notEqual, L_regular_unlock); // if !HLE RegularLock
1991 xend(); // otherwise end...
1992 jmp(DONE_LABEL); // ... and we're done
1993 bind(L_regular_unlock);
1994 }
1995 #endif
1996
1997 cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD); // Examine the displaced header
1998 jcc (Assembler::zero, DONE_LABEL); // 0 indicates recursive stack-lock
1999 movptr(tmpReg, Address(objReg, 0)); // Examine the object's markword
2000 testptr(tmpReg, markOopDesc::monitor_value); // Inflated?
2001 jccb (Assembler::zero, Stacked);
2002
2003 // It's inflated.
2004 #if INCLUDE_RTM_OPT
2005 if (use_rtm) {
2006 Label L_regular_inflated_unlock;
2007 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
2008 movptr(boxReg, Address(tmpReg, owner_offset));
2009 testptr(boxReg, boxReg);
2010 jccb(Assembler::notZero, L_regular_inflated_unlock);
2011 xend();
2012 jmpb(DONE_LABEL);
2013 bind(L_regular_inflated_unlock);
2014 }
2015 #endif
2016
2017 // Despite our balanced locking property we still check that m->_owner == Self
2018 // as java routines or native JNI code called by this thread might
2019 // have released the lock.
2020 // Refer to the comments in synchronizer.cpp for how we might encode extra
2021 // state in _succ so we can avoid fetching EntryList|cxq.
2022 //
2023 // I'd like to add more cases in fast_lock() and fast_unlock() --
2024 // such as recursive enter and exit -- but we have to be wary of
2025 // I$ bloat, T$ effects and BP$ effects.
2026 //
2027 // If there's no contention try a 1-0 exit. That is, exit without
2028 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
2029 // we detect and recover from the race that the 1-0 exit admits.
2030 //
2031 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
2032 // before it STs null into _owner, releasing the lock. Updates
2033 // to data protected by the critical section must be visible before
2034 // we drop the lock (and thus before any other thread could acquire
2035 // the lock and observe the fields protected by the lock).
2036 // IA32's memory-model is SPO, so STs are ordered with respect to
2037 // each other and there's no need for an explicit barrier (fence).
2038 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
2039 #ifndef _LP64
2040 get_thread (boxReg);
2041 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
2042 // prefetchw [ebx + Offset(_owner)-2]
2043 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2044 }
2045
2046 // Note that we could employ various encoding schemes to reduce
2047 // the number of loads below (currently 4) to just 2 or 3.
2048 // Refer to the comments in synchronizer.cpp.
2049 // In practice the chain of fetches doesn't seem to impact performance, however.
2050 xorptr(boxReg, boxReg);
2051 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
2052 // Attempt to reduce branch density - AMD's branch predictor.
2053 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2054 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2055 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2056 jccb (Assembler::notZero, DONE_LABEL);
2057 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2058 jmpb (DONE_LABEL);
2059 } else {
2060 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2061 jccb (Assembler::notZero, DONE_LABEL);
2062 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2063 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2064 jccb (Assembler::notZero, CheckSucc);
2065 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2066 jmpb (DONE_LABEL);
2067 }
2068
2069 // The Following code fragment (EmitSync & 65536) improves the performance of
2070 // contended applications and contended synchronization microbenchmarks.
2071 // Unfortunately the emission of the code - even though not executed - causes regressions
2072 // in scimark and jetstream, evidently because of $ effects. Replacing the code
2073 // with an equal number of never-executed NOPs results in the same regression.
2074 // We leave it off by default.
2075
2076 if ((EmitSync & 65536) != 0) {
2077 Label LSuccess, LGoSlowPath ;
2078
2079 bind (CheckSucc);
2080
2081 // Optional pre-test ... it's safe to elide this
2082 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2083 jccb(Assembler::zero, LGoSlowPath);
2084
2085 // We have a classic Dekker-style idiom:
2086 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
2087 // There are a number of ways to implement the barrier:
2088 // (1) lock:andl &m->_owner, 0
2089 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
2090 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
2091 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
2092 // (2) If supported, an explicit MFENCE is appealing.
2093 // In older IA32 processors MFENCE is slower than lock:add or xchg
2094 // particularly if the write-buffer is full as might be the case if
2095 // if stores closely precede the fence or fence-equivalent instruction.
2096 // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences
2097 // as the situation has changed with Nehalem and Shanghai.
2098 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
2099 // The $lines underlying the top-of-stack should be in M-state.
2100 // The locked add instruction is serializing, of course.
2101 // (4) Use xchg, which is serializing
2102 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
2103 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
2104 // The integer condition codes will tell us if succ was 0.
2105 // Since _succ and _owner should reside in the same $line and
2106 // we just stored into _owner, it's likely that the $line
2107 // remains in M-state for the lock:orl.
2108 //
2109 // We currently use (3), although it's likely that switching to (2)
2110 // is correct for the future.
2111
2112 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2113 if (os::is_MP()) {
2114 lock(); addptr(Address(rsp, 0), 0);
2115 }
2116 // Ratify _succ remains non-null
2117 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), 0);
2118 jccb (Assembler::notZero, LSuccess);
2119
2120 xorptr(boxReg, boxReg); // box is really EAX
2121 if (os::is_MP()) { lock(); }
2122 cmpxchgptr(rsp, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2123 // There's no successor so we tried to regrab the lock with the
2124 // placeholder value. If that didn't work, then another thread
2125 // grabbed the lock so we're done (and exit was a success).
2126 jccb (Assembler::notEqual, LSuccess);
2127 // Since we're low on registers we installed rsp as a placeholding in _owner.
2128 // Now install Self over rsp. This is safe as we're transitioning from
2129 // non-null to non=null
2130 get_thread (boxReg);
2131 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), boxReg);
2132 // Intentional fall-through into LGoSlowPath ...
2133
2134 bind (LGoSlowPath);
2135 orptr(boxReg, 1); // set ICC.ZF=0 to indicate failure
2136 jmpb (DONE_LABEL);
2137
2138 bind (LSuccess);
2139 xorptr(boxReg, boxReg); // set ICC.ZF=1 to indicate success
2140 jmpb (DONE_LABEL);
2141 }
2142
2143 bind (Stacked);
2144 // It's not inflated and it's not recursively stack-locked and it's not biased.
2145 // It must be stack-locked.
2146 // Try to reset the header to displaced header.
2147 // The "box" value on the stack is stable, so we can reload
2148 // and be assured we observe the same value as above.
2149 movptr(tmpReg, Address(boxReg, 0));
2150 if (os::is_MP()) {
2151 lock();
2152 }
2153 cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
2154 // Intention fall-thru into DONE_LABEL
2155
2156 // DONE_LABEL is a hot target - we'd really like to place it at the
2157 // start of cache line by padding with NOPs.
2158 // See the AMD and Intel software optimization manuals for the
2159 // most efficient "long" NOP encodings.
2160 // Unfortunately none of our alignment mechanisms suffice.
2161 if ((EmitSync & 65536) == 0) {
2162 bind (CheckSucc);
2163 }
2164 #else // _LP64
2165 // It's inflated
2166 if (EmitSync & 1024) {
2167 // Emit code to check that _owner == Self
2168 // We could fold the _owner test into subsequent code more efficiently
2169 // than using a stand-alone check, but since _owner checking is off by
2170 // default we don't bother. We also might consider predicating the
2171 // _owner==Self check on Xcheck:jni or running on a debug build.
2172 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2173 xorptr(boxReg, r15_thread);
2174 } else {
2175 xorptr(boxReg, boxReg);
2176 }
2177 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2178 jccb (Assembler::notZero, DONE_LABEL);
2179 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2180 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2181 jccb (Assembler::notZero, CheckSucc);
2182 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD);
2183 jmpb (DONE_LABEL);
2184
2185 if ((EmitSync & 65536) == 0) {
2186 // Try to avoid passing control into the slow_path ...
2187 Label LSuccess, LGoSlowPath ;
2188 bind (CheckSucc);
2189
2190 // The following optional optimization can be elided if necessary
2191 // Effectively: if (succ == null) goto SlowPath
2192 // The code reduces the window for a race, however,
2193 // and thus benefits performance.
2194 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2195 jccb (Assembler::zero, LGoSlowPath);
2196
2197 xorptr(boxReg, boxReg);
2198 if ((EmitSync & 16) && os::is_MP()) {
2199 xchgptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2200 } else {
2201 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD);
2202 if (os::is_MP()) {
2203 // Memory barrier/fence
2204 // Dekker pivot point -- fulcrum : ST Owner; MEMBAR; LD Succ
2205 // Instead of MFENCE we use a dummy locked add of 0 to the top-of-stack.
2206 // This is faster on Nehalem and AMD Shanghai/Barcelona.
2207 // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences
2208 // We might also restructure (ST Owner=0;barrier;LD _Succ) to
2209 // (mov box,0; xchgq box, &m->Owner; LD _succ) .
2210 lock(); addl(Address(rsp, 0), 0);
2211 }
2212 }
2213 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2214 jccb (Assembler::notZero, LSuccess);
2215
2216 // Rare inopportune interleaving - race.
2217 // The successor vanished in the small window above.
2218 // The lock is contended -- (cxq|EntryList) != null -- and there's no apparent successor.
2219 // We need to ensure progress and succession.
2220 // Try to reacquire the lock.
2221 // If that fails then the new owner is responsible for succession and this
2222 // thread needs to take no further action and can exit via the fast path (success).
2223 // If the re-acquire succeeds then pass control into the slow path.
2224 // As implemented, this latter mode is horrible because we generated more
2225 // coherence traffic on the lock *and* artifically extended the critical section
2226 // length while by virtue of passing control into the slow path.
2227
2228 // box is really RAX -- the following CMPXCHG depends on that binding
2229 // cmpxchg R,[M] is equivalent to rax = CAS(M,rax,R)
2230 if (os::is_MP()) { lock(); }
2231 cmpxchgptr(r15_thread, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2232 // There's no successor so we tried to regrab the lock.
2233 // If that didn't work, then another thread grabbed the
2234 // lock so we're done (and exit was a success).
2235 jccb (Assembler::notEqual, LSuccess);
2236 // Intentional fall-through into slow-path
2237
2238 bind (LGoSlowPath);
2239 orl (boxReg, 1); // set ICC.ZF=0 to indicate failure
2240 jmpb (DONE_LABEL);
2241
2242 bind (LSuccess);
2243 testl (boxReg, 0); // set ICC.ZF=1 to indicate success
2244 jmpb (DONE_LABEL);
2245 }
2246
2247 bind (Stacked);
2248 movptr(tmpReg, Address (boxReg, 0)); // re-fetch
2249 if (os::is_MP()) { lock(); }
2250 cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
2251
2252 if (EmitSync & 65536) {
2253 bind (CheckSucc);
2254 }
2255 #endif
2256 bind(DONE_LABEL);
2257 }
2258 }
2259 #endif // COMPILER2
2260
2261 void MacroAssembler::c2bool(Register x) {
2262 // implements x == 0 ? 0 : 1
2263 // note: must only look at least-significant byte of x
2264 // since C-style booleans are stored in one byte
2265 // only! (was bug)
2266 andl(x, 0xFF);
2267 setb(Assembler::notZero, x);
2268 }
2269
2270 // Wouldn't need if AddressLiteral version had new name
2271 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
2272 Assembler::call(L, rtype);
2273 }
2274
2275 void MacroAssembler::call(Register entry) {
2276 Assembler::call(entry);
2277 }
2278
2279 void MacroAssembler::call(AddressLiteral entry) {
2280 if (reachable(entry)) {
2281 Assembler::call_literal(entry.target(), entry.rspec());
2282 } else {
2283 lea(rscratch1, entry);
2284 Assembler::call(rscratch1);
2285 }
2286 }
2287
2288 void MacroAssembler::ic_call(address entry, jint method_index) {
2289 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
2290 movptr(rax, (intptr_t)Universe::non_oop_word());
2291 call(AddressLiteral(entry, rh));
2292 }
2293
2294 // Implementation of call_VM versions
2295
2296 void MacroAssembler::call_VM(Register oop_result,
2297 address entry_point,
2298 bool check_exceptions) {
2299 Label C, E;
2300 call(C, relocInfo::none);
2301 jmp(E);
2302
2303 bind(C);
2304 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
2305 ret(0);
2306
2307 bind(E);
2308 }
2309
2310 void MacroAssembler::call_VM(Register oop_result,
2311 address entry_point,
2312 Register arg_1,
2313 bool check_exceptions) {
2314 Label C, E;
2315 call(C, relocInfo::none);
2316 jmp(E);
2317
2318 bind(C);
2319 pass_arg1(this, arg_1);
2320 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
2321 ret(0);
2322
2323 bind(E);
2324 }
2325
2326 void MacroAssembler::call_VM(Register oop_result,
2327 address entry_point,
2328 Register arg_1,
2329 Register arg_2,
2330 bool check_exceptions) {
2331 Label C, E;
2332 call(C, relocInfo::none);
2333 jmp(E);
2334
2335 bind(C);
2336
2337 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2338
2339 pass_arg2(this, arg_2);
2340 pass_arg1(this, arg_1);
2341 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
2342 ret(0);
2343
2344 bind(E);
2345 }
2346
2347 void MacroAssembler::call_VM(Register oop_result,
2348 address entry_point,
2349 Register arg_1,
2350 Register arg_2,
2351 Register arg_3,
2352 bool check_exceptions) {
2353 Label C, E;
2354 call(C, relocInfo::none);
2355 jmp(E);
2356
2357 bind(C);
2358
2359 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2360 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2361 pass_arg3(this, arg_3);
2362
2363 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2364 pass_arg2(this, arg_2);
2365
2366 pass_arg1(this, arg_1);
2367 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
2368 ret(0);
2369
2370 bind(E);
2371 }
2372
2373 void MacroAssembler::call_VM(Register oop_result,
2374 Register last_java_sp,
2375 address entry_point,
2376 int number_of_arguments,
2377 bool check_exceptions) {
2378 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2379 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2380 }
2381
2382 void MacroAssembler::call_VM(Register oop_result,
2383 Register last_java_sp,
2384 address entry_point,
2385 Register arg_1,
2386 bool check_exceptions) {
2387 pass_arg1(this, arg_1);
2388 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2389 }
2390
2391 void MacroAssembler::call_VM(Register oop_result,
2392 Register last_java_sp,
2393 address entry_point,
2394 Register arg_1,
2395 Register arg_2,
2396 bool check_exceptions) {
2397
2398 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2399 pass_arg2(this, arg_2);
2400 pass_arg1(this, arg_1);
2401 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2402 }
2403
2404 void MacroAssembler::call_VM(Register oop_result,
2405 Register last_java_sp,
2406 address entry_point,
2407 Register arg_1,
2408 Register arg_2,
2409 Register arg_3,
2410 bool check_exceptions) {
2411 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2412 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2413 pass_arg3(this, arg_3);
2414 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2415 pass_arg2(this, arg_2);
2416 pass_arg1(this, arg_1);
2417 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2418 }
2419
2420 void MacroAssembler::super_call_VM(Register oop_result,
2421 Register last_java_sp,
2422 address entry_point,
2423 int number_of_arguments,
2424 bool check_exceptions) {
2425 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2426 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2427 }
2428
2429 void MacroAssembler::super_call_VM(Register oop_result,
2430 Register last_java_sp,
2431 address entry_point,
2432 Register arg_1,
2433 bool check_exceptions) {
2434 pass_arg1(this, arg_1);
2435 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2436 }
2437
2438 void MacroAssembler::super_call_VM(Register oop_result,
2439 Register last_java_sp,
2440 address entry_point,
2441 Register arg_1,
2442 Register arg_2,
2443 bool check_exceptions) {
2444
2445 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2446 pass_arg2(this, arg_2);
2447 pass_arg1(this, arg_1);
2448 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2449 }
2450
2451 void MacroAssembler::super_call_VM(Register oop_result,
2452 Register last_java_sp,
2453 address entry_point,
2454 Register arg_1,
2455 Register arg_2,
2456 Register arg_3,
2457 bool check_exceptions) {
2458 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2459 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2460 pass_arg3(this, arg_3);
2461 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2462 pass_arg2(this, arg_2);
2463 pass_arg1(this, arg_1);
2464 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2465 }
2466
2467 void MacroAssembler::call_VM_base(Register oop_result,
2468 Register java_thread,
2469 Register last_java_sp,
2470 address entry_point,
2471 int number_of_arguments,
2472 bool check_exceptions) {
2473 // determine java_thread register
2474 if (!java_thread->is_valid()) {
2475 #ifdef _LP64
2476 java_thread = r15_thread;
2477 #else
2478 java_thread = rdi;
2479 get_thread(java_thread);
2480 #endif // LP64
2481 }
2482 // determine last_java_sp register
2483 if (!last_java_sp->is_valid()) {
2484 last_java_sp = rsp;
2485 }
2486 // debugging support
2487 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
2488 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
2489 #ifdef ASSERT
2490 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
2491 // r12 is the heapbase.
2492 LP64_ONLY(if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");)
2493 #endif // ASSERT
2494
2495 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
2496 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
2497
2498 // push java thread (becomes first argument of C function)
2499
2500 NOT_LP64(push(java_thread); number_of_arguments++);
2501 LP64_ONLY(mov(c_rarg0, r15_thread));
2502
2503 // set last Java frame before call
2504 assert(last_java_sp != rbp, "can't use ebp/rbp");
2505
2506 // Only interpreter should have to set fp
2507 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL);
2508
2509 // do the call, remove parameters
2510 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
2511
2512 // restore the thread (cannot use the pushed argument since arguments
2513 // may be overwritten by C code generated by an optimizing compiler);
2514 // however can use the register value directly if it is callee saved.
2515 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
2516 // rdi & rsi (also r15) are callee saved -> nothing to do
2517 #ifdef ASSERT
2518 guarantee(java_thread != rax, "change this code");
2519 push(rax);
2520 { Label L;
2521 get_thread(rax);
2522 cmpptr(java_thread, rax);
2523 jcc(Assembler::equal, L);
2524 STOP("MacroAssembler::call_VM_base: rdi not callee saved?");
2525 bind(L);
2526 }
2527 pop(rax);
2528 #endif
2529 } else {
2530 get_thread(java_thread);
2531 }
2532 // reset last Java frame
2533 // Only interpreter should have to clear fp
2534 reset_last_Java_frame(java_thread, true, false);
2535
2536 // C++ interp handles this in the interpreter
2537 check_and_handle_popframe(java_thread);
2538 check_and_handle_earlyret(java_thread);
2539
2540 if (check_exceptions) {
2541 // check for pending exceptions (java_thread is set upon return)
2542 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD);
2543 #ifndef _LP64
2544 jump_cc(Assembler::notEqual,
2545 RuntimeAddress(StubRoutines::forward_exception_entry()));
2546 #else
2547 // This used to conditionally jump to forward_exception however it is
2548 // possible if we relocate that the branch will not reach. So we must jump
2549 // around so we can always reach
2550
2551 Label ok;
2552 jcc(Assembler::equal, ok);
2553 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
2554 bind(ok);
2555 #endif // LP64
2556 }
2557
2558 // get oop result if there is one and reset the value in the thread
2559 if (oop_result->is_valid()) {
2560 get_vm_result(oop_result, java_thread);
2561 }
2562 }
2563
2564 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
2565
2566 // Calculate the value for last_Java_sp
2567 // somewhat subtle. call_VM does an intermediate call
2568 // which places a return address on the stack just under the
2569 // stack pointer as the user finsihed with it. This allows
2570 // use to retrieve last_Java_pc from last_Java_sp[-1].
2571 // On 32bit we then have to push additional args on the stack to accomplish
2572 // the actual requested call. On 64bit call_VM only can use register args
2573 // so the only extra space is the return address that call_VM created.
2574 // This hopefully explains the calculations here.
2575
2576 #ifdef _LP64
2577 // We've pushed one address, correct last_Java_sp
2578 lea(rax, Address(rsp, wordSize));
2579 #else
2580 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
2581 #endif // LP64
2582
2583 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
2584
2585 }
2586
2587 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
2588 call_VM_leaf_base(entry_point, number_of_arguments);
2589 }
2590
2591 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
2592 pass_arg0(this, arg_0);
2593 call_VM_leaf(entry_point, 1);
2594 }
2595
2596 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2597
2598 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2599 pass_arg1(this, arg_1);
2600 pass_arg0(this, arg_0);
2601 call_VM_leaf(entry_point, 2);
2602 }
2603
2604 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2605 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2606 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2607 pass_arg2(this, arg_2);
2608 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2609 pass_arg1(this, arg_1);
2610 pass_arg0(this, arg_0);
2611 call_VM_leaf(entry_point, 3);
2612 }
2613
2614 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
2615 pass_arg0(this, arg_0);
2616 MacroAssembler::call_VM_leaf_base(entry_point, 1);
2617 }
2618
2619 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2620
2621 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2622 pass_arg1(this, arg_1);
2623 pass_arg0(this, arg_0);
2624 MacroAssembler::call_VM_leaf_base(entry_point, 2);
2625 }
2626
2627 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2628 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2629 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2630 pass_arg2(this, arg_2);
2631 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2632 pass_arg1(this, arg_1);
2633 pass_arg0(this, arg_0);
2634 MacroAssembler::call_VM_leaf_base(entry_point, 3);
2635 }
2636
2637 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
2638 LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg"));
2639 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2640 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2641 pass_arg3(this, arg_3);
2642 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2643 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2644 pass_arg2(this, arg_2);
2645 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2646 pass_arg1(this, arg_1);
2647 pass_arg0(this, arg_0);
2648 MacroAssembler::call_VM_leaf_base(entry_point, 4);
2649 }
2650
2651 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
2652 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
2653 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
2654 verify_oop(oop_result, "broken oop in call_VM_base");
2655 }
2656
2657 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
2658 movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
2659 movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD);
2660 }
2661
2662 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
2663 }
2664
2665 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
2666 }
2667
2668 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) {
2669 if (reachable(src1)) {
2670 cmpl(as_Address(src1), imm);
2671 } else {
2672 lea(rscratch1, src1);
2673 cmpl(Address(rscratch1, 0), imm);
2674 }
2675 }
2676
2677 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) {
2678 assert(!src2.is_lval(), "use cmpptr");
2679 if (reachable(src2)) {
2680 cmpl(src1, as_Address(src2));
2681 } else {
2682 lea(rscratch1, src2);
2683 cmpl(src1, Address(rscratch1, 0));
2684 }
2685 }
2686
2687 void MacroAssembler::cmp32(Register src1, int32_t imm) {
2688 Assembler::cmpl(src1, imm);
2689 }
2690
2691 void MacroAssembler::cmp32(Register src1, Address src2) {
2692 Assembler::cmpl(src1, src2);
2693 }
2694
2695 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2696 ucomisd(opr1, opr2);
2697
2698 Label L;
2699 if (unordered_is_less) {
2700 movl(dst, -1);
2701 jcc(Assembler::parity, L);
2702 jcc(Assembler::below , L);
2703 movl(dst, 0);
2704 jcc(Assembler::equal , L);
2705 increment(dst);
2706 } else { // unordered is greater
2707 movl(dst, 1);
2708 jcc(Assembler::parity, L);
2709 jcc(Assembler::above , L);
2710 movl(dst, 0);
2711 jcc(Assembler::equal , L);
2712 decrementl(dst);
2713 }
2714 bind(L);
2715 }
2716
2717 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2718 ucomiss(opr1, opr2);
2719
2720 Label L;
2721 if (unordered_is_less) {
2722 movl(dst, -1);
2723 jcc(Assembler::parity, L);
2724 jcc(Assembler::below , L);
2725 movl(dst, 0);
2726 jcc(Assembler::equal , L);
2727 increment(dst);
2728 } else { // unordered is greater
2729 movl(dst, 1);
2730 jcc(Assembler::parity, L);
2731 jcc(Assembler::above , L);
2732 movl(dst, 0);
2733 jcc(Assembler::equal , L);
2734 decrementl(dst);
2735 }
2736 bind(L);
2737 }
2738
2739
2740 void MacroAssembler::cmp8(AddressLiteral src1, int imm) {
2741 if (reachable(src1)) {
2742 cmpb(as_Address(src1), imm);
2743 } else {
2744 lea(rscratch1, src1);
2745 cmpb(Address(rscratch1, 0), imm);
2746 }
2747 }
2748
2749 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) {
2750 #ifdef _LP64
2751 if (src2.is_lval()) {
2752 movptr(rscratch1, src2);
2753 Assembler::cmpq(src1, rscratch1);
2754 } else if (reachable(src2)) {
2755 cmpq(src1, as_Address(src2));
2756 } else {
2757 lea(rscratch1, src2);
2758 Assembler::cmpq(src1, Address(rscratch1, 0));
2759 }
2760 #else
2761 if (src2.is_lval()) {
2762 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2763 } else {
2764 cmpl(src1, as_Address(src2));
2765 }
2766 #endif // _LP64
2767 }
2768
2769 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) {
2770 assert(src2.is_lval(), "not a mem-mem compare");
2771 #ifdef _LP64
2772 // moves src2's literal address
2773 movptr(rscratch1, src2);
2774 Assembler::cmpq(src1, rscratch1);
2775 #else
2776 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2777 #endif // _LP64
2778 }
2779
2780 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) {
2781 if (reachable(adr)) {
2782 if (os::is_MP())
2783 lock();
2784 cmpxchgptr(reg, as_Address(adr));
2785 } else {
2786 lea(rscratch1, adr);
2787 if (os::is_MP())
2788 lock();
2789 cmpxchgptr(reg, Address(rscratch1, 0));
2790 }
2791 }
2792
2793 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
2794 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
2795 }
2796
2797 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) {
2798 if (reachable(src)) {
2799 Assembler::comisd(dst, as_Address(src));
2800 } else {
2801 lea(rscratch1, src);
2802 Assembler::comisd(dst, Address(rscratch1, 0));
2803 }
2804 }
2805
2806 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) {
2807 if (reachable(src)) {
2808 Assembler::comiss(dst, as_Address(src));
2809 } else {
2810 lea(rscratch1, src);
2811 Assembler::comiss(dst, Address(rscratch1, 0));
2812 }
2813 }
2814
2815
2816 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) {
2817 Condition negated_cond = negate_condition(cond);
2818 Label L;
2819 jcc(negated_cond, L);
2820 pushf(); // Preserve flags
2821 atomic_incl(counter_addr);
2822 popf();
2823 bind(L);
2824 }
2825
2826 int MacroAssembler::corrected_idivl(Register reg) {
2827 // Full implementation of Java idiv and irem; checks for
2828 // special case as described in JVM spec., p.243 & p.271.
2829 // The function returns the (pc) offset of the idivl
2830 // instruction - may be needed for implicit exceptions.
2831 //
2832 // normal case special case
2833 //
2834 // input : rax,: dividend min_int
2835 // reg: divisor (may not be rax,/rdx) -1
2836 //
2837 // output: rax,: quotient (= rax, idiv reg) min_int
2838 // rdx: remainder (= rax, irem reg) 0
2839 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
2840 const int min_int = 0x80000000;
2841 Label normal_case, special_case;
2842
2843 // check for special case
2844 cmpl(rax, min_int);
2845 jcc(Assembler::notEqual, normal_case);
2846 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
2847 cmpl(reg, -1);
2848 jcc(Assembler::equal, special_case);
2849
2850 // handle normal case
2851 bind(normal_case);
2852 cdql();
2853 int idivl_offset = offset();
2854 idivl(reg);
2855
2856 // normal and special case exit
2857 bind(special_case);
2858
2859 return idivl_offset;
2860 }
2861
2862
2863
2864 void MacroAssembler::decrementl(Register reg, int value) {
2865 if (value == min_jint) {subl(reg, value) ; return; }
2866 if (value < 0) { incrementl(reg, -value); return; }
2867 if (value == 0) { ; return; }
2868 if (value == 1 && UseIncDec) { decl(reg) ; return; }
2869 /* else */ { subl(reg, value) ; return; }
2870 }
2871
2872 void MacroAssembler::decrementl(Address dst, int value) {
2873 if (value == min_jint) {subl(dst, value) ; return; }
2874 if (value < 0) { incrementl(dst, -value); return; }
2875 if (value == 0) { ; return; }
2876 if (value == 1 && UseIncDec) { decl(dst) ; return; }
2877 /* else */ { subl(dst, value) ; return; }
2878 }
2879
2880 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
2881 assert (shift_value > 0, "illegal shift value");
2882 Label _is_positive;
2883 testl (reg, reg);
2884 jcc (Assembler::positive, _is_positive);
2885 int offset = (1 << shift_value) - 1 ;
2886
2887 if (offset == 1) {
2888 incrementl(reg);
2889 } else {
2890 addl(reg, offset);
2891 }
2892
2893 bind (_is_positive);
2894 sarl(reg, shift_value);
2895 }
2896
2897 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) {
2898 if (reachable(src)) {
2899 Assembler::divsd(dst, as_Address(src));
2900 } else {
2901 lea(rscratch1, src);
2902 Assembler::divsd(dst, Address(rscratch1, 0));
2903 }
2904 }
2905
2906 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) {
2907 if (reachable(src)) {
2908 Assembler::divss(dst, as_Address(src));
2909 } else {
2910 lea(rscratch1, src);
2911 Assembler::divss(dst, Address(rscratch1, 0));
2912 }
2913 }
2914
2915 // !defined(COMPILER2) is because of stupid core builds
2916 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2) || INCLUDE_JVMCI
2917 void MacroAssembler::empty_FPU_stack() {
2918 if (VM_Version::supports_mmx()) {
2919 emms();
2920 } else {
2921 for (int i = 8; i-- > 0; ) ffree(i);
2922 }
2923 }
2924 #endif // !LP64 || C1 || !C2 || INCLUDE_JVMCI
2925
2926
2927 // Defines obj, preserves var_size_in_bytes
2928 void MacroAssembler::eden_allocate(Register obj,
2929 Register var_size_in_bytes,
2930 int con_size_in_bytes,
2931 Register t1,
2932 Label& slow_case) {
2933 assert(obj == rax, "obj must be in rax, for cmpxchg");
2934 assert_different_registers(obj, var_size_in_bytes, t1);
2935 if (!Universe::heap()->supports_inline_contig_alloc()) {
2936 jmp(slow_case);
2937 } else {
2938 Register end = t1;
2939 Label retry;
2940 bind(retry);
2941 ExternalAddress heap_top((address) Universe::heap()->top_addr());
2942 movptr(obj, heap_top);
2943 if (var_size_in_bytes == noreg) {
2944 lea(end, Address(obj, con_size_in_bytes));
2945 } else {
2946 lea(end, Address(obj, var_size_in_bytes, Address::times_1));
2947 }
2948 // if end < obj then we wrapped around => object too long => slow case
2949 cmpptr(end, obj);
2950 jcc(Assembler::below, slow_case);
2951 cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr()));
2952 jcc(Assembler::above, slow_case);
2953 // Compare obj with the top addr, and if still equal, store the new top addr in
2954 // end at the address of the top addr pointer. Sets ZF if was equal, and clears
2955 // it otherwise. Use lock prefix for atomicity on MPs.
2956 locked_cmpxchgptr(end, heap_top);
2957 jcc(Assembler::notEqual, retry);
2958 }
2959 }
2960
2961 void MacroAssembler::enter() {
2962 push(rbp);
2963 mov(rbp, rsp);
2964 }
2965
2966 // A 5 byte nop that is safe for patching (see patch_verified_entry)
2967 void MacroAssembler::fat_nop() {
2968 if (UseAddressNop) {
2969 addr_nop_5();
2970 } else {
2971 emit_int8(0x26); // es:
2972 emit_int8(0x2e); // cs:
2973 emit_int8(0x64); // fs:
2974 emit_int8(0x65); // gs:
2975 emit_int8((unsigned char)0x90);
2976 }
2977 }
2978
2979 void MacroAssembler::fcmp(Register tmp) {
2980 fcmp(tmp, 1, true, true);
2981 }
2982
2983 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
2984 assert(!pop_right || pop_left, "usage error");
2985 if (VM_Version::supports_cmov()) {
2986 assert(tmp == noreg, "unneeded temp");
2987 if (pop_left) {
2988 fucomip(index);
2989 } else {
2990 fucomi(index);
2991 }
2992 if (pop_right) {
2993 fpop();
2994 }
2995 } else {
2996 assert(tmp != noreg, "need temp");
2997 if (pop_left) {
2998 if (pop_right) {
2999 fcompp();
3000 } else {
3001 fcomp(index);
3002 }
3003 } else {
3004 fcom(index);
3005 }
3006 // convert FPU condition into eflags condition via rax,
3007 save_rax(tmp);
3008 fwait(); fnstsw_ax();
3009 sahf();
3010 restore_rax(tmp);
3011 }
3012 // condition codes set as follows:
3013 //
3014 // CF (corresponds to C0) if x < y
3015 // PF (corresponds to C2) if unordered
3016 // ZF (corresponds to C3) if x = y
3017 }
3018
3019 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
3020 fcmp2int(dst, unordered_is_less, 1, true, true);
3021 }
3022
3023 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
3024 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
3025 Label L;
3026 if (unordered_is_less) {
3027 movl(dst, -1);
3028 jcc(Assembler::parity, L);
3029 jcc(Assembler::below , L);
3030 movl(dst, 0);
3031 jcc(Assembler::equal , L);
3032 increment(dst);
3033 } else { // unordered is greater
3034 movl(dst, 1);
3035 jcc(Assembler::parity, L);
3036 jcc(Assembler::above , L);
3037 movl(dst, 0);
3038 jcc(Assembler::equal , L);
3039 decrementl(dst);
3040 }
3041 bind(L);
3042 }
3043
3044 void MacroAssembler::fld_d(AddressLiteral src) {
3045 fld_d(as_Address(src));
3046 }
3047
3048 void MacroAssembler::fld_s(AddressLiteral src) {
3049 fld_s(as_Address(src));
3050 }
3051
3052 void MacroAssembler::fld_x(AddressLiteral src) {
3053 Assembler::fld_x(as_Address(src));
3054 }
3055
3056 void MacroAssembler::fldcw(AddressLiteral src) {
3057 Assembler::fldcw(as_Address(src));
3058 }
3059
3060 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src) {
3061 if (reachable(src)) {
3062 Assembler::mulpd(dst, as_Address(src));
3063 } else {
3064 lea(rscratch1, src);
3065 Assembler::mulpd(dst, Address(rscratch1, 0));
3066 }
3067 }
3068
3069 void MacroAssembler::increase_precision() {
3070 subptr(rsp, BytesPerWord);
3071 fnstcw(Address(rsp, 0));
3072 movl(rax, Address(rsp, 0));
3073 orl(rax, 0x300);
3074 push(rax);
3075 fldcw(Address(rsp, 0));
3076 pop(rax);
3077 }
3078
3079 void MacroAssembler::restore_precision() {
3080 fldcw(Address(rsp, 0));
3081 addptr(rsp, BytesPerWord);
3082 }
3083
3084 void MacroAssembler::fpop() {
3085 ffree();
3086 fincstp();
3087 }
3088
3089 void MacroAssembler::load_float(Address src) {
3090 if (UseSSE >= 1) {
3091 movflt(xmm0, src);
3092 } else {
3093 LP64_ONLY(ShouldNotReachHere());
3094 NOT_LP64(fld_s(src));
3095 }
3096 }
3097
3098 void MacroAssembler::store_float(Address dst) {
3099 if (UseSSE >= 1) {
3100 movflt(dst, xmm0);
3101 } else {
3102 LP64_ONLY(ShouldNotReachHere());
3103 NOT_LP64(fstp_s(dst));
3104 }
3105 }
3106
3107 void MacroAssembler::load_double(Address src) {
3108 if (UseSSE >= 2) {
3109 movdbl(xmm0, src);
3110 } else {
3111 LP64_ONLY(ShouldNotReachHere());
3112 NOT_LP64(fld_d(src));
3113 }
3114 }
3115
3116 void MacroAssembler::store_double(Address dst) {
3117 if (UseSSE >= 2) {
3118 movdbl(dst, xmm0);
3119 } else {
3120 LP64_ONLY(ShouldNotReachHere());
3121 NOT_LP64(fstp_d(dst));
3122 }
3123 }
3124
3125 void MacroAssembler::fremr(Register tmp) {
3126 save_rax(tmp);
3127 { Label L;
3128 bind(L);
3129 fprem();
3130 fwait(); fnstsw_ax();
3131 #ifdef _LP64
3132 testl(rax, 0x400);
3133 jcc(Assembler::notEqual, L);
3134 #else
3135 sahf();
3136 jcc(Assembler::parity, L);
3137 #endif // _LP64
3138 }
3139 restore_rax(tmp);
3140 // Result is in ST0.
3141 // Note: fxch & fpop to get rid of ST1
3142 // (otherwise FPU stack could overflow eventually)
3143 fxch(1);
3144 fpop();
3145 }
3146
3147
3148 void MacroAssembler::incrementl(AddressLiteral dst) {
3149 if (reachable(dst)) {
3150 incrementl(as_Address(dst));
3151 } else {
3152 lea(rscratch1, dst);
3153 incrementl(Address(rscratch1, 0));
3154 }
3155 }
3156
3157 void MacroAssembler::incrementl(ArrayAddress dst) {
3158 incrementl(as_Address(dst));
3159 }
3160
3161 void MacroAssembler::incrementl(Register reg, int value) {
3162 if (value == min_jint) {addl(reg, value) ; return; }
3163 if (value < 0) { decrementl(reg, -value); return; }
3164 if (value == 0) { ; return; }
3165 if (value == 1 && UseIncDec) { incl(reg) ; return; }
3166 /* else */ { addl(reg, value) ; return; }
3167 }
3168
3169 void MacroAssembler::incrementl(Address dst, int value) {
3170 if (value == min_jint) {addl(dst, value) ; return; }
3171 if (value < 0) { decrementl(dst, -value); return; }
3172 if (value == 0) { ; return; }
3173 if (value == 1 && UseIncDec) { incl(dst) ; return; }
3174 /* else */ { addl(dst, value) ; return; }
3175 }
3176
3177 void MacroAssembler::jump(AddressLiteral dst) {
3178 if (reachable(dst)) {
3179 jmp_literal(dst.target(), dst.rspec());
3180 } else {
3181 lea(rscratch1, dst);
3182 jmp(rscratch1);
3183 }
3184 }
3185
3186 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) {
3187 if (reachable(dst)) {
3188 InstructionMark im(this);
3189 relocate(dst.reloc());
3190 const int short_size = 2;
3191 const int long_size = 6;
3192 int offs = (intptr_t)dst.target() - ((intptr_t)pc());
3193 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
3194 // 0111 tttn #8-bit disp
3195 emit_int8(0x70 | cc);
3196 emit_int8((offs - short_size) & 0xFF);
3197 } else {
3198 // 0000 1111 1000 tttn #32-bit disp
3199 emit_int8(0x0F);
3200 emit_int8((unsigned char)(0x80 | cc));
3201 emit_int32(offs - long_size);
3202 }
3203 } else {
3204 #ifdef ASSERT
3205 warning("reversing conditional branch");
3206 #endif /* ASSERT */
3207 Label skip;
3208 jccb(reverse[cc], skip);
3209 lea(rscratch1, dst);
3210 Assembler::jmp(rscratch1);
3211 bind(skip);
3212 }
3213 }
3214
3215 void MacroAssembler::ldmxcsr(AddressLiteral src) {
3216 if (reachable(src)) {
3217 Assembler::ldmxcsr(as_Address(src));
3218 } else {
3219 lea(rscratch1, src);
3220 Assembler::ldmxcsr(Address(rscratch1, 0));
3221 }
3222 }
3223
3224 int MacroAssembler::load_signed_byte(Register dst, Address src) {
3225 int off;
3226 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3227 off = offset();
3228 movsbl(dst, src); // movsxb
3229 } else {
3230 off = load_unsigned_byte(dst, src);
3231 shll(dst, 24);
3232 sarl(dst, 24);
3233 }
3234 return off;
3235 }
3236
3237 // Note: load_signed_short used to be called load_signed_word.
3238 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
3239 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
3240 // The term "word" in HotSpot means a 32- or 64-bit machine word.
3241 int MacroAssembler::load_signed_short(Register dst, Address src) {
3242 int off;
3243 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3244 // This is dubious to me since it seems safe to do a signed 16 => 64 bit
3245 // version but this is what 64bit has always done. This seems to imply
3246 // that users are only using 32bits worth.
3247 off = offset();
3248 movswl(dst, src); // movsxw
3249 } else {
3250 off = load_unsigned_short(dst, src);
3251 shll(dst, 16);
3252 sarl(dst, 16);
3253 }
3254 return off;
3255 }
3256
3257 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
3258 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3259 // and "3.9 Partial Register Penalties", p. 22).
3260 int off;
3261 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
3262 off = offset();
3263 movzbl(dst, src); // movzxb
3264 } else {
3265 xorl(dst, dst);
3266 off = offset();
3267 movb(dst, src);
3268 }
3269 return off;
3270 }
3271
3272 // Note: load_unsigned_short used to be called load_unsigned_word.
3273 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
3274 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3275 // and "3.9 Partial Register Penalties", p. 22).
3276 int off;
3277 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
3278 off = offset();
3279 movzwl(dst, src); // movzxw
3280 } else {
3281 xorl(dst, dst);
3282 off = offset();
3283 movw(dst, src);
3284 }
3285 return off;
3286 }
3287
3288 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
3289 switch (size_in_bytes) {
3290 #ifndef _LP64
3291 case 8:
3292 assert(dst2 != noreg, "second dest register required");
3293 movl(dst, src);
3294 movl(dst2, src.plus_disp(BytesPerInt));
3295 break;
3296 #else
3297 case 8: movq(dst, src); break;
3298 #endif
3299 case 4: movl(dst, src); break;
3300 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
3301 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
3302 default: ShouldNotReachHere();
3303 }
3304 }
3305
3306 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
3307 switch (size_in_bytes) {
3308 #ifndef _LP64
3309 case 8:
3310 assert(src2 != noreg, "second source register required");
3311 movl(dst, src);
3312 movl(dst.plus_disp(BytesPerInt), src2);
3313 break;
3314 #else
3315 case 8: movq(dst, src); break;
3316 #endif
3317 case 4: movl(dst, src); break;
3318 case 2: movw(dst, src); break;
3319 case 1: movb(dst, src); break;
3320 default: ShouldNotReachHere();
3321 }
3322 }
3323
3324 void MacroAssembler::mov32(AddressLiteral dst, Register src) {
3325 if (reachable(dst)) {
3326 movl(as_Address(dst), src);
3327 } else {
3328 lea(rscratch1, dst);
3329 movl(Address(rscratch1, 0), src);
3330 }
3331 }
3332
3333 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
3334 if (reachable(src)) {
3335 movl(dst, as_Address(src));
3336 } else {
3337 lea(rscratch1, src);
3338 movl(dst, Address(rscratch1, 0));
3339 }
3340 }
3341
3342 // C++ bool manipulation
3343
3344 void MacroAssembler::movbool(Register dst, Address src) {
3345 if(sizeof(bool) == 1)
3346 movb(dst, src);
3347 else if(sizeof(bool) == 2)
3348 movw(dst, src);
3349 else if(sizeof(bool) == 4)
3350 movl(dst, src);
3351 else
3352 // unsupported
3353 ShouldNotReachHere();
3354 }
3355
3356 void MacroAssembler::movbool(Address dst, bool boolconst) {
3357 if(sizeof(bool) == 1)
3358 movb(dst, (int) boolconst);
3359 else if(sizeof(bool) == 2)
3360 movw(dst, (int) boolconst);
3361 else if(sizeof(bool) == 4)
3362 movl(dst, (int) boolconst);
3363 else
3364 // unsupported
3365 ShouldNotReachHere();
3366 }
3367
3368 void MacroAssembler::movbool(Address dst, Register src) {
3369 if(sizeof(bool) == 1)
3370 movb(dst, src);
3371 else if(sizeof(bool) == 2)
3372 movw(dst, src);
3373 else if(sizeof(bool) == 4)
3374 movl(dst, src);
3375 else
3376 // unsupported
3377 ShouldNotReachHere();
3378 }
3379
3380 void MacroAssembler::movbyte(ArrayAddress dst, int src) {
3381 movb(as_Address(dst), src);
3382 }
3383
3384 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src) {
3385 if (reachable(src)) {
3386 movdl(dst, as_Address(src));
3387 } else {
3388 lea(rscratch1, src);
3389 movdl(dst, Address(rscratch1, 0));
3390 }
3391 }
3392
3393 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src) {
3394 if (reachable(src)) {
3395 movq(dst, as_Address(src));
3396 } else {
3397 lea(rscratch1, src);
3398 movq(dst, Address(rscratch1, 0));
3399 }
3400 }
3401
3402 void MacroAssembler::setvectmask(Register dst, Register src) {
3403 Assembler::movl(dst, 1);
3404 Assembler::shlxl(dst, dst, src);
3405 Assembler::decl(dst);
3406 Assembler::kmovdl(k1, dst);
3407 Assembler::movl(dst, src);
3408 }
3409
3410 void MacroAssembler::restorevectmask() {
3411 Assembler::knotwl(k1, k0);
3412 }
3413
3414 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) {
3415 if (reachable(src)) {
3416 if (UseXmmLoadAndClearUpper) {
3417 movsd (dst, as_Address(src));
3418 } else {
3419 movlpd(dst, as_Address(src));
3420 }
3421 } else {
3422 lea(rscratch1, src);
3423 if (UseXmmLoadAndClearUpper) {
3424 movsd (dst, Address(rscratch1, 0));
3425 } else {
3426 movlpd(dst, Address(rscratch1, 0));
3427 }
3428 }
3429 }
3430
3431 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) {
3432 if (reachable(src)) {
3433 movss(dst, as_Address(src));
3434 } else {
3435 lea(rscratch1, src);
3436 movss(dst, Address(rscratch1, 0));
3437 }
3438 }
3439
3440 void MacroAssembler::movptr(Register dst, Register src) {
3441 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3442 }
3443
3444 void MacroAssembler::movptr(Register dst, Address src) {
3445 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3446 }
3447
3448 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
3449 void MacroAssembler::movptr(Register dst, intptr_t src) {
3450 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src));
3451 }
3452
3453 void MacroAssembler::movptr(Address dst, Register src) {
3454 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3455 }
3456
3457 void MacroAssembler::movdqu(Address dst, XMMRegister src) {
3458 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (src->encoding() > 15)) {
3459 Assembler::vextractf32x4(dst, src, 0);
3460 } else {
3461 Assembler::movdqu(dst, src);
3462 }
3463 }
3464
3465 void MacroAssembler::movdqu(XMMRegister dst, Address src) {
3466 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (dst->encoding() > 15)) {
3467 Assembler::vinsertf32x4(dst, dst, src, 0);
3468 } else {
3469 Assembler::movdqu(dst, src);
3470 }
3471 }
3472
3473 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) {
3474 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3475 Assembler::evmovdqul(dst, src, Assembler::AVX_512bit);
3476 } else {
3477 Assembler::movdqu(dst, src);
3478 }
3479 }
3480
3481 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src) {
3482 if (reachable(src)) {
3483 movdqu(dst, as_Address(src));
3484 } else {
3485 lea(rscratch1, src);
3486 movdqu(dst, Address(rscratch1, 0));
3487 }
3488 }
3489
3490 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) {
3491 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (src->encoding() > 15)) {
3492 vextractf64x4_low(dst, src);
3493 } else {
3494 Assembler::vmovdqu(dst, src);
3495 }
3496 }
3497
3498 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) {
3499 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (dst->encoding() > 15)) {
3500 vinsertf64x4_low(dst, src);
3501 } else {
3502 Assembler::vmovdqu(dst, src);
3503 }
3504 }
3505
3506 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) {
3507 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3508 Assembler::evmovdqul(dst, src, Assembler::AVX_512bit);
3509 }
3510 else {
3511 Assembler::vmovdqu(dst, src);
3512 }
3513 }
3514
3515 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src) {
3516 if (reachable(src)) {
3517 vmovdqu(dst, as_Address(src));
3518 }
3519 else {
3520 lea(rscratch1, src);
3521 vmovdqu(dst, Address(rscratch1, 0));
3522 }
3523 }
3524
3525 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src) {
3526 if (reachable(src)) {
3527 Assembler::movdqa(dst, as_Address(src));
3528 } else {
3529 lea(rscratch1, src);
3530 Assembler::movdqa(dst, Address(rscratch1, 0));
3531 }
3532 }
3533
3534 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) {
3535 if (reachable(src)) {
3536 Assembler::movsd(dst, as_Address(src));
3537 } else {
3538 lea(rscratch1, src);
3539 Assembler::movsd(dst, Address(rscratch1, 0));
3540 }
3541 }
3542
3543 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) {
3544 if (reachable(src)) {
3545 Assembler::movss(dst, as_Address(src));
3546 } else {
3547 lea(rscratch1, src);
3548 Assembler::movss(dst, Address(rscratch1, 0));
3549 }
3550 }
3551
3552 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) {
3553 if (reachable(src)) {
3554 Assembler::mulsd(dst, as_Address(src));
3555 } else {
3556 lea(rscratch1, src);
3557 Assembler::mulsd(dst, Address(rscratch1, 0));
3558 }
3559 }
3560
3561 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) {
3562 if (reachable(src)) {
3563 Assembler::mulss(dst, as_Address(src));
3564 } else {
3565 lea(rscratch1, src);
3566 Assembler::mulss(dst, Address(rscratch1, 0));
3567 }
3568 }
3569
3570 void MacroAssembler::null_check(Register reg, int offset) {
3571 if (needs_explicit_null_check(offset)) {
3572 // provoke OS NULL exception if reg = NULL by
3573 // accessing M[reg] w/o changing any (non-CC) registers
3574 // NOTE: cmpl is plenty here to provoke a segv
3575 cmpptr(rax, Address(reg, 0));
3576 // Note: should probably use testl(rax, Address(reg, 0));
3577 // may be shorter code (however, this version of
3578 // testl needs to be implemented first)
3579 } else {
3580 // nothing to do, (later) access of M[reg + offset]
3581 // will provoke OS NULL exception if reg = NULL
3582 }
3583 }
3584
3585 void MacroAssembler::os_breakpoint() {
3586 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
3587 // (e.g., MSVC can't call ps() otherwise)
3588 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
3589 }
3590
3591 #ifdef _LP64
3592 #define XSTATE_BV 0x200
3593 #endif
3594
3595 void MacroAssembler::pop_CPU_state() {
3596 pop_FPU_state();
3597 pop_IU_state();
3598 }
3599
3600 void MacroAssembler::pop_FPU_state() {
3601 #ifndef _LP64
3602 frstor(Address(rsp, 0));
3603 #else
3604 fxrstor(Address(rsp, 0));
3605 #endif
3606 addptr(rsp, FPUStateSizeInWords * wordSize);
3607 }
3608
3609 void MacroAssembler::pop_IU_state() {
3610 popa();
3611 LP64_ONLY(addq(rsp, 8));
3612 popf();
3613 }
3614
3615 // Save Integer and Float state
3616 // Warning: Stack must be 16 byte aligned (64bit)
3617 void MacroAssembler::push_CPU_state() {
3618 push_IU_state();
3619 push_FPU_state();
3620 }
3621
3622 void MacroAssembler::push_FPU_state() {
3623 subptr(rsp, FPUStateSizeInWords * wordSize);
3624 #ifndef _LP64
3625 fnsave(Address(rsp, 0));
3626 fwait();
3627 #else
3628 fxsave(Address(rsp, 0));
3629 #endif // LP64
3630 }
3631
3632 void MacroAssembler::push_IU_state() {
3633 // Push flags first because pusha kills them
3634 pushf();
3635 // Make sure rsp stays 16-byte aligned
3636 LP64_ONLY(subq(rsp, 8));
3637 pusha();
3638 }
3639
3640 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp, bool clear_pc) {
3641 // determine java_thread register
3642 if (!java_thread->is_valid()) {
3643 java_thread = rdi;
3644 get_thread(java_thread);
3645 }
3646 // we must set sp to zero to clear frame
3647 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
3648 if (clear_fp) {
3649 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
3650 }
3651
3652 if (clear_pc)
3653 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
3654
3655 }
3656
3657 void MacroAssembler::restore_rax(Register tmp) {
3658 if (tmp == noreg) pop(rax);
3659 else if (tmp != rax) mov(rax, tmp);
3660 }
3661
3662 void MacroAssembler::round_to(Register reg, int modulus) {
3663 addptr(reg, modulus - 1);
3664 andptr(reg, -modulus);
3665 }
3666
3667 void MacroAssembler::save_rax(Register tmp) {
3668 if (tmp == noreg) push(rax);
3669 else if (tmp != rax) mov(tmp, rax);
3670 }
3671
3672 // Write serialization page so VM thread can do a pseudo remote membar.
3673 // We use the current thread pointer to calculate a thread specific
3674 // offset to write to within the page. This minimizes bus traffic
3675 // due to cache line collision.
3676 void MacroAssembler::serialize_memory(Register thread, Register tmp) {
3677 movl(tmp, thread);
3678 shrl(tmp, os::get_serialize_page_shift_count());
3679 andl(tmp, (os::vm_page_size() - sizeof(int)));
3680
3681 Address index(noreg, tmp, Address::times_1);
3682 ExternalAddress page(os::get_memory_serialize_page());
3683
3684 // Size of store must match masking code above
3685 movl(as_Address(ArrayAddress(page, index)), tmp);
3686 }
3687
3688 // Calls to C land
3689 //
3690 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
3691 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
3692 // has to be reset to 0. This is required to allow proper stack traversal.
3693 void MacroAssembler::set_last_Java_frame(Register java_thread,
3694 Register last_java_sp,
3695 Register last_java_fp,
3696 address last_java_pc) {
3697 // determine java_thread register
3698 if (!java_thread->is_valid()) {
3699 java_thread = rdi;
3700 get_thread(java_thread);
3701 }
3702 // determine last_java_sp register
3703 if (!last_java_sp->is_valid()) {
3704 last_java_sp = rsp;
3705 }
3706
3707 // last_java_fp is optional
3708
3709 if (last_java_fp->is_valid()) {
3710 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
3711 }
3712
3713 // last_java_pc is optional
3714
3715 if (last_java_pc != NULL) {
3716 lea(Address(java_thread,
3717 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()),
3718 InternalAddress(last_java_pc));
3719
3720 }
3721 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
3722 }
3723
3724 void MacroAssembler::shlptr(Register dst, int imm8) {
3725 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
3726 }
3727
3728 void MacroAssembler::shrptr(Register dst, int imm8) {
3729 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
3730 }
3731
3732 void MacroAssembler::sign_extend_byte(Register reg) {
3733 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
3734 movsbl(reg, reg); // movsxb
3735 } else {
3736 shll(reg, 24);
3737 sarl(reg, 24);
3738 }
3739 }
3740
3741 void MacroAssembler::sign_extend_short(Register reg) {
3742 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3743 movswl(reg, reg); // movsxw
3744 } else {
3745 shll(reg, 16);
3746 sarl(reg, 16);
3747 }
3748 }
3749
3750 void MacroAssembler::testl(Register dst, AddressLiteral src) {
3751 assert(reachable(src), "Address should be reachable");
3752 testl(dst, as_Address(src));
3753 }
3754
3755 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
3756 int dst_enc = dst->encoding();
3757 int src_enc = src->encoding();
3758 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
3759 Assembler::pcmpeqb(dst, src);
3760 } else if ((dst_enc < 16) && (src_enc < 16)) {
3761 Assembler::pcmpeqb(dst, src);
3762 } else if (src_enc < 16) {
3763 subptr(rsp, 64);
3764 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3765 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3766 Assembler::pcmpeqb(xmm0, src);
3767 movdqu(dst, xmm0);
3768 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3769 addptr(rsp, 64);
3770 } else if (dst_enc < 16) {
3771 subptr(rsp, 64);
3772 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3773 evmovdqul(xmm0, src, Assembler::AVX_512bit);
3774 Assembler::pcmpeqb(dst, xmm0);
3775 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3776 addptr(rsp, 64);
3777 } else {
3778 subptr(rsp, 64);
3779 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3780 subptr(rsp, 64);
3781 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
3782 movdqu(xmm0, src);
3783 movdqu(xmm1, dst);
3784 Assembler::pcmpeqb(xmm1, xmm0);
3785 movdqu(dst, xmm1);
3786 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
3787 addptr(rsp, 64);
3788 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3789 addptr(rsp, 64);
3790 }
3791 }
3792
3793 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3794 int dst_enc = dst->encoding();
3795 int src_enc = src->encoding();
3796 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
3797 Assembler::pcmpeqw(dst, src);
3798 } else if ((dst_enc < 16) && (src_enc < 16)) {
3799 Assembler::pcmpeqw(dst, src);
3800 } else if (src_enc < 16) {
3801 subptr(rsp, 64);
3802 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3803 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3804 Assembler::pcmpeqw(xmm0, src);
3805 movdqu(dst, xmm0);
3806 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3807 addptr(rsp, 64);
3808 } else if (dst_enc < 16) {
3809 subptr(rsp, 64);
3810 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3811 evmovdqul(xmm0, src, Assembler::AVX_512bit);
3812 Assembler::pcmpeqw(dst, xmm0);
3813 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3814 addptr(rsp, 64);
3815 } else {
3816 subptr(rsp, 64);
3817 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3818 subptr(rsp, 64);
3819 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
3820 movdqu(xmm0, src);
3821 movdqu(xmm1, dst);
3822 Assembler::pcmpeqw(xmm1, xmm0);
3823 movdqu(dst, xmm1);
3824 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
3825 addptr(rsp, 64);
3826 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3827 addptr(rsp, 64);
3828 }
3829 }
3830
3831 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3832 int dst_enc = dst->encoding();
3833 if (dst_enc < 16) {
3834 Assembler::pcmpestri(dst, src, imm8);
3835 } else {
3836 subptr(rsp, 64);
3837 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3838 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3839 Assembler::pcmpestri(xmm0, src, imm8);
3840 movdqu(dst, xmm0);
3841 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3842 addptr(rsp, 64);
3843 }
3844 }
3845
3846 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3847 int dst_enc = dst->encoding();
3848 int src_enc = src->encoding();
3849 if ((dst_enc < 16) && (src_enc < 16)) {
3850 Assembler::pcmpestri(dst, src, imm8);
3851 } else if (src_enc < 16) {
3852 subptr(rsp, 64);
3853 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3854 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3855 Assembler::pcmpestri(xmm0, src, imm8);
3856 movdqu(dst, xmm0);
3857 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3858 addptr(rsp, 64);
3859 } else if (dst_enc < 16) {
3860 subptr(rsp, 64);
3861 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3862 evmovdqul(xmm0, src, Assembler::AVX_512bit);
3863 Assembler::pcmpestri(dst, xmm0, imm8);
3864 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3865 addptr(rsp, 64);
3866 } else {
3867 subptr(rsp, 64);
3868 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3869 subptr(rsp, 64);
3870 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
3871 movdqu(xmm0, src);
3872 movdqu(xmm1, dst);
3873 Assembler::pcmpestri(xmm1, xmm0, imm8);
3874 movdqu(dst, xmm1);
3875 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
3876 addptr(rsp, 64);
3877 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3878 addptr(rsp, 64);
3879 }
3880 }
3881
3882 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3883 int dst_enc = dst->encoding();
3884 int src_enc = src->encoding();
3885 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
3886 Assembler::pmovzxbw(dst, src);
3887 } else if ((dst_enc < 16) && (src_enc < 16)) {
3888 Assembler::pmovzxbw(dst, src);
3889 } else if (src_enc < 16) {
3890 subptr(rsp, 64);
3891 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3892 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3893 Assembler::pmovzxbw(xmm0, src);
3894 movdqu(dst, xmm0);
3895 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3896 addptr(rsp, 64);
3897 } else if (dst_enc < 16) {
3898 subptr(rsp, 64);
3899 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3900 evmovdqul(xmm0, src, Assembler::AVX_512bit);
3901 Assembler::pmovzxbw(dst, xmm0);
3902 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3903 addptr(rsp, 64);
3904 } else {
3905 subptr(rsp, 64);
3906 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3907 subptr(rsp, 64);
3908 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
3909 movdqu(xmm0, src);
3910 movdqu(xmm1, dst);
3911 Assembler::pmovzxbw(xmm1, xmm0);
3912 movdqu(dst, xmm1);
3913 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
3914 addptr(rsp, 64);
3915 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3916 addptr(rsp, 64);
3917 }
3918 }
3919
3920 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) {
3921 int dst_enc = dst->encoding();
3922 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
3923 Assembler::pmovzxbw(dst, src);
3924 } else if (dst_enc < 16) {
3925 Assembler::pmovzxbw(dst, src);
3926 } else {
3927 subptr(rsp, 64);
3928 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3929 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3930 Assembler::pmovzxbw(xmm0, src);
3931 movdqu(dst, xmm0);
3932 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3933 addptr(rsp, 64);
3934 }
3935 }
3936
3937 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) {
3938 int src_enc = src->encoding();
3939 if (src_enc < 16) {
3940 Assembler::pmovmskb(dst, src);
3941 } else {
3942 subptr(rsp, 64);
3943 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3944 evmovdqul(xmm0, src, Assembler::AVX_512bit);
3945 Assembler::pmovmskb(dst, xmm0);
3946 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3947 addptr(rsp, 64);
3948 }
3949 }
3950
3951 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) {
3952 int dst_enc = dst->encoding();
3953 int src_enc = src->encoding();
3954 if ((dst_enc < 16) && (src_enc < 16)) {
3955 Assembler::ptest(dst, src);
3956 } else if (src_enc < 16) {
3957 subptr(rsp, 64);
3958 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3959 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3960 Assembler::ptest(xmm0, src);
3961 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3962 addptr(rsp, 64);
3963 } else if (dst_enc < 16) {
3964 subptr(rsp, 64);
3965 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3966 evmovdqul(xmm0, src, Assembler::AVX_512bit);
3967 Assembler::ptest(dst, xmm0);
3968 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3969 addptr(rsp, 64);
3970 } else {
3971 subptr(rsp, 64);
3972 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3973 subptr(rsp, 64);
3974 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
3975 movdqu(xmm0, src);
3976 movdqu(xmm1, dst);
3977 Assembler::ptest(xmm1, xmm0);
3978 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
3979 addptr(rsp, 64);
3980 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3981 addptr(rsp, 64);
3982 }
3983 }
3984
3985 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) {
3986 if (reachable(src)) {
3987 Assembler::sqrtsd(dst, as_Address(src));
3988 } else {
3989 lea(rscratch1, src);
3990 Assembler::sqrtsd(dst, Address(rscratch1, 0));
3991 }
3992 }
3993
3994 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) {
3995 if (reachable(src)) {
3996 Assembler::sqrtss(dst, as_Address(src));
3997 } else {
3998 lea(rscratch1, src);
3999 Assembler::sqrtss(dst, Address(rscratch1, 0));
4000 }
4001 }
4002
4003 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) {
4004 if (reachable(src)) {
4005 Assembler::subsd(dst, as_Address(src));
4006 } else {
4007 lea(rscratch1, src);
4008 Assembler::subsd(dst, Address(rscratch1, 0));
4009 }
4010 }
4011
4012 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) {
4013 if (reachable(src)) {
4014 Assembler::subss(dst, as_Address(src));
4015 } else {
4016 lea(rscratch1, src);
4017 Assembler::subss(dst, Address(rscratch1, 0));
4018 }
4019 }
4020
4021 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) {
4022 if (reachable(src)) {
4023 Assembler::ucomisd(dst, as_Address(src));
4024 } else {
4025 lea(rscratch1, src);
4026 Assembler::ucomisd(dst, Address(rscratch1, 0));
4027 }
4028 }
4029
4030 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) {
4031 if (reachable(src)) {
4032 Assembler::ucomiss(dst, as_Address(src));
4033 } else {
4034 lea(rscratch1, src);
4035 Assembler::ucomiss(dst, Address(rscratch1, 0));
4036 }
4037 }
4038
4039 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) {
4040 // Used in sign-bit flipping with aligned address.
4041 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
4042 if (reachable(src)) {
4043 Assembler::xorpd(dst, as_Address(src));
4044 } else {
4045 lea(rscratch1, src);
4046 Assembler::xorpd(dst, Address(rscratch1, 0));
4047 }
4048 }
4049
4050 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) {
4051 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
4052 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
4053 }
4054 else {
4055 Assembler::xorpd(dst, src);
4056 }
4057 }
4058
4059 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) {
4060 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
4061 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
4062 } else {
4063 Assembler::xorps(dst, src);
4064 }
4065 }
4066
4067 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) {
4068 // Used in sign-bit flipping with aligned address.
4069 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
4070 if (reachable(src)) {
4071 Assembler::xorps(dst, as_Address(src));
4072 } else {
4073 lea(rscratch1, src);
4074 Assembler::xorps(dst, Address(rscratch1, 0));
4075 }
4076 }
4077
4078 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src) {
4079 // Used in sign-bit flipping with aligned address.
4080 bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
4081 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
4082 if (reachable(src)) {
4083 Assembler::pshufb(dst, as_Address(src));
4084 } else {
4085 lea(rscratch1, src);
4086 Assembler::pshufb(dst, Address(rscratch1, 0));
4087 }
4088 }
4089
4090 // AVX 3-operands instructions
4091
4092 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4093 if (reachable(src)) {
4094 vaddsd(dst, nds, as_Address(src));
4095 } else {
4096 lea(rscratch1, src);
4097 vaddsd(dst, nds, Address(rscratch1, 0));
4098 }
4099 }
4100
4101 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4102 if (reachable(src)) {
4103 vaddss(dst, nds, as_Address(src));
4104 } else {
4105 lea(rscratch1, src);
4106 vaddss(dst, nds, Address(rscratch1, 0));
4107 }
4108 }
4109
4110 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) {
4111 int dst_enc = dst->encoding();
4112 int nds_enc = nds->encoding();
4113 int src_enc = src->encoding();
4114 if ((dst_enc < 16) && (nds_enc < 16)) {
4115 vandps(dst, nds, negate_field, vector_len);
4116 } else if ((src_enc < 16) && (dst_enc < 16)) {
4117 movss(src, nds);
4118 vandps(dst, src, negate_field, vector_len);
4119 } else if (src_enc < 16) {
4120 movss(src, nds);
4121 vandps(src, src, negate_field, vector_len);
4122 movss(dst, src);
4123 } else if (dst_enc < 16) {
4124 movdqu(src, xmm0);
4125 movss(xmm0, nds);
4126 vandps(dst, xmm0, negate_field, vector_len);
4127 movdqu(xmm0, src);
4128 } else if (nds_enc < 16) {
4129 movdqu(src, xmm0);
4130 vandps(xmm0, nds, negate_field, vector_len);
4131 movss(dst, xmm0);
4132 movdqu(xmm0, src);
4133 } else {
4134 movdqu(src, xmm0);
4135 movss(xmm0, nds);
4136 vandps(xmm0, xmm0, negate_field, vector_len);
4137 movss(dst, xmm0);
4138 movdqu(xmm0, src);
4139 }
4140 }
4141
4142 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) {
4143 int dst_enc = dst->encoding();
4144 int nds_enc = nds->encoding();
4145 int src_enc = src->encoding();
4146 if ((dst_enc < 16) && (nds_enc < 16)) {
4147 vandpd(dst, nds, negate_field, vector_len);
4148 } else if ((src_enc < 16) && (dst_enc < 16)) {
4149 movsd(src, nds);
4150 vandpd(dst, src, negate_field, vector_len);
4151 } else if (src_enc < 16) {
4152 movsd(src, nds);
4153 vandpd(src, src, negate_field, vector_len);
4154 movsd(dst, src);
4155 } else if (dst_enc < 16) {
4156 movdqu(src, xmm0);
4157 movsd(xmm0, nds);
4158 vandpd(dst, xmm0, negate_field, vector_len);
4159 movdqu(xmm0, src);
4160 } else if (nds_enc < 16) {
4161 movdqu(src, xmm0);
4162 vandpd(xmm0, nds, negate_field, vector_len);
4163 movsd(dst, xmm0);
4164 movdqu(xmm0, src);
4165 } else {
4166 movdqu(src, xmm0);
4167 movsd(xmm0, nds);
4168 vandpd(xmm0, xmm0, negate_field, vector_len);
4169 movsd(dst, xmm0);
4170 movdqu(xmm0, src);
4171 }
4172 }
4173
4174 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4175 int dst_enc = dst->encoding();
4176 int nds_enc = nds->encoding();
4177 int src_enc = src->encoding();
4178 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4179 Assembler::vpaddb(dst, nds, src, vector_len);
4180 } else if ((dst_enc < 16) && (src_enc < 16)) {
4181 Assembler::vpaddb(dst, dst, src, vector_len);
4182 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4183 // use nds as scratch for src
4184 evmovdqul(nds, src, Assembler::AVX_512bit);
4185 Assembler::vpaddb(dst, dst, nds, vector_len);
4186 } else if ((src_enc < 16) && (nds_enc < 16)) {
4187 // use nds as scratch for dst
4188 evmovdqul(nds, dst, Assembler::AVX_512bit);
4189 Assembler::vpaddb(nds, nds, src, vector_len);
4190 evmovdqul(dst, nds, Assembler::AVX_512bit);
4191 } else if (dst_enc < 16) {
4192 // use nds as scatch for xmm0 to hold src
4193 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4194 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4195 Assembler::vpaddb(dst, dst, xmm0, vector_len);
4196 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4197 } else {
4198 // worse case scenario, all regs are in the upper bank
4199 subptr(rsp, 64);
4200 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4201 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4202 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4203 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4204 Assembler::vpaddb(xmm0, xmm0, xmm1, vector_len);
4205 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4206 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4207 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4208 addptr(rsp, 64);
4209 }
4210 }
4211
4212 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4213 int dst_enc = dst->encoding();
4214 int nds_enc = nds->encoding();
4215 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4216 Assembler::vpaddb(dst, nds, src, vector_len);
4217 } else if (dst_enc < 16) {
4218 Assembler::vpaddb(dst, dst, src, vector_len);
4219 } else if (nds_enc < 16) {
4220 // implies dst_enc in upper bank with src as scratch
4221 evmovdqul(nds, dst, Assembler::AVX_512bit);
4222 Assembler::vpaddb(nds, nds, src, vector_len);
4223 evmovdqul(dst, nds, Assembler::AVX_512bit);
4224 } else {
4225 // worse case scenario, all regs in upper bank
4226 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4227 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4228 Assembler::vpaddb(xmm0, xmm0, src, vector_len);
4229 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4230 }
4231 }
4232
4233 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4234 int dst_enc = dst->encoding();
4235 int nds_enc = nds->encoding();
4236 int src_enc = src->encoding();
4237 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4238 Assembler::vpaddw(dst, nds, src, vector_len);
4239 } else if ((dst_enc < 16) && (src_enc < 16)) {
4240 Assembler::vpaddw(dst, dst, src, vector_len);
4241 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4242 // use nds as scratch for src
4243 evmovdqul(nds, src, Assembler::AVX_512bit);
4244 Assembler::vpaddw(dst, dst, nds, vector_len);
4245 } else if ((src_enc < 16) && (nds_enc < 16)) {
4246 // use nds as scratch for dst
4247 evmovdqul(nds, dst, Assembler::AVX_512bit);
4248 Assembler::vpaddw(nds, nds, src, vector_len);
4249 evmovdqul(dst, nds, Assembler::AVX_512bit);
4250 } else if (dst_enc < 16) {
4251 // use nds as scatch for xmm0 to hold src
4252 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4253 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4254 Assembler::vpaddw(dst, dst, xmm0, vector_len);
4255 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4256 } else {
4257 // worse case scenario, all regs are in the upper bank
4258 subptr(rsp, 64);
4259 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4260 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4261 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4262 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4263 Assembler::vpaddw(xmm0, xmm0, xmm1, vector_len);
4264 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4265 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4266 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4267 addptr(rsp, 64);
4268 }
4269 }
4270
4271 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4272 int dst_enc = dst->encoding();
4273 int nds_enc = nds->encoding();
4274 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4275 Assembler::vpaddw(dst, nds, src, vector_len);
4276 } else if (dst_enc < 16) {
4277 Assembler::vpaddw(dst, dst, src, vector_len);
4278 } else if (nds_enc < 16) {
4279 // implies dst_enc in upper bank with src as scratch
4280 evmovdqul(nds, dst, Assembler::AVX_512bit);
4281 Assembler::vpaddw(nds, nds, src, vector_len);
4282 evmovdqul(dst, nds, Assembler::AVX_512bit);
4283 } else {
4284 // worse case scenario, all regs in upper bank
4285 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4286 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4287 Assembler::vpaddw(xmm0, xmm0, src, vector_len);
4288 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4289 }
4290 }
4291
4292 void MacroAssembler::vpbroadcastw(XMMRegister dst, XMMRegister src) {
4293 int dst_enc = dst->encoding();
4294 int src_enc = src->encoding();
4295 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4296 Assembler::vpbroadcastw(dst, src);
4297 } else if ((dst_enc < 16) && (src_enc < 16)) {
4298 Assembler::vpbroadcastw(dst, src);
4299 } else if (src_enc < 16) {
4300 subptr(rsp, 64);
4301 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4302 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4303 Assembler::vpbroadcastw(xmm0, src);
4304 movdqu(dst, xmm0);
4305 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4306 addptr(rsp, 64);
4307 } else if (dst_enc < 16) {
4308 subptr(rsp, 64);
4309 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4310 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4311 Assembler::vpbroadcastw(dst, xmm0);
4312 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4313 addptr(rsp, 64);
4314 } else {
4315 subptr(rsp, 64);
4316 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4317 subptr(rsp, 64);
4318 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4319 movdqu(xmm0, src);
4320 movdqu(xmm1, dst);
4321 Assembler::vpbroadcastw(xmm1, xmm0);
4322 movdqu(dst, xmm1);
4323 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4324 addptr(rsp, 64);
4325 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4326 addptr(rsp, 64);
4327 }
4328 }
4329
4330 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4331 int dst_enc = dst->encoding();
4332 int nds_enc = nds->encoding();
4333 int src_enc = src->encoding();
4334 assert(dst_enc == nds_enc, "");
4335 if ((dst_enc < 16) && (src_enc < 16)) {
4336 Assembler::vpcmpeqb(dst, nds, src, vector_len);
4337 } else if (src_enc < 16) {
4338 subptr(rsp, 64);
4339 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4340 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4341 Assembler::vpcmpeqb(xmm0, xmm0, src, vector_len);
4342 movdqu(dst, xmm0);
4343 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4344 addptr(rsp, 64);
4345 } else if (dst_enc < 16) {
4346 subptr(rsp, 64);
4347 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4348 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4349 Assembler::vpcmpeqb(dst, dst, xmm0, vector_len);
4350 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4351 addptr(rsp, 64);
4352 } else {
4353 subptr(rsp, 64);
4354 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4355 subptr(rsp, 64);
4356 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4357 movdqu(xmm0, src);
4358 movdqu(xmm1, dst);
4359 Assembler::vpcmpeqb(xmm1, xmm1, xmm0, vector_len);
4360 movdqu(dst, xmm1);
4361 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4362 addptr(rsp, 64);
4363 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4364 addptr(rsp, 64);
4365 }
4366 }
4367
4368 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4369 int dst_enc = dst->encoding();
4370 int nds_enc = nds->encoding();
4371 int src_enc = src->encoding();
4372 assert(dst_enc == nds_enc, "");
4373 if ((dst_enc < 16) && (src_enc < 16)) {
4374 Assembler::vpcmpeqw(dst, nds, src, vector_len);
4375 } else if (src_enc < 16) {
4376 subptr(rsp, 64);
4377 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4378 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4379 Assembler::vpcmpeqw(xmm0, xmm0, src, vector_len);
4380 movdqu(dst, xmm0);
4381 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4382 addptr(rsp, 64);
4383 } else if (dst_enc < 16) {
4384 subptr(rsp, 64);
4385 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4386 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4387 Assembler::vpcmpeqw(dst, dst, xmm0, vector_len);
4388 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4389 addptr(rsp, 64);
4390 } else {
4391 subptr(rsp, 64);
4392 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4393 subptr(rsp, 64);
4394 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4395 movdqu(xmm0, src);
4396 movdqu(xmm1, dst);
4397 Assembler::vpcmpeqw(xmm1, xmm1, xmm0, vector_len);
4398 movdqu(dst, xmm1);
4399 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4400 addptr(rsp, 64);
4401 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4402 addptr(rsp, 64);
4403 }
4404 }
4405
4406 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
4407 int dst_enc = dst->encoding();
4408 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4409 Assembler::vpmovzxbw(dst, src, vector_len);
4410 } else if (dst_enc < 16) {
4411 Assembler::vpmovzxbw(dst, src, vector_len);
4412 } else {
4413 subptr(rsp, 64);
4414 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4415 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4416 Assembler::vpmovzxbw(xmm0, src, vector_len);
4417 movdqu(dst, xmm0);
4418 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4419 addptr(rsp, 64);
4420 }
4421 }
4422
4423 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src) {
4424 int src_enc = src->encoding();
4425 if (src_enc < 16) {
4426 Assembler::vpmovmskb(dst, src);
4427 } else {
4428 subptr(rsp, 64);
4429 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4430 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4431 Assembler::vpmovmskb(dst, xmm0);
4432 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4433 addptr(rsp, 64);
4434 }
4435 }
4436
4437 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4438 int dst_enc = dst->encoding();
4439 int nds_enc = nds->encoding();
4440 int src_enc = src->encoding();
4441 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4442 Assembler::vpmullw(dst, nds, src, vector_len);
4443 } else if ((dst_enc < 16) && (src_enc < 16)) {
4444 Assembler::vpmullw(dst, dst, src, vector_len);
4445 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4446 // use nds as scratch for src
4447 evmovdqul(nds, src, Assembler::AVX_512bit);
4448 Assembler::vpmullw(dst, dst, nds, vector_len);
4449 } else if ((src_enc < 16) && (nds_enc < 16)) {
4450 // use nds as scratch for dst
4451 evmovdqul(nds, dst, Assembler::AVX_512bit);
4452 Assembler::vpmullw(nds, nds, src, vector_len);
4453 evmovdqul(dst, nds, Assembler::AVX_512bit);
4454 } else if (dst_enc < 16) {
4455 // use nds as scatch for xmm0 to hold src
4456 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4457 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4458 Assembler::vpmullw(dst, dst, xmm0, vector_len);
4459 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4460 } else {
4461 // worse case scenario, all regs are in the upper bank
4462 subptr(rsp, 64);
4463 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4464 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4465 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4466 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4467 Assembler::vpmullw(xmm0, xmm0, xmm1, vector_len);
4468 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4469 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4470 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4471 addptr(rsp, 64);
4472 }
4473 }
4474
4475 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4476 int dst_enc = dst->encoding();
4477 int nds_enc = nds->encoding();
4478 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4479 Assembler::vpmullw(dst, nds, src, vector_len);
4480 } else if (dst_enc < 16) {
4481 Assembler::vpmullw(dst, dst, src, vector_len);
4482 } else if (nds_enc < 16) {
4483 // implies dst_enc in upper bank with src as scratch
4484 evmovdqul(nds, dst, Assembler::AVX_512bit);
4485 Assembler::vpmullw(nds, nds, src, vector_len);
4486 evmovdqul(dst, nds, Assembler::AVX_512bit);
4487 } else {
4488 // worse case scenario, all regs in upper bank
4489 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4490 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4491 Assembler::vpmullw(xmm0, xmm0, src, vector_len);
4492 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4493 }
4494 }
4495
4496 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4497 int dst_enc = dst->encoding();
4498 int nds_enc = nds->encoding();
4499 int src_enc = src->encoding();
4500 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4501 Assembler::vpsubb(dst, nds, src, vector_len);
4502 } else if ((dst_enc < 16) && (src_enc < 16)) {
4503 Assembler::vpsubb(dst, dst, src, vector_len);
4504 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4505 // use nds as scratch for src
4506 evmovdqul(nds, src, Assembler::AVX_512bit);
4507 Assembler::vpsubb(dst, dst, nds, vector_len);
4508 } else if ((src_enc < 16) && (nds_enc < 16)) {
4509 // use nds as scratch for dst
4510 evmovdqul(nds, dst, Assembler::AVX_512bit);
4511 Assembler::vpsubb(nds, nds, src, vector_len);
4512 evmovdqul(dst, nds, Assembler::AVX_512bit);
4513 } else if (dst_enc < 16) {
4514 // use nds as scatch for xmm0 to hold src
4515 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4516 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4517 Assembler::vpsubb(dst, dst, xmm0, vector_len);
4518 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4519 } else {
4520 // worse case scenario, all regs are in the upper bank
4521 subptr(rsp, 64);
4522 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4523 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4524 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4525 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4526 Assembler::vpsubb(xmm0, xmm0, xmm1, vector_len);
4527 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4528 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4529 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4530 addptr(rsp, 64);
4531 }
4532 }
4533
4534 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4535 int dst_enc = dst->encoding();
4536 int nds_enc = nds->encoding();
4537 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4538 Assembler::vpsubb(dst, nds, src, vector_len);
4539 } else if (dst_enc < 16) {
4540 Assembler::vpsubb(dst, dst, src, vector_len);
4541 } else if (nds_enc < 16) {
4542 // implies dst_enc in upper bank with src as scratch
4543 evmovdqul(nds, dst, Assembler::AVX_512bit);
4544 Assembler::vpsubb(nds, nds, src, vector_len);
4545 evmovdqul(dst, nds, Assembler::AVX_512bit);
4546 } else {
4547 // worse case scenario, all regs in upper bank
4548 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4549 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4550 Assembler::vpsubw(xmm0, xmm0, src, vector_len);
4551 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4552 }
4553 }
4554
4555 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4556 int dst_enc = dst->encoding();
4557 int nds_enc = nds->encoding();
4558 int src_enc = src->encoding();
4559 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4560 Assembler::vpsubw(dst, nds, src, vector_len);
4561 } else if ((dst_enc < 16) && (src_enc < 16)) {
4562 Assembler::vpsubw(dst, dst, src, vector_len);
4563 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4564 // use nds as scratch for src
4565 evmovdqul(nds, src, Assembler::AVX_512bit);
4566 Assembler::vpsubw(dst, dst, nds, vector_len);
4567 } else if ((src_enc < 16) && (nds_enc < 16)) {
4568 // use nds as scratch for dst
4569 evmovdqul(nds, dst, Assembler::AVX_512bit);
4570 Assembler::vpsubw(nds, nds, src, vector_len);
4571 evmovdqul(dst, nds, Assembler::AVX_512bit);
4572 } else if (dst_enc < 16) {
4573 // use nds as scatch for xmm0 to hold src
4574 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4575 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4576 Assembler::vpsubw(dst, dst, xmm0, vector_len);
4577 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4578 } else {
4579 // worse case scenario, all regs are in the upper bank
4580 subptr(rsp, 64);
4581 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4582 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4583 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4584 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4585 Assembler::vpsubw(xmm0, xmm0, xmm1, vector_len);
4586 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4587 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4588 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4589 addptr(rsp, 64);
4590 }
4591 }
4592
4593 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4594 int dst_enc = dst->encoding();
4595 int nds_enc = nds->encoding();
4596 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4597 Assembler::vpsubw(dst, nds, src, vector_len);
4598 } else if (dst_enc < 16) {
4599 Assembler::vpsubw(dst, dst, src, vector_len);
4600 } else if (nds_enc < 16) {
4601 // implies dst_enc in upper bank with src as scratch
4602 evmovdqul(nds, dst, Assembler::AVX_512bit);
4603 Assembler::vpsubw(nds, nds, src, vector_len);
4604 evmovdqul(dst, nds, Assembler::AVX_512bit);
4605 } else {
4606 // worse case scenario, all regs in upper bank
4607 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4608 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4609 Assembler::vpsubw(xmm0, xmm0, src, vector_len);
4610 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4611 }
4612 }
4613
4614 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
4615 int dst_enc = dst->encoding();
4616 int nds_enc = nds->encoding();
4617 int shift_enc = shift->encoding();
4618 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4619 Assembler::vpsraw(dst, nds, shift, vector_len);
4620 } else if ((dst_enc < 16) && (shift_enc < 16)) {
4621 Assembler::vpsraw(dst, dst, shift, vector_len);
4622 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4623 // use nds_enc as scratch with shift
4624 evmovdqul(nds, shift, Assembler::AVX_512bit);
4625 Assembler::vpsraw(dst, dst, nds, vector_len);
4626 } else if ((shift_enc < 16) && (nds_enc < 16)) {
4627 // use nds as scratch with dst
4628 evmovdqul(nds, dst, Assembler::AVX_512bit);
4629 Assembler::vpsraw(nds, nds, shift, vector_len);
4630 evmovdqul(dst, nds, Assembler::AVX_512bit);
4631 } else if (dst_enc < 16) {
4632 // use nds to save a copy of xmm0 and hold shift
4633 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4634 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4635 Assembler::vpsraw(dst, dst, xmm0, vector_len);
4636 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4637 } else if (nds_enc < 16) {
4638 // use nds as dest as temps
4639 evmovdqul(nds, dst, Assembler::AVX_512bit);
4640 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4641 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4642 Assembler::vpsraw(nds, nds, xmm0, vector_len);
4643 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4644 evmovdqul(dst, nds, Assembler::AVX_512bit);
4645 } else {
4646 // worse case scenario, all regs are in the upper bank
4647 subptr(rsp, 64);
4648 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4649 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4650 evmovdqul(xmm1, shift, Assembler::AVX_512bit);
4651 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4652 Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len);
4653 evmovdqul(xmm1, dst, Assembler::AVX_512bit);
4654 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4655 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4656 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4657 addptr(rsp, 64);
4658 }
4659 }
4660
4661 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
4662 int dst_enc = dst->encoding();
4663 int nds_enc = nds->encoding();
4664 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4665 Assembler::vpsraw(dst, nds, shift, vector_len);
4666 } else if (dst_enc < 16) {
4667 Assembler::vpsraw(dst, dst, shift, vector_len);
4668 } else if (nds_enc < 16) {
4669 // use nds as scratch
4670 evmovdqul(nds, dst, Assembler::AVX_512bit);
4671 Assembler::vpsraw(nds, nds, shift, vector_len);
4672 evmovdqul(dst, nds, Assembler::AVX_512bit);
4673 } else {
4674 // use nds as scratch for xmm0
4675 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4676 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4677 Assembler::vpsraw(xmm0, xmm0, shift, vector_len);
4678 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4679 }
4680 }
4681
4682 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
4683 int dst_enc = dst->encoding();
4684 int nds_enc = nds->encoding();
4685 int shift_enc = shift->encoding();
4686 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4687 Assembler::vpsrlw(dst, nds, shift, vector_len);
4688 } else if ((dst_enc < 16) && (shift_enc < 16)) {
4689 Assembler::vpsrlw(dst, dst, shift, vector_len);
4690 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4691 // use nds_enc as scratch with shift
4692 evmovdqul(nds, shift, Assembler::AVX_512bit);
4693 Assembler::vpsrlw(dst, dst, nds, vector_len);
4694 } else if ((shift_enc < 16) && (nds_enc < 16)) {
4695 // use nds as scratch with dst
4696 evmovdqul(nds, dst, Assembler::AVX_512bit);
4697 Assembler::vpsrlw(nds, nds, shift, vector_len);
4698 evmovdqul(dst, nds, Assembler::AVX_512bit);
4699 } else if (dst_enc < 16) {
4700 // use nds to save a copy of xmm0 and hold shift
4701 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4702 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4703 Assembler::vpsrlw(dst, dst, xmm0, vector_len);
4704 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4705 } else if (nds_enc < 16) {
4706 // use nds as dest as temps
4707 evmovdqul(nds, dst, Assembler::AVX_512bit);
4708 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4709 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4710 Assembler::vpsrlw(nds, nds, xmm0, vector_len);
4711 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4712 evmovdqul(dst, nds, Assembler::AVX_512bit);
4713 } else {
4714 // worse case scenario, all regs are in the upper bank
4715 subptr(rsp, 64);
4716 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4717 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4718 evmovdqul(xmm1, shift, Assembler::AVX_512bit);
4719 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4720 Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len);
4721 evmovdqul(xmm1, dst, Assembler::AVX_512bit);
4722 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4723 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4724 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4725 addptr(rsp, 64);
4726 }
4727 }
4728
4729 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
4730 int dst_enc = dst->encoding();
4731 int nds_enc = nds->encoding();
4732 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4733 Assembler::vpsrlw(dst, nds, shift, vector_len);
4734 } else if (dst_enc < 16) {
4735 Assembler::vpsrlw(dst, dst, shift, vector_len);
4736 } else if (nds_enc < 16) {
4737 // use nds as scratch
4738 evmovdqul(nds, dst, Assembler::AVX_512bit);
4739 Assembler::vpsrlw(nds, nds, shift, vector_len);
4740 evmovdqul(dst, nds, Assembler::AVX_512bit);
4741 } else {
4742 // use nds as scratch for xmm0
4743 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4744 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4745 Assembler::vpsrlw(xmm0, xmm0, shift, vector_len);
4746 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4747 }
4748 }
4749
4750 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
4751 int dst_enc = dst->encoding();
4752 int nds_enc = nds->encoding();
4753 int shift_enc = shift->encoding();
4754 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4755 Assembler::vpsllw(dst, nds, shift, vector_len);
4756 } else if ((dst_enc < 16) && (shift_enc < 16)) {
4757 Assembler::vpsllw(dst, dst, shift, vector_len);
4758 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4759 // use nds_enc as scratch with shift
4760 evmovdqul(nds, shift, Assembler::AVX_512bit);
4761 Assembler::vpsllw(dst, dst, nds, vector_len);
4762 } else if ((shift_enc < 16) && (nds_enc < 16)) {
4763 // use nds as scratch with dst
4764 evmovdqul(nds, dst, Assembler::AVX_512bit);
4765 Assembler::vpsllw(nds, nds, shift, vector_len);
4766 evmovdqul(dst, nds, Assembler::AVX_512bit);
4767 } else if (dst_enc < 16) {
4768 // use nds to save a copy of xmm0 and hold shift
4769 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4770 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4771 Assembler::vpsllw(dst, dst, xmm0, vector_len);
4772 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4773 } else if (nds_enc < 16) {
4774 // use nds as dest as temps
4775 evmovdqul(nds, dst, Assembler::AVX_512bit);
4776 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4777 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4778 Assembler::vpsllw(nds, nds, xmm0, vector_len);
4779 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4780 evmovdqul(dst, nds, Assembler::AVX_512bit);
4781 } else {
4782 // worse case scenario, all regs are in the upper bank
4783 subptr(rsp, 64);
4784 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4785 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4786 evmovdqul(xmm1, shift, Assembler::AVX_512bit);
4787 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4788 Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len);
4789 evmovdqul(xmm1, dst, Assembler::AVX_512bit);
4790 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4791 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4792 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4793 addptr(rsp, 64);
4794 }
4795 }
4796
4797 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
4798 int dst_enc = dst->encoding();
4799 int nds_enc = nds->encoding();
4800 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4801 Assembler::vpsllw(dst, nds, shift, vector_len);
4802 } else if (dst_enc < 16) {
4803 Assembler::vpsllw(dst, dst, shift, vector_len);
4804 } else if (nds_enc < 16) {
4805 // use nds as scratch
4806 evmovdqul(nds, dst, Assembler::AVX_512bit);
4807 Assembler::vpsllw(nds, nds, shift, vector_len);
4808 evmovdqul(dst, nds, Assembler::AVX_512bit);
4809 } else {
4810 // use nds as scratch for xmm0
4811 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4812 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4813 Assembler::vpsllw(xmm0, xmm0, shift, vector_len);
4814 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4815 }
4816 }
4817
4818 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) {
4819 int dst_enc = dst->encoding();
4820 int src_enc = src->encoding();
4821 if ((dst_enc < 16) && (src_enc < 16)) {
4822 Assembler::vptest(dst, src);
4823 } else if (src_enc < 16) {
4824 subptr(rsp, 64);
4825 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4826 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4827 Assembler::vptest(xmm0, src);
4828 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4829 addptr(rsp, 64);
4830 } else if (dst_enc < 16) {
4831 subptr(rsp, 64);
4832 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4833 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4834 Assembler::vptest(dst, xmm0);
4835 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4836 addptr(rsp, 64);
4837 } else {
4838 subptr(rsp, 64);
4839 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4840 subptr(rsp, 64);
4841 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4842 movdqu(xmm0, src);
4843 movdqu(xmm1, dst);
4844 Assembler::vptest(xmm1, xmm0);
4845 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4846 addptr(rsp, 64);
4847 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4848 addptr(rsp, 64);
4849 }
4850 }
4851
4852 // This instruction exists within macros, ergo we cannot control its input
4853 // when emitted through those patterns.
4854 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) {
4855 if (VM_Version::supports_avx512nobw()) {
4856 int dst_enc = dst->encoding();
4857 int src_enc = src->encoding();
4858 if (dst_enc == src_enc) {
4859 if (dst_enc < 16) {
4860 Assembler::punpcklbw(dst, src);
4861 } else {
4862 subptr(rsp, 64);
4863 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4864 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4865 Assembler::punpcklbw(xmm0, xmm0);
4866 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4867 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4868 addptr(rsp, 64);
4869 }
4870 } else {
4871 if ((src_enc < 16) && (dst_enc < 16)) {
4872 Assembler::punpcklbw(dst, src);
4873 } else if (src_enc < 16) {
4874 subptr(rsp, 64);
4875 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4876 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4877 Assembler::punpcklbw(xmm0, src);
4878 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4879 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4880 addptr(rsp, 64);
4881 } else if (dst_enc < 16) {
4882 subptr(rsp, 64);
4883 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4884 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4885 Assembler::punpcklbw(dst, xmm0);
4886 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4887 addptr(rsp, 64);
4888 } else {
4889 subptr(rsp, 64);
4890 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4891 subptr(rsp, 64);
4892 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4893 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4894 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4895 Assembler::punpcklbw(xmm0, xmm1);
4896 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4897 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4898 addptr(rsp, 64);
4899 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4900 addptr(rsp, 64);
4901 }
4902 }
4903 } else {
4904 Assembler::punpcklbw(dst, src);
4905 }
4906 }
4907
4908 // This instruction exists within macros, ergo we cannot control its input
4909 // when emitted through those patterns.
4910 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
4911 if (VM_Version::supports_avx512nobw()) {
4912 int dst_enc = dst->encoding();
4913 int src_enc = src->encoding();
4914 if (dst_enc == src_enc) {
4915 if (dst_enc < 16) {
4916 Assembler::pshuflw(dst, src, mode);
4917 } else {
4918 subptr(rsp, 64);
4919 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4920 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4921 Assembler::pshuflw(xmm0, xmm0, mode);
4922 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4923 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4924 addptr(rsp, 64);
4925 }
4926 } else {
4927 if ((src_enc < 16) && (dst_enc < 16)) {
4928 Assembler::pshuflw(dst, src, mode);
4929 } else if (src_enc < 16) {
4930 subptr(rsp, 64);
4931 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4932 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4933 Assembler::pshuflw(xmm0, src, mode);
4934 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4935 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4936 addptr(rsp, 64);
4937 } else if (dst_enc < 16) {
4938 subptr(rsp, 64);
4939 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4940 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4941 Assembler::pshuflw(dst, xmm0, mode);
4942 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4943 addptr(rsp, 64);
4944 } else {
4945 subptr(rsp, 64);
4946 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4947 subptr(rsp, 64);
4948 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4949 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4950 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4951 Assembler::pshuflw(xmm0, xmm1, mode);
4952 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4953 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4954 addptr(rsp, 64);
4955 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4956 addptr(rsp, 64);
4957 }
4958 }
4959 } else {
4960 Assembler::pshuflw(dst, src, mode);
4961 }
4962 }
4963
4964 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
4965 if (reachable(src)) {
4966 vandpd(dst, nds, as_Address(src), vector_len);
4967 } else {
4968 lea(rscratch1, src);
4969 vandpd(dst, nds, Address(rscratch1, 0), vector_len);
4970 }
4971 }
4972
4973 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
4974 if (reachable(src)) {
4975 vandps(dst, nds, as_Address(src), vector_len);
4976 } else {
4977 lea(rscratch1, src);
4978 vandps(dst, nds, Address(rscratch1, 0), vector_len);
4979 }
4980 }
4981
4982 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4983 if (reachable(src)) {
4984 vdivsd(dst, nds, as_Address(src));
4985 } else {
4986 lea(rscratch1, src);
4987 vdivsd(dst, nds, Address(rscratch1, 0));
4988 }
4989 }
4990
4991 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4992 if (reachable(src)) {
4993 vdivss(dst, nds, as_Address(src));
4994 } else {
4995 lea(rscratch1, src);
4996 vdivss(dst, nds, Address(rscratch1, 0));
4997 }
4998 }
4999
5000 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5001 if (reachable(src)) {
5002 vmulsd(dst, nds, as_Address(src));
5003 } else {
5004 lea(rscratch1, src);
5005 vmulsd(dst, nds, Address(rscratch1, 0));
5006 }
5007 }
5008
5009 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5010 if (reachable(src)) {
5011 vmulss(dst, nds, as_Address(src));
5012 } else {
5013 lea(rscratch1, src);
5014 vmulss(dst, nds, Address(rscratch1, 0));
5015 }
5016 }
5017
5018 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5019 if (reachable(src)) {
5020 vsubsd(dst, nds, as_Address(src));
5021 } else {
5022 lea(rscratch1, src);
5023 vsubsd(dst, nds, Address(rscratch1, 0));
5024 }
5025 }
5026
5027 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5028 if (reachable(src)) {
5029 vsubss(dst, nds, as_Address(src));
5030 } else {
5031 lea(rscratch1, src);
5032 vsubss(dst, nds, Address(rscratch1, 0));
5033 }
5034 }
5035
5036 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5037 int nds_enc = nds->encoding();
5038 int dst_enc = dst->encoding();
5039 bool dst_upper_bank = (dst_enc > 15);
5040 bool nds_upper_bank = (nds_enc > 15);
5041 if (VM_Version::supports_avx512novl() &&
5042 (nds_upper_bank || dst_upper_bank)) {
5043 if (dst_upper_bank) {
5044 subptr(rsp, 64);
5045 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
5046 movflt(xmm0, nds);
5047 vxorps(xmm0, xmm0, src, Assembler::AVX_128bit);
5048 movflt(dst, xmm0);
5049 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
5050 addptr(rsp, 64);
5051 } else {
5052 movflt(dst, nds);
5053 vxorps(dst, dst, src, Assembler::AVX_128bit);
5054 }
5055 } else {
5056 vxorps(dst, nds, src, Assembler::AVX_128bit);
5057 }
5058 }
5059
5060 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5061 int nds_enc = nds->encoding();
5062 int dst_enc = dst->encoding();
5063 bool dst_upper_bank = (dst_enc > 15);
5064 bool nds_upper_bank = (nds_enc > 15);
5065 if (VM_Version::supports_avx512novl() &&
5066 (nds_upper_bank || dst_upper_bank)) {
5067 if (dst_upper_bank) {
5068 subptr(rsp, 64);
5069 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
5070 movdbl(xmm0, nds);
5071 vxorpd(xmm0, xmm0, src, Assembler::AVX_128bit);
5072 movdbl(dst, xmm0);
5073 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
5074 addptr(rsp, 64);
5075 } else {
5076 movdbl(dst, nds);
5077 vxorpd(dst, dst, src, Assembler::AVX_128bit);
5078 }
5079 } else {
5080 vxorpd(dst, nds, src, Assembler::AVX_128bit);
5081 }
5082 }
5083
5084 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
5085 if (reachable(src)) {
5086 vxorpd(dst, nds, as_Address(src), vector_len);
5087 } else {
5088 lea(rscratch1, src);
5089 vxorpd(dst, nds, Address(rscratch1, 0), vector_len);
5090 }
5091 }
5092
5093 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
5094 if (reachable(src)) {
5095 vxorps(dst, nds, as_Address(src), vector_len);
5096 } else {
5097 lea(rscratch1, src);
5098 vxorps(dst, nds, Address(rscratch1, 0), vector_len);
5099 }
5100 }
5101
5102
5103 //////////////////////////////////////////////////////////////////////////////////
5104 #if INCLUDE_ALL_GCS
5105
5106 void MacroAssembler::g1_write_barrier_pre(Register obj,
5107 Register pre_val,
5108 Register thread,
5109 Register tmp,
5110 bool tosca_live,
5111 bool expand_call) {
5112
5113 // If expand_call is true then we expand the call_VM_leaf macro
5114 // directly to skip generating the check by
5115 // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp.
5116
5117 #ifdef _LP64
5118 assert(thread == r15_thread, "must be");
5119 #endif // _LP64
5120
5121 Label done;
5122 Label runtime;
5123
5124 assert(pre_val != noreg, "check this code");
5125
5126 if (obj != noreg) {
5127 assert_different_registers(obj, pre_val, tmp);
5128 assert(pre_val != rax, "check this code");
5129 }
5130
5131 Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
5132 SATBMarkQueue::byte_offset_of_active()));
5133 Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
5134 SATBMarkQueue::byte_offset_of_index()));
5135 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
5136 SATBMarkQueue::byte_offset_of_buf()));
5137
5138
5139 // Is marking active?
5140 if (in_bytes(SATBMarkQueue::byte_width_of_active()) == 4) {
5141 cmpl(in_progress, 0);
5142 } else {
5143 assert(in_bytes(SATBMarkQueue::byte_width_of_active()) == 1, "Assumption");
5144 cmpb(in_progress, 0);
5145 }
5146 jcc(Assembler::equal, done);
5147
5148 // Do we need to load the previous value?
5149 if (obj != noreg) {
5150 load_heap_oop(pre_val, Address(obj, 0));
5151 }
5152
5153 // Is the previous value null?
5154 cmpptr(pre_val, (int32_t) NULL_WORD);
5155 jcc(Assembler::equal, done);
5156
5157 // Can we store original value in the thread's buffer?
5158 // Is index == 0?
5159 // (The index field is typed as size_t.)
5160
5161 movptr(tmp, index); // tmp := *index_adr
5162 cmpptr(tmp, 0); // tmp == 0?
5163 jcc(Assembler::equal, runtime); // If yes, goto runtime
5164
5165 subptr(tmp, wordSize); // tmp := tmp - wordSize
5166 movptr(index, tmp); // *index_adr := tmp
5167 addptr(tmp, buffer); // tmp := tmp + *buffer_adr
5168
5169 // Record the previous value
5170 movptr(Address(tmp, 0), pre_val);
5171 jmp(done);
5172
5173 bind(runtime);
5174 // save the live input values
5175 if(tosca_live) push(rax);
5176
5177 if (obj != noreg && obj != rax)
5178 push(obj);
5179
5180 if (pre_val != rax)
5181 push(pre_val);
5182
5183 // Calling the runtime using the regular call_VM_leaf mechanism generates
5184 // code (generated by InterpreterMacroAssember::call_VM_leaf_base)
5185 // that checks that the *(ebp+frame::interpreter_frame_last_sp) == NULL.
5186 //
5187 // If we care generating the pre-barrier without a frame (e.g. in the
5188 // intrinsified Reference.get() routine) then ebp might be pointing to
5189 // the caller frame and so this check will most likely fail at runtime.
5190 //
5191 // Expanding the call directly bypasses the generation of the check.
5192 // So when we do not have have a full interpreter frame on the stack
5193 // expand_call should be passed true.
5194
5195 NOT_LP64( push(thread); )
5196
5197 if (expand_call) {
5198 LP64_ONLY( assert(pre_val != c_rarg1, "smashed arg"); )
5199 pass_arg1(this, thread);
5200 pass_arg0(this, pre_val);
5201 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), 2);
5202 } else {
5203 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), pre_val, thread);
5204 }
5205
5206 NOT_LP64( pop(thread); )
5207
5208 // save the live input values
5209 if (pre_val != rax)
5210 pop(pre_val);
5211
5212 if (obj != noreg && obj != rax)
5213 pop(obj);
5214
5215 if(tosca_live) pop(rax);
5216
5217 bind(done);
5218 }
5219
5220 void MacroAssembler::g1_write_barrier_post(Register store_addr,
5221 Register new_val,
5222 Register thread,
5223 Register tmp,
5224 Register tmp2) {
5225 #ifdef _LP64
5226 assert(thread == r15_thread, "must be");
5227 #endif // _LP64
5228
5229 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
5230 DirtyCardQueue::byte_offset_of_index()));
5231 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
5232 DirtyCardQueue::byte_offset_of_buf()));
5233
5234 CardTableModRefBS* ct =
5235 barrier_set_cast<CardTableModRefBS>(Universe::heap()->barrier_set());
5236 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
5237
5238 Label done;
5239 Label runtime;
5240
5241 // Does store cross heap regions?
5242
5243 movptr(tmp, store_addr);
5244 xorptr(tmp, new_val);
5245 shrptr(tmp, HeapRegion::LogOfHRGrainBytes);
5246 jcc(Assembler::equal, done);
5247
5248 // crosses regions, storing NULL?
5249
5250 cmpptr(new_val, (int32_t) NULL_WORD);
5251 jcc(Assembler::equal, done);
5252
5253 // storing region crossing non-NULL, is card already dirty?
5254
5255 const Register card_addr = tmp;
5256 const Register cardtable = tmp2;
5257
5258 movptr(card_addr, store_addr);
5259 shrptr(card_addr, CardTableModRefBS::card_shift);
5260 // Do not use ExternalAddress to load 'byte_map_base', since 'byte_map_base' is NOT
5261 // a valid address and therefore is not properly handled by the relocation code.
5262 movptr(cardtable, (intptr_t)ct->byte_map_base);
5263 addptr(card_addr, cardtable);
5264
5265 cmpb(Address(card_addr, 0), (int)G1SATBCardTableModRefBS::g1_young_card_val());
5266 jcc(Assembler::equal, done);
5267
5268 membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
5269 cmpb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val());
5270 jcc(Assembler::equal, done);
5271
5272
5273 // storing a region crossing, non-NULL oop, card is clean.
5274 // dirty card and log.
5275
5276 movb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val());
5277
5278 cmpl(queue_index, 0);
5279 jcc(Assembler::equal, runtime);
5280 subl(queue_index, wordSize);
5281 movptr(tmp2, buffer);
5282 #ifdef _LP64
5283 movslq(rscratch1, queue_index);
5284 addq(tmp2, rscratch1);
5285 movq(Address(tmp2, 0), card_addr);
5286 #else
5287 addl(tmp2, queue_index);
5288 movl(Address(tmp2, 0), card_addr);
5289 #endif
5290 jmp(done);
5291
5292 bind(runtime);
5293 // save the live input values
5294 push(store_addr);
5295 push(new_val);
5296 #ifdef _LP64
5297 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, r15_thread);
5298 #else
5299 push(thread);
5300 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread);
5301 pop(thread);
5302 #endif
5303 pop(new_val);
5304 pop(store_addr);
5305
5306 bind(done);
5307 }
5308
5309 #endif // INCLUDE_ALL_GCS
5310 //////////////////////////////////////////////////////////////////////////////////
5311
5312
5313 void MacroAssembler::store_check(Register obj, Address dst) {
5314 store_check(obj);
5315 }
5316
5317 void MacroAssembler::store_check(Register obj) {
5318 // Does a store check for the oop in register obj. The content of
5319 // register obj is destroyed afterwards.
5320 BarrierSet* bs = Universe::heap()->barrier_set();
5321 assert(bs->kind() == BarrierSet::CardTableForRS ||
5322 bs->kind() == BarrierSet::CardTableExtension,
5323 "Wrong barrier set kind");
5324
5325 CardTableModRefBS* ct = barrier_set_cast<CardTableModRefBS>(bs);
5326 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
5327
5328 shrptr(obj, CardTableModRefBS::card_shift);
5329
5330 Address card_addr;
5331
5332 // The calculation for byte_map_base is as follows:
5333 // byte_map_base = _byte_map - (uintptr_t(low_bound) >> card_shift);
5334 // So this essentially converts an address to a displacement and it will
5335 // never need to be relocated. On 64bit however the value may be too
5336 // large for a 32bit displacement.
5337 intptr_t disp = (intptr_t) ct->byte_map_base;
5338 if (is_simm32(disp)) {
5339 card_addr = Address(noreg, obj, Address::times_1, disp);
5340 } else {
5341 // By doing it as an ExternalAddress 'disp' could be converted to a rip-relative
5342 // displacement and done in a single instruction given favorable mapping and a
5343 // smarter version of as_Address. However, 'ExternalAddress' generates a relocation
5344 // entry and that entry is not properly handled by the relocation code.
5345 AddressLiteral cardtable((address)ct->byte_map_base, relocInfo::none);
5346 Address index(noreg, obj, Address::times_1);
5347 card_addr = as_Address(ArrayAddress(cardtable, index));
5348 }
5349
5350 int dirty = CardTableModRefBS::dirty_card_val();
5351 if (UseCondCardMark) {
5352 Label L_already_dirty;
5353 if (UseConcMarkSweepGC) {
5354 membar(Assembler::StoreLoad);
5355 }
5356 cmpb(card_addr, dirty);
5357 jcc(Assembler::equal, L_already_dirty);
5358 movb(card_addr, dirty);
5359 bind(L_already_dirty);
5360 } else {
5361 movb(card_addr, dirty);
5362 }
5363 }
5364
5365 void MacroAssembler::subptr(Register dst, int32_t imm32) {
5366 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
5367 }
5368
5369 // Force generation of a 4 byte immediate value even if it fits into 8bit
5370 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
5371 LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32));
5372 }
5373
5374 void MacroAssembler::subptr(Register dst, Register src) {
5375 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
5376 }
5377
5378 // C++ bool manipulation
5379 void MacroAssembler::testbool(Register dst) {
5380 if(sizeof(bool) == 1)
5381 testb(dst, 0xff);
5382 else if(sizeof(bool) == 2) {
5383 // testw implementation needed for two byte bools
5384 ShouldNotReachHere();
5385 } else if(sizeof(bool) == 4)
5386 testl(dst, dst);
5387 else
5388 // unsupported
5389 ShouldNotReachHere();
5390 }
5391
5392 void MacroAssembler::testptr(Register dst, Register src) {
5393 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
5394 }
5395
5396 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
5397 void MacroAssembler::tlab_allocate(Register obj,
5398 Register var_size_in_bytes,
5399 int con_size_in_bytes,
5400 Register t1,
5401 Register t2,
5402 Label& slow_case) {
5403 assert_different_registers(obj, t1, t2);
5404 assert_different_registers(obj, var_size_in_bytes, t1);
5405 Register end = t2;
5406 Register thread = NOT_LP64(t1) LP64_ONLY(r15_thread);
5407
5408 verify_tlab();
5409
5410 NOT_LP64(get_thread(thread));
5411
5412 movptr(obj, Address(thread, JavaThread::tlab_top_offset()));
5413 if (var_size_in_bytes == noreg) {
5414 lea(end, Address(obj, con_size_in_bytes));
5415 } else {
5416 lea(end, Address(obj, var_size_in_bytes, Address::times_1));
5417 }
5418 cmpptr(end, Address(thread, JavaThread::tlab_end_offset()));
5419 jcc(Assembler::above, slow_case);
5420
5421 // update the tlab top pointer
5422 movptr(Address(thread, JavaThread::tlab_top_offset()), end);
5423
5424 // recover var_size_in_bytes if necessary
5425 if (var_size_in_bytes == end) {
5426 subptr(var_size_in_bytes, obj);
5427 }
5428 verify_tlab();
5429 }
5430
5431 // Preserves rbx, and rdx.
5432 Register MacroAssembler::tlab_refill(Label& retry,
5433 Label& try_eden,
5434 Label& slow_case) {
5435 Register top = rax;
5436 Register t1 = rcx; // object size
5437 Register t2 = rsi;
5438 Register thread_reg = NOT_LP64(rdi) LP64_ONLY(r15_thread);
5439 assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ rbx, rdx);
5440 Label do_refill, discard_tlab;
5441
5442 if (!Universe::heap()->supports_inline_contig_alloc()) {
5443 // No allocation in the shared eden.
5444 jmp(slow_case);
5445 }
5446
5447 NOT_LP64(get_thread(thread_reg));
5448
5449 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5450 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
5451
5452 // calculate amount of free space
5453 subptr(t1, top);
5454 shrptr(t1, LogHeapWordSize);
5455
5456 // Retain tlab and allocate object in shared space if
5457 // the amount free in the tlab is too large to discard.
5458 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())));
5459 jcc(Assembler::lessEqual, discard_tlab);
5460
5461 // Retain
5462 // %%% yuck as movptr...
5463 movptr(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment());
5464 addptr(Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())), t2);
5465 if (TLABStats) {
5466 // increment number of slow_allocations
5467 addl(Address(thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())), 1);
5468 }
5469 jmp(try_eden);
5470
5471 bind(discard_tlab);
5472 if (TLABStats) {
5473 // increment number of refills
5474 addl(Address(thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1);
5475 // accumulate wastage -- t1 is amount free in tlab
5476 addl(Address(thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1);
5477 }
5478
5479 // if tlab is currently allocated (top or end != null) then
5480 // fill [top, end + alignment_reserve) with array object
5481 testptr(top, top);
5482 jcc(Assembler::zero, do_refill);
5483
5484 // set up the mark word
5485 movptr(Address(top, oopDesc::mark_offset_in_bytes()), (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2));
5486 // set the length to the remaining space
5487 subptr(t1, typeArrayOopDesc::header_size(T_INT));
5488 addptr(t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve());
5489 shlptr(t1, log2_intptr(HeapWordSize/sizeof(jint)));
5490 movl(Address(top, arrayOopDesc::length_offset_in_bytes()), t1);
5491 // set klass to intArrayKlass
5492 // dubious reloc why not an oop reloc?
5493 movptr(t1, ExternalAddress((address)Universe::intArrayKlassObj_addr()));
5494 // store klass last. concurrent gcs assumes klass length is valid if
5495 // klass field is not null.
5496 store_klass(top, t1);
5497
5498 movptr(t1, top);
5499 subptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
5500 incr_allocated_bytes(thread_reg, t1, 0);
5501
5502 // refill the tlab with an eden allocation
5503 bind(do_refill);
5504 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
5505 shlptr(t1, LogHeapWordSize);
5506 // allocate new tlab, address returned in top
5507 eden_allocate(top, t1, 0, t2, slow_case);
5508
5509 // Check that t1 was preserved in eden_allocate.
5510 #ifdef ASSERT
5511 if (UseTLAB) {
5512 Label ok;
5513 Register tsize = rsi;
5514 assert_different_registers(tsize, thread_reg, t1);
5515 push(tsize);
5516 movptr(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
5517 shlptr(tsize, LogHeapWordSize);
5518 cmpptr(t1, tsize);
5519 jcc(Assembler::equal, ok);
5520 STOP("assert(t1 != tlab size)");
5521 should_not_reach_here();
5522
5523 bind(ok);
5524 pop(tsize);
5525 }
5526 #endif
5527 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top);
5528 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top);
5529 addptr(top, t1);
5530 subptr(top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes());
5531 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top);
5532
5533 if (ZeroTLAB) {
5534 // This is a fast TLAB refill, therefore the GC is not notified of it.
5535 // So compiled code must fill the new TLAB with zeroes.
5536 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
5537 zero_memory(top, t1, 0, t2);
5538 }
5539
5540 verify_tlab();
5541 jmp(retry);
5542
5543 return thread_reg; // for use by caller
5544 }
5545
5546 // Preserves the contents of address, destroys the contents length_in_bytes and temp.
5547 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) {
5548 assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different");
5549 assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord");
5550 Label done;
5551
5552 testptr(length_in_bytes, length_in_bytes);
5553 jcc(Assembler::zero, done);
5554
5555 // initialize topmost word, divide index by 2, check if odd and test if zero
5556 // note: for the remaining code to work, index must be a multiple of BytesPerWord
5557 #ifdef ASSERT
5558 {
5559 Label L;
5560 testptr(length_in_bytes, BytesPerWord - 1);
5561 jcc(Assembler::zero, L);
5562 stop("length must be a multiple of BytesPerWord");
5563 bind(L);
5564 }
5565 #endif
5566 Register index = length_in_bytes;
5567 xorptr(temp, temp); // use _zero reg to clear memory (shorter code)
5568 if (UseIncDec) {
5569 shrptr(index, 3); // divide by 8/16 and set carry flag if bit 2 was set
5570 } else {
5571 shrptr(index, 2); // use 2 instructions to avoid partial flag stall
5572 shrptr(index, 1);
5573 }
5574 #ifndef _LP64
5575 // index could have not been a multiple of 8 (i.e., bit 2 was set)
5576 {
5577 Label even;
5578 // note: if index was a multiple of 8, then it cannot
5579 // be 0 now otherwise it must have been 0 before
5580 // => if it is even, we don't need to check for 0 again
5581 jcc(Assembler::carryClear, even);
5582 // clear topmost word (no jump would be needed if conditional assignment worked here)
5583 movptr(Address(address, index, Address::times_8, offset_in_bytes - 0*BytesPerWord), temp);
5584 // index could be 0 now, must check again
5585 jcc(Assembler::zero, done);
5586 bind(even);
5587 }
5588 #endif // !_LP64
5589 // initialize remaining object fields: index is a multiple of 2 now
5590 {
5591 Label loop;
5592 bind(loop);
5593 movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp);
5594 NOT_LP64(movptr(Address(address, index, Address::times_8, offset_in_bytes - 2*BytesPerWord), temp);)
5595 decrement(index);
5596 jcc(Assembler::notZero, loop);
5597 }
5598
5599 bind(done);
5600 }
5601
5602 void MacroAssembler::incr_allocated_bytes(Register thread,
5603 Register var_size_in_bytes,
5604 int con_size_in_bytes,
5605 Register t1) {
5606 if (!thread->is_valid()) {
5607 #ifdef _LP64
5608 thread = r15_thread;
5609 #else
5610 assert(t1->is_valid(), "need temp reg");
5611 thread = t1;
5612 get_thread(thread);
5613 #endif
5614 }
5615
5616 #ifdef _LP64
5617 if (var_size_in_bytes->is_valid()) {
5618 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes);
5619 } else {
5620 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes);
5621 }
5622 #else
5623 if (var_size_in_bytes->is_valid()) {
5624 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes);
5625 } else {
5626 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes);
5627 }
5628 adcl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())+4), 0);
5629 #endif
5630 }
5631
5632 void MacroAssembler::mathfunc(address runtime_entry) {
5633 MacroAssembler::call_VM_leaf_base(runtime_entry, 0);
5634 }
5635
5636 // Look up the method for a megamorphic invokeinterface call.
5637 // The target method is determined by <intf_klass, itable_index>.
5638 // The receiver klass is in recv_klass.
5639 // On success, the result will be in method_result, and execution falls through.
5640 // On failure, execution transfers to the given label.
5641 void MacroAssembler::lookup_interface_method(Register recv_klass,
5642 Register intf_klass,
5643 RegisterOrConstant itable_index,
5644 Register method_result,
5645 Register scan_temp,
5646 Label& L_no_such_interface) {
5647 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp);
5648 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
5649 "caller must use same register for non-constant itable index as for method");
5650
5651 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
5652 int vtable_base = in_bytes(Klass::vtable_start_offset());
5653 int itentry_off = itableMethodEntry::method_offset_in_bytes();
5654 int scan_step = itableOffsetEntry::size() * wordSize;
5655 int vte_size = vtableEntry::size_in_bytes();
5656 Address::ScaleFactor times_vte_scale = Address::times_ptr;
5657 assert(vte_size == wordSize, "else adjust times_vte_scale");
5658
5659 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
5660
5661 // %%% Could store the aligned, prescaled offset in the klassoop.
5662 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
5663
5664 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
5665 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
5666 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
5667
5668 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
5669 // if (scan->interface() == intf) {
5670 // result = (klass + scan->offset() + itable_index);
5671 // }
5672 // }
5673 Label search, found_method;
5674
5675 for (int peel = 1; peel >= 0; peel--) {
5676 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
5677 cmpptr(intf_klass, method_result);
5678
5679 if (peel) {
5680 jccb(Assembler::equal, found_method);
5681 } else {
5682 jccb(Assembler::notEqual, search);
5683 // (invert the test to fall through to found_method...)
5684 }
5685
5686 if (!peel) break;
5687
5688 bind(search);
5689
5690 // Check that the previous entry is non-null. A null entry means that
5691 // the receiver class doesn't implement the interface, and wasn't the
5692 // same as when the caller was compiled.
5693 testptr(method_result, method_result);
5694 jcc(Assembler::zero, L_no_such_interface);
5695 addptr(scan_temp, scan_step);
5696 }
5697
5698 bind(found_method);
5699
5700 // Got a hit.
5701 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes()));
5702 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
5703 }
5704
5705
5706 // virtual method calling
5707 void MacroAssembler::lookup_virtual_method(Register recv_klass,
5708 RegisterOrConstant vtable_index,
5709 Register method_result) {
5710 const int base = in_bytes(Klass::vtable_start_offset());
5711 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
5712 Address vtable_entry_addr(recv_klass,
5713 vtable_index, Address::times_ptr,
5714 base + vtableEntry::method_offset_in_bytes());
5715 movptr(method_result, vtable_entry_addr);
5716 }
5717
5718
5719 void MacroAssembler::check_klass_subtype(Register sub_klass,
5720 Register super_klass,
5721 Register temp_reg,
5722 Label& L_success) {
5723 Label L_failure;
5724 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL);
5725 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL);
5726 bind(L_failure);
5727 }
5728
5729
5730 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
5731 Register super_klass,
5732 Register temp_reg,
5733 Label* L_success,
5734 Label* L_failure,
5735 Label* L_slow_path,
5736 RegisterOrConstant super_check_offset) {
5737 assert_different_registers(sub_klass, super_klass, temp_reg);
5738 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
5739 if (super_check_offset.is_register()) {
5740 assert_different_registers(sub_klass, super_klass,
5741 super_check_offset.as_register());
5742 } else if (must_load_sco) {
5743 assert(temp_reg != noreg, "supply either a temp or a register offset");
5744 }
5745
5746 Label L_fallthrough;
5747 int label_nulls = 0;
5748 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
5749 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
5750 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
5751 assert(label_nulls <= 1, "at most one NULL in the batch");
5752
5753 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
5754 int sco_offset = in_bytes(Klass::super_check_offset_offset());
5755 Address super_check_offset_addr(super_klass, sco_offset);
5756
5757 // Hacked jcc, which "knows" that L_fallthrough, at least, is in
5758 // range of a jccb. If this routine grows larger, reconsider at
5759 // least some of these.
5760 #define local_jcc(assembler_cond, label) \
5761 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \
5762 else jcc( assembler_cond, label) /*omit semi*/
5763
5764 // Hacked jmp, which may only be used just before L_fallthrough.
5765 #define final_jmp(label) \
5766 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
5767 else jmp(label) /*omit semi*/
5768
5769 // If the pointers are equal, we are done (e.g., String[] elements).
5770 // This self-check enables sharing of secondary supertype arrays among
5771 // non-primary types such as array-of-interface. Otherwise, each such
5772 // type would need its own customized SSA.
5773 // We move this check to the front of the fast path because many
5774 // type checks are in fact trivially successful in this manner,
5775 // so we get a nicely predicted branch right at the start of the check.
5776 cmpptr(sub_klass, super_klass);
5777 local_jcc(Assembler::equal, *L_success);
5778
5779 // Check the supertype display:
5780 if (must_load_sco) {
5781 // Positive movl does right thing on LP64.
5782 movl(temp_reg, super_check_offset_addr);
5783 super_check_offset = RegisterOrConstant(temp_reg);
5784 }
5785 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
5786 cmpptr(super_klass, super_check_addr); // load displayed supertype
5787
5788 // This check has worked decisively for primary supers.
5789 // Secondary supers are sought in the super_cache ('super_cache_addr').
5790 // (Secondary supers are interfaces and very deeply nested subtypes.)
5791 // This works in the same check above because of a tricky aliasing
5792 // between the super_cache and the primary super display elements.
5793 // (The 'super_check_addr' can address either, as the case requires.)
5794 // Note that the cache is updated below if it does not help us find
5795 // what we need immediately.
5796 // So if it was a primary super, we can just fail immediately.
5797 // Otherwise, it's the slow path for us (no success at this point).
5798
5799 if (super_check_offset.is_register()) {
5800 local_jcc(Assembler::equal, *L_success);
5801 cmpl(super_check_offset.as_register(), sc_offset);
5802 if (L_failure == &L_fallthrough) {
5803 local_jcc(Assembler::equal, *L_slow_path);
5804 } else {
5805 local_jcc(Assembler::notEqual, *L_failure);
5806 final_jmp(*L_slow_path);
5807 }
5808 } else if (super_check_offset.as_constant() == sc_offset) {
5809 // Need a slow path; fast failure is impossible.
5810 if (L_slow_path == &L_fallthrough) {
5811 local_jcc(Assembler::equal, *L_success);
5812 } else {
5813 local_jcc(Assembler::notEqual, *L_slow_path);
5814 final_jmp(*L_success);
5815 }
5816 } else {
5817 // No slow path; it's a fast decision.
5818 if (L_failure == &L_fallthrough) {
5819 local_jcc(Assembler::equal, *L_success);
5820 } else {
5821 local_jcc(Assembler::notEqual, *L_failure);
5822 final_jmp(*L_success);
5823 }
5824 }
5825
5826 bind(L_fallthrough);
5827
5828 #undef local_jcc
5829 #undef final_jmp
5830 }
5831
5832
5833 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
5834 Register super_klass,
5835 Register temp_reg,
5836 Register temp2_reg,
5837 Label* L_success,
5838 Label* L_failure,
5839 bool set_cond_codes) {
5840 assert_different_registers(sub_klass, super_klass, temp_reg);
5841 if (temp2_reg != noreg)
5842 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
5843 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
5844
5845 Label L_fallthrough;
5846 int label_nulls = 0;
5847 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
5848 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
5849 assert(label_nulls <= 1, "at most one NULL in the batch");
5850
5851 // a couple of useful fields in sub_klass:
5852 int ss_offset = in_bytes(Klass::secondary_supers_offset());
5853 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
5854 Address secondary_supers_addr(sub_klass, ss_offset);
5855 Address super_cache_addr( sub_klass, sc_offset);
5856
5857 // Do a linear scan of the secondary super-klass chain.
5858 // This code is rarely used, so simplicity is a virtue here.
5859 // The repne_scan instruction uses fixed registers, which we must spill.
5860 // Don't worry too much about pre-existing connections with the input regs.
5861
5862 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
5863 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
5864
5865 // Get super_klass value into rax (even if it was in rdi or rcx).
5866 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
5867 if (super_klass != rax || UseCompressedOops) {
5868 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
5869 mov(rax, super_klass);
5870 }
5871 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
5872 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
5873
5874 #ifndef PRODUCT
5875 int* pst_counter = &SharedRuntime::_partial_subtype_ctr;
5876 ExternalAddress pst_counter_addr((address) pst_counter);
5877 NOT_LP64( incrementl(pst_counter_addr) );
5878 LP64_ONLY( lea(rcx, pst_counter_addr) );
5879 LP64_ONLY( incrementl(Address(rcx, 0)) );
5880 #endif //PRODUCT
5881
5882 // We will consult the secondary-super array.
5883 movptr(rdi, secondary_supers_addr);
5884 // Load the array length. (Positive movl does right thing on LP64.)
5885 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
5886 // Skip to start of data.
5887 addptr(rdi, Array<Klass*>::base_offset_in_bytes());
5888
5889 // Scan RCX words at [RDI] for an occurrence of RAX.
5890 // Set NZ/Z based on last compare.
5891 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
5892 // not change flags (only scas instruction which is repeated sets flags).
5893 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
5894
5895 testptr(rax,rax); // Set Z = 0
5896 repne_scan();
5897
5898 // Unspill the temp. registers:
5899 if (pushed_rdi) pop(rdi);
5900 if (pushed_rcx) pop(rcx);
5901 if (pushed_rax) pop(rax);
5902
5903 if (set_cond_codes) {
5904 // Special hack for the AD files: rdi is guaranteed non-zero.
5905 assert(!pushed_rdi, "rdi must be left non-NULL");
5906 // Also, the condition codes are properly set Z/NZ on succeed/failure.
5907 }
5908
5909 if (L_failure == &L_fallthrough)
5910 jccb(Assembler::notEqual, *L_failure);
5911 else jcc(Assembler::notEqual, *L_failure);
5912
5913 // Success. Cache the super we found and proceed in triumph.
5914 movptr(super_cache_addr, super_klass);
5915
5916 if (L_success != &L_fallthrough) {
5917 jmp(*L_success);
5918 }
5919
5920 #undef IS_A_TEMP
5921
5922 bind(L_fallthrough);
5923 }
5924
5925
5926 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
5927 if (VM_Version::supports_cmov()) {
5928 cmovl(cc, dst, src);
5929 } else {
5930 Label L;
5931 jccb(negate_condition(cc), L);
5932 movl(dst, src);
5933 bind(L);
5934 }
5935 }
5936
5937 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
5938 if (VM_Version::supports_cmov()) {
5939 cmovl(cc, dst, src);
5940 } else {
5941 Label L;
5942 jccb(negate_condition(cc), L);
5943 movl(dst, src);
5944 bind(L);
5945 }
5946 }
5947
5948 void MacroAssembler::verify_oop(Register reg, const char* s) {
5949 if (!VerifyOops) return;
5950
5951 // Pass register number to verify_oop_subroutine
5952 const char* b = NULL;
5953 {
5954 ResourceMark rm;
5955 stringStream ss;
5956 ss.print("verify_oop: %s: %s", reg->name(), s);
5957 b = code_string(ss.as_string());
5958 }
5959 BLOCK_COMMENT("verify_oop {");
5960 #ifdef _LP64
5961 push(rscratch1); // save r10, trashed by movptr()
5962 #endif
5963 push(rax); // save rax,
5964 push(reg); // pass register argument
5965 ExternalAddress buffer((address) b);
5966 // avoid using pushptr, as it modifies scratch registers
5967 // and our contract is not to modify anything
5968 movptr(rax, buffer.addr());
5969 push(rax);
5970 // call indirectly to solve generation ordering problem
5971 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5972 call(rax);
5973 // Caller pops the arguments (oop, message) and restores rax, r10
5974 BLOCK_COMMENT("} verify_oop");
5975 }
5976
5977
5978 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
5979 Register tmp,
5980 int offset) {
5981 intptr_t value = *delayed_value_addr;
5982 if (value != 0)
5983 return RegisterOrConstant(value + offset);
5984
5985 // load indirectly to solve generation ordering problem
5986 movptr(tmp, ExternalAddress((address) delayed_value_addr));
5987
5988 #ifdef ASSERT
5989 { Label L;
5990 testptr(tmp, tmp);
5991 if (WizardMode) {
5992 const char* buf = NULL;
5993 {
5994 ResourceMark rm;
5995 stringStream ss;
5996 ss.print("DelayedValue=" INTPTR_FORMAT, delayed_value_addr[1]);
5997 buf = code_string(ss.as_string());
5998 }
5999 jcc(Assembler::notZero, L);
6000 STOP(buf);
6001 } else {
6002 jccb(Assembler::notZero, L);
6003 hlt();
6004 }
6005 bind(L);
6006 }
6007 #endif
6008
6009 if (offset != 0)
6010 addptr(tmp, offset);
6011
6012 return RegisterOrConstant(tmp);
6013 }
6014
6015
6016 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
6017 int extra_slot_offset) {
6018 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
6019 int stackElementSize = Interpreter::stackElementSize;
6020 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
6021 #ifdef ASSERT
6022 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
6023 assert(offset1 - offset == stackElementSize, "correct arithmetic");
6024 #endif
6025 Register scale_reg = noreg;
6026 Address::ScaleFactor scale_factor = Address::no_scale;
6027 if (arg_slot.is_constant()) {
6028 offset += arg_slot.as_constant() * stackElementSize;
6029 } else {
6030 scale_reg = arg_slot.as_register();
6031 scale_factor = Address::times(stackElementSize);
6032 }
6033 offset += wordSize; // return PC is on stack
6034 return Address(rsp, scale_reg, scale_factor, offset);
6035 }
6036
6037
6038 void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
6039 if (!VerifyOops) return;
6040
6041 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord);
6042 // Pass register number to verify_oop_subroutine
6043 const char* b = NULL;
6044 {
6045 ResourceMark rm;
6046 stringStream ss;
6047 ss.print("verify_oop_addr: %s", s);
6048 b = code_string(ss.as_string());
6049 }
6050 #ifdef _LP64
6051 push(rscratch1); // save r10, trashed by movptr()
6052 #endif
6053 push(rax); // save rax,
6054 // addr may contain rsp so we will have to adjust it based on the push
6055 // we just did (and on 64 bit we do two pushes)
6056 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
6057 // stores rax into addr which is backwards of what was intended.
6058 if (addr.uses(rsp)) {
6059 lea(rax, addr);
6060 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord));
6061 } else {
6062 pushptr(addr);
6063 }
6064
6065 ExternalAddress buffer((address) b);
6066 // pass msg argument
6067 // avoid using pushptr, as it modifies scratch registers
6068 // and our contract is not to modify anything
6069 movptr(rax, buffer.addr());
6070 push(rax);
6071
6072 // call indirectly to solve generation ordering problem
6073 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
6074 call(rax);
6075 // Caller pops the arguments (addr, message) and restores rax, r10.
6076 }
6077
6078 void MacroAssembler::verify_tlab() {
6079 #ifdef ASSERT
6080 if (UseTLAB && VerifyOops) {
6081 Label next, ok;
6082 Register t1 = rsi;
6083 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
6084
6085 push(t1);
6086 NOT_LP64(push(thread_reg));
6087 NOT_LP64(get_thread(thread_reg));
6088
6089 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
6090 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
6091 jcc(Assembler::aboveEqual, next);
6092 STOP("assert(top >= start)");
6093 should_not_reach_here();
6094
6095 bind(next);
6096 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
6097 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
6098 jcc(Assembler::aboveEqual, ok);
6099 STOP("assert(top <= end)");
6100 should_not_reach_here();
6101
6102 bind(ok);
6103 NOT_LP64(pop(thread_reg));
6104 pop(t1);
6105 }
6106 #endif
6107 }
6108
6109 class ControlWord {
6110 public:
6111 int32_t _value;
6112
6113 int rounding_control() const { return (_value >> 10) & 3 ; }
6114 int precision_control() const { return (_value >> 8) & 3 ; }
6115 bool precision() const { return ((_value >> 5) & 1) != 0; }
6116 bool underflow() const { return ((_value >> 4) & 1) != 0; }
6117 bool overflow() const { return ((_value >> 3) & 1) != 0; }
6118 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
6119 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
6120 bool invalid() const { return ((_value >> 0) & 1) != 0; }
6121
6122 void print() const {
6123 // rounding control
6124 const char* rc;
6125 switch (rounding_control()) {
6126 case 0: rc = "round near"; break;
6127 case 1: rc = "round down"; break;
6128 case 2: rc = "round up "; break;
6129 case 3: rc = "chop "; break;
6130 };
6131 // precision control
6132 const char* pc;
6133 switch (precision_control()) {
6134 case 0: pc = "24 bits "; break;
6135 case 1: pc = "reserved"; break;
6136 case 2: pc = "53 bits "; break;
6137 case 3: pc = "64 bits "; break;
6138 };
6139 // flags
6140 char f[9];
6141 f[0] = ' ';
6142 f[1] = ' ';
6143 f[2] = (precision ()) ? 'P' : 'p';
6144 f[3] = (underflow ()) ? 'U' : 'u';
6145 f[4] = (overflow ()) ? 'O' : 'o';
6146 f[5] = (zero_divide ()) ? 'Z' : 'z';
6147 f[6] = (denormalized()) ? 'D' : 'd';
6148 f[7] = (invalid ()) ? 'I' : 'i';
6149 f[8] = '\x0';
6150 // output
6151 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
6152 }
6153
6154 };
6155
6156 class StatusWord {
6157 public:
6158 int32_t _value;
6159
6160 bool busy() const { return ((_value >> 15) & 1) != 0; }
6161 bool C3() const { return ((_value >> 14) & 1) != 0; }
6162 bool C2() const { return ((_value >> 10) & 1) != 0; }
6163 bool C1() const { return ((_value >> 9) & 1) != 0; }
6164 bool C0() const { return ((_value >> 8) & 1) != 0; }
6165 int top() const { return (_value >> 11) & 7 ; }
6166 bool error_status() const { return ((_value >> 7) & 1) != 0; }
6167 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
6168 bool precision() const { return ((_value >> 5) & 1) != 0; }
6169 bool underflow() const { return ((_value >> 4) & 1) != 0; }
6170 bool overflow() const { return ((_value >> 3) & 1) != 0; }
6171 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
6172 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
6173 bool invalid() const { return ((_value >> 0) & 1) != 0; }
6174
6175 void print() const {
6176 // condition codes
6177 char c[5];
6178 c[0] = (C3()) ? '3' : '-';
6179 c[1] = (C2()) ? '2' : '-';
6180 c[2] = (C1()) ? '1' : '-';
6181 c[3] = (C0()) ? '0' : '-';
6182 c[4] = '\x0';
6183 // flags
6184 char f[9];
6185 f[0] = (error_status()) ? 'E' : '-';
6186 f[1] = (stack_fault ()) ? 'S' : '-';
6187 f[2] = (precision ()) ? 'P' : '-';
6188 f[3] = (underflow ()) ? 'U' : '-';
6189 f[4] = (overflow ()) ? 'O' : '-';
6190 f[5] = (zero_divide ()) ? 'Z' : '-';
6191 f[6] = (denormalized()) ? 'D' : '-';
6192 f[7] = (invalid ()) ? 'I' : '-';
6193 f[8] = '\x0';
6194 // output
6195 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
6196 }
6197
6198 };
6199
6200 class TagWord {
6201 public:
6202 int32_t _value;
6203
6204 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
6205
6206 void print() const {
6207 printf("%04x", _value & 0xFFFF);
6208 }
6209
6210 };
6211
6212 class FPU_Register {
6213 public:
6214 int32_t _m0;
6215 int32_t _m1;
6216 int16_t _ex;
6217
6218 bool is_indefinite() const {
6219 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
6220 }
6221
6222 void print() const {
6223 char sign = (_ex < 0) ? '-' : '+';
6224 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
6225 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
6226 };
6227
6228 };
6229
6230 class FPU_State {
6231 public:
6232 enum {
6233 register_size = 10,
6234 number_of_registers = 8,
6235 register_mask = 7
6236 };
6237
6238 ControlWord _control_word;
6239 StatusWord _status_word;
6240 TagWord _tag_word;
6241 int32_t _error_offset;
6242 int32_t _error_selector;
6243 int32_t _data_offset;
6244 int32_t _data_selector;
6245 int8_t _register[register_size * number_of_registers];
6246
6247 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
6248 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
6249
6250 const char* tag_as_string(int tag) const {
6251 switch (tag) {
6252 case 0: return "valid";
6253 case 1: return "zero";
6254 case 2: return "special";
6255 case 3: return "empty";
6256 }
6257 ShouldNotReachHere();
6258 return NULL;
6259 }
6260
6261 void print() const {
6262 // print computation registers
6263 { int t = _status_word.top();
6264 for (int i = 0; i < number_of_registers; i++) {
6265 int j = (i - t) & register_mask;
6266 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
6267 st(j)->print();
6268 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
6269 }
6270 }
6271 printf("\n");
6272 // print control registers
6273 printf("ctrl = "); _control_word.print(); printf("\n");
6274 printf("stat = "); _status_word .print(); printf("\n");
6275 printf("tags = "); _tag_word .print(); printf("\n");
6276 }
6277
6278 };
6279
6280 class Flag_Register {
6281 public:
6282 int32_t _value;
6283
6284 bool overflow() const { return ((_value >> 11) & 1) != 0; }
6285 bool direction() const { return ((_value >> 10) & 1) != 0; }
6286 bool sign() const { return ((_value >> 7) & 1) != 0; }
6287 bool zero() const { return ((_value >> 6) & 1) != 0; }
6288 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
6289 bool parity() const { return ((_value >> 2) & 1) != 0; }
6290 bool carry() const { return ((_value >> 0) & 1) != 0; }
6291
6292 void print() const {
6293 // flags
6294 char f[8];
6295 f[0] = (overflow ()) ? 'O' : '-';
6296 f[1] = (direction ()) ? 'D' : '-';
6297 f[2] = (sign ()) ? 'S' : '-';
6298 f[3] = (zero ()) ? 'Z' : '-';
6299 f[4] = (auxiliary_carry()) ? 'A' : '-';
6300 f[5] = (parity ()) ? 'P' : '-';
6301 f[6] = (carry ()) ? 'C' : '-';
6302 f[7] = '\x0';
6303 // output
6304 printf("%08x flags = %s", _value, f);
6305 }
6306
6307 };
6308
6309 class IU_Register {
6310 public:
6311 int32_t _value;
6312
6313 void print() const {
6314 printf("%08x %11d", _value, _value);
6315 }
6316
6317 };
6318
6319 class IU_State {
6320 public:
6321 Flag_Register _eflags;
6322 IU_Register _rdi;
6323 IU_Register _rsi;
6324 IU_Register _rbp;
6325 IU_Register _rsp;
6326 IU_Register _rbx;
6327 IU_Register _rdx;
6328 IU_Register _rcx;
6329 IU_Register _rax;
6330
6331 void print() const {
6332 // computation registers
6333 printf("rax, = "); _rax.print(); printf("\n");
6334 printf("rbx, = "); _rbx.print(); printf("\n");
6335 printf("rcx = "); _rcx.print(); printf("\n");
6336 printf("rdx = "); _rdx.print(); printf("\n");
6337 printf("rdi = "); _rdi.print(); printf("\n");
6338 printf("rsi = "); _rsi.print(); printf("\n");
6339 printf("rbp, = "); _rbp.print(); printf("\n");
6340 printf("rsp = "); _rsp.print(); printf("\n");
6341 printf("\n");
6342 // control registers
6343 printf("flgs = "); _eflags.print(); printf("\n");
6344 }
6345 };
6346
6347
6348 class CPU_State {
6349 public:
6350 FPU_State _fpu_state;
6351 IU_State _iu_state;
6352
6353 void print() const {
6354 printf("--------------------------------------------------\n");
6355 _iu_state .print();
6356 printf("\n");
6357 _fpu_state.print();
6358 printf("--------------------------------------------------\n");
6359 }
6360
6361 };
6362
6363
6364 static void _print_CPU_state(CPU_State* state) {
6365 state->print();
6366 };
6367
6368
6369 void MacroAssembler::print_CPU_state() {
6370 push_CPU_state();
6371 push(rsp); // pass CPU state
6372 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
6373 addptr(rsp, wordSize); // discard argument
6374 pop_CPU_state();
6375 }
6376
6377
6378 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
6379 static int counter = 0;
6380 FPU_State* fs = &state->_fpu_state;
6381 counter++;
6382 // For leaf calls, only verify that the top few elements remain empty.
6383 // We only need 1 empty at the top for C2 code.
6384 if( stack_depth < 0 ) {
6385 if( fs->tag_for_st(7) != 3 ) {
6386 printf("FPR7 not empty\n");
6387 state->print();
6388 assert(false, "error");
6389 return false;
6390 }
6391 return true; // All other stack states do not matter
6392 }
6393
6394 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std,
6395 "bad FPU control word");
6396
6397 // compute stack depth
6398 int i = 0;
6399 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++;
6400 int d = i;
6401 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
6402 // verify findings
6403 if (i != FPU_State::number_of_registers) {
6404 // stack not contiguous
6405 printf("%s: stack not contiguous at ST%d\n", s, i);
6406 state->print();
6407 assert(false, "error");
6408 return false;
6409 }
6410 // check if computed stack depth corresponds to expected stack depth
6411 if (stack_depth < 0) {
6412 // expected stack depth is -stack_depth or less
6413 if (d > -stack_depth) {
6414 // too many elements on the stack
6415 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
6416 state->print();
6417 assert(false, "error");
6418 return false;
6419 }
6420 } else {
6421 // expected stack depth is stack_depth
6422 if (d != stack_depth) {
6423 // wrong stack depth
6424 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
6425 state->print();
6426 assert(false, "error");
6427 return false;
6428 }
6429 }
6430 // everything is cool
6431 return true;
6432 }
6433
6434
6435 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
6436 if (!VerifyFPU) return;
6437 push_CPU_state();
6438 push(rsp); // pass CPU state
6439 ExternalAddress msg((address) s);
6440 // pass message string s
6441 pushptr(msg.addr());
6442 push(stack_depth); // pass stack depth
6443 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
6444 addptr(rsp, 3 * wordSize); // discard arguments
6445 // check for error
6446 { Label L;
6447 testl(rax, rax);
6448 jcc(Assembler::notZero, L);
6449 int3(); // break if error condition
6450 bind(L);
6451 }
6452 pop_CPU_state();
6453 }
6454
6455 void MacroAssembler::restore_cpu_control_state_after_jni() {
6456 // Either restore the MXCSR register after returning from the JNI Call
6457 // or verify that it wasn't changed (with -Xcheck:jni flag).
6458 if (VM_Version::supports_sse()) {
6459 if (RestoreMXCSROnJNICalls) {
6460 ldmxcsr(ExternalAddress(StubRoutines::addr_mxcsr_std()));
6461 } else if (CheckJNICalls) {
6462 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
6463 }
6464 }
6465 if (VM_Version::supports_avx()) {
6466 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
6467 vzeroupper();
6468 }
6469
6470 #ifndef _LP64
6471 // Either restore the x87 floating pointer control word after returning
6472 // from the JNI call or verify that it wasn't changed.
6473 if (CheckJNICalls) {
6474 call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry()));
6475 }
6476 #endif // _LP64
6477 }
6478
6479 void MacroAssembler::load_mirror(Register mirror, Register method) {
6480 // get mirror
6481 const int mirror_offset = in_bytes(Klass::java_mirror_offset());
6482 movptr(mirror, Address(method, Method::const_offset()));
6483 movptr(mirror, Address(mirror, ConstMethod::constants_offset()));
6484 movptr(mirror, Address(mirror, ConstantPool::pool_holder_offset_in_bytes()));
6485 movptr(mirror, Address(mirror, mirror_offset));
6486 }
6487
6488 void MacroAssembler::load_klass(Register dst, Register src) {
6489 #ifdef _LP64
6490 if (UseCompressedClassPointers) {
6491 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
6492 decode_klass_not_null(dst);
6493 } else
6494 #endif
6495 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
6496 }
6497
6498 void MacroAssembler::load_prototype_header(Register dst, Register src) {
6499 load_klass(dst, src);
6500 movptr(dst, Address(dst, Klass::prototype_header_offset()));
6501 }
6502
6503 void MacroAssembler::store_klass(Register dst, Register src) {
6504 #ifdef _LP64
6505 if (UseCompressedClassPointers) {
6506 encode_klass_not_null(src);
6507 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
6508 } else
6509 #endif
6510 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
6511 }
6512
6513 void MacroAssembler::load_heap_oop(Register dst, Address src) {
6514 #ifdef _LP64
6515 // FIXME: Must change all places where we try to load the klass.
6516 if (UseCompressedOops) {
6517 movl(dst, src);
6518 decode_heap_oop(dst);
6519 } else
6520 #endif
6521 movptr(dst, src);
6522 }
6523
6524 // Doesn't do verfication, generates fixed size code
6525 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src) {
6526 #ifdef _LP64
6527 if (UseCompressedOops) {
6528 movl(dst, src);
6529 decode_heap_oop_not_null(dst);
6530 } else
6531 #endif
6532 movptr(dst, src);
6533 }
6534
6535 void MacroAssembler::store_heap_oop(Address dst, Register src) {
6536 #ifdef _LP64
6537 if (UseCompressedOops) {
6538 assert(!dst.uses(src), "not enough registers");
6539 encode_heap_oop(src);
6540 movl(dst, src);
6541 } else
6542 #endif
6543 movptr(dst, src);
6544 }
6545
6546 void MacroAssembler::cmp_heap_oop(Register src1, Address src2, Register tmp) {
6547 assert_different_registers(src1, tmp);
6548 #ifdef _LP64
6549 if (UseCompressedOops) {
6550 bool did_push = false;
6551 if (tmp == noreg) {
6552 tmp = rax;
6553 push(tmp);
6554 did_push = true;
6555 assert(!src2.uses(rsp), "can't push");
6556 }
6557 load_heap_oop(tmp, src2);
6558 cmpptr(src1, tmp);
6559 if (did_push) pop(tmp);
6560 } else
6561 #endif
6562 cmpptr(src1, src2);
6563 }
6564
6565 // Used for storing NULLs.
6566 void MacroAssembler::store_heap_oop_null(Address dst) {
6567 #ifdef _LP64
6568 if (UseCompressedOops) {
6569 movl(dst, (int32_t)NULL_WORD);
6570 } else {
6571 movslq(dst, (int32_t)NULL_WORD);
6572 }
6573 #else
6574 movl(dst, (int32_t)NULL_WORD);
6575 #endif
6576 }
6577
6578 #ifdef _LP64
6579 void MacroAssembler::store_klass_gap(Register dst, Register src) {
6580 if (UseCompressedClassPointers) {
6581 // Store to klass gap in destination
6582 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
6583 }
6584 }
6585
6586 #ifdef ASSERT
6587 void MacroAssembler::verify_heapbase(const char* msg) {
6588 assert (UseCompressedOops, "should be compressed");
6589 assert (Universe::heap() != NULL, "java heap should be initialized");
6590 if (CheckCompressedOops) {
6591 Label ok;
6592 push(rscratch1); // cmpptr trashes rscratch1
6593 cmpptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
6594 jcc(Assembler::equal, ok);
6595 STOP(msg);
6596 bind(ok);
6597 pop(rscratch1);
6598 }
6599 }
6600 #endif
6601
6602 // Algorithm must match oop.inline.hpp encode_heap_oop.
6603 void MacroAssembler::encode_heap_oop(Register r) {
6604 #ifdef ASSERT
6605 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
6606 #endif
6607 verify_oop(r, "broken oop in encode_heap_oop");
6608 if (Universe::narrow_oop_base() == NULL) {
6609 if (Universe::narrow_oop_shift() != 0) {
6610 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6611 shrq(r, LogMinObjAlignmentInBytes);
6612 }
6613 return;
6614 }
6615 testq(r, r);
6616 cmovq(Assembler::equal, r, r12_heapbase);
6617 subq(r, r12_heapbase);
6618 shrq(r, LogMinObjAlignmentInBytes);
6619 }
6620
6621 void MacroAssembler::encode_heap_oop_not_null(Register r) {
6622 #ifdef ASSERT
6623 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
6624 if (CheckCompressedOops) {
6625 Label ok;
6626 testq(r, r);
6627 jcc(Assembler::notEqual, ok);
6628 STOP("null oop passed to encode_heap_oop_not_null");
6629 bind(ok);
6630 }
6631 #endif
6632 verify_oop(r, "broken oop in encode_heap_oop_not_null");
6633 if (Universe::narrow_oop_base() != NULL) {
6634 subq(r, r12_heapbase);
6635 }
6636 if (Universe::narrow_oop_shift() != 0) {
6637 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6638 shrq(r, LogMinObjAlignmentInBytes);
6639 }
6640 }
6641
6642 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
6643 #ifdef ASSERT
6644 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
6645 if (CheckCompressedOops) {
6646 Label ok;
6647 testq(src, src);
6648 jcc(Assembler::notEqual, ok);
6649 STOP("null oop passed to encode_heap_oop_not_null2");
6650 bind(ok);
6651 }
6652 #endif
6653 verify_oop(src, "broken oop in encode_heap_oop_not_null2");
6654 if (dst != src) {
6655 movq(dst, src);
6656 }
6657 if (Universe::narrow_oop_base() != NULL) {
6658 subq(dst, r12_heapbase);
6659 }
6660 if (Universe::narrow_oop_shift() != 0) {
6661 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6662 shrq(dst, LogMinObjAlignmentInBytes);
6663 }
6664 }
6665
6666 void MacroAssembler::decode_heap_oop(Register r) {
6667 #ifdef ASSERT
6668 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
6669 #endif
6670 if (Universe::narrow_oop_base() == NULL) {
6671 if (Universe::narrow_oop_shift() != 0) {
6672 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6673 shlq(r, LogMinObjAlignmentInBytes);
6674 }
6675 } else {
6676 Label done;
6677 shlq(r, LogMinObjAlignmentInBytes);
6678 jccb(Assembler::equal, done);
6679 addq(r, r12_heapbase);
6680 bind(done);
6681 }
6682 verify_oop(r, "broken oop in decode_heap_oop");
6683 }
6684
6685 void MacroAssembler::decode_heap_oop_not_null(Register r) {
6686 // Note: it will change flags
6687 assert (UseCompressedOops, "should only be used for compressed headers");
6688 assert (Universe::heap() != NULL, "java heap should be initialized");
6689 // Cannot assert, unverified entry point counts instructions (see .ad file)
6690 // vtableStubs also counts instructions in pd_code_size_limit.
6691 // Also do not verify_oop as this is called by verify_oop.
6692 if (Universe::narrow_oop_shift() != 0) {
6693 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6694 shlq(r, LogMinObjAlignmentInBytes);
6695 if (Universe::narrow_oop_base() != NULL) {
6696 addq(r, r12_heapbase);
6697 }
6698 } else {
6699 assert (Universe::narrow_oop_base() == NULL, "sanity");
6700 }
6701 }
6702
6703 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
6704 // Note: it will change flags
6705 assert (UseCompressedOops, "should only be used for compressed headers");
6706 assert (Universe::heap() != NULL, "java heap should be initialized");
6707 // Cannot assert, unverified entry point counts instructions (see .ad file)
6708 // vtableStubs also counts instructions in pd_code_size_limit.
6709 // Also do not verify_oop as this is called by verify_oop.
6710 if (Universe::narrow_oop_shift() != 0) {
6711 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6712 if (LogMinObjAlignmentInBytes == Address::times_8) {
6713 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
6714 } else {
6715 if (dst != src) {
6716 movq(dst, src);
6717 }
6718 shlq(dst, LogMinObjAlignmentInBytes);
6719 if (Universe::narrow_oop_base() != NULL) {
6720 addq(dst, r12_heapbase);
6721 }
6722 }
6723 } else {
6724 assert (Universe::narrow_oop_base() == NULL, "sanity");
6725 if (dst != src) {
6726 movq(dst, src);
6727 }
6728 }
6729 }
6730
6731 void MacroAssembler::encode_klass_not_null(Register r) {
6732 if (Universe::narrow_klass_base() != NULL) {
6733 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
6734 assert(r != r12_heapbase, "Encoding a klass in r12");
6735 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
6736 subq(r, r12_heapbase);
6737 }
6738 if (Universe::narrow_klass_shift() != 0) {
6739 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6740 shrq(r, LogKlassAlignmentInBytes);
6741 }
6742 if (Universe::narrow_klass_base() != NULL) {
6743 reinit_heapbase();
6744 }
6745 }
6746
6747 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
6748 if (dst == src) {
6749 encode_klass_not_null(src);
6750 } else {
6751 if (Universe::narrow_klass_base() != NULL) {
6752 mov64(dst, (int64_t)Universe::narrow_klass_base());
6753 negq(dst);
6754 addq(dst, src);
6755 } else {
6756 movptr(dst, src);
6757 }
6758 if (Universe::narrow_klass_shift() != 0) {
6759 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6760 shrq(dst, LogKlassAlignmentInBytes);
6761 }
6762 }
6763 }
6764
6765 // Function instr_size_for_decode_klass_not_null() counts the instructions
6766 // generated by decode_klass_not_null(register r) and reinit_heapbase(),
6767 // when (Universe::heap() != NULL). Hence, if the instructions they
6768 // generate change, then this method needs to be updated.
6769 int MacroAssembler::instr_size_for_decode_klass_not_null() {
6770 assert (UseCompressedClassPointers, "only for compressed klass ptrs");
6771 if (Universe::narrow_klass_base() != NULL) {
6772 // mov64 + addq + shlq? + mov64 (for reinit_heapbase()).
6773 return (Universe::narrow_klass_shift() == 0 ? 20 : 24);
6774 } else {
6775 // longest load decode klass function, mov64, leaq
6776 return 16;
6777 }
6778 }
6779
6780 // !!! If the instructions that get generated here change then function
6781 // instr_size_for_decode_klass_not_null() needs to get updated.
6782 void MacroAssembler::decode_klass_not_null(Register r) {
6783 // Note: it will change flags
6784 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6785 assert(r != r12_heapbase, "Decoding a klass in r12");
6786 // Cannot assert, unverified entry point counts instructions (see .ad file)
6787 // vtableStubs also counts instructions in pd_code_size_limit.
6788 // Also do not verify_oop as this is called by verify_oop.
6789 if (Universe::narrow_klass_shift() != 0) {
6790 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6791 shlq(r, LogKlassAlignmentInBytes);
6792 }
6793 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
6794 if (Universe::narrow_klass_base() != NULL) {
6795 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
6796 addq(r, r12_heapbase);
6797 reinit_heapbase();
6798 }
6799 }
6800
6801 void MacroAssembler::decode_klass_not_null(Register dst, Register src) {
6802 // Note: it will change flags
6803 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6804 if (dst == src) {
6805 decode_klass_not_null(dst);
6806 } else {
6807 // Cannot assert, unverified entry point counts instructions (see .ad file)
6808 // vtableStubs also counts instructions in pd_code_size_limit.
6809 // Also do not verify_oop as this is called by verify_oop.
6810 mov64(dst, (int64_t)Universe::narrow_klass_base());
6811 if (Universe::narrow_klass_shift() != 0) {
6812 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6813 assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?");
6814 leaq(dst, Address(dst, src, Address::times_8, 0));
6815 } else {
6816 addq(dst, src);
6817 }
6818 }
6819 }
6820
6821 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
6822 assert (UseCompressedOops, "should only be used for compressed headers");
6823 assert (Universe::heap() != NULL, "java heap should be initialized");
6824 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6825 int oop_index = oop_recorder()->find_index(obj);
6826 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6827 mov_narrow_oop(dst, oop_index, rspec);
6828 }
6829
6830 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
6831 assert (UseCompressedOops, "should only be used for compressed headers");
6832 assert (Universe::heap() != NULL, "java heap should be initialized");
6833 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6834 int oop_index = oop_recorder()->find_index(obj);
6835 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6836 mov_narrow_oop(dst, oop_index, rspec);
6837 }
6838
6839 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
6840 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6841 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6842 int klass_index = oop_recorder()->find_index(k);
6843 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6844 mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
6845 }
6846
6847 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
6848 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6849 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6850 int klass_index = oop_recorder()->find_index(k);
6851 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6852 mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
6853 }
6854
6855 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
6856 assert (UseCompressedOops, "should only be used for compressed headers");
6857 assert (Universe::heap() != NULL, "java heap should be initialized");
6858 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6859 int oop_index = oop_recorder()->find_index(obj);
6860 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6861 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6862 }
6863
6864 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
6865 assert (UseCompressedOops, "should only be used for compressed headers");
6866 assert (Universe::heap() != NULL, "java heap should be initialized");
6867 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6868 int oop_index = oop_recorder()->find_index(obj);
6869 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6870 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6871 }
6872
6873 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
6874 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6875 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6876 int klass_index = oop_recorder()->find_index(k);
6877 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6878 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
6879 }
6880
6881 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
6882 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6883 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6884 int klass_index = oop_recorder()->find_index(k);
6885 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6886 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
6887 }
6888
6889 void MacroAssembler::reinit_heapbase() {
6890 if (UseCompressedOops || UseCompressedClassPointers) {
6891 if (Universe::heap() != NULL) {
6892 if (Universe::narrow_oop_base() == NULL) {
6893 MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
6894 } else {
6895 mov64(r12_heapbase, (int64_t)Universe::narrow_ptrs_base());
6896 }
6897 } else {
6898 movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
6899 }
6900 }
6901 }
6902
6903 #endif // _LP64
6904
6905
6906 // C2 compiled method's prolog code.
6907 void MacroAssembler::verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b) {
6908
6909 // WARNING: Initial instruction MUST be 5 bytes or longer so that
6910 // NativeJump::patch_verified_entry will be able to patch out the entry
6911 // code safely. The push to verify stack depth is ok at 5 bytes,
6912 // the frame allocation can be either 3 or 6 bytes. So if we don't do
6913 // stack bang then we must use the 6 byte frame allocation even if
6914 // we have no frame. :-(
6915 assert(stack_bang_size >= framesize || stack_bang_size <= 0, "stack bang size incorrect");
6916
6917 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
6918 // Remove word for return addr
6919 framesize -= wordSize;
6920 stack_bang_size -= wordSize;
6921
6922 // Calls to C2R adapters often do not accept exceptional returns.
6923 // We require that their callers must bang for them. But be careful, because
6924 // some VM calls (such as call site linkage) can use several kilobytes of
6925 // stack. But the stack safety zone should account for that.
6926 // See bugs 4446381, 4468289, 4497237.
6927 if (stack_bang_size > 0) {
6928 generate_stack_overflow_check(stack_bang_size);
6929
6930 // We always push rbp, so that on return to interpreter rbp, will be
6931 // restored correctly and we can correct the stack.
6932 push(rbp);
6933 // Save caller's stack pointer into RBP if the frame pointer is preserved.
6934 if (PreserveFramePointer) {
6935 mov(rbp, rsp);
6936 }
6937 // Remove word for ebp
6938 framesize -= wordSize;
6939
6940 // Create frame
6941 if (framesize) {
6942 subptr(rsp, framesize);
6943 }
6944 } else {
6945 // Create frame (force generation of a 4 byte immediate value)
6946 subptr_imm32(rsp, framesize);
6947
6948 // Save RBP register now.
6949 framesize -= wordSize;
6950 movptr(Address(rsp, framesize), rbp);
6951 // Save caller's stack pointer into RBP if the frame pointer is preserved.
6952 if (PreserveFramePointer) {
6953 movptr(rbp, rsp);
6954 if (framesize > 0) {
6955 addptr(rbp, framesize);
6956 }
6957 }
6958 }
6959
6960 if (VerifyStackAtCalls) { // Majik cookie to verify stack depth
6961 framesize -= wordSize;
6962 movptr(Address(rsp, framesize), (int32_t)0xbadb100d);
6963 }
6964
6965 #ifndef _LP64
6966 // If method sets FPU control word do it now
6967 if (fp_mode_24b) {
6968 fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
6969 }
6970 if (UseSSE >= 2 && VerifyFPU) {
6971 verify_FPU(0, "FPU stack must be clean on entry");
6972 }
6973 #endif
6974
6975 #ifdef ASSERT
6976 if (VerifyStackAtCalls) {
6977 Label L;
6978 push(rax);
6979 mov(rax, rsp);
6980 andptr(rax, StackAlignmentInBytes-1);
6981 cmpptr(rax, StackAlignmentInBytes-wordSize);
6982 pop(rax);
6983 jcc(Assembler::equal, L);
6984 STOP("Stack is not properly aligned!");
6985 bind(L);
6986 }
6987 #endif
6988
6989 }
6990
6991 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp, bool is_large) {
6992 // cnt - number of qwords (8-byte words).
6993 // base - start address, qword aligned.
6994 // is_large - if optimizers know cnt is larger than InitArrayShortSize
6995 assert(base==rdi, "base register must be edi for rep stos");
6996 assert(tmp==rax, "tmp register must be eax for rep stos");
6997 assert(cnt==rcx, "cnt register must be ecx for rep stos");
6998 assert(InitArrayShortSize % BytesPerLong == 0,
6999 "InitArrayShortSize should be the multiple of BytesPerLong");
7000
7001 Label DONE;
7002
7003 xorptr(tmp, tmp);
7004
7005 if (!is_large) {
7006 Label LOOP, LONG;
7007 cmpptr(cnt, InitArrayShortSize/BytesPerLong);
7008 jccb(Assembler::greater, LONG);
7009
7010 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
7011
7012 decrement(cnt);
7013 jccb(Assembler::negative, DONE); // Zero length
7014
7015 // Use individual pointer-sized stores for small counts:
7016 BIND(LOOP);
7017 movptr(Address(base, cnt, Address::times_ptr), tmp);
7018 decrement(cnt);
7019 jccb(Assembler::greaterEqual, LOOP);
7020 jmpb(DONE);
7021
7022 BIND(LONG);
7023 }
7024
7025 // Use longer rep-prefixed ops for non-small counts:
7026 if (UseFastStosb) {
7027 shlptr(cnt, 3); // convert to number of bytes
7028 rep_stosb();
7029 } else {
7030 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
7031 rep_stos();
7032 }
7033
7034 BIND(DONE);
7035 }
7036
7037 #ifdef COMPILER2
7038
7039 // IndexOf for constant substrings with size >= 8 chars
7040 // which don't need to be loaded through stack.
7041 void MacroAssembler::string_indexofC8(Register str1, Register str2,
7042 Register cnt1, Register cnt2,
7043 int int_cnt2, Register result,
7044 XMMRegister vec, Register tmp,
7045 int ae) {
7046 ShortBranchVerifier sbv(this);
7047 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
7048 assert(UseSSE >= 4, "SSE4 must be enabled for SSE4.2 intrinsics to be available");
7049 assert(ae != StrIntrinsicNode::LU, "Invalid encoding");
7050
7051 // This method uses the pcmpestri instruction with bound registers
7052 // inputs:
7053 // xmm - substring
7054 // rax - substring length (elements count)
7055 // mem - scanned string
7056 // rdx - string length (elements count)
7057 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
7058 // 0xc - mode: 1100 (substring search) + 00 (unsigned bytes)
7059 // outputs:
7060 // rcx - matched index in string
7061 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
7062 int mode = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts
7063 int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8
7064 Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2;
7065 Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1;
7066
7067 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR,
7068 RET_FOUND, RET_NOT_FOUND, EXIT, FOUND_SUBSTR,
7069 MATCH_SUBSTR_HEAD, RELOAD_STR, FOUND_CANDIDATE;
7070
7071 // Note, inline_string_indexOf() generates checks:
7072 // if (substr.count > string.count) return -1;
7073 // if (substr.count == 0) return 0;
7074 assert(int_cnt2 >= stride, "this code is used only for cnt2 >= 8 chars");
7075
7076 // Load substring.
7077 if (ae == StrIntrinsicNode::UL) {
7078 pmovzxbw(vec, Address(str2, 0));
7079 } else {
7080 movdqu(vec, Address(str2, 0));
7081 }
7082 movl(cnt2, int_cnt2);
7083 movptr(result, str1); // string addr
7084
7085 if (int_cnt2 > stride) {
7086 jmpb(SCAN_TO_SUBSTR);
7087
7088 // Reload substr for rescan, this code
7089 // is executed only for large substrings (> 8 chars)
7090 bind(RELOAD_SUBSTR);
7091 if (ae == StrIntrinsicNode::UL) {
7092 pmovzxbw(vec, Address(str2, 0));
7093 } else {
7094 movdqu(vec, Address(str2, 0));
7095 }
7096 negptr(cnt2); // Jumped here with negative cnt2, convert to positive
7097
7098 bind(RELOAD_STR);
7099 // We came here after the beginning of the substring was
7100 // matched but the rest of it was not so we need to search
7101 // again. Start from the next element after the previous match.
7102
7103 // cnt2 is number of substring reminding elements and
7104 // cnt1 is number of string reminding elements when cmp failed.
7105 // Restored cnt1 = cnt1 - cnt2 + int_cnt2
7106 subl(cnt1, cnt2);
7107 addl(cnt1, int_cnt2);
7108 movl(cnt2, int_cnt2); // Now restore cnt2
7109
7110 decrementl(cnt1); // Shift to next element
7111 cmpl(cnt1, cnt2);
7112 jcc(Assembler::negative, RET_NOT_FOUND); // Left less then substring
7113
7114 addptr(result, (1<<scale1));
7115
7116 } // (int_cnt2 > 8)
7117
7118 // Scan string for start of substr in 16-byte vectors
7119 bind(SCAN_TO_SUBSTR);
7120 pcmpestri(vec, Address(result, 0), mode);
7121 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
7122 subl(cnt1, stride);
7123 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
7124 cmpl(cnt1, cnt2);
7125 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
7126 addptr(result, 16);
7127 jmpb(SCAN_TO_SUBSTR);
7128
7129 // Found a potential substr
7130 bind(FOUND_CANDIDATE);
7131 // Matched whole vector if first element matched (tmp(rcx) == 0).
7132 if (int_cnt2 == stride) {
7133 jccb(Assembler::overflow, RET_FOUND); // OF == 1
7134 } else { // int_cnt2 > 8
7135 jccb(Assembler::overflow, FOUND_SUBSTR);
7136 }
7137 // After pcmpestri tmp(rcx) contains matched element index
7138 // Compute start addr of substr
7139 lea(result, Address(result, tmp, scale1));
7140
7141 // Make sure string is still long enough
7142 subl(cnt1, tmp);
7143 cmpl(cnt1, cnt2);
7144 if (int_cnt2 == stride) {
7145 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
7146 } else { // int_cnt2 > 8
7147 jccb(Assembler::greaterEqual, MATCH_SUBSTR_HEAD);
7148 }
7149 // Left less then substring.
7150
7151 bind(RET_NOT_FOUND);
7152 movl(result, -1);
7153 jmp(EXIT);
7154
7155 if (int_cnt2 > stride) {
7156 // This code is optimized for the case when whole substring
7157 // is matched if its head is matched.
7158 bind(MATCH_SUBSTR_HEAD);
7159 pcmpestri(vec, Address(result, 0), mode);
7160 // Reload only string if does not match
7161 jcc(Assembler::noOverflow, RELOAD_STR); // OF == 0
7162
7163 Label CONT_SCAN_SUBSTR;
7164 // Compare the rest of substring (> 8 chars).
7165 bind(FOUND_SUBSTR);
7166 // First 8 chars are already matched.
7167 negptr(cnt2);
7168 addptr(cnt2, stride);
7169
7170 bind(SCAN_SUBSTR);
7171 subl(cnt1, stride);
7172 cmpl(cnt2, -stride); // Do not read beyond substring
7173 jccb(Assembler::lessEqual, CONT_SCAN_SUBSTR);
7174 // Back-up strings to avoid reading beyond substring:
7175 // cnt1 = cnt1 - cnt2 + 8
7176 addl(cnt1, cnt2); // cnt2 is negative
7177 addl(cnt1, stride);
7178 movl(cnt2, stride); negptr(cnt2);
7179 bind(CONT_SCAN_SUBSTR);
7180 if (int_cnt2 < (int)G) {
7181 int tail_off1 = int_cnt2<<scale1;
7182 int tail_off2 = int_cnt2<<scale2;
7183 if (ae == StrIntrinsicNode::UL) {
7184 pmovzxbw(vec, Address(str2, cnt2, scale2, tail_off2));
7185 } else {
7186 movdqu(vec, Address(str2, cnt2, scale2, tail_off2));
7187 }
7188 pcmpestri(vec, Address(result, cnt2, scale1, tail_off1), mode);
7189 } else {
7190 // calculate index in register to avoid integer overflow (int_cnt2*2)
7191 movl(tmp, int_cnt2);
7192 addptr(tmp, cnt2);
7193 if (ae == StrIntrinsicNode::UL) {
7194 pmovzxbw(vec, Address(str2, tmp, scale2, 0));
7195 } else {
7196 movdqu(vec, Address(str2, tmp, scale2, 0));
7197 }
7198 pcmpestri(vec, Address(result, tmp, scale1, 0), mode);
7199 }
7200 // Need to reload strings pointers if not matched whole vector
7201 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
7202 addptr(cnt2, stride);
7203 jcc(Assembler::negative, SCAN_SUBSTR);
7204 // Fall through if found full substring
7205
7206 } // (int_cnt2 > 8)
7207
7208 bind(RET_FOUND);
7209 // Found result if we matched full small substring.
7210 // Compute substr offset
7211 subptr(result, str1);
7212 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
7213 shrl(result, 1); // index
7214 }
7215 bind(EXIT);
7216
7217 } // string_indexofC8
7218
7219 // Small strings are loaded through stack if they cross page boundary.
7220 void MacroAssembler::string_indexof(Register str1, Register str2,
7221 Register cnt1, Register cnt2,
7222 int int_cnt2, Register result,
7223 XMMRegister vec, Register tmp,
7224 int ae) {
7225 ShortBranchVerifier sbv(this);
7226 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
7227 assert(UseSSE >= 4, "SSE4 must be enabled for SSE4.2 intrinsics to be available");
7228 assert(ae != StrIntrinsicNode::LU, "Invalid encoding");
7229
7230 //
7231 // int_cnt2 is length of small (< 8 chars) constant substring
7232 // or (-1) for non constant substring in which case its length
7233 // is in cnt2 register.
7234 //
7235 // Note, inline_string_indexOf() generates checks:
7236 // if (substr.count > string.count) return -1;
7237 // if (substr.count == 0) return 0;
7238 //
7239 int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8
7240 assert(int_cnt2 == -1 || (0 < int_cnt2 && int_cnt2 < stride), "should be != 0");
7241 // This method uses the pcmpestri instruction with bound registers
7242 // inputs:
7243 // xmm - substring
7244 // rax - substring length (elements count)
7245 // mem - scanned string
7246 // rdx - string length (elements count)
7247 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
7248 // 0xc - mode: 1100 (substring search) + 00 (unsigned bytes)
7249 // outputs:
7250 // rcx - matched index in string
7251 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
7252 int mode = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts
7253 Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2;
7254 Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1;
7255
7256 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, ADJUST_STR,
7257 RET_FOUND, RET_NOT_FOUND, CLEANUP, FOUND_SUBSTR,
7258 FOUND_CANDIDATE;
7259
7260 { //========================================================
7261 // We don't know where these strings are located
7262 // and we can't read beyond them. Load them through stack.
7263 Label BIG_STRINGS, CHECK_STR, COPY_SUBSTR, COPY_STR;
7264
7265 movptr(tmp, rsp); // save old SP
7266
7267 if (int_cnt2 > 0) { // small (< 8 chars) constant substring
7268 if (int_cnt2 == (1>>scale2)) { // One byte
7269 assert((ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL), "Only possible for latin1 encoding");
7270 load_unsigned_byte(result, Address(str2, 0));
7271 movdl(vec, result); // move 32 bits
7272 } else if (ae == StrIntrinsicNode::LL && int_cnt2 == 3) { // Three bytes
7273 // Not enough header space in 32-bit VM: 12+3 = 15.
7274 movl(result, Address(str2, -1));
7275 shrl(result, 8);
7276 movdl(vec, result); // move 32 bits
7277 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (2>>scale2)) { // One char
7278 load_unsigned_short(result, Address(str2, 0));
7279 movdl(vec, result); // move 32 bits
7280 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (4>>scale2)) { // Two chars
7281 movdl(vec, Address(str2, 0)); // move 32 bits
7282 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (8>>scale2)) { // Four chars
7283 movq(vec, Address(str2, 0)); // move 64 bits
7284 } else { // cnt2 = { 3, 5, 6, 7 } || (ae == StrIntrinsicNode::UL && cnt2 ={2, ..., 7})
7285 // Array header size is 12 bytes in 32-bit VM
7286 // + 6 bytes for 3 chars == 18 bytes,
7287 // enough space to load vec and shift.
7288 assert(HeapWordSize*TypeArrayKlass::header_size() >= 12,"sanity");
7289 if (ae == StrIntrinsicNode::UL) {
7290 int tail_off = int_cnt2-8;
7291 pmovzxbw(vec, Address(str2, tail_off));
7292 psrldq(vec, -2*tail_off);
7293 }
7294 else {
7295 int tail_off = int_cnt2*(1<<scale2);
7296 movdqu(vec, Address(str2, tail_off-16));
7297 psrldq(vec, 16-tail_off);
7298 }
7299 }
7300 } else { // not constant substring
7301 cmpl(cnt2, stride);
7302 jccb(Assembler::aboveEqual, BIG_STRINGS); // Both strings are big enough
7303
7304 // We can read beyond string if srt+16 does not cross page boundary
7305 // since heaps are aligned and mapped by pages.
7306 assert(os::vm_page_size() < (int)G, "default page should be small");
7307 movl(result, str2); // We need only low 32 bits
7308 andl(result, (os::vm_page_size()-1));
7309 cmpl(result, (os::vm_page_size()-16));
7310 jccb(Assembler::belowEqual, CHECK_STR);
7311
7312 // Move small strings to stack to allow load 16 bytes into vec.
7313 subptr(rsp, 16);
7314 int stk_offset = wordSize-(1<<scale2);
7315 push(cnt2);
7316
7317 bind(COPY_SUBSTR);
7318 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL) {
7319 load_unsigned_byte(result, Address(str2, cnt2, scale2, -1));
7320 movb(Address(rsp, cnt2, scale2, stk_offset), result);
7321 } else if (ae == StrIntrinsicNode::UU) {
7322 load_unsigned_short(result, Address(str2, cnt2, scale2, -2));
7323 movw(Address(rsp, cnt2, scale2, stk_offset), result);
7324 }
7325 decrement(cnt2);
7326 jccb(Assembler::notZero, COPY_SUBSTR);
7327
7328 pop(cnt2);
7329 movptr(str2, rsp); // New substring address
7330 } // non constant
7331
7332 bind(CHECK_STR);
7333 cmpl(cnt1, stride);
7334 jccb(Assembler::aboveEqual, BIG_STRINGS);
7335
7336 // Check cross page boundary.
7337 movl(result, str1); // We need only low 32 bits
7338 andl(result, (os::vm_page_size()-1));
7339 cmpl(result, (os::vm_page_size()-16));
7340 jccb(Assembler::belowEqual, BIG_STRINGS);
7341
7342 subptr(rsp, 16);
7343 int stk_offset = -(1<<scale1);
7344 if (int_cnt2 < 0) { // not constant
7345 push(cnt2);
7346 stk_offset += wordSize;
7347 }
7348 movl(cnt2, cnt1);
7349
7350 bind(COPY_STR);
7351 if (ae == StrIntrinsicNode::LL) {
7352 load_unsigned_byte(result, Address(str1, cnt2, scale1, -1));
7353 movb(Address(rsp, cnt2, scale1, stk_offset), result);
7354 } else {
7355 load_unsigned_short(result, Address(str1, cnt2, scale1, -2));
7356 movw(Address(rsp, cnt2, scale1, stk_offset), result);
7357 }
7358 decrement(cnt2);
7359 jccb(Assembler::notZero, COPY_STR);
7360
7361 if (int_cnt2 < 0) { // not constant
7362 pop(cnt2);
7363 }
7364 movptr(str1, rsp); // New string address
7365
7366 bind(BIG_STRINGS);
7367 // Load substring.
7368 if (int_cnt2 < 0) { // -1
7369 if (ae == StrIntrinsicNode::UL) {
7370 pmovzxbw(vec, Address(str2, 0));
7371 } else {
7372 movdqu(vec, Address(str2, 0));
7373 }
7374 push(cnt2); // substr count
7375 push(str2); // substr addr
7376 push(str1); // string addr
7377 } else {
7378 // Small (< 8 chars) constant substrings are loaded already.
7379 movl(cnt2, int_cnt2);
7380 }
7381 push(tmp); // original SP
7382
7383 } // Finished loading
7384
7385 //========================================================
7386 // Start search
7387 //
7388
7389 movptr(result, str1); // string addr
7390
7391 if (int_cnt2 < 0) { // Only for non constant substring
7392 jmpb(SCAN_TO_SUBSTR);
7393
7394 // SP saved at sp+0
7395 // String saved at sp+1*wordSize
7396 // Substr saved at sp+2*wordSize
7397 // Substr count saved at sp+3*wordSize
7398
7399 // Reload substr for rescan, this code
7400 // is executed only for large substrings (> 8 chars)
7401 bind(RELOAD_SUBSTR);
7402 movptr(str2, Address(rsp, 2*wordSize));
7403 movl(cnt2, Address(rsp, 3*wordSize));
7404 if (ae == StrIntrinsicNode::UL) {
7405 pmovzxbw(vec, Address(str2, 0));
7406 } else {
7407 movdqu(vec, Address(str2, 0));
7408 }
7409 // We came here after the beginning of the substring was
7410 // matched but the rest of it was not so we need to search
7411 // again. Start from the next element after the previous match.
7412 subptr(str1, result); // Restore counter
7413 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
7414 shrl(str1, 1);
7415 }
7416 addl(cnt1, str1);
7417 decrementl(cnt1); // Shift to next element
7418 cmpl(cnt1, cnt2);
7419 jcc(Assembler::negative, RET_NOT_FOUND); // Left less then substring
7420
7421 addptr(result, (1<<scale1));
7422 } // non constant
7423
7424 // Scan string for start of substr in 16-byte vectors
7425 bind(SCAN_TO_SUBSTR);
7426 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
7427 pcmpestri(vec, Address(result, 0), mode);
7428 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
7429 subl(cnt1, stride);
7430 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
7431 cmpl(cnt1, cnt2);
7432 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
7433 addptr(result, 16);
7434
7435 bind(ADJUST_STR);
7436 cmpl(cnt1, stride); // Do not read beyond string
7437 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
7438 // Back-up string to avoid reading beyond string.
7439 lea(result, Address(result, cnt1, scale1, -16));
7440 movl(cnt1, stride);
7441 jmpb(SCAN_TO_SUBSTR);
7442
7443 // Found a potential substr
7444 bind(FOUND_CANDIDATE);
7445 // After pcmpestri tmp(rcx) contains matched element index
7446
7447 // Make sure string is still long enough
7448 subl(cnt1, tmp);
7449 cmpl(cnt1, cnt2);
7450 jccb(Assembler::greaterEqual, FOUND_SUBSTR);
7451 // Left less then substring.
7452
7453 bind(RET_NOT_FOUND);
7454 movl(result, -1);
7455 jmpb(CLEANUP);
7456
7457 bind(FOUND_SUBSTR);
7458 // Compute start addr of substr
7459 lea(result, Address(result, tmp, scale1));
7460 if (int_cnt2 > 0) { // Constant substring
7461 // Repeat search for small substring (< 8 chars)
7462 // from new point without reloading substring.
7463 // Have to check that we don't read beyond string.
7464 cmpl(tmp, stride-int_cnt2);
7465 jccb(Assembler::greater, ADJUST_STR);
7466 // Fall through if matched whole substring.
7467 } else { // non constant
7468 assert(int_cnt2 == -1, "should be != 0");
7469
7470 addl(tmp, cnt2);
7471 // Found result if we matched whole substring.
7472 cmpl(tmp, stride);
7473 jccb(Assembler::lessEqual, RET_FOUND);
7474
7475 // Repeat search for small substring (<= 8 chars)
7476 // from new point 'str1' without reloading substring.
7477 cmpl(cnt2, stride);
7478 // Have to check that we don't read beyond string.
7479 jccb(Assembler::lessEqual, ADJUST_STR);
7480
7481 Label CHECK_NEXT, CONT_SCAN_SUBSTR, RET_FOUND_LONG;
7482 // Compare the rest of substring (> 8 chars).
7483 movptr(str1, result);
7484
7485 cmpl(tmp, cnt2);
7486 // First 8 chars are already matched.
7487 jccb(Assembler::equal, CHECK_NEXT);
7488
7489 bind(SCAN_SUBSTR);
7490 pcmpestri(vec, Address(str1, 0), mode);
7491 // Need to reload strings pointers if not matched whole vector
7492 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
7493
7494 bind(CHECK_NEXT);
7495 subl(cnt2, stride);
7496 jccb(Assembler::lessEqual, RET_FOUND_LONG); // Found full substring
7497 addptr(str1, 16);
7498 if (ae == StrIntrinsicNode::UL) {
7499 addptr(str2, 8);
7500 } else {
7501 addptr(str2, 16);
7502 }
7503 subl(cnt1, stride);
7504 cmpl(cnt2, stride); // Do not read beyond substring
7505 jccb(Assembler::greaterEqual, CONT_SCAN_SUBSTR);
7506 // Back-up strings to avoid reading beyond substring.
7507
7508 if (ae == StrIntrinsicNode::UL) {
7509 lea(str2, Address(str2, cnt2, scale2, -8));
7510 lea(str1, Address(str1, cnt2, scale1, -16));
7511 } else {
7512 lea(str2, Address(str2, cnt2, scale2, -16));
7513 lea(str1, Address(str1, cnt2, scale1, -16));
7514 }
7515 subl(cnt1, cnt2);
7516 movl(cnt2, stride);
7517 addl(cnt1, stride);
7518 bind(CONT_SCAN_SUBSTR);
7519 if (ae == StrIntrinsicNode::UL) {
7520 pmovzxbw(vec, Address(str2, 0));
7521 } else {
7522 movdqu(vec, Address(str2, 0));
7523 }
7524 jmp(SCAN_SUBSTR);
7525
7526 bind(RET_FOUND_LONG);
7527 movptr(str1, Address(rsp, wordSize));
7528 } // non constant
7529
7530 bind(RET_FOUND);
7531 // Compute substr offset
7532 subptr(result, str1);
7533 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
7534 shrl(result, 1); // index
7535 }
7536 bind(CLEANUP);
7537 pop(rsp); // restore SP
7538
7539 } // string_indexof
7540
7541 void MacroAssembler::string_indexof_char(Register str1, Register cnt1, Register ch, Register result,
7542 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp) {
7543 ShortBranchVerifier sbv(this);
7544 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
7545 assert(UseSSE >= 4, "SSE4 must be enabled for SSE4.2 intrinsics to be available");
7546
7547 int stride = 8;
7548
7549 Label FOUND_CHAR, SCAN_TO_CHAR, SCAN_TO_CHAR_LOOP,
7550 SCAN_TO_8_CHAR, SCAN_TO_8_CHAR_LOOP, SCAN_TO_16_CHAR_LOOP,
7551 RET_NOT_FOUND, SCAN_TO_8_CHAR_INIT,
7552 FOUND_SEQ_CHAR, DONE_LABEL;
7553
7554 movptr(result, str1);
7555 if (UseAVX >= 2) {
7556 cmpl(cnt1, stride);
7557 jcc(Assembler::less, SCAN_TO_CHAR_LOOP);
7558 cmpl(cnt1, 2*stride);
7559 jcc(Assembler::less, SCAN_TO_8_CHAR_INIT);
7560 movdl(vec1, ch);
7561 vpbroadcastw(vec1, vec1);
7562 vpxor(vec2, vec2);
7563 movl(tmp, cnt1);
7564 andl(tmp, 0xFFFFFFF0); //vector count (in chars)
7565 andl(cnt1,0x0000000F); //tail count (in chars)
7566
7567 bind(SCAN_TO_16_CHAR_LOOP);
7568 vmovdqu(vec3, Address(result, 0));
7569 vpcmpeqw(vec3, vec3, vec1, 1);
7570 vptest(vec2, vec3);
7571 jcc(Assembler::carryClear, FOUND_CHAR);
7572 addptr(result, 32);
7573 subl(tmp, 2*stride);
7574 jccb(Assembler::notZero, SCAN_TO_16_CHAR_LOOP);
7575 jmp(SCAN_TO_8_CHAR);
7576 bind(SCAN_TO_8_CHAR_INIT);
7577 movdl(vec1, ch);
7578 pshuflw(vec1, vec1, 0x00);
7579 pshufd(vec1, vec1, 0);
7580 pxor(vec2, vec2);
7581 }
7582 bind(SCAN_TO_8_CHAR);
7583 cmpl(cnt1, stride);
7584 if (UseAVX >= 2) {
7585 jcc(Assembler::less, SCAN_TO_CHAR);
7586 } else {
7587 jcc(Assembler::less, SCAN_TO_CHAR_LOOP);
7588 movdl(vec1, ch);
7589 pshuflw(vec1, vec1, 0x00);
7590 pshufd(vec1, vec1, 0);
7591 pxor(vec2, vec2);
7592 }
7593 movl(tmp, cnt1);
7594 andl(tmp, 0xFFFFFFF8); //vector count (in chars)
7595 andl(cnt1,0x00000007); //tail count (in chars)
7596
7597 bind(SCAN_TO_8_CHAR_LOOP);
7598 movdqu(vec3, Address(result, 0));
7599 pcmpeqw(vec3, vec1);
7600 ptest(vec2, vec3);
7601 jcc(Assembler::carryClear, FOUND_CHAR);
7602 addptr(result, 16);
7603 subl(tmp, stride);
7604 jccb(Assembler::notZero, SCAN_TO_8_CHAR_LOOP);
7605 bind(SCAN_TO_CHAR);
7606 testl(cnt1, cnt1);
7607 jcc(Assembler::zero, RET_NOT_FOUND);
7608 bind(SCAN_TO_CHAR_LOOP);
7609 load_unsigned_short(tmp, Address(result, 0));
7610 cmpl(ch, tmp);
7611 jccb(Assembler::equal, FOUND_SEQ_CHAR);
7612 addptr(result, 2);
7613 subl(cnt1, 1);
7614 jccb(Assembler::zero, RET_NOT_FOUND);
7615 jmp(SCAN_TO_CHAR_LOOP);
7616
7617 bind(RET_NOT_FOUND);
7618 movl(result, -1);
7619 jmpb(DONE_LABEL);
7620
7621 bind(FOUND_CHAR);
7622 if (UseAVX >= 2) {
7623 vpmovmskb(tmp, vec3);
7624 } else {
7625 pmovmskb(tmp, vec3);
7626 }
7627 bsfl(ch, tmp);
7628 addl(result, ch);
7629
7630 bind(FOUND_SEQ_CHAR);
7631 subptr(result, str1);
7632 shrl(result, 1);
7633
7634 bind(DONE_LABEL);
7635 } // string_indexof_char
7636
7637 // helper function for string_compare
7638 void MacroAssembler::load_next_elements(Register elem1, Register elem2, Register str1, Register str2,
7639 Address::ScaleFactor scale, Address::ScaleFactor scale1,
7640 Address::ScaleFactor scale2, Register index, int ae) {
7641 if (ae == StrIntrinsicNode::LL) {
7642 load_unsigned_byte(elem1, Address(str1, index, scale, 0));
7643 load_unsigned_byte(elem2, Address(str2, index, scale, 0));
7644 } else if (ae == StrIntrinsicNode::UU) {
7645 load_unsigned_short(elem1, Address(str1, index, scale, 0));
7646 load_unsigned_short(elem2, Address(str2, index, scale, 0));
7647 } else {
7648 load_unsigned_byte(elem1, Address(str1, index, scale1, 0));
7649 load_unsigned_short(elem2, Address(str2, index, scale2, 0));
7650 }
7651 }
7652
7653 // Compare strings, used for char[] and byte[].
7654 void MacroAssembler::string_compare(Register str1, Register str2,
7655 Register cnt1, Register cnt2, Register result,
7656 XMMRegister vec1, int ae) {
7657 ShortBranchVerifier sbv(this);
7658 Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL;
7659 Label COMPARE_WIDE_VECTORS_LOOP_FAILED; // used only _LP64 && AVX3
7660 int stride, stride2, adr_stride, adr_stride1, adr_stride2;
7661 int stride2x2 = 0x40;
7662 Address::ScaleFactor scale = Address::no_scale;
7663 Address::ScaleFactor scale1 = Address::no_scale;
7664 Address::ScaleFactor scale2 = Address::no_scale;
7665
7666 if (ae != StrIntrinsicNode::LL) {
7667 stride2x2 = 0x20;
7668 }
7669
7670 if (ae == StrIntrinsicNode::LU || ae == StrIntrinsicNode::UL) {
7671 shrl(cnt2, 1);
7672 }
7673 // Compute the minimum of the string lengths and the
7674 // difference of the string lengths (stack).
7675 // Do the conditional move stuff
7676 movl(result, cnt1);
7677 subl(cnt1, cnt2);
7678 push(cnt1);
7679 cmov32(Assembler::lessEqual, cnt2, result); // cnt2 = min(cnt1, cnt2)
7680
7681 // Is the minimum length zero?
7682 testl(cnt2, cnt2);
7683 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
7684 if (ae == StrIntrinsicNode::LL) {
7685 // Load first bytes
7686 load_unsigned_byte(result, Address(str1, 0)); // result = str1[0]
7687 load_unsigned_byte(cnt1, Address(str2, 0)); // cnt1 = str2[0]
7688 } else if (ae == StrIntrinsicNode::UU) {
7689 // Load first characters
7690 load_unsigned_short(result, Address(str1, 0));
7691 load_unsigned_short(cnt1, Address(str2, 0));
7692 } else {
7693 load_unsigned_byte(result, Address(str1, 0));
7694 load_unsigned_short(cnt1, Address(str2, 0));
7695 }
7696 subl(result, cnt1);
7697 jcc(Assembler::notZero, POP_LABEL);
7698
7699 if (ae == StrIntrinsicNode::UU) {
7700 // Divide length by 2 to get number of chars
7701 shrl(cnt2, 1);
7702 }
7703 cmpl(cnt2, 1);
7704 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
7705
7706 // Check if the strings start at the same location and setup scale and stride
7707 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7708 cmpptr(str1, str2);
7709 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
7710 if (ae == StrIntrinsicNode::LL) {
7711 scale = Address::times_1;
7712 stride = 16;
7713 } else {
7714 scale = Address::times_2;
7715 stride = 8;
7716 }
7717 } else {
7718 scale1 = Address::times_1;
7719 scale2 = Address::times_2;
7720 // scale not used
7721 stride = 8;
7722 }
7723
7724 if (UseAVX >= 2 && UseSSE42Intrinsics) {
7725 assert(UseSSE >= 4, "SSE4 must be enabled for SSE4.2 intrinsics to be available");
7726 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_WIDE_TAIL, COMPARE_SMALL_STR;
7727 Label COMPARE_WIDE_VECTORS_LOOP, COMPARE_16_CHARS, COMPARE_INDEX_CHAR;
7728 Label COMPARE_WIDE_VECTORS_LOOP_AVX2;
7729 Label COMPARE_TAIL_LONG;
7730 Label COMPARE_WIDE_VECTORS_LOOP_AVX3; // used only _LP64 && AVX3
7731
7732 int pcmpmask = 0x19;
7733 if (ae == StrIntrinsicNode::LL) {
7734 pcmpmask &= ~0x01;
7735 }
7736
7737 // Setup to compare 16-chars (32-bytes) vectors,
7738 // start from first character again because it has aligned address.
7739 if (ae == StrIntrinsicNode::LL) {
7740 stride2 = 32;
7741 } else {
7742 stride2 = 16;
7743 }
7744 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7745 adr_stride = stride << scale;
7746 } else {
7747 adr_stride1 = 8; //stride << scale1;
7748 adr_stride2 = 16; //stride << scale2;
7749 }
7750
7751 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
7752 // rax and rdx are used by pcmpestri as elements counters
7753 movl(result, cnt2);
7754 andl(cnt2, ~(stride2-1)); // cnt2 holds the vector count
7755 jcc(Assembler::zero, COMPARE_TAIL_LONG);
7756
7757 // fast path : compare first 2 8-char vectors.
7758 bind(COMPARE_16_CHARS);
7759 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7760 movdqu(vec1, Address(str1, 0));
7761 } else {
7762 pmovzxbw(vec1, Address(str1, 0));
7763 }
7764 pcmpestri(vec1, Address(str2, 0), pcmpmask);
7765 jccb(Assembler::below, COMPARE_INDEX_CHAR);
7766
7767 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7768 movdqu(vec1, Address(str1, adr_stride));
7769 pcmpestri(vec1, Address(str2, adr_stride), pcmpmask);
7770 } else {
7771 pmovzxbw(vec1, Address(str1, adr_stride1));
7772 pcmpestri(vec1, Address(str2, adr_stride2), pcmpmask);
7773 }
7774 jccb(Assembler::aboveEqual, COMPARE_WIDE_VECTORS);
7775 addl(cnt1, stride);
7776
7777 // Compare the characters at index in cnt1
7778 bind(COMPARE_INDEX_CHAR); // cnt1 has the offset of the mismatching character
7779 load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae);
7780 subl(result, cnt2);
7781 jmp(POP_LABEL);
7782
7783 // Setup the registers to start vector comparison loop
7784 bind(COMPARE_WIDE_VECTORS);
7785 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7786 lea(str1, Address(str1, result, scale));
7787 lea(str2, Address(str2, result, scale));
7788 } else {
7789 lea(str1, Address(str1, result, scale1));
7790 lea(str2, Address(str2, result, scale2));
7791 }
7792 subl(result, stride2);
7793 subl(cnt2, stride2);
7794 jcc(Assembler::zero, COMPARE_WIDE_TAIL);
7795 negptr(result);
7796
7797 // In a loop, compare 16-chars (32-bytes) at once using (vpxor+vptest)
7798 bind(COMPARE_WIDE_VECTORS_LOOP);
7799
7800 #ifdef _LP64
7801 if (VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop
7802 cmpl(cnt2, stride2x2);
7803 jccb(Assembler::below, COMPARE_WIDE_VECTORS_LOOP_AVX2);
7804 testl(cnt2, stride2x2-1); // cnt2 holds the vector count
7805 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX2); // means we cannot subtract by 0x40
7806
7807 bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop
7808 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7809 evmovdquq(vec1, Address(str1, result, scale), Assembler::AVX_512bit);
7810 evpcmpeqb(k7, vec1, Address(str2, result, scale), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0
7811 } else {
7812 vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_512bit);
7813 evpcmpeqb(k7, vec1, Address(str2, result, scale2), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0
7814 }
7815 kortestql(k7, k7);
7816 jcc(Assembler::aboveEqual, COMPARE_WIDE_VECTORS_LOOP_FAILED); // miscompare
7817 addptr(result, stride2x2); // update since we already compared at this addr
7818 subl(cnt2, stride2x2); // and sub the size too
7819 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX3);
7820
7821 vpxor(vec1, vec1);
7822 jmpb(COMPARE_WIDE_TAIL);
7823 }//if (VM_Version::supports_avx512vlbw())
7824 #endif // _LP64
7825
7826
7827 bind(COMPARE_WIDE_VECTORS_LOOP_AVX2);
7828 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7829 vmovdqu(vec1, Address(str1, result, scale));
7830 vpxor(vec1, Address(str2, result, scale));
7831 } else {
7832 vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_256bit);
7833 vpxor(vec1, Address(str2, result, scale2));
7834 }
7835 vptest(vec1, vec1);
7836 jcc(Assembler::notZero, VECTOR_NOT_EQUAL);
7837 addptr(result, stride2);
7838 subl(cnt2, stride2);
7839 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP);
7840 // clean upper bits of YMM registers
7841 vpxor(vec1, vec1);
7842
7843 // compare wide vectors tail
7844 bind(COMPARE_WIDE_TAIL);
7845 testptr(result, result);
7846 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
7847
7848 movl(result, stride2);
7849 movl(cnt2, result);
7850 negptr(result);
7851 jmp(COMPARE_WIDE_VECTORS_LOOP_AVX2);
7852
7853 // Identifies the mismatching (higher or lower)16-bytes in the 32-byte vectors.
7854 bind(VECTOR_NOT_EQUAL);
7855 // clean upper bits of YMM registers
7856 vpxor(vec1, vec1);
7857 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7858 lea(str1, Address(str1, result, scale));
7859 lea(str2, Address(str2, result, scale));
7860 } else {
7861 lea(str1, Address(str1, result, scale1));
7862 lea(str2, Address(str2, result, scale2));
7863 }
7864 jmp(COMPARE_16_CHARS);
7865
7866 // Compare tail chars, length between 1 to 15 chars
7867 bind(COMPARE_TAIL_LONG);
7868 movl(cnt2, result);
7869 cmpl(cnt2, stride);
7870 jcc(Assembler::less, COMPARE_SMALL_STR);
7871
7872 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7873 movdqu(vec1, Address(str1, 0));
7874 } else {
7875 pmovzxbw(vec1, Address(str1, 0));
7876 }
7877 pcmpestri(vec1, Address(str2, 0), pcmpmask);
7878 jcc(Assembler::below, COMPARE_INDEX_CHAR);
7879 subptr(cnt2, stride);
7880 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
7881 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7882 lea(str1, Address(str1, result, scale));
7883 lea(str2, Address(str2, result, scale));
7884 } else {
7885 lea(str1, Address(str1, result, scale1));
7886 lea(str2, Address(str2, result, scale2));
7887 }
7888 negptr(cnt2);
7889 jmpb(WHILE_HEAD_LABEL);
7890
7891 bind(COMPARE_SMALL_STR);
7892 } else if (UseSSE42Intrinsics) {
7893 assert(UseSSE >= 4, "SSE4 must be enabled for SSE4.2 intrinsics to be available");
7894 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL;
7895 int pcmpmask = 0x19;
7896 // Setup to compare 8-char (16-byte) vectors,
7897 // start from first character again because it has aligned address.
7898 movl(result, cnt2);
7899 andl(cnt2, ~(stride - 1)); // cnt2 holds the vector count
7900 if (ae == StrIntrinsicNode::LL) {
7901 pcmpmask &= ~0x01;
7902 }
7903 jcc(Assembler::zero, COMPARE_TAIL);
7904 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7905 lea(str1, Address(str1, result, scale));
7906 lea(str2, Address(str2, result, scale));
7907 } else {
7908 lea(str1, Address(str1, result, scale1));
7909 lea(str2, Address(str2, result, scale2));
7910 }
7911 negptr(result);
7912
7913 // pcmpestri
7914 // inputs:
7915 // vec1- substring
7916 // rax - negative string length (elements count)
7917 // mem - scanned string
7918 // rdx - string length (elements count)
7919 // pcmpmask - cmp mode: 11000 (string compare with negated result)
7920 // + 00 (unsigned bytes) or + 01 (unsigned shorts)
7921 // outputs:
7922 // rcx - first mismatched element index
7923 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
7924
7925 bind(COMPARE_WIDE_VECTORS);
7926 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7927 movdqu(vec1, Address(str1, result, scale));
7928 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
7929 } else {
7930 pmovzxbw(vec1, Address(str1, result, scale1));
7931 pcmpestri(vec1, Address(str2, result, scale2), pcmpmask);
7932 }
7933 // After pcmpestri cnt1(rcx) contains mismatched element index
7934
7935 jccb(Assembler::below, VECTOR_NOT_EQUAL); // CF==1
7936 addptr(result, stride);
7937 subptr(cnt2, stride);
7938 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS);
7939
7940 // compare wide vectors tail
7941 testptr(result, result);
7942 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
7943
7944 movl(cnt2, stride);
7945 movl(result, stride);
7946 negptr(result);
7947 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7948 movdqu(vec1, Address(str1, result, scale));
7949 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
7950 } else {
7951 pmovzxbw(vec1, Address(str1, result, scale1));
7952 pcmpestri(vec1, Address(str2, result, scale2), pcmpmask);
7953 }
7954 jccb(Assembler::aboveEqual, LENGTH_DIFF_LABEL);
7955
7956 // Mismatched characters in the vectors
7957 bind(VECTOR_NOT_EQUAL);
7958 addptr(cnt1, result);
7959 load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae);
7960 subl(result, cnt2);
7961 jmpb(POP_LABEL);
7962
7963 bind(COMPARE_TAIL); // limit is zero
7964 movl(cnt2, result);
7965 // Fallthru to tail compare
7966 }
7967 // Shift str2 and str1 to the end of the arrays, negate min
7968 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7969 lea(str1, Address(str1, cnt2, scale));
7970 lea(str2, Address(str2, cnt2, scale));
7971 } else {
7972 lea(str1, Address(str1, cnt2, scale1));
7973 lea(str2, Address(str2, cnt2, scale2));
7974 }
7975 decrementl(cnt2); // first character was compared already
7976 negptr(cnt2);
7977
7978 // Compare the rest of the elements
7979 bind(WHILE_HEAD_LABEL);
7980 load_next_elements(result, cnt1, str1, str2, scale, scale1, scale2, cnt2, ae);
7981 subl(result, cnt1);
7982 jccb(Assembler::notZero, POP_LABEL);
7983 increment(cnt2);
7984 jccb(Assembler::notZero, WHILE_HEAD_LABEL);
7985
7986 // Strings are equal up to min length. Return the length difference.
7987 bind(LENGTH_DIFF_LABEL);
7988 pop(result);
7989 if (ae == StrIntrinsicNode::UU) {
7990 // Divide diff by 2 to get number of chars
7991 sarl(result, 1);
7992 }
7993 jmpb(DONE_LABEL);
7994
7995 #ifdef _LP64
7996 if (VM_Version::supports_avx512vlbw()) {
7997
7998 bind(COMPARE_WIDE_VECTORS_LOOP_FAILED);
7999
8000 kmovql(cnt1, k7);
8001 notq(cnt1);
8002 bsfq(cnt2, cnt1);
8003 if (ae != StrIntrinsicNode::LL) {
8004 // Divide diff by 2 to get number of chars
8005 sarl(cnt2, 1);
8006 }
8007 addq(result, cnt2);
8008 if (ae == StrIntrinsicNode::LL) {
8009 load_unsigned_byte(cnt1, Address(str2, result));
8010 load_unsigned_byte(result, Address(str1, result));
8011 } else if (ae == StrIntrinsicNode::UU) {
8012 load_unsigned_short(cnt1, Address(str2, result, scale));
8013 load_unsigned_short(result, Address(str1, result, scale));
8014 } else {
8015 load_unsigned_short(cnt1, Address(str2, result, scale2));
8016 load_unsigned_byte(result, Address(str1, result, scale1));
8017 }
8018 subl(result, cnt1);
8019 jmpb(POP_LABEL);
8020 }//if (VM_Version::supports_avx512vlbw())
8021 #endif // _LP64
8022
8023 // Discard the stored length difference
8024 bind(POP_LABEL);
8025 pop(cnt1);
8026
8027 // That's it
8028 bind(DONE_LABEL);
8029 if(ae == StrIntrinsicNode::UL) {
8030 negl(result);
8031 }
8032
8033 }
8034
8035 // Search for Non-ASCII character (Negative byte value) in a byte array,
8036 // return true if it has any and false otherwise.
8037 // ..\jdk\src\java.base\share\classes\java\lang\StringCoding.java
8038 // @HotSpotIntrinsicCandidate
8039 // private static boolean hasNegatives(byte[] ba, int off, int len) {
8040 // for (int i = off; i < off + len; i++) {
8041 // if (ba[i] < 0) {
8042 // return true;
8043 // }
8044 // }
8045 // return false;
8046 // }
8047 void MacroAssembler::has_negatives(Register ary1, Register len,
8048 Register result, Register tmp1,
8049 XMMRegister vec1, XMMRegister vec2) {
8050 // rsi: byte array
8051 // rcx: len
8052 // rax: result
8053 ShortBranchVerifier sbv(this);
8054 assert_different_registers(ary1, len, result, tmp1);
8055 assert_different_registers(vec1, vec2);
8056 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_CHAR, COMPARE_VECTORS, COMPARE_BYTE;
8057
8058 // len == 0
8059 testl(len, len);
8060 jcc(Assembler::zero, FALSE_LABEL);
8061
8062 if ((UseAVX > 2) && // AVX512
8063 VM_Version::supports_avx512vlbw() &&
8064 VM_Version::supports_bmi2()) {
8065
8066 set_vector_masking(); // opening of the stub context for programming mask registers
8067
8068 Label test_64_loop, test_tail;
8069 Register tmp3_aliased = len;
8070
8071 movl(tmp1, len);
8072 vpxor(vec2, vec2, vec2, Assembler::AVX_512bit);
8073
8074 andl(tmp1, 64 - 1); // tail count (in chars) 0x3F
8075 andl(len, ~(64 - 1)); // vector count (in chars)
8076 jccb(Assembler::zero, test_tail);
8077
8078 lea(ary1, Address(ary1, len, Address::times_1));
8079 negptr(len);
8080
8081 bind(test_64_loop);
8082 // Check whether our 64 elements of size byte contain negatives
8083 evpcmpgtb(k2, vec2, Address(ary1, len, Address::times_1), Assembler::AVX_512bit);
8084 kortestql(k2, k2);
8085 jcc(Assembler::notZero, TRUE_LABEL);
8086
8087 addptr(len, 64);
8088 jccb(Assembler::notZero, test_64_loop);
8089
8090
8091 bind(test_tail);
8092 // bail out when there is nothing to be done
8093 testl(tmp1, -1);
8094 jcc(Assembler::zero, FALSE_LABEL);
8095
8096 // Save k1
8097 kmovql(k3, k1);
8098
8099 // ~(~0 << len) applied up to two times (for 32-bit scenario)
8100 #ifdef _LP64
8101 mov64(tmp3_aliased, 0xFFFFFFFFFFFFFFFF);
8102 shlxq(tmp3_aliased, tmp3_aliased, tmp1);
8103 notq(tmp3_aliased);
8104 kmovql(k1, tmp3_aliased);
8105 #else
8106 Label k_init;
8107 jmp(k_init);
8108
8109 // We could not read 64-bits from a general purpose register thus we move
8110 // data required to compose 64 1's to the instruction stream
8111 // We emit 64 byte wide series of elements from 0..63 which later on would
8112 // be used as a compare targets with tail count contained in tmp1 register.
8113 // Result would be a k1 register having tmp1 consecutive number or 1
8114 // counting from least significant bit.
8115 address tmp = pc();
8116 emit_int64(0x0706050403020100);
8117 emit_int64(0x0F0E0D0C0B0A0908);
8118 emit_int64(0x1716151413121110);
8119 emit_int64(0x1F1E1D1C1B1A1918);
8120 emit_int64(0x2726252423222120);
8121 emit_int64(0x2F2E2D2C2B2A2928);
8122 emit_int64(0x3736353433323130);
8123 emit_int64(0x3F3E3D3C3B3A3938);
8124
8125 bind(k_init);
8126 lea(len, InternalAddress(tmp));
8127 // create mask to test for negative byte inside a vector
8128 evpbroadcastb(vec1, tmp1, Assembler::AVX_512bit);
8129 evpcmpgtb(k1, vec1, Address(len, 0), Assembler::AVX_512bit);
8130
8131 #endif
8132 evpcmpgtb(k2, k1, vec2, Address(ary1, 0), Assembler::AVX_512bit);
8133 ktestq(k2, k1);
8134 // Restore k1
8135 kmovql(k1, k3);
8136 jcc(Assembler::notZero, TRUE_LABEL);
8137
8138 jmp(FALSE_LABEL);
8139
8140 clear_vector_masking(); // closing of the stub context for programming mask registers
8141 }
8142 else {
8143 movl(result, len); // copy
8144
8145 if (UseAVX == 2 && UseSSE >= 2) {
8146 // With AVX2, use 32-byte vector compare
8147 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
8148
8149 // Compare 32-byte vectors
8150 andl(result, 0x0000001f); // tail count (in bytes)
8151 andl(len, 0xffffffe0); // vector count (in bytes)
8152 jccb(Assembler::zero, COMPARE_TAIL);
8153
8154 lea(ary1, Address(ary1, len, Address::times_1));
8155 negptr(len);
8156
8157 movl(tmp1, 0x80808080); // create mask to test for Unicode chars in vector
8158 movdl(vec2, tmp1);
8159 vpbroadcastd(vec2, vec2);
8160
8161 bind(COMPARE_WIDE_VECTORS);
8162 vmovdqu(vec1, Address(ary1, len, Address::times_1));
8163 vptest(vec1, vec2);
8164 jccb(Assembler::notZero, TRUE_LABEL);
8165 addptr(len, 32);
8166 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
8167
8168 testl(result, result);
8169 jccb(Assembler::zero, FALSE_LABEL);
8170
8171 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32));
8172 vptest(vec1, vec2);
8173 jccb(Assembler::notZero, TRUE_LABEL);
8174 jmpb(FALSE_LABEL);
8175
8176 bind(COMPARE_TAIL); // len is zero
8177 movl(len, result);
8178 // Fallthru to tail compare
8179 }
8180 else if (UseSSE42Intrinsics) {
8181 assert(UseSSE >= 4, "SSE4 must be for SSE4.2 intrinsics to be available");
8182 // With SSE4.2, use double quad vector compare
8183 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
8184
8185 // Compare 16-byte vectors
8186 andl(result, 0x0000000f); // tail count (in bytes)
8187 andl(len, 0xfffffff0); // vector count (in bytes)
8188 jccb(Assembler::zero, COMPARE_TAIL);
8189
8190 lea(ary1, Address(ary1, len, Address::times_1));
8191 negptr(len);
8192
8193 movl(tmp1, 0x80808080);
8194 movdl(vec2, tmp1);
8195 pshufd(vec2, vec2, 0);
8196
8197 bind(COMPARE_WIDE_VECTORS);
8198 movdqu(vec1, Address(ary1, len, Address::times_1));
8199 ptest(vec1, vec2);
8200 jccb(Assembler::notZero, TRUE_LABEL);
8201 addptr(len, 16);
8202 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
8203
8204 testl(result, result);
8205 jccb(Assembler::zero, FALSE_LABEL);
8206
8207 movdqu(vec1, Address(ary1, result, Address::times_1, -16));
8208 ptest(vec1, vec2);
8209 jccb(Assembler::notZero, TRUE_LABEL);
8210 jmpb(FALSE_LABEL);
8211
8212 bind(COMPARE_TAIL); // len is zero
8213 movl(len, result);
8214 // Fallthru to tail compare
8215 }
8216 }
8217 // Compare 4-byte vectors
8218 andl(len, 0xfffffffc); // vector count (in bytes)
8219 jccb(Assembler::zero, COMPARE_CHAR);
8220
8221 lea(ary1, Address(ary1, len, Address::times_1));
8222 negptr(len);
8223
8224 bind(COMPARE_VECTORS);
8225 movl(tmp1, Address(ary1, len, Address::times_1));
8226 andl(tmp1, 0x80808080);
8227 jccb(Assembler::notZero, TRUE_LABEL);
8228 addptr(len, 4);
8229 jcc(Assembler::notZero, COMPARE_VECTORS);
8230
8231 // Compare trailing char (final 2 bytes), if any
8232 bind(COMPARE_CHAR);
8233 testl(result, 0x2); // tail char
8234 jccb(Assembler::zero, COMPARE_BYTE);
8235 load_unsigned_short(tmp1, Address(ary1, 0));
8236 andl(tmp1, 0x00008080);
8237 jccb(Assembler::notZero, TRUE_LABEL);
8238 subptr(result, 2);
8239 lea(ary1, Address(ary1, 2));
8240
8241 bind(COMPARE_BYTE);
8242 testl(result, 0x1); // tail byte
8243 jccb(Assembler::zero, FALSE_LABEL);
8244 load_unsigned_byte(tmp1, Address(ary1, 0));
8245 andl(tmp1, 0x00000080);
8246 jccb(Assembler::notEqual, TRUE_LABEL);
8247 jmpb(FALSE_LABEL);
8248
8249 bind(TRUE_LABEL);
8250 movl(result, 1); // return true
8251 jmpb(DONE);
8252
8253 bind(FALSE_LABEL);
8254 xorl(result, result); // return false
8255
8256 // That's it
8257 bind(DONE);
8258 if (UseAVX >= 2 && UseSSE >= 2) {
8259 // clean upper bits of YMM registers
8260 vpxor(vec1, vec1);
8261 vpxor(vec2, vec2);
8262 }
8263 }
8264 // Compare char[] or byte[] arrays aligned to 4 bytes or substrings.
8265 void MacroAssembler::arrays_equals(bool is_array_equ, Register ary1, Register ary2,
8266 Register limit, Register result, Register chr,
8267 XMMRegister vec1, XMMRegister vec2, bool is_char) {
8268 ShortBranchVerifier sbv(this);
8269 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR, COMPARE_BYTE;
8270
8271 int length_offset = arrayOopDesc::length_offset_in_bytes();
8272 int base_offset = arrayOopDesc::base_offset_in_bytes(is_char ? T_CHAR : T_BYTE);
8273
8274 if (is_array_equ) {
8275 // Check the input args
8276 cmpptr(ary1, ary2);
8277 jcc(Assembler::equal, TRUE_LABEL);
8278
8279 // Need additional checks for arrays_equals.
8280 testptr(ary1, ary1);
8281 jcc(Assembler::zero, FALSE_LABEL);
8282 testptr(ary2, ary2);
8283 jcc(Assembler::zero, FALSE_LABEL);
8284
8285 // Check the lengths
8286 movl(limit, Address(ary1, length_offset));
8287 cmpl(limit, Address(ary2, length_offset));
8288 jcc(Assembler::notEqual, FALSE_LABEL);
8289 }
8290
8291 // count == 0
8292 testl(limit, limit);
8293 jcc(Assembler::zero, TRUE_LABEL);
8294
8295 if (is_array_equ) {
8296 // Load array address
8297 lea(ary1, Address(ary1, base_offset));
8298 lea(ary2, Address(ary2, base_offset));
8299 }
8300
8301 if (is_array_equ && is_char) {
8302 // arrays_equals when used for char[].
8303 shll(limit, 1); // byte count != 0
8304 }
8305 movl(result, limit); // copy
8306
8307 if (UseAVX >= 2) {
8308 // With AVX2, use 32-byte vector compare
8309 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
8310
8311 // Compare 32-byte vectors
8312 andl(result, 0x0000001f); // tail count (in bytes)
8313 andl(limit, 0xffffffe0); // vector count (in bytes)
8314 jcc(Assembler::zero, COMPARE_TAIL);
8315
8316 lea(ary1, Address(ary1, limit, Address::times_1));
8317 lea(ary2, Address(ary2, limit, Address::times_1));
8318 negptr(limit);
8319
8320 bind(COMPARE_WIDE_VECTORS);
8321
8322 #ifdef _LP64
8323 if (VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop
8324 Label COMPARE_WIDE_VECTORS_LOOP_AVX2, COMPARE_WIDE_VECTORS_LOOP_AVX3;
8325
8326 cmpl(limit, -64);
8327 jccb(Assembler::greater, COMPARE_WIDE_VECTORS_LOOP_AVX2);
8328
8329 bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop
8330
8331 evmovdquq(vec1, Address(ary1, limit, Address::times_1), Assembler::AVX_512bit);
8332 evpcmpeqb(k7, vec1, Address(ary2, limit, Address::times_1), Assembler::AVX_512bit);
8333 kortestql(k7, k7);
8334 jcc(Assembler::aboveEqual, FALSE_LABEL); // miscompare
8335 addptr(limit, 64); // update since we already compared at this addr
8336 cmpl(limit, -64);
8337 jccb(Assembler::lessEqual, COMPARE_WIDE_VECTORS_LOOP_AVX3);
8338
8339 // At this point we may still need to compare -limit+result bytes.
8340 // We could execute the next two instruction and just continue via non-wide path:
8341 // cmpl(limit, 0);
8342 // jcc(Assembler::equal, COMPARE_TAIL); // true
8343 // But since we stopped at the points ary{1,2}+limit which are
8344 // not farther than 64 bytes from the ends of arrays ary{1,2}+result
8345 // (|limit| <= 32 and result < 32),
8346 // we may just compare the last 64 bytes.
8347 //
8348 addptr(result, -64); // it is safe, bc we just came from this area
8349 evmovdquq(vec1, Address(ary1, result, Address::times_1), Assembler::AVX_512bit);
8350 evpcmpeqb(k7, vec1, Address(ary2, result, Address::times_1), Assembler::AVX_512bit);
8351 kortestql(k7, k7);
8352 jcc(Assembler::aboveEqual, FALSE_LABEL); // miscompare
8353
8354 jmp(TRUE_LABEL);
8355
8356 bind(COMPARE_WIDE_VECTORS_LOOP_AVX2);
8357
8358 }//if (VM_Version::supports_avx512vlbw())
8359 #endif //_LP64
8360
8361 vmovdqu(vec1, Address(ary1, limit, Address::times_1));
8362 vmovdqu(vec2, Address(ary2, limit, Address::times_1));
8363 vpxor(vec1, vec2);
8364
8365 vptest(vec1, vec1);
8366 jcc(Assembler::notZero, FALSE_LABEL);
8367 addptr(limit, 32);
8368 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
8369
8370 testl(result, result);
8371 jcc(Assembler::zero, TRUE_LABEL);
8372
8373 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32));
8374 vmovdqu(vec2, Address(ary2, result, Address::times_1, -32));
8375 vpxor(vec1, vec2);
8376
8377 vptest(vec1, vec1);
8378 jccb(Assembler::notZero, FALSE_LABEL);
8379 jmpb(TRUE_LABEL);
8380
8381 bind(COMPARE_TAIL); // limit is zero
8382 movl(limit, result);
8383 // Fallthru to tail compare
8384 } else if (UseSSE42Intrinsics) {
8385 assert(UseSSE >= 4, "SSE4 must be enabled for SSE4.2 intrinsics to be available");
8386 // With SSE4.2, use double quad vector compare
8387 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
8388
8389 // Compare 16-byte vectors
8390 andl(result, 0x0000000f); // tail count (in bytes)
8391 andl(limit, 0xfffffff0); // vector count (in bytes)
8392 jcc(Assembler::zero, COMPARE_TAIL);
8393
8394 lea(ary1, Address(ary1, limit, Address::times_1));
8395 lea(ary2, Address(ary2, limit, Address::times_1));
8396 negptr(limit);
8397
8398 bind(COMPARE_WIDE_VECTORS);
8399 movdqu(vec1, Address(ary1, limit, Address::times_1));
8400 movdqu(vec2, Address(ary2, limit, Address::times_1));
8401 pxor(vec1, vec2);
8402
8403 ptest(vec1, vec1);
8404 jcc(Assembler::notZero, FALSE_LABEL);
8405 addptr(limit, 16);
8406 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
8407
8408 testl(result, result);
8409 jcc(Assembler::zero, TRUE_LABEL);
8410
8411 movdqu(vec1, Address(ary1, result, Address::times_1, -16));
8412 movdqu(vec2, Address(ary2, result, Address::times_1, -16));
8413 pxor(vec1, vec2);
8414
8415 ptest(vec1, vec1);
8416 jccb(Assembler::notZero, FALSE_LABEL);
8417 jmpb(TRUE_LABEL);
8418
8419 bind(COMPARE_TAIL); // limit is zero
8420 movl(limit, result);
8421 // Fallthru to tail compare
8422 }
8423
8424 // Compare 4-byte vectors
8425 andl(limit, 0xfffffffc); // vector count (in bytes)
8426 jccb(Assembler::zero, COMPARE_CHAR);
8427
8428 lea(ary1, Address(ary1, limit, Address::times_1));
8429 lea(ary2, Address(ary2, limit, Address::times_1));
8430 negptr(limit);
8431
8432 bind(COMPARE_VECTORS);
8433 movl(chr, Address(ary1, limit, Address::times_1));
8434 cmpl(chr, Address(ary2, limit, Address::times_1));
8435 jccb(Assembler::notEqual, FALSE_LABEL);
8436 addptr(limit, 4);
8437 jcc(Assembler::notZero, COMPARE_VECTORS);
8438
8439 // Compare trailing char (final 2 bytes), if any
8440 bind(COMPARE_CHAR);
8441 testl(result, 0x2); // tail char
8442 jccb(Assembler::zero, COMPARE_BYTE);
8443 load_unsigned_short(chr, Address(ary1, 0));
8444 load_unsigned_short(limit, Address(ary2, 0));
8445 cmpl(chr, limit);
8446 jccb(Assembler::notEqual, FALSE_LABEL);
8447
8448 if (is_array_equ && is_char) {
8449 bind(COMPARE_BYTE);
8450 } else {
8451 lea(ary1, Address(ary1, 2));
8452 lea(ary2, Address(ary2, 2));
8453
8454 bind(COMPARE_BYTE);
8455 testl(result, 0x1); // tail byte
8456 jccb(Assembler::zero, TRUE_LABEL);
8457 load_unsigned_byte(chr, Address(ary1, 0));
8458 load_unsigned_byte(limit, Address(ary2, 0));
8459 cmpl(chr, limit);
8460 jccb(Assembler::notEqual, FALSE_LABEL);
8461 }
8462 bind(TRUE_LABEL);
8463 movl(result, 1); // return true
8464 jmpb(DONE);
8465
8466 bind(FALSE_LABEL);
8467 xorl(result, result); // return false
8468
8469 // That's it
8470 bind(DONE);
8471 if (UseAVX >= 2) {
8472 // clean upper bits of YMM registers
8473 vpxor(vec1, vec1);
8474 vpxor(vec2, vec2);
8475 }
8476 }
8477
8478 #endif
8479
8480 void MacroAssembler::generate_fill(BasicType t, bool aligned,
8481 Register to, Register value, Register count,
8482 Register rtmp, XMMRegister xtmp) {
8483 ShortBranchVerifier sbv(this);
8484 assert_different_registers(to, value, count, rtmp);
8485 Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte;
8486 Label L_fill_2_bytes, L_fill_4_bytes;
8487
8488 int shift = -1;
8489 switch (t) {
8490 case T_BYTE:
8491 shift = 2;
8492 break;
8493 case T_SHORT:
8494 shift = 1;
8495 break;
8496 case T_INT:
8497 shift = 0;
8498 break;
8499 default: ShouldNotReachHere();
8500 }
8501
8502 if (t == T_BYTE) {
8503 andl(value, 0xff);
8504 movl(rtmp, value);
8505 shll(rtmp, 8);
8506 orl(value, rtmp);
8507 }
8508 if (t == T_SHORT) {
8509 andl(value, 0xffff);
8510 }
8511 if (t == T_BYTE || t == T_SHORT) {
8512 movl(rtmp, value);
8513 shll(rtmp, 16);
8514 orl(value, rtmp);
8515 }
8516
8517 cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element
8518 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
8519 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
8520 // align source address at 4 bytes address boundary
8521 if (t == T_BYTE) {
8522 // One byte misalignment happens only for byte arrays
8523 testptr(to, 1);
8524 jccb(Assembler::zero, L_skip_align1);
8525 movb(Address(to, 0), value);
8526 increment(to);
8527 decrement(count);
8528 BIND(L_skip_align1);
8529 }
8530 // Two bytes misalignment happens only for byte and short (char) arrays
8531 testptr(to, 2);
8532 jccb(Assembler::zero, L_skip_align2);
8533 movw(Address(to, 0), value);
8534 addptr(to, 2);
8535 subl(count, 1<<(shift-1));
8536 BIND(L_skip_align2);
8537 }
8538 if (UseSSE < 2) {
8539 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
8540 // Fill 32-byte chunks
8541 subl(count, 8 << shift);
8542 jcc(Assembler::less, L_check_fill_8_bytes);
8543 align(16);
8544
8545 BIND(L_fill_32_bytes_loop);
8546
8547 for (int i = 0; i < 32; i += 4) {
8548 movl(Address(to, i), value);
8549 }
8550
8551 addptr(to, 32);
8552 subl(count, 8 << shift);
8553 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
8554 BIND(L_check_fill_8_bytes);
8555 addl(count, 8 << shift);
8556 jccb(Assembler::zero, L_exit);
8557 jmpb(L_fill_8_bytes);
8558
8559 //
8560 // length is too short, just fill qwords
8561 //
8562 BIND(L_fill_8_bytes_loop);
8563 movl(Address(to, 0), value);
8564 movl(Address(to, 4), value);
8565 addptr(to, 8);
8566 BIND(L_fill_8_bytes);
8567 subl(count, 1 << (shift + 1));
8568 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
8569 // fall through to fill 4 bytes
8570 } else {
8571 Label L_fill_32_bytes;
8572 if (!UseUnalignedLoadStores) {
8573 // align to 8 bytes, we know we are 4 byte aligned to start
8574 testptr(to, 4);
8575 jccb(Assembler::zero, L_fill_32_bytes);
8576 movl(Address(to, 0), value);
8577 addptr(to, 4);
8578 subl(count, 1<<shift);
8579 }
8580 BIND(L_fill_32_bytes);
8581 {
8582 assert( UseSSE >= 2, "supported cpu only" );
8583 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
8584 if (UseAVX > 2) {
8585 movl(rtmp, 0xffff);
8586 kmovwl(k1, rtmp);
8587 }
8588 movdl(xtmp, value);
8589 if (UseAVX > 2 && UseUnalignedLoadStores) {
8590 // Fill 64-byte chunks
8591 Label L_fill_64_bytes_loop, L_check_fill_32_bytes;
8592 evpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit);
8593
8594 subl(count, 16 << shift);
8595 jcc(Assembler::less, L_check_fill_32_bytes);
8596 align(16);
8597
8598 BIND(L_fill_64_bytes_loop);
8599 evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit);
8600 addptr(to, 64);
8601 subl(count, 16 << shift);
8602 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
8603
8604 BIND(L_check_fill_32_bytes);
8605 addl(count, 8 << shift);
8606 jccb(Assembler::less, L_check_fill_8_bytes);
8607 vmovdqu(Address(to, 0), xtmp);
8608 addptr(to, 32);
8609 subl(count, 8 << shift);
8610
8611 BIND(L_check_fill_8_bytes);
8612 } else if (UseAVX == 2 && UseUnalignedLoadStores) {
8613 // Fill 64-byte chunks
8614 Label L_fill_64_bytes_loop, L_check_fill_32_bytes;
8615 vpbroadcastd(xtmp, xtmp);
8616
8617 subl(count, 16 << shift);
8618 jcc(Assembler::less, L_check_fill_32_bytes);
8619 align(16);
8620
8621 BIND(L_fill_64_bytes_loop);
8622 vmovdqu(Address(to, 0), xtmp);
8623 vmovdqu(Address(to, 32), xtmp);
8624 addptr(to, 64);
8625 subl(count, 16 << shift);
8626 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
8627
8628 BIND(L_check_fill_32_bytes);
8629 addl(count, 8 << shift);
8630 jccb(Assembler::less, L_check_fill_8_bytes);
8631 vmovdqu(Address(to, 0), xtmp);
8632 addptr(to, 32);
8633 subl(count, 8 << shift);
8634
8635 BIND(L_check_fill_8_bytes);
8636 // clean upper bits of YMM registers
8637 movdl(xtmp, value);
8638 pshufd(xtmp, xtmp, 0);
8639 } else {
8640 // Fill 32-byte chunks
8641 pshufd(xtmp, xtmp, 0);
8642
8643 subl(count, 8 << shift);
8644 jcc(Assembler::less, L_check_fill_8_bytes);
8645 align(16);
8646
8647 BIND(L_fill_32_bytes_loop);
8648
8649 if (UseUnalignedLoadStores) {
8650 movdqu(Address(to, 0), xtmp);
8651 movdqu(Address(to, 16), xtmp);
8652 } else {
8653 movq(Address(to, 0), xtmp);
8654 movq(Address(to, 8), xtmp);
8655 movq(Address(to, 16), xtmp);
8656 movq(Address(to, 24), xtmp);
8657 }
8658
8659 addptr(to, 32);
8660 subl(count, 8 << shift);
8661 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
8662
8663 BIND(L_check_fill_8_bytes);
8664 }
8665 addl(count, 8 << shift);
8666 jccb(Assembler::zero, L_exit);
8667 jmpb(L_fill_8_bytes);
8668
8669 //
8670 // length is too short, just fill qwords
8671 //
8672 BIND(L_fill_8_bytes_loop);
8673 movq(Address(to, 0), xtmp);
8674 addptr(to, 8);
8675 BIND(L_fill_8_bytes);
8676 subl(count, 1 << (shift + 1));
8677 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
8678 }
8679 }
8680 // fill trailing 4 bytes
8681 BIND(L_fill_4_bytes);
8682 testl(count, 1<<shift);
8683 jccb(Assembler::zero, L_fill_2_bytes);
8684 movl(Address(to, 0), value);
8685 if (t == T_BYTE || t == T_SHORT) {
8686 addptr(to, 4);
8687 BIND(L_fill_2_bytes);
8688 // fill trailing 2 bytes
8689 testl(count, 1<<(shift-1));
8690 jccb(Assembler::zero, L_fill_byte);
8691 movw(Address(to, 0), value);
8692 if (t == T_BYTE) {
8693 addptr(to, 2);
8694 BIND(L_fill_byte);
8695 // fill trailing byte
8696 testl(count, 1);
8697 jccb(Assembler::zero, L_exit);
8698 movb(Address(to, 0), value);
8699 } else {
8700 BIND(L_fill_byte);
8701 }
8702 } else {
8703 BIND(L_fill_2_bytes);
8704 }
8705 BIND(L_exit);
8706 }
8707
8708 // encode char[] to byte[] in ISO_8859_1
8709 //@HotSpotIntrinsicCandidate
8710 //private static int implEncodeISOArray(byte[] sa, int sp,
8711 //byte[] da, int dp, int len) {
8712 // int i = 0;
8713 // for (; i < len; i++) {
8714 // char c = StringUTF16.getChar(sa, sp++);
8715 // if (c > '\u00FF')
8716 // break;
8717 // da[dp++] = (byte)c;
8718 // }
8719 // return i;
8720 //}
8721 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
8722 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
8723 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
8724 Register tmp5, Register result) {
8725
8726 // rsi: src
8727 // rdi: dst
8728 // rdx: len
8729 // rcx: tmp5
8730 // rax: result
8731 ShortBranchVerifier sbv(this);
8732 assert_different_registers(src, dst, len, tmp5, result);
8733 Label L_done, L_copy_1_char, L_copy_1_char_exit;
8734
8735 // set result
8736 xorl(result, result);
8737 // check for zero length
8738 testl(len, len);
8739 jcc(Assembler::zero, L_done);
8740
8741 movl(result, len);
8742
8743 // Setup pointers
8744 lea(src, Address(src, len, Address::times_2)); // char[]
8745 lea(dst, Address(dst, len, Address::times_1)); // byte[]
8746 negptr(len);
8747
8748 if (UseSSE42Intrinsics || UseAVX >= 2) {
8749 assert(UseSSE42Intrinsics ? UseSSE >= 4 : true, "SSE4 must be enabled for SSE4.2 intrinsics to be available");
8750 Label L_chars_8_check, L_copy_8_chars, L_copy_8_chars_exit;
8751 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
8752
8753 if (UseAVX >= 2) {
8754 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
8755 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector
8756 movdl(tmp1Reg, tmp5);
8757 vpbroadcastd(tmp1Reg, tmp1Reg);
8758 jmp(L_chars_32_check);
8759
8760 bind(L_copy_32_chars);
8761 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
8762 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
8763 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
8764 vptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
8765 jccb(Assembler::notZero, L_copy_32_chars_exit);
8766 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
8767 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1);
8768 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
8769
8770 bind(L_chars_32_check);
8771 addptr(len, 32);
8772 jcc(Assembler::lessEqual, L_copy_32_chars);
8773
8774 bind(L_copy_32_chars_exit);
8775 subptr(len, 16);
8776 jccb(Assembler::greater, L_copy_16_chars_exit);
8777
8778 } else if (UseSSE42Intrinsics) {
8779 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector
8780 movdl(tmp1Reg, tmp5);
8781 pshufd(tmp1Reg, tmp1Reg, 0);
8782 jmpb(L_chars_16_check);
8783 }
8784
8785 bind(L_copy_16_chars);
8786 if (UseAVX >= 2) {
8787 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
8788 vptest(tmp2Reg, tmp1Reg);
8789 jcc(Assembler::notZero, L_copy_16_chars_exit);
8790 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1);
8791 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1);
8792 } else {
8793 if (UseAVX > 0) {
8794 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
8795 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
8796 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0);
8797 } else {
8798 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
8799 por(tmp2Reg, tmp3Reg);
8800 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
8801 por(tmp2Reg, tmp4Reg);
8802 }
8803 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
8804 jccb(Assembler::notZero, L_copy_16_chars_exit);
8805 packuswb(tmp3Reg, tmp4Reg);
8806 }
8807 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
8808
8809 bind(L_chars_16_check);
8810 addptr(len, 16);
8811 jcc(Assembler::lessEqual, L_copy_16_chars);
8812
8813 bind(L_copy_16_chars_exit);
8814 if (UseAVX >= 2) {
8815 // clean upper bits of YMM registers
8816 vpxor(tmp2Reg, tmp2Reg);
8817 vpxor(tmp3Reg, tmp3Reg);
8818 vpxor(tmp4Reg, tmp4Reg);
8819 movdl(tmp1Reg, tmp5);
8820 pshufd(tmp1Reg, tmp1Reg, 0);
8821 }
8822 subptr(len, 8);
8823 jccb(Assembler::greater, L_copy_8_chars_exit);
8824
8825 bind(L_copy_8_chars);
8826 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
8827 ptest(tmp3Reg, tmp1Reg);
8828 jccb(Assembler::notZero, L_copy_8_chars_exit);
8829 packuswb(tmp3Reg, tmp1Reg);
8830 movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
8831 addptr(len, 8);
8832 jccb(Assembler::lessEqual, L_copy_8_chars);
8833
8834 bind(L_copy_8_chars_exit);
8835 subptr(len, 8);
8836 jccb(Assembler::zero, L_done);
8837 }
8838
8839 bind(L_copy_1_char);
8840 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
8841 testl(tmp5, 0xff00); // check if Unicode char
8842 jccb(Assembler::notZero, L_copy_1_char_exit);
8843 movb(Address(dst, len, Address::times_1, 0), tmp5);
8844 addptr(len, 1);
8845 jccb(Assembler::less, L_copy_1_char);
8846
8847 bind(L_copy_1_char_exit);
8848 addptr(result, len); // len is negative count of not processed elements
8849
8850 bind(L_done);
8851 }
8852
8853 #ifdef _LP64
8854 /**
8855 * Helper for multiply_to_len().
8856 */
8857 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
8858 addq(dest_lo, src1);
8859 adcq(dest_hi, 0);
8860 addq(dest_lo, src2);
8861 adcq(dest_hi, 0);
8862 }
8863
8864 /**
8865 * Multiply 64 bit by 64 bit first loop.
8866 */
8867 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
8868 Register y, Register y_idx, Register z,
8869 Register carry, Register product,
8870 Register idx, Register kdx) {
8871 //
8872 // jlong carry, x[], y[], z[];
8873 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
8874 // huge_128 product = y[idx] * x[xstart] + carry;
8875 // z[kdx] = (jlong)product;
8876 // carry = (jlong)(product >>> 64);
8877 // }
8878 // z[xstart] = carry;
8879 //
8880
8881 Label L_first_loop, L_first_loop_exit;
8882 Label L_one_x, L_one_y, L_multiply;
8883
8884 decrementl(xstart);
8885 jcc(Assembler::negative, L_one_x);
8886
8887 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
8888 rorq(x_xstart, 32); // convert big-endian to little-endian
8889
8890 bind(L_first_loop);
8891 decrementl(idx);
8892 jcc(Assembler::negative, L_first_loop_exit);
8893 decrementl(idx);
8894 jcc(Assembler::negative, L_one_y);
8895 movq(y_idx, Address(y, idx, Address::times_4, 0));
8896 rorq(y_idx, 32); // convert big-endian to little-endian
8897 bind(L_multiply);
8898 movq(product, x_xstart);
8899 mulq(y_idx); // product(rax) * y_idx -> rdx:rax
8900 addq(product, carry);
8901 adcq(rdx, 0);
8902 subl(kdx, 2);
8903 movl(Address(z, kdx, Address::times_4, 4), product);
8904 shrq(product, 32);
8905 movl(Address(z, kdx, Address::times_4, 0), product);
8906 movq(carry, rdx);
8907 jmp(L_first_loop);
8908
8909 bind(L_one_y);
8910 movl(y_idx, Address(y, 0));
8911 jmp(L_multiply);
8912
8913 bind(L_one_x);
8914 movl(x_xstart, Address(x, 0));
8915 jmp(L_first_loop);
8916
8917 bind(L_first_loop_exit);
8918 }
8919
8920 /**
8921 * Multiply 64 bit by 64 bit and add 128 bit.
8922 */
8923 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
8924 Register yz_idx, Register idx,
8925 Register carry, Register product, int offset) {
8926 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
8927 // z[kdx] = (jlong)product;
8928
8929 movq(yz_idx, Address(y, idx, Address::times_4, offset));
8930 rorq(yz_idx, 32); // convert big-endian to little-endian
8931 movq(product, x_xstart);
8932 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
8933 movq(yz_idx, Address(z, idx, Address::times_4, offset));
8934 rorq(yz_idx, 32); // convert big-endian to little-endian
8935
8936 add2_with_carry(rdx, product, carry, yz_idx);
8937
8938 movl(Address(z, idx, Address::times_4, offset+4), product);
8939 shrq(product, 32);
8940 movl(Address(z, idx, Address::times_4, offset), product);
8941
8942 }
8943
8944 /**
8945 * Multiply 128 bit by 128 bit. Unrolled inner loop.
8946 */
8947 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
8948 Register yz_idx, Register idx, Register jdx,
8949 Register carry, Register product,
8950 Register carry2) {
8951 // jlong carry, x[], y[], z[];
8952 // int kdx = ystart+1;
8953 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
8954 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
8955 // z[kdx+idx+1] = (jlong)product;
8956 // jlong carry2 = (jlong)(product >>> 64);
8957 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
8958 // z[kdx+idx] = (jlong)product;
8959 // carry = (jlong)(product >>> 64);
8960 // }
8961 // idx += 2;
8962 // if (idx > 0) {
8963 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
8964 // z[kdx+idx] = (jlong)product;
8965 // carry = (jlong)(product >>> 64);
8966 // }
8967 //
8968
8969 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
8970
8971 movl(jdx, idx);
8972 andl(jdx, 0xFFFFFFFC);
8973 shrl(jdx, 2);
8974
8975 bind(L_third_loop);
8976 subl(jdx, 1);
8977 jcc(Assembler::negative, L_third_loop_exit);
8978 subl(idx, 4);
8979
8980 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
8981 movq(carry2, rdx);
8982
8983 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
8984 movq(carry, rdx);
8985 jmp(L_third_loop);
8986
8987 bind (L_third_loop_exit);
8988
8989 andl (idx, 0x3);
8990 jcc(Assembler::zero, L_post_third_loop_done);
8991
8992 Label L_check_1;
8993 subl(idx, 2);
8994 jcc(Assembler::negative, L_check_1);
8995
8996 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
8997 movq(carry, rdx);
8998
8999 bind (L_check_1);
9000 addl (idx, 0x2);
9001 andl (idx, 0x1);
9002 subl(idx, 1);
9003 jcc(Assembler::negative, L_post_third_loop_done);
9004
9005 movl(yz_idx, Address(y, idx, Address::times_4, 0));
9006 movq(product, x_xstart);
9007 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
9008 movl(yz_idx, Address(z, idx, Address::times_4, 0));
9009
9010 add2_with_carry(rdx, product, yz_idx, carry);
9011
9012 movl(Address(z, idx, Address::times_4, 0), product);
9013 shrq(product, 32);
9014
9015 shlq(rdx, 32);
9016 orq(product, rdx);
9017 movq(carry, product);
9018
9019 bind(L_post_third_loop_done);
9020 }
9021
9022 /**
9023 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
9024 *
9025 */
9026 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
9027 Register carry, Register carry2,
9028 Register idx, Register jdx,
9029 Register yz_idx1, Register yz_idx2,
9030 Register tmp, Register tmp3, Register tmp4) {
9031 assert(UseBMI2Instructions, "should be used only when BMI2 is available");
9032
9033 // jlong carry, x[], y[], z[];
9034 // int kdx = ystart+1;
9035 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
9036 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
9037 // jlong carry2 = (jlong)(tmp3 >>> 64);
9038 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2;
9039 // carry = (jlong)(tmp4 >>> 64);
9040 // z[kdx+idx+1] = (jlong)tmp3;
9041 // z[kdx+idx] = (jlong)tmp4;
9042 // }
9043 // idx += 2;
9044 // if (idx > 0) {
9045 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
9046 // z[kdx+idx] = (jlong)yz_idx1;
9047 // carry = (jlong)(yz_idx1 >>> 64);
9048 // }
9049 //
9050
9051 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
9052
9053 movl(jdx, idx);
9054 andl(jdx, 0xFFFFFFFC);
9055 shrl(jdx, 2);
9056
9057 bind(L_third_loop);
9058 subl(jdx, 1);
9059 jcc(Assembler::negative, L_third_loop_exit);
9060 subl(idx, 4);
9061
9062 movq(yz_idx1, Address(y, idx, Address::times_4, 8));
9063 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
9064 movq(yz_idx2, Address(y, idx, Address::times_4, 0));
9065 rorxq(yz_idx2, yz_idx2, 32);
9066
9067 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
9068 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp
9069
9070 movq(yz_idx1, Address(z, idx, Address::times_4, 8));
9071 rorxq(yz_idx1, yz_idx1, 32);
9072 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
9073 rorxq(yz_idx2, yz_idx2, 32);
9074
9075 if (VM_Version::supports_adx()) {
9076 adcxq(tmp3, carry);
9077 adoxq(tmp3, yz_idx1);
9078
9079 adcxq(tmp4, tmp);
9080 adoxq(tmp4, yz_idx2);
9081
9082 movl(carry, 0); // does not affect flags
9083 adcxq(carry2, carry);
9084 adoxq(carry2, carry);
9085 } else {
9086 add2_with_carry(tmp4, tmp3, carry, yz_idx1);
9087 add2_with_carry(carry2, tmp4, tmp, yz_idx2);
9088 }
9089 movq(carry, carry2);
9090
9091 movl(Address(z, idx, Address::times_4, 12), tmp3);
9092 shrq(tmp3, 32);
9093 movl(Address(z, idx, Address::times_4, 8), tmp3);
9094
9095 movl(Address(z, idx, Address::times_4, 4), tmp4);
9096 shrq(tmp4, 32);
9097 movl(Address(z, idx, Address::times_4, 0), tmp4);
9098
9099 jmp(L_third_loop);
9100
9101 bind (L_third_loop_exit);
9102
9103 andl (idx, 0x3);
9104 jcc(Assembler::zero, L_post_third_loop_done);
9105
9106 Label L_check_1;
9107 subl(idx, 2);
9108 jcc(Assembler::negative, L_check_1);
9109
9110 movq(yz_idx1, Address(y, idx, Address::times_4, 0));
9111 rorxq(yz_idx1, yz_idx1, 32);
9112 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
9113 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
9114 rorxq(yz_idx2, yz_idx2, 32);
9115
9116 add2_with_carry(tmp4, tmp3, carry, yz_idx2);
9117
9118 movl(Address(z, idx, Address::times_4, 4), tmp3);
9119 shrq(tmp3, 32);
9120 movl(Address(z, idx, Address::times_4, 0), tmp3);
9121 movq(carry, tmp4);
9122
9123 bind (L_check_1);
9124 addl (idx, 0x2);
9125 andl (idx, 0x1);
9126 subl(idx, 1);
9127 jcc(Assembler::negative, L_post_third_loop_done);
9128 movl(tmp4, Address(y, idx, Address::times_4, 0));
9129 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3
9130 movl(tmp4, Address(z, idx, Address::times_4, 0));
9131
9132 add2_with_carry(carry2, tmp3, tmp4, carry);
9133
9134 movl(Address(z, idx, Address::times_4, 0), tmp3);
9135 shrq(tmp3, 32);
9136
9137 shlq(carry2, 32);
9138 orq(tmp3, carry2);
9139 movq(carry, tmp3);
9140
9141 bind(L_post_third_loop_done);
9142 }
9143
9144 /**
9145 * Code for BigInteger::multiplyToLen() instrinsic.
9146 *
9147 * rdi: x
9148 * rax: xlen
9149 * rsi: y
9150 * rcx: ylen
9151 * r8: z
9152 * r11: zlen
9153 * r12: tmp1
9154 * r13: tmp2
9155 * r14: tmp3
9156 * r15: tmp4
9157 * rbx: tmp5
9158 *
9159 */
9160 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
9161 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
9162 ShortBranchVerifier sbv(this);
9163 assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
9164
9165 push(tmp1);
9166 push(tmp2);
9167 push(tmp3);
9168 push(tmp4);
9169 push(tmp5);
9170
9171 push(xlen);
9172 push(zlen);
9173
9174 const Register idx = tmp1;
9175 const Register kdx = tmp2;
9176 const Register xstart = tmp3;
9177
9178 const Register y_idx = tmp4;
9179 const Register carry = tmp5;
9180 const Register product = xlen;
9181 const Register x_xstart = zlen; // reuse register
9182
9183 // First Loop.
9184 //
9185 // final static long LONG_MASK = 0xffffffffL;
9186 // int xstart = xlen - 1;
9187 // int ystart = ylen - 1;
9188 // long carry = 0;
9189 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
9190 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
9191 // z[kdx] = (int)product;
9192 // carry = product >>> 32;
9193 // }
9194 // z[xstart] = (int)carry;
9195 //
9196
9197 movl(idx, ylen); // idx = ylen;
9198 movl(kdx, zlen); // kdx = xlen+ylen;
9199 xorq(carry, carry); // carry = 0;
9200
9201 Label L_done;
9202
9203 movl(xstart, xlen);
9204 decrementl(xstart);
9205 jcc(Assembler::negative, L_done);
9206
9207 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
9208
9209 Label L_second_loop;
9210 testl(kdx, kdx);
9211 jcc(Assembler::zero, L_second_loop);
9212
9213 Label L_carry;
9214 subl(kdx, 1);
9215 jcc(Assembler::zero, L_carry);
9216
9217 movl(Address(z, kdx, Address::times_4, 0), carry);
9218 shrq(carry, 32);
9219 subl(kdx, 1);
9220
9221 bind(L_carry);
9222 movl(Address(z, kdx, Address::times_4, 0), carry);
9223
9224 // Second and third (nested) loops.
9225 //
9226 // for (int i = xstart-1; i >= 0; i--) { // Second loop
9227 // carry = 0;
9228 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
9229 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
9230 // (z[k] & LONG_MASK) + carry;
9231 // z[k] = (int)product;
9232 // carry = product >>> 32;
9233 // }
9234 // z[i] = (int)carry;
9235 // }
9236 //
9237 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
9238
9239 const Register jdx = tmp1;
9240
9241 bind(L_second_loop);
9242 xorl(carry, carry); // carry = 0;
9243 movl(jdx, ylen); // j = ystart+1
9244
9245 subl(xstart, 1); // i = xstart-1;
9246 jcc(Assembler::negative, L_done);
9247
9248 push (z);
9249
9250 Label L_last_x;
9251 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
9252 subl(xstart, 1); // i = xstart-1;
9253 jcc(Assembler::negative, L_last_x);
9254
9255 if (UseBMI2Instructions) {
9256 movq(rdx, Address(x, xstart, Address::times_4, 0));
9257 rorxq(rdx, rdx, 32); // convert big-endian to little-endian
9258 } else {
9259 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
9260 rorq(x_xstart, 32); // convert big-endian to little-endian
9261 }
9262
9263 Label L_third_loop_prologue;
9264 bind(L_third_loop_prologue);
9265
9266 push (x);
9267 push (xstart);
9268 push (ylen);
9269
9270
9271 if (UseBMI2Instructions) {
9272 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
9273 } else { // !UseBMI2Instructions
9274 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
9275 }
9276
9277 pop(ylen);
9278 pop(xlen);
9279 pop(x);
9280 pop(z);
9281
9282 movl(tmp3, xlen);
9283 addl(tmp3, 1);
9284 movl(Address(z, tmp3, Address::times_4, 0), carry);
9285 subl(tmp3, 1);
9286 jccb(Assembler::negative, L_done);
9287
9288 shrq(carry, 32);
9289 movl(Address(z, tmp3, Address::times_4, 0), carry);
9290 jmp(L_second_loop);
9291
9292 // Next infrequent code is moved outside loops.
9293 bind(L_last_x);
9294 if (UseBMI2Instructions) {
9295 movl(rdx, Address(x, 0));
9296 } else {
9297 movl(x_xstart, Address(x, 0));
9298 }
9299 jmp(L_third_loop_prologue);
9300
9301 bind(L_done);
9302
9303 pop(zlen);
9304 pop(xlen);
9305
9306 pop(tmp5);
9307 pop(tmp4);
9308 pop(tmp3);
9309 pop(tmp2);
9310 pop(tmp1);
9311 }
9312
9313 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
9314 Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){
9315 assert(UseSSE42Intrinsics, "SSE4.2 must be enabled.");
9316 Label VECTOR64_LOOP, VECTOR64_TAIL, VECTOR64_NOT_EQUAL, VECTOR32_TAIL;
9317 Label VECTOR32_LOOP, VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP;
9318 Label VECTOR16_TAIL, VECTOR8_TAIL, VECTOR4_TAIL;
9319 Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL;
9320 Label SAME_TILL_END, DONE;
9321 Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL;
9322
9323 //scale is in rcx in both Win64 and Unix
9324 ShortBranchVerifier sbv(this);
9325
9326 shlq(length);
9327 xorq(result, result);
9328
9329 if ((UseAVX > 2) &&
9330 VM_Version::supports_avx512vlbw()) {
9331 set_vector_masking(); // opening of the stub context for programming mask registers
9332 cmpq(length, 64);
9333 jcc(Assembler::less, VECTOR32_TAIL);
9334 movq(tmp1, length);
9335 andq(tmp1, 0x3F); // tail count
9336 andq(length, ~(0x3F)); //vector count
9337
9338 bind(VECTOR64_LOOP);
9339 // AVX512 code to compare 64 byte vectors.
9340 evmovdqub(rymm0, Address(obja, result), Assembler::AVX_512bit);
9341 evpcmpeqb(k7, rymm0, Address(objb, result), Assembler::AVX_512bit);
9342 kortestql(k7, k7);
9343 jcc(Assembler::aboveEqual, VECTOR64_NOT_EQUAL); // mismatch
9344 addq(result, 64);
9345 subq(length, 64);
9346 jccb(Assembler::notZero, VECTOR64_LOOP);
9347
9348 //bind(VECTOR64_TAIL);
9349 testq(tmp1, tmp1);
9350 jcc(Assembler::zero, SAME_TILL_END);
9351
9352 bind(VECTOR64_TAIL);
9353 // AVX512 code to compare upto 63 byte vectors.
9354 // Save k1
9355 kmovql(k3, k1);
9356 mov64(tmp2, 0xFFFFFFFFFFFFFFFF);
9357 shlxq(tmp2, tmp2, tmp1);
9358 notq(tmp2);
9359 kmovql(k1, tmp2);
9360
9361 evmovdqub(rymm0, k1, Address(obja, result), Assembler::AVX_512bit);
9362 evpcmpeqb(k7, k1, rymm0, Address(objb, result), Assembler::AVX_512bit);
9363
9364 ktestql(k7, k1);
9365 // Restore k1
9366 kmovql(k1, k3);
9367 jcc(Assembler::below, SAME_TILL_END); // not mismatch
9368
9369 bind(VECTOR64_NOT_EQUAL);
9370 kmovql(tmp1, k7);
9371 notq(tmp1);
9372 tzcntq(tmp1, tmp1);
9373 addq(result, tmp1);
9374 shrq(result);
9375 jmp(DONE);
9376 bind(VECTOR32_TAIL);
9377 clear_vector_masking(); // closing of the stub context for programming mask registers
9378 }
9379
9380 cmpq(length, 8);
9381 jcc(Assembler::equal, VECTOR8_LOOP);
9382 jcc(Assembler::less, VECTOR4_TAIL);
9383
9384 if (UseAVX >= 2) {
9385
9386 cmpq(length, 16);
9387 jcc(Assembler::equal, VECTOR16_LOOP);
9388 jcc(Assembler::less, VECTOR8_LOOP);
9389
9390 cmpq(length, 32);
9391 jccb(Assembler::less, VECTOR16_TAIL);
9392
9393 subq(length, 32);
9394 bind(VECTOR32_LOOP);
9395 vmovdqu(rymm0, Address(obja, result));
9396 vmovdqu(rymm1, Address(objb, result));
9397 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit);
9398 vptest(rymm2, rymm2);
9399 jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found
9400 addq(result, 32);
9401 subq(length, 32);
9402 jccb(Assembler::greaterEqual, VECTOR32_LOOP);
9403 addq(length, 32);
9404 jcc(Assembler::equal, SAME_TILL_END);
9405 //falling through if less than 32 bytes left //close the branch here.
9406
9407 bind(VECTOR16_TAIL);
9408 cmpq(length, 16);
9409 jccb(Assembler::less, VECTOR8_TAIL);
9410 bind(VECTOR16_LOOP);
9411 movdqu(rymm0, Address(obja, result));
9412 movdqu(rymm1, Address(objb, result));
9413 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit);
9414 ptest(rymm2, rymm2);
9415 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
9416 addq(result, 16);
9417 subq(length, 16);
9418 jcc(Assembler::equal, SAME_TILL_END);
9419 //falling through if less than 16 bytes left
9420 } else {//regular intrinsics
9421
9422 cmpq(length, 16);
9423 jccb(Assembler::less, VECTOR8_TAIL);
9424
9425 subq(length, 16);
9426 bind(VECTOR16_LOOP);
9427 movdqu(rymm0, Address(obja, result));
9428 movdqu(rymm1, Address(objb, result));
9429 pxor(rymm0, rymm1);
9430 ptest(rymm0, rymm0);
9431 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
9432 addq(result, 16);
9433 subq(length, 16);
9434 jccb(Assembler::greaterEqual, VECTOR16_LOOP);
9435 addq(length, 16);
9436 jcc(Assembler::equal, SAME_TILL_END);
9437 //falling through if less than 16 bytes left
9438 }
9439
9440 bind(VECTOR8_TAIL);
9441 cmpq(length, 8);
9442 jccb(Assembler::less, VECTOR4_TAIL);
9443 bind(VECTOR8_LOOP);
9444 movq(tmp1, Address(obja, result));
9445 movq(tmp2, Address(objb, result));
9446 xorq(tmp1, tmp2);
9447 testq(tmp1, tmp1);
9448 jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found
9449 addq(result, 8);
9450 subq(length, 8);
9451 jcc(Assembler::equal, SAME_TILL_END);
9452 //falling through if less than 8 bytes left
9453
9454 bind(VECTOR4_TAIL);
9455 cmpq(length, 4);
9456 jccb(Assembler::less, BYTES_TAIL);
9457 bind(VECTOR4_LOOP);
9458 movl(tmp1, Address(obja, result));
9459 xorl(tmp1, Address(objb, result));
9460 testl(tmp1, tmp1);
9461 jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found
9462 addq(result, 4);
9463 subq(length, 4);
9464 jcc(Assembler::equal, SAME_TILL_END);
9465 //falling through if less than 4 bytes left
9466
9467 bind(BYTES_TAIL);
9468 bind(BYTES_LOOP);
9469 load_unsigned_byte(tmp1, Address(obja, result));
9470 load_unsigned_byte(tmp2, Address(objb, result));
9471 xorl(tmp1, tmp2);
9472 testl(tmp1, tmp1);
9473 jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
9474 decq(length);
9475 jccb(Assembler::zero, SAME_TILL_END);
9476 incq(result);
9477 load_unsigned_byte(tmp1, Address(obja, result));
9478 load_unsigned_byte(tmp2, Address(objb, result));
9479 xorl(tmp1, tmp2);
9480 testl(tmp1, tmp1);
9481 jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
9482 decq(length);
9483 jccb(Assembler::zero, SAME_TILL_END);
9484 incq(result);
9485 load_unsigned_byte(tmp1, Address(obja, result));
9486 load_unsigned_byte(tmp2, Address(objb, result));
9487 xorl(tmp1, tmp2);
9488 testl(tmp1, tmp1);
9489 jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
9490 jmpb(SAME_TILL_END);
9491
9492 if (UseAVX >= 2) {
9493 bind(VECTOR32_NOT_EQUAL);
9494 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit);
9495 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit);
9496 vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit);
9497 vpmovmskb(tmp1, rymm0);
9498 bsfq(tmp1, tmp1);
9499 addq(result, tmp1);
9500 shrq(result);
9501 jmpb(DONE);
9502 }
9503
9504 bind(VECTOR16_NOT_EQUAL);
9505 if (UseAVX >= 2) {
9506 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit);
9507 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit);
9508 pxor(rymm0, rymm2);
9509 } else {
9510 pcmpeqb(rymm2, rymm2);
9511 pxor(rymm0, rymm1);
9512 pcmpeqb(rymm0, rymm1);
9513 pxor(rymm0, rymm2);
9514 }
9515 pmovmskb(tmp1, rymm0);
9516 bsfq(tmp1, tmp1);
9517 addq(result, tmp1);
9518 shrq(result);
9519 jmpb(DONE);
9520
9521 bind(VECTOR8_NOT_EQUAL);
9522 bind(VECTOR4_NOT_EQUAL);
9523 bsfq(tmp1, tmp1);
9524 shrq(tmp1, 3);
9525 addq(result, tmp1);
9526 bind(BYTES_NOT_EQUAL);
9527 shrq(result);
9528 jmpb(DONE);
9529
9530 bind(SAME_TILL_END);
9531 mov64(result, -1);
9532
9533 bind(DONE);
9534 }
9535
9536 //Helper functions for square_to_len()
9537
9538 /**
9539 * Store the squares of x[], right shifted one bit (divided by 2) into z[]
9540 * Preserves x and z and modifies rest of the registers.
9541 */
9542 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
9543 // Perform square and right shift by 1
9544 // Handle odd xlen case first, then for even xlen do the following
9545 // jlong carry = 0;
9546 // for (int j=0, i=0; j < xlen; j+=2, i+=4) {
9547 // huge_128 product = x[j:j+1] * x[j:j+1];
9548 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65);
9549 // z[i+2:i+3] = (jlong)(product >>> 1);
9550 // carry = (jlong)product;
9551 // }
9552
9553 xorq(tmp5, tmp5); // carry
9554 xorq(rdxReg, rdxReg);
9555 xorl(tmp1, tmp1); // index for x
9556 xorl(tmp4, tmp4); // index for z
9557
9558 Label L_first_loop, L_first_loop_exit;
9559
9560 testl(xlen, 1);
9561 jccb(Assembler::zero, L_first_loop); //jump if xlen is even
9562
9563 // Square and right shift by 1 the odd element using 32 bit multiply
9564 movl(raxReg, Address(x, tmp1, Address::times_4, 0));
9565 imulq(raxReg, raxReg);
9566 shrq(raxReg, 1);
9567 adcq(tmp5, 0);
9568 movq(Address(z, tmp4, Address::times_4, 0), raxReg);
9569 incrementl(tmp1);
9570 addl(tmp4, 2);
9571
9572 // Square and right shift by 1 the rest using 64 bit multiply
9573 bind(L_first_loop);
9574 cmpptr(tmp1, xlen);
9575 jccb(Assembler::equal, L_first_loop_exit);
9576
9577 // Square
9578 movq(raxReg, Address(x, tmp1, Address::times_4, 0));
9579 rorq(raxReg, 32); // convert big-endian to little-endian
9580 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax
9581
9582 // Right shift by 1 and save carry
9583 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1
9584 rcrq(rdxReg, 1);
9585 rcrq(raxReg, 1);
9586 adcq(tmp5, 0);
9587
9588 // Store result in z
9589 movq(Address(z, tmp4, Address::times_4, 0), rdxReg);
9590 movq(Address(z, tmp4, Address::times_4, 8), raxReg);
9591
9592 // Update indices for x and z
9593 addl(tmp1, 2);
9594 addl(tmp4, 4);
9595 jmp(L_first_loop);
9596
9597 bind(L_first_loop_exit);
9598 }
9599
9600
9601 /**
9602 * Perform the following multiply add operation using BMI2 instructions
9603 * carry:sum = sum + op1*op2 + carry
9604 * op2 should be in rdx
9605 * op2 is preserved, all other registers are modified
9606 */
9607 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) {
9608 // assert op2 is rdx
9609 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1
9610 addq(sum, carry);
9611 adcq(tmp2, 0);
9612 addq(sum, op1);
9613 adcq(tmp2, 0);
9614 movq(carry, tmp2);
9615 }
9616
9617 /**
9618 * Perform the following multiply add operation:
9619 * carry:sum = sum + op1*op2 + carry
9620 * Preserves op1, op2 and modifies rest of registers
9621 */
9622 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) {
9623 // rdx:rax = op1 * op2
9624 movq(raxReg, op2);
9625 mulq(op1);
9626
9627 // rdx:rax = sum + carry + rdx:rax
9628 addq(sum, carry);
9629 adcq(rdxReg, 0);
9630 addq(sum, raxReg);
9631 adcq(rdxReg, 0);
9632
9633 // carry:sum = rdx:sum
9634 movq(carry, rdxReg);
9635 }
9636
9637 /**
9638 * Add 64 bit long carry into z[] with carry propogation.
9639 * Preserves z and carry register values and modifies rest of registers.
9640 *
9641 */
9642 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) {
9643 Label L_fourth_loop, L_fourth_loop_exit;
9644
9645 movl(tmp1, 1);
9646 subl(zlen, 2);
9647 addq(Address(z, zlen, Address::times_4, 0), carry);
9648
9649 bind(L_fourth_loop);
9650 jccb(Assembler::carryClear, L_fourth_loop_exit);
9651 subl(zlen, 2);
9652 jccb(Assembler::negative, L_fourth_loop_exit);
9653 addq(Address(z, zlen, Address::times_4, 0), tmp1);
9654 jmp(L_fourth_loop);
9655 bind(L_fourth_loop_exit);
9656 }
9657
9658 /**
9659 * Shift z[] left by 1 bit.
9660 * Preserves x, len, z and zlen registers and modifies rest of the registers.
9661 *
9662 */
9663 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
9664
9665 Label L_fifth_loop, L_fifth_loop_exit;
9666
9667 // Fifth loop
9668 // Perform primitiveLeftShift(z, zlen, 1)
9669
9670 const Register prev_carry = tmp1;
9671 const Register new_carry = tmp4;
9672 const Register value = tmp2;
9673 const Register zidx = tmp3;
9674
9675 // int zidx, carry;
9676 // long value;
9677 // carry = 0;
9678 // for (zidx = zlen-2; zidx >=0; zidx -= 2) {
9679 // (carry:value) = (z[i] << 1) | carry ;
9680 // z[i] = value;
9681 // }
9682
9683 movl(zidx, zlen);
9684 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register
9685
9686 bind(L_fifth_loop);
9687 decl(zidx); // Use decl to preserve carry flag
9688 decl(zidx);
9689 jccb(Assembler::negative, L_fifth_loop_exit);
9690
9691 if (UseBMI2Instructions) {
9692 movq(value, Address(z, zidx, Address::times_4, 0));
9693 rclq(value, 1);
9694 rorxq(value, value, 32);
9695 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
9696 }
9697 else {
9698 // clear new_carry
9699 xorl(new_carry, new_carry);
9700
9701 // Shift z[i] by 1, or in previous carry and save new carry
9702 movq(value, Address(z, zidx, Address::times_4, 0));
9703 shlq(value, 1);
9704 adcl(new_carry, 0);
9705
9706 orq(value, prev_carry);
9707 rorq(value, 0x20);
9708 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
9709
9710 // Set previous carry = new carry
9711 movl(prev_carry, new_carry);
9712 }
9713 jmp(L_fifth_loop);
9714
9715 bind(L_fifth_loop_exit);
9716 }
9717
9718
9719 /**
9720 * Code for BigInteger::squareToLen() intrinsic
9721 *
9722 * rdi: x
9723 * rsi: len
9724 * r8: z
9725 * rcx: zlen
9726 * r12: tmp1
9727 * r13: tmp2
9728 * r14: tmp3
9729 * r15: tmp4
9730 * rbx: tmp5
9731 *
9732 */
9733 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
9734
9735 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, fifth_loop, fifth_loop_exit, L_last_x, L_multiply;
9736 push(tmp1);
9737 push(tmp2);
9738 push(tmp3);
9739 push(tmp4);
9740 push(tmp5);
9741
9742 // First loop
9743 // Store the squares, right shifted one bit (i.e., divided by 2).
9744 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg);
9745
9746 // Add in off-diagonal sums.
9747 //
9748 // Second, third (nested) and fourth loops.
9749 // zlen +=2;
9750 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) {
9751 // carry = 0;
9752 // long op2 = x[xidx:xidx+1];
9753 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) {
9754 // k -= 2;
9755 // long op1 = x[j:j+1];
9756 // long sum = z[k:k+1];
9757 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs);
9758 // z[k:k+1] = sum;
9759 // }
9760 // add_one_64(z, k, carry, tmp_regs);
9761 // }
9762
9763 const Register carry = tmp5;
9764 const Register sum = tmp3;
9765 const Register op1 = tmp4;
9766 Register op2 = tmp2;
9767
9768 push(zlen);
9769 push(len);
9770 addl(zlen,2);
9771 bind(L_second_loop);
9772 xorq(carry, carry);
9773 subl(zlen, 4);
9774 subl(len, 2);
9775 push(zlen);
9776 push(len);
9777 cmpl(len, 0);
9778 jccb(Assembler::lessEqual, L_second_loop_exit);
9779
9780 // Multiply an array by one 64 bit long.
9781 if (UseBMI2Instructions) {
9782 op2 = rdxReg;
9783 movq(op2, Address(x, len, Address::times_4, 0));
9784 rorxq(op2, op2, 32);
9785 }
9786 else {
9787 movq(op2, Address(x, len, Address::times_4, 0));
9788 rorq(op2, 32);
9789 }
9790
9791 bind(L_third_loop);
9792 decrementl(len);
9793 jccb(Assembler::negative, L_third_loop_exit);
9794 decrementl(len);
9795 jccb(Assembler::negative, L_last_x);
9796
9797 movq(op1, Address(x, len, Address::times_4, 0));
9798 rorq(op1, 32);
9799
9800 bind(L_multiply);
9801 subl(zlen, 2);
9802 movq(sum, Address(z, zlen, Address::times_4, 0));
9803
9804 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry.
9805 if (UseBMI2Instructions) {
9806 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2);
9807 }
9808 else {
9809 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
9810 }
9811
9812 movq(Address(z, zlen, Address::times_4, 0), sum);
9813
9814 jmp(L_third_loop);
9815 bind(L_third_loop_exit);
9816
9817 // Fourth loop
9818 // Add 64 bit long carry into z with carry propogation.
9819 // Uses offsetted zlen.
9820 add_one_64(z, zlen, carry, tmp1);
9821
9822 pop(len);
9823 pop(zlen);
9824 jmp(L_second_loop);
9825
9826 // Next infrequent code is moved outside loops.
9827 bind(L_last_x);
9828 movl(op1, Address(x, 0));
9829 jmp(L_multiply);
9830
9831 bind(L_second_loop_exit);
9832 pop(len);
9833 pop(zlen);
9834 pop(len);
9835 pop(zlen);
9836
9837 // Fifth loop
9838 // Shift z left 1 bit.
9839 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4);
9840
9841 // z[zlen-1] |= x[len-1] & 1;
9842 movl(tmp3, Address(x, len, Address::times_4, -4));
9843 andl(tmp3, 1);
9844 orl(Address(z, zlen, Address::times_4, -4), tmp3);
9845
9846 pop(tmp5);
9847 pop(tmp4);
9848 pop(tmp3);
9849 pop(tmp2);
9850 pop(tmp1);
9851 }
9852
9853 /**
9854 * Helper function for mul_add()
9855 * Multiply the in[] by int k and add to out[] starting at offset offs using
9856 * 128 bit by 32 bit multiply and return the carry in tmp5.
9857 * Only quad int aligned length of in[] is operated on in this function.
9858 * k is in rdxReg for BMI2Instructions, for others it is in tmp2.
9859 * This function preserves out, in and k registers.
9860 * len and offset point to the appropriate index in "in" & "out" correspondingly
9861 * tmp5 has the carry.
9862 * other registers are temporary and are modified.
9863 *
9864 */
9865 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in,
9866 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3,
9867 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
9868
9869 Label L_first_loop, L_first_loop_exit;
9870
9871 movl(tmp1, len);
9872 shrl(tmp1, 2);
9873
9874 bind(L_first_loop);
9875 subl(tmp1, 1);
9876 jccb(Assembler::negative, L_first_loop_exit);
9877
9878 subl(len, 4);
9879 subl(offset, 4);
9880
9881 Register op2 = tmp2;
9882 const Register sum = tmp3;
9883 const Register op1 = tmp4;
9884 const Register carry = tmp5;
9885
9886 if (UseBMI2Instructions) {
9887 op2 = rdxReg;
9888 }
9889
9890 movq(op1, Address(in, len, Address::times_4, 8));
9891 rorq(op1, 32);
9892 movq(sum, Address(out, offset, Address::times_4, 8));
9893 rorq(sum, 32);
9894 if (UseBMI2Instructions) {
9895 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
9896 }
9897 else {
9898 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
9899 }
9900 // Store back in big endian from little endian
9901 rorq(sum, 0x20);
9902 movq(Address(out, offset, Address::times_4, 8), sum);
9903
9904 movq(op1, Address(in, len, Address::times_4, 0));
9905 rorq(op1, 32);
9906 movq(sum, Address(out, offset, Address::times_4, 0));
9907 rorq(sum, 32);
9908 if (UseBMI2Instructions) {
9909 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
9910 }
9911 else {
9912 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
9913 }
9914 // Store back in big endian from little endian
9915 rorq(sum, 0x20);
9916 movq(Address(out, offset, Address::times_4, 0), sum);
9917
9918 jmp(L_first_loop);
9919 bind(L_first_loop_exit);
9920 }
9921
9922 /**
9923 * Code for BigInteger::mulAdd() intrinsic
9924 *
9925 * rdi: out
9926 * rsi: in
9927 * r11: offs (out.length - offset)
9928 * rcx: len
9929 * r8: k
9930 * r12: tmp1
9931 * r13: tmp2
9932 * r14: tmp3
9933 * r15: tmp4
9934 * rbx: tmp5
9935 * Multiply the in[] by word k and add to out[], return the carry in rax
9936 */
9937 void MacroAssembler::mul_add(Register out, Register in, Register offs,
9938 Register len, Register k, Register tmp1, Register tmp2, Register tmp3,
9939 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
9940
9941 Label L_carry, L_last_in, L_done;
9942
9943 // carry = 0;
9944 // for (int j=len-1; j >= 0; j--) {
9945 // long product = (in[j] & LONG_MASK) * kLong +
9946 // (out[offs] & LONG_MASK) + carry;
9947 // out[offs--] = (int)product;
9948 // carry = product >>> 32;
9949 // }
9950 //
9951 push(tmp1);
9952 push(tmp2);
9953 push(tmp3);
9954 push(tmp4);
9955 push(tmp5);
9956
9957 Register op2 = tmp2;
9958 const Register sum = tmp3;
9959 const Register op1 = tmp4;
9960 const Register carry = tmp5;
9961
9962 if (UseBMI2Instructions) {
9963 op2 = rdxReg;
9964 movl(op2, k);
9965 }
9966 else {
9967 movl(op2, k);
9968 }
9969
9970 xorq(carry, carry);
9971
9972 //First loop
9973
9974 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply
9975 //The carry is in tmp5
9976 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg);
9977
9978 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any
9979 decrementl(len);
9980 jccb(Assembler::negative, L_carry);
9981 decrementl(len);
9982 jccb(Assembler::negative, L_last_in);
9983
9984 movq(op1, Address(in, len, Address::times_4, 0));
9985 rorq(op1, 32);
9986
9987 subl(offs, 2);
9988 movq(sum, Address(out, offs, Address::times_4, 0));
9989 rorq(sum, 32);
9990
9991 if (UseBMI2Instructions) {
9992 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
9993 }
9994 else {
9995 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
9996 }
9997
9998 // Store back in big endian from little endian
9999 rorq(sum, 0x20);
10000 movq(Address(out, offs, Address::times_4, 0), sum);
10001
10002 testl(len, len);
10003 jccb(Assembler::zero, L_carry);
10004
10005 //Multiply the last in[] entry, if any
10006 bind(L_last_in);
10007 movl(op1, Address(in, 0));
10008 movl(sum, Address(out, offs, Address::times_4, -4));
10009
10010 movl(raxReg, k);
10011 mull(op1); //tmp4 * eax -> edx:eax
10012 addl(sum, carry);
10013 adcl(rdxReg, 0);
10014 addl(sum, raxReg);
10015 adcl(rdxReg, 0);
10016 movl(carry, rdxReg);
10017
10018 movl(Address(out, offs, Address::times_4, -4), sum);
10019
10020 bind(L_carry);
10021 //return tmp5/carry as carry in rax
10022 movl(rax, carry);
10023
10024 bind(L_done);
10025 pop(tmp5);
10026 pop(tmp4);
10027 pop(tmp3);
10028 pop(tmp2);
10029 pop(tmp1);
10030 }
10031 #endif
10032
10033 /**
10034 * Emits code to update CRC-32 with a byte value according to constants in table
10035 *
10036 * @param [in,out]crc Register containing the crc.
10037 * @param [in]val Register containing the byte to fold into the CRC.
10038 * @param [in]table Register containing the table of crc constants.
10039 *
10040 * uint32_t crc;
10041 * val = crc_table[(val ^ crc) & 0xFF];
10042 * crc = val ^ (crc >> 8);
10043 *
10044 */
10045 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
10046 xorl(val, crc);
10047 andl(val, 0xFF);
10048 shrl(crc, 8); // unsigned shift
10049 xorl(crc, Address(table, val, Address::times_4, 0));
10050 }
10051
10052 /**
10053 * Fold 128-bit data chunk
10054 */
10055 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
10056 if (UseAVX > 0) {
10057 vpclmulhdq(xtmp, xK, xcrc); // [123:64]
10058 vpclmulldq(xcrc, xK, xcrc); // [63:0]
10059 vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */);
10060 pxor(xcrc, xtmp);
10061 } else {
10062 movdqa(xtmp, xcrc);
10063 pclmulhdq(xtmp, xK); // [123:64]
10064 pclmulldq(xcrc, xK); // [63:0]
10065 pxor(xcrc, xtmp);
10066 movdqu(xtmp, Address(buf, offset));
10067 pxor(xcrc, xtmp);
10068 }
10069 }
10070
10071 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
10072 if (UseAVX > 0) {
10073 vpclmulhdq(xtmp, xK, xcrc);
10074 vpclmulldq(xcrc, xK, xcrc);
10075 pxor(xcrc, xbuf);
10076 pxor(xcrc, xtmp);
10077 } else {
10078 movdqa(xtmp, xcrc);
10079 pclmulhdq(xtmp, xK);
10080 pclmulldq(xcrc, xK);
10081 pxor(xcrc, xbuf);
10082 pxor(xcrc, xtmp);
10083 }
10084 }
10085
10086 /**
10087 * 8-bit folds to compute 32-bit CRC
10088 *
10089 * uint64_t xcrc;
10090 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
10091 */
10092 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
10093 movdl(tmp, xcrc);
10094 andl(tmp, 0xFF);
10095 movdl(xtmp, Address(table, tmp, Address::times_4, 0));
10096 psrldq(xcrc, 1); // unsigned shift one byte
10097 pxor(xcrc, xtmp);
10098 }
10099
10100 /**
10101 * uint32_t crc;
10102 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
10103 */
10104 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
10105 movl(tmp, crc);
10106 andl(tmp, 0xFF);
10107 shrl(crc, 8);
10108 xorl(crc, Address(table, tmp, Address::times_4, 0));
10109 }
10110
10111 /**
10112 * @param crc register containing existing CRC (32-bit)
10113 * @param buf register pointing to input byte buffer (byte*)
10114 * @param len register containing number of bytes
10115 * @param table register that will contain address of CRC table
10116 * @param tmp scratch register
10117 */
10118 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
10119 assert_different_registers(crc, buf, len, table, tmp, rax);
10120
10121 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
10122 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
10123
10124 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
10125 // context for the registers used, where all instructions below are using 128-bit mode
10126 // On EVEX without VL and BW, these instructions will all be AVX.
10127 if (VM_Version::supports_avx512vlbw()) {
10128 movl(tmp, 0xffff);
10129 kmovwl(k1, tmp);
10130 }
10131
10132 lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
10133 notl(crc); // ~crc
10134 cmpl(len, 16);
10135 jcc(Assembler::less, L_tail);
10136
10137 // Align buffer to 16 bytes
10138 movl(tmp, buf);
10139 andl(tmp, 0xF);
10140 jccb(Assembler::zero, L_aligned);
10141 subl(tmp, 16);
10142 addl(len, tmp);
10143
10144 align(4);
10145 BIND(L_align_loop);
10146 movsbl(rax, Address(buf, 0)); // load byte with sign extension
10147 update_byte_crc32(crc, rax, table);
10148 increment(buf);
10149 incrementl(tmp);
10150 jccb(Assembler::less, L_align_loop);
10151
10152 BIND(L_aligned);
10153 movl(tmp, len); // save
10154 shrl(len, 4);
10155 jcc(Assembler::zero, L_tail_restore);
10156
10157 // Fold crc into first bytes of vector
10158 movdqa(xmm1, Address(buf, 0));
10159 movdl(rax, xmm1);
10160 xorl(crc, rax);
10161 pinsrd(xmm1, crc, 0);
10162 addptr(buf, 16);
10163 subl(len, 4); // len > 0
10164 jcc(Assembler::less, L_fold_tail);
10165
10166 movdqa(xmm2, Address(buf, 0));
10167 movdqa(xmm3, Address(buf, 16));
10168 movdqa(xmm4, Address(buf, 32));
10169 addptr(buf, 48);
10170 subl(len, 3);
10171 jcc(Assembler::lessEqual, L_fold_512b);
10172
10173 // Fold total 512 bits of polynomial on each iteration,
10174 // 128 bits per each of 4 parallel streams.
10175 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32));
10176
10177 align(32);
10178 BIND(L_fold_512b_loop);
10179 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
10180 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
10181 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
10182 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
10183 addptr(buf, 64);
10184 subl(len, 4);
10185 jcc(Assembler::greater, L_fold_512b_loop);
10186
10187 // Fold 512 bits to 128 bits.
10188 BIND(L_fold_512b);
10189 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
10190 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
10191 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
10192 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
10193
10194 // Fold the rest of 128 bits data chunks
10195 BIND(L_fold_tail);
10196 addl(len, 3);
10197 jccb(Assembler::lessEqual, L_fold_128b);
10198 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
10199
10200 BIND(L_fold_tail_loop);
10201 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
10202 addptr(buf, 16);
10203 decrementl(len);
10204 jccb(Assembler::greater, L_fold_tail_loop);
10205
10206 // Fold 128 bits in xmm1 down into 32 bits in crc register.
10207 BIND(L_fold_128b);
10208 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()));
10209 if (UseAVX > 0) {
10210 vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
10211 vpand(xmm3, xmm0, xmm2, 0 /* vector_len */);
10212 vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
10213 } else {
10214 movdqa(xmm2, xmm0);
10215 pclmulqdq(xmm2, xmm1, 0x1);
10216 movdqa(xmm3, xmm0);
10217 pand(xmm3, xmm2);
10218 pclmulqdq(xmm0, xmm3, 0x1);
10219 }
10220 psrldq(xmm1, 8);
10221 psrldq(xmm2, 4);
10222 pxor(xmm0, xmm1);
10223 pxor(xmm0, xmm2);
10224
10225 // 8 8-bit folds to compute 32-bit CRC.
10226 for (int j = 0; j < 4; j++) {
10227 fold_8bit_crc32(xmm0, table, xmm1, rax);
10228 }
10229 movdl(crc, xmm0); // mov 32 bits to general register
10230 for (int j = 0; j < 4; j++) {
10231 fold_8bit_crc32(crc, table, rax);
10232 }
10233
10234 BIND(L_tail_restore);
10235 movl(len, tmp); // restore
10236 BIND(L_tail);
10237 andl(len, 0xf);
10238 jccb(Assembler::zero, L_exit);
10239
10240 // Fold the rest of bytes
10241 align(4);
10242 BIND(L_tail_loop);
10243 movsbl(rax, Address(buf, 0)); // load byte with sign extension
10244 update_byte_crc32(crc, rax, table);
10245 increment(buf);
10246 decrementl(len);
10247 jccb(Assembler::greater, L_tail_loop);
10248
10249 BIND(L_exit);
10250 notl(crc); // ~c
10251 }
10252
10253 #ifdef _LP64
10254 // S. Gueron / Information Processing Letters 112 (2012) 184
10255 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table.
10256 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0].
10257 // Output: the 64-bit carry-less product of B * CONST
10258 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n,
10259 Register tmp1, Register tmp2, Register tmp3) {
10260 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
10261 if (n > 0) {
10262 addq(tmp3, n * 256 * 8);
10263 }
10264 // Q1 = TABLEExt[n][B & 0xFF];
10265 movl(tmp1, in);
10266 andl(tmp1, 0x000000FF);
10267 shll(tmp1, 3);
10268 addq(tmp1, tmp3);
10269 movq(tmp1, Address(tmp1, 0));
10270
10271 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
10272 movl(tmp2, in);
10273 shrl(tmp2, 8);
10274 andl(tmp2, 0x000000FF);
10275 shll(tmp2, 3);
10276 addq(tmp2, tmp3);
10277 movq(tmp2, Address(tmp2, 0));
10278
10279 shlq(tmp2, 8);
10280 xorq(tmp1, tmp2);
10281
10282 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
10283 movl(tmp2, in);
10284 shrl(tmp2, 16);
10285 andl(tmp2, 0x000000FF);
10286 shll(tmp2, 3);
10287 addq(tmp2, tmp3);
10288 movq(tmp2, Address(tmp2, 0));
10289
10290 shlq(tmp2, 16);
10291 xorq(tmp1, tmp2);
10292
10293 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
10294 shrl(in, 24);
10295 andl(in, 0x000000FF);
10296 shll(in, 3);
10297 addq(in, tmp3);
10298 movq(in, Address(in, 0));
10299
10300 shlq(in, 24);
10301 xorq(in, tmp1);
10302 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
10303 }
10304
10305 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
10306 Register in_out,
10307 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
10308 XMMRegister w_xtmp2,
10309 Register tmp1,
10310 Register n_tmp2, Register n_tmp3) {
10311 if (is_pclmulqdq_supported) {
10312 movdl(w_xtmp1, in_out); // modified blindly
10313
10314 movl(tmp1, const_or_pre_comp_const_index);
10315 movdl(w_xtmp2, tmp1);
10316 pclmulqdq(w_xtmp1, w_xtmp2, 0);
10317
10318 movdq(in_out, w_xtmp1);
10319 } else {
10320 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3);
10321 }
10322 }
10323
10324 // Recombination Alternative 2: No bit-reflections
10325 // T1 = (CRC_A * U1) << 1
10326 // T2 = (CRC_B * U2) << 1
10327 // C1 = T1 >> 32
10328 // C2 = T2 >> 32
10329 // T1 = T1 & 0xFFFFFFFF
10330 // T2 = T2 & 0xFFFFFFFF
10331 // T1 = CRC32(0, T1)
10332 // T2 = CRC32(0, T2)
10333 // C1 = C1 ^ T1
10334 // C2 = C2 ^ T2
10335 // CRC = C1 ^ C2 ^ CRC_C
10336 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
10337 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10338 Register tmp1, Register tmp2,
10339 Register n_tmp3) {
10340 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
10341 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
10342 shlq(in_out, 1);
10343 movl(tmp1, in_out);
10344 shrq(in_out, 32);
10345 xorl(tmp2, tmp2);
10346 crc32(tmp2, tmp1, 4);
10347 xorl(in_out, tmp2); // we don't care about upper 32 bit contents here
10348 shlq(in1, 1);
10349 movl(tmp1, in1);
10350 shrq(in1, 32);
10351 xorl(tmp2, tmp2);
10352 crc32(tmp2, tmp1, 4);
10353 xorl(in1, tmp2);
10354 xorl(in_out, in1);
10355 xorl(in_out, in2);
10356 }
10357
10358 // Set N to predefined value
10359 // Subtract from a lenght of a buffer
10360 // execute in a loop:
10361 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0
10362 // for i = 1 to N do
10363 // CRC_A = CRC32(CRC_A, A[i])
10364 // CRC_B = CRC32(CRC_B, B[i])
10365 // CRC_C = CRC32(CRC_C, C[i])
10366 // end for
10367 // Recombine
10368 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
10369 Register in_out1, Register in_out2, Register in_out3,
10370 Register tmp1, Register tmp2, Register tmp3,
10371 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10372 Register tmp4, Register tmp5,
10373 Register n_tmp6) {
10374 Label L_processPartitions;
10375 Label L_processPartition;
10376 Label L_exit;
10377
10378 bind(L_processPartitions);
10379 cmpl(in_out1, 3 * size);
10380 jcc(Assembler::less, L_exit);
10381 xorl(tmp1, tmp1);
10382 xorl(tmp2, tmp2);
10383 movq(tmp3, in_out2);
10384 addq(tmp3, size);
10385
10386 bind(L_processPartition);
10387 crc32(in_out3, Address(in_out2, 0), 8);
10388 crc32(tmp1, Address(in_out2, size), 8);
10389 crc32(tmp2, Address(in_out2, size * 2), 8);
10390 addq(in_out2, 8);
10391 cmpq(in_out2, tmp3);
10392 jcc(Assembler::less, L_processPartition);
10393 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
10394 w_xtmp1, w_xtmp2, w_xtmp3,
10395 tmp4, tmp5,
10396 n_tmp6);
10397 addq(in_out2, 2 * size);
10398 subl(in_out1, 3 * size);
10399 jmp(L_processPartitions);
10400
10401 bind(L_exit);
10402 }
10403 #else
10404 void MacroAssembler::crc32c_ipl_alg4(Register in_out, uint32_t n,
10405 Register tmp1, Register tmp2, Register tmp3,
10406 XMMRegister xtmp1, XMMRegister xtmp2) {
10407 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
10408 if (n > 0) {
10409 addl(tmp3, n * 256 * 8);
10410 }
10411 // Q1 = TABLEExt[n][B & 0xFF];
10412 movl(tmp1, in_out);
10413 andl(tmp1, 0x000000FF);
10414 shll(tmp1, 3);
10415 addl(tmp1, tmp3);
10416 movq(xtmp1, Address(tmp1, 0));
10417
10418 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
10419 movl(tmp2, in_out);
10420 shrl(tmp2, 8);
10421 andl(tmp2, 0x000000FF);
10422 shll(tmp2, 3);
10423 addl(tmp2, tmp3);
10424 movq(xtmp2, Address(tmp2, 0));
10425
10426 psllq(xtmp2, 8);
10427 pxor(xtmp1, xtmp2);
10428
10429 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
10430 movl(tmp2, in_out);
10431 shrl(tmp2, 16);
10432 andl(tmp2, 0x000000FF);
10433 shll(tmp2, 3);
10434 addl(tmp2, tmp3);
10435 movq(xtmp2, Address(tmp2, 0));
10436
10437 psllq(xtmp2, 16);
10438 pxor(xtmp1, xtmp2);
10439
10440 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
10441 shrl(in_out, 24);
10442 andl(in_out, 0x000000FF);
10443 shll(in_out, 3);
10444 addl(in_out, tmp3);
10445 movq(xtmp2, Address(in_out, 0));
10446
10447 psllq(xtmp2, 24);
10448 pxor(xtmp1, xtmp2); // Result in CXMM
10449 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
10450 }
10451
10452 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
10453 Register in_out,
10454 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
10455 XMMRegister w_xtmp2,
10456 Register tmp1,
10457 Register n_tmp2, Register n_tmp3) {
10458 if (is_pclmulqdq_supported) {
10459 movdl(w_xtmp1, in_out);
10460
10461 movl(tmp1, const_or_pre_comp_const_index);
10462 movdl(w_xtmp2, tmp1);
10463 pclmulqdq(w_xtmp1, w_xtmp2, 0);
10464 // Keep result in XMM since GPR is 32 bit in length
10465 } else {
10466 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3, w_xtmp1, w_xtmp2);
10467 }
10468 }
10469
10470 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
10471 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10472 Register tmp1, Register tmp2,
10473 Register n_tmp3) {
10474 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
10475 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
10476
10477 psllq(w_xtmp1, 1);
10478 movdl(tmp1, w_xtmp1);
10479 psrlq(w_xtmp1, 32);
10480 movdl(in_out, w_xtmp1);
10481
10482 xorl(tmp2, tmp2);
10483 crc32(tmp2, tmp1, 4);
10484 xorl(in_out, tmp2);
10485
10486 psllq(w_xtmp2, 1);
10487 movdl(tmp1, w_xtmp2);
10488 psrlq(w_xtmp2, 32);
10489 movdl(in1, w_xtmp2);
10490
10491 xorl(tmp2, tmp2);
10492 crc32(tmp2, tmp1, 4);
10493 xorl(in1, tmp2);
10494 xorl(in_out, in1);
10495 xorl(in_out, in2);
10496 }
10497
10498 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
10499 Register in_out1, Register in_out2, Register in_out3,
10500 Register tmp1, Register tmp2, Register tmp3,
10501 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10502 Register tmp4, Register tmp5,
10503 Register n_tmp6) {
10504 Label L_processPartitions;
10505 Label L_processPartition;
10506 Label L_exit;
10507
10508 bind(L_processPartitions);
10509 cmpl(in_out1, 3 * size);
10510 jcc(Assembler::less, L_exit);
10511 xorl(tmp1, tmp1);
10512 xorl(tmp2, tmp2);
10513 movl(tmp3, in_out2);
10514 addl(tmp3, size);
10515
10516 bind(L_processPartition);
10517 crc32(in_out3, Address(in_out2, 0), 4);
10518 crc32(tmp1, Address(in_out2, size), 4);
10519 crc32(tmp2, Address(in_out2, size*2), 4);
10520 crc32(in_out3, Address(in_out2, 0+4), 4);
10521 crc32(tmp1, Address(in_out2, size+4), 4);
10522 crc32(tmp2, Address(in_out2, size*2+4), 4);
10523 addl(in_out2, 8);
10524 cmpl(in_out2, tmp3);
10525 jcc(Assembler::less, L_processPartition);
10526
10527 push(tmp3);
10528 push(in_out1);
10529 push(in_out2);
10530 tmp4 = tmp3;
10531 tmp5 = in_out1;
10532 n_tmp6 = in_out2;
10533
10534 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
10535 w_xtmp1, w_xtmp2, w_xtmp3,
10536 tmp4, tmp5,
10537 n_tmp6);
10538
10539 pop(in_out2);
10540 pop(in_out1);
10541 pop(tmp3);
10542
10543 addl(in_out2, 2 * size);
10544 subl(in_out1, 3 * size);
10545 jmp(L_processPartitions);
10546
10547 bind(L_exit);
10548 }
10549 #endif //LP64
10550
10551 #ifdef _LP64
10552 // Algorithm 2: Pipelined usage of the CRC32 instruction.
10553 // Input: A buffer I of L bytes.
10554 // Output: the CRC32C value of the buffer.
10555 // Notations:
10556 // Write L = 24N + r, with N = floor (L/24).
10557 // r = L mod 24 (0 <= r < 24).
10558 // Consider I as the concatenation of A|B|C|R, where A, B, C, each,
10559 // N quadwords, and R consists of r bytes.
10560 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1
10561 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1
10562 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1
10563 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1
10564 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
10565 Register tmp1, Register tmp2, Register tmp3,
10566 Register tmp4, Register tmp5, Register tmp6,
10567 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10568 bool is_pclmulqdq_supported) {
10569 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
10570 Label L_wordByWord;
10571 Label L_byteByByteProlog;
10572 Label L_byteByByte;
10573 Label L_exit;
10574
10575 if (is_pclmulqdq_supported ) {
10576 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
10577 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr+1);
10578
10579 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
10580 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
10581
10582 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
10583 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
10584 assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\"");
10585 } else {
10586 const_or_pre_comp_const_index[0] = 1;
10587 const_or_pre_comp_const_index[1] = 0;
10588
10589 const_or_pre_comp_const_index[2] = 3;
10590 const_or_pre_comp_const_index[3] = 2;
10591
10592 const_or_pre_comp_const_index[4] = 5;
10593 const_or_pre_comp_const_index[5] = 4;
10594 }
10595 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
10596 in2, in1, in_out,
10597 tmp1, tmp2, tmp3,
10598 w_xtmp1, w_xtmp2, w_xtmp3,
10599 tmp4, tmp5,
10600 tmp6);
10601 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
10602 in2, in1, in_out,
10603 tmp1, tmp2, tmp3,
10604 w_xtmp1, w_xtmp2, w_xtmp3,
10605 tmp4, tmp5,
10606 tmp6);
10607 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
10608 in2, in1, in_out,
10609 tmp1, tmp2, tmp3,
10610 w_xtmp1, w_xtmp2, w_xtmp3,
10611 tmp4, tmp5,
10612 tmp6);
10613 movl(tmp1, in2);
10614 andl(tmp1, 0x00000007);
10615 negl(tmp1);
10616 addl(tmp1, in2);
10617 addq(tmp1, in1);
10618
10619 BIND(L_wordByWord);
10620 cmpq(in1, tmp1);
10621 jcc(Assembler::greaterEqual, L_byteByByteProlog);
10622 crc32(in_out, Address(in1, 0), 4);
10623 addq(in1, 4);
10624 jmp(L_wordByWord);
10625
10626 BIND(L_byteByByteProlog);
10627 andl(in2, 0x00000007);
10628 movl(tmp2, 1);
10629
10630 BIND(L_byteByByte);
10631 cmpl(tmp2, in2);
10632 jccb(Assembler::greater, L_exit);
10633 crc32(in_out, Address(in1, 0), 1);
10634 incq(in1);
10635 incl(tmp2);
10636 jmp(L_byteByByte);
10637
10638 BIND(L_exit);
10639 }
10640 #else
10641 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
10642 Register tmp1, Register tmp2, Register tmp3,
10643 Register tmp4, Register tmp5, Register tmp6,
10644 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10645 bool is_pclmulqdq_supported) {
10646 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
10647 Label L_wordByWord;
10648 Label L_byteByByteProlog;
10649 Label L_byteByByte;
10650 Label L_exit;
10651
10652 if (is_pclmulqdq_supported) {
10653 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
10654 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 1);
10655
10656 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
10657 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
10658
10659 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
10660 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
10661 } else {
10662 const_or_pre_comp_const_index[0] = 1;
10663 const_or_pre_comp_const_index[1] = 0;
10664
10665 const_or_pre_comp_const_index[2] = 3;
10666 const_or_pre_comp_const_index[3] = 2;
10667
10668 const_or_pre_comp_const_index[4] = 5;
10669 const_or_pre_comp_const_index[5] = 4;
10670 }
10671 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
10672 in2, in1, in_out,
10673 tmp1, tmp2, tmp3,
10674 w_xtmp1, w_xtmp2, w_xtmp3,
10675 tmp4, tmp5,
10676 tmp6);
10677 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
10678 in2, in1, in_out,
10679 tmp1, tmp2, tmp3,
10680 w_xtmp1, w_xtmp2, w_xtmp3,
10681 tmp4, tmp5,
10682 tmp6);
10683 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
10684 in2, in1, in_out,
10685 tmp1, tmp2, tmp3,
10686 w_xtmp1, w_xtmp2, w_xtmp3,
10687 tmp4, tmp5,
10688 tmp6);
10689 movl(tmp1, in2);
10690 andl(tmp1, 0x00000007);
10691 negl(tmp1);
10692 addl(tmp1, in2);
10693 addl(tmp1, in1);
10694
10695 BIND(L_wordByWord);
10696 cmpl(in1, tmp1);
10697 jcc(Assembler::greaterEqual, L_byteByByteProlog);
10698 crc32(in_out, Address(in1,0), 4);
10699 addl(in1, 4);
10700 jmp(L_wordByWord);
10701
10702 BIND(L_byteByByteProlog);
10703 andl(in2, 0x00000007);
10704 movl(tmp2, 1);
10705
10706 BIND(L_byteByByte);
10707 cmpl(tmp2, in2);
10708 jccb(Assembler::greater, L_exit);
10709 movb(tmp1, Address(in1, 0));
10710 crc32(in_out, tmp1, 1);
10711 incl(in1);
10712 incl(tmp2);
10713 jmp(L_byteByByte);
10714
10715 BIND(L_exit);
10716 }
10717 #endif // LP64
10718 #undef BIND
10719 #undef BLOCK_COMMENT
10720
10721 // Compress char[] array to byte[].
10722 // ..\jdk\src\java.base\share\classes\java\lang\StringUTF16.java
10723 // @HotSpotIntrinsicCandidate
10724 // private static int compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) {
10725 // for (int i = 0; i < len; i++) {
10726 // int c = src[srcOff++];
10727 // if (c >>> 8 != 0) {
10728 // return 0;
10729 // }
10730 // dst[dstOff++] = (byte)c;
10731 // }
10732 // return len;
10733 // }
10734 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
10735 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
10736 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
10737 Register tmp5, Register result) {
10738 Label copy_chars_loop, return_length, return_zero, done, below_threshold;
10739
10740 // rsi: src
10741 // rdi: dst
10742 // rdx: len
10743 // rcx: tmp5
10744 // rax: result
10745
10746 // rsi holds start addr of source char[] to be compressed
10747 // rdi holds start addr of destination byte[]
10748 // rdx holds length
10749
10750 assert(len != result, "");
10751
10752 // save length for return
10753 push(len);
10754
10755 if ((UseAVX > 2) && // AVX512
10756 VM_Version::supports_avx512vlbw() &&
10757 VM_Version::supports_bmi2()) {
10758
10759 set_vector_masking(); // opening of the stub context for programming mask registers
10760
10761 Label copy_32_loop, copy_loop_tail, copy_just_portion_of_candidates;
10762
10763 // alignement
10764 Label post_alignement;
10765
10766 // if length of the string is less than 16, handle it in an old fashioned
10767 // way
10768 testl(len, -32);
10769 jcc(Assembler::zero, below_threshold);
10770
10771 // First check whether a character is compressable ( <= 0xFF).
10772 // Create mask to test for Unicode chars inside zmm vector
10773 movl(result, 0x00FF);
10774 evpbroadcastw(tmp2Reg, result, Assembler::AVX_512bit);
10775
10776 testl(len, -64);
10777 jcc(Assembler::zero, post_alignement);
10778
10779 // Save k1
10780 kmovql(k3, k1);
10781
10782 movl(tmp5, dst);
10783 andl(tmp5, (64 - 1));
10784 negl(tmp5);
10785 andl(tmp5, (64 - 1));
10786
10787 // bail out when there is nothing to be done
10788 testl(tmp5, 0xFFFFFFFF);
10789 jcc(Assembler::zero, post_alignement);
10790
10791 // ~(~0 << len), where len is the # of remaining elements to process
10792 movl(result, 0xFFFFFFFF);
10793 shlxl(result, result, tmp5);
10794 notl(result);
10795
10796 kmovdl(k1, result);
10797
10798 evmovdquw(tmp1Reg, k1, Address(src, 0), Assembler::AVX_512bit);
10799 evpcmpuw(k2, k1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
10800 ktestd(k2, k1);
10801 jcc(Assembler::carryClear, copy_just_portion_of_candidates);
10802
10803 evpmovwb(Address(dst, 0), k1, tmp1Reg, Assembler::AVX_512bit);
10804
10805 addptr(src, tmp5);
10806 addptr(src, tmp5);
10807 addptr(dst, tmp5);
10808 subl(len, tmp5);
10809
10810 bind(post_alignement);
10811 // end of alignement
10812
10813 movl(tmp5, len);
10814 andl(tmp5, (32 - 1)); // tail count (in chars)
10815 andl(len, ~(32 - 1)); // vector count (in chars)
10816 jcc(Assembler::zero, copy_loop_tail);
10817
10818 lea(src, Address(src, len, Address::times_2));
10819 lea(dst, Address(dst, len, Address::times_1));
10820 negptr(len);
10821
10822 bind(copy_32_loop);
10823 evmovdquw(tmp1Reg, Address(src, len, Address::times_2), Assembler::AVX_512bit);
10824 evpcmpuw(k2, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
10825 kortestdl(k2, k2);
10826 jcc(Assembler::carryClear, copy_just_portion_of_candidates);
10827
10828 // All elements in current processed chunk are valid candidates for
10829 // compression. Write a truncated byte elements to the memory.
10830 evpmovwb(Address(dst, len, Address::times_1), tmp1Reg, Assembler::AVX_512bit);
10831 addptr(len, 32);
10832 jcc(Assembler::notZero, copy_32_loop);
10833
10834 bind(copy_loop_tail);
10835 // bail out when there is nothing to be done
10836 testl(tmp5, 0xFFFFFFFF);
10837 jcc(Assembler::zero, return_length);
10838
10839 // Save k1
10840 kmovql(k3, k1);
10841
10842 movl(len, tmp5);
10843
10844 // ~(~0 << len), where len is the # of remaining elements to process
10845 movl(result, 0xFFFFFFFF);
10846 shlxl(result, result, len);
10847 notl(result);
10848
10849 kmovdl(k1, result);
10850
10851 evmovdquw(tmp1Reg, k1, Address(src, 0), Assembler::AVX_512bit);
10852 evpcmpuw(k2, k1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
10853 ktestd(k2, k1);
10854 jcc(Assembler::carryClear, copy_just_portion_of_candidates);
10855
10856 evpmovwb(Address(dst, 0), k1, tmp1Reg, Assembler::AVX_512bit);
10857 // Restore k1
10858 kmovql(k1, k3);
10859
10860 jmp(return_length);
10861
10862 bind(copy_just_portion_of_candidates);
10863 kmovdl(tmp5, k2);
10864 tzcntl(tmp5, tmp5);
10865
10866 // ~(~0 << tmp5), where tmp5 is a number of elements in an array from the
10867 // result to the first element larger than 0xFF
10868 movl(result, 0xFFFFFFFF);
10869 shlxl(result, result, tmp5);
10870 notl(result);
10871
10872 kmovdl(k1, result);
10873
10874 evpmovwb(Address(dst, 0), k1, tmp1Reg, Assembler::AVX_512bit);
10875 // Restore k1
10876 kmovql(k1, k3);
10877
10878 jmp(return_zero);
10879
10880 clear_vector_masking(); // closing of the stub context for programming mask registers
10881 }
10882 if (UseSSE42Intrinsics) {
10883 assert(UseSSE >= 4, "SSE4 must be enabled for SSE4.2 intrinsics to be available");
10884 Label copy_32_loop, copy_16, copy_tail;
10885
10886 bind(below_threshold);
10887
10888 movl(result, len);
10889
10890 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vectors
10891
10892 // vectored compression
10893 andl(len, 0xfffffff0); // vector count (in chars)
10894 andl(result, 0x0000000f); // tail count (in chars)
10895 testl(len, len);
10896 jccb(Assembler::zero, copy_16);
10897
10898 // compress 16 chars per iter
10899 movdl(tmp1Reg, tmp5);
10900 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
10901 pxor(tmp4Reg, tmp4Reg);
10902
10903 lea(src, Address(src, len, Address::times_2));
10904 lea(dst, Address(dst, len, Address::times_1));
10905 negptr(len);
10906
10907 bind(copy_32_loop);
10908 movdqu(tmp2Reg, Address(src, len, Address::times_2)); // load 1st 8 characters
10909 por(tmp4Reg, tmp2Reg);
10910 movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters
10911 por(tmp4Reg, tmp3Reg);
10912 ptest(tmp4Reg, tmp1Reg); // check for Unicode chars in next vector
10913 jcc(Assembler::notZero, return_zero);
10914 packuswb(tmp2Reg, tmp3Reg); // only ASCII chars; compress each to 1 byte
10915 movdqu(Address(dst, len, Address::times_1), tmp2Reg);
10916 addptr(len, 16);
10917 jcc(Assembler::notZero, copy_32_loop);
10918
10919 // compress next vector of 8 chars (if any)
10920 bind(copy_16);
10921 movl(len, result);
10922 andl(len, 0xfffffff8); // vector count (in chars)
10923 andl(result, 0x00000007); // tail count (in chars)
10924 testl(len, len);
10925 jccb(Assembler::zero, copy_tail);
10926
10927 movdl(tmp1Reg, tmp5);
10928 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
10929 pxor(tmp3Reg, tmp3Reg);
10930
10931 movdqu(tmp2Reg, Address(src, 0));
10932 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
10933 jccb(Assembler::notZero, return_zero);
10934 packuswb(tmp2Reg, tmp3Reg); // only LATIN1 chars; compress each to 1 byte
10935 movq(Address(dst, 0), tmp2Reg);
10936 addptr(src, 16);
10937 addptr(dst, 8);
10938
10939 bind(copy_tail);
10940 movl(len, result);
10941 }
10942 // compress 1 char per iter
10943 testl(len, len);
10944 jccb(Assembler::zero, return_length);
10945 lea(src, Address(src, len, Address::times_2));
10946 lea(dst, Address(dst, len, Address::times_1));
10947 negptr(len);
10948
10949 bind(copy_chars_loop);
10950 load_unsigned_short(result, Address(src, len, Address::times_2));
10951 testl(result, 0xff00); // check if Unicode char
10952 jccb(Assembler::notZero, return_zero);
10953 movb(Address(dst, len, Address::times_1), result); // ASCII char; compress to 1 byte
10954 increment(len);
10955 jcc(Assembler::notZero, copy_chars_loop);
10956
10957 // if compression succeeded, return length
10958 bind(return_length);
10959 pop(result);
10960 jmpb(done);
10961
10962 // if compression failed, return 0
10963 bind(return_zero);
10964 xorl(result, result);
10965 addptr(rsp, wordSize);
10966
10967 bind(done);
10968 }
10969
10970 // Inflate byte[] array to char[].
10971 // ..\jdk\src\java.base\share\classes\java\lang\StringLatin1.java
10972 // @HotSpotIntrinsicCandidate
10973 // private static void inflate(byte[] src, int srcOff, char[] dst, int dstOff, int len) {
10974 // for (int i = 0; i < len; i++) {
10975 // dst[dstOff++] = (char)(src[srcOff++] & 0xff);
10976 // }
10977 // }
10978 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
10979 XMMRegister tmp1, Register tmp2) {
10980 Label copy_chars_loop, done, below_threshold;
10981 // rsi: src
10982 // rdi: dst
10983 // rdx: len
10984 // rcx: tmp2
10985
10986 // rsi holds start addr of source byte[] to be inflated
10987 // rdi holds start addr of destination char[]
10988 // rdx holds length
10989 assert_different_registers(src, dst, len, tmp2);
10990
10991 if ((UseAVX > 2) && // AVX512
10992 VM_Version::supports_avx512vlbw() &&
10993 VM_Version::supports_bmi2()) {
10994
10995 set_vector_masking(); // opening of the stub context for programming mask registers
10996
10997 Label copy_32_loop, copy_tail;
10998 Register tmp3_aliased = len;
10999
11000 // if length of the string is less than 16, handle it in an old fashioned
11001 // way
11002 testl(len, -16);
11003 jcc(Assembler::zero, below_threshold);
11004
11005 // In order to use only one arithmetic operation for the main loop we use
11006 // this pre-calculation
11007 movl(tmp2, len);
11008 andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop
11009 andl(len, -32); // vector count
11010 jccb(Assembler::zero, copy_tail);
11011
11012 lea(src, Address(src, len, Address::times_1));
11013 lea(dst, Address(dst, len, Address::times_2));
11014 negptr(len);
11015
11016
11017 // inflate 32 chars per iter
11018 bind(copy_32_loop);
11019 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_512bit);
11020 evmovdquw(Address(dst, len, Address::times_2), tmp1, Assembler::AVX_512bit);
11021 addptr(len, 32);
11022 jcc(Assembler::notZero, copy_32_loop);
11023
11024 bind(copy_tail);
11025 // bail out when there is nothing to be done
11026 testl(tmp2, -1); // we don't destroy the contents of tmp2 here
11027 jcc(Assembler::zero, done);
11028
11029 // Save k1
11030 kmovql(k2, k1);
11031
11032 // ~(~0 << length), where length is the # of remaining elements to process
11033 movl(tmp3_aliased, -1);
11034 shlxl(tmp3_aliased, tmp3_aliased, tmp2);
11035 notl(tmp3_aliased);
11036 kmovdl(k1, tmp3_aliased);
11037 evpmovzxbw(tmp1, k1, Address(src, 0), Assembler::AVX_512bit);
11038 evmovdquw(Address(dst, 0), k1, tmp1, Assembler::AVX_512bit);
11039
11040 // Restore k1
11041 kmovql(k1, k2);
11042 jmp(done);
11043
11044 clear_vector_masking(); // closing of the stub context for programming mask registers
11045 }
11046 if (UseSSE42Intrinsics) {
11047 assert(UseSSE >= 4, "SSE4 must be enabled for SSE4.2 intrinsics to be available");
11048 Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail;
11049
11050 movl(tmp2, len);
11051
11052 if (UseAVX > 1) {
11053 andl(tmp2, (16 - 1));
11054 andl(len, -16);
11055 jccb(Assembler::zero, copy_new_tail);
11056 } else {
11057 andl(tmp2, 0x00000007); // tail count (in chars)
11058 andl(len, 0xfffffff8); // vector count (in chars)
11059 jccb(Assembler::zero, copy_tail);
11060 }
11061
11062 // vectored inflation
11063 lea(src, Address(src, len, Address::times_1));
11064 lea(dst, Address(dst, len, Address::times_2));
11065 negptr(len);
11066
11067 if (UseAVX > 1) {
11068 bind(copy_16_loop);
11069 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_256bit);
11070 vmovdqu(Address(dst, len, Address::times_2), tmp1);
11071 addptr(len, 16);
11072 jcc(Assembler::notZero, copy_16_loop);
11073
11074 bind(below_threshold);
11075 bind(copy_new_tail);
11076 if (UseAVX > 2) {
11077 movl(tmp2, len);
11078 }
11079 else {
11080 movl(len, tmp2);
11081 }
11082 andl(tmp2, 0x00000007);
11083 andl(len, 0xFFFFFFF8);
11084 jccb(Assembler::zero, copy_tail);
11085
11086 pmovzxbw(tmp1, Address(src, 0));
11087 movdqu(Address(dst, 0), tmp1);
11088 addptr(src, 8);
11089 addptr(dst, 2 * 8);
11090
11091 jmp(copy_tail, true);
11092 }
11093
11094 // inflate 8 chars per iter
11095 bind(copy_8_loop);
11096 pmovzxbw(tmp1, Address(src, len, Address::times_1)); // unpack to 8 words
11097 movdqu(Address(dst, len, Address::times_2), tmp1);
11098 addptr(len, 8);
11099 jcc(Assembler::notZero, copy_8_loop);
11100
11101 bind(copy_tail);
11102 movl(len, tmp2);
11103
11104 cmpl(len, 4);
11105 jccb(Assembler::less, copy_bytes);
11106
11107 movdl(tmp1, Address(src, 0)); // load 4 byte chars
11108 pmovzxbw(tmp1, tmp1);
11109 movq(Address(dst, 0), tmp1);
11110 subptr(len, 4);
11111 addptr(src, 4);
11112 addptr(dst, 8);
11113
11114 bind(copy_bytes);
11115 }
11116 testl(len, len);
11117 jccb(Assembler::zero, done);
11118 lea(src, Address(src, len, Address::times_1));
11119 lea(dst, Address(dst, len, Address::times_2));
11120 negptr(len);
11121
11122 // inflate 1 char per iter
11123 bind(copy_chars_loop);
11124 load_unsigned_byte(tmp2, Address(src, len, Address::times_1)); // load byte char
11125 movw(Address(dst, len, Address::times_2), tmp2); // inflate byte char to word
11126 increment(len);
11127 jcc(Assembler::notZero, copy_chars_loop);
11128
11129 bind(done);
11130 }
11131
11132 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
11133 switch (cond) {
11134 // Note some conditions are synonyms for others
11135 case Assembler::zero: return Assembler::notZero;
11136 case Assembler::notZero: return Assembler::zero;
11137 case Assembler::less: return Assembler::greaterEqual;
11138 case Assembler::lessEqual: return Assembler::greater;
11139 case Assembler::greater: return Assembler::lessEqual;
11140 case Assembler::greaterEqual: return Assembler::less;
11141 case Assembler::below: return Assembler::aboveEqual;
11142 case Assembler::belowEqual: return Assembler::above;
11143 case Assembler::above: return Assembler::belowEqual;
11144 case Assembler::aboveEqual: return Assembler::below;
11145 case Assembler::overflow: return Assembler::noOverflow;
11146 case Assembler::noOverflow: return Assembler::overflow;
11147 case Assembler::negative: return Assembler::positive;
11148 case Assembler::positive: return Assembler::negative;
11149 case Assembler::parity: return Assembler::noParity;
11150 case Assembler::noParity: return Assembler::parity;
11151 }
11152 ShouldNotReachHere(); return Assembler::overflow;
11153 }
11154
11155 SkipIfEqual::SkipIfEqual(
11156 MacroAssembler* masm, const bool* flag_addr, bool value) {
11157 _masm = masm;
11158 _masm->cmp8(ExternalAddress((address)flag_addr), value);
11159 _masm->jcc(Assembler::equal, _label);
11160 }
11161
11162 SkipIfEqual::~SkipIfEqual() {
11163 _masm->bind(_label);
11164 }
11165
11166 // 32-bit Windows has its own fast-path implementation
11167 // of get_thread
11168 #if !defined(WIN32) || defined(_LP64)
11169
11170 // This is simply a call to Thread::current()
11171 void MacroAssembler::get_thread(Register thread) {
11172 if (thread != rax) {
11173 push(rax);
11174 }
11175 LP64_ONLY(push(rdi);)
11176 LP64_ONLY(push(rsi);)
11177 push(rdx);
11178 push(rcx);
11179 #ifdef _LP64
11180 push(r8);
11181 push(r9);
11182 push(r10);
11183 push(r11);
11184 #endif
11185
11186 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0);
11187
11188 #ifdef _LP64
11189 pop(r11);
11190 pop(r10);
11191 pop(r9);
11192 pop(r8);
11193 #endif
11194 pop(rcx);
11195 pop(rdx);
11196 LP64_ONLY(pop(rsi);)
11197 LP64_ONLY(pop(rdi);)
11198 if (thread != rax) {
11199 mov(thread, rax);
11200 pop(rax);
11201 }
11202 }
11203
11204 #endif