1 /*
2 * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
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23 */
24
25 #ifndef CPU_X86_VM_MACROASSEMBLER_X86_HPP
26 #define CPU_X86_VM_MACROASSEMBLER_X86_HPP
27
28 #include "asm/assembler.hpp"
29 #include "utilities/macros.hpp"
30 #include "runtime/rtmLocking.hpp"
31
32 // MacroAssembler extends Assembler by frequently used macros.
33 //
34 // Instructions for which a 'better' code sequence exists depending
35 // on arguments should also go in here.
36
37 class MacroAssembler: public Assembler {
38 friend class LIR_Assembler;
39 friend class Runtime1; // as_Address()
40
41 protected:
42
43 Address as_Address(AddressLiteral adr);
44 Address as_Address(ArrayAddress adr);
45
46 // Support for VM calls
47 //
48 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
49 // may customize this version by overriding it for its purposes (e.g., to save/restore
50 // additional registers when doing a VM call).
51
52 virtual void call_VM_leaf_base(
53 address entry_point, // the entry point
54 int number_of_arguments // the number of arguments to pop after the call
55 );
56
57 // This is the base routine called by the different versions of call_VM. The interpreter
58 // may customize this version by overriding it for its purposes (e.g., to save/restore
59 // additional registers when doing a VM call).
60 //
61 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
62 // returns the register which contains the thread upon return. If a thread register has been
63 // specified, the return value will correspond to that register. If no last_java_sp is specified
64 // (noreg) than rsp will be used instead.
65 virtual void call_VM_base( // returns the register containing the thread upon return
66 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
67 Register java_thread, // the thread if computed before ; use noreg otherwise
68 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
69 address entry_point, // the entry point
70 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
71 bool check_exceptions // whether to check for pending exceptions after return
72 );
73
74 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
75 // The implementation is only non-empty for the InterpreterMacroAssembler,
76 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
77 virtual void check_and_handle_popframe(Register java_thread);
78 virtual void check_and_handle_earlyret(Register java_thread);
79
80 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
81
82 // helpers for FPU flag access
83 // tmp is a temporary register, if none is available use noreg
84 void save_rax (Register tmp);
85 void restore_rax(Register tmp);
86
87 public:
88 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
89
90 // Support for NULL-checks
91 //
92 // Generates code that causes a NULL OS exception if the content of reg is NULL.
93 // If the accessed location is M[reg + offset] and the offset is known, provide the
94 // offset. No explicit code generation is needed if the offset is within a certain
95 // range (0 <= offset <= page_size).
96
97 void null_check(Register reg, int offset = -1);
98 static bool needs_explicit_null_check(intptr_t offset);
99
100 // Required platform-specific helpers for Label::patch_instructions.
101 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
102 void pd_patch_instruction(address branch, address target) {
103 unsigned char op = branch[0];
104 assert(op == 0xE8 /* call */ ||
105 op == 0xE9 /* jmp */ ||
106 op == 0xEB /* short jmp */ ||
107 (op & 0xF0) == 0x70 /* short jcc */ ||
108 op == 0x0F && (branch[1] & 0xF0) == 0x80 /* jcc */ ||
109 op == 0xC7 && branch[1] == 0xF8 /* xbegin */,
110 "Invalid opcode at patch point");
111
112 if (op == 0xEB || (op & 0xF0) == 0x70) {
113 // short offset operators (jmp and jcc)
114 char* disp = (char*) &branch[1];
115 int imm8 = target - (address) &disp[1];
116 guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset");
117 *disp = imm8;
118 } else {
119 int* disp = (int*) &branch[(op == 0x0F || op == 0xC7)? 2: 1];
120 int imm32 = target - (address) &disp[1];
121 *disp = imm32;
122 }
123 }
124
125 // The following 4 methods return the offset of the appropriate move instruction
126
127 // Support for fast byte/short loading with zero extension (depending on particular CPU)
128 int load_unsigned_byte(Register dst, Address src);
129 int load_unsigned_short(Register dst, Address src);
130
131 // Support for fast byte/short loading with sign extension (depending on particular CPU)
132 int load_signed_byte(Register dst, Address src);
133 int load_signed_short(Register dst, Address src);
134
135 // Support for sign-extension (hi:lo = extend_sign(lo))
136 void extend_sign(Register hi, Register lo);
137
138 // Load and store values by size and signed-ness
139 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
140 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
141
142 // Support for inc/dec with optimal instruction selection depending on value
143
144 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
145 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
146
147 void decrementl(Address dst, int value = 1);
148 void decrementl(Register reg, int value = 1);
149
150 void decrementq(Register reg, int value = 1);
151 void decrementq(Address dst, int value = 1);
152
153 void incrementl(Address dst, int value = 1);
154 void incrementl(Register reg, int value = 1);
155
156 void incrementq(Register reg, int value = 1);
157 void incrementq(Address dst, int value = 1);
158
159 // special instructions for EVEX
160 void setvectmask(Register dst, Register src);
161 void restorevectmask();
162
163 // Support optimal SSE move instructions.
164 void movflt(XMMRegister dst, XMMRegister src) {
165 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
166 else { movss (dst, src); return; }
167 }
168 void movflt(XMMRegister dst, Address src) { movss(dst, src); }
169 void movflt(XMMRegister dst, AddressLiteral src);
170 void movflt(Address dst, XMMRegister src) { movss(dst, src); }
171
172 void movdbl(XMMRegister dst, XMMRegister src) {
173 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
174 else { movsd (dst, src); return; }
175 }
176
177 void movdbl(XMMRegister dst, AddressLiteral src);
178
179 void movdbl(XMMRegister dst, Address src) {
180 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
181 else { movlpd(dst, src); return; }
182 }
183 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
184
185 void incrementl(AddressLiteral dst);
186 void incrementl(ArrayAddress dst);
187
188 void incrementq(AddressLiteral dst);
189
190 // Alignment
191 void align(int modulus);
192 void align(int modulus, int target);
193
194 // A 5 byte nop that is safe for patching (see patch_verified_entry)
195 void fat_nop();
196
197 // Stack frame creation/removal
198 void enter();
199 void leave();
200
201 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
202 // The pointer will be loaded into the thread register.
203 void get_thread(Register thread);
204
205
206 // Support for VM calls
207 //
208 // It is imperative that all calls into the VM are handled via the call_VM macros.
209 // They make sure that the stack linkage is setup correctly. call_VM's correspond
210 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
211
212
213 void call_VM(Register oop_result,
214 address entry_point,
215 bool check_exceptions = true);
216 void call_VM(Register oop_result,
217 address entry_point,
218 Register arg_1,
219 bool check_exceptions = true);
220 void call_VM(Register oop_result,
221 address entry_point,
222 Register arg_1, Register arg_2,
223 bool check_exceptions = true);
224 void call_VM(Register oop_result,
225 address entry_point,
226 Register arg_1, Register arg_2, Register arg_3,
227 bool check_exceptions = true);
228
229 // Overloadings with last_Java_sp
230 void call_VM(Register oop_result,
231 Register last_java_sp,
232 address entry_point,
233 int number_of_arguments = 0,
234 bool check_exceptions = true);
235 void call_VM(Register oop_result,
236 Register last_java_sp,
237 address entry_point,
238 Register arg_1, bool
239 check_exceptions = true);
240 void call_VM(Register oop_result,
241 Register last_java_sp,
242 address entry_point,
243 Register arg_1, Register arg_2,
244 bool check_exceptions = true);
245 void call_VM(Register oop_result,
246 Register last_java_sp,
247 address entry_point,
248 Register arg_1, Register arg_2, Register arg_3,
249 bool check_exceptions = true);
250
251 void get_vm_result (Register oop_result, Register thread);
252 void get_vm_result_2(Register metadata_result, Register thread);
253
254 // These always tightly bind to MacroAssembler::call_VM_base
255 // bypassing the virtual implementation
256 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
257 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
258 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
259 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
260 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
261
262 void call_VM_leaf(address entry_point,
263 int number_of_arguments = 0);
264 void call_VM_leaf(address entry_point,
265 Register arg_1);
266 void call_VM_leaf(address entry_point,
267 Register arg_1, Register arg_2);
268 void call_VM_leaf(address entry_point,
269 Register arg_1, Register arg_2, Register arg_3);
270
271 // These always tightly bind to MacroAssembler::call_VM_leaf_base
272 // bypassing the virtual implementation
273 void super_call_VM_leaf(address entry_point);
274 void super_call_VM_leaf(address entry_point, Register arg_1);
275 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
276 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
277 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
278
279 // last Java Frame (fills frame anchor)
280 void set_last_Java_frame(Register thread,
281 Register last_java_sp,
282 Register last_java_fp,
283 address last_java_pc);
284
285 // thread in the default location (r15_thread on 64bit)
286 void set_last_Java_frame(Register last_java_sp,
287 Register last_java_fp,
288 address last_java_pc);
289
290 void reset_last_Java_frame(Register thread, bool clear_fp, bool clear_pc);
291
292 // thread in the default location (r15_thread on 64bit)
293 void reset_last_Java_frame(bool clear_fp, bool clear_pc);
294
295 // Stores
296 void store_check(Register obj); // store check for obj - register is destroyed afterwards
297 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
298
299 #if INCLUDE_ALL_GCS
300
301 void g1_write_barrier_pre(Register obj,
302 Register pre_val,
303 Register thread,
304 Register tmp,
305 bool tosca_live,
306 bool expand_call);
307
308 void g1_write_barrier_post(Register store_addr,
309 Register new_val,
310 Register thread,
311 Register tmp,
312 Register tmp2);
313
314 #endif // INCLUDE_ALL_GCS
315
316 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
317 void c2bool(Register x);
318
319 // C++ bool manipulation
320
321 void movbool(Register dst, Address src);
322 void movbool(Address dst, bool boolconst);
323 void movbool(Address dst, Register src);
324 void testbool(Register dst);
325
326 void load_mirror(Register mirror, Register method);
327
328 // oop manipulations
329 void load_klass(Register dst, Register src);
330 void store_klass(Register dst, Register src);
331
332 void load_heap_oop(Register dst, Address src);
333 void load_heap_oop_not_null(Register dst, Address src);
334 void store_heap_oop(Address dst, Register src);
335 void cmp_heap_oop(Register src1, Address src2, Register tmp = noreg);
336
337 // Used for storing NULL. All other oop constants should be
338 // stored using routines that take a jobject.
339 void store_heap_oop_null(Address dst);
340
341 void load_prototype_header(Register dst, Register src);
342
343 #ifdef _LP64
344 void store_klass_gap(Register dst, Register src);
345
346 // This dummy is to prevent a call to store_heap_oop from
347 // converting a zero (like NULL) into a Register by giving
348 // the compiler two choices it can't resolve
349
350 void store_heap_oop(Address dst, void* dummy);
351
352 void encode_heap_oop(Register r);
353 void decode_heap_oop(Register r);
354 void encode_heap_oop_not_null(Register r);
355 void decode_heap_oop_not_null(Register r);
356 void encode_heap_oop_not_null(Register dst, Register src);
357 void decode_heap_oop_not_null(Register dst, Register src);
358
359 void set_narrow_oop(Register dst, jobject obj);
360 void set_narrow_oop(Address dst, jobject obj);
361 void cmp_narrow_oop(Register dst, jobject obj);
362 void cmp_narrow_oop(Address dst, jobject obj);
363
364 void encode_klass_not_null(Register r);
365 void decode_klass_not_null(Register r);
366 void encode_klass_not_null(Register dst, Register src);
367 void decode_klass_not_null(Register dst, Register src);
368 void set_narrow_klass(Register dst, Klass* k);
369 void set_narrow_klass(Address dst, Klass* k);
370 void cmp_narrow_klass(Register dst, Klass* k);
371 void cmp_narrow_klass(Address dst, Klass* k);
372
373 // Returns the byte size of the instructions generated by decode_klass_not_null()
374 // when compressed klass pointers are being used.
375 static int instr_size_for_decode_klass_not_null();
376
377 // if heap base register is used - reinit it with the correct value
378 void reinit_heapbase();
379
380 DEBUG_ONLY(void verify_heapbase(const char* msg);)
381
382 #endif // _LP64
383
384 // Int division/remainder for Java
385 // (as idivl, but checks for special case as described in JVM spec.)
386 // returns idivl instruction offset for implicit exception handling
387 int corrected_idivl(Register reg);
388
389 // Long division/remainder for Java
390 // (as idivq, but checks for special case as described in JVM spec.)
391 // returns idivq instruction offset for implicit exception handling
392 int corrected_idivq(Register reg);
393
394 void int3();
395
396 // Long operation macros for a 32bit cpu
397 // Long negation for Java
398 void lneg(Register hi, Register lo);
399
400 // Long multiplication for Java
401 // (destroys contents of eax, ebx, ecx and edx)
402 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
403
404 // Long shifts for Java
405 // (semantics as described in JVM spec.)
406 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f)
407 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f)
408
409 // Long compare for Java
410 // (semantics as described in JVM spec.)
411 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
412
413
414 // misc
415
416 // Sign extension
417 void sign_extend_short(Register reg);
418 void sign_extend_byte(Register reg);
419
420 // Division by power of 2, rounding towards 0
421 void division_with_shift(Register reg, int shift_value);
422
423 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
424 //
425 // CF (corresponds to C0) if x < y
426 // PF (corresponds to C2) if unordered
427 // ZF (corresponds to C3) if x = y
428 //
429 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
430 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
431 void fcmp(Register tmp);
432 // Variant of the above which allows y to be further down the stack
433 // and which only pops x and y if specified. If pop_right is
434 // specified then pop_left must also be specified.
435 void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
436
437 // Floating-point comparison for Java
438 // Compares the top-most stack entries on the FPU stack and stores the result in dst.
439 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
440 // (semantics as described in JVM spec.)
441 void fcmp2int(Register dst, bool unordered_is_less);
442 // Variant of the above which allows y to be further down the stack
443 // and which only pops x and y if specified. If pop_right is
444 // specified then pop_left must also be specified.
445 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
446
447 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
448 // tmp is a temporary register, if none is available use noreg
449 void fremr(Register tmp);
450
451
452 // same as fcmp2int, but using SSE2
453 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
454 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
455
456 // Inlined sin/cos generator for Java; must not use CPU instruction
457 // directly on Intel as it does not have high enough precision
458 // outside of the range [-pi/4, pi/4]. Extra argument indicate the
459 // number of FPU stack slots in use; all but the topmost will
460 // require saving if a slow case is necessary. Assumes argument is
461 // on FP TOS; result is on FP TOS. No cpu registers are changed by
462 // this code.
463 void trigfunc(char trig, int num_fpu_regs_in_use = 1);
464
465 // branch to L if FPU flag C2 is set/not set
466 // tmp is a temporary register, if none is available use noreg
467 void jC2 (Register tmp, Label& L);
468 void jnC2(Register tmp, Label& L);
469
470 // Pop ST (ffree & fincstp combined)
471 void fpop();
472
473 // Load float value from 'address'. If UseSSE >= 1, the value is loaded into
474 // register xmm0. Otherwise, the value is loaded onto the FPU stack.
475 void load_float(Address src);
476
477 // Store float value to 'address'. If UseSSE >= 1, the value is stored
478 // from register xmm0. Otherwise, the value is stored from the FPU stack.
479 void store_float(Address dst);
480
481 // Load double value from 'address'. If UseSSE >= 2, the value is loaded into
482 // register xmm0. Otherwise, the value is loaded onto the FPU stack.
483 void load_double(Address src);
484
485 // Store double value to 'address'. If UseSSE >= 2, the value is stored
486 // from register xmm0. Otherwise, the value is stored from the FPU stack.
487 void store_double(Address dst);
488
489 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
490 void push_fTOS();
491
492 // pops double TOS element from CPU stack and pushes on FPU stack
493 void pop_fTOS();
494
495 void empty_FPU_stack();
496
497 void push_IU_state();
498 void pop_IU_state();
499
500 void push_FPU_state();
501 void pop_FPU_state();
502
503 void push_CPU_state();
504 void pop_CPU_state();
505
506 // Round up to a power of two
507 void round_to(Register reg, int modulus);
508
509 // Callee saved registers handling
510 void push_callee_saved_registers();
511 void pop_callee_saved_registers();
512
513 // allocation
514 void eden_allocate(
515 Register obj, // result: pointer to object after successful allocation
516 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
517 int con_size_in_bytes, // object size in bytes if known at compile time
518 Register t1, // temp register
519 Label& slow_case // continuation point if fast allocation fails
520 );
521 void tlab_allocate(
522 Register obj, // result: pointer to object after successful allocation
523 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
524 int con_size_in_bytes, // object size in bytes if known at compile time
525 Register t1, // temp register
526 Register t2, // temp register
527 Label& slow_case // continuation point if fast allocation fails
528 );
529 Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address
530 void zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp);
531
532 void incr_allocated_bytes(Register thread,
533 Register var_size_in_bytes, int con_size_in_bytes,
534 Register t1 = noreg);
535
536 // interface method calling
537 void lookup_interface_method(Register recv_klass,
538 Register intf_klass,
539 RegisterOrConstant itable_index,
540 Register method_result,
541 Register scan_temp,
542 Label& no_such_interface);
543
544 // virtual method calling
545 void lookup_virtual_method(Register recv_klass,
546 RegisterOrConstant vtable_index,
547 Register method_result);
548
549 // Test sub_klass against super_klass, with fast and slow paths.
550
551 // The fast path produces a tri-state answer: yes / no / maybe-slow.
552 // One of the three labels can be NULL, meaning take the fall-through.
553 // If super_check_offset is -1, the value is loaded up from super_klass.
554 // No registers are killed, except temp_reg.
555 void check_klass_subtype_fast_path(Register sub_klass,
556 Register super_klass,
557 Register temp_reg,
558 Label* L_success,
559 Label* L_failure,
560 Label* L_slow_path,
561 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
562
563 // The rest of the type check; must be wired to a corresponding fast path.
564 // It does not repeat the fast path logic, so don't use it standalone.
565 // The temp_reg and temp2_reg can be noreg, if no temps are available.
566 // Updates the sub's secondary super cache as necessary.
567 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
568 void check_klass_subtype_slow_path(Register sub_klass,
569 Register super_klass,
570 Register temp_reg,
571 Register temp2_reg,
572 Label* L_success,
573 Label* L_failure,
574 bool set_cond_codes = false);
575
576 // Simplified, combined version, good for typical uses.
577 // Falls through on failure.
578 void check_klass_subtype(Register sub_klass,
579 Register super_klass,
580 Register temp_reg,
581 Label& L_success);
582
583 // method handles (JSR 292)
584 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
585
586 //----
587 void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
588
589 // Debugging
590
591 // only if +VerifyOops
592 // TODO: Make these macros with file and line like sparc version!
593 void verify_oop(Register reg, const char* s = "broken oop");
594 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
595
596 // TODO: verify method and klass metadata (compare against vptr?)
597 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
598 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
599
600 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
601 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
602
603 // only if +VerifyFPU
604 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
605
606 // Verify or restore cpu control state after JNI call
607 void restore_cpu_control_state_after_jni();
608
609 // prints msg, dumps registers and stops execution
610 void stop(const char* msg);
611
612 // prints msg and continues
613 void warn(const char* msg);
614
615 // dumps registers and other state
616 void print_state();
617
618 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
619 static void debug64(char* msg, int64_t pc, int64_t regs[]);
620 static void print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip);
621 static void print_state64(int64_t pc, int64_t regs[]);
622
623 void os_breakpoint();
624
625 void untested() { stop("untested"); }
626
627 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, 1024, "unimplemented: %s", what); stop(b); }
628
629 void should_not_reach_here() { stop("should not reach here"); }
630
631 void print_CPU_state();
632
633 // Stack overflow checking
634 void bang_stack_with_offset(int offset) {
635 // stack grows down, caller passes positive offset
636 assert(offset > 0, "must bang with negative offset");
637 movl(Address(rsp, (-offset)), rax);
638 }
639
640 // Writes to stack successive pages until offset reached to check for
641 // stack overflow + shadow pages. Also, clobbers tmp
642 void bang_stack_size(Register size, Register tmp);
643
644 // Check for reserved stack access in method being exited (for JIT)
645 void reserved_stack_check();
646
647 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
648 Register tmp,
649 int offset);
650
651 // Support for serializing memory accesses between threads
652 void serialize_memory(Register thread, Register tmp);
653
654 void verify_tlab();
655
656 // Biased locking support
657 // lock_reg and obj_reg must be loaded up with the appropriate values.
658 // swap_reg must be rax, and is killed.
659 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
660 // be killed; if not supplied, push/pop will be used internally to
661 // allocate a temporary (inefficient, avoid if possible).
662 // Optional slow case is for implementations (interpreter and C1) which branch to
663 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
664 // Returns offset of first potentially-faulting instruction for null
665 // check info (currently consumed only by C1). If
666 // swap_reg_contains_mark is true then returns -1 as it is assumed
667 // the calling code has already passed any potential faults.
668 int biased_locking_enter(Register lock_reg, Register obj_reg,
669 Register swap_reg, Register tmp_reg,
670 bool swap_reg_contains_mark,
671 Label& done, Label* slow_case = NULL,
672 BiasedLockingCounters* counters = NULL);
673 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
674 #ifdef COMPILER2
675 // Code used by cmpFastLock and cmpFastUnlock mach instructions in .ad file.
676 // See full desription in macroAssembler_x86.cpp.
677 void fast_lock(Register obj, Register box, Register tmp,
678 Register scr, Register cx1, Register cx2,
679 BiasedLockingCounters* counters,
680 RTMLockingCounters* rtm_counters,
681 RTMLockingCounters* stack_rtm_counters,
682 Metadata* method_data,
683 bool use_rtm, bool profile_rtm);
684 void fast_unlock(Register obj, Register box, Register tmp, bool use_rtm);
685 #if INCLUDE_RTM_OPT
686 void rtm_counters_update(Register abort_status, Register rtm_counters);
687 void branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel);
688 void rtm_abort_ratio_calculation(Register tmp, Register rtm_counters_reg,
689 RTMLockingCounters* rtm_counters,
690 Metadata* method_data);
691 void rtm_profiling(Register abort_status_Reg, Register rtm_counters_Reg,
692 RTMLockingCounters* rtm_counters, Metadata* method_data, bool profile_rtm);
693 void rtm_retry_lock_on_abort(Register retry_count, Register abort_status, Label& retryLabel);
694 void rtm_retry_lock_on_busy(Register retry_count, Register box, Register tmp, Register scr, Label& retryLabel);
695 void rtm_stack_locking(Register obj, Register tmp, Register scr,
696 Register retry_on_abort_count,
697 RTMLockingCounters* stack_rtm_counters,
698 Metadata* method_data, bool profile_rtm,
699 Label& DONE_LABEL, Label& IsInflated);
700 void rtm_inflated_locking(Register obj, Register box, Register tmp,
701 Register scr, Register retry_on_busy_count,
702 Register retry_on_abort_count,
703 RTMLockingCounters* rtm_counters,
704 Metadata* method_data, bool profile_rtm,
705 Label& DONE_LABEL);
706 #endif
707 #endif
708
709 Condition negate_condition(Condition cond);
710
711 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
712 // operands. In general the names are modified to avoid hiding the instruction in Assembler
713 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
714 // here in MacroAssembler. The major exception to this rule is call
715
716 // Arithmetics
717
718
719 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
720 void addptr(Address dst, Register src);
721
722 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
723 void addptr(Register dst, int32_t src);
724 void addptr(Register dst, Register src);
725 void addptr(Register dst, RegisterOrConstant src) {
726 if (src.is_constant()) addptr(dst, (int) src.as_constant());
727 else addptr(dst, src.as_register());
728 }
729
730 void andptr(Register dst, int32_t src);
731 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
732
733 void cmp8(AddressLiteral src1, int imm);
734
735 // renamed to drag out the casting of address to int32_t/intptr_t
736 void cmp32(Register src1, int32_t imm);
737
738 void cmp32(AddressLiteral src1, int32_t imm);
739 // compare reg - mem, or reg - &mem
740 void cmp32(Register src1, AddressLiteral src2);
741
742 void cmp32(Register src1, Address src2);
743
744 #ifndef _LP64
745 void cmpklass(Address dst, Metadata* obj);
746 void cmpklass(Register dst, Metadata* obj);
747 void cmpoop(Address dst, jobject obj);
748 void cmpoop(Register dst, jobject obj);
749 #endif // _LP64
750
751 // NOTE src2 must be the lval. This is NOT an mem-mem compare
752 void cmpptr(Address src1, AddressLiteral src2);
753
754 void cmpptr(Register src1, AddressLiteral src2);
755
756 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
757 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
758 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
759
760 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
761 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
762
763 // cmp64 to avoild hiding cmpq
764 void cmp64(Register src1, AddressLiteral src);
765
766 void cmpxchgptr(Register reg, Address adr);
767
768 void locked_cmpxchgptr(Register reg, AddressLiteral adr);
769
770
771 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
772 void imulptr(Register dst, Register src, int imm32) { LP64_ONLY(imulq(dst, src, imm32)) NOT_LP64(imull(dst, src, imm32)); }
773
774
775 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
776
777 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
778
779 void shlptr(Register dst, int32_t shift);
780 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
781
782 void shrptr(Register dst, int32_t shift);
783 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
784
785 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
786 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
787
788 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
789
790 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
791 void subptr(Register dst, int32_t src);
792 // Force generation of a 4 byte immediate value even if it fits into 8bit
793 void subptr_imm32(Register dst, int32_t src);
794 void subptr(Register dst, Register src);
795 void subptr(Register dst, RegisterOrConstant src) {
796 if (src.is_constant()) subptr(dst, (int) src.as_constant());
797 else subptr(dst, src.as_register());
798 }
799
800 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
801 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
802
803 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
804 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
805
806 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
807
808
809
810 // Helper functions for statistics gathering.
811 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
812 void cond_inc32(Condition cond, AddressLiteral counter_addr);
813 // Unconditional atomic increment.
814 void atomic_incl(Address counter_addr);
815 void atomic_incl(AddressLiteral counter_addr, Register scr = rscratch1);
816 #ifdef _LP64
817 void atomic_incq(Address counter_addr);
818 void atomic_incq(AddressLiteral counter_addr, Register scr = rscratch1);
819 #endif
820 void atomic_incptr(AddressLiteral counter_addr, Register scr = rscratch1) { LP64_ONLY(atomic_incq(counter_addr, scr)) NOT_LP64(atomic_incl(counter_addr, scr)) ; }
821 void atomic_incptr(Address counter_addr) { LP64_ONLY(atomic_incq(counter_addr)) NOT_LP64(atomic_incl(counter_addr)) ; }
822
823 void lea(Register dst, AddressLiteral adr);
824 void lea(Address dst, AddressLiteral adr);
825 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
826
827 void leal32(Register dst, Address src) { leal(dst, src); }
828
829 // Import other testl() methods from the parent class or else
830 // they will be hidden by the following overriding declaration.
831 using Assembler::testl;
832 void testl(Register dst, AddressLiteral src);
833
834 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
835 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
836 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
837 void orptr(Address dst, int32_t imm32) { LP64_ONLY(orq(dst, imm32)) NOT_LP64(orl(dst, imm32)); }
838
839 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
840 void testptr(Register src1, Register src2);
841
842 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
843 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
844
845 // Calls
846
847 void call(Label& L, relocInfo::relocType rtype);
848 void call(Register entry);
849
850 // NOTE: this call transfers to the effective address of entry NOT
851 // the address contained by entry. This is because this is more natural
852 // for jumps/calls.
853 void call(AddressLiteral entry);
854
855 // Emit the CompiledIC call idiom
856 void ic_call(address entry, jint method_index = 0);
857
858 // Jumps
859
860 // NOTE: these jumps tranfer to the effective address of dst NOT
861 // the address contained by dst. This is because this is more natural
862 // for jumps/calls.
863 void jump(AddressLiteral dst);
864 void jump_cc(Condition cc, AddressLiteral dst);
865
866 // 32bit can do a case table jump in one instruction but we no longer allow the base
867 // to be installed in the Address class. This jump will tranfers to the address
868 // contained in the location described by entry (not the address of entry)
869 void jump(ArrayAddress entry);
870
871 // Floating
872
873 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
874 void andpd(XMMRegister dst, AddressLiteral src);
875 void andpd(XMMRegister dst, XMMRegister src) { Assembler::andpd(dst, src); }
876
877 void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); }
878 void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); }
879 void andps(XMMRegister dst, AddressLiteral src);
880
881 void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); }
882 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
883 void comiss(XMMRegister dst, AddressLiteral src);
884
885 void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); }
886 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
887 void comisd(XMMRegister dst, AddressLiteral src);
888
889 void fadd_s(Address src) { Assembler::fadd_s(src); }
890 void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); }
891
892 void fldcw(Address src) { Assembler::fldcw(src); }
893 void fldcw(AddressLiteral src);
894
895 void fld_s(int index) { Assembler::fld_s(index); }
896 void fld_s(Address src) { Assembler::fld_s(src); }
897 void fld_s(AddressLiteral src);
898
899 void fld_d(Address src) { Assembler::fld_d(src); }
900 void fld_d(AddressLiteral src);
901
902 void fld_x(Address src) { Assembler::fld_x(src); }
903 void fld_x(AddressLiteral src);
904
905 void fmul_s(Address src) { Assembler::fmul_s(src); }
906 void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); }
907
908 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
909 void ldmxcsr(AddressLiteral src);
910
911 #ifdef _LP64
912 private:
913 void sha256_AVX2_one_round_compute(
914 Register reg_old_h,
915 Register reg_a,
916 Register reg_b,
917 Register reg_c,
918 Register reg_d,
919 Register reg_e,
920 Register reg_f,
921 Register reg_g,
922 Register reg_h,
923 int iter);
924 void sha256_AVX2_four_rounds_compute_first(int start);
925 void sha256_AVX2_four_rounds_compute_last(int start);
926 void sha256_AVX2_one_round_and_sched(
927 XMMRegister xmm_0, /* == ymm4 on 0, 1, 2, 3 iterations, then rotate 4 registers left on 4, 8, 12 iterations */
928 XMMRegister xmm_1, /* ymm5 */ /* full cycle is 16 iterations */
929 XMMRegister xmm_2, /* ymm6 */
930 XMMRegister xmm_3, /* ymm7 */
931 Register reg_a, /* == eax on 0 iteration, then rotate 8 register right on each next iteration */
932 Register reg_b, /* ebx */ /* full cycle is 8 iterations */
933 Register reg_c, /* edi */
934 Register reg_d, /* esi */
935 Register reg_e, /* r8d */
936 Register reg_f, /* r9d */
937 Register reg_g, /* r10d */
938 Register reg_h, /* r11d */
939 int iter);
940
941 void addm(int disp, Register r1, Register r2);
942
943 public:
944 void sha256_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
945 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
946 Register buf, Register state, Register ofs, Register limit, Register rsp,
947 bool multi_block, XMMRegister shuf_mask);
948 #endif
949
950 void fast_sha1(XMMRegister abcd, XMMRegister e0, XMMRegister e1, XMMRegister msg0,
951 XMMRegister msg1, XMMRegister msg2, XMMRegister msg3, XMMRegister shuf_mask,
952 Register buf, Register state, Register ofs, Register limit, Register rsp,
953 bool multi_block);
954
955 #ifdef _LP64
956 void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
957 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
958 Register buf, Register state, Register ofs, Register limit, Register rsp,
959 bool multi_block, XMMRegister shuf_mask);
960 #else
961 void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
962 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
963 Register buf, Register state, Register ofs, Register limit, Register rsp,
964 bool multi_block);
965 #endif
966
967 void fast_exp(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
968 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
969 Register rax, Register rcx, Register rdx, Register tmp);
970
971 #ifdef _LP64
972 void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
973 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
974 Register rax, Register rcx, Register rdx, Register tmp1, Register tmp2);
975
976 void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
977 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
978 Register rax, Register rcx, Register rdx, Register r11);
979
980 void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
981 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
982 Register rdx, Register tmp1, Register tmp2, Register tmp3, Register tmp4);
983
984 void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
985 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
986 Register rax, Register rbx, Register rcx, Register rdx, Register tmp1, Register tmp2,
987 Register tmp3, Register tmp4);
988
989 void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
990 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
991 Register rax, Register rcx, Register rdx, Register tmp1,
992 Register tmp2, Register tmp3, Register tmp4);
993 void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
994 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
995 Register rax, Register rcx, Register rdx, Register tmp1,
996 Register tmp2, Register tmp3, Register tmp4);
997 #else
998 void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
999 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1000 Register rax, Register rcx, Register rdx, Register tmp1);
1001
1002 void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1003 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1004 Register rax, Register rcx, Register rdx, Register tmp);
1005
1006 void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
1007 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
1008 Register rdx, Register tmp);
1009
1010 void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1011 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1012 Register rax, Register rbx, Register rdx);
1013
1014 void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1015 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1016 Register rax, Register rcx, Register rdx, Register tmp);
1017
1018 void libm_sincos_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1019 Register edx, Register ebx, Register esi, Register edi,
1020 Register ebp, Register esp);
1021
1022 void libm_reduce_pi04l(Register eax, Register ecx, Register edx, Register ebx,
1023 Register esi, Register edi, Register ebp, Register esp);
1024
1025 void libm_tancot_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1026 Register edx, Register ebx, Register esi, Register edi,
1027 Register ebp, Register esp);
1028
1029 void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1030 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1031 Register rax, Register rcx, Register rdx, Register tmp);
1032 #endif
1033
1034 void increase_precision();
1035 void restore_precision();
1036
1037 private:
1038
1039 // call runtime as a fallback for trig functions and pow/exp.
1040 void fp_runtime_fallback(address runtime_entry, int nb_args, int num_fpu_regs_in_use);
1041
1042 // these are private because users should be doing movflt/movdbl
1043
1044 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); }
1045 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
1046 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); }
1047 void movss(XMMRegister dst, AddressLiteral src);
1048
1049 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); }
1050 void movlpd(XMMRegister dst, AddressLiteral src);
1051
1052 public:
1053
1054 void addsd(XMMRegister dst, XMMRegister src) { Assembler::addsd(dst, src); }
1055 void addsd(XMMRegister dst, Address src) { Assembler::addsd(dst, src); }
1056 void addsd(XMMRegister dst, AddressLiteral src);
1057
1058 void addss(XMMRegister dst, XMMRegister src) { Assembler::addss(dst, src); }
1059 void addss(XMMRegister dst, Address src) { Assembler::addss(dst, src); }
1060 void addss(XMMRegister dst, AddressLiteral src);
1061
1062 void addpd(XMMRegister dst, XMMRegister src) { Assembler::addpd(dst, src); }
1063 void addpd(XMMRegister dst, Address src) { Assembler::addpd(dst, src); }
1064 void addpd(XMMRegister dst, AddressLiteral src);
1065
1066 void divsd(XMMRegister dst, XMMRegister src) { Assembler::divsd(dst, src); }
1067 void divsd(XMMRegister dst, Address src) { Assembler::divsd(dst, src); }
1068 void divsd(XMMRegister dst, AddressLiteral src);
1069
1070 void divss(XMMRegister dst, XMMRegister src) { Assembler::divss(dst, src); }
1071 void divss(XMMRegister dst, Address src) { Assembler::divss(dst, src); }
1072 void divss(XMMRegister dst, AddressLiteral src);
1073
1074 // Move Unaligned Double Quadword
1075 void movdqu(Address dst, XMMRegister src);
1076 void movdqu(XMMRegister dst, Address src);
1077 void movdqu(XMMRegister dst, XMMRegister src);
1078 void movdqu(XMMRegister dst, AddressLiteral src);
1079 // AVX Unaligned forms
1080 void vmovdqu(Address dst, XMMRegister src);
1081 void vmovdqu(XMMRegister dst, Address src);
1082 void vmovdqu(XMMRegister dst, XMMRegister src);
1083 void vmovdqu(XMMRegister dst, AddressLiteral src);
1084
1085 // Move Aligned Double Quadword
1086 void movdqa(XMMRegister dst, Address src) { Assembler::movdqa(dst, src); }
1087 void movdqa(XMMRegister dst, XMMRegister src) { Assembler::movdqa(dst, src); }
1088 void movdqa(XMMRegister dst, AddressLiteral src);
1089
1090 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
1091 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); }
1092 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); }
1093 void movsd(XMMRegister dst, AddressLiteral src);
1094
1095 void mulpd(XMMRegister dst, XMMRegister src) { Assembler::mulpd(dst, src); }
1096 void mulpd(XMMRegister dst, Address src) { Assembler::mulpd(dst, src); }
1097 void mulpd(XMMRegister dst, AddressLiteral src);
1098
1099 void mulsd(XMMRegister dst, XMMRegister src) { Assembler::mulsd(dst, src); }
1100 void mulsd(XMMRegister dst, Address src) { Assembler::mulsd(dst, src); }
1101 void mulsd(XMMRegister dst, AddressLiteral src);
1102
1103 void mulss(XMMRegister dst, XMMRegister src) { Assembler::mulss(dst, src); }
1104 void mulss(XMMRegister dst, Address src) { Assembler::mulss(dst, src); }
1105 void mulss(XMMRegister dst, AddressLiteral src);
1106
1107 // Carry-Less Multiplication Quadword
1108 void pclmulldq(XMMRegister dst, XMMRegister src) {
1109 // 0x00 - multiply lower 64 bits [0:63]
1110 Assembler::pclmulqdq(dst, src, 0x00);
1111 }
1112 void pclmulhdq(XMMRegister dst, XMMRegister src) {
1113 // 0x11 - multiply upper 64 bits [64:127]
1114 Assembler::pclmulqdq(dst, src, 0x11);
1115 }
1116
1117 void pcmpeqb(XMMRegister dst, XMMRegister src);
1118 void pcmpeqw(XMMRegister dst, XMMRegister src);
1119
1120 void pcmpestri(XMMRegister dst, Address src, int imm8);
1121 void pcmpestri(XMMRegister dst, XMMRegister src, int imm8);
1122
1123 void pmovzxbw(XMMRegister dst, XMMRegister src);
1124 void pmovzxbw(XMMRegister dst, Address src);
1125
1126 void pmovmskb(Register dst, XMMRegister src);
1127
1128 void ptest(XMMRegister dst, XMMRegister src);
1129
1130 void sqrtsd(XMMRegister dst, XMMRegister src) { Assembler::sqrtsd(dst, src); }
1131 void sqrtsd(XMMRegister dst, Address src) { Assembler::sqrtsd(dst, src); }
1132 void sqrtsd(XMMRegister dst, AddressLiteral src);
1133
1134 void sqrtss(XMMRegister dst, XMMRegister src) { Assembler::sqrtss(dst, src); }
1135 void sqrtss(XMMRegister dst, Address src) { Assembler::sqrtss(dst, src); }
1136 void sqrtss(XMMRegister dst, AddressLiteral src);
1137
1138 void subsd(XMMRegister dst, XMMRegister src) { Assembler::subsd(dst, src); }
1139 void subsd(XMMRegister dst, Address src) { Assembler::subsd(dst, src); }
1140 void subsd(XMMRegister dst, AddressLiteral src);
1141
1142 void subss(XMMRegister dst, XMMRegister src) { Assembler::subss(dst, src); }
1143 void subss(XMMRegister dst, Address src) { Assembler::subss(dst, src); }
1144 void subss(XMMRegister dst, AddressLiteral src);
1145
1146 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
1147 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); }
1148 void ucomiss(XMMRegister dst, AddressLiteral src);
1149
1150 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
1151 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); }
1152 void ucomisd(XMMRegister dst, AddressLiteral src);
1153
1154 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1155 void xorpd(XMMRegister dst, XMMRegister src);
1156 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); }
1157 void xorpd(XMMRegister dst, AddressLiteral src);
1158
1159 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1160 void xorps(XMMRegister dst, XMMRegister src);
1161 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); }
1162 void xorps(XMMRegister dst, AddressLiteral src);
1163
1164 // Shuffle Bytes
1165 void pshufb(XMMRegister dst, XMMRegister src) { Assembler::pshufb(dst, src); }
1166 void pshufb(XMMRegister dst, Address src) { Assembler::pshufb(dst, src); }
1167 void pshufb(XMMRegister dst, AddressLiteral src);
1168 // AVX 3-operands instructions
1169
1170 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); }
1171 void vaddsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddsd(dst, nds, src); }
1172 void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1173
1174 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); }
1175 void vaddss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddss(dst, nds, src); }
1176 void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1177
1178 void vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1179 void vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1180
1181 void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1182 void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1183
1184 void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1185 void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1186
1187 void vpbroadcastw(XMMRegister dst, XMMRegister src);
1188
1189 void vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1190 void vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1191
1192 void vpmovzxbw(XMMRegister dst, Address src, int vector_len);
1193 void vpmovmskb(Register dst, XMMRegister src);
1194
1195 void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1196 void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1197
1198 void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1199 void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1200
1201 void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1202 void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1203
1204 void vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1205 void vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1206
1207 void vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1208 void vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1209
1210 void vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1211 void vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1212
1213 void vptest(XMMRegister dst, XMMRegister src);
1214
1215 void punpcklbw(XMMRegister dst, XMMRegister src);
1216 void punpcklbw(XMMRegister dst, Address src) { Assembler::punpcklbw(dst, src); }
1217
1218 void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1219 void pshuflw(XMMRegister dst, Address src, int mode) { Assembler::pshuflw(dst, src, mode); }
1220
1221 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1222 void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1223 void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1224
1225 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1226 void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1227 void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1228
1229 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); }
1230 void vdivsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivsd(dst, nds, src); }
1231 void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1232
1233 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); }
1234 void vdivss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivss(dst, nds, src); }
1235 void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1236
1237 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); }
1238 void vmulsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulsd(dst, nds, src); }
1239 void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1240
1241 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); }
1242 void vmulss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulss(dst, nds, src); }
1243 void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1244
1245 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); }
1246 void vsubsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubsd(dst, nds, src); }
1247 void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1248
1249 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); }
1250 void vsubss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubss(dst, nds, src); }
1251 void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1252
1253 void vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1254 void vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1255
1256 // AVX Vector instructions
1257
1258 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1259 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1260 void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1261
1262 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1263 void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1264 void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1265
1266 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1267 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1268 Assembler::vpxor(dst, nds, src, vector_len);
1269 else
1270 Assembler::vxorpd(dst, nds, src, vector_len);
1271 }
1272 void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
1273 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1274 Assembler::vpxor(dst, nds, src, vector_len);
1275 else
1276 Assembler::vxorpd(dst, nds, src, vector_len);
1277 }
1278
1279 // Simple version for AVX2 256bit vectors
1280 void vpxor(XMMRegister dst, XMMRegister src) { Assembler::vpxor(dst, dst, src, true); }
1281 void vpxor(XMMRegister dst, Address src) { Assembler::vpxor(dst, dst, src, true); }
1282
1283 void vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
1284 if (UseAVX > 2) {
1285 Assembler::vinserti32x4(dst, dst, src, imm8);
1286 } else if (UseAVX > 1) {
1287 // vinserti128 is available only in AVX2
1288 Assembler::vinserti128(dst, nds, src, imm8);
1289 } else {
1290 Assembler::vinsertf128(dst, nds, src, imm8);
1291 }
1292 }
1293
1294 void vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
1295 if (UseAVX > 2) {
1296 Assembler::vinserti32x4(dst, dst, src, imm8);
1297 } else if (UseAVX > 1) {
1298 // vinserti128 is available only in AVX2
1299 Assembler::vinserti128(dst, nds, src, imm8);
1300 } else {
1301 Assembler::vinsertf128(dst, nds, src, imm8);
1302 }
1303 }
1304
1305 void vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
1306 if (UseAVX > 2) {
1307 Assembler::vextracti32x4(dst, src, imm8);
1308 } else if (UseAVX > 1) {
1309 // vextracti128 is available only in AVX2
1310 Assembler::vextracti128(dst, src, imm8);
1311 } else {
1312 Assembler::vextractf128(dst, src, imm8);
1313 }
1314 }
1315
1316 void vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
1317 if (UseAVX > 2) {
1318 Assembler::vextracti32x4(dst, src, imm8);
1319 } else if (UseAVX > 1) {
1320 // vextracti128 is available only in AVX2
1321 Assembler::vextracti128(dst, src, imm8);
1322 } else {
1323 Assembler::vextractf128(dst, src, imm8);
1324 }
1325 }
1326
1327 // 128bit copy to/from high 128 bits of 256bit (YMM) vector registers
1328 void vinserti128_high(XMMRegister dst, XMMRegister src) {
1329 vinserti128(dst, dst, src, 1);
1330 }
1331 void vinserti128_high(XMMRegister dst, Address src) {
1332 vinserti128(dst, dst, src, 1);
1333 }
1334 void vextracti128_high(XMMRegister dst, XMMRegister src) {
1335 vextracti128(dst, src, 1);
1336 }
1337 void vextracti128_high(Address dst, XMMRegister src) {
1338 vextracti128(dst, src, 1);
1339 }
1340
1341 void vinsertf128_high(XMMRegister dst, XMMRegister src) {
1342 if (UseAVX > 2) {
1343 Assembler::vinsertf32x4(dst, dst, src, 1);
1344 } else {
1345 Assembler::vinsertf128(dst, dst, src, 1);
1346 }
1347 }
1348
1349 void vinsertf128_high(XMMRegister dst, Address src) {
1350 if (UseAVX > 2) {
1351 Assembler::vinsertf32x4(dst, dst, src, 1);
1352 } else {
1353 Assembler::vinsertf128(dst, dst, src, 1);
1354 }
1355 }
1356
1357 void vextractf128_high(XMMRegister dst, XMMRegister src) {
1358 if (UseAVX > 2) {
1359 Assembler::vextractf32x4(dst, src, 1);
1360 } else {
1361 Assembler::vextractf128(dst, src, 1);
1362 }
1363 }
1364
1365 void vextractf128_high(Address dst, XMMRegister src) {
1366 if (UseAVX > 2) {
1367 Assembler::vextractf32x4(dst, src, 1);
1368 } else {
1369 Assembler::vextractf128(dst, src, 1);
1370 }
1371 }
1372
1373 // 256bit copy to/from high 256 bits of 512bit (ZMM) vector registers
1374 void vinserti64x4_high(XMMRegister dst, XMMRegister src) {
1375 Assembler::vinserti64x4(dst, dst, src, 1);
1376 }
1377 void vinsertf64x4_high(XMMRegister dst, XMMRegister src) {
1378 Assembler::vinsertf64x4(dst, dst, src, 1);
1379 }
1380 void vextracti64x4_high(XMMRegister dst, XMMRegister src) {
1381 Assembler::vextracti64x4(dst, src, 1);
1382 }
1383 void vextractf64x4_high(XMMRegister dst, XMMRegister src) {
1384 Assembler::vextractf64x4(dst, src, 1);
1385 }
1386 void vextractf64x4_high(Address dst, XMMRegister src) {
1387 Assembler::vextractf64x4(dst, src, 1);
1388 }
1389 void vinsertf64x4_high(XMMRegister dst, Address src) {
1390 Assembler::vinsertf64x4(dst, dst, src, 1);
1391 }
1392
1393 // 128bit copy to/from low 128 bits of 256bit (YMM) vector registers
1394 void vinserti128_low(XMMRegister dst, XMMRegister src) {
1395 vinserti128(dst, dst, src, 0);
1396 }
1397 void vinserti128_low(XMMRegister dst, Address src) {
1398 vinserti128(dst, dst, src, 0);
1399 }
1400 void vextracti128_low(XMMRegister dst, XMMRegister src) {
1401 vextracti128(dst, src, 0);
1402 }
1403 void vextracti128_low(Address dst, XMMRegister src) {
1404 vextracti128(dst, src, 0);
1405 }
1406
1407 void vinsertf128_low(XMMRegister dst, XMMRegister src) {
1408 if (UseAVX > 2) {
1409 Assembler::vinsertf32x4(dst, dst, src, 0);
1410 } else {
1411 Assembler::vinsertf128(dst, dst, src, 0);
1412 }
1413 }
1414
1415 void vinsertf128_low(XMMRegister dst, Address src) {
1416 if (UseAVX > 2) {
1417 Assembler::vinsertf32x4(dst, dst, src, 0);
1418 } else {
1419 Assembler::vinsertf128(dst, dst, src, 0);
1420 }
1421 }
1422
1423 void vextractf128_low(XMMRegister dst, XMMRegister src) {
1424 if (UseAVX > 2) {
1425 Assembler::vextractf32x4(dst, src, 0);
1426 } else {
1427 Assembler::vextractf128(dst, src, 0);
1428 }
1429 }
1430
1431 void vextractf128_low(Address dst, XMMRegister src) {
1432 if (UseAVX > 2) {
1433 Assembler::vextractf32x4(dst, src, 0);
1434 } else {
1435 Assembler::vextractf128(dst, src, 0);
1436 }
1437 }
1438
1439 // 256bit copy to/from low 256 bits of 512bit (ZMM) vector registers
1440 void vinserti64x4_low(XMMRegister dst, XMMRegister src) {
1441 Assembler::vinserti64x4(dst, dst, src, 0);
1442 }
1443 void vinsertf64x4_low(XMMRegister dst, XMMRegister src) {
1444 Assembler::vinsertf64x4(dst, dst, src, 0);
1445 }
1446 void vextracti64x4_low(XMMRegister dst, XMMRegister src) {
1447 Assembler::vextracti64x4(dst, src, 0);
1448 }
1449 void vextractf64x4_low(XMMRegister dst, XMMRegister src) {
1450 Assembler::vextractf64x4(dst, src, 0);
1451 }
1452 void vextractf64x4_low(Address dst, XMMRegister src) {
1453 Assembler::vextractf64x4(dst, src, 0);
1454 }
1455 void vinsertf64x4_low(XMMRegister dst, Address src) {
1456 Assembler::vinsertf64x4(dst, dst, src, 0);
1457 }
1458
1459 // Carry-Less Multiplication Quadword
1460 void vpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1461 // 0x00 - multiply lower 64 bits [0:63]
1462 Assembler::vpclmulqdq(dst, nds, src, 0x00);
1463 }
1464 void vpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1465 // 0x11 - multiply upper 64 bits [64:127]
1466 Assembler::vpclmulqdq(dst, nds, src, 0x11);
1467 }
1468
1469 // Data
1470
1471 void cmov32( Condition cc, Register dst, Address src);
1472 void cmov32( Condition cc, Register dst, Register src);
1473
1474 void cmov( Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); }
1475
1476 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1477 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1478
1479 void movoop(Register dst, jobject obj);
1480 void movoop(Address dst, jobject obj);
1481
1482 void mov_metadata(Register dst, Metadata* obj);
1483 void mov_metadata(Address dst, Metadata* obj);
1484
1485 void movptr(ArrayAddress dst, Register src);
1486 // can this do an lea?
1487 void movptr(Register dst, ArrayAddress src);
1488
1489 void movptr(Register dst, Address src);
1490
1491 #ifdef _LP64
1492 void movptr(Register dst, AddressLiteral src, Register scratch=rscratch1);
1493 #else
1494 void movptr(Register dst, AddressLiteral src, Register scratch=noreg); // Scratch reg is ignored in 32-bit
1495 #endif
1496
1497 void movptr(Register dst, intptr_t src);
1498 void movptr(Register dst, Register src);
1499 void movptr(Address dst, intptr_t src);
1500
1501 void movptr(Address dst, Register src);
1502
1503 void movptr(Register dst, RegisterOrConstant src) {
1504 if (src.is_constant()) movptr(dst, src.as_constant());
1505 else movptr(dst, src.as_register());
1506 }
1507
1508 #ifdef _LP64
1509 // Generally the next two are only used for moving NULL
1510 // Although there are situations in initializing the mark word where
1511 // they could be used. They are dangerous.
1512
1513 // They only exist on LP64 so that int32_t and intptr_t are not the same
1514 // and we have ambiguous declarations.
1515
1516 void movptr(Address dst, int32_t imm32);
1517 void movptr(Register dst, int32_t imm32);
1518 #endif // _LP64
1519
1520 // to avoid hiding movl
1521 void mov32(AddressLiteral dst, Register src);
1522 void mov32(Register dst, AddressLiteral src);
1523
1524 // to avoid hiding movb
1525 void movbyte(ArrayAddress dst, int src);
1526
1527 // Import other mov() methods from the parent class or else
1528 // they will be hidden by the following overriding declaration.
1529 using Assembler::movdl;
1530 using Assembler::movq;
1531 void movdl(XMMRegister dst, AddressLiteral src);
1532 void movq(XMMRegister dst, AddressLiteral src);
1533
1534 // Can push value or effective address
1535 void pushptr(AddressLiteral src);
1536
1537 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
1538 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
1539
1540 void pushoop(jobject obj);
1541 void pushklass(Metadata* obj);
1542
1543 // sign extend as need a l to ptr sized element
1544 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
1545 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
1546
1547 // C2 compiled method's prolog code.
1548 void verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b);
1549
1550 // clear memory of size 'cnt' qwords, starting at 'base';
1551 // if 'is_large' is set, do not try to produce short loop
1552 void clear_mem(Register base, Register cnt, Register rtmp, bool is_large);
1553
1554 #ifdef COMPILER2
1555 void string_indexof_char(Register str1, Register cnt1, Register ch, Register result,
1556 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp);
1557
1558 // IndexOf strings.
1559 // Small strings are loaded through stack if they cross page boundary.
1560 void string_indexof(Register str1, Register str2,
1561 Register cnt1, Register cnt2,
1562 int int_cnt2, Register result,
1563 XMMRegister vec, Register tmp,
1564 int ae);
1565
1566 // IndexOf for constant substrings with size >= 8 elements
1567 // which don't need to be loaded through stack.
1568 void string_indexofC8(Register str1, Register str2,
1569 Register cnt1, Register cnt2,
1570 int int_cnt2, Register result,
1571 XMMRegister vec, Register tmp,
1572 int ae);
1573
1574 // Smallest code: we don't need to load through stack,
1575 // check string tail.
1576
1577 // helper function for string_compare
1578 void load_next_elements(Register elem1, Register elem2, Register str1, Register str2,
1579 Address::ScaleFactor scale, Address::ScaleFactor scale1,
1580 Address::ScaleFactor scale2, Register index, int ae);
1581 // Compare strings.
1582 void string_compare(Register str1, Register str2,
1583 Register cnt1, Register cnt2, Register result,
1584 XMMRegister vec1, int ae);
1585
1586 // Search for Non-ASCII character (Negative byte value) in a byte array,
1587 // return true if it has any and false otherwise.
1588 void has_negatives(Register ary1, Register len,
1589 Register result, Register tmp1,
1590 XMMRegister vec1, XMMRegister vec2);
1591
1592 // Compare char[] or byte[] arrays.
1593 void arrays_equals(bool is_array_equ, Register ary1, Register ary2,
1594 Register limit, Register result, Register chr,
1595 XMMRegister vec1, XMMRegister vec2, bool is_char);
1596
1597 #endif
1598
1599 // Fill primitive arrays
1600 void generate_fill(BasicType t, bool aligned,
1601 Register to, Register value, Register count,
1602 Register rtmp, XMMRegister xtmp);
1603
1604 void encode_iso_array(Register src, Register dst, Register len,
1605 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1606 XMMRegister tmp4, Register tmp5, Register result);
1607
1608 #ifdef _LP64
1609 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2);
1610 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1611 Register y, Register y_idx, Register z,
1612 Register carry, Register product,
1613 Register idx, Register kdx);
1614 void multiply_add_128_x_128(Register x_xstart, Register y, Register z,
1615 Register yz_idx, Register idx,
1616 Register carry, Register product, int offset);
1617 void multiply_128_x_128_bmi2_loop(Register y, Register z,
1618 Register carry, Register carry2,
1619 Register idx, Register jdx,
1620 Register yz_idx1, Register yz_idx2,
1621 Register tmp, Register tmp3, Register tmp4);
1622 void multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
1623 Register yz_idx, Register idx, Register jdx,
1624 Register carry, Register product,
1625 Register carry2);
1626 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
1627 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5);
1628 void square_rshift(Register x, Register len, Register z, Register tmp1, Register tmp3,
1629 Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1630 void multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry,
1631 Register tmp2);
1632 void multiply_add_64(Register sum, Register op1, Register op2, Register carry,
1633 Register rdxReg, Register raxReg);
1634 void add_one_64(Register z, Register zlen, Register carry, Register tmp1);
1635 void lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1636 Register tmp3, Register tmp4);
1637 void square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1638 Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1639
1640 void mul_add_128_x_32_loop(Register out, Register in, Register offset, Register len, Register tmp1,
1641 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1642 Register raxReg);
1643 void mul_add(Register out, Register in, Register offset, Register len, Register k, Register tmp1,
1644 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1645 Register raxReg);
1646 void vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
1647 Register result, Register tmp1, Register tmp2,
1648 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3);
1649 #endif
1650
1651 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1652 void update_byte_crc32(Register crc, Register val, Register table);
1653 void kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp);
1654 // CRC32C code for java.util.zip.CRC32C::updateBytes() intrinsic
1655 // Note on a naming convention:
1656 // Prefix w = register only used on a Westmere+ architecture
1657 // Prefix n = register only used on a Nehalem architecture
1658 #ifdef _LP64
1659 void crc32c_ipl_alg4(Register in_out, uint32_t n,
1660 Register tmp1, Register tmp2, Register tmp3);
1661 #else
1662 void crc32c_ipl_alg4(Register in_out, uint32_t n,
1663 Register tmp1, Register tmp2, Register tmp3,
1664 XMMRegister xtmp1, XMMRegister xtmp2);
1665 #endif
1666 void crc32c_pclmulqdq(XMMRegister w_xtmp1,
1667 Register in_out,
1668 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
1669 XMMRegister w_xtmp2,
1670 Register tmp1,
1671 Register n_tmp2, Register n_tmp3);
1672 void crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
1673 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1674 Register tmp1, Register tmp2,
1675 Register n_tmp3);
1676 void crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
1677 Register in_out1, Register in_out2, Register in_out3,
1678 Register tmp1, Register tmp2, Register tmp3,
1679 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1680 Register tmp4, Register tmp5,
1681 Register n_tmp6);
1682 void crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
1683 Register tmp1, Register tmp2, Register tmp3,
1684 Register tmp4, Register tmp5, Register tmp6,
1685 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1686 bool is_pclmulqdq_supported);
1687 // Fold 128-bit data chunk
1688 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
1689 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf);
1690 // Fold 8-bit data
1691 void fold_8bit_crc32(Register crc, Register table, Register tmp);
1692 void fold_8bit_crc32(XMMRegister crc, Register table, XMMRegister xtmp, Register tmp);
1693
1694 // Compress char[] array to byte[].
1695 void char_array_compress(Register src, Register dst, Register len,
1696 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1697 XMMRegister tmp4, Register tmp5, Register result);
1698
1699 // Inflate byte[] array to char[].
1700 void byte_array_inflate(Register src, Register dst, Register len,
1701 XMMRegister tmp1, Register tmp2);
1702
1703 };
1704
1705 /**
1706 * class SkipIfEqual:
1707 *
1708 * Instantiating this class will result in assembly code being output that will
1709 * jump around any code emitted between the creation of the instance and it's
1710 * automatic destruction at the end of a scope block, depending on the value of
1711 * the flag passed to the constructor, which will be checked at run-time.
1712 */
1713 class SkipIfEqual {
1714 private:
1715 MacroAssembler* _masm;
1716 Label _label;
1717
1718 public:
1719 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1720 ~SkipIfEqual();
1721 };
1722
1723 #endif // CPU_X86_VM_MACROASSEMBLER_X86_HPP