1 /*
2 * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "gc/shared/cardTableModRefBS.hpp"
29 #include "gc/shared/collectedHeap.inline.hpp"
30 #include "interpreter/interpreter.hpp"
31 #include "memory/resourceArea.hpp"
32 #include "prims/methodHandles.hpp"
33 #include "runtime/biasedLocking.hpp"
34 #include "runtime/interfaceSupport.hpp"
35 #include "runtime/objectMonitor.hpp"
36 #include "runtime/os.hpp"
37 #include "runtime/sharedRuntime.hpp"
38 #include "runtime/stubRoutines.hpp"
39 #include "utilities/macros.hpp"
40 #if INCLUDE_ALL_GCS
41 #include "gc/g1/g1CollectedHeap.inline.hpp"
42 #include "gc/g1/g1SATBCardTableModRefBS.hpp"
43 #include "gc/g1/heapRegion.hpp"
44 #endif // INCLUDE_ALL_GCS
45
46 #ifdef PRODUCT
47 #define BLOCK_COMMENT(str) /* nothing */
48 #define STOP(error) stop(error)
49 #else
50 #define BLOCK_COMMENT(str) block_comment(str)
51 #define STOP(error) block_comment(error); stop(error)
52 #endif
53
54 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
55 // Implementation of AddressLiteral
56
57 // A 2-D table for managing compressed displacement(disp8) on EVEX enabled platforms.
58 unsigned char tuple_table[Assembler::EVEX_ETUP + 1][Assembler::AVX_512bit + 1] = {
59 // -----------------Table 4.5 -------------------- //
60 16, 32, 64, // EVEX_FV(0)
61 4, 4, 4, // EVEX_FV(1) - with Evex.b
62 16, 32, 64, // EVEX_FV(2) - with Evex.w
63 8, 8, 8, // EVEX_FV(3) - with Evex.w and Evex.b
64 8, 16, 32, // EVEX_HV(0)
65 4, 4, 4, // EVEX_HV(1) - with Evex.b
66 // -----------------Table 4.6 -------------------- //
67 16, 32, 64, // EVEX_FVM(0)
68 1, 1, 1, // EVEX_T1S(0)
69 2, 2, 2, // EVEX_T1S(1)
70 4, 4, 4, // EVEX_T1S(2)
71 8, 8, 8, // EVEX_T1S(3)
72 4, 4, 4, // EVEX_T1F(0)
73 8, 8, 8, // EVEX_T1F(1)
74 8, 8, 8, // EVEX_T2(0)
75 0, 16, 16, // EVEX_T2(1)
76 0, 16, 16, // EVEX_T4(0)
77 0, 0, 32, // EVEX_T4(1)
78 0, 0, 32, // EVEX_T8(0)
79 8, 16, 32, // EVEX_HVM(0)
80 4, 8, 16, // EVEX_QVM(0)
81 2, 4, 8, // EVEX_OVM(0)
82 16, 16, 16, // EVEX_M128(0)
83 8, 32, 64, // EVEX_DUP(0)
84 0, 0, 0 // EVEX_NTUP
85 };
86
87 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
88 _is_lval = false;
89 _target = target;
90 switch (rtype) {
91 case relocInfo::oop_type:
92 case relocInfo::metadata_type:
93 // Oops are a special case. Normally they would be their own section
94 // but in cases like icBuffer they are literals in the code stream that
95 // we don't have a section for. We use none so that we get a literal address
96 // which is always patchable.
97 break;
98 case relocInfo::external_word_type:
99 _rspec = external_word_Relocation::spec(target);
100 break;
101 case relocInfo::internal_word_type:
102 _rspec = internal_word_Relocation::spec(target);
103 break;
104 case relocInfo::opt_virtual_call_type:
105 _rspec = opt_virtual_call_Relocation::spec();
106 break;
107 case relocInfo::static_call_type:
108 _rspec = static_call_Relocation::spec();
109 break;
110 case relocInfo::runtime_call_type:
111 _rspec = runtime_call_Relocation::spec();
112 break;
113 case relocInfo::poll_type:
114 case relocInfo::poll_return_type:
115 _rspec = Relocation::spec_simple(rtype);
116 break;
117 case relocInfo::none:
118 break;
119 default:
120 ShouldNotReachHere();
121 break;
122 }
123 }
124
125 // Implementation of Address
126
127 #ifdef _LP64
128
129 Address Address::make_array(ArrayAddress adr) {
130 // Not implementable on 64bit machines
131 // Should have been handled higher up the call chain.
132 ShouldNotReachHere();
133 return Address();
134 }
135
136 // exceedingly dangerous constructor
137 Address::Address(int disp, address loc, relocInfo::relocType rtype) {
138 _base = noreg;
139 _index = noreg;
140 _scale = no_scale;
141 _disp = disp;
142 switch (rtype) {
143 case relocInfo::external_word_type:
144 _rspec = external_word_Relocation::spec(loc);
145 break;
146 case relocInfo::internal_word_type:
147 _rspec = internal_word_Relocation::spec(loc);
148 break;
149 case relocInfo::runtime_call_type:
150 // HMM
151 _rspec = runtime_call_Relocation::spec();
152 break;
153 case relocInfo::poll_type:
154 case relocInfo::poll_return_type:
155 _rspec = Relocation::spec_simple(rtype);
156 break;
157 case relocInfo::none:
158 break;
159 default:
160 ShouldNotReachHere();
161 }
162 }
163 #else // LP64
164
165 Address Address::make_array(ArrayAddress adr) {
166 AddressLiteral base = adr.base();
167 Address index = adr.index();
168 assert(index._disp == 0, "must not have disp"); // maybe it can?
169 Address array(index._base, index._index, index._scale, (intptr_t) base.target());
170 array._rspec = base._rspec;
171 return array;
172 }
173
174 // exceedingly dangerous constructor
175 Address::Address(address loc, RelocationHolder spec) {
176 _base = noreg;
177 _index = noreg;
178 _scale = no_scale;
179 _disp = (intptr_t) loc;
180 _rspec = spec;
181 }
182
183 #endif // _LP64
184
185
186
187 // Convert the raw encoding form into the form expected by the constructor for
188 // Address. An index of 4 (rsp) corresponds to having no index, so convert
189 // that to noreg for the Address constructor.
190 Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) {
191 RelocationHolder rspec;
192 if (disp_reloc != relocInfo::none) {
193 rspec = Relocation::spec_simple(disp_reloc);
194 }
195 bool valid_index = index != rsp->encoding();
196 if (valid_index) {
197 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));
198 madr._rspec = rspec;
199 return madr;
200 } else {
201 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));
202 madr._rspec = rspec;
203 return madr;
204 }
205 }
206
207 // Implementation of Assembler
208
209 int AbstractAssembler::code_fill_byte() {
210 return (u_char)'\xF4'; // hlt
211 }
212
213 // make this go away someday
214 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) {
215 if (rtype == relocInfo::none)
216 emit_int32(data);
217 else
218 emit_data(data, Relocation::spec_simple(rtype), format);
219 }
220
221 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) {
222 assert(imm_operand == 0, "default format must be immediate in this file");
223 assert(inst_mark() != NULL, "must be inside InstructionMark");
224 if (rspec.type() != relocInfo::none) {
225 #ifdef ASSERT
226 check_relocation(rspec, format);
227 #endif
228 // Do not use AbstractAssembler::relocate, which is not intended for
229 // embedded words. Instead, relocate to the enclosing instruction.
230
231 // hack. call32 is too wide for mask so use disp32
232 if (format == call32_operand)
233 code_section()->relocate(inst_mark(), rspec, disp32_operand);
234 else
235 code_section()->relocate(inst_mark(), rspec, format);
236 }
237 emit_int32(data);
238 }
239
240 static int encode(Register r) {
241 int enc = r->encoding();
242 if (enc >= 8) {
243 enc -= 8;
244 }
245 return enc;
246 }
247
248 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
249 assert(dst->has_byte_register(), "must have byte register");
250 assert(isByte(op1) && isByte(op2), "wrong opcode");
251 assert(isByte(imm8), "not a byte");
252 assert((op1 & 0x01) == 0, "should be 8bit operation");
253 emit_int8(op1);
254 emit_int8(op2 | encode(dst));
255 emit_int8(imm8);
256 }
257
258
259 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) {
260 assert(isByte(op1) && isByte(op2), "wrong opcode");
261 assert((op1 & 0x01) == 1, "should be 32bit operation");
262 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
263 if (is8bit(imm32)) {
264 emit_int8(op1 | 0x02); // set sign bit
265 emit_int8(op2 | encode(dst));
266 emit_int8(imm32 & 0xFF);
267 } else {
268 emit_int8(op1);
269 emit_int8(op2 | encode(dst));
270 emit_int32(imm32);
271 }
272 }
273
274 // Force generation of a 4 byte immediate value even if it fits into 8bit
275 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) {
276 assert(isByte(op1) && isByte(op2), "wrong opcode");
277 assert((op1 & 0x01) == 1, "should be 32bit operation");
278 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
279 emit_int8(op1);
280 emit_int8(op2 | encode(dst));
281 emit_int32(imm32);
282 }
283
284 // immediate-to-memory forms
285 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) {
286 assert((op1 & 0x01) == 1, "should be 32bit operation");
287 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
288 if (is8bit(imm32)) {
289 emit_int8(op1 | 0x02); // set sign bit
290 emit_operand(rm, adr, 1);
291 emit_int8(imm32 & 0xFF);
292 } else {
293 emit_int8(op1);
294 emit_operand(rm, adr, 4);
295 emit_int32(imm32);
296 }
297 }
298
299
300 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
301 assert(isByte(op1) && isByte(op2), "wrong opcode");
302 emit_int8(op1);
303 emit_int8(op2 | encode(dst) << 3 | encode(src));
304 }
305
306
307 bool Assembler::query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len,
308 int cur_tuple_type, int in_size_in_bits, int cur_encoding) {
309 int mod_idx = 0;
310 // We will test if the displacement fits the compressed format and if so
311 // apply the compression to the displacment iff the result is8bit.
312 if (VM_Version::supports_evex() && is_evex_inst) {
313 switch (cur_tuple_type) {
314 case EVEX_FV:
315 if ((cur_encoding & VEX_W) == VEX_W) {
316 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2;
317 } else {
318 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
319 }
320 break;
321
322 case EVEX_HV:
323 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
324 break;
325
326 case EVEX_FVM:
327 break;
328
329 case EVEX_T1S:
330 switch (in_size_in_bits) {
331 case EVEX_8bit:
332 break;
333
334 case EVEX_16bit:
335 mod_idx = 1;
336 break;
337
338 case EVEX_32bit:
339 mod_idx = 2;
340 break;
341
342 case EVEX_64bit:
343 mod_idx = 3;
344 break;
345 }
346 break;
347
348 case EVEX_T1F:
349 case EVEX_T2:
350 case EVEX_T4:
351 mod_idx = (in_size_in_bits == EVEX_64bit) ? 1 : 0;
352 break;
353
354 case EVEX_T8:
355 break;
356
357 case EVEX_HVM:
358 break;
359
360 case EVEX_QVM:
361 break;
362
363 case EVEX_OVM:
364 break;
365
366 case EVEX_M128:
367 break;
368
369 case EVEX_DUP:
370 break;
371
372 default:
373 assert(0, "no valid evex tuple_table entry");
374 break;
375 }
376
377 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
378 int disp_factor = tuple_table[cur_tuple_type + mod_idx][vector_len];
379 if ((disp % disp_factor) == 0) {
380 int new_disp = disp / disp_factor;
381 if ((-0x80 <= new_disp && new_disp < 0x80)) {
382 disp = new_disp;
383 }
384 } else {
385 return false;
386 }
387 }
388 }
389 return (-0x80 <= disp && disp < 0x80);
390 }
391
392
393 bool Assembler::emit_compressed_disp_byte(int &disp) {
394 int mod_idx = 0;
395 // We will test if the displacement fits the compressed format and if so
396 // apply the compression to the displacment iff the result is8bit.
397 if (VM_Version::supports_evex() && _attributes && _attributes->is_evex_instruction()) {
398 int evex_encoding = _attributes->get_evex_encoding();
399 int tuple_type = _attributes->get_tuple_type();
400 switch (tuple_type) {
401 case EVEX_FV:
402 if ((evex_encoding & VEX_W) == VEX_W) {
403 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2;
404 } else {
405 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
406 }
407 break;
408
409 case EVEX_HV:
410 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
411 break;
412
413 case EVEX_FVM:
414 break;
415
416 case EVEX_T1S:
417 switch (_attributes->get_input_size()) {
418 case EVEX_8bit:
419 break;
420
421 case EVEX_16bit:
422 mod_idx = 1;
423 break;
424
425 case EVEX_32bit:
426 mod_idx = 2;
427 break;
428
429 case EVEX_64bit:
430 mod_idx = 3;
431 break;
432 }
433 break;
434
435 case EVEX_T1F:
436 case EVEX_T2:
437 case EVEX_T4:
438 mod_idx = (_attributes->get_input_size() == EVEX_64bit) ? 1 : 0;
439 break;
440
441 case EVEX_T8:
442 break;
443
444 case EVEX_HVM:
445 break;
446
447 case EVEX_QVM:
448 break;
449
450 case EVEX_OVM:
451 break;
452
453 case EVEX_M128:
454 break;
455
456 case EVEX_DUP:
457 break;
458
459 default:
460 assert(0, "no valid evex tuple_table entry");
461 break;
462 }
463
464 int vector_len = _attributes->get_vector_len();
465 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
466 int disp_factor = tuple_table[tuple_type + mod_idx][vector_len];
467 if ((disp % disp_factor) == 0) {
468 int new_disp = disp / disp_factor;
469 if (is8bit(new_disp)) {
470 disp = new_disp;
471 }
472 } else {
473 return false;
474 }
475 }
476 }
477 return is8bit(disp);
478 }
479
480
481 void Assembler::emit_operand(Register reg, Register base, Register index,
482 Address::ScaleFactor scale, int disp,
483 RelocationHolder const& rspec,
484 int rip_relative_correction) {
485 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();
486
487 // Encode the registers as needed in the fields they are used in
488
489 int regenc = encode(reg) << 3;
490 int indexenc = index->is_valid() ? encode(index) << 3 : 0;
491 int baseenc = base->is_valid() ? encode(base) : 0;
492
493 if (base->is_valid()) {
494 if (index->is_valid()) {
495 assert(scale != Address::no_scale, "inconsistent address");
496 // [base + index*scale + disp]
497 if (disp == 0 && rtype == relocInfo::none &&
498 base != rbp LP64_ONLY(&& base != r13)) {
499 // [base + index*scale]
500 // [00 reg 100][ss index base]
501 assert(index != rsp, "illegal addressing mode");
502 emit_int8(0x04 | regenc);
503 emit_int8(scale << 6 | indexenc | baseenc);
504 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
505 // [base + index*scale + imm8]
506 // [01 reg 100][ss index base] imm8
507 assert(index != rsp, "illegal addressing mode");
508 emit_int8(0x44 | regenc);
509 emit_int8(scale << 6 | indexenc | baseenc);
510 emit_int8(disp & 0xFF);
511 } else {
512 // [base + index*scale + disp32]
513 // [10 reg 100][ss index base] disp32
514 assert(index != rsp, "illegal addressing mode");
515 emit_int8(0x84 | regenc);
516 emit_int8(scale << 6 | indexenc | baseenc);
517 emit_data(disp, rspec, disp32_operand);
518 }
519 } else if (base == rsp LP64_ONLY(|| base == r12)) {
520 // [rsp + disp]
521 if (disp == 0 && rtype == relocInfo::none) {
522 // [rsp]
523 // [00 reg 100][00 100 100]
524 emit_int8(0x04 | regenc);
525 emit_int8(0x24);
526 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
527 // [rsp + imm8]
528 // [01 reg 100][00 100 100] disp8
529 emit_int8(0x44 | regenc);
530 emit_int8(0x24);
531 emit_int8(disp & 0xFF);
532 } else {
533 // [rsp + imm32]
534 // [10 reg 100][00 100 100] disp32
535 emit_int8(0x84 | regenc);
536 emit_int8(0x24);
537 emit_data(disp, rspec, disp32_operand);
538 }
539 } else {
540 // [base + disp]
541 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode");
542 if (disp == 0 && rtype == relocInfo::none &&
543 base != rbp LP64_ONLY(&& base != r13)) {
544 // [base]
545 // [00 reg base]
546 emit_int8(0x00 | regenc | baseenc);
547 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
548 // [base + disp8]
549 // [01 reg base] disp8
550 emit_int8(0x40 | regenc | baseenc);
551 emit_int8(disp & 0xFF);
552 } else {
553 // [base + disp32]
554 // [10 reg base] disp32
555 emit_int8(0x80 | regenc | baseenc);
556 emit_data(disp, rspec, disp32_operand);
557 }
558 }
559 } else {
560 if (index->is_valid()) {
561 assert(scale != Address::no_scale, "inconsistent address");
562 // [index*scale + disp]
563 // [00 reg 100][ss index 101] disp32
564 assert(index != rsp, "illegal addressing mode");
565 emit_int8(0x04 | regenc);
566 emit_int8(scale << 6 | indexenc | 0x05);
567 emit_data(disp, rspec, disp32_operand);
568 } else if (rtype != relocInfo::none ) {
569 // [disp] (64bit) RIP-RELATIVE (32bit) abs
570 // [00 000 101] disp32
571
572 emit_int8(0x05 | regenc);
573 // Note that the RIP-rel. correction applies to the generated
574 // disp field, but _not_ to the target address in the rspec.
575
576 // disp was created by converting the target address minus the pc
577 // at the start of the instruction. That needs more correction here.
578 // intptr_t disp = target - next_ip;
579 assert(inst_mark() != NULL, "must be inside InstructionMark");
580 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction;
581 int64_t adjusted = disp;
582 // Do rip-rel adjustment for 64bit
583 LP64_ONLY(adjusted -= (next_ip - inst_mark()));
584 assert(is_simm32(adjusted),
585 "must be 32bit offset (RIP relative address)");
586 emit_data((int32_t) adjusted, rspec, disp32_operand);
587
588 } else {
589 // 32bit never did this, did everything as the rip-rel/disp code above
590 // [disp] ABSOLUTE
591 // [00 reg 100][00 100 101] disp32
592 emit_int8(0x04 | regenc);
593 emit_int8(0x25);
594 emit_data(disp, rspec, disp32_operand);
595 }
596 }
597 }
598
599 void Assembler::emit_operand(XMMRegister reg, Register base, Register index,
600 Address::ScaleFactor scale, int disp,
601 RelocationHolder const& rspec) {
602 if (UseAVX > 2) {
603 int xreg_enc = reg->encoding();
604 if (xreg_enc > 15) {
605 XMMRegister new_reg = as_XMMRegister(xreg_enc & 0xf);
606 emit_operand((Register)new_reg, base, index, scale, disp, rspec);
607 return;
608 }
609 }
610 emit_operand((Register)reg, base, index, scale, disp, rspec);
611 }
612
613 // Secret local extension to Assembler::WhichOperand:
614 #define end_pc_operand (_WhichOperand_limit)
615
616 address Assembler::locate_operand(address inst, WhichOperand which) {
617 // Decode the given instruction, and return the address of
618 // an embedded 32-bit operand word.
619
620 // If "which" is disp32_operand, selects the displacement portion
621 // of an effective address specifier.
622 // If "which" is imm64_operand, selects the trailing immediate constant.
623 // If "which" is call32_operand, selects the displacement of a call or jump.
624 // Caller is responsible for ensuring that there is such an operand,
625 // and that it is 32/64 bits wide.
626
627 // If "which" is end_pc_operand, find the end of the instruction.
628
629 address ip = inst;
630 bool is_64bit = false;
631
632 debug_only(bool has_disp32 = false);
633 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn
634
635 again_after_prefix:
636 switch (0xFF & *ip++) {
637
638 // These convenience macros generate groups of "case" labels for the switch.
639 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3
640 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \
641 case (x)+4: case (x)+5: case (x)+6: case (x)+7
642 #define REP16(x) REP8((x)+0): \
643 case REP8((x)+8)
644
645 case CS_segment:
646 case SS_segment:
647 case DS_segment:
648 case ES_segment:
649 case FS_segment:
650 case GS_segment:
651 // Seems dubious
652 LP64_ONLY(assert(false, "shouldn't have that prefix"));
653 assert(ip == inst+1, "only one prefix allowed");
654 goto again_after_prefix;
655
656 case 0x67:
657 case REX:
658 case REX_B:
659 case REX_X:
660 case REX_XB:
661 case REX_R:
662 case REX_RB:
663 case REX_RX:
664 case REX_RXB:
665 NOT_LP64(assert(false, "64bit prefixes"));
666 goto again_after_prefix;
667
668 case REX_W:
669 case REX_WB:
670 case REX_WX:
671 case REX_WXB:
672 case REX_WR:
673 case REX_WRB:
674 case REX_WRX:
675 case REX_WRXB:
676 NOT_LP64(assert(false, "64bit prefixes"));
677 is_64bit = true;
678 goto again_after_prefix;
679
680 case 0xFF: // pushq a; decl a; incl a; call a; jmp a
681 case 0x88: // movb a, r
682 case 0x89: // movl a, r
683 case 0x8A: // movb r, a
684 case 0x8B: // movl r, a
685 case 0x8F: // popl a
686 debug_only(has_disp32 = true);
687 break;
688
689 case 0x68: // pushq #32
690 if (which == end_pc_operand) {
691 return ip + 4;
692 }
693 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate");
694 return ip; // not produced by emit_operand
695
696 case 0x66: // movw ... (size prefix)
697 again_after_size_prefix2:
698 switch (0xFF & *ip++) {
699 case REX:
700 case REX_B:
701 case REX_X:
702 case REX_XB:
703 case REX_R:
704 case REX_RB:
705 case REX_RX:
706 case REX_RXB:
707 case REX_W:
708 case REX_WB:
709 case REX_WX:
710 case REX_WXB:
711 case REX_WR:
712 case REX_WRB:
713 case REX_WRX:
714 case REX_WRXB:
715 NOT_LP64(assert(false, "64bit prefix found"));
716 goto again_after_size_prefix2;
717 case 0x8B: // movw r, a
718 case 0x89: // movw a, r
719 debug_only(has_disp32 = true);
720 break;
721 case 0xC7: // movw a, #16
722 debug_only(has_disp32 = true);
723 tail_size = 2; // the imm16
724 break;
725 case 0x0F: // several SSE/SSE2 variants
726 ip--; // reparse the 0x0F
727 goto again_after_prefix;
728 default:
729 ShouldNotReachHere();
730 }
731 break;
732
733 case REP8(0xB8): // movl/q r, #32/#64(oop?)
734 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4);
735 // these asserts are somewhat nonsensical
736 #ifndef _LP64
737 assert(which == imm_operand || which == disp32_operand,
738 "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip));
739 #else
740 assert((which == call32_operand || which == imm_operand) && is_64bit ||
741 which == narrow_oop_operand && !is_64bit,
742 "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip));
743 #endif // _LP64
744 return ip;
745
746 case 0x69: // imul r, a, #32
747 case 0xC7: // movl a, #32(oop?)
748 tail_size = 4;
749 debug_only(has_disp32 = true); // has both kinds of operands!
750 break;
751
752 case 0x0F: // movx..., etc.
753 switch (0xFF & *ip++) {
754 case 0x3A: // pcmpestri
755 tail_size = 1;
756 case 0x38: // ptest, pmovzxbw
757 ip++; // skip opcode
758 debug_only(has_disp32 = true); // has both kinds of operands!
759 break;
760
761 case 0x70: // pshufd r, r/a, #8
762 debug_only(has_disp32 = true); // has both kinds of operands!
763 case 0x73: // psrldq r, #8
764 tail_size = 1;
765 break;
766
767 case 0x12: // movlps
768 case 0x28: // movaps
769 case 0x2E: // ucomiss
770 case 0x2F: // comiss
771 case 0x54: // andps
772 case 0x55: // andnps
773 case 0x56: // orps
774 case 0x57: // xorps
775 case 0x58: // addpd
776 case 0x59: // mulpd
777 case 0x6E: // movd
778 case 0x7E: // movd
779 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush
780 case 0xFE: // paddd
781 debug_only(has_disp32 = true);
782 break;
783
784 case 0xAD: // shrd r, a, %cl
785 case 0xAF: // imul r, a
786 case 0xBE: // movsbl r, a (movsxb)
787 case 0xBF: // movswl r, a (movsxw)
788 case 0xB6: // movzbl r, a (movzxb)
789 case 0xB7: // movzwl r, a (movzxw)
790 case REP16(0x40): // cmovl cc, r, a
791 case 0xB0: // cmpxchgb
792 case 0xB1: // cmpxchg
793 case 0xC1: // xaddl
794 case 0xC7: // cmpxchg8
795 case REP16(0x90): // setcc a
796 debug_only(has_disp32 = true);
797 // fall out of the switch to decode the address
798 break;
799
800 case 0xC4: // pinsrw r, a, #8
801 debug_only(has_disp32 = true);
802 case 0xC5: // pextrw r, r, #8
803 tail_size = 1; // the imm8
804 break;
805
806 case 0xAC: // shrd r, a, #8
807 debug_only(has_disp32 = true);
808 tail_size = 1; // the imm8
809 break;
810
811 case REP16(0x80): // jcc rdisp32
812 if (which == end_pc_operand) return ip + 4;
813 assert(which == call32_operand, "jcc has no disp32 or imm");
814 return ip;
815 default:
816 ShouldNotReachHere();
817 }
818 break;
819
820 case 0x81: // addl a, #32; addl r, #32
821 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
822 // on 32bit in the case of cmpl, the imm might be an oop
823 tail_size = 4;
824 debug_only(has_disp32 = true); // has both kinds of operands!
825 break;
826
827 case 0x83: // addl a, #8; addl r, #8
828 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
829 debug_only(has_disp32 = true); // has both kinds of operands!
830 tail_size = 1;
831 break;
832
833 case 0x9B:
834 switch (0xFF & *ip++) {
835 case 0xD9: // fnstcw a
836 debug_only(has_disp32 = true);
837 break;
838 default:
839 ShouldNotReachHere();
840 }
841 break;
842
843 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a
844 case REP4(0x10): // adc...
845 case REP4(0x20): // and...
846 case REP4(0x30): // xor...
847 case REP4(0x08): // or...
848 case REP4(0x18): // sbb...
849 case REP4(0x28): // sub...
850 case 0xF7: // mull a
851 case 0x8D: // lea r, a
852 case 0x87: // xchg r, a
853 case REP4(0x38): // cmp...
854 case 0x85: // test r, a
855 debug_only(has_disp32 = true); // has both kinds of operands!
856 break;
857
858 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8
859 case 0xC6: // movb a, #8
860 case 0x80: // cmpb a, #8
861 case 0x6B: // imul r, a, #8
862 debug_only(has_disp32 = true); // has both kinds of operands!
863 tail_size = 1; // the imm8
864 break;
865
866 case 0xC4: // VEX_3bytes
867 case 0xC5: // VEX_2bytes
868 assert((UseAVX > 0), "shouldn't have VEX prefix");
869 assert(ip == inst+1, "no prefixes allowed");
870 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions
871 // but they have prefix 0x0F and processed when 0x0F processed above.
872 //
873 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES
874 // instructions (these instructions are not supported in 64-bit mode).
875 // To distinguish them bits [7:6] are set in the VEX second byte since
876 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set
877 // those VEX bits REX and vvvv bits are inverted.
878 //
879 // Fortunately C2 doesn't generate these instructions so we don't need
880 // to check for them in product version.
881
882 // Check second byte
883 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions"));
884
885 int vex_opcode;
886 // First byte
887 if ((0xFF & *inst) == VEX_3bytes) {
888 vex_opcode = VEX_OPCODE_MASK & *ip;
889 ip++; // third byte
890 is_64bit = ((VEX_W & *ip) == VEX_W);
891 } else {
892 vex_opcode = VEX_OPCODE_0F;
893 }
894 ip++; // opcode
895 // To find the end of instruction (which == end_pc_operand).
896 switch (vex_opcode) {
897 case VEX_OPCODE_0F:
898 switch (0xFF & *ip) {
899 case 0x70: // pshufd r, r/a, #8
900 case 0x71: // ps[rl|ra|ll]w r, #8
901 case 0x72: // ps[rl|ra|ll]d r, #8
902 case 0x73: // ps[rl|ra|ll]q r, #8
903 case 0xC2: // cmp[ps|pd|ss|sd] r, r, r/a, #8
904 case 0xC4: // pinsrw r, r, r/a, #8
905 case 0xC5: // pextrw r/a, r, #8
906 case 0xC6: // shufp[s|d] r, r, r/a, #8
907 tail_size = 1; // the imm8
908 break;
909 }
910 break;
911 case VEX_OPCODE_0F_3A:
912 tail_size = 1;
913 break;
914 }
915 ip++; // skip opcode
916 debug_only(has_disp32 = true); // has both kinds of operands!
917 break;
918
919 case 0x62: // EVEX_4bytes
920 assert((UseAVX > 0), "shouldn't have EVEX prefix");
921 assert(ip == inst+1, "no prefixes allowed");
922 // no EVEX collisions, all instructions that have 0x62 opcodes
923 // have EVEX versions and are subopcodes of 0x66
924 ip++; // skip P0 and exmaine W in P1
925 is_64bit = ((VEX_W & *ip) == VEX_W);
926 ip++; // move to P2
927 ip++; // skip P2, move to opcode
928 // To find the end of instruction (which == end_pc_operand).
929 switch (0xFF & *ip) {
930 case 0x22: // pinsrd r, r/a, #8
931 case 0x61: // pcmpestri r, r/a, #8
932 case 0x70: // pshufd r, r/a, #8
933 case 0x73: // psrldq r, #8
934 tail_size = 1; // the imm8
935 break;
936 default:
937 break;
938 }
939 ip++; // skip opcode
940 debug_only(has_disp32 = true); // has both kinds of operands!
941 break;
942
943 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
944 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
945 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a
946 case 0xDD: // fld_d a; fst_d a; fstp_d a
947 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a
948 case 0xDF: // fild_d a; fistp_d a
949 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a
950 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a
951 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a
952 debug_only(has_disp32 = true);
953 break;
954
955 case 0xE8: // call rdisp32
956 case 0xE9: // jmp rdisp32
957 if (which == end_pc_operand) return ip + 4;
958 assert(which == call32_operand, "call has no disp32 or imm");
959 return ip;
960
961 case 0xF0: // Lock
962 assert(os::is_MP(), "only on MP");
963 goto again_after_prefix;
964
965 case 0xF3: // For SSE
966 case 0xF2: // For SSE2
967 switch (0xFF & *ip++) {
968 case REX:
969 case REX_B:
970 case REX_X:
971 case REX_XB:
972 case REX_R:
973 case REX_RB:
974 case REX_RX:
975 case REX_RXB:
976 case REX_W:
977 case REX_WB:
978 case REX_WX:
979 case REX_WXB:
980 case REX_WR:
981 case REX_WRB:
982 case REX_WRX:
983 case REX_WRXB:
984 NOT_LP64(assert(false, "found 64bit prefix"));
985 ip++;
986 default:
987 ip++;
988 }
989 debug_only(has_disp32 = true); // has both kinds of operands!
990 break;
991
992 default:
993 ShouldNotReachHere();
994
995 #undef REP8
996 #undef REP16
997 }
998
999 assert(which != call32_operand, "instruction is not a call, jmp, or jcc");
1000 #ifdef _LP64
1001 assert(which != imm_operand, "instruction is not a movq reg, imm64");
1002 #else
1003 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field");
1004 assert(which != imm_operand || has_disp32, "instruction has no imm32 field");
1005 #endif // LP64
1006 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field");
1007
1008 // parse the output of emit_operand
1009 int op2 = 0xFF & *ip++;
1010 int base = op2 & 0x07;
1011 int op3 = -1;
1012 const int b100 = 4;
1013 const int b101 = 5;
1014 if (base == b100 && (op2 >> 6) != 3) {
1015 op3 = 0xFF & *ip++;
1016 base = op3 & 0x07; // refetch the base
1017 }
1018 // now ip points at the disp (if any)
1019
1020 switch (op2 >> 6) {
1021 case 0:
1022 // [00 reg 100][ss index base]
1023 // [00 reg 100][00 100 esp]
1024 // [00 reg base]
1025 // [00 reg 100][ss index 101][disp32]
1026 // [00 reg 101] [disp32]
1027
1028 if (base == b101) {
1029 if (which == disp32_operand)
1030 return ip; // caller wants the disp32
1031 ip += 4; // skip the disp32
1032 }
1033 break;
1034
1035 case 1:
1036 // [01 reg 100][ss index base][disp8]
1037 // [01 reg 100][00 100 esp][disp8]
1038 // [01 reg base] [disp8]
1039 ip += 1; // skip the disp8
1040 break;
1041
1042 case 2:
1043 // [10 reg 100][ss index base][disp32]
1044 // [10 reg 100][00 100 esp][disp32]
1045 // [10 reg base] [disp32]
1046 if (which == disp32_operand)
1047 return ip; // caller wants the disp32
1048 ip += 4; // skip the disp32
1049 break;
1050
1051 case 3:
1052 // [11 reg base] (not a memory addressing mode)
1053 break;
1054 }
1055
1056 if (which == end_pc_operand) {
1057 return ip + tail_size;
1058 }
1059
1060 #ifdef _LP64
1061 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32");
1062 #else
1063 assert(which == imm_operand, "instruction has only an imm field");
1064 #endif // LP64
1065 return ip;
1066 }
1067
1068 address Assembler::locate_next_instruction(address inst) {
1069 // Secretly share code with locate_operand:
1070 return locate_operand(inst, end_pc_operand);
1071 }
1072
1073
1074 #ifdef ASSERT
1075 void Assembler::check_relocation(RelocationHolder const& rspec, int format) {
1076 address inst = inst_mark();
1077 assert(inst != NULL && inst < pc(), "must point to beginning of instruction");
1078 address opnd;
1079
1080 Relocation* r = rspec.reloc();
1081 if (r->type() == relocInfo::none) {
1082 return;
1083 } else if (r->is_call() || format == call32_operand) {
1084 // assert(format == imm32_operand, "cannot specify a nonzero format");
1085 opnd = locate_operand(inst, call32_operand);
1086 } else if (r->is_data()) {
1087 assert(format == imm_operand || format == disp32_operand
1088 LP64_ONLY(|| format == narrow_oop_operand), "format ok");
1089 opnd = locate_operand(inst, (WhichOperand)format);
1090 } else {
1091 assert(format == imm_operand, "cannot specify a format");
1092 return;
1093 }
1094 assert(opnd == pc(), "must put operand where relocs can find it");
1095 }
1096 #endif // ASSERT
1097
1098 void Assembler::emit_operand32(Register reg, Address adr) {
1099 assert(reg->encoding() < 8, "no extended registers");
1100 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1101 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1102 adr._rspec);
1103 }
1104
1105 void Assembler::emit_operand(Register reg, Address adr,
1106 int rip_relative_correction) {
1107 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1108 adr._rspec,
1109 rip_relative_correction);
1110 }
1111
1112 void Assembler::emit_operand(XMMRegister reg, Address adr) {
1113 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1114 adr._rspec);
1115 }
1116
1117 // MMX operations
1118 void Assembler::emit_operand(MMXRegister reg, Address adr) {
1119 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1120 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1121 }
1122
1123 // work around gcc (3.2.1-7a) bug
1124 void Assembler::emit_operand(Address adr, MMXRegister reg) {
1125 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1126 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1127 }
1128
1129
1130 void Assembler::emit_farith(int b1, int b2, int i) {
1131 assert(isByte(b1) && isByte(b2), "wrong opcode");
1132 assert(0 <= i && i < 8, "illegal stack offset");
1133 emit_int8(b1);
1134 emit_int8(b2 + i);
1135 }
1136
1137
1138 // Now the Assembler instructions (identical for 32/64 bits)
1139
1140 void Assembler::adcl(Address dst, int32_t imm32) {
1141 InstructionMark im(this);
1142 prefix(dst);
1143 emit_arith_operand(0x81, rdx, dst, imm32);
1144 }
1145
1146 void Assembler::adcl(Address dst, Register src) {
1147 InstructionMark im(this);
1148 prefix(dst, src);
1149 emit_int8(0x11);
1150 emit_operand(src, dst);
1151 }
1152
1153 void Assembler::adcl(Register dst, int32_t imm32) {
1154 prefix(dst);
1155 emit_arith(0x81, 0xD0, dst, imm32);
1156 }
1157
1158 void Assembler::adcl(Register dst, Address src) {
1159 InstructionMark im(this);
1160 prefix(src, dst);
1161 emit_int8(0x13);
1162 emit_operand(dst, src);
1163 }
1164
1165 void Assembler::adcl(Register dst, Register src) {
1166 (void) prefix_and_encode(dst->encoding(), src->encoding());
1167 emit_arith(0x13, 0xC0, dst, src);
1168 }
1169
1170 void Assembler::addl(Address dst, int32_t imm32) {
1171 InstructionMark im(this);
1172 prefix(dst);
1173 emit_arith_operand(0x81, rax, dst, imm32);
1174 }
1175
1176 void Assembler::addb(Address dst, int imm8) {
1177 InstructionMark im(this);
1178 prefix(dst);
1179 emit_int8((unsigned char)0x80);
1180 emit_operand(rax, dst, 1);
1181 emit_int8(imm8);
1182 }
1183
1184 void Assembler::addw(Address dst, int imm16) {
1185 InstructionMark im(this);
1186 emit_int8(0x66);
1187 prefix(dst);
1188 emit_int8((unsigned char)0x81);
1189 emit_operand(rax, dst, 2);
1190 emit_int16(imm16);
1191 }
1192
1193 void Assembler::addl(Address dst, Register src) {
1194 InstructionMark im(this);
1195 prefix(dst, src);
1196 emit_int8(0x01);
1197 emit_operand(src, dst);
1198 }
1199
1200 void Assembler::addl(Register dst, int32_t imm32) {
1201 prefix(dst);
1202 emit_arith(0x81, 0xC0, dst, imm32);
1203 }
1204
1205 void Assembler::addl(Register dst, Address src) {
1206 InstructionMark im(this);
1207 prefix(src, dst);
1208 emit_int8(0x03);
1209 emit_operand(dst, src);
1210 }
1211
1212 void Assembler::addl(Register dst, Register src) {
1213 (void) prefix_and_encode(dst->encoding(), src->encoding());
1214 emit_arith(0x03, 0xC0, dst, src);
1215 }
1216
1217 void Assembler::addr_nop_4() {
1218 assert(UseAddressNop, "no CPU support");
1219 // 4 bytes: NOP DWORD PTR [EAX+0]
1220 emit_int8(0x0F);
1221 emit_int8(0x1F);
1222 emit_int8(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
1223 emit_int8(0); // 8-bits offset (1 byte)
1224 }
1225
1226 void Assembler::addr_nop_5() {
1227 assert(UseAddressNop, "no CPU support");
1228 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
1229 emit_int8(0x0F);
1230 emit_int8(0x1F);
1231 emit_int8(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
1232 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1233 emit_int8(0); // 8-bits offset (1 byte)
1234 }
1235
1236 void Assembler::addr_nop_7() {
1237 assert(UseAddressNop, "no CPU support");
1238 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
1239 emit_int8(0x0F);
1240 emit_int8(0x1F);
1241 emit_int8((unsigned char)0x80);
1242 // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
1243 emit_int32(0); // 32-bits offset (4 bytes)
1244 }
1245
1246 void Assembler::addr_nop_8() {
1247 assert(UseAddressNop, "no CPU support");
1248 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
1249 emit_int8(0x0F);
1250 emit_int8(0x1F);
1251 emit_int8((unsigned char)0x84);
1252 // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
1253 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1254 emit_int32(0); // 32-bits offset (4 bytes)
1255 }
1256
1257 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
1258 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1259 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1260 attributes.set_rex_vex_w_reverted();
1261 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1262 emit_int8(0x58);
1263 emit_int8((unsigned char)(0xC0 | encode));
1264 }
1265
1266 void Assembler::addsd(XMMRegister dst, Address src) {
1267 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1268 InstructionMark im(this);
1269 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1270 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1271 attributes.set_rex_vex_w_reverted();
1272 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1273 emit_int8(0x58);
1274 emit_operand(dst, src);
1275 }
1276
1277 void Assembler::addss(XMMRegister dst, XMMRegister src) {
1278 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1279 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1280 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1281 emit_int8(0x58);
1282 emit_int8((unsigned char)(0xC0 | encode));
1283 }
1284
1285 void Assembler::addss(XMMRegister dst, Address src) {
1286 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1287 InstructionMark im(this);
1288 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1289 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1290 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1291 emit_int8(0x58);
1292 emit_operand(dst, src);
1293 }
1294
1295 void Assembler::aesdec(XMMRegister dst, Address src) {
1296 assert(VM_Version::supports_aes(), "");
1297 InstructionMark im(this);
1298 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1299 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1300 emit_int8((unsigned char)0xDE);
1301 emit_operand(dst, src);
1302 }
1303
1304 void Assembler::aesdec(XMMRegister dst, XMMRegister src) {
1305 assert(VM_Version::supports_aes(), "");
1306 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1307 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1308 emit_int8((unsigned char)0xDE);
1309 emit_int8(0xC0 | encode);
1310 }
1311
1312 void Assembler::aesdeclast(XMMRegister dst, Address src) {
1313 assert(VM_Version::supports_aes(), "");
1314 InstructionMark im(this);
1315 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1316 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1317 emit_int8((unsigned char)0xDF);
1318 emit_operand(dst, src);
1319 }
1320
1321 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) {
1322 assert(VM_Version::supports_aes(), "");
1323 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1324 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1325 emit_int8((unsigned char)0xDF);
1326 emit_int8((unsigned char)(0xC0 | encode));
1327 }
1328
1329 void Assembler::aesenc(XMMRegister dst, Address src) {
1330 assert(VM_Version::supports_aes(), "");
1331 InstructionMark im(this);
1332 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1333 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1334 emit_int8((unsigned char)0xDC);
1335 emit_operand(dst, src);
1336 }
1337
1338 void Assembler::aesenc(XMMRegister dst, XMMRegister src) {
1339 assert(VM_Version::supports_aes(), "");
1340 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1341 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1342 emit_int8((unsigned char)0xDC);
1343 emit_int8(0xC0 | encode);
1344 }
1345
1346 void Assembler::aesenclast(XMMRegister dst, Address src) {
1347 assert(VM_Version::supports_aes(), "");
1348 InstructionMark im(this);
1349 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1350 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1351 emit_int8((unsigned char)0xDD);
1352 emit_operand(dst, src);
1353 }
1354
1355 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) {
1356 assert(VM_Version::supports_aes(), "");
1357 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1358 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1359 emit_int8((unsigned char)0xDD);
1360 emit_int8((unsigned char)(0xC0 | encode));
1361 }
1362
1363 void Assembler::andl(Address dst, int32_t imm32) {
1364 InstructionMark im(this);
1365 prefix(dst);
1366 emit_int8((unsigned char)0x81);
1367 emit_operand(rsp, dst, 4);
1368 emit_int32(imm32);
1369 }
1370
1371 void Assembler::andl(Register dst, int32_t imm32) {
1372 prefix(dst);
1373 emit_arith(0x81, 0xE0, dst, imm32);
1374 }
1375
1376 void Assembler::andl(Register dst, Address src) {
1377 InstructionMark im(this);
1378 prefix(src, dst);
1379 emit_int8(0x23);
1380 emit_operand(dst, src);
1381 }
1382
1383 void Assembler::andl(Register dst, Register src) {
1384 (void) prefix_and_encode(dst->encoding(), src->encoding());
1385 emit_arith(0x23, 0xC0, dst, src);
1386 }
1387
1388 void Assembler::andnl(Register dst, Register src1, Register src2) {
1389 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1390 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1391 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1392 emit_int8((unsigned char)0xF2);
1393 emit_int8((unsigned char)(0xC0 | encode));
1394 }
1395
1396 void Assembler::andnl(Register dst, Register src1, Address src2) {
1397 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1398 InstructionMark im(this);
1399 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1400 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1401 emit_int8((unsigned char)0xF2);
1402 emit_operand(dst, src2);
1403 }
1404
1405 void Assembler::bsfl(Register dst, Register src) {
1406 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1407 emit_int8(0x0F);
1408 emit_int8((unsigned char)0xBC);
1409 emit_int8((unsigned char)(0xC0 | encode));
1410 }
1411
1412 void Assembler::bsrl(Register dst, Register src) {
1413 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1414 emit_int8(0x0F);
1415 emit_int8((unsigned char)0xBD);
1416 emit_int8((unsigned char)(0xC0 | encode));
1417 }
1418
1419 void Assembler::bswapl(Register reg) { // bswap
1420 int encode = prefix_and_encode(reg->encoding());
1421 emit_int8(0x0F);
1422 emit_int8((unsigned char)(0xC8 | encode));
1423 }
1424
1425 void Assembler::blsil(Register dst, Register src) {
1426 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1427 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1428 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1429 emit_int8((unsigned char)0xF3);
1430 emit_int8((unsigned char)(0xC0 | encode));
1431 }
1432
1433 void Assembler::blsil(Register dst, Address src) {
1434 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1435 InstructionMark im(this);
1436 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1437 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1438 emit_int8((unsigned char)0xF3);
1439 emit_operand(rbx, src);
1440 }
1441
1442 void Assembler::blsmskl(Register dst, Register src) {
1443 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1444 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1445 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1446 emit_int8((unsigned char)0xF3);
1447 emit_int8((unsigned char)(0xC0 | encode));
1448 }
1449
1450 void Assembler::blsmskl(Register dst, Address src) {
1451 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1452 InstructionMark im(this);
1453 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1454 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1455 emit_int8((unsigned char)0xF3);
1456 emit_operand(rdx, src);
1457 }
1458
1459 void Assembler::blsrl(Register dst, Register src) {
1460 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1461 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1462 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1463 emit_int8((unsigned char)0xF3);
1464 emit_int8((unsigned char)(0xC0 | encode));
1465 }
1466
1467 void Assembler::blsrl(Register dst, Address src) {
1468 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1469 InstructionMark im(this);
1470 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1471 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1472 emit_int8((unsigned char)0xF3);
1473 emit_operand(rcx, src);
1474 }
1475
1476 void Assembler::call(Label& L, relocInfo::relocType rtype) {
1477 // suspect disp32 is always good
1478 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
1479
1480 if (L.is_bound()) {
1481 const int long_size = 5;
1482 int offs = (int)( target(L) - pc() );
1483 assert(offs <= 0, "assembler error");
1484 InstructionMark im(this);
1485 // 1110 1000 #32-bit disp
1486 emit_int8((unsigned char)0xE8);
1487 emit_data(offs - long_size, rtype, operand);
1488 } else {
1489 InstructionMark im(this);
1490 // 1110 1000 #32-bit disp
1491 L.add_patch_at(code(), locator());
1492
1493 emit_int8((unsigned char)0xE8);
1494 emit_data(int(0), rtype, operand);
1495 }
1496 }
1497
1498 void Assembler::call(Register dst) {
1499 int encode = prefix_and_encode(dst->encoding());
1500 emit_int8((unsigned char)0xFF);
1501 emit_int8((unsigned char)(0xD0 | encode));
1502 }
1503
1504
1505 void Assembler::call(Address adr) {
1506 InstructionMark im(this);
1507 prefix(adr);
1508 emit_int8((unsigned char)0xFF);
1509 emit_operand(rdx, adr);
1510 }
1511
1512 void Assembler::call_literal(address entry, RelocationHolder const& rspec) {
1513 assert(entry != NULL, "call most probably wrong");
1514 InstructionMark im(this);
1515 emit_int8((unsigned char)0xE8);
1516 intptr_t disp = entry - (pc() + sizeof(int32_t));
1517 assert(is_simm32(disp), "must be 32bit offset (call2)");
1518 // Technically, should use call32_operand, but this format is
1519 // implied by the fact that we're emitting a call instruction.
1520
1521 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand);
1522 emit_data((int) disp, rspec, operand);
1523 }
1524
1525 void Assembler::cdql() {
1526 emit_int8((unsigned char)0x99);
1527 }
1528
1529 void Assembler::cld() {
1530 emit_int8((unsigned char)0xFC);
1531 }
1532
1533 void Assembler::cmovl(Condition cc, Register dst, Register src) {
1534 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1535 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1536 emit_int8(0x0F);
1537 emit_int8(0x40 | cc);
1538 emit_int8((unsigned char)(0xC0 | encode));
1539 }
1540
1541
1542 void Assembler::cmovl(Condition cc, Register dst, Address src) {
1543 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1544 prefix(src, dst);
1545 emit_int8(0x0F);
1546 emit_int8(0x40 | cc);
1547 emit_operand(dst, src);
1548 }
1549
1550 void Assembler::cmpb(Address dst, int imm8) {
1551 InstructionMark im(this);
1552 prefix(dst);
1553 emit_int8((unsigned char)0x80);
1554 emit_operand(rdi, dst, 1);
1555 emit_int8(imm8);
1556 }
1557
1558 void Assembler::cmpl(Address dst, int32_t imm32) {
1559 InstructionMark im(this);
1560 prefix(dst);
1561 emit_int8((unsigned char)0x81);
1562 emit_operand(rdi, dst, 4);
1563 emit_int32(imm32);
1564 }
1565
1566 void Assembler::cmpl(Register dst, int32_t imm32) {
1567 prefix(dst);
1568 emit_arith(0x81, 0xF8, dst, imm32);
1569 }
1570
1571 void Assembler::cmpl(Register dst, Register src) {
1572 (void) prefix_and_encode(dst->encoding(), src->encoding());
1573 emit_arith(0x3B, 0xC0, dst, src);
1574 }
1575
1576 void Assembler::cmpl(Register dst, Address src) {
1577 InstructionMark im(this);
1578 prefix(src, dst);
1579 emit_int8((unsigned char)0x3B);
1580 emit_operand(dst, src);
1581 }
1582
1583 void Assembler::cmpw(Address dst, int imm16) {
1584 InstructionMark im(this);
1585 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers");
1586 emit_int8(0x66);
1587 emit_int8((unsigned char)0x81);
1588 emit_operand(rdi, dst, 2);
1589 emit_int16(imm16);
1590 }
1591
1592 // The 32-bit cmpxchg compares the value at adr with the contents of rax,
1593 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1594 // The ZF is set if the compared values were equal, and cleared otherwise.
1595 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg
1596 InstructionMark im(this);
1597 prefix(adr, reg);
1598 emit_int8(0x0F);
1599 emit_int8((unsigned char)0xB1);
1600 emit_operand(reg, adr);
1601 }
1602
1603 // The 8-bit cmpxchg compares the value at adr with the contents of rax,
1604 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1605 // The ZF is set if the compared values were equal, and cleared otherwise.
1606 void Assembler::cmpxchgb(Register reg, Address adr) { // cmpxchg
1607 InstructionMark im(this);
1608 prefix(adr, reg, true);
1609 emit_int8(0x0F);
1610 emit_int8((unsigned char)0xB0);
1611 emit_operand(reg, adr);
1612 }
1613
1614 void Assembler::comisd(XMMRegister dst, Address src) {
1615 // NOTE: dbx seems to decode this as comiss even though the
1616 // 0x66 is there. Strangly ucomisd comes out correct
1617 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1618 InstructionMark im(this);
1619 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);;
1620 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1621 attributes.set_rex_vex_w_reverted();
1622 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1623 emit_int8(0x2F);
1624 emit_operand(dst, src);
1625 }
1626
1627 void Assembler::comisd(XMMRegister dst, XMMRegister src) {
1628 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1629 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1630 attributes.set_rex_vex_w_reverted();
1631 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1632 emit_int8(0x2F);
1633 emit_int8((unsigned char)(0xC0 | encode));
1634 }
1635
1636 void Assembler::comiss(XMMRegister dst, Address src) {
1637 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1638 InstructionMark im(this);
1639 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1640 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1641 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1642 emit_int8(0x2F);
1643 emit_operand(dst, src);
1644 }
1645
1646 void Assembler::comiss(XMMRegister dst, XMMRegister src) {
1647 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1648 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1649 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1650 emit_int8(0x2F);
1651 emit_int8((unsigned char)(0xC0 | encode));
1652 }
1653
1654 void Assembler::cpuid() {
1655 emit_int8(0x0F);
1656 emit_int8((unsigned char)0xA2);
1657 }
1658
1659 // Opcode / Instruction Op / En 64 - Bit Mode Compat / Leg Mode Description Implemented
1660 // F2 0F 38 F0 / r CRC32 r32, r / m8 RM Valid Valid Accumulate CRC32 on r / m8. v
1661 // F2 REX 0F 38 F0 / r CRC32 r32, r / m8* RM Valid N.E. Accumulate CRC32 on r / m8. -
1662 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E. Accumulate CRC32 on r / m8. -
1663 //
1664 // F2 0F 38 F1 / r CRC32 r32, r / m16 RM Valid Valid Accumulate CRC32 on r / m16. v
1665 //
1666 // F2 0F 38 F1 / r CRC32 r32, r / m32 RM Valid Valid Accumulate CRC32 on r / m32. v
1667 //
1668 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E. Accumulate CRC32 on r / m64. v
1669 void Assembler::crc32(Register crc, Register v, int8_t sizeInBytes) {
1670 assert(VM_Version::supports_sse4_2(), "");
1671 int8_t w = 0x01;
1672 Prefix p = Prefix_EMPTY;
1673
1674 emit_int8((int8_t)0xF2);
1675 switch (sizeInBytes) {
1676 case 1:
1677 w = 0;
1678 break;
1679 case 2:
1680 case 4:
1681 break;
1682 LP64_ONLY(case 8:)
1683 // This instruction is not valid in 32 bits
1684 // Note:
1685 // http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
1686 //
1687 // Page B - 72 Vol. 2C says
1688 // qwreg2 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : 11 qwreg1 qwreg2
1689 // mem64 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : mod qwreg r / m
1690 // F0!!!
1691 // while 3 - 208 Vol. 2A
1692 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E.Accumulate CRC32 on r / m64.
1693 //
1694 // the 0 on a last bit is reserved for a different flavor of this instruction :
1695 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E.Accumulate CRC32 on r / m8.
1696 p = REX_W;
1697 break;
1698 default:
1699 assert(0, "Unsupported value for a sizeInBytes argument");
1700 break;
1701 }
1702 LP64_ONLY(prefix(crc, v, p);)
1703 emit_int8((int8_t)0x0F);
1704 emit_int8(0x38);
1705 emit_int8((int8_t)(0xF0 | w));
1706 emit_int8(0xC0 | ((crc->encoding() & 0x7) << 3) | (v->encoding() & 7));
1707 }
1708
1709 void Assembler::crc32(Register crc, Address adr, int8_t sizeInBytes) {
1710 assert(VM_Version::supports_sse4_2(), "");
1711 InstructionMark im(this);
1712 int8_t w = 0x01;
1713 Prefix p = Prefix_EMPTY;
1714
1715 emit_int8((int8_t)0xF2);
1716 switch (sizeInBytes) {
1717 case 1:
1718 w = 0;
1719 break;
1720 case 2:
1721 case 4:
1722 break;
1723 LP64_ONLY(case 8:)
1724 // This instruction is not valid in 32 bits
1725 p = REX_W;
1726 break;
1727 default:
1728 assert(0, "Unsupported value for a sizeInBytes argument");
1729 break;
1730 }
1731 LP64_ONLY(prefix(crc, adr, p);)
1732 emit_int8((int8_t)0x0F);
1733 emit_int8(0x38);
1734 emit_int8((int8_t)(0xF0 | w));
1735 emit_operand(crc, adr);
1736 }
1737
1738 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
1739 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1740 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
1741 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1742 emit_int8((unsigned char)0xE6);
1743 emit_int8((unsigned char)(0xC0 | encode));
1744 }
1745
1746 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
1747 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1748 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
1749 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1750 emit_int8(0x5B);
1751 emit_int8((unsigned char)(0xC0 | encode));
1752 }
1753
1754 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
1755 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1756 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1757 attributes.set_rex_vex_w_reverted();
1758 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1759 emit_int8(0x5A);
1760 emit_int8((unsigned char)(0xC0 | encode));
1761 }
1762
1763 void Assembler::cvtsd2ss(XMMRegister dst, Address src) {
1764 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1765 InstructionMark im(this);
1766 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1767 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1768 attributes.set_rex_vex_w_reverted();
1769 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1770 emit_int8(0x5A);
1771 emit_operand(dst, src);
1772 }
1773
1774 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
1775 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1776 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1777 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1778 emit_int8(0x2A);
1779 emit_int8((unsigned char)(0xC0 | encode));
1780 }
1781
1782 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) {
1783 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1784 InstructionMark im(this);
1785 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1786 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1787 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1788 emit_int8(0x2A);
1789 emit_operand(dst, src);
1790 }
1791
1792 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
1793 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1794 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1795 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1796 emit_int8(0x2A);
1797 emit_int8((unsigned char)(0xC0 | encode));
1798 }
1799
1800 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) {
1801 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1802 InstructionMark im(this);
1803 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1804 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1805 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1806 emit_int8(0x2A);
1807 emit_operand(dst, src);
1808 }
1809
1810 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
1811 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1812 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1813 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1814 emit_int8(0x2A);
1815 emit_int8((unsigned char)(0xC0 | encode));
1816 }
1817
1818 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
1819 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1820 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1821 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1822 emit_int8(0x5A);
1823 emit_int8((unsigned char)(0xC0 | encode));
1824 }
1825
1826 void Assembler::cvtss2sd(XMMRegister dst, Address src) {
1827 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1828 InstructionMark im(this);
1829 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1830 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1831 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1832 emit_int8(0x5A);
1833 emit_operand(dst, src);
1834 }
1835
1836
1837 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
1838 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1839 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1840 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1841 emit_int8(0x2C);
1842 emit_int8((unsigned char)(0xC0 | encode));
1843 }
1844
1845 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
1846 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1847 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1848 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1849 emit_int8(0x2C);
1850 emit_int8((unsigned char)(0xC0 | encode));
1851 }
1852
1853 void Assembler::cvttpd2dq(XMMRegister dst, XMMRegister src) {
1854 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1855 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
1856 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
1857 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1858 emit_int8((unsigned char)0xE6);
1859 emit_int8((unsigned char)(0xC0 | encode));
1860 }
1861
1862 void Assembler::decl(Address dst) {
1863 // Don't use it directly. Use MacroAssembler::decrement() instead.
1864 InstructionMark im(this);
1865 prefix(dst);
1866 emit_int8((unsigned char)0xFF);
1867 emit_operand(rcx, dst);
1868 }
1869
1870 void Assembler::divsd(XMMRegister dst, Address src) {
1871 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1872 InstructionMark im(this);
1873 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1874 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1875 attributes.set_rex_vex_w_reverted();
1876 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1877 emit_int8(0x5E);
1878 emit_operand(dst, src);
1879 }
1880
1881 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
1882 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1883 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1884 attributes.set_rex_vex_w_reverted();
1885 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1886 emit_int8(0x5E);
1887 emit_int8((unsigned char)(0xC0 | encode));
1888 }
1889
1890 void Assembler::divss(XMMRegister dst, Address src) {
1891 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1892 InstructionMark im(this);
1893 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1894 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1895 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1896 emit_int8(0x5E);
1897 emit_operand(dst, src);
1898 }
1899
1900 void Assembler::divss(XMMRegister dst, XMMRegister src) {
1901 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1902 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1903 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1904 emit_int8(0x5E);
1905 emit_int8((unsigned char)(0xC0 | encode));
1906 }
1907
1908 void Assembler::emms() {
1909 NOT_LP64(assert(VM_Version::supports_mmx(), ""));
1910 emit_int8(0x0F);
1911 emit_int8(0x77);
1912 }
1913
1914 void Assembler::hlt() {
1915 emit_int8((unsigned char)0xF4);
1916 }
1917
1918 void Assembler::idivl(Register src) {
1919 int encode = prefix_and_encode(src->encoding());
1920 emit_int8((unsigned char)0xF7);
1921 emit_int8((unsigned char)(0xF8 | encode));
1922 }
1923
1924 void Assembler::divl(Register src) { // Unsigned
1925 int encode = prefix_and_encode(src->encoding());
1926 emit_int8((unsigned char)0xF7);
1927 emit_int8((unsigned char)(0xF0 | encode));
1928 }
1929
1930 void Assembler::imull(Register src) {
1931 int encode = prefix_and_encode(src->encoding());
1932 emit_int8((unsigned char)0xF7);
1933 emit_int8((unsigned char)(0xE8 | encode));
1934 }
1935
1936 void Assembler::imull(Register dst, Register src) {
1937 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1938 emit_int8(0x0F);
1939 emit_int8((unsigned char)0xAF);
1940 emit_int8((unsigned char)(0xC0 | encode));
1941 }
1942
1943
1944 void Assembler::imull(Register dst, Register src, int value) {
1945 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1946 if (is8bit(value)) {
1947 emit_int8(0x6B);
1948 emit_int8((unsigned char)(0xC0 | encode));
1949 emit_int8(value & 0xFF);
1950 } else {
1951 emit_int8(0x69);
1952 emit_int8((unsigned char)(0xC0 | encode));
1953 emit_int32(value);
1954 }
1955 }
1956
1957 void Assembler::imull(Register dst, Address src) {
1958 InstructionMark im(this);
1959 prefix(src, dst);
1960 emit_int8(0x0F);
1961 emit_int8((unsigned char) 0xAF);
1962 emit_operand(dst, src);
1963 }
1964
1965
1966 void Assembler::incl(Address dst) {
1967 // Don't use it directly. Use MacroAssembler::increment() instead.
1968 InstructionMark im(this);
1969 prefix(dst);
1970 emit_int8((unsigned char)0xFF);
1971 emit_operand(rax, dst);
1972 }
1973
1974 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) {
1975 InstructionMark im(this);
1976 assert((0 <= cc) && (cc < 16), "illegal cc");
1977 if (L.is_bound()) {
1978 address dst = target(L);
1979 assert(dst != NULL, "jcc most probably wrong");
1980
1981 const int short_size = 2;
1982 const int long_size = 6;
1983 intptr_t offs = (intptr_t)dst - (intptr_t)pc();
1984 if (maybe_short && is8bit(offs - short_size)) {
1985 // 0111 tttn #8-bit disp
1986 emit_int8(0x70 | cc);
1987 emit_int8((offs - short_size) & 0xFF);
1988 } else {
1989 // 0000 1111 1000 tttn #32-bit disp
1990 assert(is_simm32(offs - long_size),
1991 "must be 32bit offset (call4)");
1992 emit_int8(0x0F);
1993 emit_int8((unsigned char)(0x80 | cc));
1994 emit_int32(offs - long_size);
1995 }
1996 } else {
1997 // Note: could eliminate cond. jumps to this jump if condition
1998 // is the same however, seems to be rather unlikely case.
1999 // Note: use jccb() if label to be bound is very close to get
2000 // an 8-bit displacement
2001 L.add_patch_at(code(), locator());
2002 emit_int8(0x0F);
2003 emit_int8((unsigned char)(0x80 | cc));
2004 emit_int32(0);
2005 }
2006 }
2007
2008 void Assembler::jccb(Condition cc, Label& L) {
2009 if (L.is_bound()) {
2010 const int short_size = 2;
2011 address entry = target(L);
2012 #ifdef ASSERT
2013 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
2014 intptr_t delta = short_branch_delta();
2015 if (delta != 0) {
2016 dist += (dist < 0 ? (-delta) :delta);
2017 }
2018 assert(is8bit(dist), "Dispacement too large for a short jmp");
2019 #endif
2020 intptr_t offs = (intptr_t)entry - (intptr_t)pc();
2021 // 0111 tttn #8-bit disp
2022 emit_int8(0x70 | cc);
2023 emit_int8((offs - short_size) & 0xFF);
2024 } else {
2025 InstructionMark im(this);
2026 L.add_patch_at(code(), locator());
2027 emit_int8(0x70 | cc);
2028 emit_int8(0);
2029 }
2030 }
2031
2032 void Assembler::jmp(Address adr) {
2033 InstructionMark im(this);
2034 prefix(adr);
2035 emit_int8((unsigned char)0xFF);
2036 emit_operand(rsp, adr);
2037 }
2038
2039 void Assembler::jmp(Label& L, bool maybe_short) {
2040 if (L.is_bound()) {
2041 address entry = target(L);
2042 assert(entry != NULL, "jmp most probably wrong");
2043 InstructionMark im(this);
2044 const int short_size = 2;
2045 const int long_size = 5;
2046 intptr_t offs = entry - pc();
2047 if (maybe_short && is8bit(offs - short_size)) {
2048 emit_int8((unsigned char)0xEB);
2049 emit_int8((offs - short_size) & 0xFF);
2050 } else {
2051 emit_int8((unsigned char)0xE9);
2052 emit_int32(offs - long_size);
2053 }
2054 } else {
2055 // By default, forward jumps are always 32-bit displacements, since
2056 // we can't yet know where the label will be bound. If you're sure that
2057 // the forward jump will not run beyond 256 bytes, use jmpb to
2058 // force an 8-bit displacement.
2059 InstructionMark im(this);
2060 L.add_patch_at(code(), locator());
2061 emit_int8((unsigned char)0xE9);
2062 emit_int32(0);
2063 }
2064 }
2065
2066 void Assembler::jmp(Register entry) {
2067 int encode = prefix_and_encode(entry->encoding());
2068 emit_int8((unsigned char)0xFF);
2069 emit_int8((unsigned char)(0xE0 | encode));
2070 }
2071
2072 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
2073 InstructionMark im(this);
2074 emit_int8((unsigned char)0xE9);
2075 assert(dest != NULL, "must have a target");
2076 intptr_t disp = dest - (pc() + sizeof(int32_t));
2077 assert(is_simm32(disp), "must be 32bit offset (jmp)");
2078 emit_data(disp, rspec.reloc(), call32_operand);
2079 }
2080
2081 void Assembler::jmpb(Label& L) {
2082 if (L.is_bound()) {
2083 const int short_size = 2;
2084 address entry = target(L);
2085 assert(entry != NULL, "jmp most probably wrong");
2086 #ifdef ASSERT
2087 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
2088 intptr_t delta = short_branch_delta();
2089 if (delta != 0) {
2090 dist += (dist < 0 ? (-delta) :delta);
2091 }
2092 assert(is8bit(dist), "Dispacement too large for a short jmp");
2093 #endif
2094 intptr_t offs = entry - pc();
2095 emit_int8((unsigned char)0xEB);
2096 emit_int8((offs - short_size) & 0xFF);
2097 } else {
2098 InstructionMark im(this);
2099 L.add_patch_at(code(), locator());
2100 emit_int8((unsigned char)0xEB);
2101 emit_int8(0);
2102 }
2103 }
2104
2105 void Assembler::ldmxcsr( Address src) {
2106 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2107 InstructionMark im(this);
2108 prefix(src);
2109 emit_int8(0x0F);
2110 emit_int8((unsigned char)0xAE);
2111 emit_operand(as_Register(2), src);
2112 }
2113
2114 void Assembler::leal(Register dst, Address src) {
2115 InstructionMark im(this);
2116 #ifdef _LP64
2117 emit_int8(0x67); // addr32
2118 prefix(src, dst);
2119 #endif // LP64
2120 emit_int8((unsigned char)0x8D);
2121 emit_operand(dst, src);
2122 }
2123
2124 void Assembler::lfence() {
2125 emit_int8(0x0F);
2126 emit_int8((unsigned char)0xAE);
2127 emit_int8((unsigned char)0xE8);
2128 }
2129
2130 void Assembler::lock() {
2131 emit_int8((unsigned char)0xF0);
2132 }
2133
2134 void Assembler::lzcntl(Register dst, Register src) {
2135 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
2136 emit_int8((unsigned char)0xF3);
2137 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2138 emit_int8(0x0F);
2139 emit_int8((unsigned char)0xBD);
2140 emit_int8((unsigned char)(0xC0 | encode));
2141 }
2142
2143 // Emit mfence instruction
2144 void Assembler::mfence() {
2145 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
2146 emit_int8(0x0F);
2147 emit_int8((unsigned char)0xAE);
2148 emit_int8((unsigned char)0xF0);
2149 }
2150
2151 void Assembler::mov(Register dst, Register src) {
2152 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2153 }
2154
2155 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
2156 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2157 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2158 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2159 attributes.set_rex_vex_w_reverted();
2160 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2161 emit_int8(0x28);
2162 emit_int8((unsigned char)(0xC0 | encode));
2163 }
2164
2165 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
2166 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2167 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2168 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2169 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2170 emit_int8(0x28);
2171 emit_int8((unsigned char)(0xC0 | encode));
2172 }
2173
2174 void Assembler::movlhps(XMMRegister dst, XMMRegister src) {
2175 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2176 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2177 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2178 emit_int8(0x16);
2179 emit_int8((unsigned char)(0xC0 | encode));
2180 }
2181
2182 void Assembler::movb(Register dst, Address src) {
2183 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
2184 InstructionMark im(this);
2185 prefix(src, dst, true);
2186 emit_int8((unsigned char)0x8A);
2187 emit_operand(dst, src);
2188 }
2189
2190 void Assembler::movddup(XMMRegister dst, XMMRegister src) {
2191 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
2192 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2193 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2194 attributes.set_rex_vex_w_reverted();
2195 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2196 emit_int8(0x12);
2197 emit_int8(0xC0 | encode);
2198 }
2199
2200 void Assembler::kmovbl(KRegister dst, Register src) {
2201 assert(VM_Version::supports_avx512dq(), "");
2202 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2203 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2204 emit_int8((unsigned char)0x92);
2205 emit_int8((unsigned char)(0xC0 | encode));
2206 }
2207
2208 void Assembler::kmovbl(Register dst, KRegister src) {
2209 assert(VM_Version::supports_avx512dq(), "");
2210 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2211 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2212 emit_int8((unsigned char)0x93);
2213 emit_int8((unsigned char)(0xC0 | encode));
2214 }
2215
2216 void Assembler::kmovwl(KRegister dst, Register src) {
2217 assert(VM_Version::supports_evex(), "");
2218 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2219 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2220 emit_int8((unsigned char)0x92);
2221 emit_int8((unsigned char)(0xC0 | encode));
2222 }
2223
2224 void Assembler::kmovwl(Register dst, KRegister src) {
2225 assert(VM_Version::supports_evex(), "");
2226 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2227 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2228 emit_int8((unsigned char)0x93);
2229 emit_int8((unsigned char)(0xC0 | encode));
2230 }
2231
2232 void Assembler::kmovwl(KRegister dst, Address src) {
2233 assert(VM_Version::supports_evex(), "");
2234 InstructionMark im(this);
2235 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2236 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2237 emit_int8((unsigned char)0x90);
2238 emit_operand((Register)dst, src);
2239 }
2240
2241 void Assembler::kmovdl(KRegister dst, Register src) {
2242 assert(VM_Version::supports_avx512bw(), "");
2243 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2244 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2245 emit_int8((unsigned char)0x92);
2246 emit_int8((unsigned char)(0xC0 | encode));
2247 }
2248
2249 void Assembler::kmovdl(Register dst, KRegister src) {
2250 assert(VM_Version::supports_avx512bw(), "");
2251 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2252 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2253 emit_int8((unsigned char)0x93);
2254 emit_int8((unsigned char)(0xC0 | encode));
2255 }
2256
2257 void Assembler::kmovql(KRegister dst, KRegister src) {
2258 assert(VM_Version::supports_avx512bw(), "");
2259 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2260 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2261 emit_int8((unsigned char)0x90);
2262 emit_int8((unsigned char)(0xC0 | encode));
2263 }
2264
2265 void Assembler::kmovql(KRegister dst, Address src) {
2266 assert(VM_Version::supports_avx512bw(), "");
2267 InstructionMark im(this);
2268 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2269 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2270 emit_int8((unsigned char)0x90);
2271 emit_operand((Register)dst, src);
2272 }
2273
2274 void Assembler::kmovql(Address dst, KRegister src) {
2275 assert(VM_Version::supports_avx512bw(), "");
2276 InstructionMark im(this);
2277 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2278 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2279 emit_int8((unsigned char)0x90);
2280 emit_operand((Register)src, dst);
2281 }
2282
2283 void Assembler::kmovql(KRegister dst, Register src) {
2284 assert(VM_Version::supports_avx512bw(), "");
2285 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2286 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2287 emit_int8((unsigned char)0x92);
2288 emit_int8((unsigned char)(0xC0 | encode));
2289 }
2290
2291 void Assembler::kmovql(Register dst, KRegister src) {
2292 assert(VM_Version::supports_avx512bw(), "");
2293 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2294 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2295 emit_int8((unsigned char)0x93);
2296 emit_int8((unsigned char)(0xC0 | encode));
2297 }
2298
2299 void Assembler::knotwl(KRegister dst, KRegister src) {
2300 assert(VM_Version::supports_evex(), "");
2301 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2302 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2303 emit_int8((unsigned char)0x44);
2304 emit_int8((unsigned char)(0xC0 | encode));
2305 }
2306
2307 // This instruction produces ZF or CF flags
2308 void Assembler::kortestbl(KRegister src1, KRegister src2) {
2309 assert(VM_Version::supports_avx512dq(), "");
2310 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2311 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2312 emit_int8((unsigned char)0x98);
2313 emit_int8((unsigned char)(0xC0 | encode));
2314 }
2315
2316 // This instruction produces ZF or CF flags
2317 void Assembler::kortestwl(KRegister src1, KRegister src2) {
2318 assert(VM_Version::supports_evex(), "");
2319 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2320 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2321 emit_int8((unsigned char)0x98);
2322 emit_int8((unsigned char)(0xC0 | encode));
2323 }
2324
2325 // This instruction produces ZF or CF flags
2326 void Assembler::kortestdl(KRegister src1, KRegister src2) {
2327 assert(VM_Version::supports_avx512bw(), "");
2328 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2329 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2330 emit_int8((unsigned char)0x98);
2331 emit_int8((unsigned char)(0xC0 | encode));
2332 }
2333
2334 // This instruction produces ZF or CF flags
2335 void Assembler::kortestql(KRegister src1, KRegister src2) {
2336 assert(VM_Version::supports_avx512bw(), "");
2337 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2338 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2339 emit_int8((unsigned char)0x98);
2340 emit_int8((unsigned char)(0xC0 | encode));
2341 }
2342
2343 // This instruction produces ZF or CF flags
2344 void Assembler::ktestql(KRegister src1, KRegister src2) {
2345 assert(VM_Version::supports_avx512bw(), "");
2346 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2347 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2348 emit_int8((unsigned char)0x99);
2349 emit_int8((unsigned char)(0xC0 | encode));
2350 }
2351
2352 void Assembler::ktestq(KRegister src1, KRegister src2) {
2353 assert(VM_Version::supports_avx512bw(), "");
2354 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2355 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2356 emit_int8((unsigned char)0x99);
2357 emit_int8((unsigned char)(0xC0 | encode));
2358 }
2359
2360 void Assembler::ktestd(KRegister src1, KRegister src2) {
2361 assert(VM_Version::supports_avx512bw(), "");
2362 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2363 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2364 emit_int8((unsigned char)0x99);
2365 emit_int8((unsigned char)(0xC0 | encode));
2366 }
2367
2368 void Assembler::movb(Address dst, int imm8) {
2369 InstructionMark im(this);
2370 prefix(dst);
2371 emit_int8((unsigned char)0xC6);
2372 emit_operand(rax, dst, 1);
2373 emit_int8(imm8);
2374 }
2375
2376
2377 void Assembler::movb(Address dst, Register src) {
2378 assert(src->has_byte_register(), "must have byte register");
2379 InstructionMark im(this);
2380 prefix(dst, src, true);
2381 emit_int8((unsigned char)0x88);
2382 emit_operand(src, dst);
2383 }
2384
2385 void Assembler::movdl(XMMRegister dst, Register src) {
2386 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2387 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2388 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2389 emit_int8(0x6E);
2390 emit_int8((unsigned char)(0xC0 | encode));
2391 }
2392
2393 void Assembler::movdl(Register dst, XMMRegister src) {
2394 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2395 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2396 // swap src/dst to get correct prefix
2397 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2398 emit_int8(0x7E);
2399 emit_int8((unsigned char)(0xC0 | encode));
2400 }
2401
2402 void Assembler::movdl(XMMRegister dst, Address src) {
2403 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2404 InstructionMark im(this);
2405 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2406 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2407 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2408 emit_int8(0x6E);
2409 emit_operand(dst, src);
2410 }
2411
2412 void Assembler::movdl(Address dst, XMMRegister src) {
2413 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2414 InstructionMark im(this);
2415 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2416 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2417 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2418 emit_int8(0x7E);
2419 emit_operand(src, dst);
2420 }
2421
2422 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
2423 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2424 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2425 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2426 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2427 emit_int8(0x6F);
2428 emit_int8((unsigned char)(0xC0 | encode));
2429 }
2430
2431 void Assembler::movdqa(XMMRegister dst, Address src) {
2432 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2433 InstructionMark im(this);
2434 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2435 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2436 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2437 emit_int8(0x6F);
2438 emit_operand(dst, src);
2439 }
2440
2441 void Assembler::movdqu(XMMRegister dst, Address src) {
2442 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2443 InstructionMark im(this);
2444 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2445 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2446 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2447 emit_int8(0x6F);
2448 emit_operand(dst, src);
2449 }
2450
2451 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
2452 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2453 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2454 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2455 emit_int8(0x6F);
2456 emit_int8((unsigned char)(0xC0 | encode));
2457 }
2458
2459 void Assembler::movdqu(Address dst, XMMRegister src) {
2460 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2461 InstructionMark im(this);
2462 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2463 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2464 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2465 emit_int8(0x7F);
2466 emit_operand(src, dst);
2467 }
2468
2469 // Move Unaligned 256bit Vector
2470 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2471 assert(UseAVX > 0, "");
2472 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2473 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2474 emit_int8(0x6F);
2475 emit_int8((unsigned char)(0xC0 | encode));
2476 }
2477
2478 void Assembler::vmovdqu(XMMRegister dst, Address src) {
2479 assert(UseAVX > 0, "");
2480 InstructionMark im(this);
2481 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2482 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2483 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2484 emit_int8(0x6F);
2485 emit_operand(dst, src);
2486 }
2487
2488 void Assembler::vmovdqu(Address dst, XMMRegister src) {
2489 assert(UseAVX > 0, "");
2490 InstructionMark im(this);
2491 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2492 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2493 // swap src<->dst for encoding
2494 assert(src != xnoreg, "sanity");
2495 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2496 emit_int8(0x7F);
2497 emit_operand(src, dst);
2498 }
2499
2500 // Move Unaligned EVEX enabled Vector (programmable : 8,16,32,64)
2501 void Assembler::evmovdqub(XMMRegister dst, XMMRegister src, int vector_len) {
2502 assert(VM_Version::supports_evex(), "");
2503 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2504 attributes.set_is_evex_instruction();
2505 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2506 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2507 emit_int8(0x6F);
2508 emit_int8((unsigned char)(0xC0 | encode));
2509 }
2510
2511 void Assembler::evmovdqub(XMMRegister dst, Address src, int vector_len) {
2512 assert(VM_Version::supports_evex(), "");
2513 InstructionMark im(this);
2514 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2515 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2516 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2517 attributes.set_is_evex_instruction();
2518 vex_prefix(src, 0, dst->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2519 emit_int8(0x6F);
2520 emit_operand(dst, src);
2521 }
2522
2523 void Assembler::evmovdqub(Address dst, XMMRegister src, int vector_len) {
2524 assert(VM_Version::supports_evex(), "");
2525 assert(src != xnoreg, "sanity");
2526 InstructionMark im(this);
2527 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2528 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2529 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2530 attributes.set_is_evex_instruction();
2531 vex_prefix(dst, 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2532 emit_int8(0x7F);
2533 emit_operand(src, dst);
2534 }
2535
2536 void Assembler::evmovdqub(XMMRegister dst, KRegister mask, Address src, int vector_len) {
2537 assert(VM_Version::supports_avx512vlbw(), "");
2538 assert(is_vector_masking(), ""); // For stub code use only
2539 InstructionMark im(this);
2540 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
2541 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2542 attributes.set_embedded_opmask_register_specifier(mask);
2543 attributes.set_is_evex_instruction();
2544 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2545 emit_int8(0x6F);
2546 emit_operand(dst, src);
2547 }
2548
2549 void Assembler::evmovdquw(XMMRegister dst, Address src, int vector_len) {
2550 assert(VM_Version::supports_evex(), "");
2551 InstructionMark im(this);
2552 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2553 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2554 attributes.set_is_evex_instruction();
2555 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2556 vex_prefix(src, 0, dst->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2557 emit_int8(0x6F);
2558 emit_operand(dst, src);
2559 }
2560
2561 void Assembler::evmovdquw(XMMRegister dst, KRegister mask, Address src, int vector_len) {
2562 assert(is_vector_masking(), "");
2563 assert(VM_Version::supports_avx512vlbw(), "");
2564 InstructionMark im(this);
2565 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
2566 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2567 attributes.set_embedded_opmask_register_specifier(mask);
2568 attributes.set_is_evex_instruction();
2569 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2570 emit_int8(0x6F);
2571 emit_operand(dst, src);
2572 }
2573
2574 void Assembler::evmovdquw(Address dst, XMMRegister src, int vector_len) {
2575 assert(VM_Version::supports_evex(), "");
2576 assert(src != xnoreg, "sanity");
2577 InstructionMark im(this);
2578 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2579 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2580 attributes.set_is_evex_instruction();
2581 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2582 vex_prefix(dst, 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2583 emit_int8(0x7F);
2584 emit_operand(src, dst);
2585 }
2586
2587 void Assembler::evmovdquw(Address dst, KRegister mask, XMMRegister src, int vector_len) {
2588 assert(VM_Version::supports_avx512vlbw(), "");
2589 assert(src != xnoreg, "sanity");
2590 InstructionMark im(this);
2591 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2592 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2593 attributes.set_embedded_opmask_register_specifier(mask);
2594 attributes.set_is_evex_instruction();
2595 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2596 emit_int8(0x7F);
2597 emit_operand(src, dst);
2598 }
2599
2600 void Assembler::evmovdqul(XMMRegister dst, XMMRegister src, int vector_len) {
2601 assert(VM_Version::supports_evex(), "");
2602 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2603 attributes.set_is_evex_instruction();
2604 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2605 emit_int8(0x6F);
2606 emit_int8((unsigned char)(0xC0 | encode));
2607 }
2608
2609 void Assembler::evmovdqul(XMMRegister dst, Address src, int vector_len) {
2610 assert(VM_Version::supports_evex(), "");
2611 InstructionMark im(this);
2612 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false , /* uses_vl */ true);
2613 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2614 attributes.set_is_evex_instruction();
2615 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2616 emit_int8(0x6F);
2617 emit_operand(dst, src);
2618 }
2619
2620 void Assembler::evmovdqul(Address dst, XMMRegister src, int vector_len) {
2621 assert(VM_Version::supports_evex(), "");
2622 assert(src != xnoreg, "sanity");
2623 InstructionMark im(this);
2624 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2625 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2626 attributes.set_is_evex_instruction();
2627 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2628 emit_int8(0x7F);
2629 emit_operand(src, dst);
2630 }
2631
2632 void Assembler::evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) {
2633 assert(VM_Version::supports_evex(), "");
2634 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2635 attributes.set_is_evex_instruction();
2636 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2637 emit_int8(0x6F);
2638 emit_int8((unsigned char)(0xC0 | encode));
2639 }
2640
2641 void Assembler::evmovdquq(XMMRegister dst, Address src, int vector_len) {
2642 assert(VM_Version::supports_evex(), "");
2643 InstructionMark im(this);
2644 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2645 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2646 attributes.set_is_evex_instruction();
2647 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2648 emit_int8(0x6F);
2649 emit_operand(dst, src);
2650 }
2651
2652 void Assembler::evmovdquq(Address dst, XMMRegister src, int vector_len) {
2653 assert(VM_Version::supports_evex(), "");
2654 assert(src != xnoreg, "sanity");
2655 InstructionMark im(this);
2656 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2657 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2658 attributes.set_is_evex_instruction();
2659 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2660 emit_int8(0x7F);
2661 emit_operand(src, dst);
2662 }
2663
2664 // Uses zero extension on 64bit
2665
2666 void Assembler::movl(Register dst, int32_t imm32) {
2667 int encode = prefix_and_encode(dst->encoding());
2668 emit_int8((unsigned char)(0xB8 | encode));
2669 emit_int32(imm32);
2670 }
2671
2672 void Assembler::movl(Register dst, Register src) {
2673 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2674 emit_int8((unsigned char)0x8B);
2675 emit_int8((unsigned char)(0xC0 | encode));
2676 }
2677
2678 void Assembler::movl(Register dst, Address src) {
2679 InstructionMark im(this);
2680 prefix(src, dst);
2681 emit_int8((unsigned char)0x8B);
2682 emit_operand(dst, src);
2683 }
2684
2685 void Assembler::movl(Address dst, int32_t imm32) {
2686 InstructionMark im(this);
2687 prefix(dst);
2688 emit_int8((unsigned char)0xC7);
2689 emit_operand(rax, dst, 4);
2690 emit_int32(imm32);
2691 }
2692
2693 void Assembler::movl(Address dst, Register src) {
2694 InstructionMark im(this);
2695 prefix(dst, src);
2696 emit_int8((unsigned char)0x89);
2697 emit_operand(src, dst);
2698 }
2699
2700 // New cpus require to use movsd and movss to avoid partial register stall
2701 // when loading from memory. But for old Opteron use movlpd instead of movsd.
2702 // The selection is done in MacroAssembler::movdbl() and movflt().
2703 void Assembler::movlpd(XMMRegister dst, Address src) {
2704 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2705 InstructionMark im(this);
2706 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2707 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2708 attributes.set_rex_vex_w_reverted();
2709 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2710 emit_int8(0x12);
2711 emit_operand(dst, src);
2712 }
2713
2714 void Assembler::movq( MMXRegister dst, Address src ) {
2715 assert( VM_Version::supports_mmx(), "" );
2716 emit_int8(0x0F);
2717 emit_int8(0x6F);
2718 emit_operand(dst, src);
2719 }
2720
2721 void Assembler::movq( Address dst, MMXRegister src ) {
2722 assert( VM_Version::supports_mmx(), "" );
2723 emit_int8(0x0F);
2724 emit_int8(0x7F);
2725 // workaround gcc (3.2.1-7a) bug
2726 // In that version of gcc with only an emit_operand(MMX, Address)
2727 // gcc will tail jump and try and reverse the parameters completely
2728 // obliterating dst in the process. By having a version available
2729 // that doesn't need to swap the args at the tail jump the bug is
2730 // avoided.
2731 emit_operand(dst, src);
2732 }
2733
2734 void Assembler::movq(XMMRegister dst, Address src) {
2735 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2736 InstructionMark im(this);
2737 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2738 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2739 attributes.set_rex_vex_w_reverted();
2740 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2741 emit_int8(0x7E);
2742 emit_operand(dst, src);
2743 }
2744
2745 void Assembler::movq(Address dst, XMMRegister src) {
2746 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2747 InstructionMark im(this);
2748 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2749 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2750 attributes.set_rex_vex_w_reverted();
2751 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2752 emit_int8((unsigned char)0xD6);
2753 emit_operand(src, dst);
2754 }
2755
2756 void Assembler::movsbl(Register dst, Address src) { // movsxb
2757 InstructionMark im(this);
2758 prefix(src, dst);
2759 emit_int8(0x0F);
2760 emit_int8((unsigned char)0xBE);
2761 emit_operand(dst, src);
2762 }
2763
2764 void Assembler::movsbl(Register dst, Register src) { // movsxb
2765 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2766 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
2767 emit_int8(0x0F);
2768 emit_int8((unsigned char)0xBE);
2769 emit_int8((unsigned char)(0xC0 | encode));
2770 }
2771
2772 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
2773 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2774 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2775 attributes.set_rex_vex_w_reverted();
2776 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2777 emit_int8(0x10);
2778 emit_int8((unsigned char)(0xC0 | encode));
2779 }
2780
2781 void Assembler::movsd(XMMRegister dst, Address src) {
2782 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2783 InstructionMark im(this);
2784 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2785 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2786 attributes.set_rex_vex_w_reverted();
2787 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2788 emit_int8(0x10);
2789 emit_operand(dst, src);
2790 }
2791
2792 void Assembler::movsd(Address dst, XMMRegister src) {
2793 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2794 InstructionMark im(this);
2795 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2796 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2797 attributes.set_rex_vex_w_reverted();
2798 simd_prefix(src, xnoreg, dst, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2799 emit_int8(0x11);
2800 emit_operand(src, dst);
2801 }
2802
2803 void Assembler::movss(XMMRegister dst, XMMRegister src) {
2804 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2805 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2806 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2807 emit_int8(0x10);
2808 emit_int8((unsigned char)(0xC0 | encode));
2809 }
2810
2811 void Assembler::movss(XMMRegister dst, Address src) {
2812 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2813 InstructionMark im(this);
2814 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2815 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2816 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2817 emit_int8(0x10);
2818 emit_operand(dst, src);
2819 }
2820
2821 void Assembler::movss(Address dst, XMMRegister src) {
2822 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2823 InstructionMark im(this);
2824 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2825 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2826 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2827 emit_int8(0x11);
2828 emit_operand(src, dst);
2829 }
2830
2831 void Assembler::movswl(Register dst, Address src) { // movsxw
2832 InstructionMark im(this);
2833 prefix(src, dst);
2834 emit_int8(0x0F);
2835 emit_int8((unsigned char)0xBF);
2836 emit_operand(dst, src);
2837 }
2838
2839 void Assembler::movswl(Register dst, Register src) { // movsxw
2840 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2841 emit_int8(0x0F);
2842 emit_int8((unsigned char)0xBF);
2843 emit_int8((unsigned char)(0xC0 | encode));
2844 }
2845
2846 void Assembler::movw(Address dst, int imm16) {
2847 InstructionMark im(this);
2848
2849 emit_int8(0x66); // switch to 16-bit mode
2850 prefix(dst);
2851 emit_int8((unsigned char)0xC7);
2852 emit_operand(rax, dst, 2);
2853 emit_int16(imm16);
2854 }
2855
2856 void Assembler::movw(Register dst, Address src) {
2857 InstructionMark im(this);
2858 emit_int8(0x66);
2859 prefix(src, dst);
2860 emit_int8((unsigned char)0x8B);
2861 emit_operand(dst, src);
2862 }
2863
2864 void Assembler::movw(Address dst, Register src) {
2865 InstructionMark im(this);
2866 emit_int8(0x66);
2867 prefix(dst, src);
2868 emit_int8((unsigned char)0x89);
2869 emit_operand(src, dst);
2870 }
2871
2872 void Assembler::movzbl(Register dst, Address src) { // movzxb
2873 InstructionMark im(this);
2874 prefix(src, dst);
2875 emit_int8(0x0F);
2876 emit_int8((unsigned char)0xB6);
2877 emit_operand(dst, src);
2878 }
2879
2880 void Assembler::movzbl(Register dst, Register src) { // movzxb
2881 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2882 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
2883 emit_int8(0x0F);
2884 emit_int8((unsigned char)0xB6);
2885 emit_int8(0xC0 | encode);
2886 }
2887
2888 void Assembler::movzwl(Register dst, Address src) { // movzxw
2889 InstructionMark im(this);
2890 prefix(src, dst);
2891 emit_int8(0x0F);
2892 emit_int8((unsigned char)0xB7);
2893 emit_operand(dst, src);
2894 }
2895
2896 void Assembler::movzwl(Register dst, Register src) { // movzxw
2897 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2898 emit_int8(0x0F);
2899 emit_int8((unsigned char)0xB7);
2900 emit_int8(0xC0 | encode);
2901 }
2902
2903 void Assembler::mull(Address src) {
2904 InstructionMark im(this);
2905 prefix(src);
2906 emit_int8((unsigned char)0xF7);
2907 emit_operand(rsp, src);
2908 }
2909
2910 void Assembler::mull(Register src) {
2911 int encode = prefix_and_encode(src->encoding());
2912 emit_int8((unsigned char)0xF7);
2913 emit_int8((unsigned char)(0xE0 | encode));
2914 }
2915
2916 void Assembler::mulsd(XMMRegister dst, Address src) {
2917 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2918 InstructionMark im(this);
2919 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2920 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2921 attributes.set_rex_vex_w_reverted();
2922 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2923 emit_int8(0x59);
2924 emit_operand(dst, src);
2925 }
2926
2927 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
2928 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2929 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2930 attributes.set_rex_vex_w_reverted();
2931 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2932 emit_int8(0x59);
2933 emit_int8((unsigned char)(0xC0 | encode));
2934 }
2935
2936 void Assembler::mulss(XMMRegister dst, Address src) {
2937 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2938 InstructionMark im(this);
2939 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2940 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2941 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2942 emit_int8(0x59);
2943 emit_operand(dst, src);
2944 }
2945
2946 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
2947 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2948 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2949 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2950 emit_int8(0x59);
2951 emit_int8((unsigned char)(0xC0 | encode));
2952 }
2953
2954 void Assembler::negl(Register dst) {
2955 int encode = prefix_and_encode(dst->encoding());
2956 emit_int8((unsigned char)0xF7);
2957 emit_int8((unsigned char)(0xD8 | encode));
2958 }
2959
2960 void Assembler::nop(int i) {
2961 #ifdef ASSERT
2962 assert(i > 0, " ");
2963 // The fancy nops aren't currently recognized by debuggers making it a
2964 // pain to disassemble code while debugging. If asserts are on clearly
2965 // speed is not an issue so simply use the single byte traditional nop
2966 // to do alignment.
2967
2968 for (; i > 0 ; i--) emit_int8((unsigned char)0x90);
2969 return;
2970
2971 #endif // ASSERT
2972
2973 if (UseAddressNop && VM_Version::is_intel()) {
2974 //
2975 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel
2976 // 1: 0x90
2977 // 2: 0x66 0x90
2978 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2979 // 4: 0x0F 0x1F 0x40 0x00
2980 // 5: 0x0F 0x1F 0x44 0x00 0x00
2981 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2982 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2983 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2984 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2985 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2986 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2987
2988 // The rest coding is Intel specific - don't use consecutive address nops
2989
2990 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2991 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2992 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2993 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2994
2995 while(i >= 15) {
2996 // For Intel don't generate consecutive addess nops (mix with regular nops)
2997 i -= 15;
2998 emit_int8(0x66); // size prefix
2999 emit_int8(0x66); // size prefix
3000 emit_int8(0x66); // size prefix
3001 addr_nop_8();
3002 emit_int8(0x66); // size prefix
3003 emit_int8(0x66); // size prefix
3004 emit_int8(0x66); // size prefix
3005 emit_int8((unsigned char)0x90);
3006 // nop
3007 }
3008 switch (i) {
3009 case 14:
3010 emit_int8(0x66); // size prefix
3011 case 13:
3012 emit_int8(0x66); // size prefix
3013 case 12:
3014 addr_nop_8();
3015 emit_int8(0x66); // size prefix
3016 emit_int8(0x66); // size prefix
3017 emit_int8(0x66); // size prefix
3018 emit_int8((unsigned char)0x90);
3019 // nop
3020 break;
3021 case 11:
3022 emit_int8(0x66); // size prefix
3023 case 10:
3024 emit_int8(0x66); // size prefix
3025 case 9:
3026 emit_int8(0x66); // size prefix
3027 case 8:
3028 addr_nop_8();
3029 break;
3030 case 7:
3031 addr_nop_7();
3032 break;
3033 case 6:
3034 emit_int8(0x66); // size prefix
3035 case 5:
3036 addr_nop_5();
3037 break;
3038 case 4:
3039 addr_nop_4();
3040 break;
3041 case 3:
3042 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
3043 emit_int8(0x66); // size prefix
3044 case 2:
3045 emit_int8(0x66); // size prefix
3046 case 1:
3047 emit_int8((unsigned char)0x90);
3048 // nop
3049 break;
3050 default:
3051 assert(i == 0, " ");
3052 }
3053 return;
3054 }
3055 if (UseAddressNop && VM_Version::is_amd()) {
3056 //
3057 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD.
3058 // 1: 0x90
3059 // 2: 0x66 0x90
3060 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
3061 // 4: 0x0F 0x1F 0x40 0x00
3062 // 5: 0x0F 0x1F 0x44 0x00 0x00
3063 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
3064 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3065 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3066 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3067 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3068 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3069
3070 // The rest coding is AMD specific - use consecutive address nops
3071
3072 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
3073 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
3074 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3075 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3076 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3077 // Size prefixes (0x66) are added for larger sizes
3078
3079 while(i >= 22) {
3080 i -= 11;
3081 emit_int8(0x66); // size prefix
3082 emit_int8(0x66); // size prefix
3083 emit_int8(0x66); // size prefix
3084 addr_nop_8();
3085 }
3086 // Generate first nop for size between 21-12
3087 switch (i) {
3088 case 21:
3089 i -= 1;
3090 emit_int8(0x66); // size prefix
3091 case 20:
3092 case 19:
3093 i -= 1;
3094 emit_int8(0x66); // size prefix
3095 case 18:
3096 case 17:
3097 i -= 1;
3098 emit_int8(0x66); // size prefix
3099 case 16:
3100 case 15:
3101 i -= 8;
3102 addr_nop_8();
3103 break;
3104 case 14:
3105 case 13:
3106 i -= 7;
3107 addr_nop_7();
3108 break;
3109 case 12:
3110 i -= 6;
3111 emit_int8(0x66); // size prefix
3112 addr_nop_5();
3113 break;
3114 default:
3115 assert(i < 12, " ");
3116 }
3117
3118 // Generate second nop for size between 11-1
3119 switch (i) {
3120 case 11:
3121 emit_int8(0x66); // size prefix
3122 case 10:
3123 emit_int8(0x66); // size prefix
3124 case 9:
3125 emit_int8(0x66); // size prefix
3126 case 8:
3127 addr_nop_8();
3128 break;
3129 case 7:
3130 addr_nop_7();
3131 break;
3132 case 6:
3133 emit_int8(0x66); // size prefix
3134 case 5:
3135 addr_nop_5();
3136 break;
3137 case 4:
3138 addr_nop_4();
3139 break;
3140 case 3:
3141 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
3142 emit_int8(0x66); // size prefix
3143 case 2:
3144 emit_int8(0x66); // size prefix
3145 case 1:
3146 emit_int8((unsigned char)0x90);
3147 // nop
3148 break;
3149 default:
3150 assert(i == 0, " ");
3151 }
3152 return;
3153 }
3154
3155 // Using nops with size prefixes "0x66 0x90".
3156 // From AMD Optimization Guide:
3157 // 1: 0x90
3158 // 2: 0x66 0x90
3159 // 3: 0x66 0x66 0x90
3160 // 4: 0x66 0x66 0x66 0x90
3161 // 5: 0x66 0x66 0x90 0x66 0x90
3162 // 6: 0x66 0x66 0x90 0x66 0x66 0x90
3163 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90
3164 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90
3165 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
3166 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
3167 //
3168 while(i > 12) {
3169 i -= 4;
3170 emit_int8(0x66); // size prefix
3171 emit_int8(0x66);
3172 emit_int8(0x66);
3173 emit_int8((unsigned char)0x90);
3174 // nop
3175 }
3176 // 1 - 12 nops
3177 if(i > 8) {
3178 if(i > 9) {
3179 i -= 1;
3180 emit_int8(0x66);
3181 }
3182 i -= 3;
3183 emit_int8(0x66);
3184 emit_int8(0x66);
3185 emit_int8((unsigned char)0x90);
3186 }
3187 // 1 - 8 nops
3188 if(i > 4) {
3189 if(i > 6) {
3190 i -= 1;
3191 emit_int8(0x66);
3192 }
3193 i -= 3;
3194 emit_int8(0x66);
3195 emit_int8(0x66);
3196 emit_int8((unsigned char)0x90);
3197 }
3198 switch (i) {
3199 case 4:
3200 emit_int8(0x66);
3201 case 3:
3202 emit_int8(0x66);
3203 case 2:
3204 emit_int8(0x66);
3205 case 1:
3206 emit_int8((unsigned char)0x90);
3207 break;
3208 default:
3209 assert(i == 0, " ");
3210 }
3211 }
3212
3213 void Assembler::notl(Register dst) {
3214 int encode = prefix_and_encode(dst->encoding());
3215 emit_int8((unsigned char)0xF7);
3216 emit_int8((unsigned char)(0xD0 | encode));
3217 }
3218
3219 void Assembler::orl(Address dst, int32_t imm32) {
3220 InstructionMark im(this);
3221 prefix(dst);
3222 emit_arith_operand(0x81, rcx, dst, imm32);
3223 }
3224
3225 void Assembler::orl(Register dst, int32_t imm32) {
3226 prefix(dst);
3227 emit_arith(0x81, 0xC8, dst, imm32);
3228 }
3229
3230 void Assembler::orl(Register dst, Address src) {
3231 InstructionMark im(this);
3232 prefix(src, dst);
3233 emit_int8(0x0B);
3234 emit_operand(dst, src);
3235 }
3236
3237 void Assembler::orl(Register dst, Register src) {
3238 (void) prefix_and_encode(dst->encoding(), src->encoding());
3239 emit_arith(0x0B, 0xC0, dst, src);
3240 }
3241
3242 void Assembler::orl(Address dst, Register src) {
3243 InstructionMark im(this);
3244 prefix(dst, src);
3245 emit_int8(0x09);
3246 emit_operand(src, dst);
3247 }
3248
3249 void Assembler::packuswb(XMMRegister dst, Address src) {
3250 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3251 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3252 InstructionMark im(this);
3253 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3254 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3255 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3256 emit_int8(0x67);
3257 emit_operand(dst, src);
3258 }
3259
3260 void Assembler::packuswb(XMMRegister dst, XMMRegister src) {
3261 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3262 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3263 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3264 emit_int8(0x67);
3265 emit_int8((unsigned char)(0xC0 | encode));
3266 }
3267
3268 void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3269 assert(UseAVX > 0, "some form of AVX must be enabled");
3270 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3271 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3272 emit_int8(0x67);
3273 emit_int8((unsigned char)(0xC0 | encode));
3274 }
3275
3276 void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len) {
3277 assert(VM_Version::supports_avx2(), "");
3278 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3279 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3280 emit_int8(0x00);
3281 emit_int8(0xC0 | encode);
3282 emit_int8(imm8);
3283 }
3284
3285 void Assembler::vperm2i128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) {
3286 assert(VM_Version::supports_avx2(), "");
3287 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3288 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3289 emit_int8(0x46);
3290 emit_int8(0xC0 | encode);
3291 emit_int8(imm8);
3292 }
3293
3294
3295 void Assembler::pause() {
3296 emit_int8((unsigned char)0xF3);
3297 emit_int8((unsigned char)0x90);
3298 }
3299
3300 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3301 assert(VM_Version::supports_sse4_2(), "");
3302 InstructionMark im(this);
3303 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3304 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3305 emit_int8(0x61);
3306 emit_operand(dst, src);
3307 emit_int8(imm8);
3308 }
3309
3310 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3311 assert(VM_Version::supports_sse4_2(), "");
3312 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3313 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3314 emit_int8(0x61);
3315 emit_int8((unsigned char)(0xC0 | encode));
3316 emit_int8(imm8);
3317 }
3318
3319 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3320 void Assembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
3321 assert(VM_Version::supports_sse2(), "");
3322 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3323 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3324 emit_int8(0x74);
3325 emit_int8((unsigned char)(0xC0 | encode));
3326 }
3327
3328 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3329 void Assembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3330 assert(VM_Version::supports_avx(), "");
3331 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3332 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3333 emit_int8(0x74);
3334 emit_int8((unsigned char)(0xC0 | encode));
3335 }
3336
3337 // In this context, kdst is written the mask used to process the equal components
3338 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3339 assert(VM_Version::supports_avx512bw(), "");
3340 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3341 attributes.set_is_evex_instruction();
3342 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3343 emit_int8(0x74);
3344 emit_int8((unsigned char)(0xC0 | encode));
3345 }
3346
3347 void Assembler::evpcmpgtb(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3348 assert(VM_Version::supports_avx512vlbw(), "");
3349 InstructionMark im(this);
3350 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3351 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3352 attributes.set_is_evex_instruction();
3353 int dst_enc = kdst->encoding();
3354 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3355 emit_int8(0x64);
3356 emit_operand(as_Register(dst_enc), src);
3357 }
3358
3359 void Assembler::evpcmpgtb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len) {
3360 assert(is_vector_masking(), "");
3361 assert(VM_Version::supports_avx512vlbw(), "");
3362 InstructionMark im(this);
3363 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
3364 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3365 attributes.set_embedded_opmask_register_specifier(mask);
3366 attributes.set_is_evex_instruction();
3367 int dst_enc = kdst->encoding();
3368 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3369 emit_int8(0x64);
3370 emit_operand(as_Register(dst_enc), src);
3371 }
3372
3373 void Assembler::evpcmpuw(KRegister kdst, XMMRegister nds, XMMRegister src, ComparisonPredicate vcc, int vector_len) {
3374 assert(VM_Version::supports_avx512vlbw(), "");
3375 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3376 attributes.set_is_evex_instruction();
3377 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3378 emit_int8(0x3E);
3379 emit_int8((unsigned char)(0xC0 | encode));
3380 emit_int8(vcc);
3381 }
3382
3383 void Assembler::evpcmpuw(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, ComparisonPredicate vcc, int vector_len) {
3384 assert(is_vector_masking(), "");
3385 assert(VM_Version::supports_avx512vlbw(), "");
3386 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
3387 attributes.set_embedded_opmask_register_specifier(mask);
3388 attributes.set_is_evex_instruction();
3389 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3390 emit_int8(0x3E);
3391 emit_int8((unsigned char)(0xC0 | encode));
3392 emit_int8(vcc);
3393 }
3394
3395 void Assembler::evpcmpuw(KRegister kdst, XMMRegister nds, Address src, ComparisonPredicate vcc, int vector_len) {
3396 assert(VM_Version::supports_avx512vlbw(), "");
3397 InstructionMark im(this);
3398 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3399 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3400 attributes.set_is_evex_instruction();
3401 int dst_enc = kdst->encoding();
3402 vex_prefix(src, nds->encoding(), kdst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3403 emit_int8(0x3E);
3404 emit_operand(as_Register(dst_enc), src);
3405 emit_int8(vcc);
3406 }
3407
3408 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3409 assert(VM_Version::supports_avx512bw(), "");
3410 InstructionMark im(this);
3411 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3412 attributes.set_is_evex_instruction();
3413 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3414 int dst_enc = kdst->encoding();
3415 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3416 emit_int8(0x74);
3417 emit_operand(as_Register(dst_enc), src);
3418 }
3419
3420 void Assembler::evpcmpeqb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len) {
3421 assert(VM_Version::supports_avx512vlbw(), "");
3422 assert(is_vector_masking(), ""); // For stub code use only
3423 InstructionMark im(this);
3424 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_reg_mask */ false, /* uses_vl */ false);
3425 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3426 attributes.set_embedded_opmask_register_specifier(mask);
3427 attributes.set_is_evex_instruction();
3428 vex_prefix(src, nds->encoding(), kdst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3429 emit_int8(0x74);
3430 emit_operand(as_Register(kdst->encoding()), src);
3431 }
3432
3433 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3434 void Assembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3435 assert(VM_Version::supports_sse2(), "");
3436 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3437 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3438 emit_int8(0x75);
3439 emit_int8((unsigned char)(0xC0 | encode));
3440 }
3441
3442 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3443 void Assembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3444 assert(VM_Version::supports_avx(), "");
3445 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3446 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3447 emit_int8(0x75);
3448 emit_int8((unsigned char)(0xC0 | encode));
3449 }
3450
3451 // In this context, kdst is written the mask used to process the equal components
3452 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3453 assert(VM_Version::supports_avx512bw(), "");
3454 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3455 attributes.set_is_evex_instruction();
3456 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3457 emit_int8(0x75);
3458 emit_int8((unsigned char)(0xC0 | encode));
3459 }
3460
3461 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3462 assert(VM_Version::supports_avx512bw(), "");
3463 InstructionMark im(this);
3464 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3465 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3466 attributes.set_is_evex_instruction();
3467 int dst_enc = kdst->encoding();
3468 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3469 emit_int8(0x75);
3470 emit_operand(as_Register(dst_enc), src);
3471 }
3472
3473 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3474 void Assembler::pcmpeqd(XMMRegister dst, XMMRegister src) {
3475 assert(VM_Version::supports_sse2(), "");
3476 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3477 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3478 emit_int8(0x76);
3479 emit_int8((unsigned char)(0xC0 | encode));
3480 }
3481
3482 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3483 void Assembler::vpcmpeqd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3484 assert(VM_Version::supports_avx(), "");
3485 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3486 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3487 emit_int8(0x76);
3488 emit_int8((unsigned char)(0xC0 | encode));
3489 }
3490
3491 // In this context, kdst is written the mask used to process the equal components
3492 void Assembler::evpcmpeqd(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3493 assert(VM_Version::supports_evex(), "");
3494 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3495 attributes.set_is_evex_instruction();
3496 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3497 emit_int8(0x76);
3498 emit_int8((unsigned char)(0xC0 | encode));
3499 }
3500
3501 void Assembler::evpcmpeqd(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3502 assert(VM_Version::supports_evex(), "");
3503 InstructionMark im(this);
3504 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3505 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3506 attributes.set_is_evex_instruction();
3507 int dst_enc = kdst->encoding();
3508 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3509 emit_int8(0x76);
3510 emit_operand(as_Register(dst_enc), src);
3511 }
3512
3513 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3514 void Assembler::pcmpeqq(XMMRegister dst, XMMRegister src) {
3515 assert(VM_Version::supports_sse4_1(), "");
3516 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3517 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3518 emit_int8(0x29);
3519 emit_int8((unsigned char)(0xC0 | encode));
3520 }
3521
3522 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3523 void Assembler::vpcmpeqq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3524 assert(VM_Version::supports_avx(), "");
3525 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3526 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3527 emit_int8(0x29);
3528 emit_int8((unsigned char)(0xC0 | encode));
3529 }
3530
3531 // In this context, kdst is written the mask used to process the equal components
3532 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3533 assert(VM_Version::supports_evex(), "");
3534 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3535 attributes.set_is_evex_instruction();
3536 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3537 emit_int8(0x29);
3538 emit_int8((unsigned char)(0xC0 | encode));
3539 }
3540
3541 // In this context, kdst is written the mask used to process the equal components
3542 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3543 assert(VM_Version::supports_evex(), "");
3544 InstructionMark im(this);
3545 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3546 attributes.set_is_evex_instruction();
3547 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
3548 int dst_enc = kdst->encoding();
3549 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3550 emit_int8(0x29);
3551 emit_operand(as_Register(dst_enc), src);
3552 }
3553
3554 void Assembler::pmovmskb(Register dst, XMMRegister src) {
3555 assert(VM_Version::supports_sse2(), "");
3556 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3557 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3558 emit_int8((unsigned char)0xD7);
3559 emit_int8((unsigned char)(0xC0 | encode));
3560 }
3561
3562 void Assembler::vpmovmskb(Register dst, XMMRegister src) {
3563 assert(VM_Version::supports_avx2(), "");
3564 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3565 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3566 emit_int8((unsigned char)0xD7);
3567 emit_int8((unsigned char)(0xC0 | encode));
3568 }
3569
3570 void Assembler::pextrd(Register dst, XMMRegister src, int imm8) {
3571 assert(VM_Version::supports_sse4_1(), "");
3572 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3573 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3574 emit_int8(0x16);
3575 emit_int8((unsigned char)(0xC0 | encode));
3576 emit_int8(imm8);
3577 }
3578
3579 void Assembler::pextrd(Address dst, XMMRegister src, int imm8) {
3580 assert(VM_Version::supports_sse4_1(), "");
3581 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3582 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3583 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3584 emit_int8(0x16);
3585 emit_operand(src, dst);
3586 emit_int8(imm8);
3587 }
3588
3589 void Assembler::pextrq(Register dst, XMMRegister src, int imm8) {
3590 assert(VM_Version::supports_sse4_1(), "");
3591 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3592 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3593 emit_int8(0x16);
3594 emit_int8((unsigned char)(0xC0 | encode));
3595 emit_int8(imm8);
3596 }
3597
3598 void Assembler::pextrq(Address dst, XMMRegister src, int imm8) {
3599 assert(VM_Version::supports_sse4_1(), "");
3600 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3601 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3602 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3603 emit_int8(0x16);
3604 emit_operand(src, dst);
3605 emit_int8(imm8);
3606 }
3607
3608 void Assembler::pextrw(Register dst, XMMRegister src, int imm8) {
3609 assert(VM_Version::supports_sse2(), "");
3610 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3611 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3612 emit_int8((unsigned char)0xC5);
3613 emit_int8((unsigned char)(0xC0 | encode));
3614 emit_int8(imm8);
3615 }
3616
3617 void Assembler::pextrw(Address dst, XMMRegister src, int imm8) {
3618 assert(VM_Version::supports_sse4_1(), "");
3619 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3620 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
3621 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3622 emit_int8((unsigned char)0x15);
3623 emit_operand(src, dst);
3624 emit_int8(imm8);
3625 }
3626
3627 void Assembler::pextrb(Address dst, XMMRegister src, int imm8) {
3628 assert(VM_Version::supports_sse4_1(), "");
3629 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3630 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
3631 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3632 emit_int8(0x14);
3633 emit_operand(src, dst);
3634 emit_int8(imm8);
3635 }
3636
3637 void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) {
3638 assert(VM_Version::supports_sse4_1(), "");
3639 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3640 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3641 emit_int8(0x22);
3642 emit_int8((unsigned char)(0xC0 | encode));
3643 emit_int8(imm8);
3644 }
3645
3646 void Assembler::pinsrd(XMMRegister dst, Address src, int imm8) {
3647 assert(VM_Version::supports_sse4_1(), "");
3648 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3649 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3650 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3651 emit_int8(0x22);
3652 emit_operand(dst,src);
3653 emit_int8(imm8);
3654 }
3655
3656 void Assembler::pinsrq(XMMRegister dst, Register src, int imm8) {
3657 assert(VM_Version::supports_sse4_1(), "");
3658 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3659 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3660 emit_int8(0x22);
3661 emit_int8((unsigned char)(0xC0 | encode));
3662 emit_int8(imm8);
3663 }
3664
3665 void Assembler::pinsrq(XMMRegister dst, Address src, int imm8) {
3666 assert(VM_Version::supports_sse4_1(), "");
3667 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3668 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3669 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3670 emit_int8(0x22);
3671 emit_operand(dst, src);
3672 emit_int8(imm8);
3673 }
3674
3675 void Assembler::pinsrw(XMMRegister dst, Register src, int imm8) {
3676 assert(VM_Version::supports_sse2(), "");
3677 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3678 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3679 emit_int8((unsigned char)0xC4);
3680 emit_int8((unsigned char)(0xC0 | encode));
3681 emit_int8(imm8);
3682 }
3683
3684 void Assembler::pinsrw(XMMRegister dst, Address src, int imm8) {
3685 assert(VM_Version::supports_sse2(), "");
3686 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3687 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
3688 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3689 emit_int8((unsigned char)0xC4);
3690 emit_operand(dst, src);
3691 emit_int8(imm8);
3692 }
3693
3694 void Assembler::pinsrb(XMMRegister dst, Address src, int imm8) {
3695 assert(VM_Version::supports_sse4_1(), "");
3696 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3697 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
3698 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3699 emit_int8(0x20);
3700 emit_operand(dst, src);
3701 emit_int8(imm8);
3702 }
3703
3704 void Assembler::pmovzxbw(XMMRegister dst, Address src) {
3705 assert(VM_Version::supports_sse4_1(), "");
3706 InstructionMark im(this);
3707 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3708 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3709 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3710 emit_int8(0x30);
3711 emit_operand(dst, src);
3712 }
3713
3714 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3715 assert(VM_Version::supports_sse4_1(), "");
3716 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3717 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3718 emit_int8(0x30);
3719 emit_int8((unsigned char)(0xC0 | encode));
3720 }
3721
3722 void Assembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
3723 assert(VM_Version::supports_avx(), "");
3724 InstructionMark im(this);
3725 assert(dst != xnoreg, "sanity");
3726 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3727 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3728 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3729 emit_int8(0x30);
3730 emit_operand(dst, src);
3731 }
3732
3733 void Assembler::evpmovzxbw(XMMRegister dst, KRegister mask, Address src, int vector_len) {
3734 assert(is_vector_masking(), "");
3735 assert(VM_Version::supports_avx512vlbw(), "");
3736 assert(dst != xnoreg, "sanity");
3737 InstructionMark im(this);
3738 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
3739 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3740 attributes.set_embedded_opmask_register_specifier(mask);
3741 attributes.set_is_evex_instruction();
3742 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3743 emit_int8(0x30);
3744 emit_operand(dst, src);
3745 }
3746
3747 void Assembler::evpmovwb(Address dst, XMMRegister src, int vector_len) {
3748 assert(VM_Version::supports_avx512vlbw(), "");
3749 assert(src != xnoreg, "sanity");
3750 InstructionMark im(this);
3751 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3752 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3753 attributes.set_is_evex_instruction();
3754 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
3755 emit_int8(0x30);
3756 emit_operand(src, dst);
3757 }
3758
3759 void Assembler::evpmovwb(Address dst, KRegister mask, XMMRegister src, int vector_len) {
3760 assert(is_vector_masking(), "");
3761 assert(VM_Version::supports_avx512vlbw(), "");
3762 assert(src != xnoreg, "sanity");
3763 InstructionMark im(this);
3764 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
3765 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3766 attributes.set_embedded_opmask_register_specifier(mask);
3767 attributes.set_is_evex_instruction();
3768 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
3769 emit_int8(0x30);
3770 emit_operand(src, dst);
3771 }
3772
3773 // generic
3774 void Assembler::pop(Register dst) {
3775 int encode = prefix_and_encode(dst->encoding());
3776 emit_int8(0x58 | encode);
3777 }
3778
3779 void Assembler::popcntl(Register dst, Address src) {
3780 assert(VM_Version::supports_popcnt(), "must support");
3781 InstructionMark im(this);
3782 emit_int8((unsigned char)0xF3);
3783 prefix(src, dst);
3784 emit_int8(0x0F);
3785 emit_int8((unsigned char)0xB8);
3786 emit_operand(dst, src);
3787 }
3788
3789 void Assembler::popcntl(Register dst, Register src) {
3790 assert(VM_Version::supports_popcnt(), "must support");
3791 emit_int8((unsigned char)0xF3);
3792 int encode = prefix_and_encode(dst->encoding(), src->encoding());
3793 emit_int8(0x0F);
3794 emit_int8((unsigned char)0xB8);
3795 emit_int8((unsigned char)(0xC0 | encode));
3796 }
3797
3798 void Assembler::popf() {
3799 emit_int8((unsigned char)0x9D);
3800 }
3801
3802 #ifndef _LP64 // no 32bit push/pop on amd64
3803 void Assembler::popl(Address dst) {
3804 // NOTE: this will adjust stack by 8byte on 64bits
3805 InstructionMark im(this);
3806 prefix(dst);
3807 emit_int8((unsigned char)0x8F);
3808 emit_operand(rax, dst);
3809 }
3810 #endif
3811
3812 void Assembler::prefetch_prefix(Address src) {
3813 prefix(src);
3814 emit_int8(0x0F);
3815 }
3816
3817 void Assembler::prefetchnta(Address src) {
3818 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3819 InstructionMark im(this);
3820 prefetch_prefix(src);
3821 emit_int8(0x18);
3822 emit_operand(rax, src); // 0, src
3823 }
3824
3825 void Assembler::prefetchr(Address src) {
3826 assert(VM_Version::supports_3dnow_prefetch(), "must support");
3827 InstructionMark im(this);
3828 prefetch_prefix(src);
3829 emit_int8(0x0D);
3830 emit_operand(rax, src); // 0, src
3831 }
3832
3833 void Assembler::prefetcht0(Address src) {
3834 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3835 InstructionMark im(this);
3836 prefetch_prefix(src);
3837 emit_int8(0x18);
3838 emit_operand(rcx, src); // 1, src
3839 }
3840
3841 void Assembler::prefetcht1(Address src) {
3842 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3843 InstructionMark im(this);
3844 prefetch_prefix(src);
3845 emit_int8(0x18);
3846 emit_operand(rdx, src); // 2, src
3847 }
3848
3849 void Assembler::prefetcht2(Address src) {
3850 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3851 InstructionMark im(this);
3852 prefetch_prefix(src);
3853 emit_int8(0x18);
3854 emit_operand(rbx, src); // 3, src
3855 }
3856
3857 void Assembler::prefetchw(Address src) {
3858 assert(VM_Version::supports_3dnow_prefetch(), "must support");
3859 InstructionMark im(this);
3860 prefetch_prefix(src);
3861 emit_int8(0x0D);
3862 emit_operand(rcx, src); // 1, src
3863 }
3864
3865 void Assembler::prefix(Prefix p) {
3866 emit_int8(p);
3867 }
3868
3869 void Assembler::pshufb(XMMRegister dst, XMMRegister src) {
3870 assert(VM_Version::supports_ssse3(), "");
3871 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3872 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3873 emit_int8(0x00);
3874 emit_int8((unsigned char)(0xC0 | encode));
3875 }
3876
3877 void Assembler::vpshufb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3878 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
3879 vector_len == AVX_256bit? VM_Version::supports_avx2() :
3880 0, "");
3881 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3882 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3883 emit_int8(0x00);
3884 emit_int8((unsigned char)(0xC0 | encode));
3885 }
3886
3887 void Assembler::pshufb(XMMRegister dst, Address src) {
3888 assert(VM_Version::supports_ssse3(), "");
3889 InstructionMark im(this);
3890 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3891 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3892 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3893 emit_int8(0x00);
3894 emit_operand(dst, src);
3895 }
3896
3897 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
3898 assert(isByte(mode), "invalid value");
3899 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3900 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
3901 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3902 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3903 emit_int8(0x70);
3904 emit_int8((unsigned char)(0xC0 | encode));
3905 emit_int8(mode & 0xFF);
3906 }
3907
3908 void Assembler::vpshufd(XMMRegister dst, XMMRegister src, int mode, int vector_len) {
3909 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
3910 vector_len == AVX_256bit? VM_Version::supports_avx2() :
3911 0, "");
3912 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3913 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3914 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3915 emit_int8(0x70);
3916 emit_int8((unsigned char)(0xC0 | encode));
3917 emit_int8(mode & 0xFF);
3918 }
3919
3920 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
3921 assert(isByte(mode), "invalid value");
3922 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3923 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3924 InstructionMark im(this);
3925 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3926 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3927 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3928 emit_int8(0x70);
3929 emit_operand(dst, src);
3930 emit_int8(mode & 0xFF);
3931 }
3932
3933 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
3934 assert(isByte(mode), "invalid value");
3935 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3936 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3937 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3938 emit_int8(0x70);
3939 emit_int8((unsigned char)(0xC0 | encode));
3940 emit_int8(mode & 0xFF);
3941 }
3942
3943 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
3944 assert(isByte(mode), "invalid value");
3945 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3946 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3947 InstructionMark im(this);
3948 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3949 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3950 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3951 emit_int8(0x70);
3952 emit_operand(dst, src);
3953 emit_int8(mode & 0xFF);
3954 }
3955
3956 void Assembler::psrldq(XMMRegister dst, int shift) {
3957 // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
3958 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3959 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3960 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3961 emit_int8(0x73);
3962 emit_int8((unsigned char)(0xC0 | encode));
3963 emit_int8(shift);
3964 }
3965
3966 void Assembler::pslldq(XMMRegister dst, int shift) {
3967 // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
3968 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3969 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3970 // XMM7 is for /7 encoding: 66 0F 73 /7 ib
3971 int encode = simd_prefix_and_encode(xmm7, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3972 emit_int8(0x73);
3973 emit_int8((unsigned char)(0xC0 | encode));
3974 emit_int8(shift);
3975 }
3976
3977 void Assembler::ptest(XMMRegister dst, Address src) {
3978 assert(VM_Version::supports_sse4_1(), "");
3979 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3980 InstructionMark im(this);
3981 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3982 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3983 emit_int8(0x17);
3984 emit_operand(dst, src);
3985 }
3986
3987 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
3988 assert(VM_Version::supports_sse4_1(), "");
3989 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3990 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3991 emit_int8(0x17);
3992 emit_int8((unsigned char)(0xC0 | encode));
3993 }
3994
3995 void Assembler::vptest(XMMRegister dst, Address src) {
3996 assert(VM_Version::supports_avx(), "");
3997 InstructionMark im(this);
3998 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3999 assert(dst != xnoreg, "sanity");
4000 // swap src<->dst for encoding
4001 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4002 emit_int8(0x17);
4003 emit_operand(dst, src);
4004 }
4005
4006 void Assembler::vptest(XMMRegister dst, XMMRegister src) {
4007 assert(VM_Version::supports_avx(), "");
4008 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4009 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4010 emit_int8(0x17);
4011 emit_int8((unsigned char)(0xC0 | encode));
4012 }
4013
4014 void Assembler::punpcklbw(XMMRegister dst, Address src) {
4015 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4016 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4017 InstructionMark im(this);
4018 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ false, /* uses_vl */ true);
4019 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4020 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4021 emit_int8(0x60);
4022 emit_operand(dst, src);
4023 }
4024
4025 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
4026 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4027 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ false, /* uses_vl */ true);
4028 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4029 emit_int8(0x60);
4030 emit_int8((unsigned char)(0xC0 | encode));
4031 }
4032
4033 void Assembler::punpckldq(XMMRegister dst, Address src) {
4034 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4035 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4036 InstructionMark im(this);
4037 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4038 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4039 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4040 emit_int8(0x62);
4041 emit_operand(dst, src);
4042 }
4043
4044 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) {
4045 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4046 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4047 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4048 emit_int8(0x62);
4049 emit_int8((unsigned char)(0xC0 | encode));
4050 }
4051
4052 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) {
4053 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4054 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4055 attributes.set_rex_vex_w_reverted();
4056 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4057 emit_int8(0x6C);
4058 emit_int8((unsigned char)(0xC0 | encode));
4059 }
4060
4061 void Assembler::push(int32_t imm32) {
4062 // in 64bits we push 64bits onto the stack but only
4063 // take a 32bit immediate
4064 emit_int8(0x68);
4065 emit_int32(imm32);
4066 }
4067
4068 void Assembler::push(Register src) {
4069 int encode = prefix_and_encode(src->encoding());
4070
4071 emit_int8(0x50 | encode);
4072 }
4073
4074 void Assembler::pushf() {
4075 emit_int8((unsigned char)0x9C);
4076 }
4077
4078 #ifndef _LP64 // no 32bit push/pop on amd64
4079 void Assembler::pushl(Address src) {
4080 // Note this will push 64bit on 64bit
4081 InstructionMark im(this);
4082 prefix(src);
4083 emit_int8((unsigned char)0xFF);
4084 emit_operand(rsi, src);
4085 }
4086 #endif
4087
4088 void Assembler::rcll(Register dst, int imm8) {
4089 assert(isShiftCount(imm8), "illegal shift count");
4090 int encode = prefix_and_encode(dst->encoding());
4091 if (imm8 == 1) {
4092 emit_int8((unsigned char)0xD1);
4093 emit_int8((unsigned char)(0xD0 | encode));
4094 } else {
4095 emit_int8((unsigned char)0xC1);
4096 emit_int8((unsigned char)0xD0 | encode);
4097 emit_int8(imm8);
4098 }
4099 }
4100
4101 void Assembler::rcpps(XMMRegister dst, XMMRegister src) {
4102 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4103 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4104 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4105 emit_int8(0x53);
4106 emit_int8((unsigned char)(0xC0 | encode));
4107 }
4108
4109 void Assembler::rcpss(XMMRegister dst, XMMRegister src) {
4110 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4111 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4112 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4113 emit_int8(0x53);
4114 emit_int8((unsigned char)(0xC0 | encode));
4115 }
4116
4117 void Assembler::rdtsc() {
4118 emit_int8((unsigned char)0x0F);
4119 emit_int8((unsigned char)0x31);
4120 }
4121
4122 // copies data from [esi] to [edi] using rcx pointer sized words
4123 // generic
4124 void Assembler::rep_mov() {
4125 emit_int8((unsigned char)0xF3);
4126 // MOVSQ
4127 LP64_ONLY(prefix(REX_W));
4128 emit_int8((unsigned char)0xA5);
4129 }
4130
4131 // sets rcx bytes with rax, value at [edi]
4132 void Assembler::rep_stosb() {
4133 emit_int8((unsigned char)0xF3); // REP
4134 LP64_ONLY(prefix(REX_W));
4135 emit_int8((unsigned char)0xAA); // STOSB
4136 }
4137
4138 // sets rcx pointer sized words with rax, value at [edi]
4139 // generic
4140 void Assembler::rep_stos() {
4141 emit_int8((unsigned char)0xF3); // REP
4142 LP64_ONLY(prefix(REX_W)); // LP64:STOSQ, LP32:STOSD
4143 emit_int8((unsigned char)0xAB);
4144 }
4145
4146 // scans rcx pointer sized words at [edi] for occurance of rax,
4147 // generic
4148 void Assembler::repne_scan() { // repne_scan
4149 emit_int8((unsigned char)0xF2);
4150 // SCASQ
4151 LP64_ONLY(prefix(REX_W));
4152 emit_int8((unsigned char)0xAF);
4153 }
4154
4155 #ifdef _LP64
4156 // scans rcx 4 byte words at [edi] for occurance of rax,
4157 // generic
4158 void Assembler::repne_scanl() { // repne_scan
4159 emit_int8((unsigned char)0xF2);
4160 // SCASL
4161 emit_int8((unsigned char)0xAF);
4162 }
4163 #endif
4164
4165 void Assembler::ret(int imm16) {
4166 if (imm16 == 0) {
4167 emit_int8((unsigned char)0xC3);
4168 } else {
4169 emit_int8((unsigned char)0xC2);
4170 emit_int16(imm16);
4171 }
4172 }
4173
4174 void Assembler::sahf() {
4175 #ifdef _LP64
4176 // Not supported in 64bit mode
4177 ShouldNotReachHere();
4178 #endif
4179 emit_int8((unsigned char)0x9E);
4180 }
4181
4182 void Assembler::sarl(Register dst, int imm8) {
4183 int encode = prefix_and_encode(dst->encoding());
4184 assert(isShiftCount(imm8), "illegal shift count");
4185 if (imm8 == 1) {
4186 emit_int8((unsigned char)0xD1);
4187 emit_int8((unsigned char)(0xF8 | encode));
4188 } else {
4189 emit_int8((unsigned char)0xC1);
4190 emit_int8((unsigned char)(0xF8 | encode));
4191 emit_int8(imm8);
4192 }
4193 }
4194
4195 void Assembler::sarl(Register dst) {
4196 int encode = prefix_and_encode(dst->encoding());
4197 emit_int8((unsigned char)0xD3);
4198 emit_int8((unsigned char)(0xF8 | encode));
4199 }
4200
4201 void Assembler::sbbl(Address dst, int32_t imm32) {
4202 InstructionMark im(this);
4203 prefix(dst);
4204 emit_arith_operand(0x81, rbx, dst, imm32);
4205 }
4206
4207 void Assembler::sbbl(Register dst, int32_t imm32) {
4208 prefix(dst);
4209 emit_arith(0x81, 0xD8, dst, imm32);
4210 }
4211
4212
4213 void Assembler::sbbl(Register dst, Address src) {
4214 InstructionMark im(this);
4215 prefix(src, dst);
4216 emit_int8(0x1B);
4217 emit_operand(dst, src);
4218 }
4219
4220 void Assembler::sbbl(Register dst, Register src) {
4221 (void) prefix_and_encode(dst->encoding(), src->encoding());
4222 emit_arith(0x1B, 0xC0, dst, src);
4223 }
4224
4225 void Assembler::setb(Condition cc, Register dst) {
4226 assert(0 <= cc && cc < 16, "illegal cc");
4227 int encode = prefix_and_encode(dst->encoding(), true);
4228 emit_int8(0x0F);
4229 emit_int8((unsigned char)0x90 | cc);
4230 emit_int8((unsigned char)(0xC0 | encode));
4231 }
4232
4233 void Assembler::palignr(XMMRegister dst, XMMRegister src, int imm8) {
4234 assert(VM_Version::supports_ssse3(), "");
4235 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ false);
4236 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4237 emit_int8((unsigned char)0x0F);
4238 emit_int8((unsigned char)(0xC0 | encode));
4239 emit_int8(imm8);
4240 }
4241
4242 void Assembler::vpalignr(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
4243 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
4244 vector_len == AVX_256bit? VM_Version::supports_avx2() :
4245 0, "");
4246 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4247 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4248 emit_int8((unsigned char)0x0F);
4249 emit_int8((unsigned char)(0xC0 | encode));
4250 emit_int8(imm8);
4251 }
4252
4253 void Assembler::pblendw(XMMRegister dst, XMMRegister src, int imm8) {
4254 assert(VM_Version::supports_sse4_1(), "");
4255 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4256 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4257 emit_int8((unsigned char)0x0E);
4258 emit_int8((unsigned char)(0xC0 | encode));
4259 emit_int8(imm8);
4260 }
4261
4262 void Assembler::sha1rnds4(XMMRegister dst, XMMRegister src, int imm8) {
4263 assert(VM_Version::supports_sha(), "");
4264 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4265 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_3A, &attributes);
4266 emit_int8((unsigned char)0xCC);
4267 emit_int8((unsigned char)(0xC0 | encode));
4268 emit_int8((unsigned char)imm8);
4269 }
4270
4271 void Assembler::sha1nexte(XMMRegister dst, XMMRegister src) {
4272 assert(VM_Version::supports_sha(), "");
4273 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4274 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4275 emit_int8((unsigned char)0xC8);
4276 emit_int8((unsigned char)(0xC0 | encode));
4277 }
4278
4279 void Assembler::sha1msg1(XMMRegister dst, XMMRegister src) {
4280 assert(VM_Version::supports_sha(), "");
4281 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4282 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4283 emit_int8((unsigned char)0xC9);
4284 emit_int8((unsigned char)(0xC0 | encode));
4285 }
4286
4287 void Assembler::sha1msg2(XMMRegister dst, XMMRegister src) {
4288 assert(VM_Version::supports_sha(), "");
4289 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4290 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4291 emit_int8((unsigned char)0xCA);
4292 emit_int8((unsigned char)(0xC0 | encode));
4293 }
4294
4295 // xmm0 is implicit additional source to this instruction.
4296 void Assembler::sha256rnds2(XMMRegister dst, XMMRegister src) {
4297 assert(VM_Version::supports_sha(), "");
4298 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4299 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4300 emit_int8((unsigned char)0xCB);
4301 emit_int8((unsigned char)(0xC0 | encode));
4302 }
4303
4304 void Assembler::sha256msg1(XMMRegister dst, XMMRegister src) {
4305 assert(VM_Version::supports_sha(), "");
4306 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4307 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4308 emit_int8((unsigned char)0xCC);
4309 emit_int8((unsigned char)(0xC0 | encode));
4310 }
4311
4312 void Assembler::sha256msg2(XMMRegister dst, XMMRegister src) {
4313 assert(VM_Version::supports_sha(), "");
4314 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4315 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4316 emit_int8((unsigned char)0xCD);
4317 emit_int8((unsigned char)(0xC0 | encode));
4318 }
4319
4320
4321 void Assembler::shll(Register dst, int imm8) {
4322 assert(isShiftCount(imm8), "illegal shift count");
4323 int encode = prefix_and_encode(dst->encoding());
4324 if (imm8 == 1 ) {
4325 emit_int8((unsigned char)0xD1);
4326 emit_int8((unsigned char)(0xE0 | encode));
4327 } else {
4328 emit_int8((unsigned char)0xC1);
4329 emit_int8((unsigned char)(0xE0 | encode));
4330 emit_int8(imm8);
4331 }
4332 }
4333
4334 void Assembler::shll(Register dst) {
4335 int encode = prefix_and_encode(dst->encoding());
4336 emit_int8((unsigned char)0xD3);
4337 emit_int8((unsigned char)(0xE0 | encode));
4338 }
4339
4340 void Assembler::shrl(Register dst, int imm8) {
4341 assert(isShiftCount(imm8), "illegal shift count");
4342 int encode = prefix_and_encode(dst->encoding());
4343 emit_int8((unsigned char)0xC1);
4344 emit_int8((unsigned char)(0xE8 | encode));
4345 emit_int8(imm8);
4346 }
4347
4348 void Assembler::shrl(Register dst) {
4349 int encode = prefix_and_encode(dst->encoding());
4350 emit_int8((unsigned char)0xD3);
4351 emit_int8((unsigned char)(0xE8 | encode));
4352 }
4353
4354 // copies a single word from [esi] to [edi]
4355 void Assembler::smovl() {
4356 emit_int8((unsigned char)0xA5);
4357 }
4358
4359 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
4360 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4361 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4362 attributes.set_rex_vex_w_reverted();
4363 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4364 emit_int8(0x51);
4365 emit_int8((unsigned char)(0xC0 | encode));
4366 }
4367
4368 void Assembler::sqrtsd(XMMRegister dst, Address src) {
4369 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4370 InstructionMark im(this);
4371 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4372 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4373 attributes.set_rex_vex_w_reverted();
4374 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4375 emit_int8(0x51);
4376 emit_operand(dst, src);
4377 }
4378
4379 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
4380 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4381 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4382 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4383 emit_int8(0x51);
4384 emit_int8((unsigned char)(0xC0 | encode));
4385 }
4386
4387 void Assembler::std() {
4388 emit_int8((unsigned char)0xFD);
4389 }
4390
4391 void Assembler::sqrtss(XMMRegister dst, Address src) {
4392 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4393 InstructionMark im(this);
4394 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4395 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4396 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4397 emit_int8(0x51);
4398 emit_operand(dst, src);
4399 }
4400
4401 void Assembler::stmxcsr( Address dst) {
4402 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4403 InstructionMark im(this);
4404 prefix(dst);
4405 emit_int8(0x0F);
4406 emit_int8((unsigned char)0xAE);
4407 emit_operand(as_Register(3), dst);
4408 }
4409
4410 void Assembler::subl(Address dst, int32_t imm32) {
4411 InstructionMark im(this);
4412 prefix(dst);
4413 emit_arith_operand(0x81, rbp, dst, imm32);
4414 }
4415
4416 void Assembler::subl(Address dst, Register src) {
4417 InstructionMark im(this);
4418 prefix(dst, src);
4419 emit_int8(0x29);
4420 emit_operand(src, dst);
4421 }
4422
4423 void Assembler::subl(Register dst, int32_t imm32) {
4424 prefix(dst);
4425 emit_arith(0x81, 0xE8, dst, imm32);
4426 }
4427
4428 // Force generation of a 4 byte immediate value even if it fits into 8bit
4429 void Assembler::subl_imm32(Register dst, int32_t imm32) {
4430 prefix(dst);
4431 emit_arith_imm32(0x81, 0xE8, dst, imm32);
4432 }
4433
4434 void Assembler::subl(Register dst, Address src) {
4435 InstructionMark im(this);
4436 prefix(src, dst);
4437 emit_int8(0x2B);
4438 emit_operand(dst, src);
4439 }
4440
4441 void Assembler::subl(Register dst, Register src) {
4442 (void) prefix_and_encode(dst->encoding(), src->encoding());
4443 emit_arith(0x2B, 0xC0, dst, src);
4444 }
4445
4446 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
4447 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4448 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4449 attributes.set_rex_vex_w_reverted();
4450 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4451 emit_int8(0x5C);
4452 emit_int8((unsigned char)(0xC0 | encode));
4453 }
4454
4455 void Assembler::subsd(XMMRegister dst, Address src) {
4456 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4457 InstructionMark im(this);
4458 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4459 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4460 attributes.set_rex_vex_w_reverted();
4461 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4462 emit_int8(0x5C);
4463 emit_operand(dst, src);
4464 }
4465
4466 void Assembler::subss(XMMRegister dst, XMMRegister src) {
4467 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4468 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false , /* uses_vl */ false);
4469 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4470 emit_int8(0x5C);
4471 emit_int8((unsigned char)(0xC0 | encode));
4472 }
4473
4474 void Assembler::subss(XMMRegister dst, Address src) {
4475 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4476 InstructionMark im(this);
4477 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4478 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4479 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4480 emit_int8(0x5C);
4481 emit_operand(dst, src);
4482 }
4483
4484 void Assembler::testb(Register dst, int imm8) {
4485 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
4486 (void) prefix_and_encode(dst->encoding(), true);
4487 emit_arith_b(0xF6, 0xC0, dst, imm8);
4488 }
4489
4490 void Assembler::testb(Address dst, int imm8) {
4491 InstructionMark im(this);
4492 prefix(dst);
4493 emit_int8((unsigned char)0xF6);
4494 emit_operand(rax, dst, 1);
4495 emit_int8(imm8);
4496 }
4497
4498 void Assembler::testl(Register dst, int32_t imm32) {
4499 // not using emit_arith because test
4500 // doesn't support sign-extension of
4501 // 8bit operands
4502 int encode = dst->encoding();
4503 if (encode == 0) {
4504 emit_int8((unsigned char)0xA9);
4505 } else {
4506 encode = prefix_and_encode(encode);
4507 emit_int8((unsigned char)0xF7);
4508 emit_int8((unsigned char)(0xC0 | encode));
4509 }
4510 emit_int32(imm32);
4511 }
4512
4513 void Assembler::testl(Register dst, Register src) {
4514 (void) prefix_and_encode(dst->encoding(), src->encoding());
4515 emit_arith(0x85, 0xC0, dst, src);
4516 }
4517
4518 void Assembler::testl(Register dst, Address src) {
4519 InstructionMark im(this);
4520 prefix(src, dst);
4521 emit_int8((unsigned char)0x85);
4522 emit_operand(dst, src);
4523 }
4524
4525 void Assembler::tzcntl(Register dst, Register src) {
4526 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
4527 emit_int8((unsigned char)0xF3);
4528 int encode = prefix_and_encode(dst->encoding(), src->encoding());
4529 emit_int8(0x0F);
4530 emit_int8((unsigned char)0xBC);
4531 emit_int8((unsigned char)0xC0 | encode);
4532 }
4533
4534 void Assembler::tzcntq(Register dst, Register src) {
4535 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
4536 emit_int8((unsigned char)0xF3);
4537 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4538 emit_int8(0x0F);
4539 emit_int8((unsigned char)0xBC);
4540 emit_int8((unsigned char)(0xC0 | encode));
4541 }
4542
4543 void Assembler::ucomisd(XMMRegister dst, Address src) {
4544 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4545 InstructionMark im(this);
4546 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4547 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4548 attributes.set_rex_vex_w_reverted();
4549 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4550 emit_int8(0x2E);
4551 emit_operand(dst, src);
4552 }
4553
4554 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
4555 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4556 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4557 attributes.set_rex_vex_w_reverted();
4558 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4559 emit_int8(0x2E);
4560 emit_int8((unsigned char)(0xC0 | encode));
4561 }
4562
4563 void Assembler::ucomiss(XMMRegister dst, Address src) {
4564 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4565 InstructionMark im(this);
4566 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4567 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4568 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4569 emit_int8(0x2E);
4570 emit_operand(dst, src);
4571 }
4572
4573 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
4574 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4575 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4576 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4577 emit_int8(0x2E);
4578 emit_int8((unsigned char)(0xC0 | encode));
4579 }
4580
4581 void Assembler::xabort(int8_t imm8) {
4582 emit_int8((unsigned char)0xC6);
4583 emit_int8((unsigned char)0xF8);
4584 emit_int8((unsigned char)(imm8 & 0xFF));
4585 }
4586
4587 void Assembler::xaddb(Address dst, Register src) {
4588 InstructionMark im(this);
4589 prefix(dst, src, true);
4590 emit_int8(0x0F);
4591 emit_int8((unsigned char)0xC0);
4592 emit_operand(src, dst);
4593 }
4594
4595 void Assembler::xaddw(Address dst, Register src) {
4596 InstructionMark im(this);
4597 emit_int8(0x66);
4598 prefix(dst, src);
4599 emit_int8(0x0F);
4600 emit_int8((unsigned char)0xC1);
4601 emit_operand(src, dst);
4602 }
4603
4604 void Assembler::xaddl(Address dst, Register src) {
4605 InstructionMark im(this);
4606 prefix(dst, src);
4607 emit_int8(0x0F);
4608 emit_int8((unsigned char)0xC1);
4609 emit_operand(src, dst);
4610 }
4611
4612 void Assembler::xbegin(Label& abort, relocInfo::relocType rtype) {
4613 InstructionMark im(this);
4614 relocate(rtype);
4615 if (abort.is_bound()) {
4616 address entry = target(abort);
4617 assert(entry != NULL, "abort entry NULL");
4618 intptr_t offset = entry - pc();
4619 emit_int8((unsigned char)0xC7);
4620 emit_int8((unsigned char)0xF8);
4621 emit_int32(offset - 6); // 2 opcode + 4 address
4622 } else {
4623 abort.add_patch_at(code(), locator());
4624 emit_int8((unsigned char)0xC7);
4625 emit_int8((unsigned char)0xF8);
4626 emit_int32(0);
4627 }
4628 }
4629
4630 void Assembler::xchgb(Register dst, Address src) { // xchg
4631 InstructionMark im(this);
4632 prefix(src, dst, true);
4633 emit_int8((unsigned char)0x86);
4634 emit_operand(dst, src);
4635 }
4636
4637 void Assembler::xchgw(Register dst, Address src) { // xchg
4638 InstructionMark im(this);
4639 emit_int8(0x66);
4640 prefix(src, dst);
4641 emit_int8((unsigned char)0x87);
4642 emit_operand(dst, src);
4643 }
4644
4645 void Assembler::xchgl(Register dst, Address src) { // xchg
4646 InstructionMark im(this);
4647 prefix(src, dst);
4648 emit_int8((unsigned char)0x87);
4649 emit_operand(dst, src);
4650 }
4651
4652 void Assembler::xchgl(Register dst, Register src) {
4653 int encode = prefix_and_encode(dst->encoding(), src->encoding());
4654 emit_int8((unsigned char)0x87);
4655 emit_int8((unsigned char)(0xC0 | encode));
4656 }
4657
4658 void Assembler::xend() {
4659 emit_int8((unsigned char)0x0F);
4660 emit_int8((unsigned char)0x01);
4661 emit_int8((unsigned char)0xD5);
4662 }
4663
4664 void Assembler::xgetbv() {
4665 emit_int8(0x0F);
4666 emit_int8(0x01);
4667 emit_int8((unsigned char)0xD0);
4668 }
4669
4670 void Assembler::xorl(Register dst, int32_t imm32) {
4671 prefix(dst);
4672 emit_arith(0x81, 0xF0, dst, imm32);
4673 }
4674
4675 void Assembler::xorl(Register dst, Address src) {
4676 InstructionMark im(this);
4677 prefix(src, dst);
4678 emit_int8(0x33);
4679 emit_operand(dst, src);
4680 }
4681
4682 void Assembler::xorl(Register dst, Register src) {
4683 (void) prefix_and_encode(dst->encoding(), src->encoding());
4684 emit_arith(0x33, 0xC0, dst, src);
4685 }
4686
4687 void Assembler::xorb(Register dst, Address src) {
4688 InstructionMark im(this);
4689 prefix(src, dst);
4690 emit_int8(0x32);
4691 emit_operand(dst, src);
4692 }
4693
4694 // AVX 3-operands scalar float-point arithmetic instructions
4695
4696 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) {
4697 assert(VM_Version::supports_avx(), "");
4698 InstructionMark im(this);
4699 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4700 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4701 attributes.set_rex_vex_w_reverted();
4702 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4703 emit_int8(0x58);
4704 emit_operand(dst, src);
4705 }
4706
4707 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4708 assert(VM_Version::supports_avx(), "");
4709 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4710 attributes.set_rex_vex_w_reverted();
4711 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4712 emit_int8(0x58);
4713 emit_int8((unsigned char)(0xC0 | encode));
4714 }
4715
4716 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) {
4717 assert(VM_Version::supports_avx(), "");
4718 InstructionMark im(this);
4719 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4720 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4721 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4722 emit_int8(0x58);
4723 emit_operand(dst, src);
4724 }
4725
4726 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4727 assert(VM_Version::supports_avx(), "");
4728 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4729 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4730 emit_int8(0x58);
4731 emit_int8((unsigned char)(0xC0 | encode));
4732 }
4733
4734 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) {
4735 assert(VM_Version::supports_avx(), "");
4736 InstructionMark im(this);
4737 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4738 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4739 attributes.set_rex_vex_w_reverted();
4740 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4741 emit_int8(0x5E);
4742 emit_operand(dst, src);
4743 }
4744
4745 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4746 assert(VM_Version::supports_avx(), "");
4747 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4748 attributes.set_rex_vex_w_reverted();
4749 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4750 emit_int8(0x5E);
4751 emit_int8((unsigned char)(0xC0 | encode));
4752 }
4753
4754 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) {
4755 assert(VM_Version::supports_avx(), "");
4756 InstructionMark im(this);
4757 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4758 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4759 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4760 emit_int8(0x5E);
4761 emit_operand(dst, src);
4762 }
4763
4764 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4765 assert(VM_Version::supports_avx(), "");
4766 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4767 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4768 emit_int8(0x5E);
4769 emit_int8((unsigned char)(0xC0 | encode));
4770 }
4771
4772 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) {
4773 assert(VM_Version::supports_avx(), "");
4774 InstructionMark im(this);
4775 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4776 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4777 attributes.set_rex_vex_w_reverted();
4778 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4779 emit_int8(0x59);
4780 emit_operand(dst, src);
4781 }
4782
4783 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4784 assert(VM_Version::supports_avx(), "");
4785 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4786 attributes.set_rex_vex_w_reverted();
4787 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4788 emit_int8(0x59);
4789 emit_int8((unsigned char)(0xC0 | encode));
4790 }
4791
4792 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) {
4793 assert(VM_Version::supports_avx(), "");
4794 InstructionMark im(this);
4795 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4796 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4797 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4798 emit_int8(0x59);
4799 emit_operand(dst, src);
4800 }
4801
4802 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4803 assert(VM_Version::supports_avx(), "");
4804 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4805 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4806 emit_int8(0x59);
4807 emit_int8((unsigned char)(0xC0 | encode));
4808 }
4809
4810 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) {
4811 assert(VM_Version::supports_avx(), "");
4812 InstructionMark im(this);
4813 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4814 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4815 attributes.set_rex_vex_w_reverted();
4816 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4817 emit_int8(0x5C);
4818 emit_operand(dst, src);
4819 }
4820
4821 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4822 assert(VM_Version::supports_avx(), "");
4823 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4824 attributes.set_rex_vex_w_reverted();
4825 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4826 emit_int8(0x5C);
4827 emit_int8((unsigned char)(0xC0 | encode));
4828 }
4829
4830 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) {
4831 assert(VM_Version::supports_avx(), "");
4832 InstructionMark im(this);
4833 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4834 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4835 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4836 emit_int8(0x5C);
4837 emit_operand(dst, src);
4838 }
4839
4840 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4841 assert(VM_Version::supports_avx(), "");
4842 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4843 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4844 emit_int8(0x5C);
4845 emit_int8((unsigned char)(0xC0 | encode));
4846 }
4847
4848 //====================VECTOR ARITHMETIC=====================================
4849
4850 // Float-point vector arithmetic
4851
4852 void Assembler::addpd(XMMRegister dst, XMMRegister src) {
4853 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4854 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4855 attributes.set_rex_vex_w_reverted();
4856 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4857 emit_int8(0x58);
4858 emit_int8((unsigned char)(0xC0 | encode));
4859 }
4860
4861 void Assembler::addpd(XMMRegister dst, Address src) {
4862 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4863 InstructionMark im(this);
4864 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4865 attributes.set_rex_vex_w_reverted();
4866 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4867 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4868 emit_int8(0x58);
4869 emit_operand(dst, src);
4870 }
4871
4872
4873 void Assembler::addps(XMMRegister dst, XMMRegister src) {
4874 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4875 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4876 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4877 emit_int8(0x58);
4878 emit_int8((unsigned char)(0xC0 | encode));
4879 }
4880
4881 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4882 assert(VM_Version::supports_avx(), "");
4883 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4884 attributes.set_rex_vex_w_reverted();
4885 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4886 emit_int8(0x58);
4887 emit_int8((unsigned char)(0xC0 | encode));
4888 }
4889
4890 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4891 assert(VM_Version::supports_avx(), "");
4892 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4893 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4894 emit_int8(0x58);
4895 emit_int8((unsigned char)(0xC0 | encode));
4896 }
4897
4898 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4899 assert(VM_Version::supports_avx(), "");
4900 InstructionMark im(this);
4901 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4902 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4903 attributes.set_rex_vex_w_reverted();
4904 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4905 emit_int8(0x58);
4906 emit_operand(dst, src);
4907 }
4908
4909 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4910 assert(VM_Version::supports_avx(), "");
4911 InstructionMark im(this);
4912 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4913 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4914 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4915 emit_int8(0x58);
4916 emit_operand(dst, src);
4917 }
4918
4919 void Assembler::subpd(XMMRegister dst, XMMRegister src) {
4920 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4921 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4922 attributes.set_rex_vex_w_reverted();
4923 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4924 emit_int8(0x5C);
4925 emit_int8((unsigned char)(0xC0 | encode));
4926 }
4927
4928 void Assembler::subps(XMMRegister dst, XMMRegister src) {
4929 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4930 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4931 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4932 emit_int8(0x5C);
4933 emit_int8((unsigned char)(0xC0 | encode));
4934 }
4935
4936 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4937 assert(VM_Version::supports_avx(), "");
4938 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4939 attributes.set_rex_vex_w_reverted();
4940 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4941 emit_int8(0x5C);
4942 emit_int8((unsigned char)(0xC0 | encode));
4943 }
4944
4945 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4946 assert(VM_Version::supports_avx(), "");
4947 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4948 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4949 emit_int8(0x5C);
4950 emit_int8((unsigned char)(0xC0 | encode));
4951 }
4952
4953 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4954 assert(VM_Version::supports_avx(), "");
4955 InstructionMark im(this);
4956 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4957 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4958 attributes.set_rex_vex_w_reverted();
4959 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4960 emit_int8(0x5C);
4961 emit_operand(dst, src);
4962 }
4963
4964 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4965 assert(VM_Version::supports_avx(), "");
4966 InstructionMark im(this);
4967 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4968 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4969 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4970 emit_int8(0x5C);
4971 emit_operand(dst, src);
4972 }
4973
4974 void Assembler::mulpd(XMMRegister dst, XMMRegister src) {
4975 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4976 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4977 attributes.set_rex_vex_w_reverted();
4978 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4979 emit_int8(0x59);
4980 emit_int8((unsigned char)(0xC0 | encode));
4981 }
4982
4983 void Assembler::mulpd(XMMRegister dst, Address src) {
4984 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4985 InstructionMark im(this);
4986 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4987 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4988 attributes.set_rex_vex_w_reverted();
4989 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4990 emit_int8(0x59);
4991 emit_operand(dst, src);
4992 }
4993
4994 void Assembler::mulps(XMMRegister dst, XMMRegister src) {
4995 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4996 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4997 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4998 emit_int8(0x59);
4999 emit_int8((unsigned char)(0xC0 | encode));
5000 }
5001
5002 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5003 assert(VM_Version::supports_avx(), "");
5004 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5005 attributes.set_rex_vex_w_reverted();
5006 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5007 emit_int8(0x59);
5008 emit_int8((unsigned char)(0xC0 | encode));
5009 }
5010
5011 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5012 assert(VM_Version::supports_avx(), "");
5013 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5014 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5015 emit_int8(0x59);
5016 emit_int8((unsigned char)(0xC0 | encode));
5017 }
5018
5019 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5020 assert(VM_Version::supports_avx(), "");
5021 InstructionMark im(this);
5022 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5023 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5024 attributes.set_rex_vex_w_reverted();
5025 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5026 emit_int8(0x59);
5027 emit_operand(dst, src);
5028 }
5029
5030 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5031 assert(VM_Version::supports_avx(), "");
5032 InstructionMark im(this);
5033 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5034 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5035 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5036 emit_int8(0x59);
5037 emit_operand(dst, src);
5038 }
5039
5040 void Assembler::divpd(XMMRegister dst, XMMRegister src) {
5041 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5042 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5043 attributes.set_rex_vex_w_reverted();
5044 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5045 emit_int8(0x5E);
5046 emit_int8((unsigned char)(0xC0 | encode));
5047 }
5048
5049 void Assembler::divps(XMMRegister dst, XMMRegister src) {
5050 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5051 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5052 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5053 emit_int8(0x5E);
5054 emit_int8((unsigned char)(0xC0 | encode));
5055 }
5056
5057 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5058 assert(VM_Version::supports_avx(), "");
5059 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5060 attributes.set_rex_vex_w_reverted();
5061 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5062 emit_int8(0x5E);
5063 emit_int8((unsigned char)(0xC0 | encode));
5064 }
5065
5066 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5067 assert(VM_Version::supports_avx(), "");
5068 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5069 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5070 emit_int8(0x5E);
5071 emit_int8((unsigned char)(0xC0 | encode));
5072 }
5073
5074 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5075 assert(VM_Version::supports_avx(), "");
5076 InstructionMark im(this);
5077 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5078 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5079 attributes.set_rex_vex_w_reverted();
5080 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5081 emit_int8(0x5E);
5082 emit_operand(dst, src);
5083 }
5084
5085 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5086 assert(VM_Version::supports_avx(), "");
5087 InstructionMark im(this);
5088 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5089 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5090 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5091 emit_int8(0x5E);
5092 emit_operand(dst, src);
5093 }
5094
5095 void Assembler::vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len) {
5096 assert(VM_Version::supports_avx(), "");
5097 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5098 attributes.set_rex_vex_w_reverted();
5099 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5100 emit_int8(0x51);
5101 emit_int8((unsigned char)(0xC0 | encode));
5102 }
5103
5104 void Assembler::vsqrtpd(XMMRegister dst, Address src, int vector_len) {
5105 assert(VM_Version::supports_avx(), "");
5106 InstructionMark im(this);
5107 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5108 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5109 attributes.set_rex_vex_w_reverted();
5110 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5111 emit_int8(0x51);
5112 emit_operand(dst, src);
5113 }
5114
5115 void Assembler::andpd(XMMRegister dst, XMMRegister src) {
5116 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5117 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5118 attributes.set_rex_vex_w_reverted();
5119 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5120 emit_int8(0x54);
5121 emit_int8((unsigned char)(0xC0 | encode));
5122 }
5123
5124 void Assembler::andps(XMMRegister dst, XMMRegister src) {
5125 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5126 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5127 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5128 emit_int8(0x54);
5129 emit_int8((unsigned char)(0xC0 | encode));
5130 }
5131
5132 void Assembler::andps(XMMRegister dst, Address src) {
5133 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5134 InstructionMark im(this);
5135 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5136 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5137 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5138 emit_int8(0x54);
5139 emit_operand(dst, src);
5140 }
5141
5142 void Assembler::andpd(XMMRegister dst, Address src) {
5143 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5144 InstructionMark im(this);
5145 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5146 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5147 attributes.set_rex_vex_w_reverted();
5148 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5149 emit_int8(0x54);
5150 emit_operand(dst, src);
5151 }
5152
5153 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5154 assert(VM_Version::supports_avx(), "");
5155 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5156 attributes.set_rex_vex_w_reverted();
5157 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5158 emit_int8(0x54);
5159 emit_int8((unsigned char)(0xC0 | encode));
5160 }
5161
5162 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5163 assert(VM_Version::supports_avx(), "");
5164 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5165 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5166 emit_int8(0x54);
5167 emit_int8((unsigned char)(0xC0 | encode));
5168 }
5169
5170 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5171 assert(VM_Version::supports_avx(), "");
5172 InstructionMark im(this);
5173 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5174 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5175 attributes.set_rex_vex_w_reverted();
5176 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5177 emit_int8(0x54);
5178 emit_operand(dst, src);
5179 }
5180
5181 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5182 assert(VM_Version::supports_avx(), "");
5183 InstructionMark im(this);
5184 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5185 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5186 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5187 emit_int8(0x54);
5188 emit_operand(dst, src);
5189 }
5190
5191 void Assembler::unpckhpd(XMMRegister dst, XMMRegister src) {
5192 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5193 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5194 attributes.set_rex_vex_w_reverted();
5195 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5196 emit_int8(0x15);
5197 emit_int8((unsigned char)(0xC0 | encode));
5198 }
5199
5200 void Assembler::unpcklpd(XMMRegister dst, XMMRegister src) {
5201 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5202 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5203 attributes.set_rex_vex_w_reverted();
5204 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5205 emit_int8(0x14);
5206 emit_int8((unsigned char)(0xC0 | encode));
5207 }
5208
5209 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
5210 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5211 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5212 attributes.set_rex_vex_w_reverted();
5213 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5214 emit_int8(0x57);
5215 emit_int8((unsigned char)(0xC0 | encode));
5216 }
5217
5218 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
5219 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5220 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5221 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5222 emit_int8(0x57);
5223 emit_int8((unsigned char)(0xC0 | encode));
5224 }
5225
5226 void Assembler::xorpd(XMMRegister dst, Address src) {
5227 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5228 InstructionMark im(this);
5229 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5230 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5231 attributes.set_rex_vex_w_reverted();
5232 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5233 emit_int8(0x57);
5234 emit_operand(dst, src);
5235 }
5236
5237 void Assembler::xorps(XMMRegister dst, Address src) {
5238 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5239 InstructionMark im(this);
5240 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5241 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5242 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5243 emit_int8(0x57);
5244 emit_operand(dst, src);
5245 }
5246
5247 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5248 assert(VM_Version::supports_avx(), "");
5249 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5250 attributes.set_rex_vex_w_reverted();
5251 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5252 emit_int8(0x57);
5253 emit_int8((unsigned char)(0xC0 | encode));
5254 }
5255
5256 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5257 assert(VM_Version::supports_avx(), "");
5258 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5259 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5260 emit_int8(0x57);
5261 emit_int8((unsigned char)(0xC0 | encode));
5262 }
5263
5264 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5265 assert(VM_Version::supports_avx(), "");
5266 InstructionMark im(this);
5267 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5268 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5269 attributes.set_rex_vex_w_reverted();
5270 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5271 emit_int8(0x57);
5272 emit_operand(dst, src);
5273 }
5274
5275 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5276 assert(VM_Version::supports_avx(), "");
5277 InstructionMark im(this);
5278 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5279 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5280 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5281 emit_int8(0x57);
5282 emit_operand(dst, src);
5283 }
5284
5285 // Integer vector arithmetic
5286 void Assembler::vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5287 assert(VM_Version::supports_avx() && (vector_len == 0) ||
5288 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
5289 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5290 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5291 emit_int8(0x01);
5292 emit_int8((unsigned char)(0xC0 | encode));
5293 }
5294
5295 void Assembler::vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5296 assert(VM_Version::supports_avx() && (vector_len == 0) ||
5297 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
5298 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5299 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5300 emit_int8(0x02);
5301 emit_int8((unsigned char)(0xC0 | encode));
5302 }
5303
5304 void Assembler::paddb(XMMRegister dst, XMMRegister src) {
5305 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5306 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5307 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5308 emit_int8((unsigned char)0xFC);
5309 emit_int8((unsigned char)(0xC0 | encode));
5310 }
5311
5312 void Assembler::paddw(XMMRegister dst, XMMRegister src) {
5313 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5314 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5315 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5316 emit_int8((unsigned char)0xFD);
5317 emit_int8((unsigned char)(0xC0 | encode));
5318 }
5319
5320 void Assembler::paddd(XMMRegister dst, XMMRegister src) {
5321 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5322 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5323 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5324 emit_int8((unsigned char)0xFE);
5325 emit_int8((unsigned char)(0xC0 | encode));
5326 }
5327
5328 void Assembler::paddd(XMMRegister dst, Address src) {
5329 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5330 InstructionMark im(this);
5331 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5332 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5333 emit_int8((unsigned char)0xFE);
5334 emit_operand(dst, src);
5335 }
5336
5337 void Assembler::paddq(XMMRegister dst, XMMRegister src) {
5338 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5339 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5340 attributes.set_rex_vex_w_reverted();
5341 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5342 emit_int8((unsigned char)0xD4);
5343 emit_int8((unsigned char)(0xC0 | encode));
5344 }
5345
5346 void Assembler::phaddw(XMMRegister dst, XMMRegister src) {
5347 assert(VM_Version::supports_sse3(), "");
5348 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5349 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5350 emit_int8(0x01);
5351 emit_int8((unsigned char)(0xC0 | encode));
5352 }
5353
5354 void Assembler::phaddd(XMMRegister dst, XMMRegister src) {
5355 assert(VM_Version::supports_sse3(), "");
5356 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5357 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5358 emit_int8(0x02);
5359 emit_int8((unsigned char)(0xC0 | encode));
5360 }
5361
5362 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5363 assert(UseAVX > 0, "requires some form of AVX");
5364 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5365 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5366 emit_int8((unsigned char)0xFC);
5367 emit_int8((unsigned char)(0xC0 | encode));
5368 }
5369
5370 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5371 assert(UseAVX > 0, "requires some form of AVX");
5372 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5373 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5374 emit_int8((unsigned char)0xFD);
5375 emit_int8((unsigned char)(0xC0 | encode));
5376 }
5377
5378 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5379 assert(UseAVX > 0, "requires some form of AVX");
5380 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5381 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5382 emit_int8((unsigned char)0xFE);
5383 emit_int8((unsigned char)(0xC0 | encode));
5384 }
5385
5386 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5387 assert(UseAVX > 0, "requires some form of AVX");
5388 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5389 attributes.set_rex_vex_w_reverted();
5390 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5391 emit_int8((unsigned char)0xD4);
5392 emit_int8((unsigned char)(0xC0 | encode));
5393 }
5394
5395 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5396 assert(UseAVX > 0, "requires some form of AVX");
5397 InstructionMark im(this);
5398 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5399 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5400 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5401 emit_int8((unsigned char)0xFC);
5402 emit_operand(dst, src);
5403 }
5404
5405 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5406 assert(UseAVX > 0, "requires some form of AVX");
5407 InstructionMark im(this);
5408 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5409 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5410 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5411 emit_int8((unsigned char)0xFD);
5412 emit_operand(dst, src);
5413 }
5414
5415 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5416 assert(UseAVX > 0, "requires some form of AVX");
5417 InstructionMark im(this);
5418 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5419 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5420 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5421 emit_int8((unsigned char)0xFE);
5422 emit_operand(dst, src);
5423 }
5424
5425 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5426 assert(UseAVX > 0, "requires some form of AVX");
5427 InstructionMark im(this);
5428 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5429 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5430 attributes.set_rex_vex_w_reverted();
5431 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5432 emit_int8((unsigned char)0xD4);
5433 emit_operand(dst, src);
5434 }
5435
5436 void Assembler::psubb(XMMRegister dst, XMMRegister src) {
5437 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5438 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5439 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5440 emit_int8((unsigned char)0xF8);
5441 emit_int8((unsigned char)(0xC0 | encode));
5442 }
5443
5444 void Assembler::psubw(XMMRegister dst, XMMRegister src) {
5445 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5446 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5447 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5448 emit_int8((unsigned char)0xF9);
5449 emit_int8((unsigned char)(0xC0 | encode));
5450 }
5451
5452 void Assembler::psubd(XMMRegister dst, XMMRegister src) {
5453 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5454 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5455 emit_int8((unsigned char)0xFA);
5456 emit_int8((unsigned char)(0xC0 | encode));
5457 }
5458
5459 void Assembler::psubq(XMMRegister dst, XMMRegister src) {
5460 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5461 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5462 attributes.set_rex_vex_w_reverted();
5463 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5464 emit_int8((unsigned char)0xFB);
5465 emit_int8((unsigned char)(0xC0 | encode));
5466 }
5467
5468 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5469 assert(UseAVX > 0, "requires some form of AVX");
5470 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5471 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5472 emit_int8((unsigned char)0xF8);
5473 emit_int8((unsigned char)(0xC0 | encode));
5474 }
5475
5476 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5477 assert(UseAVX > 0, "requires some form of AVX");
5478 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5479 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5480 emit_int8((unsigned char)0xF9);
5481 emit_int8((unsigned char)(0xC0 | encode));
5482 }
5483
5484 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5485 assert(UseAVX > 0, "requires some form of AVX");
5486 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5487 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5488 emit_int8((unsigned char)0xFA);
5489 emit_int8((unsigned char)(0xC0 | encode));
5490 }
5491
5492 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5493 assert(UseAVX > 0, "requires some form of AVX");
5494 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5495 attributes.set_rex_vex_w_reverted();
5496 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5497 emit_int8((unsigned char)0xFB);
5498 emit_int8((unsigned char)(0xC0 | encode));
5499 }
5500
5501 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5502 assert(UseAVX > 0, "requires some form of AVX");
5503 InstructionMark im(this);
5504 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5505 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5506 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5507 emit_int8((unsigned char)0xF8);
5508 emit_operand(dst, src);
5509 }
5510
5511 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5512 assert(UseAVX > 0, "requires some form of AVX");
5513 InstructionMark im(this);
5514 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5515 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5516 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5517 emit_int8((unsigned char)0xF9);
5518 emit_operand(dst, src);
5519 }
5520
5521 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5522 assert(UseAVX > 0, "requires some form of AVX");
5523 InstructionMark im(this);
5524 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5525 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5526 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5527 emit_int8((unsigned char)0xFA);
5528 emit_operand(dst, src);
5529 }
5530
5531 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5532 assert(UseAVX > 0, "requires some form of AVX");
5533 InstructionMark im(this);
5534 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5535 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5536 attributes.set_rex_vex_w_reverted();
5537 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5538 emit_int8((unsigned char)0xFB);
5539 emit_operand(dst, src);
5540 }
5541
5542 void Assembler::pmullw(XMMRegister dst, XMMRegister src) {
5543 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5544 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5545 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5546 emit_int8((unsigned char)0xD5);
5547 emit_int8((unsigned char)(0xC0 | encode));
5548 }
5549
5550 void Assembler::pmulld(XMMRegister dst, XMMRegister src) {
5551 assert(VM_Version::supports_sse4_1(), "");
5552 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5553 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5554 emit_int8(0x40);
5555 emit_int8((unsigned char)(0xC0 | encode));
5556 }
5557
5558 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5559 assert(UseAVX > 0, "requires some form of AVX");
5560 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5561 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5562 emit_int8((unsigned char)0xD5);
5563 emit_int8((unsigned char)(0xC0 | encode));
5564 }
5565
5566 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5567 assert(UseAVX > 0, "requires some form of AVX");
5568 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5569 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5570 emit_int8(0x40);
5571 emit_int8((unsigned char)(0xC0 | encode));
5572 }
5573
5574 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5575 assert(UseAVX > 2, "requires some form of EVEX");
5576 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5577 attributes.set_is_evex_instruction();
5578 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5579 emit_int8(0x40);
5580 emit_int8((unsigned char)(0xC0 | encode));
5581 }
5582
5583 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5584 assert(UseAVX > 0, "requires some form of AVX");
5585 InstructionMark im(this);
5586 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5587 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5588 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5589 emit_int8((unsigned char)0xD5);
5590 emit_operand(dst, src);
5591 }
5592
5593 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5594 assert(UseAVX > 0, "requires some form of AVX");
5595 InstructionMark im(this);
5596 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5597 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5598 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5599 emit_int8(0x40);
5600 emit_operand(dst, src);
5601 }
5602
5603 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5604 assert(UseAVX > 2, "requires some form of EVEX");
5605 InstructionMark im(this);
5606 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5607 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5608 attributes.set_is_evex_instruction();
5609 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5610 emit_int8(0x40);
5611 emit_operand(dst, src);
5612 }
5613
5614 // Shift packed integers left by specified number of bits.
5615 void Assembler::psllw(XMMRegister dst, int shift) {
5616 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5617 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5618 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
5619 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5620 emit_int8(0x71);
5621 emit_int8((unsigned char)(0xC0 | encode));
5622 emit_int8(shift & 0xFF);
5623 }
5624
5625 void Assembler::pslld(XMMRegister dst, int shift) {
5626 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5627 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5628 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
5629 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5630 emit_int8(0x72);
5631 emit_int8((unsigned char)(0xC0 | encode));
5632 emit_int8(shift & 0xFF);
5633 }
5634
5635 void Assembler::psllq(XMMRegister dst, int shift) {
5636 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5637 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5638 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
5639 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5640 emit_int8(0x73);
5641 emit_int8((unsigned char)(0xC0 | encode));
5642 emit_int8(shift & 0xFF);
5643 }
5644
5645 void Assembler::psllw(XMMRegister dst, XMMRegister shift) {
5646 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5647 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5648 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5649 emit_int8((unsigned char)0xF1);
5650 emit_int8((unsigned char)(0xC0 | encode));
5651 }
5652
5653 void Assembler::pslld(XMMRegister dst, XMMRegister shift) {
5654 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5655 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5656 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5657 emit_int8((unsigned char)0xF2);
5658 emit_int8((unsigned char)(0xC0 | encode));
5659 }
5660
5661 void Assembler::psllq(XMMRegister dst, XMMRegister shift) {
5662 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5663 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5664 attributes.set_rex_vex_w_reverted();
5665 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5666 emit_int8((unsigned char)0xF3);
5667 emit_int8((unsigned char)(0xC0 | encode));
5668 }
5669
5670 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5671 assert(UseAVX > 0, "requires some form of AVX");
5672 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5673 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
5674 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5675 emit_int8(0x71);
5676 emit_int8((unsigned char)(0xC0 | encode));
5677 emit_int8(shift & 0xFF);
5678 }
5679
5680 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5681 assert(UseAVX > 0, "requires some form of AVX");
5682 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5683 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5684 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
5685 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5686 emit_int8(0x72);
5687 emit_int8((unsigned char)(0xC0 | encode));
5688 emit_int8(shift & 0xFF);
5689 }
5690
5691 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5692 assert(UseAVX > 0, "requires some form of AVX");
5693 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5694 attributes.set_rex_vex_w_reverted();
5695 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
5696 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5697 emit_int8(0x73);
5698 emit_int8((unsigned char)(0xC0 | encode));
5699 emit_int8(shift & 0xFF);
5700 }
5701
5702 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5703 assert(UseAVX > 0, "requires some form of AVX");
5704 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5705 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5706 emit_int8((unsigned char)0xF1);
5707 emit_int8((unsigned char)(0xC0 | encode));
5708 }
5709
5710 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5711 assert(UseAVX > 0, "requires some form of AVX");
5712 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5713 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5714 emit_int8((unsigned char)0xF2);
5715 emit_int8((unsigned char)(0xC0 | encode));
5716 }
5717
5718 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5719 assert(UseAVX > 0, "requires some form of AVX");
5720 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5721 attributes.set_rex_vex_w_reverted();
5722 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5723 emit_int8((unsigned char)0xF3);
5724 emit_int8((unsigned char)(0xC0 | encode));
5725 }
5726
5727 // Shift packed integers logically right by specified number of bits.
5728 void Assembler::psrlw(XMMRegister dst, int shift) {
5729 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5730 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5731 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
5732 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5733 emit_int8(0x71);
5734 emit_int8((unsigned char)(0xC0 | encode));
5735 emit_int8(shift & 0xFF);
5736 }
5737
5738 void Assembler::psrld(XMMRegister dst, int shift) {
5739 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5740 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5741 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
5742 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5743 emit_int8(0x72);
5744 emit_int8((unsigned char)(0xC0 | encode));
5745 emit_int8(shift & 0xFF);
5746 }
5747
5748 void Assembler::psrlq(XMMRegister dst, int shift) {
5749 // Do not confuse it with psrldq SSE2 instruction which
5750 // shifts 128 bit value in xmm register by number of bytes.
5751 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5752 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5753 attributes.set_rex_vex_w_reverted();
5754 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
5755 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5756 emit_int8(0x73);
5757 emit_int8((unsigned char)(0xC0 | encode));
5758 emit_int8(shift & 0xFF);
5759 }
5760
5761 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) {
5762 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5763 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5764 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5765 emit_int8((unsigned char)0xD1);
5766 emit_int8((unsigned char)(0xC0 | encode));
5767 }
5768
5769 void Assembler::psrld(XMMRegister dst, XMMRegister shift) {
5770 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5771 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5772 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5773 emit_int8((unsigned char)0xD2);
5774 emit_int8((unsigned char)(0xC0 | encode));
5775 }
5776
5777 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) {
5778 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5779 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5780 attributes.set_rex_vex_w_reverted();
5781 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5782 emit_int8((unsigned char)0xD3);
5783 emit_int8((unsigned char)(0xC0 | encode));
5784 }
5785
5786 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5787 assert(UseAVX > 0, "requires some form of AVX");
5788 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5789 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
5790 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5791 emit_int8(0x71);
5792 emit_int8((unsigned char)(0xC0 | encode));
5793 emit_int8(shift & 0xFF);
5794 }
5795
5796 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5797 assert(UseAVX > 0, "requires some form of AVX");
5798 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5799 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
5800 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5801 emit_int8(0x72);
5802 emit_int8((unsigned char)(0xC0 | encode));
5803 emit_int8(shift & 0xFF);
5804 }
5805
5806 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5807 assert(UseAVX > 0, "requires some form of AVX");
5808 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5809 attributes.set_rex_vex_w_reverted();
5810 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
5811 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5812 emit_int8(0x73);
5813 emit_int8((unsigned char)(0xC0 | encode));
5814 emit_int8(shift & 0xFF);
5815 }
5816
5817 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5818 assert(UseAVX > 0, "requires some form of AVX");
5819 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5820 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5821 emit_int8((unsigned char)0xD1);
5822 emit_int8((unsigned char)(0xC0 | encode));
5823 }
5824
5825 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5826 assert(UseAVX > 0, "requires some form of AVX");
5827 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5828 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5829 emit_int8((unsigned char)0xD2);
5830 emit_int8((unsigned char)(0xC0 | encode));
5831 }
5832
5833 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5834 assert(UseAVX > 0, "requires some form of AVX");
5835 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5836 attributes.set_rex_vex_w_reverted();
5837 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5838 emit_int8((unsigned char)0xD3);
5839 emit_int8((unsigned char)(0xC0 | encode));
5840 }
5841
5842 // Shift packed integers arithmetically right by specified number of bits.
5843 void Assembler::psraw(XMMRegister dst, int shift) {
5844 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5845 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5846 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
5847 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5848 emit_int8(0x71);
5849 emit_int8((unsigned char)(0xC0 | encode));
5850 emit_int8(shift & 0xFF);
5851 }
5852
5853 void Assembler::psrad(XMMRegister dst, int shift) {
5854 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5855 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5856 // XMM4 is for /4 encoding: 66 0F 72 /4 ib
5857 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5858 emit_int8(0x72);
5859 emit_int8((unsigned char)(0xC0 | encode));
5860 emit_int8(shift & 0xFF);
5861 }
5862
5863 void Assembler::psraw(XMMRegister dst, XMMRegister shift) {
5864 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5865 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5866 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5867 emit_int8((unsigned char)0xE1);
5868 emit_int8((unsigned char)(0xC0 | encode));
5869 }
5870
5871 void Assembler::psrad(XMMRegister dst, XMMRegister shift) {
5872 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5873 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5874 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5875 emit_int8((unsigned char)0xE2);
5876 emit_int8((unsigned char)(0xC0 | encode));
5877 }
5878
5879 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5880 assert(UseAVX > 0, "requires some form of AVX");
5881 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5882 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
5883 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5884 emit_int8(0x71);
5885 emit_int8((unsigned char)(0xC0 | encode));
5886 emit_int8(shift & 0xFF);
5887 }
5888
5889 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5890 assert(UseAVX > 0, "requires some form of AVX");
5891 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5892 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
5893 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5894 emit_int8(0x72);
5895 emit_int8((unsigned char)(0xC0 | encode));
5896 emit_int8(shift & 0xFF);
5897 }
5898
5899 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5900 assert(UseAVX > 0, "requires some form of AVX");
5901 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5902 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5903 emit_int8((unsigned char)0xE1);
5904 emit_int8((unsigned char)(0xC0 | encode));
5905 }
5906
5907 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5908 assert(UseAVX > 0, "requires some form of AVX");
5909 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5910 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5911 emit_int8((unsigned char)0xE2);
5912 emit_int8((unsigned char)(0xC0 | encode));
5913 }
5914
5915
5916 // logical operations packed integers
5917 void Assembler::pand(XMMRegister dst, XMMRegister src) {
5918 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5919 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5920 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5921 emit_int8((unsigned char)0xDB);
5922 emit_int8((unsigned char)(0xC0 | encode));
5923 }
5924
5925 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5926 assert(UseAVX > 0, "requires some form of AVX");
5927 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5928 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5929 emit_int8((unsigned char)0xDB);
5930 emit_int8((unsigned char)(0xC0 | encode));
5931 }
5932
5933 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5934 assert(UseAVX > 0, "requires some form of AVX");
5935 InstructionMark im(this);
5936 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5937 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5938 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5939 emit_int8((unsigned char)0xDB);
5940 emit_operand(dst, src);
5941 }
5942
5943 void Assembler::pandn(XMMRegister dst, XMMRegister src) {
5944 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5945 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5946 attributes.set_rex_vex_w_reverted();
5947 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5948 emit_int8((unsigned char)0xDF);
5949 emit_int8((unsigned char)(0xC0 | encode));
5950 }
5951
5952 void Assembler::por(XMMRegister dst, XMMRegister src) {
5953 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5954 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5955 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5956 emit_int8((unsigned char)0xEB);
5957 emit_int8((unsigned char)(0xC0 | encode));
5958 }
5959
5960 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5961 assert(UseAVX > 0, "requires some form of AVX");
5962 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5963 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5964 emit_int8((unsigned char)0xEB);
5965 emit_int8((unsigned char)(0xC0 | encode));
5966 }
5967
5968 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5969 assert(UseAVX > 0, "requires some form of AVX");
5970 InstructionMark im(this);
5971 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5972 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5973 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5974 emit_int8((unsigned char)0xEB);
5975 emit_operand(dst, src);
5976 }
5977
5978 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
5979 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5980 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5981 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5982 emit_int8((unsigned char)0xEF);
5983 emit_int8((unsigned char)(0xC0 | encode));
5984 }
5985
5986 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5987 assert(UseAVX > 0, "requires some form of AVX");
5988 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5989 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5990 emit_int8((unsigned char)0xEF);
5991 emit_int8((unsigned char)(0xC0 | encode));
5992 }
5993
5994 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5995 assert(UseAVX > 0, "requires some form of AVX");
5996 InstructionMark im(this);
5997 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5998 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5999 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6000 emit_int8((unsigned char)0xEF);
6001 emit_operand(dst, src);
6002 }
6003
6004
6005 // vinserti forms
6006
6007 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6008 assert(VM_Version::supports_avx2(), "");
6009 assert(imm8 <= 0x01, "imm8: %u", imm8);
6010 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
6011 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6012 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6013 emit_int8(0x38);
6014 emit_int8((unsigned char)(0xC0 | encode));
6015 // 0x00 - insert into lower 128 bits
6016 // 0x01 - insert into upper 128 bits
6017 emit_int8(imm8 & 0x01);
6018 }
6019
6020 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6021 assert(VM_Version::supports_avx2(), "");
6022 assert(dst != xnoreg, "sanity");
6023 assert(imm8 <= 0x01, "imm8: %u", imm8);
6024 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
6025 InstructionMark im(this);
6026 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6027 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6028 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6029 emit_int8(0x38);
6030 emit_operand(dst, src);
6031 // 0x00 - insert into lower 128 bits
6032 // 0x01 - insert into upper 128 bits
6033 emit_int8(imm8 & 0x01);
6034 }
6035
6036 void Assembler::vinserti32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6037 assert(VM_Version::supports_evex(), "");
6038 assert(imm8 <= 0x03, "imm8: %u", imm8);
6039 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6040 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6041 emit_int8(0x38);
6042 emit_int8((unsigned char)(0xC0 | encode));
6043 // 0x00 - insert into q0 128 bits (0..127)
6044 // 0x01 - insert into q1 128 bits (128..255)
6045 // 0x02 - insert into q2 128 bits (256..383)
6046 // 0x03 - insert into q3 128 bits (384..511)
6047 emit_int8(imm8 & 0x03);
6048 }
6049
6050 void Assembler::vinserti32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6051 assert(VM_Version::supports_avx(), "");
6052 assert(dst != xnoreg, "sanity");
6053 assert(imm8 <= 0x03, "imm8: %u", imm8);
6054 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
6055 InstructionMark im(this);
6056 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6057 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6058 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6059 emit_int8(0x18);
6060 emit_operand(dst, src);
6061 // 0x00 - insert into q0 128 bits (0..127)
6062 // 0x01 - insert into q1 128 bits (128..255)
6063 // 0x02 - insert into q2 128 bits (256..383)
6064 // 0x03 - insert into q3 128 bits (384..511)
6065 emit_int8(imm8 & 0x03);
6066 }
6067
6068 void Assembler::vinserti64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6069 assert(VM_Version::supports_evex(), "");
6070 assert(imm8 <= 0x01, "imm8: %u", imm8);
6071 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6072 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6073 emit_int8(0x38);
6074 emit_int8((unsigned char)(0xC0 | encode));
6075 // 0x00 - insert into lower 256 bits
6076 // 0x01 - insert into upper 256 bits
6077 emit_int8(imm8 & 0x01);
6078 }
6079
6080
6081 // vinsertf forms
6082
6083 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6084 assert(VM_Version::supports_avx(), "");
6085 assert(imm8 <= 0x01, "imm8: %u", imm8);
6086 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
6087 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6088 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6089 emit_int8(0x18);
6090 emit_int8((unsigned char)(0xC0 | encode));
6091 // 0x00 - insert into lower 128 bits
6092 // 0x01 - insert into upper 128 bits
6093 emit_int8(imm8 & 0x01);
6094 }
6095
6096 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6097 assert(VM_Version::supports_avx(), "");
6098 assert(dst != xnoreg, "sanity");
6099 assert(imm8 <= 0x01, "imm8: %u", imm8);
6100 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
6101 InstructionMark im(this);
6102 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6103 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6104 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6105 emit_int8(0x18);
6106 emit_operand(dst, src);
6107 // 0x00 - insert into lower 128 bits
6108 // 0x01 - insert into upper 128 bits
6109 emit_int8(imm8 & 0x01);
6110 }
6111
6112 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6113 assert(VM_Version::supports_evex(), "");
6114 assert(imm8 <= 0x03, "imm8: %u", imm8);
6115 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6116 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6117 emit_int8(0x18);
6118 emit_int8((unsigned char)(0xC0 | encode));
6119 // 0x00 - insert into q0 128 bits (0..127)
6120 // 0x01 - insert into q1 128 bits (128..255)
6121 // 0x02 - insert into q2 128 bits (256..383)
6122 // 0x03 - insert into q3 128 bits (384..511)
6123 emit_int8(imm8 & 0x03);
6124 }
6125
6126 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6127 assert(VM_Version::supports_avx(), "");
6128 assert(dst != xnoreg, "sanity");
6129 assert(imm8 <= 0x03, "imm8: %u", imm8);
6130 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
6131 InstructionMark im(this);
6132 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6133 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6134 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6135 emit_int8(0x18);
6136 emit_operand(dst, src);
6137 // 0x00 - insert into q0 128 bits (0..127)
6138 // 0x01 - insert into q1 128 bits (128..255)
6139 // 0x02 - insert into q2 128 bits (256..383)
6140 // 0x03 - insert into q3 128 bits (384..511)
6141 emit_int8(imm8 & 0x03);
6142 }
6143
6144 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6145 assert(VM_Version::supports_evex(), "");
6146 assert(imm8 <= 0x01, "imm8: %u", imm8);
6147 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6148 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6149 emit_int8(0x1A);
6150 emit_int8((unsigned char)(0xC0 | encode));
6151 // 0x00 - insert into lower 256 bits
6152 // 0x01 - insert into upper 256 bits
6153 emit_int8(imm8 & 0x01);
6154 }
6155
6156 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6157 assert(VM_Version::supports_evex(), "");
6158 assert(dst != xnoreg, "sanity");
6159 assert(imm8 <= 0x01, "imm8: %u", imm8);
6160 InstructionMark im(this);
6161 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6162 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_64bit);
6163 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6164 emit_int8(0x1A);
6165 emit_operand(dst, src);
6166 // 0x00 - insert into lower 256 bits
6167 // 0x01 - insert into upper 256 bits
6168 emit_int8(imm8 & 0x01);
6169 }
6170
6171
6172 // vextracti forms
6173
6174 void Assembler::vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6175 assert(VM_Version::supports_avx(), "");
6176 assert(imm8 <= 0x01, "imm8: %u", imm8);
6177 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
6178 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6179 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6180 emit_int8(0x39);
6181 emit_int8((unsigned char)(0xC0 | encode));
6182 // 0x00 - extract from lower 128 bits
6183 // 0x01 - extract from upper 128 bits
6184 emit_int8(imm8 & 0x01);
6185 }
6186
6187 void Assembler::vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
6188 assert(VM_Version::supports_avx2(), "");
6189 assert(src != xnoreg, "sanity");
6190 assert(imm8 <= 0x01, "imm8: %u", imm8);
6191 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
6192 InstructionMark im(this);
6193 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6194 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6195 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6196 emit_int8(0x39);
6197 emit_operand(src, dst);
6198 // 0x00 - extract from lower 128 bits
6199 // 0x01 - extract from upper 128 bits
6200 emit_int8(imm8 & 0x01);
6201 }
6202
6203 void Assembler::vextracti32x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6204 assert(VM_Version::supports_avx(), "");
6205 assert(imm8 <= 0x03, "imm8: %u", imm8);
6206 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
6207 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6208 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6209 emit_int8(0x39);
6210 emit_int8((unsigned char)(0xC0 | encode));
6211 // 0x00 - extract from bits 127:0
6212 // 0x01 - extract from bits 255:128
6213 // 0x02 - extract from bits 383:256
6214 // 0x03 - extract from bits 511:384
6215 emit_int8(imm8 & 0x03);
6216 }
6217
6218 void Assembler::vextracti32x4(Address dst, XMMRegister src, uint8_t imm8) {
6219 assert(VM_Version::supports_evex(), "");
6220 assert(src != xnoreg, "sanity");
6221 assert(imm8 <= 0x03, "imm8: %u", imm8);
6222 InstructionMark im(this);
6223 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6224 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6225 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6226 emit_int8(0x39);
6227 emit_operand(src, dst);
6228 // 0x00 - extract from bits 127:0
6229 // 0x01 - extract from bits 255:128
6230 // 0x02 - extract from bits 383:256
6231 // 0x03 - extract from bits 511:384
6232 emit_int8(imm8 & 0x03);
6233 }
6234
6235 void Assembler::vextracti64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6236 assert(VM_Version::supports_avx512dq(), "");
6237 assert(imm8 <= 0x03, "imm8: %u", imm8);
6238 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6239 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6240 emit_int8(0x39);
6241 emit_int8((unsigned char)(0xC0 | encode));
6242 // 0x00 - extract from bits 127:0
6243 // 0x01 - extract from bits 255:128
6244 // 0x02 - extract from bits 383:256
6245 // 0x03 - extract from bits 511:384
6246 emit_int8(imm8 & 0x03);
6247 }
6248
6249 void Assembler::vextracti64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6250 assert(VM_Version::supports_evex(), "");
6251 assert(imm8 <= 0x01, "imm8: %u", imm8);
6252 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6253 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6254 emit_int8(0x3B);
6255 emit_int8((unsigned char)(0xC0 | encode));
6256 // 0x00 - extract from lower 256 bits
6257 // 0x01 - extract from upper 256 bits
6258 emit_int8(imm8 & 0x01);
6259 }
6260
6261
6262 // vextractf forms
6263
6264 void Assembler::vextractf128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6265 assert(VM_Version::supports_avx(), "");
6266 assert(imm8 <= 0x01, "imm8: %u", imm8);
6267 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
6268 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6269 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6270 emit_int8(0x19);
6271 emit_int8((unsigned char)(0xC0 | encode));
6272 // 0x00 - extract from lower 128 bits
6273 // 0x01 - extract from upper 128 bits
6274 emit_int8(imm8 & 0x01);
6275 }
6276
6277 void Assembler::vextractf128(Address dst, XMMRegister src, uint8_t imm8) {
6278 assert(VM_Version::supports_avx(), "");
6279 assert(src != xnoreg, "sanity");
6280 assert(imm8 <= 0x01, "imm8: %u", imm8);
6281 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
6282 InstructionMark im(this);
6283 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6284 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6285 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6286 emit_int8(0x19);
6287 emit_operand(src, dst);
6288 // 0x00 - extract from lower 128 bits
6289 // 0x01 - extract from upper 128 bits
6290 emit_int8(imm8 & 0x01);
6291 }
6292
6293 void Assembler::vextractf32x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6294 assert(VM_Version::supports_avx(), "");
6295 assert(imm8 <= 0x03, "imm8: %u", imm8);
6296 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
6297 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6298 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6299 emit_int8(0x19);
6300 emit_int8((unsigned char)(0xC0 | encode));
6301 // 0x00 - extract from bits 127:0
6302 // 0x01 - extract from bits 255:128
6303 // 0x02 - extract from bits 383:256
6304 // 0x03 - extract from bits 511:384
6305 emit_int8(imm8 & 0x03);
6306 }
6307
6308 void Assembler::vextractf32x4(Address dst, XMMRegister src, uint8_t imm8) {
6309 assert(VM_Version::supports_evex(), "");
6310 assert(src != xnoreg, "sanity");
6311 assert(imm8 <= 0x03, "imm8: %u", imm8);
6312 InstructionMark im(this);
6313 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6314 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6315 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6316 emit_int8(0x19);
6317 emit_operand(src, dst);
6318 // 0x00 - extract from bits 127:0
6319 // 0x01 - extract from bits 255:128
6320 // 0x02 - extract from bits 383:256
6321 // 0x03 - extract from bits 511:384
6322 emit_int8(imm8 & 0x03);
6323 }
6324
6325 void Assembler::vextractf64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6326 assert(VM_Version::supports_avx512dq(), "");
6327 assert(imm8 <= 0x03, "imm8: %u", imm8);
6328 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6329 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6330 emit_int8(0x19);
6331 emit_int8((unsigned char)(0xC0 | encode));
6332 // 0x00 - extract from bits 127:0
6333 // 0x01 - extract from bits 255:128
6334 // 0x02 - extract from bits 383:256
6335 // 0x03 - extract from bits 511:384
6336 emit_int8(imm8 & 0x03);
6337 }
6338
6339 void Assembler::vextractf64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6340 assert(VM_Version::supports_evex(), "");
6341 assert(imm8 <= 0x01, "imm8: %u", imm8);
6342 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6343 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6344 emit_int8(0x1B);
6345 emit_int8((unsigned char)(0xC0 | encode));
6346 // 0x00 - extract from lower 256 bits
6347 // 0x01 - extract from upper 256 bits
6348 emit_int8(imm8 & 0x01);
6349 }
6350
6351 void Assembler::vextractf64x4(Address dst, XMMRegister src, uint8_t imm8) {
6352 assert(VM_Version::supports_evex(), "");
6353 assert(src != xnoreg, "sanity");
6354 assert(imm8 <= 0x01, "imm8: %u", imm8);
6355 InstructionMark im(this);
6356 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6357 attributes.set_address_attributes(/* tuple_type */ EVEX_T4,/* input_size_in_bits */ EVEX_64bit);
6358 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6359 emit_int8(0x1B);
6360 emit_operand(src, dst);
6361 // 0x00 - extract from lower 256 bits
6362 // 0x01 - extract from upper 256 bits
6363 emit_int8(imm8 & 0x01);
6364 }
6365
6366
6367 // legacy word/dword replicate
6368 void Assembler::vpbroadcastw(XMMRegister dst, XMMRegister src) {
6369 assert(VM_Version::supports_avx2(), "");
6370 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6371 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6372 emit_int8(0x79);
6373 emit_int8((unsigned char)(0xC0 | encode));
6374 }
6375
6376 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src) {
6377 assert(VM_Version::supports_avx2(), "");
6378 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6379 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6380 emit_int8(0x58);
6381 emit_int8((unsigned char)(0xC0 | encode));
6382 }
6383
6384
6385 // xmm/mem sourced byte/word/dword/qword replicate
6386
6387 // duplicate 1-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
6388 void Assembler::evpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len) {
6389 assert(VM_Version::supports_evex(), "");
6390 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6391 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6392 emit_int8(0x78);
6393 emit_int8((unsigned char)(0xC0 | encode));
6394 }
6395
6396 void Assembler::evpbroadcastb(XMMRegister dst, Address src, int vector_len) {
6397 assert(VM_Version::supports_evex(), "");
6398 assert(dst != xnoreg, "sanity");
6399 InstructionMark im(this);
6400 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6401 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
6402 // swap src<->dst for encoding
6403 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6404 emit_int8(0x78);
6405 emit_operand(dst, src);
6406 }
6407
6408 // duplicate 2-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
6409 void Assembler::evpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len) {
6410 assert(VM_Version::supports_evex(), "");
6411 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6412 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6413 emit_int8(0x79);
6414 emit_int8((unsigned char)(0xC0 | encode));
6415 }
6416
6417 void Assembler::evpbroadcastw(XMMRegister dst, Address src, int vector_len) {
6418 assert(VM_Version::supports_evex(), "");
6419 assert(dst != xnoreg, "sanity");
6420 InstructionMark im(this);
6421 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6422 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
6423 // swap src<->dst for encoding
6424 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6425 emit_int8(0x79);
6426 emit_operand(dst, src);
6427 }
6428
6429 // duplicate 4-byte integer data from src into programmed locations in dest : requires AVX512VL
6430 void Assembler::evpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len) {
6431 assert(VM_Version::supports_evex(), "");
6432 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6433 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6434 emit_int8(0x58);
6435 emit_int8((unsigned char)(0xC0 | encode));
6436 }
6437
6438 void Assembler::evpbroadcastd(XMMRegister dst, Address src, int vector_len) {
6439 assert(VM_Version::supports_evex(), "");
6440 assert(dst != xnoreg, "sanity");
6441 InstructionMark im(this);
6442 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6443 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
6444 // swap src<->dst for encoding
6445 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6446 emit_int8(0x58);
6447 emit_operand(dst, src);
6448 }
6449
6450 // duplicate 8-byte integer data from src into programmed locations in dest : requires AVX512VL
6451 void Assembler::evpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len) {
6452 assert(VM_Version::supports_evex(), "");
6453 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6454 attributes.set_rex_vex_w_reverted();
6455 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6456 emit_int8(0x59);
6457 emit_int8((unsigned char)(0xC0 | encode));
6458 }
6459
6460 void Assembler::evpbroadcastq(XMMRegister dst, Address src, int vector_len) {
6461 assert(VM_Version::supports_evex(), "");
6462 assert(dst != xnoreg, "sanity");
6463 InstructionMark im(this);
6464 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6465 attributes.set_rex_vex_w_reverted();
6466 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6467 // swap src<->dst for encoding
6468 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6469 emit_int8(0x59);
6470 emit_operand(dst, src);
6471 }
6472
6473
6474 // scalar single/double precision replicate
6475
6476 // duplicate single precision data from src into programmed locations in dest : requires AVX512VL
6477 void Assembler::evpbroadcastss(XMMRegister dst, XMMRegister src, int vector_len) {
6478 assert(VM_Version::supports_evex(), "");
6479 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6480 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6481 emit_int8(0x18);
6482 emit_int8((unsigned char)(0xC0 | encode));
6483 }
6484
6485 void Assembler::evpbroadcastss(XMMRegister dst, Address src, int vector_len) {
6486 assert(VM_Version::supports_evex(), "");
6487 assert(dst != xnoreg, "sanity");
6488 InstructionMark im(this);
6489 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6490 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
6491 // swap src<->dst for encoding
6492 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6493 emit_int8(0x18);
6494 emit_operand(dst, src);
6495 }
6496
6497 // duplicate double precision data from src into programmed locations in dest : requires AVX512VL
6498 void Assembler::evpbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len) {
6499 assert(VM_Version::supports_evex(), "");
6500 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6501 attributes.set_rex_vex_w_reverted();
6502 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6503 emit_int8(0x19);
6504 emit_int8((unsigned char)(0xC0 | encode));
6505 }
6506
6507 void Assembler::evpbroadcastsd(XMMRegister dst, Address src, int vector_len) {
6508 assert(VM_Version::supports_evex(), "");
6509 assert(dst != xnoreg, "sanity");
6510 InstructionMark im(this);
6511 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6512 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6513 attributes.set_rex_vex_w_reverted();
6514 // swap src<->dst for encoding
6515 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6516 emit_int8(0x19);
6517 emit_operand(dst, src);
6518 }
6519
6520
6521 // gpr source broadcast forms
6522
6523 // duplicate 1-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
6524 void Assembler::evpbroadcastb(XMMRegister dst, Register src, int vector_len) {
6525 assert(VM_Version::supports_evex(), "");
6526 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6527 attributes.set_is_evex_instruction();
6528 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6529 emit_int8(0x7A);
6530 emit_int8((unsigned char)(0xC0 | encode));
6531 }
6532
6533 // duplicate 2-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
6534 void Assembler::evpbroadcastw(XMMRegister dst, Register src, int vector_len) {
6535 assert(VM_Version::supports_evex(), "");
6536 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6537 attributes.set_is_evex_instruction();
6538 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6539 emit_int8(0x7B);
6540 emit_int8((unsigned char)(0xC0 | encode));
6541 }
6542
6543 // duplicate 4-byte integer data from src into programmed locations in dest : requires AVX512VL
6544 void Assembler::evpbroadcastd(XMMRegister dst, Register src, int vector_len) {
6545 assert(VM_Version::supports_evex(), "");
6546 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6547 attributes.set_is_evex_instruction();
6548 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6549 emit_int8(0x7C);
6550 emit_int8((unsigned char)(0xC0 | encode));
6551 }
6552
6553 // duplicate 8-byte integer data from src into programmed locations in dest : requires AVX512VL
6554 void Assembler::evpbroadcastq(XMMRegister dst, Register src, int vector_len) {
6555 assert(VM_Version::supports_evex(), "");
6556 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6557 attributes.set_is_evex_instruction();
6558 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6559 emit_int8(0x7C);
6560 emit_int8((unsigned char)(0xC0 | encode));
6561 }
6562
6563
6564 // Carry-Less Multiplication Quadword
6565 void Assembler::pclmulqdq(XMMRegister dst, XMMRegister src, int mask) {
6566 assert(VM_Version::supports_clmul(), "");
6567 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6568 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6569 emit_int8(0x44);
6570 emit_int8((unsigned char)(0xC0 | encode));
6571 emit_int8((unsigned char)mask);
6572 }
6573
6574 // Carry-Less Multiplication Quadword
6575 void Assembler::vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask) {
6576 assert(VM_Version::supports_avx() && VM_Version::supports_clmul(), "");
6577 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6578 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6579 emit_int8(0x44);
6580 emit_int8((unsigned char)(0xC0 | encode));
6581 emit_int8((unsigned char)mask);
6582 }
6583
6584 void Assembler::vzeroupper() {
6585 assert(VM_Version::supports_avx(), "");
6586 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6587 (void)vex_prefix_and_encode(0, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6588 emit_int8(0x77);
6589 }
6590
6591 #ifndef _LP64
6592 // 32bit only pieces of the assembler
6593
6594 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
6595 // NO PREFIX AS NEVER 64BIT
6596 InstructionMark im(this);
6597 emit_int8((unsigned char)0x81);
6598 emit_int8((unsigned char)(0xF8 | src1->encoding()));
6599 emit_data(imm32, rspec, 0);
6600 }
6601
6602 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
6603 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
6604 InstructionMark im(this);
6605 emit_int8((unsigned char)0x81);
6606 emit_operand(rdi, src1);
6607 emit_data(imm32, rspec, 0);
6608 }
6609
6610 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax,
6611 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded
6612 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise.
6613 void Assembler::cmpxchg8(Address adr) {
6614 InstructionMark im(this);
6615 emit_int8(0x0F);
6616 emit_int8((unsigned char)0xC7);
6617 emit_operand(rcx, adr);
6618 }
6619
6620 void Assembler::decl(Register dst) {
6621 // Don't use it directly. Use MacroAssembler::decrementl() instead.
6622 emit_int8(0x48 | dst->encoding());
6623 }
6624
6625 #endif // _LP64
6626
6627 // 64bit typically doesn't use the x87 but needs to for the trig funcs
6628
6629 void Assembler::fabs() {
6630 emit_int8((unsigned char)0xD9);
6631 emit_int8((unsigned char)0xE1);
6632 }
6633
6634 void Assembler::fadd(int i) {
6635 emit_farith(0xD8, 0xC0, i);
6636 }
6637
6638 void Assembler::fadd_d(Address src) {
6639 InstructionMark im(this);
6640 emit_int8((unsigned char)0xDC);
6641 emit_operand32(rax, src);
6642 }
6643
6644 void Assembler::fadd_s(Address src) {
6645 InstructionMark im(this);
6646 emit_int8((unsigned char)0xD8);
6647 emit_operand32(rax, src);
6648 }
6649
6650 void Assembler::fadda(int i) {
6651 emit_farith(0xDC, 0xC0, i);
6652 }
6653
6654 void Assembler::faddp(int i) {
6655 emit_farith(0xDE, 0xC0, i);
6656 }
6657
6658 void Assembler::fchs() {
6659 emit_int8((unsigned char)0xD9);
6660 emit_int8((unsigned char)0xE0);
6661 }
6662
6663 void Assembler::fcom(int i) {
6664 emit_farith(0xD8, 0xD0, i);
6665 }
6666
6667 void Assembler::fcomp(int i) {
6668 emit_farith(0xD8, 0xD8, i);
6669 }
6670
6671 void Assembler::fcomp_d(Address src) {
6672 InstructionMark im(this);
6673 emit_int8((unsigned char)0xDC);
6674 emit_operand32(rbx, src);
6675 }
6676
6677 void Assembler::fcomp_s(Address src) {
6678 InstructionMark im(this);
6679 emit_int8((unsigned char)0xD8);
6680 emit_operand32(rbx, src);
6681 }
6682
6683 void Assembler::fcompp() {
6684 emit_int8((unsigned char)0xDE);
6685 emit_int8((unsigned char)0xD9);
6686 }
6687
6688 void Assembler::fcos() {
6689 emit_int8((unsigned char)0xD9);
6690 emit_int8((unsigned char)0xFF);
6691 }
6692
6693 void Assembler::fdecstp() {
6694 emit_int8((unsigned char)0xD9);
6695 emit_int8((unsigned char)0xF6);
6696 }
6697
6698 void Assembler::fdiv(int i) {
6699 emit_farith(0xD8, 0xF0, i);
6700 }
6701
6702 void Assembler::fdiv_d(Address src) {
6703 InstructionMark im(this);
6704 emit_int8((unsigned char)0xDC);
6705 emit_operand32(rsi, src);
6706 }
6707
6708 void Assembler::fdiv_s(Address src) {
6709 InstructionMark im(this);
6710 emit_int8((unsigned char)0xD8);
6711 emit_operand32(rsi, src);
6712 }
6713
6714 void Assembler::fdiva(int i) {
6715 emit_farith(0xDC, 0xF8, i);
6716 }
6717
6718 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994)
6719 // is erroneous for some of the floating-point instructions below.
6720
6721 void Assembler::fdivp(int i) {
6722 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong)
6723 }
6724
6725 void Assembler::fdivr(int i) {
6726 emit_farith(0xD8, 0xF8, i);
6727 }
6728
6729 void Assembler::fdivr_d(Address src) {
6730 InstructionMark im(this);
6731 emit_int8((unsigned char)0xDC);
6732 emit_operand32(rdi, src);
6733 }
6734
6735 void Assembler::fdivr_s(Address src) {
6736 InstructionMark im(this);
6737 emit_int8((unsigned char)0xD8);
6738 emit_operand32(rdi, src);
6739 }
6740
6741 void Assembler::fdivra(int i) {
6742 emit_farith(0xDC, 0xF0, i);
6743 }
6744
6745 void Assembler::fdivrp(int i) {
6746 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong)
6747 }
6748
6749 void Assembler::ffree(int i) {
6750 emit_farith(0xDD, 0xC0, i);
6751 }
6752
6753 void Assembler::fild_d(Address adr) {
6754 InstructionMark im(this);
6755 emit_int8((unsigned char)0xDF);
6756 emit_operand32(rbp, adr);
6757 }
6758
6759 void Assembler::fild_s(Address adr) {
6760 InstructionMark im(this);
6761 emit_int8((unsigned char)0xDB);
6762 emit_operand32(rax, adr);
6763 }
6764
6765 void Assembler::fincstp() {
6766 emit_int8((unsigned char)0xD9);
6767 emit_int8((unsigned char)0xF7);
6768 }
6769
6770 void Assembler::finit() {
6771 emit_int8((unsigned char)0x9B);
6772 emit_int8((unsigned char)0xDB);
6773 emit_int8((unsigned char)0xE3);
6774 }
6775
6776 void Assembler::fist_s(Address adr) {
6777 InstructionMark im(this);
6778 emit_int8((unsigned char)0xDB);
6779 emit_operand32(rdx, adr);
6780 }
6781
6782 void Assembler::fistp_d(Address adr) {
6783 InstructionMark im(this);
6784 emit_int8((unsigned char)0xDF);
6785 emit_operand32(rdi, adr);
6786 }
6787
6788 void Assembler::fistp_s(Address adr) {
6789 InstructionMark im(this);
6790 emit_int8((unsigned char)0xDB);
6791 emit_operand32(rbx, adr);
6792 }
6793
6794 void Assembler::fld1() {
6795 emit_int8((unsigned char)0xD9);
6796 emit_int8((unsigned char)0xE8);
6797 }
6798
6799 void Assembler::fld_d(Address adr) {
6800 InstructionMark im(this);
6801 emit_int8((unsigned char)0xDD);
6802 emit_operand32(rax, adr);
6803 }
6804
6805 void Assembler::fld_s(Address adr) {
6806 InstructionMark im(this);
6807 emit_int8((unsigned char)0xD9);
6808 emit_operand32(rax, adr);
6809 }
6810
6811
6812 void Assembler::fld_s(int index) {
6813 emit_farith(0xD9, 0xC0, index);
6814 }
6815
6816 void Assembler::fld_x(Address adr) {
6817 InstructionMark im(this);
6818 emit_int8((unsigned char)0xDB);
6819 emit_operand32(rbp, adr);
6820 }
6821
6822 void Assembler::fldcw(Address src) {
6823 InstructionMark im(this);
6824 emit_int8((unsigned char)0xD9);
6825 emit_operand32(rbp, src);
6826 }
6827
6828 void Assembler::fldenv(Address src) {
6829 InstructionMark im(this);
6830 emit_int8((unsigned char)0xD9);
6831 emit_operand32(rsp, src);
6832 }
6833
6834 void Assembler::fldlg2() {
6835 emit_int8((unsigned char)0xD9);
6836 emit_int8((unsigned char)0xEC);
6837 }
6838
6839 void Assembler::fldln2() {
6840 emit_int8((unsigned char)0xD9);
6841 emit_int8((unsigned char)0xED);
6842 }
6843
6844 void Assembler::fldz() {
6845 emit_int8((unsigned char)0xD9);
6846 emit_int8((unsigned char)0xEE);
6847 }
6848
6849 void Assembler::flog() {
6850 fldln2();
6851 fxch();
6852 fyl2x();
6853 }
6854
6855 void Assembler::flog10() {
6856 fldlg2();
6857 fxch();
6858 fyl2x();
6859 }
6860
6861 void Assembler::fmul(int i) {
6862 emit_farith(0xD8, 0xC8, i);
6863 }
6864
6865 void Assembler::fmul_d(Address src) {
6866 InstructionMark im(this);
6867 emit_int8((unsigned char)0xDC);
6868 emit_operand32(rcx, src);
6869 }
6870
6871 void Assembler::fmul_s(Address src) {
6872 InstructionMark im(this);
6873 emit_int8((unsigned char)0xD8);
6874 emit_operand32(rcx, src);
6875 }
6876
6877 void Assembler::fmula(int i) {
6878 emit_farith(0xDC, 0xC8, i);
6879 }
6880
6881 void Assembler::fmulp(int i) {
6882 emit_farith(0xDE, 0xC8, i);
6883 }
6884
6885 void Assembler::fnsave(Address dst) {
6886 InstructionMark im(this);
6887 emit_int8((unsigned char)0xDD);
6888 emit_operand32(rsi, dst);
6889 }
6890
6891 void Assembler::fnstcw(Address src) {
6892 InstructionMark im(this);
6893 emit_int8((unsigned char)0x9B);
6894 emit_int8((unsigned char)0xD9);
6895 emit_operand32(rdi, src);
6896 }
6897
6898 void Assembler::fnstsw_ax() {
6899 emit_int8((unsigned char)0xDF);
6900 emit_int8((unsigned char)0xE0);
6901 }
6902
6903 void Assembler::fprem() {
6904 emit_int8((unsigned char)0xD9);
6905 emit_int8((unsigned char)0xF8);
6906 }
6907
6908 void Assembler::fprem1() {
6909 emit_int8((unsigned char)0xD9);
6910 emit_int8((unsigned char)0xF5);
6911 }
6912
6913 void Assembler::frstor(Address src) {
6914 InstructionMark im(this);
6915 emit_int8((unsigned char)0xDD);
6916 emit_operand32(rsp, src);
6917 }
6918
6919 void Assembler::fsin() {
6920 emit_int8((unsigned char)0xD9);
6921 emit_int8((unsigned char)0xFE);
6922 }
6923
6924 void Assembler::fsqrt() {
6925 emit_int8((unsigned char)0xD9);
6926 emit_int8((unsigned char)0xFA);
6927 }
6928
6929 void Assembler::fst_d(Address adr) {
6930 InstructionMark im(this);
6931 emit_int8((unsigned char)0xDD);
6932 emit_operand32(rdx, adr);
6933 }
6934
6935 void Assembler::fst_s(Address adr) {
6936 InstructionMark im(this);
6937 emit_int8((unsigned char)0xD9);
6938 emit_operand32(rdx, adr);
6939 }
6940
6941 void Assembler::fstp_d(Address adr) {
6942 InstructionMark im(this);
6943 emit_int8((unsigned char)0xDD);
6944 emit_operand32(rbx, adr);
6945 }
6946
6947 void Assembler::fstp_d(int index) {
6948 emit_farith(0xDD, 0xD8, index);
6949 }
6950
6951 void Assembler::fstp_s(Address adr) {
6952 InstructionMark im(this);
6953 emit_int8((unsigned char)0xD9);
6954 emit_operand32(rbx, adr);
6955 }
6956
6957 void Assembler::fstp_x(Address adr) {
6958 InstructionMark im(this);
6959 emit_int8((unsigned char)0xDB);
6960 emit_operand32(rdi, adr);
6961 }
6962
6963 void Assembler::fsub(int i) {
6964 emit_farith(0xD8, 0xE0, i);
6965 }
6966
6967 void Assembler::fsub_d(Address src) {
6968 InstructionMark im(this);
6969 emit_int8((unsigned char)0xDC);
6970 emit_operand32(rsp, src);
6971 }
6972
6973 void Assembler::fsub_s(Address src) {
6974 InstructionMark im(this);
6975 emit_int8((unsigned char)0xD8);
6976 emit_operand32(rsp, src);
6977 }
6978
6979 void Assembler::fsuba(int i) {
6980 emit_farith(0xDC, 0xE8, i);
6981 }
6982
6983 void Assembler::fsubp(int i) {
6984 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong)
6985 }
6986
6987 void Assembler::fsubr(int i) {
6988 emit_farith(0xD8, 0xE8, i);
6989 }
6990
6991 void Assembler::fsubr_d(Address src) {
6992 InstructionMark im(this);
6993 emit_int8((unsigned char)0xDC);
6994 emit_operand32(rbp, src);
6995 }
6996
6997 void Assembler::fsubr_s(Address src) {
6998 InstructionMark im(this);
6999 emit_int8((unsigned char)0xD8);
7000 emit_operand32(rbp, src);
7001 }
7002
7003 void Assembler::fsubra(int i) {
7004 emit_farith(0xDC, 0xE0, i);
7005 }
7006
7007 void Assembler::fsubrp(int i) {
7008 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong)
7009 }
7010
7011 void Assembler::ftan() {
7012 emit_int8((unsigned char)0xD9);
7013 emit_int8((unsigned char)0xF2);
7014 emit_int8((unsigned char)0xDD);
7015 emit_int8((unsigned char)0xD8);
7016 }
7017
7018 void Assembler::ftst() {
7019 emit_int8((unsigned char)0xD9);
7020 emit_int8((unsigned char)0xE4);
7021 }
7022
7023 void Assembler::fucomi(int i) {
7024 // make sure the instruction is supported (introduced for P6, together with cmov)
7025 guarantee(VM_Version::supports_cmov(), "illegal instruction");
7026 emit_farith(0xDB, 0xE8, i);
7027 }
7028
7029 void Assembler::fucomip(int i) {
7030 // make sure the instruction is supported (introduced for P6, together with cmov)
7031 guarantee(VM_Version::supports_cmov(), "illegal instruction");
7032 emit_farith(0xDF, 0xE8, i);
7033 }
7034
7035 void Assembler::fwait() {
7036 emit_int8((unsigned char)0x9B);
7037 }
7038
7039 void Assembler::fxch(int i) {
7040 emit_farith(0xD9, 0xC8, i);
7041 }
7042
7043 void Assembler::fyl2x() {
7044 emit_int8((unsigned char)0xD9);
7045 emit_int8((unsigned char)0xF1);
7046 }
7047
7048 void Assembler::frndint() {
7049 emit_int8((unsigned char)0xD9);
7050 emit_int8((unsigned char)0xFC);
7051 }
7052
7053 void Assembler::f2xm1() {
7054 emit_int8((unsigned char)0xD9);
7055 emit_int8((unsigned char)0xF0);
7056 }
7057
7058 void Assembler::fldl2e() {
7059 emit_int8((unsigned char)0xD9);
7060 emit_int8((unsigned char)0xEA);
7061 }
7062
7063 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding.
7064 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 };
7065 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding.
7066 static int simd_opc[4] = { 0, 0, 0x38, 0x3A };
7067
7068 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding.
7069 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
7070 if (pre > 0) {
7071 emit_int8(simd_pre[pre]);
7072 }
7073 if (rex_w) {
7074 prefixq(adr, xreg);
7075 } else {
7076 prefix(adr, xreg);
7077 }
7078 if (opc > 0) {
7079 emit_int8(0x0F);
7080 int opc2 = simd_opc[opc];
7081 if (opc2 > 0) {
7082 emit_int8(opc2);
7083 }
7084 }
7085 }
7086
7087 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
7088 if (pre > 0) {
7089 emit_int8(simd_pre[pre]);
7090 }
7091 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) : prefix_and_encode(dst_enc, src_enc);
7092 if (opc > 0) {
7093 emit_int8(0x0F);
7094 int opc2 = simd_opc[opc];
7095 if (opc2 > 0) {
7096 emit_int8(opc2);
7097 }
7098 }
7099 return encode;
7100 }
7101
7102
7103 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc) {
7104 int vector_len = _attributes->get_vector_len();
7105 bool vex_w = _attributes->is_rex_vex_w();
7106 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) {
7107 prefix(VEX_3bytes);
7108
7109 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0);
7110 byte1 = (~byte1) & 0xE0;
7111 byte1 |= opc;
7112 emit_int8(byte1);
7113
7114 int byte2 = ((~nds_enc) & 0xf) << 3;
7115 byte2 |= (vex_w ? VEX_W : 0) | ((vector_len > 0) ? 4 : 0) | pre;
7116 emit_int8(byte2);
7117 } else {
7118 prefix(VEX_2bytes);
7119
7120 int byte1 = vex_r ? VEX_R : 0;
7121 byte1 = (~byte1) & 0x80;
7122 byte1 |= ((~nds_enc) & 0xf) << 3;
7123 byte1 |= ((vector_len > 0 ) ? 4 : 0) | pre;
7124 emit_int8(byte1);
7125 }
7126 }
7127
7128 // This is a 4 byte encoding
7129 void Assembler::evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_r, bool evex_v, int nds_enc, VexSimdPrefix pre, VexOpcode opc){
7130 // EVEX 0x62 prefix
7131 prefix(EVEX_4bytes);
7132 bool vex_w = _attributes->is_rex_vex_w();
7133 int evex_encoding = (vex_w ? VEX_W : 0);
7134 // EVEX.b is not currently used for broadcast of single element or data rounding modes
7135 _attributes->set_evex_encoding(evex_encoding);
7136
7137 // P0: byte 2, initialized to RXBR`00mm
7138 // instead of not'd
7139 int byte2 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0) | (evex_r ? EVEX_Rb : 0);
7140 byte2 = (~byte2) & 0xF0;
7141 // confine opc opcode extensions in mm bits to lower two bits
7142 // of form {0F, 0F_38, 0F_3A}
7143 byte2 |= opc;
7144 emit_int8(byte2);
7145
7146 // P1: byte 3 as Wvvvv1pp
7147 int byte3 = ((~nds_enc) & 0xf) << 3;
7148 // p[10] is always 1
7149 byte3 |= EVEX_F;
7150 byte3 |= (vex_w & 1) << 7;
7151 // confine pre opcode extensions in pp bits to lower two bits
7152 // of form {66, F3, F2}
7153 byte3 |= pre;
7154 emit_int8(byte3);
7155
7156 // P2: byte 4 as zL'Lbv'aaa
7157 // kregs are implemented in the low 3 bits as aaa (hard code k1, it will be initialized for now)
7158 int byte4 = (_attributes->is_no_reg_mask()) ?
7159 0 :
7160 _attributes->get_embedded_opmask_register_specifier();
7161 // EVEX.v` for extending EVEX.vvvv or VIDX
7162 byte4 |= (evex_v ? 0: EVEX_V);
7163 // third EXEC.b for broadcast actions
7164 byte4 |= (_attributes->is_extended_context() ? EVEX_Rb : 0);
7165 // fourth EVEX.L'L for vector length : 0 is 128, 1 is 256, 2 is 512, currently we do not support 1024
7166 byte4 |= ((_attributes->get_vector_len())& 0x3) << 5;
7167 // last is EVEX.z for zero/merge actions
7168 byte4 |= (_attributes->is_clear_context() ? EVEX_Z : 0);
7169 emit_int8(byte4);
7170 }
7171
7172 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) {
7173 bool vex_r = ((xreg_enc & 8) == 8) ? 1 : 0;
7174 bool vex_b = adr.base_needs_rex();
7175 bool vex_x = adr.index_needs_rex();
7176 set_attributes(attributes);
7177 attributes->set_current_assembler(this);
7178
7179 // if vector length is turned off, revert to AVX for vectors smaller than 512-bit
7180 if (UseAVX > 2 && _legacy_mode_vl && attributes->uses_vl()) {
7181 switch (attributes->get_vector_len()) {
7182 case AVX_128bit:
7183 case AVX_256bit:
7184 attributes->set_is_legacy_mode();
7185 break;
7186 }
7187 }
7188
7189 // For pure EVEX check and see if this instruction
7190 // is allowed in legacy mode and has resources which will
7191 // fit in it. Pure EVEX instructions will use set_is_evex_instruction in their definition,
7192 // else that field is set when we encode to EVEX
7193 if (UseAVX > 2 && !attributes->is_legacy_mode() &&
7194 !_is_managed && !attributes->is_evex_instruction()) {
7195 if (!_legacy_mode_vl && attributes->get_vector_len() != AVX_512bit) {
7196 bool check_register_bank = NOT_IA32(true) IA32_ONLY(false);
7197 if (check_register_bank) {
7198 // check nds_enc and xreg_enc for upper bank usage
7199 if (nds_enc < 16 && xreg_enc < 16) {
7200 attributes->set_is_legacy_mode();
7201 }
7202 } else {
7203 attributes->set_is_legacy_mode();
7204 }
7205 }
7206 }
7207
7208 _is_managed = false;
7209 if (UseAVX > 2 && !attributes->is_legacy_mode())
7210 {
7211 bool evex_r = (xreg_enc >= 16);
7212 bool evex_v = (nds_enc >= 16);
7213 attributes->set_is_evex_instruction();
7214 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc);
7215 } else {
7216 if (UseAVX > 2 && attributes->is_rex_vex_w_reverted()) {
7217 attributes->set_rex_vex_w(false);
7218 }
7219 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc);
7220 }
7221 }
7222
7223 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) {
7224 bool vex_r = ((dst_enc & 8) == 8) ? 1 : 0;
7225 bool vex_b = ((src_enc & 8) == 8) ? 1 : 0;
7226 bool vex_x = false;
7227 set_attributes(attributes);
7228 attributes->set_current_assembler(this);
7229 bool check_register_bank = NOT_IA32(true) IA32_ONLY(false);
7230
7231 // if vector length is turned off, revert to AVX for vectors smaller than 512-bit
7232 if (UseAVX > 2 && _legacy_mode_vl && attributes->uses_vl()) {
7233 switch (attributes->get_vector_len()) {
7234 case AVX_128bit:
7235 case AVX_256bit:
7236 if (check_register_bank) {
7237 if (dst_enc >= 16 || nds_enc >= 16 || src_enc >= 16) {
7238 // up propagate arithmetic instructions to meet RA requirements
7239 attributes->set_vector_len(AVX_512bit);
7240 } else {
7241 attributes->set_is_legacy_mode();
7242 }
7243 } else {
7244 attributes->set_is_legacy_mode();
7245 }
7246 break;
7247 }
7248 }
7249
7250 // For pure EVEX check and see if this instruction
7251 // is allowed in legacy mode and has resources which will
7252 // fit in it. Pure EVEX instructions will use set_is_evex_instruction in their definition,
7253 // else that field is set when we encode to EVEX
7254 if (UseAVX > 2 && !attributes->is_legacy_mode() &&
7255 !_is_managed && !attributes->is_evex_instruction()) {
7256 if (!_legacy_mode_vl && attributes->get_vector_len() != AVX_512bit) {
7257 if (check_register_bank) {
7258 // check dst_enc, nds_enc and src_enc for upper bank usage
7259 if (dst_enc < 16 && nds_enc < 16 && src_enc < 16) {
7260 attributes->set_is_legacy_mode();
7261 }
7262 } else {
7263 attributes->set_is_legacy_mode();
7264 }
7265 }
7266 }
7267
7268 _is_managed = false;
7269 if (UseAVX > 2 && !attributes->is_legacy_mode())
7270 {
7271 bool evex_r = (dst_enc >= 16);
7272 bool evex_v = (nds_enc >= 16);
7273 // can use vex_x as bank extender on rm encoding
7274 vex_x = (src_enc >= 16);
7275 attributes->set_is_evex_instruction();
7276 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc);
7277 } else {
7278 if (UseAVX > 2 && attributes->is_rex_vex_w_reverted()) {
7279 attributes->set_rex_vex_w(false);
7280 }
7281 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc);
7282 }
7283
7284 // return modrm byte components for operands
7285 return (((dst_enc & 7) << 3) | (src_enc & 7));
7286 }
7287
7288
7289 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre,
7290 VexOpcode opc, InstructionAttr *attributes) {
7291 if (UseAVX > 0) {
7292 int xreg_enc = xreg->encoding();
7293 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
7294 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, attributes);
7295 } else {
7296 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding");
7297 rex_prefix(adr, xreg, pre, opc, attributes->is_rex_vex_w());
7298 }
7299 }
7300
7301 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre,
7302 VexOpcode opc, InstructionAttr *attributes) {
7303 int dst_enc = dst->encoding();
7304 int src_enc = src->encoding();
7305 if (UseAVX > 0) {
7306 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
7307 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, attributes);
7308 } else {
7309 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding");
7310 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, attributes->is_rex_vex_w());
7311 }
7312 }
7313
7314 void Assembler::cmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) {
7315 assert(VM_Version::supports_avx(), "");
7316 assert(!VM_Version::supports_evex(), "");
7317 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7318 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7319 emit_int8((unsigned char)0xC2);
7320 emit_int8((unsigned char)(0xC0 | encode));
7321 emit_int8((unsigned char)(0xF & cop));
7322 }
7323
7324 void Assembler::vpblendd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) {
7325 assert(VM_Version::supports_avx(), "");
7326 assert(!VM_Version::supports_evex(), "");
7327 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7328 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7329 emit_int8((unsigned char)0x4B);
7330 emit_int8((unsigned char)(0xC0 | encode));
7331 int src2_enc = src2->encoding();
7332 emit_int8((unsigned char)(0xF0 & src2_enc<<4));
7333 }
7334
7335 void Assembler::shlxl(Register dst, Register src1, Register src2) {
7336 assert(VM_Version::supports_bmi2(), "");
7337 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7338 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7339 emit_int8((unsigned char)0xF7);
7340 emit_int8((unsigned char)(0xC0 | encode));
7341 }
7342
7343 void Assembler::shlxq(Register dst, Register src1, Register src2) {
7344 assert(VM_Version::supports_bmi2(), "");
7345 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7346 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7347 emit_int8((unsigned char)0xF7);
7348 emit_int8((unsigned char)(0xC0 | encode));
7349 }
7350
7351 #ifndef _LP64
7352
7353 void Assembler::incl(Register dst) {
7354 // Don't use it directly. Use MacroAssembler::incrementl() instead.
7355 emit_int8(0x40 | dst->encoding());
7356 }
7357
7358 void Assembler::lea(Register dst, Address src) {
7359 leal(dst, src);
7360 }
7361
7362 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
7363 InstructionMark im(this);
7364 emit_int8((unsigned char)0xC7);
7365 emit_operand(rax, dst);
7366 emit_data((int)imm32, rspec, 0);
7367 }
7368
7369 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
7370 InstructionMark im(this);
7371 int encode = prefix_and_encode(dst->encoding());
7372 emit_int8((unsigned char)(0xB8 | encode));
7373 emit_data((int)imm32, rspec, 0);
7374 }
7375
7376 void Assembler::popa() { // 32bit
7377 emit_int8(0x61);
7378 }
7379
7380 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
7381 InstructionMark im(this);
7382 emit_int8(0x68);
7383 emit_data(imm32, rspec, 0);
7384 }
7385
7386 void Assembler::pusha() { // 32bit
7387 emit_int8(0x60);
7388 }
7389
7390 void Assembler::set_byte_if_not_zero(Register dst) {
7391 emit_int8(0x0F);
7392 emit_int8((unsigned char)0x95);
7393 emit_int8((unsigned char)(0xE0 | dst->encoding()));
7394 }
7395
7396 void Assembler::shldl(Register dst, Register src) {
7397 emit_int8(0x0F);
7398 emit_int8((unsigned char)0xA5);
7399 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
7400 }
7401
7402 // 0F A4 / r ib
7403 void Assembler::shldl(Register dst, Register src, int8_t imm8) {
7404 emit_int8(0x0F);
7405 emit_int8((unsigned char)0xA4);
7406 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
7407 emit_int8(imm8);
7408 }
7409
7410 void Assembler::shrdl(Register dst, Register src) {
7411 emit_int8(0x0F);
7412 emit_int8((unsigned char)0xAD);
7413 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
7414 }
7415
7416 #else // LP64
7417
7418 void Assembler::set_byte_if_not_zero(Register dst) {
7419 int enc = prefix_and_encode(dst->encoding(), true);
7420 emit_int8(0x0F);
7421 emit_int8((unsigned char)0x95);
7422 emit_int8((unsigned char)(0xE0 | enc));
7423 }
7424
7425 // 64bit only pieces of the assembler
7426 // This should only be used by 64bit instructions that can use rip-relative
7427 // it cannot be used by instructions that want an immediate value.
7428
7429 bool Assembler::reachable(AddressLiteral adr) {
7430 int64_t disp;
7431 // None will force a 64bit literal to the code stream. Likely a placeholder
7432 // for something that will be patched later and we need to certain it will
7433 // always be reachable.
7434 if (adr.reloc() == relocInfo::none) {
7435 return false;
7436 }
7437 if (adr.reloc() == relocInfo::internal_word_type) {
7438 // This should be rip relative and easily reachable.
7439 return true;
7440 }
7441 if (adr.reloc() == relocInfo::virtual_call_type ||
7442 adr.reloc() == relocInfo::opt_virtual_call_type ||
7443 adr.reloc() == relocInfo::static_call_type ||
7444 adr.reloc() == relocInfo::static_stub_type ) {
7445 // This should be rip relative within the code cache and easily
7446 // reachable until we get huge code caches. (At which point
7447 // ic code is going to have issues).
7448 return true;
7449 }
7450 if (adr.reloc() != relocInfo::external_word_type &&
7451 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special
7452 adr.reloc() != relocInfo::poll_type && // relocs to identify them
7453 adr.reloc() != relocInfo::runtime_call_type ) {
7454 return false;
7455 }
7456
7457 // Stress the correction code
7458 if (ForceUnreachable) {
7459 // Must be runtimecall reloc, see if it is in the codecache
7460 // Flipping stuff in the codecache to be unreachable causes issues
7461 // with things like inline caches where the additional instructions
7462 // are not handled.
7463 if (CodeCache::find_blob(adr._target) == NULL) {
7464 return false;
7465 }
7466 }
7467 // For external_word_type/runtime_call_type if it is reachable from where we
7468 // are now (possibly a temp buffer) and where we might end up
7469 // anywhere in the codeCache then we are always reachable.
7470 // This would have to change if we ever save/restore shared code
7471 // to be more pessimistic.
7472 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int));
7473 if (!is_simm32(disp)) return false;
7474 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int));
7475 if (!is_simm32(disp)) return false;
7476
7477 disp = (int64_t)adr._target - ((int64_t)pc() + sizeof(int));
7478
7479 // Because rip relative is a disp + address_of_next_instruction and we
7480 // don't know the value of address_of_next_instruction we apply a fudge factor
7481 // to make sure we will be ok no matter the size of the instruction we get placed into.
7482 // We don't have to fudge the checks above here because they are already worst case.
7483
7484 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal
7485 // + 4 because better safe than sorry.
7486 const int fudge = 12 + 4;
7487 if (disp < 0) {
7488 disp -= fudge;
7489 } else {
7490 disp += fudge;
7491 }
7492 return is_simm32(disp);
7493 }
7494
7495 // Check if the polling page is not reachable from the code cache using rip-relative
7496 // addressing.
7497 bool Assembler::is_polling_page_far() {
7498 intptr_t addr = (intptr_t)os::get_polling_page();
7499 return ForceUnreachable ||
7500 !is_simm32(addr - (intptr_t)CodeCache::low_bound()) ||
7501 !is_simm32(addr - (intptr_t)CodeCache::high_bound());
7502 }
7503
7504 void Assembler::emit_data64(jlong data,
7505 relocInfo::relocType rtype,
7506 int format) {
7507 if (rtype == relocInfo::none) {
7508 emit_int64(data);
7509 } else {
7510 emit_data64(data, Relocation::spec_simple(rtype), format);
7511 }
7512 }
7513
7514 void Assembler::emit_data64(jlong data,
7515 RelocationHolder const& rspec,
7516 int format) {
7517 assert(imm_operand == 0, "default format must be immediate in this file");
7518 assert(imm_operand == format, "must be immediate");
7519 assert(inst_mark() != NULL, "must be inside InstructionMark");
7520 // Do not use AbstractAssembler::relocate, which is not intended for
7521 // embedded words. Instead, relocate to the enclosing instruction.
7522 code_section()->relocate(inst_mark(), rspec, format);
7523 #ifdef ASSERT
7524 check_relocation(rspec, format);
7525 #endif
7526 emit_int64(data);
7527 }
7528
7529 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) {
7530 if (reg_enc >= 8) {
7531 prefix(REX_B);
7532 reg_enc -= 8;
7533 } else if (byteinst && reg_enc >= 4) {
7534 prefix(REX);
7535 }
7536 return reg_enc;
7537 }
7538
7539 int Assembler::prefixq_and_encode(int reg_enc) {
7540 if (reg_enc < 8) {
7541 prefix(REX_W);
7542 } else {
7543 prefix(REX_WB);
7544 reg_enc -= 8;
7545 }
7546 return reg_enc;
7547 }
7548
7549 int Assembler::prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte) {
7550 if (dst_enc < 8) {
7551 if (src_enc >= 8) {
7552 prefix(REX_B);
7553 src_enc -= 8;
7554 } else if ((src_is_byte && src_enc >= 4) || (dst_is_byte && dst_enc >= 4)) {
7555 prefix(REX);
7556 }
7557 } else {
7558 if (src_enc < 8) {
7559 prefix(REX_R);
7560 } else {
7561 prefix(REX_RB);
7562 src_enc -= 8;
7563 }
7564 dst_enc -= 8;
7565 }
7566 return dst_enc << 3 | src_enc;
7567 }
7568
7569 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) {
7570 if (dst_enc < 8) {
7571 if (src_enc < 8) {
7572 prefix(REX_W);
7573 } else {
7574 prefix(REX_WB);
7575 src_enc -= 8;
7576 }
7577 } else {
7578 if (src_enc < 8) {
7579 prefix(REX_WR);
7580 } else {
7581 prefix(REX_WRB);
7582 src_enc -= 8;
7583 }
7584 dst_enc -= 8;
7585 }
7586 return dst_enc << 3 | src_enc;
7587 }
7588
7589 void Assembler::prefix(Register reg) {
7590 if (reg->encoding() >= 8) {
7591 prefix(REX_B);
7592 }
7593 }
7594
7595 void Assembler::prefix(Register dst, Register src, Prefix p) {
7596 if (src->encoding() >= 8) {
7597 p = (Prefix)(p | REX_B);
7598 }
7599 if (dst->encoding() >= 8) {
7600 p = (Prefix)( p | REX_R);
7601 }
7602 if (p != Prefix_EMPTY) {
7603 // do not generate an empty prefix
7604 prefix(p);
7605 }
7606 }
7607
7608 void Assembler::prefix(Register dst, Address adr, Prefix p) {
7609 if (adr.base_needs_rex()) {
7610 if (adr.index_needs_rex()) {
7611 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X");
7612 } else {
7613 prefix(REX_B);
7614 }
7615 } else {
7616 if (adr.index_needs_rex()) {
7617 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X");
7618 }
7619 }
7620 if (dst->encoding() >= 8) {
7621 p = (Prefix)(p | REX_R);
7622 }
7623 if (p != Prefix_EMPTY) {
7624 // do not generate an empty prefix
7625 prefix(p);
7626 }
7627 }
7628
7629 void Assembler::prefix(Address adr) {
7630 if (adr.base_needs_rex()) {
7631 if (adr.index_needs_rex()) {
7632 prefix(REX_XB);
7633 } else {
7634 prefix(REX_B);
7635 }
7636 } else {
7637 if (adr.index_needs_rex()) {
7638 prefix(REX_X);
7639 }
7640 }
7641 }
7642
7643 void Assembler::prefixq(Address adr) {
7644 if (adr.base_needs_rex()) {
7645 if (adr.index_needs_rex()) {
7646 prefix(REX_WXB);
7647 } else {
7648 prefix(REX_WB);
7649 }
7650 } else {
7651 if (adr.index_needs_rex()) {
7652 prefix(REX_WX);
7653 } else {
7654 prefix(REX_W);
7655 }
7656 }
7657 }
7658
7659
7660 void Assembler::prefix(Address adr, Register reg, bool byteinst) {
7661 if (reg->encoding() < 8) {
7662 if (adr.base_needs_rex()) {
7663 if (adr.index_needs_rex()) {
7664 prefix(REX_XB);
7665 } else {
7666 prefix(REX_B);
7667 }
7668 } else {
7669 if (adr.index_needs_rex()) {
7670 prefix(REX_X);
7671 } else if (byteinst && reg->encoding() >= 4 ) {
7672 prefix(REX);
7673 }
7674 }
7675 } else {
7676 if (adr.base_needs_rex()) {
7677 if (adr.index_needs_rex()) {
7678 prefix(REX_RXB);
7679 } else {
7680 prefix(REX_RB);
7681 }
7682 } else {
7683 if (adr.index_needs_rex()) {
7684 prefix(REX_RX);
7685 } else {
7686 prefix(REX_R);
7687 }
7688 }
7689 }
7690 }
7691
7692 void Assembler::prefixq(Address adr, Register src) {
7693 if (src->encoding() < 8) {
7694 if (adr.base_needs_rex()) {
7695 if (adr.index_needs_rex()) {
7696 prefix(REX_WXB);
7697 } else {
7698 prefix(REX_WB);
7699 }
7700 } else {
7701 if (adr.index_needs_rex()) {
7702 prefix(REX_WX);
7703 } else {
7704 prefix(REX_W);
7705 }
7706 }
7707 } else {
7708 if (adr.base_needs_rex()) {
7709 if (adr.index_needs_rex()) {
7710 prefix(REX_WRXB);
7711 } else {
7712 prefix(REX_WRB);
7713 }
7714 } else {
7715 if (adr.index_needs_rex()) {
7716 prefix(REX_WRX);
7717 } else {
7718 prefix(REX_WR);
7719 }
7720 }
7721 }
7722 }
7723
7724 void Assembler::prefix(Address adr, XMMRegister reg) {
7725 if (reg->encoding() < 8) {
7726 if (adr.base_needs_rex()) {
7727 if (adr.index_needs_rex()) {
7728 prefix(REX_XB);
7729 } else {
7730 prefix(REX_B);
7731 }
7732 } else {
7733 if (adr.index_needs_rex()) {
7734 prefix(REX_X);
7735 }
7736 }
7737 } else {
7738 if (adr.base_needs_rex()) {
7739 if (adr.index_needs_rex()) {
7740 prefix(REX_RXB);
7741 } else {
7742 prefix(REX_RB);
7743 }
7744 } else {
7745 if (adr.index_needs_rex()) {
7746 prefix(REX_RX);
7747 } else {
7748 prefix(REX_R);
7749 }
7750 }
7751 }
7752 }
7753
7754 void Assembler::prefixq(Address adr, XMMRegister src) {
7755 if (src->encoding() < 8) {
7756 if (adr.base_needs_rex()) {
7757 if (adr.index_needs_rex()) {
7758 prefix(REX_WXB);
7759 } else {
7760 prefix(REX_WB);
7761 }
7762 } else {
7763 if (adr.index_needs_rex()) {
7764 prefix(REX_WX);
7765 } else {
7766 prefix(REX_W);
7767 }
7768 }
7769 } else {
7770 if (adr.base_needs_rex()) {
7771 if (adr.index_needs_rex()) {
7772 prefix(REX_WRXB);
7773 } else {
7774 prefix(REX_WRB);
7775 }
7776 } else {
7777 if (adr.index_needs_rex()) {
7778 prefix(REX_WRX);
7779 } else {
7780 prefix(REX_WR);
7781 }
7782 }
7783 }
7784 }
7785
7786 void Assembler::adcq(Register dst, int32_t imm32) {
7787 (void) prefixq_and_encode(dst->encoding());
7788 emit_arith(0x81, 0xD0, dst, imm32);
7789 }
7790
7791 void Assembler::adcq(Register dst, Address src) {
7792 InstructionMark im(this);
7793 prefixq(src, dst);
7794 emit_int8(0x13);
7795 emit_operand(dst, src);
7796 }
7797
7798 void Assembler::adcq(Register dst, Register src) {
7799 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7800 emit_arith(0x13, 0xC0, dst, src);
7801 }
7802
7803 void Assembler::addq(Address dst, int32_t imm32) {
7804 InstructionMark im(this);
7805 prefixq(dst);
7806 emit_arith_operand(0x81, rax, dst,imm32);
7807 }
7808
7809 void Assembler::addq(Address dst, Register src) {
7810 InstructionMark im(this);
7811 prefixq(dst, src);
7812 emit_int8(0x01);
7813 emit_operand(src, dst);
7814 }
7815
7816 void Assembler::addq(Register dst, int32_t imm32) {
7817 (void) prefixq_and_encode(dst->encoding());
7818 emit_arith(0x81, 0xC0, dst, imm32);
7819 }
7820
7821 void Assembler::addq(Register dst, Address src) {
7822 InstructionMark im(this);
7823 prefixq(src, dst);
7824 emit_int8(0x03);
7825 emit_operand(dst, src);
7826 }
7827
7828 void Assembler::addq(Register dst, Register src) {
7829 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7830 emit_arith(0x03, 0xC0, dst, src);
7831 }
7832
7833 void Assembler::adcxq(Register dst, Register src) {
7834 //assert(VM_Version::supports_adx(), "adx instructions not supported");
7835 emit_int8((unsigned char)0x66);
7836 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7837 emit_int8(0x0F);
7838 emit_int8(0x38);
7839 emit_int8((unsigned char)0xF6);
7840 emit_int8((unsigned char)(0xC0 | encode));
7841 }
7842
7843 void Assembler::adoxq(Register dst, Register src) {
7844 //assert(VM_Version::supports_adx(), "adx instructions not supported");
7845 emit_int8((unsigned char)0xF3);
7846 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7847 emit_int8(0x0F);
7848 emit_int8(0x38);
7849 emit_int8((unsigned char)0xF6);
7850 emit_int8((unsigned char)(0xC0 | encode));
7851 }
7852
7853 void Assembler::andq(Address dst, int32_t imm32) {
7854 InstructionMark im(this);
7855 prefixq(dst);
7856 emit_int8((unsigned char)0x81);
7857 emit_operand(rsp, dst, 4);
7858 emit_int32(imm32);
7859 }
7860
7861 void Assembler::andq(Register dst, int32_t imm32) {
7862 (void) prefixq_and_encode(dst->encoding());
7863 emit_arith(0x81, 0xE0, dst, imm32);
7864 }
7865
7866 void Assembler::andq(Register dst, Address src) {
7867 InstructionMark im(this);
7868 prefixq(src, dst);
7869 emit_int8(0x23);
7870 emit_operand(dst, src);
7871 }
7872
7873 void Assembler::andq(Register dst, Register src) {
7874 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7875 emit_arith(0x23, 0xC0, dst, src);
7876 }
7877
7878 void Assembler::andnq(Register dst, Register src1, Register src2) {
7879 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7880 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7881 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7882 emit_int8((unsigned char)0xF2);
7883 emit_int8((unsigned char)(0xC0 | encode));
7884 }
7885
7886 void Assembler::andnq(Register dst, Register src1, Address src2) {
7887 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7888 InstructionMark im(this);
7889 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7890 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7891 emit_int8((unsigned char)0xF2);
7892 emit_operand(dst, src2);
7893 }
7894
7895 void Assembler::bsfq(Register dst, Register src) {
7896 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7897 emit_int8(0x0F);
7898 emit_int8((unsigned char)0xBC);
7899 emit_int8((unsigned char)(0xC0 | encode));
7900 }
7901
7902 void Assembler::bsrq(Register dst, Register src) {
7903 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7904 emit_int8(0x0F);
7905 emit_int8((unsigned char)0xBD);
7906 emit_int8((unsigned char)(0xC0 | encode));
7907 }
7908
7909 void Assembler::bswapq(Register reg) {
7910 int encode = prefixq_and_encode(reg->encoding());
7911 emit_int8(0x0F);
7912 emit_int8((unsigned char)(0xC8 | encode));
7913 }
7914
7915 void Assembler::blsiq(Register dst, Register src) {
7916 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7917 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7918 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7919 emit_int8((unsigned char)0xF3);
7920 emit_int8((unsigned char)(0xC0 | encode));
7921 }
7922
7923 void Assembler::blsiq(Register dst, Address src) {
7924 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7925 InstructionMark im(this);
7926 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7927 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7928 emit_int8((unsigned char)0xF3);
7929 emit_operand(rbx, src);
7930 }
7931
7932 void Assembler::blsmskq(Register dst, Register src) {
7933 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7934 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7935 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7936 emit_int8((unsigned char)0xF3);
7937 emit_int8((unsigned char)(0xC0 | encode));
7938 }
7939
7940 void Assembler::blsmskq(Register dst, Address src) {
7941 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7942 InstructionMark im(this);
7943 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7944 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7945 emit_int8((unsigned char)0xF3);
7946 emit_operand(rdx, src);
7947 }
7948
7949 void Assembler::blsrq(Register dst, Register src) {
7950 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7951 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7952 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7953 emit_int8((unsigned char)0xF3);
7954 emit_int8((unsigned char)(0xC0 | encode));
7955 }
7956
7957 void Assembler::blsrq(Register dst, Address src) {
7958 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7959 InstructionMark im(this);
7960 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7961 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7962 emit_int8((unsigned char)0xF3);
7963 emit_operand(rcx, src);
7964 }
7965
7966 void Assembler::cdqq() {
7967 prefix(REX_W);
7968 emit_int8((unsigned char)0x99);
7969 }
7970
7971 void Assembler::clflush(Address adr) {
7972 prefix(adr);
7973 emit_int8(0x0F);
7974 emit_int8((unsigned char)0xAE);
7975 emit_operand(rdi, adr);
7976 }
7977
7978 void Assembler::cmovq(Condition cc, Register dst, Register src) {
7979 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7980 emit_int8(0x0F);
7981 emit_int8(0x40 | cc);
7982 emit_int8((unsigned char)(0xC0 | encode));
7983 }
7984
7985 void Assembler::cmovq(Condition cc, Register dst, Address src) {
7986 InstructionMark im(this);
7987 prefixq(src, dst);
7988 emit_int8(0x0F);
7989 emit_int8(0x40 | cc);
7990 emit_operand(dst, src);
7991 }
7992
7993 void Assembler::cmpq(Address dst, int32_t imm32) {
7994 InstructionMark im(this);
7995 prefixq(dst);
7996 emit_int8((unsigned char)0x81);
7997 emit_operand(rdi, dst, 4);
7998 emit_int32(imm32);
7999 }
8000
8001 void Assembler::cmpq(Register dst, int32_t imm32) {
8002 (void) prefixq_and_encode(dst->encoding());
8003 emit_arith(0x81, 0xF8, dst, imm32);
8004 }
8005
8006 void Assembler::cmpq(Address dst, Register src) {
8007 InstructionMark im(this);
8008 prefixq(dst, src);
8009 emit_int8(0x3B);
8010 emit_operand(src, dst);
8011 }
8012
8013 void Assembler::cmpq(Register dst, Register src) {
8014 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8015 emit_arith(0x3B, 0xC0, dst, src);
8016 }
8017
8018 void Assembler::cmpq(Register dst, Address src) {
8019 InstructionMark im(this);
8020 prefixq(src, dst);
8021 emit_int8(0x3B);
8022 emit_operand(dst, src);
8023 }
8024
8025 void Assembler::cmpxchgq(Register reg, Address adr) {
8026 InstructionMark im(this);
8027 prefixq(adr, reg);
8028 emit_int8(0x0F);
8029 emit_int8((unsigned char)0xB1);
8030 emit_operand(reg, adr);
8031 }
8032
8033 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
8034 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8035 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8036 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
8037 emit_int8(0x2A);
8038 emit_int8((unsigned char)(0xC0 | encode));
8039 }
8040
8041 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) {
8042 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8043 InstructionMark im(this);
8044 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8045 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
8046 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
8047 emit_int8(0x2A);
8048 emit_operand(dst, src);
8049 }
8050
8051 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) {
8052 NOT_LP64(assert(VM_Version::supports_sse(), ""));
8053 InstructionMark im(this);
8054 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8055 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
8056 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
8057 emit_int8(0x2A);
8058 emit_operand(dst, src);
8059 }
8060
8061 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
8062 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8063 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8064 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
8065 emit_int8(0x2C);
8066 emit_int8((unsigned char)(0xC0 | encode));
8067 }
8068
8069 void Assembler::cvttss2siq(Register dst, XMMRegister src) {
8070 NOT_LP64(assert(VM_Version::supports_sse(), ""));
8071 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8072 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
8073 emit_int8(0x2C);
8074 emit_int8((unsigned char)(0xC0 | encode));
8075 }
8076
8077 void Assembler::decl(Register dst) {
8078 // Don't use it directly. Use MacroAssembler::decrementl() instead.
8079 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
8080 int encode = prefix_and_encode(dst->encoding());
8081 emit_int8((unsigned char)0xFF);
8082 emit_int8((unsigned char)(0xC8 | encode));
8083 }
8084
8085 void Assembler::decq(Register dst) {
8086 // Don't use it directly. Use MacroAssembler::decrementq() instead.
8087 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
8088 int encode = prefixq_and_encode(dst->encoding());
8089 emit_int8((unsigned char)0xFF);
8090 emit_int8(0xC8 | encode);
8091 }
8092
8093 void Assembler::decq(Address dst) {
8094 // Don't use it directly. Use MacroAssembler::decrementq() instead.
8095 InstructionMark im(this);
8096 prefixq(dst);
8097 emit_int8((unsigned char)0xFF);
8098 emit_operand(rcx, dst);
8099 }
8100
8101 void Assembler::fxrstor(Address src) {
8102 prefixq(src);
8103 emit_int8(0x0F);
8104 emit_int8((unsigned char)0xAE);
8105 emit_operand(as_Register(1), src);
8106 }
8107
8108 void Assembler::xrstor(Address src) {
8109 prefixq(src);
8110 emit_int8(0x0F);
8111 emit_int8((unsigned char)0xAE);
8112 emit_operand(as_Register(5), src);
8113 }
8114
8115 void Assembler::fxsave(Address dst) {
8116 prefixq(dst);
8117 emit_int8(0x0F);
8118 emit_int8((unsigned char)0xAE);
8119 emit_operand(as_Register(0), dst);
8120 }
8121
8122 void Assembler::xsave(Address dst) {
8123 prefixq(dst);
8124 emit_int8(0x0F);
8125 emit_int8((unsigned char)0xAE);
8126 emit_operand(as_Register(4), dst);
8127 }
8128
8129 void Assembler::idivq(Register src) {
8130 int encode = prefixq_and_encode(src->encoding());
8131 emit_int8((unsigned char)0xF7);
8132 emit_int8((unsigned char)(0xF8 | encode));
8133 }
8134
8135 void Assembler::imulq(Register dst, Register src) {
8136 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8137 emit_int8(0x0F);
8138 emit_int8((unsigned char)0xAF);
8139 emit_int8((unsigned char)(0xC0 | encode));
8140 }
8141
8142 void Assembler::imulq(Register dst, Register src, int value) {
8143 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8144 if (is8bit(value)) {
8145 emit_int8(0x6B);
8146 emit_int8((unsigned char)(0xC0 | encode));
8147 emit_int8(value & 0xFF);
8148 } else {
8149 emit_int8(0x69);
8150 emit_int8((unsigned char)(0xC0 | encode));
8151 emit_int32(value);
8152 }
8153 }
8154
8155 void Assembler::imulq(Register dst, Address src) {
8156 InstructionMark im(this);
8157 prefixq(src, dst);
8158 emit_int8(0x0F);
8159 emit_int8((unsigned char) 0xAF);
8160 emit_operand(dst, src);
8161 }
8162
8163 void Assembler::incl(Register dst) {
8164 // Don't use it directly. Use MacroAssembler::incrementl() instead.
8165 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
8166 int encode = prefix_and_encode(dst->encoding());
8167 emit_int8((unsigned char)0xFF);
8168 emit_int8((unsigned char)(0xC0 | encode));
8169 }
8170
8171 void Assembler::incq(Register dst) {
8172 // Don't use it directly. Use MacroAssembler::incrementq() instead.
8173 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
8174 int encode = prefixq_and_encode(dst->encoding());
8175 emit_int8((unsigned char)0xFF);
8176 emit_int8((unsigned char)(0xC0 | encode));
8177 }
8178
8179 void Assembler::incq(Address dst) {
8180 // Don't use it directly. Use MacroAssembler::incrementq() instead.
8181 InstructionMark im(this);
8182 prefixq(dst);
8183 emit_int8((unsigned char)0xFF);
8184 emit_operand(rax, dst);
8185 }
8186
8187 void Assembler::lea(Register dst, Address src) {
8188 leaq(dst, src);
8189 }
8190
8191 void Assembler::leaq(Register dst, Address src) {
8192 InstructionMark im(this);
8193 prefixq(src, dst);
8194 emit_int8((unsigned char)0x8D);
8195 emit_operand(dst, src);
8196 }
8197
8198 void Assembler::mov64(Register dst, int64_t imm64) {
8199 InstructionMark im(this);
8200 int encode = prefixq_and_encode(dst->encoding());
8201 emit_int8((unsigned char)(0xB8 | encode));
8202 emit_int64(imm64);
8203 }
8204
8205 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) {
8206 InstructionMark im(this);
8207 int encode = prefixq_and_encode(dst->encoding());
8208 emit_int8(0xB8 | encode);
8209 emit_data64(imm64, rspec);
8210 }
8211
8212 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) {
8213 InstructionMark im(this);
8214 int encode = prefix_and_encode(dst->encoding());
8215 emit_int8((unsigned char)(0xB8 | encode));
8216 emit_data((int)imm32, rspec, narrow_oop_operand);
8217 }
8218
8219 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) {
8220 InstructionMark im(this);
8221 prefix(dst);
8222 emit_int8((unsigned char)0xC7);
8223 emit_operand(rax, dst, 4);
8224 emit_data((int)imm32, rspec, narrow_oop_operand);
8225 }
8226
8227 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) {
8228 InstructionMark im(this);
8229 int encode = prefix_and_encode(src1->encoding());
8230 emit_int8((unsigned char)0x81);
8231 emit_int8((unsigned char)(0xF8 | encode));
8232 emit_data((int)imm32, rspec, narrow_oop_operand);
8233 }
8234
8235 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) {
8236 InstructionMark im(this);
8237 prefix(src1);
8238 emit_int8((unsigned char)0x81);
8239 emit_operand(rax, src1, 4);
8240 emit_data((int)imm32, rspec, narrow_oop_operand);
8241 }
8242
8243 void Assembler::lzcntq(Register dst, Register src) {
8244 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
8245 emit_int8((unsigned char)0xF3);
8246 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8247 emit_int8(0x0F);
8248 emit_int8((unsigned char)0xBD);
8249 emit_int8((unsigned char)(0xC0 | encode));
8250 }
8251
8252 void Assembler::movdq(XMMRegister dst, Register src) {
8253 // table D-1 says MMX/SSE2
8254 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8255 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8256 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8257 emit_int8(0x6E);
8258 emit_int8((unsigned char)(0xC0 | encode));
8259 }
8260
8261 void Assembler::movdq(Register dst, XMMRegister src) {
8262 // table D-1 says MMX/SSE2
8263 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8264 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8265 // swap src/dst to get correct prefix
8266 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8267 emit_int8(0x7E);
8268 emit_int8((unsigned char)(0xC0 | encode));
8269 }
8270
8271 void Assembler::movq(Register dst, Register src) {
8272 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8273 emit_int8((unsigned char)0x8B);
8274 emit_int8((unsigned char)(0xC0 | encode));
8275 }
8276
8277 void Assembler::movq(Register dst, Address src) {
8278 InstructionMark im(this);
8279 prefixq(src, dst);
8280 emit_int8((unsigned char)0x8B);
8281 emit_operand(dst, src);
8282 }
8283
8284 void Assembler::movq(Address dst, Register src) {
8285 InstructionMark im(this);
8286 prefixq(dst, src);
8287 emit_int8((unsigned char)0x89);
8288 emit_operand(src, dst);
8289 }
8290
8291 void Assembler::movsbq(Register dst, Address src) {
8292 InstructionMark im(this);
8293 prefixq(src, dst);
8294 emit_int8(0x0F);
8295 emit_int8((unsigned char)0xBE);
8296 emit_operand(dst, src);
8297 }
8298
8299 void Assembler::movsbq(Register dst, Register src) {
8300 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8301 emit_int8(0x0F);
8302 emit_int8((unsigned char)0xBE);
8303 emit_int8((unsigned char)(0xC0 | encode));
8304 }
8305
8306 void Assembler::movslq(Register dst, int32_t imm32) {
8307 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx)
8308 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx)
8309 // as a result we shouldn't use until tested at runtime...
8310 ShouldNotReachHere();
8311 InstructionMark im(this);
8312 int encode = prefixq_and_encode(dst->encoding());
8313 emit_int8((unsigned char)(0xC7 | encode));
8314 emit_int32(imm32);
8315 }
8316
8317 void Assembler::movslq(Address dst, int32_t imm32) {
8318 assert(is_simm32(imm32), "lost bits");
8319 InstructionMark im(this);
8320 prefixq(dst);
8321 emit_int8((unsigned char)0xC7);
8322 emit_operand(rax, dst, 4);
8323 emit_int32(imm32);
8324 }
8325
8326 void Assembler::movslq(Register dst, Address src) {
8327 InstructionMark im(this);
8328 prefixq(src, dst);
8329 emit_int8(0x63);
8330 emit_operand(dst, src);
8331 }
8332
8333 void Assembler::movslq(Register dst, Register src) {
8334 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8335 emit_int8(0x63);
8336 emit_int8((unsigned char)(0xC0 | encode));
8337 }
8338
8339 void Assembler::movswq(Register dst, Address src) {
8340 InstructionMark im(this);
8341 prefixq(src, dst);
8342 emit_int8(0x0F);
8343 emit_int8((unsigned char)0xBF);
8344 emit_operand(dst, src);
8345 }
8346
8347 void Assembler::movswq(Register dst, Register src) {
8348 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8349 emit_int8((unsigned char)0x0F);
8350 emit_int8((unsigned char)0xBF);
8351 emit_int8((unsigned char)(0xC0 | encode));
8352 }
8353
8354 void Assembler::movzbq(Register dst, Address src) {
8355 InstructionMark im(this);
8356 prefixq(src, dst);
8357 emit_int8((unsigned char)0x0F);
8358 emit_int8((unsigned char)0xB6);
8359 emit_operand(dst, src);
8360 }
8361
8362 void Assembler::movzbq(Register dst, Register src) {
8363 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8364 emit_int8(0x0F);
8365 emit_int8((unsigned char)0xB6);
8366 emit_int8(0xC0 | encode);
8367 }
8368
8369 void Assembler::movzwq(Register dst, Address src) {
8370 InstructionMark im(this);
8371 prefixq(src, dst);
8372 emit_int8((unsigned char)0x0F);
8373 emit_int8((unsigned char)0xB7);
8374 emit_operand(dst, src);
8375 }
8376
8377 void Assembler::movzwq(Register dst, Register src) {
8378 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8379 emit_int8((unsigned char)0x0F);
8380 emit_int8((unsigned char)0xB7);
8381 emit_int8((unsigned char)(0xC0 | encode));
8382 }
8383
8384 void Assembler::mulq(Address src) {
8385 InstructionMark im(this);
8386 prefixq(src);
8387 emit_int8((unsigned char)0xF7);
8388 emit_operand(rsp, src);
8389 }
8390
8391 void Assembler::mulq(Register src) {
8392 int encode = prefixq_and_encode(src->encoding());
8393 emit_int8((unsigned char)0xF7);
8394 emit_int8((unsigned char)(0xE0 | encode));
8395 }
8396
8397 void Assembler::mulxq(Register dst1, Register dst2, Register src) {
8398 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
8399 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
8400 int encode = vex_prefix_and_encode(dst1->encoding(), dst2->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
8401 emit_int8((unsigned char)0xF6);
8402 emit_int8((unsigned char)(0xC0 | encode));
8403 }
8404
8405 void Assembler::negq(Register dst) {
8406 int encode = prefixq_and_encode(dst->encoding());
8407 emit_int8((unsigned char)0xF7);
8408 emit_int8((unsigned char)(0xD8 | encode));
8409 }
8410
8411 void Assembler::notq(Register dst) {
8412 int encode = prefixq_and_encode(dst->encoding());
8413 emit_int8((unsigned char)0xF7);
8414 emit_int8((unsigned char)(0xD0 | encode));
8415 }
8416
8417 void Assembler::orq(Address dst, int32_t imm32) {
8418 InstructionMark im(this);
8419 prefixq(dst);
8420 emit_int8((unsigned char)0x81);
8421 emit_operand(rcx, dst, 4);
8422 emit_int32(imm32);
8423 }
8424
8425 void Assembler::orq(Register dst, int32_t imm32) {
8426 (void) prefixq_and_encode(dst->encoding());
8427 emit_arith(0x81, 0xC8, dst, imm32);
8428 }
8429
8430 void Assembler::orq(Register dst, Address src) {
8431 InstructionMark im(this);
8432 prefixq(src, dst);
8433 emit_int8(0x0B);
8434 emit_operand(dst, src);
8435 }
8436
8437 void Assembler::orq(Register dst, Register src) {
8438 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8439 emit_arith(0x0B, 0xC0, dst, src);
8440 }
8441
8442 void Assembler::popa() { // 64bit
8443 movq(r15, Address(rsp, 0));
8444 movq(r14, Address(rsp, wordSize));
8445 movq(r13, Address(rsp, 2 * wordSize));
8446 movq(r12, Address(rsp, 3 * wordSize));
8447 movq(r11, Address(rsp, 4 * wordSize));
8448 movq(r10, Address(rsp, 5 * wordSize));
8449 movq(r9, Address(rsp, 6 * wordSize));
8450 movq(r8, Address(rsp, 7 * wordSize));
8451 movq(rdi, Address(rsp, 8 * wordSize));
8452 movq(rsi, Address(rsp, 9 * wordSize));
8453 movq(rbp, Address(rsp, 10 * wordSize));
8454 // skip rsp
8455 movq(rbx, Address(rsp, 12 * wordSize));
8456 movq(rdx, Address(rsp, 13 * wordSize));
8457 movq(rcx, Address(rsp, 14 * wordSize));
8458 movq(rax, Address(rsp, 15 * wordSize));
8459
8460 addq(rsp, 16 * wordSize);
8461 }
8462
8463 void Assembler::popcntq(Register dst, Address src) {
8464 assert(VM_Version::supports_popcnt(), "must support");
8465 InstructionMark im(this);
8466 emit_int8((unsigned char)0xF3);
8467 prefixq(src, dst);
8468 emit_int8((unsigned char)0x0F);
8469 emit_int8((unsigned char)0xB8);
8470 emit_operand(dst, src);
8471 }
8472
8473 void Assembler::popcntq(Register dst, Register src) {
8474 assert(VM_Version::supports_popcnt(), "must support");
8475 emit_int8((unsigned char)0xF3);
8476 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8477 emit_int8((unsigned char)0x0F);
8478 emit_int8((unsigned char)0xB8);
8479 emit_int8((unsigned char)(0xC0 | encode));
8480 }
8481
8482 void Assembler::popq(Address dst) {
8483 InstructionMark im(this);
8484 prefixq(dst);
8485 emit_int8((unsigned char)0x8F);
8486 emit_operand(rax, dst);
8487 }
8488
8489 void Assembler::pusha() { // 64bit
8490 // we have to store original rsp. ABI says that 128 bytes
8491 // below rsp are local scratch.
8492 movq(Address(rsp, -5 * wordSize), rsp);
8493
8494 subq(rsp, 16 * wordSize);
8495
8496 movq(Address(rsp, 15 * wordSize), rax);
8497 movq(Address(rsp, 14 * wordSize), rcx);
8498 movq(Address(rsp, 13 * wordSize), rdx);
8499 movq(Address(rsp, 12 * wordSize), rbx);
8500 // skip rsp
8501 movq(Address(rsp, 10 * wordSize), rbp);
8502 movq(Address(rsp, 9 * wordSize), rsi);
8503 movq(Address(rsp, 8 * wordSize), rdi);
8504 movq(Address(rsp, 7 * wordSize), r8);
8505 movq(Address(rsp, 6 * wordSize), r9);
8506 movq(Address(rsp, 5 * wordSize), r10);
8507 movq(Address(rsp, 4 * wordSize), r11);
8508 movq(Address(rsp, 3 * wordSize), r12);
8509 movq(Address(rsp, 2 * wordSize), r13);
8510 movq(Address(rsp, wordSize), r14);
8511 movq(Address(rsp, 0), r15);
8512 }
8513
8514 void Assembler::pushq(Address src) {
8515 InstructionMark im(this);
8516 prefixq(src);
8517 emit_int8((unsigned char)0xFF);
8518 emit_operand(rsi, src);
8519 }
8520
8521 void Assembler::rclq(Register dst, int imm8) {
8522 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8523 int encode = prefixq_and_encode(dst->encoding());
8524 if (imm8 == 1) {
8525 emit_int8((unsigned char)0xD1);
8526 emit_int8((unsigned char)(0xD0 | encode));
8527 } else {
8528 emit_int8((unsigned char)0xC1);
8529 emit_int8((unsigned char)(0xD0 | encode));
8530 emit_int8(imm8);
8531 }
8532 }
8533
8534 void Assembler::rcrq(Register dst, int imm8) {
8535 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8536 int encode = prefixq_and_encode(dst->encoding());
8537 if (imm8 == 1) {
8538 emit_int8((unsigned char)0xD1);
8539 emit_int8((unsigned char)(0xD8 | encode));
8540 } else {
8541 emit_int8((unsigned char)0xC1);
8542 emit_int8((unsigned char)(0xD8 | encode));
8543 emit_int8(imm8);
8544 }
8545 }
8546
8547 void Assembler::rorq(Register dst, int imm8) {
8548 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8549 int encode = prefixq_and_encode(dst->encoding());
8550 if (imm8 == 1) {
8551 emit_int8((unsigned char)0xD1);
8552 emit_int8((unsigned char)(0xC8 | encode));
8553 } else {
8554 emit_int8((unsigned char)0xC1);
8555 emit_int8((unsigned char)(0xc8 | encode));
8556 emit_int8(imm8);
8557 }
8558 }
8559
8560 void Assembler::rorxq(Register dst, Register src, int imm8) {
8561 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
8562 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
8563 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes);
8564 emit_int8((unsigned char)0xF0);
8565 emit_int8((unsigned char)(0xC0 | encode));
8566 emit_int8(imm8);
8567 }
8568
8569 void Assembler::rorxd(Register dst, Register src, int imm8) {
8570 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
8571 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
8572 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes);
8573 emit_int8((unsigned char)0xF0);
8574 emit_int8((unsigned char)(0xC0 | encode));
8575 emit_int8(imm8);
8576 }
8577
8578 void Assembler::sarq(Register dst, int imm8) {
8579 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8580 int encode = prefixq_and_encode(dst->encoding());
8581 if (imm8 == 1) {
8582 emit_int8((unsigned char)0xD1);
8583 emit_int8((unsigned char)(0xF8 | encode));
8584 } else {
8585 emit_int8((unsigned char)0xC1);
8586 emit_int8((unsigned char)(0xF8 | encode));
8587 emit_int8(imm8);
8588 }
8589 }
8590
8591 void Assembler::sarq(Register dst) {
8592 int encode = prefixq_and_encode(dst->encoding());
8593 emit_int8((unsigned char)0xD3);
8594 emit_int8((unsigned char)(0xF8 | encode));
8595 }
8596
8597 void Assembler::sbbq(Address dst, int32_t imm32) {
8598 InstructionMark im(this);
8599 prefixq(dst);
8600 emit_arith_operand(0x81, rbx, dst, imm32);
8601 }
8602
8603 void Assembler::sbbq(Register dst, int32_t imm32) {
8604 (void) prefixq_and_encode(dst->encoding());
8605 emit_arith(0x81, 0xD8, dst, imm32);
8606 }
8607
8608 void Assembler::sbbq(Register dst, Address src) {
8609 InstructionMark im(this);
8610 prefixq(src, dst);
8611 emit_int8(0x1B);
8612 emit_operand(dst, src);
8613 }
8614
8615 void Assembler::sbbq(Register dst, Register src) {
8616 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8617 emit_arith(0x1B, 0xC0, dst, src);
8618 }
8619
8620 void Assembler::shlq(Register dst, int imm8) {
8621 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8622 int encode = prefixq_and_encode(dst->encoding());
8623 if (imm8 == 1) {
8624 emit_int8((unsigned char)0xD1);
8625 emit_int8((unsigned char)(0xE0 | encode));
8626 } else {
8627 emit_int8((unsigned char)0xC1);
8628 emit_int8((unsigned char)(0xE0 | encode));
8629 emit_int8(imm8);
8630 }
8631 }
8632
8633 void Assembler::shlq(Register dst) {
8634 int encode = prefixq_and_encode(dst->encoding());
8635 emit_int8((unsigned char)0xD3);
8636 emit_int8((unsigned char)(0xE0 | encode));
8637 }
8638
8639 void Assembler::shrq(Register dst, int imm8) {
8640 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8641 int encode = prefixq_and_encode(dst->encoding());
8642 emit_int8((unsigned char)0xC1);
8643 emit_int8((unsigned char)(0xE8 | encode));
8644 emit_int8(imm8);
8645 }
8646
8647 void Assembler::shrq(Register dst) {
8648 int encode = prefixq_and_encode(dst->encoding());
8649 emit_int8((unsigned char)0xD3);
8650 emit_int8(0xE8 | encode);
8651 }
8652
8653 void Assembler::subq(Address dst, int32_t imm32) {
8654 InstructionMark im(this);
8655 prefixq(dst);
8656 emit_arith_operand(0x81, rbp, dst, imm32);
8657 }
8658
8659 void Assembler::subq(Address dst, Register src) {
8660 InstructionMark im(this);
8661 prefixq(dst, src);
8662 emit_int8(0x29);
8663 emit_operand(src, dst);
8664 }
8665
8666 void Assembler::subq(Register dst, int32_t imm32) {
8667 (void) prefixq_and_encode(dst->encoding());
8668 emit_arith(0x81, 0xE8, dst, imm32);
8669 }
8670
8671 // Force generation of a 4 byte immediate value even if it fits into 8bit
8672 void Assembler::subq_imm32(Register dst, int32_t imm32) {
8673 (void) prefixq_and_encode(dst->encoding());
8674 emit_arith_imm32(0x81, 0xE8, dst, imm32);
8675 }
8676
8677 void Assembler::subq(Register dst, Address src) {
8678 InstructionMark im(this);
8679 prefixq(src, dst);
8680 emit_int8(0x2B);
8681 emit_operand(dst, src);
8682 }
8683
8684 void Assembler::subq(Register dst, Register src) {
8685 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8686 emit_arith(0x2B, 0xC0, dst, src);
8687 }
8688
8689 void Assembler::testq(Register dst, int32_t imm32) {
8690 // not using emit_arith because test
8691 // doesn't support sign-extension of
8692 // 8bit operands
8693 int encode = dst->encoding();
8694 if (encode == 0) {
8695 prefix(REX_W);
8696 emit_int8((unsigned char)0xA9);
8697 } else {
8698 encode = prefixq_and_encode(encode);
8699 emit_int8((unsigned char)0xF7);
8700 emit_int8((unsigned char)(0xC0 | encode));
8701 }
8702 emit_int32(imm32);
8703 }
8704
8705 void Assembler::testq(Register dst, Register src) {
8706 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8707 emit_arith(0x85, 0xC0, dst, src);
8708 }
8709
8710 void Assembler::xaddq(Address dst, Register src) {
8711 InstructionMark im(this);
8712 prefixq(dst, src);
8713 emit_int8(0x0F);
8714 emit_int8((unsigned char)0xC1);
8715 emit_operand(src, dst);
8716 }
8717
8718 void Assembler::xchgq(Register dst, Address src) {
8719 InstructionMark im(this);
8720 prefixq(src, dst);
8721 emit_int8((unsigned char)0x87);
8722 emit_operand(dst, src);
8723 }
8724
8725 void Assembler::xchgq(Register dst, Register src) {
8726 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8727 emit_int8((unsigned char)0x87);
8728 emit_int8((unsigned char)(0xc0 | encode));
8729 }
8730
8731 void Assembler::xorq(Register dst, Register src) {
8732 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8733 emit_arith(0x33, 0xC0, dst, src);
8734 }
8735
8736 void Assembler::xorq(Register dst, Address src) {
8737 InstructionMark im(this);
8738 prefixq(src, dst);
8739 emit_int8(0x33);
8740 emit_operand(dst, src);
8741 }
8742
8743 #endif // !LP64