src/cpu/x86/vm/assembler_x86.cpp

*** 4767,4776 ****
--- 4767,4792 ----
    int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
    emit_int8(0x5E);
    emit_int8((unsigned char)(0xC0 | encode));
  }
  
+ void Assembler::vfmadd231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
+   assert(VM_Version::supports_fma(), "");
+   InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
+   int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
+   emit_int8((unsigned char)0xB9);
+   emit_int8((unsigned char)(0xC0 | encode));
+ }
+ 
+ void Assembler::vfmadd231ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
+   assert(VM_Version::supports_fma(), "");
+   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
+   int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
+   emit_int8((unsigned char)0xB9);
+   emit_int8((unsigned char)(0xC0 | encode));
+ }
+ 
  void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) {
    assert(VM_Version::supports_avx(), "");
    InstructionMark im(this);
    InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
    attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);