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src/cpu/x86/vm/assembler_x86.cpp

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4752 }
4753 
4754 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) {
4755   assert(VM_Version::supports_avx(), "");
4756   InstructionMark im(this);
4757   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4758   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4759   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4760   emit_int8(0x5E);
4761   emit_operand(dst, src);
4762 }
4763 
4764 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4765   assert(VM_Version::supports_avx(), "");
4766   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4767   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4768   emit_int8(0x5E);
4769   emit_int8((unsigned char)(0xC0 | encode));
4770 }
4771 
















4772 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) {
4773   assert(VM_Version::supports_avx(), "");
4774   InstructionMark im(this);
4775   InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4776   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4777   attributes.set_rex_vex_w_reverted();
4778   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4779   emit_int8(0x59);
4780   emit_operand(dst, src);
4781 }
4782 
4783 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4784   assert(VM_Version::supports_avx(), "");
4785   InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4786   attributes.set_rex_vex_w_reverted();
4787   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4788   emit_int8(0x59);
4789   emit_int8((unsigned char)(0xC0 | encode));
4790 }
4791 




4752 }
4753 
4754 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) {
4755   assert(VM_Version::supports_avx(), "");
4756   InstructionMark im(this);
4757   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4758   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4759   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4760   emit_int8(0x5E);
4761   emit_operand(dst, src);
4762 }
4763 
4764 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4765   assert(VM_Version::supports_avx(), "");
4766   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4767   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4768   emit_int8(0x5E);
4769   emit_int8((unsigned char)(0xC0 | encode));
4770 }
4771 
4772 void Assembler::vfmadd231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
4773   assert(VM_Version::supports_fma(), "");
4774   InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4775   int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4776   emit_int8((unsigned char)0xB9);
4777   emit_int8((unsigned char)(0xC0 | encode));
4778 }
4779 
4780 void Assembler::vfmadd231ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
4781   assert(VM_Version::supports_fma(), "");
4782   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4783   int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4784   emit_int8((unsigned char)0xB9);
4785   emit_int8((unsigned char)(0xC0 | encode));
4786 }
4787 
4788 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) {
4789   assert(VM_Version::supports_avx(), "");
4790   InstructionMark im(this);
4791   InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4792   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4793   attributes.set_rex_vex_w_reverted();
4794   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4795   emit_int8(0x59);
4796   emit_operand(dst, src);
4797 }
4798 
4799 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4800   assert(VM_Version::supports_avx(), "");
4801   InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4802   attributes.set_rex_vex_w_reverted();
4803   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4804   emit_int8(0x59);
4805   emit_int8((unsigned char)(0xC0 | encode));
4806 }
4807 


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