1328 case 2: return Address::times_2;
1329 case 4: return Address::times_4;
1330 case 8: return Address::times_8;
1331 }
1332 ShouldNotReachHere();
1333 return Address::no_scale;
1334 }
1335
1336
1337 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1338 switch (op->code()) {
1339 case lir_idiv:
1340 case lir_irem:
1341 arithmetic_idiv(op->code(),
1342 op->in_opr1(),
1343 op->in_opr2(),
1344 op->in_opr3(),
1345 op->result_opr(),
1346 op->info());
1347 break;
1348 default: ShouldNotReachHere(); break;
1349 }
1350 }
1351
1352 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1353 #ifdef ASSERT
1354 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
1355 if (op->block() != NULL) _branch_target_blocks.append(op->block());
1356 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
1357 #endif
1358
1359 if (op->cond() == lir_cond_always) {
1360 if (op->info() != NULL) add_debug_info_for_branch(op->info());
1361 __ jmp (*(op->label()));
1362 } else {
1363 Assembler::Condition acond = Assembler::zero;
1364 if (op->code() == lir_cond_float_branch) {
1365 assert(op->ublock() != NULL, "must have unordered successor");
1366 __ jcc(Assembler::parity, *(op->ublock()->label()));
1367 switch(op->cond()) {
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1328 case 2: return Address::times_2;
1329 case 4: return Address::times_4;
1330 case 8: return Address::times_8;
1331 }
1332 ShouldNotReachHere();
1333 return Address::no_scale;
1334 }
1335
1336
1337 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1338 switch (op->code()) {
1339 case lir_idiv:
1340 case lir_irem:
1341 arithmetic_idiv(op->code(),
1342 op->in_opr1(),
1343 op->in_opr2(),
1344 op->in_opr3(),
1345 op->result_opr(),
1346 op->info());
1347 break;
1348 case lir_fmad:
1349 __ vfmadd231sd(op->in_opr3()->as_xmm_double_reg(),
1350 op->in_opr1()->as_xmm_double_reg(),
1351 op->in_opr2()->as_xmm_double_reg());
1352 __ movdqu(op->result_opr()->as_xmm_double_reg(), op->in_opr3()->as_xmm_double_reg());
1353 break;
1354 case lir_fmaf:
1355 __ vfmadd231ss(op->in_opr3()->as_xmm_float_reg(),
1356 op->in_opr1()->as_xmm_float_reg(),
1357 op->in_opr2()->as_xmm_float_reg());
1358 __ movdqu(op->result_opr()->as_xmm_float_reg(), op->in_opr3()->as_xmm_float_reg());
1359 break;
1360 default: ShouldNotReachHere(); break;
1361 }
1362 }
1363
1364 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1365 #ifdef ASSERT
1366 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
1367 if (op->block() != NULL) _branch_target_blocks.append(op->block());
1368 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
1369 #endif
1370
1371 if (op->cond() == lir_cond_always) {
1372 if (op->info() != NULL) add_debug_info_for_branch(op->info());
1373 __ jmp (*(op->label()));
1374 } else {
1375 Assembler::Condition acond = Assembler::zero;
1376 if (op->code() == lir_cond_float_branch) {
1377 assert(op->ublock() != NULL, "must have unordered successor");
1378 __ jcc(Assembler::parity, *(op->ublock()->label()));
1379 switch(op->cond()) {
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