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src/cpu/x86/vm/vm_version_x86.hpp

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*** 72,82 **** : 1, est : 1, : 1, ssse3 : 1, cid : 1, ! : 2, cmpxchg16: 1, : 4, dca : 1, sse4_1 : 1, sse4_2 : 1, --- 72,83 ---- : 1, est : 1, : 1, ssse3 : 1, cid : 1, ! : 1, ! fma : 1, cmpxchg16: 1, : 4, dca : 1, sse4_1 : 1, sse4_2 : 1,
*** 287,296 **** --- 288,298 ---- }; #define CPU_AVX512BW ((uint64_t)UCONST64(0x100000000)) // enums are limited to 31 bit #define CPU_AVX512VL ((uint64_t)UCONST64(0x200000000)) // EVEX instructions with smaller vector length #define CPU_SHA ((uint64_t)UCONST64(0x400000000)) // SHA instructions + #define CPU_FMA ((uint64_t)UCONST64(0x800000000)) // FMA instructions enum Extended_Family { // AMD CPU_FAMILY_AMD_11H = 0x11, // Intel
*** 520,529 **** --- 522,533 ---- result |= CPU_BMI2; if (_cpuid_info.sef_cpuid7_ebx.bits.sha != 0) result |= CPU_SHA; if(_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0) result |= CPU_LZCNT; + if (_cpuid_info.std_cpuid1_ecx.bits.fma != 0) + result |= CPU_FMA; // for Intel, ecx.bits.misalignsse bit (bit 8) indicates support for prefetchw if (_cpuid_info.ext_cpuid1_ecx.bits.misalignsse != 0) { result |= CPU_3DNOW_PREFETCH; } }
*** 724,733 **** --- 728,738 ---- static bool supports_avx512novl() { return (supports_evex() && !supports_avx512vl()); } static bool supports_avx512nobw() { return (supports_evex() && !supports_avx512bw()); } static bool supports_avx256only() { return (supports_avx2() && !supports_evex()); } static bool supports_avxonly() { return ((supports_avx2() || supports_avx()) && !supports_evex()); } static bool supports_sha() { return (_features & CPU_SHA) != 0; } + static bool supports_fma() { return (_features & CPU_FMA) != 0; } // Intel features static bool is_intel_family_core() { return is_intel() && extended_cpu_family() == CPU_FAMILY_INTEL_CORE; } static bool is_intel_tsc_synched_at_init() {
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