1 /* 2 * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #ifndef CPU_X86_VM_VM_VERSION_X86_HPP 26 #define CPU_X86_VM_VM_VERSION_X86_HPP 27 28 #include "runtime/globals_extension.hpp" 29 #include "runtime/vm_version.hpp" 30 31 class VM_Version : public Abstract_VM_Version { 32 friend class VMStructs; 33 friend class JVMCIVMStructs; 34 35 public: 36 // cpuid result register layouts. These are all unions of a uint32_t 37 // (in case anyone wants access to the register as a whole) and a bitfield. 38 39 union StdCpuid1Eax { 40 uint32_t value; 41 struct { 42 uint32_t stepping : 4, 43 model : 4, 44 family : 4, 45 proc_type : 2, 46 : 2, 47 ext_model : 4, 48 ext_family : 8, 49 : 4; 50 } bits; 51 }; 52 53 union StdCpuid1Ebx { // example, unused 54 uint32_t value; 55 struct { 56 uint32_t brand_id : 8, 57 clflush_size : 8, 58 threads_per_cpu : 8, 59 apic_id : 8; 60 } bits; 61 }; 62 63 union StdCpuid1Ecx { 64 uint32_t value; 65 struct { 66 uint32_t sse3 : 1, 67 clmul : 1, 68 : 1, 69 monitor : 1, 70 : 1, 71 vmx : 1, 72 : 1, 73 est : 1, 74 : 1, 75 ssse3 : 1, 76 cid : 1, 77 : 1, 78 fma : 1, 79 cmpxchg16: 1, 80 : 4, 81 dca : 1, 82 sse4_1 : 1, 83 sse4_2 : 1, 84 : 2, 85 popcnt : 1, 86 : 1, 87 aes : 1, 88 : 1, 89 osxsave : 1, 90 avx : 1, 91 : 3; 92 } bits; 93 }; 94 95 union StdCpuid1Edx { 96 uint32_t value; 97 struct { 98 uint32_t : 4, 99 tsc : 1, 100 : 3, 101 cmpxchg8 : 1, 102 : 6, 103 cmov : 1, 104 : 3, 105 clflush : 1, 106 : 3, 107 mmx : 1, 108 fxsr : 1, 109 sse : 1, 110 sse2 : 1, 111 : 1, 112 ht : 1, 113 : 3; 114 } bits; 115 }; 116 117 union DcpCpuid4Eax { 118 uint32_t value; 119 struct { 120 uint32_t cache_type : 5, 121 : 21, 122 cores_per_cpu : 6; 123 } bits; 124 }; 125 126 union DcpCpuid4Ebx { 127 uint32_t value; 128 struct { 129 uint32_t L1_line_size : 12, 130 partitions : 10, 131 associativity : 10; 132 } bits; 133 }; 134 135 union TplCpuidBEbx { 136 uint32_t value; 137 struct { 138 uint32_t logical_cpus : 16, 139 : 16; 140 } bits; 141 }; 142 143 union ExtCpuid1Ecx { 144 uint32_t value; 145 struct { 146 uint32_t LahfSahf : 1, 147 CmpLegacy : 1, 148 : 3, 149 lzcnt_intel : 1, 150 lzcnt : 1, 151 sse4a : 1, 152 misalignsse : 1, 153 prefetchw : 1, 154 : 22; 155 } bits; 156 }; 157 158 union ExtCpuid1Edx { 159 uint32_t value; 160 struct { 161 uint32_t : 22, 162 mmx_amd : 1, 163 mmx : 1, 164 fxsr : 1, 165 : 4, 166 long_mode : 1, 167 tdnow2 : 1, 168 tdnow : 1; 169 } bits; 170 }; 171 172 union ExtCpuid5Ex { 173 uint32_t value; 174 struct { 175 uint32_t L1_line_size : 8, 176 L1_tag_lines : 8, 177 L1_assoc : 8, 178 L1_size : 8; 179 } bits; 180 }; 181 182 union ExtCpuid7Edx { 183 uint32_t value; 184 struct { 185 uint32_t : 8, 186 tsc_invariance : 1, 187 : 23; 188 } bits; 189 }; 190 191 union ExtCpuid8Ecx { 192 uint32_t value; 193 struct { 194 uint32_t cores_per_cpu : 8, 195 : 24; 196 } bits; 197 }; 198 199 union SefCpuid7Eax { 200 uint32_t value; 201 }; 202 203 union SefCpuid7Ebx { 204 uint32_t value; 205 struct { 206 uint32_t fsgsbase : 1, 207 : 2, 208 bmi1 : 1, 209 : 1, 210 avx2 : 1, 211 : 2, 212 bmi2 : 1, 213 erms : 1, 214 : 1, 215 rtm : 1, 216 : 4, 217 avx512f : 1, 218 avx512dq : 1, 219 : 1, 220 adx : 1, 221 : 6, 222 avx512pf : 1, 223 avx512er : 1, 224 avx512cd : 1, 225 sha : 1, 226 avx512bw : 1, 227 avx512vl : 1; 228 } bits; 229 }; 230 231 union XemXcr0Eax { 232 uint32_t value; 233 struct { 234 uint32_t x87 : 1, 235 sse : 1, 236 ymm : 1, 237 bndregs : 1, 238 bndcsr : 1, 239 opmask : 1, 240 zmm512 : 1, 241 zmm32 : 1, 242 : 24; 243 } bits; 244 }; 245 246 protected: 247 static int _cpu; 248 static int _model; 249 static int _stepping; 250 251 static address _cpuinfo_segv_addr; // address of instruction which causes SEGV 252 static address _cpuinfo_cont_addr; // address of instruction after the one which causes SEGV 253 254 enum Feature_Flag { 255 CPU_CX8 = (1 << 0), // next bits are from cpuid 1 (EDX) 256 CPU_CMOV = (1 << 1), 257 CPU_FXSR = (1 << 2), 258 CPU_HT = (1 << 3), 259 CPU_MMX = (1 << 4), 260 CPU_3DNOW_PREFETCH = (1 << 5), // Processor supports 3dnow prefetch and prefetchw instructions 261 // may not necessarily support other 3dnow instructions 262 CPU_SSE = (1 << 6), 263 CPU_SSE2 = (1 << 7), 264 CPU_SSE3 = (1 << 8), // SSE3 comes from cpuid 1 (ECX) 265 CPU_SSSE3 = (1 << 9), 266 CPU_SSE4A = (1 << 10), 267 CPU_SSE4_1 = (1 << 11), 268 CPU_SSE4_2 = (1 << 12), 269 CPU_POPCNT = (1 << 13), 270 CPU_LZCNT = (1 << 14), 271 CPU_TSC = (1 << 15), 272 CPU_TSCINV = (1 << 16), 273 CPU_AVX = (1 << 17), 274 CPU_AVX2 = (1 << 18), 275 CPU_AES = (1 << 19), 276 CPU_ERMS = (1 << 20), // enhanced 'rep movsb/stosb' instructions 277 CPU_CLMUL = (1 << 21), // carryless multiply for CRC 278 CPU_BMI1 = (1 << 22), 279 CPU_BMI2 = (1 << 23), 280 CPU_RTM = (1 << 24), // Restricted Transactional Memory instructions 281 CPU_ADX = (1 << 25), 282 CPU_AVX512F = (1 << 26), // AVX 512bit foundation instructions 283 CPU_AVX512DQ = (1 << 27), 284 CPU_AVX512PF = (1 << 28), 285 CPU_AVX512ER = (1 << 29), 286 CPU_AVX512CD = (1 << 30) 287 // Keeping sign bit 31 unassigned. 288 }; 289 290 #define CPU_AVX512BW ((uint64_t)UCONST64(0x100000000)) // enums are limited to 31 bit 291 #define CPU_AVX512VL ((uint64_t)UCONST64(0x200000000)) // EVEX instructions with smaller vector length 292 #define CPU_SHA ((uint64_t)UCONST64(0x400000000)) // SHA instructions 293 #define CPU_FMA ((uint64_t)UCONST64(0x800000000)) // FMA instructions 294 295 enum Extended_Family { 296 // AMD 297 CPU_FAMILY_AMD_11H = 0x11, 298 // Intel 299 CPU_FAMILY_INTEL_CORE = 6, 300 CPU_MODEL_NEHALEM = 0x1e, 301 CPU_MODEL_NEHALEM_EP = 0x1a, 302 CPU_MODEL_NEHALEM_EX = 0x2e, 303 CPU_MODEL_WESTMERE = 0x25, 304 CPU_MODEL_WESTMERE_EP = 0x2c, 305 CPU_MODEL_WESTMERE_EX = 0x2f, 306 CPU_MODEL_SANDYBRIDGE = 0x2a, 307 CPU_MODEL_SANDYBRIDGE_EP = 0x2d, 308 CPU_MODEL_IVYBRIDGE_EP = 0x3a, 309 CPU_MODEL_HASWELL_E3 = 0x3c, 310 CPU_MODEL_HASWELL_E7 = 0x3f, 311 CPU_MODEL_BROADWELL = 0x3d, 312 CPU_MODEL_SKYLAKE = CPU_MODEL_HASWELL_E3 313 }; 314 315 // cpuid information block. All info derived from executing cpuid with 316 // various function numbers is stored here. Intel and AMD info is 317 // merged in this block: accessor methods disentangle it. 318 // 319 // The info block is laid out in subblocks of 4 dwords corresponding to 320 // eax, ebx, ecx and edx, whether or not they contain anything useful. 321 struct CpuidInfo { 322 // cpuid function 0 323 uint32_t std_max_function; 324 uint32_t std_vendor_name_0; 325 uint32_t std_vendor_name_1; 326 uint32_t std_vendor_name_2; 327 328 // cpuid function 1 329 StdCpuid1Eax std_cpuid1_eax; 330 StdCpuid1Ebx std_cpuid1_ebx; 331 StdCpuid1Ecx std_cpuid1_ecx; 332 StdCpuid1Edx std_cpuid1_edx; 333 334 // cpuid function 4 (deterministic cache parameters) 335 DcpCpuid4Eax dcp_cpuid4_eax; 336 DcpCpuid4Ebx dcp_cpuid4_ebx; 337 uint32_t dcp_cpuid4_ecx; // unused currently 338 uint32_t dcp_cpuid4_edx; // unused currently 339 340 // cpuid function 7 (structured extended features) 341 SefCpuid7Eax sef_cpuid7_eax; 342 SefCpuid7Ebx sef_cpuid7_ebx; 343 uint32_t sef_cpuid7_ecx; // unused currently 344 uint32_t sef_cpuid7_edx; // unused currently 345 346 // cpuid function 0xB (processor topology) 347 // ecx = 0 348 uint32_t tpl_cpuidB0_eax; 349 TplCpuidBEbx tpl_cpuidB0_ebx; 350 uint32_t tpl_cpuidB0_ecx; // unused currently 351 uint32_t tpl_cpuidB0_edx; // unused currently 352 353 // ecx = 1 354 uint32_t tpl_cpuidB1_eax; 355 TplCpuidBEbx tpl_cpuidB1_ebx; 356 uint32_t tpl_cpuidB1_ecx; // unused currently 357 uint32_t tpl_cpuidB1_edx; // unused currently 358 359 // ecx = 2 360 uint32_t tpl_cpuidB2_eax; 361 TplCpuidBEbx tpl_cpuidB2_ebx; 362 uint32_t tpl_cpuidB2_ecx; // unused currently 363 uint32_t tpl_cpuidB2_edx; // unused currently 364 365 // cpuid function 0x80000000 // example, unused 366 uint32_t ext_max_function; 367 uint32_t ext_vendor_name_0; 368 uint32_t ext_vendor_name_1; 369 uint32_t ext_vendor_name_2; 370 371 // cpuid function 0x80000001 372 uint32_t ext_cpuid1_eax; // reserved 373 uint32_t ext_cpuid1_ebx; // reserved 374 ExtCpuid1Ecx ext_cpuid1_ecx; 375 ExtCpuid1Edx ext_cpuid1_edx; 376 377 // cpuid functions 0x80000002 thru 0x80000004: example, unused 378 uint32_t proc_name_0, proc_name_1, proc_name_2, proc_name_3; 379 uint32_t proc_name_4, proc_name_5, proc_name_6, proc_name_7; 380 uint32_t proc_name_8, proc_name_9, proc_name_10,proc_name_11; 381 382 // cpuid function 0x80000005 // AMD L1, Intel reserved 383 uint32_t ext_cpuid5_eax; // unused currently 384 uint32_t ext_cpuid5_ebx; // reserved 385 ExtCpuid5Ex ext_cpuid5_ecx; // L1 data cache info (AMD) 386 ExtCpuid5Ex ext_cpuid5_edx; // L1 instruction cache info (AMD) 387 388 // cpuid function 0x80000007 389 uint32_t ext_cpuid7_eax; // reserved 390 uint32_t ext_cpuid7_ebx; // reserved 391 uint32_t ext_cpuid7_ecx; // reserved 392 ExtCpuid7Edx ext_cpuid7_edx; // tscinv 393 394 // cpuid function 0x80000008 395 uint32_t ext_cpuid8_eax; // unused currently 396 uint32_t ext_cpuid8_ebx; // reserved 397 ExtCpuid8Ecx ext_cpuid8_ecx; 398 uint32_t ext_cpuid8_edx; // reserved 399 400 // extended control register XCR0 (the XFEATURE_ENABLED_MASK register) 401 XemXcr0Eax xem_xcr0_eax; 402 uint32_t xem_xcr0_edx; // reserved 403 404 // Space to save ymm registers after signal handle 405 int ymm_save[8*4]; // Save ymm0, ymm7, ymm8, ymm15 406 407 // Space to save zmm registers after signal handle 408 int zmm_save[16*4]; // Save zmm0, zmm7, zmm8, zmm31 409 }; 410 411 // The actual cpuid info block 412 static CpuidInfo _cpuid_info; 413 414 // Extractors and predicates 415 static uint32_t extended_cpu_family() { 416 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.family; 417 result += _cpuid_info.std_cpuid1_eax.bits.ext_family; 418 return result; 419 } 420 421 static uint32_t extended_cpu_model() { 422 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.model; 423 result |= _cpuid_info.std_cpuid1_eax.bits.ext_model << 4; 424 return result; 425 } 426 427 static uint32_t cpu_stepping() { 428 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.stepping; 429 return result; 430 } 431 432 static uint logical_processor_count() { 433 uint result = threads_per_core(); 434 return result; 435 } 436 437 static uint64_t feature_flags() { 438 uint64_t result = 0; 439 if (_cpuid_info.std_cpuid1_edx.bits.cmpxchg8 != 0) 440 result |= CPU_CX8; 441 if (_cpuid_info.std_cpuid1_edx.bits.cmov != 0) 442 result |= CPU_CMOV; 443 if (_cpuid_info.std_cpuid1_edx.bits.fxsr != 0 || (is_amd() && 444 _cpuid_info.ext_cpuid1_edx.bits.fxsr != 0)) 445 result |= CPU_FXSR; 446 // HT flag is set for multi-core processors also. 447 if (threads_per_core() > 1) 448 result |= CPU_HT; 449 if (_cpuid_info.std_cpuid1_edx.bits.mmx != 0 || (is_amd() && 450 _cpuid_info.ext_cpuid1_edx.bits.mmx != 0)) 451 result |= CPU_MMX; 452 if (_cpuid_info.std_cpuid1_edx.bits.sse != 0) 453 result |= CPU_SSE; 454 if (_cpuid_info.std_cpuid1_edx.bits.sse2 != 0) 455 result |= CPU_SSE2; 456 if (_cpuid_info.std_cpuid1_ecx.bits.sse3 != 0) 457 result |= CPU_SSE3; 458 if (_cpuid_info.std_cpuid1_ecx.bits.ssse3 != 0) 459 result |= CPU_SSSE3; 460 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_1 != 0) 461 result |= CPU_SSE4_1; 462 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_2 != 0) 463 result |= CPU_SSE4_2; 464 if (_cpuid_info.std_cpuid1_ecx.bits.popcnt != 0) 465 result |= CPU_POPCNT; 466 if (_cpuid_info.std_cpuid1_ecx.bits.avx != 0 && 467 _cpuid_info.std_cpuid1_ecx.bits.osxsave != 0 && 468 _cpuid_info.xem_xcr0_eax.bits.sse != 0 && 469 _cpuid_info.xem_xcr0_eax.bits.ymm != 0) { 470 result |= CPU_AVX; 471 if (_cpuid_info.sef_cpuid7_ebx.bits.avx2 != 0) 472 result |= CPU_AVX2; 473 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512f != 0 && 474 _cpuid_info.xem_xcr0_eax.bits.opmask != 0 && 475 _cpuid_info.xem_xcr0_eax.bits.zmm512 != 0 && 476 _cpuid_info.xem_xcr0_eax.bits.zmm32 != 0) { 477 result |= CPU_AVX512F; 478 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512cd != 0) 479 result |= CPU_AVX512CD; 480 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512dq != 0) 481 result |= CPU_AVX512DQ; 482 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512pf != 0) 483 result |= CPU_AVX512PF; 484 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512er != 0) 485 result |= CPU_AVX512ER; 486 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512bw != 0) 487 result |= CPU_AVX512BW; 488 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512vl != 0) 489 result |= CPU_AVX512VL; 490 } 491 } 492 if(_cpuid_info.sef_cpuid7_ebx.bits.bmi1 != 0) 493 result |= CPU_BMI1; 494 if (_cpuid_info.std_cpuid1_edx.bits.tsc != 0) 495 result |= CPU_TSC; 496 if (_cpuid_info.ext_cpuid7_edx.bits.tsc_invariance != 0) 497 result |= CPU_TSCINV; 498 if (_cpuid_info.std_cpuid1_ecx.bits.aes != 0) 499 result |= CPU_AES; 500 if (_cpuid_info.sef_cpuid7_ebx.bits.erms != 0) 501 result |= CPU_ERMS; 502 if (_cpuid_info.std_cpuid1_ecx.bits.clmul != 0) 503 result |= CPU_CLMUL; 504 if (_cpuid_info.sef_cpuid7_ebx.bits.rtm != 0) 505 result |= CPU_RTM; 506 507 // AMD features. 508 if (is_amd()) { 509 if ((_cpuid_info.ext_cpuid1_edx.bits.tdnow != 0) || 510 (_cpuid_info.ext_cpuid1_ecx.bits.prefetchw != 0)) 511 result |= CPU_3DNOW_PREFETCH; 512 if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt != 0) 513 result |= CPU_LZCNT; 514 if (_cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0) 515 result |= CPU_SSE4A; 516 } 517 // Intel features. 518 if(is_intel()) { 519 if(_cpuid_info.sef_cpuid7_ebx.bits.adx != 0) 520 result |= CPU_ADX; 521 if(_cpuid_info.sef_cpuid7_ebx.bits.bmi2 != 0) 522 result |= CPU_BMI2; 523 if (_cpuid_info.sef_cpuid7_ebx.bits.sha != 0) 524 result |= CPU_SHA; 525 if(_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0) 526 result |= CPU_LZCNT; 527 if (_cpuid_info.std_cpuid1_ecx.bits.fma != 0) 528 result |= CPU_FMA; 529 // for Intel, ecx.bits.misalignsse bit (bit 8) indicates support for prefetchw 530 if (_cpuid_info.ext_cpuid1_ecx.bits.misalignsse != 0) { 531 result |= CPU_3DNOW_PREFETCH; 532 } 533 } 534 535 return result; 536 } 537 538 static bool os_supports_avx_vectors() { 539 bool retVal = false; 540 if (supports_evex()) { 541 // Verify that OS save/restore all bits of EVEX registers 542 // during signal processing. 543 int nreg = 2 LP64_ONLY(+2); 544 retVal = true; 545 for (int i = 0; i < 16 * nreg; i++) { // 64 bytes per zmm register 546 if (_cpuid_info.zmm_save[i] != ymm_test_value()) { 547 retVal = false; 548 break; 549 } 550 } 551 } else if (supports_avx()) { 552 // Verify that OS save/restore all bits of AVX registers 553 // during signal processing. 554 int nreg = 2 LP64_ONLY(+2); 555 retVal = true; 556 for (int i = 0; i < 8 * nreg; i++) { // 32 bytes per ymm register 557 if (_cpuid_info.ymm_save[i] != ymm_test_value()) { 558 retVal = false; 559 break; 560 } 561 } 562 // zmm_save will be set on a EVEX enabled machine even if we choose AVX code gen 563 if (retVal == false) { 564 // Verify that OS save/restore all bits of EVEX registers 565 // during signal processing. 566 int nreg = 2 LP64_ONLY(+2); 567 retVal = true; 568 for (int i = 0; i < 16 * nreg; i++) { // 64 bytes per zmm register 569 if (_cpuid_info.zmm_save[i] != ymm_test_value()) { 570 retVal = false; 571 break; 572 } 573 } 574 } 575 } 576 return retVal; 577 } 578 579 static void get_processor_features(); 580 581 public: 582 // Offsets for cpuid asm stub 583 static ByteSize std_cpuid0_offset() { return byte_offset_of(CpuidInfo, std_max_function); } 584 static ByteSize std_cpuid1_offset() { return byte_offset_of(CpuidInfo, std_cpuid1_eax); } 585 static ByteSize dcp_cpuid4_offset() { return byte_offset_of(CpuidInfo, dcp_cpuid4_eax); } 586 static ByteSize sef_cpuid7_offset() { return byte_offset_of(CpuidInfo, sef_cpuid7_eax); } 587 static ByteSize ext_cpuid1_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1_eax); } 588 static ByteSize ext_cpuid5_offset() { return byte_offset_of(CpuidInfo, ext_cpuid5_eax); } 589 static ByteSize ext_cpuid7_offset() { return byte_offset_of(CpuidInfo, ext_cpuid7_eax); } 590 static ByteSize ext_cpuid8_offset() { return byte_offset_of(CpuidInfo, ext_cpuid8_eax); } 591 static ByteSize tpl_cpuidB0_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB0_eax); } 592 static ByteSize tpl_cpuidB1_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB1_eax); } 593 static ByteSize tpl_cpuidB2_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB2_eax); } 594 static ByteSize xem_xcr0_offset() { return byte_offset_of(CpuidInfo, xem_xcr0_eax); } 595 static ByteSize ymm_save_offset() { return byte_offset_of(CpuidInfo, ymm_save); } 596 static ByteSize zmm_save_offset() { return byte_offset_of(CpuidInfo, zmm_save); } 597 598 // The value used to check ymm register after signal handle 599 static int ymm_test_value() { return 0xCAFEBABE; } 600 601 static void get_cpu_info_wrapper(); 602 static void set_cpuinfo_segv_addr(address pc) { _cpuinfo_segv_addr = pc; } 603 static bool is_cpuinfo_segv_addr(address pc) { return _cpuinfo_segv_addr == pc; } 604 static void set_cpuinfo_cont_addr(address pc) { _cpuinfo_cont_addr = pc; } 605 static address cpuinfo_cont_addr() { return _cpuinfo_cont_addr; } 606 607 static void clean_cpuFeatures() { _features = 0; } 608 static void set_avx_cpuFeatures() { _features = (CPU_SSE | CPU_SSE2 | CPU_AVX); } 609 static void set_evex_cpuFeatures() { _features = (CPU_AVX512F | CPU_SSE | CPU_SSE2 ); } 610 611 612 // Initialization 613 static void initialize(); 614 615 // Override Abstract_VM_Version implementation 616 static bool use_biased_locking(); 617 618 // Asserts 619 static void assert_is_initialized() { 620 assert(_cpuid_info.std_cpuid1_eax.bits.family != 0, "VM_Version not initialized"); 621 } 622 623 // 624 // Processor family: 625 // 3 - 386 626 // 4 - 486 627 // 5 - Pentium 628 // 6 - PentiumPro, Pentium II, Celeron, Xeon, Pentium III, Athlon, 629 // Pentium M, Core Solo, Core Duo, Core2 Duo 630 // family 6 model: 9, 13, 14, 15 631 // 0x0f - Pentium 4, Opteron 632 // 633 // Note: The cpu family should be used to select between 634 // instruction sequences which are valid on all Intel 635 // processors. Use the feature test functions below to 636 // determine whether a particular instruction is supported. 637 // 638 static int cpu_family() { return _cpu;} 639 static bool is_P6() { return cpu_family() >= 6; } 640 static bool is_amd() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x68747541; } // 'htuA' 641 static bool is_intel() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x756e6547; } // 'uneG' 642 643 static bool supports_processor_topology() { 644 return (_cpuid_info.std_max_function >= 0xB) && 645 // eax[4:0] | ebx[0:15] == 0 indicates invalid topology level. 646 // Some cpus have max cpuid >= 0xB but do not support processor topology. 647 (((_cpuid_info.tpl_cpuidB0_eax & 0x1f) | _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus) != 0); 648 } 649 650 static uint cores_per_cpu() { 651 uint result = 1; 652 if (is_intel()) { 653 bool supports_topology = supports_processor_topology(); 654 if (supports_topology) { 655 result = _cpuid_info.tpl_cpuidB1_ebx.bits.logical_cpus / 656 _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus; 657 } 658 if (!supports_topology || result == 0) { 659 result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1); 660 } 661 } else if (is_amd()) { 662 result = (_cpuid_info.ext_cpuid8_ecx.bits.cores_per_cpu + 1); 663 } 664 return result; 665 } 666 667 static uint threads_per_core() { 668 uint result = 1; 669 if (is_intel() && supports_processor_topology()) { 670 result = _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus; 671 } else if (_cpuid_info.std_cpuid1_edx.bits.ht != 0) { 672 result = _cpuid_info.std_cpuid1_ebx.bits.threads_per_cpu / 673 cores_per_cpu(); 674 } 675 return (result == 0 ? 1 : result); 676 } 677 678 static intx L1_line_size() { 679 intx result = 0; 680 if (is_intel()) { 681 result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1); 682 } else if (is_amd()) { 683 result = _cpuid_info.ext_cpuid5_ecx.bits.L1_line_size; 684 } 685 if (result < 32) // not defined ? 686 result = 32; // 32 bytes by default on x86 and other x64 687 return result; 688 } 689 690 static intx prefetch_data_size() { 691 return L1_line_size(); 692 } 693 694 // 695 // Feature identification 696 // 697 static bool supports_cpuid() { return _features != 0; } 698 static bool supports_cmpxchg8() { return (_features & CPU_CX8) != 0; } 699 static bool supports_cmov() { return (_features & CPU_CMOV) != 0; } 700 static bool supports_fxsr() { return (_features & CPU_FXSR) != 0; } 701 static bool supports_ht() { return (_features & CPU_HT) != 0; } 702 static bool supports_mmx() { return (_features & CPU_MMX) != 0; } 703 static bool supports_sse() { return (_features & CPU_SSE) != 0; } 704 static bool supports_sse2() { return (_features & CPU_SSE2) != 0; } 705 static bool supports_sse3() { return (_features & CPU_SSE3) != 0; } 706 static bool supports_ssse3() { return (_features & CPU_SSSE3)!= 0; } 707 static bool supports_sse4_1() { return (_features & CPU_SSE4_1) != 0; } 708 static bool supports_sse4_2() { return (_features & CPU_SSE4_2) != 0; } 709 static bool supports_popcnt() { return (_features & CPU_POPCNT) != 0; } 710 static bool supports_avx() { return (_features & CPU_AVX) != 0; } 711 static bool supports_avx2() { return (_features & CPU_AVX2) != 0; } 712 static bool supports_tsc() { return (_features & CPU_TSC) != 0; } 713 static bool supports_aes() { return (_features & CPU_AES) != 0; } 714 static bool supports_erms() { return (_features & CPU_ERMS) != 0; } 715 static bool supports_clmul() { return (_features & CPU_CLMUL) != 0; } 716 static bool supports_rtm() { return (_features & CPU_RTM) != 0; } 717 static bool supports_bmi1() { return (_features & CPU_BMI1) != 0; } 718 static bool supports_bmi2() { return (_features & CPU_BMI2) != 0; } 719 static bool supports_adx() { return (_features & CPU_ADX) != 0; } 720 static bool supports_evex() { return (_features & CPU_AVX512F) != 0; } 721 static bool supports_avx512dq() { return (_features & CPU_AVX512DQ) != 0; } 722 static bool supports_avx512pf() { return (_features & CPU_AVX512PF) != 0; } 723 static bool supports_avx512er() { return (_features & CPU_AVX512ER) != 0; } 724 static bool supports_avx512cd() { return (_features & CPU_AVX512CD) != 0; } 725 static bool supports_avx512bw() { return (_features & CPU_AVX512BW) != 0; } 726 static bool supports_avx512vl() { return (_features & CPU_AVX512VL) != 0; } 727 static bool supports_avx512vlbw() { return (supports_avx512bw() && supports_avx512vl()); } 728 static bool supports_avx512novl() { return (supports_evex() && !supports_avx512vl()); } 729 static bool supports_avx512nobw() { return (supports_evex() && !supports_avx512bw()); } 730 static bool supports_avx256only() { return (supports_avx2() && !supports_evex()); } 731 static bool supports_avxonly() { return ((supports_avx2() || supports_avx()) && !supports_evex()); } 732 static bool supports_sha() { return (_features & CPU_SHA) != 0; } 733 static bool supports_fma() { return (_features & CPU_FMA) != 0; } 734 // Intel features 735 static bool is_intel_family_core() { return is_intel() && 736 extended_cpu_family() == CPU_FAMILY_INTEL_CORE; } 737 738 static bool is_intel_tsc_synched_at_init() { 739 if (is_intel_family_core()) { 740 uint32_t ext_model = extended_cpu_model(); 741 if (ext_model == CPU_MODEL_NEHALEM_EP || 742 ext_model == CPU_MODEL_WESTMERE_EP || 743 ext_model == CPU_MODEL_SANDYBRIDGE_EP || 744 ext_model == CPU_MODEL_IVYBRIDGE_EP) { 745 // <= 2-socket invariant tsc support. EX versions are usually used 746 // in > 2-socket systems and likely don't synchronize tscs at 747 // initialization. 748 // Code that uses tsc values must be prepared for them to arbitrarily 749 // jump forward or backward. 750 return true; 751 } 752 } 753 return false; 754 } 755 756 // AMD features 757 static bool supports_3dnow_prefetch() { return (_features & CPU_3DNOW_PREFETCH) != 0; } 758 static bool supports_mmx_ext() { return is_amd() && _cpuid_info.ext_cpuid1_edx.bits.mmx_amd != 0; } 759 static bool supports_lzcnt() { return (_features & CPU_LZCNT) != 0; } 760 static bool supports_sse4a() { return (_features & CPU_SSE4A) != 0; } 761 762 static bool is_amd_Barcelona() { return is_amd() && 763 extended_cpu_family() == CPU_FAMILY_AMD_11H; } 764 765 // Intel and AMD newer cores support fast timestamps well 766 static bool supports_tscinv_bit() { 767 return (_features & CPU_TSCINV) != 0; 768 } 769 static bool supports_tscinv() { 770 return supports_tscinv_bit() && 771 ( (is_amd() && !is_amd_Barcelona()) || 772 is_intel_tsc_synched_at_init() ); 773 } 774 775 // Intel Core and newer cpus have fast IDIV instruction (excluding Atom). 776 static bool has_fast_idiv() { return is_intel() && cpu_family() == 6 && 777 supports_sse3() && _model != 0x1C; } 778 779 static bool supports_compare_and_exchange() { return true; } 780 781 static intx allocate_prefetch_distance() { 782 // This method should be called before allocate_prefetch_style(). 783 // 784 // Hardware prefetching (distance/size in bytes): 785 // Pentium 3 - 64 / 32 786 // Pentium 4 - 256 / 128 787 // Athlon - 64 / 32 ???? 788 // Opteron - 128 / 64 only when 2 sequential cache lines accessed 789 // Core - 128 / 64 790 // 791 // Software prefetching (distance in bytes / instruction with best score): 792 // Pentium 3 - 128 / prefetchnta 793 // Pentium 4 - 512 / prefetchnta 794 // Athlon - 128 / prefetchnta 795 // Opteron - 256 / prefetchnta 796 // Core - 256 / prefetchnta 797 // It will be used only when AllocatePrefetchStyle > 0 798 799 intx count = AllocatePrefetchDistance; 800 if (count < 0) { // default ? 801 if (is_amd()) { // AMD 802 if (supports_sse2()) 803 count = 256; // Opteron 804 else 805 count = 128; // Athlon 806 } else { // Intel 807 if (supports_sse2()) 808 if (cpu_family() == 6) { 809 count = 256; // Pentium M, Core, Core2 810 } else { 811 count = 512; // Pentium 4 812 } 813 else 814 count = 128; // Pentium 3 (and all other old CPUs) 815 } 816 } 817 return count; 818 } 819 static intx allocate_prefetch_style() { 820 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive"); 821 // Return 0 if AllocatePrefetchDistance was not defined. 822 return AllocatePrefetchDistance > 0 ? AllocatePrefetchStyle : 0; 823 } 824 825 // Prefetch interval for gc copy/scan == 9 dcache lines. Derived from 826 // 50-warehouse specjbb runs on a 2-way 1.8ghz opteron using a 4gb heap. 827 // Tested intervals from 128 to 2048 in increments of 64 == one cache line. 828 // 256 bytes (4 dcache lines) was the nearest runner-up to 576. 829 830 // gc copy/scan is disabled if prefetchw isn't supported, because 831 // Prefetch::write emits an inlined prefetchw on Linux. 832 // Do not use the 3dnow prefetchw instruction. It isn't supported on em64t. 833 // The used prefetcht0 instruction works for both amd64 and em64t. 834 static intx prefetch_copy_interval_in_bytes() { 835 intx interval = PrefetchCopyIntervalInBytes; 836 return interval >= 0 ? interval : 576; 837 } 838 static intx prefetch_scan_interval_in_bytes() { 839 intx interval = PrefetchScanIntervalInBytes; 840 return interval >= 0 ? interval : 576; 841 } 842 static intx prefetch_fields_ahead() { 843 intx count = PrefetchFieldsAhead; 844 return count >= 0 ? count : 1; 845 } 846 static uint32_t get_xsave_header_lower_segment() { 847 return _cpuid_info.xem_xcr0_eax.value; 848 } 849 static uint32_t get_xsave_header_upper_segment() { 850 return _cpuid_info.xem_xcr0_edx; 851 } 852 853 // SSE2 and later processors implement a 'pause' instruction 854 // that can be used for efficient implementation of 855 // the intrinsic for java.lang.Thread.onSpinWait() 856 static bool supports_on_spin_wait() { return supports_sse2(); } 857 }; 858 859 #endif // CPU_X86_VM_VM_VERSION_X86_HPP