1 /* 2 * Copyright (c) 2000, 2015, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "c1/c1_InstructionPrinter.hpp" 27 #include "c1/c1_LIR.hpp" 28 #include "c1/c1_LIRAssembler.hpp" 29 #include "c1/c1_ValueStack.hpp" 30 #include "ci/ciInstance.hpp" 31 #include "runtime/sharedRuntime.hpp" 32 33 Register LIR_OprDesc::as_register() const { 34 return FrameMap::cpu_rnr2reg(cpu_regnr()); 35 } 36 37 Register LIR_OprDesc::as_register_lo() const { 38 return FrameMap::cpu_rnr2reg(cpu_regnrLo()); 39 } 40 41 Register LIR_OprDesc::as_register_hi() const { 42 return FrameMap::cpu_rnr2reg(cpu_regnrHi()); 43 } 44 45 #if defined(X86) 46 47 XMMRegister LIR_OprDesc::as_xmm_float_reg() const { 48 return FrameMap::nr2xmmreg(xmm_regnr()); 49 } 50 51 XMMRegister LIR_OprDesc::as_xmm_double_reg() const { 52 assert(xmm_regnrLo() == xmm_regnrHi(), "assumed in calculation"); 53 return FrameMap::nr2xmmreg(xmm_regnrLo()); 54 } 55 56 #endif // X86 57 58 #if defined(SPARC) || defined(PPC32) 59 60 FloatRegister LIR_OprDesc::as_float_reg() const { 61 return FrameMap::nr2floatreg(fpu_regnr()); 62 } 63 64 FloatRegister LIR_OprDesc::as_double_reg() const { 65 return FrameMap::nr2floatreg(fpu_regnrHi()); 66 } 67 68 #endif 69 70 #if defined(ARM) || defined(AARCH64) || defined(PPC64) 71 72 FloatRegister LIR_OprDesc::as_float_reg() const { 73 return as_FloatRegister(fpu_regnr()); 74 } 75 76 FloatRegister LIR_OprDesc::as_double_reg() const { 77 return as_FloatRegister(fpu_regnrLo()); 78 } 79 80 #endif 81 82 83 LIR_Opr LIR_OprFact::illegalOpr = LIR_OprFact::illegal(); 84 85 LIR_Opr LIR_OprFact::value_type(ValueType* type) { 86 ValueTag tag = type->tag(); 87 switch (tag) { 88 case metaDataTag : { 89 ClassConstant* c = type->as_ClassConstant(); 90 if (c != NULL && !c->value()->is_loaded()) { 91 return LIR_OprFact::metadataConst(NULL); 92 } else if (c != NULL) { 93 return LIR_OprFact::metadataConst(c->value()->constant_encoding()); 94 } else { 95 MethodConstant* m = type->as_MethodConstant(); 96 assert (m != NULL, "not a class or a method?"); 97 return LIR_OprFact::metadataConst(m->value()->constant_encoding()); 98 } 99 } 100 case objectTag : { 101 return LIR_OprFact::oopConst(type->as_ObjectType()->encoding()); 102 } 103 case addressTag: return LIR_OprFact::addressConst(type->as_AddressConstant()->value()); 104 case intTag : return LIR_OprFact::intConst(type->as_IntConstant()->value()); 105 case floatTag : return LIR_OprFact::floatConst(type->as_FloatConstant()->value()); 106 case longTag : return LIR_OprFact::longConst(type->as_LongConstant()->value()); 107 case doubleTag : return LIR_OprFact::doubleConst(type->as_DoubleConstant()->value()); 108 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1); 109 } 110 } 111 112 113 LIR_Opr LIR_OprFact::dummy_value_type(ValueType* type) { 114 switch (type->tag()) { 115 case objectTag: return LIR_OprFact::oopConst(NULL); 116 case addressTag:return LIR_OprFact::addressConst(0); 117 case intTag: return LIR_OprFact::intConst(0); 118 case floatTag: return LIR_OprFact::floatConst(0.0); 119 case longTag: return LIR_OprFact::longConst(0); 120 case doubleTag: return LIR_OprFact::doubleConst(0.0); 121 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1); 122 } 123 return illegalOpr; 124 } 125 126 127 128 //--------------------------------------------------- 129 130 131 LIR_Address::Scale LIR_Address::scale(BasicType type) { 132 int elem_size = type2aelembytes(type); 133 switch (elem_size) { 134 case 1: return LIR_Address::times_1; 135 case 2: return LIR_Address::times_2; 136 case 4: return LIR_Address::times_4; 137 case 8: return LIR_Address::times_8; 138 } 139 ShouldNotReachHere(); 140 return LIR_Address::times_1; 141 } 142 143 144 #ifndef PRODUCT 145 void LIR_Address::verify0() const { 146 #if defined(SPARC) || defined(PPC) 147 assert(scale() == times_1, "Scaled addressing mode not available on SPARC/PPC and should not be used"); 148 assert(disp() == 0 || index()->is_illegal(), "can't have both"); 149 #endif 150 #ifdef _LP64 151 assert(base()->is_cpu_register(), "wrong base operand"); 152 #ifndef AARCH64 153 assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand"); 154 #else 155 assert(index()->is_illegal() || index()->is_double_cpu() || index()->is_single_cpu(), "wrong index operand"); 156 #endif 157 assert(base()->type() == T_OBJECT || base()->type() == T_LONG || base()->type() == T_METADATA, 158 "wrong type for addresses"); 159 #else 160 assert(base()->is_single_cpu(), "wrong base operand"); 161 assert(index()->is_illegal() || index()->is_single_cpu(), "wrong index operand"); 162 assert(base()->type() == T_OBJECT || base()->type() == T_INT || base()->type() == T_METADATA, 163 "wrong type for addresses"); 164 #endif 165 } 166 #endif 167 168 169 //--------------------------------------------------- 170 171 char LIR_OprDesc::type_char(BasicType t) { 172 switch (t) { 173 case T_ARRAY: 174 t = T_OBJECT; 175 case T_BOOLEAN: 176 case T_CHAR: 177 case T_FLOAT: 178 case T_DOUBLE: 179 case T_BYTE: 180 case T_SHORT: 181 case T_INT: 182 case T_LONG: 183 case T_OBJECT: 184 case T_ADDRESS: 185 case T_VOID: 186 return ::type2char(t); 187 case T_METADATA: 188 return 'M'; 189 case T_ILLEGAL: 190 return '?'; 191 192 default: 193 ShouldNotReachHere(); 194 return '?'; 195 } 196 } 197 198 #ifndef PRODUCT 199 void LIR_OprDesc::validate_type() const { 200 201 #ifdef ASSERT 202 if (!is_pointer() && !is_illegal()) { 203 OprKind kindfield = kind_field(); // Factored out because of compiler bug, see 8002160 204 switch (as_BasicType(type_field())) { 205 case T_LONG: 206 assert((kindfield == cpu_register || kindfield == stack_value) && 207 size_field() == double_size, "must match"); 208 break; 209 case T_FLOAT: 210 // FP return values can be also in CPU registers on ARM and PPC32 (softfp ABI) 211 assert((kindfield == fpu_register || kindfield == stack_value 212 ARM_ONLY(|| kindfield == cpu_register) 213 PPC32_ONLY(|| kindfield == cpu_register) ) && 214 size_field() == single_size, "must match"); 215 break; 216 case T_DOUBLE: 217 // FP return values can be also in CPU registers on ARM and PPC32 (softfp ABI) 218 assert((kindfield == fpu_register || kindfield == stack_value 219 ARM_ONLY(|| kindfield == cpu_register) 220 PPC32_ONLY(|| kindfield == cpu_register) ) && 221 size_field() == double_size, "must match"); 222 break; 223 case T_BOOLEAN: 224 case T_CHAR: 225 case T_BYTE: 226 case T_SHORT: 227 case T_INT: 228 case T_ADDRESS: 229 case T_OBJECT: 230 case T_METADATA: 231 case T_ARRAY: 232 assert((kindfield == cpu_register || kindfield == stack_value) && 233 size_field() == single_size, "must match"); 234 break; 235 236 case T_ILLEGAL: 237 // XXX TKR also means unknown right now 238 // assert(is_illegal(), "must match"); 239 break; 240 241 default: 242 ShouldNotReachHere(); 243 } 244 } 245 #endif 246 247 } 248 #endif // PRODUCT 249 250 251 bool LIR_OprDesc::is_oop() const { 252 if (is_pointer()) { 253 return pointer()->is_oop_pointer(); 254 } else { 255 OprType t= type_field(); 256 assert(t != unknown_type, "not set"); 257 return t == object_type; 258 } 259 } 260 261 262 263 void LIR_Op2::verify() const { 264 #ifdef ASSERT 265 switch (code()) { 266 case lir_cmove: 267 case lir_xchg: 268 break; 269 270 default: 271 assert(!result_opr()->is_register() || !result_opr()->is_oop_register(), 272 "can't produce oops from arith"); 273 } 274 275 if (TwoOperandLIRForm) { 276 switch (code()) { 277 case lir_add: 278 case lir_sub: 279 case lir_mul: 280 case lir_mul_strictfp: 281 case lir_div: 282 case lir_div_strictfp: 283 case lir_rem: 284 case lir_logic_and: 285 case lir_logic_or: 286 case lir_logic_xor: 287 case lir_shl: 288 case lir_shr: 289 assert(in_opr1() == result_opr(), "opr1 and result must match"); 290 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid"); 291 break; 292 293 // special handling for lir_ushr because of write barriers 294 case lir_ushr: 295 assert(in_opr1() == result_opr() || in_opr2()->is_constant(), "opr1 and result must match or shift count is constant"); 296 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid"); 297 break; 298 299 } 300 } 301 #endif 302 } 303 304 305 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block) 306 : LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL) 307 , _cond(cond) 308 , _type(type) 309 , _label(block->label()) 310 , _block(block) 311 , _ublock(NULL) 312 , _stub(NULL) { 313 } 314 315 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, CodeStub* stub) : 316 LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL) 317 , _cond(cond) 318 , _type(type) 319 , _label(stub->entry()) 320 , _block(NULL) 321 , _ublock(NULL) 322 , _stub(stub) { 323 } 324 325 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block, BlockBegin* ublock) 326 : LIR_Op(lir_cond_float_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL) 327 , _cond(cond) 328 , _type(type) 329 , _label(block->label()) 330 , _block(block) 331 , _ublock(ublock) 332 , _stub(NULL) 333 { 334 } 335 336 void LIR_OpBranch::change_block(BlockBegin* b) { 337 assert(_block != NULL, "must have old block"); 338 assert(_block->label() == label(), "must be equal"); 339 340 _block = b; 341 _label = b->label(); 342 } 343 344 void LIR_OpBranch::change_ublock(BlockBegin* b) { 345 assert(_ublock != NULL, "must have old block"); 346 _ublock = b; 347 } 348 349 void LIR_OpBranch::negate_cond() { 350 switch (_cond) { 351 case lir_cond_equal: _cond = lir_cond_notEqual; break; 352 case lir_cond_notEqual: _cond = lir_cond_equal; break; 353 case lir_cond_less: _cond = lir_cond_greaterEqual; break; 354 case lir_cond_lessEqual: _cond = lir_cond_greater; break; 355 case lir_cond_greaterEqual: _cond = lir_cond_less; break; 356 case lir_cond_greater: _cond = lir_cond_lessEqual; break; 357 default: ShouldNotReachHere(); 358 } 359 } 360 361 362 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr result, LIR_Opr object, ciKlass* klass, 363 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, 364 bool fast_check, CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch, 365 CodeStub* stub) 366 367 : LIR_Op(code, result, NULL) 368 , _object(object) 369 , _array(LIR_OprFact::illegalOpr) 370 , _klass(klass) 371 , _tmp1(tmp1) 372 , _tmp2(tmp2) 373 , _tmp3(tmp3) 374 , _fast_check(fast_check) 375 , _stub(stub) 376 , _info_for_patch(info_for_patch) 377 , _info_for_exception(info_for_exception) 378 , _profiled_method(NULL) 379 , _profiled_bci(-1) 380 , _should_profile(false) 381 { 382 if (code == lir_checkcast) { 383 assert(info_for_exception != NULL, "checkcast throws exceptions"); 384 } else if (code == lir_instanceof) { 385 assert(info_for_exception == NULL, "instanceof throws no exceptions"); 386 } else { 387 ShouldNotReachHere(); 388 } 389 } 390 391 392 393 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, CodeEmitInfo* info_for_exception) 394 : LIR_Op(code, LIR_OprFact::illegalOpr, NULL) 395 , _object(object) 396 , _array(array) 397 , _klass(NULL) 398 , _tmp1(tmp1) 399 , _tmp2(tmp2) 400 , _tmp3(tmp3) 401 , _fast_check(false) 402 , _stub(NULL) 403 , _info_for_patch(NULL) 404 , _info_for_exception(info_for_exception) 405 , _profiled_method(NULL) 406 , _profiled_bci(-1) 407 , _should_profile(false) 408 { 409 if (code == lir_store_check) { 410 _stub = new ArrayStoreExceptionStub(object, info_for_exception); 411 assert(info_for_exception != NULL, "store_check throws exceptions"); 412 } else { 413 ShouldNotReachHere(); 414 } 415 } 416 417 418 LIR_OpArrayCopy::LIR_OpArrayCopy(LIR_Opr src, LIR_Opr src_pos, LIR_Opr dst, LIR_Opr dst_pos, LIR_Opr length, 419 LIR_Opr tmp, ciArrayKlass* expected_type, int flags, CodeEmitInfo* info) 420 : LIR_Op(lir_arraycopy, LIR_OprFact::illegalOpr, info) 421 , _tmp(tmp) 422 , _src(src) 423 , _src_pos(src_pos) 424 , _dst(dst) 425 , _dst_pos(dst_pos) 426 , _flags(flags) 427 , _expected_type(expected_type) 428 , _length(length) { 429 _stub = new ArrayCopyStub(this); 430 } 431 432 LIR_OpUpdateCRC32::LIR_OpUpdateCRC32(LIR_Opr crc, LIR_Opr val, LIR_Opr res) 433 : LIR_Op(lir_updatecrc32, res, NULL) 434 , _crc(crc) 435 , _val(val) { 436 } 437 438 //-------------------verify-------------------------- 439 440 void LIR_Op1::verify() const { 441 switch(code()) { 442 case lir_move: 443 assert(in_opr()->is_valid() && result_opr()->is_valid(), "must be"); 444 break; 445 case lir_null_check: 446 assert(in_opr()->is_register(), "must be"); 447 break; 448 case lir_return: 449 assert(in_opr()->is_register() || in_opr()->is_illegal(), "must be"); 450 break; 451 } 452 } 453 454 void LIR_OpRTCall::verify() const { 455 assert(strcmp(Runtime1::name_for_address(addr()), "<unknown function>") != 0, "unknown function"); 456 } 457 458 //-------------------visits-------------------------- 459 460 // complete rework of LIR instruction visitor. 461 // The virtual call for each instruction type is replaced by a big 462 // switch that adds the operands for each instruction 463 464 void LIR_OpVisitState::visit(LIR_Op* op) { 465 // copy information from the LIR_Op 466 reset(); 467 set_op(op); 468 469 switch (op->code()) { 470 471 // LIR_Op0 472 case lir_word_align: // result and info always invalid 473 case lir_backwardbranch_target: // result and info always invalid 474 case lir_build_frame: // result and info always invalid 475 case lir_fpop_raw: // result and info always invalid 476 case lir_24bit_FPU: // result and info always invalid 477 case lir_reset_FPU: // result and info always invalid 478 case lir_breakpoint: // result and info always invalid 479 case lir_membar: // result and info always invalid 480 case lir_membar_acquire: // result and info always invalid 481 case lir_membar_release: // result and info always invalid 482 case lir_membar_loadload: // result and info always invalid 483 case lir_membar_storestore: // result and info always invalid 484 case lir_membar_loadstore: // result and info always invalid 485 case lir_membar_storeload: // result and info always invalid 486 case lir_on_spin_wait: 487 { 488 assert(op->as_Op0() != NULL, "must be"); 489 assert(op->_info == NULL, "info not used by this instruction"); 490 assert(op->_result->is_illegal(), "not used"); 491 break; 492 } 493 494 case lir_nop: // may have info, result always invalid 495 case lir_std_entry: // may have result, info always invalid 496 case lir_osr_entry: // may have result, info always invalid 497 case lir_get_thread: // may have result, info always invalid 498 { 499 assert(op->as_Op0() != NULL, "must be"); 500 if (op->_info != NULL) do_info(op->_info); 501 if (op->_result->is_valid()) do_output(op->_result); 502 break; 503 } 504 505 506 // LIR_OpLabel 507 case lir_label: // result and info always invalid 508 { 509 assert(op->as_OpLabel() != NULL, "must be"); 510 assert(op->_info == NULL, "info not used by this instruction"); 511 assert(op->_result->is_illegal(), "not used"); 512 break; 513 } 514 515 516 // LIR_Op1 517 case lir_fxch: // input always valid, result and info always invalid 518 case lir_fld: // input always valid, result and info always invalid 519 case lir_ffree: // input always valid, result and info always invalid 520 case lir_push: // input always valid, result and info always invalid 521 case lir_pop: // input always valid, result and info always invalid 522 case lir_return: // input always valid, result and info always invalid 523 case lir_leal: // input and result always valid, info always invalid 524 case lir_neg: // input and result always valid, info always invalid 525 case lir_monaddr: // input and result always valid, info always invalid 526 case lir_null_check: // input and info always valid, result always invalid 527 case lir_move: // input and result always valid, may have info 528 case lir_pack64: // input and result always valid 529 case lir_unpack64: // input and result always valid 530 { 531 assert(op->as_Op1() != NULL, "must be"); 532 LIR_Op1* op1 = (LIR_Op1*)op; 533 534 if (op1->_info) do_info(op1->_info); 535 if (op1->_opr->is_valid()) do_input(op1->_opr); 536 if (op1->_result->is_valid()) do_output(op1->_result); 537 538 break; 539 } 540 541 case lir_safepoint: 542 { 543 assert(op->as_Op1() != NULL, "must be"); 544 LIR_Op1* op1 = (LIR_Op1*)op; 545 546 assert(op1->_info != NULL, ""); do_info(op1->_info); 547 if (op1->_opr->is_valid()) do_temp(op1->_opr); // safepoints on SPARC need temporary register 548 assert(op1->_result->is_illegal(), "safepoint does not produce value"); 549 550 break; 551 } 552 553 // LIR_OpConvert; 554 case lir_convert: // input and result always valid, info always invalid 555 { 556 assert(op->as_OpConvert() != NULL, "must be"); 557 LIR_OpConvert* opConvert = (LIR_OpConvert*)op; 558 559 assert(opConvert->_info == NULL, "must be"); 560 if (opConvert->_opr->is_valid()) do_input(opConvert->_opr); 561 if (opConvert->_result->is_valid()) do_output(opConvert->_result); 562 #ifdef PPC32 563 if (opConvert->_tmp1->is_valid()) do_temp(opConvert->_tmp1); 564 if (opConvert->_tmp2->is_valid()) do_temp(opConvert->_tmp2); 565 #endif 566 do_stub(opConvert->_stub); 567 568 break; 569 } 570 571 // LIR_OpBranch; 572 case lir_branch: // may have info, input and result register always invalid 573 case lir_cond_float_branch: // may have info, input and result register always invalid 574 { 575 assert(op->as_OpBranch() != NULL, "must be"); 576 LIR_OpBranch* opBranch = (LIR_OpBranch*)op; 577 578 if (opBranch->_info != NULL) do_info(opBranch->_info); 579 assert(opBranch->_result->is_illegal(), "not used"); 580 if (opBranch->_stub != NULL) opBranch->stub()->visit(this); 581 582 break; 583 } 584 585 586 // LIR_OpAllocObj 587 case lir_alloc_object: 588 { 589 assert(op->as_OpAllocObj() != NULL, "must be"); 590 LIR_OpAllocObj* opAllocObj = (LIR_OpAllocObj*)op; 591 592 if (opAllocObj->_info) do_info(opAllocObj->_info); 593 if (opAllocObj->_opr->is_valid()) { do_input(opAllocObj->_opr); 594 do_temp(opAllocObj->_opr); 595 } 596 if (opAllocObj->_tmp1->is_valid()) do_temp(opAllocObj->_tmp1); 597 if (opAllocObj->_tmp2->is_valid()) do_temp(opAllocObj->_tmp2); 598 if (opAllocObj->_tmp3->is_valid()) do_temp(opAllocObj->_tmp3); 599 if (opAllocObj->_tmp4->is_valid()) do_temp(opAllocObj->_tmp4); 600 if (opAllocObj->_result->is_valid()) do_output(opAllocObj->_result); 601 do_stub(opAllocObj->_stub); 602 break; 603 } 604 605 606 // LIR_OpRoundFP; 607 case lir_roundfp: { 608 assert(op->as_OpRoundFP() != NULL, "must be"); 609 LIR_OpRoundFP* opRoundFP = (LIR_OpRoundFP*)op; 610 611 assert(op->_info == NULL, "info not used by this instruction"); 612 assert(opRoundFP->_tmp->is_illegal(), "not used"); 613 do_input(opRoundFP->_opr); 614 do_output(opRoundFP->_result); 615 616 break; 617 } 618 619 620 // LIR_Op2 621 case lir_cmp: 622 case lir_cmp_l2i: 623 case lir_ucmp_fd2i: 624 case lir_cmp_fd2i: 625 case lir_add: 626 case lir_sub: 627 case lir_mul: 628 case lir_div: 629 case lir_rem: 630 case lir_sqrt: 631 case lir_abs: 632 case lir_logic_and: 633 case lir_logic_or: 634 case lir_logic_xor: 635 case lir_shl: 636 case lir_shr: 637 case lir_ushr: 638 case lir_xadd: 639 case lir_xchg: 640 case lir_assert: 641 { 642 assert(op->as_Op2() != NULL, "must be"); 643 LIR_Op2* op2 = (LIR_Op2*)op; 644 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() && 645 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used"); 646 647 if (op2->_info) do_info(op2->_info); 648 if (op2->_opr1->is_valid()) do_input(op2->_opr1); 649 if (op2->_opr2->is_valid()) do_input(op2->_opr2); 650 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1); 651 if (op2->_result->is_valid()) do_output(op2->_result); 652 if (op->code() == lir_xchg || op->code() == lir_xadd) { 653 // on ARM and PPC, return value is loaded first so could 654 // destroy inputs. On other platforms that implement those 655 // (x86, sparc), the extra constrainsts are harmless. 656 if (op2->_opr1->is_valid()) do_temp(op2->_opr1); 657 if (op2->_opr2->is_valid()) do_temp(op2->_opr2); 658 } 659 660 break; 661 } 662 663 // special handling for cmove: right input operand must not be equal 664 // to the result operand, otherwise the backend fails 665 case lir_cmove: 666 { 667 assert(op->as_Op2() != NULL, "must be"); 668 LIR_Op2* op2 = (LIR_Op2*)op; 669 670 assert(op2->_info == NULL && op2->_tmp1->is_illegal() && op2->_tmp2->is_illegal() && 671 op2->_tmp3->is_illegal() && op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used"); 672 assert(op2->_opr1->is_valid() && op2->_opr2->is_valid() && op2->_result->is_valid(), "used"); 673 674 do_input(op2->_opr1); 675 do_input(op2->_opr2); 676 do_temp(op2->_opr2); 677 do_output(op2->_result); 678 679 break; 680 } 681 682 // vspecial handling for strict operations: register input operands 683 // as temp to guarantee that they do not overlap with other 684 // registers 685 case lir_mul_strictfp: 686 case lir_div_strictfp: 687 { 688 assert(op->as_Op2() != NULL, "must be"); 689 LIR_Op2* op2 = (LIR_Op2*)op; 690 691 assert(op2->_info == NULL, "not used"); 692 assert(op2->_opr1->is_valid(), "used"); 693 assert(op2->_opr2->is_valid(), "used"); 694 assert(op2->_result->is_valid(), "used"); 695 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() && 696 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used"); 697 698 do_input(op2->_opr1); do_temp(op2->_opr1); 699 do_input(op2->_opr2); do_temp(op2->_opr2); 700 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1); 701 do_output(op2->_result); 702 703 break; 704 } 705 706 case lir_throw: { 707 assert(op->as_Op2() != NULL, "must be"); 708 LIR_Op2* op2 = (LIR_Op2*)op; 709 710 if (op2->_info) do_info(op2->_info); 711 if (op2->_opr1->is_valid()) do_temp(op2->_opr1); 712 if (op2->_opr2->is_valid()) do_input(op2->_opr2); // exception object is input parameter 713 assert(op2->_result->is_illegal(), "no result"); 714 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() && 715 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used"); 716 717 break; 718 } 719 720 case lir_unwind: { 721 assert(op->as_Op1() != NULL, "must be"); 722 LIR_Op1* op1 = (LIR_Op1*)op; 723 724 assert(op1->_info == NULL, "no info"); 725 assert(op1->_opr->is_valid(), "exception oop"); do_input(op1->_opr); 726 assert(op1->_result->is_illegal(), "no result"); 727 728 break; 729 } 730 731 // LIR_Op3 732 case lir_idiv: 733 case lir_irem: { 734 assert(op->as_Op3() != NULL, "must be"); 735 LIR_Op3* op3= (LIR_Op3*)op; 736 737 if (op3->_info) do_info(op3->_info); 738 if (op3->_opr1->is_valid()) do_input(op3->_opr1); 739 740 // second operand is input and temp, so ensure that second operand 741 // and third operand get not the same register 742 if (op3->_opr2->is_valid()) do_input(op3->_opr2); 743 if (op3->_opr2->is_valid()) do_temp(op3->_opr2); 744 if (op3->_opr3->is_valid()) do_temp(op3->_opr3); 745 746 if (op3->_result->is_valid()) do_output(op3->_result); 747 748 break; 749 } 750 751 752 // LIR_OpJavaCall 753 case lir_static_call: 754 case lir_optvirtual_call: 755 case lir_icvirtual_call: 756 case lir_virtual_call: 757 case lir_dynamic_call: { 758 LIR_OpJavaCall* opJavaCall = op->as_OpJavaCall(); 759 assert(opJavaCall != NULL, "must be"); 760 761 if (opJavaCall->_receiver->is_valid()) do_input(opJavaCall->_receiver); 762 763 // only visit register parameters 764 int n = opJavaCall->_arguments->length(); 765 for (int i = opJavaCall->_receiver->is_valid() ? 1 : 0; i < n; i++) { 766 if (!opJavaCall->_arguments->at(i)->is_pointer()) { 767 do_input(*opJavaCall->_arguments->adr_at(i)); 768 } 769 } 770 771 if (opJavaCall->_info) do_info(opJavaCall->_info); 772 if (FrameMap::method_handle_invoke_SP_save_opr() != LIR_OprFact::illegalOpr && 773 opJavaCall->is_method_handle_invoke()) { 774 opJavaCall->_method_handle_invoke_SP_save_opr = FrameMap::method_handle_invoke_SP_save_opr(); 775 do_temp(opJavaCall->_method_handle_invoke_SP_save_opr); 776 } 777 do_call(); 778 if (opJavaCall->_result->is_valid()) do_output(opJavaCall->_result); 779 780 break; 781 } 782 783 784 // LIR_OpRTCall 785 case lir_rtcall: { 786 assert(op->as_OpRTCall() != NULL, "must be"); 787 LIR_OpRTCall* opRTCall = (LIR_OpRTCall*)op; 788 789 // only visit register parameters 790 int n = opRTCall->_arguments->length(); 791 for (int i = 0; i < n; i++) { 792 if (!opRTCall->_arguments->at(i)->is_pointer()) { 793 do_input(*opRTCall->_arguments->adr_at(i)); 794 } 795 } 796 if (opRTCall->_info) do_info(opRTCall->_info); 797 if (opRTCall->_tmp->is_valid()) do_temp(opRTCall->_tmp); 798 do_call(); 799 if (opRTCall->_result->is_valid()) do_output(opRTCall->_result); 800 801 break; 802 } 803 804 805 // LIR_OpArrayCopy 806 case lir_arraycopy: { 807 assert(op->as_OpArrayCopy() != NULL, "must be"); 808 LIR_OpArrayCopy* opArrayCopy = (LIR_OpArrayCopy*)op; 809 810 assert(opArrayCopy->_result->is_illegal(), "unused"); 811 assert(opArrayCopy->_src->is_valid(), "used"); do_input(opArrayCopy->_src); do_temp(opArrayCopy->_src); 812 assert(opArrayCopy->_src_pos->is_valid(), "used"); do_input(opArrayCopy->_src_pos); do_temp(opArrayCopy->_src_pos); 813 assert(opArrayCopy->_dst->is_valid(), "used"); do_input(opArrayCopy->_dst); do_temp(opArrayCopy->_dst); 814 assert(opArrayCopy->_dst_pos->is_valid(), "used"); do_input(opArrayCopy->_dst_pos); do_temp(opArrayCopy->_dst_pos); 815 assert(opArrayCopy->_length->is_valid(), "used"); do_input(opArrayCopy->_length); do_temp(opArrayCopy->_length); 816 assert(opArrayCopy->_tmp->is_valid(), "used"); do_temp(opArrayCopy->_tmp); 817 if (opArrayCopy->_info) do_info(opArrayCopy->_info); 818 819 // the implementation of arraycopy always has a call into the runtime 820 do_call(); 821 822 break; 823 } 824 825 826 // LIR_OpUpdateCRC32 827 case lir_updatecrc32: { 828 assert(op->as_OpUpdateCRC32() != NULL, "must be"); 829 LIR_OpUpdateCRC32* opUp = (LIR_OpUpdateCRC32*)op; 830 831 assert(opUp->_crc->is_valid(), "used"); do_input(opUp->_crc); do_temp(opUp->_crc); 832 assert(opUp->_val->is_valid(), "used"); do_input(opUp->_val); do_temp(opUp->_val); 833 assert(opUp->_result->is_valid(), "used"); do_output(opUp->_result); 834 assert(opUp->_info == NULL, "no info for LIR_OpUpdateCRC32"); 835 836 break; 837 } 838 839 840 // LIR_OpLock 841 case lir_lock: 842 case lir_unlock: { 843 assert(op->as_OpLock() != NULL, "must be"); 844 LIR_OpLock* opLock = (LIR_OpLock*)op; 845 846 if (opLock->_info) do_info(opLock->_info); 847 848 // TODO: check if these operands really have to be temp 849 // (or if input is sufficient). This may have influence on the oop map! 850 assert(opLock->_lock->is_valid(), "used"); do_temp(opLock->_lock); 851 assert(opLock->_hdr->is_valid(), "used"); do_temp(opLock->_hdr); 852 assert(opLock->_obj->is_valid(), "used"); do_temp(opLock->_obj); 853 854 if (opLock->_scratch->is_valid()) do_temp(opLock->_scratch); 855 assert(opLock->_result->is_illegal(), "unused"); 856 857 do_stub(opLock->_stub); 858 859 break; 860 } 861 862 863 // LIR_OpDelay 864 case lir_delay_slot: { 865 assert(op->as_OpDelay() != NULL, "must be"); 866 LIR_OpDelay* opDelay = (LIR_OpDelay*)op; 867 868 visit(opDelay->delay_op()); 869 break; 870 } 871 872 // LIR_OpTypeCheck 873 case lir_instanceof: 874 case lir_checkcast: 875 case lir_store_check: { 876 assert(op->as_OpTypeCheck() != NULL, "must be"); 877 LIR_OpTypeCheck* opTypeCheck = (LIR_OpTypeCheck*)op; 878 879 if (opTypeCheck->_info_for_exception) do_info(opTypeCheck->_info_for_exception); 880 if (opTypeCheck->_info_for_patch) do_info(opTypeCheck->_info_for_patch); 881 if (opTypeCheck->_object->is_valid()) do_input(opTypeCheck->_object); 882 if (op->code() == lir_store_check && opTypeCheck->_object->is_valid()) { 883 do_temp(opTypeCheck->_object); 884 } 885 if (opTypeCheck->_array->is_valid()) do_input(opTypeCheck->_array); 886 if (opTypeCheck->_tmp1->is_valid()) do_temp(opTypeCheck->_tmp1); 887 if (opTypeCheck->_tmp2->is_valid()) do_temp(opTypeCheck->_tmp2); 888 if (opTypeCheck->_tmp3->is_valid()) do_temp(opTypeCheck->_tmp3); 889 if (opTypeCheck->_result->is_valid()) do_output(opTypeCheck->_result); 890 do_stub(opTypeCheck->_stub); 891 break; 892 } 893 894 // LIR_OpCompareAndSwap 895 case lir_cas_long: 896 case lir_cas_obj: 897 case lir_cas_int: { 898 assert(op->as_OpCompareAndSwap() != NULL, "must be"); 899 LIR_OpCompareAndSwap* opCompareAndSwap = (LIR_OpCompareAndSwap*)op; 900 901 assert(opCompareAndSwap->_addr->is_valid(), "used"); 902 assert(opCompareAndSwap->_cmp_value->is_valid(), "used"); 903 assert(opCompareAndSwap->_new_value->is_valid(), "used"); 904 if (opCompareAndSwap->_info) do_info(opCompareAndSwap->_info); 905 do_input(opCompareAndSwap->_addr); 906 do_temp(opCompareAndSwap->_addr); 907 do_input(opCompareAndSwap->_cmp_value); 908 do_temp(opCompareAndSwap->_cmp_value); 909 do_input(opCompareAndSwap->_new_value); 910 do_temp(opCompareAndSwap->_new_value); 911 if (opCompareAndSwap->_tmp1->is_valid()) do_temp(opCompareAndSwap->_tmp1); 912 if (opCompareAndSwap->_tmp2->is_valid()) do_temp(opCompareAndSwap->_tmp2); 913 if (opCompareAndSwap->_result->is_valid()) do_output(opCompareAndSwap->_result); 914 915 break; 916 } 917 918 919 // LIR_OpAllocArray; 920 case lir_alloc_array: { 921 assert(op->as_OpAllocArray() != NULL, "must be"); 922 LIR_OpAllocArray* opAllocArray = (LIR_OpAllocArray*)op; 923 924 if (opAllocArray->_info) do_info(opAllocArray->_info); 925 if (opAllocArray->_klass->is_valid()) do_input(opAllocArray->_klass); do_temp(opAllocArray->_klass); 926 if (opAllocArray->_len->is_valid()) do_input(opAllocArray->_len); do_temp(opAllocArray->_len); 927 if (opAllocArray->_tmp1->is_valid()) do_temp(opAllocArray->_tmp1); 928 if (opAllocArray->_tmp2->is_valid()) do_temp(opAllocArray->_tmp2); 929 if (opAllocArray->_tmp3->is_valid()) do_temp(opAllocArray->_tmp3); 930 if (opAllocArray->_tmp4->is_valid()) do_temp(opAllocArray->_tmp4); 931 if (opAllocArray->_result->is_valid()) do_output(opAllocArray->_result); 932 do_stub(opAllocArray->_stub); 933 break; 934 } 935 936 // LIR_OpProfileCall: 937 case lir_profile_call: { 938 assert(op->as_OpProfileCall() != NULL, "must be"); 939 LIR_OpProfileCall* opProfileCall = (LIR_OpProfileCall*)op; 940 941 if (opProfileCall->_recv->is_valid()) do_temp(opProfileCall->_recv); 942 assert(opProfileCall->_mdo->is_valid(), "used"); do_temp(opProfileCall->_mdo); 943 assert(opProfileCall->_tmp1->is_valid(), "used"); do_temp(opProfileCall->_tmp1); 944 break; 945 } 946 947 // LIR_OpProfileType: 948 case lir_profile_type: { 949 assert(op->as_OpProfileType() != NULL, "must be"); 950 LIR_OpProfileType* opProfileType = (LIR_OpProfileType*)op; 951 952 do_input(opProfileType->_mdp); do_temp(opProfileType->_mdp); 953 do_input(opProfileType->_obj); 954 do_temp(opProfileType->_tmp); 955 break; 956 } 957 default: 958 ShouldNotReachHere(); 959 } 960 } 961 962 963 void LIR_OpVisitState::do_stub(CodeStub* stub) { 964 if (stub != NULL) { 965 stub->visit(this); 966 } 967 } 968 969 XHandlers* LIR_OpVisitState::all_xhandler() { 970 XHandlers* result = NULL; 971 972 int i; 973 for (i = 0; i < info_count(); i++) { 974 if (info_at(i)->exception_handlers() != NULL) { 975 result = info_at(i)->exception_handlers(); 976 break; 977 } 978 } 979 980 #ifdef ASSERT 981 for (i = 0; i < info_count(); i++) { 982 assert(info_at(i)->exception_handlers() == NULL || 983 info_at(i)->exception_handlers() == result, 984 "only one xhandler list allowed per LIR-operation"); 985 } 986 #endif 987 988 if (result != NULL) { 989 return result; 990 } else { 991 return new XHandlers(); 992 } 993 994 return result; 995 } 996 997 998 #ifdef ASSERT 999 bool LIR_OpVisitState::no_operands(LIR_Op* op) { 1000 visit(op); 1001 1002 return opr_count(inputMode) == 0 && 1003 opr_count(outputMode) == 0 && 1004 opr_count(tempMode) == 0 && 1005 info_count() == 0 && 1006 !has_call() && 1007 !has_slow_case(); 1008 } 1009 #endif 1010 1011 //--------------------------------------------------- 1012 1013 1014 void LIR_OpJavaCall::emit_code(LIR_Assembler* masm) { 1015 masm->emit_call(this); 1016 } 1017 1018 void LIR_OpRTCall::emit_code(LIR_Assembler* masm) { 1019 masm->emit_rtcall(this); 1020 } 1021 1022 void LIR_OpLabel::emit_code(LIR_Assembler* masm) { 1023 masm->emit_opLabel(this); 1024 } 1025 1026 void LIR_OpArrayCopy::emit_code(LIR_Assembler* masm) { 1027 masm->emit_arraycopy(this); 1028 masm->append_code_stub(stub()); 1029 } 1030 1031 void LIR_OpUpdateCRC32::emit_code(LIR_Assembler* masm) { 1032 masm->emit_updatecrc32(this); 1033 } 1034 1035 void LIR_Op0::emit_code(LIR_Assembler* masm) { 1036 masm->emit_op0(this); 1037 } 1038 1039 void LIR_Op1::emit_code(LIR_Assembler* masm) { 1040 masm->emit_op1(this); 1041 } 1042 1043 void LIR_OpAllocObj::emit_code(LIR_Assembler* masm) { 1044 masm->emit_alloc_obj(this); 1045 masm->append_code_stub(stub()); 1046 } 1047 1048 void LIR_OpBranch::emit_code(LIR_Assembler* masm) { 1049 masm->emit_opBranch(this); 1050 if (stub()) { 1051 masm->append_code_stub(stub()); 1052 } 1053 } 1054 1055 void LIR_OpConvert::emit_code(LIR_Assembler* masm) { 1056 masm->emit_opConvert(this); 1057 if (stub() != NULL) { 1058 masm->append_code_stub(stub()); 1059 } 1060 } 1061 1062 void LIR_Op2::emit_code(LIR_Assembler* masm) { 1063 masm->emit_op2(this); 1064 } 1065 1066 void LIR_OpAllocArray::emit_code(LIR_Assembler* masm) { 1067 masm->emit_alloc_array(this); 1068 masm->append_code_stub(stub()); 1069 } 1070 1071 void LIR_OpTypeCheck::emit_code(LIR_Assembler* masm) { 1072 masm->emit_opTypeCheck(this); 1073 if (stub()) { 1074 masm->append_code_stub(stub()); 1075 } 1076 } 1077 1078 void LIR_OpCompareAndSwap::emit_code(LIR_Assembler* masm) { 1079 masm->emit_compare_and_swap(this); 1080 } 1081 1082 void LIR_Op3::emit_code(LIR_Assembler* masm) { 1083 masm->emit_op3(this); 1084 } 1085 1086 void LIR_OpLock::emit_code(LIR_Assembler* masm) { 1087 masm->emit_lock(this); 1088 if (stub()) { 1089 masm->append_code_stub(stub()); 1090 } 1091 } 1092 1093 #ifdef ASSERT 1094 void LIR_OpAssert::emit_code(LIR_Assembler* masm) { 1095 masm->emit_assert(this); 1096 } 1097 #endif 1098 1099 void LIR_OpDelay::emit_code(LIR_Assembler* masm) { 1100 masm->emit_delay(this); 1101 } 1102 1103 void LIR_OpProfileCall::emit_code(LIR_Assembler* masm) { 1104 masm->emit_profile_call(this); 1105 } 1106 1107 void LIR_OpProfileType::emit_code(LIR_Assembler* masm) { 1108 masm->emit_profile_type(this); 1109 } 1110 1111 // LIR_List 1112 LIR_List::LIR_List(Compilation* compilation, BlockBegin* block) 1113 : _operations(8) 1114 , _compilation(compilation) 1115 #ifndef PRODUCT 1116 , _block(block) 1117 #endif 1118 #ifdef ASSERT 1119 , _file(NULL) 1120 , _line(0) 1121 #endif 1122 { } 1123 1124 1125 #ifdef ASSERT 1126 void LIR_List::set_file_and_line(const char * file, int line) { 1127 const char * f = strrchr(file, '/'); 1128 if (f == NULL) f = strrchr(file, '\\'); 1129 if (f == NULL) { 1130 f = file; 1131 } else { 1132 f++; 1133 } 1134 _file = f; 1135 _line = line; 1136 } 1137 #endif 1138 1139 1140 void LIR_List::append(LIR_InsertionBuffer* buffer) { 1141 assert(this == buffer->lir_list(), "wrong lir list"); 1142 const int n = _operations.length(); 1143 1144 if (buffer->number_of_ops() > 0) { 1145 // increase size of instructions list 1146 _operations.at_grow(n + buffer->number_of_ops() - 1, NULL); 1147 // insert ops from buffer into instructions list 1148 int op_index = buffer->number_of_ops() - 1; 1149 int ip_index = buffer->number_of_insertion_points() - 1; 1150 int from_index = n - 1; 1151 int to_index = _operations.length() - 1; 1152 for (; ip_index >= 0; ip_index --) { 1153 int index = buffer->index_at(ip_index); 1154 // make room after insertion point 1155 while (index < from_index) { 1156 _operations.at_put(to_index --, _operations.at(from_index --)); 1157 } 1158 // insert ops from buffer 1159 for (int i = buffer->count_at(ip_index); i > 0; i --) { 1160 _operations.at_put(to_index --, buffer->op_at(op_index --)); 1161 } 1162 } 1163 } 1164 1165 buffer->finish(); 1166 } 1167 1168 1169 void LIR_List::oop2reg_patch(jobject o, LIR_Opr reg, CodeEmitInfo* info) { 1170 assert(reg->type() == T_OBJECT, "bad reg"); 1171 append(new LIR_Op1(lir_move, LIR_OprFact::oopConst(o), reg, T_OBJECT, lir_patch_normal, info)); 1172 } 1173 1174 void LIR_List::klass2reg_patch(Metadata* o, LIR_Opr reg, CodeEmitInfo* info) { 1175 assert(reg->type() == T_METADATA, "bad reg"); 1176 append(new LIR_Op1(lir_move, LIR_OprFact::metadataConst(o), reg, T_METADATA, lir_patch_normal, info)); 1177 } 1178 1179 void LIR_List::load(LIR_Address* addr, LIR_Opr src, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1180 append(new LIR_Op1( 1181 lir_move, 1182 LIR_OprFact::address(addr), 1183 src, 1184 addr->type(), 1185 patch_code, 1186 info)); 1187 } 1188 1189 1190 void LIR_List::volatile_load_mem_reg(LIR_Address* address, LIR_Opr dst, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1191 append(new LIR_Op1( 1192 lir_move, 1193 LIR_OprFact::address(address), 1194 dst, 1195 address->type(), 1196 patch_code, 1197 info, lir_move_volatile)); 1198 } 1199 1200 void LIR_List::volatile_load_unsafe_reg(LIR_Opr base, LIR_Opr offset, LIR_Opr dst, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1201 append(new LIR_Op1( 1202 lir_move, 1203 LIR_OprFact::address(new LIR_Address(base, offset, type)), 1204 dst, 1205 type, 1206 patch_code, 1207 info, lir_move_volatile)); 1208 } 1209 1210 1211 void LIR_List::store_mem_int(jint v, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1212 append(new LIR_Op1( 1213 lir_move, 1214 LIR_OprFact::intConst(v), 1215 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)), 1216 type, 1217 patch_code, 1218 info)); 1219 } 1220 1221 1222 void LIR_List::store_mem_oop(jobject o, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1223 append(new LIR_Op1( 1224 lir_move, 1225 LIR_OprFact::oopConst(o), 1226 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)), 1227 type, 1228 patch_code, 1229 info)); 1230 } 1231 1232 1233 void LIR_List::store(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1234 append(new LIR_Op1( 1235 lir_move, 1236 src, 1237 LIR_OprFact::address(addr), 1238 addr->type(), 1239 patch_code, 1240 info)); 1241 } 1242 1243 1244 void LIR_List::volatile_store_mem_reg(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1245 append(new LIR_Op1( 1246 lir_move, 1247 src, 1248 LIR_OprFact::address(addr), 1249 addr->type(), 1250 patch_code, 1251 info, 1252 lir_move_volatile)); 1253 } 1254 1255 void LIR_List::volatile_store_unsafe_reg(LIR_Opr src, LIR_Opr base, LIR_Opr offset, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1256 append(new LIR_Op1( 1257 lir_move, 1258 src, 1259 LIR_OprFact::address(new LIR_Address(base, offset, type)), 1260 type, 1261 patch_code, 1262 info, lir_move_volatile)); 1263 } 1264 1265 1266 void LIR_List::idiv(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) { 1267 append(new LIR_Op3( 1268 lir_idiv, 1269 left, 1270 right, 1271 tmp, 1272 res, 1273 info)); 1274 } 1275 1276 1277 void LIR_List::idiv(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) { 1278 append(new LIR_Op3( 1279 lir_idiv, 1280 left, 1281 LIR_OprFact::intConst(right), 1282 tmp, 1283 res, 1284 info)); 1285 } 1286 1287 1288 void LIR_List::irem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) { 1289 append(new LIR_Op3( 1290 lir_irem, 1291 left, 1292 right, 1293 tmp, 1294 res, 1295 info)); 1296 } 1297 1298 1299 void LIR_List::irem(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) { 1300 append(new LIR_Op3( 1301 lir_irem, 1302 left, 1303 LIR_OprFact::intConst(right), 1304 tmp, 1305 res, 1306 info)); 1307 } 1308 1309 1310 void LIR_List::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) { 1311 append(new LIR_Op2( 1312 lir_cmp, 1313 condition, 1314 LIR_OprFact::address(new LIR_Address(base, disp, T_INT)), 1315 LIR_OprFact::intConst(c), 1316 info)); 1317 } 1318 1319 1320 void LIR_List::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Address* addr, CodeEmitInfo* info) { 1321 append(new LIR_Op2( 1322 lir_cmp, 1323 condition, 1324 reg, 1325 LIR_OprFact::address(addr), 1326 info)); 1327 } 1328 1329 void LIR_List::allocate_object(LIR_Opr dst, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4, 1330 int header_size, int object_size, LIR_Opr klass, bool init_check, CodeStub* stub) { 1331 append(new LIR_OpAllocObj( 1332 klass, 1333 dst, 1334 t1, 1335 t2, 1336 t3, 1337 t4, 1338 header_size, 1339 object_size, 1340 init_check, 1341 stub)); 1342 } 1343 1344 void LIR_List::allocate_array(LIR_Opr dst, LIR_Opr len, LIR_Opr t1,LIR_Opr t2, LIR_Opr t3,LIR_Opr t4, BasicType type, LIR_Opr klass, CodeStub* stub) { 1345 append(new LIR_OpAllocArray( 1346 klass, 1347 len, 1348 dst, 1349 t1, 1350 t2, 1351 t3, 1352 t4, 1353 type, 1354 stub)); 1355 } 1356 1357 void LIR_List::shift_left(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) { 1358 append(new LIR_Op2( 1359 lir_shl, 1360 value, 1361 count, 1362 dst, 1363 tmp)); 1364 } 1365 1366 void LIR_List::shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) { 1367 append(new LIR_Op2( 1368 lir_shr, 1369 value, 1370 count, 1371 dst, 1372 tmp)); 1373 } 1374 1375 1376 void LIR_List::unsigned_shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) { 1377 append(new LIR_Op2( 1378 lir_ushr, 1379 value, 1380 count, 1381 dst, 1382 tmp)); 1383 } 1384 1385 void LIR_List::fcmp2int(LIR_Opr left, LIR_Opr right, LIR_Opr dst, bool is_unordered_less) { 1386 append(new LIR_Op2(is_unordered_less ? lir_ucmp_fd2i : lir_cmp_fd2i, 1387 left, 1388 right, 1389 dst)); 1390 } 1391 1392 void LIR_List::lock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub, CodeEmitInfo* info) { 1393 append(new LIR_OpLock( 1394 lir_lock, 1395 hdr, 1396 obj, 1397 lock, 1398 scratch, 1399 stub, 1400 info)); 1401 } 1402 1403 void LIR_List::unlock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub) { 1404 append(new LIR_OpLock( 1405 lir_unlock, 1406 hdr, 1407 obj, 1408 lock, 1409 scratch, 1410 stub, 1411 NULL)); 1412 } 1413 1414 1415 void check_LIR() { 1416 // cannot do the proper checking as PRODUCT and other modes return different results 1417 // guarantee(sizeof(LIR_OprDesc) == wordSize, "may not have a v-table"); 1418 } 1419 1420 1421 1422 void LIR_List::checkcast (LIR_Opr result, LIR_Opr object, ciKlass* klass, 1423 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check, 1424 CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch, CodeStub* stub, 1425 ciMethod* profiled_method, int profiled_bci) { 1426 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_checkcast, result, object, klass, 1427 tmp1, tmp2, tmp3, fast_check, info_for_exception, info_for_patch, stub); 1428 if (profiled_method != NULL) { 1429 c->set_profiled_method(profiled_method); 1430 c->set_profiled_bci(profiled_bci); 1431 c->set_should_profile(true); 1432 } 1433 append(c); 1434 } 1435 1436 void LIR_List::instanceof(LIR_Opr result, LIR_Opr object, ciKlass* klass, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check, CodeEmitInfo* info_for_patch, ciMethod* profiled_method, int profiled_bci) { 1437 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_instanceof, result, object, klass, tmp1, tmp2, tmp3, fast_check, NULL, info_for_patch, NULL); 1438 if (profiled_method != NULL) { 1439 c->set_profiled_method(profiled_method); 1440 c->set_profiled_bci(profiled_bci); 1441 c->set_should_profile(true); 1442 } 1443 append(c); 1444 } 1445 1446 1447 void LIR_List::store_check(LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, 1448 CodeEmitInfo* info_for_exception, ciMethod* profiled_method, int profiled_bci) { 1449 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_store_check, object, array, tmp1, tmp2, tmp3, info_for_exception); 1450 if (profiled_method != NULL) { 1451 c->set_profiled_method(profiled_method); 1452 c->set_profiled_bci(profiled_bci); 1453 c->set_should_profile(true); 1454 } 1455 append(c); 1456 } 1457 1458 1459 void LIR_List::cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, 1460 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) { 1461 append(new LIR_OpCompareAndSwap(lir_cas_long, addr, cmp_value, new_value, t1, t2, result)); 1462 } 1463 1464 void LIR_List::cas_obj(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, 1465 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) { 1466 append(new LIR_OpCompareAndSwap(lir_cas_obj, addr, cmp_value, new_value, t1, t2, result)); 1467 } 1468 1469 void LIR_List::cas_int(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, 1470 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) { 1471 append(new LIR_OpCompareAndSwap(lir_cas_int, addr, cmp_value, new_value, t1, t2, result)); 1472 } 1473 1474 1475 #ifdef PRODUCT 1476 1477 void print_LIR(BlockList* blocks) { 1478 } 1479 1480 #else 1481 // LIR_OprDesc 1482 void LIR_OprDesc::print() const { 1483 print(tty); 1484 } 1485 1486 void LIR_OprDesc::print(outputStream* out) const { 1487 if (is_illegal()) { 1488 return; 1489 } 1490 1491 out->print("["); 1492 if (is_pointer()) { 1493 pointer()->print_value_on(out); 1494 } else if (is_single_stack()) { 1495 out->print("stack:%d", single_stack_ix()); 1496 } else if (is_double_stack()) { 1497 out->print("dbl_stack:%d",double_stack_ix()); 1498 } else if (is_virtual()) { 1499 out->print("R%d", vreg_number()); 1500 } else if (is_single_cpu()) { 1501 out->print("%s", as_register()->name()); 1502 } else if (is_double_cpu()) { 1503 out->print("%s", as_register_hi()->name()); 1504 out->print("%s", as_register_lo()->name()); 1505 #if defined(X86) 1506 } else if (is_single_xmm()) { 1507 out->print("%s", as_xmm_float_reg()->name()); 1508 } else if (is_double_xmm()) { 1509 out->print("%s", as_xmm_double_reg()->name()); 1510 } else if (is_single_fpu()) { 1511 out->print("fpu%d", fpu_regnr()); 1512 } else if (is_double_fpu()) { 1513 out->print("fpu%d", fpu_regnrLo()); 1514 #elif defined(AARCH64) 1515 } else if (is_single_fpu()) { 1516 out->print("fpu%d", fpu_regnr()); 1517 } else if (is_double_fpu()) { 1518 out->print("fpu%d", fpu_regnrLo()); 1519 #elif defined(ARM) 1520 } else if (is_single_fpu()) { 1521 out->print("s%d", fpu_regnr()); 1522 } else if (is_double_fpu()) { 1523 out->print("d%d", fpu_regnrLo() >> 1); 1524 #else 1525 } else if (is_single_fpu()) { 1526 out->print("%s", as_float_reg()->name()); 1527 } else if (is_double_fpu()) { 1528 out->print("%s", as_double_reg()->name()); 1529 #endif 1530 1531 } else if (is_illegal()) { 1532 out->print("-"); 1533 } else { 1534 out->print("Unknown Operand"); 1535 } 1536 if (!is_illegal()) { 1537 out->print("|%c", type_char()); 1538 } 1539 if (is_register() && is_last_use()) { 1540 out->print("(last_use)"); 1541 } 1542 out->print("]"); 1543 } 1544 1545 1546 // LIR_Address 1547 void LIR_Const::print_value_on(outputStream* out) const { 1548 switch (type()) { 1549 case T_ADDRESS:out->print("address:%d",as_jint()); break; 1550 case T_INT: out->print("int:%d", as_jint()); break; 1551 case T_LONG: out->print("lng:" JLONG_FORMAT, as_jlong()); break; 1552 case T_FLOAT: out->print("flt:%f", as_jfloat()); break; 1553 case T_DOUBLE: out->print("dbl:%f", as_jdouble()); break; 1554 case T_OBJECT: out->print("obj:" INTPTR_FORMAT, p2i(as_jobject())); break; 1555 case T_METADATA: out->print("metadata:" INTPTR_FORMAT, p2i(as_metadata()));break; 1556 default: out->print("%3d:0x" UINT64_FORMAT_X, type(), (uint64_t)as_jlong()); break; 1557 } 1558 } 1559 1560 // LIR_Address 1561 void LIR_Address::print_value_on(outputStream* out) const { 1562 out->print("Base:"); _base->print(out); 1563 if (!_index->is_illegal()) { 1564 out->print(" Index:"); _index->print(out); 1565 switch (scale()) { 1566 case times_1: break; 1567 case times_2: out->print(" * 2"); break; 1568 case times_4: out->print(" * 4"); break; 1569 case times_8: out->print(" * 8"); break; 1570 } 1571 } 1572 out->print(" Disp: " INTX_FORMAT, _disp); 1573 } 1574 1575 // debug output of block header without InstructionPrinter 1576 // (because phi functions are not necessary for LIR) 1577 static void print_block(BlockBegin* x) { 1578 // print block id 1579 BlockEnd* end = x->end(); 1580 tty->print("B%d ", x->block_id()); 1581 1582 // print flags 1583 if (x->is_set(BlockBegin::std_entry_flag)) tty->print("std "); 1584 if (x->is_set(BlockBegin::osr_entry_flag)) tty->print("osr "); 1585 if (x->is_set(BlockBegin::exception_entry_flag)) tty->print("ex "); 1586 if (x->is_set(BlockBegin::subroutine_entry_flag)) tty->print("jsr "); 1587 if (x->is_set(BlockBegin::backward_branch_target_flag)) tty->print("bb "); 1588 if (x->is_set(BlockBegin::linear_scan_loop_header_flag)) tty->print("lh "); 1589 if (x->is_set(BlockBegin::linear_scan_loop_end_flag)) tty->print("le "); 1590 1591 // print block bci range 1592 tty->print("[%d, %d] ", x->bci(), (end == NULL ? -1 : end->printable_bci())); 1593 1594 // print predecessors and successors 1595 if (x->number_of_preds() > 0) { 1596 tty->print("preds: "); 1597 for (int i = 0; i < x->number_of_preds(); i ++) { 1598 tty->print("B%d ", x->pred_at(i)->block_id()); 1599 } 1600 } 1601 1602 if (x->number_of_sux() > 0) { 1603 tty->print("sux: "); 1604 for (int i = 0; i < x->number_of_sux(); i ++) { 1605 tty->print("B%d ", x->sux_at(i)->block_id()); 1606 } 1607 } 1608 1609 // print exception handlers 1610 if (x->number_of_exception_handlers() > 0) { 1611 tty->print("xhandler: "); 1612 for (int i = 0; i < x->number_of_exception_handlers(); i++) { 1613 tty->print("B%d ", x->exception_handler_at(i)->block_id()); 1614 } 1615 } 1616 1617 tty->cr(); 1618 } 1619 1620 void print_LIR(BlockList* blocks) { 1621 tty->print_cr("LIR:"); 1622 int i; 1623 for (i = 0; i < blocks->length(); i++) { 1624 BlockBegin* bb = blocks->at(i); 1625 print_block(bb); 1626 tty->print("__id_Instruction___________________________________________"); tty->cr(); 1627 bb->lir()->print_instructions(); 1628 } 1629 } 1630 1631 void LIR_List::print_instructions() { 1632 for (int i = 0; i < _operations.length(); i++) { 1633 _operations.at(i)->print(); tty->cr(); 1634 } 1635 tty->cr(); 1636 } 1637 1638 // LIR_Ops printing routines 1639 // LIR_Op 1640 void LIR_Op::print_on(outputStream* out) const { 1641 if (id() != -1 || PrintCFGToFile) { 1642 out->print("%4d ", id()); 1643 } else { 1644 out->print(" "); 1645 } 1646 out->print("%s ", name()); 1647 print_instr(out); 1648 if (info() != NULL) out->print(" [bci:%d]", info()->stack()->bci()); 1649 #ifdef ASSERT 1650 if (Verbose && _file != NULL) { 1651 out->print(" (%s:%d)", _file, _line); 1652 } 1653 #endif 1654 } 1655 1656 const char * LIR_Op::name() const { 1657 const char* s = NULL; 1658 switch(code()) { 1659 // LIR_Op0 1660 case lir_membar: s = "membar"; break; 1661 case lir_membar_acquire: s = "membar_acquire"; break; 1662 case lir_membar_release: s = "membar_release"; break; 1663 case lir_membar_loadload: s = "membar_loadload"; break; 1664 case lir_membar_storestore: s = "membar_storestore"; break; 1665 case lir_membar_loadstore: s = "membar_loadstore"; break; 1666 case lir_membar_storeload: s = "membar_storeload"; break; 1667 case lir_word_align: s = "word_align"; break; 1668 case lir_label: s = "label"; break; 1669 case lir_nop: s = "nop"; break; 1670 case lir_on_spin_wait: s = "on_spin_wait"; break; 1671 case lir_backwardbranch_target: s = "backbranch"; break; 1672 case lir_std_entry: s = "std_entry"; break; 1673 case lir_osr_entry: s = "osr_entry"; break; 1674 case lir_build_frame: s = "build_frm"; break; 1675 case lir_fpop_raw: s = "fpop_raw"; break; 1676 case lir_24bit_FPU: s = "24bit_FPU"; break; 1677 case lir_reset_FPU: s = "reset_FPU"; break; 1678 case lir_breakpoint: s = "breakpoint"; break; 1679 case lir_get_thread: s = "get_thread"; break; 1680 // LIR_Op1 1681 case lir_fxch: s = "fxch"; break; 1682 case lir_fld: s = "fld"; break; 1683 case lir_ffree: s = "ffree"; break; 1684 case lir_push: s = "push"; break; 1685 case lir_pop: s = "pop"; break; 1686 case lir_null_check: s = "null_check"; break; 1687 case lir_return: s = "return"; break; 1688 case lir_safepoint: s = "safepoint"; break; 1689 case lir_neg: s = "neg"; break; 1690 case lir_leal: s = "leal"; break; 1691 case lir_branch: s = "branch"; break; 1692 case lir_cond_float_branch: s = "flt_cond_br"; break; 1693 case lir_move: s = "move"; break; 1694 case lir_roundfp: s = "roundfp"; break; 1695 case lir_rtcall: s = "rtcall"; break; 1696 case lir_throw: s = "throw"; break; 1697 case lir_unwind: s = "unwind"; break; 1698 case lir_convert: s = "convert"; break; 1699 case lir_alloc_object: s = "alloc_obj"; break; 1700 case lir_monaddr: s = "mon_addr"; break; 1701 case lir_pack64: s = "pack64"; break; 1702 case lir_unpack64: s = "unpack64"; break; 1703 // LIR_Op2 1704 case lir_cmp: s = "cmp"; break; 1705 case lir_cmp_l2i: s = "cmp_l2i"; break; 1706 case lir_ucmp_fd2i: s = "ucomp_fd2i"; break; 1707 case lir_cmp_fd2i: s = "comp_fd2i"; break; 1708 case lir_cmove: s = "cmove"; break; 1709 case lir_add: s = "add"; break; 1710 case lir_sub: s = "sub"; break; 1711 case lir_mul: s = "mul"; break; 1712 case lir_mul_strictfp: s = "mul_strictfp"; break; 1713 case lir_div: s = "div"; break; 1714 case lir_div_strictfp: s = "div_strictfp"; break; 1715 case lir_rem: s = "rem"; break; 1716 case lir_abs: s = "abs"; break; 1717 case lir_sqrt: s = "sqrt"; break; 1718 case lir_logic_and: s = "logic_and"; break; 1719 case lir_logic_or: s = "logic_or"; break; 1720 case lir_logic_xor: s = "logic_xor"; break; 1721 case lir_shl: s = "shift_left"; break; 1722 case lir_shr: s = "shift_right"; break; 1723 case lir_ushr: s = "ushift_right"; break; 1724 case lir_alloc_array: s = "alloc_array"; break; 1725 case lir_xadd: s = "xadd"; break; 1726 case lir_xchg: s = "xchg"; break; 1727 // LIR_Op3 1728 case lir_idiv: s = "idiv"; break; 1729 case lir_irem: s = "irem"; break; 1730 // LIR_OpJavaCall 1731 case lir_static_call: s = "static"; break; 1732 case lir_optvirtual_call: s = "optvirtual"; break; 1733 case lir_icvirtual_call: s = "icvirtual"; break; 1734 case lir_virtual_call: s = "virtual"; break; 1735 case lir_dynamic_call: s = "dynamic"; break; 1736 // LIR_OpArrayCopy 1737 case lir_arraycopy: s = "arraycopy"; break; 1738 // LIR_OpUpdateCRC32 1739 case lir_updatecrc32: s = "updatecrc32"; break; 1740 // LIR_OpLock 1741 case lir_lock: s = "lock"; break; 1742 case lir_unlock: s = "unlock"; break; 1743 // LIR_OpDelay 1744 case lir_delay_slot: s = "delay"; break; 1745 // LIR_OpTypeCheck 1746 case lir_instanceof: s = "instanceof"; break; 1747 case lir_checkcast: s = "checkcast"; break; 1748 case lir_store_check: s = "store_check"; break; 1749 // LIR_OpCompareAndSwap 1750 case lir_cas_long: s = "cas_long"; break; 1751 case lir_cas_obj: s = "cas_obj"; break; 1752 case lir_cas_int: s = "cas_int"; break; 1753 // LIR_OpProfileCall 1754 case lir_profile_call: s = "profile_call"; break; 1755 // LIR_OpProfileType 1756 case lir_profile_type: s = "profile_type"; break; 1757 // LIR_OpAssert 1758 #ifdef ASSERT 1759 case lir_assert: s = "assert"; break; 1760 #endif 1761 case lir_none: ShouldNotReachHere();break; 1762 default: s = "illegal_op"; break; 1763 } 1764 return s; 1765 } 1766 1767 // LIR_OpJavaCall 1768 void LIR_OpJavaCall::print_instr(outputStream* out) const { 1769 out->print("call: "); 1770 out->print("[addr: " INTPTR_FORMAT "]", p2i(address())); 1771 if (receiver()->is_valid()) { 1772 out->print(" [recv: "); receiver()->print(out); out->print("]"); 1773 } 1774 if (result_opr()->is_valid()) { 1775 out->print(" [result: "); result_opr()->print(out); out->print("]"); 1776 } 1777 } 1778 1779 // LIR_OpLabel 1780 void LIR_OpLabel::print_instr(outputStream* out) const { 1781 out->print("[label:" INTPTR_FORMAT "]", p2i(_label)); 1782 } 1783 1784 // LIR_OpArrayCopy 1785 void LIR_OpArrayCopy::print_instr(outputStream* out) const { 1786 src()->print(out); out->print(" "); 1787 src_pos()->print(out); out->print(" "); 1788 dst()->print(out); out->print(" "); 1789 dst_pos()->print(out); out->print(" "); 1790 length()->print(out); out->print(" "); 1791 tmp()->print(out); out->print(" "); 1792 } 1793 1794 // LIR_OpUpdateCRC32 1795 void LIR_OpUpdateCRC32::print_instr(outputStream* out) const { 1796 crc()->print(out); out->print(" "); 1797 val()->print(out); out->print(" "); 1798 result_opr()->print(out); out->print(" "); 1799 } 1800 1801 // LIR_OpCompareAndSwap 1802 void LIR_OpCompareAndSwap::print_instr(outputStream* out) const { 1803 addr()->print(out); out->print(" "); 1804 cmp_value()->print(out); out->print(" "); 1805 new_value()->print(out); out->print(" "); 1806 tmp1()->print(out); out->print(" "); 1807 tmp2()->print(out); out->print(" "); 1808 1809 } 1810 1811 // LIR_Op0 1812 void LIR_Op0::print_instr(outputStream* out) const { 1813 result_opr()->print(out); 1814 } 1815 1816 // LIR_Op1 1817 const char * LIR_Op1::name() const { 1818 if (code() == lir_move) { 1819 switch (move_kind()) { 1820 case lir_move_normal: 1821 return "move"; 1822 case lir_move_unaligned: 1823 return "unaligned move"; 1824 case lir_move_volatile: 1825 return "volatile_move"; 1826 case lir_move_wide: 1827 return "wide_move"; 1828 default: 1829 ShouldNotReachHere(); 1830 return "illegal_op"; 1831 } 1832 } else { 1833 return LIR_Op::name(); 1834 } 1835 } 1836 1837 1838 void LIR_Op1::print_instr(outputStream* out) const { 1839 _opr->print(out); out->print(" "); 1840 result_opr()->print(out); out->print(" "); 1841 print_patch_code(out, patch_code()); 1842 } 1843 1844 1845 // LIR_Op1 1846 void LIR_OpRTCall::print_instr(outputStream* out) const { 1847 intx a = (intx)addr(); 1848 out->print("%s", Runtime1::name_for_address(addr())); 1849 out->print(" "); 1850 tmp()->print(out); 1851 } 1852 1853 void LIR_Op1::print_patch_code(outputStream* out, LIR_PatchCode code) { 1854 switch(code) { 1855 case lir_patch_none: break; 1856 case lir_patch_low: out->print("[patch_low]"); break; 1857 case lir_patch_high: out->print("[patch_high]"); break; 1858 case lir_patch_normal: out->print("[patch_normal]"); break; 1859 default: ShouldNotReachHere(); 1860 } 1861 } 1862 1863 // LIR_OpBranch 1864 void LIR_OpBranch::print_instr(outputStream* out) const { 1865 print_condition(out, cond()); out->print(" "); 1866 if (block() != NULL) { 1867 out->print("[B%d] ", block()->block_id()); 1868 } else if (stub() != NULL) { 1869 out->print("["); 1870 stub()->print_name(out); 1871 out->print(": " INTPTR_FORMAT "]", p2i(stub())); 1872 if (stub()->info() != NULL) out->print(" [bci:%d]", stub()->info()->stack()->bci()); 1873 } else { 1874 out->print("[label:" INTPTR_FORMAT "] ", p2i(label())); 1875 } 1876 if (ublock() != NULL) { 1877 out->print("unordered: [B%d] ", ublock()->block_id()); 1878 } 1879 } 1880 1881 void LIR_Op::print_condition(outputStream* out, LIR_Condition cond) { 1882 switch(cond) { 1883 case lir_cond_equal: out->print("[EQ]"); break; 1884 case lir_cond_notEqual: out->print("[NE]"); break; 1885 case lir_cond_less: out->print("[LT]"); break; 1886 case lir_cond_lessEqual: out->print("[LE]"); break; 1887 case lir_cond_greaterEqual: out->print("[GE]"); break; 1888 case lir_cond_greater: out->print("[GT]"); break; 1889 case lir_cond_belowEqual: out->print("[BE]"); break; 1890 case lir_cond_aboveEqual: out->print("[AE]"); break; 1891 case lir_cond_always: out->print("[AL]"); break; 1892 default: out->print("[%d]",cond); break; 1893 } 1894 } 1895 1896 // LIR_OpConvert 1897 void LIR_OpConvert::print_instr(outputStream* out) const { 1898 print_bytecode(out, bytecode()); 1899 in_opr()->print(out); out->print(" "); 1900 result_opr()->print(out); out->print(" "); 1901 #ifdef PPC32 1902 if(tmp1()->is_valid()) { 1903 tmp1()->print(out); out->print(" "); 1904 tmp2()->print(out); out->print(" "); 1905 } 1906 #endif 1907 } 1908 1909 void LIR_OpConvert::print_bytecode(outputStream* out, Bytecodes::Code code) { 1910 switch(code) { 1911 case Bytecodes::_d2f: out->print("[d2f] "); break; 1912 case Bytecodes::_d2i: out->print("[d2i] "); break; 1913 case Bytecodes::_d2l: out->print("[d2l] "); break; 1914 case Bytecodes::_f2d: out->print("[f2d] "); break; 1915 case Bytecodes::_f2i: out->print("[f2i] "); break; 1916 case Bytecodes::_f2l: out->print("[f2l] "); break; 1917 case Bytecodes::_i2b: out->print("[i2b] "); break; 1918 case Bytecodes::_i2c: out->print("[i2c] "); break; 1919 case Bytecodes::_i2d: out->print("[i2d] "); break; 1920 case Bytecodes::_i2f: out->print("[i2f] "); break; 1921 case Bytecodes::_i2l: out->print("[i2l] "); break; 1922 case Bytecodes::_i2s: out->print("[i2s] "); break; 1923 case Bytecodes::_l2i: out->print("[l2i] "); break; 1924 case Bytecodes::_l2f: out->print("[l2f] "); break; 1925 case Bytecodes::_l2d: out->print("[l2d] "); break; 1926 default: 1927 out->print("[?%d]",code); 1928 break; 1929 } 1930 } 1931 1932 void LIR_OpAllocObj::print_instr(outputStream* out) const { 1933 klass()->print(out); out->print(" "); 1934 obj()->print(out); out->print(" "); 1935 tmp1()->print(out); out->print(" "); 1936 tmp2()->print(out); out->print(" "); 1937 tmp3()->print(out); out->print(" "); 1938 tmp4()->print(out); out->print(" "); 1939 out->print("[hdr:%d]", header_size()); out->print(" "); 1940 out->print("[obj:%d]", object_size()); out->print(" "); 1941 out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry())); 1942 } 1943 1944 void LIR_OpRoundFP::print_instr(outputStream* out) const { 1945 _opr->print(out); out->print(" "); 1946 tmp()->print(out); out->print(" "); 1947 result_opr()->print(out); out->print(" "); 1948 } 1949 1950 // LIR_Op2 1951 void LIR_Op2::print_instr(outputStream* out) const { 1952 if (code() == lir_cmove || code() == lir_cmp) { 1953 print_condition(out, condition()); out->print(" "); 1954 } 1955 in_opr1()->print(out); out->print(" "); 1956 in_opr2()->print(out); out->print(" "); 1957 if (tmp1_opr()->is_valid()) { tmp1_opr()->print(out); out->print(" "); } 1958 if (tmp2_opr()->is_valid()) { tmp2_opr()->print(out); out->print(" "); } 1959 if (tmp3_opr()->is_valid()) { tmp3_opr()->print(out); out->print(" "); } 1960 if (tmp4_opr()->is_valid()) { tmp4_opr()->print(out); out->print(" "); } 1961 if (tmp5_opr()->is_valid()) { tmp5_opr()->print(out); out->print(" "); } 1962 result_opr()->print(out); 1963 } 1964 1965 void LIR_OpAllocArray::print_instr(outputStream* out) const { 1966 klass()->print(out); out->print(" "); 1967 len()->print(out); out->print(" "); 1968 obj()->print(out); out->print(" "); 1969 tmp1()->print(out); out->print(" "); 1970 tmp2()->print(out); out->print(" "); 1971 tmp3()->print(out); out->print(" "); 1972 tmp4()->print(out); out->print(" "); 1973 out->print("[type:0x%x]", type()); out->print(" "); 1974 out->print("[label:" INTPTR_FORMAT "]", p2i(stub()->entry())); 1975 } 1976 1977 1978 void LIR_OpTypeCheck::print_instr(outputStream* out) const { 1979 object()->print(out); out->print(" "); 1980 if (code() == lir_store_check) { 1981 array()->print(out); out->print(" "); 1982 } 1983 if (code() != lir_store_check) { 1984 klass()->print_name_on(out); out->print(" "); 1985 if (fast_check()) out->print("fast_check "); 1986 } 1987 tmp1()->print(out); out->print(" "); 1988 tmp2()->print(out); out->print(" "); 1989 tmp3()->print(out); out->print(" "); 1990 result_opr()->print(out); out->print(" "); 1991 if (info_for_exception() != NULL) out->print(" [bci:%d]", info_for_exception()->stack()->bci()); 1992 } 1993 1994 1995 // LIR_Op3 1996 void LIR_Op3::print_instr(outputStream* out) const { 1997 in_opr1()->print(out); out->print(" "); 1998 in_opr2()->print(out); out->print(" "); 1999 in_opr3()->print(out); out->print(" "); 2000 result_opr()->print(out); 2001 } 2002 2003 2004 void LIR_OpLock::print_instr(outputStream* out) const { 2005 hdr_opr()->print(out); out->print(" "); 2006 obj_opr()->print(out); out->print(" "); 2007 lock_opr()->print(out); out->print(" "); 2008 if (_scratch->is_valid()) { 2009 _scratch->print(out); out->print(" "); 2010 } 2011 out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry())); 2012 } 2013 2014 #ifdef ASSERT 2015 void LIR_OpAssert::print_instr(outputStream* out) const { 2016 print_condition(out, condition()); out->print(" "); 2017 in_opr1()->print(out); out->print(" "); 2018 in_opr2()->print(out); out->print(", \""); 2019 out->print("%s", msg()); out->print("\""); 2020 } 2021 #endif 2022 2023 2024 void LIR_OpDelay::print_instr(outputStream* out) const { 2025 _op->print_on(out); 2026 } 2027 2028 2029 // LIR_OpProfileCall 2030 void LIR_OpProfileCall::print_instr(outputStream* out) const { 2031 profiled_method()->name()->print_symbol_on(out); 2032 out->print("."); 2033 profiled_method()->holder()->name()->print_symbol_on(out); 2034 out->print(" @ %d ", profiled_bci()); 2035 mdo()->print(out); out->print(" "); 2036 recv()->print(out); out->print(" "); 2037 tmp1()->print(out); out->print(" "); 2038 } 2039 2040 // LIR_OpProfileType 2041 void LIR_OpProfileType::print_instr(outputStream* out) const { 2042 out->print("exact = "); 2043 if (exact_klass() == NULL) { 2044 out->print("unknown"); 2045 } else { 2046 exact_klass()->print_name_on(out); 2047 } 2048 out->print(" current = "); ciTypeEntries::print_ciklass(out, current_klass()); 2049 out->print(" "); 2050 mdp()->print(out); out->print(" "); 2051 obj()->print(out); out->print(" "); 2052 tmp()->print(out); out->print(" "); 2053 } 2054 2055 #endif // PRODUCT 2056 2057 // Implementation of LIR_InsertionBuffer 2058 2059 void LIR_InsertionBuffer::append(int index, LIR_Op* op) { 2060 assert(_index_and_count.length() % 2 == 0, "must have a count for each index"); 2061 2062 int i = number_of_insertion_points() - 1; 2063 if (i < 0 || index_at(i) < index) { 2064 append_new(index, 1); 2065 } else { 2066 assert(index_at(i) == index, "can append LIR_Ops in ascending order only"); 2067 assert(count_at(i) > 0, "check"); 2068 set_count_at(i, count_at(i) + 1); 2069 } 2070 _ops.push(op); 2071 2072 DEBUG_ONLY(verify()); 2073 } 2074 2075 #ifdef ASSERT 2076 void LIR_InsertionBuffer::verify() { 2077 int sum = 0; 2078 int prev_idx = -1; 2079 2080 for (int i = 0; i < number_of_insertion_points(); i++) { 2081 assert(prev_idx < index_at(i), "index must be ordered ascending"); 2082 sum += count_at(i); 2083 } 2084 assert(sum == number_of_ops(), "wrong total sum"); 2085 } 2086 #endif