713 assert(op2->_result->is_illegal(), "no result");
714 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
715 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
716
717 break;
718 }
719
720 case lir_unwind: {
721 assert(op->as_Op1() != NULL, "must be");
722 LIR_Op1* op1 = (LIR_Op1*)op;
723
724 assert(op1->_info == NULL, "no info");
725 assert(op1->_opr->is_valid(), "exception oop"); do_input(op1->_opr);
726 assert(op1->_result->is_illegal(), "no result");
727
728 break;
729 }
730
731 // LIR_Op3
732 case lir_idiv:
733 case lir_irem: {
734 assert(op->as_Op3() != NULL, "must be");
735 LIR_Op3* op3= (LIR_Op3*)op;
736
737 if (op3->_info) do_info(op3->_info);
738 if (op3->_opr1->is_valid()) do_input(op3->_opr1);
739
740 // second operand is input and temp, so ensure that second operand
741 // and third operand get not the same register
742 if (op3->_opr2->is_valid()) do_input(op3->_opr2);
743 if (op3->_opr2->is_valid()) do_temp(op3->_opr2);
744 if (op3->_opr3->is_valid()) do_temp(op3->_opr3);
745
746 if (op3->_result->is_valid()) do_output(op3->_result);
747
748 break;
749 }
750
751
752 // LIR_OpJavaCall
753 case lir_static_call:
1710 case lir_sub: s = "sub"; break;
1711 case lir_mul: s = "mul"; break;
1712 case lir_mul_strictfp: s = "mul_strictfp"; break;
1713 case lir_div: s = "div"; break;
1714 case lir_div_strictfp: s = "div_strictfp"; break;
1715 case lir_rem: s = "rem"; break;
1716 case lir_abs: s = "abs"; break;
1717 case lir_sqrt: s = "sqrt"; break;
1718 case lir_logic_and: s = "logic_and"; break;
1719 case lir_logic_or: s = "logic_or"; break;
1720 case lir_logic_xor: s = "logic_xor"; break;
1721 case lir_shl: s = "shift_left"; break;
1722 case lir_shr: s = "shift_right"; break;
1723 case lir_ushr: s = "ushift_right"; break;
1724 case lir_alloc_array: s = "alloc_array"; break;
1725 case lir_xadd: s = "xadd"; break;
1726 case lir_xchg: s = "xchg"; break;
1727 // LIR_Op3
1728 case lir_idiv: s = "idiv"; break;
1729 case lir_irem: s = "irem"; break;
1730 // LIR_OpJavaCall
1731 case lir_static_call: s = "static"; break;
1732 case lir_optvirtual_call: s = "optvirtual"; break;
1733 case lir_icvirtual_call: s = "icvirtual"; break;
1734 case lir_virtual_call: s = "virtual"; break;
1735 case lir_dynamic_call: s = "dynamic"; break;
1736 // LIR_OpArrayCopy
1737 case lir_arraycopy: s = "arraycopy"; break;
1738 // LIR_OpUpdateCRC32
1739 case lir_updatecrc32: s = "updatecrc32"; break;
1740 // LIR_OpLock
1741 case lir_lock: s = "lock"; break;
1742 case lir_unlock: s = "unlock"; break;
1743 // LIR_OpDelay
1744 case lir_delay_slot: s = "delay"; break;
1745 // LIR_OpTypeCheck
1746 case lir_instanceof: s = "instanceof"; break;
1747 case lir_checkcast: s = "checkcast"; break;
1748 case lir_store_check: s = "store_check"; break;
1749 // LIR_OpCompareAndSwap
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713 assert(op2->_result->is_illegal(), "no result");
714 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
715 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
716
717 break;
718 }
719
720 case lir_unwind: {
721 assert(op->as_Op1() != NULL, "must be");
722 LIR_Op1* op1 = (LIR_Op1*)op;
723
724 assert(op1->_info == NULL, "no info");
725 assert(op1->_opr->is_valid(), "exception oop"); do_input(op1->_opr);
726 assert(op1->_result->is_illegal(), "no result");
727
728 break;
729 }
730
731 // LIR_Op3
732 case lir_idiv:
733 case lir_irem:
734 case lir_fmad:
735 case lir_fmaf: {
736 assert(op->as_Op3() != NULL, "must be");
737 LIR_Op3* op3= (LIR_Op3*)op;
738
739 if (op3->_info) do_info(op3->_info);
740 if (op3->_opr1->is_valid()) do_input(op3->_opr1);
741
742 // second operand is input and temp, so ensure that second operand
743 // and third operand get not the same register
744 if (op3->_opr2->is_valid()) do_input(op3->_opr2);
745 if (op3->_opr2->is_valid()) do_temp(op3->_opr2);
746 if (op3->_opr3->is_valid()) do_temp(op3->_opr3);
747
748 if (op3->_result->is_valid()) do_output(op3->_result);
749
750 break;
751 }
752
753
754 // LIR_OpJavaCall
755 case lir_static_call:
1712 case lir_sub: s = "sub"; break;
1713 case lir_mul: s = "mul"; break;
1714 case lir_mul_strictfp: s = "mul_strictfp"; break;
1715 case lir_div: s = "div"; break;
1716 case lir_div_strictfp: s = "div_strictfp"; break;
1717 case lir_rem: s = "rem"; break;
1718 case lir_abs: s = "abs"; break;
1719 case lir_sqrt: s = "sqrt"; break;
1720 case lir_logic_and: s = "logic_and"; break;
1721 case lir_logic_or: s = "logic_or"; break;
1722 case lir_logic_xor: s = "logic_xor"; break;
1723 case lir_shl: s = "shift_left"; break;
1724 case lir_shr: s = "shift_right"; break;
1725 case lir_ushr: s = "ushift_right"; break;
1726 case lir_alloc_array: s = "alloc_array"; break;
1727 case lir_xadd: s = "xadd"; break;
1728 case lir_xchg: s = "xchg"; break;
1729 // LIR_Op3
1730 case lir_idiv: s = "idiv"; break;
1731 case lir_irem: s = "irem"; break;
1732 case lir_fmad: s = "fmad"; break;
1733 case lir_fmaf: s = "fmaf"; break;
1734 // LIR_OpJavaCall
1735 case lir_static_call: s = "static"; break;
1736 case lir_optvirtual_call: s = "optvirtual"; break;
1737 case lir_icvirtual_call: s = "icvirtual"; break;
1738 case lir_virtual_call: s = "virtual"; break;
1739 case lir_dynamic_call: s = "dynamic"; break;
1740 // LIR_OpArrayCopy
1741 case lir_arraycopy: s = "arraycopy"; break;
1742 // LIR_OpUpdateCRC32
1743 case lir_updatecrc32: s = "updatecrc32"; break;
1744 // LIR_OpLock
1745 case lir_lock: s = "lock"; break;
1746 case lir_unlock: s = "unlock"; break;
1747 // LIR_OpDelay
1748 case lir_delay_slot: s = "delay"; break;
1749 // LIR_OpTypeCheck
1750 case lir_instanceof: s = "instanceof"; break;
1751 case lir_checkcast: s = "checkcast"; break;
1752 case lir_store_check: s = "store_check"; break;
1753 // LIR_OpCompareAndSwap
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