760
761 case 0x70: // pshufd r, r/a, #8
762 debug_only(has_disp32 = true); // has both kinds of operands!
763 case 0x73: // psrldq r, #8
764 tail_size = 1;
765 break;
766
767 case 0x12: // movlps
768 case 0x28: // movaps
769 case 0x2E: // ucomiss
770 case 0x2F: // comiss
771 case 0x54: // andps
772 case 0x55: // andnps
773 case 0x56: // orps
774 case 0x57: // xorps
775 case 0x58: // addpd
776 case 0x59: // mulpd
777 case 0x6E: // movd
778 case 0x7E: // movd
779 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush
780 debug_only(has_disp32 = true);
781 break;
782
783 case 0xAD: // shrd r, a, %cl
784 case 0xAF: // imul r, a
785 case 0xBE: // movsbl r, a (movsxb)
786 case 0xBF: // movswl r, a (movsxw)
787 case 0xB6: // movzbl r, a (movzxb)
788 case 0xB7: // movzwl r, a (movzxw)
789 case REP16(0x40): // cmovl cc, r, a
790 case 0xB0: // cmpxchgb
791 case 0xB1: // cmpxchg
792 case 0xC1: // xaddl
793 case 0xC7: // cmpxchg8
794 case REP16(0x90): // setcc a
795 debug_only(has_disp32 = true);
796 // fall out of the switch to decode the address
797 break;
798
799 case 0xC4: // pinsrw r, a, #8
909 break;
910 case VEX_OPCODE_0F_3A:
911 tail_size = 1;
912 break;
913 }
914 ip++; // skip opcode
915 debug_only(has_disp32 = true); // has both kinds of operands!
916 break;
917
918 case 0x62: // EVEX_4bytes
919 assert((UseAVX > 0), "shouldn't have EVEX prefix");
920 assert(ip == inst+1, "no prefixes allowed");
921 // no EVEX collisions, all instructions that have 0x62 opcodes
922 // have EVEX versions and are subopcodes of 0x66
923 ip++; // skip P0 and exmaine W in P1
924 is_64bit = ((VEX_W & *ip) == VEX_W);
925 ip++; // move to P2
926 ip++; // skip P2, move to opcode
927 // To find the end of instruction (which == end_pc_operand).
928 switch (0xFF & *ip) {
929 case 0x61: // pcmpestri r, r/a, #8
930 case 0x70: // pshufd r, r/a, #8
931 case 0x73: // psrldq r, #8
932 tail_size = 1; // the imm8
933 break;
934 default:
935 break;
936 }
937 ip++; // skip opcode
938 debug_only(has_disp32 = true); // has both kinds of operands!
939 break;
940
941 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
942 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
943 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a
944 case 0xDD: // fld_d a; fst_d a; fstp_d a
945 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a
946 case 0xDF: // fild_d a; fistp_d a
947 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a
948 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a
3936 void Assembler::sbbl(Register dst, Address src) {
3937 InstructionMark im(this);
3938 prefix(src, dst);
3939 emit_int8(0x1B);
3940 emit_operand(dst, src);
3941 }
3942
3943 void Assembler::sbbl(Register dst, Register src) {
3944 (void) prefix_and_encode(dst->encoding(), src->encoding());
3945 emit_arith(0x1B, 0xC0, dst, src);
3946 }
3947
3948 void Assembler::setb(Condition cc, Register dst) {
3949 assert(0 <= cc && cc < 16, "illegal cc");
3950 int encode = prefix_and_encode(dst->encoding(), true);
3951 emit_int8(0x0F);
3952 emit_int8((unsigned char)0x90 | cc);
3953 emit_int8((unsigned char)(0xC0 | encode));
3954 }
3955
3956 void Assembler::shll(Register dst, int imm8) {
3957 assert(isShiftCount(imm8), "illegal shift count");
3958 int encode = prefix_and_encode(dst->encoding());
3959 if (imm8 == 1 ) {
3960 emit_int8((unsigned char)0xD1);
3961 emit_int8((unsigned char)(0xE0 | encode));
3962 } else {
3963 emit_int8((unsigned char)0xC1);
3964 emit_int8((unsigned char)(0xE0 | encode));
3965 emit_int8(imm8);
3966 }
3967 }
3968
3969 void Assembler::shll(Register dst) {
3970 int encode = prefix_and_encode(dst->encoding());
3971 emit_int8((unsigned char)0xD3);
3972 emit_int8((unsigned char)(0xE0 | encode));
3973 }
3974
3975 void Assembler::shrl(Register dst, int imm8) {
4912 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4913 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4914 emit_int8((unsigned char)0xFC);
4915 emit_int8((unsigned char)(0xC0 | encode));
4916 }
4917
4918 void Assembler::paddw(XMMRegister dst, XMMRegister src) {
4919 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4920 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4921 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4922 emit_int8((unsigned char)0xFD);
4923 emit_int8((unsigned char)(0xC0 | encode));
4924 }
4925
4926 void Assembler::paddd(XMMRegister dst, XMMRegister src) {
4927 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4928 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4929 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4930 emit_int8((unsigned char)0xFE);
4931 emit_int8((unsigned char)(0xC0 | encode));
4932 }
4933
4934 void Assembler::paddq(XMMRegister dst, XMMRegister src) {
4935 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4936 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4937 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4938 emit_int8((unsigned char)0xD4);
4939 emit_int8((unsigned char)(0xC0 | encode));
4940 }
4941
4942 void Assembler::phaddw(XMMRegister dst, XMMRegister src) {
4943 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
4944 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4945 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4946 emit_int8(0x01);
4947 emit_int8((unsigned char)(0xC0 | encode));
4948 }
4949
4950 void Assembler::phaddd(XMMRegister dst, XMMRegister src) {
4951 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
|
760
761 case 0x70: // pshufd r, r/a, #8
762 debug_only(has_disp32 = true); // has both kinds of operands!
763 case 0x73: // psrldq r, #8
764 tail_size = 1;
765 break;
766
767 case 0x12: // movlps
768 case 0x28: // movaps
769 case 0x2E: // ucomiss
770 case 0x2F: // comiss
771 case 0x54: // andps
772 case 0x55: // andnps
773 case 0x56: // orps
774 case 0x57: // xorps
775 case 0x58: // addpd
776 case 0x59: // mulpd
777 case 0x6E: // movd
778 case 0x7E: // movd
779 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush
780 case 0xFE: // paddd
781 debug_only(has_disp32 = true);
782 break;
783
784 case 0xAD: // shrd r, a, %cl
785 case 0xAF: // imul r, a
786 case 0xBE: // movsbl r, a (movsxb)
787 case 0xBF: // movswl r, a (movsxw)
788 case 0xB6: // movzbl r, a (movzxb)
789 case 0xB7: // movzwl r, a (movzxw)
790 case REP16(0x40): // cmovl cc, r, a
791 case 0xB0: // cmpxchgb
792 case 0xB1: // cmpxchg
793 case 0xC1: // xaddl
794 case 0xC7: // cmpxchg8
795 case REP16(0x90): // setcc a
796 debug_only(has_disp32 = true);
797 // fall out of the switch to decode the address
798 break;
799
800 case 0xC4: // pinsrw r, a, #8
910 break;
911 case VEX_OPCODE_0F_3A:
912 tail_size = 1;
913 break;
914 }
915 ip++; // skip opcode
916 debug_only(has_disp32 = true); // has both kinds of operands!
917 break;
918
919 case 0x62: // EVEX_4bytes
920 assert((UseAVX > 0), "shouldn't have EVEX prefix");
921 assert(ip == inst+1, "no prefixes allowed");
922 // no EVEX collisions, all instructions that have 0x62 opcodes
923 // have EVEX versions and are subopcodes of 0x66
924 ip++; // skip P0 and exmaine W in P1
925 is_64bit = ((VEX_W & *ip) == VEX_W);
926 ip++; // move to P2
927 ip++; // skip P2, move to opcode
928 // To find the end of instruction (which == end_pc_operand).
929 switch (0xFF & *ip) {
930 case 0x22: // pinsrd r, r/a, #8
931 case 0x61: // pcmpestri r, r/a, #8
932 case 0x70: // pshufd r, r/a, #8
933 case 0x73: // psrldq r, #8
934 tail_size = 1; // the imm8
935 break;
936 default:
937 break;
938 }
939 ip++; // skip opcode
940 debug_only(has_disp32 = true); // has both kinds of operands!
941 break;
942
943 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
944 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
945 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a
946 case 0xDD: // fld_d a; fst_d a; fstp_d a
947 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a
948 case 0xDF: // fild_d a; fistp_d a
949 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a
950 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a
3938 void Assembler::sbbl(Register dst, Address src) {
3939 InstructionMark im(this);
3940 prefix(src, dst);
3941 emit_int8(0x1B);
3942 emit_operand(dst, src);
3943 }
3944
3945 void Assembler::sbbl(Register dst, Register src) {
3946 (void) prefix_and_encode(dst->encoding(), src->encoding());
3947 emit_arith(0x1B, 0xC0, dst, src);
3948 }
3949
3950 void Assembler::setb(Condition cc, Register dst) {
3951 assert(0 <= cc && cc < 16, "illegal cc");
3952 int encode = prefix_and_encode(dst->encoding(), true);
3953 emit_int8(0x0F);
3954 emit_int8((unsigned char)0x90 | cc);
3955 emit_int8((unsigned char)(0xC0 | encode));
3956 }
3957
3958 void Assembler::palignr(XMMRegister dst, XMMRegister src, int imm8) {
3959 assert(VM_Version::supports_ssse3(), "");
3960 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ false);
3961 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3962 emit_int8((unsigned char)0x0F);
3963 emit_int8((unsigned char)(0xC0 | encode));
3964 emit_int8(imm8);
3965 }
3966
3967 void Assembler::pblendw(XMMRegister dst, XMMRegister src, int imm8) {
3968 assert(VM_Version::supports_sse4_1(), "");
3969 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3970 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3971 emit_int8((unsigned char)0x0E);
3972 emit_int8((unsigned char)(0xC0 | encode));
3973 emit_int8(imm8);
3974 }
3975
3976 void Assembler::sha1rnds4(XMMRegister dst, XMMRegister src, int imm8) {
3977 assert(VM_Version::supports_sha(), "");
3978 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3979 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_3A, &attributes);
3980 emit_int8((unsigned char)0xCC);
3981 emit_int8((unsigned char)(0xC0 | encode));
3982 emit_int8((unsigned char)imm8);
3983 }
3984
3985 void Assembler::sha1nexte(XMMRegister dst, XMMRegister src) {
3986 assert(VM_Version::supports_sha(), "");
3987 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3988 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
3989 emit_int8((unsigned char)0xC8);
3990 emit_int8((unsigned char)(0xC0 | encode));
3991 }
3992
3993 void Assembler::sha1msg1(XMMRegister dst, XMMRegister src) {
3994 assert(VM_Version::supports_sha(), "");
3995 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3996 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
3997 emit_int8((unsigned char)0xC9);
3998 emit_int8((unsigned char)(0xC0 | encode));
3999 }
4000
4001 void Assembler::sha1msg2(XMMRegister dst, XMMRegister src) {
4002 assert(VM_Version::supports_sha(), "");
4003 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4004 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4005 emit_int8((unsigned char)0xCA);
4006 emit_int8((unsigned char)(0xC0 | encode));
4007 }
4008
4009 // xmm0 is implicit additional source to this instruction.
4010 void Assembler::sha256rnds2(XMMRegister dst, XMMRegister src) {
4011 assert(VM_Version::supports_sha(), "");
4012 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4013 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4014 emit_int8((unsigned char)0xCB);
4015 emit_int8((unsigned char)(0xC0 | encode));
4016 }
4017
4018 void Assembler::sha256msg1(XMMRegister dst, XMMRegister src) {
4019 assert(VM_Version::supports_sha(), "");
4020 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4021 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4022 emit_int8((unsigned char)0xCC);
4023 emit_int8((unsigned char)(0xC0 | encode));
4024 }
4025
4026 void Assembler::sha256msg2(XMMRegister dst, XMMRegister src) {
4027 assert(VM_Version::supports_sha(), "");
4028 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4029 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4030 emit_int8((unsigned char)0xCD);
4031 emit_int8((unsigned char)(0xC0 | encode));
4032 }
4033
4034
4035 void Assembler::shll(Register dst, int imm8) {
4036 assert(isShiftCount(imm8), "illegal shift count");
4037 int encode = prefix_and_encode(dst->encoding());
4038 if (imm8 == 1 ) {
4039 emit_int8((unsigned char)0xD1);
4040 emit_int8((unsigned char)(0xE0 | encode));
4041 } else {
4042 emit_int8((unsigned char)0xC1);
4043 emit_int8((unsigned char)(0xE0 | encode));
4044 emit_int8(imm8);
4045 }
4046 }
4047
4048 void Assembler::shll(Register dst) {
4049 int encode = prefix_and_encode(dst->encoding());
4050 emit_int8((unsigned char)0xD3);
4051 emit_int8((unsigned char)(0xE0 | encode));
4052 }
4053
4054 void Assembler::shrl(Register dst, int imm8) {
4991 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4992 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4993 emit_int8((unsigned char)0xFC);
4994 emit_int8((unsigned char)(0xC0 | encode));
4995 }
4996
4997 void Assembler::paddw(XMMRegister dst, XMMRegister src) {
4998 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4999 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5000 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5001 emit_int8((unsigned char)0xFD);
5002 emit_int8((unsigned char)(0xC0 | encode));
5003 }
5004
5005 void Assembler::paddd(XMMRegister dst, XMMRegister src) {
5006 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5007 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5008 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5009 emit_int8((unsigned char)0xFE);
5010 emit_int8((unsigned char)(0xC0 | encode));
5011 }
5012
5013 void Assembler::paddd(XMMRegister dst, Address src) {
5014 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5015 InstructionMark im(this);
5016 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5017 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5018 emit_int8((unsigned char)0xFE);
5019 emit_operand(dst, src);
5020 }
5021
5022 void Assembler::paddq(XMMRegister dst, XMMRegister src) {
5023 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5024 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5025 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5026 emit_int8((unsigned char)0xD4);
5027 emit_int8((unsigned char)(0xC0 | encode));
5028 }
5029
5030 void Assembler::phaddw(XMMRegister dst, XMMRegister src) {
5031 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
5032 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5033 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5034 emit_int8(0x01);
5035 emit_int8((unsigned char)(0xC0 | encode));
5036 }
5037
5038 void Assembler::phaddd(XMMRegister dst, XMMRegister src) {
5039 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
|