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src/cpu/x86/vm/vm_version_x86.hpp
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*** 219,229 ****
adx : 1,
: 6,
avx512pf : 1,
avx512er : 1,
avx512cd : 1,
! : 1,
avx512bw : 1,
avx512vl : 1;
} bits;
};
--- 219,229 ----
adx : 1,
: 6,
avx512pf : 1,
avx512er : 1,
avx512cd : 1,
! sha : 1,
avx512bw : 1,
avx512vl : 1;
} bits;
};
*** 280,294 ****
CPU_ADX = (1 << 25),
CPU_AVX512F = (1 << 26), // AVX 512bit foundation instructions
CPU_AVX512DQ = (1 << 27),
CPU_AVX512PF = (1 << 28),
CPU_AVX512ER = (1 << 29),
! CPU_AVX512CD = (1 << 30),
! CPU_AVX512BW = (1 << 31)
};
! #define CPU_AVX512VL UCONST64(0x100000000) // EVEX instructions with smaller vector length : enums are limited to 32bit
enum Extended_Family {
// AMD
CPU_FAMILY_AMD_11H = 0x11,
// Intel
--- 280,296 ----
CPU_ADX = (1 << 25),
CPU_AVX512F = (1 << 26), // AVX 512bit foundation instructions
CPU_AVX512DQ = (1 << 27),
CPU_AVX512PF = (1 << 28),
CPU_AVX512ER = (1 << 29),
! CPU_AVX512CD = (1 << 30)
! // Keeping sign bit 31 unassigned.
};
! #define CPU_AVX512BW ((uint64_t)UCONST64(0x100000000)) // enums are limited to 31 bit
! #define CPU_AVX512VL ((uint64_t)UCONST64(0x200000000)) // EVEX instructions with smaller vector length
! #define CPU_SHA ((uint64_t)UCONST64(0x400000000)) // SHA instructions
enum Extended_Family {
// AMD
CPU_FAMILY_AMD_11H = 0x11,
// Intel
*** 514,523 ****
--- 516,527 ----
if(is_intel()) {
if(_cpuid_info.sef_cpuid7_ebx.bits.adx != 0)
result |= CPU_ADX;
if(_cpuid_info.sef_cpuid7_ebx.bits.bmi2 != 0)
result |= CPU_BMI2;
+ if (_cpuid_info.sef_cpuid7_ebx.bits.sha != 0)
+ result |= CPU_SHA;
if(_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0)
result |= CPU_LZCNT;
// for Intel, ecx.bits.misalignsse bit (bit 8) indicates support for prefetchw
if (_cpuid_info.ext_cpuid1_ecx.bits.misalignsse != 0) {
result |= CPU_3DNOW_PREFETCH;
*** 719,728 ****
--- 723,733 ----
static bool supports_avx512vlbw() { return (supports_avx512bw() && supports_avx512vl()); }
static bool supports_avx512novl() { return (supports_evex() && !supports_avx512vl()); }
static bool supports_avx512nobw() { return (supports_evex() && !supports_avx512bw()); }
static bool supports_avx256only() { return (supports_avx2() && !supports_evex()); }
static bool supports_avxonly() { return ((supports_avx2() || supports_avx()) && !supports_evex()); }
+ static bool supports_sha() { return (_features & CPU_SHA) != 0; }
// Intel features
static bool is_intel_family_core() { return is_intel() &&
extended_cpu_family() == CPU_FAMILY_INTEL_CORE; }
static bool is_intel_tsc_synched_at_init() {
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