src/hotspot/cpu/x86/assembler_x86.cpp

*** 3744,3753 ****
--- 3744,3774 ----
    emit_int8(0x00);
    emit_int8(0xC0 | encode);
    emit_int8(imm8);
  }
  
+ void Assembler::vpermb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
+   assert(VM_Version::supports_avx512vbmi(), "");
+   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
+   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
+   emit_int8((unsigned char)0x8D);
+   emit_int8((unsigned char)(0xC0 | encode));
+ }
+ 
+ void Assembler::vpermw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
+   assert(VM_Version::supports_avx512vlbw(), "");
+   InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
+   attributes.set_embedded_opmask_register_specifier(mask);
+   attributes.set_is_evex_instruction();
+   if (merge) {
+     attributes.reset_is_clear_context();
+   }
+   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
+   emit_int8((unsigned char)0x8D);
+   emit_int8((unsigned char)(0xC0 | encode));
+ }
+ 
  void Assembler::vpermd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
    assert(VM_Version::supports_avx2(), "");
    // VEX.NDS.256.66.0F38.W0 36 /r
    InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
    int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
*** 3763,3772 ****
--- 3784,3801 ----
    vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
    emit_int8(0x36);
    emit_operand(dst, src);
  }
  
+ void Assembler::evpermd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
+   assert(VM_Version::supports_evex(), "");
+   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
+   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
+   emit_int8(0x36);
+   emit_int8((unsigned char)(0xC0 | encode));
+ }
+ 
  void Assembler::vperm2i128(XMMRegister dst,  XMMRegister nds, XMMRegister src, int imm8) {
    assert(VM_Version::supports_avx2(), "");
    InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
    int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
    emit_int8(0x46);