1 /*
2 * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "gc/shared/cardTableBarrierSet.hpp"
29 #include "gc/shared/collectedHeap.inline.hpp"
30 #include "interpreter/interpreter.hpp"
31 #include "memory/resourceArea.hpp"
32 #include "prims/methodHandles.hpp"
33 #include "runtime/biasedLocking.hpp"
34 #include "runtime/objectMonitor.hpp"
35 #include "runtime/os.hpp"
36 #include "runtime/sharedRuntime.hpp"
37 #include "runtime/stubRoutines.hpp"
38 #include "utilities/macros.hpp"
39
40 #ifdef PRODUCT
41 #define BLOCK_COMMENT(str) /* nothing */
42 #define STOP(error) stop(error)
43 #else
44 #define BLOCK_COMMENT(str) block_comment(str)
45 #define STOP(error) block_comment(error); stop(error)
46 #endif
47
48 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
49 // Implementation of AddressLiteral
50
51 // A 2-D table for managing compressed displacement(disp8) on EVEX enabled platforms.
52 unsigned char tuple_table[Assembler::EVEX_ETUP + 1][Assembler::AVX_512bit + 1] = {
53 // -----------------Table 4.5 -------------------- //
54 16, 32, 64, // EVEX_FV(0)
55 4, 4, 4, // EVEX_FV(1) - with Evex.b
56 16, 32, 64, // EVEX_FV(2) - with Evex.w
57 8, 8, 8, // EVEX_FV(3) - with Evex.w and Evex.b
58 8, 16, 32, // EVEX_HV(0)
59 4, 4, 4, // EVEX_HV(1) - with Evex.b
60 // -----------------Table 4.6 -------------------- //
61 16, 32, 64, // EVEX_FVM(0)
62 1, 1, 1, // EVEX_T1S(0)
63 2, 2, 2, // EVEX_T1S(1)
64 4, 4, 4, // EVEX_T1S(2)
65 8, 8, 8, // EVEX_T1S(3)
66 4, 4, 4, // EVEX_T1F(0)
67 8, 8, 8, // EVEX_T1F(1)
68 8, 8, 8, // EVEX_T2(0)
69 0, 16, 16, // EVEX_T2(1)
70 0, 16, 16, // EVEX_T4(0)
71 0, 0, 32, // EVEX_T4(1)
72 0, 0, 32, // EVEX_T8(0)
73 8, 16, 32, // EVEX_HVM(0)
74 4, 8, 16, // EVEX_QVM(0)
75 2, 4, 8, // EVEX_OVM(0)
76 16, 16, 16, // EVEX_M128(0)
77 8, 32, 64, // EVEX_DUP(0)
78 0, 0, 0 // EVEX_NTUP
79 };
80
81 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
82 _is_lval = false;
83 _target = target;
84 switch (rtype) {
85 case relocInfo::oop_type:
86 case relocInfo::metadata_type:
87 // Oops are a special case. Normally they would be their own section
88 // but in cases like icBuffer they are literals in the code stream that
89 // we don't have a section for. We use none so that we get a literal address
90 // which is always patchable.
91 break;
92 case relocInfo::external_word_type:
93 _rspec = external_word_Relocation::spec(target);
94 break;
95 case relocInfo::internal_word_type:
96 _rspec = internal_word_Relocation::spec(target);
97 break;
98 case relocInfo::opt_virtual_call_type:
99 _rspec = opt_virtual_call_Relocation::spec();
100 break;
101 case relocInfo::static_call_type:
102 _rspec = static_call_Relocation::spec();
103 break;
104 case relocInfo::runtime_call_type:
105 _rspec = runtime_call_Relocation::spec();
106 break;
107 case relocInfo::poll_type:
108 case relocInfo::poll_return_type:
109 _rspec = Relocation::spec_simple(rtype);
110 break;
111 case relocInfo::none:
112 break;
113 default:
114 ShouldNotReachHere();
115 break;
116 }
117 }
118
119 // Implementation of Address
120
121 #ifdef _LP64
122
123 Address Address::make_array(ArrayAddress adr) {
124 // Not implementable on 64bit machines
125 // Should have been handled higher up the call chain.
126 ShouldNotReachHere();
127 return Address();
128 }
129
130 // exceedingly dangerous constructor
131 Address::Address(int disp, address loc, relocInfo::relocType rtype) {
132 _base = noreg;
133 _index = noreg;
134 _scale = no_scale;
135 _disp = disp;
136 _xmmindex = xnoreg;
137 _isxmmindex = false;
138 switch (rtype) {
139 case relocInfo::external_word_type:
140 _rspec = external_word_Relocation::spec(loc);
141 break;
142 case relocInfo::internal_word_type:
143 _rspec = internal_word_Relocation::spec(loc);
144 break;
145 case relocInfo::runtime_call_type:
146 // HMM
147 _rspec = runtime_call_Relocation::spec();
148 break;
149 case relocInfo::poll_type:
150 case relocInfo::poll_return_type:
151 _rspec = Relocation::spec_simple(rtype);
152 break;
153 case relocInfo::none:
154 break;
155 default:
156 ShouldNotReachHere();
157 }
158 }
159 #else // LP64
160
161 Address Address::make_array(ArrayAddress adr) {
162 AddressLiteral base = adr.base();
163 Address index = adr.index();
164 assert(index._disp == 0, "must not have disp"); // maybe it can?
165 Address array(index._base, index._index, index._scale, (intptr_t) base.target());
166 array._rspec = base._rspec;
167 return array;
168 }
169
170 // exceedingly dangerous constructor
171 Address::Address(address loc, RelocationHolder spec) {
172 _base = noreg;
173 _index = noreg;
174 _scale = no_scale;
175 _disp = (intptr_t) loc;
176 _rspec = spec;
177 _xmmindex = xnoreg;
178 _isxmmindex = false;
179 }
180
181 #endif // _LP64
182
183
184
185 // Convert the raw encoding form into the form expected by the constructor for
186 // Address. An index of 4 (rsp) corresponds to having no index, so convert
187 // that to noreg for the Address constructor.
188 Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) {
189 RelocationHolder rspec;
190 if (disp_reloc != relocInfo::none) {
191 rspec = Relocation::spec_simple(disp_reloc);
192 }
193 bool valid_index = index != rsp->encoding();
194 if (valid_index) {
195 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));
196 madr._rspec = rspec;
197 return madr;
198 } else {
199 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));
200 madr._rspec = rspec;
201 return madr;
202 }
203 }
204
205 // Implementation of Assembler
206
207 int AbstractAssembler::code_fill_byte() {
208 return (u_char)'\xF4'; // hlt
209 }
210
211 // make this go away someday
212 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) {
213 if (rtype == relocInfo::none)
214 emit_int32(data);
215 else
216 emit_data(data, Relocation::spec_simple(rtype), format);
217 }
218
219 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) {
220 assert(imm_operand == 0, "default format must be immediate in this file");
221 assert(inst_mark() != NULL, "must be inside InstructionMark");
222 if (rspec.type() != relocInfo::none) {
223 #ifdef ASSERT
224 check_relocation(rspec, format);
225 #endif
226 // Do not use AbstractAssembler::relocate, which is not intended for
227 // embedded words. Instead, relocate to the enclosing instruction.
228
229 // hack. call32 is too wide for mask so use disp32
230 if (format == call32_operand)
231 code_section()->relocate(inst_mark(), rspec, disp32_operand);
232 else
233 code_section()->relocate(inst_mark(), rspec, format);
234 }
235 emit_int32(data);
236 }
237
238 static int encode(Register r) {
239 int enc = r->encoding();
240 if (enc >= 8) {
241 enc -= 8;
242 }
243 return enc;
244 }
245
246 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
247 assert(dst->has_byte_register(), "must have byte register");
248 assert(isByte(op1) && isByte(op2), "wrong opcode");
249 assert(isByte(imm8), "not a byte");
250 assert((op1 & 0x01) == 0, "should be 8bit operation");
251 emit_int8(op1);
252 emit_int8(op2 | encode(dst));
253 emit_int8(imm8);
254 }
255
256
257 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) {
258 assert(isByte(op1) && isByte(op2), "wrong opcode");
259 assert((op1 & 0x01) == 1, "should be 32bit operation");
260 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
261 if (is8bit(imm32)) {
262 emit_int8(op1 | 0x02); // set sign bit
263 emit_int8(op2 | encode(dst));
264 emit_int8(imm32 & 0xFF);
265 } else {
266 emit_int8(op1);
267 emit_int8(op2 | encode(dst));
268 emit_int32(imm32);
269 }
270 }
271
272 // Force generation of a 4 byte immediate value even if it fits into 8bit
273 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) {
274 assert(isByte(op1) && isByte(op2), "wrong opcode");
275 assert((op1 & 0x01) == 1, "should be 32bit operation");
276 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
277 emit_int8(op1);
278 emit_int8(op2 | encode(dst));
279 emit_int32(imm32);
280 }
281
282 // immediate-to-memory forms
283 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) {
284 assert((op1 & 0x01) == 1, "should be 32bit operation");
285 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
286 if (is8bit(imm32)) {
287 emit_int8(op1 | 0x02); // set sign bit
288 emit_operand(rm, adr, 1);
289 emit_int8(imm32 & 0xFF);
290 } else {
291 emit_int8(op1);
292 emit_operand(rm, adr, 4);
293 emit_int32(imm32);
294 }
295 }
296
297
298 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
299 assert(isByte(op1) && isByte(op2), "wrong opcode");
300 emit_int8(op1);
301 emit_int8(op2 | encode(dst) << 3 | encode(src));
302 }
303
304
305 bool Assembler::query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len,
306 int cur_tuple_type, int in_size_in_bits, int cur_encoding) {
307 int mod_idx = 0;
308 // We will test if the displacement fits the compressed format and if so
309 // apply the compression to the displacment iff the result is8bit.
310 if (VM_Version::supports_evex() && is_evex_inst) {
311 switch (cur_tuple_type) {
312 case EVEX_FV:
313 if ((cur_encoding & VEX_W) == VEX_W) {
314 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2;
315 } else {
316 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
317 }
318 break;
319
320 case EVEX_HV:
321 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
322 break;
323
324 case EVEX_FVM:
325 break;
326
327 case EVEX_T1S:
328 switch (in_size_in_bits) {
329 case EVEX_8bit:
330 break;
331
332 case EVEX_16bit:
333 mod_idx = 1;
334 break;
335
336 case EVEX_32bit:
337 mod_idx = 2;
338 break;
339
340 case EVEX_64bit:
341 mod_idx = 3;
342 break;
343 }
344 break;
345
346 case EVEX_T1F:
347 case EVEX_T2:
348 case EVEX_T4:
349 mod_idx = (in_size_in_bits == EVEX_64bit) ? 1 : 0;
350 break;
351
352 case EVEX_T8:
353 break;
354
355 case EVEX_HVM:
356 break;
357
358 case EVEX_QVM:
359 break;
360
361 case EVEX_OVM:
362 break;
363
364 case EVEX_M128:
365 break;
366
367 case EVEX_DUP:
368 break;
369
370 default:
371 assert(0, "no valid evex tuple_table entry");
372 break;
373 }
374
375 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
376 int disp_factor = tuple_table[cur_tuple_type + mod_idx][vector_len];
377 if ((disp % disp_factor) == 0) {
378 int new_disp = disp / disp_factor;
379 if ((-0x80 <= new_disp && new_disp < 0x80)) {
380 disp = new_disp;
381 }
382 } else {
383 return false;
384 }
385 }
386 }
387 return (-0x80 <= disp && disp < 0x80);
388 }
389
390
391 bool Assembler::emit_compressed_disp_byte(int &disp) {
392 int mod_idx = 0;
393 // We will test if the displacement fits the compressed format and if so
394 // apply the compression to the displacment iff the result is8bit.
395 if (VM_Version::supports_evex() && _attributes && _attributes->is_evex_instruction()) {
396 int evex_encoding = _attributes->get_evex_encoding();
397 int tuple_type = _attributes->get_tuple_type();
398 switch (tuple_type) {
399 case EVEX_FV:
400 if ((evex_encoding & VEX_W) == VEX_W) {
401 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2;
402 } else {
403 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
404 }
405 break;
406
407 case EVEX_HV:
408 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
409 break;
410
411 case EVEX_FVM:
412 break;
413
414 case EVEX_T1S:
415 switch (_attributes->get_input_size()) {
416 case EVEX_8bit:
417 break;
418
419 case EVEX_16bit:
420 mod_idx = 1;
421 break;
422
423 case EVEX_32bit:
424 mod_idx = 2;
425 break;
426
427 case EVEX_64bit:
428 mod_idx = 3;
429 break;
430 }
431 break;
432
433 case EVEX_T1F:
434 case EVEX_T2:
435 case EVEX_T4:
436 mod_idx = (_attributes->get_input_size() == EVEX_64bit) ? 1 : 0;
437 break;
438
439 case EVEX_T8:
440 break;
441
442 case EVEX_HVM:
443 break;
444
445 case EVEX_QVM:
446 break;
447
448 case EVEX_OVM:
449 break;
450
451 case EVEX_M128:
452 break;
453
454 case EVEX_DUP:
455 break;
456
457 default:
458 assert(0, "no valid evex tuple_table entry");
459 break;
460 }
461
462 int vector_len = _attributes->get_vector_len();
463 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
464 int disp_factor = tuple_table[tuple_type + mod_idx][vector_len];
465 if ((disp % disp_factor) == 0) {
466 int new_disp = disp / disp_factor;
467 if (is8bit(new_disp)) {
468 disp = new_disp;
469 }
470 } else {
471 return false;
472 }
473 }
474 }
475 return is8bit(disp);
476 }
477
478
479 void Assembler::emit_operand(Register reg, Register base, Register index,
480 Address::ScaleFactor scale, int disp,
481 RelocationHolder const& rspec,
482 int rip_relative_correction) {
483 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();
484
485 // Encode the registers as needed in the fields they are used in
486
487 int regenc = encode(reg) << 3;
488 int indexenc = index->is_valid() ? encode(index) << 3 : 0;
489 int baseenc = base->is_valid() ? encode(base) : 0;
490
491 if (base->is_valid()) {
492 if (index->is_valid()) {
493 assert(scale != Address::no_scale, "inconsistent address");
494 // [base + index*scale + disp]
495 if (disp == 0 && rtype == relocInfo::none &&
496 base != rbp LP64_ONLY(&& base != r13)) {
497 // [base + index*scale]
498 // [00 reg 100][ss index base]
499 assert(index != rsp, "illegal addressing mode");
500 emit_int8(0x04 | regenc);
501 emit_int8(scale << 6 | indexenc | baseenc);
502 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
503 // [base + index*scale + imm8]
504 // [01 reg 100][ss index base] imm8
505 assert(index != rsp, "illegal addressing mode");
506 emit_int8(0x44 | regenc);
507 emit_int8(scale << 6 | indexenc | baseenc);
508 emit_int8(disp & 0xFF);
509 } else {
510 // [base + index*scale + disp32]
511 // [10 reg 100][ss index base] disp32
512 assert(index != rsp, "illegal addressing mode");
513 emit_int8(0x84 | regenc);
514 emit_int8(scale << 6 | indexenc | baseenc);
515 emit_data(disp, rspec, disp32_operand);
516 }
517 } else if (base == rsp LP64_ONLY(|| base == r12)) {
518 // [rsp + disp]
519 if (disp == 0 && rtype == relocInfo::none) {
520 // [rsp]
521 // [00 reg 100][00 100 100]
522 emit_int8(0x04 | regenc);
523 emit_int8(0x24);
524 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
525 // [rsp + imm8]
526 // [01 reg 100][00 100 100] disp8
527 emit_int8(0x44 | regenc);
528 emit_int8(0x24);
529 emit_int8(disp & 0xFF);
530 } else {
531 // [rsp + imm32]
532 // [10 reg 100][00 100 100] disp32
533 emit_int8(0x84 | regenc);
534 emit_int8(0x24);
535 emit_data(disp, rspec, disp32_operand);
536 }
537 } else {
538 // [base + disp]
539 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode");
540 if (disp == 0 && rtype == relocInfo::none &&
541 base != rbp LP64_ONLY(&& base != r13)) {
542 // [base]
543 // [00 reg base]
544 emit_int8(0x00 | regenc | baseenc);
545 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
546 // [base + disp8]
547 // [01 reg base] disp8
548 emit_int8(0x40 | regenc | baseenc);
549 emit_int8(disp & 0xFF);
550 } else {
551 // [base + disp32]
552 // [10 reg base] disp32
553 emit_int8(0x80 | regenc | baseenc);
554 emit_data(disp, rspec, disp32_operand);
555 }
556 }
557 } else {
558 if (index->is_valid()) {
559 assert(scale != Address::no_scale, "inconsistent address");
560 // [index*scale + disp]
561 // [00 reg 100][ss index 101] disp32
562 assert(index != rsp, "illegal addressing mode");
563 emit_int8(0x04 | regenc);
564 emit_int8(scale << 6 | indexenc | 0x05);
565 emit_data(disp, rspec, disp32_operand);
566 } else if (rtype != relocInfo::none ) {
567 // [disp] (64bit) RIP-RELATIVE (32bit) abs
568 // [00 000 101] disp32
569
570 emit_int8(0x05 | regenc);
571 // Note that the RIP-rel. correction applies to the generated
572 // disp field, but _not_ to the target address in the rspec.
573
574 // disp was created by converting the target address minus the pc
575 // at the start of the instruction. That needs more correction here.
576 // intptr_t disp = target - next_ip;
577 assert(inst_mark() != NULL, "must be inside InstructionMark");
578 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction;
579 int64_t adjusted = disp;
580 // Do rip-rel adjustment for 64bit
581 LP64_ONLY(adjusted -= (next_ip - inst_mark()));
582 assert(is_simm32(adjusted),
583 "must be 32bit offset (RIP relative address)");
584 emit_data((int32_t) adjusted, rspec, disp32_operand);
585
586 } else {
587 // 32bit never did this, did everything as the rip-rel/disp code above
588 // [disp] ABSOLUTE
589 // [00 reg 100][00 100 101] disp32
590 emit_int8(0x04 | regenc);
591 emit_int8(0x25);
592 emit_data(disp, rspec, disp32_operand);
593 }
594 }
595 }
596
597 void Assembler::emit_operand(XMMRegister reg, Register base, Register index,
598 Address::ScaleFactor scale, int disp,
599 RelocationHolder const& rspec) {
600 if (UseAVX > 2) {
601 int xreg_enc = reg->encoding();
602 if (xreg_enc > 15) {
603 XMMRegister new_reg = as_XMMRegister(xreg_enc & 0xf);
604 emit_operand((Register)new_reg, base, index, scale, disp, rspec);
605 return;
606 }
607 }
608 emit_operand((Register)reg, base, index, scale, disp, rspec);
609 }
610
611 void Assembler::emit_operand(XMMRegister reg, Register base, XMMRegister index,
612 Address::ScaleFactor scale, int disp,
613 RelocationHolder const& rspec) {
614 if (UseAVX > 2) {
615 int xreg_enc = reg->encoding();
616 int xmmindex_enc = index->encoding();
617 XMMRegister new_reg = as_XMMRegister(xreg_enc & 0xf);
618 XMMRegister new_index = as_XMMRegister(xmmindex_enc & 0xf);
619 emit_operand((Register)new_reg, base, (Register)new_index, scale, disp, rspec);
620 } else {
621 emit_operand((Register)reg, base, (Register)index, scale, disp, rspec);
622 }
623 }
624
625
626 // Secret local extension to Assembler::WhichOperand:
627 #define end_pc_operand (_WhichOperand_limit)
628
629 address Assembler::locate_operand(address inst, WhichOperand which) {
630 // Decode the given instruction, and return the address of
631 // an embedded 32-bit operand word.
632
633 // If "which" is disp32_operand, selects the displacement portion
634 // of an effective address specifier.
635 // If "which" is imm64_operand, selects the trailing immediate constant.
636 // If "which" is call32_operand, selects the displacement of a call or jump.
637 // Caller is responsible for ensuring that there is such an operand,
638 // and that it is 32/64 bits wide.
639
640 // If "which" is end_pc_operand, find the end of the instruction.
641
642 address ip = inst;
643 bool is_64bit = false;
644
645 debug_only(bool has_disp32 = false);
646 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn
647
648 again_after_prefix:
649 switch (0xFF & *ip++) {
650
651 // These convenience macros generate groups of "case" labels for the switch.
652 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3
653 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \
654 case (x)+4: case (x)+5: case (x)+6: case (x)+7
655 #define REP16(x) REP8((x)+0): \
656 case REP8((x)+8)
657
658 case CS_segment:
659 case SS_segment:
660 case DS_segment:
661 case ES_segment:
662 case FS_segment:
663 case GS_segment:
664 // Seems dubious
665 LP64_ONLY(assert(false, "shouldn't have that prefix"));
666 assert(ip == inst+1, "only one prefix allowed");
667 goto again_after_prefix;
668
669 case 0x67:
670 case REX:
671 case REX_B:
672 case REX_X:
673 case REX_XB:
674 case REX_R:
675 case REX_RB:
676 case REX_RX:
677 case REX_RXB:
678 NOT_LP64(assert(false, "64bit prefixes"));
679 goto again_after_prefix;
680
681 case REX_W:
682 case REX_WB:
683 case REX_WX:
684 case REX_WXB:
685 case REX_WR:
686 case REX_WRB:
687 case REX_WRX:
688 case REX_WRXB:
689 NOT_LP64(assert(false, "64bit prefixes"));
690 is_64bit = true;
691 goto again_after_prefix;
692
693 case 0xFF: // pushq a; decl a; incl a; call a; jmp a
694 case 0x88: // movb a, r
695 case 0x89: // movl a, r
696 case 0x8A: // movb r, a
697 case 0x8B: // movl r, a
698 case 0x8F: // popl a
699 debug_only(has_disp32 = true);
700 break;
701
702 case 0x68: // pushq #32
703 if (which == end_pc_operand) {
704 return ip + 4;
705 }
706 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate");
707 return ip; // not produced by emit_operand
708
709 case 0x66: // movw ... (size prefix)
710 again_after_size_prefix2:
711 switch (0xFF & *ip++) {
712 case REX:
713 case REX_B:
714 case REX_X:
715 case REX_XB:
716 case REX_R:
717 case REX_RB:
718 case REX_RX:
719 case REX_RXB:
720 case REX_W:
721 case REX_WB:
722 case REX_WX:
723 case REX_WXB:
724 case REX_WR:
725 case REX_WRB:
726 case REX_WRX:
727 case REX_WRXB:
728 NOT_LP64(assert(false, "64bit prefix found"));
729 goto again_after_size_prefix2;
730 case 0x8B: // movw r, a
731 case 0x89: // movw a, r
732 debug_only(has_disp32 = true);
733 break;
734 case 0xC7: // movw a, #16
735 debug_only(has_disp32 = true);
736 tail_size = 2; // the imm16
737 break;
738 case 0x0F: // several SSE/SSE2 variants
739 ip--; // reparse the 0x0F
740 goto again_after_prefix;
741 default:
742 ShouldNotReachHere();
743 }
744 break;
745
746 case REP8(0xB8): // movl/q r, #32/#64(oop?)
747 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4);
748 // these asserts are somewhat nonsensical
749 #ifndef _LP64
750 assert(which == imm_operand || which == disp32_operand,
751 "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip));
752 #else
753 assert((which == call32_operand || which == imm_operand) && is_64bit ||
754 which == narrow_oop_operand && !is_64bit,
755 "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip));
756 #endif // _LP64
757 return ip;
758
759 case 0x69: // imul r, a, #32
760 case 0xC7: // movl a, #32(oop?)
761 tail_size = 4;
762 debug_only(has_disp32 = true); // has both kinds of operands!
763 break;
764
765 case 0x0F: // movx..., etc.
766 switch (0xFF & *ip++) {
767 case 0x3A: // pcmpestri
768 tail_size = 1;
769 case 0x38: // ptest, pmovzxbw
770 ip++; // skip opcode
771 debug_only(has_disp32 = true); // has both kinds of operands!
772 break;
773
774 case 0x70: // pshufd r, r/a, #8
775 debug_only(has_disp32 = true); // has both kinds of operands!
776 case 0x73: // psrldq r, #8
777 tail_size = 1;
778 break;
779
780 case 0x12: // movlps
781 case 0x28: // movaps
782 case 0x2E: // ucomiss
783 case 0x2F: // comiss
784 case 0x54: // andps
785 case 0x55: // andnps
786 case 0x56: // orps
787 case 0x57: // xorps
788 case 0x58: // addpd
789 case 0x59: // mulpd
790 case 0x6E: // movd
791 case 0x7E: // movd
792 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush
793 case 0xFE: // paddd
794 debug_only(has_disp32 = true);
795 break;
796
797 case 0xAD: // shrd r, a, %cl
798 case 0xAF: // imul r, a
799 case 0xBE: // movsbl r, a (movsxb)
800 case 0xBF: // movswl r, a (movsxw)
801 case 0xB6: // movzbl r, a (movzxb)
802 case 0xB7: // movzwl r, a (movzxw)
803 case REP16(0x40): // cmovl cc, r, a
804 case 0xB0: // cmpxchgb
805 case 0xB1: // cmpxchg
806 case 0xC1: // xaddl
807 case 0xC7: // cmpxchg8
808 case REP16(0x90): // setcc a
809 debug_only(has_disp32 = true);
810 // fall out of the switch to decode the address
811 break;
812
813 case 0xC4: // pinsrw r, a, #8
814 debug_only(has_disp32 = true);
815 case 0xC5: // pextrw r, r, #8
816 tail_size = 1; // the imm8
817 break;
818
819 case 0xAC: // shrd r, a, #8
820 debug_only(has_disp32 = true);
821 tail_size = 1; // the imm8
822 break;
823
824 case REP16(0x80): // jcc rdisp32
825 if (which == end_pc_operand) return ip + 4;
826 assert(which == call32_operand, "jcc has no disp32 or imm");
827 return ip;
828 default:
829 ShouldNotReachHere();
830 }
831 break;
832
833 case 0x81: // addl a, #32; addl r, #32
834 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
835 // on 32bit in the case of cmpl, the imm might be an oop
836 tail_size = 4;
837 debug_only(has_disp32 = true); // has both kinds of operands!
838 break;
839
840 case 0x83: // addl a, #8; addl r, #8
841 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
842 debug_only(has_disp32 = true); // has both kinds of operands!
843 tail_size = 1;
844 break;
845
846 case 0x9B:
847 switch (0xFF & *ip++) {
848 case 0xD9: // fnstcw a
849 debug_only(has_disp32 = true);
850 break;
851 default:
852 ShouldNotReachHere();
853 }
854 break;
855
856 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a
857 case REP4(0x10): // adc...
858 case REP4(0x20): // and...
859 case REP4(0x30): // xor...
860 case REP4(0x08): // or...
861 case REP4(0x18): // sbb...
862 case REP4(0x28): // sub...
863 case 0xF7: // mull a
864 case 0x8D: // lea r, a
865 case 0x87: // xchg r, a
866 case REP4(0x38): // cmp...
867 case 0x85: // test r, a
868 debug_only(has_disp32 = true); // has both kinds of operands!
869 break;
870
871 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8
872 case 0xC6: // movb a, #8
873 case 0x80: // cmpb a, #8
874 case 0x6B: // imul r, a, #8
875 debug_only(has_disp32 = true); // has both kinds of operands!
876 tail_size = 1; // the imm8
877 break;
878
879 case 0xC4: // VEX_3bytes
880 case 0xC5: // VEX_2bytes
881 assert((UseAVX > 0), "shouldn't have VEX prefix");
882 assert(ip == inst+1, "no prefixes allowed");
883 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions
884 // but they have prefix 0x0F and processed when 0x0F processed above.
885 //
886 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES
887 // instructions (these instructions are not supported in 64-bit mode).
888 // To distinguish them bits [7:6] are set in the VEX second byte since
889 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set
890 // those VEX bits REX and vvvv bits are inverted.
891 //
892 // Fortunately C2 doesn't generate these instructions so we don't need
893 // to check for them in product version.
894
895 // Check second byte
896 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions"));
897
898 int vex_opcode;
899 // First byte
900 if ((0xFF & *inst) == VEX_3bytes) {
901 vex_opcode = VEX_OPCODE_MASK & *ip;
902 ip++; // third byte
903 is_64bit = ((VEX_W & *ip) == VEX_W);
904 } else {
905 vex_opcode = VEX_OPCODE_0F;
906 }
907 ip++; // opcode
908 // To find the end of instruction (which == end_pc_operand).
909 switch (vex_opcode) {
910 case VEX_OPCODE_0F:
911 switch (0xFF & *ip) {
912 case 0x70: // pshufd r, r/a, #8
913 case 0x71: // ps[rl|ra|ll]w r, #8
914 case 0x72: // ps[rl|ra|ll]d r, #8
915 case 0x73: // ps[rl|ra|ll]q r, #8
916 case 0xC2: // cmp[ps|pd|ss|sd] r, r, r/a, #8
917 case 0xC4: // pinsrw r, r, r/a, #8
918 case 0xC5: // pextrw r/a, r, #8
919 case 0xC6: // shufp[s|d] r, r, r/a, #8
920 tail_size = 1; // the imm8
921 break;
922 }
923 break;
924 case VEX_OPCODE_0F_3A:
925 tail_size = 1;
926 break;
927 }
928 ip++; // skip opcode
929 debug_only(has_disp32 = true); // has both kinds of operands!
930 break;
931
932 case 0x62: // EVEX_4bytes
933 assert(VM_Version::supports_evex(), "shouldn't have EVEX prefix");
934 assert(ip == inst+1, "no prefixes allowed");
935 // no EVEX collisions, all instructions that have 0x62 opcodes
936 // have EVEX versions and are subopcodes of 0x66
937 ip++; // skip P0 and exmaine W in P1
938 is_64bit = ((VEX_W & *ip) == VEX_W);
939 ip++; // move to P2
940 ip++; // skip P2, move to opcode
941 // To find the end of instruction (which == end_pc_operand).
942 switch (0xFF & *ip) {
943 case 0x22: // pinsrd r, r/a, #8
944 case 0x61: // pcmpestri r, r/a, #8
945 case 0x70: // pshufd r, r/a, #8
946 case 0x73: // psrldq r, #8
947 case 0x1f: // evpcmpd/evpcmpq
948 case 0x3f: // evpcmpb/evpcmpw
949 tail_size = 1; // the imm8
950 break;
951 default:
952 break;
953 }
954 ip++; // skip opcode
955 debug_only(has_disp32 = true); // has both kinds of operands!
956 break;
957
958 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
959 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
960 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a
961 case 0xDD: // fld_d a; fst_d a; fstp_d a
962 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a
963 case 0xDF: // fild_d a; fistp_d a
964 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a
965 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a
966 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a
967 debug_only(has_disp32 = true);
968 break;
969
970 case 0xE8: // call rdisp32
971 case 0xE9: // jmp rdisp32
972 if (which == end_pc_operand) return ip + 4;
973 assert(which == call32_operand, "call has no disp32 or imm");
974 return ip;
975
976 case 0xF0: // Lock
977 assert(os::is_MP(), "only on MP");
978 goto again_after_prefix;
979
980 case 0xF3: // For SSE
981 case 0xF2: // For SSE2
982 switch (0xFF & *ip++) {
983 case REX:
984 case REX_B:
985 case REX_X:
986 case REX_XB:
987 case REX_R:
988 case REX_RB:
989 case REX_RX:
990 case REX_RXB:
991 case REX_W:
992 case REX_WB:
993 case REX_WX:
994 case REX_WXB:
995 case REX_WR:
996 case REX_WRB:
997 case REX_WRX:
998 case REX_WRXB:
999 NOT_LP64(assert(false, "found 64bit prefix"));
1000 ip++;
1001 default:
1002 ip++;
1003 }
1004 debug_only(has_disp32 = true); // has both kinds of operands!
1005 break;
1006
1007 default:
1008 ShouldNotReachHere();
1009
1010 #undef REP8
1011 #undef REP16
1012 }
1013
1014 assert(which != call32_operand, "instruction is not a call, jmp, or jcc");
1015 #ifdef _LP64
1016 assert(which != imm_operand, "instruction is not a movq reg, imm64");
1017 #else
1018 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field");
1019 assert(which != imm_operand || has_disp32, "instruction has no imm32 field");
1020 #endif // LP64
1021 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field");
1022
1023 // parse the output of emit_operand
1024 int op2 = 0xFF & *ip++;
1025 int base = op2 & 0x07;
1026 int op3 = -1;
1027 const int b100 = 4;
1028 const int b101 = 5;
1029 if (base == b100 && (op2 >> 6) != 3) {
1030 op3 = 0xFF & *ip++;
1031 base = op3 & 0x07; // refetch the base
1032 }
1033 // now ip points at the disp (if any)
1034
1035 switch (op2 >> 6) {
1036 case 0:
1037 // [00 reg 100][ss index base]
1038 // [00 reg 100][00 100 esp]
1039 // [00 reg base]
1040 // [00 reg 100][ss index 101][disp32]
1041 // [00 reg 101] [disp32]
1042
1043 if (base == b101) {
1044 if (which == disp32_operand)
1045 return ip; // caller wants the disp32
1046 ip += 4; // skip the disp32
1047 }
1048 break;
1049
1050 case 1:
1051 // [01 reg 100][ss index base][disp8]
1052 // [01 reg 100][00 100 esp][disp8]
1053 // [01 reg base] [disp8]
1054 ip += 1; // skip the disp8
1055 break;
1056
1057 case 2:
1058 // [10 reg 100][ss index base][disp32]
1059 // [10 reg 100][00 100 esp][disp32]
1060 // [10 reg base] [disp32]
1061 if (which == disp32_operand)
1062 return ip; // caller wants the disp32
1063 ip += 4; // skip the disp32
1064 break;
1065
1066 case 3:
1067 // [11 reg base] (not a memory addressing mode)
1068 break;
1069 }
1070
1071 if (which == end_pc_operand) {
1072 return ip + tail_size;
1073 }
1074
1075 #ifdef _LP64
1076 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32");
1077 #else
1078 assert(which == imm_operand, "instruction has only an imm field");
1079 #endif // LP64
1080 return ip;
1081 }
1082
1083 address Assembler::locate_next_instruction(address inst) {
1084 // Secretly share code with locate_operand:
1085 return locate_operand(inst, end_pc_operand);
1086 }
1087
1088
1089 #ifdef ASSERT
1090 void Assembler::check_relocation(RelocationHolder const& rspec, int format) {
1091 address inst = inst_mark();
1092 assert(inst != NULL && inst < pc(), "must point to beginning of instruction");
1093 address opnd;
1094
1095 Relocation* r = rspec.reloc();
1096 if (r->type() == relocInfo::none) {
1097 return;
1098 } else if (r->is_call() || format == call32_operand) {
1099 // assert(format == imm32_operand, "cannot specify a nonzero format");
1100 opnd = locate_operand(inst, call32_operand);
1101 } else if (r->is_data()) {
1102 assert(format == imm_operand || format == disp32_operand
1103 LP64_ONLY(|| format == narrow_oop_operand), "format ok");
1104 opnd = locate_operand(inst, (WhichOperand)format);
1105 } else {
1106 assert(format == imm_operand, "cannot specify a format");
1107 return;
1108 }
1109 assert(opnd == pc(), "must put operand where relocs can find it");
1110 }
1111 #endif // ASSERT
1112
1113 void Assembler::emit_operand32(Register reg, Address adr) {
1114 assert(reg->encoding() < 8, "no extended registers");
1115 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1116 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1117 adr._rspec);
1118 }
1119
1120 void Assembler::emit_operand(Register reg, Address adr,
1121 int rip_relative_correction) {
1122 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1123 adr._rspec,
1124 rip_relative_correction);
1125 }
1126
1127 void Assembler::emit_operand(XMMRegister reg, Address adr) {
1128 if (adr.isxmmindex()) {
1129 emit_operand(reg, adr._base, adr._xmmindex, adr._scale, adr._disp, adr._rspec);
1130 } else {
1131 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1132 adr._rspec);
1133 }
1134 }
1135
1136 // MMX operations
1137 void Assembler::emit_operand(MMXRegister reg, Address adr) {
1138 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1139 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1140 }
1141
1142 // work around gcc (3.2.1-7a) bug
1143 void Assembler::emit_operand(Address adr, MMXRegister reg) {
1144 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1145 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1146 }
1147
1148
1149 void Assembler::emit_farith(int b1, int b2, int i) {
1150 assert(isByte(b1) && isByte(b2), "wrong opcode");
1151 assert(0 <= i && i < 8, "illegal stack offset");
1152 emit_int8(b1);
1153 emit_int8(b2 + i);
1154 }
1155
1156
1157 // Now the Assembler instructions (identical for 32/64 bits)
1158
1159 void Assembler::adcl(Address dst, int32_t imm32) {
1160 InstructionMark im(this);
1161 prefix(dst);
1162 emit_arith_operand(0x81, rdx, dst, imm32);
1163 }
1164
1165 void Assembler::adcl(Address dst, Register src) {
1166 InstructionMark im(this);
1167 prefix(dst, src);
1168 emit_int8(0x11);
1169 emit_operand(src, dst);
1170 }
1171
1172 void Assembler::adcl(Register dst, int32_t imm32) {
1173 prefix(dst);
1174 emit_arith(0x81, 0xD0, dst, imm32);
1175 }
1176
1177 void Assembler::adcl(Register dst, Address src) {
1178 InstructionMark im(this);
1179 prefix(src, dst);
1180 emit_int8(0x13);
1181 emit_operand(dst, src);
1182 }
1183
1184 void Assembler::adcl(Register dst, Register src) {
1185 (void) prefix_and_encode(dst->encoding(), src->encoding());
1186 emit_arith(0x13, 0xC0, dst, src);
1187 }
1188
1189 void Assembler::addl(Address dst, int32_t imm32) {
1190 InstructionMark im(this);
1191 prefix(dst);
1192 emit_arith_operand(0x81, rax, dst, imm32);
1193 }
1194
1195 void Assembler::addb(Address dst, int imm8) {
1196 InstructionMark im(this);
1197 prefix(dst);
1198 emit_int8((unsigned char)0x80);
1199 emit_operand(rax, dst, 1);
1200 emit_int8(imm8);
1201 }
1202
1203 void Assembler::addw(Register dst, Register src) {
1204 (void)prefix_and_encode(dst->encoding(), src->encoding());
1205 emit_arith(0x03, 0xC0, dst, src);
1206 }
1207
1208 void Assembler::addw(Address dst, int imm16) {
1209 InstructionMark im(this);
1210 emit_int8(0x66);
1211 prefix(dst);
1212 emit_int8((unsigned char)0x81);
1213 emit_operand(rax, dst, 2);
1214 emit_int16(imm16);
1215 }
1216
1217 void Assembler::addl(Address dst, Register src) {
1218 InstructionMark im(this);
1219 prefix(dst, src);
1220 emit_int8(0x01);
1221 emit_operand(src, dst);
1222 }
1223
1224 void Assembler::addl(Register dst, int32_t imm32) {
1225 prefix(dst);
1226 emit_arith(0x81, 0xC0, dst, imm32);
1227 }
1228
1229 void Assembler::addl(Register dst, Address src) {
1230 InstructionMark im(this);
1231 prefix(src, dst);
1232 emit_int8(0x03);
1233 emit_operand(dst, src);
1234 }
1235
1236 void Assembler::addl(Register dst, Register src) {
1237 (void) prefix_and_encode(dst->encoding(), src->encoding());
1238 emit_arith(0x03, 0xC0, dst, src);
1239 }
1240
1241 void Assembler::addr_nop_4() {
1242 assert(UseAddressNop, "no CPU support");
1243 // 4 bytes: NOP DWORD PTR [EAX+0]
1244 emit_int8(0x0F);
1245 emit_int8(0x1F);
1246 emit_int8(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
1247 emit_int8(0); // 8-bits offset (1 byte)
1248 }
1249
1250 void Assembler::addr_nop_5() {
1251 assert(UseAddressNop, "no CPU support");
1252 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
1253 emit_int8(0x0F);
1254 emit_int8(0x1F);
1255 emit_int8(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
1256 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1257 emit_int8(0); // 8-bits offset (1 byte)
1258 }
1259
1260 void Assembler::addr_nop_7() {
1261 assert(UseAddressNop, "no CPU support");
1262 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
1263 emit_int8(0x0F);
1264 emit_int8(0x1F);
1265 emit_int8((unsigned char)0x80);
1266 // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
1267 emit_int32(0); // 32-bits offset (4 bytes)
1268 }
1269
1270 void Assembler::addr_nop_8() {
1271 assert(UseAddressNop, "no CPU support");
1272 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
1273 emit_int8(0x0F);
1274 emit_int8(0x1F);
1275 emit_int8((unsigned char)0x84);
1276 // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
1277 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1278 emit_int32(0); // 32-bits offset (4 bytes)
1279 }
1280
1281 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
1282 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1283 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1284 attributes.set_rex_vex_w_reverted();
1285 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1286 emit_int8(0x58);
1287 emit_int8((unsigned char)(0xC0 | encode));
1288 }
1289
1290 void Assembler::addsd(XMMRegister dst, Address src) {
1291 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1292 InstructionMark im(this);
1293 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1294 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1295 attributes.set_rex_vex_w_reverted();
1296 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1297 emit_int8(0x58);
1298 emit_operand(dst, src);
1299 }
1300
1301 void Assembler::addss(XMMRegister dst, XMMRegister src) {
1302 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1303 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1304 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1305 emit_int8(0x58);
1306 emit_int8((unsigned char)(0xC0 | encode));
1307 }
1308
1309 void Assembler::addss(XMMRegister dst, Address src) {
1310 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1311 InstructionMark im(this);
1312 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1313 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1314 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1315 emit_int8(0x58);
1316 emit_operand(dst, src);
1317 }
1318
1319 void Assembler::aesdec(XMMRegister dst, Address src) {
1320 assert(VM_Version::supports_aes(), "");
1321 InstructionMark im(this);
1322 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1323 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1324 emit_int8((unsigned char)0xDE);
1325 emit_operand(dst, src);
1326 }
1327
1328 void Assembler::aesdec(XMMRegister dst, XMMRegister src) {
1329 assert(VM_Version::supports_aes(), "");
1330 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1331 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1332 emit_int8((unsigned char)0xDE);
1333 emit_int8(0xC0 | encode);
1334 }
1335
1336 void Assembler::vaesdec(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1337 assert(VM_Version::supports_vaes(), "");
1338 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1339 attributes.set_is_evex_instruction();
1340 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1341 emit_int8((unsigned char)0xDE);
1342 emit_int8((unsigned char)(0xC0 | encode));
1343 }
1344
1345
1346 void Assembler::aesdeclast(XMMRegister dst, Address src) {
1347 assert(VM_Version::supports_aes(), "");
1348 InstructionMark im(this);
1349 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1350 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1351 emit_int8((unsigned char)0xDF);
1352 emit_operand(dst, src);
1353 }
1354
1355 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) {
1356 assert(VM_Version::supports_aes(), "");
1357 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1358 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1359 emit_int8((unsigned char)0xDF);
1360 emit_int8((unsigned char)(0xC0 | encode));
1361 }
1362
1363 void Assembler::vaesdeclast(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1364 assert(VM_Version::supports_vaes(), "");
1365 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1366 attributes.set_is_evex_instruction();
1367 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1368 emit_int8((unsigned char)0xDF);
1369 emit_int8((unsigned char)(0xC0 | encode));
1370 }
1371
1372 void Assembler::aesenc(XMMRegister dst, Address src) {
1373 assert(VM_Version::supports_aes(), "");
1374 InstructionMark im(this);
1375 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1376 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1377 emit_int8((unsigned char)0xDC);
1378 emit_operand(dst, src);
1379 }
1380
1381 void Assembler::aesenc(XMMRegister dst, XMMRegister src) {
1382 assert(VM_Version::supports_aes(), "");
1383 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1384 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1385 emit_int8((unsigned char)0xDC);
1386 emit_int8(0xC0 | encode);
1387 }
1388
1389 void Assembler::aesenclast(XMMRegister dst, Address src) {
1390 assert(VM_Version::supports_aes(), "");
1391 InstructionMark im(this);
1392 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1393 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1394 emit_int8((unsigned char)0xDD);
1395 emit_operand(dst, src);
1396 }
1397
1398 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) {
1399 assert(VM_Version::supports_aes(), "");
1400 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1401 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1402 emit_int8((unsigned char)0xDD);
1403 emit_int8((unsigned char)(0xC0 | encode));
1404 }
1405
1406 void Assembler::andw(Register dst, Register src) {
1407 (void)prefix_and_encode(dst->encoding(), src->encoding());
1408 emit_arith(0x23, 0xC0, dst, src);
1409 }
1410
1411 void Assembler::andl(Address dst, int32_t imm32) {
1412 InstructionMark im(this);
1413 prefix(dst);
1414 emit_int8((unsigned char)0x81);
1415 emit_operand(rsp, dst, 4);
1416 emit_int32(imm32);
1417 }
1418
1419 void Assembler::andl(Register dst, int32_t imm32) {
1420 prefix(dst);
1421 emit_arith(0x81, 0xE0, dst, imm32);
1422 }
1423
1424 void Assembler::andl(Register dst, Address src) {
1425 InstructionMark im(this);
1426 prefix(src, dst);
1427 emit_int8(0x23);
1428 emit_operand(dst, src);
1429 }
1430
1431 void Assembler::andl(Register dst, Register src) {
1432 (void) prefix_and_encode(dst->encoding(), src->encoding());
1433 emit_arith(0x23, 0xC0, dst, src);
1434 }
1435
1436 void Assembler::andnl(Register dst, Register src1, Register src2) {
1437 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1438 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1439 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1440 emit_int8((unsigned char)0xF2);
1441 emit_int8((unsigned char)(0xC0 | encode));
1442 }
1443
1444 void Assembler::andnl(Register dst, Register src1, Address src2) {
1445 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1446 InstructionMark im(this);
1447 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1448 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1449 emit_int8((unsigned char)0xF2);
1450 emit_operand(dst, src2);
1451 }
1452
1453 void Assembler::bsfl(Register dst, Register src) {
1454 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1455 emit_int8(0x0F);
1456 emit_int8((unsigned char)0xBC);
1457 emit_int8((unsigned char)(0xC0 | encode));
1458 }
1459
1460 void Assembler::bsrl(Register dst, Register src) {
1461 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1462 emit_int8(0x0F);
1463 emit_int8((unsigned char)0xBD);
1464 emit_int8((unsigned char)(0xC0 | encode));
1465 }
1466
1467 void Assembler::bswapl(Register reg) { // bswap
1468 int encode = prefix_and_encode(reg->encoding());
1469 emit_int8(0x0F);
1470 emit_int8((unsigned char)(0xC8 | encode));
1471 }
1472
1473 void Assembler::blsil(Register dst, Register src) {
1474 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1475 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1476 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1477 emit_int8((unsigned char)0xF3);
1478 emit_int8((unsigned char)(0xC0 | encode));
1479 }
1480
1481 void Assembler::blsil(Register dst, Address src) {
1482 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1483 InstructionMark im(this);
1484 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1485 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1486 emit_int8((unsigned char)0xF3);
1487 emit_operand(rbx, src);
1488 }
1489
1490 void Assembler::blsmskl(Register dst, Register src) {
1491 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1492 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1493 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1494 emit_int8((unsigned char)0xF3);
1495 emit_int8((unsigned char)(0xC0 | encode));
1496 }
1497
1498 void Assembler::blsmskl(Register dst, Address src) {
1499 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1500 InstructionMark im(this);
1501 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1502 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1503 emit_int8((unsigned char)0xF3);
1504 emit_operand(rdx, src);
1505 }
1506
1507 void Assembler::blsrl(Register dst, Register src) {
1508 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1509 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1510 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1511 emit_int8((unsigned char)0xF3);
1512 emit_int8((unsigned char)(0xC0 | encode));
1513 }
1514
1515 void Assembler::blsrl(Register dst, Address src) {
1516 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1517 InstructionMark im(this);
1518 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1519 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1520 emit_int8((unsigned char)0xF3);
1521 emit_operand(rcx, src);
1522 }
1523
1524 void Assembler::call(Label& L, relocInfo::relocType rtype) {
1525 // suspect disp32 is always good
1526 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
1527
1528 if (L.is_bound()) {
1529 const int long_size = 5;
1530 int offs = (int)( target(L) - pc() );
1531 assert(offs <= 0, "assembler error");
1532 InstructionMark im(this);
1533 // 1110 1000 #32-bit disp
1534 emit_int8((unsigned char)0xE8);
1535 emit_data(offs - long_size, rtype, operand);
1536 } else {
1537 InstructionMark im(this);
1538 // 1110 1000 #32-bit disp
1539 L.add_patch_at(code(), locator());
1540
1541 emit_int8((unsigned char)0xE8);
1542 emit_data(int(0), rtype, operand);
1543 }
1544 }
1545
1546 void Assembler::call(Register dst) {
1547 int encode = prefix_and_encode(dst->encoding());
1548 emit_int8((unsigned char)0xFF);
1549 emit_int8((unsigned char)(0xD0 | encode));
1550 }
1551
1552
1553 void Assembler::call(Address adr) {
1554 InstructionMark im(this);
1555 prefix(adr);
1556 emit_int8((unsigned char)0xFF);
1557 emit_operand(rdx, adr);
1558 }
1559
1560 void Assembler::call_literal(address entry, RelocationHolder const& rspec) {
1561 InstructionMark im(this);
1562 emit_int8((unsigned char)0xE8);
1563 intptr_t disp = entry - (pc() + sizeof(int32_t));
1564 // Entry is NULL in case of a scratch emit.
1565 assert(entry == NULL || is_simm32(disp), "disp=" INTPTR_FORMAT " must be 32bit offset (call2)", disp);
1566 // Technically, should use call32_operand, but this format is
1567 // implied by the fact that we're emitting a call instruction.
1568
1569 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand);
1570 emit_data((int) disp, rspec, operand);
1571 }
1572
1573 void Assembler::cdql() {
1574 emit_int8((unsigned char)0x99);
1575 }
1576
1577 void Assembler::cld() {
1578 emit_int8((unsigned char)0xFC);
1579 }
1580
1581 void Assembler::cmovl(Condition cc, Register dst, Register src) {
1582 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1583 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1584 emit_int8(0x0F);
1585 emit_int8(0x40 | cc);
1586 emit_int8((unsigned char)(0xC0 | encode));
1587 }
1588
1589
1590 void Assembler::cmovl(Condition cc, Register dst, Address src) {
1591 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1592 prefix(src, dst);
1593 emit_int8(0x0F);
1594 emit_int8(0x40 | cc);
1595 emit_operand(dst, src);
1596 }
1597
1598 void Assembler::cmpb(Address dst, int imm8) {
1599 InstructionMark im(this);
1600 prefix(dst);
1601 emit_int8((unsigned char)0x80);
1602 emit_operand(rdi, dst, 1);
1603 emit_int8(imm8);
1604 }
1605
1606 void Assembler::cmpl(Address dst, int32_t imm32) {
1607 InstructionMark im(this);
1608 prefix(dst);
1609 emit_int8((unsigned char)0x81);
1610 emit_operand(rdi, dst, 4);
1611 emit_int32(imm32);
1612 }
1613
1614 void Assembler::cmpl(Register dst, int32_t imm32) {
1615 prefix(dst);
1616 emit_arith(0x81, 0xF8, dst, imm32);
1617 }
1618
1619 void Assembler::cmpl(Register dst, Register src) {
1620 (void) prefix_and_encode(dst->encoding(), src->encoding());
1621 emit_arith(0x3B, 0xC0, dst, src);
1622 }
1623
1624 void Assembler::cmpl(Register dst, Address src) {
1625 InstructionMark im(this);
1626 prefix(src, dst);
1627 emit_int8((unsigned char)0x3B);
1628 emit_operand(dst, src);
1629 }
1630
1631 void Assembler::cmpw(Address dst, int imm16) {
1632 InstructionMark im(this);
1633 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers");
1634 emit_int8(0x66);
1635 emit_int8((unsigned char)0x81);
1636 emit_operand(rdi, dst, 2);
1637 emit_int16(imm16);
1638 }
1639
1640 // The 32-bit cmpxchg compares the value at adr with the contents of rax,
1641 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1642 // The ZF is set if the compared values were equal, and cleared otherwise.
1643 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg
1644 InstructionMark im(this);
1645 prefix(adr, reg);
1646 emit_int8(0x0F);
1647 emit_int8((unsigned char)0xB1);
1648 emit_operand(reg, adr);
1649 }
1650
1651 // The 8-bit cmpxchg compares the value at adr with the contents of rax,
1652 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1653 // The ZF is set if the compared values were equal, and cleared otherwise.
1654 void Assembler::cmpxchgb(Register reg, Address adr) { // cmpxchg
1655 InstructionMark im(this);
1656 prefix(adr, reg, true);
1657 emit_int8(0x0F);
1658 emit_int8((unsigned char)0xB0);
1659 emit_operand(reg, adr);
1660 }
1661
1662 void Assembler::comisd(XMMRegister dst, Address src) {
1663 // NOTE: dbx seems to decode this as comiss even though the
1664 // 0x66 is there. Strangly ucomisd comes out correct
1665 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1666 InstructionMark im(this);
1667 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);;
1668 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1669 attributes.set_rex_vex_w_reverted();
1670 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1671 emit_int8(0x2F);
1672 emit_operand(dst, src);
1673 }
1674
1675 void Assembler::comisd(XMMRegister dst, XMMRegister src) {
1676 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1677 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1678 attributes.set_rex_vex_w_reverted();
1679 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1680 emit_int8(0x2F);
1681 emit_int8((unsigned char)(0xC0 | encode));
1682 }
1683
1684 void Assembler::comiss(XMMRegister dst, Address src) {
1685 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1686 InstructionMark im(this);
1687 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1688 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1689 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1690 emit_int8(0x2F);
1691 emit_operand(dst, src);
1692 }
1693
1694 void Assembler::comiss(XMMRegister dst, XMMRegister src) {
1695 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1696 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1697 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1698 emit_int8(0x2F);
1699 emit_int8((unsigned char)(0xC0 | encode));
1700 }
1701
1702 void Assembler::cpuid() {
1703 emit_int8(0x0F);
1704 emit_int8((unsigned char)0xA2);
1705 }
1706
1707 // Opcode / Instruction Op / En 64 - Bit Mode Compat / Leg Mode Description Implemented
1708 // F2 0F 38 F0 / r CRC32 r32, r / m8 RM Valid Valid Accumulate CRC32 on r / m8. v
1709 // F2 REX 0F 38 F0 / r CRC32 r32, r / m8* RM Valid N.E. Accumulate CRC32 on r / m8. -
1710 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E. Accumulate CRC32 on r / m8. -
1711 //
1712 // F2 0F 38 F1 / r CRC32 r32, r / m16 RM Valid Valid Accumulate CRC32 on r / m16. v
1713 //
1714 // F2 0F 38 F1 / r CRC32 r32, r / m32 RM Valid Valid Accumulate CRC32 on r / m32. v
1715 //
1716 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E. Accumulate CRC32 on r / m64. v
1717 void Assembler::crc32(Register crc, Register v, int8_t sizeInBytes) {
1718 assert(VM_Version::supports_sse4_2(), "");
1719 int8_t w = 0x01;
1720 Prefix p = Prefix_EMPTY;
1721
1722 emit_int8((int8_t)0xF2);
1723 switch (sizeInBytes) {
1724 case 1:
1725 w = 0;
1726 break;
1727 case 2:
1728 case 4:
1729 break;
1730 LP64_ONLY(case 8:)
1731 // This instruction is not valid in 32 bits
1732 // Note:
1733 // http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
1734 //
1735 // Page B - 72 Vol. 2C says
1736 // qwreg2 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : 11 qwreg1 qwreg2
1737 // mem64 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : mod qwreg r / m
1738 // F0!!!
1739 // while 3 - 208 Vol. 2A
1740 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E.Accumulate CRC32 on r / m64.
1741 //
1742 // the 0 on a last bit is reserved for a different flavor of this instruction :
1743 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E.Accumulate CRC32 on r / m8.
1744 p = REX_W;
1745 break;
1746 default:
1747 assert(0, "Unsupported value for a sizeInBytes argument");
1748 break;
1749 }
1750 LP64_ONLY(prefix(crc, v, p);)
1751 emit_int8((int8_t)0x0F);
1752 emit_int8(0x38);
1753 emit_int8((int8_t)(0xF0 | w));
1754 emit_int8(0xC0 | ((crc->encoding() & 0x7) << 3) | (v->encoding() & 7));
1755 }
1756
1757 void Assembler::crc32(Register crc, Address adr, int8_t sizeInBytes) {
1758 assert(VM_Version::supports_sse4_2(), "");
1759 InstructionMark im(this);
1760 int8_t w = 0x01;
1761 Prefix p = Prefix_EMPTY;
1762
1763 emit_int8((int8_t)0xF2);
1764 switch (sizeInBytes) {
1765 case 1:
1766 w = 0;
1767 break;
1768 case 2:
1769 case 4:
1770 break;
1771 LP64_ONLY(case 8:)
1772 // This instruction is not valid in 32 bits
1773 p = REX_W;
1774 break;
1775 default:
1776 assert(0, "Unsupported value for a sizeInBytes argument");
1777 break;
1778 }
1779 LP64_ONLY(prefix(crc, adr, p);)
1780 emit_int8((int8_t)0x0F);
1781 emit_int8(0x38);
1782 emit_int8((int8_t)(0xF0 | w));
1783 emit_operand(crc, adr);
1784 }
1785
1786 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
1787 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1788 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
1789 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1790 emit_int8((unsigned char)0xE6);
1791 emit_int8((unsigned char)(0xC0 | encode));
1792 }
1793
1794 void Assembler::vcvtdq2pd(XMMRegister dst, XMMRegister src, int vector_len) {
1795 assert(vector_len <= AVX_256bit ? VM_Version::supports_avx() : VM_Version::supports_evex(), "");
1796 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1797 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1798 emit_int8((unsigned char)0xE6);
1799 emit_int8((unsigned char)(0xC0 | encode));
1800 }
1801
1802 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
1803 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1804 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
1805 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1806 emit_int8(0x5B);
1807 emit_int8((unsigned char)(0xC0 | encode));
1808 }
1809
1810 void Assembler::vcvtdq2ps(XMMRegister dst, XMMRegister src, int vector_len) {
1811 assert(vector_len <= AVX_256bit ? VM_Version::supports_avx() : VM_Version::supports_evex(), "");
1812 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
1813 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1814 emit_int8(0x5B);
1815 emit_int8((unsigned char)(0xC0 | encode));
1816 }
1817
1818 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
1819 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1820 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1821 attributes.set_rex_vex_w_reverted();
1822 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1823 emit_int8(0x5A);
1824 emit_int8((unsigned char)(0xC0 | encode));
1825 }
1826
1827 void Assembler::cvtsd2ss(XMMRegister dst, Address src) {
1828 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1829 InstructionMark im(this);
1830 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1831 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1832 attributes.set_rex_vex_w_reverted();
1833 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1834 emit_int8(0x5A);
1835 emit_operand(dst, src);
1836 }
1837
1838 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
1839 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1840 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1841 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1842 emit_int8(0x2A);
1843 emit_int8((unsigned char)(0xC0 | encode));
1844 }
1845
1846 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) {
1847 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1848 InstructionMark im(this);
1849 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1850 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1851 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1852 emit_int8(0x2A);
1853 emit_operand(dst, src);
1854 }
1855
1856 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
1857 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1858 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1859 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1860 emit_int8(0x2A);
1861 emit_int8((unsigned char)(0xC0 | encode));
1862 }
1863
1864 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) {
1865 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1866 InstructionMark im(this);
1867 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1868 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1869 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1870 emit_int8(0x2A);
1871 emit_operand(dst, src);
1872 }
1873
1874 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
1875 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1876 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1877 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1878 emit_int8(0x2A);
1879 emit_int8((unsigned char)(0xC0 | encode));
1880 }
1881
1882 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
1883 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1884 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1885 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1886 emit_int8(0x5A);
1887 emit_int8((unsigned char)(0xC0 | encode));
1888 }
1889
1890 void Assembler::cvtss2sd(XMMRegister dst, Address src) {
1891 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1892 InstructionMark im(this);
1893 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1894 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1895 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1896 emit_int8(0x5A);
1897 emit_operand(dst, src);
1898 }
1899
1900
1901 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
1902 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1903 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1904 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1905 emit_int8(0x2C);
1906 emit_int8((unsigned char)(0xC0 | encode));
1907 }
1908
1909 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
1910 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1911 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1912 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1913 emit_int8(0x2C);
1914 emit_int8((unsigned char)(0xC0 | encode));
1915 }
1916
1917 void Assembler::cvttpd2dq(XMMRegister dst, XMMRegister src) {
1918 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1919 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
1920 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
1921 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1922 emit_int8((unsigned char)0xE6);
1923 emit_int8((unsigned char)(0xC0 | encode));
1924 }
1925
1926 void Assembler::vcvtps2pd(XMMRegister dst, XMMRegister src, int vector_len) {
1927 assert(UseAVX > 0 && (vector_len == AVX_128bit || vector_len == AVX_256bit), "");
1928 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1929 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1930 emit_int8((unsigned char)0x5A);
1931 emit_int8((unsigned char)(0xC0 | encode));
1932 }
1933
1934 void Assembler::evcvtps2pd(XMMRegister dst, XMMRegister src, int vector_len) {
1935 assert(UseAVX > 2, "");
1936 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
1937 attributes.set_is_evex_instruction();
1938 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1939 emit_int8((unsigned char)0x5A);
1940 emit_int8((unsigned char)(0xC0 | encode));
1941 }
1942
1943 void Assembler::pabsb(XMMRegister dst, XMMRegister src) {
1944 assert(VM_Version::supports_ssse3(), "");
1945 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1946 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1947 emit_int8(0x1C);
1948 emit_int8((unsigned char)(0xC0 | encode));
1949 }
1950
1951 void Assembler::pabsw(XMMRegister dst, XMMRegister src) {
1952 assert(VM_Version::supports_ssse3(), "");
1953 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1954 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1955 emit_int8(0x1D);
1956 emit_int8((unsigned char)(0xC0 | encode));
1957 }
1958
1959 void Assembler::vcvtpd2ps(XMMRegister dst, XMMRegister src, int vector_len) {
1960 assert(UseAVX > 0 && (vector_len == AVX_128bit || vector_len == AVX_256bit), "");
1961 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1962 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1963 emit_int8((unsigned char)0x5A);
1964 emit_int8((unsigned char)(0xC0 | encode));
1965 }
1966
1967 void Assembler::evcvtpd2ps(XMMRegister dst, XMMRegister src, int vector_len) {
1968 assert(UseAVX > 2, "");
1969 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
1970 attributes.set_is_evex_instruction();
1971 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1972 emit_int8((unsigned char)0x5A);
1973 emit_int8((unsigned char)(0xC0 | encode));
1974 }
1975
1976 void Assembler::evcvtqq2ps(XMMRegister dst, XMMRegister src, int vector_len) {
1977 assert(UseAVX > 2 && VM_Version::supports_avx512dq(), "");
1978 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1979 attributes.set_is_evex_instruction();
1980 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1981 emit_int8((unsigned char)0x5B);
1982 emit_int8((unsigned char)(0xC0 | encode));
1983 }
1984
1985 void Assembler::evcvtqq2pd(XMMRegister dst, XMMRegister src, int vector_len) {
1986 assert(UseAVX > 2 && VM_Version::supports_avx512dq(), "");
1987 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1988 attributes.set_is_evex_instruction();
1989 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1990 emit_int8((unsigned char)0xE6);
1991 emit_int8((unsigned char)(0xC0 | encode));
1992 }
1993
1994 void Assembler::evpmovwb(XMMRegister dst, XMMRegister src, int vector_len) {
1995 assert(UseAVX > 2, "");
1996 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1997 attributes.set_is_evex_instruction();
1998 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
1999 emit_int8((unsigned char)0x30);
2000 emit_int8((unsigned char)(0xC0 | encode));
2001 }
2002
2003 void Assembler::evpmovdw(XMMRegister dst, XMMRegister src, int vector_len) {
2004 assert(UseAVX > 2, "");
2005 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2006 attributes.set_is_evex_instruction();
2007 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
2008 emit_int8((unsigned char)0x33);
2009 emit_int8((unsigned char)(0xC0 | encode));
2010 }
2011
2012 void Assembler::evpmovdb(XMMRegister dst, XMMRegister src, int vector_len) {
2013 assert(UseAVX > 2, "");
2014 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2015 attributes.set_is_evex_instruction();
2016 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
2017 emit_int8((unsigned char)0x31);
2018 emit_int8((unsigned char)(0xC0 | encode));
2019 }
2020
2021 void Assembler::evpmovqd(XMMRegister dst, XMMRegister src, int vector_len) {
2022 assert(UseAVX > 2, "");
2023 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2024 attributes.set_is_evex_instruction();
2025 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
2026 emit_int8((unsigned char)0x35);
2027 emit_int8((unsigned char)(0xC0 | encode));
2028 }
2029
2030 void Assembler::evpmovqb(XMMRegister dst, XMMRegister src, int vector_len) {
2031 assert(UseAVX > 2, "");
2032 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2033 attributes.set_is_evex_instruction();
2034 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
2035 emit_int8((unsigned char)0x32);
2036 emit_int8((unsigned char)(0xC0 | encode));
2037 }
2038
2039 void Assembler::evpmovqw(XMMRegister dst, XMMRegister src, int vector_len) {
2040 assert(UseAVX > 2, "");
2041 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2042 attributes.set_is_evex_instruction();
2043 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
2044 emit_int8((unsigned char)0x34);
2045 emit_int8((unsigned char)(0xC0 | encode));
2046 }
2047
2048 void Assembler::pabsd(XMMRegister dst, XMMRegister src) {
2049 assert(VM_Version::supports_ssse3(), "");
2050 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2051 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
2052 emit_int8(0x1E);
2053 emit_int8((unsigned char)(0xC0 | encode));
2054 }
2055
2056 void Assembler::vpabsb(XMMRegister dst, XMMRegister src, int vector_len) {
2057 assert(UseAVX > 0 && (vector_len == AVX_128bit || vector_len == AVX_256bit), "");
2058 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2059 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
2060 emit_int8((unsigned char)0x1C);
2061 emit_int8((unsigned char)(0xC0 | encode));
2062 }
2063
2064 void Assembler::vpabsw(XMMRegister dst, XMMRegister src, int vector_len) {
2065 assert(UseAVX > 0 && (vector_len == AVX_128bit || vector_len == AVX_256bit), "");
2066 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2067 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
2068 emit_int8((unsigned char)0x1D);
2069 emit_int8((unsigned char)(0xC0 | encode));
2070 }
2071
2072 void Assembler::vpabsd(XMMRegister dst, XMMRegister src, int vector_len) {
2073 assert(UseAVX > 0 && (vector_len == AVX_128bit || vector_len == AVX_256bit), "");
2074 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2075 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
2076 emit_int8((unsigned char)0x1E);
2077 emit_int8((unsigned char)(0xC0 | encode));
2078 }
2079
2080 void Assembler::evpabsb(XMMRegister dst, XMMRegister src, int vector_len) {
2081 assert(UseAVX > 2, "");
2082 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2083 attributes.set_is_evex_instruction();
2084 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
2085 emit_int8((unsigned char)0x1C);
2086 emit_int8((unsigned char)(0xC0 | encode));
2087 }
2088
2089 void Assembler::evpabsw(XMMRegister dst, XMMRegister src, int vector_len) {
2090 assert(UseAVX > 2, "");
2091 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2092 attributes.set_is_evex_instruction();
2093 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
2094 emit_int8((unsigned char)0x1D);
2095 emit_int8((unsigned char)(0xC0 | encode));
2096 }
2097
2098 void Assembler::evpabsd(XMMRegister dst, XMMRegister src, int vector_len) {
2099 assert(UseAVX > 2, "");
2100 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2101 attributes.set_is_evex_instruction();
2102 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
2103 emit_int8((unsigned char)0x1E);
2104 emit_int8((unsigned char)(0xC0 | encode));
2105 }
2106
2107 void Assembler::evpabsq(XMMRegister dst, XMMRegister src, int vector_len) {
2108 assert(UseAVX > 2, "");
2109 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2110 attributes.set_is_evex_instruction();
2111 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
2112 emit_int8((unsigned char)0x1F);
2113 emit_int8((unsigned char)(0xC0 | encode));
2114 }
2115
2116 void Assembler::decl(Address dst) {
2117 // Don't use it directly. Use MacroAssembler::decrement() instead.
2118 InstructionMark im(this);
2119 prefix(dst);
2120 emit_int8((unsigned char)0xFF);
2121 emit_operand(rcx, dst);
2122 }
2123
2124 void Assembler::divsd(XMMRegister dst, Address src) {
2125 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2126 InstructionMark im(this);
2127 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2128 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2129 attributes.set_rex_vex_w_reverted();
2130 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2131 emit_int8(0x5E);
2132 emit_operand(dst, src);
2133 }
2134
2135 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
2136 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2137 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2138 attributes.set_rex_vex_w_reverted();
2139 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2140 emit_int8(0x5E);
2141 emit_int8((unsigned char)(0xC0 | encode));
2142 }
2143
2144 void Assembler::divss(XMMRegister dst, Address src) {
2145 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2146 InstructionMark im(this);
2147 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2148 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2149 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2150 emit_int8(0x5E);
2151 emit_operand(dst, src);
2152 }
2153
2154 void Assembler::divss(XMMRegister dst, XMMRegister src) {
2155 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2156 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2157 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2158 emit_int8(0x5E);
2159 emit_int8((unsigned char)(0xC0 | encode));
2160 }
2161
2162 void Assembler::emms() {
2163 NOT_LP64(assert(VM_Version::supports_mmx(), ""));
2164 emit_int8(0x0F);
2165 emit_int8(0x77);
2166 }
2167
2168 void Assembler::hlt() {
2169 emit_int8((unsigned char)0xF4);
2170 }
2171
2172 void Assembler::idivl(Register src) {
2173 int encode = prefix_and_encode(src->encoding());
2174 emit_int8((unsigned char)0xF7);
2175 emit_int8((unsigned char)(0xF8 | encode));
2176 }
2177
2178 void Assembler::divl(Register src) { // Unsigned
2179 int encode = prefix_and_encode(src->encoding());
2180 emit_int8((unsigned char)0xF7);
2181 emit_int8((unsigned char)(0xF0 | encode));
2182 }
2183
2184 void Assembler::imull(Register src) {
2185 int encode = prefix_and_encode(src->encoding());
2186 emit_int8((unsigned char)0xF7);
2187 emit_int8((unsigned char)(0xE8 | encode));
2188 }
2189
2190 void Assembler::imull(Register dst, Register src) {
2191 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2192 emit_int8(0x0F);
2193 emit_int8((unsigned char)0xAF);
2194 emit_int8((unsigned char)(0xC0 | encode));
2195 }
2196
2197
2198 void Assembler::imull(Register dst, Register src, int value) {
2199 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2200 if (is8bit(value)) {
2201 emit_int8(0x6B);
2202 emit_int8((unsigned char)(0xC0 | encode));
2203 emit_int8(value & 0xFF);
2204 } else {
2205 emit_int8(0x69);
2206 emit_int8((unsigned char)(0xC0 | encode));
2207 emit_int32(value);
2208 }
2209 }
2210
2211 void Assembler::imull(Register dst, Address src) {
2212 InstructionMark im(this);
2213 prefix(src, dst);
2214 emit_int8(0x0F);
2215 emit_int8((unsigned char) 0xAF);
2216 emit_operand(dst, src);
2217 }
2218
2219
2220 void Assembler::incl(Address dst) {
2221 // Don't use it directly. Use MacroAssembler::increment() instead.
2222 InstructionMark im(this);
2223 prefix(dst);
2224 emit_int8((unsigned char)0xFF);
2225 emit_operand(rax, dst);
2226 }
2227
2228 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) {
2229 InstructionMark im(this);
2230 assert((0 <= cc) && (cc < 16), "illegal cc");
2231 if (L.is_bound()) {
2232 address dst = target(L);
2233 assert(dst != NULL, "jcc most probably wrong");
2234
2235 const int short_size = 2;
2236 const int long_size = 6;
2237 intptr_t offs = (intptr_t)dst - (intptr_t)pc();
2238 if (maybe_short && is8bit(offs - short_size)) {
2239 // 0111 tttn #8-bit disp
2240 emit_int8(0x70 | cc);
2241 emit_int8((offs - short_size) & 0xFF);
2242 } else {
2243 // 0000 1111 1000 tttn #32-bit disp
2244 assert(is_simm32(offs - long_size),
2245 "must be 32bit offset (call4)");
2246 emit_int8(0x0F);
2247 emit_int8((unsigned char)(0x80 | cc));
2248 emit_int32(offs - long_size);
2249 }
2250 } else {
2251 // Note: could eliminate cond. jumps to this jump if condition
2252 // is the same however, seems to be rather unlikely case.
2253 // Note: use jccb() if label to be bound is very close to get
2254 // an 8-bit displacement
2255 L.add_patch_at(code(), locator());
2256 emit_int8(0x0F);
2257 emit_int8((unsigned char)(0x80 | cc));
2258 emit_int32(0);
2259 }
2260 }
2261
2262 void Assembler::jccb_0(Condition cc, Label& L, const char* file, int line) {
2263 if (L.is_bound()) {
2264 const int short_size = 2;
2265 address entry = target(L);
2266 #ifdef ASSERT
2267 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
2268 intptr_t delta = short_branch_delta();
2269 if (delta != 0) {
2270 dist += (dist < 0 ? (-delta) :delta);
2271 }
2272 assert(is8bit(dist), "Dispacement too large for a short jmp at %s:%d", file, line);
2273 #endif
2274 intptr_t offs = (intptr_t)entry - (intptr_t)pc();
2275 // 0111 tttn #8-bit disp
2276 emit_int8(0x70 | cc);
2277 emit_int8((offs - short_size) & 0xFF);
2278 } else {
2279 InstructionMark im(this);
2280 L.add_patch_at(code(), locator(), file, line);
2281 emit_int8(0x70 | cc);
2282 emit_int8(0);
2283 }
2284 }
2285
2286 void Assembler::jmp(Address adr) {
2287 InstructionMark im(this);
2288 prefix(adr);
2289 emit_int8((unsigned char)0xFF);
2290 emit_operand(rsp, adr);
2291 }
2292
2293 void Assembler::jmp(Label& L, bool maybe_short) {
2294 if (L.is_bound()) {
2295 address entry = target(L);
2296 assert(entry != NULL, "jmp most probably wrong");
2297 InstructionMark im(this);
2298 const int short_size = 2;
2299 const int long_size = 5;
2300 intptr_t offs = entry - pc();
2301 if (maybe_short && is8bit(offs - short_size)) {
2302 emit_int8((unsigned char)0xEB);
2303 emit_int8((offs - short_size) & 0xFF);
2304 } else {
2305 emit_int8((unsigned char)0xE9);
2306 emit_int32(offs - long_size);
2307 }
2308 } else {
2309 // By default, forward jumps are always 32-bit displacements, since
2310 // we can't yet know where the label will be bound. If you're sure that
2311 // the forward jump will not run beyond 256 bytes, use jmpb to
2312 // force an 8-bit displacement.
2313 InstructionMark im(this);
2314 L.add_patch_at(code(), locator());
2315 emit_int8((unsigned char)0xE9);
2316 emit_int32(0);
2317 }
2318 }
2319
2320 void Assembler::jmp(Register entry) {
2321 int encode = prefix_and_encode(entry->encoding());
2322 emit_int8((unsigned char)0xFF);
2323 emit_int8((unsigned char)(0xE0 | encode));
2324 }
2325
2326 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
2327 InstructionMark im(this);
2328 emit_int8((unsigned char)0xE9);
2329 assert(dest != NULL, "must have a target");
2330 intptr_t disp = dest - (pc() + sizeof(int32_t));
2331 assert(is_simm32(disp), "must be 32bit offset (jmp)");
2332 emit_data(disp, rspec.reloc(), call32_operand);
2333 }
2334
2335 void Assembler::jmpb_0(Label& L, const char* file, int line) {
2336 if (L.is_bound()) {
2337 const int short_size = 2;
2338 address entry = target(L);
2339 assert(entry != NULL, "jmp most probably wrong");
2340 #ifdef ASSERT
2341 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
2342 intptr_t delta = short_branch_delta();
2343 if (delta != 0) {
2344 dist += (dist < 0 ? (-delta) :delta);
2345 }
2346 assert(is8bit(dist), "Dispacement too large for a short jmp at %s:%d", file, line);
2347 #endif
2348 intptr_t offs = entry - pc();
2349 emit_int8((unsigned char)0xEB);
2350 emit_int8((offs - short_size) & 0xFF);
2351 } else {
2352 InstructionMark im(this);
2353 L.add_patch_at(code(), locator(), file, line);
2354 emit_int8((unsigned char)0xEB);
2355 emit_int8(0);
2356 }
2357 }
2358
2359 void Assembler::ldmxcsr( Address src) {
2360 if (UseAVX > 0 ) {
2361 InstructionMark im(this);
2362 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2363 vex_prefix(src, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2364 emit_int8((unsigned char)0xAE);
2365 emit_operand(as_Register(2), src);
2366 } else {
2367 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2368 InstructionMark im(this);
2369 prefix(src);
2370 emit_int8(0x0F);
2371 emit_int8((unsigned char)0xAE);
2372 emit_operand(as_Register(2), src);
2373 }
2374 }
2375
2376 void Assembler::leal(Register dst, Address src) {
2377 InstructionMark im(this);
2378 #ifdef _LP64
2379 emit_int8(0x67); // addr32
2380 prefix(src, dst);
2381 #endif // LP64
2382 emit_int8((unsigned char)0x8D);
2383 emit_operand(dst, src);
2384 }
2385
2386 void Assembler::lfence() {
2387 emit_int8(0x0F);
2388 emit_int8((unsigned char)0xAE);
2389 emit_int8((unsigned char)0xE8);
2390 }
2391
2392 void Assembler::lock() {
2393 emit_int8((unsigned char)0xF0);
2394 }
2395
2396 void Assembler::lzcntl(Register dst, Register src) {
2397 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
2398 emit_int8((unsigned char)0xF3);
2399 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2400 emit_int8(0x0F);
2401 emit_int8((unsigned char)0xBD);
2402 emit_int8((unsigned char)(0xC0 | encode));
2403 }
2404
2405 // Emit mfence instruction
2406 void Assembler::mfence() {
2407 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
2408 emit_int8(0x0F);
2409 emit_int8((unsigned char)0xAE);
2410 emit_int8((unsigned char)0xF0);
2411 }
2412
2413 void Assembler::mov(Register dst, Register src) {
2414 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2415 }
2416
2417 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
2418 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2419 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2420 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2421 attributes.set_rex_vex_w_reverted();
2422 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2423 emit_int8(0x28);
2424 emit_int8((unsigned char)(0xC0 | encode));
2425 }
2426
2427 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
2428 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2429 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2430 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2431 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2432 emit_int8(0x28);
2433 emit_int8((unsigned char)(0xC0 | encode));
2434 }
2435
2436 void Assembler::movlhps(XMMRegister dst, XMMRegister src) {
2437 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2438 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2439 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2440 emit_int8(0x16);
2441 emit_int8((unsigned char)(0xC0 | encode));
2442 }
2443
2444 void Assembler::movb(Register dst, Address src) {
2445 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
2446 InstructionMark im(this);
2447 prefix(src, dst, true);
2448 emit_int8((unsigned char)0x8A);
2449 emit_operand(dst, src);
2450 }
2451
2452 void Assembler::movddup(XMMRegister dst, XMMRegister src) {
2453 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
2454 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2455 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2456 attributes.set_rex_vex_w_reverted();
2457 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2458 emit_int8(0x12);
2459 emit_int8(0xC0 | encode);
2460 }
2461
2462 void Assembler::kmovbl(KRegister dst, Register src) {
2463 assert(VM_Version::supports_avx512dq(), "");
2464 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2465 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2466 emit_int8((unsigned char)0x92);
2467 emit_int8((unsigned char)(0xC0 | encode));
2468 }
2469
2470 void Assembler::kmovbl(Register dst, KRegister src) {
2471 assert(VM_Version::supports_avx512dq(), "");
2472 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2473 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2474 emit_int8((unsigned char)0x93);
2475 emit_int8((unsigned char)(0xC0 | encode));
2476 }
2477
2478 void Assembler::kmovwl(KRegister dst, Register src) {
2479 assert(VM_Version::supports_evex(), "");
2480 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2481 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2482 emit_int8((unsigned char)0x92);
2483 emit_int8((unsigned char)(0xC0 | encode));
2484 }
2485
2486 void Assembler::kmovwl(Register dst, KRegister src) {
2487 assert(VM_Version::supports_evex(), "");
2488 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2489 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2490 emit_int8((unsigned char)0x93);
2491 emit_int8((unsigned char)(0xC0 | encode));
2492 }
2493
2494 void Assembler::kmovwl(KRegister dst, Address src) {
2495 assert(VM_Version::supports_evex(), "");
2496 InstructionMark im(this);
2497 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2498 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2499 emit_int8((unsigned char)0x90);
2500 emit_operand((Register)dst, src);
2501 }
2502
2503 void Assembler::kmovdl(KRegister dst, Register src) {
2504 assert(VM_Version::supports_avx512bw(), "");
2505 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2506 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2507 emit_int8((unsigned char)0x92);
2508 emit_int8((unsigned char)(0xC0 | encode));
2509 }
2510
2511 void Assembler::kmovdl(Register dst, KRegister src) {
2512 assert(VM_Version::supports_avx512bw(), "");
2513 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2514 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2515 emit_int8((unsigned char)0x93);
2516 emit_int8((unsigned char)(0xC0 | encode));
2517 }
2518
2519 void Assembler::kmovql(KRegister dst, KRegister src) {
2520 assert(VM_Version::supports_avx512bw(), "");
2521 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2522 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2523 emit_int8((unsigned char)0x90);
2524 emit_int8((unsigned char)(0xC0 | encode));
2525 }
2526
2527 void Assembler::kmovql(KRegister dst, Address src) {
2528 assert(VM_Version::supports_avx512bw(), "");
2529 InstructionMark im(this);
2530 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2531 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2532 emit_int8((unsigned char)0x90);
2533 emit_operand((Register)dst, src);
2534 }
2535
2536 void Assembler::kmovql(Address dst, KRegister src) {
2537 assert(VM_Version::supports_avx512bw(), "");
2538 InstructionMark im(this);
2539 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2540 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2541 emit_int8((unsigned char)0x90);
2542 emit_operand((Register)src, dst);
2543 }
2544
2545 void Assembler::kmovql(KRegister dst, Register src) {
2546 assert(VM_Version::supports_avx512bw(), "");
2547 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2548 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2549 emit_int8((unsigned char)0x92);
2550 emit_int8((unsigned char)(0xC0 | encode));
2551 }
2552
2553 void Assembler::kmovql(Register dst, KRegister src) {
2554 assert(VM_Version::supports_avx512bw(), "");
2555 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2556 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2557 emit_int8((unsigned char)0x93);
2558 emit_int8((unsigned char)(0xC0 | encode));
2559 }
2560
2561 void Assembler::knotwl(KRegister dst, KRegister src) {
2562 assert(VM_Version::supports_evex(), "");
2563 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2564 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2565 emit_int8((unsigned char)0x44);
2566 emit_int8((unsigned char)(0xC0 | encode));
2567 }
2568
2569 // This instruction produces ZF or CF flags
2570 void Assembler::kortestbl(KRegister src1, KRegister src2) {
2571 assert(VM_Version::supports_avx512dq(), "");
2572 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2573 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2574 emit_int8((unsigned char)0x98);
2575 emit_int8((unsigned char)(0xC0 | encode));
2576 }
2577
2578 // This instruction produces ZF or CF flags
2579 void Assembler::kortestwl(KRegister src1, KRegister src2) {
2580 assert(VM_Version::supports_evex(), "");
2581 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2582 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2583 emit_int8((unsigned char)0x98);
2584 emit_int8((unsigned char)(0xC0 | encode));
2585 }
2586
2587 // This instruction produces ZF or CF flags
2588 void Assembler::kortestdl(KRegister src1, KRegister src2) {
2589 assert(VM_Version::supports_avx512bw(), "");
2590 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2591 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2592 emit_int8((unsigned char)0x98);
2593 emit_int8((unsigned char)(0xC0 | encode));
2594 }
2595
2596 // This instruction produces ZF or CF flags
2597 void Assembler::kortestql(KRegister src1, KRegister src2) {
2598 assert(VM_Version::supports_avx512bw(), "");
2599 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2600 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2601 emit_int8((unsigned char)0x98);
2602 emit_int8((unsigned char)(0xC0 | encode));
2603 }
2604
2605 // This instruction produces ZF or CF flags
2606 void Assembler::ktestql(KRegister src1, KRegister src2) {
2607 assert(VM_Version::supports_avx512bw(), "");
2608 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2609 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2610 emit_int8((unsigned char)0x99);
2611 emit_int8((unsigned char)(0xC0 | encode));
2612 }
2613
2614 void Assembler::ktestq(KRegister src1, KRegister src2) {
2615 assert(VM_Version::supports_avx512bw(), "");
2616 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2617 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2618 emit_int8((unsigned char)0x99);
2619 emit_int8((unsigned char)(0xC0 | encode));
2620 }
2621
2622 void Assembler::ktestd(KRegister src1, KRegister src2) {
2623 assert(VM_Version::supports_avx512bw(), "");
2624 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2625 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2626 emit_int8((unsigned char)0x99);
2627 emit_int8((unsigned char)(0xC0 | encode));
2628 }
2629
2630 void Assembler::movb(Address dst, int imm8) {
2631 InstructionMark im(this);
2632 prefix(dst);
2633 emit_int8((unsigned char)0xC6);
2634 emit_operand(rax, dst, 1);
2635 emit_int8(imm8);
2636 }
2637
2638
2639 void Assembler::movb(Address dst, Register src) {
2640 assert(src->has_byte_register(), "must have byte register");
2641 InstructionMark im(this);
2642 prefix(dst, src, true);
2643 emit_int8((unsigned char)0x88);
2644 emit_operand(src, dst);
2645 }
2646
2647 void Assembler::movdl(XMMRegister dst, Register src) {
2648 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2649 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2650 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2651 emit_int8(0x6E);
2652 emit_int8((unsigned char)(0xC0 | encode));
2653 }
2654
2655 void Assembler::movdl(Register dst, XMMRegister src) {
2656 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2657 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2658 // swap src/dst to get correct prefix
2659 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2660 emit_int8(0x7E);
2661 emit_int8((unsigned char)(0xC0 | encode));
2662 }
2663
2664 void Assembler::movdl(XMMRegister dst, Address src) {
2665 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2666 InstructionMark im(this);
2667 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2668 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2669 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2670 emit_int8(0x6E);
2671 emit_operand(dst, src);
2672 }
2673
2674 void Assembler::movdl(Address dst, XMMRegister src) {
2675 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2676 InstructionMark im(this);
2677 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2678 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2679 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2680 emit_int8(0x7E);
2681 emit_operand(src, dst);
2682 }
2683
2684 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
2685 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2686 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2687 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2688 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2689 emit_int8(0x6F);
2690 emit_int8((unsigned char)(0xC0 | encode));
2691 }
2692
2693 void Assembler::movdqa(XMMRegister dst, Address src) {
2694 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2695 InstructionMark im(this);
2696 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2697 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2698 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2699 emit_int8(0x6F);
2700 emit_operand(dst, src);
2701 }
2702
2703 void Assembler::movdqu(XMMRegister dst, Address src) {
2704 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2705 InstructionMark im(this);
2706 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2707 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2708 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2709 emit_int8(0x6F);
2710 emit_operand(dst, src);
2711 }
2712
2713 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
2714 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2715 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2716 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2717 emit_int8(0x6F);
2718 emit_int8((unsigned char)(0xC0 | encode));
2719 }
2720
2721 void Assembler::movdqu(Address dst, XMMRegister src) {
2722 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2723 InstructionMark im(this);
2724 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2725 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2726 attributes.reset_is_clear_context();
2727 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2728 emit_int8(0x7F);
2729 emit_operand(src, dst);
2730 }
2731
2732 // Move Unaligned 256bit Vector
2733 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2734 assert(UseAVX > 0, "");
2735 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2736 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2737 emit_int8(0x6F);
2738 emit_int8((unsigned char)(0xC0 | encode));
2739 }
2740
2741 void Assembler::vmovdqu(XMMRegister dst, Address src) {
2742 assert(UseAVX > 0, "");
2743 InstructionMark im(this);
2744 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2745 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2746 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2747 emit_int8(0x6F);
2748 emit_operand(dst, src);
2749 }
2750
2751 void Assembler::vmovdqu(Address dst, XMMRegister src) {
2752 assert(UseAVX > 0, "");
2753 InstructionMark im(this);
2754 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2755 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2756 attributes.reset_is_clear_context();
2757 // swap src<->dst for encoding
2758 assert(src != xnoreg, "sanity");
2759 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2760 emit_int8(0x7F);
2761 emit_operand(src, dst);
2762 }
2763
2764 // Move Unaligned EVEX enabled Vector (programmable : 8,16,32,64)
2765 void Assembler::evmovdqub(XMMRegister dst, XMMRegister src, bool merge, int vector_len) {
2766 assert(VM_Version::supports_evex(), "");
2767 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2768 attributes.set_is_evex_instruction();
2769 if (merge) {
2770 attributes.reset_is_clear_context();
2771 }
2772 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2773 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2774 emit_int8(0x6F);
2775 emit_int8((unsigned char)(0xC0 | encode));
2776 }
2777
2778 void Assembler::evmovdqub(XMMRegister dst, Address src, bool merge, int vector_len) {
2779 assert(VM_Version::supports_evex(), "");
2780 InstructionMark im(this);
2781 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2782 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2783 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2784 attributes.set_is_evex_instruction();
2785 if (merge) {
2786 attributes.reset_is_clear_context();
2787 }
2788 vex_prefix(src, 0, dst->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2789 emit_int8(0x6F);
2790 emit_operand(dst, src);
2791 }
2792
2793 void Assembler::evmovdqub(Address dst, XMMRegister src, bool merge, int vector_len) {
2794 assert(VM_Version::supports_evex(), "");
2795 assert(src != xnoreg, "sanity");
2796 InstructionMark im(this);
2797 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2798 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2799 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2800 attributes.set_is_evex_instruction();
2801 if (merge) {
2802 attributes.reset_is_clear_context();
2803 }
2804 vex_prefix(dst, 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2805 emit_int8(0x7F);
2806 emit_operand(src, dst);
2807 }
2808
2809 void Assembler::evmovdqub(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) {
2810 assert(VM_Version::supports_avx512vlbw(), "");
2811 InstructionMark im(this);
2812 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
2813 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2814 attributes.set_embedded_opmask_register_specifier(mask);
2815 attributes.set_is_evex_instruction();
2816 if (merge) {
2817 attributes.reset_is_clear_context();
2818 }
2819 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2820 emit_int8(0x6F);
2821 emit_operand(dst, src);
2822 }
2823
2824 void Assembler::evmovdquw(XMMRegister dst, Address src, bool merge, int vector_len) {
2825 assert(VM_Version::supports_evex(), "");
2826 InstructionMark im(this);
2827 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2828 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2829 attributes.set_is_evex_instruction();
2830 if (merge) {
2831 attributes.reset_is_clear_context();
2832 }
2833 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2834 vex_prefix(src, 0, dst->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2835 emit_int8(0x6F);
2836 emit_operand(dst, src);
2837 }
2838
2839 void Assembler::evmovdquw(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) {
2840 assert(VM_Version::supports_avx512vlbw(), "");
2841 InstructionMark im(this);
2842 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
2843 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2844 attributes.set_embedded_opmask_register_specifier(mask);
2845 attributes.set_is_evex_instruction();
2846 if (merge) {
2847 attributes.reset_is_clear_context();
2848 }
2849 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2850 emit_int8(0x6F);
2851 emit_operand(dst, src);
2852 }
2853
2854 void Assembler::evmovdquw(Address dst, XMMRegister src, bool merge, int vector_len) {
2855 assert(VM_Version::supports_evex(), "");
2856 assert(src != xnoreg, "sanity");
2857 InstructionMark im(this);
2858 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2859 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2860 attributes.set_is_evex_instruction();
2861 if (merge) {
2862 attributes.reset_is_clear_context();
2863 }
2864 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2865 vex_prefix(dst, 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2866 emit_int8(0x7F);
2867 emit_operand(src, dst);
2868 }
2869
2870 void Assembler::evmovdquw(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
2871 assert(VM_Version::supports_avx512vlbw(), "");
2872 assert(src != xnoreg, "sanity");
2873 InstructionMark im(this);
2874 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2875 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2876 attributes.set_embedded_opmask_register_specifier(mask);
2877 attributes.set_is_evex_instruction();
2878 if (merge) {
2879 attributes.reset_is_clear_context();
2880 }
2881 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2882 emit_int8(0x7F);
2883 emit_operand(src, dst);
2884 }
2885
2886 void Assembler::evmovdqul(XMMRegister dst, XMMRegister src, int vector_len) {
2887 // Users of this routine assume k1 usage.
2888 evmovdqul(dst, k1, src, /*merge*/ false, vector_len);
2889 }
2890
2891 void Assembler::evmovdqul(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
2892 assert(VM_Version::supports_evex(), "");
2893 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2894 attributes.set_embedded_opmask_register_specifier(mask);
2895 attributes.set_is_evex_instruction();
2896 if (merge) {
2897 attributes.reset_is_clear_context();
2898 }
2899 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2900 emit_int8(0x6F);
2901 emit_int8((unsigned char)(0xC0 | encode));
2902 }
2903
2904 void Assembler::evmovdqul(XMMRegister dst, Address src, int vector_len) {
2905 // Users of this routine assume k1 usage.
2906 evmovdqul(dst, k1, src, /*merge*/ false, vector_len);
2907 }
2908
2909 void Assembler::evmovdqul(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) {
2910 assert(VM_Version::supports_evex(), "");
2911 InstructionMark im(this);
2912 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false , /* uses_vl */ true);
2913 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2914 attributes.set_embedded_opmask_register_specifier(mask);
2915 attributes.set_is_evex_instruction();
2916 if (merge) {
2917 attributes.reset_is_clear_context();
2918 }
2919 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2920 emit_int8(0x6F);
2921 emit_operand(dst, src);
2922 }
2923
2924 void Assembler::evmovdqul(Address dst, XMMRegister src, int vector_len) {
2925 // Users of this routine assume k1 usage.
2926 evmovdqul(dst, k1, src, /*merge*/ true, vector_len);
2927 }
2928
2929 void Assembler::evmovdqul(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
2930 assert(VM_Version::supports_evex(), "");
2931 assert(src != xnoreg, "sanity");
2932 InstructionMark im(this);
2933 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2934 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2935 attributes.set_embedded_opmask_register_specifier(mask);
2936 attributes.set_is_evex_instruction();
2937 if (merge) {
2938 attributes.reset_is_clear_context();
2939 }
2940 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2941 emit_int8(0x7F);
2942 emit_operand(src, dst);
2943 }
2944
2945 void Assembler::evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) {
2946 // Users of this routine assume k1 usage.
2947 evmovdquq(dst, k1, src, /*merge*/ false, vector_len);
2948 }
2949
2950 void Assembler::evmovdquq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
2951 assert(VM_Version::supports_evex(), "");
2952 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2953 attributes.set_embedded_opmask_register_specifier(mask);
2954 attributes.set_is_evex_instruction();
2955 if (merge) {
2956 attributes.reset_is_clear_context();
2957 }
2958 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2959 emit_int8(0x6F);
2960 emit_int8((unsigned char)(0xC0 | encode));
2961 }
2962
2963 void Assembler::evmovdquq(XMMRegister dst, Address src, int vector_len) {
2964 // Users of this routine assume k1 usage.
2965 evmovdquq(dst, k1, src, /*merge*/ false, vector_len);
2966 }
2967
2968 void Assembler::evmovdquq(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) {
2969 assert(VM_Version::supports_evex(), "");
2970 InstructionMark im(this);
2971 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2972 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2973 attributes.set_embedded_opmask_register_specifier(mask);
2974 attributes.set_is_evex_instruction();
2975 if (merge) {
2976 attributes.reset_is_clear_context();
2977 }
2978 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2979 emit_int8(0x6F);
2980 emit_operand(dst, src);
2981 }
2982
2983 void Assembler::evmovdquq(Address dst, XMMRegister src, int vector_len) {
2984 // Users of this routine assume k1 usage.
2985 evmovdquq(dst, k1, src, /*merge*/ true, vector_len);
2986 }
2987
2988 void Assembler::evmovdquq(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
2989 assert(VM_Version::supports_evex(), "");
2990 assert(src != xnoreg, "sanity");
2991 InstructionMark im(this);
2992 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2993 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2994 attributes.set_embedded_opmask_register_specifier(mask);
2995 if (merge) {
2996 attributes.reset_is_clear_context();
2997 }
2998 attributes.set_is_evex_instruction();
2999 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3000 emit_int8(0x7F);
3001 emit_operand(src, dst);
3002 }
3003
3004 // Uses zero extension on 64bit
3005
3006 void Assembler::movl(Register dst, int32_t imm32) {
3007 int encode = prefix_and_encode(dst->encoding());
3008 emit_int8((unsigned char)(0xB8 | encode));
3009 emit_int32(imm32);
3010 }
3011
3012 void Assembler::movl(Register dst, Register src) {
3013 int encode = prefix_and_encode(dst->encoding(), src->encoding());
3014 emit_int8((unsigned char)0x8B);
3015 emit_int8((unsigned char)(0xC0 | encode));
3016 }
3017
3018 void Assembler::movl(Register dst, Address src) {
3019 InstructionMark im(this);
3020 prefix(src, dst);
3021 emit_int8((unsigned char)0x8B);
3022 emit_operand(dst, src);
3023 }
3024
3025 void Assembler::movl(Address dst, int32_t imm32) {
3026 InstructionMark im(this);
3027 prefix(dst);
3028 emit_int8((unsigned char)0xC7);
3029 emit_operand(rax, dst, 4);
3030 emit_int32(imm32);
3031 }
3032
3033 void Assembler::movl(Address dst, Register src) {
3034 InstructionMark im(this);
3035 prefix(dst, src);
3036 emit_int8((unsigned char)0x89);
3037 emit_operand(src, dst);
3038 }
3039
3040 // New cpus require to use movsd and movss to avoid partial register stall
3041 // when loading from memory. But for old Opteron use movlpd instead of movsd.
3042 // The selection is done in MacroAssembler::movdbl() and movflt().
3043 void Assembler::movlpd(XMMRegister dst, Address src) {
3044 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3045 InstructionMark im(this);
3046 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3047 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3048 attributes.set_rex_vex_w_reverted();
3049 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3050 emit_int8(0x12);
3051 emit_operand(dst, src);
3052 }
3053
3054 void Assembler::movq( MMXRegister dst, Address src ) {
3055 assert( VM_Version::supports_mmx(), "" );
3056 emit_int8(0x0F);
3057 emit_int8(0x6F);
3058 emit_operand(dst, src);
3059 }
3060
3061 void Assembler::movq( Address dst, MMXRegister src ) {
3062 assert( VM_Version::supports_mmx(), "" );
3063 emit_int8(0x0F);
3064 emit_int8(0x7F);
3065 // workaround gcc (3.2.1-7a) bug
3066 // In that version of gcc with only an emit_operand(MMX, Address)
3067 // gcc will tail jump and try and reverse the parameters completely
3068 // obliterating dst in the process. By having a version available
3069 // that doesn't need to swap the args at the tail jump the bug is
3070 // avoided.
3071 emit_operand(dst, src);
3072 }
3073
3074 void Assembler::movq(XMMRegister dst, Address src) {
3075 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3076 InstructionMark im(this);
3077 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3078 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3079 attributes.set_rex_vex_w_reverted();
3080 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3081 emit_int8(0x7E);
3082 emit_operand(dst, src);
3083 }
3084
3085 void Assembler::movq(Address dst, XMMRegister src) {
3086 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3087 InstructionMark im(this);
3088 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3089 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3090 attributes.set_rex_vex_w_reverted();
3091 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3092 emit_int8((unsigned char)0xD6);
3093 emit_operand(src, dst);
3094 }
3095
3096 void Assembler::movq(Register dst, XMMRegister src) {
3097 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3098 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3099 // swap src/dst to get correct prefix
3100 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3101 emit_int8(0x7E);
3102 emit_int8((unsigned char)(0xC0 | encode));
3103 }
3104
3105 void Assembler::movq(XMMRegister dst, Register src) {
3106 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3107 InstructionAttr attributes(AVX_128bit, /* rex_w */true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3108 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3109 emit_int8(0x6E);
3110 emit_int8((unsigned char)(0xC0 | encode));
3111 }
3112
3113 void Assembler::movsbl(Register dst, Address src) { // movsxb
3114 InstructionMark im(this);
3115 prefix(src, dst);
3116 emit_int8(0x0F);
3117 emit_int8((unsigned char)0xBE);
3118 emit_operand(dst, src);
3119 }
3120
3121 void Assembler::movsbl(Register dst, Register src) { // movsxb
3122 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
3123 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
3124 emit_int8(0x0F);
3125 emit_int8((unsigned char)0xBE);
3126 emit_int8((unsigned char)(0xC0 | encode));
3127 }
3128
3129 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
3130 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3131 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3132 attributes.set_rex_vex_w_reverted();
3133 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3134 emit_int8(0x10);
3135 emit_int8((unsigned char)(0xC0 | encode));
3136 }
3137
3138 void Assembler::movsd(XMMRegister dst, Address src) {
3139 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3140 InstructionMark im(this);
3141 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3142 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3143 attributes.set_rex_vex_w_reverted();
3144 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3145 emit_int8(0x10);
3146 emit_operand(dst, src);
3147 }
3148
3149 void Assembler::movsd(Address dst, XMMRegister src) {
3150 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3151 InstructionMark im(this);
3152 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3153 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3154 attributes.reset_is_clear_context();
3155 attributes.set_rex_vex_w_reverted();
3156 simd_prefix(src, xnoreg, dst, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3157 emit_int8(0x11);
3158 emit_operand(src, dst);
3159 }
3160
3161 void Assembler::movss(XMMRegister dst, XMMRegister src) {
3162 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3163 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3164 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3165 emit_int8(0x10);
3166 emit_int8((unsigned char)(0xC0 | encode));
3167 }
3168
3169 void Assembler::movss(XMMRegister dst, Address src) {
3170 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3171 InstructionMark im(this);
3172 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3173 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3174 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3175 emit_int8(0x10);
3176 emit_operand(dst, src);
3177 }
3178
3179 void Assembler::movss(Address dst, XMMRegister src) {
3180 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3181 InstructionMark im(this);
3182 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3183 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3184 attributes.reset_is_clear_context();
3185 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3186 emit_int8(0x11);
3187 emit_operand(src, dst);
3188 }
3189
3190 void Assembler::movswl(Register dst, Address src) { // movsxw
3191 InstructionMark im(this);
3192 prefix(src, dst);
3193 emit_int8(0x0F);
3194 emit_int8((unsigned char)0xBF);
3195 emit_operand(dst, src);
3196 }
3197
3198 void Assembler::movswl(Register dst, Register src) { // movsxw
3199 int encode = prefix_and_encode(dst->encoding(), src->encoding());
3200 emit_int8(0x0F);
3201 emit_int8((unsigned char)0xBF);
3202 emit_int8((unsigned char)(0xC0 | encode));
3203 }
3204
3205 void Assembler::movw(Address dst, int imm16) {
3206 InstructionMark im(this);
3207
3208 emit_int8(0x66); // switch to 16-bit mode
3209 prefix(dst);
3210 emit_int8((unsigned char)0xC7);
3211 emit_operand(rax, dst, 2);
3212 emit_int16(imm16);
3213 }
3214
3215 void Assembler::movw(Register dst, Address src) {
3216 InstructionMark im(this);
3217 emit_int8(0x66);
3218 prefix(src, dst);
3219 emit_int8((unsigned char)0x8B);
3220 emit_operand(dst, src);
3221 }
3222
3223 void Assembler::movw(Address dst, Register src) {
3224 InstructionMark im(this);
3225 emit_int8(0x66);
3226 prefix(dst, src);
3227 emit_int8((unsigned char)0x89);
3228 emit_operand(src, dst);
3229 }
3230
3231 void Assembler::movzbl(Register dst, Address src) { // movzxb
3232 InstructionMark im(this);
3233 prefix(src, dst);
3234 emit_int8(0x0F);
3235 emit_int8((unsigned char)0xB6);
3236 emit_operand(dst, src);
3237 }
3238
3239 void Assembler::movzbl(Register dst, Register src) { // movzxb
3240 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
3241 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
3242 emit_int8(0x0F);
3243 emit_int8((unsigned char)0xB6);
3244 emit_int8(0xC0 | encode);
3245 }
3246
3247 void Assembler::movzwl(Register dst, Address src) { // movzxw
3248 InstructionMark im(this);
3249 prefix(src, dst);
3250 emit_int8(0x0F);
3251 emit_int8((unsigned char)0xB7);
3252 emit_operand(dst, src);
3253 }
3254
3255 void Assembler::movzwl(Register dst, Register src) { // movzxw
3256 int encode = prefix_and_encode(dst->encoding(), src->encoding());
3257 emit_int8(0x0F);
3258 emit_int8((unsigned char)0xB7);
3259 emit_int8(0xC0 | encode);
3260 }
3261
3262 void Assembler::mull(Address src) {
3263 InstructionMark im(this);
3264 prefix(src);
3265 emit_int8((unsigned char)0xF7);
3266 emit_operand(rsp, src);
3267 }
3268
3269 void Assembler::mull(Register src) {
3270 int encode = prefix_and_encode(src->encoding());
3271 emit_int8((unsigned char)0xF7);
3272 emit_int8((unsigned char)(0xE0 | encode));
3273 }
3274
3275 void Assembler::mulsd(XMMRegister dst, Address src) {
3276 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3277 InstructionMark im(this);
3278 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3279 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3280 attributes.set_rex_vex_w_reverted();
3281 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3282 emit_int8(0x59);
3283 emit_operand(dst, src);
3284 }
3285
3286 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
3287 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3288 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3289 attributes.set_rex_vex_w_reverted();
3290 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3291 emit_int8(0x59);
3292 emit_int8((unsigned char)(0xC0 | encode));
3293 }
3294
3295 void Assembler::mulss(XMMRegister dst, Address src) {
3296 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3297 InstructionMark im(this);
3298 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3299 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3300 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3301 emit_int8(0x59);
3302 emit_operand(dst, src);
3303 }
3304
3305 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
3306 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3307 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3308 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3309 emit_int8(0x59);
3310 emit_int8((unsigned char)(0xC0 | encode));
3311 }
3312
3313 void Assembler::negl(Register dst) {
3314 int encode = prefix_and_encode(dst->encoding());
3315 emit_int8((unsigned char)0xF7);
3316 emit_int8((unsigned char)(0xD8 | encode));
3317 }
3318
3319 void Assembler::nop(int i) {
3320 #ifdef ASSERT
3321 assert(i > 0, " ");
3322 // The fancy nops aren't currently recognized by debuggers making it a
3323 // pain to disassemble code while debugging. If asserts are on clearly
3324 // speed is not an issue so simply use the single byte traditional nop
3325 // to do alignment.
3326
3327 for (; i > 0 ; i--) emit_int8((unsigned char)0x90);
3328 return;
3329
3330 #endif // ASSERT
3331
3332 if (UseAddressNop && VM_Version::is_intel()) {
3333 //
3334 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel
3335 // 1: 0x90
3336 // 2: 0x66 0x90
3337 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
3338 // 4: 0x0F 0x1F 0x40 0x00
3339 // 5: 0x0F 0x1F 0x44 0x00 0x00
3340 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
3341 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3342 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3343 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3344 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3345 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3346
3347 // The rest coding is Intel specific - don't use consecutive address nops
3348
3349 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3350 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3351 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3352 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3353
3354 while(i >= 15) {
3355 // For Intel don't generate consecutive addess nops (mix with regular nops)
3356 i -= 15;
3357 emit_int8(0x66); // size prefix
3358 emit_int8(0x66); // size prefix
3359 emit_int8(0x66); // size prefix
3360 addr_nop_8();
3361 emit_int8(0x66); // size prefix
3362 emit_int8(0x66); // size prefix
3363 emit_int8(0x66); // size prefix
3364 emit_int8((unsigned char)0x90);
3365 // nop
3366 }
3367 switch (i) {
3368 case 14:
3369 emit_int8(0x66); // size prefix
3370 case 13:
3371 emit_int8(0x66); // size prefix
3372 case 12:
3373 addr_nop_8();
3374 emit_int8(0x66); // size prefix
3375 emit_int8(0x66); // size prefix
3376 emit_int8(0x66); // size prefix
3377 emit_int8((unsigned char)0x90);
3378 // nop
3379 break;
3380 case 11:
3381 emit_int8(0x66); // size prefix
3382 case 10:
3383 emit_int8(0x66); // size prefix
3384 case 9:
3385 emit_int8(0x66); // size prefix
3386 case 8:
3387 addr_nop_8();
3388 break;
3389 case 7:
3390 addr_nop_7();
3391 break;
3392 case 6:
3393 emit_int8(0x66); // size prefix
3394 case 5:
3395 addr_nop_5();
3396 break;
3397 case 4:
3398 addr_nop_4();
3399 break;
3400 case 3:
3401 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
3402 emit_int8(0x66); // size prefix
3403 case 2:
3404 emit_int8(0x66); // size prefix
3405 case 1:
3406 emit_int8((unsigned char)0x90);
3407 // nop
3408 break;
3409 default:
3410 assert(i == 0, " ");
3411 }
3412 return;
3413 }
3414 if (UseAddressNop && VM_Version::is_amd()) {
3415 //
3416 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD.
3417 // 1: 0x90
3418 // 2: 0x66 0x90
3419 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
3420 // 4: 0x0F 0x1F 0x40 0x00
3421 // 5: 0x0F 0x1F 0x44 0x00 0x00
3422 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
3423 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3424 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3425 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3426 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3427 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3428
3429 // The rest coding is AMD specific - use consecutive address nops
3430
3431 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
3432 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
3433 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3434 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3435 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3436 // Size prefixes (0x66) are added for larger sizes
3437
3438 while(i >= 22) {
3439 i -= 11;
3440 emit_int8(0x66); // size prefix
3441 emit_int8(0x66); // size prefix
3442 emit_int8(0x66); // size prefix
3443 addr_nop_8();
3444 }
3445 // Generate first nop for size between 21-12
3446 switch (i) {
3447 case 21:
3448 i -= 1;
3449 emit_int8(0x66); // size prefix
3450 case 20:
3451 case 19:
3452 i -= 1;
3453 emit_int8(0x66); // size prefix
3454 case 18:
3455 case 17:
3456 i -= 1;
3457 emit_int8(0x66); // size prefix
3458 case 16:
3459 case 15:
3460 i -= 8;
3461 addr_nop_8();
3462 break;
3463 case 14:
3464 case 13:
3465 i -= 7;
3466 addr_nop_7();
3467 break;
3468 case 12:
3469 i -= 6;
3470 emit_int8(0x66); // size prefix
3471 addr_nop_5();
3472 break;
3473 default:
3474 assert(i < 12, " ");
3475 }
3476
3477 // Generate second nop for size between 11-1
3478 switch (i) {
3479 case 11:
3480 emit_int8(0x66); // size prefix
3481 case 10:
3482 emit_int8(0x66); // size prefix
3483 case 9:
3484 emit_int8(0x66); // size prefix
3485 case 8:
3486 addr_nop_8();
3487 break;
3488 case 7:
3489 addr_nop_7();
3490 break;
3491 case 6:
3492 emit_int8(0x66); // size prefix
3493 case 5:
3494 addr_nop_5();
3495 break;
3496 case 4:
3497 addr_nop_4();
3498 break;
3499 case 3:
3500 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
3501 emit_int8(0x66); // size prefix
3502 case 2:
3503 emit_int8(0x66); // size prefix
3504 case 1:
3505 emit_int8((unsigned char)0x90);
3506 // nop
3507 break;
3508 default:
3509 assert(i == 0, " ");
3510 }
3511 return;
3512 }
3513
3514 if (UseAddressNop && VM_Version::is_zx()) {
3515 //
3516 // Using multi-bytes nops "0x0F 0x1F [address]" for ZX
3517 // 1: 0x90
3518 // 2: 0x66 0x90
3519 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
3520 // 4: 0x0F 0x1F 0x40 0x00
3521 // 5: 0x0F 0x1F 0x44 0x00 0x00
3522 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
3523 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3524 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3525 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3526 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3527 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3528
3529 // The rest coding is ZX specific - don't use consecutive address nops
3530
3531 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3532 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3533 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3534 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3535
3536 while (i >= 15) {
3537 // For ZX don't generate consecutive addess nops (mix with regular nops)
3538 i -= 15;
3539 emit_int8(0x66); // size prefix
3540 emit_int8(0x66); // size prefix
3541 emit_int8(0x66); // size prefix
3542 addr_nop_8();
3543 emit_int8(0x66); // size prefix
3544 emit_int8(0x66); // size prefix
3545 emit_int8(0x66); // size prefix
3546 emit_int8((unsigned char)0x90);
3547 // nop
3548 }
3549 switch (i) {
3550 case 14:
3551 emit_int8(0x66); // size prefix
3552 case 13:
3553 emit_int8(0x66); // size prefix
3554 case 12:
3555 addr_nop_8();
3556 emit_int8(0x66); // size prefix
3557 emit_int8(0x66); // size prefix
3558 emit_int8(0x66); // size prefix
3559 emit_int8((unsigned char)0x90);
3560 // nop
3561 break;
3562 case 11:
3563 emit_int8(0x66); // size prefix
3564 case 10:
3565 emit_int8(0x66); // size prefix
3566 case 9:
3567 emit_int8(0x66); // size prefix
3568 case 8:
3569 addr_nop_8();
3570 break;
3571 case 7:
3572 addr_nop_7();
3573 break;
3574 case 6:
3575 emit_int8(0x66); // size prefix
3576 case 5:
3577 addr_nop_5();
3578 break;
3579 case 4:
3580 addr_nop_4();
3581 break;
3582 case 3:
3583 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
3584 emit_int8(0x66); // size prefix
3585 case 2:
3586 emit_int8(0x66); // size prefix
3587 case 1:
3588 emit_int8((unsigned char)0x90);
3589 // nop
3590 break;
3591 default:
3592 assert(i == 0, " ");
3593 }
3594 return;
3595 }
3596
3597 // Using nops with size prefixes "0x66 0x90".
3598 // From AMD Optimization Guide:
3599 // 1: 0x90
3600 // 2: 0x66 0x90
3601 // 3: 0x66 0x66 0x90
3602 // 4: 0x66 0x66 0x66 0x90
3603 // 5: 0x66 0x66 0x90 0x66 0x90
3604 // 6: 0x66 0x66 0x90 0x66 0x66 0x90
3605 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90
3606 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90
3607 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
3608 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
3609 //
3610 while(i > 12) {
3611 i -= 4;
3612 emit_int8(0x66); // size prefix
3613 emit_int8(0x66);
3614 emit_int8(0x66);
3615 emit_int8((unsigned char)0x90);
3616 // nop
3617 }
3618 // 1 - 12 nops
3619 if(i > 8) {
3620 if(i > 9) {
3621 i -= 1;
3622 emit_int8(0x66);
3623 }
3624 i -= 3;
3625 emit_int8(0x66);
3626 emit_int8(0x66);
3627 emit_int8((unsigned char)0x90);
3628 }
3629 // 1 - 8 nops
3630 if(i > 4) {
3631 if(i > 6) {
3632 i -= 1;
3633 emit_int8(0x66);
3634 }
3635 i -= 3;
3636 emit_int8(0x66);
3637 emit_int8(0x66);
3638 emit_int8((unsigned char)0x90);
3639 }
3640 switch (i) {
3641 case 4:
3642 emit_int8(0x66);
3643 case 3:
3644 emit_int8(0x66);
3645 case 2:
3646 emit_int8(0x66);
3647 case 1:
3648 emit_int8((unsigned char)0x90);
3649 break;
3650 default:
3651 assert(i == 0, " ");
3652 }
3653 }
3654
3655 void Assembler::notl(Register dst) {
3656 int encode = prefix_and_encode(dst->encoding());
3657 emit_int8((unsigned char)0xF7);
3658 emit_int8((unsigned char)(0xD0 | encode));
3659 }
3660
3661 void Assembler::orw(Register dst, Register src) {
3662 (void)prefix_and_encode(dst->encoding(), src->encoding());
3663 emit_arith(0x0B, 0xC0, dst, src);
3664 }
3665
3666 void Assembler::orl(Address dst, int32_t imm32) {
3667 InstructionMark im(this);
3668 prefix(dst);
3669 emit_arith_operand(0x81, rcx, dst, imm32);
3670 }
3671
3672 void Assembler::orl(Register dst, int32_t imm32) {
3673 prefix(dst);
3674 emit_arith(0x81, 0xC8, dst, imm32);
3675 }
3676
3677 void Assembler::orl(Register dst, Address src) {
3678 InstructionMark im(this);
3679 prefix(src, dst);
3680 emit_int8(0x0B);
3681 emit_operand(dst, src);
3682 }
3683
3684 void Assembler::orl(Register dst, Register src) {
3685 (void) prefix_and_encode(dst->encoding(), src->encoding());
3686 emit_arith(0x0B, 0xC0, dst, src);
3687 }
3688
3689 void Assembler::orl(Address dst, Register src) {
3690 InstructionMark im(this);
3691 prefix(dst, src);
3692 emit_int8(0x09);
3693 emit_operand(src, dst);
3694 }
3695
3696 void Assembler::orb(Address dst, int imm8) {
3697 InstructionMark im(this);
3698 prefix(dst);
3699 emit_int8((unsigned char)0x80);
3700 emit_operand(rcx, dst, 1);
3701 emit_int8(imm8);
3702 }
3703
3704 void Assembler::packuswb(XMMRegister dst, Address src) {
3705 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3706 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3707 InstructionMark im(this);
3708 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3709 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3710 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3711 emit_int8(0x67);
3712 emit_operand(dst, src);
3713 }
3714
3715 void Assembler::packuswb(XMMRegister dst, XMMRegister src) {
3716 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3717 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3718 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3719 emit_int8(0x67);
3720 emit_int8((unsigned char)(0xC0 | encode));
3721 }
3722
3723 void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3724 assert(UseAVX > 0, "some form of AVX must be enabled");
3725 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3726 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3727 emit_int8(0x67);
3728 emit_int8((unsigned char)(0xC0 | encode));
3729 }
3730
3731 void Assembler::vpackusdw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3732 assert(UseAVX > 0, "some form of AVX must be enabled");
3733 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3734 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3735 emit_int8(0x2B);
3736 emit_int8((unsigned char)(0xC0 | encode));
3737 }
3738
3739 void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len) {
3740 assert(VM_Version::supports_avx2(), "");
3741 // VEX.256.66.0F3A.W1 00 /r ib
3742 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3743 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3744 emit_int8(0x00);
3745 emit_int8(0xC0 | encode);
3746 emit_int8(imm8);
3747 }
3748
3749 void Assembler::vpermb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3750 assert(VM_Version::supports_avx512vbmi(), "");
3751 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3752 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3753 emit_int8((unsigned char)0x8D);
3754 emit_int8((unsigned char)(0xC0 | encode));
3755 }
3756
3757 void Assembler::vpermw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
3758 assert(VM_Version::supports_avx512vlbw(), "");
3759 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3760 attributes.set_embedded_opmask_register_specifier(mask);
3761 attributes.set_is_evex_instruction();
3762 if (merge) {
3763 attributes.reset_is_clear_context();
3764 }
3765 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3766 emit_int8((unsigned char)0x8D);
3767 emit_int8((unsigned char)(0xC0 | encode));
3768 }
3769
3770 void Assembler::vpermd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3771 assert(VM_Version::supports_avx2(), "");
3772 // VEX.NDS.256.66.0F38.W0 36 /r
3773 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3774 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3775 emit_int8(0x36);
3776 emit_int8(0xC0 | encode);
3777 }
3778
3779 void Assembler::vpermd(XMMRegister dst, XMMRegister nds, Address src) {
3780 assert(VM_Version::supports_avx2(), "");
3781 // VEX.NDS.256.66.0F38.W0 36 /r
3782 InstructionMark im(this);
3783 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3784 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3785 emit_int8(0x36);
3786 emit_operand(dst, src);
3787 }
3788
3789 void Assembler::evpermd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3790 assert(VM_Version::supports_evex(), "");
3791 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3792 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3793 emit_int8(0x36);
3794 emit_int8((unsigned char)(0xC0 | encode));
3795 }
3796
3797 void Assembler::vperm2i128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) {
3798 assert(VM_Version::supports_avx2(), "");
3799 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3800 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3801 emit_int8(0x46);
3802 emit_int8(0xC0 | encode);
3803 emit_int8(imm8);
3804 }
3805
3806 void Assembler::vperm2f128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) {
3807 assert(VM_Version::supports_avx(), "");
3808 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3809 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3810 emit_int8(0x06);
3811 emit_int8(0xC0 | encode);
3812 emit_int8(imm8);
3813 }
3814
3815 void Assembler::vpermilps(XMMRegister dst, XMMRegister src, int imm8, int vector_len) {
3816 assert(VM_Version::supports_avx(), "");
3817 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
3818 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3819 emit_int8(0x04);
3820 emit_int8(0xC0 | encode);
3821 emit_int8(imm8);
3822 }
3823
3824 void Assembler::vpermpd(XMMRegister dst, XMMRegister src, int imm8, int vector_len) {
3825 assert(VM_Version::supports_avx2(), "");
3826 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
3827 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3828 emit_int8(0x01);
3829 emit_int8(0xC0 | encode);
3830 emit_int8(imm8);
3831 }
3832
3833 void Assembler::evpermi2q(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3834 assert(VM_Version::supports_evex(), "");
3835 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3836 attributes.set_is_evex_instruction();
3837 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3838 emit_int8(0x76);
3839 emit_int8((unsigned char)(0xC0 | encode));
3840 }
3841
3842 void Assembler::pause() {
3843 emit_int8((unsigned char)0xF3);
3844 emit_int8((unsigned char)0x90);
3845 }
3846
3847 void Assembler::ud2() {
3848 emit_int8(0x0F);
3849 emit_int8(0x0B);
3850 }
3851
3852 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3853 assert(VM_Version::supports_sse4_2(), "");
3854 InstructionMark im(this);
3855 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3856 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3857 emit_int8(0x61);
3858 emit_operand(dst, src);
3859 emit_int8(imm8);
3860 }
3861
3862 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3863 assert(VM_Version::supports_sse4_2(), "");
3864 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3865 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3866 emit_int8(0x61);
3867 emit_int8((unsigned char)(0xC0 | encode));
3868 emit_int8(imm8);
3869 }
3870
3871 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3872 void Assembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
3873 assert(VM_Version::supports_sse2(), "");
3874 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3875 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3876 emit_int8(0x74);
3877 emit_int8((unsigned char)(0xC0 | encode));
3878 }
3879
3880 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3881 void Assembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3882 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2(), "");
3883 assert(vector_len <= AVX_256bit, "evex encoding is different - has k register as dest");
3884 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3885 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3886 emit_int8(0x74);
3887 emit_int8((unsigned char)(0xC0 | encode));
3888 }
3889
3890 // In this context, kdst is written the mask used to process the equal components
3891 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3892 assert(VM_Version::supports_avx512bw(), "");
3893 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3894 attributes.set_is_evex_instruction();
3895 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3896 emit_int8(0x74);
3897 emit_int8((unsigned char)(0xC0 | encode));
3898 }
3899
3900 void Assembler::evpcmpgtb(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3901 assert(VM_Version::supports_avx512vlbw(), "");
3902 InstructionMark im(this);
3903 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3904 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3905 attributes.set_is_evex_instruction();
3906 int dst_enc = kdst->encoding();
3907 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3908 emit_int8(0x64);
3909 emit_operand(as_Register(dst_enc), src);
3910 }
3911
3912 void Assembler::evpcmpgtb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len) {
3913 assert(is_vector_masking(), "");
3914 assert(VM_Version::supports_avx512vlbw(), "");
3915 InstructionMark im(this);
3916 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
3917 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3918 attributes.reset_is_clear_context();
3919 attributes.set_embedded_opmask_register_specifier(mask);
3920 attributes.set_is_evex_instruction();
3921 int dst_enc = kdst->encoding();
3922 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3923 emit_int8(0x64);
3924 emit_operand(as_Register(dst_enc), src);
3925 }
3926
3927 void Assembler::evpcmpuw(KRegister kdst, XMMRegister nds, XMMRegister src, ComparisonPredicate vcc, int vector_len) {
3928 assert(VM_Version::supports_avx512vlbw(), "");
3929 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3930 attributes.set_is_evex_instruction();
3931 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3932 emit_int8(0x3E);
3933 emit_int8((unsigned char)(0xC0 | encode));
3934 emit_int8(vcc);
3935 }
3936
3937 void Assembler::evpcmpuw(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, ComparisonPredicate vcc, int vector_len) {
3938 assert(is_vector_masking(), "");
3939 assert(VM_Version::supports_avx512vlbw(), "");
3940 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
3941 attributes.reset_is_clear_context();
3942 attributes.set_embedded_opmask_register_specifier(mask);
3943 attributes.set_is_evex_instruction();
3944 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3945 emit_int8(0x3E);
3946 emit_int8((unsigned char)(0xC0 | encode));
3947 emit_int8(vcc);
3948 }
3949
3950 void Assembler::evpcmpuw(KRegister kdst, XMMRegister nds, Address src, ComparisonPredicate vcc, int vector_len) {
3951 assert(VM_Version::supports_avx512vlbw(), "");
3952 InstructionMark im(this);
3953 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3954 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3955 attributes.set_is_evex_instruction();
3956 int dst_enc = kdst->encoding();
3957 vex_prefix(src, nds->encoding(), kdst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3958 emit_int8(0x3E);
3959 emit_operand(as_Register(dst_enc), src);
3960 emit_int8(vcc);
3961 }
3962
3963 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3964 assert(VM_Version::supports_avx512bw(), "");
3965 InstructionMark im(this);
3966 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3967 attributes.set_is_evex_instruction();
3968 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3969 int dst_enc = kdst->encoding();
3970 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3971 emit_int8(0x74);
3972 emit_operand(as_Register(dst_enc), src);
3973 }
3974
3975 void Assembler::evpcmpeqb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len) {
3976 assert(VM_Version::supports_avx512vlbw(), "");
3977 assert(is_vector_masking(), ""); // For stub code use only
3978 InstructionMark im(this);
3979 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_reg_mask */ false, /* uses_vl */ false);
3980 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3981 attributes.reset_is_clear_context();
3982 attributes.set_embedded_opmask_register_specifier(mask);
3983 attributes.set_is_evex_instruction();
3984 vex_prefix(src, nds->encoding(), kdst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3985 emit_int8(0x74);
3986 emit_operand(as_Register(kdst->encoding()), src);
3987 }
3988
3989 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3990 void Assembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3991 assert(VM_Version::supports_sse2(), "");
3992 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3993 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3994 emit_int8(0x75);
3995 emit_int8((unsigned char)(0xC0 | encode));
3996 }
3997
3998 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3999 void Assembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4000 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2(), "");
4001 assert(vector_len <= AVX_256bit, "evex encoding is different - has k register as dest");
4002 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4003 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4004 emit_int8(0x75);
4005 emit_int8((unsigned char)(0xC0 | encode));
4006 }
4007
4008 // In this context, kdst is written the mask used to process the equal components
4009 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
4010 assert(VM_Version::supports_avx512bw(), "");
4011 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4012 attributes.set_is_evex_instruction();
4013 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4014 emit_int8(0x75);
4015 emit_int8((unsigned char)(0xC0 | encode));
4016 }
4017
4018 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
4019 assert(VM_Version::supports_avx512bw(), "");
4020 InstructionMark im(this);
4021 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4022 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4023 attributes.set_is_evex_instruction();
4024 int dst_enc = kdst->encoding();
4025 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4026 emit_int8(0x75);
4027 emit_operand(as_Register(dst_enc), src);
4028 }
4029
4030 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
4031 void Assembler::pcmpeqd(XMMRegister dst, XMMRegister src) {
4032 assert(VM_Version::supports_sse2(), "");
4033 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4034 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4035 emit_int8(0x76);
4036 emit_int8((unsigned char)(0xC0 | encode));
4037 }
4038
4039 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
4040 void Assembler::vpcmpeqd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4041 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2(), "");
4042 assert(vector_len <= AVX_256bit, "evex encoding is different - has k register as dest");
4043 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4044 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4045 emit_int8((unsigned char)0x76);
4046 emit_int8((unsigned char)(0xC0 | encode));
4047 }
4048
4049 // In this context, kdst is written the mask used to process the equal components
4050 void Assembler::evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, int vector_len) {
4051 assert(VM_Version::supports_evex(), "");
4052 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4053 attributes.set_is_evex_instruction();
4054 attributes.reset_is_clear_context();
4055 attributes.set_embedded_opmask_register_specifier(mask);
4056 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4057 emit_int8(0x76);
4058 emit_int8((unsigned char)(0xC0 | encode));
4059 }
4060
4061 void Assembler::evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len) {
4062 assert(VM_Version::supports_evex(), "");
4063 InstructionMark im(this);
4064 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4065 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4066 attributes.set_is_evex_instruction();
4067 attributes.reset_is_clear_context();
4068 attributes.set_embedded_opmask_register_specifier(mask);
4069 int dst_enc = kdst->encoding();
4070 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4071 emit_int8(0x76);
4072 emit_operand(as_Register(dst_enc), src);
4073 }
4074
4075 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
4076 void Assembler::pcmpeqq(XMMRegister dst, XMMRegister src) {
4077 assert(VM_Version::supports_sse4_1(), "");
4078 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4079 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4080 emit_int8(0x29);
4081 emit_int8((unsigned char)(0xC0 | encode));
4082 }
4083
4084 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
4085 void Assembler::vpcmpeqq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4086 assert(VM_Version::supports_avx(), "");
4087 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4088 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4089 emit_int8(0x29);
4090 emit_int8((unsigned char)(0xC0 | encode));
4091 }
4092
4093 // In this context, kdst is written the mask used to process the equal components
4094 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
4095 assert(VM_Version::supports_evex(), "");
4096 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4097 attributes.reset_is_clear_context();
4098 attributes.set_is_evex_instruction();
4099 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4100 emit_int8(0x29);
4101 emit_int8((unsigned char)(0xC0 | encode));
4102 }
4103
4104 // In this context, kdst is written the mask used to process the equal components
4105 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
4106 assert(VM_Version::supports_evex(), "");
4107 InstructionMark im(this);
4108 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4109 attributes.reset_is_clear_context();
4110 attributes.set_is_evex_instruction();
4111 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4112 int dst_enc = kdst->encoding();
4113 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4114 emit_int8(0x29);
4115 emit_operand(as_Register(dst_enc), src);
4116 }
4117
4118 void Assembler::pcmpgtq(XMMRegister dst, XMMRegister src) {
4119 assert(VM_Version::supports_sse4_1(), "");
4120 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4121 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4122 emit_int8(0x37);
4123 emit_int8((unsigned char)(0xC0 | encode));
4124 }
4125
4126 void Assembler::pmovmskb(Register dst, XMMRegister src) {
4127 assert(VM_Version::supports_sse2(), "");
4128 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4129 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4130 emit_int8((unsigned char)0xD7);
4131 emit_int8((unsigned char)(0xC0 | encode));
4132 }
4133
4134 void Assembler::vpmovmskb(Register dst, XMMRegister src) {
4135 assert(VM_Version::supports_avx2(), "");
4136 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4137 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4138 emit_int8((unsigned char)0xD7);
4139 emit_int8((unsigned char)(0xC0 | encode));
4140 }
4141
4142 void Assembler::pextrd(Register dst, XMMRegister src, int imm8) {
4143 assert(VM_Version::supports_sse4_1(), "");
4144 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
4145 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4146 emit_int8(0x16);
4147 emit_int8((unsigned char)(0xC0 | encode));
4148 emit_int8(imm8);
4149 }
4150
4151 void Assembler::pextrd(Address dst, XMMRegister src, int imm8) {
4152 assert(VM_Version::supports_sse4_1(), "");
4153 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
4154 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4155 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4156 emit_int8(0x16);
4157 emit_operand(src, dst);
4158 emit_int8(imm8);
4159 }
4160
4161 void Assembler::pextrq(Register dst, XMMRegister src, int imm8) {
4162 assert(VM_Version::supports_sse4_1(), "");
4163 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
4164 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4165 emit_int8(0x16);
4166 emit_int8((unsigned char)(0xC0 | encode));
4167 emit_int8(imm8);
4168 }
4169
4170 void Assembler::pextrq(Address dst, XMMRegister src, int imm8) {
4171 assert(VM_Version::supports_sse4_1(), "");
4172 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
4173 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4174 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4175 emit_int8(0x16);
4176 emit_operand(src, dst);
4177 emit_int8(imm8);
4178 }
4179
4180 void Assembler::pextrw(Register dst, XMMRegister src, int imm8) {
4181 assert(VM_Version::supports_sse2(), "");
4182 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4183 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4184 emit_int8((unsigned char)0xC5);
4185 emit_int8((unsigned char)(0xC0 | encode));
4186 emit_int8(imm8);
4187 }
4188
4189 void Assembler::pextrw(Address dst, XMMRegister src, int imm8) {
4190 assert(VM_Version::supports_sse4_1(), "");
4191 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4192 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
4193 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4194 emit_int8((unsigned char)0x15);
4195 emit_operand(src, dst);
4196 emit_int8(imm8);
4197 }
4198
4199 void Assembler::pextrb(Register dst, XMMRegister src, int imm8) {
4200 assert(VM_Version::supports_sse4_1(), "");
4201 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
4202 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4203 emit_int8(0x14);
4204 emit_int8((unsigned char)(0xC0 | encode));
4205 emit_int8(imm8);
4206 }
4207
4208 void Assembler::pextrb(Address dst, XMMRegister src, int imm8) {
4209 assert(VM_Version::supports_sse4_1(), "");
4210 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4211 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
4212 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4213 emit_int8(0x14);
4214 emit_operand(src, dst);
4215 emit_int8(imm8);
4216 }
4217
4218 void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) {
4219 assert(VM_Version::supports_sse4_1(), "");
4220 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
4221 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4222 emit_int8(0x22);
4223 emit_int8((unsigned char)(0xC0 | encode));
4224 emit_int8(imm8);
4225 }
4226
4227 void Assembler::pinsrd(XMMRegister dst, Address src, int imm8) {
4228 assert(VM_Version::supports_sse4_1(), "");
4229 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
4230 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4231 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4232 emit_int8(0x22);
4233 emit_operand(dst,src);
4234 emit_int8(imm8);
4235 }
4236
4237 void Assembler::vpinsrd(XMMRegister dst, XMMRegister nds, Register src, int imm8) {
4238 assert(VM_Version::supports_avx(), "");
4239 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4240 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4241 emit_int8((unsigned char)0x22);
4242 emit_int8((unsigned char)(0xC0 | encode));
4243 emit_int8((unsigned char)imm8);
4244 }
4245
4246 void Assembler::pinsrq(XMMRegister dst, Register src, int imm8) {
4247 assert(VM_Version::supports_sse4_1(), "");
4248 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
4249 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4250 emit_int8(0x22);
4251 emit_int8((unsigned char)(0xC0 | encode));
4252 emit_int8(imm8);
4253 }
4254
4255 void Assembler::pinsrq(XMMRegister dst, Address src, int imm8) {
4256 assert(VM_Version::supports_sse4_1(), "");
4257 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
4258 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4259 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4260 emit_int8(0x22);
4261 emit_operand(dst, src);
4262 emit_int8(imm8);
4263 }
4264
4265 void Assembler::vpinsrq(XMMRegister dst, XMMRegister nds, Register src, int imm8) {
4266 assert(VM_Version::supports_avx(), "");
4267 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4268 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4269 emit_int8((unsigned char)0x22);
4270 emit_int8((unsigned char)(0xC0 | encode));
4271 emit_int8((unsigned char)imm8);
4272 }
4273
4274 void Assembler::pinsrw(XMMRegister dst, Register src, int imm8) {
4275 assert(VM_Version::supports_sse2(), "");
4276 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4277 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4278 emit_int8((unsigned char)0xC4);
4279 emit_int8((unsigned char)(0xC0 | encode));
4280 emit_int8(imm8);
4281 }
4282
4283 void Assembler::pinsrw(XMMRegister dst, Address src, int imm8) {
4284 assert(VM_Version::supports_sse2(), "");
4285 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4286 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
4287 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4288 emit_int8((unsigned char)0xC4);
4289 emit_operand(dst, src);
4290 emit_int8(imm8);
4291 }
4292
4293 void Assembler::vpinsrw(XMMRegister dst, XMMRegister nds, Register src, int imm8) {
4294 assert(VM_Version::supports_avx(), "");
4295 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4296 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4297 emit_int8((unsigned char)0xC4);
4298 emit_int8((unsigned char)(0xC0 | encode));
4299 emit_int8((unsigned char)imm8);
4300 }
4301
4302 void Assembler::pinsrb(XMMRegister dst, Address src, int imm8) {
4303 assert(VM_Version::supports_sse4_1(), "");
4304 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4305 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
4306 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4307 emit_int8(0x20);
4308 emit_operand(dst, src);
4309 emit_int8(imm8);
4310 }
4311
4312 void Assembler::pinsrb(XMMRegister dst, Register src, int imm8) {
4313 assert(VM_Version::supports_sse4_1(), "");
4314 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
4315 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4316 emit_int8(0x20);
4317 emit_int8((unsigned char)(0xC0 | encode));
4318 emit_int8(imm8);
4319 }
4320
4321 void Assembler::vpinsrb(XMMRegister dst, XMMRegister nds, Register src, int imm8) {
4322 assert(VM_Version::supports_avx(), "");
4323 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4324 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4325 emit_int8((unsigned char)0x20);
4326 emit_int8((unsigned char)(0xC0 | encode));
4327 emit_int8((unsigned char)imm8);
4328 }
4329
4330 void Assembler::insertps(XMMRegister dst, XMMRegister src, int imm8) {
4331 assert(VM_Version::supports_sse4_1(), "");
4332 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4333 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4334 emit_int8(0x21);
4335 emit_int8((unsigned char)(0xC0 | encode));
4336 emit_int8(imm8);
4337 }
4338
4339 void Assembler::vinsertps(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) {
4340 assert(VM_Version::supports_avx(), "");
4341 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4342 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4343 emit_int8(0x21);
4344 emit_int8((unsigned char)(0xC0 | encode));
4345 emit_int8(imm8);
4346 }
4347
4348 void Assembler::pmovzxbw(XMMRegister dst, Address src) {
4349 assert(VM_Version::supports_sse4_1(), "");
4350 InstructionMark im(this);
4351 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4352 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
4353 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4354 emit_int8(0x30);
4355 emit_operand(dst, src);
4356 }
4357
4358 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
4359 assert(VM_Version::supports_sse4_1(), "");
4360 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4361 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4362 emit_int8(0x30);
4363 emit_int8((unsigned char)(0xC0 | encode));
4364 }
4365
4366 void Assembler::pmovzxdq(XMMRegister dst, XMMRegister src) {
4367 assert(VM_Version::supports_sse4_1(), "");
4368 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4369 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4370 emit_int8(0x35);
4371 emit_int8((unsigned char)(0xC0 | encode));
4372 }
4373
4374 void Assembler::pmovsxbw(XMMRegister dst, XMMRegister src) {
4375 assert(VM_Version::supports_sse4_1(), "");
4376 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4377 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4378 emit_int8(0x20);
4379 emit_int8((unsigned char)(0xC0 | encode));
4380 }
4381
4382 void Assembler::pmovsxbd(XMMRegister dst, XMMRegister src) {
4383 assert(VM_Version::supports_sse4_1(), "");
4384 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4385 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4386 emit_int8(0x21);
4387 emit_int8((unsigned char)(0xC0 | encode));
4388 }
4389
4390 void Assembler::pmovsxbq(XMMRegister dst, XMMRegister src) {
4391 assert(VM_Version::supports_sse4_1(), "");
4392 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4393 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4394 emit_int8(0x22);
4395 emit_int8((unsigned char)(0xC0 | encode));
4396 }
4397
4398 void Assembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
4399 assert(VM_Version::supports_avx(), "");
4400 InstructionMark im(this);
4401 assert(dst != xnoreg, "sanity");
4402 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4403 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
4404 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4405 emit_int8(0x30);
4406 emit_operand(dst, src);
4407 }
4408
4409 void Assembler::vpmovzxbw(XMMRegister dst, XMMRegister src, int vector_len) {
4410 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
4411 vector_len == AVX_256bit? VM_Version::supports_avx2() :
4412 vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0, "");
4413 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4414 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4415 emit_int8(0x30);
4416 emit_int8((unsigned char) (0xC0 | encode));
4417 }
4418
4419 void Assembler::evpmovzxbw(XMMRegister dst, KRegister mask, Address src, int vector_len) {
4420 assert(is_vector_masking(), "");
4421 assert(VM_Version::supports_avx512vlbw(), "");
4422 assert(dst != xnoreg, "sanity");
4423 InstructionMark im(this);
4424 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4425 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
4426 attributes.set_embedded_opmask_register_specifier(mask);
4427 attributes.set_is_evex_instruction();
4428 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4429 emit_int8(0x30);
4430 emit_operand(dst, src);
4431 }
4432 void Assembler::vpmovzxdq(XMMRegister dst, XMMRegister src, int vector_len) {
4433 assert(vector_len > AVX_128bit ? VM_Version::supports_avx2() : VM_Version::supports_avx(), "");
4434 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4435 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4436 emit_int8(0x35);
4437 emit_int8((unsigned char)(0xC0 | encode));
4438 }
4439
4440 void Assembler::vpmovzxbd(XMMRegister dst, XMMRegister src, int vector_len) {
4441 assert(vector_len > AVX_128bit ? VM_Version::supports_avx2() : VM_Version::supports_avx(), "");
4442 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4443 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4444 emit_int8(0x31);
4445 emit_int8((unsigned char)(0xC0 | encode));
4446 }
4447
4448 void Assembler::vpmovzxbq(XMMRegister dst, XMMRegister src, int vector_len) {
4449 assert(vector_len > AVX_128bit ? VM_Version::supports_avx2() : VM_Version::supports_avx(), "");
4450 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4451 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4452 emit_int8(0x32);
4453 emit_int8((unsigned char)(0xC0 | encode));
4454 }
4455
4456 void Assembler::vpmovsxbd(XMMRegister dst, XMMRegister src, int vector_len) {
4457 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
4458 vector_len == AVX_256bit ? VM_Version::supports_avx2() :
4459 VM_Version::supports_evex(), "");
4460 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4461 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4462 emit_int8(0x21);
4463 emit_int8((unsigned char)(0xC0 | encode));
4464 }
4465
4466 void Assembler::vpmovsxbq(XMMRegister dst, XMMRegister src, int vector_len) {
4467 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
4468 vector_len == AVX_256bit ? VM_Version::supports_avx2() :
4469 VM_Version::supports_evex(), "");
4470 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4471 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4472 emit_int8(0x22);
4473 emit_int8((unsigned char)(0xC0 | encode));
4474 }
4475
4476 void Assembler::vpmovsxbw(XMMRegister dst, XMMRegister src, int vector_len) {
4477 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
4478 vector_len == AVX_256bit ? VM_Version::supports_avx2() :
4479 VM_Version::supports_evex(), "");
4480 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4481 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4482 emit_int8(0x20);
4483 emit_int8((unsigned char)(0xC0 | encode));
4484 }
4485
4486 void Assembler::vpmovsxwd(XMMRegister dst, XMMRegister src, int vector_len) {
4487 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
4488 vector_len == AVX_256bit ? VM_Version::supports_avx2() :
4489 VM_Version::supports_evex(), "");
4490 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4491 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4492 emit_int8(0x23);
4493 emit_int8((unsigned char)(0xC0 | encode));
4494 }
4495
4496 void Assembler::vpmovsxwq(XMMRegister dst, XMMRegister src, int vector_len) {
4497 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
4498 vector_len == AVX_256bit ? VM_Version::supports_avx2() :
4499 VM_Version::supports_evex(), "");
4500 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4501 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4502 emit_int8(0x24);
4503 emit_int8((unsigned char)(0xC0 | encode));
4504 }
4505
4506 void Assembler::vpmovsxdq(XMMRegister dst, XMMRegister src, int vector_len) {
4507 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
4508 vector_len == AVX_256bit ? VM_Version::supports_avx2() :
4509 VM_Version::supports_evex(), "");
4510 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4511 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4512 emit_int8(0x25);
4513 emit_int8((unsigned char)(0xC0 | encode));
4514 }
4515
4516 void Assembler::evpmovwb(Address dst, XMMRegister src, int vector_len) {
4517 assert(VM_Version::supports_avx512vlbw(), "");
4518 assert(src != xnoreg, "sanity");
4519 InstructionMark im(this);
4520 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4521 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
4522 attributes.set_is_evex_instruction();
4523 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
4524 emit_int8(0x30);
4525 emit_operand(src, dst);
4526 }
4527
4528 void Assembler::evpmovwb(Address dst, KRegister mask, XMMRegister src, int vector_len) {
4529 assert(is_vector_masking(), "");
4530 assert(VM_Version::supports_avx512vlbw(), "");
4531 assert(src != xnoreg, "sanity");
4532 InstructionMark im(this);
4533 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4534 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
4535 attributes.reset_is_clear_context();
4536 attributes.set_embedded_opmask_register_specifier(mask);
4537 attributes.set_is_evex_instruction();
4538 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
4539 emit_int8(0x30);
4540 emit_operand(src, dst);
4541 }
4542
4543 void Assembler::evpmovdb(Address dst, XMMRegister src, int vector_len) {
4544 assert(VM_Version::supports_evex(), "");
4545 assert(src != xnoreg, "sanity");
4546 InstructionMark im(this);
4547 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4548 attributes.set_address_attributes(/* tuple_type */ EVEX_QVM, /* input_size_in_bits */ EVEX_NObit);
4549 attributes.set_is_evex_instruction();
4550 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
4551 emit_int8(0x31);
4552 emit_operand(src, dst);
4553 }
4554
4555 void Assembler::vpmovzxwd(XMMRegister dst, XMMRegister src, int vector_len) {
4556 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
4557 vector_len == AVX_256bit? VM_Version::supports_avx2() :
4558 vector_len == AVX_512bit? VM_Version::supports_evex() : 0, " ");
4559 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4560 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4561 emit_int8(0x33);
4562 emit_int8((unsigned char)(0xC0 | encode));
4563 }
4564
4565 // generic
4566 void Assembler::pop(Register dst) {
4567 int encode = prefix_and_encode(dst->encoding());
4568 emit_int8(0x58 | encode);
4569 }
4570
4571 void Assembler::popcntl(Register dst, Address src) {
4572 assert(VM_Version::supports_popcnt(), "must support");
4573 InstructionMark im(this);
4574 emit_int8((unsigned char)0xF3);
4575 prefix(src, dst);
4576 emit_int8(0x0F);
4577 emit_int8((unsigned char)0xB8);
4578 emit_operand(dst, src);
4579 }
4580
4581 void Assembler::popcntl(Register dst, Register src) {
4582 assert(VM_Version::supports_popcnt(), "must support");
4583 emit_int8((unsigned char)0xF3);
4584 int encode = prefix_and_encode(dst->encoding(), src->encoding());
4585 emit_int8(0x0F);
4586 emit_int8((unsigned char)0xB8);
4587 emit_int8((unsigned char)(0xC0 | encode));
4588 }
4589
4590 void Assembler::vpopcntd(XMMRegister dst, XMMRegister src, int vector_len) {
4591 assert(VM_Version::supports_vpopcntdq(), "must support vpopcntdq feature");
4592 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4593 attributes.set_is_evex_instruction();
4594 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4595 emit_int8(0x55);
4596 emit_int8((unsigned char)(0xC0 | encode));
4597 }
4598
4599 void Assembler::popf() {
4600 emit_int8((unsigned char)0x9D);
4601 }
4602
4603 #ifndef _LP64 // no 32bit push/pop on amd64
4604 void Assembler::popl(Address dst) {
4605 // NOTE: this will adjust stack by 8byte on 64bits
4606 InstructionMark im(this);
4607 prefix(dst);
4608 emit_int8((unsigned char)0x8F);
4609 emit_operand(rax, dst);
4610 }
4611 #endif
4612
4613 void Assembler::prefetch_prefix(Address src) {
4614 prefix(src);
4615 emit_int8(0x0F);
4616 }
4617
4618 void Assembler::prefetchnta(Address src) {
4619 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
4620 InstructionMark im(this);
4621 prefetch_prefix(src);
4622 emit_int8(0x18);
4623 emit_operand(rax, src); // 0, src
4624 }
4625
4626 void Assembler::prefetchr(Address src) {
4627 assert(VM_Version::supports_3dnow_prefetch(), "must support");
4628 InstructionMark im(this);
4629 prefetch_prefix(src);
4630 emit_int8(0x0D);
4631 emit_operand(rax, src); // 0, src
4632 }
4633
4634 void Assembler::prefetcht0(Address src) {
4635 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
4636 InstructionMark im(this);
4637 prefetch_prefix(src);
4638 emit_int8(0x18);
4639 emit_operand(rcx, src); // 1, src
4640 }
4641
4642 void Assembler::prefetcht1(Address src) {
4643 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
4644 InstructionMark im(this);
4645 prefetch_prefix(src);
4646 emit_int8(0x18);
4647 emit_operand(rdx, src); // 2, src
4648 }
4649
4650 void Assembler::prefetcht2(Address src) {
4651 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
4652 InstructionMark im(this);
4653 prefetch_prefix(src);
4654 emit_int8(0x18);
4655 emit_operand(rbx, src); // 3, src
4656 }
4657
4658 void Assembler::prefetchw(Address src) {
4659 assert(VM_Version::supports_3dnow_prefetch(), "must support");
4660 InstructionMark im(this);
4661 prefetch_prefix(src);
4662 emit_int8(0x0D);
4663 emit_operand(rcx, src); // 1, src
4664 }
4665
4666 void Assembler::prefix(Prefix p) {
4667 emit_int8(p);
4668 }
4669
4670 void Assembler::pshufb(XMMRegister dst, XMMRegister src) {
4671 assert(VM_Version::supports_ssse3(), "");
4672 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4673 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4674 emit_int8(0x00);
4675 emit_int8((unsigned char)(0xC0 | encode));
4676 }
4677
4678 void Assembler::vpshufb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4679 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
4680 vector_len == AVX_256bit? VM_Version::supports_avx2() :
4681 0, "");
4682 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4683 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4684 emit_int8(0x00);
4685 emit_int8((unsigned char)(0xC0 | encode));
4686 }
4687
4688 void Assembler::pshufb(XMMRegister dst, Address src) {
4689 assert(VM_Version::supports_ssse3(), "");
4690 InstructionMark im(this);
4691 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4692 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4693 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4694 emit_int8(0x00);
4695 emit_operand(dst, src);
4696 }
4697
4698 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
4699 assert(isByte(mode), "invalid value");
4700 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4701 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
4702 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4703 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4704 emit_int8(0x70);
4705 emit_int8((unsigned char)(0xC0 | encode));
4706 emit_int8(mode & 0xFF);
4707 }
4708
4709 void Assembler::vpshufd(XMMRegister dst, XMMRegister src, int mode, int vector_len) {
4710 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
4711 vector_len == AVX_256bit? VM_Version::supports_avx2() :
4712 0, "");
4713 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4714 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4715 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4716 emit_int8(0x70);
4717 emit_int8((unsigned char)(0xC0 | encode));
4718 emit_int8(mode & 0xFF);
4719 }
4720
4721 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
4722 assert(isByte(mode), "invalid value");
4723 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4724 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4725 InstructionMark im(this);
4726 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4727 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4728 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4729 emit_int8(0x70);
4730 emit_operand(dst, src);
4731 emit_int8(mode & 0xFF);
4732 }
4733
4734 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
4735 assert(isByte(mode), "invalid value");
4736 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4737 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4738 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4739 emit_int8(0x70);
4740 emit_int8((unsigned char)(0xC0 | encode));
4741 emit_int8(mode & 0xFF);
4742 }
4743
4744 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
4745 assert(isByte(mode), "invalid value");
4746 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4747 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4748 InstructionMark im(this);
4749 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4750 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4751 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4752 emit_int8(0x70);
4753 emit_operand(dst, src);
4754 emit_int8(mode & 0xFF);
4755 }
4756 void Assembler::evshufi64x2(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
4757 assert(VM_Version::supports_evex(), "requires EVEX support");
4758 assert(vector_len == Assembler::AVX_256bit || vector_len == Assembler::AVX_512bit, "");
4759 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4760 attributes.set_is_evex_instruction();
4761 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4762 emit_int8(0x43);
4763 emit_int8((unsigned char)(0xC0 | encode));
4764 emit_int8(imm8 & 0xFF);
4765 }
4766 void Assembler::vpshufpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
4767 assert(vector_len == Assembler::AVX_128bit || Assembler::AVX_256bit || vector_len == Assembler::AVX_512bit, "");
4768 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4769 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4770 emit_int8(0xC6);
4771 emit_int8((unsigned char)(0xC0 | encode));
4772 emit_int8(imm8 & 0xFF);
4773 }
4774
4775 void Assembler::vpshufps(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
4776 assert(vector_len == Assembler::AVX_128bit || Assembler::AVX_256bit || vector_len == Assembler::AVX_512bit, "");
4777 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4778 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4779 emit_int8(0xC6);
4780 emit_int8((unsigned char)(0xC0 | encode));
4781 emit_int8(imm8 & 0xFF);
4782 }
4783 void Assembler::psrldq(XMMRegister dst, int shift) {
4784 // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
4785 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4786 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4787 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4788 emit_int8(0x73);
4789 emit_int8((unsigned char)(0xC0 | encode));
4790 emit_int8(shift);
4791 }
4792
4793 void Assembler::pslldq(XMMRegister dst, int shift) {
4794 // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
4795 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4796 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4797 // XMM7 is for /7 encoding: 66 0F 73 /7 ib
4798 int encode = simd_prefix_and_encode(xmm7, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4799 emit_int8(0x73);
4800 emit_int8((unsigned char)(0xC0 | encode));
4801 emit_int8(shift);
4802 }
4803
4804 void Assembler::ptest(XMMRegister dst, Address src) {
4805 assert(VM_Version::supports_sse4_1(), "");
4806 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4807 InstructionMark im(this);
4808 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4809 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4810 emit_int8(0x17);
4811 emit_operand(dst, src);
4812 }
4813
4814 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
4815 assert(VM_Version::supports_sse4_1(), "");
4816 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4817 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4818 emit_int8(0x17);
4819 emit_int8((unsigned char)(0xC0 | encode));
4820 }
4821
4822 void Assembler::vptest(XMMRegister dst, Address src) {
4823 assert(VM_Version::supports_avx(), "");
4824 InstructionMark im(this);
4825 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4826 assert(dst != xnoreg, "sanity");
4827 // swap src<->dst for encoding
4828 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4829 emit_int8(0x17);
4830 emit_operand(dst, src);
4831 }
4832
4833 void Assembler::vptest(XMMRegister dst, XMMRegister src) {
4834 assert(VM_Version::supports_avx(), "");
4835 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4836 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4837 emit_int8(0x17);
4838 emit_int8((unsigned char)(0xC0 | encode));
4839 }
4840
4841 void Assembler::vptest(XMMRegister dst, XMMRegister src, int vector_len) {
4842 assert(VM_Version::supports_avx(), "");
4843 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4844 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4845 emit_int8(0x17);
4846 emit_int8((unsigned char)(0xC0 | encode));
4847 }
4848
4849 void Assembler::punpcklbw(XMMRegister dst, Address src) {
4850 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4851 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4852 InstructionMark im(this);
4853 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ true, /* uses_vl */ true);
4854 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4855 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4856 emit_int8(0x60);
4857 emit_operand(dst, src);
4858 }
4859
4860 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
4861 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4862 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ true, /* uses_vl */ true);
4863 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4864 emit_int8(0x60);
4865 emit_int8((unsigned char)(0xC0 | encode));
4866 }
4867
4868 void Assembler::punpckldq(XMMRegister dst, Address src) {
4869 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4870 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4871 InstructionMark im(this);
4872 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4873 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4874 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4875 emit_int8(0x62);
4876 emit_operand(dst, src);
4877 }
4878
4879 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) {
4880 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4881 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4882 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4883 emit_int8(0x62);
4884 emit_int8((unsigned char)(0xC0 | encode));
4885 }
4886
4887 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) {
4888 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4889 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4890 attributes.set_rex_vex_w_reverted();
4891 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4892 emit_int8(0x6C);
4893 emit_int8((unsigned char)(0xC0 | encode));
4894 }
4895
4896 void Assembler::push(int32_t imm32) {
4897 // in 64bits we push 64bits onto the stack but only
4898 // take a 32bit immediate
4899 emit_int8(0x68);
4900 emit_int32(imm32);
4901 }
4902
4903 void Assembler::push(Register src) {
4904 int encode = prefix_and_encode(src->encoding());
4905
4906 emit_int8(0x50 | encode);
4907 }
4908
4909 void Assembler::pushf() {
4910 emit_int8((unsigned char)0x9C);
4911 }
4912
4913 #ifndef _LP64 // no 32bit push/pop on amd64
4914 void Assembler::pushl(Address src) {
4915 // Note this will push 64bit on 64bit
4916 InstructionMark im(this);
4917 prefix(src);
4918 emit_int8((unsigned char)0xFF);
4919 emit_operand(rsi, src);
4920 }
4921 #endif
4922
4923 void Assembler::rcll(Register dst, int imm8) {
4924 assert(isShiftCount(imm8), "illegal shift count");
4925 int encode = prefix_and_encode(dst->encoding());
4926 if (imm8 == 1) {
4927 emit_int8((unsigned char)0xD1);
4928 emit_int8((unsigned char)(0xD0 | encode));
4929 } else {
4930 emit_int8((unsigned char)0xC1);
4931 emit_int8((unsigned char)0xD0 | encode);
4932 emit_int8(imm8);
4933 }
4934 }
4935
4936 void Assembler::rcpps(XMMRegister dst, XMMRegister src) {
4937 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4938 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4939 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4940 emit_int8(0x53);
4941 emit_int8((unsigned char)(0xC0 | encode));
4942 }
4943
4944 void Assembler::rcpss(XMMRegister dst, XMMRegister src) {
4945 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4946 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4947 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4948 emit_int8(0x53);
4949 emit_int8((unsigned char)(0xC0 | encode));
4950 }
4951
4952 void Assembler::rdtsc() {
4953 emit_int8((unsigned char)0x0F);
4954 emit_int8((unsigned char)0x31);
4955 }
4956
4957 // copies data from [esi] to [edi] using rcx pointer sized words
4958 // generic
4959 void Assembler::rep_mov() {
4960 emit_int8((unsigned char)0xF3);
4961 // MOVSQ
4962 LP64_ONLY(prefix(REX_W));
4963 emit_int8((unsigned char)0xA5);
4964 }
4965
4966 // sets rcx bytes with rax, value at [edi]
4967 void Assembler::rep_stosb() {
4968 emit_int8((unsigned char)0xF3); // REP
4969 LP64_ONLY(prefix(REX_W));
4970 emit_int8((unsigned char)0xAA); // STOSB
4971 }
4972
4973 // sets rcx pointer sized words with rax, value at [edi]
4974 // generic
4975 void Assembler::rep_stos() {
4976 emit_int8((unsigned char)0xF3); // REP
4977 LP64_ONLY(prefix(REX_W)); // LP64:STOSQ, LP32:STOSD
4978 emit_int8((unsigned char)0xAB);
4979 }
4980
4981 // scans rcx pointer sized words at [edi] for occurance of rax,
4982 // generic
4983 void Assembler::repne_scan() { // repne_scan
4984 emit_int8((unsigned char)0xF2);
4985 // SCASQ
4986 LP64_ONLY(prefix(REX_W));
4987 emit_int8((unsigned char)0xAF);
4988 }
4989
4990 #ifdef _LP64
4991 // scans rcx 4 byte words at [edi] for occurance of rax,
4992 // generic
4993 void Assembler::repne_scanl() { // repne_scan
4994 emit_int8((unsigned char)0xF2);
4995 // SCASL
4996 emit_int8((unsigned char)0xAF);
4997 }
4998 #endif
4999
5000 void Assembler::ret(int imm16) {
5001 if (imm16 == 0) {
5002 emit_int8((unsigned char)0xC3);
5003 } else {
5004 emit_int8((unsigned char)0xC2);
5005 emit_int16(imm16);
5006 }
5007 }
5008
5009 void Assembler::sahf() {
5010 #ifdef _LP64
5011 // Not supported in 64bit mode
5012 ShouldNotReachHere();
5013 #endif
5014 emit_int8((unsigned char)0x9E);
5015 }
5016
5017 void Assembler::sarl(Register dst, int imm8) {
5018 int encode = prefix_and_encode(dst->encoding());
5019 assert(isShiftCount(imm8), "illegal shift count");
5020 if (imm8 == 1) {
5021 emit_int8((unsigned char)0xD1);
5022 emit_int8((unsigned char)(0xF8 | encode));
5023 } else {
5024 emit_int8((unsigned char)0xC1);
5025 emit_int8((unsigned char)(0xF8 | encode));
5026 emit_int8(imm8);
5027 }
5028 }
5029
5030 void Assembler::sarl(Register dst) {
5031 int encode = prefix_and_encode(dst->encoding());
5032 emit_int8((unsigned char)0xD3);
5033 emit_int8((unsigned char)(0xF8 | encode));
5034 }
5035
5036 void Assembler::sbbl(Address dst, int32_t imm32) {
5037 InstructionMark im(this);
5038 prefix(dst);
5039 emit_arith_operand(0x81, rbx, dst, imm32);
5040 }
5041
5042 void Assembler::sbbl(Register dst, int32_t imm32) {
5043 prefix(dst);
5044 emit_arith(0x81, 0xD8, dst, imm32);
5045 }
5046
5047
5048 void Assembler::sbbl(Register dst, Address src) {
5049 InstructionMark im(this);
5050 prefix(src, dst);
5051 emit_int8(0x1B);
5052 emit_operand(dst, src);
5053 }
5054
5055 void Assembler::sbbl(Register dst, Register src) {
5056 (void) prefix_and_encode(dst->encoding(), src->encoding());
5057 emit_arith(0x1B, 0xC0, dst, src);
5058 }
5059
5060 void Assembler::setb(Condition cc, Register dst) {
5061 assert(0 <= cc && cc < 16, "illegal cc");
5062 int encode = prefix_and_encode(dst->encoding(), true);
5063 emit_int8(0x0F);
5064 emit_int8((unsigned char)0x90 | cc);
5065 emit_int8((unsigned char)(0xC0 | encode));
5066 }
5067
5068 void Assembler::palignr(XMMRegister dst, XMMRegister src, int imm8) {
5069 assert(VM_Version::supports_ssse3(), "");
5070 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ false);
5071 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5072 emit_int8((unsigned char)0x0F);
5073 emit_int8((unsigned char)(0xC0 | encode));
5074 emit_int8(imm8);
5075 }
5076
5077 void Assembler::vpalignr(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
5078 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
5079 vector_len == AVX_256bit? VM_Version::supports_avx2() :
5080 0, "");
5081 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
5082 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5083 emit_int8((unsigned char)0x0F);
5084 emit_int8((unsigned char)(0xC0 | encode));
5085 emit_int8(imm8);
5086 }
5087
5088 void Assembler::evalignq(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
5089 assert(VM_Version::supports_evex(), "");
5090 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5091 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5092 emit_int8(0x3);
5093 emit_int8((unsigned char)(0xC0 | encode));
5094 emit_int8(imm8);
5095 }
5096
5097 void Assembler::pblendw(XMMRegister dst, XMMRegister src, int imm8) {
5098 assert(VM_Version::supports_sse4_1(), "");
5099 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
5100 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5101 emit_int8((unsigned char)0x0E);
5102 emit_int8((unsigned char)(0xC0 | encode));
5103 emit_int8(imm8);
5104 }
5105
5106 void Assembler::sha1rnds4(XMMRegister dst, XMMRegister src, int imm8) {
5107 assert(VM_Version::supports_sha(), "");
5108 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3A, /* rex_w */ false);
5109 emit_int8((unsigned char)0xCC);
5110 emit_int8((unsigned char)(0xC0 | encode));
5111 emit_int8((unsigned char)imm8);
5112 }
5113
5114 void Assembler::sha1nexte(XMMRegister dst, XMMRegister src) {
5115 assert(VM_Version::supports_sha(), "");
5116 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
5117 emit_int8((unsigned char)0xC8);
5118 emit_int8((unsigned char)(0xC0 | encode));
5119 }
5120
5121 void Assembler::sha1msg1(XMMRegister dst, XMMRegister src) {
5122 assert(VM_Version::supports_sha(), "");
5123 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
5124 emit_int8((unsigned char)0xC9);
5125 emit_int8((unsigned char)(0xC0 | encode));
5126 }
5127
5128 void Assembler::sha1msg2(XMMRegister dst, XMMRegister src) {
5129 assert(VM_Version::supports_sha(), "");
5130 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
5131 emit_int8((unsigned char)0xCA);
5132 emit_int8((unsigned char)(0xC0 | encode));
5133 }
5134
5135 // xmm0 is implicit additional source to this instruction.
5136 void Assembler::sha256rnds2(XMMRegister dst, XMMRegister src) {
5137 assert(VM_Version::supports_sha(), "");
5138 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
5139 emit_int8((unsigned char)0xCB);
5140 emit_int8((unsigned char)(0xC0 | encode));
5141 }
5142
5143 void Assembler::sha256msg1(XMMRegister dst, XMMRegister src) {
5144 assert(VM_Version::supports_sha(), "");
5145 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
5146 emit_int8((unsigned char)0xCC);
5147 emit_int8((unsigned char)(0xC0 | encode));
5148 }
5149
5150 void Assembler::sha256msg2(XMMRegister dst, XMMRegister src) {
5151 assert(VM_Version::supports_sha(), "");
5152 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
5153 emit_int8((unsigned char)0xCD);
5154 emit_int8((unsigned char)(0xC0 | encode));
5155 }
5156
5157
5158 void Assembler::shll(Register dst, int imm8) {
5159 assert(isShiftCount(imm8), "illegal shift count");
5160 int encode = prefix_and_encode(dst->encoding());
5161 if (imm8 == 1 ) {
5162 emit_int8((unsigned char)0xD1);
5163 emit_int8((unsigned char)(0xE0 | encode));
5164 } else {
5165 emit_int8((unsigned char)0xC1);
5166 emit_int8((unsigned char)(0xE0 | encode));
5167 emit_int8(imm8);
5168 }
5169 }
5170
5171 void Assembler::shll(Register dst) {
5172 int encode = prefix_and_encode(dst->encoding());
5173 emit_int8((unsigned char)0xD3);
5174 emit_int8((unsigned char)(0xE0 | encode));
5175 }
5176
5177 void Assembler::shrl(Register dst, int imm8) {
5178 assert(isShiftCount(imm8), "illegal shift count");
5179 int encode = prefix_and_encode(dst->encoding());
5180 emit_int8((unsigned char)0xC1);
5181 emit_int8((unsigned char)(0xE8 | encode));
5182 emit_int8(imm8);
5183 }
5184
5185 void Assembler::shrl(Register dst) {
5186 int encode = prefix_and_encode(dst->encoding());
5187 emit_int8((unsigned char)0xD3);
5188 emit_int8((unsigned char)(0xE8 | encode));
5189 }
5190
5191 // copies a single word from [esi] to [edi]
5192 void Assembler::smovl() {
5193 emit_int8((unsigned char)0xA5);
5194 }
5195
5196 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
5197 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5198 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5199 attributes.set_rex_vex_w_reverted();
5200 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5201 emit_int8(0x51);
5202 emit_int8((unsigned char)(0xC0 | encode));
5203 }
5204
5205 void Assembler::sqrtsd(XMMRegister dst, Address src) {
5206 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5207 InstructionMark im(this);
5208 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5209 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
5210 attributes.set_rex_vex_w_reverted();
5211 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5212 emit_int8(0x51);
5213 emit_operand(dst, src);
5214 }
5215
5216 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
5217 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5218 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5219 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5220 emit_int8(0x51);
5221 emit_int8((unsigned char)(0xC0 | encode));
5222 }
5223
5224 void Assembler::std() {
5225 emit_int8((unsigned char)0xFD);
5226 }
5227
5228 void Assembler::sqrtss(XMMRegister dst, Address src) {
5229 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5230 InstructionMark im(this);
5231 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5232 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
5233 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5234 emit_int8(0x51);
5235 emit_operand(dst, src);
5236 }
5237
5238 void Assembler::stmxcsr( Address dst) {
5239 if (UseAVX > 0 ) {
5240 assert(VM_Version::supports_avx(), "");
5241 InstructionMark im(this);
5242 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5243 vex_prefix(dst, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5244 emit_int8((unsigned char)0xAE);
5245 emit_operand(as_Register(3), dst);
5246 } else {
5247 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5248 InstructionMark im(this);
5249 prefix(dst);
5250 emit_int8(0x0F);
5251 emit_int8((unsigned char)0xAE);
5252 emit_operand(as_Register(3), dst);
5253 }
5254 }
5255
5256 void Assembler::subl(Address dst, int32_t imm32) {
5257 InstructionMark im(this);
5258 prefix(dst);
5259 emit_arith_operand(0x81, rbp, dst, imm32);
5260 }
5261
5262 void Assembler::subl(Address dst, Register src) {
5263 InstructionMark im(this);
5264 prefix(dst, src);
5265 emit_int8(0x29);
5266 emit_operand(src, dst);
5267 }
5268
5269 void Assembler::subl(Register dst, int32_t imm32) {
5270 prefix(dst);
5271 emit_arith(0x81, 0xE8, dst, imm32);
5272 }
5273
5274 // Force generation of a 4 byte immediate value even if it fits into 8bit
5275 void Assembler::subl_imm32(Register dst, int32_t imm32) {
5276 prefix(dst);
5277 emit_arith_imm32(0x81, 0xE8, dst, imm32);
5278 }
5279
5280 void Assembler::subl(Register dst, Address src) {
5281 InstructionMark im(this);
5282 prefix(src, dst);
5283 emit_int8(0x2B);
5284 emit_operand(dst, src);
5285 }
5286
5287 void Assembler::subl(Register dst, Register src) {
5288 (void) prefix_and_encode(dst->encoding(), src->encoding());
5289 emit_arith(0x2B, 0xC0, dst, src);
5290 }
5291
5292 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
5293 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5294 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5295 attributes.set_rex_vex_w_reverted();
5296 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5297 emit_int8(0x5C);
5298 emit_int8((unsigned char)(0xC0 | encode));
5299 }
5300
5301 void Assembler::subsd(XMMRegister dst, Address src) {
5302 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5303 InstructionMark im(this);
5304 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5305 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
5306 attributes.set_rex_vex_w_reverted();
5307 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5308 emit_int8(0x5C);
5309 emit_operand(dst, src);
5310 }
5311
5312 void Assembler::subss(XMMRegister dst, XMMRegister src) {
5313 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5314 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true , /* uses_vl */ false);
5315 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5316 emit_int8(0x5C);
5317 emit_int8((unsigned char)(0xC0 | encode));
5318 }
5319
5320 void Assembler::subss(XMMRegister dst, Address src) {
5321 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5322 InstructionMark im(this);
5323 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5324 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
5325 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5326 emit_int8(0x5C);
5327 emit_operand(dst, src);
5328 }
5329
5330 void Assembler::testb(Register dst, int imm8) {
5331 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
5332 (void) prefix_and_encode(dst->encoding(), true);
5333 emit_arith_b(0xF6, 0xC0, dst, imm8);
5334 }
5335
5336 void Assembler::testb(Address dst, int imm8) {
5337 InstructionMark im(this);
5338 prefix(dst);
5339 emit_int8((unsigned char)0xF6);
5340 emit_operand(rax, dst, 1);
5341 emit_int8(imm8);
5342 }
5343
5344 void Assembler::testl(Register dst, int32_t imm32) {
5345 // not using emit_arith because test
5346 // doesn't support sign-extension of
5347 // 8bit operands
5348 int encode = dst->encoding();
5349 if (encode == 0) {
5350 emit_int8((unsigned char)0xA9);
5351 } else {
5352 encode = prefix_and_encode(encode);
5353 emit_int8((unsigned char)0xF7);
5354 emit_int8((unsigned char)(0xC0 | encode));
5355 }
5356 emit_int32(imm32);
5357 }
5358
5359 void Assembler::testl(Register dst, Register src) {
5360 (void) prefix_and_encode(dst->encoding(), src->encoding());
5361 emit_arith(0x85, 0xC0, dst, src);
5362 }
5363
5364 void Assembler::testl(Register dst, Address src) {
5365 InstructionMark im(this);
5366 prefix(src, dst);
5367 emit_int8((unsigned char)0x85);
5368 emit_operand(dst, src);
5369 }
5370
5371 void Assembler::tzcntl(Register dst, Register src) {
5372 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
5373 emit_int8((unsigned char)0xF3);
5374 int encode = prefix_and_encode(dst->encoding(), src->encoding());
5375 emit_int8(0x0F);
5376 emit_int8((unsigned char)0xBC);
5377 emit_int8((unsigned char)0xC0 | encode);
5378 }
5379
5380 void Assembler::tzcntq(Register dst, Register src) {
5381 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
5382 emit_int8((unsigned char)0xF3);
5383 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5384 emit_int8(0x0F);
5385 emit_int8((unsigned char)0xBC);
5386 emit_int8((unsigned char)(0xC0 | encode));
5387 }
5388
5389 void Assembler::ucomisd(XMMRegister dst, Address src) {
5390 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5391 InstructionMark im(this);
5392 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5393 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
5394 attributes.set_rex_vex_w_reverted();
5395 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5396 emit_int8(0x2E);
5397 emit_operand(dst, src);
5398 }
5399
5400 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
5401 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5402 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5403 attributes.set_rex_vex_w_reverted();
5404 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5405 emit_int8(0x2E);
5406 emit_int8((unsigned char)(0xC0 | encode));
5407 }
5408
5409 void Assembler::ucomiss(XMMRegister dst, Address src) {
5410 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5411 InstructionMark im(this);
5412 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5413 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
5414 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5415 emit_int8(0x2E);
5416 emit_operand(dst, src);
5417 }
5418
5419 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
5420 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5421 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5422 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5423 emit_int8(0x2E);
5424 emit_int8((unsigned char)(0xC0 | encode));
5425 }
5426
5427 void Assembler::xabort(int8_t imm8) {
5428 emit_int8((unsigned char)0xC6);
5429 emit_int8((unsigned char)0xF8);
5430 emit_int8((unsigned char)(imm8 & 0xFF));
5431 }
5432
5433 void Assembler::xaddb(Address dst, Register src) {
5434 InstructionMark im(this);
5435 prefix(dst, src, true);
5436 emit_int8(0x0F);
5437 emit_int8((unsigned char)0xC0);
5438 emit_operand(src, dst);
5439 }
5440
5441 void Assembler::xaddw(Address dst, Register src) {
5442 InstructionMark im(this);
5443 emit_int8(0x66);
5444 prefix(dst, src);
5445 emit_int8(0x0F);
5446 emit_int8((unsigned char)0xC1);
5447 emit_operand(src, dst);
5448 }
5449
5450 void Assembler::xaddl(Address dst, Register src) {
5451 InstructionMark im(this);
5452 prefix(dst, src);
5453 emit_int8(0x0F);
5454 emit_int8((unsigned char)0xC1);
5455 emit_operand(src, dst);
5456 }
5457
5458 void Assembler::xbegin(Label& abort, relocInfo::relocType rtype) {
5459 InstructionMark im(this);
5460 relocate(rtype);
5461 if (abort.is_bound()) {
5462 address entry = target(abort);
5463 assert(entry != NULL, "abort entry NULL");
5464 intptr_t offset = entry - pc();
5465 emit_int8((unsigned char)0xC7);
5466 emit_int8((unsigned char)0xF8);
5467 emit_int32(offset - 6); // 2 opcode + 4 address
5468 } else {
5469 abort.add_patch_at(code(), locator());
5470 emit_int8((unsigned char)0xC7);
5471 emit_int8((unsigned char)0xF8);
5472 emit_int32(0);
5473 }
5474 }
5475
5476 void Assembler::xchgb(Register dst, Address src) { // xchg
5477 InstructionMark im(this);
5478 prefix(src, dst, true);
5479 emit_int8((unsigned char)0x86);
5480 emit_operand(dst, src);
5481 }
5482
5483 void Assembler::xchgw(Register dst, Address src) { // xchg
5484 InstructionMark im(this);
5485 emit_int8(0x66);
5486 prefix(src, dst);
5487 emit_int8((unsigned char)0x87);
5488 emit_operand(dst, src);
5489 }
5490
5491 void Assembler::xchgl(Register dst, Address src) { // xchg
5492 InstructionMark im(this);
5493 prefix(src, dst);
5494 emit_int8((unsigned char)0x87);
5495 emit_operand(dst, src);
5496 }
5497
5498 void Assembler::xchgl(Register dst, Register src) {
5499 int encode = prefix_and_encode(dst->encoding(), src->encoding());
5500 emit_int8((unsigned char)0x87);
5501 emit_int8((unsigned char)(0xC0 | encode));
5502 }
5503
5504 void Assembler::xend() {
5505 emit_int8((unsigned char)0x0F);
5506 emit_int8((unsigned char)0x01);
5507 emit_int8((unsigned char)0xD5);
5508 }
5509
5510 void Assembler::xgetbv() {
5511 emit_int8(0x0F);
5512 emit_int8(0x01);
5513 emit_int8((unsigned char)0xD0);
5514 }
5515
5516 void Assembler::xorl(Register dst, int32_t imm32) {
5517 prefix(dst);
5518 emit_arith(0x81, 0xF0, dst, imm32);
5519 }
5520
5521 void Assembler::xorl(Register dst, Address src) {
5522 InstructionMark im(this);
5523 prefix(src, dst);
5524 emit_int8(0x33);
5525 emit_operand(dst, src);
5526 }
5527
5528 void Assembler::xorl(Register dst, Register src) {
5529 (void) prefix_and_encode(dst->encoding(), src->encoding());
5530 emit_arith(0x33, 0xC0, dst, src);
5531 }
5532
5533 void Assembler::xorb(Register dst, Address src) {
5534 InstructionMark im(this);
5535 prefix(src, dst);
5536 emit_int8(0x32);
5537 emit_operand(dst, src);
5538 }
5539
5540 void Assembler::xorw(Register dst, Register src) {
5541 (void)prefix_and_encode(dst->encoding(), src->encoding());
5542 emit_arith(0x33, 0xC0, dst, src);
5543 }
5544
5545 // AVX 3-operands scalar float-point arithmetic instructions
5546
5547 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) {
5548 assert(VM_Version::supports_avx(), "");
5549 InstructionMark im(this);
5550 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5551 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
5552 attributes.set_rex_vex_w_reverted();
5553 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5554 emit_int8(0x58);
5555 emit_operand(dst, src);
5556 }
5557
5558 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5559 assert(VM_Version::supports_avx(), "");
5560 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5561 attributes.set_rex_vex_w_reverted();
5562 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5563 emit_int8(0x58);
5564 emit_int8((unsigned char)(0xC0 | encode));
5565 }
5566
5567 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) {
5568 assert(VM_Version::supports_avx(), "");
5569 InstructionMark im(this);
5570 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5571 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
5572 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5573 emit_int8(0x58);
5574 emit_operand(dst, src);
5575 }
5576
5577 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5578 assert(VM_Version::supports_avx(), "");
5579 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5580 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5581 emit_int8(0x58);
5582 emit_int8((unsigned char)(0xC0 | encode));
5583 }
5584
5585 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) {
5586 assert(VM_Version::supports_avx(), "");
5587 InstructionMark im(this);
5588 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5589 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
5590 attributes.set_rex_vex_w_reverted();
5591 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5592 emit_int8(0x5E);
5593 emit_operand(dst, src);
5594 }
5595
5596 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5597 assert(VM_Version::supports_avx(), "");
5598 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5599 attributes.set_rex_vex_w_reverted();
5600 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5601 emit_int8(0x5E);
5602 emit_int8((unsigned char)(0xC0 | encode));
5603 }
5604
5605 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) {
5606 assert(VM_Version::supports_avx(), "");
5607 InstructionMark im(this);
5608 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5609 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
5610 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5611 emit_int8(0x5E);
5612 emit_operand(dst, src);
5613 }
5614
5615 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5616 assert(VM_Version::supports_avx(), "");
5617 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5618 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5619 emit_int8(0x5E);
5620 emit_int8((unsigned char)(0xC0 | encode));
5621 }
5622
5623 void Assembler::vfmadd231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
5624 assert(VM_Version::supports_fma(), "");
5625 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5626 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5627 emit_int8((unsigned char)0xB9);
5628 emit_int8((unsigned char)(0xC0 | encode));
5629 }
5630
5631 void Assembler::vfmadd231ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
5632 assert(VM_Version::supports_fma(), "");
5633 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5634 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5635 emit_int8((unsigned char)0xB9);
5636 emit_int8((unsigned char)(0xC0 | encode));
5637 }
5638
5639 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) {
5640 assert(VM_Version::supports_avx(), "");
5641 InstructionMark im(this);
5642 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5643 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
5644 attributes.set_rex_vex_w_reverted();
5645 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5646 emit_int8(0x59);
5647 emit_operand(dst, src);
5648 }
5649
5650 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5651 assert(VM_Version::supports_avx(), "");
5652 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5653 attributes.set_rex_vex_w_reverted();
5654 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5655 emit_int8(0x59);
5656 emit_int8((unsigned char)(0xC0 | encode));
5657 }
5658
5659 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) {
5660 assert(VM_Version::supports_avx(), "");
5661 InstructionMark im(this);
5662 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5663 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
5664 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5665 emit_int8(0x59);
5666 emit_operand(dst, src);
5667 }
5668
5669 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5670 assert(VM_Version::supports_avx(), "");
5671 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5672 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5673 emit_int8(0x59);
5674 emit_int8((unsigned char)(0xC0 | encode));
5675 }
5676
5677 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) {
5678 assert(VM_Version::supports_avx(), "");
5679 InstructionMark im(this);
5680 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5681 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
5682 attributes.set_rex_vex_w_reverted();
5683 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5684 emit_int8(0x5C);
5685 emit_operand(dst, src);
5686 }
5687
5688 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5689 assert(VM_Version::supports_avx(), "");
5690 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5691 attributes.set_rex_vex_w_reverted();
5692 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5693 emit_int8(0x5C);
5694 emit_int8((unsigned char)(0xC0 | encode));
5695 }
5696
5697 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) {
5698 assert(VM_Version::supports_avx(), "");
5699 InstructionMark im(this);
5700 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5701 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
5702 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5703 emit_int8(0x5C);
5704 emit_operand(dst, src);
5705 }
5706
5707 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5708 assert(VM_Version::supports_avx(), "");
5709 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5710 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5711 emit_int8(0x5C);
5712 emit_int8((unsigned char)(0xC0 | encode));
5713 }
5714
5715 //====================VECTOR ARITHMETIC=====================================
5716
5717 // Float-point vector arithmetic
5718
5719 void Assembler::addpd(XMMRegister dst, XMMRegister src) {
5720 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5721 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5722 attributes.set_rex_vex_w_reverted();
5723 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5724 emit_int8(0x58);
5725 emit_int8((unsigned char)(0xC0 | encode));
5726 }
5727
5728 void Assembler::addpd(XMMRegister dst, Address src) {
5729 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5730 InstructionMark im(this);
5731 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5732 attributes.set_rex_vex_w_reverted();
5733 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5734 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5735 emit_int8(0x58);
5736 emit_operand(dst, src);
5737 }
5738
5739
5740 void Assembler::addps(XMMRegister dst, XMMRegister src) {
5741 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5742 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5743 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5744 emit_int8(0x58);
5745 emit_int8((unsigned char)(0xC0 | encode));
5746 }
5747
5748 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5749 assert(VM_Version::supports_avx(), "");
5750 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5751 attributes.set_rex_vex_w_reverted();
5752 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5753 emit_int8(0x58);
5754 emit_int8((unsigned char)(0xC0 | encode));
5755 }
5756
5757 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5758 assert(VM_Version::supports_avx(), "");
5759 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5760 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5761 emit_int8(0x58);
5762 emit_int8((unsigned char)(0xC0 | encode));
5763 }
5764
5765 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5766 assert(VM_Version::supports_avx(), "");
5767 InstructionMark im(this);
5768 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5769 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5770 attributes.set_rex_vex_w_reverted();
5771 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5772 emit_int8(0x58);
5773 emit_operand(dst, src);
5774 }
5775
5776 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5777 assert(VM_Version::supports_avx(), "");
5778 InstructionMark im(this);
5779 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5780 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5781 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5782 emit_int8(0x58);
5783 emit_operand(dst, src);
5784 }
5785
5786 void Assembler::subpd(XMMRegister dst, XMMRegister src) {
5787 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5788 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5789 attributes.set_rex_vex_w_reverted();
5790 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5791 emit_int8(0x5C);
5792 emit_int8((unsigned char)(0xC0 | encode));
5793 }
5794
5795 void Assembler::subps(XMMRegister dst, XMMRegister src) {
5796 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5797 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5798 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5799 emit_int8(0x5C);
5800 emit_int8((unsigned char)(0xC0 | encode));
5801 }
5802
5803 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5804 assert(VM_Version::supports_avx(), "");
5805 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5806 attributes.set_rex_vex_w_reverted();
5807 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5808 emit_int8(0x5C);
5809 emit_int8((unsigned char)(0xC0 | encode));
5810 }
5811
5812 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5813 assert(VM_Version::supports_avx(), "");
5814 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5815 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5816 emit_int8(0x5C);
5817 emit_int8((unsigned char)(0xC0 | encode));
5818 }
5819
5820 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5821 assert(VM_Version::supports_avx(), "");
5822 InstructionMark im(this);
5823 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5824 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5825 attributes.set_rex_vex_w_reverted();
5826 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5827 emit_int8(0x5C);
5828 emit_operand(dst, src);
5829 }
5830
5831 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5832 assert(VM_Version::supports_avx(), "");
5833 InstructionMark im(this);
5834 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5835 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5836 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5837 emit_int8(0x5C);
5838 emit_operand(dst, src);
5839 }
5840
5841 void Assembler::mulpd(XMMRegister dst, XMMRegister src) {
5842 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5843 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5844 attributes.set_rex_vex_w_reverted();
5845 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5846 emit_int8(0x59);
5847 emit_int8((unsigned char)(0xC0 | encode));
5848 }
5849
5850 void Assembler::mulpd(XMMRegister dst, Address src) {
5851 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5852 InstructionMark im(this);
5853 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5854 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5855 attributes.set_rex_vex_w_reverted();
5856 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5857 emit_int8(0x59);
5858 emit_operand(dst, src);
5859 }
5860
5861 void Assembler::mulps(XMMRegister dst, XMMRegister src) {
5862 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5863 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5864 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5865 emit_int8(0x59);
5866 emit_int8((unsigned char)(0xC0 | encode));
5867 }
5868
5869 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5870 assert(VM_Version::supports_avx(), "");
5871 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5872 attributes.set_rex_vex_w_reverted();
5873 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5874 emit_int8(0x59);
5875 emit_int8((unsigned char)(0xC0 | encode));
5876 }
5877
5878 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5879 assert(VM_Version::supports_avx(), "");
5880 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5881 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5882 emit_int8(0x59);
5883 emit_int8((unsigned char)(0xC0 | encode));
5884 }
5885
5886 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5887 assert(VM_Version::supports_avx(), "");
5888 InstructionMark im(this);
5889 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5890 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5891 attributes.set_rex_vex_w_reverted();
5892 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5893 emit_int8(0x59);
5894 emit_operand(dst, src);
5895 }
5896
5897 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5898 assert(VM_Version::supports_avx(), "");
5899 InstructionMark im(this);
5900 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5901 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5902 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5903 emit_int8(0x59);
5904 emit_operand(dst, src);
5905 }
5906
5907 void Assembler::vfmadd231pd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len) {
5908 assert(VM_Version::supports_fma(), "");
5909 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5910 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5911 emit_int8((unsigned char)0xB8);
5912 emit_int8((unsigned char)(0xC0 | encode));
5913 }
5914
5915 void Assembler::vfmadd231ps(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len) {
5916 assert(VM_Version::supports_fma(), "");
5917 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5918 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5919 emit_int8((unsigned char)0xB8);
5920 emit_int8((unsigned char)(0xC0 | encode));
5921 }
5922
5923 void Assembler::vfmadd231pd(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) {
5924 assert(VM_Version::supports_fma(), "");
5925 InstructionMark im(this);
5926 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5927 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5928 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5929 emit_int8((unsigned char)0xB8);
5930 emit_operand(dst, src2);
5931 }
5932
5933 void Assembler::vfmadd231ps(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) {
5934 assert(VM_Version::supports_fma(), "");
5935 InstructionMark im(this);
5936 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5937 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5938 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5939 emit_int8((unsigned char)0xB8);
5940 emit_operand(dst, src2);
5941 }
5942
5943 void Assembler::divpd(XMMRegister dst, XMMRegister src) {
5944 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5945 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5946 attributes.set_rex_vex_w_reverted();
5947 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5948 emit_int8(0x5E);
5949 emit_int8((unsigned char)(0xC0 | encode));
5950 }
5951
5952 void Assembler::divps(XMMRegister dst, XMMRegister src) {
5953 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5954 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5955 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5956 emit_int8(0x5E);
5957 emit_int8((unsigned char)(0xC0 | encode));
5958 }
5959
5960 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5961 assert(VM_Version::supports_avx(), "");
5962 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5963 attributes.set_rex_vex_w_reverted();
5964 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5965 emit_int8(0x5E);
5966 emit_int8((unsigned char)(0xC0 | encode));
5967 }
5968
5969 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5970 assert(VM_Version::supports_avx(), "");
5971 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5972 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5973 emit_int8(0x5E);
5974 emit_int8((unsigned char)(0xC0 | encode));
5975 }
5976
5977 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5978 assert(VM_Version::supports_avx(), "");
5979 InstructionMark im(this);
5980 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5981 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5982 attributes.set_rex_vex_w_reverted();
5983 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5984 emit_int8(0x5E);
5985 emit_operand(dst, src);
5986 }
5987
5988 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5989 assert(VM_Version::supports_avx(), "");
5990 InstructionMark im(this);
5991 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5992 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5993 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5994 emit_int8(0x5E);
5995 emit_operand(dst, src);
5996 }
5997
5998 void Assembler::vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len) {
5999 assert(VM_Version::supports_avx(), "");
6000 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6001 attributes.set_rex_vex_w_reverted();
6002 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6003 emit_int8(0x51);
6004 emit_int8((unsigned char)(0xC0 | encode));
6005 }
6006
6007 void Assembler::vsqrtpd(XMMRegister dst, Address src, int vector_len) {
6008 assert(VM_Version::supports_avx(), "");
6009 InstructionMark im(this);
6010 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6011 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
6012 attributes.set_rex_vex_w_reverted();
6013 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6014 emit_int8(0x51);
6015 emit_operand(dst, src);
6016 }
6017
6018 void Assembler::vsqrtps(XMMRegister dst, XMMRegister src, int vector_len) {
6019 assert(VM_Version::supports_avx(), "");
6020 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6021 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6022 emit_int8(0x51);
6023 emit_int8((unsigned char)(0xC0 | encode));
6024 }
6025
6026 void Assembler::vsqrtps(XMMRegister dst, Address src, int vector_len) {
6027 assert(VM_Version::supports_avx(), "");
6028 InstructionMark im(this);
6029 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6030 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
6031 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6032 emit_int8(0x51);
6033 emit_operand(dst, src);
6034 }
6035
6036 void Assembler::andpd(XMMRegister dst, XMMRegister src) {
6037 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6038 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
6039 attributes.set_rex_vex_w_reverted();
6040 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6041 emit_int8(0x54);
6042 emit_int8((unsigned char)(0xC0 | encode));
6043 }
6044
6045 void Assembler::andps(XMMRegister dst, XMMRegister src) {
6046 NOT_LP64(assert(VM_Version::supports_sse(), ""));
6047 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
6048 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6049 emit_int8(0x54);
6050 emit_int8((unsigned char)(0xC0 | encode));
6051 }
6052
6053 void Assembler::andps(XMMRegister dst, Address src) {
6054 NOT_LP64(assert(VM_Version::supports_sse(), ""));
6055 InstructionMark im(this);
6056 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
6057 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
6058 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6059 emit_int8(0x54);
6060 emit_operand(dst, src);
6061 }
6062
6063 void Assembler::andpd(XMMRegister dst, Address src) {
6064 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6065 InstructionMark im(this);
6066 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
6067 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
6068 attributes.set_rex_vex_w_reverted();
6069 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6070 emit_int8(0x54);
6071 emit_operand(dst, src);
6072 }
6073
6074 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6075 assert(VM_Version::supports_avx(), "");
6076 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
6077 attributes.set_rex_vex_w_reverted();
6078 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6079 emit_int8(0x54);
6080 emit_int8((unsigned char)(0xC0 | encode));
6081 }
6082
6083 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6084 assert(VM_Version::supports_avx(), "");
6085 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
6086 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6087 emit_int8(0x54);
6088 emit_int8((unsigned char)(0xC0 | encode));
6089 }
6090
6091 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6092 assert(VM_Version::supports_avx(), "");
6093 InstructionMark im(this);
6094 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
6095 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
6096 attributes.set_rex_vex_w_reverted();
6097 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6098 emit_int8(0x54);
6099 emit_operand(dst, src);
6100 }
6101
6102 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6103 assert(VM_Version::supports_avx(), "");
6104 InstructionMark im(this);
6105 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
6106 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
6107 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6108 emit_int8(0x54);
6109 emit_operand(dst, src);
6110 }
6111
6112 void Assembler::unpckhpd(XMMRegister dst, XMMRegister src) {
6113 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6114 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6115 attributes.set_rex_vex_w_reverted();
6116 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6117 emit_int8(0x15);
6118 emit_int8((unsigned char)(0xC0 | encode));
6119 }
6120
6121 void Assembler::unpcklpd(XMMRegister dst, XMMRegister src) {
6122 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6123 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6124 attributes.set_rex_vex_w_reverted();
6125 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6126 emit_int8(0x14);
6127 emit_int8((unsigned char)(0xC0 | encode));
6128 }
6129
6130 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
6131 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6132 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
6133 attributes.set_rex_vex_w_reverted();
6134 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6135 emit_int8(0x57);
6136 emit_int8((unsigned char)(0xC0 | encode));
6137 }
6138
6139 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
6140 NOT_LP64(assert(VM_Version::supports_sse(), ""));
6141 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
6142 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6143 emit_int8(0x57);
6144 emit_int8((unsigned char)(0xC0 | encode));
6145 }
6146
6147 void Assembler::xorpd(XMMRegister dst, Address src) {
6148 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6149 InstructionMark im(this);
6150 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
6151 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
6152 attributes.set_rex_vex_w_reverted();
6153 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6154 emit_int8(0x57);
6155 emit_operand(dst, src);
6156 }
6157
6158 void Assembler::xorps(XMMRegister dst, Address src) {
6159 NOT_LP64(assert(VM_Version::supports_sse(), ""));
6160 InstructionMark im(this);
6161 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
6162 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
6163 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6164 emit_int8(0x57);
6165 emit_operand(dst, src);
6166 }
6167
6168 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6169 assert(VM_Version::supports_avx(), "");
6170 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
6171 attributes.set_rex_vex_w_reverted();
6172 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6173 emit_int8(0x57);
6174 emit_int8((unsigned char)(0xC0 | encode));
6175 }
6176
6177 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6178 assert(VM_Version::supports_avx(), "");
6179 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
6180 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6181 emit_int8(0x57);
6182 emit_int8((unsigned char)(0xC0 | encode));
6183 }
6184
6185 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6186 assert(VM_Version::supports_avx(), "");
6187 InstructionMark im(this);
6188 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
6189 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
6190 attributes.set_rex_vex_w_reverted();
6191 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6192 emit_int8(0x57);
6193 emit_operand(dst, src);
6194 }
6195
6196 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6197 assert(VM_Version::supports_avx(), "");
6198 InstructionMark im(this);
6199 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
6200 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
6201 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6202 emit_int8(0x57);
6203 emit_operand(dst, src);
6204 }
6205
6206 // Integer vector arithmetic
6207 void Assembler::vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6208 assert(VM_Version::supports_avx() && (vector_len == 0) ||
6209 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
6210 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
6211 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6212 emit_int8(0x01);
6213 emit_int8((unsigned char)(0xC0 | encode));
6214 }
6215
6216 void Assembler::vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6217 assert(VM_Version::supports_avx() && (vector_len == 0) ||
6218 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
6219 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6220 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6221 emit_int8(0x02);
6222 emit_int8((unsigned char)(0xC0 | encode));
6223 }
6224
6225 void Assembler::paddb(XMMRegister dst, XMMRegister src) {
6226 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6227 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6228 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6229 emit_int8((unsigned char)0xFC);
6230 emit_int8((unsigned char)(0xC0 | encode));
6231 }
6232
6233 void Assembler::paddw(XMMRegister dst, XMMRegister src) {
6234 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6235 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6236 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6237 emit_int8((unsigned char)0xFD);
6238 emit_int8((unsigned char)(0xC0 | encode));
6239 }
6240
6241 void Assembler::paddd(XMMRegister dst, XMMRegister src) {
6242 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6243 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6244 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6245 emit_int8((unsigned char)0xFE);
6246 emit_int8((unsigned char)(0xC0 | encode));
6247 }
6248
6249 void Assembler::paddd(XMMRegister dst, Address src) {
6250 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6251 InstructionMark im(this);
6252 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6253 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6254 emit_int8((unsigned char)0xFE);
6255 emit_operand(dst, src);
6256 }
6257
6258 void Assembler::paddq(XMMRegister dst, XMMRegister src) {
6259 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6260 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6261 attributes.set_rex_vex_w_reverted();
6262 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6263 emit_int8((unsigned char)0xD4);
6264 emit_int8((unsigned char)(0xC0 | encode));
6265 }
6266
6267 void Assembler::phaddw(XMMRegister dst, XMMRegister src) {
6268 assert(VM_Version::supports_sse3(), "");
6269 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
6270 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6271 emit_int8(0x01);
6272 emit_int8((unsigned char)(0xC0 | encode));
6273 }
6274
6275 void Assembler::phaddd(XMMRegister dst, XMMRegister src) {
6276 assert(VM_Version::supports_sse3(), "");
6277 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6278 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6279 emit_int8(0x02);
6280 emit_int8((unsigned char)(0xC0 | encode));
6281 }
6282
6283 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6284 assert(UseAVX > 0, "requires some form of AVX");
6285 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6286 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6287 emit_int8((unsigned char)0xFC);
6288 emit_int8((unsigned char)(0xC0 | encode));
6289 }
6290
6291 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6292 assert(UseAVX > 0, "requires some form of AVX");
6293 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6294 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6295 emit_int8((unsigned char)0xFD);
6296 emit_int8((unsigned char)(0xC0 | encode));
6297 }
6298
6299 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6300 assert(UseAVX > 0, "requires some form of AVX");
6301 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6302 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6303 emit_int8((unsigned char)0xFE);
6304 emit_int8((unsigned char)(0xC0 | encode));
6305 }
6306
6307 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6308 assert(UseAVX > 0, "requires some form of AVX");
6309 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6310 attributes.set_rex_vex_w_reverted();
6311 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6312 emit_int8((unsigned char)0xD4);
6313 emit_int8((unsigned char)(0xC0 | encode));
6314 }
6315
6316 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6317 assert(UseAVX > 0, "requires some form of AVX");
6318 InstructionMark im(this);
6319 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6320 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
6321 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6322 emit_int8((unsigned char)0xFC);
6323 emit_operand(dst, src);
6324 }
6325
6326 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6327 assert(UseAVX > 0, "requires some form of AVX");
6328 InstructionMark im(this);
6329 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6330 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
6331 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6332 emit_int8((unsigned char)0xFD);
6333 emit_operand(dst, src);
6334 }
6335
6336 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6337 assert(UseAVX > 0, "requires some form of AVX");
6338 InstructionMark im(this);
6339 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6340 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
6341 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6342 emit_int8((unsigned char)0xFE);
6343 emit_operand(dst, src);
6344 }
6345
6346 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6347 assert(UseAVX > 0, "requires some form of AVX");
6348 InstructionMark im(this);
6349 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6350 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
6351 attributes.set_rex_vex_w_reverted();
6352 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6353 emit_int8((unsigned char)0xD4);
6354 emit_operand(dst, src);
6355 }
6356
6357 void Assembler::psubb(XMMRegister dst, XMMRegister src) {
6358 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6359 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6360 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6361 emit_int8((unsigned char)0xF8);
6362 emit_int8((unsigned char)(0xC0 | encode));
6363 }
6364
6365 void Assembler::psubw(XMMRegister dst, XMMRegister src) {
6366 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6367 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6368 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6369 emit_int8((unsigned char)0xF9);
6370 emit_int8((unsigned char)(0xC0 | encode));
6371 }
6372
6373 void Assembler::psubd(XMMRegister dst, XMMRegister src) {
6374 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6375 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6376 emit_int8((unsigned char)0xFA);
6377 emit_int8((unsigned char)(0xC0 | encode));
6378 }
6379
6380 void Assembler::psubq(XMMRegister dst, XMMRegister src) {
6381 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6382 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6383 attributes.set_rex_vex_w_reverted();
6384 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6385 emit_int8((unsigned char)0xFB);
6386 emit_int8((unsigned char)(0xC0 | encode));
6387 }
6388
6389 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6390 assert(UseAVX > 0, "requires some form of AVX");
6391 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6392 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6393 emit_int8((unsigned char)0xF8);
6394 emit_int8((unsigned char)(0xC0 | encode));
6395 }
6396
6397 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6398 assert(UseAVX > 0, "requires some form of AVX");
6399 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6400 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6401 emit_int8((unsigned char)0xF9);
6402 emit_int8((unsigned char)(0xC0 | encode));
6403 }
6404
6405 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6406 assert(UseAVX > 0, "requires some form of AVX");
6407 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6408 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6409 emit_int8((unsigned char)0xFA);
6410 emit_int8((unsigned char)(0xC0 | encode));
6411 }
6412
6413 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6414 assert(UseAVX > 0, "requires some form of AVX");
6415 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6416 attributes.set_rex_vex_w_reverted();
6417 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6418 emit_int8((unsigned char)0xFB);
6419 emit_int8((unsigned char)(0xC0 | encode));
6420 }
6421
6422 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6423 assert(UseAVX > 0, "requires some form of AVX");
6424 InstructionMark im(this);
6425 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6426 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
6427 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6428 emit_int8((unsigned char)0xF8);
6429 emit_operand(dst, src);
6430 }
6431
6432 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6433 assert(UseAVX > 0, "requires some form of AVX");
6434 InstructionMark im(this);
6435 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6436 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
6437 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6438 emit_int8((unsigned char)0xF9);
6439 emit_operand(dst, src);
6440 }
6441
6442 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6443 assert(UseAVX > 0, "requires some form of AVX");
6444 InstructionMark im(this);
6445 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6446 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
6447 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6448 emit_int8((unsigned char)0xFA);
6449 emit_operand(dst, src);
6450 }
6451
6452 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6453 assert(UseAVX > 0, "requires some form of AVX");
6454 InstructionMark im(this);
6455 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6456 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
6457 attributes.set_rex_vex_w_reverted();
6458 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6459 emit_int8((unsigned char)0xFB);
6460 emit_operand(dst, src);
6461 }
6462
6463 void Assembler::pmullw(XMMRegister dst, XMMRegister src) {
6464 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6465 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6466 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6467 emit_int8((unsigned char)0xD5);
6468 emit_int8((unsigned char)(0xC0 | encode));
6469 }
6470
6471 void Assembler::pmulld(XMMRegister dst, XMMRegister src) {
6472 assert(VM_Version::supports_sse4_1(), "");
6473 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6474 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6475 emit_int8(0x40);
6476 emit_int8((unsigned char)(0xC0 | encode));
6477 }
6478
6479 void Assembler::pmuludq(XMMRegister dst, XMMRegister src) {
6480 assert(VM_Version::supports_sse2(), "");
6481 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6482 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6483 emit_int8((unsigned char)(0xF4));
6484 emit_int8((unsigned char)(0xC0 | encode));
6485 }
6486
6487 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6488 assert(UseAVX > 0, "requires some form of AVX");
6489 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6490 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6491 emit_int8((unsigned char)0xD5);
6492 emit_int8((unsigned char)(0xC0 | encode));
6493 }
6494
6495 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6496 assert(UseAVX > 0, "requires some form of AVX");
6497 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6498 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6499 emit_int8(0x40);
6500 emit_int8((unsigned char)(0xC0 | encode));
6501 }
6502
6503 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6504 assert(UseAVX > 2, "requires some form of EVEX");
6505 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
6506 attributes.set_is_evex_instruction();
6507 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6508 emit_int8(0x40);
6509 emit_int8((unsigned char)(0xC0 | encode));
6510 }
6511
6512 void Assembler::vpmuludq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6513 assert(UseAVX > 0, "requires some form of AVX");
6514 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6515 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6516 emit_int8((unsigned char)(0xF4));
6517 emit_int8((unsigned char)(0xC0 | encode));
6518 }
6519
6520 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6521 assert(UseAVX > 0, "requires some form of AVX");
6522 InstructionMark im(this);
6523 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6524 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
6525 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6526 emit_int8((unsigned char)0xD5);
6527 emit_operand(dst, src);
6528 }
6529
6530 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6531 assert(UseAVX > 0, "requires some form of AVX");
6532 InstructionMark im(this);
6533 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6534 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
6535 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6536 emit_int8(0x40);
6537 emit_operand(dst, src);
6538 }
6539
6540 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6541 assert(UseAVX > 2, "requires some form of EVEX");
6542 InstructionMark im(this);
6543 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
6544 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
6545 attributes.set_is_evex_instruction();
6546 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6547 emit_int8(0x40);
6548 emit_operand(dst, src);
6549 }
6550
6551 // Min, max
6552 void Assembler::pminsb(XMMRegister dst, XMMRegister src) {
6553 assert(VM_Version::supports_sse4_1(), "");
6554 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6555 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6556 emit_int8(0x38);
6557 emit_int8((unsigned char)(0xC0 | encode));
6558 }
6559
6560 void Assembler::vpminsb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6561 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
6562 (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_avx512bw()), "");
6563 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6564 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6565 emit_int8(0x38);
6566 emit_int8((unsigned char)(0xC0 | encode));
6567 }
6568
6569 void Assembler::pminsw(XMMRegister dst, XMMRegister src) {
6570 assert(VM_Version::supports_sse2(), "");
6571 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6572 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6573 emit_int8((unsigned char)0xEA);
6574 emit_int8((unsigned char)(0xC0 | encode));
6575 }
6576
6577 void Assembler::vpminsw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6578 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
6579 (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_avx512bw()), "");
6580 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6581 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6582 emit_int8((unsigned char)0xEA);
6583 emit_int8((unsigned char)(0xC0 | encode));
6584 }
6585
6586 void Assembler::pminsd(XMMRegister dst, XMMRegister src) {
6587 assert(VM_Version::supports_sse4_1(), "");
6588 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
6589 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6590 emit_int8(0x39);
6591 emit_int8((unsigned char)(0xC0 | encode));
6592 }
6593
6594 void Assembler::vpminsd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6595 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
6596 (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex()), "");
6597 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
6598 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6599 emit_int8(0x39);
6600 emit_int8((unsigned char)(0xC0 | encode));
6601 }
6602
6603 void Assembler::vpminsq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6604 assert(UseAVX > 2, "requires AVX512F");
6605 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6606 attributes.set_is_evex_instruction();
6607 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6608 emit_int8(0x39);
6609 emit_int8((unsigned char)(0xC0 | encode));
6610 }
6611
6612 void Assembler::minps(XMMRegister dst, XMMRegister src) {
6613 NOT_LP64(assert(VM_Version::supports_sse(), ""));
6614 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6615 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6616 emit_int8(0x5D);
6617 emit_int8((unsigned char)(0xC0 | encode));
6618 }
6619 void Assembler::vminps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6620 assert(vector_len >= AVX_512bit ? VM_Version::supports_evex() : VM_Version::supports_avx(), "");
6621 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6622 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6623 emit_int8(0x5D);
6624 emit_int8((unsigned char)(0xC0 | encode));
6625 }
6626
6627 void Assembler::minpd(XMMRegister dst, XMMRegister src) {
6628 NOT_LP64(assert(VM_Version::supports_sse(), ""));
6629 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6630 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6631 emit_int8(0x5D);
6632 emit_int8((unsigned char)(0xC0 | encode));
6633 }
6634 void Assembler::vminpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6635 assert(vector_len >= AVX_512bit ? VM_Version::supports_evex() : VM_Version::supports_avx(), "");
6636 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6637 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6638 emit_int8(0x5D);
6639 emit_int8((unsigned char)(0xC0 | encode));
6640 }
6641
6642 void Assembler::pmaxsb(XMMRegister dst, XMMRegister src) {
6643 assert(VM_Version::supports_sse4_1(), "");
6644 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6645 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6646 emit_int8(0x3C);
6647 emit_int8((unsigned char)(0xC0 | encode));
6648 }
6649
6650 void Assembler::vpmaxsb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6651 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
6652 (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_avx512bw()), "");
6653 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6654 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6655 emit_int8(0x3C);
6656 emit_int8((unsigned char)(0xC0 | encode));
6657 }
6658
6659 void Assembler::pmaxsw(XMMRegister dst, XMMRegister src) {
6660 assert(VM_Version::supports_sse2(), "");
6661 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6662 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6663 emit_int8((unsigned char)0xEE);
6664 emit_int8((unsigned char)(0xC0 | encode));
6665 }
6666
6667 void Assembler::vpmaxsw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6668 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
6669 (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_avx512bw()), "");
6670 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6671 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6672 emit_int8((unsigned char)0xEE);
6673 emit_int8((unsigned char)(0xC0 | encode));
6674 }
6675
6676 void Assembler::pmaxsd(XMMRegister dst, XMMRegister src) {
6677 assert(VM_Version::supports_sse4_1(), "");
6678 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
6679 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6680 emit_int8(0x3D);
6681 emit_int8((unsigned char)(0xC0 | encode));
6682 }
6683
6684 void Assembler::vpmaxsd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6685 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
6686 (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex()), "");
6687 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
6688 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6689 emit_int8(0x3D);
6690 emit_int8((unsigned char)(0xC0 | encode));
6691 }
6692
6693 void Assembler::vpmaxsq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6694 assert(UseAVX > 2, "requires AVX512F");
6695 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6696 attributes.set_is_evex_instruction();
6697 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6698 emit_int8(0x3D);
6699 emit_int8((unsigned char)(0xC0 | encode));
6700 }
6701
6702 void Assembler::maxps(XMMRegister dst, XMMRegister src) {
6703 NOT_LP64(assert(VM_Version::supports_sse(), ""));
6704 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6705 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6706 emit_int8(0x5F);
6707 emit_int8((unsigned char)(0xC0 | encode));
6708 }
6709
6710 void Assembler::vmaxps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6711 assert(vector_len >= AVX_512bit ? VM_Version::supports_evex() : VM_Version::supports_avx(), "");
6712 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6713 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6714 emit_int8(0x5F);
6715 emit_int8((unsigned char)(0xC0 | encode));
6716 }
6717
6718 void Assembler::maxpd(XMMRegister dst, XMMRegister src) {
6719 NOT_LP64(assert(VM_Version::supports_sse(), ""));
6720 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6721 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6722 emit_int8(0x5F);
6723 emit_int8((unsigned char)(0xC0 | encode));
6724 }
6725
6726 void Assembler::vmaxpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6727 assert(vector_len >= AVX_512bit ? VM_Version::supports_evex() : VM_Version::supports_avx(), "");
6728 InstructionAttr attributes(vector_len, /* vex_w */true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6729 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6730 emit_int8(0x5F);
6731 emit_int8((unsigned char)(0xC0 | encode));
6732 }
6733
6734 // Shift packed integers left by specified number of bits.
6735 void Assembler::psllw(XMMRegister dst, int shift) {
6736 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6737 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6738 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
6739 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6740 emit_int8(0x71);
6741 emit_int8((unsigned char)(0xC0 | encode));
6742 emit_int8(shift & 0xFF);
6743 }
6744
6745 void Assembler::pslld(XMMRegister dst, int shift) {
6746 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6747 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6748 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
6749 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6750 emit_int8(0x72);
6751 emit_int8((unsigned char)(0xC0 | encode));
6752 emit_int8(shift & 0xFF);
6753 }
6754
6755 void Assembler::psllq(XMMRegister dst, int shift) {
6756 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6757 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6758 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
6759 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6760 emit_int8(0x73);
6761 emit_int8((unsigned char)(0xC0 | encode));
6762 emit_int8(shift & 0xFF);
6763 }
6764
6765 void Assembler::psllw(XMMRegister dst, XMMRegister shift) {
6766 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6767 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6768 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6769 emit_int8((unsigned char)0xF1);
6770 emit_int8((unsigned char)(0xC0 | encode));
6771 }
6772
6773 void Assembler::pslld(XMMRegister dst, XMMRegister shift) {
6774 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6775 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6776 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6777 emit_int8((unsigned char)0xF2);
6778 emit_int8((unsigned char)(0xC0 | encode));
6779 }
6780
6781 void Assembler::psllq(XMMRegister dst, XMMRegister shift) {
6782 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6783 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6784 attributes.set_rex_vex_w_reverted();
6785 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6786 emit_int8((unsigned char)0xF3);
6787 emit_int8((unsigned char)(0xC0 | encode));
6788 }
6789
6790 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6791 assert(UseAVX > 0, "requires some form of AVX");
6792 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6793 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
6794 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6795 emit_int8(0x71);
6796 emit_int8((unsigned char)(0xC0 | encode));
6797 emit_int8(shift & 0xFF);
6798 }
6799
6800 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6801 assert(UseAVX > 0, "requires some form of AVX");
6802 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6803 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6804 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
6805 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6806 emit_int8(0x72);
6807 emit_int8((unsigned char)(0xC0 | encode));
6808 emit_int8(shift & 0xFF);
6809 }
6810
6811 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6812 assert(UseAVX > 0, "requires some form of AVX");
6813 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6814 attributes.set_rex_vex_w_reverted();
6815 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
6816 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6817 emit_int8(0x73);
6818 emit_int8((unsigned char)(0xC0 | encode));
6819 emit_int8(shift & 0xFF);
6820 }
6821
6822 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6823 assert(UseAVX > 0, "requires some form of AVX");
6824 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6825 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6826 emit_int8((unsigned char)0xF1);
6827 emit_int8((unsigned char)(0xC0 | encode));
6828 }
6829
6830 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6831 assert(UseAVX > 0, "requires some form of AVX");
6832 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6833 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6834 emit_int8((unsigned char)0xF2);
6835 emit_int8((unsigned char)(0xC0 | encode));
6836 }
6837
6838 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6839 assert(UseAVX > 0, "requires some form of AVX");
6840 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6841 attributes.set_rex_vex_w_reverted();
6842 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6843 emit_int8((unsigned char)0xF3);
6844 emit_int8((unsigned char)(0xC0 | encode));
6845 }
6846
6847 // Shift packed integers logically right by specified number of bits.
6848 void Assembler::psrlw(XMMRegister dst, int shift) {
6849 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6850 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6851 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
6852 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6853 emit_int8(0x71);
6854 emit_int8((unsigned char)(0xC0 | encode));
6855 emit_int8(shift & 0xFF);
6856 }
6857
6858 void Assembler::psrld(XMMRegister dst, int shift) {
6859 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6860 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6861 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
6862 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6863 emit_int8(0x72);
6864 emit_int8((unsigned char)(0xC0 | encode));
6865 emit_int8(shift & 0xFF);
6866 }
6867
6868 void Assembler::psrlq(XMMRegister dst, int shift) {
6869 // Do not confuse it with psrldq SSE2 instruction which
6870 // shifts 128 bit value in xmm register by number of bytes.
6871 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6872 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6873 attributes.set_rex_vex_w_reverted();
6874 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
6875 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6876 emit_int8(0x73);
6877 emit_int8((unsigned char)(0xC0 | encode));
6878 emit_int8(shift & 0xFF);
6879 }
6880
6881 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) {
6882 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6883 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6884 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6885 emit_int8((unsigned char)0xD1);
6886 emit_int8((unsigned char)(0xC0 | encode));
6887 }
6888
6889 void Assembler::psrld(XMMRegister dst, XMMRegister shift) {
6890 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6891 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6892 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6893 emit_int8((unsigned char)0xD2);
6894 emit_int8((unsigned char)(0xC0 | encode));
6895 }
6896
6897 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) {
6898 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6899 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6900 attributes.set_rex_vex_w_reverted();
6901 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6902 emit_int8((unsigned char)0xD3);
6903 emit_int8((unsigned char)(0xC0 | encode));
6904 }
6905
6906 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6907 assert(UseAVX > 0, "requires some form of AVX");
6908 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6909 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
6910 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6911 emit_int8(0x71);
6912 emit_int8((unsigned char)(0xC0 | encode));
6913 emit_int8(shift & 0xFF);
6914 }
6915
6916 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6917 assert(UseAVX > 0, "requires some form of AVX");
6918 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6919 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
6920 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6921 emit_int8(0x72);
6922 emit_int8((unsigned char)(0xC0 | encode));
6923 emit_int8(shift & 0xFF);
6924 }
6925
6926 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6927 assert(UseAVX > 0, "requires some form of AVX");
6928 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6929 attributes.set_rex_vex_w_reverted();
6930 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
6931 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6932 emit_int8(0x73);
6933 emit_int8((unsigned char)(0xC0 | encode));
6934 emit_int8(shift & 0xFF);
6935 }
6936
6937 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6938 assert(UseAVX > 0, "requires some form of AVX");
6939 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6940 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6941 emit_int8((unsigned char)0xD1);
6942 emit_int8((unsigned char)(0xC0 | encode));
6943 }
6944
6945 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6946 assert(UseAVX > 0, "requires some form of AVX");
6947 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6948 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6949 emit_int8((unsigned char)0xD2);
6950 emit_int8((unsigned char)(0xC0 | encode));
6951 }
6952
6953 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6954 assert(UseAVX > 0, "requires some form of AVX");
6955 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6956 attributes.set_rex_vex_w_reverted();
6957 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6958 emit_int8((unsigned char)0xD3);
6959 emit_int8((unsigned char)(0xC0 | encode));
6960 }
6961
6962 void Assembler::evpsrlvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6963 assert(VM_Version::supports_avx512bw(), "");
6964 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6965 attributes.set_is_evex_instruction();
6966 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6967 emit_int8(0x10);
6968 emit_int8((unsigned char)(0xC0 | encode));
6969 }
6970
6971 void Assembler::evpsllvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6972 assert(VM_Version::supports_avx512bw(), "");
6973 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6974 attributes.set_is_evex_instruction();
6975 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6976 emit_int8(0x12);
6977 emit_int8((unsigned char)(0xC0 | encode));
6978 }
6979
6980 // Shift packed integers arithmetically right by specified number of bits.
6981 void Assembler::psraw(XMMRegister dst, int shift) {
6982 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6983 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6984 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
6985 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6986 emit_int8(0x71);
6987 emit_int8((unsigned char)(0xC0 | encode));
6988 emit_int8(shift & 0xFF);
6989 }
6990
6991 void Assembler::psrad(XMMRegister dst, int shift) {
6992 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6993 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6994 // XMM4 is for /4 encoding: 66 0F 72 /4 ib
6995 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6996 emit_int8(0x72);
6997 emit_int8((unsigned char)(0xC0 | encode));
6998 emit_int8(shift & 0xFF);
6999 }
7000
7001 void Assembler::psraw(XMMRegister dst, XMMRegister shift) {
7002 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7003 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7004 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7005 emit_int8((unsigned char)0xE1);
7006 emit_int8((unsigned char)(0xC0 | encode));
7007 }
7008
7009 void Assembler::psrad(XMMRegister dst, XMMRegister shift) {
7010 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7011 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
7012 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7013 emit_int8((unsigned char)0xE2);
7014 emit_int8((unsigned char)(0xC0 | encode));
7015 }
7016
7017 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
7018 assert(UseAVX > 0, "requires some form of AVX");
7019 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7020 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
7021 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7022 emit_int8(0x71);
7023 emit_int8((unsigned char)(0xC0 | encode));
7024 emit_int8(shift & 0xFF);
7025 }
7026
7027 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
7028 assert(UseAVX > 0, "requires some form of AVX");
7029 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
7030 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
7031 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7032 emit_int8(0x72);
7033 emit_int8((unsigned char)(0xC0 | encode));
7034 emit_int8(shift & 0xFF);
7035 }
7036
7037 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
7038 assert(UseAVX > 0, "requires some form of AVX");
7039 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7040 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7041 emit_int8((unsigned char)0xE1);
7042 emit_int8((unsigned char)(0xC0 | encode));
7043 }
7044
7045 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
7046 assert(UseAVX > 0, "requires some form of AVX");
7047 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
7048 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7049 emit_int8((unsigned char)0xE2);
7050 emit_int8((unsigned char)(0xC0 | encode));
7051 }
7052
7053 void Assembler::evpsraq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
7054 assert(UseAVX > 2, "requires AVX512");
7055 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
7056 attributes.set_is_evex_instruction();
7057 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7058 emit_int8((unsigned char)0x72);
7059 emit_int8((unsigned char)(0xC0 | encode));
7060 emit_int8(shift & 0xFF);
7061 }
7062
7063 void Assembler::evpsraq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
7064 assert(UseAVX > 2, "requires AVX512");
7065 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
7066 attributes.set_is_evex_instruction();
7067 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7068 emit_int8((unsigned char)0xE2);
7069 emit_int8((unsigned char)(0xC0 | encode));
7070 }
7071
7072 //Variable Shift packed integers logically left.
7073 void Assembler::vpsllvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
7074 assert(UseAVX > 1, "requires AVX2");
7075 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
7076 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7077 emit_int8(0x47);
7078 emit_int8((unsigned char)(0xC0 | encode));
7079 }
7080
7081 void Assembler::vpsllvq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
7082 assert(UseAVX > 1, "requires AVX2");
7083 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
7084 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7085 emit_int8(0x47);
7086 emit_int8((unsigned char)(0xC0 | encode));
7087 }
7088
7089 //Variable Shift packed integers logically right.
7090 void Assembler::vpsrlvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
7091 assert(UseAVX > 1, "requires AVX2");
7092 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
7093 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7094 emit_int8(0x45);
7095 emit_int8((unsigned char)(0xC0 | encode));
7096 }
7097
7098 void Assembler::vpsrlvq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
7099 assert(UseAVX > 1, "requires AVX2");
7100 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
7101 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7102 emit_int8(0x45);
7103 emit_int8((unsigned char)(0xC0 | encode));
7104 }
7105
7106 //Variable right Shift arithmetic packed integers .
7107 void Assembler::vpsravd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
7108 assert(UseAVX > 1, "requires AVX2");
7109 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
7110 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7111 emit_int8(0x46);
7112 emit_int8((unsigned char)(0xC0 | encode));
7113 }
7114
7115 void Assembler::evpsravq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
7116 assert(UseAVX > 2, "requires AVX512");
7117 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
7118 attributes.set_is_evex_instruction();
7119 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7120 emit_int8(0x46);
7121 emit_int8((unsigned char)(0xC0 | encode));
7122 }
7123
7124 // logical operations packed integers
7125 void Assembler::pand(XMMRegister dst, XMMRegister src) {
7126 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7127 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
7128 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7129 emit_int8((unsigned char)0xDB);
7130 emit_int8((unsigned char)(0xC0 | encode));
7131 }
7132
7133 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7134 assert(UseAVX > 0, "requires some form of AVX");
7135 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
7136 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7137 emit_int8((unsigned char)0xDB);
7138 emit_int8((unsigned char)(0xC0 | encode));
7139 }
7140
7141 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
7142 assert(UseAVX > 0, "requires some form of AVX");
7143 InstructionMark im(this);
7144 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
7145 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
7146 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7147 emit_int8((unsigned char)0xDB);
7148 emit_operand(dst, src);
7149 }
7150
7151 void Assembler::evpandd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
7152 assert(VM_Version::supports_evex(), "");
7153 // Encoding: EVEX.NDS.XXX.66.0F.W0 DB /r
7154 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
7155 attributes.set_is_evex_instruction();
7156 attributes.set_embedded_opmask_register_specifier(mask);
7157 if (merge) {
7158 attributes.reset_is_clear_context();
7159 }
7160 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7161 emit_int8((unsigned char)0xDB);
7162 emit_int8((unsigned char)(0xC0 | encode));
7163 }
7164
7165 void Assembler::vpandq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7166 assert(VM_Version::supports_evex(), "");
7167 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
7168 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7169 emit_int8((unsigned char)0xDB);
7170 emit_int8((unsigned char)(0xC0 | encode));
7171 }
7172
7173 void Assembler::pandn(XMMRegister dst, XMMRegister src) {
7174 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7175 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
7176 attributes.set_rex_vex_w_reverted();
7177 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7178 emit_int8((unsigned char)0xDF);
7179 emit_int8((unsigned char)(0xC0 | encode));
7180 }
7181
7182 void Assembler::por(XMMRegister dst, XMMRegister src) {
7183 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7184 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
7185 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7186 emit_int8((unsigned char)0xEB);
7187 emit_int8((unsigned char)(0xC0 | encode));
7188 }
7189
7190 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7191 assert(UseAVX > 0, "requires some form of AVX");
7192 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
7193 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7194 emit_int8((unsigned char)0xEB);
7195 emit_int8((unsigned char)(0xC0 | encode));
7196 }
7197
7198 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
7199 assert(UseAVX > 0, "requires some form of AVX");
7200 InstructionMark im(this);
7201 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
7202 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
7203 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7204 emit_int8((unsigned char)0xEB);
7205 emit_operand(dst, src);
7206 }
7207
7208 void Assembler::vporq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7209 assert(VM_Version::supports_evex(), "");
7210 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
7211 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7212 emit_int8((unsigned char)0xEB);
7213 emit_int8((unsigned char)(0xC0 | encode));
7214 }
7215
7216
7217 void Assembler::evpord(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
7218 assert(VM_Version::supports_evex(), "");
7219 // Encoding: EVEX.NDS.XXX.66.0F.W0 EB /r
7220 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
7221 attributes.set_is_evex_instruction();
7222 attributes.set_embedded_opmask_register_specifier(mask);
7223 if (merge) {
7224 attributes.reset_is_clear_context();
7225 }
7226 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7227 emit_int8((unsigned char)0xEB);
7228 emit_int8((unsigned char)(0xC0 | encode));
7229 }
7230
7231 void Assembler::evpord(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
7232 assert(VM_Version::supports_evex(), "");
7233 // Encoding: EVEX.NDS.XXX.66.0F.W0 EB /r
7234 InstructionMark im(this);
7235 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
7236 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_NObit);
7237 attributes.set_is_evex_instruction();
7238 attributes.set_embedded_opmask_register_specifier(mask);
7239 if (merge) {
7240 attributes.reset_is_clear_context();
7241 }
7242 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7243 emit_int8((unsigned char)0xEB);
7244 emit_operand(dst, src);
7245 }
7246
7247 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
7248 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7249 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
7250 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7251 emit_int8((unsigned char)0xEF);
7252 emit_int8((unsigned char)(0xC0 | encode));
7253 }
7254
7255 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7256 assert(UseAVX > 0, "requires some form of AVX");
7257 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
7258 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7259 emit_int8((unsigned char)0xEF);
7260 emit_int8((unsigned char)(0xC0 | encode));
7261 }
7262
7263 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
7264 assert(UseAVX > 0, "requires some form of AVX");
7265 InstructionMark im(this);
7266 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
7267 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
7268 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7269 emit_int8((unsigned char)0xEF);
7270 emit_operand(dst, src);
7271 }
7272
7273 void Assembler::vpxorq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7274 assert(UseAVX > 2, "requires some form of EVEX");
7275 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
7276 attributes.set_rex_vex_w_reverted();
7277 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7278 emit_int8((unsigned char)0xEF);
7279 emit_int8((unsigned char)(0xC0 | encode));
7280 }
7281
7282 void Assembler::evpxord(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
7283 assert(VM_Version::supports_evex(), "");
7284 // Encoding: EVEX.NDS.XXX.66.0F.W0 EF /r
7285 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
7286 attributes.set_is_evex_instruction();
7287 attributes.set_embedded_opmask_register_specifier(mask);
7288 if (merge) {
7289 attributes.reset_is_clear_context();
7290 }
7291 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7292 emit_int8((unsigned char)0xEF);
7293 emit_int8((unsigned char)(0xC0 | encode));
7294 }
7295
7296 void Assembler::evpxorq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7297 assert(VM_Version::supports_evex(), "requires EVEX support");
7298 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7299 attributes.set_is_evex_instruction();
7300 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7301 emit_int8((unsigned char)0xEF);
7302 emit_int8((unsigned char)(0xC0 | encode));
7303 }
7304
7305 void Assembler::evpxorq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
7306 assert(VM_Version::supports_evex(), "requires EVEX support");
7307 assert(dst != xnoreg, "sanity");
7308 InstructionMark im(this);
7309 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7310 attributes.set_is_evex_instruction();
7311 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
7312 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7313 emit_int8((unsigned char)0xEF);
7314 emit_operand(dst, src);
7315 }
7316
7317 // vinserti forms
7318
7319 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
7320 assert(VM_Version::supports_avx2(), "");
7321 assert(imm8 <= 0x01, "imm8: %u", imm8);
7322 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
7323 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
7324 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7325 emit_int8(0x38);
7326 emit_int8((unsigned char)(0xC0 | encode));
7327 // 0x00 - insert into lower 128 bits
7328 // 0x01 - insert into upper 128 bits
7329 emit_int8(imm8 & 0x01);
7330 }
7331
7332 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
7333 assert(VM_Version::supports_avx2(), "");
7334 assert(dst != xnoreg, "sanity");
7335 assert(imm8 <= 0x01, "imm8: %u", imm8);
7336 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
7337 InstructionMark im(this);
7338 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
7339 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
7340 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7341 emit_int8(0x38);
7342 emit_operand(dst, src);
7343 // 0x00 - insert into lower 128 bits
7344 // 0x01 - insert into upper 128 bits
7345 emit_int8(imm8 & 0x01);
7346 }
7347
7348 void Assembler::vinserti32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
7349 assert(VM_Version::supports_evex(), "");
7350 assert(imm8 <= 0x03, "imm8: %u", imm8);
7351 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
7352 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7353 emit_int8(0x38);
7354 emit_int8((unsigned char)(0xC0 | encode));
7355 // 0x00 - insert into q0 128 bits (0..127)
7356 // 0x01 - insert into q1 128 bits (128..255)
7357 // 0x02 - insert into q2 128 bits (256..383)
7358 // 0x03 - insert into q3 128 bits (384..511)
7359 emit_int8(imm8 & 0x03);
7360 }
7361
7362 void Assembler::vinserti32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
7363 assert(VM_Version::supports_avx(), "");
7364 assert(dst != xnoreg, "sanity");
7365 assert(imm8 <= 0x03, "imm8: %u", imm8);
7366 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
7367 InstructionMark im(this);
7368 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
7369 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
7370 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7371 emit_int8(0x18);
7372 emit_operand(dst, src);
7373 // 0x00 - insert into q0 128 bits (0..127)
7374 // 0x01 - insert into q1 128 bits (128..255)
7375 // 0x02 - insert into q2 128 bits (256..383)
7376 // 0x03 - insert into q3 128 bits (384..511)
7377 emit_int8(imm8 & 0x03);
7378 }
7379
7380 void Assembler::vinserti64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
7381 assert(VM_Version::supports_evex(), "");
7382 assert(imm8 <= 0x01, "imm8: %u", imm8);
7383 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
7384 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7385 emit_int8(0x3A);
7386 emit_int8((unsigned char)(0xC0 | encode));
7387 // 0x00 - insert into lower 256 bits
7388 // 0x01 - insert into upper 256 bits
7389 emit_int8(imm8 & 0x01);
7390 }
7391
7392
7393 // vinsertf forms
7394
7395 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
7396 assert(VM_Version::supports_avx(), "");
7397 assert(imm8 <= 0x01, "imm8: %u", imm8);
7398 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
7399 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
7400 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7401 emit_int8(0x18);
7402 emit_int8((unsigned char)(0xC0 | encode));
7403 // 0x00 - insert into lower 128 bits
7404 // 0x01 - insert into upper 128 bits
7405 emit_int8(imm8 & 0x01);
7406 }
7407
7408 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
7409 assert(VM_Version::supports_avx(), "");
7410 assert(dst != xnoreg, "sanity");
7411 assert(imm8 <= 0x01, "imm8: %u", imm8);
7412 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
7413 InstructionMark im(this);
7414 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
7415 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
7416 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7417 emit_int8(0x18);
7418 emit_operand(dst, src);
7419 // 0x00 - insert into lower 128 bits
7420 // 0x01 - insert into upper 128 bits
7421 emit_int8(imm8 & 0x01);
7422 }
7423
7424 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
7425 assert(VM_Version::supports_evex(), "");
7426 assert(imm8 <= 0x03, "imm8: %u", imm8);
7427 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
7428 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7429 emit_int8(0x18);
7430 emit_int8((unsigned char)(0xC0 | encode));
7431 // 0x00 - insert into q0 128 bits (0..127)
7432 // 0x01 - insert into q1 128 bits (128..255)
7433 // 0x02 - insert into q2 128 bits (256..383)
7434 // 0x03 - insert into q3 128 bits (384..511)
7435 emit_int8(imm8 & 0x03);
7436 }
7437
7438 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
7439 assert(VM_Version::supports_avx(), "");
7440 assert(dst != xnoreg, "sanity");
7441 assert(imm8 <= 0x03, "imm8: %u", imm8);
7442 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
7443 InstructionMark im(this);
7444 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
7445 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
7446 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7447 emit_int8(0x18);
7448 emit_operand(dst, src);
7449 // 0x00 - insert into q0 128 bits (0..127)
7450 // 0x01 - insert into q1 128 bits (128..255)
7451 // 0x02 - insert into q2 128 bits (256..383)
7452 // 0x03 - insert into q3 128 bits (384..511)
7453 emit_int8(imm8 & 0x03);
7454 }
7455
7456 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
7457 assert(VM_Version::supports_evex(), "");
7458 assert(imm8 <= 0x01, "imm8: %u", imm8);
7459 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
7460 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7461 emit_int8(0x1A);
7462 emit_int8((unsigned char)(0xC0 | encode));
7463 // 0x00 - insert into lower 256 bits
7464 // 0x01 - insert into upper 256 bits
7465 emit_int8(imm8 & 0x01);
7466 }
7467
7468 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
7469 assert(VM_Version::supports_evex(), "");
7470 assert(dst != xnoreg, "sanity");
7471 assert(imm8 <= 0x01, "imm8: %u", imm8);
7472 InstructionMark im(this);
7473 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
7474 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_64bit);
7475 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7476 emit_int8(0x1A);
7477 emit_operand(dst, src);
7478 // 0x00 - insert into lower 256 bits
7479 // 0x01 - insert into upper 256 bits
7480 emit_int8(imm8 & 0x01);
7481 }
7482
7483
7484 // vextracti forms
7485
7486 void Assembler::vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
7487 assert(VM_Version::supports_avx(), "");
7488 assert(imm8 <= 0x01, "imm8: %u", imm8);
7489 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
7490 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
7491 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7492 emit_int8(0x39);
7493 emit_int8((unsigned char)(0xC0 | encode));
7494 // 0x00 - extract from lower 128 bits
7495 // 0x01 - extract from upper 128 bits
7496 emit_int8(imm8 & 0x01);
7497 }
7498
7499 void Assembler::vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
7500 assert(VM_Version::supports_avx2(), "");
7501 assert(src != xnoreg, "sanity");
7502 assert(imm8 <= 0x01, "imm8: %u", imm8);
7503 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
7504 InstructionMark im(this);
7505 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
7506 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
7507 attributes.reset_is_clear_context();
7508 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7509 emit_int8(0x39);
7510 emit_operand(src, dst);
7511 // 0x00 - extract from lower 128 bits
7512 // 0x01 - extract from upper 128 bits
7513 emit_int8(imm8 & 0x01);
7514 }
7515
7516 void Assembler::vextracti32x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
7517 assert(VM_Version::supports_avx(), "");
7518 assert(imm8 <= 0x03, "imm8: %u", imm8);
7519 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
7520 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
7521 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7522 emit_int8(0x39);
7523 emit_int8((unsigned char)(0xC0 | encode));
7524 // 0x00 - extract from bits 127:0
7525 // 0x01 - extract from bits 255:128
7526 // 0x02 - extract from bits 383:256
7527 // 0x03 - extract from bits 511:384
7528 emit_int8(imm8 & 0x03);
7529 }
7530
7531 void Assembler::vextracti32x4(Address dst, XMMRegister src, uint8_t imm8) {
7532 assert(VM_Version::supports_evex(), "");
7533 assert(src != xnoreg, "sanity");
7534 assert(imm8 <= 0x03, "imm8: %u", imm8);
7535 InstructionMark im(this);
7536 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
7537 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
7538 attributes.reset_is_clear_context();
7539 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7540 emit_int8(0x39);
7541 emit_operand(src, dst);
7542 // 0x00 - extract from bits 127:0
7543 // 0x01 - extract from bits 255:128
7544 // 0x02 - extract from bits 383:256
7545 // 0x03 - extract from bits 511:384
7546 emit_int8(imm8 & 0x03);
7547 }
7548
7549 void Assembler::vextracti64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) {
7550 assert(VM_Version::supports_avx512dq(), "");
7551 assert(imm8 <= 0x03, "imm8: %u", imm8);
7552 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
7553 attributes.set_is_evex_instruction();
7554 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7555 emit_int8(0x39);
7556 emit_int8((unsigned char)(0xC0 | encode));
7557 // 0x00 - extract from bits 127:0
7558 // 0x01 - extract from bits 255:128
7559 // 0x02 - extract from bits 383:256
7560 // 0x03 - extract from bits 511:384
7561 emit_int8(imm8 & 0x03);
7562 }
7563
7564 void Assembler::vextracti64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
7565 assert(VM_Version::supports_evex(), "");
7566 assert(imm8 <= 0x01, "imm8: %u", imm8);
7567 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
7568 attributes.set_is_evex_instruction();
7569 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7570 emit_int8(0x3B);
7571 emit_int8((unsigned char)(0xC0 | encode));
7572 // 0x00 - extract from lower 256 bits
7573 // 0x01 - extract from upper 256 bits
7574 emit_int8(imm8 & 0x01);
7575 }
7576
7577
7578 // vextractf forms
7579
7580 void Assembler::vextractf128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
7581 assert(VM_Version::supports_avx(), "");
7582 assert(imm8 <= 0x01, "imm8: %u", imm8);
7583 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
7584 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
7585 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7586 emit_int8(0x19);
7587 emit_int8((unsigned char)(0xC0 | encode));
7588 // 0x00 - extract from lower 128 bits
7589 // 0x01 - extract from upper 128 bits
7590 emit_int8(imm8 & 0x01);
7591 }
7592
7593 void Assembler::vextractf128(Address dst, XMMRegister src, uint8_t imm8) {
7594 assert(VM_Version::supports_avx(), "");
7595 assert(src != xnoreg, "sanity");
7596 assert(imm8 <= 0x01, "imm8: %u", imm8);
7597 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
7598 InstructionMark im(this);
7599 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
7600 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
7601 attributes.reset_is_clear_context();
7602 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7603 emit_int8(0x19);
7604 emit_operand(src, dst);
7605 // 0x00 - extract from lower 128 bits
7606 // 0x01 - extract from upper 128 bits
7607 emit_int8(imm8 & 0x01);
7608 }
7609
7610 void Assembler::vextractf32x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
7611 assert(VM_Version::supports_avx(), "");
7612 assert(imm8 <= 0x03, "imm8: %u", imm8);
7613 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
7614 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
7615 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7616 emit_int8(0x19);
7617 emit_int8((unsigned char)(0xC0 | encode));
7618 // 0x00 - extract from bits 127:0
7619 // 0x01 - extract from bits 255:128
7620 // 0x02 - extract from bits 383:256
7621 // 0x03 - extract from bits 511:384
7622 emit_int8(imm8 & 0x03);
7623 }
7624
7625 void Assembler::vextractf32x4(Address dst, XMMRegister src, uint8_t imm8) {
7626 assert(VM_Version::supports_evex(), "");
7627 assert(src != xnoreg, "sanity");
7628 assert(imm8 <= 0x03, "imm8: %u", imm8);
7629 InstructionMark im(this);
7630 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
7631 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
7632 attributes.reset_is_clear_context();
7633 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7634 emit_int8(0x19);
7635 emit_operand(src, dst);
7636 // 0x00 - extract from bits 127:0
7637 // 0x01 - extract from bits 255:128
7638 // 0x02 - extract from bits 383:256
7639 // 0x03 - extract from bits 511:384
7640 emit_int8(imm8 & 0x03);
7641 }
7642
7643 void Assembler::vextractf64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) {
7644 assert(VM_Version::supports_avx512dq(), "");
7645 assert(imm8 <= 0x03, "imm8: %u", imm8);
7646 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
7647 attributes.set_is_evex_instruction();
7648 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7649 emit_int8(0x19);
7650 emit_int8((unsigned char)(0xC0 | encode));
7651 // 0x00 - extract from bits 127:0
7652 // 0x01 - extract from bits 255:128
7653 // 0x02 - extract from bits 383:256
7654 // 0x03 - extract from bits 511:384
7655 emit_int8(imm8 & 0x03);
7656 }
7657
7658 void Assembler::vextractf64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
7659 assert(VM_Version::supports_evex(), "");
7660 assert(imm8 <= 0x01, "imm8: %u", imm8);
7661 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
7662 attributes.set_is_evex_instruction();
7663 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7664 emit_int8(0x1B);
7665 emit_int8((unsigned char)(0xC0 | encode));
7666 // 0x00 - extract from lower 256 bits
7667 // 0x01 - extract from upper 256 bits
7668 emit_int8(imm8 & 0x01);
7669 }
7670
7671 void Assembler::vextractf64x4(Address dst, XMMRegister src, uint8_t imm8) {
7672 assert(VM_Version::supports_evex(), "");
7673 assert(src != xnoreg, "sanity");
7674 assert(imm8 <= 0x01, "imm8: %u", imm8);
7675 InstructionMark im(this);
7676 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
7677 attributes.set_address_attributes(/* tuple_type */ EVEX_T4,/* input_size_in_bits */ EVEX_64bit);
7678 attributes.reset_is_clear_context();
7679 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7680 emit_int8(0x1B);
7681 emit_operand(src, dst);
7682 // 0x00 - extract from lower 256 bits
7683 // 0x01 - extract from upper 256 bits
7684 emit_int8(imm8 & 0x01);
7685 }
7686
7687
7688 // legacy word/dword replicate
7689 void Assembler::vpbroadcastw(XMMRegister dst, XMMRegister src) {
7690 assert(VM_Version::supports_avx2(), "");
7691 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7692 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7693 emit_int8(0x79);
7694 emit_int8((unsigned char)(0xC0 | encode));
7695 }
7696
7697 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src) {
7698 assert(VM_Version::supports_avx2(), "");
7699 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
7700 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7701 emit_int8(0x58);
7702 emit_int8((unsigned char)(0xC0 | encode));
7703 }
7704
7705
7706 // xmm/mem sourced byte/word/dword/qword replicate
7707
7708 // duplicate 1-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
7709 void Assembler::evpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len) {
7710 assert(VM_Version::supports_evex(), "");
7711 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7712 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7713 emit_int8(0x78);
7714 emit_int8((unsigned char)(0xC0 | encode));
7715 }
7716
7717 void Assembler::evpbroadcastb(XMMRegister dst, Address src, int vector_len) {
7718 assert(VM_Version::supports_evex(), "");
7719 assert(dst != xnoreg, "sanity");
7720 InstructionMark im(this);
7721 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7722 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
7723 // swap src<->dst for encoding
7724 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7725 emit_int8(0x78);
7726 emit_operand(dst, src);
7727 }
7728
7729 // duplicate 2-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
7730 void Assembler::evpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len) {
7731 assert(VM_Version::supports_evex(), "");
7732 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7733 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7734 emit_int8(0x79);
7735 emit_int8((unsigned char)(0xC0 | encode));
7736 }
7737
7738 void Assembler::evpbroadcastw(XMMRegister dst, Address src, int vector_len) {
7739 assert(VM_Version::supports_evex(), "");
7740 assert(dst != xnoreg, "sanity");
7741 InstructionMark im(this);
7742 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7743 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
7744 // swap src<->dst for encoding
7745 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7746 emit_int8(0x79);
7747 emit_operand(dst, src);
7748 }
7749
7750 // duplicate 4-byte integer data from src into programmed locations in dest : requires AVX512VL
7751 void Assembler::evpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len) {
7752 assert(VM_Version::supports_evex(), "");
7753 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
7754 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7755 emit_int8(0x58);
7756 emit_int8((unsigned char)(0xC0 | encode));
7757 }
7758
7759 void Assembler::evpbroadcastd(XMMRegister dst, Address src, int vector_len) {
7760 assert(VM_Version::supports_evex(), "");
7761 assert(dst != xnoreg, "sanity");
7762 InstructionMark im(this);
7763 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
7764 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
7765 // swap src<->dst for encoding
7766 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7767 emit_int8(0x58);
7768 emit_operand(dst, src);
7769 }
7770
7771 // duplicate 8-byte integer data from src into programmed locations in dest : requires AVX512VL
7772 void Assembler::evpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len) {
7773 assert(VM_Version::supports_evex(), "");
7774 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
7775 attributes.set_rex_vex_w_reverted();
7776 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7777 emit_int8(0x59);
7778 emit_int8((unsigned char)(0xC0 | encode));
7779 }
7780
7781 void Assembler::evpbroadcastq(XMMRegister dst, Address src, int vector_len) {
7782 assert(VM_Version::supports_evex(), "");
7783 assert(dst != xnoreg, "sanity");
7784 InstructionMark im(this);
7785 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
7786 attributes.set_rex_vex_w_reverted();
7787 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
7788 // swap src<->dst for encoding
7789 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7790 emit_int8(0x59);
7791 emit_operand(dst, src);
7792 }
7793 void Assembler::evbroadcasti64x2(XMMRegister dst, XMMRegister src, int vector_len) {
7794 assert(vector_len != Assembler::AVX_128bit, "");
7795 assert(VM_Version::supports_avx512dq(), "");
7796 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
7797 attributes.set_rex_vex_w_reverted();
7798 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7799 emit_int8(0x5A);
7800 emit_int8((unsigned char)(0xC0 | encode));
7801 }
7802
7803 void Assembler::evbroadcasti64x2(XMMRegister dst, Address src, int vector_len) {
7804 assert(vector_len != Assembler::AVX_128bit, "");
7805 assert(VM_Version::supports_avx512dq(), "");
7806 assert(dst != xnoreg, "sanity");
7807 InstructionMark im(this);
7808 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
7809 attributes.set_rex_vex_w_reverted();
7810 attributes.set_address_attributes(/* tuple_type */ EVEX_T2, /* input_size_in_bits */ EVEX_64bit);
7811 // swap src<->dst for encoding
7812 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7813 emit_int8(0x5A);
7814 emit_operand(dst, src);
7815 }
7816
7817 // scalar single/double precision replicate
7818
7819 // duplicate single precision data from src into programmed locations in dest : requires AVX512VL
7820 void Assembler::evpbroadcastss(XMMRegister dst, XMMRegister src, int vector_len) {
7821 assert(VM_Version::supports_evex(), "");
7822 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
7823 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7824 emit_int8(0x18);
7825 emit_int8((unsigned char)(0xC0 | encode));
7826 }
7827
7828 void Assembler::evpbroadcastss(XMMRegister dst, Address src, int vector_len) {
7829 assert(VM_Version::supports_evex(), "");
7830 assert(dst != xnoreg, "sanity");
7831 InstructionMark im(this);
7832 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
7833 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
7834 // swap src<->dst for encoding
7835 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7836 emit_int8(0x18);
7837 emit_operand(dst, src);
7838 }
7839
7840 // duplicate double precision data from src into programmed locations in dest : requires AVX512VL
7841 void Assembler::evpbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len) {
7842 assert(VM_Version::supports_evex(), "");
7843 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
7844 attributes.set_rex_vex_w_reverted();
7845 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7846 emit_int8(0x19);
7847 emit_int8((unsigned char)(0xC0 | encode));
7848 }
7849
7850 void Assembler::evpbroadcastsd(XMMRegister dst, Address src, int vector_len) {
7851 assert(VM_Version::supports_evex(), "");
7852 assert(dst != xnoreg, "sanity");
7853 InstructionMark im(this);
7854 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
7855 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
7856 attributes.set_rex_vex_w_reverted();
7857 // swap src<->dst for encoding
7858 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7859 emit_int8(0x19);
7860 emit_operand(dst, src);
7861 }
7862
7863
7864 // gpr source broadcast forms
7865
7866 // duplicate 1-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
7867 void Assembler::evpbroadcastb(XMMRegister dst, Register src, int vector_len) {
7868 assert(VM_Version::supports_evex(), "");
7869 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7870 attributes.set_is_evex_instruction();
7871 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7872 emit_int8(0x7A);
7873 emit_int8((unsigned char)(0xC0 | encode));
7874 }
7875
7876 // duplicate 2-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
7877 void Assembler::evpbroadcastw(XMMRegister dst, Register src, int vector_len) {
7878 assert(VM_Version::supports_evex(), "");
7879 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7880 attributes.set_is_evex_instruction();
7881 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7882 emit_int8(0x7B);
7883 emit_int8((unsigned char)(0xC0 | encode));
7884 }
7885
7886 // duplicate 4-byte integer data from src into programmed locations in dest : requires AVX512VL
7887 void Assembler::evpbroadcastd(XMMRegister dst, Register src, int vector_len) {
7888 assert(VM_Version::supports_evex(), "");
7889 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
7890 attributes.set_is_evex_instruction();
7891 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7892 emit_int8(0x7C);
7893 emit_int8((unsigned char)(0xC0 | encode));
7894 }
7895
7896 // duplicate 8-byte integer data from src into programmed locations in dest : requires AVX512VL
7897 void Assembler::evpbroadcastq(XMMRegister dst, Register src, int vector_len) {
7898 assert(VM_Version::supports_evex(), "");
7899 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
7900 attributes.set_is_evex_instruction();
7901 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7902 emit_int8(0x7C);
7903 emit_int8((unsigned char)(0xC0 | encode));
7904 }
7905
7906 void Assembler::evpgatherdd(XMMRegister dst, KRegister mask, Address src, int vector_len) {
7907 assert(VM_Version::supports_evex(), "");
7908 assert(dst != xnoreg, "sanity");
7909 InstructionMark im(this);
7910 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
7911 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
7912 attributes.reset_is_clear_context();
7913 attributes.set_embedded_opmask_register_specifier(mask);
7914 attributes.set_is_evex_instruction();
7915 // swap src<->dst for encoding
7916 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7917 emit_int8((unsigned char)0x90);
7918 emit_operand(dst, src);
7919 }
7920
7921 // Carry-Less Multiplication Quadword
7922 void Assembler::pclmulqdq(XMMRegister dst, XMMRegister src, int mask) {
7923 assert(VM_Version::supports_clmul(), "");
7924 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7925 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7926 emit_int8(0x44);
7927 emit_int8((unsigned char)(0xC0 | encode));
7928 emit_int8((unsigned char)mask);
7929 }
7930
7931 // Carry-Less Multiplication Quadword
7932 void Assembler::vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask) {
7933 assert(VM_Version::supports_avx() && VM_Version::supports_clmul(), "");
7934 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7935 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7936 emit_int8(0x44);
7937 emit_int8((unsigned char)(0xC0 | encode));
7938 emit_int8((unsigned char)mask);
7939 }
7940
7941 void Assembler::evpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask, int vector_len) {
7942 assert(VM_Version::supports_vpclmulqdq(), "Requires vector carryless multiplication support");
7943 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7944 attributes.set_is_evex_instruction();
7945 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7946 emit_int8(0x44);
7947 emit_int8((unsigned char)(0xC0 | encode));
7948 emit_int8((unsigned char)mask);
7949 }
7950
7951 void Assembler::vzeroupper() {
7952 if (VM_Version::supports_vzeroupper()) {
7953 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
7954 (void)vex_prefix_and_encode(0, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7955 emit_int8(0x77);
7956 }
7957 }
7958
7959 #ifndef _LP64
7960 // 32bit only pieces of the assembler
7961
7962 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
7963 // NO PREFIX AS NEVER 64BIT
7964 InstructionMark im(this);
7965 emit_int8((unsigned char)0x81);
7966 emit_int8((unsigned char)(0xF8 | src1->encoding()));
7967 emit_data(imm32, rspec, 0);
7968 }
7969
7970 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
7971 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
7972 InstructionMark im(this);
7973 emit_int8((unsigned char)0x81);
7974 emit_operand(rdi, src1);
7975 emit_data(imm32, rspec, 0);
7976 }
7977
7978 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax,
7979 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded
7980 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise.
7981 void Assembler::cmpxchg8(Address adr) {
7982 InstructionMark im(this);
7983 emit_int8(0x0F);
7984 emit_int8((unsigned char)0xC7);
7985 emit_operand(rcx, adr);
7986 }
7987
7988 void Assembler::decl(Register dst) {
7989 // Don't use it directly. Use MacroAssembler::decrementl() instead.
7990 emit_int8(0x48 | dst->encoding());
7991 }
7992
7993 #endif // _LP64
7994
7995 // 64bit typically doesn't use the x87 but needs to for the trig funcs
7996
7997 void Assembler::fabs() {
7998 emit_int8((unsigned char)0xD9);
7999 emit_int8((unsigned char)0xE1);
8000 }
8001
8002 void Assembler::fadd(int i) {
8003 emit_farith(0xD8, 0xC0, i);
8004 }
8005
8006 void Assembler::fadd_d(Address src) {
8007 InstructionMark im(this);
8008 emit_int8((unsigned char)0xDC);
8009 emit_operand32(rax, src);
8010 }
8011
8012 void Assembler::fadd_s(Address src) {
8013 InstructionMark im(this);
8014 emit_int8((unsigned char)0xD8);
8015 emit_operand32(rax, src);
8016 }
8017
8018 void Assembler::fadda(int i) {
8019 emit_farith(0xDC, 0xC0, i);
8020 }
8021
8022 void Assembler::faddp(int i) {
8023 emit_farith(0xDE, 0xC0, i);
8024 }
8025
8026 void Assembler::fchs() {
8027 emit_int8((unsigned char)0xD9);
8028 emit_int8((unsigned char)0xE0);
8029 }
8030
8031 void Assembler::fcom(int i) {
8032 emit_farith(0xD8, 0xD0, i);
8033 }
8034
8035 void Assembler::fcomp(int i) {
8036 emit_farith(0xD8, 0xD8, i);
8037 }
8038
8039 void Assembler::fcomp_d(Address src) {
8040 InstructionMark im(this);
8041 emit_int8((unsigned char)0xDC);
8042 emit_operand32(rbx, src);
8043 }
8044
8045 void Assembler::fcomp_s(Address src) {
8046 InstructionMark im(this);
8047 emit_int8((unsigned char)0xD8);
8048 emit_operand32(rbx, src);
8049 }
8050
8051 void Assembler::fcompp() {
8052 emit_int8((unsigned char)0xDE);
8053 emit_int8((unsigned char)0xD9);
8054 }
8055
8056 void Assembler::fcos() {
8057 emit_int8((unsigned char)0xD9);
8058 emit_int8((unsigned char)0xFF);
8059 }
8060
8061 void Assembler::fdecstp() {
8062 emit_int8((unsigned char)0xD9);
8063 emit_int8((unsigned char)0xF6);
8064 }
8065
8066 void Assembler::fdiv(int i) {
8067 emit_farith(0xD8, 0xF0, i);
8068 }
8069
8070 void Assembler::fdiv_d(Address src) {
8071 InstructionMark im(this);
8072 emit_int8((unsigned char)0xDC);
8073 emit_operand32(rsi, src);
8074 }
8075
8076 void Assembler::fdiv_s(Address src) {
8077 InstructionMark im(this);
8078 emit_int8((unsigned char)0xD8);
8079 emit_operand32(rsi, src);
8080 }
8081
8082 void Assembler::fdiva(int i) {
8083 emit_farith(0xDC, 0xF8, i);
8084 }
8085
8086 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994)
8087 // is erroneous for some of the floating-point instructions below.
8088
8089 void Assembler::fdivp(int i) {
8090 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong)
8091 }
8092
8093 void Assembler::fdivr(int i) {
8094 emit_farith(0xD8, 0xF8, i);
8095 }
8096
8097 void Assembler::fdivr_d(Address src) {
8098 InstructionMark im(this);
8099 emit_int8((unsigned char)0xDC);
8100 emit_operand32(rdi, src);
8101 }
8102
8103 void Assembler::fdivr_s(Address src) {
8104 InstructionMark im(this);
8105 emit_int8((unsigned char)0xD8);
8106 emit_operand32(rdi, src);
8107 }
8108
8109 void Assembler::fdivra(int i) {
8110 emit_farith(0xDC, 0xF0, i);
8111 }
8112
8113 void Assembler::fdivrp(int i) {
8114 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong)
8115 }
8116
8117 void Assembler::ffree(int i) {
8118 emit_farith(0xDD, 0xC0, i);
8119 }
8120
8121 void Assembler::fild_d(Address adr) {
8122 InstructionMark im(this);
8123 emit_int8((unsigned char)0xDF);
8124 emit_operand32(rbp, adr);
8125 }
8126
8127 void Assembler::fild_s(Address adr) {
8128 InstructionMark im(this);
8129 emit_int8((unsigned char)0xDB);
8130 emit_operand32(rax, adr);
8131 }
8132
8133 void Assembler::fincstp() {
8134 emit_int8((unsigned char)0xD9);
8135 emit_int8((unsigned char)0xF7);
8136 }
8137
8138 void Assembler::finit() {
8139 emit_int8((unsigned char)0x9B);
8140 emit_int8((unsigned char)0xDB);
8141 emit_int8((unsigned char)0xE3);
8142 }
8143
8144 void Assembler::fist_s(Address adr) {
8145 InstructionMark im(this);
8146 emit_int8((unsigned char)0xDB);
8147 emit_operand32(rdx, adr);
8148 }
8149
8150 void Assembler::fistp_d(Address adr) {
8151 InstructionMark im(this);
8152 emit_int8((unsigned char)0xDF);
8153 emit_operand32(rdi, adr);
8154 }
8155
8156 void Assembler::fistp_s(Address adr) {
8157 InstructionMark im(this);
8158 emit_int8((unsigned char)0xDB);
8159 emit_operand32(rbx, adr);
8160 }
8161
8162 void Assembler::fld1() {
8163 emit_int8((unsigned char)0xD9);
8164 emit_int8((unsigned char)0xE8);
8165 }
8166
8167 void Assembler::fld_d(Address adr) {
8168 InstructionMark im(this);
8169 emit_int8((unsigned char)0xDD);
8170 emit_operand32(rax, adr);
8171 }
8172
8173 void Assembler::fld_s(Address adr) {
8174 InstructionMark im(this);
8175 emit_int8((unsigned char)0xD9);
8176 emit_operand32(rax, adr);
8177 }
8178
8179
8180 void Assembler::fld_s(int index) {
8181 emit_farith(0xD9, 0xC0, index);
8182 }
8183
8184 void Assembler::fld_x(Address adr) {
8185 InstructionMark im(this);
8186 emit_int8((unsigned char)0xDB);
8187 emit_operand32(rbp, adr);
8188 }
8189
8190 void Assembler::fldcw(Address src) {
8191 InstructionMark im(this);
8192 emit_int8((unsigned char)0xD9);
8193 emit_operand32(rbp, src);
8194 }
8195
8196 void Assembler::fldenv(Address src) {
8197 InstructionMark im(this);
8198 emit_int8((unsigned char)0xD9);
8199 emit_operand32(rsp, src);
8200 }
8201
8202 void Assembler::fldlg2() {
8203 emit_int8((unsigned char)0xD9);
8204 emit_int8((unsigned char)0xEC);
8205 }
8206
8207 void Assembler::fldln2() {
8208 emit_int8((unsigned char)0xD9);
8209 emit_int8((unsigned char)0xED);
8210 }
8211
8212 void Assembler::fldz() {
8213 emit_int8((unsigned char)0xD9);
8214 emit_int8((unsigned char)0xEE);
8215 }
8216
8217 void Assembler::flog() {
8218 fldln2();
8219 fxch();
8220 fyl2x();
8221 }
8222
8223 void Assembler::flog10() {
8224 fldlg2();
8225 fxch();
8226 fyl2x();
8227 }
8228
8229 void Assembler::fmul(int i) {
8230 emit_farith(0xD8, 0xC8, i);
8231 }
8232
8233 void Assembler::fmul_d(Address src) {
8234 InstructionMark im(this);
8235 emit_int8((unsigned char)0xDC);
8236 emit_operand32(rcx, src);
8237 }
8238
8239 void Assembler::fmul_s(Address src) {
8240 InstructionMark im(this);
8241 emit_int8((unsigned char)0xD8);
8242 emit_operand32(rcx, src);
8243 }
8244
8245 void Assembler::fmula(int i) {
8246 emit_farith(0xDC, 0xC8, i);
8247 }
8248
8249 void Assembler::fmulp(int i) {
8250 emit_farith(0xDE, 0xC8, i);
8251 }
8252
8253 void Assembler::fnsave(Address dst) {
8254 InstructionMark im(this);
8255 emit_int8((unsigned char)0xDD);
8256 emit_operand32(rsi, dst);
8257 }
8258
8259 void Assembler::fnstcw(Address src) {
8260 InstructionMark im(this);
8261 emit_int8((unsigned char)0x9B);
8262 emit_int8((unsigned char)0xD9);
8263 emit_operand32(rdi, src);
8264 }
8265
8266 void Assembler::fnstsw_ax() {
8267 emit_int8((unsigned char)0xDF);
8268 emit_int8((unsigned char)0xE0);
8269 }
8270
8271 void Assembler::fprem() {
8272 emit_int8((unsigned char)0xD9);
8273 emit_int8((unsigned char)0xF8);
8274 }
8275
8276 void Assembler::fprem1() {
8277 emit_int8((unsigned char)0xD9);
8278 emit_int8((unsigned char)0xF5);
8279 }
8280
8281 void Assembler::frstor(Address src) {
8282 InstructionMark im(this);
8283 emit_int8((unsigned char)0xDD);
8284 emit_operand32(rsp, src);
8285 }
8286
8287 void Assembler::fsin() {
8288 emit_int8((unsigned char)0xD9);
8289 emit_int8((unsigned char)0xFE);
8290 }
8291
8292 void Assembler::fsqrt() {
8293 emit_int8((unsigned char)0xD9);
8294 emit_int8((unsigned char)0xFA);
8295 }
8296
8297 void Assembler::fst_d(Address adr) {
8298 InstructionMark im(this);
8299 emit_int8((unsigned char)0xDD);
8300 emit_operand32(rdx, adr);
8301 }
8302
8303 void Assembler::fst_s(Address adr) {
8304 InstructionMark im(this);
8305 emit_int8((unsigned char)0xD9);
8306 emit_operand32(rdx, adr);
8307 }
8308
8309 void Assembler::fstp_d(Address adr) {
8310 InstructionMark im(this);
8311 emit_int8((unsigned char)0xDD);
8312 emit_operand32(rbx, adr);
8313 }
8314
8315 void Assembler::fstp_d(int index) {
8316 emit_farith(0xDD, 0xD8, index);
8317 }
8318
8319 void Assembler::fstp_s(Address adr) {
8320 InstructionMark im(this);
8321 emit_int8((unsigned char)0xD9);
8322 emit_operand32(rbx, adr);
8323 }
8324
8325 void Assembler::fstp_x(Address adr) {
8326 InstructionMark im(this);
8327 emit_int8((unsigned char)0xDB);
8328 emit_operand32(rdi, adr);
8329 }
8330
8331 void Assembler::fsub(int i) {
8332 emit_farith(0xD8, 0xE0, i);
8333 }
8334
8335 void Assembler::fsub_d(Address src) {
8336 InstructionMark im(this);
8337 emit_int8((unsigned char)0xDC);
8338 emit_operand32(rsp, src);
8339 }
8340
8341 void Assembler::fsub_s(Address src) {
8342 InstructionMark im(this);
8343 emit_int8((unsigned char)0xD8);
8344 emit_operand32(rsp, src);
8345 }
8346
8347 void Assembler::fsuba(int i) {
8348 emit_farith(0xDC, 0xE8, i);
8349 }
8350
8351 void Assembler::fsubp(int i) {
8352 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong)
8353 }
8354
8355 void Assembler::fsubr(int i) {
8356 emit_farith(0xD8, 0xE8, i);
8357 }
8358
8359 void Assembler::fsubr_d(Address src) {
8360 InstructionMark im(this);
8361 emit_int8((unsigned char)0xDC);
8362 emit_operand32(rbp, src);
8363 }
8364
8365 void Assembler::fsubr_s(Address src) {
8366 InstructionMark im(this);
8367 emit_int8((unsigned char)0xD8);
8368 emit_operand32(rbp, src);
8369 }
8370
8371 void Assembler::fsubra(int i) {
8372 emit_farith(0xDC, 0xE0, i);
8373 }
8374
8375 void Assembler::fsubrp(int i) {
8376 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong)
8377 }
8378
8379 void Assembler::ftan() {
8380 emit_int8((unsigned char)0xD9);
8381 emit_int8((unsigned char)0xF2);
8382 emit_int8((unsigned char)0xDD);
8383 emit_int8((unsigned char)0xD8);
8384 }
8385
8386 void Assembler::ftst() {
8387 emit_int8((unsigned char)0xD9);
8388 emit_int8((unsigned char)0xE4);
8389 }
8390
8391 void Assembler::fucomi(int i) {
8392 // make sure the instruction is supported (introduced for P6, together with cmov)
8393 guarantee(VM_Version::supports_cmov(), "illegal instruction");
8394 emit_farith(0xDB, 0xE8, i);
8395 }
8396
8397 void Assembler::fucomip(int i) {
8398 // make sure the instruction is supported (introduced for P6, together with cmov)
8399 guarantee(VM_Version::supports_cmov(), "illegal instruction");
8400 emit_farith(0xDF, 0xE8, i);
8401 }
8402
8403 void Assembler::fwait() {
8404 emit_int8((unsigned char)0x9B);
8405 }
8406
8407 void Assembler::fxch(int i) {
8408 emit_farith(0xD9, 0xC8, i);
8409 }
8410
8411 void Assembler::fyl2x() {
8412 emit_int8((unsigned char)0xD9);
8413 emit_int8((unsigned char)0xF1);
8414 }
8415
8416 void Assembler::frndint() {
8417 emit_int8((unsigned char)0xD9);
8418 emit_int8((unsigned char)0xFC);
8419 }
8420
8421 void Assembler::f2xm1() {
8422 emit_int8((unsigned char)0xD9);
8423 emit_int8((unsigned char)0xF0);
8424 }
8425
8426 void Assembler::fldl2e() {
8427 emit_int8((unsigned char)0xD9);
8428 emit_int8((unsigned char)0xEA);
8429 }
8430
8431 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding.
8432 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 };
8433 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding.
8434 static int simd_opc[4] = { 0, 0, 0x38, 0x3A };
8435
8436 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding.
8437 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
8438 if (pre > 0) {
8439 emit_int8(simd_pre[pre]);
8440 }
8441 if (rex_w) {
8442 prefixq(adr, xreg);
8443 } else {
8444 prefix(adr, xreg);
8445 }
8446 if (opc > 0) {
8447 emit_int8(0x0F);
8448 int opc2 = simd_opc[opc];
8449 if (opc2 > 0) {
8450 emit_int8(opc2);
8451 }
8452 }
8453 }
8454
8455 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
8456 if (pre > 0) {
8457 emit_int8(simd_pre[pre]);
8458 }
8459 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) : prefix_and_encode(dst_enc, src_enc);
8460 if (opc > 0) {
8461 emit_int8(0x0F);
8462 int opc2 = simd_opc[opc];
8463 if (opc2 > 0) {
8464 emit_int8(opc2);
8465 }
8466 }
8467 return encode;
8468 }
8469
8470
8471 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc) {
8472 int vector_len = _attributes->get_vector_len();
8473 bool vex_w = _attributes->is_rex_vex_w();
8474 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) {
8475 prefix(VEX_3bytes);
8476
8477 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0);
8478 byte1 = (~byte1) & 0xE0;
8479 byte1 |= opc;
8480 emit_int8(byte1);
8481
8482 int byte2 = ((~nds_enc) & 0xf) << 3;
8483 byte2 |= (vex_w ? VEX_W : 0) | ((vector_len > 0) ? 4 : 0) | pre;
8484 emit_int8(byte2);
8485 } else {
8486 prefix(VEX_2bytes);
8487
8488 int byte1 = vex_r ? VEX_R : 0;
8489 byte1 = (~byte1) & 0x80;
8490 byte1 |= ((~nds_enc) & 0xf) << 3;
8491 byte1 |= ((vector_len > 0 ) ? 4 : 0) | pre;
8492 emit_int8(byte1);
8493 }
8494 }
8495
8496 // This is a 4 byte encoding
8497 void Assembler::evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_r, bool evex_v, int nds_enc, VexSimdPrefix pre, VexOpcode opc){
8498 // EVEX 0x62 prefix
8499 prefix(EVEX_4bytes);
8500 bool vex_w = _attributes->is_rex_vex_w();
8501 int evex_encoding = (vex_w ? VEX_W : 0);
8502 // EVEX.b is not currently used for broadcast of single element or data rounding modes
8503 _attributes->set_evex_encoding(evex_encoding);
8504
8505 // P0: byte 2, initialized to RXBR`00mm
8506 // instead of not'd
8507 int byte2 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0) | (evex_r ? EVEX_Rb : 0);
8508 byte2 = (~byte2) & 0xF0;
8509 // confine opc opcode extensions in mm bits to lower two bits
8510 // of form {0F, 0F_38, 0F_3A}
8511 byte2 |= opc;
8512 emit_int8(byte2);
8513
8514 // P1: byte 3 as Wvvvv1pp
8515 int byte3 = ((~nds_enc) & 0xf) << 3;
8516 // p[10] is always 1
8517 byte3 |= EVEX_F;
8518 byte3 |= (vex_w & 1) << 7;
8519 // confine pre opcode extensions in pp bits to lower two bits
8520 // of form {66, F3, F2}
8521 byte3 |= pre;
8522 emit_int8(byte3);
8523
8524 // P2: byte 4 as zL'Lbv'aaa
8525 // kregs are implemented in the low 3 bits as aaa (hard code k1, it will be initialized for now)
8526 int byte4 = (_attributes->is_no_reg_mask()) ?
8527 0 :
8528 _attributes->get_embedded_opmask_register_specifier();
8529 // EVEX.v` for extending EVEX.vvvv or VIDX
8530 byte4 |= (evex_v ? 0: EVEX_V);
8531 // third EXEC.b for broadcast actions
8532 byte4 |= (_attributes->is_extended_context() ? EVEX_Rb : 0);
8533 // fourth EVEX.L'L for vector length : 0 is 128, 1 is 256, 2 is 512, currently we do not support 1024
8534 byte4 |= ((_attributes->get_vector_len())& 0x3) << 5;
8535 // last is EVEX.z for zero/merge actions
8536 if (_attributes->is_no_reg_mask() == false) {
8537 byte4 |= (_attributes->is_clear_context() ? EVEX_Z : 0);
8538 }
8539 emit_int8(byte4);
8540 }
8541
8542 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) {
8543 bool vex_r = ((xreg_enc & 8) == 8) ? 1 : 0;
8544 bool vex_b = adr.base_needs_rex();
8545 bool vex_x;
8546 if (adr.isxmmindex()) {
8547 vex_x = adr.xmmindex_needs_rex();
8548 } else {
8549 vex_x = adr.index_needs_rex();
8550 }
8551 set_attributes(attributes);
8552 attributes->set_current_assembler(this);
8553
8554 // if vector length is turned off, revert to AVX for vectors smaller than 512-bit
8555 if (UseAVX > 2 && _legacy_mode_vl && attributes->uses_vl()) {
8556 switch (attributes->get_vector_len()) {
8557 case AVX_128bit:
8558 case AVX_256bit:
8559 attributes->set_is_legacy_mode();
8560 break;
8561 }
8562 }
8563
8564 // For pure EVEX check and see if this instruction
8565 // is allowed in legacy mode and has resources which will
8566 // fit in it. Pure EVEX instructions will use set_is_evex_instruction in their definition,
8567 // else that field is set when we encode to EVEX
8568 if (UseAVX > 2 && !attributes->is_legacy_mode() &&
8569 !_is_managed && !attributes->is_evex_instruction()) {
8570 if (!_legacy_mode_vl && attributes->get_vector_len() != AVX_512bit) {
8571 bool check_register_bank = NOT_IA32(true) IA32_ONLY(false);
8572 if (check_register_bank) {
8573 // check nds_enc and xreg_enc for upper bank usage
8574 if (nds_enc < 16 && xreg_enc < 16) {
8575 attributes->set_is_legacy_mode();
8576 }
8577 } else {
8578 attributes->set_is_legacy_mode();
8579 }
8580 }
8581 }
8582
8583 _is_managed = false;
8584 if (UseAVX > 2 && !attributes->is_legacy_mode())
8585 {
8586 bool evex_r = (xreg_enc >= 16);
8587 bool evex_v;
8588 // EVEX.V' is set to true when VSIB is used as we may need to use higher order XMM registers (16-31)
8589 if (adr.isxmmindex()) {
8590 evex_v = ((adr._xmmindex->encoding() > 15) ? true : false);
8591 } else {
8592 evex_v = (nds_enc >= 16);
8593 }
8594 attributes->set_is_evex_instruction();
8595 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc);
8596 } else {
8597 if (UseAVX > 2 && attributes->is_rex_vex_w_reverted()) {
8598 attributes->set_rex_vex_w(false);
8599 }
8600 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc);
8601 }
8602 }
8603
8604 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) {
8605 bool vex_r = ((dst_enc & 8) == 8) ? 1 : 0;
8606 bool vex_b = ((src_enc & 8) == 8) ? 1 : 0;
8607 bool vex_x = false;
8608 set_attributes(attributes);
8609 attributes->set_current_assembler(this);
8610 bool check_register_bank = NOT_IA32(true) IA32_ONLY(false);
8611
8612 // if vector length is turned off, revert to AVX for vectors smaller than 512-bit
8613 if (UseAVX > 2 && _legacy_mode_vl && attributes->uses_vl()) {
8614 switch (attributes->get_vector_len()) {
8615 case AVX_128bit:
8616 case AVX_256bit:
8617 if (check_register_bank) {
8618 if (dst_enc >= 16 || nds_enc >= 16 || src_enc >= 16) {
8619 // up propagate arithmetic instructions to meet RA requirements
8620 attributes->set_vector_len(AVX_512bit);
8621 } else {
8622 attributes->set_is_legacy_mode();
8623 }
8624 } else {
8625 attributes->set_is_legacy_mode();
8626 }
8627 break;
8628 }
8629 }
8630
8631 // For pure EVEX check and see if this instruction
8632 // is allowed in legacy mode and has resources which will
8633 // fit in it. Pure EVEX instructions will use set_is_evex_instruction in their definition,
8634 // else that field is set when we encode to EVEX
8635 if (UseAVX > 2 && !attributes->is_legacy_mode() &&
8636 !_is_managed && !attributes->is_evex_instruction()) {
8637 if (!_legacy_mode_vl && attributes->get_vector_len() != AVX_512bit) {
8638 if (check_register_bank) {
8639 // check dst_enc, nds_enc and src_enc for upper bank usage
8640 if (dst_enc < 16 && nds_enc < 16 && src_enc < 16) {
8641 attributes->set_is_legacy_mode();
8642 }
8643 } else {
8644 attributes->set_is_legacy_mode();
8645 }
8646 }
8647 }
8648
8649 _is_managed = false;
8650 if (UseAVX > 2 && !attributes->is_legacy_mode())
8651 {
8652 bool evex_r = (dst_enc >= 16);
8653 bool evex_v = (nds_enc >= 16);
8654 // can use vex_x as bank extender on rm encoding
8655 vex_x = (src_enc >= 16);
8656 attributes->set_is_evex_instruction();
8657 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc);
8658 } else {
8659 if (UseAVX > 2 && attributes->is_rex_vex_w_reverted()) {
8660 attributes->set_rex_vex_w(false);
8661 }
8662 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc);
8663 }
8664
8665 // return modrm byte components for operands
8666 return (((dst_enc & 7) << 3) | (src_enc & 7));
8667 }
8668
8669
8670 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre,
8671 VexOpcode opc, InstructionAttr *attributes) {
8672 if (UseAVX > 0) {
8673 int xreg_enc = xreg->encoding();
8674 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
8675 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, attributes);
8676 } else {
8677 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding");
8678 rex_prefix(adr, xreg, pre, opc, attributes->is_rex_vex_w());
8679 }
8680 }
8681
8682 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre,
8683 VexOpcode opc, InstructionAttr *attributes) {
8684 int dst_enc = dst->encoding();
8685 int src_enc = src->encoding();
8686 if (UseAVX > 0) {
8687 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
8688 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, attributes);
8689 } else {
8690 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding");
8691 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, attributes->is_rex_vex_w());
8692 }
8693 }
8694
8695 void Assembler::vcmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) {
8696 // This encoding is upto AVX2
8697 assert(VM_Version::supports_avx(), "");
8698 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
8699 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8700 emit_int8((unsigned char)0xC2);
8701 emit_int8((unsigned char)(0xC0 | encode));
8702 emit_int8((unsigned char)(0xF & cop));
8703 }
8704
8705 void Assembler::vblendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) {
8706 assert(UseAVX > 0 && (vector_len == AVX_128bit || vector_len == AVX_256bit), "");
8707 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
8708 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8709 emit_int8((unsigned char)0x4B);
8710 emit_int8((unsigned char)(0xC0 | encode));
8711 int src2_enc = src2->encoding();
8712 emit_int8((unsigned char)(0xF0 & src2_enc<<4));
8713 }
8714
8715 void Assembler::vpblendd(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
8716 assert(VM_Version::supports_avx2(), "");
8717 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
8718 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8719 emit_int8((unsigned char)0x02);
8720 emit_int8((unsigned char)(0xC0 | encode));
8721 emit_int8((unsigned char)imm8);
8722 }
8723
8724 void Assembler::vcmpps(XMMRegister dst, XMMRegister nds, XMMRegister src, int comparison, int vector_len) {
8725 assert(VM_Version::supports_avx(), "");
8726 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8727 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
8728 emit_int8((unsigned char)0xC2);
8729 emit_int8((unsigned char)(0xC0 | encode));
8730 emit_int8((unsigned char)comparison);
8731 }
8732
8733 void Assembler::evcmpps(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
8734 ComparisonPredicateFP comparison, int vector_len) {
8735 assert(VM_Version::supports_evex(), "");
8736 // Encoding: EVEX.NDS.XXX.0F.W0 C2 /r ib
8737 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
8738 attributes.set_is_evex_instruction();
8739 attributes.set_embedded_opmask_register_specifier(mask);
8740 attributes.reset_is_clear_context();
8741 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
8742 emit_int8((unsigned char)0xC2);
8743 emit_int8((unsigned char)(0xC0 | encode));
8744 emit_int8((unsigned char)comparison);
8745 }
8746
8747 void Assembler::evcmppd(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
8748 ComparisonPredicateFP comparison, int vector_len) {
8749 assert(VM_Version::supports_evex(), "");
8750 // Encoding: EVEX.NDS.XXX.66.0F.W1 C2 /r ib
8751 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
8752 attributes.set_is_evex_instruction();
8753 attributes.set_embedded_opmask_register_specifier(mask);
8754 attributes.reset_is_clear_context();
8755 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8756 emit_int8((unsigned char)0xC2);
8757 emit_int8((unsigned char)(0xC0 | encode));
8758 emit_int8((unsigned char)comparison);
8759 }
8760
8761 void Assembler::blendvps(XMMRegister dst, XMMRegister src) {
8762 assert(VM_Version::supports_sse4_1(), "");
8763 assert(UseAVX <= 0, "sse encoding is inconsistent with avx encoding");
8764 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
8765 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8766 emit_int8(0x14);
8767 emit_int8((unsigned char)(0xC0 | encode));
8768 }
8769
8770 void Assembler::blendvpd(XMMRegister dst, XMMRegister src) {
8771 assert(VM_Version::supports_sse4_1(), "");
8772 assert(UseAVX <= 0, "sse encoding is inconsistent with avx encoding");
8773 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
8774 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8775 emit_int8(0x15);
8776 emit_int8((unsigned char)(0xC0 | encode));
8777 }
8778
8779 void Assembler::pblendvb(XMMRegister dst, XMMRegister src) {
8780 assert(VM_Version::supports_sse4_1(), "");
8781 assert(UseAVX <= 0, "sse encoding is inconsistent with avx encoding");
8782 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8783 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8784 emit_int8(0x10);
8785 emit_int8((unsigned char)(0xC0 | encode));
8786 }
8787
8788 void Assembler::vblendvps(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len) {
8789 assert(UseAVX > 0 && (vector_len == AVX_128bit || vector_len == AVX_256bit), "");
8790 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8791 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8792 emit_int8((unsigned char)0x4A);
8793 emit_int8((unsigned char)(0xC0 | encode));
8794 int mask_enc = mask->encoding();
8795 emit_int8((unsigned char)(0xF0 & mask_enc<<4));
8796 }
8797
8798 void Assembler::vpcmpgtb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
8799 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2(), "");
8800 assert(vector_len <= AVX_256bit, "evex encoding is different - has k register as dest");
8801 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
8802 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8803 emit_int8((unsigned char)0x64);
8804 emit_int8((unsigned char)(0xC0 | encode));
8805 }
8806
8807 void Assembler::vpcmpgtw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
8808 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2(), "");
8809 assert(vector_len <= AVX_256bit, "evex encoding is different - has k register as dest");
8810 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
8811 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8812 emit_int8((unsigned char)0x65);
8813 emit_int8((unsigned char)(0xC0 | encode));
8814 }
8815
8816 void Assembler::vpcmpgtd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
8817 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2(), "");
8818 assert(vector_len <= AVX_256bit, "evex encoding is different - has k register as dest");
8819 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
8820 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8821 emit_int8((unsigned char)0x66);
8822 emit_int8((unsigned char)(0xC0 | encode));
8823 }
8824
8825 void Assembler::vpcmpgtq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
8826 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2(), "");
8827 assert(vector_len <= AVX_256bit, "evex encoding is different - has k register as dest");
8828 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
8829 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8830 emit_int8((unsigned char)0x37);
8831 emit_int8((unsigned char)(0xC0 | encode));
8832 }
8833
8834 void Assembler::evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
8835 int comparison, int vector_len) {
8836 assert(VM_Version::supports_evex(), "");
8837 assert(comparison >= Assembler::eq && comparison <= Assembler::_true, "");
8838 // Encoding: EVEX.NDS.XXX.66.0F3A.W0 1F /r ib
8839 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
8840 attributes.set_is_evex_instruction();
8841 attributes.set_embedded_opmask_register_specifier(mask);
8842 attributes.reset_is_clear_context();
8843 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8844 emit_int8((unsigned char)0x1F);
8845 emit_int8((unsigned char)(0xC0 | encode));
8846 emit_int8((unsigned char)comparison);
8847 }
8848
8849 void Assembler::evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, Address src,
8850 int comparison, int vector_len) {
8851 assert(VM_Version::supports_evex(), "");
8852 assert(comparison >= Assembler::eq && comparison <= Assembler::_true, "");
8853 // Encoding: EVEX.NDS.XXX.66.0F3A.W0 1F /r ib
8854 InstructionMark im(this);
8855 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
8856 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_NObit);
8857 attributes.set_is_evex_instruction();
8858 attributes.set_embedded_opmask_register_specifier(mask);
8859 attributes.reset_is_clear_context();
8860 int dst_enc = kdst->encoding();
8861 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8862 emit_int8((unsigned char)0x1F);
8863 emit_operand(as_Register(dst_enc), src);
8864 emit_int8((unsigned char)comparison);
8865 }
8866
8867 void Assembler::evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
8868 int comparison, int vector_len) {
8869 assert(VM_Version::supports_evex(), "");
8870 assert(comparison >= Assembler::eq && comparison <= Assembler::_true, "");
8871 // Encoding: EVEX.NDS.XXX.66.0F3A.W1 1F /r ib
8872 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
8873 attributes.set_is_evex_instruction();
8874 attributes.set_embedded_opmask_register_specifier(mask);
8875 attributes.reset_is_clear_context();
8876 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8877 emit_int8((unsigned char)0x1F);
8878 emit_int8((unsigned char)(0xC0 | encode));
8879 emit_int8((unsigned char)comparison);
8880 }
8881
8882 void Assembler::evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, Address src,
8883 int comparison, int vector_len) {
8884 assert(VM_Version::supports_evex(), "");
8885 assert(comparison >= Assembler::eq && comparison <= Assembler::_true, "");
8886 // Encoding: EVEX.NDS.XXX.66.0F3A.W1 1F /r ib
8887 InstructionMark im(this);
8888 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
8889 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_NObit);
8890 attributes.set_is_evex_instruction();
8891 attributes.set_embedded_opmask_register_specifier(mask);
8892 attributes.reset_is_clear_context();
8893 int dst_enc = kdst->encoding();
8894 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8895 emit_int8((unsigned char)0x1F);
8896 emit_operand(as_Register(dst_enc), src);
8897 emit_int8((unsigned char)comparison);
8898 }
8899
8900 void Assembler::evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
8901 int comparison, int vector_len) {
8902 assert(VM_Version::supports_evex(), "");
8903 assert(VM_Version::supports_avx512bw(), "");
8904 assert(comparison >= Assembler::eq && comparison <= Assembler::_true, "");
8905 // Encoding: EVEX.NDS.XXX.66.0F3A.W0 3F /r ib
8906 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
8907 attributes.set_is_evex_instruction();
8908 attributes.set_embedded_opmask_register_specifier(mask);
8909 attributes.reset_is_clear_context();
8910 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8911 emit_int8((unsigned char)0x3F);
8912 emit_int8((unsigned char)(0xC0 | encode));
8913 emit_int8((unsigned char)comparison);
8914 }
8915
8916 void Assembler::evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, Address src,
8917 int comparison, int vector_len) {
8918 assert(VM_Version::supports_evex(), "");
8919 assert(VM_Version::supports_avx512bw(), "");
8920 assert(comparison >= Assembler::eq && comparison <= Assembler::_true, "");
8921 // Encoding: EVEX.NDS.XXX.66.0F3A.W0 3F /r ib
8922 InstructionMark im(this);
8923 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
8924 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
8925 attributes.set_is_evex_instruction();
8926 attributes.set_embedded_opmask_register_specifier(mask);
8927 attributes.reset_is_clear_context();
8928 int dst_enc = kdst->encoding();
8929 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8930 emit_int8((unsigned char)0x3F);
8931 emit_operand(as_Register(dst_enc), src);
8932 emit_int8((unsigned char)comparison);
8933 }
8934
8935 void Assembler::evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
8936 int comparison, int vector_len) {
8937 assert(VM_Version::supports_evex(), "");
8938 assert(VM_Version::supports_avx512bw(), "");
8939 assert(comparison >= Assembler::eq && comparison <= Assembler::_true, "");
8940 // Encoding: EVEX.NDS.XXX.66.0F3A.W1 3F /r ib
8941 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
8942 attributes.set_is_evex_instruction();
8943 attributes.set_embedded_opmask_register_specifier(mask);
8944 attributes.reset_is_clear_context();
8945 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8946 emit_int8((unsigned char)0x3F);
8947 emit_int8((unsigned char)(0xC0 | encode));
8948 emit_int8((unsigned char)comparison);
8949 }
8950
8951 void Assembler::evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, Address src,
8952 int comparison, int vector_len) {
8953 assert(VM_Version::supports_evex(), "");
8954 assert(VM_Version::supports_avx512bw(), "");
8955 assert(comparison >= Assembler::eq && comparison <= Assembler::_true, "");
8956 // Encoding: EVEX.NDS.XXX.66.0F3A.W1 3F /r ib
8957 InstructionMark im(this);
8958 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
8959 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
8960 attributes.set_is_evex_instruction();
8961 attributes.set_embedded_opmask_register_specifier(mask);
8962 attributes.reset_is_clear_context();
8963 int dst_enc = kdst->encoding();
8964 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8965 emit_int8((unsigned char)0x3F);
8966 emit_operand(as_Register(dst_enc), src);
8967 emit_int8((unsigned char)comparison);
8968 }
8969
8970 void Assembler::vpblendvb(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len) {
8971 assert(VM_Version::supports_avx(), "");
8972 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8973 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8974 emit_int8((unsigned char)0x4C);
8975 emit_int8((unsigned char)(0xC0 | encode));
8976 int mask_enc = mask->encoding();
8977 emit_int8((unsigned char)(0xF0 & mask_enc << 4));
8978 }
8979
8980 void Assembler::evblendmpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
8981 assert(VM_Version::supports_evex(), "");
8982 // Encoding: EVEX.NDS.XXX.66.0F38.W1 65 /r
8983 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
8984 attributes.set_is_evex_instruction();
8985 attributes.set_embedded_opmask_register_specifier(mask);
8986 if (merge) {
8987 attributes.reset_is_clear_context();
8988 }
8989 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8990 emit_int8((unsigned char)0x65);
8991 emit_int8((unsigned char)(0xC0 | encode));
8992 }
8993
8994 void Assembler::evblendmps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
8995 assert(VM_Version::supports_evex(), "");
8996 // Encoding: EVEX.NDS.XXX.66.0F38.W0 65 /r
8997 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
8998 attributes.set_is_evex_instruction();
8999 attributes.set_embedded_opmask_register_specifier(mask);
9000 if (merge) {
9001 attributes.reset_is_clear_context();
9002 }
9003 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9004 emit_int8((unsigned char)0x65);
9005 emit_int8((unsigned char)(0xC0 | encode));
9006 }
9007
9008 void Assembler::evpblendmb (XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9009 assert(VM_Version::supports_evex(), "");
9010 assert(VM_Version::supports_avx512bw(), "");
9011 // Encoding: EVEX.NDS.512.66.0F38.W0 66 /r
9012 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
9013 attributes.set_is_evex_instruction();
9014 attributes.set_embedded_opmask_register_specifier(mask);
9015 if (merge) {
9016 attributes.reset_is_clear_context();
9017 }
9018 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9019 emit_int8((unsigned char)0x66);
9020 emit_int8((unsigned char)(0xC0 | encode));
9021 }
9022
9023 void Assembler::evpblendmw (XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9024 assert(VM_Version::supports_evex(), "");
9025 assert(VM_Version::supports_avx512bw(), "");
9026 // Encoding: EVEX.NDS.512.66.0F38.W1 66 /r
9027 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
9028 attributes.set_is_evex_instruction();
9029 attributes.set_embedded_opmask_register_specifier(mask);
9030 if (merge) {
9031 attributes.reset_is_clear_context();
9032 }
9033 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9034 emit_int8((unsigned char)0x66);
9035 emit_int8((unsigned char)(0xC0 | encode));
9036 }
9037
9038 void Assembler::evpblendmd (XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9039 assert(VM_Version::supports_evex(), "");
9040 //Encoding: EVEX.NDS.512.66.0F38.W0 64 /r
9041 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
9042 attributes.set_is_evex_instruction();
9043 attributes.set_embedded_opmask_register_specifier(mask);
9044 if (merge) {
9045 attributes.reset_is_clear_context();
9046 }
9047 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9048 emit_int8((unsigned char)0x64);
9049 emit_int8((unsigned char)(0xC0 | encode));
9050 }
9051
9052 void Assembler::evpblendmq (XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9053 assert(VM_Version::supports_evex(), "");
9054 //Encoding: EVEX.NDS.512.66.0F38.W1 64 /r
9055 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
9056 attributes.set_is_evex_instruction();
9057 attributes.set_embedded_opmask_register_specifier(mask);
9058 if (merge) {
9059 attributes.reset_is_clear_context();
9060 }
9061 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9062 emit_int8((unsigned char)0x64);
9063 emit_int8((unsigned char)(0xC0 | encode));
9064 }
9065
9066 void Assembler::shlxl(Register dst, Register src1, Register src2) {
9067 assert(VM_Version::supports_bmi2(), "");
9068 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
9069 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9070 emit_int8((unsigned char)0xF7);
9071 emit_int8((unsigned char)(0xC0 | encode));
9072 }
9073
9074 void Assembler::shlxq(Register dst, Register src1, Register src2) {
9075 assert(VM_Version::supports_bmi2(), "");
9076 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
9077 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9078 emit_int8((unsigned char)0xF7);
9079 emit_int8((unsigned char)(0xC0 | encode));
9080 }
9081
9082 #ifndef _LP64
9083
9084 void Assembler::incl(Register dst) {
9085 // Don't use it directly. Use MacroAssembler::incrementl() instead.
9086 emit_int8(0x40 | dst->encoding());
9087 }
9088
9089 void Assembler::lea(Register dst, Address src) {
9090 leal(dst, src);
9091 }
9092
9093 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
9094 InstructionMark im(this);
9095 emit_int8((unsigned char)0xC7);
9096 emit_operand(rax, dst);
9097 emit_data((int)imm32, rspec, 0);
9098 }
9099
9100 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
9101 InstructionMark im(this);
9102 int encode = prefix_and_encode(dst->encoding());
9103 emit_int8((unsigned char)(0xB8 | encode));
9104 emit_data((int)imm32, rspec, 0);
9105 }
9106
9107 void Assembler::popa() { // 32bit
9108 emit_int8(0x61);
9109 }
9110
9111 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
9112 InstructionMark im(this);
9113 emit_int8(0x68);
9114 emit_data(imm32, rspec, 0);
9115 }
9116
9117 void Assembler::pusha() { // 32bit
9118 emit_int8(0x60);
9119 }
9120
9121 void Assembler::set_byte_if_not_zero(Register dst) {
9122 emit_int8(0x0F);
9123 emit_int8((unsigned char)0x95);
9124 emit_int8((unsigned char)(0xE0 | dst->encoding()));
9125 }
9126
9127 void Assembler::shldl(Register dst, Register src) {
9128 emit_int8(0x0F);
9129 emit_int8((unsigned char)0xA5);
9130 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
9131 }
9132
9133 // 0F A4 / r ib
9134 void Assembler::shldl(Register dst, Register src, int8_t imm8) {
9135 emit_int8(0x0F);
9136 emit_int8((unsigned char)0xA4);
9137 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
9138 emit_int8(imm8);
9139 }
9140
9141 void Assembler::shrdl(Register dst, Register src) {
9142 emit_int8(0x0F);
9143 emit_int8((unsigned char)0xAD);
9144 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
9145 }
9146
9147 #else // LP64
9148
9149 void Assembler::set_byte_if_not_zero(Register dst) {
9150 int enc = prefix_and_encode(dst->encoding(), true);
9151 emit_int8(0x0F);
9152 emit_int8((unsigned char)0x95);
9153 emit_int8((unsigned char)(0xE0 | enc));
9154 }
9155
9156 // 64bit only pieces of the assembler
9157 // This should only be used by 64bit instructions that can use rip-relative
9158 // it cannot be used by instructions that want an immediate value.
9159
9160 bool Assembler::reachable(AddressLiteral adr) {
9161 int64_t disp;
9162 // None will force a 64bit literal to the code stream. Likely a placeholder
9163 // for something that will be patched later and we need to certain it will
9164 // always be reachable.
9165 if (adr.reloc() == relocInfo::none) {
9166 return false;
9167 }
9168 if (adr.reloc() == relocInfo::internal_word_type) {
9169 // This should be rip relative and easily reachable.
9170 return true;
9171 }
9172 if (adr.reloc() == relocInfo::virtual_call_type ||
9173 adr.reloc() == relocInfo::opt_virtual_call_type ||
9174 adr.reloc() == relocInfo::static_call_type ||
9175 adr.reloc() == relocInfo::static_stub_type ) {
9176 // This should be rip relative within the code cache and easily
9177 // reachable until we get huge code caches. (At which point
9178 // ic code is going to have issues).
9179 return true;
9180 }
9181 if (adr.reloc() != relocInfo::external_word_type &&
9182 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special
9183 adr.reloc() != relocInfo::poll_type && // relocs to identify them
9184 adr.reloc() != relocInfo::runtime_call_type ) {
9185 return false;
9186 }
9187
9188 // Stress the correction code
9189 if (ForceUnreachable) {
9190 // Must be runtimecall reloc, see if it is in the codecache
9191 // Flipping stuff in the codecache to be unreachable causes issues
9192 // with things like inline caches where the additional instructions
9193 // are not handled.
9194 if (CodeCache::find_blob(adr._target) == NULL) {
9195 return false;
9196 }
9197 }
9198 // For external_word_type/runtime_call_type if it is reachable from where we
9199 // are now (possibly a temp buffer) and where we might end up
9200 // anywhere in the codeCache then we are always reachable.
9201 // This would have to change if we ever save/restore shared code
9202 // to be more pessimistic.
9203 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int));
9204 if (!is_simm32(disp)) return false;
9205 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int));
9206 if (!is_simm32(disp)) return false;
9207
9208 disp = (int64_t)adr._target - ((int64_t)pc() + sizeof(int));
9209
9210 // Because rip relative is a disp + address_of_next_instruction and we
9211 // don't know the value of address_of_next_instruction we apply a fudge factor
9212 // to make sure we will be ok no matter the size of the instruction we get placed into.
9213 // We don't have to fudge the checks above here because they are already worst case.
9214
9215 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal
9216 // + 4 because better safe than sorry.
9217 const int fudge = 12 + 4;
9218 if (disp < 0) {
9219 disp -= fudge;
9220 } else {
9221 disp += fudge;
9222 }
9223 return is_simm32(disp);
9224 }
9225
9226 // Check if the polling page is not reachable from the code cache using rip-relative
9227 // addressing.
9228 bool Assembler::is_polling_page_far() {
9229 intptr_t addr = (intptr_t)os::get_polling_page();
9230 return ForceUnreachable ||
9231 !is_simm32(addr - (intptr_t)CodeCache::low_bound()) ||
9232 !is_simm32(addr - (intptr_t)CodeCache::high_bound());
9233 }
9234
9235 void Assembler::emit_data64(jlong data,
9236 relocInfo::relocType rtype,
9237 int format) {
9238 if (rtype == relocInfo::none) {
9239 emit_int64(data);
9240 } else {
9241 emit_data64(data, Relocation::spec_simple(rtype), format);
9242 }
9243 }
9244
9245 void Assembler::emit_data64(jlong data,
9246 RelocationHolder const& rspec,
9247 int format) {
9248 assert(imm_operand == 0, "default format must be immediate in this file");
9249 assert(imm_operand == format, "must be immediate");
9250 assert(inst_mark() != NULL, "must be inside InstructionMark");
9251 // Do not use AbstractAssembler::relocate, which is not intended for
9252 // embedded words. Instead, relocate to the enclosing instruction.
9253 code_section()->relocate(inst_mark(), rspec, format);
9254 #ifdef ASSERT
9255 check_relocation(rspec, format);
9256 #endif
9257 emit_int64(data);
9258 }
9259
9260 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) {
9261 if (reg_enc >= 8) {
9262 prefix(REX_B);
9263 reg_enc -= 8;
9264 } else if (byteinst && reg_enc >= 4) {
9265 prefix(REX);
9266 }
9267 return reg_enc;
9268 }
9269
9270 int Assembler::prefixq_and_encode(int reg_enc) {
9271 if (reg_enc < 8) {
9272 prefix(REX_W);
9273 } else {
9274 prefix(REX_WB);
9275 reg_enc -= 8;
9276 }
9277 return reg_enc;
9278 }
9279
9280 int Assembler::prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte) {
9281 if (dst_enc < 8) {
9282 if (src_enc >= 8) {
9283 prefix(REX_B);
9284 src_enc -= 8;
9285 } else if ((src_is_byte && src_enc >= 4) || (dst_is_byte && dst_enc >= 4)) {
9286 prefix(REX);
9287 }
9288 } else {
9289 if (src_enc < 8) {
9290 prefix(REX_R);
9291 } else {
9292 prefix(REX_RB);
9293 src_enc -= 8;
9294 }
9295 dst_enc -= 8;
9296 }
9297 return dst_enc << 3 | src_enc;
9298 }
9299
9300 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) {
9301 if (dst_enc < 8) {
9302 if (src_enc < 8) {
9303 prefix(REX_W);
9304 } else {
9305 prefix(REX_WB);
9306 src_enc -= 8;
9307 }
9308 } else {
9309 if (src_enc < 8) {
9310 prefix(REX_WR);
9311 } else {
9312 prefix(REX_WRB);
9313 src_enc -= 8;
9314 }
9315 dst_enc -= 8;
9316 }
9317 return dst_enc << 3 | src_enc;
9318 }
9319
9320 void Assembler::prefix(Register reg) {
9321 if (reg->encoding() >= 8) {
9322 prefix(REX_B);
9323 }
9324 }
9325
9326 void Assembler::prefix(Register dst, Register src, Prefix p) {
9327 if (src->encoding() >= 8) {
9328 p = (Prefix)(p | REX_B);
9329 }
9330 if (dst->encoding() >= 8) {
9331 p = (Prefix)( p | REX_R);
9332 }
9333 if (p != Prefix_EMPTY) {
9334 // do not generate an empty prefix
9335 prefix(p);
9336 }
9337 }
9338
9339 void Assembler::prefix(Register dst, Address adr, Prefix p) {
9340 if (adr.base_needs_rex()) {
9341 if (adr.index_needs_rex()) {
9342 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X");
9343 } else {
9344 prefix(REX_B);
9345 }
9346 } else {
9347 if (adr.index_needs_rex()) {
9348 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X");
9349 }
9350 }
9351 if (dst->encoding() >= 8) {
9352 p = (Prefix)(p | REX_R);
9353 }
9354 if (p != Prefix_EMPTY) {
9355 // do not generate an empty prefix
9356 prefix(p);
9357 }
9358 }
9359
9360 void Assembler::prefix(Address adr) {
9361 if (adr.base_needs_rex()) {
9362 if (adr.index_needs_rex()) {
9363 prefix(REX_XB);
9364 } else {
9365 prefix(REX_B);
9366 }
9367 } else {
9368 if (adr.index_needs_rex()) {
9369 prefix(REX_X);
9370 }
9371 }
9372 }
9373
9374 void Assembler::prefixq(Address adr) {
9375 if (adr.base_needs_rex()) {
9376 if (adr.index_needs_rex()) {
9377 prefix(REX_WXB);
9378 } else {
9379 prefix(REX_WB);
9380 }
9381 } else {
9382 if (adr.index_needs_rex()) {
9383 prefix(REX_WX);
9384 } else {
9385 prefix(REX_W);
9386 }
9387 }
9388 }
9389
9390
9391 void Assembler::prefix(Address adr, Register reg, bool byteinst) {
9392 if (reg->encoding() < 8) {
9393 if (adr.base_needs_rex()) {
9394 if (adr.index_needs_rex()) {
9395 prefix(REX_XB);
9396 } else {
9397 prefix(REX_B);
9398 }
9399 } else {
9400 if (adr.index_needs_rex()) {
9401 prefix(REX_X);
9402 } else if (byteinst && reg->encoding() >= 4 ) {
9403 prefix(REX);
9404 }
9405 }
9406 } else {
9407 if (adr.base_needs_rex()) {
9408 if (adr.index_needs_rex()) {
9409 prefix(REX_RXB);
9410 } else {
9411 prefix(REX_RB);
9412 }
9413 } else {
9414 if (adr.index_needs_rex()) {
9415 prefix(REX_RX);
9416 } else {
9417 prefix(REX_R);
9418 }
9419 }
9420 }
9421 }
9422
9423 void Assembler::prefixq(Address adr, Register src) {
9424 if (src->encoding() < 8) {
9425 if (adr.base_needs_rex()) {
9426 if (adr.index_needs_rex()) {
9427 prefix(REX_WXB);
9428 } else {
9429 prefix(REX_WB);
9430 }
9431 } else {
9432 if (adr.index_needs_rex()) {
9433 prefix(REX_WX);
9434 } else {
9435 prefix(REX_W);
9436 }
9437 }
9438 } else {
9439 if (adr.base_needs_rex()) {
9440 if (adr.index_needs_rex()) {
9441 prefix(REX_WRXB);
9442 } else {
9443 prefix(REX_WRB);
9444 }
9445 } else {
9446 if (adr.index_needs_rex()) {
9447 prefix(REX_WRX);
9448 } else {
9449 prefix(REX_WR);
9450 }
9451 }
9452 }
9453 }
9454
9455 void Assembler::prefix(Address adr, XMMRegister reg) {
9456 if (reg->encoding() < 8) {
9457 if (adr.base_needs_rex()) {
9458 if (adr.index_needs_rex()) {
9459 prefix(REX_XB);
9460 } else {
9461 prefix(REX_B);
9462 }
9463 } else {
9464 if (adr.index_needs_rex()) {
9465 prefix(REX_X);
9466 }
9467 }
9468 } else {
9469 if (adr.base_needs_rex()) {
9470 if (adr.index_needs_rex()) {
9471 prefix(REX_RXB);
9472 } else {
9473 prefix(REX_RB);
9474 }
9475 } else {
9476 if (adr.index_needs_rex()) {
9477 prefix(REX_RX);
9478 } else {
9479 prefix(REX_R);
9480 }
9481 }
9482 }
9483 }
9484
9485 void Assembler::prefixq(Address adr, XMMRegister src) {
9486 if (src->encoding() < 8) {
9487 if (adr.base_needs_rex()) {
9488 if (adr.index_needs_rex()) {
9489 prefix(REX_WXB);
9490 } else {
9491 prefix(REX_WB);
9492 }
9493 } else {
9494 if (adr.index_needs_rex()) {
9495 prefix(REX_WX);
9496 } else {
9497 prefix(REX_W);
9498 }
9499 }
9500 } else {
9501 if (adr.base_needs_rex()) {
9502 if (adr.index_needs_rex()) {
9503 prefix(REX_WRXB);
9504 } else {
9505 prefix(REX_WRB);
9506 }
9507 } else {
9508 if (adr.index_needs_rex()) {
9509 prefix(REX_WRX);
9510 } else {
9511 prefix(REX_WR);
9512 }
9513 }
9514 }
9515 }
9516
9517 void Assembler::adcq(Register dst, int32_t imm32) {
9518 (void) prefixq_and_encode(dst->encoding());
9519 emit_arith(0x81, 0xD0, dst, imm32);
9520 }
9521
9522 void Assembler::adcq(Register dst, Address src) {
9523 InstructionMark im(this);
9524 prefixq(src, dst);
9525 emit_int8(0x13);
9526 emit_operand(dst, src);
9527 }
9528
9529 void Assembler::adcq(Register dst, Register src) {
9530 (void) prefixq_and_encode(dst->encoding(), src->encoding());
9531 emit_arith(0x13, 0xC0, dst, src);
9532 }
9533
9534 void Assembler::addq(Address dst, int32_t imm32) {
9535 InstructionMark im(this);
9536 prefixq(dst);
9537 emit_arith_operand(0x81, rax, dst,imm32);
9538 }
9539
9540 void Assembler::addq(Address dst, Register src) {
9541 InstructionMark im(this);
9542 prefixq(dst, src);
9543 emit_int8(0x01);
9544 emit_operand(src, dst);
9545 }
9546
9547 void Assembler::addq(Register dst, int32_t imm32) {
9548 (void) prefixq_and_encode(dst->encoding());
9549 emit_arith(0x81, 0xC0, dst, imm32);
9550 }
9551
9552 void Assembler::addq(Register dst, Address src) {
9553 InstructionMark im(this);
9554 prefixq(src, dst);
9555 emit_int8(0x03);
9556 emit_operand(dst, src);
9557 }
9558
9559 void Assembler::addq(Register dst, Register src) {
9560 (void) prefixq_and_encode(dst->encoding(), src->encoding());
9561 emit_arith(0x03, 0xC0, dst, src);
9562 }
9563
9564 void Assembler::adcxq(Register dst, Register src) {
9565 //assert(VM_Version::supports_adx(), "adx instructions not supported");
9566 emit_int8((unsigned char)0x66);
9567 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
9568 emit_int8(0x0F);
9569 emit_int8(0x38);
9570 emit_int8((unsigned char)0xF6);
9571 emit_int8((unsigned char)(0xC0 | encode));
9572 }
9573
9574 void Assembler::adoxq(Register dst, Register src) {
9575 //assert(VM_Version::supports_adx(), "adx instructions not supported");
9576 emit_int8((unsigned char)0xF3);
9577 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
9578 emit_int8(0x0F);
9579 emit_int8(0x38);
9580 emit_int8((unsigned char)0xF6);
9581 emit_int8((unsigned char)(0xC0 | encode));
9582 }
9583
9584 void Assembler::andq(Address dst, int32_t imm32) {
9585 InstructionMark im(this);
9586 prefixq(dst);
9587 emit_int8((unsigned char)0x81);
9588 emit_operand(rsp, dst, 4);
9589 emit_int32(imm32);
9590 }
9591
9592 void Assembler::andq(Register dst, int32_t imm32) {
9593 (void) prefixq_and_encode(dst->encoding());
9594 emit_arith(0x81, 0xE0, dst, imm32);
9595 }
9596
9597 void Assembler::andq(Register dst, Address src) {
9598 InstructionMark im(this);
9599 prefixq(src, dst);
9600 emit_int8(0x23);
9601 emit_operand(dst, src);
9602 }
9603
9604 void Assembler::andq(Register dst, Register src) {
9605 (void) prefixq_and_encode(dst->encoding(), src->encoding());
9606 emit_arith(0x23, 0xC0, dst, src);
9607 }
9608
9609 void Assembler::andnq(Register dst, Register src1, Register src2) {
9610 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
9611 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
9612 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
9613 emit_int8((unsigned char)0xF2);
9614 emit_int8((unsigned char)(0xC0 | encode));
9615 }
9616
9617 void Assembler::andnq(Register dst, Register src1, Address src2) {
9618 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
9619 InstructionMark im(this);
9620 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
9621 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
9622 emit_int8((unsigned char)0xF2);
9623 emit_operand(dst, src2);
9624 }
9625
9626 void Assembler::bsfq(Register dst, Register src) {
9627 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
9628 emit_int8(0x0F);
9629 emit_int8((unsigned char)0xBC);
9630 emit_int8((unsigned char)(0xC0 | encode));
9631 }
9632
9633 void Assembler::bsrq(Register dst, Register src) {
9634 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
9635 emit_int8(0x0F);
9636 emit_int8((unsigned char)0xBD);
9637 emit_int8((unsigned char)(0xC0 | encode));
9638 }
9639
9640 void Assembler::bswapq(Register reg) {
9641 int encode = prefixq_and_encode(reg->encoding());
9642 emit_int8(0x0F);
9643 emit_int8((unsigned char)(0xC8 | encode));
9644 }
9645
9646 void Assembler::blsiq(Register dst, Register src) {
9647 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
9648 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
9649 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
9650 emit_int8((unsigned char)0xF3);
9651 emit_int8((unsigned char)(0xC0 | encode));
9652 }
9653
9654 void Assembler::blsiq(Register dst, Address src) {
9655 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
9656 InstructionMark im(this);
9657 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
9658 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
9659 emit_int8((unsigned char)0xF3);
9660 emit_operand(rbx, src);
9661 }
9662
9663 void Assembler::blsmskq(Register dst, Register src) {
9664 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
9665 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
9666 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
9667 emit_int8((unsigned char)0xF3);
9668 emit_int8((unsigned char)(0xC0 | encode));
9669 }
9670
9671 void Assembler::blsmskq(Register dst, Address src) {
9672 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
9673 InstructionMark im(this);
9674 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
9675 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
9676 emit_int8((unsigned char)0xF3);
9677 emit_operand(rdx, src);
9678 }
9679
9680 void Assembler::blsrq(Register dst, Register src) {
9681 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
9682 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
9683 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
9684 emit_int8((unsigned char)0xF3);
9685 emit_int8((unsigned char)(0xC0 | encode));
9686 }
9687
9688 void Assembler::blsrq(Register dst, Address src) {
9689 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
9690 InstructionMark im(this);
9691 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
9692 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
9693 emit_int8((unsigned char)0xF3);
9694 emit_operand(rcx, src);
9695 }
9696
9697 void Assembler::cdqq() {
9698 prefix(REX_W);
9699 emit_int8((unsigned char)0x99);
9700 }
9701
9702 void Assembler::clflush(Address adr) {
9703 prefix(adr);
9704 emit_int8(0x0F);
9705 emit_int8((unsigned char)0xAE);
9706 emit_operand(rdi, adr);
9707 }
9708
9709 void Assembler::cmovq(Condition cc, Register dst, Register src) {
9710 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
9711 emit_int8(0x0F);
9712 emit_int8(0x40 | cc);
9713 emit_int8((unsigned char)(0xC0 | encode));
9714 }
9715
9716 void Assembler::cmovq(Condition cc, Register dst, Address src) {
9717 InstructionMark im(this);
9718 prefixq(src, dst);
9719 emit_int8(0x0F);
9720 emit_int8(0x40 | cc);
9721 emit_operand(dst, src);
9722 }
9723
9724 void Assembler::cmpq(Address dst, int32_t imm32) {
9725 InstructionMark im(this);
9726 prefixq(dst);
9727 emit_int8((unsigned char)0x81);
9728 emit_operand(rdi, dst, 4);
9729 emit_int32(imm32);
9730 }
9731
9732 void Assembler::cmpq(Register dst, int32_t imm32) {
9733 (void) prefixq_and_encode(dst->encoding());
9734 emit_arith(0x81, 0xF8, dst, imm32);
9735 }
9736
9737 void Assembler::cmpq(Address dst, Register src) {
9738 InstructionMark im(this);
9739 prefixq(dst, src);
9740 emit_int8(0x3B);
9741 emit_operand(src, dst);
9742 }
9743
9744 void Assembler::cmpq(Register dst, Register src) {
9745 (void) prefixq_and_encode(dst->encoding(), src->encoding());
9746 emit_arith(0x3B, 0xC0, dst, src);
9747 }
9748
9749 void Assembler::cmpq(Register dst, Address src) {
9750 InstructionMark im(this);
9751 prefixq(src, dst);
9752 emit_int8(0x3B);
9753 emit_operand(dst, src);
9754 }
9755
9756 void Assembler::cmpxchgq(Register reg, Address adr) {
9757 InstructionMark im(this);
9758 prefixq(adr, reg);
9759 emit_int8(0x0F);
9760 emit_int8((unsigned char)0xB1);
9761 emit_operand(reg, adr);
9762 }
9763
9764 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
9765 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
9766 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
9767 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
9768 emit_int8(0x2A);
9769 emit_int8((unsigned char)(0xC0 | encode));
9770 }
9771
9772 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) {
9773 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
9774 InstructionMark im(this);
9775 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
9776 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
9777 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
9778 emit_int8(0x2A);
9779 emit_operand(dst, src);
9780 }
9781
9782 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) {
9783 NOT_LP64(assert(VM_Version::supports_sse(), ""));
9784 InstructionMark im(this);
9785 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
9786 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
9787 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
9788 emit_int8(0x2A);
9789 emit_operand(dst, src);
9790 }
9791
9792 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
9793 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
9794 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
9795 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
9796 emit_int8(0x2C);
9797 emit_int8((unsigned char)(0xC0 | encode));
9798 }
9799
9800 void Assembler::cvttss2siq(Register dst, XMMRegister src) {
9801 NOT_LP64(assert(VM_Version::supports_sse(), ""));
9802 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
9803 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
9804 emit_int8(0x2C);
9805 emit_int8((unsigned char)(0xC0 | encode));
9806 }
9807
9808 void Assembler::decl(Register dst) {
9809 // Don't use it directly. Use MacroAssembler::decrementl() instead.
9810 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
9811 int encode = prefix_and_encode(dst->encoding());
9812 emit_int8((unsigned char)0xFF);
9813 emit_int8((unsigned char)(0xC8 | encode));
9814 }
9815
9816 void Assembler::decq(Register dst) {
9817 // Don't use it directly. Use MacroAssembler::decrementq() instead.
9818 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
9819 int encode = prefixq_and_encode(dst->encoding());
9820 emit_int8((unsigned char)0xFF);
9821 emit_int8(0xC8 | encode);
9822 }
9823
9824 void Assembler::decq(Address dst) {
9825 // Don't use it directly. Use MacroAssembler::decrementq() instead.
9826 InstructionMark im(this);
9827 prefixq(dst);
9828 emit_int8((unsigned char)0xFF);
9829 emit_operand(rcx, dst);
9830 }
9831
9832 void Assembler::fxrstor(Address src) {
9833 prefixq(src);
9834 emit_int8(0x0F);
9835 emit_int8((unsigned char)0xAE);
9836 emit_operand(as_Register(1), src);
9837 }
9838
9839 void Assembler::xrstor(Address src) {
9840 prefixq(src);
9841 emit_int8(0x0F);
9842 emit_int8((unsigned char)0xAE);
9843 emit_operand(as_Register(5), src);
9844 }
9845
9846 void Assembler::fxsave(Address dst) {
9847 prefixq(dst);
9848 emit_int8(0x0F);
9849 emit_int8((unsigned char)0xAE);
9850 emit_operand(as_Register(0), dst);
9851 }
9852
9853 void Assembler::xsave(Address dst) {
9854 prefixq(dst);
9855 emit_int8(0x0F);
9856 emit_int8((unsigned char)0xAE);
9857 emit_operand(as_Register(4), dst);
9858 }
9859
9860 void Assembler::idivq(Register src) {
9861 int encode = prefixq_and_encode(src->encoding());
9862 emit_int8((unsigned char)0xF7);
9863 emit_int8((unsigned char)(0xF8 | encode));
9864 }
9865
9866 void Assembler::imulq(Register dst, Register src) {
9867 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
9868 emit_int8(0x0F);
9869 emit_int8((unsigned char)0xAF);
9870 emit_int8((unsigned char)(0xC0 | encode));
9871 }
9872
9873 void Assembler::imulq(Register dst, Register src, int value) {
9874 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
9875 if (is8bit(value)) {
9876 emit_int8(0x6B);
9877 emit_int8((unsigned char)(0xC0 | encode));
9878 emit_int8(value & 0xFF);
9879 } else {
9880 emit_int8(0x69);
9881 emit_int8((unsigned char)(0xC0 | encode));
9882 emit_int32(value);
9883 }
9884 }
9885
9886 void Assembler::imulq(Register dst, Address src) {
9887 InstructionMark im(this);
9888 prefixq(src, dst);
9889 emit_int8(0x0F);
9890 emit_int8((unsigned char) 0xAF);
9891 emit_operand(dst, src);
9892 }
9893
9894 void Assembler::incl(Register dst) {
9895 // Don't use it directly. Use MacroAssembler::incrementl() instead.
9896 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
9897 int encode = prefix_and_encode(dst->encoding());
9898 emit_int8((unsigned char)0xFF);
9899 emit_int8((unsigned char)(0xC0 | encode));
9900 }
9901
9902 void Assembler::incq(Register dst) {
9903 // Don't use it directly. Use MacroAssembler::incrementq() instead.
9904 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
9905 int encode = prefixq_and_encode(dst->encoding());
9906 emit_int8((unsigned char)0xFF);
9907 emit_int8((unsigned char)(0xC0 | encode));
9908 }
9909
9910 void Assembler::incq(Address dst) {
9911 // Don't use it directly. Use MacroAssembler::incrementq() instead.
9912 InstructionMark im(this);
9913 prefixq(dst);
9914 emit_int8((unsigned char)0xFF);
9915 emit_operand(rax, dst);
9916 }
9917
9918 void Assembler::lea(Register dst, Address src) {
9919 leaq(dst, src);
9920 }
9921
9922 void Assembler::leaq(Register dst, Address src) {
9923 InstructionMark im(this);
9924 prefixq(src, dst);
9925 emit_int8((unsigned char)0x8D);
9926 emit_operand(dst, src);
9927 }
9928
9929 void Assembler::mov64(Register dst, int64_t imm64) {
9930 InstructionMark im(this);
9931 int encode = prefixq_and_encode(dst->encoding());
9932 emit_int8((unsigned char)(0xB8 | encode));
9933 emit_int64(imm64);
9934 }
9935
9936 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) {
9937 InstructionMark im(this);
9938 int encode = prefixq_and_encode(dst->encoding());
9939 emit_int8(0xB8 | encode);
9940 emit_data64(imm64, rspec);
9941 }
9942
9943 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) {
9944 InstructionMark im(this);
9945 int encode = prefix_and_encode(dst->encoding());
9946 emit_int8((unsigned char)(0xB8 | encode));
9947 emit_data((int)imm32, rspec, narrow_oop_operand);
9948 }
9949
9950 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) {
9951 InstructionMark im(this);
9952 prefix(dst);
9953 emit_int8((unsigned char)0xC7);
9954 emit_operand(rax, dst, 4);
9955 emit_data((int)imm32, rspec, narrow_oop_operand);
9956 }
9957
9958 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) {
9959 InstructionMark im(this);
9960 int encode = prefix_and_encode(src1->encoding());
9961 emit_int8((unsigned char)0x81);
9962 emit_int8((unsigned char)(0xF8 | encode));
9963 emit_data((int)imm32, rspec, narrow_oop_operand);
9964 }
9965
9966 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) {
9967 InstructionMark im(this);
9968 prefix(src1);
9969 emit_int8((unsigned char)0x81);
9970 emit_operand(rax, src1, 4);
9971 emit_data((int)imm32, rspec, narrow_oop_operand);
9972 }
9973
9974 void Assembler::lzcntq(Register dst, Register src) {
9975 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
9976 emit_int8((unsigned char)0xF3);
9977 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
9978 emit_int8(0x0F);
9979 emit_int8((unsigned char)0xBD);
9980 emit_int8((unsigned char)(0xC0 | encode));
9981 }
9982
9983 void Assembler::movdq(XMMRegister dst, Register src) {
9984 // table D-1 says MMX/SSE2
9985 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
9986 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
9987 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9988 emit_int8(0x6E);
9989 emit_int8((unsigned char)(0xC0 | encode));
9990 }
9991
9992 void Assembler::movdq(Register dst, XMMRegister src) {
9993 // table D-1 says MMX/SSE2
9994 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
9995 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
9996 // swap src/dst to get correct prefix
9997 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9998 emit_int8(0x7E);
9999 emit_int8((unsigned char)(0xC0 | encode));
10000 }
10001
10002 void Assembler::movq(Register dst, Register src) {
10003 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
10004 emit_int8((unsigned char)0x8B);
10005 emit_int8((unsigned char)(0xC0 | encode));
10006 }
10007
10008 void Assembler::movq(Register dst, Address src) {
10009 InstructionMark im(this);
10010 prefixq(src, dst);
10011 emit_int8((unsigned char)0x8B);
10012 emit_operand(dst, src);
10013 }
10014
10015 void Assembler::movq(Address dst, Register src) {
10016 InstructionMark im(this);
10017 prefixq(dst, src);
10018 emit_int8((unsigned char)0x89);
10019 emit_operand(src, dst);
10020 }
10021
10022 void Assembler::movsbq(Register dst, Address src) {
10023 InstructionMark im(this);
10024 prefixq(src, dst);
10025 emit_int8(0x0F);
10026 emit_int8((unsigned char)0xBE);
10027 emit_operand(dst, src);
10028 }
10029
10030 void Assembler::movsbq(Register dst, Register src) {
10031 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
10032 emit_int8(0x0F);
10033 emit_int8((unsigned char)0xBE);
10034 emit_int8((unsigned char)(0xC0 | encode));
10035 }
10036
10037 void Assembler::movslq(Register dst, int32_t imm32) {
10038 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx)
10039 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx)
10040 // as a result we shouldn't use until tested at runtime...
10041 ShouldNotReachHere();
10042 InstructionMark im(this);
10043 int encode = prefixq_and_encode(dst->encoding());
10044 emit_int8((unsigned char)(0xC7 | encode));
10045 emit_int32(imm32);
10046 }
10047
10048 void Assembler::movslq(Address dst, int32_t imm32) {
10049 assert(is_simm32(imm32), "lost bits");
10050 InstructionMark im(this);
10051 prefixq(dst);
10052 emit_int8((unsigned char)0xC7);
10053 emit_operand(rax, dst, 4);
10054 emit_int32(imm32);
10055 }
10056
10057 void Assembler::movslq(Register dst, Address src) {
10058 InstructionMark im(this);
10059 prefixq(src, dst);
10060 emit_int8(0x63);
10061 emit_operand(dst, src);
10062 }
10063
10064 void Assembler::movslq(Register dst, Register src) {
10065 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
10066 emit_int8(0x63);
10067 emit_int8((unsigned char)(0xC0 | encode));
10068 }
10069
10070 void Assembler::movswq(Register dst, Address src) {
10071 InstructionMark im(this);
10072 prefixq(src, dst);
10073 emit_int8(0x0F);
10074 emit_int8((unsigned char)0xBF);
10075 emit_operand(dst, src);
10076 }
10077
10078 void Assembler::movswq(Register dst, Register src) {
10079 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
10080 emit_int8((unsigned char)0x0F);
10081 emit_int8((unsigned char)0xBF);
10082 emit_int8((unsigned char)(0xC0 | encode));
10083 }
10084
10085 void Assembler::movzbq(Register dst, Address src) {
10086 InstructionMark im(this);
10087 prefixq(src, dst);
10088 emit_int8((unsigned char)0x0F);
10089 emit_int8((unsigned char)0xB6);
10090 emit_operand(dst, src);
10091 }
10092
10093 void Assembler::movzbq(Register dst, Register src) {
10094 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
10095 emit_int8(0x0F);
10096 emit_int8((unsigned char)0xB6);
10097 emit_int8(0xC0 | encode);
10098 }
10099
10100 void Assembler::movzwq(Register dst, Address src) {
10101 InstructionMark im(this);
10102 prefixq(src, dst);
10103 emit_int8((unsigned char)0x0F);
10104 emit_int8((unsigned char)0xB7);
10105 emit_operand(dst, src);
10106 }
10107
10108 void Assembler::movzwq(Register dst, Register src) {
10109 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
10110 emit_int8((unsigned char)0x0F);
10111 emit_int8((unsigned char)0xB7);
10112 emit_int8((unsigned char)(0xC0 | encode));
10113 }
10114
10115 void Assembler::mulq(Address src) {
10116 InstructionMark im(this);
10117 prefixq(src);
10118 emit_int8((unsigned char)0xF7);
10119 emit_operand(rsp, src);
10120 }
10121
10122 void Assembler::mulq(Register src) {
10123 int encode = prefixq_and_encode(src->encoding());
10124 emit_int8((unsigned char)0xF7);
10125 emit_int8((unsigned char)(0xE0 | encode));
10126 }
10127
10128 void Assembler::mulxq(Register dst1, Register dst2, Register src) {
10129 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
10130 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
10131 int encode = vex_prefix_and_encode(dst1->encoding(), dst2->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
10132 emit_int8((unsigned char)0xF6);
10133 emit_int8((unsigned char)(0xC0 | encode));
10134 }
10135
10136 void Assembler::negq(Register dst) {
10137 int encode = prefixq_and_encode(dst->encoding());
10138 emit_int8((unsigned char)0xF7);
10139 emit_int8((unsigned char)(0xD8 | encode));
10140 }
10141
10142 void Assembler::notq(Register dst) {
10143 int encode = prefixq_and_encode(dst->encoding());
10144 emit_int8((unsigned char)0xF7);
10145 emit_int8((unsigned char)(0xD0 | encode));
10146 }
10147
10148 void Assembler::orq(Address dst, int32_t imm32) {
10149 InstructionMark im(this);
10150 prefixq(dst);
10151 emit_int8((unsigned char)0x81);
10152 emit_operand(rcx, dst, 4);
10153 emit_int32(imm32);
10154 }
10155
10156 void Assembler::orq(Register dst, int32_t imm32) {
10157 (void) prefixq_and_encode(dst->encoding());
10158 emit_arith(0x81, 0xC8, dst, imm32);
10159 }
10160
10161 void Assembler::orq(Register dst, Address src) {
10162 InstructionMark im(this);
10163 prefixq(src, dst);
10164 emit_int8(0x0B);
10165 emit_operand(dst, src);
10166 }
10167
10168 void Assembler::orq(Register dst, Register src) {
10169 (void) prefixq_and_encode(dst->encoding(), src->encoding());
10170 emit_arith(0x0B, 0xC0, dst, src);
10171 }
10172
10173 void Assembler::popa() { // 64bit
10174 movq(r15, Address(rsp, 0));
10175 movq(r14, Address(rsp, wordSize));
10176 movq(r13, Address(rsp, 2 * wordSize));
10177 movq(r12, Address(rsp, 3 * wordSize));
10178 movq(r11, Address(rsp, 4 * wordSize));
10179 movq(r10, Address(rsp, 5 * wordSize));
10180 movq(r9, Address(rsp, 6 * wordSize));
10181 movq(r8, Address(rsp, 7 * wordSize));
10182 movq(rdi, Address(rsp, 8 * wordSize));
10183 movq(rsi, Address(rsp, 9 * wordSize));
10184 movq(rbp, Address(rsp, 10 * wordSize));
10185 // skip rsp
10186 movq(rbx, Address(rsp, 12 * wordSize));
10187 movq(rdx, Address(rsp, 13 * wordSize));
10188 movq(rcx, Address(rsp, 14 * wordSize));
10189 movq(rax, Address(rsp, 15 * wordSize));
10190
10191 addq(rsp, 16 * wordSize);
10192 }
10193
10194 void Assembler::popcntq(Register dst, Address src) {
10195 assert(VM_Version::supports_popcnt(), "must support");
10196 InstructionMark im(this);
10197 emit_int8((unsigned char)0xF3);
10198 prefixq(src, dst);
10199 emit_int8((unsigned char)0x0F);
10200 emit_int8((unsigned char)0xB8);
10201 emit_operand(dst, src);
10202 }
10203
10204 void Assembler::popcntq(Register dst, Register src) {
10205 assert(VM_Version::supports_popcnt(), "must support");
10206 emit_int8((unsigned char)0xF3);
10207 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
10208 emit_int8((unsigned char)0x0F);
10209 emit_int8((unsigned char)0xB8);
10210 emit_int8((unsigned char)(0xC0 | encode));
10211 }
10212
10213 void Assembler::popq(Address dst) {
10214 InstructionMark im(this);
10215 prefixq(dst);
10216 emit_int8((unsigned char)0x8F);
10217 emit_operand(rax, dst);
10218 }
10219
10220 void Assembler::pusha() { // 64bit
10221 // we have to store original rsp. ABI says that 128 bytes
10222 // below rsp are local scratch.
10223 movq(Address(rsp, -5 * wordSize), rsp);
10224
10225 subq(rsp, 16 * wordSize);
10226
10227 movq(Address(rsp, 15 * wordSize), rax);
10228 movq(Address(rsp, 14 * wordSize), rcx);
10229 movq(Address(rsp, 13 * wordSize), rdx);
10230 movq(Address(rsp, 12 * wordSize), rbx);
10231 // skip rsp
10232 movq(Address(rsp, 10 * wordSize), rbp);
10233 movq(Address(rsp, 9 * wordSize), rsi);
10234 movq(Address(rsp, 8 * wordSize), rdi);
10235 movq(Address(rsp, 7 * wordSize), r8);
10236 movq(Address(rsp, 6 * wordSize), r9);
10237 movq(Address(rsp, 5 * wordSize), r10);
10238 movq(Address(rsp, 4 * wordSize), r11);
10239 movq(Address(rsp, 3 * wordSize), r12);
10240 movq(Address(rsp, 2 * wordSize), r13);
10241 movq(Address(rsp, wordSize), r14);
10242 movq(Address(rsp, 0), r15);
10243 }
10244
10245 void Assembler::pushq(Address src) {
10246 InstructionMark im(this);
10247 prefixq(src);
10248 emit_int8((unsigned char)0xFF);
10249 emit_operand(rsi, src);
10250 }
10251
10252 void Assembler::rclq(Register dst, int imm8) {
10253 assert(isShiftCount(imm8 >> 1), "illegal shift count");
10254 int encode = prefixq_and_encode(dst->encoding());
10255 if (imm8 == 1) {
10256 emit_int8((unsigned char)0xD1);
10257 emit_int8((unsigned char)(0xD0 | encode));
10258 } else {
10259 emit_int8((unsigned char)0xC1);
10260 emit_int8((unsigned char)(0xD0 | encode));
10261 emit_int8(imm8);
10262 }
10263 }
10264
10265 void Assembler::rcrq(Register dst, int imm8) {
10266 assert(isShiftCount(imm8 >> 1), "illegal shift count");
10267 int encode = prefixq_and_encode(dst->encoding());
10268 if (imm8 == 1) {
10269 emit_int8((unsigned char)0xD1);
10270 emit_int8((unsigned char)(0xD8 | encode));
10271 } else {
10272 emit_int8((unsigned char)0xC1);
10273 emit_int8((unsigned char)(0xD8 | encode));
10274 emit_int8(imm8);
10275 }
10276 }
10277
10278 void Assembler::rorq(Register dst, int imm8) {
10279 assert(isShiftCount(imm8 >> 1), "illegal shift count");
10280 int encode = prefixq_and_encode(dst->encoding());
10281 if (imm8 == 1) {
10282 emit_int8((unsigned char)0xD1);
10283 emit_int8((unsigned char)(0xC8 | encode));
10284 } else {
10285 emit_int8((unsigned char)0xC1);
10286 emit_int8((unsigned char)(0xc8 | encode));
10287 emit_int8(imm8);
10288 }
10289 }
10290
10291 void Assembler::rorxq(Register dst, Register src, int imm8) {
10292 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
10293 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
10294 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes);
10295 emit_int8((unsigned char)0xF0);
10296 emit_int8((unsigned char)(0xC0 | encode));
10297 emit_int8(imm8);
10298 }
10299
10300 void Assembler::rorxd(Register dst, Register src, int imm8) {
10301 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
10302 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
10303 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes);
10304 emit_int8((unsigned char)0xF0);
10305 emit_int8((unsigned char)(0xC0 | encode));
10306 emit_int8(imm8);
10307 }
10308
10309 void Assembler::sarq(Register dst, int imm8) {
10310 assert(isShiftCount(imm8 >> 1), "illegal shift count");
10311 int encode = prefixq_and_encode(dst->encoding());
10312 if (imm8 == 1) {
10313 emit_int8((unsigned char)0xD1);
10314 emit_int8((unsigned char)(0xF8 | encode));
10315 } else {
10316 emit_int8((unsigned char)0xC1);
10317 emit_int8((unsigned char)(0xF8 | encode));
10318 emit_int8(imm8);
10319 }
10320 }
10321
10322 void Assembler::sarq(Register dst) {
10323 int encode = prefixq_and_encode(dst->encoding());
10324 emit_int8((unsigned char)0xD3);
10325 emit_int8((unsigned char)(0xF8 | encode));
10326 }
10327
10328 void Assembler::sbbq(Address dst, int32_t imm32) {
10329 InstructionMark im(this);
10330 prefixq(dst);
10331 emit_arith_operand(0x81, rbx, dst, imm32);
10332 }
10333
10334 void Assembler::sbbq(Register dst, int32_t imm32) {
10335 (void) prefixq_and_encode(dst->encoding());
10336 emit_arith(0x81, 0xD8, dst, imm32);
10337 }
10338
10339 void Assembler::sbbq(Register dst, Address src) {
10340 InstructionMark im(this);
10341 prefixq(src, dst);
10342 emit_int8(0x1B);
10343 emit_operand(dst, src);
10344 }
10345
10346 void Assembler::sbbq(Register dst, Register src) {
10347 (void) prefixq_and_encode(dst->encoding(), src->encoding());
10348 emit_arith(0x1B, 0xC0, dst, src);
10349 }
10350
10351 void Assembler::shlq(Register dst, int imm8) {
10352 assert(isShiftCount(imm8 >> 1), "illegal shift count");
10353 int encode = prefixq_and_encode(dst->encoding());
10354 if (imm8 == 1) {
10355 emit_int8((unsigned char)0xD1);
10356 emit_int8((unsigned char)(0xE0 | encode));
10357 } else {
10358 emit_int8((unsigned char)0xC1);
10359 emit_int8((unsigned char)(0xE0 | encode));
10360 emit_int8(imm8);
10361 }
10362 }
10363
10364 void Assembler::shlq(Register dst) {
10365 int encode = prefixq_and_encode(dst->encoding());
10366 emit_int8((unsigned char)0xD3);
10367 emit_int8((unsigned char)(0xE0 | encode));
10368 }
10369
10370 void Assembler::shrq(Register dst, int imm8) {
10371 assert(isShiftCount(imm8 >> 1), "illegal shift count");
10372 int encode = prefixq_and_encode(dst->encoding());
10373 emit_int8((unsigned char)0xC1);
10374 emit_int8((unsigned char)(0xE8 | encode));
10375 emit_int8(imm8);
10376 }
10377
10378 void Assembler::shrq(Register dst) {
10379 int encode = prefixq_and_encode(dst->encoding());
10380 emit_int8((unsigned char)0xD3);
10381 emit_int8(0xE8 | encode);
10382 }
10383
10384 void Assembler::subq(Address dst, int32_t imm32) {
10385 InstructionMark im(this);
10386 prefixq(dst);
10387 emit_arith_operand(0x81, rbp, dst, imm32);
10388 }
10389
10390 void Assembler::subq(Address dst, Register src) {
10391 InstructionMark im(this);
10392 prefixq(dst, src);
10393 emit_int8(0x29);
10394 emit_operand(src, dst);
10395 }
10396
10397 void Assembler::subq(Register dst, int32_t imm32) {
10398 (void) prefixq_and_encode(dst->encoding());
10399 emit_arith(0x81, 0xE8, dst, imm32);
10400 }
10401
10402 // Force generation of a 4 byte immediate value even if it fits into 8bit
10403 void Assembler::subq_imm32(Register dst, int32_t imm32) {
10404 (void) prefixq_and_encode(dst->encoding());
10405 emit_arith_imm32(0x81, 0xE8, dst, imm32);
10406 }
10407
10408 void Assembler::subq(Register dst, Address src) {
10409 InstructionMark im(this);
10410 prefixq(src, dst);
10411 emit_int8(0x2B);
10412 emit_operand(dst, src);
10413 }
10414
10415 void Assembler::subq(Register dst, Register src) {
10416 (void) prefixq_and_encode(dst->encoding(), src->encoding());
10417 emit_arith(0x2B, 0xC0, dst, src);
10418 }
10419
10420 void Assembler::testq(Register dst, int32_t imm32) {
10421 // not using emit_arith because test
10422 // doesn't support sign-extension of
10423 // 8bit operands
10424 int encode = dst->encoding();
10425 if (encode == 0) {
10426 prefix(REX_W);
10427 emit_int8((unsigned char)0xA9);
10428 } else {
10429 encode = prefixq_and_encode(encode);
10430 emit_int8((unsigned char)0xF7);
10431 emit_int8((unsigned char)(0xC0 | encode));
10432 }
10433 emit_int32(imm32);
10434 }
10435
10436 void Assembler::testq(Register dst, Register src) {
10437 (void) prefixq_and_encode(dst->encoding(), src->encoding());
10438 emit_arith(0x85, 0xC0, dst, src);
10439 }
10440
10441 void Assembler::testq(Register dst, Address src) {
10442 InstructionMark im(this);
10443 prefixq(src, dst);
10444 emit_int8((unsigned char)0x85);
10445 emit_operand(dst, src);
10446 }
10447
10448 void Assembler::xaddq(Address dst, Register src) {
10449 InstructionMark im(this);
10450 prefixq(dst, src);
10451 emit_int8(0x0F);
10452 emit_int8((unsigned char)0xC1);
10453 emit_operand(src, dst);
10454 }
10455
10456 void Assembler::xchgq(Register dst, Address src) {
10457 InstructionMark im(this);
10458 prefixq(src, dst);
10459 emit_int8((unsigned char)0x87);
10460 emit_operand(dst, src);
10461 }
10462
10463 void Assembler::xchgq(Register dst, Register src) {
10464 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
10465 emit_int8((unsigned char)0x87);
10466 emit_int8((unsigned char)(0xc0 | encode));
10467 }
10468
10469 void Assembler::xorq(Register dst, Register src) {
10470 (void) prefixq_and_encode(dst->encoding(), src->encoding());
10471 emit_arith(0x33, 0xC0, dst, src);
10472 }
10473
10474 void Assembler::xorq(Register dst, Address src) {
10475 InstructionMark im(this);
10476 prefixq(src, dst);
10477 emit_int8(0x33);
10478 emit_operand(dst, src);
10479 }
10480
10481 #endif // !LP64