3729 }
3730
3731 void Assembler::vpackusdw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3732 assert(UseAVX > 0, "some form of AVX must be enabled");
3733 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3734 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3735 emit_int8(0x2B);
3736 emit_int8((unsigned char)(0xC0 | encode));
3737 }
3738
3739 void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len) {
3740 assert(VM_Version::supports_avx2(), "");
3741 // VEX.256.66.0F3A.W1 00 /r ib
3742 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3743 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3744 emit_int8(0x00);
3745 emit_int8(0xC0 | encode);
3746 emit_int8(imm8);
3747 }
3748
3749 void Assembler::vpermd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3750 assert(VM_Version::supports_avx2(), "");
3751 // VEX.NDS.256.66.0F38.W0 36 /r
3752 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3753 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3754 emit_int8(0x36);
3755 emit_int8(0xC0 | encode);
3756 }
3757
3758 void Assembler::vpermd(XMMRegister dst, XMMRegister nds, Address src) {
3759 assert(VM_Version::supports_avx2(), "");
3760 // VEX.NDS.256.66.0F38.W0 36 /r
3761 InstructionMark im(this);
3762 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3763 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3764 emit_int8(0x36);
3765 emit_operand(dst, src);
3766 }
3767
3768 void Assembler::vperm2i128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) {
3769 assert(VM_Version::supports_avx2(), "");
3770 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3771 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3772 emit_int8(0x46);
3773 emit_int8(0xC0 | encode);
3774 emit_int8(imm8);
3775 }
3776
3777 void Assembler::vperm2f128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) {
3778 assert(VM_Version::supports_avx(), "");
3779 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3780 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3781 emit_int8(0x06);
3782 emit_int8(0xC0 | encode);
3783 emit_int8(imm8);
3784 }
3785
|
3729 }
3730
3731 void Assembler::vpackusdw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3732 assert(UseAVX > 0, "some form of AVX must be enabled");
3733 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3734 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3735 emit_int8(0x2B);
3736 emit_int8((unsigned char)(0xC0 | encode));
3737 }
3738
3739 void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len) {
3740 assert(VM_Version::supports_avx2(), "");
3741 // VEX.256.66.0F3A.W1 00 /r ib
3742 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3743 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3744 emit_int8(0x00);
3745 emit_int8(0xC0 | encode);
3746 emit_int8(imm8);
3747 }
3748
3749 void Assembler::vpermb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3750 assert(VM_Version::supports_avx512vbmi(), "");
3751 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3752 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3753 emit_int8((unsigned char)0x8D);
3754 emit_int8((unsigned char)(0xC0 | encode));
3755 }
3756
3757 void Assembler::vpermw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
3758 assert(VM_Version::supports_avx512vlbw(), "");
3759 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3760 attributes.set_embedded_opmask_register_specifier(mask);
3761 attributes.set_is_evex_instruction();
3762 if (merge) {
3763 attributes.reset_is_clear_context();
3764 }
3765 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3766 emit_int8((unsigned char)0x8D);
3767 emit_int8((unsigned char)(0xC0 | encode));
3768 }
3769
3770 void Assembler::vpermd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3771 assert(VM_Version::supports_avx2(), "");
3772 // VEX.NDS.256.66.0F38.W0 36 /r
3773 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3774 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3775 emit_int8(0x36);
3776 emit_int8(0xC0 | encode);
3777 }
3778
3779 void Assembler::vpermd(XMMRegister dst, XMMRegister nds, Address src) {
3780 assert(VM_Version::supports_avx2(), "");
3781 // VEX.NDS.256.66.0F38.W0 36 /r
3782 InstructionMark im(this);
3783 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3784 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3785 emit_int8(0x36);
3786 emit_operand(dst, src);
3787 }
3788
3789 void Assembler::evpermd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3790 assert(VM_Version::supports_evex(), "");
3791 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3792 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3793 emit_int8(0x36);
3794 emit_int8((unsigned char)(0xC0 | encode));
3795 }
3796
3797 void Assembler::vperm2i128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) {
3798 assert(VM_Version::supports_avx2(), "");
3799 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3800 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3801 emit_int8(0x46);
3802 emit_int8(0xC0 | encode);
3803 emit_int8(imm8);
3804 }
3805
3806 void Assembler::vperm2f128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) {
3807 assert(VM_Version::supports_avx(), "");
3808 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3809 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3810 emit_int8(0x06);
3811 emit_int8(0xC0 | encode);
3812 emit_int8(imm8);
3813 }
3814
|