1 /*
   2  * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "jvm.h"
  27 #include "asm/macroAssembler.hpp"
  28 #include "asm/macroAssembler.inline.hpp"
  29 #include "logging/log.hpp"
  30 #include "logging/logStream.hpp"
  31 #include "memory/resourceArea.hpp"
  32 #include "runtime/java.hpp"
  33 #include "runtime/os.hpp"
  34 #include "runtime/stubCodeGenerator.hpp"
  35 #include "vm_version_x86.hpp"
  36 
  37 
  38 int VM_Version::_cpu;
  39 int VM_Version::_model;
  40 int VM_Version::_stepping;
  41 VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, };
  42 
  43 // Address of instruction which causes SEGV
  44 address VM_Version::_cpuinfo_segv_addr = 0;
  45 // Address of instruction after the one which causes SEGV
  46 address VM_Version::_cpuinfo_cont_addr = 0;
  47 
  48 static BufferBlob* stub_blob;
  49 static const int stub_size = 1100;
  50 
  51 extern "C" {
  52   typedef void (*get_cpu_info_stub_t)(void*);
  53 }
  54 static get_cpu_info_stub_t get_cpu_info_stub = NULL;
  55 
  56 
  57 class VM_Version_StubGenerator: public StubCodeGenerator {
  58  public:
  59 
  60   VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
  61 
  62   address generate_get_cpu_info() {
  63     // Flags to test CPU type.
  64     const uint32_t HS_EFL_AC = 0x40000;
  65     const uint32_t HS_EFL_ID = 0x200000;
  66     // Values for when we don't have a CPUID instruction.
  67     const int      CPU_FAMILY_SHIFT = 8;
  68     const uint32_t CPU_FAMILY_386 = (3 << CPU_FAMILY_SHIFT);
  69     const uint32_t CPU_FAMILY_486 = (4 << CPU_FAMILY_SHIFT);
  70     bool use_evex = FLAG_IS_DEFAULT(UseAVX) || (UseAVX > 2);
  71 
  72     Label detect_486, cpu486, detect_586, std_cpuid1, std_cpuid4;
  73     Label sef_cpuid, ext_cpuid, ext_cpuid1, ext_cpuid5, ext_cpuid7, ext_cpuid8, done, wrapup;
  74     Label legacy_setup, save_restore_except, legacy_save_restore, start_simd_check;
  75 
  76     StubCodeMark mark(this, "VM_Version", "get_cpu_info_stub");
  77 #   define __ _masm->
  78 
  79     address start = __ pc();
  80 
  81     //
  82     // void get_cpu_info(VM_Version::CpuidInfo* cpuid_info);
  83     //
  84     // LP64: rcx and rdx are first and second argument registers on windows
  85 
  86     __ push(rbp);
  87 #ifdef _LP64
  88     __ mov(rbp, c_rarg0); // cpuid_info address
  89 #else
  90     __ movptr(rbp, Address(rsp, 8)); // cpuid_info address
  91 #endif
  92     __ push(rbx);
  93     __ push(rsi);
  94     __ pushf();          // preserve rbx, and flags
  95     __ pop(rax);
  96     __ push(rax);
  97     __ mov(rcx, rax);
  98     //
  99     // if we are unable to change the AC flag, we have a 386
 100     //
 101     __ xorl(rax, HS_EFL_AC);
 102     __ push(rax);
 103     __ popf();
 104     __ pushf();
 105     __ pop(rax);
 106     __ cmpptr(rax, rcx);
 107     __ jccb(Assembler::notEqual, detect_486);
 108 
 109     __ movl(rax, CPU_FAMILY_386);
 110     __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
 111     __ jmp(done);
 112 
 113     //
 114     // If we are unable to change the ID flag, we have a 486 which does
 115     // not support the "cpuid" instruction.
 116     //
 117     __ bind(detect_486);
 118     __ mov(rax, rcx);
 119     __ xorl(rax, HS_EFL_ID);
 120     __ push(rax);
 121     __ popf();
 122     __ pushf();
 123     __ pop(rax);
 124     __ cmpptr(rcx, rax);
 125     __ jccb(Assembler::notEqual, detect_586);
 126 
 127     __ bind(cpu486);
 128     __ movl(rax, CPU_FAMILY_486);
 129     __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
 130     __ jmp(done);
 131 
 132     //
 133     // At this point, we have a chip which supports the "cpuid" instruction
 134     //
 135     __ bind(detect_586);
 136     __ xorl(rax, rax);
 137     __ cpuid();
 138     __ orl(rax, rax);
 139     __ jcc(Assembler::equal, cpu486);   // if cpuid doesn't support an input
 140                                         // value of at least 1, we give up and
 141                                         // assume a 486
 142     __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));
 143     __ movl(Address(rsi, 0), rax);
 144     __ movl(Address(rsi, 4), rbx);
 145     __ movl(Address(rsi, 8), rcx);
 146     __ movl(Address(rsi,12), rdx);
 147 
 148     __ cmpl(rax, 0xa);                  // Is cpuid(0xB) supported?
 149     __ jccb(Assembler::belowEqual, std_cpuid4);
 150 
 151     //
 152     // cpuid(0xB) Processor Topology
 153     //
 154     __ movl(rax, 0xb);
 155     __ xorl(rcx, rcx);   // Threads level
 156     __ cpuid();
 157 
 158     __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB0_offset())));
 159     __ movl(Address(rsi, 0), rax);
 160     __ movl(Address(rsi, 4), rbx);
 161     __ movl(Address(rsi, 8), rcx);
 162     __ movl(Address(rsi,12), rdx);
 163 
 164     __ movl(rax, 0xb);
 165     __ movl(rcx, 1);     // Cores level
 166     __ cpuid();
 167     __ push(rax);
 168     __ andl(rax, 0x1f);  // Determine if valid topology level
 169     __ orl(rax, rbx);    // eax[4:0] | ebx[0:15] == 0 indicates invalid level
 170     __ andl(rax, 0xffff);
 171     __ pop(rax);
 172     __ jccb(Assembler::equal, std_cpuid4);
 173 
 174     __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB1_offset())));
 175     __ movl(Address(rsi, 0), rax);
 176     __ movl(Address(rsi, 4), rbx);
 177     __ movl(Address(rsi, 8), rcx);
 178     __ movl(Address(rsi,12), rdx);
 179 
 180     __ movl(rax, 0xb);
 181     __ movl(rcx, 2);     // Packages level
 182     __ cpuid();
 183     __ push(rax);
 184     __ andl(rax, 0x1f);  // Determine if valid topology level
 185     __ orl(rax, rbx);    // eax[4:0] | ebx[0:15] == 0 indicates invalid level
 186     __ andl(rax, 0xffff);
 187     __ pop(rax);
 188     __ jccb(Assembler::equal, std_cpuid4);
 189 
 190     __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB2_offset())));
 191     __ movl(Address(rsi, 0), rax);
 192     __ movl(Address(rsi, 4), rbx);
 193     __ movl(Address(rsi, 8), rcx);
 194     __ movl(Address(rsi,12), rdx);
 195 
 196     //
 197     // cpuid(0x4) Deterministic cache params
 198     //
 199     __ bind(std_cpuid4);
 200     __ movl(rax, 4);
 201     __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x4) supported?
 202     __ jccb(Assembler::greater, std_cpuid1);
 203 
 204     __ xorl(rcx, rcx);   // L1 cache
 205     __ cpuid();
 206     __ push(rax);
 207     __ andl(rax, 0x1f);  // Determine if valid cache parameters used
 208     __ orl(rax, rax);    // eax[4:0] == 0 indicates invalid cache
 209     __ pop(rax);
 210     __ jccb(Assembler::equal, std_cpuid1);
 211 
 212     __ lea(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset())));
 213     __ movl(Address(rsi, 0), rax);
 214     __ movl(Address(rsi, 4), rbx);
 215     __ movl(Address(rsi, 8), rcx);
 216     __ movl(Address(rsi,12), rdx);
 217 
 218     //
 219     // Standard cpuid(0x1)
 220     //
 221     __ bind(std_cpuid1);
 222     __ movl(rax, 1);
 223     __ cpuid();
 224     __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
 225     __ movl(Address(rsi, 0), rax);
 226     __ movl(Address(rsi, 4), rbx);
 227     __ movl(Address(rsi, 8), rcx);
 228     __ movl(Address(rsi,12), rdx);
 229 
 230     //
 231     // Check if OS has enabled XGETBV instruction to access XCR0
 232     // (OSXSAVE feature flag) and CPU supports AVX
 233     //
 234     __ andl(rcx, 0x18000000); // cpuid1 bits osxsave | avx
 235     __ cmpl(rcx, 0x18000000);
 236     __ jccb(Assembler::notEqual, sef_cpuid); // jump if AVX is not supported
 237 
 238     //
 239     // XCR0, XFEATURE_ENABLED_MASK register
 240     //
 241     __ xorl(rcx, rcx);   // zero for XCR0 register
 242     __ xgetbv();
 243     __ lea(rsi, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset())));
 244     __ movl(Address(rsi, 0), rax);
 245     __ movl(Address(rsi, 4), rdx);
 246 
 247     //
 248     // cpuid(0x7) Structured Extended Features
 249     //
 250     __ bind(sef_cpuid);
 251     __ movl(rax, 7);
 252     __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x7) supported?
 253     __ jccb(Assembler::greater, ext_cpuid);
 254 
 255     __ xorl(rcx, rcx);
 256     __ cpuid();
 257     __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
 258     __ movl(Address(rsi, 0), rax);
 259     __ movl(Address(rsi, 4), rbx);
 260     __ movl(Address(rsi, 8), rcx);
 261     __ movl(Address(rsi, 12), rdx);
 262 
 263     //
 264     // Extended cpuid(0x80000000)
 265     //
 266     __ bind(ext_cpuid);
 267     __ movl(rax, 0x80000000);
 268     __ cpuid();
 269     __ cmpl(rax, 0x80000000);     // Is cpuid(0x80000001) supported?
 270     __ jcc(Assembler::belowEqual, done);
 271     __ cmpl(rax, 0x80000004);     // Is cpuid(0x80000005) supported?
 272     __ jcc(Assembler::belowEqual, ext_cpuid1);
 273     __ cmpl(rax, 0x80000006);     // Is cpuid(0x80000007) supported?
 274     __ jccb(Assembler::belowEqual, ext_cpuid5);
 275     __ cmpl(rax, 0x80000007);     // Is cpuid(0x80000008) supported?
 276     __ jccb(Assembler::belowEqual, ext_cpuid7);
 277     __ cmpl(rax, 0x80000008);     // Is cpuid(0x80000009 and above) supported?
 278     __ jccb(Assembler::belowEqual, ext_cpuid8);
 279     __ cmpl(rax, 0x8000001E);     // Is cpuid(0x8000001E) supported?
 280     __ jccb(Assembler::below, ext_cpuid8);
 281     //
 282     // Extended cpuid(0x8000001E)
 283     //
 284     __ movl(rax, 0x8000001E);
 285     __ cpuid();
 286     __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1E_offset())));
 287     __ movl(Address(rsi, 0), rax);
 288     __ movl(Address(rsi, 4), rbx);
 289     __ movl(Address(rsi, 8), rcx);
 290     __ movl(Address(rsi,12), rdx);
 291 
 292     //
 293     // Extended cpuid(0x80000008)
 294     //
 295     __ bind(ext_cpuid8);
 296     __ movl(rax, 0x80000008);
 297     __ cpuid();
 298     __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset())));
 299     __ movl(Address(rsi, 0), rax);
 300     __ movl(Address(rsi, 4), rbx);
 301     __ movl(Address(rsi, 8), rcx);
 302     __ movl(Address(rsi,12), rdx);
 303 
 304     //
 305     // Extended cpuid(0x80000007)
 306     //
 307     __ bind(ext_cpuid7);
 308     __ movl(rax, 0x80000007);
 309     __ cpuid();
 310     __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid7_offset())));
 311     __ movl(Address(rsi, 0), rax);
 312     __ movl(Address(rsi, 4), rbx);
 313     __ movl(Address(rsi, 8), rcx);
 314     __ movl(Address(rsi,12), rdx);
 315 
 316     //
 317     // Extended cpuid(0x80000005)
 318     //
 319     __ bind(ext_cpuid5);
 320     __ movl(rax, 0x80000005);
 321     __ cpuid();
 322     __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset())));
 323     __ movl(Address(rsi, 0), rax);
 324     __ movl(Address(rsi, 4), rbx);
 325     __ movl(Address(rsi, 8), rcx);
 326     __ movl(Address(rsi,12), rdx);
 327 
 328     //
 329     // Extended cpuid(0x80000001)
 330     //
 331     __ bind(ext_cpuid1);
 332     __ movl(rax, 0x80000001);
 333     __ cpuid();
 334     __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset())));
 335     __ movl(Address(rsi, 0), rax);
 336     __ movl(Address(rsi, 4), rbx);
 337     __ movl(Address(rsi, 8), rcx);
 338     __ movl(Address(rsi,12), rdx);
 339 
 340     //
 341     // Check if OS has enabled XGETBV instruction to access XCR0
 342     // (OSXSAVE feature flag) and CPU supports AVX
 343     //
 344     __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
 345     __ movl(rcx, 0x18000000); // cpuid1 bits osxsave | avx
 346     __ andl(rcx, Address(rsi, 8)); // cpuid1 bits osxsave | avx
 347     __ cmpl(rcx, 0x18000000);
 348     __ jccb(Assembler::notEqual, done); // jump if AVX is not supported
 349 
 350     __ movl(rax, 0x6);
 351     __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm
 352     __ cmpl(rax, 0x6);
 353     __ jccb(Assembler::equal, start_simd_check); // return if AVX is not supported
 354 
 355     // we need to bridge farther than imm8, so we use this island as a thunk
 356     __ bind(done);
 357     __ jmp(wrapup);
 358 
 359     __ bind(start_simd_check);
 360     //
 361     // Some OSs have a bug when upper 128/256bits of YMM/ZMM
 362     // registers are not restored after a signal processing.
 363     // Generate SEGV here (reference through NULL)
 364     // and check upper YMM/ZMM bits after it.
 365     //
 366     intx saved_useavx = UseAVX;
 367     intx saved_usesse = UseSSE;
 368     // check _cpuid_info.sef_cpuid7_ebx.bits.avx512f
 369     __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
 370     __ movl(rax, 0x10000);
 371     __ andl(rax, Address(rsi, 4)); // xcr0 bits sse | ymm
 372     __ cmpl(rax, 0x10000);
 373     __ jccb(Assembler::notEqual, legacy_setup); // jump if EVEX is not supported
 374     // check _cpuid_info.xem_xcr0_eax.bits.opmask
 375     // check _cpuid_info.xem_xcr0_eax.bits.zmm512
 376     // check _cpuid_info.xem_xcr0_eax.bits.zmm32
 377     __ movl(rax, 0xE0);
 378     __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm
 379     __ cmpl(rax, 0xE0);
 380     __ jccb(Assembler::notEqual, legacy_setup); // jump if EVEX is not supported
 381 
 382     // If UseAVX is unitialized or is set by the user to include EVEX
 383     if (use_evex) {
 384       // EVEX setup: run in lowest evex mode
 385       VM_Version::set_evex_cpuFeatures(); // Enable temporary to pass asserts
 386       UseAVX = 3;
 387       UseSSE = 2;
 388 #ifdef _WINDOWS
 389       // xmm5-xmm15 are not preserved by caller on windows
 390       // https://msdn.microsoft.com/en-us/library/9z1stfyw.aspx
 391       __ subptr(rsp, 64);
 392       __ evmovdqul(Address(rsp, 0), xmm7, Assembler::AVX_512bit);
 393 #ifdef _LP64
 394       __ subptr(rsp, 64);
 395       __ evmovdqul(Address(rsp, 0), xmm8, Assembler::AVX_512bit);
 396       __ subptr(rsp, 64);
 397       __ evmovdqul(Address(rsp, 0), xmm31, Assembler::AVX_512bit);
 398 #endif // _LP64
 399 #endif // _WINDOWS
 400 
 401       // load value into all 64 bytes of zmm7 register
 402       __ movl(rcx, VM_Version::ymm_test_value());
 403       __ movdl(xmm0, rcx);
 404       __ movl(rcx, 0xffff);
 405       __ kmovwl(k1, rcx);
 406       __ evpbroadcastd(xmm0, xmm0, Assembler::AVX_512bit);
 407       __ evmovdqul(xmm7, xmm0, Assembler::AVX_512bit);
 408 #ifdef _LP64
 409       __ evmovdqul(xmm8, xmm0, Assembler::AVX_512bit);
 410       __ evmovdqul(xmm31, xmm0, Assembler::AVX_512bit);
 411 #endif
 412       VM_Version::clean_cpuFeatures();
 413       __ jmp(save_restore_except);
 414     }
 415 
 416     __ bind(legacy_setup);
 417     // AVX setup
 418     VM_Version::set_avx_cpuFeatures(); // Enable temporary to pass asserts
 419     UseAVX = 1;
 420     UseSSE = 2;
 421 #ifdef _WINDOWS
 422     __ subptr(rsp, 32);
 423     __ vmovdqu(Address(rsp, 0), xmm7);
 424 #ifdef _LP64
 425     __ subptr(rsp, 32);
 426     __ vmovdqu(Address(rsp, 0), xmm8);
 427     __ subptr(rsp, 32);
 428     __ vmovdqu(Address(rsp, 0), xmm15);
 429 #endif // _LP64
 430 #endif // _WINDOWS
 431 
 432     // load value into all 32 bytes of ymm7 register
 433     __ movl(rcx, VM_Version::ymm_test_value());
 434 
 435     __ movdl(xmm0, rcx);
 436     __ pshufd(xmm0, xmm0, 0x00);
 437     __ vinsertf128_high(xmm0, xmm0);
 438     __ vmovdqu(xmm7, xmm0);
 439 #ifdef _LP64
 440     __ vmovdqu(xmm8, xmm0);
 441     __ vmovdqu(xmm15, xmm0);
 442 #endif
 443     VM_Version::clean_cpuFeatures();
 444 
 445     __ bind(save_restore_except);
 446     __ xorl(rsi, rsi);
 447     VM_Version::set_cpuinfo_segv_addr(__ pc());
 448     // Generate SEGV
 449     __ movl(rax, Address(rsi, 0));
 450 
 451     VM_Version::set_cpuinfo_cont_addr(__ pc());
 452     // Returns here after signal. Save xmm0 to check it later.
 453 
 454     // check _cpuid_info.sef_cpuid7_ebx.bits.avx512f
 455     __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
 456     __ movl(rax, 0x10000);
 457     __ andl(rax, Address(rsi, 4));
 458     __ cmpl(rax, 0x10000);
 459     __ jcc(Assembler::notEqual, legacy_save_restore);
 460     // check _cpuid_info.xem_xcr0_eax.bits.opmask
 461     // check _cpuid_info.xem_xcr0_eax.bits.zmm512
 462     // check _cpuid_info.xem_xcr0_eax.bits.zmm32
 463     __ movl(rax, 0xE0);
 464     __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm
 465     __ cmpl(rax, 0xE0);
 466     __ jcc(Assembler::notEqual, legacy_save_restore);
 467 
 468     // If UseAVX is unitialized or is set by the user to include EVEX
 469     if (use_evex) {
 470       // EVEX check: run in lowest evex mode
 471       VM_Version::set_evex_cpuFeatures(); // Enable temporary to pass asserts
 472       UseAVX = 3;
 473       UseSSE = 2;
 474       __ lea(rsi, Address(rbp, in_bytes(VM_Version::zmm_save_offset())));
 475       __ evmovdqul(Address(rsi, 0), xmm0, Assembler::AVX_512bit);
 476       __ evmovdqul(Address(rsi, 64), xmm7, Assembler::AVX_512bit);
 477 #ifdef _LP64
 478       __ evmovdqul(Address(rsi, 128), xmm8, Assembler::AVX_512bit);
 479       __ evmovdqul(Address(rsi, 192), xmm31, Assembler::AVX_512bit);
 480 #endif
 481 
 482 #ifdef _WINDOWS
 483 #ifdef _LP64
 484       __ evmovdqul(xmm31, Address(rsp, 0), Assembler::AVX_512bit);
 485       __ addptr(rsp, 64);
 486       __ evmovdqul(xmm8, Address(rsp, 0), Assembler::AVX_512bit);
 487       __ addptr(rsp, 64);
 488 #endif // _LP64
 489       __ evmovdqul(xmm7, Address(rsp, 0), Assembler::AVX_512bit);
 490       __ addptr(rsp, 64);
 491 #endif // _WINDOWS
 492       generate_vzeroupper(wrapup);
 493       VM_Version::clean_cpuFeatures();
 494       UseAVX = saved_useavx;
 495       UseSSE = saved_usesse;
 496       __ jmp(wrapup);
 497    }
 498 
 499     __ bind(legacy_save_restore);
 500     // AVX check
 501     VM_Version::set_avx_cpuFeatures(); // Enable temporary to pass asserts
 502     UseAVX = 1;
 503     UseSSE = 2;
 504     __ lea(rsi, Address(rbp, in_bytes(VM_Version::ymm_save_offset())));
 505     __ vmovdqu(Address(rsi, 0), xmm0);
 506     __ vmovdqu(Address(rsi, 32), xmm7);
 507 #ifdef _LP64
 508     __ vmovdqu(Address(rsi, 64), xmm8);
 509     __ vmovdqu(Address(rsi, 96), xmm15);
 510 #endif
 511 
 512 #ifdef _WINDOWS
 513 #ifdef _LP64
 514     __ vmovdqu(xmm15, Address(rsp, 0));
 515     __ addptr(rsp, 32);
 516     __ vmovdqu(xmm8, Address(rsp, 0));
 517     __ addptr(rsp, 32);
 518 #endif // _LP64
 519     __ vmovdqu(xmm7, Address(rsp, 0));
 520     __ addptr(rsp, 32);
 521 #endif // _WINDOWS
 522     generate_vzeroupper(wrapup);
 523     VM_Version::clean_cpuFeatures();
 524     UseAVX = saved_useavx;
 525     UseSSE = saved_usesse;
 526 
 527     __ bind(wrapup);
 528     __ popf();
 529     __ pop(rsi);
 530     __ pop(rbx);
 531     __ pop(rbp);
 532     __ ret(0);
 533 
 534 #   undef __
 535 
 536     return start;
 537   };
 538   void generate_vzeroupper(Label& L_wrapup) {
 539 #   define __ _masm->
 540     __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));
 541     __ cmpl(Address(rsi, 4), 0x756e6547);  // 'uneG'
 542     __ jcc(Assembler::notEqual, L_wrapup);
 543     __ movl(rcx, 0x0FFF0FF0);
 544     __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
 545     __ andl(rcx, Address(rsi, 0));
 546     __ cmpl(rcx, 0x00050670);              // If it is Xeon Phi 3200/5200/7200
 547     __ jcc(Assembler::equal, L_wrapup);
 548     __ cmpl(rcx, 0x00080650);              // If it is Future Xeon Phi
 549     __ jcc(Assembler::equal, L_wrapup);
 550     __ vzeroupper();
 551 #   undef __
 552   }
 553 };
 554 
 555 void VM_Version::get_processor_features() {
 556 
 557   _cpu = 4; // 486 by default
 558   _model = 0;
 559   _stepping = 0;
 560   _features = 0;
 561   _logical_processors_per_package = 1;
 562   // i486 internal cache is both I&D and has a 16-byte line size
 563   _L1_data_cache_line_size = 16;
 564 
 565   // Get raw processor info
 566 
 567   get_cpu_info_stub(&_cpuid_info);
 568 
 569   assert_is_initialized();
 570   _cpu = extended_cpu_family();
 571   _model = extended_cpu_model();
 572   _stepping = cpu_stepping();
 573 
 574   if (cpu_family() > 4) { // it supports CPUID
 575     _features = feature_flags();
 576     // Logical processors are only available on P4s and above,
 577     // and only if hyperthreading is available.
 578     _logical_processors_per_package = logical_processor_count();
 579     _L1_data_cache_line_size = L1_line_size();
 580   }
 581 
 582   _supports_cx8 = supports_cmpxchg8();
 583   // xchg and xadd instructions
 584   _supports_atomic_getset4 = true;
 585   _supports_atomic_getadd4 = true;
 586   LP64_ONLY(_supports_atomic_getset8 = true);
 587   LP64_ONLY(_supports_atomic_getadd8 = true);
 588 
 589 #ifdef _LP64
 590   // OS should support SSE for x64 and hardware should support at least SSE2.
 591   if (!VM_Version::supports_sse2()) {
 592     vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported");
 593   }
 594   // in 64 bit the use of SSE2 is the minimum
 595   if (UseSSE < 2) UseSSE = 2;
 596 #endif
 597 
 598 #ifdef AMD64
 599   // flush_icache_stub have to be generated first.
 600   // That is why Icache line size is hard coded in ICache class,
 601   // see icache_x86.hpp. It is also the reason why we can't use
 602   // clflush instruction in 32-bit VM since it could be running
 603   // on CPU which does not support it.
 604   //
 605   // The only thing we can do is to verify that flushed
 606   // ICache::line_size has correct value.
 607   guarantee(_cpuid_info.std_cpuid1_edx.bits.clflush != 0, "clflush is not supported");
 608   // clflush_size is size in quadwords (8 bytes).
 609   guarantee(_cpuid_info.std_cpuid1_ebx.bits.clflush_size == 8, "such clflush size is not supported");
 610 #endif
 611 
 612   // If the OS doesn't support SSE, we can't use this feature even if the HW does
 613   if (!os::supports_sse())
 614     _features &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4A|CPU_SSE4_1|CPU_SSE4_2);
 615 
 616   if (UseSSE < 4) {
 617     _features &= ~CPU_SSE4_1;
 618     _features &= ~CPU_SSE4_2;
 619   }
 620 
 621   if (UseSSE < 3) {
 622     _features &= ~CPU_SSE3;
 623     _features &= ~CPU_SSSE3;
 624     _features &= ~CPU_SSE4A;
 625   }
 626 
 627   if (UseSSE < 2)
 628     _features &= ~CPU_SSE2;
 629 
 630   if (UseSSE < 1)
 631     _features &= ~CPU_SSE;
 632 
 633   //since AVX instructions is slower than SSE in some ZX cpus, force USEAVX=0.
 634   if (is_zx() && ((cpu_family() == 6) || (cpu_family() == 7))) {
 635     UseAVX = 0;
 636   }
 637 
 638   // first try initial setting and detect what we can support
 639   int use_avx_limit = 0;
 640   if (UseAVX > 0) {
 641     if (UseAVX > 2 && supports_evex()) {
 642       use_avx_limit = 3;
 643     } else if (UseAVX > 1 && supports_avx2()) {
 644       use_avx_limit = 2;
 645     } else if (UseAVX > 0 && supports_avx()) {
 646       use_avx_limit = 1;
 647     } else {
 648       use_avx_limit = 0;
 649     }
 650   }
 651   if (FLAG_IS_DEFAULT(UseAVX)) {
 652     FLAG_SET_DEFAULT(UseAVX, use_avx_limit);
 653   } else if (UseAVX > use_avx_limit) {
 654     warning("UseAVX=%d is not supported on this CPU, setting it to UseAVX=%d", (int) UseAVX, use_avx_limit);
 655     FLAG_SET_DEFAULT(UseAVX, use_avx_limit);
 656   } else if (UseAVX < 0) {
 657     warning("UseAVX=%d is not valid, setting it to UseAVX=0", (int) UseAVX);
 658     FLAG_SET_DEFAULT(UseAVX, 0);
 659   }
 660 
 661   if (UseAVX < 3) {
 662     _features &= ~CPU_AVX512F;
 663     _features &= ~CPU_AVX512DQ;
 664     _features &= ~CPU_AVX512CD;
 665     _features &= ~CPU_AVX512BW;
 666     _features &= ~CPU_AVX512VL;
 667     _features &= ~CPU_AVX512_VPOPCNTDQ;
 668     _features &= ~CPU_VPCLMULQDQ;
 669     _features &= ~CPU_VAES;
 670   }
 671 
 672   if (UseAVX < 2)
 673     _features &= ~CPU_AVX2;
 674 
 675   if (UseAVX < 1) {
 676     _features &= ~CPU_AVX;
 677     _features &= ~CPU_VZEROUPPER;
 678   }
 679 
 680   if (logical_processors_per_package() == 1) {
 681     // HT processor could be installed on a system which doesn't support HT.
 682     _features &= ~CPU_HT;
 683   }
 684 
 685   if( is_intel() ) { // Intel cpus specific settings
 686     if (is_knights_family()) {
 687       _features &= ~CPU_VZEROUPPER;
 688     }
 689   }
 690 
 691   char buf[256];
 692   jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
 693                cores_per_cpu(), threads_per_core(),
 694                cpu_family(), _model, _stepping,
 695                (supports_cmov() ? ", cmov" : ""),
 696                (supports_cmpxchg8() ? ", cx8" : ""),
 697                (supports_fxsr() ? ", fxsr" : ""),
 698                (supports_mmx()  ? ", mmx"  : ""),
 699                (supports_sse()  ? ", sse"  : ""),
 700                (supports_sse2() ? ", sse2" : ""),
 701                (supports_sse3() ? ", sse3" : ""),
 702                (supports_ssse3()? ", ssse3": ""),
 703                (supports_sse4_1() ? ", sse4.1" : ""),
 704                (supports_sse4_2() ? ", sse4.2" : ""),
 705                (supports_popcnt() ? ", popcnt" : ""),
 706                (supports_avx()    ? ", avx" : ""),
 707                (supports_avx2()   ? ", avx2" : ""),
 708                (supports_aes()    ? ", aes" : ""),
 709                (supports_clmul()  ? ", clmul" : ""),
 710                (supports_erms()   ? ", erms" : ""),
 711                (supports_rtm()    ? ", rtm" : ""),
 712                (supports_mmx_ext() ? ", mmxext" : ""),
 713                (supports_3dnow_prefetch() ? ", 3dnowpref" : ""),
 714                (supports_lzcnt()   ? ", lzcnt": ""),
 715                (supports_sse4a()   ? ", sse4a": ""),
 716                (supports_ht() ? ", ht": ""),
 717                (supports_tsc() ? ", tsc": ""),
 718                (supports_tscinv_bit() ? ", tscinvbit": ""),
 719                (supports_tscinv() ? ", tscinv": ""),
 720                (supports_bmi1() ? ", bmi1" : ""),
 721                (supports_bmi2() ? ", bmi2" : ""),
 722                (supports_adx() ? ", adx" : ""),
 723                (supports_evex() ? ", evex" : ""),
 724                (supports_sha() ? ", sha" : ""),
 725                (supports_fma() ? ", fma" : ""));
 726   _features_string = os::strdup(buf);
 727 
 728   // UseSSE is set to the smaller of what hardware supports and what
 729   // the command line requires.  I.e., you cannot set UseSSE to 2 on
 730   // older Pentiums which do not support it.
 731   int use_sse_limit = 0;
 732   if (UseSSE > 0) {
 733     if (UseSSE > 3 && supports_sse4_1()) {
 734       use_sse_limit = 4;
 735     } else if (UseSSE > 2 && supports_sse3()) {
 736       use_sse_limit = 3;
 737     } else if (UseSSE > 1 && supports_sse2()) {
 738       use_sse_limit = 2;
 739     } else if (UseSSE > 0 && supports_sse()) {
 740       use_sse_limit = 1;
 741     } else {
 742       use_sse_limit = 0;
 743     }
 744   }
 745   if (FLAG_IS_DEFAULT(UseSSE)) {
 746     FLAG_SET_DEFAULT(UseSSE, use_sse_limit);
 747   } else if (UseSSE > use_sse_limit) {
 748     warning("UseSSE=%d is not supported on this CPU, setting it to UseSSE=%d", (int) UseSSE, use_sse_limit);
 749     FLAG_SET_DEFAULT(UseSSE, use_sse_limit);
 750   } else if (UseSSE < 0) {
 751     warning("UseSSE=%d is not valid, setting it to UseSSE=0", (int) UseSSE);
 752     FLAG_SET_DEFAULT(UseSSE, 0);
 753   }
 754 
 755   // Use AES instructions if available.
 756   if (supports_aes()) {
 757     if (FLAG_IS_DEFAULT(UseAES)) {
 758       FLAG_SET_DEFAULT(UseAES, true);
 759     }
 760     if (!UseAES) {
 761       if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
 762         warning("AES intrinsics require UseAES flag to be enabled. Intrinsics will be disabled.");
 763       }
 764       FLAG_SET_DEFAULT(UseAESIntrinsics, false);
 765     } else {
 766       if (UseSSE > 2) {
 767         if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
 768           FLAG_SET_DEFAULT(UseAESIntrinsics, true);
 769         }
 770       } else {
 771         // The AES intrinsic stubs require AES instruction support (of course)
 772         // but also require sse3 mode or higher for instructions it use.
 773         if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
 774           warning("X86 AES intrinsics require SSE3 instructions or higher. Intrinsics will be disabled.");
 775         }
 776         FLAG_SET_DEFAULT(UseAESIntrinsics, false);
 777       }
 778 
 779       // --AES-CTR begins--
 780       if (!UseAESIntrinsics) {
 781         if (UseAESCTRIntrinsics && !FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
 782           warning("AES-CTR intrinsics require UseAESIntrinsics flag to be enabled. Intrinsics will be disabled.");
 783           FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
 784         }
 785       } else {
 786         if(supports_sse4_1()) {
 787           if (FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
 788             FLAG_SET_DEFAULT(UseAESCTRIntrinsics, true);
 789           }
 790         } else {
 791            // The AES-CTR intrinsic stubs require AES instruction support (of course)
 792            // but also require sse4.1 mode or higher for instructions it use.
 793           if (UseAESCTRIntrinsics && !FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
 794              warning("X86 AES-CTR intrinsics require SSE4.1 instructions or higher. Intrinsics will be disabled.");
 795            }
 796            FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
 797         }
 798       }
 799       // --AES-CTR ends--
 800     }
 801   } else if (UseAES || UseAESIntrinsics || UseAESCTRIntrinsics) {
 802     if (UseAES && !FLAG_IS_DEFAULT(UseAES)) {
 803       warning("AES instructions are not available on this CPU");
 804       FLAG_SET_DEFAULT(UseAES, false);
 805     }
 806     if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
 807       warning("AES intrinsics are not available on this CPU");
 808       FLAG_SET_DEFAULT(UseAESIntrinsics, false);
 809     }
 810     if (UseAESCTRIntrinsics && !FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
 811       warning("AES-CTR intrinsics are not available on this CPU");
 812       FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
 813     }
 814   }
 815 
 816   // Use CLMUL instructions if available.
 817   if (supports_clmul()) {
 818     if (FLAG_IS_DEFAULT(UseCLMUL)) {
 819       UseCLMUL = true;
 820     }
 821   } else if (UseCLMUL) {
 822     if (!FLAG_IS_DEFAULT(UseCLMUL))
 823       warning("CLMUL instructions not available on this CPU (AVX may also be required)");
 824     FLAG_SET_DEFAULT(UseCLMUL, false);
 825   }
 826 
 827   if (UseCLMUL && (UseSSE > 2)) {
 828     if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
 829       UseCRC32Intrinsics = true;
 830     }
 831   } else if (UseCRC32Intrinsics) {
 832     if (!FLAG_IS_DEFAULT(UseCRC32Intrinsics))
 833       warning("CRC32 Intrinsics requires CLMUL instructions (not available on this CPU)");
 834     FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
 835   }
 836 
 837   if (supports_sse4_2() && supports_clmul()) {
 838     if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
 839       UseCRC32CIntrinsics = true;
 840     }
 841   } else if (UseCRC32CIntrinsics) {
 842     if (!FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
 843       warning("CRC32C intrinsics are not available on this CPU");
 844     }
 845     FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
 846   }
 847 
 848   // GHASH/GCM intrinsics
 849   if (UseCLMUL && (UseSSE > 2)) {
 850     if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
 851       UseGHASHIntrinsics = true;
 852     }
 853   } else if (UseGHASHIntrinsics) {
 854     if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics))
 855       warning("GHASH intrinsic requires CLMUL and SSE2 instructions on this CPU");
 856     FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
 857   }
 858 
 859   // Base64 Intrinsics (Check the condition for which the intrinsic will be active)
 860   if ((UseAVX > 2) && supports_avx512vl() && supports_avx512bw()) {
 861     if (FLAG_IS_DEFAULT(UseBASE64Intrinsics)) {
 862       UseBASE64Intrinsics = true;
 863     }
 864   } else if (UseBASE64Intrinsics) {
 865      if (!FLAG_IS_DEFAULT(UseBASE64Intrinsics))
 866       warning("Base64 intrinsic requires EVEX instructions on this CPU");
 867     FLAG_SET_DEFAULT(UseBASE64Intrinsics, false);
 868   }
 869 
 870   if (supports_fma() && UseSSE >= 2) { // Check UseSSE since FMA code uses SSE instructions
 871     if (FLAG_IS_DEFAULT(UseFMA)) {
 872       UseFMA = true;
 873     }
 874   } else if (UseFMA) {
 875     warning("FMA instructions are not available on this CPU");
 876     FLAG_SET_DEFAULT(UseFMA, false);
 877   }
 878 
 879   if (supports_sha() LP64_ONLY(|| supports_avx2() && supports_bmi2())) {
 880     if (FLAG_IS_DEFAULT(UseSHA)) {
 881       UseSHA = true;
 882     }
 883   } else if (UseSHA) {
 884     warning("SHA instructions are not available on this CPU");
 885     FLAG_SET_DEFAULT(UseSHA, false);
 886   }
 887 
 888   if (supports_sha() && UseSHA) {
 889     if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
 890       FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
 891     }
 892   } else if (UseSHA1Intrinsics) {
 893     warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
 894     FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
 895   }
 896 
 897   if (UseSHA) {
 898     if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
 899       FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
 900     }
 901   } else if (UseSHA256Intrinsics) {
 902     warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
 903     FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
 904   }
 905 
 906   if (UseSHA && supports_avx2() && supports_bmi2()) {
 907     if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
 908       FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
 909     }
 910   } else if (UseSHA512Intrinsics) {
 911     warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
 912     FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
 913   }
 914 
 915   if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
 916     FLAG_SET_DEFAULT(UseSHA, false);
 917   }
 918 
 919   if (UseAdler32Intrinsics) {
 920     warning("Adler32Intrinsics not available on this CPU.");
 921     FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
 922   }
 923 
 924   if (!supports_rtm() && UseRTMLocking) {
 925     // Can't continue because UseRTMLocking affects UseBiasedLocking flag
 926     // setting during arguments processing. See use_biased_locking().
 927     // VM_Version_init() is executed after UseBiasedLocking is used
 928     // in Thread::allocate().
 929     vm_exit_during_initialization("RTM instructions are not available on this CPU");
 930   }
 931 
 932 #if INCLUDE_RTM_OPT
 933   if (UseRTMLocking) {
 934     if (is_client_compilation_mode_vm()) {
 935       // Only C2 does RTM locking optimization.
 936       // Can't continue because UseRTMLocking affects UseBiasedLocking flag
 937       // setting during arguments processing. See use_biased_locking().
 938       vm_exit_during_initialization("RTM locking optimization is not supported in this VM");
 939     }
 940     if (is_intel_family_core()) {
 941       if ((_model == CPU_MODEL_HASWELL_E3) ||
 942           (_model == CPU_MODEL_HASWELL_E7 && _stepping < 3) ||
 943           (_model == CPU_MODEL_BROADWELL  && _stepping < 4)) {
 944         // currently a collision between SKL and HSW_E3
 945         if (!UnlockExperimentalVMOptions && UseAVX < 3) {
 946           vm_exit_during_initialization("UseRTMLocking is only available as experimental option on this "
 947                                         "platform. It must be enabled via -XX:+UnlockExperimentalVMOptions flag.");
 948         } else {
 949           warning("UseRTMLocking is only available as experimental option on this platform.");
 950         }
 951       }
 952     }
 953     if (!FLAG_IS_CMDLINE(UseRTMLocking)) {
 954       // RTM locking should be used only for applications with
 955       // high lock contention. For now we do not use it by default.
 956       vm_exit_during_initialization("UseRTMLocking flag should be only set on command line");
 957     }
 958   } else { // !UseRTMLocking
 959     if (UseRTMForStackLocks) {
 960       if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) {
 961         warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off");
 962       }
 963       FLAG_SET_DEFAULT(UseRTMForStackLocks, false);
 964     }
 965     if (UseRTMDeopt) {
 966       FLAG_SET_DEFAULT(UseRTMDeopt, false);
 967     }
 968     if (PrintPreciseRTMLockingStatistics) {
 969       FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false);
 970     }
 971   }
 972 #else
 973   if (UseRTMLocking) {
 974     // Only C2 does RTM locking optimization.
 975     // Can't continue because UseRTMLocking affects UseBiasedLocking flag
 976     // setting during arguments processing. See use_biased_locking().
 977     vm_exit_during_initialization("RTM locking optimization is not supported in this VM");
 978   }
 979 #endif
 980 
 981 #ifdef COMPILER2
 982   if (UseFPUForSpilling) {
 983     if (UseSSE < 2) {
 984       // Only supported with SSE2+
 985       FLAG_SET_DEFAULT(UseFPUForSpilling, false);
 986     }
 987   }
 988 #endif
 989 #if COMPILER2_OR_JVMCI
 990   if (MaxVectorSize > 0) {
 991     if (!is_power_of_2(MaxVectorSize)) {
 992       warning("MaxVectorSize must be a power of 2");
 993       FLAG_SET_DEFAULT(MaxVectorSize, 64);
 994     }
 995     if (UseSSE < 2) {
 996       // Vectors (in XMM) are only supported with SSE2+
 997       if (MaxVectorSize > 0) {
 998         if (!FLAG_IS_DEFAULT(MaxVectorSize))
 999           warning("MaxVectorSize must be 0");
1000         FLAG_SET_DEFAULT(MaxVectorSize, 0);
1001       }
1002     }
1003     else if (UseAVX == 0 || !os_supports_avx_vectors()) {
1004       // 32 bytes vectors (in YMM) are only supported with AVX+
1005       if (MaxVectorSize > 16) {
1006         if (!FLAG_IS_DEFAULT(MaxVectorSize))
1007           warning("MaxVectorSize must be <= 16");
1008         FLAG_SET_DEFAULT(MaxVectorSize, 16);
1009       }
1010     }
1011     else if (UseAVX == 1 || UseAVX == 2) {
1012       // 64 bytes vectors (in ZMM) are only supported with AVX 3
1013       if (MaxVectorSize > 32) {
1014         if (!FLAG_IS_DEFAULT(MaxVectorSize))
1015           warning("MaxVectorSize must be <= 32");
1016         FLAG_SET_DEFAULT(MaxVectorSize, 32);
1017       }
1018     }
1019     else if (UseAVX > 2 ) {
1020       if (MaxVectorSize > 64) {
1021         if (!FLAG_IS_DEFAULT(MaxVectorSize))
1022           warning("MaxVectorSize must be <= 64");
1023         FLAG_SET_DEFAULT(MaxVectorSize, 64);
1024       }
1025     }
1026 #if defined(COMPILER2) && defined(ASSERT)
1027     if (supports_avx() && PrintMiscellaneous && Verbose && TraceNewVectors) {
1028       tty->print_cr("State of YMM registers after signal handle:");
1029       int nreg = 2 LP64_ONLY(+2);
1030       const char* ymm_name[4] = {"0", "7", "8", "15"};
1031       for (int i = 0; i < nreg; i++) {
1032         tty->print("YMM%s:", ymm_name[i]);
1033         for (int j = 7; j >=0; j--) {
1034           tty->print(" %x", _cpuid_info.ymm_save[i*8 + j]);
1035         }
1036         tty->cr();
1037       }
1038     }
1039 #endif // COMPILER2 && ASSERT
1040   }
1041 #endif // COMPILER2_OR_JVMCI
1042 
1043 #ifdef COMPILER2
1044 #ifdef _LP64
1045   if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
1046     UseMultiplyToLenIntrinsic = true;
1047   }
1048   if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
1049     UseSquareToLenIntrinsic = true;
1050   }
1051   if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
1052     UseMulAddIntrinsic = true;
1053   }
1054   if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
1055     UseMontgomeryMultiplyIntrinsic = true;
1056   }
1057   if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
1058     UseMontgomerySquareIntrinsic = true;
1059   }
1060 #else
1061   if (UseMultiplyToLenIntrinsic) {
1062     if (!FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
1063       warning("multiplyToLen intrinsic is not available in 32-bit VM");
1064     }
1065     FLAG_SET_DEFAULT(UseMultiplyToLenIntrinsic, false);
1066   }
1067   if (UseMontgomeryMultiplyIntrinsic) {
1068     if (!FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
1069       warning("montgomeryMultiply intrinsic is not available in 32-bit VM");
1070     }
1071     FLAG_SET_DEFAULT(UseMontgomeryMultiplyIntrinsic, false);
1072   }
1073   if (UseMontgomerySquareIntrinsic) {
1074     if (!FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
1075       warning("montgomerySquare intrinsic is not available in 32-bit VM");
1076     }
1077     FLAG_SET_DEFAULT(UseMontgomerySquareIntrinsic, false);
1078   }
1079   if (UseSquareToLenIntrinsic) {
1080     if (!FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
1081       warning("squareToLen intrinsic is not available in 32-bit VM");
1082     }
1083     FLAG_SET_DEFAULT(UseSquareToLenIntrinsic, false);
1084   }
1085   if (UseMulAddIntrinsic) {
1086     if (!FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
1087       warning("mulAdd intrinsic is not available in 32-bit VM");
1088     }
1089     FLAG_SET_DEFAULT(UseMulAddIntrinsic, false);
1090   }
1091 #endif
1092 #endif // COMPILER2
1093 
1094   // On new cpus instructions which update whole XMM register should be used
1095   // to prevent partial register stall due to dependencies on high half.
1096   //
1097   // UseXmmLoadAndClearUpper == true  --> movsd(xmm, mem)
1098   // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem)
1099   // UseXmmRegToRegMoveAll == true  --> movaps(xmm, xmm), movapd(xmm, xmm).
1100   // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm),  movsd(xmm, xmm).
1101 
1102 
1103   if (is_zx()) { // ZX cpus specific settings
1104     if (FLAG_IS_DEFAULT(UseStoreImmI16)) {
1105       UseStoreImmI16 = false; // don't use it on ZX cpus
1106     }
1107     if ((cpu_family() == 6) || (cpu_family() == 7)) {
1108       if (FLAG_IS_DEFAULT(UseAddressNop)) {
1109         // Use it on all ZX cpus
1110         UseAddressNop = true;
1111       }
1112     }
1113     if (FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper)) {
1114       UseXmmLoadAndClearUpper = true; // use movsd on all ZX cpus
1115     }
1116     if (FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll)) {
1117       if (supports_sse3()) {
1118         UseXmmRegToRegMoveAll = true; // use movaps, movapd on new ZX cpus
1119       } else {
1120         UseXmmRegToRegMoveAll = false;
1121       }
1122     }
1123     if (((cpu_family() == 6) || (cpu_family() == 7)) && supports_sse3()) { // new ZX cpus
1124 #ifdef COMPILER2
1125       if (FLAG_IS_DEFAULT(MaxLoopPad)) {
1126         // For new ZX cpus do the next optimization:
1127         // don't align the beginning of a loop if there are enough instructions
1128         // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
1129         // in current fetch line (OptoLoopAlignment) or the padding
1130         // is big (> MaxLoopPad).
1131         // Set MaxLoopPad to 11 for new ZX cpus to reduce number of
1132         // generated NOP instructions. 11 is the largest size of one
1133         // address NOP instruction '0F 1F' (see Assembler::nop(i)).
1134         MaxLoopPad = 11;
1135       }
1136 #endif // COMPILER2
1137       if (FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1138         UseXMMForArrayCopy = true; // use SSE2 movq on new ZX cpus
1139       }
1140       if (supports_sse4_2()) { // new ZX cpus
1141         if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1142           UseUnalignedLoadStores = true; // use movdqu on newest ZX cpus
1143         }
1144       }
1145       if (supports_sse4_2()) {
1146         if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
1147           FLAG_SET_DEFAULT(UseSSE42Intrinsics, true);
1148         }
1149       } else {
1150         if (UseSSE42Intrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
1151           warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled.");
1152         }
1153         FLAG_SET_DEFAULT(UseSSE42Intrinsics, false);
1154       }
1155     }
1156 
1157     if (FLAG_IS_DEFAULT(AllocatePrefetchInstr) && supports_3dnow_prefetch()) {
1158       FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3);
1159     }
1160   }
1161 
1162   if( is_amd() ) { // AMD cpus specific settings
1163     if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) {
1164       // Use it on new AMD cpus starting from Opteron.
1165       UseAddressNop = true;
1166     }
1167     if( supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift) ) {
1168       // Use it on new AMD cpus starting from Opteron.
1169       UseNewLongLShift = true;
1170     }
1171     if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
1172       if (supports_sse4a()) {
1173         UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron
1174       } else {
1175         UseXmmLoadAndClearUpper = false;
1176       }
1177     }
1178     if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
1179       if( supports_sse4a() ) {
1180         UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h'
1181       } else {
1182         UseXmmRegToRegMoveAll = false;
1183       }
1184     }
1185     if( FLAG_IS_DEFAULT(UseXmmI2F) ) {
1186       if( supports_sse4a() ) {
1187         UseXmmI2F = true;
1188       } else {
1189         UseXmmI2F = false;
1190       }
1191     }
1192     if( FLAG_IS_DEFAULT(UseXmmI2D) ) {
1193       if( supports_sse4a() ) {
1194         UseXmmI2D = true;
1195       } else {
1196         UseXmmI2D = false;
1197       }
1198     }
1199     if (supports_sse4_2()) {
1200       if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
1201         FLAG_SET_DEFAULT(UseSSE42Intrinsics, true);
1202       }
1203     } else {
1204       if (UseSSE42Intrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
1205         warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled.");
1206       }
1207       FLAG_SET_DEFAULT(UseSSE42Intrinsics, false);
1208     }
1209 
1210     // some defaults for AMD family 15h
1211     if ( cpu_family() == 0x15 ) {
1212       // On family 15h processors default is no sw prefetch
1213       if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
1214         FLAG_SET_DEFAULT(AllocatePrefetchStyle, 0);
1215       }
1216       // Also, if some other prefetch style is specified, default instruction type is PREFETCHW
1217       if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
1218         FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3);
1219       }
1220       // On family 15h processors use XMM and UnalignedLoadStores for Array Copy
1221       if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1222         FLAG_SET_DEFAULT(UseXMMForArrayCopy, true);
1223       }
1224       if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1225         FLAG_SET_DEFAULT(UseUnalignedLoadStores, true);
1226       }
1227     }
1228 
1229 #ifdef COMPILER2
1230     if (cpu_family() < 0x17 && MaxVectorSize > 16) {
1231       // Limit vectors size to 16 bytes on AMD cpus < 17h.
1232       FLAG_SET_DEFAULT(MaxVectorSize, 16);
1233     }
1234 #endif // COMPILER2
1235 
1236     // Some defaults for AMD family 17h
1237     if ( cpu_family() == 0x17 ) {
1238       // On family 17h processors use XMM and UnalignedLoadStores for Array Copy
1239       if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1240         FLAG_SET_DEFAULT(UseXMMForArrayCopy, true);
1241       }
1242       if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1243         FLAG_SET_DEFAULT(UseUnalignedLoadStores, true);
1244       }
1245 #ifdef COMPILER2
1246       if (supports_sse4_2() && FLAG_IS_DEFAULT(UseFPUForSpilling)) {
1247         FLAG_SET_DEFAULT(UseFPUForSpilling, true);
1248       }
1249 #endif
1250     }
1251   }
1252 
1253   if( is_intel() ) { // Intel cpus specific settings
1254     if( FLAG_IS_DEFAULT(UseStoreImmI16) ) {
1255       UseStoreImmI16 = false; // don't use it on Intel cpus
1256     }
1257     if( cpu_family() == 6 || cpu_family() == 15 ) {
1258       if( FLAG_IS_DEFAULT(UseAddressNop) ) {
1259         // Use it on all Intel cpus starting from PentiumPro
1260         UseAddressNop = true;
1261       }
1262     }
1263     if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
1264       UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus
1265     }
1266     if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
1267       if( supports_sse3() ) {
1268         UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus
1269       } else {
1270         UseXmmRegToRegMoveAll = false;
1271       }
1272     }
1273     if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus
1274 #ifdef COMPILER2
1275       if( FLAG_IS_DEFAULT(MaxLoopPad) ) {
1276         // For new Intel cpus do the next optimization:
1277         // don't align the beginning of a loop if there are enough instructions
1278         // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
1279         // in current fetch line (OptoLoopAlignment) or the padding
1280         // is big (> MaxLoopPad).
1281         // Set MaxLoopPad to 11 for new Intel cpus to reduce number of
1282         // generated NOP instructions. 11 is the largest size of one
1283         // address NOP instruction '0F 1F' (see Assembler::nop(i)).
1284         MaxLoopPad = 11;
1285       }
1286 #endif // COMPILER2
1287       if (FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1288         UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus
1289       }
1290       if (supports_sse4_2() && supports_ht()) { // Newest Intel cpus
1291         if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1292           UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
1293         }
1294       }
1295       if (supports_sse4_2()) {
1296         if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
1297           FLAG_SET_DEFAULT(UseSSE42Intrinsics, true);
1298         }
1299       } else {
1300         if (UseSSE42Intrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
1301           warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled.");
1302         }
1303         FLAG_SET_DEFAULT(UseSSE42Intrinsics, false);
1304       }
1305     }
1306     if (is_atom_family() || is_knights_family()) {
1307 #ifdef COMPILER2
1308       if (FLAG_IS_DEFAULT(OptoScheduling)) {
1309         OptoScheduling = true;
1310       }
1311 #endif
1312       if (supports_sse4_2()) { // Silvermont
1313         if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1314           UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
1315         }
1316       }
1317       if (FLAG_IS_DEFAULT(UseIncDec)) {
1318         FLAG_SET_DEFAULT(UseIncDec, false);
1319       }
1320     }
1321     if(FLAG_IS_DEFAULT(AllocatePrefetchInstr) && supports_3dnow_prefetch()) {
1322       FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3);
1323     }
1324   }
1325 
1326 #ifdef _LP64
1327   if (UseSSE42Intrinsics) {
1328     if (FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic)) {
1329       UseVectorizedMismatchIntrinsic = true;
1330     }
1331   } else if (UseVectorizedMismatchIntrinsic) {
1332     if (!FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic))
1333       warning("vectorizedMismatch intrinsics are not available on this CPU");
1334     FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
1335   }
1336 #else
1337   if (UseVectorizedMismatchIntrinsic) {
1338     if (!FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic)) {
1339       warning("vectorizedMismatch intrinsic is not available in 32-bit VM");
1340     }
1341     FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
1342   }
1343 #endif // _LP64
1344 
1345   // Use count leading zeros count instruction if available.
1346   if (supports_lzcnt()) {
1347     if (FLAG_IS_DEFAULT(UseCountLeadingZerosInstruction)) {
1348       UseCountLeadingZerosInstruction = true;
1349     }
1350    } else if (UseCountLeadingZerosInstruction) {
1351     warning("lzcnt instruction is not available on this CPU");
1352     FLAG_SET_DEFAULT(UseCountLeadingZerosInstruction, false);
1353   }
1354 
1355   // Use count trailing zeros instruction if available
1356   if (supports_bmi1()) {
1357     // tzcnt does not require VEX prefix
1358     if (FLAG_IS_DEFAULT(UseCountTrailingZerosInstruction)) {
1359       if (!UseBMI1Instructions && !FLAG_IS_DEFAULT(UseBMI1Instructions)) {
1360         // Don't use tzcnt if BMI1 is switched off on command line.
1361         UseCountTrailingZerosInstruction = false;
1362       } else {
1363         UseCountTrailingZerosInstruction = true;
1364       }
1365     }
1366   } else if (UseCountTrailingZerosInstruction) {
1367     warning("tzcnt instruction is not available on this CPU");
1368     FLAG_SET_DEFAULT(UseCountTrailingZerosInstruction, false);
1369   }
1370 
1371   // BMI instructions (except tzcnt) use an encoding with VEX prefix.
1372   // VEX prefix is generated only when AVX > 0.
1373   if (supports_bmi1() && supports_avx()) {
1374     if (FLAG_IS_DEFAULT(UseBMI1Instructions)) {
1375       UseBMI1Instructions = true;
1376     }
1377   } else if (UseBMI1Instructions) {
1378     warning("BMI1 instructions are not available on this CPU (AVX is also required)");
1379     FLAG_SET_DEFAULT(UseBMI1Instructions, false);
1380   }
1381 
1382   if (supports_bmi2() && supports_avx()) {
1383     if (FLAG_IS_DEFAULT(UseBMI2Instructions)) {
1384       UseBMI2Instructions = true;
1385     }
1386   } else if (UseBMI2Instructions) {
1387     warning("BMI2 instructions are not available on this CPU (AVX is also required)");
1388     FLAG_SET_DEFAULT(UseBMI2Instructions, false);
1389   }
1390 
1391   // Use population count instruction if available.
1392   if (supports_popcnt()) {
1393     if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
1394       UsePopCountInstruction = true;
1395     }
1396   } else if (UsePopCountInstruction) {
1397     warning("POPCNT instruction is not available on this CPU");
1398     FLAG_SET_DEFAULT(UsePopCountInstruction, false);
1399   }
1400 
1401   // Use fast-string operations if available.
1402   if (supports_erms()) {
1403     if (FLAG_IS_DEFAULT(UseFastStosb)) {
1404       UseFastStosb = true;
1405     }
1406   } else if (UseFastStosb) {
1407     warning("fast-string operations are not available on this CPU");
1408     FLAG_SET_DEFAULT(UseFastStosb, false);
1409   }
1410 
1411   // Use XMM/YMM MOVDQU instruction for Object Initialization
1412   if (!UseFastStosb && UseSSE >= 2 && UseUnalignedLoadStores) {
1413     if (FLAG_IS_DEFAULT(UseXMMForObjInit)) {
1414       UseXMMForObjInit = true;
1415     }
1416   } else if (UseXMMForObjInit) {
1417     warning("UseXMMForObjInit requires SSE2 and unaligned load/stores. Feature is switched off.");
1418     FLAG_SET_DEFAULT(UseXMMForObjInit, false);
1419   }
1420 
1421 #ifdef COMPILER2
1422   if (FLAG_IS_DEFAULT(AlignVector)) {
1423     // Modern processors allow misaligned memory operations for vectors.
1424     AlignVector = !UseUnalignedLoadStores;
1425   }
1426 #endif // COMPILER2
1427 
1428   if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
1429     if (AllocatePrefetchInstr == 3 && !supports_3dnow_prefetch()) {
1430       FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0);
1431     } else if (!supports_sse() && supports_3dnow_prefetch()) {
1432       FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3);
1433     }
1434   }
1435 
1436   // Allocation prefetch settings
1437   intx cache_line_size = prefetch_data_size();
1438   if (FLAG_IS_DEFAULT(AllocatePrefetchStepSize) &&
1439       (cache_line_size > AllocatePrefetchStepSize)) {
1440     FLAG_SET_DEFAULT(AllocatePrefetchStepSize, cache_line_size);
1441   }
1442 
1443   if ((AllocatePrefetchDistance == 0) && (AllocatePrefetchStyle != 0)) {
1444     assert(!FLAG_IS_DEFAULT(AllocatePrefetchDistance), "default value should not be 0");
1445     if (!FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
1446       warning("AllocatePrefetchDistance is set to 0 which disable prefetching. Ignoring AllocatePrefetchStyle flag.");
1447     }
1448     FLAG_SET_DEFAULT(AllocatePrefetchStyle, 0);
1449   }
1450 
1451   if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
1452     bool use_watermark_prefetch = (AllocatePrefetchStyle == 2);
1453     FLAG_SET_DEFAULT(AllocatePrefetchDistance, allocate_prefetch_distance(use_watermark_prefetch));
1454   }
1455 
1456   if (is_intel() && cpu_family() == 6 && supports_sse3()) {
1457     if (FLAG_IS_DEFAULT(AllocatePrefetchLines) &&
1458         supports_sse4_2() && supports_ht()) { // Nehalem based cpus
1459       FLAG_SET_DEFAULT(AllocatePrefetchLines, 4);
1460     }
1461 #ifdef COMPILER2
1462     if (FLAG_IS_DEFAULT(UseFPUForSpilling) && supports_sse4_2()) {
1463       FLAG_SET_DEFAULT(UseFPUForSpilling, true);
1464     }
1465 #endif
1466   }
1467 
1468   if (is_zx() && ((cpu_family() == 6) || (cpu_family() == 7)) && supports_sse4_2()) {
1469 #ifdef COMPILER2
1470     if (FLAG_IS_DEFAULT(UseFPUForSpilling)) {
1471       FLAG_SET_DEFAULT(UseFPUForSpilling, true);
1472     }
1473 #endif
1474   }
1475 
1476 #ifdef _LP64
1477   // Prefetch settings
1478 
1479   // Prefetch interval for gc copy/scan == 9 dcache lines.  Derived from
1480   // 50-warehouse specjbb runs on a 2-way 1.8ghz opteron using a 4gb heap.
1481   // Tested intervals from 128 to 2048 in increments of 64 == one cache line.
1482   // 256 bytes (4 dcache lines) was the nearest runner-up to 576.
1483 
1484   // gc copy/scan is disabled if prefetchw isn't supported, because
1485   // Prefetch::write emits an inlined prefetchw on Linux.
1486   // Do not use the 3dnow prefetchw instruction.  It isn't supported on em64t.
1487   // The used prefetcht0 instruction works for both amd64 and em64t.
1488 
1489   if (FLAG_IS_DEFAULT(PrefetchCopyIntervalInBytes)) {
1490     FLAG_SET_DEFAULT(PrefetchCopyIntervalInBytes, 576);
1491   }
1492   if (FLAG_IS_DEFAULT(PrefetchScanIntervalInBytes)) {
1493     FLAG_SET_DEFAULT(PrefetchScanIntervalInBytes, 576);
1494   }
1495   if (FLAG_IS_DEFAULT(PrefetchFieldsAhead)) {
1496     FLAG_SET_DEFAULT(PrefetchFieldsAhead, 1);
1497   }
1498 #endif
1499 
1500   if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
1501      (cache_line_size > ContendedPaddingWidth))
1502      ContendedPaddingWidth = cache_line_size;
1503 
1504   // This machine allows unaligned memory accesses
1505   if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
1506     FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
1507   }
1508 
1509 #ifndef PRODUCT
1510   if (log_is_enabled(Info, os, cpu)) {
1511     LogStream ls(Log(os, cpu)::info());
1512     outputStream* log = &ls;
1513     log->print_cr("Logical CPUs per core: %u",
1514                   logical_processors_per_package());
1515     log->print_cr("L1 data cache line size: %u", L1_data_cache_line_size());
1516     log->print("UseSSE=%d", (int) UseSSE);
1517     if (UseAVX > 0) {
1518       log->print("  UseAVX=%d", (int) UseAVX);
1519     }
1520     if (UseAES) {
1521       log->print("  UseAES=1");
1522     }
1523 #ifdef COMPILER2
1524     if (MaxVectorSize > 0) {
1525       log->print("  MaxVectorSize=%d", (int) MaxVectorSize);
1526     }
1527 #endif
1528     log->cr();
1529     log->print("Allocation");
1530     if (AllocatePrefetchStyle <= 0 || (UseSSE == 0 && !supports_3dnow_prefetch())) {
1531       log->print_cr(": no prefetching");
1532     } else {
1533       log->print(" prefetching: ");
1534       if (UseSSE == 0 && supports_3dnow_prefetch()) {
1535         log->print("PREFETCHW");
1536       } else if (UseSSE >= 1) {
1537         if (AllocatePrefetchInstr == 0) {
1538           log->print("PREFETCHNTA");
1539         } else if (AllocatePrefetchInstr == 1) {
1540           log->print("PREFETCHT0");
1541         } else if (AllocatePrefetchInstr == 2) {
1542           log->print("PREFETCHT2");
1543         } else if (AllocatePrefetchInstr == 3) {
1544           log->print("PREFETCHW");
1545         }
1546       }
1547       if (AllocatePrefetchLines > 1) {
1548         log->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize);
1549       } else {
1550         log->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize);
1551       }
1552     }
1553 
1554     if (PrefetchCopyIntervalInBytes > 0) {
1555       log->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes);
1556     }
1557     if (PrefetchScanIntervalInBytes > 0) {
1558       log->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes);
1559     }
1560     if (PrefetchFieldsAhead > 0) {
1561       log->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead);
1562     }
1563     if (ContendedPaddingWidth > 0) {
1564       log->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth);
1565     }
1566   }
1567 #endif // !PRODUCT
1568 }
1569 
1570 bool VM_Version::use_biased_locking() {
1571 #if INCLUDE_RTM_OPT
1572   // RTM locking is most useful when there is high lock contention and
1573   // low data contention.  With high lock contention the lock is usually
1574   // inflated and biased locking is not suitable for that case.
1575   // RTM locking code requires that biased locking is off.
1576   // Note: we can't switch off UseBiasedLocking in get_processor_features()
1577   // because it is used by Thread::allocate() which is called before
1578   // VM_Version::initialize().
1579   if (UseRTMLocking && UseBiasedLocking) {
1580     if (FLAG_IS_DEFAULT(UseBiasedLocking)) {
1581       FLAG_SET_DEFAULT(UseBiasedLocking, false);
1582     } else {
1583       warning("Biased locking is not supported with RTM locking; ignoring UseBiasedLocking flag." );
1584       UseBiasedLocking = false;
1585     }
1586   }
1587 #endif
1588   return UseBiasedLocking;
1589 }
1590 
1591 void VM_Version::initialize() {
1592   ResourceMark rm;
1593   // Making this stub must be FIRST use of assembler
1594 
1595   stub_blob = BufferBlob::create("get_cpu_info_stub", stub_size);
1596   if (stub_blob == NULL) {
1597     vm_exit_during_initialization("Unable to allocate get_cpu_info_stub");
1598   }
1599   CodeBuffer c(stub_blob);
1600   VM_Version_StubGenerator g(&c);
1601   get_cpu_info_stub = CAST_TO_FN_PTR(get_cpu_info_stub_t,
1602                                      g.generate_get_cpu_info());
1603 
1604   get_processor_features();
1605 }