1 /*
2 * Copyright (c) 2000, 2015, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "c1/c1_Compilation.hpp"
29 #include "c1/c1_LIRAssembler.hpp"
30 #include "c1/c1_MacroAssembler.hpp"
31 #include "c1/c1_Runtime1.hpp"
32 #include "c1/c1_ValueStack.hpp"
33 #include "ci/ciArrayKlass.hpp"
34 #include "ci/ciInstance.hpp"
35 #include "gc/shared/barrierSet.hpp"
36 #include "gc/shared/cardTableModRefBS.hpp"
37 #include "gc/shared/collectedHeap.hpp"
38 #include "nativeInst_x86.hpp"
39 #include "oops/objArrayKlass.hpp"
40 #include "runtime/sharedRuntime.hpp"
41 #include "vmreg_x86.inline.hpp"
42
43
44 // These masks are used to provide 128-bit aligned bitmasks to the XMM
45 // instructions, to allow sign-masking or sign-bit flipping. They allow
46 // fast versions of NegF/NegD and AbsF/AbsD.
47
48 // Note: 'double' and 'long long' have 32-bits alignment on x86.
49 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
50 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
51 // of 128-bits operands for SSE instructions.
52 jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF)));
53 // Store the value to a 128-bits operand.
54 operand[0] = lo;
55 operand[1] = hi;
56 return operand;
57 }
58
59 // Buffer for 128-bits masks used by SSE instructions.
60 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
61
62 // Static initialization during VM startup.
63 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
64 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
65 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], (jlong)UCONST64(0x8000000080000000), (jlong)UCONST64(0x8000000080000000));
66 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], (jlong)UCONST64(0x8000000000000000), (jlong)UCONST64(0x8000000000000000));
67
68
69
70 NEEDS_CLEANUP // remove this definitions ?
71 const Register IC_Klass = rax; // where the IC klass is cached
72 const Register SYNC_header = rax; // synchronization header
73 const Register SHIFT_count = rcx; // where count for shift operations must be
74
75 #define __ _masm->
76
77
78 static void select_different_registers(Register preserve,
79 Register extra,
80 Register &tmp1,
81 Register &tmp2) {
82 if (tmp1 == preserve) {
83 assert_different_registers(tmp1, tmp2, extra);
84 tmp1 = extra;
85 } else if (tmp2 == preserve) {
86 assert_different_registers(tmp1, tmp2, extra);
87 tmp2 = extra;
88 }
89 assert_different_registers(preserve, tmp1, tmp2);
90 }
91
92
93
94 static void select_different_registers(Register preserve,
95 Register extra,
96 Register &tmp1,
97 Register &tmp2,
98 Register &tmp3) {
99 if (tmp1 == preserve) {
100 assert_different_registers(tmp1, tmp2, tmp3, extra);
101 tmp1 = extra;
102 } else if (tmp2 == preserve) {
103 assert_different_registers(tmp1, tmp2, tmp3, extra);
104 tmp2 = extra;
105 } else if (tmp3 == preserve) {
106 assert_different_registers(tmp1, tmp2, tmp3, extra);
107 tmp3 = extra;
108 }
109 assert_different_registers(preserve, tmp1, tmp2, tmp3);
110 }
111
112
113
114 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
115 if (opr->is_constant()) {
116 LIR_Const* constant = opr->as_constant_ptr();
117 switch (constant->type()) {
118 case T_INT: {
119 return true;
120 }
121
122 default:
123 return false;
124 }
125 }
126 return false;
127 }
128
129
130 LIR_Opr LIR_Assembler::receiverOpr() {
131 return FrameMap::receiver_opr;
132 }
133
134 LIR_Opr LIR_Assembler::osrBufferPointer() {
135 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
136 }
137
138 //--------------fpu register translations-----------------------
139
140
141 address LIR_Assembler::float_constant(float f) {
142 address const_addr = __ float_constant(f);
143 if (const_addr == NULL) {
144 bailout("const section overflow");
145 return __ code()->consts()->start();
146 } else {
147 return const_addr;
148 }
149 }
150
151
152 address LIR_Assembler::double_constant(double d) {
153 address const_addr = __ double_constant(d);
154 if (const_addr == NULL) {
155 bailout("const section overflow");
156 return __ code()->consts()->start();
157 } else {
158 return const_addr;
159 }
160 }
161
162
163 void LIR_Assembler::set_24bit_FPU() {
164 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
165 }
166
167 void LIR_Assembler::reset_FPU() {
168 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
169 }
170
171 void LIR_Assembler::fpop() {
172 __ fpop();
173 }
174
175 void LIR_Assembler::fxch(int i) {
176 __ fxch(i);
177 }
178
179 void LIR_Assembler::fld(int i) {
180 __ fld_s(i);
181 }
182
183 void LIR_Assembler::ffree(int i) {
184 __ ffree(i);
185 }
186
187 void LIR_Assembler::breakpoint() {
188 __ int3();
189 }
190
191 void LIR_Assembler::push(LIR_Opr opr) {
192 if (opr->is_single_cpu()) {
193 __ push_reg(opr->as_register());
194 } else if (opr->is_double_cpu()) {
195 NOT_LP64(__ push_reg(opr->as_register_hi()));
196 __ push_reg(opr->as_register_lo());
197 } else if (opr->is_stack()) {
198 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix()));
199 } else if (opr->is_constant()) {
200 LIR_Const* const_opr = opr->as_constant_ptr();
201 if (const_opr->type() == T_OBJECT) {
202 __ push_oop(const_opr->as_jobject());
203 } else if (const_opr->type() == T_INT) {
204 __ push_jint(const_opr->as_jint());
205 } else {
206 ShouldNotReachHere();
207 }
208
209 } else {
210 ShouldNotReachHere();
211 }
212 }
213
214 void LIR_Assembler::pop(LIR_Opr opr) {
215 if (opr->is_single_cpu()) {
216 __ pop_reg(opr->as_register());
217 } else {
218 ShouldNotReachHere();
219 }
220 }
221
222 bool LIR_Assembler::is_literal_address(LIR_Address* addr) {
223 return addr->base()->is_illegal() && addr->index()->is_illegal();
224 }
225
226 //-------------------------------------------
227
228 Address LIR_Assembler::as_Address(LIR_Address* addr) {
229 return as_Address(addr, rscratch1);
230 }
231
232 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
233 if (addr->base()->is_illegal()) {
234 assert(addr->index()->is_illegal(), "must be illegal too");
235 AddressLiteral laddr((address)addr->disp(), relocInfo::none);
236 if (! __ reachable(laddr)) {
237 __ movptr(tmp, laddr.addr());
238 Address res(tmp, 0);
239 return res;
240 } else {
241 return __ as_Address(laddr);
242 }
243 }
244
245 Register base = addr->base()->as_pointer_register();
246
247 if (addr->index()->is_illegal()) {
248 return Address( base, addr->disp());
249 } else if (addr->index()->is_cpu_register()) {
250 Register index = addr->index()->as_pointer_register();
251 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp());
252 } else if (addr->index()->is_constant()) {
253 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp();
254 assert(Assembler::is_simm32(addr_offset), "must be");
255
256 return Address(base, addr_offset);
257 } else {
258 Unimplemented();
259 return Address();
260 }
261 }
262
263
264 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
265 Address base = as_Address(addr);
266 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord);
267 }
268
269
270 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
271 return as_Address(addr);
272 }
273
274
275 void LIR_Assembler::osr_entry() {
276 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
277 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
278 ValueStack* entry_state = osr_entry->state();
279 int number_of_locks = entry_state->locks_size();
280
281 // we jump here if osr happens with the interpreter
282 // state set up to continue at the beginning of the
283 // loop that triggered osr - in particular, we have
284 // the following registers setup:
285 //
286 // rcx: osr buffer
287 //
288
289 // build frame
290 ciMethod* m = compilation()->method();
291 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
292
293 // OSR buffer is
294 //
295 // locals[nlocals-1..0]
296 // monitors[0..number_of_locks]
297 //
298 // locals is a direct copy of the interpreter frame so in the osr buffer
299 // so first slot in the local array is the last local from the interpreter
300 // and last slot is local[0] (receiver) from the interpreter
301 //
302 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
303 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
304 // in the interpreter frame (the method lock if a sync method)
305
306 // Initialize monitors in the compiled activation.
307 // rcx: pointer to osr buffer
308 //
309 // All other registers are dead at this point and the locals will be
310 // copied into place by code emitted in the IR.
311
312 Register OSR_buf = osrBufferPointer()->as_pointer_register();
313 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
314 int monitor_offset = BytesPerWord * method()->max_locals() +
315 (2 * BytesPerWord) * (number_of_locks - 1);
316 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
317 // the OSR buffer using 2 word entries: first the lock and then
318 // the oop.
319 for (int i = 0; i < number_of_locks; i++) {
320 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
321 #ifdef ASSERT
322 // verify the interpreter's monitor has a non-null object
323 {
324 Label L;
325 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD);
326 __ jcc(Assembler::notZero, L);
327 __ stop("locked object is NULL");
328 __ bind(L);
329 }
330 #endif
331 __ movptr(rbx, Address(OSR_buf, slot_offset + 0));
332 __ movptr(frame_map()->address_for_monitor_lock(i), rbx);
333 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord));
334 __ movptr(frame_map()->address_for_monitor_object(i), rbx);
335 }
336 }
337 }
338
339
340 // inline cache check; done before the frame is built.
341 int LIR_Assembler::check_icache() {
342 Register receiver = FrameMap::receiver_opr->as_register();
343 Register ic_klass = IC_Klass;
344 const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9);
345 const bool do_post_padding = VerifyOops || UseCompressedClassPointers;
346 if (!do_post_padding) {
347 // insert some nops so that the verified entry point is aligned on CodeEntryAlignment
348 __ align(CodeEntryAlignment, __ offset() + ic_cmp_size);
349 }
350 int offset = __ offset();
351 __ inline_cache_check(receiver, IC_Klass);
352 assert(__ offset() % CodeEntryAlignment == 0 || do_post_padding, "alignment must be correct");
353 if (do_post_padding) {
354 // force alignment after the cache check.
355 // It's been verified to be aligned if !VerifyOops
356 __ align(CodeEntryAlignment);
357 }
358 return offset;
359 }
360
361
362 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
363 jobject o = NULL;
364 PatchingStub* patch = new PatchingStub(_masm, patching_id(info));
365 __ movoop(reg, o);
366 patching_epilog(patch, lir_patch_normal, reg, info);
367 }
368
369 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
370 Metadata* o = NULL;
371 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id);
372 __ mov_metadata(reg, o);
373 patching_epilog(patch, lir_patch_normal, reg, info);
374 }
375
376 // This specifies the rsp decrement needed to build the frame
377 int LIR_Assembler::initial_frame_size_in_bytes() const {
378 // if rounding, must let FrameMap know!
379
380 // The frame_map records size in slots (32bit word)
381
382 // subtract two words to account for return address and link
383 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size;
384 }
385
386
387 int LIR_Assembler::emit_exception_handler() {
388 // if the last instruction is a call (typically to do a throw which
389 // is coming at the end after block reordering) the return address
390 // must still point into the code area in order to avoid assertion
391 // failures when searching for the corresponding bci => add a nop
392 // (was bug 5/14/1999 - gri)
393 __ nop();
394
395 // generate code for exception handler
396 address handler_base = __ start_a_stub(exception_handler_size);
397 if (handler_base == NULL) {
398 // not enough space left for the handler
399 bailout("exception handler overflow");
400 return -1;
401 }
402
403 int offset = code_offset();
404
405 // the exception oop and pc are in rax, and rdx
406 // no other registers need to be preserved, so invalidate them
407 __ invalidate_registers(false, true, true, false, true, true);
408
409 // check that there is really an exception
410 __ verify_not_null_oop(rax);
411
412 // search an exception handler (rax: exception oop, rdx: throwing pc)
413 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id)));
414 __ should_not_reach_here();
415 guarantee(code_offset() - offset <= exception_handler_size, "overflow");
416 __ end_a_stub();
417
418 return offset;
419 }
420
421
422 // Emit the code to remove the frame from the stack in the exception
423 // unwind path.
424 int LIR_Assembler::emit_unwind_handler() {
425 #ifndef PRODUCT
426 if (CommentedAssembly) {
427 _masm->block_comment("Unwind handler");
428 }
429 #endif
430
431 int offset = code_offset();
432
433 // Fetch the exception from TLS and clear out exception related thread state
434 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
435 NOT_LP64(__ get_thread(rsi));
436 __ movptr(rax, Address(thread, JavaThread::exception_oop_offset()));
437 __ movptr(Address(thread, JavaThread::exception_oop_offset()), (intptr_t)NULL_WORD);
438 __ movptr(Address(thread, JavaThread::exception_pc_offset()), (intptr_t)NULL_WORD);
439
440 __ bind(_unwind_handler_entry);
441 __ verify_not_null_oop(rax);
442 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
443 __ mov(rbx, rax); // Preserve the exception (rbx is always callee-saved)
444 }
445
446 // Preform needed unlocking
447 MonitorExitStub* stub = NULL;
448 if (method()->is_synchronized()) {
449 monitor_address(0, FrameMap::rax_opr);
450 stub = new MonitorExitStub(FrameMap::rax_opr, true, 0);
451 __ unlock_object(rdi, rsi, rax, *stub->entry());
452 __ bind(*stub->continuation());
453 }
454
455 if (compilation()->env()->dtrace_method_probes()) {
456 #ifdef _LP64
457 __ mov(rdi, r15_thread);
458 __ mov_metadata(rsi, method()->constant_encoding());
459 #else
460 __ get_thread(rax);
461 __ movptr(Address(rsp, 0), rax);
462 __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding());
463 #endif
464 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
465 }
466
467 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
468 __ mov(rax, rbx); // Restore the exception
469 }
470
471 // remove the activation and dispatch to the unwind handler
472 __ remove_frame(initial_frame_size_in_bytes());
473 __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));
474
475 // Emit the slow path assembly
476 if (stub != NULL) {
477 stub->emit_code(this);
478 }
479
480 return offset;
481 }
482
483
484 int LIR_Assembler::emit_deopt_handler() {
485 // if the last instruction is a call (typically to do a throw which
486 // is coming at the end after block reordering) the return address
487 // must still point into the code area in order to avoid assertion
488 // failures when searching for the corresponding bci => add a nop
489 // (was bug 5/14/1999 - gri)
490 __ nop();
491
492 // generate code for exception handler
493 address handler_base = __ start_a_stub(deopt_handler_size);
494 if (handler_base == NULL) {
495 // not enough space left for the handler
496 bailout("deopt handler overflow");
497 return -1;
498 }
499
500 int offset = code_offset();
501 InternalAddress here(__ pc());
502
503 __ pushptr(here.addr());
504 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
505 guarantee(code_offset() - offset <= deopt_handler_size, "overflow");
506 __ end_a_stub();
507
508 return offset;
509 }
510
511
512 void LIR_Assembler::return_op(LIR_Opr result) {
513 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,");
514 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) {
515 assert(result->fpu() == 0, "result must already be on TOS");
516 }
517
518 // Pop the stack before the safepoint code
519 __ remove_frame(initial_frame_size_in_bytes());
520
521 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
522 __ reserved_stack_check();
523 }
524
525 bool result_is_oop = result->is_valid() ? result->is_oop() : false;
526
527 // Note: we do not need to round double result; float result has the right precision
528 // the poll sets the condition code, but no data registers
529 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);
530
531 if (Assembler::is_polling_page_far()) {
532 __ lea(rscratch1, polling_page);
533 __ relocate(relocInfo::poll_return_type);
534 __ testl(rax, Address(rscratch1, 0));
535 } else {
536 __ testl(rax, polling_page);
537 }
538 __ ret(0);
539 }
540
541
542 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
543 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_type);
544 guarantee(info != NULL, "Shouldn't be NULL");
545 int offset = __ offset();
546 if (Assembler::is_polling_page_far()) {
547 __ lea(rscratch1, polling_page);
548 offset = __ offset();
549 add_debug_info_for_branch(info);
550 __ relocate(relocInfo::poll_type);
551 __ testl(rax, Address(rscratch1, 0));
552 } else {
553 add_debug_info_for_branch(info);
554 __ testl(rax, polling_page);
555 }
556 return offset;
557 }
558
559
560 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
561 if (from_reg != to_reg) __ mov(to_reg, from_reg);
562 }
563
564 void LIR_Assembler::swap_reg(Register a, Register b) {
565 __ xchgptr(a, b);
566 }
567
568
569 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
570 assert(src->is_constant(), "should not call otherwise");
571 assert(dest->is_register(), "should not call otherwise");
572 LIR_Const* c = src->as_constant_ptr();
573
574 switch (c->type()) {
575 case T_INT: {
576 assert(patch_code == lir_patch_none, "no patching handled here");
577 __ movl(dest->as_register(), c->as_jint());
578 break;
579 }
580
581 case T_ADDRESS: {
582 assert(patch_code == lir_patch_none, "no patching handled here");
583 __ movptr(dest->as_register(), c->as_jint());
584 break;
585 }
586
587 case T_LONG: {
588 assert(patch_code == lir_patch_none, "no patching handled here");
589 #ifdef _LP64
590 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong());
591 #else
592 __ movptr(dest->as_register_lo(), c->as_jint_lo());
593 __ movptr(dest->as_register_hi(), c->as_jint_hi());
594 #endif // _LP64
595 break;
596 }
597
598 case T_OBJECT: {
599 if (patch_code != lir_patch_none) {
600 jobject2reg_with_patching(dest->as_register(), info);
601 } else {
602 __ movoop(dest->as_register(), c->as_jobject());
603 }
604 break;
605 }
606
607 case T_METADATA: {
608 if (patch_code != lir_patch_none) {
609 klass2reg_with_patching(dest->as_register(), info);
610 } else {
611 __ mov_metadata(dest->as_register(), c->as_metadata());
612 }
613 break;
614 }
615
616 case T_FLOAT: {
617 if (dest->is_single_xmm()) {
618 if (c->is_zero_float()) {
619 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg());
620 } else {
621 __ movflt(dest->as_xmm_float_reg(),
622 InternalAddress(float_constant(c->as_jfloat())));
623 }
624 } else {
625 assert(dest->is_single_fpu(), "must be");
626 assert(dest->fpu_regnr() == 0, "dest must be TOS");
627 if (c->is_zero_float()) {
628 __ fldz();
629 } else if (c->is_one_float()) {
630 __ fld1();
631 } else {
632 __ fld_s (InternalAddress(float_constant(c->as_jfloat())));
633 }
634 }
635 break;
636 }
637
638 case T_DOUBLE: {
639 if (dest->is_double_xmm()) {
640 if (c->is_zero_double()) {
641 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg());
642 } else {
643 __ movdbl(dest->as_xmm_double_reg(),
644 InternalAddress(double_constant(c->as_jdouble())));
645 }
646 } else {
647 assert(dest->is_double_fpu(), "must be");
648 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
649 if (c->is_zero_double()) {
650 __ fldz();
651 } else if (c->is_one_double()) {
652 __ fld1();
653 } else {
654 __ fld_d (InternalAddress(double_constant(c->as_jdouble())));
655 }
656 }
657 break;
658 }
659
660 default:
661 ShouldNotReachHere();
662 }
663 }
664
665 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
666 assert(src->is_constant(), "should not call otherwise");
667 assert(dest->is_stack(), "should not call otherwise");
668 LIR_Const* c = src->as_constant_ptr();
669
670 switch (c->type()) {
671 case T_INT: // fall through
672 case T_FLOAT:
673 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
674 break;
675
676 case T_ADDRESS:
677 __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
678 break;
679
680 case T_OBJECT:
681 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject());
682 break;
683
684 case T_LONG: // fall through
685 case T_DOUBLE:
686 #ifdef _LP64
687 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
688 lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits());
689 #else
690 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
691 lo_word_offset_in_bytes), c->as_jint_lo_bits());
692 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
693 hi_word_offset_in_bytes), c->as_jint_hi_bits());
694 #endif // _LP64
695 break;
696
697 default:
698 ShouldNotReachHere();
699 }
700 }
701
702 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
703 assert(src->is_constant(), "should not call otherwise");
704 assert(dest->is_address(), "should not call otherwise");
705 LIR_Const* c = src->as_constant_ptr();
706 LIR_Address* addr = dest->as_address_ptr();
707
708 int null_check_here = code_offset();
709 switch (type) {
710 case T_INT: // fall through
711 case T_FLOAT:
712 __ movl(as_Address(addr), c->as_jint_bits());
713 break;
714
715 case T_ADDRESS:
716 __ movptr(as_Address(addr), c->as_jint_bits());
717 break;
718
719 case T_OBJECT: // fall through
720 case T_ARRAY:
721 if (c->as_jobject() == NULL) {
722 if (UseCompressedOops && !wide) {
723 __ movl(as_Address(addr), (int32_t)NULL_WORD);
724 } else {
725 #ifdef _LP64
726 __ xorptr(rscratch1, rscratch1);
727 null_check_here = code_offset();
728 __ movptr(as_Address(addr), rscratch1);
729 #else
730 __ movptr(as_Address(addr), NULL_WORD);
731 #endif
732 }
733 } else {
734 if (is_literal_address(addr)) {
735 ShouldNotReachHere();
736 __ movoop(as_Address(addr, noreg), c->as_jobject());
737 } else {
738 #ifdef _LP64
739 __ movoop(rscratch1, c->as_jobject());
740 if (UseCompressedOops && !wide) {
741 __ encode_heap_oop(rscratch1);
742 null_check_here = code_offset();
743 __ movl(as_Address_lo(addr), rscratch1);
744 } else {
745 null_check_here = code_offset();
746 __ movptr(as_Address_lo(addr), rscratch1);
747 }
748 #else
749 __ movoop(as_Address(addr), c->as_jobject());
750 #endif
751 }
752 }
753 break;
754
755 case T_LONG: // fall through
756 case T_DOUBLE:
757 #ifdef _LP64
758 if (is_literal_address(addr)) {
759 ShouldNotReachHere();
760 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits());
761 } else {
762 __ movptr(r10, (intptr_t)c->as_jlong_bits());
763 null_check_here = code_offset();
764 __ movptr(as_Address_lo(addr), r10);
765 }
766 #else
767 // Always reachable in 32bit so this doesn't produce useless move literal
768 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits());
769 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits());
770 #endif // _LP64
771 break;
772
773 case T_BOOLEAN: // fall through
774 case T_BYTE:
775 __ movb(as_Address(addr), c->as_jint() & 0xFF);
776 break;
777
778 case T_CHAR: // fall through
779 case T_SHORT:
780 __ movw(as_Address(addr), c->as_jint() & 0xFFFF);
781 break;
782
783 default:
784 ShouldNotReachHere();
785 };
786
787 if (info != NULL) {
788 add_debug_info_for_null_check(null_check_here, info);
789 }
790 }
791
792
793 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
794 assert(src->is_register(), "should not call otherwise");
795 assert(dest->is_register(), "should not call otherwise");
796
797 // move between cpu-registers
798 if (dest->is_single_cpu()) {
799 #ifdef _LP64
800 if (src->type() == T_LONG) {
801 // Can do LONG -> OBJECT
802 move_regs(src->as_register_lo(), dest->as_register());
803 return;
804 }
805 #endif
806 assert(src->is_single_cpu(), "must match");
807 if (src->type() == T_OBJECT) {
808 __ verify_oop(src->as_register());
809 }
810 move_regs(src->as_register(), dest->as_register());
811
812 } else if (dest->is_double_cpu()) {
813 #ifdef _LP64
814 if (src->type() == T_OBJECT || src->type() == T_ARRAY) {
815 // Surprising to me but we can see move of a long to t_object
816 __ verify_oop(src->as_register());
817 move_regs(src->as_register(), dest->as_register_lo());
818 return;
819 }
820 #endif
821 assert(src->is_double_cpu(), "must match");
822 Register f_lo = src->as_register_lo();
823 Register f_hi = src->as_register_hi();
824 Register t_lo = dest->as_register_lo();
825 Register t_hi = dest->as_register_hi();
826 #ifdef _LP64
827 assert(f_hi == f_lo, "must be same");
828 assert(t_hi == t_lo, "must be same");
829 move_regs(f_lo, t_lo);
830 #else
831 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation");
832
833
834 if (f_lo == t_hi && f_hi == t_lo) {
835 swap_reg(f_lo, f_hi);
836 } else if (f_hi == t_lo) {
837 assert(f_lo != t_hi, "overwriting register");
838 move_regs(f_hi, t_hi);
839 move_regs(f_lo, t_lo);
840 } else {
841 assert(f_hi != t_lo, "overwriting register");
842 move_regs(f_lo, t_lo);
843 move_regs(f_hi, t_hi);
844 }
845 #endif // LP64
846
847 // special moves from fpu-register to xmm-register
848 // necessary for method results
849 } else if (src->is_single_xmm() && !dest->is_single_xmm()) {
850 __ movflt(Address(rsp, 0), src->as_xmm_float_reg());
851 __ fld_s(Address(rsp, 0));
852 } else if (src->is_double_xmm() && !dest->is_double_xmm()) {
853 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg());
854 __ fld_d(Address(rsp, 0));
855 } else if (dest->is_single_xmm() && !src->is_single_xmm()) {
856 __ fstp_s(Address(rsp, 0));
857 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0));
858 } else if (dest->is_double_xmm() && !src->is_double_xmm()) {
859 __ fstp_d(Address(rsp, 0));
860 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0));
861
862 // move between xmm-registers
863 } else if (dest->is_single_xmm()) {
864 assert(src->is_single_xmm(), "must match");
865 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg());
866 } else if (dest->is_double_xmm()) {
867 assert(src->is_double_xmm(), "must match");
868 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg());
869
870 // move between fpu-registers (no instruction necessary because of fpu-stack)
871 } else if (dest->is_single_fpu() || dest->is_double_fpu()) {
872 assert(src->is_single_fpu() || src->is_double_fpu(), "must match");
873 assert(src->fpu() == dest->fpu(), "currently should be nothing to do");
874 } else {
875 ShouldNotReachHere();
876 }
877 }
878
879 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
880 assert(src->is_register(), "should not call otherwise");
881 assert(dest->is_stack(), "should not call otherwise");
882
883 if (src->is_single_cpu()) {
884 Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
885 if (type == T_OBJECT || type == T_ARRAY) {
886 __ verify_oop(src->as_register());
887 __ movptr (dst, src->as_register());
888 } else if (type == T_METADATA) {
889 __ movptr (dst, src->as_register());
890 } else {
891 __ movl (dst, src->as_register());
892 }
893
894 } else if (src->is_double_cpu()) {
895 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
896 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes);
897 __ movptr (dstLO, src->as_register_lo());
898 NOT_LP64(__ movptr (dstHI, src->as_register_hi()));
899
900 } else if (src->is_single_xmm()) {
901 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
902 __ movflt(dst_addr, src->as_xmm_float_reg());
903
904 } else if (src->is_double_xmm()) {
905 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
906 __ movdbl(dst_addr, src->as_xmm_double_reg());
907
908 } else if (src->is_single_fpu()) {
909 assert(src->fpu_regnr() == 0, "argument must be on TOS");
910 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
911 if (pop_fpu_stack) __ fstp_s (dst_addr);
912 else __ fst_s (dst_addr);
913
914 } else if (src->is_double_fpu()) {
915 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
916 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
917 if (pop_fpu_stack) __ fstp_d (dst_addr);
918 else __ fst_d (dst_addr);
919
920 } else {
921 ShouldNotReachHere();
922 }
923 }
924
925
926 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool /* unaligned */) {
927 LIR_Address* to_addr = dest->as_address_ptr();
928 PatchingStub* patch = NULL;
929 Register compressed_src = rscratch1;
930
931 if (type == T_ARRAY || type == T_OBJECT) {
932 __ verify_oop(src->as_register());
933 #ifdef _LP64
934 if (UseCompressedOops && !wide) {
935 __ movptr(compressed_src, src->as_register());
936 __ encode_heap_oop(compressed_src);
937 if (patch_code != lir_patch_none) {
938 info->oop_map()->set_narrowoop(compressed_src->as_VMReg());
939 }
940 }
941 #endif
942 }
943
944 if (patch_code != lir_patch_none) {
945 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
946 Address toa = as_Address(to_addr);
947 assert(toa.disp() != 0, "must have");
948 }
949
950 int null_check_here = code_offset();
951 switch (type) {
952 case T_FLOAT: {
953 if (src->is_single_xmm()) {
954 __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
955 } else {
956 assert(src->is_single_fpu(), "must be");
957 assert(src->fpu_regnr() == 0, "argument must be on TOS");
958 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr));
959 else __ fst_s (as_Address(to_addr));
960 }
961 break;
962 }
963
964 case T_DOUBLE: {
965 if (src->is_double_xmm()) {
966 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
967 } else {
968 assert(src->is_double_fpu(), "must be");
969 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
970 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr));
971 else __ fst_d (as_Address(to_addr));
972 }
973 break;
974 }
975
976 case T_ARRAY: // fall through
977 case T_OBJECT: // fall through
978 if (UseCompressedOops && !wide) {
979 __ movl(as_Address(to_addr), compressed_src);
980 } else {
981 __ movptr(as_Address(to_addr), src->as_register());
982 }
983 break;
984 case T_METADATA:
985 // We get here to store a method pointer to the stack to pass to
986 // a dtrace runtime call. This can't work on 64 bit with
987 // compressed klass ptrs: T_METADATA can be a compressed klass
988 // ptr or a 64 bit method pointer.
989 LP64_ONLY(ShouldNotReachHere());
990 __ movptr(as_Address(to_addr), src->as_register());
991 break;
992 case T_ADDRESS:
993 __ movptr(as_Address(to_addr), src->as_register());
994 break;
995 case T_INT:
996 __ movl(as_Address(to_addr), src->as_register());
997 break;
998
999 case T_LONG: {
1000 Register from_lo = src->as_register_lo();
1001 Register from_hi = src->as_register_hi();
1002 #ifdef _LP64
1003 __ movptr(as_Address_lo(to_addr), from_lo);
1004 #else
1005 Register base = to_addr->base()->as_register();
1006 Register index = noreg;
1007 if (to_addr->index()->is_register()) {
1008 index = to_addr->index()->as_register();
1009 }
1010 if (base == from_lo || index == from_lo) {
1011 assert(base != from_hi, "can't be");
1012 assert(index == noreg || (index != base && index != from_hi), "can't handle this");
1013 __ movl(as_Address_hi(to_addr), from_hi);
1014 if (patch != NULL) {
1015 patching_epilog(patch, lir_patch_high, base, info);
1016 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1017 patch_code = lir_patch_low;
1018 }
1019 __ movl(as_Address_lo(to_addr), from_lo);
1020 } else {
1021 assert(index == noreg || (index != base && index != from_lo), "can't handle this");
1022 __ movl(as_Address_lo(to_addr), from_lo);
1023 if (patch != NULL) {
1024 patching_epilog(patch, lir_patch_low, base, info);
1025 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1026 patch_code = lir_patch_high;
1027 }
1028 __ movl(as_Address_hi(to_addr), from_hi);
1029 }
1030 #endif // _LP64
1031 break;
1032 }
1033
1034 case T_BYTE: // fall through
1035 case T_BOOLEAN: {
1036 Register src_reg = src->as_register();
1037 Address dst_addr = as_Address(to_addr);
1038 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6");
1039 __ movb(dst_addr, src_reg);
1040 break;
1041 }
1042
1043 case T_CHAR: // fall through
1044 case T_SHORT:
1045 __ movw(as_Address(to_addr), src->as_register());
1046 break;
1047
1048 default:
1049 ShouldNotReachHere();
1050 }
1051 if (info != NULL) {
1052 add_debug_info_for_null_check(null_check_here, info);
1053 }
1054
1055 if (patch_code != lir_patch_none) {
1056 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info);
1057 }
1058 }
1059
1060
1061 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1062 assert(src->is_stack(), "should not call otherwise");
1063 assert(dest->is_register(), "should not call otherwise");
1064
1065 if (dest->is_single_cpu()) {
1066 if (type == T_ARRAY || type == T_OBJECT) {
1067 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1068 __ verify_oop(dest->as_register());
1069 } else if (type == T_METADATA) {
1070 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1071 } else {
1072 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1073 }
1074
1075 } else if (dest->is_double_cpu()) {
1076 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
1077 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);
1078 __ movptr(dest->as_register_lo(), src_addr_LO);
1079 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI));
1080
1081 } else if (dest->is_single_xmm()) {
1082 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1083 __ movflt(dest->as_xmm_float_reg(), src_addr);
1084
1085 } else if (dest->is_double_xmm()) {
1086 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1087 __ movdbl(dest->as_xmm_double_reg(), src_addr);
1088
1089 } else if (dest->is_single_fpu()) {
1090 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1091 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1092 __ fld_s(src_addr);
1093
1094 } else if (dest->is_double_fpu()) {
1095 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1096 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1097 __ fld_d(src_addr);
1098
1099 } else {
1100 ShouldNotReachHere();
1101 }
1102 }
1103
1104
1105 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1106 if (src->is_single_stack()) {
1107 if (type == T_OBJECT || type == T_ARRAY) {
1108 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix()));
1109 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix()));
1110 } else {
1111 #ifndef _LP64
1112 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix()));
1113 __ popl (frame_map()->address_for_slot(dest->single_stack_ix()));
1114 #else
1115 //no pushl on 64bits
1116 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix()));
1117 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1);
1118 #endif
1119 }
1120
1121 } else if (src->is_double_stack()) {
1122 #ifdef _LP64
1123 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix()));
1124 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix()));
1125 #else
1126 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0));
1127 // push and pop the part at src + wordSize, adding wordSize for the previous push
1128 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize));
1129 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize));
1130 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0));
1131 #endif // _LP64
1132
1133 } else {
1134 ShouldNotReachHere();
1135 }
1136 }
1137
1138
1139 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool /* unaligned */) {
1140 assert(src->is_address(), "should not call otherwise");
1141 assert(dest->is_register(), "should not call otherwise");
1142
1143 LIR_Address* addr = src->as_address_ptr();
1144 Address from_addr = as_Address(addr);
1145
1146 if (addr->base()->type() == T_OBJECT) {
1147 __ verify_oop(addr->base()->as_pointer_register());
1148 }
1149
1150 switch (type) {
1151 case T_BOOLEAN: // fall through
1152 case T_BYTE: // fall through
1153 case T_CHAR: // fall through
1154 case T_SHORT:
1155 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) {
1156 // on pre P6 processors we may get partial register stalls
1157 // so blow away the value of to_rinfo before loading a
1158 // partial word into it. Do it here so that it precedes
1159 // the potential patch point below.
1160 __ xorptr(dest->as_register(), dest->as_register());
1161 }
1162 break;
1163 }
1164
1165 PatchingStub* patch = NULL;
1166 if (patch_code != lir_patch_none) {
1167 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1168 assert(from_addr.disp() != 0, "must have");
1169 }
1170 if (info != NULL) {
1171 add_debug_info_for_null_check_here(info);
1172 }
1173
1174 switch (type) {
1175 case T_FLOAT: {
1176 if (dest->is_single_xmm()) {
1177 __ movflt(dest->as_xmm_float_reg(), from_addr);
1178 } else {
1179 assert(dest->is_single_fpu(), "must be");
1180 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1181 __ fld_s(from_addr);
1182 }
1183 break;
1184 }
1185
1186 case T_DOUBLE: {
1187 if (dest->is_double_xmm()) {
1188 __ movdbl(dest->as_xmm_double_reg(), from_addr);
1189 } else {
1190 assert(dest->is_double_fpu(), "must be");
1191 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1192 __ fld_d(from_addr);
1193 }
1194 break;
1195 }
1196
1197 case T_OBJECT: // fall through
1198 case T_ARRAY: // fall through
1199 if (UseCompressedOops && !wide) {
1200 __ movl(dest->as_register(), from_addr);
1201 } else {
1202 __ movptr(dest->as_register(), from_addr);
1203 }
1204 break;
1205
1206 case T_ADDRESS:
1207 if (UseCompressedClassPointers && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1208 __ movl(dest->as_register(), from_addr);
1209 } else {
1210 __ movptr(dest->as_register(), from_addr);
1211 }
1212 break;
1213 case T_INT:
1214 __ movl(dest->as_register(), from_addr);
1215 break;
1216
1217 case T_LONG: {
1218 Register to_lo = dest->as_register_lo();
1219 Register to_hi = dest->as_register_hi();
1220 #ifdef _LP64
1221 __ movptr(to_lo, as_Address_lo(addr));
1222 #else
1223 Register base = addr->base()->as_register();
1224 Register index = noreg;
1225 if (addr->index()->is_register()) {
1226 index = addr->index()->as_register();
1227 }
1228 if ((base == to_lo && index == to_hi) ||
1229 (base == to_hi && index == to_lo)) {
1230 // addresses with 2 registers are only formed as a result of
1231 // array access so this code will never have to deal with
1232 // patches or null checks.
1233 assert(info == NULL && patch == NULL, "must be");
1234 __ lea(to_hi, as_Address(addr));
1235 __ movl(to_lo, Address(to_hi, 0));
1236 __ movl(to_hi, Address(to_hi, BytesPerWord));
1237 } else if (base == to_lo || index == to_lo) {
1238 assert(base != to_hi, "can't be");
1239 assert(index == noreg || (index != base && index != to_hi), "can't handle this");
1240 __ movl(to_hi, as_Address_hi(addr));
1241 if (patch != NULL) {
1242 patching_epilog(patch, lir_patch_high, base, info);
1243 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1244 patch_code = lir_patch_low;
1245 }
1246 __ movl(to_lo, as_Address_lo(addr));
1247 } else {
1248 assert(index == noreg || (index != base && index != to_lo), "can't handle this");
1249 __ movl(to_lo, as_Address_lo(addr));
1250 if (patch != NULL) {
1251 patching_epilog(patch, lir_patch_low, base, info);
1252 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1253 patch_code = lir_patch_high;
1254 }
1255 __ movl(to_hi, as_Address_hi(addr));
1256 }
1257 #endif // _LP64
1258 break;
1259 }
1260
1261 case T_BOOLEAN: // fall through
1262 case T_BYTE: {
1263 Register dest_reg = dest->as_register();
1264 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1265 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1266 __ movsbl(dest_reg, from_addr);
1267 } else {
1268 __ movb(dest_reg, from_addr);
1269 __ shll(dest_reg, 24);
1270 __ sarl(dest_reg, 24);
1271 }
1272 break;
1273 }
1274
1275 case T_CHAR: {
1276 Register dest_reg = dest->as_register();
1277 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1278 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1279 __ movzwl(dest_reg, from_addr);
1280 } else {
1281 __ movw(dest_reg, from_addr);
1282 }
1283 break;
1284 }
1285
1286 case T_SHORT: {
1287 Register dest_reg = dest->as_register();
1288 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1289 __ movswl(dest_reg, from_addr);
1290 } else {
1291 __ movw(dest_reg, from_addr);
1292 __ shll(dest_reg, 16);
1293 __ sarl(dest_reg, 16);
1294 }
1295 break;
1296 }
1297
1298 default:
1299 ShouldNotReachHere();
1300 }
1301
1302 if (patch != NULL) {
1303 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
1304 }
1305
1306 if (type == T_ARRAY || type == T_OBJECT) {
1307 #ifdef _LP64
1308 if (UseCompressedOops && !wide) {
1309 __ decode_heap_oop(dest->as_register());
1310 }
1311 #endif
1312 __ verify_oop(dest->as_register());
1313 } else if (type == T_ADDRESS && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1314 #ifdef _LP64
1315 if (UseCompressedClassPointers) {
1316 __ decode_klass_not_null(dest->as_register());
1317 }
1318 #endif
1319 }
1320 }
1321
1322
1323 NEEDS_CLEANUP; // This could be static?
1324 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const {
1325 int elem_size = type2aelembytes(type);
1326 switch (elem_size) {
1327 case 1: return Address::times_1;
1328 case 2: return Address::times_2;
1329 case 4: return Address::times_4;
1330 case 8: return Address::times_8;
1331 }
1332 ShouldNotReachHere();
1333 return Address::no_scale;
1334 }
1335
1336
1337 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1338 switch (op->code()) {
1339 case lir_idiv:
1340 case lir_irem:
1341 arithmetic_idiv(op->code(),
1342 op->in_opr1(),
1343 op->in_opr2(),
1344 op->in_opr3(),
1345 op->result_opr(),
1346 op->info());
1347 break;
1348 default: ShouldNotReachHere(); break;
1349 }
1350 }
1351
1352 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1353 #ifdef ASSERT
1354 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
1355 if (op->block() != NULL) _branch_target_blocks.append(op->block());
1356 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
1357 #endif
1358
1359 if (op->cond() == lir_cond_always) {
1360 if (op->info() != NULL) add_debug_info_for_branch(op->info());
1361 __ jmp (*(op->label()));
1362 } else {
1363 Assembler::Condition acond = Assembler::zero;
1364 if (op->code() == lir_cond_float_branch) {
1365 assert(op->ublock() != NULL, "must have unordered successor");
1366 __ jcc(Assembler::parity, *(op->ublock()->label()));
1367 switch(op->cond()) {
1368 case lir_cond_equal: acond = Assembler::equal; break;
1369 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1370 case lir_cond_less: acond = Assembler::below; break;
1371 case lir_cond_lessEqual: acond = Assembler::belowEqual; break;
1372 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break;
1373 case lir_cond_greater: acond = Assembler::above; break;
1374 default: ShouldNotReachHere();
1375 }
1376 } else {
1377 switch (op->cond()) {
1378 case lir_cond_equal: acond = Assembler::equal; break;
1379 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1380 case lir_cond_less: acond = Assembler::less; break;
1381 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1382 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
1383 case lir_cond_greater: acond = Assembler::greater; break;
1384 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
1385 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
1386 default: ShouldNotReachHere();
1387 }
1388 }
1389 __ jcc(acond,*(op->label()));
1390 }
1391 }
1392
1393 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1394 LIR_Opr src = op->in_opr();
1395 LIR_Opr dest = op->result_opr();
1396
1397 switch (op->bytecode()) {
1398 case Bytecodes::_i2l:
1399 #ifdef _LP64
1400 __ movl2ptr(dest->as_register_lo(), src->as_register());
1401 #else
1402 move_regs(src->as_register(), dest->as_register_lo());
1403 move_regs(src->as_register(), dest->as_register_hi());
1404 __ sarl(dest->as_register_hi(), 31);
1405 #endif // LP64
1406 break;
1407
1408 case Bytecodes::_l2i:
1409 #ifdef _LP64
1410 __ movl(dest->as_register(), src->as_register_lo());
1411 #else
1412 move_regs(src->as_register_lo(), dest->as_register());
1413 #endif
1414 break;
1415
1416 case Bytecodes::_i2b:
1417 move_regs(src->as_register(), dest->as_register());
1418 __ sign_extend_byte(dest->as_register());
1419 break;
1420
1421 case Bytecodes::_i2c:
1422 move_regs(src->as_register(), dest->as_register());
1423 __ andl(dest->as_register(), 0xFFFF);
1424 break;
1425
1426 case Bytecodes::_i2s:
1427 move_regs(src->as_register(), dest->as_register());
1428 __ sign_extend_short(dest->as_register());
1429 break;
1430
1431
1432 case Bytecodes::_f2d:
1433 case Bytecodes::_d2f:
1434 if (dest->is_single_xmm()) {
1435 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1436 } else if (dest->is_double_xmm()) {
1437 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1438 } else {
1439 assert(src->fpu() == dest->fpu(), "register must be equal");
1440 // do nothing (float result is rounded later through spilling)
1441 }
1442 break;
1443
1444 case Bytecodes::_i2f:
1445 case Bytecodes::_i2d:
1446 if (dest->is_single_xmm()) {
1447 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1448 } else if (dest->is_double_xmm()) {
1449 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1450 } else {
1451 assert(dest->fpu() == 0, "result must be on TOS");
1452 __ movl(Address(rsp, 0), src->as_register());
1453 __ fild_s(Address(rsp, 0));
1454 }
1455 break;
1456
1457 case Bytecodes::_f2i:
1458 case Bytecodes::_d2i:
1459 if (src->is_single_xmm()) {
1460 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg());
1461 } else if (src->is_double_xmm()) {
1462 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg());
1463 } else {
1464 assert(src->fpu() == 0, "input must be on TOS");
1465 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
1466 __ fist_s(Address(rsp, 0));
1467 __ movl(dest->as_register(), Address(rsp, 0));
1468 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1469 }
1470
1471 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
1472 assert(op->stub() != NULL, "stub required");
1473 __ cmpl(dest->as_register(), 0x80000000);
1474 __ jcc(Assembler::equal, *op->stub()->entry());
1475 __ bind(*op->stub()->continuation());
1476 break;
1477
1478 case Bytecodes::_l2f:
1479 case Bytecodes::_l2d:
1480 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)");
1481 assert(dest->fpu() == 0, "result must be on TOS");
1482
1483 __ movptr(Address(rsp, 0), src->as_register_lo());
1484 NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi()));
1485 __ fild_d(Address(rsp, 0));
1486 // float result is rounded later through spilling
1487 break;
1488
1489 case Bytecodes::_f2l:
1490 case Bytecodes::_d2l:
1491 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)");
1492 assert(src->fpu() == 0, "input must be on TOS");
1493 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers");
1494
1495 // instruction sequence too long to inline it here
1496 {
1497 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id)));
1498 }
1499 break;
1500
1501 default: ShouldNotReachHere();
1502 }
1503 }
1504
1505 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1506 if (op->init_check()) {
1507 __ cmpb(Address(op->klass()->as_register(),
1508 InstanceKlass::init_state_offset()),
1509 InstanceKlass::fully_initialized);
1510 add_debug_info_for_null_check_here(op->stub()->info());
1511 __ jcc(Assembler::notEqual, *op->stub()->entry());
1512 }
1513 __ allocate_object(op->obj()->as_register(),
1514 op->tmp1()->as_register(),
1515 op->tmp2()->as_register(),
1516 op->header_size(),
1517 op->object_size(),
1518 op->klass()->as_register(),
1519 *op->stub()->entry());
1520 __ bind(*op->stub()->continuation());
1521 }
1522
1523 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1524 Register len = op->len()->as_register();
1525 LP64_ONLY( __ movslq(len, len); )
1526
1527 if (UseSlowPath ||
1528 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
1529 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
1530 __ jmp(*op->stub()->entry());
1531 } else {
1532 Register tmp1 = op->tmp1()->as_register();
1533 Register tmp2 = op->tmp2()->as_register();
1534 Register tmp3 = op->tmp3()->as_register();
1535 if (len == tmp1) {
1536 tmp1 = tmp3;
1537 } else if (len == tmp2) {
1538 tmp2 = tmp3;
1539 } else if (len == tmp3) {
1540 // everything is ok
1541 } else {
1542 __ mov(tmp3, len);
1543 }
1544 __ allocate_array(op->obj()->as_register(),
1545 len,
1546 tmp1,
1547 tmp2,
1548 arrayOopDesc::header_size(op->type()),
1549 array_element_size(op->type()),
1550 op->klass()->as_register(),
1551 *op->stub()->entry());
1552 }
1553 __ bind(*op->stub()->continuation());
1554 }
1555
1556 void LIR_Assembler::type_profile_helper(Register mdo,
1557 ciMethodData *md, ciProfileData *data,
1558 Register recv, Label* update_done) {
1559 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1560 Label next_test;
1561 // See if the receiver is receiver[n].
1562 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1563 __ jccb(Assembler::notEqual, next_test);
1564 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1565 __ addptr(data_addr, DataLayout::counter_increment);
1566 __ jmp(*update_done);
1567 __ bind(next_test);
1568 }
1569
1570 // Didn't find receiver; find next empty slot and fill it in
1571 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1572 Label next_test;
1573 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
1574 __ cmpptr(recv_addr, (intptr_t)NULL_WORD);
1575 __ jccb(Assembler::notEqual, next_test);
1576 __ movptr(recv_addr, recv);
1577 __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment);
1578 __ jmp(*update_done);
1579 __ bind(next_test);
1580 }
1581 }
1582
1583 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1584 // we always need a stub for the failure case.
1585 CodeStub* stub = op->stub();
1586 Register obj = op->object()->as_register();
1587 Register k_RInfo = op->tmp1()->as_register();
1588 Register klass_RInfo = op->tmp2()->as_register();
1589 Register dst = op->result_opr()->as_register();
1590 ciKlass* k = op->klass();
1591 Register Rtmp1 = noreg;
1592
1593 // check if it needs to be profiled
1594 ciMethodData* md = NULL;
1595 ciProfileData* data = NULL;
1596
1597 if (op->should_profile()) {
1598 ciMethod* method = op->profiled_method();
1599 assert(method != NULL, "Should have method");
1600 int bci = op->profiled_bci();
1601 md = method->method_data_or_null();
1602 assert(md != NULL, "Sanity");
1603 data = md->bci_to_data(bci);
1604 assert(data != NULL, "need data for type check");
1605 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1606 }
1607 Label profile_cast_success, profile_cast_failure;
1608 Label *success_target = op->should_profile() ? &profile_cast_success : success;
1609 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure;
1610
1611 if (obj == k_RInfo) {
1612 k_RInfo = dst;
1613 } else if (obj == klass_RInfo) {
1614 klass_RInfo = dst;
1615 }
1616 if (k->is_loaded() && !UseCompressedClassPointers) {
1617 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1618 } else {
1619 Rtmp1 = op->tmp3()->as_register();
1620 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1621 }
1622
1623 assert_different_registers(obj, k_RInfo, klass_RInfo);
1624
1625 __ cmpptr(obj, (int32_t)NULL_WORD);
1626 if (op->should_profile()) {
1627 Label not_null;
1628 __ jccb(Assembler::notEqual, not_null);
1629 // Object is null; update MDO and exit
1630 Register mdo = klass_RInfo;
1631 __ mov_metadata(mdo, md->constant_encoding());
1632 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
1633 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
1634 __ orl(data_addr, header_bits);
1635 __ jmp(*obj_is_null);
1636 __ bind(not_null);
1637 } else {
1638 __ jcc(Assembler::equal, *obj_is_null);
1639 }
1640
1641 if (!k->is_loaded()) {
1642 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1643 } else {
1644 #ifdef _LP64
1645 __ mov_metadata(k_RInfo, k->constant_encoding());
1646 #endif // _LP64
1647 }
1648 __ verify_oop(obj);
1649
1650 if (op->fast_check()) {
1651 // get object class
1652 // not a safepoint as obj null check happens earlier
1653 #ifdef _LP64
1654 if (UseCompressedClassPointers) {
1655 __ load_klass(Rtmp1, obj);
1656 __ cmpptr(k_RInfo, Rtmp1);
1657 } else {
1658 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1659 }
1660 #else
1661 if (k->is_loaded()) {
1662 __ cmpklass(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding());
1663 } else {
1664 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1665 }
1666 #endif
1667 __ jcc(Assembler::notEqual, *failure_target);
1668 // successful cast, fall through to profile or jump
1669 } else {
1670 // get object class
1671 // not a safepoint as obj null check happens earlier
1672 __ load_klass(klass_RInfo, obj);
1673 if (k->is_loaded()) {
1674 // See if we get an immediate positive hit
1675 #ifdef _LP64
1676 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset()));
1677 #else
1678 __ cmpklass(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding());
1679 #endif // _LP64
1680 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1681 __ jcc(Assembler::notEqual, *failure_target);
1682 // successful cast, fall through to profile or jump
1683 } else {
1684 // See if we get an immediate positive hit
1685 __ jcc(Assembler::equal, *success_target);
1686 // check for self
1687 #ifdef _LP64
1688 __ cmpptr(klass_RInfo, k_RInfo);
1689 #else
1690 __ cmpklass(klass_RInfo, k->constant_encoding());
1691 #endif // _LP64
1692 __ jcc(Assembler::equal, *success_target);
1693
1694 __ push(klass_RInfo);
1695 #ifdef _LP64
1696 __ push(k_RInfo);
1697 #else
1698 __ pushklass(k->constant_encoding());
1699 #endif // _LP64
1700 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1701 __ pop(klass_RInfo);
1702 __ pop(klass_RInfo);
1703 // result is a boolean
1704 __ cmpl(klass_RInfo, 0);
1705 __ jcc(Assembler::equal, *failure_target);
1706 // successful cast, fall through to profile or jump
1707 }
1708 } else {
1709 // perform the fast part of the checking logic
1710 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1711 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1712 __ push(klass_RInfo);
1713 __ push(k_RInfo);
1714 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1715 __ pop(klass_RInfo);
1716 __ pop(k_RInfo);
1717 // result is a boolean
1718 __ cmpl(k_RInfo, 0);
1719 __ jcc(Assembler::equal, *failure_target);
1720 // successful cast, fall through to profile or jump
1721 }
1722 }
1723 if (op->should_profile()) {
1724 Register mdo = klass_RInfo, recv = k_RInfo;
1725 __ bind(profile_cast_success);
1726 __ mov_metadata(mdo, md->constant_encoding());
1727 __ load_klass(recv, obj);
1728 Label update_done;
1729 type_profile_helper(mdo, md, data, recv, success);
1730 __ jmp(*success);
1731
1732 __ bind(profile_cast_failure);
1733 __ mov_metadata(mdo, md->constant_encoding());
1734 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1735 __ subptr(counter_addr, DataLayout::counter_increment);
1736 __ jmp(*failure);
1737 }
1738 __ jmp(*success);
1739 }
1740
1741
1742 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1743 LIR_Code code = op->code();
1744 if (code == lir_store_check) {
1745 Register value = op->object()->as_register();
1746 Register array = op->array()->as_register();
1747 Register k_RInfo = op->tmp1()->as_register();
1748 Register klass_RInfo = op->tmp2()->as_register();
1749 Register Rtmp1 = op->tmp3()->as_register();
1750
1751 CodeStub* stub = op->stub();
1752
1753 // check if it needs to be profiled
1754 ciMethodData* md = NULL;
1755 ciProfileData* data = NULL;
1756
1757 if (op->should_profile()) {
1758 ciMethod* method = op->profiled_method();
1759 assert(method != NULL, "Should have method");
1760 int bci = op->profiled_bci();
1761 md = method->method_data_or_null();
1762 assert(md != NULL, "Sanity");
1763 data = md->bci_to_data(bci);
1764 assert(data != NULL, "need data for type check");
1765 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1766 }
1767 Label profile_cast_success, profile_cast_failure, done;
1768 Label *success_target = op->should_profile() ? &profile_cast_success : &done;
1769 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
1770
1771 __ cmpptr(value, (int32_t)NULL_WORD);
1772 if (op->should_profile()) {
1773 Label not_null;
1774 __ jccb(Assembler::notEqual, not_null);
1775 // Object is null; update MDO and exit
1776 Register mdo = klass_RInfo;
1777 __ mov_metadata(mdo, md->constant_encoding());
1778 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
1779 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
1780 __ orl(data_addr, header_bits);
1781 __ jmp(done);
1782 __ bind(not_null);
1783 } else {
1784 __ jcc(Assembler::equal, done);
1785 }
1786
1787 add_debug_info_for_null_check_here(op->info_for_exception());
1788 __ load_klass(k_RInfo, array);
1789 __ load_klass(klass_RInfo, value);
1790
1791 // get instance klass (it's already uncompressed)
1792 __ movptr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1793 // perform the fast part of the checking logic
1794 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1795 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1796 __ push(klass_RInfo);
1797 __ push(k_RInfo);
1798 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1799 __ pop(klass_RInfo);
1800 __ pop(k_RInfo);
1801 // result is a boolean
1802 __ cmpl(k_RInfo, 0);
1803 __ jcc(Assembler::equal, *failure_target);
1804 // fall through to the success case
1805
1806 if (op->should_profile()) {
1807 Register mdo = klass_RInfo, recv = k_RInfo;
1808 __ bind(profile_cast_success);
1809 __ mov_metadata(mdo, md->constant_encoding());
1810 __ load_klass(recv, value);
1811 Label update_done;
1812 type_profile_helper(mdo, md, data, recv, &done);
1813 __ jmpb(done);
1814
1815 __ bind(profile_cast_failure);
1816 __ mov_metadata(mdo, md->constant_encoding());
1817 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1818 __ subptr(counter_addr, DataLayout::counter_increment);
1819 __ jmp(*stub->entry());
1820 }
1821
1822 __ bind(done);
1823 } else
1824 if (code == lir_checkcast) {
1825 Register obj = op->object()->as_register();
1826 Register dst = op->result_opr()->as_register();
1827 Label success;
1828 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1829 __ bind(success);
1830 if (dst != obj) {
1831 __ mov(dst, obj);
1832 }
1833 } else
1834 if (code == lir_instanceof) {
1835 Register obj = op->object()->as_register();
1836 Register dst = op->result_opr()->as_register();
1837 Label success, failure, done;
1838 emit_typecheck_helper(op, &success, &failure, &failure);
1839 __ bind(failure);
1840 __ xorptr(dst, dst);
1841 __ jmpb(done);
1842 __ bind(success);
1843 __ movptr(dst, 1);
1844 __ bind(done);
1845 } else {
1846 ShouldNotReachHere();
1847 }
1848
1849 }
1850
1851
1852 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1853 if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) {
1854 assert(op->cmp_value()->as_register_lo() == rax, "wrong register");
1855 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register");
1856 assert(op->new_value()->as_register_lo() == rbx, "wrong register");
1857 assert(op->new_value()->as_register_hi() == rcx, "wrong register");
1858 Register addr = op->addr()->as_register();
1859 if (os::is_MP()) {
1860 __ lock();
1861 }
1862 NOT_LP64(__ cmpxchg8(Address(addr, 0)));
1863
1864 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) {
1865 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");)
1866 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1867 Register newval = op->new_value()->as_register();
1868 Register cmpval = op->cmp_value()->as_register();
1869 assert(cmpval == rax, "wrong register");
1870 assert(newval != NULL, "new val must be register");
1871 assert(cmpval != newval, "cmp and new values must be in different registers");
1872 assert(cmpval != addr, "cmp and addr must be in different registers");
1873 assert(newval != addr, "new value and addr must be in different registers");
1874
1875 if ( op->code() == lir_cas_obj) {
1876 #ifdef _LP64
1877 if (UseCompressedOops) {
1878 __ encode_heap_oop(cmpval);
1879 __ mov(rscratch1, newval);
1880 __ encode_heap_oop(rscratch1);
1881 if (os::is_MP()) {
1882 __ lock();
1883 }
1884 // cmpval (rax) is implicitly used by this instruction
1885 __ cmpxchgl(rscratch1, Address(addr, 0));
1886 } else
1887 #endif
1888 {
1889 if (os::is_MP()) {
1890 __ lock();
1891 }
1892 __ cmpxchgptr(newval, Address(addr, 0));
1893 }
1894 } else {
1895 assert(op->code() == lir_cas_int, "lir_cas_int expected");
1896 if (os::is_MP()) {
1897 __ lock();
1898 }
1899 __ cmpxchgl(newval, Address(addr, 0));
1900 }
1901 #ifdef _LP64
1902 } else if (op->code() == lir_cas_long) {
1903 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1904 Register newval = op->new_value()->as_register_lo();
1905 Register cmpval = op->cmp_value()->as_register_lo();
1906 assert(cmpval == rax, "wrong register");
1907 assert(newval != NULL, "new val must be register");
1908 assert(cmpval != newval, "cmp and new values must be in different registers");
1909 assert(cmpval != addr, "cmp and addr must be in different registers");
1910 assert(newval != addr, "new value and addr must be in different registers");
1911 if (os::is_MP()) {
1912 __ lock();
1913 }
1914 __ cmpxchgq(newval, Address(addr, 0));
1915 #endif // _LP64
1916 } else {
1917 Unimplemented();
1918 }
1919 }
1920
1921 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1922 Assembler::Condition acond, ncond;
1923 switch (condition) {
1924 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break;
1925 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break;
1926 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break;
1927 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break;
1928 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break;
1929 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break;
1930 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break;
1931 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break;
1932 default: acond = Assembler::equal; ncond = Assembler::notEqual;
1933 ShouldNotReachHere();
1934 }
1935
1936 if (opr1->is_cpu_register()) {
1937 reg2reg(opr1, result);
1938 } else if (opr1->is_stack()) {
1939 stack2reg(opr1, result, result->type());
1940 } else if (opr1->is_constant()) {
1941 const2reg(opr1, result, lir_patch_none, NULL);
1942 } else {
1943 ShouldNotReachHere();
1944 }
1945
1946 if (VM_Version::supports_cmov() && !opr2->is_constant()) {
1947 // optimized version that does not require a branch
1948 if (opr2->is_single_cpu()) {
1949 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
1950 __ cmov(ncond, result->as_register(), opr2->as_register());
1951 } else if (opr2->is_double_cpu()) {
1952 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
1953 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
1954 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo());
1955 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());)
1956 } else if (opr2->is_single_stack()) {
1957 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()));
1958 } else if (opr2->is_double_stack()) {
1959 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes));
1960 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));)
1961 } else {
1962 ShouldNotReachHere();
1963 }
1964
1965 } else {
1966 Label skip;
1967 __ jcc (acond, skip);
1968 if (opr2->is_cpu_register()) {
1969 reg2reg(opr2, result);
1970 } else if (opr2->is_stack()) {
1971 stack2reg(opr2, result, result->type());
1972 } else if (opr2->is_constant()) {
1973 const2reg(opr2, result, lir_patch_none, NULL);
1974 } else {
1975 ShouldNotReachHere();
1976 }
1977 __ bind(skip);
1978 }
1979 }
1980
1981
1982 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
1983 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
1984
1985 if (left->is_single_cpu()) {
1986 assert(left == dest, "left and dest must be equal");
1987 Register lreg = left->as_register();
1988
1989 if (right->is_single_cpu()) {
1990 // cpu register - cpu register
1991 Register rreg = right->as_register();
1992 switch (code) {
1993 case lir_add: __ addl (lreg, rreg); break;
1994 case lir_sub: __ subl (lreg, rreg); break;
1995 case lir_mul: __ imull(lreg, rreg); break;
1996 default: ShouldNotReachHere();
1997 }
1998
1999 } else if (right->is_stack()) {
2000 // cpu register - stack
2001 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2002 switch (code) {
2003 case lir_add: __ addl(lreg, raddr); break;
2004 case lir_sub: __ subl(lreg, raddr); break;
2005 default: ShouldNotReachHere();
2006 }
2007
2008 } else if (right->is_constant()) {
2009 // cpu register - constant
2010 jint c = right->as_constant_ptr()->as_jint();
2011 switch (code) {
2012 case lir_add: {
2013 __ incrementl(lreg, c);
2014 break;
2015 }
2016 case lir_sub: {
2017 __ decrementl(lreg, c);
2018 break;
2019 }
2020 default: ShouldNotReachHere();
2021 }
2022
2023 } else {
2024 ShouldNotReachHere();
2025 }
2026
2027 } else if (left->is_double_cpu()) {
2028 assert(left == dest, "left and dest must be equal");
2029 Register lreg_lo = left->as_register_lo();
2030 Register lreg_hi = left->as_register_hi();
2031
2032 if (right->is_double_cpu()) {
2033 // cpu register - cpu register
2034 Register rreg_lo = right->as_register_lo();
2035 Register rreg_hi = right->as_register_hi();
2036 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi));
2037 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo));
2038 switch (code) {
2039 case lir_add:
2040 __ addptr(lreg_lo, rreg_lo);
2041 NOT_LP64(__ adcl(lreg_hi, rreg_hi));
2042 break;
2043 case lir_sub:
2044 __ subptr(lreg_lo, rreg_lo);
2045 NOT_LP64(__ sbbl(lreg_hi, rreg_hi));
2046 break;
2047 case lir_mul:
2048 #ifdef _LP64
2049 __ imulq(lreg_lo, rreg_lo);
2050 #else
2051 assert(lreg_lo == rax && lreg_hi == rdx, "must be");
2052 __ imull(lreg_hi, rreg_lo);
2053 __ imull(rreg_hi, lreg_lo);
2054 __ addl (rreg_hi, lreg_hi);
2055 __ mull (rreg_lo);
2056 __ addl (lreg_hi, rreg_hi);
2057 #endif // _LP64
2058 break;
2059 default:
2060 ShouldNotReachHere();
2061 }
2062
2063 } else if (right->is_constant()) {
2064 // cpu register - constant
2065 #ifdef _LP64
2066 jlong c = right->as_constant_ptr()->as_jlong_bits();
2067 __ movptr(r10, (intptr_t) c);
2068 switch (code) {
2069 case lir_add:
2070 __ addptr(lreg_lo, r10);
2071 break;
2072 case lir_sub:
2073 __ subptr(lreg_lo, r10);
2074 break;
2075 default:
2076 ShouldNotReachHere();
2077 }
2078 #else
2079 jint c_lo = right->as_constant_ptr()->as_jint_lo();
2080 jint c_hi = right->as_constant_ptr()->as_jint_hi();
2081 switch (code) {
2082 case lir_add:
2083 __ addptr(lreg_lo, c_lo);
2084 __ adcl(lreg_hi, c_hi);
2085 break;
2086 case lir_sub:
2087 __ subptr(lreg_lo, c_lo);
2088 __ sbbl(lreg_hi, c_hi);
2089 break;
2090 default:
2091 ShouldNotReachHere();
2092 }
2093 #endif // _LP64
2094
2095 } else {
2096 ShouldNotReachHere();
2097 }
2098
2099 } else if (left->is_single_xmm()) {
2100 assert(left == dest, "left and dest must be equal");
2101 XMMRegister lreg = left->as_xmm_float_reg();
2102
2103 if (right->is_single_xmm()) {
2104 XMMRegister rreg = right->as_xmm_float_reg();
2105 switch (code) {
2106 case lir_add: __ addss(lreg, rreg); break;
2107 case lir_sub: __ subss(lreg, rreg); break;
2108 case lir_mul_strictfp: // fall through
2109 case lir_mul: __ mulss(lreg, rreg); break;
2110 case lir_div_strictfp: // fall through
2111 case lir_div: __ divss(lreg, rreg); break;
2112 default: ShouldNotReachHere();
2113 }
2114 } else {
2115 Address raddr;
2116 if (right->is_single_stack()) {
2117 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2118 } else if (right->is_constant()) {
2119 // hack for now
2120 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat())));
2121 } else {
2122 ShouldNotReachHere();
2123 }
2124 switch (code) {
2125 case lir_add: __ addss(lreg, raddr); break;
2126 case lir_sub: __ subss(lreg, raddr); break;
2127 case lir_mul_strictfp: // fall through
2128 case lir_mul: __ mulss(lreg, raddr); break;
2129 case lir_div_strictfp: // fall through
2130 case lir_div: __ divss(lreg, raddr); break;
2131 default: ShouldNotReachHere();
2132 }
2133 }
2134
2135 } else if (left->is_double_xmm()) {
2136 assert(left == dest, "left and dest must be equal");
2137
2138 XMMRegister lreg = left->as_xmm_double_reg();
2139 if (right->is_double_xmm()) {
2140 XMMRegister rreg = right->as_xmm_double_reg();
2141 switch (code) {
2142 case lir_add: __ addsd(lreg, rreg); break;
2143 case lir_sub: __ subsd(lreg, rreg); break;
2144 case lir_mul_strictfp: // fall through
2145 case lir_mul: __ mulsd(lreg, rreg); break;
2146 case lir_div_strictfp: // fall through
2147 case lir_div: __ divsd(lreg, rreg); break;
2148 default: ShouldNotReachHere();
2149 }
2150 } else {
2151 Address raddr;
2152 if (right->is_double_stack()) {
2153 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2154 } else if (right->is_constant()) {
2155 // hack for now
2156 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2157 } else {
2158 ShouldNotReachHere();
2159 }
2160 switch (code) {
2161 case lir_add: __ addsd(lreg, raddr); break;
2162 case lir_sub: __ subsd(lreg, raddr); break;
2163 case lir_mul_strictfp: // fall through
2164 case lir_mul: __ mulsd(lreg, raddr); break;
2165 case lir_div_strictfp: // fall through
2166 case lir_div: __ divsd(lreg, raddr); break;
2167 default: ShouldNotReachHere();
2168 }
2169 }
2170
2171 } else if (left->is_single_fpu()) {
2172 assert(dest->is_single_fpu(), "fpu stack allocation required");
2173
2174 if (right->is_single_fpu()) {
2175 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack);
2176
2177 } else {
2178 assert(left->fpu_regnr() == 0, "left must be on TOS");
2179 assert(dest->fpu_regnr() == 0, "dest must be on TOS");
2180
2181 Address raddr;
2182 if (right->is_single_stack()) {
2183 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2184 } else if (right->is_constant()) {
2185 address const_addr = float_constant(right->as_jfloat());
2186 assert(const_addr != NULL, "incorrect float/double constant maintainance");
2187 // hack for now
2188 raddr = __ as_Address(InternalAddress(const_addr));
2189 } else {
2190 ShouldNotReachHere();
2191 }
2192
2193 switch (code) {
2194 case lir_add: __ fadd_s(raddr); break;
2195 case lir_sub: __ fsub_s(raddr); break;
2196 case lir_mul_strictfp: // fall through
2197 case lir_mul: __ fmul_s(raddr); break;
2198 case lir_div_strictfp: // fall through
2199 case lir_div: __ fdiv_s(raddr); break;
2200 default: ShouldNotReachHere();
2201 }
2202 }
2203
2204 } else if (left->is_double_fpu()) {
2205 assert(dest->is_double_fpu(), "fpu stack allocation required");
2206
2207 if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2208 // Double values require special handling for strictfp mul/div on x86
2209 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias1()));
2210 __ fmulp(left->fpu_regnrLo() + 1);
2211 }
2212
2213 if (right->is_double_fpu()) {
2214 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack);
2215
2216 } else {
2217 assert(left->fpu_regnrLo() == 0, "left must be on TOS");
2218 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS");
2219
2220 Address raddr;
2221 if (right->is_double_stack()) {
2222 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2223 } else if (right->is_constant()) {
2224 // hack for now
2225 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2226 } else {
2227 ShouldNotReachHere();
2228 }
2229
2230 switch (code) {
2231 case lir_add: __ fadd_d(raddr); break;
2232 case lir_sub: __ fsub_d(raddr); break;
2233 case lir_mul_strictfp: // fall through
2234 case lir_mul: __ fmul_d(raddr); break;
2235 case lir_div_strictfp: // fall through
2236 case lir_div: __ fdiv_d(raddr); break;
2237 default: ShouldNotReachHere();
2238 }
2239 }
2240
2241 if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2242 // Double values require special handling for strictfp mul/div on x86
2243 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2()));
2244 __ fmulp(dest->fpu_regnrLo() + 1);
2245 }
2246
2247 } else if (left->is_single_stack() || left->is_address()) {
2248 assert(left == dest, "left and dest must be equal");
2249
2250 Address laddr;
2251 if (left->is_single_stack()) {
2252 laddr = frame_map()->address_for_slot(left->single_stack_ix());
2253 } else if (left->is_address()) {
2254 laddr = as_Address(left->as_address_ptr());
2255 } else {
2256 ShouldNotReachHere();
2257 }
2258
2259 if (right->is_single_cpu()) {
2260 Register rreg = right->as_register();
2261 switch (code) {
2262 case lir_add: __ addl(laddr, rreg); break;
2263 case lir_sub: __ subl(laddr, rreg); break;
2264 default: ShouldNotReachHere();
2265 }
2266 } else if (right->is_constant()) {
2267 jint c = right->as_constant_ptr()->as_jint();
2268 switch (code) {
2269 case lir_add: {
2270 __ incrementl(laddr, c);
2271 break;
2272 }
2273 case lir_sub: {
2274 __ decrementl(laddr, c);
2275 break;
2276 }
2277 default: ShouldNotReachHere();
2278 }
2279 } else {
2280 ShouldNotReachHere();
2281 }
2282
2283 } else {
2284 ShouldNotReachHere();
2285 }
2286 }
2287
2288 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) {
2289 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR");
2290 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR");
2291 assert(left_index == 0 || right_index == 0, "either must be on top of stack");
2292
2293 bool left_is_tos = (left_index == 0);
2294 bool dest_is_tos = (dest_index == 0);
2295 int non_tos_index = (left_is_tos ? right_index : left_index);
2296
2297 switch (code) {
2298 case lir_add:
2299 if (pop_fpu_stack) __ faddp(non_tos_index);
2300 else if (dest_is_tos) __ fadd (non_tos_index);
2301 else __ fadda(non_tos_index);
2302 break;
2303
2304 case lir_sub:
2305 if (left_is_tos) {
2306 if (pop_fpu_stack) __ fsubrp(non_tos_index);
2307 else if (dest_is_tos) __ fsub (non_tos_index);
2308 else __ fsubra(non_tos_index);
2309 } else {
2310 if (pop_fpu_stack) __ fsubp (non_tos_index);
2311 else if (dest_is_tos) __ fsubr (non_tos_index);
2312 else __ fsuba (non_tos_index);
2313 }
2314 break;
2315
2316 case lir_mul_strictfp: // fall through
2317 case lir_mul:
2318 if (pop_fpu_stack) __ fmulp(non_tos_index);
2319 else if (dest_is_tos) __ fmul (non_tos_index);
2320 else __ fmula(non_tos_index);
2321 break;
2322
2323 case lir_div_strictfp: // fall through
2324 case lir_div:
2325 if (left_is_tos) {
2326 if (pop_fpu_stack) __ fdivrp(non_tos_index);
2327 else if (dest_is_tos) __ fdiv (non_tos_index);
2328 else __ fdivra(non_tos_index);
2329 } else {
2330 if (pop_fpu_stack) __ fdivp (non_tos_index);
2331 else if (dest_is_tos) __ fdivr (non_tos_index);
2332 else __ fdiva (non_tos_index);
2333 }
2334 break;
2335
2336 case lir_rem:
2337 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation");
2338 __ fremr(noreg);
2339 break;
2340
2341 default:
2342 ShouldNotReachHere();
2343 }
2344 }
2345
2346
2347 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) {
2348 if (value->is_double_xmm()) {
2349 switch(code) {
2350 case lir_abs :
2351 {
2352 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) {
2353 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg());
2354 }
2355 __ andpd(dest->as_xmm_double_reg(),
2356 ExternalAddress((address)double_signmask_pool));
2357 }
2358 break;
2359
2360 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break;
2361 // all other intrinsics are not available in the SSE instruction set, so FPU is used
2362 default : ShouldNotReachHere();
2363 }
2364
2365 } else if (value->is_double_fpu()) {
2366 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS");
2367 switch(code) {
2368 case lir_log10 : __ flog10() ; break;
2369 case lir_abs : __ fabs() ; break;
2370 case lir_sqrt : __ fsqrt(); break;
2371 case lir_sin :
2372 // Should consider not saving rbx, if not necessary
2373 __ trigfunc('s', op->as_Op2()->fpu_stack_size());
2374 break;
2375 case lir_cos :
2376 // Should consider not saving rbx, if not necessary
2377 assert(op->as_Op2()->fpu_stack_size() <= 6, "sin and cos need two free stack slots");
2378 __ trigfunc('c', op->as_Op2()->fpu_stack_size());
2379 break;
2380 case lir_tan :
2381 // Should consider not saving rbx, if not necessary
2382 __ trigfunc('t', op->as_Op2()->fpu_stack_size());
2383 break;
2384 default : ShouldNotReachHere();
2385 }
2386 } else {
2387 Unimplemented();
2388 }
2389 }
2390
2391 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
2392 // assert(left->destroys_register(), "check");
2393 if (left->is_single_cpu()) {
2394 Register reg = left->as_register();
2395 if (right->is_constant()) {
2396 int val = right->as_constant_ptr()->as_jint();
2397 switch (code) {
2398 case lir_logic_and: __ andl (reg, val); break;
2399 case lir_logic_or: __ orl (reg, val); break;
2400 case lir_logic_xor: __ xorl (reg, val); break;
2401 default: ShouldNotReachHere();
2402 }
2403 } else if (right->is_stack()) {
2404 // added support for stack operands
2405 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2406 switch (code) {
2407 case lir_logic_and: __ andl (reg, raddr); break;
2408 case lir_logic_or: __ orl (reg, raddr); break;
2409 case lir_logic_xor: __ xorl (reg, raddr); break;
2410 default: ShouldNotReachHere();
2411 }
2412 } else {
2413 Register rright = right->as_register();
2414 switch (code) {
2415 case lir_logic_and: __ andptr (reg, rright); break;
2416 case lir_logic_or : __ orptr (reg, rright); break;
2417 case lir_logic_xor: __ xorptr (reg, rright); break;
2418 default: ShouldNotReachHere();
2419 }
2420 }
2421 move_regs(reg, dst->as_register());
2422 } else {
2423 Register l_lo = left->as_register_lo();
2424 Register l_hi = left->as_register_hi();
2425 if (right->is_constant()) {
2426 #ifdef _LP64
2427 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong());
2428 switch (code) {
2429 case lir_logic_and:
2430 __ andq(l_lo, rscratch1);
2431 break;
2432 case lir_logic_or:
2433 __ orq(l_lo, rscratch1);
2434 break;
2435 case lir_logic_xor:
2436 __ xorq(l_lo, rscratch1);
2437 break;
2438 default: ShouldNotReachHere();
2439 }
2440 #else
2441 int r_lo = right->as_constant_ptr()->as_jint_lo();
2442 int r_hi = right->as_constant_ptr()->as_jint_hi();
2443 switch (code) {
2444 case lir_logic_and:
2445 __ andl(l_lo, r_lo);
2446 __ andl(l_hi, r_hi);
2447 break;
2448 case lir_logic_or:
2449 __ orl(l_lo, r_lo);
2450 __ orl(l_hi, r_hi);
2451 break;
2452 case lir_logic_xor:
2453 __ xorl(l_lo, r_lo);
2454 __ xorl(l_hi, r_hi);
2455 break;
2456 default: ShouldNotReachHere();
2457 }
2458 #endif // _LP64
2459 } else {
2460 #ifdef _LP64
2461 Register r_lo;
2462 if (right->type() == T_OBJECT || right->type() == T_ARRAY) {
2463 r_lo = right->as_register();
2464 } else {
2465 r_lo = right->as_register_lo();
2466 }
2467 #else
2468 Register r_lo = right->as_register_lo();
2469 Register r_hi = right->as_register_hi();
2470 assert(l_lo != r_hi, "overwriting registers");
2471 #endif
2472 switch (code) {
2473 case lir_logic_and:
2474 __ andptr(l_lo, r_lo);
2475 NOT_LP64(__ andptr(l_hi, r_hi);)
2476 break;
2477 case lir_logic_or:
2478 __ orptr(l_lo, r_lo);
2479 NOT_LP64(__ orptr(l_hi, r_hi);)
2480 break;
2481 case lir_logic_xor:
2482 __ xorptr(l_lo, r_lo);
2483 NOT_LP64(__ xorptr(l_hi, r_hi);)
2484 break;
2485 default: ShouldNotReachHere();
2486 }
2487 }
2488
2489 Register dst_lo = dst->as_register_lo();
2490 Register dst_hi = dst->as_register_hi();
2491
2492 #ifdef _LP64
2493 move_regs(l_lo, dst_lo);
2494 #else
2495 if (dst_lo == l_hi) {
2496 assert(dst_hi != l_lo, "overwriting registers");
2497 move_regs(l_hi, dst_hi);
2498 move_regs(l_lo, dst_lo);
2499 } else {
2500 assert(dst_lo != l_hi, "overwriting registers");
2501 move_regs(l_lo, dst_lo);
2502 move_regs(l_hi, dst_hi);
2503 }
2504 #endif // _LP64
2505 }
2506 }
2507
2508
2509 // we assume that rax, and rdx can be overwritten
2510 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
2511
2512 assert(left->is_single_cpu(), "left must be register");
2513 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
2514 assert(result->is_single_cpu(), "result must be register");
2515
2516 // assert(left->destroys_register(), "check");
2517 // assert(right->destroys_register(), "check");
2518
2519 Register lreg = left->as_register();
2520 Register dreg = result->as_register();
2521
2522 if (right->is_constant()) {
2523 int divisor = right->as_constant_ptr()->as_jint();
2524 assert(divisor > 0 && is_power_of_2(divisor), "must be");
2525 if (code == lir_idiv) {
2526 assert(lreg == rax, "must be rax,");
2527 assert(temp->as_register() == rdx, "tmp register must be rdx");
2528 __ cdql(); // sign extend into rdx:rax
2529 if (divisor == 2) {
2530 __ subl(lreg, rdx);
2531 } else {
2532 __ andl(rdx, divisor - 1);
2533 __ addl(lreg, rdx);
2534 }
2535 __ sarl(lreg, log2_intptr(divisor));
2536 move_regs(lreg, dreg);
2537 } else if (code == lir_irem) {
2538 Label done;
2539 __ mov(dreg, lreg);
2540 __ andl(dreg, 0x80000000 | (divisor - 1));
2541 __ jcc(Assembler::positive, done);
2542 __ decrement(dreg);
2543 __ orl(dreg, ~(divisor - 1));
2544 __ increment(dreg);
2545 __ bind(done);
2546 } else {
2547 ShouldNotReachHere();
2548 }
2549 } else {
2550 Register rreg = right->as_register();
2551 assert(lreg == rax, "left register must be rax,");
2552 assert(rreg != rdx, "right register must not be rdx");
2553 assert(temp->as_register() == rdx, "tmp register must be rdx");
2554
2555 move_regs(lreg, rax);
2556
2557 int idivl_offset = __ corrected_idivl(rreg);
2558 add_debug_info_for_div0(idivl_offset, info);
2559 if (code == lir_irem) {
2560 move_regs(rdx, dreg); // result is in rdx
2561 } else {
2562 move_regs(rax, dreg);
2563 }
2564 }
2565 }
2566
2567
2568 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2569 if (opr1->is_single_cpu()) {
2570 Register reg1 = opr1->as_register();
2571 if (opr2->is_single_cpu()) {
2572 // cpu register - cpu register
2573 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2574 __ cmpptr(reg1, opr2->as_register());
2575 } else {
2576 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?");
2577 __ cmpl(reg1, opr2->as_register());
2578 }
2579 } else if (opr2->is_stack()) {
2580 // cpu register - stack
2581 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2582 __ cmpptr(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2583 } else {
2584 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2585 }
2586 } else if (opr2->is_constant()) {
2587 // cpu register - constant
2588 LIR_Const* c = opr2->as_constant_ptr();
2589 if (c->type() == T_INT) {
2590 __ cmpl(reg1, c->as_jint());
2591 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2592 // In 64bit oops are single register
2593 jobject o = c->as_jobject();
2594 if (o == NULL) {
2595 __ cmpptr(reg1, (int32_t)NULL_WORD);
2596 } else {
2597 #ifdef _LP64
2598 __ movoop(rscratch1, o);
2599 __ cmpptr(reg1, rscratch1);
2600 #else
2601 __ cmpoop(reg1, c->as_jobject());
2602 #endif // _LP64
2603 }
2604 } else {
2605 fatal("unexpected type: %s", basictype_to_str(c->type()));
2606 }
2607 // cpu register - address
2608 } else if (opr2->is_address()) {
2609 if (op->info() != NULL) {
2610 add_debug_info_for_null_check_here(op->info());
2611 }
2612 __ cmpl(reg1, as_Address(opr2->as_address_ptr()));
2613 } else {
2614 ShouldNotReachHere();
2615 }
2616
2617 } else if(opr1->is_double_cpu()) {
2618 Register xlo = opr1->as_register_lo();
2619 Register xhi = opr1->as_register_hi();
2620 if (opr2->is_double_cpu()) {
2621 #ifdef _LP64
2622 __ cmpptr(xlo, opr2->as_register_lo());
2623 #else
2624 // cpu register - cpu register
2625 Register ylo = opr2->as_register_lo();
2626 Register yhi = opr2->as_register_hi();
2627 __ subl(xlo, ylo);
2628 __ sbbl(xhi, yhi);
2629 if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
2630 __ orl(xhi, xlo);
2631 }
2632 #endif // _LP64
2633 } else if (opr2->is_constant()) {
2634 // cpu register - constant 0
2635 assert(opr2->as_jlong() == (jlong)0, "only handles zero");
2636 #ifdef _LP64
2637 __ cmpptr(xlo, (int32_t)opr2->as_jlong());
2638 #else
2639 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case");
2640 __ orl(xhi, xlo);
2641 #endif // _LP64
2642 } else {
2643 ShouldNotReachHere();
2644 }
2645
2646 } else if (opr1->is_single_xmm()) {
2647 XMMRegister reg1 = opr1->as_xmm_float_reg();
2648 if (opr2->is_single_xmm()) {
2649 // xmm register - xmm register
2650 __ ucomiss(reg1, opr2->as_xmm_float_reg());
2651 } else if (opr2->is_stack()) {
2652 // xmm register - stack
2653 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2654 } else if (opr2->is_constant()) {
2655 // xmm register - constant
2656 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat())));
2657 } else if (opr2->is_address()) {
2658 // xmm register - address
2659 if (op->info() != NULL) {
2660 add_debug_info_for_null_check_here(op->info());
2661 }
2662 __ ucomiss(reg1, as_Address(opr2->as_address_ptr()));
2663 } else {
2664 ShouldNotReachHere();
2665 }
2666
2667 } else if (opr1->is_double_xmm()) {
2668 XMMRegister reg1 = opr1->as_xmm_double_reg();
2669 if (opr2->is_double_xmm()) {
2670 // xmm register - xmm register
2671 __ ucomisd(reg1, opr2->as_xmm_double_reg());
2672 } else if (opr2->is_stack()) {
2673 // xmm register - stack
2674 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix()));
2675 } else if (opr2->is_constant()) {
2676 // xmm register - constant
2677 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble())));
2678 } else if (opr2->is_address()) {
2679 // xmm register - address
2680 if (op->info() != NULL) {
2681 add_debug_info_for_null_check_here(op->info());
2682 }
2683 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address()));
2684 } else {
2685 ShouldNotReachHere();
2686 }
2687
2688 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) {
2689 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)");
2690 assert(opr2->is_fpu_register(), "both must be registers");
2691 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2692
2693 } else if (opr1->is_address() && opr2->is_constant()) {
2694 LIR_Const* c = opr2->as_constant_ptr();
2695 #ifdef _LP64
2696 if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2697 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse");
2698 __ movoop(rscratch1, c->as_jobject());
2699 }
2700 #endif // LP64
2701 if (op->info() != NULL) {
2702 add_debug_info_for_null_check_here(op->info());
2703 }
2704 // special case: address - constant
2705 LIR_Address* addr = opr1->as_address_ptr();
2706 if (c->type() == T_INT) {
2707 __ cmpl(as_Address(addr), c->as_jint());
2708 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2709 #ifdef _LP64
2710 // %%% Make this explode if addr isn't reachable until we figure out a
2711 // better strategy by giving noreg as the temp for as_Address
2712 __ cmpptr(rscratch1, as_Address(addr, noreg));
2713 #else
2714 __ cmpoop(as_Address(addr), c->as_jobject());
2715 #endif // _LP64
2716 } else {
2717 ShouldNotReachHere();
2718 }
2719
2720 } else {
2721 ShouldNotReachHere();
2722 }
2723 }
2724
2725 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
2726 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2727 if (left->is_single_xmm()) {
2728 assert(right->is_single_xmm(), "must match");
2729 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2730 } else if (left->is_double_xmm()) {
2731 assert(right->is_double_xmm(), "must match");
2732 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2733
2734 } else {
2735 assert(left->is_single_fpu() || left->is_double_fpu(), "must be");
2736 assert(right->is_single_fpu() || right->is_double_fpu(), "must match");
2737
2738 assert(left->fpu() == 0, "left must be on TOS");
2739 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(),
2740 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2741 }
2742 } else {
2743 assert(code == lir_cmp_l2i, "check");
2744 #ifdef _LP64
2745 Label done;
2746 Register dest = dst->as_register();
2747 __ cmpptr(left->as_register_lo(), right->as_register_lo());
2748 __ movl(dest, -1);
2749 __ jccb(Assembler::less, done);
2750 __ set_byte_if_not_zero(dest);
2751 __ movzbl(dest, dest);
2752 __ bind(done);
2753 #else
2754 __ lcmp2int(left->as_register_hi(),
2755 left->as_register_lo(),
2756 right->as_register_hi(),
2757 right->as_register_lo());
2758 move_regs(left->as_register_hi(), dst->as_register());
2759 #endif // _LP64
2760 }
2761 }
2762
2763
2764 void LIR_Assembler::align_call(LIR_Code code) {
2765 if (os::is_MP()) {
2766 // make sure that the displacement word of the call ends up word aligned
2767 int offset = __ offset();
2768 switch (code) {
2769 case lir_static_call:
2770 case lir_optvirtual_call:
2771 case lir_dynamic_call:
2772 offset += NativeCall::displacement_offset;
2773 break;
2774 case lir_icvirtual_call:
2775 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size;
2776 break;
2777 case lir_virtual_call: // currently, sparc-specific for niagara
2778 default: ShouldNotReachHere();
2779 }
2780 __ align(BytesPerWord, offset);
2781 }
2782 }
2783
2784
2785 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2786 assert(!os::is_MP() || (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0,
2787 "must be aligned");
2788 __ call(AddressLiteral(op->addr(), rtype));
2789 add_call_info(code_offset(), op->info());
2790 }
2791
2792
2793 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2794 __ ic_call(op->addr());
2795 add_call_info(code_offset(), op->info());
2796 assert(!os::is_MP() ||
2797 (__ offset() - NativeCall::instruction_size + NativeCall::displacement_offset) % BytesPerWord == 0,
2798 "must be aligned");
2799 }
2800
2801
2802 /* Currently, vtable-dispatch is only enabled for sparc platforms */
2803 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
2804 ShouldNotReachHere();
2805 }
2806
2807
2808 void LIR_Assembler::emit_static_call_stub() {
2809 address call_pc = __ pc();
2810 address stub = __ start_a_stub(call_stub_size);
2811 if (stub == NULL) {
2812 bailout("static call stub overflow");
2813 return;
2814 }
2815
2816 int start = __ offset();
2817 if (os::is_MP()) {
2818 // make sure that the displacement word of the call ends up word aligned
2819 __ align(BytesPerWord, __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset);
2820 }
2821 __ relocate(static_stub_Relocation::spec(call_pc));
2822 __ mov_metadata(rbx, (Metadata*)NULL);
2823 // must be set to -1 at code generation time
2824 assert(!os::is_MP() || ((__ offset() + 1) % BytesPerWord) == 0, "must be aligned on MP");
2825 // On 64bit this will die since it will take a movq & jmp, must be only a jmp
2826 __ jump(RuntimeAddress(__ pc()));
2827
2828 assert(__ offset() - start <= call_stub_size, "stub too big");
2829 __ end_a_stub();
2830 }
2831
2832
2833 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2834 assert(exceptionOop->as_register() == rax, "must match");
2835 assert(exceptionPC->as_register() == rdx, "must match");
2836
2837 // exception object is not added to oop map by LinearScan
2838 // (LinearScan assumes that no oops are in fixed registers)
2839 info->add_register_oop(exceptionOop);
2840 Runtime1::StubID unwind_id;
2841
2842 // get current pc information
2843 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2844 int pc_for_athrow_offset = __ offset();
2845 InternalAddress pc_for_athrow(__ pc());
2846 __ lea(exceptionPC->as_register(), pc_for_athrow);
2847 add_call_info(pc_for_athrow_offset, info); // for exception handler
2848
2849 __ verify_not_null_oop(rax);
2850 // search an exception handler (rax: exception oop, rdx: throwing pc)
2851 if (compilation()->has_fpu_code()) {
2852 unwind_id = Runtime1::handle_exception_id;
2853 } else {
2854 unwind_id = Runtime1::handle_exception_nofpu_id;
2855 }
2856 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2857
2858 // enough room for two byte trap
2859 __ nop();
2860 }
2861
2862
2863 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2864 assert(exceptionOop->as_register() == rax, "must match");
2865
2866 __ jmp(_unwind_handler_entry);
2867 }
2868
2869
2870 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2871
2872 // optimized version for linear scan:
2873 // * count must be already in ECX (guaranteed by LinearScan)
2874 // * left and dest must be equal
2875 // * tmp must be unused
2876 assert(count->as_register() == SHIFT_count, "count must be in ECX");
2877 assert(left == dest, "left and dest must be equal");
2878 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2879
2880 if (left->is_single_cpu()) {
2881 Register value = left->as_register();
2882 assert(value != SHIFT_count, "left cannot be ECX");
2883
2884 switch (code) {
2885 case lir_shl: __ shll(value); break;
2886 case lir_shr: __ sarl(value); break;
2887 case lir_ushr: __ shrl(value); break;
2888 default: ShouldNotReachHere();
2889 }
2890 } else if (left->is_double_cpu()) {
2891 Register lo = left->as_register_lo();
2892 Register hi = left->as_register_hi();
2893 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX");
2894 #ifdef _LP64
2895 switch (code) {
2896 case lir_shl: __ shlptr(lo); break;
2897 case lir_shr: __ sarptr(lo); break;
2898 case lir_ushr: __ shrptr(lo); break;
2899 default: ShouldNotReachHere();
2900 }
2901 #else
2902
2903 switch (code) {
2904 case lir_shl: __ lshl(hi, lo); break;
2905 case lir_shr: __ lshr(hi, lo, true); break;
2906 case lir_ushr: __ lshr(hi, lo, false); break;
2907 default: ShouldNotReachHere();
2908 }
2909 #endif // LP64
2910 } else {
2911 ShouldNotReachHere();
2912 }
2913 }
2914
2915
2916 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2917 if (dest->is_single_cpu()) {
2918 // first move left into dest so that left is not destroyed by the shift
2919 Register value = dest->as_register();
2920 count = count & 0x1F; // Java spec
2921
2922 move_regs(left->as_register(), value);
2923 switch (code) {
2924 case lir_shl: __ shll(value, count); break;
2925 case lir_shr: __ sarl(value, count); break;
2926 case lir_ushr: __ shrl(value, count); break;
2927 default: ShouldNotReachHere();
2928 }
2929 } else if (dest->is_double_cpu()) {
2930 #ifndef _LP64
2931 Unimplemented();
2932 #else
2933 // first move left into dest so that left is not destroyed by the shift
2934 Register value = dest->as_register_lo();
2935 count = count & 0x1F; // Java spec
2936
2937 move_regs(left->as_register_lo(), value);
2938 switch (code) {
2939 case lir_shl: __ shlptr(value, count); break;
2940 case lir_shr: __ sarptr(value, count); break;
2941 case lir_ushr: __ shrptr(value, count); break;
2942 default: ShouldNotReachHere();
2943 }
2944 #endif // _LP64
2945 } else {
2946 ShouldNotReachHere();
2947 }
2948 }
2949
2950
2951 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
2952 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2953 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2954 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2955 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r);
2956 }
2957
2958
2959 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
2960 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2961 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2962 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2963 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c);
2964 }
2965
2966
2967 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
2968 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2969 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2970 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2971 __ movoop (Address(rsp, offset_from_rsp_in_bytes), o);
2972 }
2973
2974
2975 void LIR_Assembler::store_parameter(Metadata* m, int offset_from_rsp_in_words) {
2976 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2977 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2978 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2979 __ mov_metadata(Address(rsp, offset_from_rsp_in_bytes), m);
2980 }
2981
2982
2983 // This code replaces a call to arraycopy; no exception may
2984 // be thrown in this code, they must be thrown in the System.arraycopy
2985 // activation frame; we could save some checks if this would not be the case
2986 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2987 ciArrayKlass* default_type = op->expected_type();
2988 Register src = op->src()->as_register();
2989 Register dst = op->dst()->as_register();
2990 Register src_pos = op->src_pos()->as_register();
2991 Register dst_pos = op->dst_pos()->as_register();
2992 Register length = op->length()->as_register();
2993 Register tmp = op->tmp()->as_register();
2994
2995 CodeStub* stub = op->stub();
2996 int flags = op->flags();
2997 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
2998 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
2999
3000 // if we don't know anything, just go through the generic arraycopy
3001 if (default_type == NULL) {
3002 Label done;
3003 // save outgoing arguments on stack in case call to System.arraycopy is needed
3004 // HACK ALERT. This code used to push the parameters in a hardwired fashion
3005 // for interpreter calling conventions. Now we have to do it in new style conventions.
3006 // For the moment until C1 gets the new register allocator I just force all the
3007 // args to the right place (except the register args) and then on the back side
3008 // reload the register args properly if we go slow path. Yuck
3009
3010 // These are proper for the calling convention
3011 store_parameter(length, 2);
3012 store_parameter(dst_pos, 1);
3013 store_parameter(dst, 0);
3014
3015 // these are just temporary placements until we need to reload
3016 store_parameter(src_pos, 3);
3017 store_parameter(src, 4);
3018 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");)
3019
3020 address C_entry = CAST_FROM_FN_PTR(address, Runtime1::arraycopy);
3021
3022 address copyfunc_addr = StubRoutines::generic_arraycopy();
3023
3024 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint
3025 #ifdef _LP64
3026 // The arguments are in java calling convention so we can trivially shift them to C
3027 // convention
3028 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
3029 __ mov(c_rarg0, j_rarg0);
3030 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
3031 __ mov(c_rarg1, j_rarg1);
3032 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
3033 __ mov(c_rarg2, j_rarg2);
3034 assert_different_registers(c_rarg3, j_rarg4);
3035 __ mov(c_rarg3, j_rarg3);
3036 #ifdef _WIN64
3037 // Allocate abi space for args but be sure to keep stack aligned
3038 __ subptr(rsp, 6*wordSize);
3039 store_parameter(j_rarg4, 4);
3040 if (copyfunc_addr == NULL) { // Use C version if stub was not generated
3041 __ call(RuntimeAddress(C_entry));
3042 } else {
3043 #ifndef PRODUCT
3044 if (PrintC1Statistics) {
3045 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3046 }
3047 #endif
3048 __ call(RuntimeAddress(copyfunc_addr));
3049 }
3050 __ addptr(rsp, 6*wordSize);
3051 #else
3052 __ mov(c_rarg4, j_rarg4);
3053 if (copyfunc_addr == NULL) { // Use C version if stub was not generated
3054 __ call(RuntimeAddress(C_entry));
3055 } else {
3056 #ifndef PRODUCT
3057 if (PrintC1Statistics) {
3058 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3059 }
3060 #endif
3061 __ call(RuntimeAddress(copyfunc_addr));
3062 }
3063 #endif // _WIN64
3064 #else
3065 __ push(length);
3066 __ push(dst_pos);
3067 __ push(dst);
3068 __ push(src_pos);
3069 __ push(src);
3070
3071 if (copyfunc_addr == NULL) { // Use C version if stub was not generated
3072 __ call_VM_leaf(C_entry, 5); // removes pushed parameter from the stack
3073 } else {
3074 #ifndef PRODUCT
3075 if (PrintC1Statistics) {
3076 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3077 }
3078 #endif
3079 __ call_VM_leaf(copyfunc_addr, 5); // removes pushed parameter from the stack
3080 }
3081
3082 #endif // _LP64
3083
3084 __ cmpl(rax, 0);
3085 __ jcc(Assembler::equal, *stub->continuation());
3086
3087 if (copyfunc_addr != NULL) {
3088 __ mov(tmp, rax);
3089 __ xorl(tmp, -1);
3090 }
3091
3092 // Reload values from the stack so they are where the stub
3093 // expects them.
3094 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3095 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3096 __ movptr (length, Address(rsp, 2*BytesPerWord));
3097 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3098 __ movptr (src, Address(rsp, 4*BytesPerWord));
3099
3100 if (copyfunc_addr != NULL) {
3101 __ subl(length, tmp);
3102 __ addl(src_pos, tmp);
3103 __ addl(dst_pos, tmp);
3104 }
3105 __ jmp(*stub->entry());
3106
3107 __ bind(*stub->continuation());
3108 return;
3109 }
3110
3111 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
3112
3113 int elem_size = type2aelembytes(basic_type);
3114 Address::ScaleFactor scale;
3115
3116 switch (elem_size) {
3117 case 1 :
3118 scale = Address::times_1;
3119 break;
3120 case 2 :
3121 scale = Address::times_2;
3122 break;
3123 case 4 :
3124 scale = Address::times_4;
3125 break;
3126 case 8 :
3127 scale = Address::times_8;
3128 break;
3129 default:
3130 scale = Address::no_scale;
3131 ShouldNotReachHere();
3132 }
3133
3134 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
3135 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
3136 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
3137 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
3138
3139 // length and pos's are all sign extended at this point on 64bit
3140
3141 // test for NULL
3142 if (flags & LIR_OpArrayCopy::src_null_check) {
3143 __ testptr(src, src);
3144 __ jcc(Assembler::zero, *stub->entry());
3145 }
3146 if (flags & LIR_OpArrayCopy::dst_null_check) {
3147 __ testptr(dst, dst);
3148 __ jcc(Assembler::zero, *stub->entry());
3149 }
3150
3151 // check if negative
3152 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
3153 __ testl(src_pos, src_pos);
3154 __ jcc(Assembler::less, *stub->entry());
3155 }
3156 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
3157 __ testl(dst_pos, dst_pos);
3158 __ jcc(Assembler::less, *stub->entry());
3159 }
3160
3161 if (flags & LIR_OpArrayCopy::src_range_check) {
3162 __ lea(tmp, Address(src_pos, length, Address::times_1, 0));
3163 __ cmpl(tmp, src_length_addr);
3164 __ jcc(Assembler::above, *stub->entry());
3165 }
3166 if (flags & LIR_OpArrayCopy::dst_range_check) {
3167 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0));
3168 __ cmpl(tmp, dst_length_addr);
3169 __ jcc(Assembler::above, *stub->entry());
3170 }
3171
3172 if (flags & LIR_OpArrayCopy::length_positive_check) {
3173 __ testl(length, length);
3174 __ jcc(Assembler::less, *stub->entry());
3175 __ jcc(Assembler::zero, *stub->continuation());
3176 }
3177
3178 #ifdef _LP64
3179 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null
3180 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null
3181 #endif
3182
3183 if (flags & LIR_OpArrayCopy::type_check) {
3184 // We don't know the array types are compatible
3185 if (basic_type != T_OBJECT) {
3186 // Simple test for basic type arrays
3187 if (UseCompressedClassPointers) {
3188 __ movl(tmp, src_klass_addr);
3189 __ cmpl(tmp, dst_klass_addr);
3190 } else {
3191 __ movptr(tmp, src_klass_addr);
3192 __ cmpptr(tmp, dst_klass_addr);
3193 }
3194 __ jcc(Assembler::notEqual, *stub->entry());
3195 } else {
3196 // For object arrays, if src is a sub class of dst then we can
3197 // safely do the copy.
3198 Label cont, slow;
3199
3200 __ push(src);
3201 __ push(dst);
3202
3203 __ load_klass(src, src);
3204 __ load_klass(dst, dst);
3205
3206 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL);
3207
3208 __ push(src);
3209 __ push(dst);
3210 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
3211 __ pop(dst);
3212 __ pop(src);
3213
3214 __ cmpl(src, 0);
3215 __ jcc(Assembler::notEqual, cont);
3216
3217 __ bind(slow);
3218 __ pop(dst);
3219 __ pop(src);
3220
3221 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
3222 if (copyfunc_addr != NULL) { // use stub if available
3223 // src is not a sub class of dst so we have to do a
3224 // per-element check.
3225
3226 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
3227 if ((flags & mask) != mask) {
3228 // Check that at least both of them object arrays.
3229 assert(flags & mask, "one of the two should be known to be an object array");
3230
3231 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3232 __ load_klass(tmp, src);
3233 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3234 __ load_klass(tmp, dst);
3235 }
3236 int lh_offset = in_bytes(Klass::layout_helper_offset());
3237 Address klass_lh_addr(tmp, lh_offset);
3238 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
3239 __ cmpl(klass_lh_addr, objArray_lh);
3240 __ jcc(Assembler::notEqual, *stub->entry());
3241 }
3242
3243 // Spill because stubs can use any register they like and it's
3244 // easier to restore just those that we care about.
3245 store_parameter(dst, 0);
3246 store_parameter(dst_pos, 1);
3247 store_parameter(length, 2);
3248 store_parameter(src_pos, 3);
3249 store_parameter(src, 4);
3250
3251 #ifndef _LP64
3252 __ movptr(tmp, dst_klass_addr);
3253 __ movptr(tmp, Address(tmp, ObjArrayKlass::element_klass_offset()));
3254 __ push(tmp);
3255 __ movl(tmp, Address(tmp, Klass::super_check_offset_offset()));
3256 __ push(tmp);
3257 __ push(length);
3258 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3259 __ push(tmp);
3260 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3261 __ push(tmp);
3262
3263 __ call_VM_leaf(copyfunc_addr, 5);
3264 #else
3265 __ movl2ptr(length, length); //higher 32bits must be null
3266
3267 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3268 assert_different_registers(c_rarg0, dst, dst_pos, length);
3269 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3270 assert_different_registers(c_rarg1, dst, length);
3271
3272 __ mov(c_rarg2, length);
3273 assert_different_registers(c_rarg2, dst);
3274
3275 #ifdef _WIN64
3276 // Allocate abi space for args but be sure to keep stack aligned
3277 __ subptr(rsp, 6*wordSize);
3278 __ load_klass(c_rarg3, dst);
3279 __ movptr(c_rarg3, Address(c_rarg3, ObjArrayKlass::element_klass_offset()));
3280 store_parameter(c_rarg3, 4);
3281 __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset()));
3282 __ call(RuntimeAddress(copyfunc_addr));
3283 __ addptr(rsp, 6*wordSize);
3284 #else
3285 __ load_klass(c_rarg4, dst);
3286 __ movptr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
3287 __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
3288 __ call(RuntimeAddress(copyfunc_addr));
3289 #endif
3290
3291 #endif
3292
3293 #ifndef PRODUCT
3294 if (PrintC1Statistics) {
3295 Label failed;
3296 __ testl(rax, rax);
3297 __ jcc(Assembler::notZero, failed);
3298 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
3299 __ bind(failed);
3300 }
3301 #endif
3302
3303 __ testl(rax, rax);
3304 __ jcc(Assembler::zero, *stub->continuation());
3305
3306 #ifndef PRODUCT
3307 if (PrintC1Statistics) {
3308 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
3309 }
3310 #endif
3311
3312 __ mov(tmp, rax);
3313
3314 __ xorl(tmp, -1);
3315
3316 // Restore previously spilled arguments
3317 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3318 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3319 __ movptr (length, Address(rsp, 2*BytesPerWord));
3320 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3321 __ movptr (src, Address(rsp, 4*BytesPerWord));
3322
3323
3324 __ subl(length, tmp);
3325 __ addl(src_pos, tmp);
3326 __ addl(dst_pos, tmp);
3327 }
3328
3329 __ jmp(*stub->entry());
3330
3331 __ bind(cont);
3332 __ pop(dst);
3333 __ pop(src);
3334 }
3335 }
3336
3337 #ifdef ASSERT
3338 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
3339 // Sanity check the known type with the incoming class. For the
3340 // primitive case the types must match exactly with src.klass and
3341 // dst.klass each exactly matching the default type. For the
3342 // object array case, if no type check is needed then either the
3343 // dst type is exactly the expected type and the src type is a
3344 // subtype which we can't check or src is the same array as dst
3345 // but not necessarily exactly of type default_type.
3346 Label known_ok, halt;
3347 __ mov_metadata(tmp, default_type->constant_encoding());
3348 #ifdef _LP64
3349 if (UseCompressedClassPointers) {
3350 __ encode_klass_not_null(tmp);
3351 }
3352 #endif
3353
3354 if (basic_type != T_OBJECT) {
3355
3356 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr);
3357 else __ cmpptr(tmp, dst_klass_addr);
3358 __ jcc(Assembler::notEqual, halt);
3359 if (UseCompressedClassPointers) __ cmpl(tmp, src_klass_addr);
3360 else __ cmpptr(tmp, src_klass_addr);
3361 __ jcc(Assembler::equal, known_ok);
3362 } else {
3363 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr);
3364 else __ cmpptr(tmp, dst_klass_addr);
3365 __ jcc(Assembler::equal, known_ok);
3366 __ cmpptr(src, dst);
3367 __ jcc(Assembler::equal, known_ok);
3368 }
3369 __ bind(halt);
3370 __ stop("incorrect type information in arraycopy");
3371 __ bind(known_ok);
3372 }
3373 #endif
3374
3375 #ifndef PRODUCT
3376 if (PrintC1Statistics) {
3377 __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
3378 }
3379 #endif
3380
3381 #ifdef _LP64
3382 assert_different_registers(c_rarg0, dst, dst_pos, length);
3383 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3384 assert_different_registers(c_rarg1, length);
3385 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3386 __ mov(c_rarg2, length);
3387
3388 #else
3389 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3390 store_parameter(tmp, 0);
3391 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3392 store_parameter(tmp, 1);
3393 store_parameter(length, 2);
3394 #endif // _LP64
3395
3396 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
3397 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
3398 const char *name;
3399 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
3400 __ call_VM_leaf(entry, 0);
3401
3402 __ bind(*stub->continuation());
3403 }
3404
3405 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3406 assert(op->crc()->is_single_cpu(), "crc must be register");
3407 assert(op->val()->is_single_cpu(), "byte value must be register");
3408 assert(op->result_opr()->is_single_cpu(), "result must be register");
3409 Register crc = op->crc()->as_register();
3410 Register val = op->val()->as_register();
3411 Register res = op->result_opr()->as_register();
3412
3413 assert_different_registers(val, crc, res);
3414
3415 __ lea(res, ExternalAddress(StubRoutines::crc_table_addr()));
3416 __ notl(crc); // ~crc
3417 __ update_byte_crc32(crc, val, res);
3418 __ notl(crc); // ~crc
3419 __ mov(res, crc);
3420 }
3421
3422 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
3423 Register obj = op->obj_opr()->as_register(); // may not be an oop
3424 Register hdr = op->hdr_opr()->as_register();
3425 Register lock = op->lock_opr()->as_register();
3426 if (!UseFastLocking) {
3427 __ jmp(*op->stub()->entry());
3428 } else if (op->code() == lir_lock) {
3429 Register scratch = noreg;
3430 if (UseBiasedLocking) {
3431 scratch = op->scratch_opr()->as_register();
3432 }
3433 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3434 // add debug info for NullPointerException only if one is possible
3435 int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry());
3436 if (op->info() != NULL) {
3437 add_debug_info_for_null_check(null_check_offset, op->info());
3438 }
3439 // done
3440 } else if (op->code() == lir_unlock) {
3441 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3442 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
3443 } else {
3444 Unimplemented();
3445 }
3446 __ bind(*op->stub()->continuation());
3447 }
3448
3449
3450 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
3451 ciMethod* method = op->profiled_method();
3452 int bci = op->profiled_bci();
3453 ciMethod* callee = op->profiled_callee();
3454
3455 // Update counter for all call types
3456 ciMethodData* md = method->method_data_or_null();
3457 assert(md != NULL, "Sanity");
3458 ciProfileData* data = md->bci_to_data(bci);
3459 assert(data->is_CounterData(), "need CounterData for calls");
3460 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
3461 Register mdo = op->mdo()->as_register();
3462 __ mov_metadata(mdo, md->constant_encoding());
3463 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
3464 Bytecodes::Code bc = method->java_code_at_bci(bci);
3465 const bool callee_is_static = callee->is_loaded() && callee->is_static();
3466 // Perform additional virtual call profiling for invokevirtual and
3467 // invokeinterface bytecodes
3468 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) &&
3469 !callee_is_static && // required for optimized MH invokes
3470 C1ProfileVirtualCalls) {
3471 assert(op->recv()->is_single_cpu(), "recv must be allocated");
3472 Register recv = op->recv()->as_register();
3473 assert_different_registers(mdo, recv);
3474 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
3475 ciKlass* known_klass = op->known_holder();
3476 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
3477 // We know the type that will be seen at this call site; we can
3478 // statically update the MethodData* rather than needing to do
3479 // dynamic tests on the receiver type
3480
3481 // NOTE: we should probably put a lock around this search to
3482 // avoid collisions by concurrent compilations
3483 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
3484 uint i;
3485 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3486 ciKlass* receiver = vc_data->receiver(i);
3487 if (known_klass->equals(receiver)) {
3488 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3489 __ addptr(data_addr, DataLayout::counter_increment);
3490 return;
3491 }
3492 }
3493
3494 // Receiver type not found in profile data; select an empty slot
3495
3496 // Note that this is less efficient than it should be because it
3497 // always does a write to the receiver part of the
3498 // VirtualCallData rather than just the first time
3499 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3500 ciKlass* receiver = vc_data->receiver(i);
3501 if (receiver == NULL) {
3502 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
3503 __ mov_metadata(recv_addr, known_klass->constant_encoding());
3504 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3505 __ addptr(data_addr, DataLayout::counter_increment);
3506 return;
3507 }
3508 }
3509 } else {
3510 __ load_klass(recv, recv);
3511 Label update_done;
3512 type_profile_helper(mdo, md, data, recv, &update_done);
3513 // Receiver did not match any saved receiver and there is no empty row for it.
3514 // Increment total counter to indicate polymorphic case.
3515 __ addptr(counter_addr, DataLayout::counter_increment);
3516
3517 __ bind(update_done);
3518 }
3519 } else {
3520 // Static call
3521 __ addptr(counter_addr, DataLayout::counter_increment);
3522 }
3523 }
3524
3525 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
3526 Register obj = op->obj()->as_register();
3527 Register tmp = op->tmp()->as_pointer_register();
3528 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
3529 ciKlass* exact_klass = op->exact_klass();
3530 intptr_t current_klass = op->current_klass();
3531 bool not_null = op->not_null();
3532 bool no_conflict = op->no_conflict();
3533
3534 Label update, next, none;
3535
3536 bool do_null = !not_null;
3537 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
3538 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
3539
3540 assert(do_null || do_update, "why are we here?");
3541 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
3542
3543 __ verify_oop(obj);
3544
3545 if (tmp != obj) {
3546 __ mov(tmp, obj);
3547 }
3548 if (do_null) {
3549 __ testptr(tmp, tmp);
3550 __ jccb(Assembler::notZero, update);
3551 if (!TypeEntries::was_null_seen(current_klass)) {
3552 __ orptr(mdo_addr, TypeEntries::null_seen);
3553 }
3554 if (do_update) {
3555 #ifndef ASSERT
3556 __ jmpb(next);
3557 }
3558 #else
3559 __ jmp(next);
3560 }
3561 } else {
3562 __ testptr(tmp, tmp);
3563 __ jccb(Assembler::notZero, update);
3564 __ stop("unexpect null obj");
3565 #endif
3566 }
3567
3568 __ bind(update);
3569
3570 if (do_update) {
3571 #ifdef ASSERT
3572 if (exact_klass != NULL) {
3573 Label ok;
3574 __ load_klass(tmp, tmp);
3575 __ push(tmp);
3576 __ mov_metadata(tmp, exact_klass->constant_encoding());
3577 __ cmpptr(tmp, Address(rsp, 0));
3578 __ jccb(Assembler::equal, ok);
3579 __ stop("exact klass and actual klass differ");
3580 __ bind(ok);
3581 __ pop(tmp);
3582 }
3583 #endif
3584 if (!no_conflict) {
3585 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
3586 if (exact_klass != NULL) {
3587 __ mov_metadata(tmp, exact_klass->constant_encoding());
3588 } else {
3589 __ load_klass(tmp, tmp);
3590 }
3591
3592 __ xorptr(tmp, mdo_addr);
3593 __ testptr(tmp, TypeEntries::type_klass_mask);
3594 // klass seen before, nothing to do. The unknown bit may have been
3595 // set already but no need to check.
3596 __ jccb(Assembler::zero, next);
3597
3598 __ testptr(tmp, TypeEntries::type_unknown);
3599 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3600
3601 if (TypeEntries::is_type_none(current_klass)) {
3602 __ cmpptr(mdo_addr, 0);
3603 __ jccb(Assembler::equal, none);
3604 __ cmpptr(mdo_addr, TypeEntries::null_seen);
3605 __ jccb(Assembler::equal, none);
3606 // There is a chance that the checks above (re-reading profiling
3607 // data from memory) fail if another thread has just set the
3608 // profiling to this obj's klass
3609 __ xorptr(tmp, mdo_addr);
3610 __ testptr(tmp, TypeEntries::type_klass_mask);
3611 __ jccb(Assembler::zero, next);
3612 }
3613 } else {
3614 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3615 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3616
3617 __ movptr(tmp, mdo_addr);
3618 __ testptr(tmp, TypeEntries::type_unknown);
3619 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3620 }
3621
3622 // different than before. Cannot keep accurate profile.
3623 __ orptr(mdo_addr, TypeEntries::type_unknown);
3624
3625 if (TypeEntries::is_type_none(current_klass)) {
3626 __ jmpb(next);
3627
3628 __ bind(none);
3629 // first time here. Set profile type.
3630 __ movptr(mdo_addr, tmp);
3631 }
3632 } else {
3633 // There's a single possible klass at this profile point
3634 assert(exact_klass != NULL, "should be");
3635 if (TypeEntries::is_type_none(current_klass)) {
3636 __ mov_metadata(tmp, exact_klass->constant_encoding());
3637 __ xorptr(tmp, mdo_addr);
3638 __ testptr(tmp, TypeEntries::type_klass_mask);
3639 #ifdef ASSERT
3640 __ jcc(Assembler::zero, next);
3641
3642 {
3643 Label ok;
3644 __ push(tmp);
3645 __ cmpptr(mdo_addr, 0);
3646 __ jcc(Assembler::equal, ok);
3647 __ cmpptr(mdo_addr, TypeEntries::null_seen);
3648 __ jcc(Assembler::equal, ok);
3649 // may have been set by another thread
3650 __ mov_metadata(tmp, exact_klass->constant_encoding());
3651 __ xorptr(tmp, mdo_addr);
3652 __ testptr(tmp, TypeEntries::type_mask);
3653 __ jcc(Assembler::zero, ok);
3654
3655 __ stop("unexpected profiling mismatch");
3656 __ bind(ok);
3657 __ pop(tmp);
3658 }
3659 #else
3660 __ jccb(Assembler::zero, next);
3661 #endif
3662 // first time here. Set profile type.
3663 __ movptr(mdo_addr, tmp);
3664 } else {
3665 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3666 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3667
3668 __ movptr(tmp, mdo_addr);
3669 __ testptr(tmp, TypeEntries::type_unknown);
3670 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3671
3672 __ orptr(mdo_addr, TypeEntries::type_unknown);
3673 }
3674 }
3675
3676 __ bind(next);
3677 }
3678 }
3679
3680 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
3681 Unimplemented();
3682 }
3683
3684
3685 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
3686 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
3687 }
3688
3689
3690 void LIR_Assembler::align_backward_branch_target() {
3691 __ align(BytesPerWord);
3692 }
3693
3694
3695 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
3696 if (left->is_single_cpu()) {
3697 __ negl(left->as_register());
3698 move_regs(left->as_register(), dest->as_register());
3699
3700 } else if (left->is_double_cpu()) {
3701 Register lo = left->as_register_lo();
3702 #ifdef _LP64
3703 Register dst = dest->as_register_lo();
3704 __ movptr(dst, lo);
3705 __ negptr(dst);
3706 #else
3707 Register hi = left->as_register_hi();
3708 __ lneg(hi, lo);
3709 if (dest->as_register_lo() == hi) {
3710 assert(dest->as_register_hi() != lo, "destroying register");
3711 move_regs(hi, dest->as_register_hi());
3712 move_regs(lo, dest->as_register_lo());
3713 } else {
3714 move_regs(lo, dest->as_register_lo());
3715 move_regs(hi, dest->as_register_hi());
3716 }
3717 #endif // _LP64
3718
3719 } else if (dest->is_single_xmm()) {
3720 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) {
3721 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg());
3722 }
3723 if (UseAVX > 0) {
3724 __ vnegatess(dest->as_xmm_float_reg(), dest->as_xmm_float_reg(),
3725 ExternalAddress((address)float_signflip_pool));
3726 } else {
3727 __ xorps(dest->as_xmm_float_reg(),
3728 ExternalAddress((address)float_signflip_pool));
3729 }
3730 } else if (dest->is_double_xmm()) {
3731 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) {
3732 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg());
3733 }
3734 if (UseAVX > 0) {
3735 __ vnegatesd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg(),
3736 ExternalAddress((address)double_signflip_pool));
3737 } else {
3738 __ xorpd(dest->as_xmm_double_reg(),
3739 ExternalAddress((address)double_signflip_pool));
3740 }
3741 } else if (left->is_single_fpu() || left->is_double_fpu()) {
3742 assert(left->fpu() == 0, "arg must be on TOS");
3743 assert(dest->fpu() == 0, "dest must be TOS");
3744 __ fchs();
3745
3746 } else {
3747 ShouldNotReachHere();
3748 }
3749 }
3750
3751
3752 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest) {
3753 assert(addr->is_address() && dest->is_register(), "check");
3754 Register reg;
3755 reg = dest->as_pointer_register();
3756 __ lea(reg, as_Address(addr->as_address_ptr()));
3757 }
3758
3759
3760
3761 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3762 assert(!tmp->is_valid(), "don't need temporary");
3763 __ call(RuntimeAddress(dest));
3764 if (info != NULL) {
3765 add_call_info_here(info);
3766 }
3767 }
3768
3769
3770 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3771 assert(type == T_LONG, "only for volatile long fields");
3772
3773 if (info != NULL) {
3774 add_debug_info_for_null_check_here(info);
3775 }
3776
3777 if (src->is_double_xmm()) {
3778 if (dest->is_double_cpu()) {
3779 #ifdef _LP64
3780 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg());
3781 #else
3782 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg());
3783 __ psrlq(src->as_xmm_double_reg(), 32);
3784 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg());
3785 #endif // _LP64
3786 } else if (dest->is_double_stack()) {
3787 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg());
3788 } else if (dest->is_address()) {
3789 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg());
3790 } else {
3791 ShouldNotReachHere();
3792 }
3793
3794 } else if (dest->is_double_xmm()) {
3795 if (src->is_double_stack()) {
3796 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix()));
3797 } else if (src->is_address()) {
3798 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr()));
3799 } else {
3800 ShouldNotReachHere();
3801 }
3802
3803 } else if (src->is_double_fpu()) {
3804 assert(src->fpu_regnrLo() == 0, "must be TOS");
3805 if (dest->is_double_stack()) {
3806 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix()));
3807 } else if (dest->is_address()) {
3808 __ fistp_d(as_Address(dest->as_address_ptr()));
3809 } else {
3810 ShouldNotReachHere();
3811 }
3812
3813 } else if (dest->is_double_fpu()) {
3814 assert(dest->fpu_regnrLo() == 0, "must be TOS");
3815 if (src->is_double_stack()) {
3816 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix()));
3817 } else if (src->is_address()) {
3818 __ fild_d(as_Address(src->as_address_ptr()));
3819 } else {
3820 ShouldNotReachHere();
3821 }
3822 } else {
3823 ShouldNotReachHere();
3824 }
3825 }
3826
3827 #ifdef ASSERT
3828 // emit run-time assertion
3829 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3830 assert(op->code() == lir_assert, "must be");
3831
3832 if (op->in_opr1()->is_valid()) {
3833 assert(op->in_opr2()->is_valid(), "both operands must be valid");
3834 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3835 } else {
3836 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3837 assert(op->condition() == lir_cond_always, "no other conditions allowed");
3838 }
3839
3840 Label ok;
3841 if (op->condition() != lir_cond_always) {
3842 Assembler::Condition acond = Assembler::zero;
3843 switch (op->condition()) {
3844 case lir_cond_equal: acond = Assembler::equal; break;
3845 case lir_cond_notEqual: acond = Assembler::notEqual; break;
3846 case lir_cond_less: acond = Assembler::less; break;
3847 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
3848 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
3849 case lir_cond_greater: acond = Assembler::greater; break;
3850 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
3851 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
3852 default: ShouldNotReachHere();
3853 }
3854 __ jcc(acond, ok);
3855 }
3856 if (op->halt()) {
3857 const char* str = __ code_string(op->msg());
3858 __ stop(str);
3859 } else {
3860 breakpoint();
3861 }
3862 __ bind(ok);
3863 }
3864 #endif
3865
3866 void LIR_Assembler::membar() {
3867 // QQQ sparc TSO uses this,
3868 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad));
3869 }
3870
3871 void LIR_Assembler::membar_acquire() {
3872 // No x86 machines currently require load fences
3873 }
3874
3875 void LIR_Assembler::membar_release() {
3876 // No x86 machines currently require store fences
3877 }
3878
3879 void LIR_Assembler::membar_loadload() {
3880 // no-op
3881 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
3882 }
3883
3884 void LIR_Assembler::membar_storestore() {
3885 // no-op
3886 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
3887 }
3888
3889 void LIR_Assembler::membar_loadstore() {
3890 // no-op
3891 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
3892 }
3893
3894 void LIR_Assembler::membar_storeload() {
3895 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
3896 }
3897
3898 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3899 assert(result_reg->is_register(), "check");
3900 #ifdef _LP64
3901 // __ get_thread(result_reg->as_register_lo());
3902 __ mov(result_reg->as_register(), r15_thread);
3903 #else
3904 __ get_thread(result_reg->as_register());
3905 #endif // _LP64
3906 }
3907
3908
3909 void LIR_Assembler::peephole(LIR_List*) {
3910 // do nothing for now
3911 }
3912
3913 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
3914 assert(data == dest, "xchg/xadd uses only 2 operands");
3915
3916 if (data->type() == T_INT) {
3917 if (code == lir_xadd) {
3918 if (os::is_MP()) {
3919 __ lock();
3920 }
3921 __ xaddl(as_Address(src->as_address_ptr()), data->as_register());
3922 } else {
3923 __ xchgl(data->as_register(), as_Address(src->as_address_ptr()));
3924 }
3925 } else if (data->is_oop()) {
3926 assert (code == lir_xchg, "xadd for oops");
3927 Register obj = data->as_register();
3928 #ifdef _LP64
3929 if (UseCompressedOops) {
3930 __ encode_heap_oop(obj);
3931 __ xchgl(obj, as_Address(src->as_address_ptr()));
3932 __ decode_heap_oop(obj);
3933 } else {
3934 __ xchgptr(obj, as_Address(src->as_address_ptr()));
3935 }
3936 #else
3937 __ xchgl(obj, as_Address(src->as_address_ptr()));
3938 #endif
3939 } else if (data->type() == T_LONG) {
3940 #ifdef _LP64
3941 assert(data->as_register_lo() == data->as_register_hi(), "should be a single register");
3942 if (code == lir_xadd) {
3943 if (os::is_MP()) {
3944 __ lock();
3945 }
3946 __ xaddq(as_Address(src->as_address_ptr()), data->as_register_lo());
3947 } else {
3948 __ xchgq(data->as_register_lo(), as_Address(src->as_address_ptr()));
3949 }
3950 #else
3951 ShouldNotReachHere();
3952 #endif
3953 } else {
3954 ShouldNotReachHere();
3955 }
3956 }
3957
3958 #undef __