1 /*
2 * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "gc/shared/cardTableModRefBS.hpp"
29 #include "gc/shared/collectedHeap.inline.hpp"
30 #include "interpreter/interpreter.hpp"
31 #include "memory/resourceArea.hpp"
32 #include "prims/methodHandles.hpp"
33 #include "runtime/biasedLocking.hpp"
34 #include "runtime/interfaceSupport.hpp"
35 #include "runtime/objectMonitor.hpp"
36 #include "runtime/os.hpp"
37 #include "runtime/sharedRuntime.hpp"
38 #include "runtime/stubRoutines.hpp"
39 #include "utilities/macros.hpp"
40 #if INCLUDE_ALL_GCS
41 #include "gc/g1/g1CollectedHeap.inline.hpp"
42 #include "gc/g1/g1SATBCardTableModRefBS.hpp"
43 #include "gc/g1/heapRegion.hpp"
44 #endif // INCLUDE_ALL_GCS
45
46 #ifdef PRODUCT
47 #define BLOCK_COMMENT(str) /* nothing */
48 #define STOP(error) stop(error)
49 #else
50 #define BLOCK_COMMENT(str) block_comment(str)
51 #define STOP(error) block_comment(error); stop(error)
52 #endif
53
54 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
55 // Implementation of AddressLiteral
56
57 // A 2-D table for managing compressed displacement(disp8) on EVEX enabled platforms.
58 unsigned char tuple_table[Assembler::EVEX_ETUP + 1][Assembler::AVX_512bit + 1] = {
59 // -----------------Table 4.5 -------------------- //
60 16, 32, 64, // EVEX_FV(0)
61 4, 4, 4, // EVEX_FV(1) - with Evex.b
62 16, 32, 64, // EVEX_FV(2) - with Evex.w
63 8, 8, 8, // EVEX_FV(3) - with Evex.w and Evex.b
64 8, 16, 32, // EVEX_HV(0)
65 4, 4, 4, // EVEX_HV(1) - with Evex.b
66 // -----------------Table 4.6 -------------------- //
67 16, 32, 64, // EVEX_FVM(0)
68 1, 1, 1, // EVEX_T1S(0)
69 2, 2, 2, // EVEX_T1S(1)
70 4, 4, 4, // EVEX_T1S(2)
71 8, 8, 8, // EVEX_T1S(3)
72 4, 4, 4, // EVEX_T1F(0)
73 8, 8, 8, // EVEX_T1F(1)
74 8, 8, 8, // EVEX_T2(0)
75 0, 16, 16, // EVEX_T2(1)
76 0, 16, 16, // EVEX_T4(0)
77 0, 0, 32, // EVEX_T4(1)
78 0, 0, 32, // EVEX_T8(0)
79 8, 16, 32, // EVEX_HVM(0)
80 4, 8, 16, // EVEX_QVM(0)
81 2, 4, 8, // EVEX_OVM(0)
82 16, 16, 16, // EVEX_M128(0)
83 8, 32, 64, // EVEX_DUP(0)
84 0, 0, 0 // EVEX_NTUP
85 };
86
87 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
88 _is_lval = false;
89 _target = target;
90 switch (rtype) {
91 case relocInfo::oop_type:
92 case relocInfo::metadata_type:
93 // Oops are a special case. Normally they would be their own section
94 // but in cases like icBuffer they are literals in the code stream that
95 // we don't have a section for. We use none so that we get a literal address
96 // which is always patchable.
97 break;
98 case relocInfo::external_word_type:
99 _rspec = external_word_Relocation::spec(target);
100 break;
101 case relocInfo::internal_word_type:
102 _rspec = internal_word_Relocation::spec(target);
103 break;
104 case relocInfo::opt_virtual_call_type:
105 _rspec = opt_virtual_call_Relocation::spec();
106 break;
107 case relocInfo::static_call_type:
108 _rspec = static_call_Relocation::spec();
109 break;
110 case relocInfo::runtime_call_type:
111 _rspec = runtime_call_Relocation::spec();
112 break;
113 case relocInfo::poll_type:
114 case relocInfo::poll_return_type:
115 _rspec = Relocation::spec_simple(rtype);
116 break;
117 case relocInfo::none:
118 break;
119 default:
120 ShouldNotReachHere();
121 break;
122 }
123 }
124
125 // Implementation of Address
126
127 #ifdef _LP64
128
129 Address Address::make_array(ArrayAddress adr) {
130 // Not implementable on 64bit machines
131 // Should have been handled higher up the call chain.
132 ShouldNotReachHere();
133 return Address();
134 }
135
136 // exceedingly dangerous constructor
137 Address::Address(int disp, address loc, relocInfo::relocType rtype) {
138 _base = noreg;
139 _index = noreg;
140 _scale = no_scale;
141 _disp = disp;
142 switch (rtype) {
143 case relocInfo::external_word_type:
144 _rspec = external_word_Relocation::spec(loc);
145 break;
146 case relocInfo::internal_word_type:
147 _rspec = internal_word_Relocation::spec(loc);
148 break;
149 case relocInfo::runtime_call_type:
150 // HMM
151 _rspec = runtime_call_Relocation::spec();
152 break;
153 case relocInfo::poll_type:
154 case relocInfo::poll_return_type:
155 _rspec = Relocation::spec_simple(rtype);
156 break;
157 case relocInfo::none:
158 break;
159 default:
160 ShouldNotReachHere();
161 }
162 }
163 #else // LP64
164
165 Address Address::make_array(ArrayAddress adr) {
166 AddressLiteral base = adr.base();
167 Address index = adr.index();
168 assert(index._disp == 0, "must not have disp"); // maybe it can?
169 Address array(index._base, index._index, index._scale, (intptr_t) base.target());
170 array._rspec = base._rspec;
171 return array;
172 }
173
174 // exceedingly dangerous constructor
175 Address::Address(address loc, RelocationHolder spec) {
176 _base = noreg;
177 _index = noreg;
178 _scale = no_scale;
179 _disp = (intptr_t) loc;
180 _rspec = spec;
181 }
182
183 #endif // _LP64
184
185
186
187 // Convert the raw encoding form into the form expected by the constructor for
188 // Address. An index of 4 (rsp) corresponds to having no index, so convert
189 // that to noreg for the Address constructor.
190 Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) {
191 RelocationHolder rspec;
192 if (disp_reloc != relocInfo::none) {
193 rspec = Relocation::spec_simple(disp_reloc);
194 }
195 bool valid_index = index != rsp->encoding();
196 if (valid_index) {
197 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));
198 madr._rspec = rspec;
199 return madr;
200 } else {
201 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));
202 madr._rspec = rspec;
203 return madr;
204 }
205 }
206
207 // Implementation of Assembler
208
209 int AbstractAssembler::code_fill_byte() {
210 return (u_char)'\xF4'; // hlt
211 }
212
213 // make this go away someday
214 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) {
215 if (rtype == relocInfo::none)
216 emit_int32(data);
217 else
218 emit_data(data, Relocation::spec_simple(rtype), format);
219 }
220
221 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) {
222 assert(imm_operand == 0, "default format must be immediate in this file");
223 assert(inst_mark() != NULL, "must be inside InstructionMark");
224 if (rspec.type() != relocInfo::none) {
225 #ifdef ASSERT
226 check_relocation(rspec, format);
227 #endif
228 // Do not use AbstractAssembler::relocate, which is not intended for
229 // embedded words. Instead, relocate to the enclosing instruction.
230
231 // hack. call32 is too wide for mask so use disp32
232 if (format == call32_operand)
233 code_section()->relocate(inst_mark(), rspec, disp32_operand);
234 else
235 code_section()->relocate(inst_mark(), rspec, format);
236 }
237 emit_int32(data);
238 }
239
240 static int encode(Register r) {
241 int enc = r->encoding();
242 if (enc >= 8) {
243 enc -= 8;
244 }
245 return enc;
246 }
247
248 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
249 assert(dst->has_byte_register(), "must have byte register");
250 assert(isByte(op1) && isByte(op2), "wrong opcode");
251 assert(isByte(imm8), "not a byte");
252 assert((op1 & 0x01) == 0, "should be 8bit operation");
253 emit_int8(op1);
254 emit_int8(op2 | encode(dst));
255 emit_int8(imm8);
256 }
257
258
259 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) {
260 assert(isByte(op1) && isByte(op2), "wrong opcode");
261 assert((op1 & 0x01) == 1, "should be 32bit operation");
262 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
263 if (is8bit(imm32)) {
264 emit_int8(op1 | 0x02); // set sign bit
265 emit_int8(op2 | encode(dst));
266 emit_int8(imm32 & 0xFF);
267 } else {
268 emit_int8(op1);
269 emit_int8(op2 | encode(dst));
270 emit_int32(imm32);
271 }
272 }
273
274 // Force generation of a 4 byte immediate value even if it fits into 8bit
275 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) {
276 assert(isByte(op1) && isByte(op2), "wrong opcode");
277 assert((op1 & 0x01) == 1, "should be 32bit operation");
278 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
279 emit_int8(op1);
280 emit_int8(op2 | encode(dst));
281 emit_int32(imm32);
282 }
283
284 // immediate-to-memory forms
285 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) {
286 assert((op1 & 0x01) == 1, "should be 32bit operation");
287 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
288 if (is8bit(imm32)) {
289 emit_int8(op1 | 0x02); // set sign bit
290 emit_operand(rm, adr, 1);
291 emit_int8(imm32 & 0xFF);
292 } else {
293 emit_int8(op1);
294 emit_operand(rm, adr, 4);
295 emit_int32(imm32);
296 }
297 }
298
299
300 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
301 assert(isByte(op1) && isByte(op2), "wrong opcode");
302 emit_int8(op1);
303 emit_int8(op2 | encode(dst) << 3 | encode(src));
304 }
305
306
307 bool Assembler::query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len,
308 int cur_tuple_type, int in_size_in_bits, int cur_encoding) {
309 int mod_idx = 0;
310 // We will test if the displacement fits the compressed format and if so
311 // apply the compression to the displacment iff the result is8bit.
312 if (VM_Version::supports_evex() && is_evex_inst) {
313 switch (cur_tuple_type) {
314 case EVEX_FV:
315 if ((cur_encoding & VEX_W) == VEX_W) {
316 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2;
317 } else {
318 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
319 }
320 break;
321
322 case EVEX_HV:
323 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
324 break;
325
326 case EVEX_FVM:
327 break;
328
329 case EVEX_T1S:
330 switch (in_size_in_bits) {
331 case EVEX_8bit:
332 break;
333
334 case EVEX_16bit:
335 mod_idx = 1;
336 break;
337
338 case EVEX_32bit:
339 mod_idx = 2;
340 break;
341
342 case EVEX_64bit:
343 mod_idx = 3;
344 break;
345 }
346 break;
347
348 case EVEX_T1F:
349 case EVEX_T2:
350 case EVEX_T4:
351 mod_idx = (in_size_in_bits == EVEX_64bit) ? 1 : 0;
352 break;
353
354 case EVEX_T8:
355 break;
356
357 case EVEX_HVM:
358 break;
359
360 case EVEX_QVM:
361 break;
362
363 case EVEX_OVM:
364 break;
365
366 case EVEX_M128:
367 break;
368
369 case EVEX_DUP:
370 break;
371
372 default:
373 assert(0, "no valid evex tuple_table entry");
374 break;
375 }
376
377 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
378 int disp_factor = tuple_table[cur_tuple_type + mod_idx][vector_len];
379 if ((disp % disp_factor) == 0) {
380 int new_disp = disp / disp_factor;
381 if ((-0x80 <= new_disp && new_disp < 0x80)) {
382 disp = new_disp;
383 }
384 } else {
385 return false;
386 }
387 }
388 }
389 return (-0x80 <= disp && disp < 0x80);
390 }
391
392
393 bool Assembler::emit_compressed_disp_byte(int &disp) {
394 int mod_idx = 0;
395 // We will test if the displacement fits the compressed format and if so
396 // apply the compression to the displacment iff the result is8bit.
397 if (VM_Version::supports_evex() && (_attributes != NULL) && _attributes->is_evex_instruction()) {
398 int evex_encoding = _attributes->get_evex_encoding();
399 int tuple_type = _attributes->get_tuple_type();
400 switch (tuple_type) {
401 case EVEX_FV:
402 if ((evex_encoding & VEX_W) == VEX_W) {
403 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2;
404 } else {
405 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
406 }
407 break;
408
409 case EVEX_HV:
410 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
411 break;
412
413 case EVEX_FVM:
414 break;
415
416 case EVEX_T1S:
417 switch (_attributes->get_input_size()) {
418 case EVEX_8bit:
419 break;
420
421 case EVEX_16bit:
422 mod_idx = 1;
423 break;
424
425 case EVEX_32bit:
426 mod_idx = 2;
427 break;
428
429 case EVEX_64bit:
430 mod_idx = 3;
431 break;
432 }
433 break;
434
435 case EVEX_T1F:
436 case EVEX_T2:
437 case EVEX_T4:
438 mod_idx = (_attributes->get_input_size() == EVEX_64bit) ? 1 : 0;
439 break;
440
441 case EVEX_T8:
442 break;
443
444 case EVEX_HVM:
445 break;
446
447 case EVEX_QVM:
448 break;
449
450 case EVEX_OVM:
451 break;
452
453 case EVEX_M128:
454 break;
455
456 case EVEX_DUP:
457 break;
458
459 default:
460 assert(0, "no valid evex tuple_table entry");
461 break;
462 }
463
464 int vector_len = _attributes->get_vector_len();
465 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
466 int disp_factor = tuple_table[tuple_type + mod_idx][vector_len];
467 if ((disp % disp_factor) == 0) {
468 int new_disp = disp / disp_factor;
469 if (is8bit(new_disp)) {
470 disp = new_disp;
471 }
472 } else {
473 return false;
474 }
475 }
476 }
477 return is8bit(disp);
478 }
479
480
481 void Assembler::emit_operand(Register reg, Register base, Register index,
482 Address::ScaleFactor scale, int disp,
483 RelocationHolder const& rspec,
484 int rip_relative_correction) {
485 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();
486
487 // Encode the registers as needed in the fields they are used in
488
489 int regenc = encode(reg) << 3;
490 int indexenc = index->is_valid() ? encode(index) << 3 : 0;
491 int baseenc = base->is_valid() ? encode(base) : 0;
492
493 if (base->is_valid()) {
494 if (index->is_valid()) {
495 assert(scale != Address::no_scale, "inconsistent address");
496 // [base + index*scale + disp]
497 if (disp == 0 && rtype == relocInfo::none &&
498 base != rbp LP64_ONLY(&& base != r13)) {
499 // [base + index*scale]
500 // [00 reg 100][ss index base]
501 assert(index != rsp, "illegal addressing mode");
502 emit_int8(0x04 | regenc);
503 emit_int8(scale << 6 | indexenc | baseenc);
504 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
505 // [base + index*scale + imm8]
506 // [01 reg 100][ss index base] imm8
507 assert(index != rsp, "illegal addressing mode");
508 emit_int8(0x44 | regenc);
509 emit_int8(scale << 6 | indexenc | baseenc);
510 emit_int8(disp & 0xFF);
511 } else {
512 // [base + index*scale + disp32]
513 // [10 reg 100][ss index base] disp32
514 assert(index != rsp, "illegal addressing mode");
515 emit_int8(0x84 | regenc);
516 emit_int8(scale << 6 | indexenc | baseenc);
517 emit_data(disp, rspec, disp32_operand);
518 }
519 } else if (base == rsp LP64_ONLY(|| base == r12)) {
520 // [rsp + disp]
521 if (disp == 0 && rtype == relocInfo::none) {
522 // [rsp]
523 // [00 reg 100][00 100 100]
524 emit_int8(0x04 | regenc);
525 emit_int8(0x24);
526 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
527 // [rsp + imm8]
528 // [01 reg 100][00 100 100] disp8
529 emit_int8(0x44 | regenc);
530 emit_int8(0x24);
531 emit_int8(disp & 0xFF);
532 } else {
533 // [rsp + imm32]
534 // [10 reg 100][00 100 100] disp32
535 emit_int8(0x84 | regenc);
536 emit_int8(0x24);
537 emit_data(disp, rspec, disp32_operand);
538 }
539 } else {
540 // [base + disp]
541 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode");
542 if (disp == 0 && rtype == relocInfo::none &&
543 base != rbp LP64_ONLY(&& base != r13)) {
544 // [base]
545 // [00 reg base]
546 emit_int8(0x00 | regenc | baseenc);
547 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
548 // [base + disp8]
549 // [01 reg base] disp8
550 emit_int8(0x40 | regenc | baseenc);
551 emit_int8(disp & 0xFF);
552 } else {
553 // [base + disp32]
554 // [10 reg base] disp32
555 emit_int8(0x80 | regenc | baseenc);
556 emit_data(disp, rspec, disp32_operand);
557 }
558 }
559 } else {
560 if (index->is_valid()) {
561 assert(scale != Address::no_scale, "inconsistent address");
562 // [index*scale + disp]
563 // [00 reg 100][ss index 101] disp32
564 assert(index != rsp, "illegal addressing mode");
565 emit_int8(0x04 | regenc);
566 emit_int8(scale << 6 | indexenc | 0x05);
567 emit_data(disp, rspec, disp32_operand);
568 } else if (rtype != relocInfo::none ) {
569 // [disp] (64bit) RIP-RELATIVE (32bit) abs
570 // [00 000 101] disp32
571
572 emit_int8(0x05 | regenc);
573 // Note that the RIP-rel. correction applies to the generated
574 // disp field, but _not_ to the target address in the rspec.
575
576 // disp was created by converting the target address minus the pc
577 // at the start of the instruction. That needs more correction here.
578 // intptr_t disp = target - next_ip;
579 assert(inst_mark() != NULL, "must be inside InstructionMark");
580 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction;
581 int64_t adjusted = disp;
582 // Do rip-rel adjustment for 64bit
583 LP64_ONLY(adjusted -= (next_ip - inst_mark()));
584 assert(is_simm32(adjusted),
585 "must be 32bit offset (RIP relative address)");
586 emit_data((int32_t) adjusted, rspec, disp32_operand);
587
588 } else {
589 // 32bit never did this, did everything as the rip-rel/disp code above
590 // [disp] ABSOLUTE
591 // [00 reg 100][00 100 101] disp32
592 emit_int8(0x04 | regenc);
593 emit_int8(0x25);
594 emit_data(disp, rspec, disp32_operand);
595 }
596 }
597 }
598
599 void Assembler::emit_operand(XMMRegister reg, Register base, Register index,
600 Address::ScaleFactor scale, int disp,
601 RelocationHolder const& rspec) {
602 if (UseAVX > 2) {
603 int xreg_enc = reg->encoding();
604 if (xreg_enc > 15) {
605 XMMRegister new_reg = as_XMMRegister(xreg_enc & 0xf);
606 emit_operand((Register)new_reg, base, index, scale, disp, rspec);
607 return;
608 }
609 }
610 emit_operand((Register)reg, base, index, scale, disp, rspec);
611 }
612
613 // Secret local extension to Assembler::WhichOperand:
614 #define end_pc_operand (_WhichOperand_limit)
615
616 address Assembler::locate_operand(address inst, WhichOperand which) {
617 // Decode the given instruction, and return the address of
618 // an embedded 32-bit operand word.
619
620 // If "which" is disp32_operand, selects the displacement portion
621 // of an effective address specifier.
622 // If "which" is imm64_operand, selects the trailing immediate constant.
623 // If "which" is call32_operand, selects the displacement of a call or jump.
624 // Caller is responsible for ensuring that there is such an operand,
625 // and that it is 32/64 bits wide.
626
627 // If "which" is end_pc_operand, find the end of the instruction.
628
629 address ip = inst;
630 bool is_64bit = false;
631
632 debug_only(bool has_disp32 = false);
633 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn
634
635 again_after_prefix:
636 switch (0xFF & *ip++) {
637
638 // These convenience macros generate groups of "case" labels for the switch.
639 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3
640 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \
641 case (x)+4: case (x)+5: case (x)+6: case (x)+7
642 #define REP16(x) REP8((x)+0): \
643 case REP8((x)+8)
644
645 case CS_segment:
646 case SS_segment:
647 case DS_segment:
648 case ES_segment:
649 case FS_segment:
650 case GS_segment:
651 // Seems dubious
652 LP64_ONLY(assert(false, "shouldn't have that prefix"));
653 assert(ip == inst+1, "only one prefix allowed");
654 goto again_after_prefix;
655
656 case 0x67:
657 case REX:
658 case REX_B:
659 case REX_X:
660 case REX_XB:
661 case REX_R:
662 case REX_RB:
663 case REX_RX:
664 case REX_RXB:
665 NOT_LP64(assert(false, "64bit prefixes"));
666 goto again_after_prefix;
667
668 case REX_W:
669 case REX_WB:
670 case REX_WX:
671 case REX_WXB:
672 case REX_WR:
673 case REX_WRB:
674 case REX_WRX:
675 case REX_WRXB:
676 NOT_LP64(assert(false, "64bit prefixes"));
677 is_64bit = true;
678 goto again_after_prefix;
679
680 case 0xFF: // pushq a; decl a; incl a; call a; jmp a
681 case 0x88: // movb a, r
682 case 0x89: // movl a, r
683 case 0x8A: // movb r, a
684 case 0x8B: // movl r, a
685 case 0x8F: // popl a
686 debug_only(has_disp32 = true);
687 break;
688
689 case 0x68: // pushq #32
690 if (which == end_pc_operand) {
691 return ip + 4;
692 }
693 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate");
694 return ip; // not produced by emit_operand
695
696 case 0x66: // movw ... (size prefix)
697 again_after_size_prefix2:
698 switch (0xFF & *ip++) {
699 case REX:
700 case REX_B:
701 case REX_X:
702 case REX_XB:
703 case REX_R:
704 case REX_RB:
705 case REX_RX:
706 case REX_RXB:
707 case REX_W:
708 case REX_WB:
709 case REX_WX:
710 case REX_WXB:
711 case REX_WR:
712 case REX_WRB:
713 case REX_WRX:
714 case REX_WRXB:
715 NOT_LP64(assert(false, "64bit prefix found"));
716 goto again_after_size_prefix2;
717 case 0x8B: // movw r, a
718 case 0x89: // movw a, r
719 debug_only(has_disp32 = true);
720 break;
721 case 0xC7: // movw a, #16
722 debug_only(has_disp32 = true);
723 tail_size = 2; // the imm16
724 break;
725 case 0x0F: // several SSE/SSE2 variants
726 ip--; // reparse the 0x0F
727 goto again_after_prefix;
728 default:
729 ShouldNotReachHere();
730 }
731 break;
732
733 case REP8(0xB8): // movl/q r, #32/#64(oop?)
734 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4);
735 // these asserts are somewhat nonsensical
736 #ifndef _LP64
737 assert(which == imm_operand || which == disp32_operand,
738 "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip));
739 #else
740 assert((which == call32_operand || which == imm_operand) && is_64bit ||
741 which == narrow_oop_operand && !is_64bit,
742 "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip));
743 #endif // _LP64
744 return ip;
745
746 case 0x69: // imul r, a, #32
747 case 0xC7: // movl a, #32(oop?)
748 tail_size = 4;
749 debug_only(has_disp32 = true); // has both kinds of operands!
750 break;
751
752 case 0x0F: // movx..., etc.
753 switch (0xFF & *ip++) {
754 case 0x3A: // pcmpestri
755 tail_size = 1;
756 case 0x38: // ptest, pmovzxbw
757 ip++; // skip opcode
758 debug_only(has_disp32 = true); // has both kinds of operands!
759 break;
760
761 case 0x70: // pshufd r, r/a, #8
762 debug_only(has_disp32 = true); // has both kinds of operands!
763 case 0x73: // psrldq r, #8
764 tail_size = 1;
765 break;
766
767 case 0x12: // movlps
768 case 0x28: // movaps
769 case 0x2E: // ucomiss
770 case 0x2F: // comiss
771 case 0x54: // andps
772 case 0x55: // andnps
773 case 0x56: // orps
774 case 0x57: // xorps
775 case 0x58: // addpd
776 case 0x59: // mulpd
777 case 0x6E: // movd
778 case 0x7E: // movd
779 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush
780 case 0xFE: // paddd
781 debug_only(has_disp32 = true);
782 break;
783
784 case 0xAD: // shrd r, a, %cl
785 case 0xAF: // imul r, a
786 case 0xBE: // movsbl r, a (movsxb)
787 case 0xBF: // movswl r, a (movsxw)
788 case 0xB6: // movzbl r, a (movzxb)
789 case 0xB7: // movzwl r, a (movzxw)
790 case REP16(0x40): // cmovl cc, r, a
791 case 0xB0: // cmpxchgb
792 case 0xB1: // cmpxchg
793 case 0xC1: // xaddl
794 case 0xC7: // cmpxchg8
795 case REP16(0x90): // setcc a
796 debug_only(has_disp32 = true);
797 // fall out of the switch to decode the address
798 break;
799
800 case 0xC4: // pinsrw r, a, #8
801 debug_only(has_disp32 = true);
802 case 0xC5: // pextrw r, r, #8
803 tail_size = 1; // the imm8
804 break;
805
806 case 0xAC: // shrd r, a, #8
807 debug_only(has_disp32 = true);
808 tail_size = 1; // the imm8
809 break;
810
811 case REP16(0x80): // jcc rdisp32
812 if (which == end_pc_operand) return ip + 4;
813 assert(which == call32_operand, "jcc has no disp32 or imm");
814 return ip;
815 default:
816 ShouldNotReachHere();
817 }
818 break;
819
820 case 0x81: // addl a, #32; addl r, #32
821 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
822 // on 32bit in the case of cmpl, the imm might be an oop
823 tail_size = 4;
824 debug_only(has_disp32 = true); // has both kinds of operands!
825 break;
826
827 case 0x83: // addl a, #8; addl r, #8
828 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
829 debug_only(has_disp32 = true); // has both kinds of operands!
830 tail_size = 1;
831 break;
832
833 case 0x9B:
834 switch (0xFF & *ip++) {
835 case 0xD9: // fnstcw a
836 debug_only(has_disp32 = true);
837 break;
838 default:
839 ShouldNotReachHere();
840 }
841 break;
842
843 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a
844 case REP4(0x10): // adc...
845 case REP4(0x20): // and...
846 case REP4(0x30): // xor...
847 case REP4(0x08): // or...
848 case REP4(0x18): // sbb...
849 case REP4(0x28): // sub...
850 case 0xF7: // mull a
851 case 0x8D: // lea r, a
852 case 0x87: // xchg r, a
853 case REP4(0x38): // cmp...
854 case 0x85: // test r, a
855 debug_only(has_disp32 = true); // has both kinds of operands!
856 break;
857
858 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8
859 case 0xC6: // movb a, #8
860 case 0x80: // cmpb a, #8
861 case 0x6B: // imul r, a, #8
862 debug_only(has_disp32 = true); // has both kinds of operands!
863 tail_size = 1; // the imm8
864 break;
865
866 case 0xC4: // VEX_3bytes
867 case 0xC5: // VEX_2bytes
868 assert((UseAVX > 0), "shouldn't have VEX prefix");
869 assert(ip == inst+1, "no prefixes allowed");
870 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions
871 // but they have prefix 0x0F and processed when 0x0F processed above.
872 //
873 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES
874 // instructions (these instructions are not supported in 64-bit mode).
875 // To distinguish them bits [7:6] are set in the VEX second byte since
876 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set
877 // those VEX bits REX and vvvv bits are inverted.
878 //
879 // Fortunately C2 doesn't generate these instructions so we don't need
880 // to check for them in product version.
881
882 // Check second byte
883 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions"));
884
885 int vex_opcode;
886 // First byte
887 if ((0xFF & *inst) == VEX_3bytes) {
888 vex_opcode = VEX_OPCODE_MASK & *ip;
889 ip++; // third byte
890 is_64bit = ((VEX_W & *ip) == VEX_W);
891 } else {
892 vex_opcode = VEX_OPCODE_0F;
893 }
894 ip++; // opcode
895 // To find the end of instruction (which == end_pc_operand).
896 switch (vex_opcode) {
897 case VEX_OPCODE_0F:
898 switch (0xFF & *ip) {
899 case 0x70: // pshufd r, r/a, #8
900 case 0x71: // ps[rl|ra|ll]w r, #8
901 case 0x72: // ps[rl|ra|ll]d r, #8
902 case 0x73: // ps[rl|ra|ll]q r, #8
903 case 0xC2: // cmp[ps|pd|ss|sd] r, r, r/a, #8
904 case 0xC4: // pinsrw r, r, r/a, #8
905 case 0xC5: // pextrw r/a, r, #8
906 case 0xC6: // shufp[s|d] r, r, r/a, #8
907 tail_size = 1; // the imm8
908 break;
909 }
910 break;
911 case VEX_OPCODE_0F_3A:
912 tail_size = 1;
913 break;
914 }
915 ip++; // skip opcode
916 debug_only(has_disp32 = true); // has both kinds of operands!
917 break;
918
919 case 0x62: // EVEX_4bytes
920 assert((UseAVX > 0), "shouldn't have EVEX prefix");
921 assert(ip == inst+1, "no prefixes allowed");
922 // no EVEX collisions, all instructions that have 0x62 opcodes
923 // have EVEX versions and are subopcodes of 0x66
924 ip++; // skip P0 and exmaine W in P1
925 is_64bit = ((VEX_W & *ip) == VEX_W);
926 ip++; // move to P2
927 ip++; // skip P2, move to opcode
928 // To find the end of instruction (which == end_pc_operand).
929 switch (0xFF & *ip) {
930 case 0x22: // pinsrd r, r/a, #8
931 case 0x61: // pcmpestri r, r/a, #8
932 case 0x70: // pshufd r, r/a, #8
933 case 0x73: // psrldq r, #8
934 tail_size = 1; // the imm8
935 break;
936 default:
937 break;
938 }
939 ip++; // skip opcode
940 debug_only(has_disp32 = true); // has both kinds of operands!
941 break;
942
943 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
944 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
945 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a
946 case 0xDD: // fld_d a; fst_d a; fstp_d a
947 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a
948 case 0xDF: // fild_d a; fistp_d a
949 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a
950 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a
951 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a
952 debug_only(has_disp32 = true);
953 break;
954
955 case 0xE8: // call rdisp32
956 case 0xE9: // jmp rdisp32
957 if (which == end_pc_operand) return ip + 4;
958 assert(which == call32_operand, "call has no disp32 or imm");
959 return ip;
960
961 case 0xF0: // Lock
962 assert(os::is_MP(), "only on MP");
963 goto again_after_prefix;
964
965 case 0xF3: // For SSE
966 case 0xF2: // For SSE2
967 switch (0xFF & *ip++) {
968 case REX:
969 case REX_B:
970 case REX_X:
971 case REX_XB:
972 case REX_R:
973 case REX_RB:
974 case REX_RX:
975 case REX_RXB:
976 case REX_W:
977 case REX_WB:
978 case REX_WX:
979 case REX_WXB:
980 case REX_WR:
981 case REX_WRB:
982 case REX_WRX:
983 case REX_WRXB:
984 NOT_LP64(assert(false, "found 64bit prefix"));
985 ip++;
986 default:
987 ip++;
988 }
989 debug_only(has_disp32 = true); // has both kinds of operands!
990 break;
991
992 default:
993 ShouldNotReachHere();
994
995 #undef REP8
996 #undef REP16
997 }
998
999 assert(which != call32_operand, "instruction is not a call, jmp, or jcc");
1000 #ifdef _LP64
1001 assert(which != imm_operand, "instruction is not a movq reg, imm64");
1002 #else
1003 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field");
1004 assert(which != imm_operand || has_disp32, "instruction has no imm32 field");
1005 #endif // LP64
1006 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field");
1007
1008 // parse the output of emit_operand
1009 int op2 = 0xFF & *ip++;
1010 int base = op2 & 0x07;
1011 int op3 = -1;
1012 const int b100 = 4;
1013 const int b101 = 5;
1014 if (base == b100 && (op2 >> 6) != 3) {
1015 op3 = 0xFF & *ip++;
1016 base = op3 & 0x07; // refetch the base
1017 }
1018 // now ip points at the disp (if any)
1019
1020 switch (op2 >> 6) {
1021 case 0:
1022 // [00 reg 100][ss index base]
1023 // [00 reg 100][00 100 esp]
1024 // [00 reg base]
1025 // [00 reg 100][ss index 101][disp32]
1026 // [00 reg 101] [disp32]
1027
1028 if (base == b101) {
1029 if (which == disp32_operand)
1030 return ip; // caller wants the disp32
1031 ip += 4; // skip the disp32
1032 }
1033 break;
1034
1035 case 1:
1036 // [01 reg 100][ss index base][disp8]
1037 // [01 reg 100][00 100 esp][disp8]
1038 // [01 reg base] [disp8]
1039 ip += 1; // skip the disp8
1040 break;
1041
1042 case 2:
1043 // [10 reg 100][ss index base][disp32]
1044 // [10 reg 100][00 100 esp][disp32]
1045 // [10 reg base] [disp32]
1046 if (which == disp32_operand)
1047 return ip; // caller wants the disp32
1048 ip += 4; // skip the disp32
1049 break;
1050
1051 case 3:
1052 // [11 reg base] (not a memory addressing mode)
1053 break;
1054 }
1055
1056 if (which == end_pc_operand) {
1057 return ip + tail_size;
1058 }
1059
1060 #ifdef _LP64
1061 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32");
1062 #else
1063 assert(which == imm_operand, "instruction has only an imm field");
1064 #endif // LP64
1065 return ip;
1066 }
1067
1068 address Assembler::locate_next_instruction(address inst) {
1069 // Secretly share code with locate_operand:
1070 return locate_operand(inst, end_pc_operand);
1071 }
1072
1073
1074 #ifdef ASSERT
1075 void Assembler::check_relocation(RelocationHolder const& rspec, int format) {
1076 address inst = inst_mark();
1077 assert(inst != NULL && inst < pc(), "must point to beginning of instruction");
1078 address opnd;
1079
1080 Relocation* r = rspec.reloc();
1081 if (r->type() == relocInfo::none) {
1082 return;
1083 } else if (r->is_call() || format == call32_operand) {
1084 // assert(format == imm32_operand, "cannot specify a nonzero format");
1085 opnd = locate_operand(inst, call32_operand);
1086 } else if (r->is_data()) {
1087 assert(format == imm_operand || format == disp32_operand
1088 LP64_ONLY(|| format == narrow_oop_operand), "format ok");
1089 opnd = locate_operand(inst, (WhichOperand)format);
1090 } else {
1091 assert(format == imm_operand, "cannot specify a format");
1092 return;
1093 }
1094 assert(opnd == pc(), "must put operand where relocs can find it");
1095 }
1096 #endif // ASSERT
1097
1098 void Assembler::emit_operand32(Register reg, Address adr) {
1099 assert(reg->encoding() < 8, "no extended registers");
1100 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1101 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1102 adr._rspec);
1103 }
1104
1105 void Assembler::emit_operand(Register reg, Address adr,
1106 int rip_relative_correction) {
1107 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1108 adr._rspec,
1109 rip_relative_correction);
1110 }
1111
1112 void Assembler::emit_operand(XMMRegister reg, Address adr) {
1113 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1114 adr._rspec);
1115 }
1116
1117 // MMX operations
1118 void Assembler::emit_operand(MMXRegister reg, Address adr) {
1119 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1120 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1121 }
1122
1123 // work around gcc (3.2.1-7a) bug
1124 void Assembler::emit_operand(Address adr, MMXRegister reg) {
1125 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1126 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1127 }
1128
1129
1130 void Assembler::emit_farith(int b1, int b2, int i) {
1131 assert(isByte(b1) && isByte(b2), "wrong opcode");
1132 assert(0 <= i && i < 8, "illegal stack offset");
1133 emit_int8(b1);
1134 emit_int8(b2 + i);
1135 }
1136
1137
1138 // Now the Assembler instructions (identical for 32/64 bits)
1139
1140 void Assembler::adcl(Address dst, int32_t imm32) {
1141 InstructionMark im(this);
1142 prefix(dst);
1143 emit_arith_operand(0x81, rdx, dst, imm32);
1144 }
1145
1146 void Assembler::adcl(Address dst, Register src) {
1147 InstructionMark im(this);
1148 prefix(dst, src);
1149 emit_int8(0x11);
1150 emit_operand(src, dst);
1151 }
1152
1153 void Assembler::adcl(Register dst, int32_t imm32) {
1154 prefix(dst);
1155 emit_arith(0x81, 0xD0, dst, imm32);
1156 }
1157
1158 void Assembler::adcl(Register dst, Address src) {
1159 InstructionMark im(this);
1160 prefix(src, dst);
1161 emit_int8(0x13);
1162 emit_operand(dst, src);
1163 }
1164
1165 void Assembler::adcl(Register dst, Register src) {
1166 (void) prefix_and_encode(dst->encoding(), src->encoding());
1167 emit_arith(0x13, 0xC0, dst, src);
1168 }
1169
1170 void Assembler::addl(Address dst, int32_t imm32) {
1171 InstructionMark im(this);
1172 prefix(dst);
1173 emit_arith_operand(0x81, rax, dst, imm32);
1174 }
1175
1176 void Assembler::addl(Address dst, Register src) {
1177 InstructionMark im(this);
1178 prefix(dst, src);
1179 emit_int8(0x01);
1180 emit_operand(src, dst);
1181 }
1182
1183 void Assembler::addl(Register dst, int32_t imm32) {
1184 prefix(dst);
1185 emit_arith(0x81, 0xC0, dst, imm32);
1186 }
1187
1188 void Assembler::addl(Register dst, Address src) {
1189 InstructionMark im(this);
1190 prefix(src, dst);
1191 emit_int8(0x03);
1192 emit_operand(dst, src);
1193 }
1194
1195 void Assembler::addl(Register dst, Register src) {
1196 (void) prefix_and_encode(dst->encoding(), src->encoding());
1197 emit_arith(0x03, 0xC0, dst, src);
1198 }
1199
1200 void Assembler::addr_nop_4() {
1201 assert(UseAddressNop, "no CPU support");
1202 // 4 bytes: NOP DWORD PTR [EAX+0]
1203 emit_int8(0x0F);
1204 emit_int8(0x1F);
1205 emit_int8(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
1206 emit_int8(0); // 8-bits offset (1 byte)
1207 }
1208
1209 void Assembler::addr_nop_5() {
1210 assert(UseAddressNop, "no CPU support");
1211 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
1212 emit_int8(0x0F);
1213 emit_int8(0x1F);
1214 emit_int8(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
1215 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1216 emit_int8(0); // 8-bits offset (1 byte)
1217 }
1218
1219 void Assembler::addr_nop_7() {
1220 assert(UseAddressNop, "no CPU support");
1221 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
1222 emit_int8(0x0F);
1223 emit_int8(0x1F);
1224 emit_int8((unsigned char)0x80);
1225 // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
1226 emit_int32(0); // 32-bits offset (4 bytes)
1227 }
1228
1229 void Assembler::addr_nop_8() {
1230 assert(UseAddressNop, "no CPU support");
1231 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
1232 emit_int8(0x0F);
1233 emit_int8(0x1F);
1234 emit_int8((unsigned char)0x84);
1235 // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
1236 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1237 emit_int32(0); // 32-bits offset (4 bytes)
1238 }
1239
1240 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
1241 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1242 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1243 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1244 emit_int8(0x58);
1245 emit_int8((unsigned char)(0xC0 | encode));
1246 }
1247
1248 void Assembler::addsd(XMMRegister dst, Address src) {
1249 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1250 InstructionMark im(this);
1251 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1252 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1253 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1254 emit_int8(0x58);
1255 emit_operand(dst, src);
1256 }
1257
1258 void Assembler::addss(XMMRegister dst, XMMRegister src) {
1259 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1260 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1261 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1262 emit_int8(0x58);
1263 emit_int8((unsigned char)(0xC0 | encode));
1264 }
1265
1266 void Assembler::addss(XMMRegister dst, Address src) {
1267 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1268 InstructionMark im(this);
1269 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1270 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1271 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1272 emit_int8(0x58);
1273 emit_operand(dst, src);
1274 }
1275
1276 void Assembler::aesdec(XMMRegister dst, Address src) {
1277 assert(VM_Version::supports_aes(), "");
1278 InstructionMark im(this);
1279 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1280 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1281 emit_int8((unsigned char)0xDE);
1282 emit_operand(dst, src);
1283 }
1284
1285 void Assembler::aesdec(XMMRegister dst, XMMRegister src) {
1286 assert(VM_Version::supports_aes(), "");
1287 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1288 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1289 emit_int8((unsigned char)0xDE);
1290 emit_int8(0xC0 | encode);
1291 }
1292
1293 void Assembler::aesdeclast(XMMRegister dst, Address src) {
1294 assert(VM_Version::supports_aes(), "");
1295 InstructionMark im(this);
1296 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1297 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1298 emit_int8((unsigned char)0xDF);
1299 emit_operand(dst, src);
1300 }
1301
1302 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) {
1303 assert(VM_Version::supports_aes(), "");
1304 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1305 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1306 emit_int8((unsigned char)0xDF);
1307 emit_int8((unsigned char)(0xC0 | encode));
1308 }
1309
1310 void Assembler::aesenc(XMMRegister dst, Address src) {
1311 assert(VM_Version::supports_aes(), "");
1312 InstructionMark im(this);
1313 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1314 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1315 emit_int8((unsigned char)0xDC);
1316 emit_operand(dst, src);
1317 }
1318
1319 void Assembler::aesenc(XMMRegister dst, XMMRegister src) {
1320 assert(VM_Version::supports_aes(), "");
1321 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1322 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1323 emit_int8((unsigned char)0xDC);
1324 emit_int8(0xC0 | encode);
1325 }
1326
1327 void Assembler::aesenclast(XMMRegister dst, Address src) {
1328 assert(VM_Version::supports_aes(), "");
1329 InstructionMark im(this);
1330 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1331 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1332 emit_int8((unsigned char)0xDD);
1333 emit_operand(dst, src);
1334 }
1335
1336 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) {
1337 assert(VM_Version::supports_aes(), "");
1338 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1339 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1340 emit_int8((unsigned char)0xDD);
1341 emit_int8((unsigned char)(0xC0 | encode));
1342 }
1343
1344 void Assembler::andl(Address dst, int32_t imm32) {
1345 InstructionMark im(this);
1346 prefix(dst);
1347 emit_int8((unsigned char)0x81);
1348 emit_operand(rsp, dst, 4);
1349 emit_int32(imm32);
1350 }
1351
1352 void Assembler::andl(Register dst, int32_t imm32) {
1353 prefix(dst);
1354 emit_arith(0x81, 0xE0, dst, imm32);
1355 }
1356
1357 void Assembler::andl(Register dst, Address src) {
1358 InstructionMark im(this);
1359 prefix(src, dst);
1360 emit_int8(0x23);
1361 emit_operand(dst, src);
1362 }
1363
1364 void Assembler::andl(Register dst, Register src) {
1365 (void) prefix_and_encode(dst->encoding(), src->encoding());
1366 emit_arith(0x23, 0xC0, dst, src);
1367 }
1368
1369 void Assembler::andnl(Register dst, Register src1, Register src2) {
1370 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1371 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1372 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1373 emit_int8((unsigned char)0xF2);
1374 emit_int8((unsigned char)(0xC0 | encode));
1375 }
1376
1377 void Assembler::andnl(Register dst, Register src1, Address src2) {
1378 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1379 InstructionMark im(this);
1380 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1381 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1382 emit_int8((unsigned char)0xF2);
1383 emit_operand(dst, src2);
1384 }
1385
1386 void Assembler::bsfl(Register dst, Register src) {
1387 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1388 emit_int8(0x0F);
1389 emit_int8((unsigned char)0xBC);
1390 emit_int8((unsigned char)(0xC0 | encode));
1391 }
1392
1393 void Assembler::bsrl(Register dst, Register src) {
1394 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1395 emit_int8(0x0F);
1396 emit_int8((unsigned char)0xBD);
1397 emit_int8((unsigned char)(0xC0 | encode));
1398 }
1399
1400 void Assembler::bswapl(Register reg) { // bswap
1401 int encode = prefix_and_encode(reg->encoding());
1402 emit_int8(0x0F);
1403 emit_int8((unsigned char)(0xC8 | encode));
1404 }
1405
1406 void Assembler::blsil(Register dst, Register src) {
1407 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1408 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1409 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1410 emit_int8((unsigned char)0xF3);
1411 emit_int8((unsigned char)(0xC0 | encode));
1412 }
1413
1414 void Assembler::blsil(Register dst, Address src) {
1415 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1416 InstructionMark im(this);
1417 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1418 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1419 emit_int8((unsigned char)0xF3);
1420 emit_operand(rbx, src);
1421 }
1422
1423 void Assembler::blsmskl(Register dst, Register src) {
1424 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1425 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1426 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1427 emit_int8((unsigned char)0xF3);
1428 emit_int8((unsigned char)(0xC0 | encode));
1429 }
1430
1431 void Assembler::blsmskl(Register dst, Address src) {
1432 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1433 InstructionMark im(this);
1434 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1435 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1436 emit_int8((unsigned char)0xF3);
1437 emit_operand(rdx, src);
1438 }
1439
1440 void Assembler::blsrl(Register dst, Register src) {
1441 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1442 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1443 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1444 emit_int8((unsigned char)0xF3);
1445 emit_int8((unsigned char)(0xC0 | encode));
1446 }
1447
1448 void Assembler::blsrl(Register dst, Address src) {
1449 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1450 InstructionMark im(this);
1451 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1452 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1453 emit_int8((unsigned char)0xF3);
1454 emit_operand(rcx, src);
1455 }
1456
1457 void Assembler::call(Label& L, relocInfo::relocType rtype) {
1458 // suspect disp32 is always good
1459 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
1460
1461 if (L.is_bound()) {
1462 const int long_size = 5;
1463 int offs = (int)( target(L) - pc() );
1464 assert(offs <= 0, "assembler error");
1465 InstructionMark im(this);
1466 // 1110 1000 #32-bit disp
1467 emit_int8((unsigned char)0xE8);
1468 emit_data(offs - long_size, rtype, operand);
1469 } else {
1470 InstructionMark im(this);
1471 // 1110 1000 #32-bit disp
1472 L.add_patch_at(code(), locator());
1473
1474 emit_int8((unsigned char)0xE8);
1475 emit_data(int(0), rtype, operand);
1476 }
1477 }
1478
1479 void Assembler::call(Register dst) {
1480 int encode = prefix_and_encode(dst->encoding());
1481 emit_int8((unsigned char)0xFF);
1482 emit_int8((unsigned char)(0xD0 | encode));
1483 }
1484
1485
1486 void Assembler::call(Address adr) {
1487 InstructionMark im(this);
1488 prefix(adr);
1489 emit_int8((unsigned char)0xFF);
1490 emit_operand(rdx, adr);
1491 }
1492
1493 void Assembler::call_literal(address entry, RelocationHolder const& rspec) {
1494 assert(entry != NULL, "call most probably wrong");
1495 InstructionMark im(this);
1496 emit_int8((unsigned char)0xE8);
1497 intptr_t disp = entry - (pc() + sizeof(int32_t));
1498 assert(is_simm32(disp), "must be 32bit offset (call2)");
1499 // Technically, should use call32_operand, but this format is
1500 // implied by the fact that we're emitting a call instruction.
1501
1502 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand);
1503 emit_data((int) disp, rspec, operand);
1504 }
1505
1506 void Assembler::cdql() {
1507 emit_int8((unsigned char)0x99);
1508 }
1509
1510 void Assembler::cld() {
1511 emit_int8((unsigned char)0xFC);
1512 }
1513
1514 void Assembler::cmovl(Condition cc, Register dst, Register src) {
1515 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1516 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1517 emit_int8(0x0F);
1518 emit_int8(0x40 | cc);
1519 emit_int8((unsigned char)(0xC0 | encode));
1520 }
1521
1522
1523 void Assembler::cmovl(Condition cc, Register dst, Address src) {
1524 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1525 prefix(src, dst);
1526 emit_int8(0x0F);
1527 emit_int8(0x40 | cc);
1528 emit_operand(dst, src);
1529 }
1530
1531 void Assembler::cmpb(Address dst, int imm8) {
1532 InstructionMark im(this);
1533 prefix(dst);
1534 emit_int8((unsigned char)0x80);
1535 emit_operand(rdi, dst, 1);
1536 emit_int8(imm8);
1537 }
1538
1539 void Assembler::cmpl(Address dst, int32_t imm32) {
1540 InstructionMark im(this);
1541 prefix(dst);
1542 emit_int8((unsigned char)0x81);
1543 emit_operand(rdi, dst, 4);
1544 emit_int32(imm32);
1545 }
1546
1547 void Assembler::cmpl(Register dst, int32_t imm32) {
1548 prefix(dst);
1549 emit_arith(0x81, 0xF8, dst, imm32);
1550 }
1551
1552 void Assembler::cmpl(Register dst, Register src) {
1553 (void) prefix_and_encode(dst->encoding(), src->encoding());
1554 emit_arith(0x3B, 0xC0, dst, src);
1555 }
1556
1557 void Assembler::cmpl(Register dst, Address src) {
1558 InstructionMark im(this);
1559 prefix(src, dst);
1560 emit_int8((unsigned char)0x3B);
1561 emit_operand(dst, src);
1562 }
1563
1564 void Assembler::cmpw(Address dst, int imm16) {
1565 InstructionMark im(this);
1566 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers");
1567 emit_int8(0x66);
1568 emit_int8((unsigned char)0x81);
1569 emit_operand(rdi, dst, 2);
1570 emit_int16(imm16);
1571 }
1572
1573 // The 32-bit cmpxchg compares the value at adr with the contents of rax,
1574 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1575 // The ZF is set if the compared values were equal, and cleared otherwise.
1576 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg
1577 InstructionMark im(this);
1578 prefix(adr, reg);
1579 emit_int8(0x0F);
1580 emit_int8((unsigned char)0xB1);
1581 emit_operand(reg, adr);
1582 }
1583
1584 // The 8-bit cmpxchg compares the value at adr with the contents of rax,
1585 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1586 // The ZF is set if the compared values were equal, and cleared otherwise.
1587 void Assembler::cmpxchgb(Register reg, Address adr) { // cmpxchg
1588 InstructionMark im(this);
1589 prefix(adr, reg, true);
1590 emit_int8(0x0F);
1591 emit_int8((unsigned char)0xB0);
1592 emit_operand(reg, adr);
1593 }
1594
1595 void Assembler::comisd(XMMRegister dst, Address src) {
1596 // NOTE: dbx seems to decode this as comiss even though the
1597 // 0x66 is there. Strangly ucomisd comes out correct
1598 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1599 InstructionMark im(this);
1600 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);;
1601 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1602 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1603 emit_int8(0x2F);
1604 emit_operand(dst, src);
1605 }
1606
1607 void Assembler::comisd(XMMRegister dst, XMMRegister src) {
1608 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1609 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1610 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1611 emit_int8(0x2F);
1612 emit_int8((unsigned char)(0xC0 | encode));
1613 }
1614
1615 void Assembler::comiss(XMMRegister dst, Address src) {
1616 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1617 InstructionMark im(this);
1618 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1619 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1620 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1621 emit_int8(0x2F);
1622 emit_operand(dst, src);
1623 }
1624
1625 void Assembler::comiss(XMMRegister dst, XMMRegister src) {
1626 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1627 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1628 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1629 emit_int8(0x2F);
1630 emit_int8((unsigned char)(0xC0 | encode));
1631 }
1632
1633 void Assembler::cpuid() {
1634 emit_int8(0x0F);
1635 emit_int8((unsigned char)0xA2);
1636 }
1637
1638 // Opcode / Instruction Op / En 64 - Bit Mode Compat / Leg Mode Description Implemented
1639 // F2 0F 38 F0 / r CRC32 r32, r / m8 RM Valid Valid Accumulate CRC32 on r / m8. v
1640 // F2 REX 0F 38 F0 / r CRC32 r32, r / m8* RM Valid N.E. Accumulate CRC32 on r / m8. -
1641 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E. Accumulate CRC32 on r / m8. -
1642 //
1643 // F2 0F 38 F1 / r CRC32 r32, r / m16 RM Valid Valid Accumulate CRC32 on r / m16. v
1644 //
1645 // F2 0F 38 F1 / r CRC32 r32, r / m32 RM Valid Valid Accumulate CRC32 on r / m32. v
1646 //
1647 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E. Accumulate CRC32 on r / m64. v
1648 void Assembler::crc32(Register crc, Register v, int8_t sizeInBytes) {
1649 assert(VM_Version::supports_sse4_2(), "");
1650 int8_t w = 0x01;
1651 Prefix p = Prefix_EMPTY;
1652
1653 emit_int8((int8_t)0xF2);
1654 switch (sizeInBytes) {
1655 case 1:
1656 w = 0;
1657 break;
1658 case 2:
1659 case 4:
1660 break;
1661 LP64_ONLY(case 8:)
1662 // This instruction is not valid in 32 bits
1663 // Note:
1664 // http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
1665 //
1666 // Page B - 72 Vol. 2C says
1667 // qwreg2 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : 11 qwreg1 qwreg2
1668 // mem64 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : mod qwreg r / m
1669 // F0!!!
1670 // while 3 - 208 Vol. 2A
1671 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E.Accumulate CRC32 on r / m64.
1672 //
1673 // the 0 on a last bit is reserved for a different flavor of this instruction :
1674 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E.Accumulate CRC32 on r / m8.
1675 p = REX_W;
1676 break;
1677 default:
1678 assert(0, "Unsupported value for a sizeInBytes argument");
1679 break;
1680 }
1681 LP64_ONLY(prefix(crc, v, p);)
1682 emit_int8((int8_t)0x0F);
1683 emit_int8(0x38);
1684 emit_int8((int8_t)(0xF0 | w));
1685 emit_int8(0xC0 | ((crc->encoding() & 0x7) << 3) | (v->encoding() & 7));
1686 }
1687
1688 void Assembler::crc32(Register crc, Address adr, int8_t sizeInBytes) {
1689 assert(VM_Version::supports_sse4_2(), "");
1690 InstructionMark im(this);
1691 int8_t w = 0x01;
1692 Prefix p = Prefix_EMPTY;
1693
1694 emit_int8((int8_t)0xF2);
1695 switch (sizeInBytes) {
1696 case 1:
1697 w = 0;
1698 break;
1699 case 2:
1700 case 4:
1701 break;
1702 LP64_ONLY(case 8:)
1703 // This instruction is not valid in 32 bits
1704 p = REX_W;
1705 break;
1706 default:
1707 assert(0, "Unsupported value for a sizeInBytes argument");
1708 break;
1709 }
1710 LP64_ONLY(prefix(crc, adr, p);)
1711 emit_int8((int8_t)0x0F);
1712 emit_int8(0x38);
1713 emit_int8((int8_t)(0xF0 | w));
1714 emit_operand(crc, adr);
1715 }
1716
1717 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
1718 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1719 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
1720 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1721 emit_int8((unsigned char)0xE6);
1722 emit_int8((unsigned char)(0xC0 | encode));
1723 }
1724
1725 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
1726 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1727 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
1728 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1729 emit_int8(0x5B);
1730 emit_int8((unsigned char)(0xC0 | encode));
1731 }
1732
1733 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
1734 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1735 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1736 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1737 emit_int8(0x5A);
1738 emit_int8((unsigned char)(0xC0 | encode));
1739 }
1740
1741 void Assembler::cvtsd2ss(XMMRegister dst, Address src) {
1742 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1743 InstructionMark im(this);
1744 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1745 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1746 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1747 emit_int8(0x5A);
1748 emit_operand(dst, src);
1749 }
1750
1751 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
1752 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1753 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1754 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1755 emit_int8(0x2A);
1756 emit_int8((unsigned char)(0xC0 | encode));
1757 }
1758
1759 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) {
1760 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1761 InstructionMark im(this);
1762 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1763 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1764 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1765 emit_int8(0x2A);
1766 emit_operand(dst, src);
1767 }
1768
1769 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
1770 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1771 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1772 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1773 emit_int8(0x2A);
1774 emit_int8((unsigned char)(0xC0 | encode));
1775 }
1776
1777 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) {
1778 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1779 InstructionMark im(this);
1780 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1781 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1782 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1783 emit_int8(0x2A);
1784 emit_operand(dst, src);
1785 }
1786
1787 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
1788 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1789 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1790 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1791 emit_int8(0x2A);
1792 emit_int8((unsigned char)(0xC0 | encode));
1793 }
1794
1795 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
1796 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1797 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1798 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1799 emit_int8(0x5A);
1800 emit_int8((unsigned char)(0xC0 | encode));
1801 }
1802
1803 void Assembler::cvtss2sd(XMMRegister dst, Address src) {
1804 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1805 InstructionMark im(this);
1806 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1807 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1808 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1809 emit_int8(0x5A);
1810 emit_operand(dst, src);
1811 }
1812
1813
1814 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
1815 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1816 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1817 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1818 emit_int8(0x2C);
1819 emit_int8((unsigned char)(0xC0 | encode));
1820 }
1821
1822 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
1823 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1824 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1825 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1826 emit_int8(0x2C);
1827 emit_int8((unsigned char)(0xC0 | encode));
1828 }
1829
1830 void Assembler::decl(Address dst) {
1831 // Don't use it directly. Use MacroAssembler::decrement() instead.
1832 InstructionMark im(this);
1833 prefix(dst);
1834 emit_int8((unsigned char)0xFF);
1835 emit_operand(rcx, dst);
1836 }
1837
1838 void Assembler::divsd(XMMRegister dst, Address src) {
1839 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1840 InstructionMark im(this);
1841 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1842 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1843 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1844 emit_int8(0x5E);
1845 emit_operand(dst, src);
1846 }
1847
1848 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
1849 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1850 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1851 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1852 emit_int8(0x5E);
1853 emit_int8((unsigned char)(0xC0 | encode));
1854 }
1855
1856 void Assembler::divss(XMMRegister dst, Address src) {
1857 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1858 InstructionMark im(this);
1859 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1860 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1861 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1862 emit_int8(0x5E);
1863 emit_operand(dst, src);
1864 }
1865
1866 void Assembler::divss(XMMRegister dst, XMMRegister src) {
1867 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1868 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1869 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1870 emit_int8(0x5E);
1871 emit_int8((unsigned char)(0xC0 | encode));
1872 }
1873
1874 void Assembler::emms() {
1875 NOT_LP64(assert(VM_Version::supports_mmx(), ""));
1876 emit_int8(0x0F);
1877 emit_int8(0x77);
1878 }
1879
1880 void Assembler::hlt() {
1881 emit_int8((unsigned char)0xF4);
1882 }
1883
1884 void Assembler::idivl(Register src) {
1885 int encode = prefix_and_encode(src->encoding());
1886 emit_int8((unsigned char)0xF7);
1887 emit_int8((unsigned char)(0xF8 | encode));
1888 }
1889
1890 void Assembler::divl(Register src) { // Unsigned
1891 int encode = prefix_and_encode(src->encoding());
1892 emit_int8((unsigned char)0xF7);
1893 emit_int8((unsigned char)(0xF0 | encode));
1894 }
1895
1896 void Assembler::imull(Register src) {
1897 int encode = prefix_and_encode(src->encoding());
1898 emit_int8((unsigned char)0xF7);
1899 emit_int8((unsigned char)(0xE8 | encode));
1900 }
1901
1902 void Assembler::imull(Register dst, Register src) {
1903 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1904 emit_int8(0x0F);
1905 emit_int8((unsigned char)0xAF);
1906 emit_int8((unsigned char)(0xC0 | encode));
1907 }
1908
1909
1910 void Assembler::imull(Register dst, Register src, int value) {
1911 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1912 if (is8bit(value)) {
1913 emit_int8(0x6B);
1914 emit_int8((unsigned char)(0xC0 | encode));
1915 emit_int8(value & 0xFF);
1916 } else {
1917 emit_int8(0x69);
1918 emit_int8((unsigned char)(0xC0 | encode));
1919 emit_int32(value);
1920 }
1921 }
1922
1923 void Assembler::imull(Register dst, Address src) {
1924 InstructionMark im(this);
1925 prefix(src, dst);
1926 emit_int8(0x0F);
1927 emit_int8((unsigned char) 0xAF);
1928 emit_operand(dst, src);
1929 }
1930
1931
1932 void Assembler::incl(Address dst) {
1933 // Don't use it directly. Use MacroAssembler::increment() instead.
1934 InstructionMark im(this);
1935 prefix(dst);
1936 emit_int8((unsigned char)0xFF);
1937 emit_operand(rax, dst);
1938 }
1939
1940 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) {
1941 InstructionMark im(this);
1942 assert((0 <= cc) && (cc < 16), "illegal cc");
1943 if (L.is_bound()) {
1944 address dst = target(L);
1945 assert(dst != NULL, "jcc most probably wrong");
1946
1947 const int short_size = 2;
1948 const int long_size = 6;
1949 intptr_t offs = (intptr_t)dst - (intptr_t)pc();
1950 if (maybe_short && is8bit(offs - short_size)) {
1951 // 0111 tttn #8-bit disp
1952 emit_int8(0x70 | cc);
1953 emit_int8((offs - short_size) & 0xFF);
1954 } else {
1955 // 0000 1111 1000 tttn #32-bit disp
1956 assert(is_simm32(offs - long_size),
1957 "must be 32bit offset (call4)");
1958 emit_int8(0x0F);
1959 emit_int8((unsigned char)(0x80 | cc));
1960 emit_int32(offs - long_size);
1961 }
1962 } else {
1963 // Note: could eliminate cond. jumps to this jump if condition
1964 // is the same however, seems to be rather unlikely case.
1965 // Note: use jccb() if label to be bound is very close to get
1966 // an 8-bit displacement
1967 L.add_patch_at(code(), locator());
1968 emit_int8(0x0F);
1969 emit_int8((unsigned char)(0x80 | cc));
1970 emit_int32(0);
1971 }
1972 }
1973
1974 void Assembler::jccb(Condition cc, Label& L) {
1975 if (L.is_bound()) {
1976 const int short_size = 2;
1977 address entry = target(L);
1978 #ifdef ASSERT
1979 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
1980 intptr_t delta = short_branch_delta();
1981 if (delta != 0) {
1982 dist += (dist < 0 ? (-delta) :delta);
1983 }
1984 assert(is8bit(dist), "Dispacement too large for a short jmp");
1985 #endif
1986 intptr_t offs = (intptr_t)entry - (intptr_t)pc();
1987 // 0111 tttn #8-bit disp
1988 emit_int8(0x70 | cc);
1989 emit_int8((offs - short_size) & 0xFF);
1990 } else {
1991 InstructionMark im(this);
1992 L.add_patch_at(code(), locator());
1993 emit_int8(0x70 | cc);
1994 emit_int8(0);
1995 }
1996 }
1997
1998 void Assembler::jmp(Address adr) {
1999 InstructionMark im(this);
2000 prefix(adr);
2001 emit_int8((unsigned char)0xFF);
2002 emit_operand(rsp, adr);
2003 }
2004
2005 void Assembler::jmp(Label& L, bool maybe_short) {
2006 if (L.is_bound()) {
2007 address entry = target(L);
2008 assert(entry != NULL, "jmp most probably wrong");
2009 InstructionMark im(this);
2010 const int short_size = 2;
2011 const int long_size = 5;
2012 intptr_t offs = entry - pc();
2013 if (maybe_short && is8bit(offs - short_size)) {
2014 emit_int8((unsigned char)0xEB);
2015 emit_int8((offs - short_size) & 0xFF);
2016 } else {
2017 emit_int8((unsigned char)0xE9);
2018 emit_int32(offs - long_size);
2019 }
2020 } else {
2021 // By default, forward jumps are always 32-bit displacements, since
2022 // we can't yet know where the label will be bound. If you're sure that
2023 // the forward jump will not run beyond 256 bytes, use jmpb to
2024 // force an 8-bit displacement.
2025 InstructionMark im(this);
2026 L.add_patch_at(code(), locator());
2027 emit_int8((unsigned char)0xE9);
2028 emit_int32(0);
2029 }
2030 }
2031
2032 void Assembler::jmp(Register entry) {
2033 int encode = prefix_and_encode(entry->encoding());
2034 emit_int8((unsigned char)0xFF);
2035 emit_int8((unsigned char)(0xE0 | encode));
2036 }
2037
2038 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
2039 InstructionMark im(this);
2040 emit_int8((unsigned char)0xE9);
2041 assert(dest != NULL, "must have a target");
2042 intptr_t disp = dest - (pc() + sizeof(int32_t));
2043 assert(is_simm32(disp), "must be 32bit offset (jmp)");
2044 emit_data(disp, rspec.reloc(), call32_operand);
2045 }
2046
2047 void Assembler::jmpb(Label& L) {
2048 if (L.is_bound()) {
2049 const int short_size = 2;
2050 address entry = target(L);
2051 assert(entry != NULL, "jmp most probably wrong");
2052 #ifdef ASSERT
2053 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
2054 intptr_t delta = short_branch_delta();
2055 if (delta != 0) {
2056 dist += (dist < 0 ? (-delta) :delta);
2057 }
2058 assert(is8bit(dist), "Dispacement too large for a short jmp");
2059 #endif
2060 intptr_t offs = entry - pc();
2061 emit_int8((unsigned char)0xEB);
2062 emit_int8((offs - short_size) & 0xFF);
2063 } else {
2064 InstructionMark im(this);
2065 L.add_patch_at(code(), locator());
2066 emit_int8((unsigned char)0xEB);
2067 emit_int8(0);
2068 }
2069 }
2070
2071 void Assembler::ldmxcsr( Address src) {
2072 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2073 InstructionMark im(this);
2074 prefix(src);
2075 emit_int8(0x0F);
2076 emit_int8((unsigned char)0xAE);
2077 emit_operand(as_Register(2), src);
2078 }
2079
2080 void Assembler::leal(Register dst, Address src) {
2081 InstructionMark im(this);
2082 #ifdef _LP64
2083 emit_int8(0x67); // addr32
2084 prefix(src, dst);
2085 #endif // LP64
2086 emit_int8((unsigned char)0x8D);
2087 emit_operand(dst, src);
2088 }
2089
2090 void Assembler::lfence() {
2091 emit_int8(0x0F);
2092 emit_int8((unsigned char)0xAE);
2093 emit_int8((unsigned char)0xE8);
2094 }
2095
2096 void Assembler::lock() {
2097 emit_int8((unsigned char)0xF0);
2098 }
2099
2100 void Assembler::lzcntl(Register dst, Register src) {
2101 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
2102 emit_int8((unsigned char)0xF3);
2103 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2104 emit_int8(0x0F);
2105 emit_int8((unsigned char)0xBD);
2106 emit_int8((unsigned char)(0xC0 | encode));
2107 }
2108
2109 // Emit mfence instruction
2110 void Assembler::mfence() {
2111 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
2112 emit_int8(0x0F);
2113 emit_int8((unsigned char)0xAE);
2114 emit_int8((unsigned char)0xF0);
2115 }
2116
2117 void Assembler::mov(Register dst, Register src) {
2118 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2119 }
2120
2121 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
2122 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2123 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2124 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2125 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2126 emit_int8(0x28);
2127 emit_int8((unsigned char)(0xC0 | encode));
2128 }
2129
2130 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
2131 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2132 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2133 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2134 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2135 emit_int8(0x28);
2136 emit_int8((unsigned char)(0xC0 | encode));
2137 }
2138
2139 void Assembler::movlhps(XMMRegister dst, XMMRegister src) {
2140 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2141 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2142 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2143 emit_int8(0x16);
2144 emit_int8((unsigned char)(0xC0 | encode));
2145 }
2146
2147 void Assembler::movb(Register dst, Address src) {
2148 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
2149 InstructionMark im(this);
2150 prefix(src, dst, true);
2151 emit_int8((unsigned char)0x8A);
2152 emit_operand(dst, src);
2153 }
2154
2155 void Assembler::movddup(XMMRegister dst, XMMRegister src) {
2156 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
2157 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_128bit;
2158 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2159 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2160 emit_int8(0x12);
2161 emit_int8(0xC0 | encode);
2162 }
2163
2164 void Assembler::kmovbl(KRegister dst, Register src) {
2165 assert(VM_Version::supports_avx512dq(), "");
2166 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2167 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2168 emit_int8((unsigned char)0x92);
2169 emit_int8((unsigned char)(0xC0 | encode));
2170 }
2171
2172 void Assembler::kmovbl(Register dst, KRegister src) {
2173 assert(VM_Version::supports_avx512dq(), "");
2174 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2175 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2176 emit_int8((unsigned char)0x93);
2177 emit_int8((unsigned char)(0xC0 | encode));
2178 }
2179
2180 void Assembler::kmovwl(KRegister dst, Register src) {
2181 assert(VM_Version::supports_evex(), "");
2182 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2183 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2184 emit_int8((unsigned char)0x92);
2185 emit_int8((unsigned char)(0xC0 | encode));
2186 }
2187
2188 void Assembler::kmovwl(Register dst, KRegister src) {
2189 assert(VM_Version::supports_evex(), "");
2190 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2191 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2192 emit_int8((unsigned char)0x93);
2193 emit_int8((unsigned char)(0xC0 | encode));
2194 }
2195
2196 void Assembler::kmovdl(KRegister dst, Register src) {
2197 assert(VM_Version::supports_avx512bw(), "");
2198 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2199 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2200 emit_int8((unsigned char)0x92);
2201 emit_int8((unsigned char)(0xC0 | encode));
2202 }
2203
2204 void Assembler::kmovdl(Register dst, KRegister src) {
2205 assert(VM_Version::supports_avx512bw(), "");
2206 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2207 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2208 emit_int8((unsigned char)0x93);
2209 emit_int8((unsigned char)(0xC0 | encode));
2210 }
2211
2212 void Assembler::kmovql(KRegister dst, KRegister src) {
2213 assert(VM_Version::supports_avx512bw(), "");
2214 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2215 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2216 emit_int8((unsigned char)0x90);
2217 emit_int8((unsigned char)(0xC0 | encode));
2218 }
2219
2220 void Assembler::kmovql(KRegister dst, Address src) {
2221 assert(VM_Version::supports_avx512bw(), "");
2222 InstructionMark im(this);
2223 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2224 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2225 emit_int8((unsigned char)0x90);
2226 emit_operand((Register)dst, src);
2227 }
2228
2229 void Assembler::kmovql(Address dst, KRegister src) {
2230 assert(VM_Version::supports_avx512bw(), "");
2231 InstructionMark im(this);
2232 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2233 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2234 emit_int8((unsigned char)0x90);
2235 emit_operand((Register)src, dst);
2236 }
2237
2238 void Assembler::kmovql(KRegister dst, Register src) {
2239 assert(VM_Version::supports_avx512bw(), "");
2240 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2241 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2242 emit_int8((unsigned char)0x92);
2243 emit_int8((unsigned char)(0xC0 | encode));
2244 }
2245
2246 void Assembler::kmovql(Register dst, KRegister src) {
2247 assert(VM_Version::supports_avx512bw(), "");
2248 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2249 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2250 emit_int8((unsigned char)0x93);
2251 emit_int8((unsigned char)(0xC0 | encode));
2252 }
2253
2254 // This instruction produces ZF or CF flags
2255 void Assembler::kortestbl(KRegister src1, KRegister src2) {
2256 assert(VM_Version::supports_avx512dq(), "");
2257 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2258 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2259 emit_int8((unsigned char)0x98);
2260 emit_int8((unsigned char)(0xC0 | encode));
2261 }
2262
2263 // This instruction produces ZF or CF flags
2264 void Assembler::kortestwl(KRegister src1, KRegister src2) {
2265 assert(VM_Version::supports_evex(), "");
2266 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2267 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2268 emit_int8((unsigned char)0x98);
2269 emit_int8((unsigned char)(0xC0 | encode));
2270 }
2271
2272 // This instruction produces ZF or CF flags
2273 void Assembler::kortestdl(KRegister src1, KRegister src2) {
2274 assert(VM_Version::supports_avx512bw(), "");
2275 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2276 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2277 emit_int8((unsigned char)0x98);
2278 emit_int8((unsigned char)(0xC0 | encode));
2279 }
2280
2281 // This instruction produces ZF or CF flags
2282 void Assembler::kortestql(KRegister src1, KRegister src2) {
2283 assert(VM_Version::supports_avx512bw(), "");
2284 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2285 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2286 emit_int8((unsigned char)0x98);
2287 emit_int8((unsigned char)(0xC0 | encode));
2288 }
2289
2290 void Assembler::movb(Address dst, int imm8) {
2291 InstructionMark im(this);
2292 prefix(dst);
2293 emit_int8((unsigned char)0xC6);
2294 emit_operand(rax, dst, 1);
2295 emit_int8(imm8);
2296 }
2297
2298
2299 void Assembler::movb(Address dst, Register src) {
2300 assert(src->has_byte_register(), "must have byte register");
2301 InstructionMark im(this);
2302 prefix(dst, src, true);
2303 emit_int8((unsigned char)0x88);
2304 emit_operand(src, dst);
2305 }
2306
2307 void Assembler::movdl(XMMRegister dst, Register src) {
2308 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2309 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2310 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2311 emit_int8(0x6E);
2312 emit_int8((unsigned char)(0xC0 | encode));
2313 }
2314
2315 void Assembler::movdl(Register dst, XMMRegister src) {
2316 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2317 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2318 // swap src/dst to get correct prefix
2319 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2320 emit_int8(0x7E);
2321 emit_int8((unsigned char)(0xC0 | encode));
2322 }
2323
2324 void Assembler::movdl(XMMRegister dst, Address src) {
2325 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2326 InstructionMark im(this);
2327 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2328 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2329 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2330 emit_int8(0x6E);
2331 emit_operand(dst, src);
2332 }
2333
2334 void Assembler::movdl(Address dst, XMMRegister src) {
2335 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2336 InstructionMark im(this);
2337 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2338 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2339 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2340 emit_int8(0x7E);
2341 emit_operand(src, dst);
2342 }
2343
2344 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
2345 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2346 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2347 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2348 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2349 emit_int8(0x6F);
2350 emit_int8((unsigned char)(0xC0 | encode));
2351 }
2352
2353 void Assembler::movdqa(XMMRegister dst, Address src) {
2354 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2355 InstructionMark im(this);
2356 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2357 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2358 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2359 emit_int8(0x6F);
2360 emit_operand(dst, src);
2361 }
2362
2363 void Assembler::movdqu(XMMRegister dst, Address src) {
2364 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2365 InstructionMark im(this);
2366 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2367 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2368 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2369 emit_int8(0x6F);
2370 emit_operand(dst, src);
2371 }
2372
2373 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
2374 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2375 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2376 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2377 emit_int8(0x6F);
2378 emit_int8((unsigned char)(0xC0 | encode));
2379 }
2380
2381 void Assembler::movdqu(Address dst, XMMRegister src) {
2382 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2383 InstructionMark im(this);
2384 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2385 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2386 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2387 emit_int8(0x7F);
2388 emit_operand(src, dst);
2389 }
2390
2391 // Move Unaligned 256bit Vector
2392 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2393 assert(UseAVX > 0, "");
2394 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2395 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2396 emit_int8(0x6F);
2397 emit_int8((unsigned char)(0xC0 | encode));
2398 }
2399
2400 void Assembler::vmovdqu(XMMRegister dst, Address src) {
2401 assert(UseAVX > 0, "");
2402 InstructionMark im(this);
2403 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2404 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2405 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2406 emit_int8(0x6F);
2407 emit_operand(dst, src);
2408 }
2409
2410 void Assembler::vmovdqu(Address dst, XMMRegister src) {
2411 assert(UseAVX > 0, "");
2412 InstructionMark im(this);
2413 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2414 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2415 // swap src<->dst for encoding
2416 assert(src != xnoreg, "sanity");
2417 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2418 emit_int8(0x7F);
2419 emit_operand(src, dst);
2420 }
2421
2422 // Move Unaligned EVEX enabled Vector (programmable : 8,16,32,64)
2423 void Assembler::evmovdqub(XMMRegister dst, XMMRegister src, int vector_len) {
2424 assert(VM_Version::supports_evex(), "");
2425 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2426 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2427 emit_int8(0x6F);
2428 emit_int8((unsigned char)(0xC0 | encode));
2429 }
2430
2431 void Assembler::evmovdqub(XMMRegister dst, Address src, int vector_len) {
2432 assert(VM_Version::supports_evex(), "");
2433 InstructionMark im(this);
2434 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2435 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2436 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2437 emit_int8(0x6F);
2438 emit_operand(dst, src);
2439 }
2440
2441 void Assembler::evmovdqub(Address dst, XMMRegister src, int vector_len) {
2442 assert(VM_Version::supports_evex(), "");
2443 assert(src != xnoreg, "sanity");
2444 InstructionMark im(this);
2445 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2446 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2447 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2448 emit_int8(0x7F);
2449 emit_operand(src, dst);
2450 }
2451
2452 void Assembler::evmovdquw(XMMRegister dst, XMMRegister src, int vector_len) {
2453 assert(VM_Version::supports_evex(), "");
2454 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2455 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2456 emit_int8(0x6F);
2457 emit_int8((unsigned char)(0xC0 | encode));
2458 }
2459
2460 void Assembler::evmovdquw(XMMRegister dst, Address src, int vector_len) {
2461 assert(VM_Version::supports_evex(), "");
2462 InstructionMark im(this);
2463 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2464 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2465 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2466 emit_int8(0x6F);
2467 emit_operand(dst, src);
2468 }
2469
2470 void Assembler::evmovdquw(Address dst, XMMRegister src, int vector_len) {
2471 assert(VM_Version::supports_evex(), "");
2472 assert(src != xnoreg, "sanity");
2473 InstructionMark im(this);
2474 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2475 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2476 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2477 emit_int8(0x7F);
2478 emit_operand(src, dst);
2479 }
2480 void Assembler::evmovdqul(XMMRegister dst, XMMRegister src, int vector_len) {
2481 assert(VM_Version::supports_evex(), "");
2482 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2483 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2484 emit_int8(0x6F);
2485 emit_int8((unsigned char)(0xC0 | encode));
2486 }
2487
2488 void Assembler::evmovdqul(XMMRegister dst, Address src, int vector_len) {
2489 assert(VM_Version::supports_evex(), "");
2490 InstructionMark im(this);
2491 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false , /* uses_vl */ true);
2492 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2493 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2494 emit_int8(0x6F);
2495 emit_operand(dst, src);
2496 }
2497
2498 void Assembler::evmovdqul(Address dst, XMMRegister src, int vector_len) {
2499 assert(VM_Version::supports_evex(), "");
2500 assert(src != xnoreg, "sanity");
2501 InstructionMark im(this);
2502 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2503 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2504 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2505 emit_int8(0x7F);
2506 emit_operand(src, dst);
2507 }
2508
2509 void Assembler::evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) {
2510 assert(VM_Version::supports_evex(), "");
2511 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2512 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2513 emit_int8(0x6F);
2514 emit_int8((unsigned char)(0xC0 | encode));
2515 }
2516
2517 void Assembler::evmovdquq(XMMRegister dst, Address src, int vector_len) {
2518 assert(VM_Version::supports_evex(), "");
2519 InstructionMark im(this);
2520 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2521 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2522 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2523 emit_int8(0x6F);
2524 emit_operand(dst, src);
2525 }
2526
2527 void Assembler::evmovdquq(Address dst, XMMRegister src, int vector_len) {
2528 assert(VM_Version::supports_evex(), "");
2529 assert(src != xnoreg, "sanity");
2530 InstructionMark im(this);
2531 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2532 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2533 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2534 emit_int8(0x7F);
2535 emit_operand(src, dst);
2536 }
2537
2538 // Uses zero extension on 64bit
2539
2540 void Assembler::movl(Register dst, int32_t imm32) {
2541 int encode = prefix_and_encode(dst->encoding());
2542 emit_int8((unsigned char)(0xB8 | encode));
2543 emit_int32(imm32);
2544 }
2545
2546 void Assembler::movl(Register dst, Register src) {
2547 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2548 emit_int8((unsigned char)0x8B);
2549 emit_int8((unsigned char)(0xC0 | encode));
2550 }
2551
2552 void Assembler::movl(Register dst, Address src) {
2553 InstructionMark im(this);
2554 prefix(src, dst);
2555 emit_int8((unsigned char)0x8B);
2556 emit_operand(dst, src);
2557 }
2558
2559 void Assembler::movl(Address dst, int32_t imm32) {
2560 InstructionMark im(this);
2561 prefix(dst);
2562 emit_int8((unsigned char)0xC7);
2563 emit_operand(rax, dst, 4);
2564 emit_int32(imm32);
2565 }
2566
2567 void Assembler::movl(Address dst, Register src) {
2568 InstructionMark im(this);
2569 prefix(dst, src);
2570 emit_int8((unsigned char)0x89);
2571 emit_operand(src, dst);
2572 }
2573
2574 // New cpus require to use movsd and movss to avoid partial register stall
2575 // when loading from memory. But for old Opteron use movlpd instead of movsd.
2576 // The selection is done in MacroAssembler::movdbl() and movflt().
2577 void Assembler::movlpd(XMMRegister dst, Address src) {
2578 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2579 InstructionMark im(this);
2580 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2581 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2582 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2583 emit_int8(0x12);
2584 emit_operand(dst, src);
2585 }
2586
2587 void Assembler::movq( MMXRegister dst, Address src ) {
2588 assert( VM_Version::supports_mmx(), "" );
2589 emit_int8(0x0F);
2590 emit_int8(0x6F);
2591 emit_operand(dst, src);
2592 }
2593
2594 void Assembler::movq( Address dst, MMXRegister src ) {
2595 assert( VM_Version::supports_mmx(), "" );
2596 emit_int8(0x0F);
2597 emit_int8(0x7F);
2598 // workaround gcc (3.2.1-7a) bug
2599 // In that version of gcc with only an emit_operand(MMX, Address)
2600 // gcc will tail jump and try and reverse the parameters completely
2601 // obliterating dst in the process. By having a version available
2602 // that doesn't need to swap the args at the tail jump the bug is
2603 // avoided.
2604 emit_operand(dst, src);
2605 }
2606
2607 void Assembler::movq(XMMRegister dst, Address src) {
2608 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2609 InstructionMark im(this);
2610 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2611 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2612 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2613 emit_int8(0x7E);
2614 emit_operand(dst, src);
2615 }
2616
2617 void Assembler::movq(Address dst, XMMRegister src) {
2618 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2619 InstructionMark im(this);
2620 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2621 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2622 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2623 emit_int8((unsigned char)0xD6);
2624 emit_operand(src, dst);
2625 }
2626
2627 void Assembler::movsbl(Register dst, Address src) { // movsxb
2628 InstructionMark im(this);
2629 prefix(src, dst);
2630 emit_int8(0x0F);
2631 emit_int8((unsigned char)0xBE);
2632 emit_operand(dst, src);
2633 }
2634
2635 void Assembler::movsbl(Register dst, Register src) { // movsxb
2636 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2637 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
2638 emit_int8(0x0F);
2639 emit_int8((unsigned char)0xBE);
2640 emit_int8((unsigned char)(0xC0 | encode));
2641 }
2642
2643 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
2644 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2645 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2646 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2647 emit_int8(0x10);
2648 emit_int8((unsigned char)(0xC0 | encode));
2649 }
2650
2651 void Assembler::movsd(XMMRegister dst, Address src) {
2652 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2653 InstructionMark im(this);
2654 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2655 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2656 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2657 emit_int8(0x10);
2658 emit_operand(dst, src);
2659 }
2660
2661 void Assembler::movsd(Address dst, XMMRegister src) {
2662 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2663 InstructionMark im(this);
2664 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2665 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2666 simd_prefix(src, xnoreg, dst, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2667 emit_int8(0x11);
2668 emit_operand(src, dst);
2669 }
2670
2671 void Assembler::movss(XMMRegister dst, XMMRegister src) {
2672 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2673 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2674 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2675 emit_int8(0x10);
2676 emit_int8((unsigned char)(0xC0 | encode));
2677 }
2678
2679 void Assembler::movss(XMMRegister dst, Address src) {
2680 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2681 InstructionMark im(this);
2682 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2683 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2684 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2685 emit_int8(0x10);
2686 emit_operand(dst, src);
2687 }
2688
2689 void Assembler::movss(Address dst, XMMRegister src) {
2690 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2691 InstructionMark im(this);
2692 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2693 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2694 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2695 emit_int8(0x11);
2696 emit_operand(src, dst);
2697 }
2698
2699 void Assembler::movswl(Register dst, Address src) { // movsxw
2700 InstructionMark im(this);
2701 prefix(src, dst);
2702 emit_int8(0x0F);
2703 emit_int8((unsigned char)0xBF);
2704 emit_operand(dst, src);
2705 }
2706
2707 void Assembler::movswl(Register dst, Register src) { // movsxw
2708 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2709 emit_int8(0x0F);
2710 emit_int8((unsigned char)0xBF);
2711 emit_int8((unsigned char)(0xC0 | encode));
2712 }
2713
2714 void Assembler::movw(Address dst, int imm16) {
2715 InstructionMark im(this);
2716
2717 emit_int8(0x66); // switch to 16-bit mode
2718 prefix(dst);
2719 emit_int8((unsigned char)0xC7);
2720 emit_operand(rax, dst, 2);
2721 emit_int16(imm16);
2722 }
2723
2724 void Assembler::movw(Register dst, Address src) {
2725 InstructionMark im(this);
2726 emit_int8(0x66);
2727 prefix(src, dst);
2728 emit_int8((unsigned char)0x8B);
2729 emit_operand(dst, src);
2730 }
2731
2732 void Assembler::movw(Address dst, Register src) {
2733 InstructionMark im(this);
2734 emit_int8(0x66);
2735 prefix(dst, src);
2736 emit_int8((unsigned char)0x89);
2737 emit_operand(src, dst);
2738 }
2739
2740 void Assembler::movzbl(Register dst, Address src) { // movzxb
2741 InstructionMark im(this);
2742 prefix(src, dst);
2743 emit_int8(0x0F);
2744 emit_int8((unsigned char)0xB6);
2745 emit_operand(dst, src);
2746 }
2747
2748 void Assembler::movzbl(Register dst, Register src) { // movzxb
2749 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2750 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
2751 emit_int8(0x0F);
2752 emit_int8((unsigned char)0xB6);
2753 emit_int8(0xC0 | encode);
2754 }
2755
2756 void Assembler::movzwl(Register dst, Address src) { // movzxw
2757 InstructionMark im(this);
2758 prefix(src, dst);
2759 emit_int8(0x0F);
2760 emit_int8((unsigned char)0xB7);
2761 emit_operand(dst, src);
2762 }
2763
2764 void Assembler::movzwl(Register dst, Register src) { // movzxw
2765 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2766 emit_int8(0x0F);
2767 emit_int8((unsigned char)0xB7);
2768 emit_int8(0xC0 | encode);
2769 }
2770
2771 void Assembler::mull(Address src) {
2772 InstructionMark im(this);
2773 prefix(src);
2774 emit_int8((unsigned char)0xF7);
2775 emit_operand(rsp, src);
2776 }
2777
2778 void Assembler::mull(Register src) {
2779 int encode = prefix_and_encode(src->encoding());
2780 emit_int8((unsigned char)0xF7);
2781 emit_int8((unsigned char)(0xE0 | encode));
2782 }
2783
2784 void Assembler::mulsd(XMMRegister dst, Address src) {
2785 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2786 InstructionMark im(this);
2787 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2788 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2789 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2790 emit_int8(0x59);
2791 emit_operand(dst, src);
2792 }
2793
2794 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
2795 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2796 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2797 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2798 emit_int8(0x59);
2799 emit_int8((unsigned char)(0xC0 | encode));
2800 }
2801
2802 void Assembler::mulss(XMMRegister dst, Address src) {
2803 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2804 InstructionMark im(this);
2805 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2806 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2807 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2808 emit_int8(0x59);
2809 emit_operand(dst, src);
2810 }
2811
2812 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
2813 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2814 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2815 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2816 emit_int8(0x59);
2817 emit_int8((unsigned char)(0xC0 | encode));
2818 }
2819
2820 void Assembler::negl(Register dst) {
2821 int encode = prefix_and_encode(dst->encoding());
2822 emit_int8((unsigned char)0xF7);
2823 emit_int8((unsigned char)(0xD8 | encode));
2824 }
2825
2826 void Assembler::nop(int i) {
2827 #ifdef ASSERT
2828 assert(i > 0, " ");
2829 // The fancy nops aren't currently recognized by debuggers making it a
2830 // pain to disassemble code while debugging. If asserts are on clearly
2831 // speed is not an issue so simply use the single byte traditional nop
2832 // to do alignment.
2833
2834 for (; i > 0 ; i--) emit_int8((unsigned char)0x90);
2835 return;
2836
2837 #endif // ASSERT
2838
2839 if (UseAddressNop && VM_Version::is_intel()) {
2840 //
2841 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel
2842 // 1: 0x90
2843 // 2: 0x66 0x90
2844 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2845 // 4: 0x0F 0x1F 0x40 0x00
2846 // 5: 0x0F 0x1F 0x44 0x00 0x00
2847 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2848 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2849 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2850 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2851 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2852 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2853
2854 // The rest coding is Intel specific - don't use consecutive address nops
2855
2856 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2857 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2858 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2859 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2860
2861 while(i >= 15) {
2862 // For Intel don't generate consecutive addess nops (mix with regular nops)
2863 i -= 15;
2864 emit_int8(0x66); // size prefix
2865 emit_int8(0x66); // size prefix
2866 emit_int8(0x66); // size prefix
2867 addr_nop_8();
2868 emit_int8(0x66); // size prefix
2869 emit_int8(0x66); // size prefix
2870 emit_int8(0x66); // size prefix
2871 emit_int8((unsigned char)0x90);
2872 // nop
2873 }
2874 switch (i) {
2875 case 14:
2876 emit_int8(0x66); // size prefix
2877 case 13:
2878 emit_int8(0x66); // size prefix
2879 case 12:
2880 addr_nop_8();
2881 emit_int8(0x66); // size prefix
2882 emit_int8(0x66); // size prefix
2883 emit_int8(0x66); // size prefix
2884 emit_int8((unsigned char)0x90);
2885 // nop
2886 break;
2887 case 11:
2888 emit_int8(0x66); // size prefix
2889 case 10:
2890 emit_int8(0x66); // size prefix
2891 case 9:
2892 emit_int8(0x66); // size prefix
2893 case 8:
2894 addr_nop_8();
2895 break;
2896 case 7:
2897 addr_nop_7();
2898 break;
2899 case 6:
2900 emit_int8(0x66); // size prefix
2901 case 5:
2902 addr_nop_5();
2903 break;
2904 case 4:
2905 addr_nop_4();
2906 break;
2907 case 3:
2908 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
2909 emit_int8(0x66); // size prefix
2910 case 2:
2911 emit_int8(0x66); // size prefix
2912 case 1:
2913 emit_int8((unsigned char)0x90);
2914 // nop
2915 break;
2916 default:
2917 assert(i == 0, " ");
2918 }
2919 return;
2920 }
2921 if (UseAddressNop && VM_Version::is_amd()) {
2922 //
2923 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD.
2924 // 1: 0x90
2925 // 2: 0x66 0x90
2926 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2927 // 4: 0x0F 0x1F 0x40 0x00
2928 // 5: 0x0F 0x1F 0x44 0x00 0x00
2929 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2930 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2931 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2932 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2933 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2934 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2935
2936 // The rest coding is AMD specific - use consecutive address nops
2937
2938 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2939 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2940 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2941 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2942 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2943 // Size prefixes (0x66) are added for larger sizes
2944
2945 while(i >= 22) {
2946 i -= 11;
2947 emit_int8(0x66); // size prefix
2948 emit_int8(0x66); // size prefix
2949 emit_int8(0x66); // size prefix
2950 addr_nop_8();
2951 }
2952 // Generate first nop for size between 21-12
2953 switch (i) {
2954 case 21:
2955 i -= 1;
2956 emit_int8(0x66); // size prefix
2957 case 20:
2958 case 19:
2959 i -= 1;
2960 emit_int8(0x66); // size prefix
2961 case 18:
2962 case 17:
2963 i -= 1;
2964 emit_int8(0x66); // size prefix
2965 case 16:
2966 case 15:
2967 i -= 8;
2968 addr_nop_8();
2969 break;
2970 case 14:
2971 case 13:
2972 i -= 7;
2973 addr_nop_7();
2974 break;
2975 case 12:
2976 i -= 6;
2977 emit_int8(0x66); // size prefix
2978 addr_nop_5();
2979 break;
2980 default:
2981 assert(i < 12, " ");
2982 }
2983
2984 // Generate second nop for size between 11-1
2985 switch (i) {
2986 case 11:
2987 emit_int8(0x66); // size prefix
2988 case 10:
2989 emit_int8(0x66); // size prefix
2990 case 9:
2991 emit_int8(0x66); // size prefix
2992 case 8:
2993 addr_nop_8();
2994 break;
2995 case 7:
2996 addr_nop_7();
2997 break;
2998 case 6:
2999 emit_int8(0x66); // size prefix
3000 case 5:
3001 addr_nop_5();
3002 break;
3003 case 4:
3004 addr_nop_4();
3005 break;
3006 case 3:
3007 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
3008 emit_int8(0x66); // size prefix
3009 case 2:
3010 emit_int8(0x66); // size prefix
3011 case 1:
3012 emit_int8((unsigned char)0x90);
3013 // nop
3014 break;
3015 default:
3016 assert(i == 0, " ");
3017 }
3018 return;
3019 }
3020
3021 // Using nops with size prefixes "0x66 0x90".
3022 // From AMD Optimization Guide:
3023 // 1: 0x90
3024 // 2: 0x66 0x90
3025 // 3: 0x66 0x66 0x90
3026 // 4: 0x66 0x66 0x66 0x90
3027 // 5: 0x66 0x66 0x90 0x66 0x90
3028 // 6: 0x66 0x66 0x90 0x66 0x66 0x90
3029 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90
3030 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90
3031 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
3032 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
3033 //
3034 while(i > 12) {
3035 i -= 4;
3036 emit_int8(0x66); // size prefix
3037 emit_int8(0x66);
3038 emit_int8(0x66);
3039 emit_int8((unsigned char)0x90);
3040 // nop
3041 }
3042 // 1 - 12 nops
3043 if(i > 8) {
3044 if(i > 9) {
3045 i -= 1;
3046 emit_int8(0x66);
3047 }
3048 i -= 3;
3049 emit_int8(0x66);
3050 emit_int8(0x66);
3051 emit_int8((unsigned char)0x90);
3052 }
3053 // 1 - 8 nops
3054 if(i > 4) {
3055 if(i > 6) {
3056 i -= 1;
3057 emit_int8(0x66);
3058 }
3059 i -= 3;
3060 emit_int8(0x66);
3061 emit_int8(0x66);
3062 emit_int8((unsigned char)0x90);
3063 }
3064 switch (i) {
3065 case 4:
3066 emit_int8(0x66);
3067 case 3:
3068 emit_int8(0x66);
3069 case 2:
3070 emit_int8(0x66);
3071 case 1:
3072 emit_int8((unsigned char)0x90);
3073 break;
3074 default:
3075 assert(i == 0, " ");
3076 }
3077 }
3078
3079 void Assembler::notl(Register dst) {
3080 int encode = prefix_and_encode(dst->encoding());
3081 emit_int8((unsigned char)0xF7);
3082 emit_int8((unsigned char)(0xD0 | encode));
3083 }
3084
3085 void Assembler::orl(Address dst, int32_t imm32) {
3086 InstructionMark im(this);
3087 prefix(dst);
3088 emit_arith_operand(0x81, rcx, dst, imm32);
3089 }
3090
3091 void Assembler::orl(Register dst, int32_t imm32) {
3092 prefix(dst);
3093 emit_arith(0x81, 0xC8, dst, imm32);
3094 }
3095
3096 void Assembler::orl(Register dst, Address src) {
3097 InstructionMark im(this);
3098 prefix(src, dst);
3099 emit_int8(0x0B);
3100 emit_operand(dst, src);
3101 }
3102
3103 void Assembler::orl(Register dst, Register src) {
3104 (void) prefix_and_encode(dst->encoding(), src->encoding());
3105 emit_arith(0x0B, 0xC0, dst, src);
3106 }
3107
3108 void Assembler::orl(Address dst, Register src) {
3109 InstructionMark im(this);
3110 prefix(dst, src);
3111 emit_int8(0x09);
3112 emit_operand(src, dst);
3113 }
3114
3115 void Assembler::packuswb(XMMRegister dst, Address src) {
3116 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3117 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3118 InstructionMark im(this);
3119 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3120 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3121 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3122 emit_int8(0x67);
3123 emit_operand(dst, src);
3124 }
3125
3126 void Assembler::packuswb(XMMRegister dst, XMMRegister src) {
3127 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3128 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3129 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3130 emit_int8(0x67);
3131 emit_int8((unsigned char)(0xC0 | encode));
3132 }
3133
3134 void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3135 assert(UseAVX > 0, "some form of AVX must be enabled");
3136 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3137 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3138 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3139 emit_int8(0x67);
3140 emit_int8((unsigned char)(0xC0 | encode));
3141 }
3142
3143 void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len) {
3144 assert(VM_Version::supports_avx2(), "");
3145 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3146 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3147 emit_int8(0x00);
3148 emit_int8(0xC0 | encode);
3149 emit_int8(imm8);
3150 }
3151
3152 void Assembler::pause() {
3153 emit_int8((unsigned char)0xF3);
3154 emit_int8((unsigned char)0x90);
3155 }
3156
3157 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3158 assert(VM_Version::supports_sse4_2(), "");
3159 InstructionMark im(this);
3160 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3161 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3162 emit_int8(0x61);
3163 emit_operand(dst, src);
3164 emit_int8(imm8);
3165 }
3166
3167 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3168 assert(VM_Version::supports_sse4_2(), "");
3169 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3170 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3171 emit_int8(0x61);
3172 emit_int8((unsigned char)(0xC0 | encode));
3173 emit_int8(imm8);
3174 }
3175
3176 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3177 void Assembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
3178 assert(VM_Version::supports_sse2(), "");
3179 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3180 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3181 emit_int8(0x74);
3182 emit_int8((unsigned char)(0xC0 | encode));
3183 }
3184
3185 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3186 void Assembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3187 assert(VM_Version::supports_avx(), "");
3188 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3189 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3190 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3191 emit_int8(0x74);
3192 emit_int8((unsigned char)(0xC0 | encode));
3193 }
3194
3195 // In this context, kdst is written the mask used to process the equal components
3196 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3197 assert(VM_Version::supports_avx512bw(), "");
3198 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3199 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3200 int encode = vex_prefix_and_encode(kdst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3201 emit_int8(0x74);
3202 emit_int8((unsigned char)(0xC0 | encode));
3203 }
3204
3205 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3206 assert(VM_Version::supports_avx512bw(), "");
3207 InstructionMark im(this);
3208 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3209 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3210 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3211 int dst_enc = kdst->encoding();
3212 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3213 emit_int8(0x74);
3214 emit_operand(as_Register(dst_enc), src);
3215 }
3216
3217 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3218 void Assembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3219 assert(VM_Version::supports_sse2(), "");
3220 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3221 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3222 emit_int8(0x75);
3223 emit_int8((unsigned char)(0xC0 | encode));
3224 }
3225
3226 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3227 void Assembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3228 assert(VM_Version::supports_avx(), "");
3229 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3230 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3231 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3232 emit_int8(0x75);
3233 emit_int8((unsigned char)(0xC0 | encode));
3234 }
3235
3236 // In this context, kdst is written the mask used to process the equal components
3237 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3238 assert(VM_Version::supports_avx512bw(), "");
3239 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3240 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3241 int encode = vex_prefix_and_encode(kdst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3242 emit_int8(0x75);
3243 emit_int8((unsigned char)(0xC0 | encode));
3244 }
3245
3246 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3247 assert(VM_Version::supports_avx512bw(), "");
3248 InstructionMark im(this);
3249 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3250 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3251 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3252 int dst_enc = kdst->encoding();
3253 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3254 emit_int8(0x75);
3255 emit_operand(as_Register(dst_enc), src);
3256 }
3257
3258 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3259 void Assembler::pcmpeqd(XMMRegister dst, XMMRegister src) {
3260 assert(VM_Version::supports_sse2(), "");
3261 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3262 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3263 emit_int8(0x76);
3264 emit_int8((unsigned char)(0xC0 | encode));
3265 }
3266
3267 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3268 void Assembler::vpcmpeqd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3269 assert(VM_Version::supports_avx(), "");
3270 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3271 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3272 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3273 emit_int8(0x76);
3274 emit_int8((unsigned char)(0xC0 | encode));
3275 }
3276
3277 // In this context, kdst is written the mask used to process the equal components
3278 void Assembler::evpcmpeqd(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3279 assert(VM_Version::supports_evex(), "");
3280 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3281 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3282 int encode = vex_prefix_and_encode(kdst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3283 emit_int8(0x76);
3284 emit_int8((unsigned char)(0xC0 | encode));
3285 }
3286
3287 void Assembler::evpcmpeqd(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3288 assert(VM_Version::supports_evex(), "");
3289 InstructionMark im(this);
3290 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3291 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3292 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3293 int dst_enc = kdst->encoding();
3294 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3295 emit_int8(0x76);
3296 emit_operand(as_Register(dst_enc), src);
3297 }
3298
3299 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3300 void Assembler::pcmpeqq(XMMRegister dst, XMMRegister src) {
3301 assert(VM_Version::supports_sse4_1(), "");
3302 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3303 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3304 emit_int8(0x29);
3305 emit_int8((unsigned char)(0xC0 | encode));
3306 }
3307
3308 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3309 void Assembler::vpcmpeqq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3310 assert(VM_Version::supports_avx(), "");
3311 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3312 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3313 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3314 emit_int8(0x29);
3315 emit_int8((unsigned char)(0xC0 | encode));
3316 }
3317
3318 // In this context, kdst is written the mask used to process the equal components
3319 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3320 assert(VM_Version::supports_evex(), "");
3321 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3322 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3323 int encode = vex_prefix_and_encode(kdst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3324 emit_int8(0x29);
3325 emit_int8((unsigned char)(0xC0 | encode));
3326 }
3327
3328 // In this context, kdst is written the mask used to process the equal components
3329 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3330 assert(VM_Version::supports_evex(), "");
3331 InstructionMark im(this);
3332 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3333 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
3334 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3335 int dst_enc = kdst->encoding();
3336 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3337 emit_int8(0x29);
3338 emit_operand(as_Register(dst_enc), src);
3339 }
3340
3341 void Assembler::pmovmskb(Register dst, XMMRegister src) {
3342 assert(VM_Version::supports_sse2(), "");
3343 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3344 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3345 emit_int8((unsigned char)0xD7);
3346 emit_int8((unsigned char)(0xC0 | encode));
3347 }
3348
3349 void Assembler::vpmovmskb(Register dst, XMMRegister src) {
3350 assert(VM_Version::supports_avx2(), "");
3351 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3352 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3353 emit_int8((unsigned char)0xD7);
3354 emit_int8((unsigned char)(0xC0 | encode));
3355 }
3356
3357 void Assembler::pextrd(Register dst, XMMRegister src, int imm8) {
3358 assert(VM_Version::supports_sse4_1(), "");
3359 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3360 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3361 emit_int8(0x16);
3362 emit_int8((unsigned char)(0xC0 | encode));
3363 emit_int8(imm8);
3364 }
3365
3366 void Assembler::pextrd(Address dst, XMMRegister src, int imm8) {
3367 assert(VM_Version::supports_sse4_1(), "");
3368 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3369 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3370 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3371 emit_int8(0x16);
3372 emit_operand(src, dst);
3373 emit_int8(imm8);
3374 }
3375
3376 void Assembler::pextrq(Register dst, XMMRegister src, int imm8) {
3377 assert(VM_Version::supports_sse4_1(), "");
3378 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3379 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3380 emit_int8(0x16);
3381 emit_int8((unsigned char)(0xC0 | encode));
3382 emit_int8(imm8);
3383 }
3384
3385 void Assembler::pextrq(Address dst, XMMRegister src, int imm8) {
3386 assert(VM_Version::supports_sse4_1(), "");
3387 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3388 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3389 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3390 emit_int8(0x16);
3391 emit_operand(src, dst);
3392 emit_int8(imm8);
3393 }
3394
3395 void Assembler::pextrw(Register dst, XMMRegister src, int imm8) {
3396 assert(VM_Version::supports_sse2(), "");
3397 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3398 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3399 emit_int8((unsigned char)0xC5);
3400 emit_int8((unsigned char)(0xC0 | encode));
3401 emit_int8(imm8);
3402 }
3403
3404 void Assembler::pextrw(Address dst, XMMRegister src, int imm8) {
3405 assert(VM_Version::supports_sse4_1(), "");
3406 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3407 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
3408 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3409 emit_int8((unsigned char)0x15);
3410 emit_operand(src, dst);
3411 emit_int8(imm8);
3412 }
3413
3414 void Assembler::pextrb(Address dst, XMMRegister src, int imm8) {
3415 assert(VM_Version::supports_sse4_1(), "");
3416 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3417 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
3418 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3419 emit_int8(0x14);
3420 emit_operand(src, dst);
3421 emit_int8(imm8);
3422 }
3423
3424 void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) {
3425 assert(VM_Version::supports_sse4_1(), "");
3426 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3427 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3428 emit_int8(0x22);
3429 emit_int8((unsigned char)(0xC0 | encode));
3430 emit_int8(imm8);
3431 }
3432
3433 void Assembler::pinsrd(XMMRegister dst, Address src, int imm8) {
3434 assert(VM_Version::supports_sse4_1(), "");
3435 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3436 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3437 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3438 emit_int8(0x22);
3439 emit_operand(dst,src);
3440 emit_int8(imm8);
3441 }
3442
3443 void Assembler::pinsrq(XMMRegister dst, Register src, int imm8) {
3444 assert(VM_Version::supports_sse4_1(), "");
3445 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3446 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3447 emit_int8(0x22);
3448 emit_int8((unsigned char)(0xC0 | encode));
3449 emit_int8(imm8);
3450 }
3451
3452 void Assembler::pinsrq(XMMRegister dst, Address src, int imm8) {
3453 assert(VM_Version::supports_sse4_1(), "");
3454 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3455 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3456 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3457 emit_int8(0x22);
3458 emit_operand(dst, src);
3459 emit_int8(imm8);
3460 }
3461
3462 void Assembler::pinsrw(XMMRegister dst, Register src, int imm8) {
3463 assert(VM_Version::supports_sse2(), "");
3464 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3465 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3466 emit_int8((unsigned char)0xC4);
3467 emit_int8((unsigned char)(0xC0 | encode));
3468 emit_int8(imm8);
3469 }
3470
3471 void Assembler::pinsrw(XMMRegister dst, Address src, int imm8) {
3472 assert(VM_Version::supports_sse2(), "");
3473 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3474 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
3475 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3476 emit_int8((unsigned char)0xC4);
3477 emit_operand(dst, src);
3478 emit_int8(imm8);
3479 }
3480
3481 void Assembler::pinsrb(XMMRegister dst, Address src, int imm8) {
3482 assert(VM_Version::supports_sse4_1(), "");
3483 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3484 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
3485 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3486 emit_int8(0x20);
3487 emit_operand(dst, src);
3488 emit_int8(imm8);
3489 }
3490
3491 void Assembler::pmovzxbw(XMMRegister dst, Address src) {
3492 assert(VM_Version::supports_sse4_1(), "");
3493 InstructionMark im(this);
3494 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3495 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3496 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3497 emit_int8(0x30);
3498 emit_operand(dst, src);
3499 }
3500
3501 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3502 assert(VM_Version::supports_sse4_1(), "");
3503 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3504 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3505 emit_int8(0x30);
3506 emit_int8((unsigned char)(0xC0 | encode));
3507 }
3508
3509 void Assembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
3510 assert(VM_Version::supports_avx(), "");
3511 InstructionMark im(this);
3512 assert(dst != xnoreg, "sanity");
3513 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3514 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3515 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3516 emit_int8(0x30);
3517 emit_operand(dst, src);
3518 }
3519
3520 // generic
3521 void Assembler::pop(Register dst) {
3522 int encode = prefix_and_encode(dst->encoding());
3523 emit_int8(0x58 | encode);
3524 }
3525
3526 void Assembler::popcntl(Register dst, Address src) {
3527 assert(VM_Version::supports_popcnt(), "must support");
3528 InstructionMark im(this);
3529 emit_int8((unsigned char)0xF3);
3530 prefix(src, dst);
3531 emit_int8(0x0F);
3532 emit_int8((unsigned char)0xB8);
3533 emit_operand(dst, src);
3534 }
3535
3536 void Assembler::popcntl(Register dst, Register src) {
3537 assert(VM_Version::supports_popcnt(), "must support");
3538 emit_int8((unsigned char)0xF3);
3539 int encode = prefix_and_encode(dst->encoding(), src->encoding());
3540 emit_int8(0x0F);
3541 emit_int8((unsigned char)0xB8);
3542 emit_int8((unsigned char)(0xC0 | encode));
3543 }
3544
3545 void Assembler::popf() {
3546 emit_int8((unsigned char)0x9D);
3547 }
3548
3549 #ifndef _LP64 // no 32bit push/pop on amd64
3550 void Assembler::popl(Address dst) {
3551 // NOTE: this will adjust stack by 8byte on 64bits
3552 InstructionMark im(this);
3553 prefix(dst);
3554 emit_int8((unsigned char)0x8F);
3555 emit_operand(rax, dst);
3556 }
3557 #endif
3558
3559 void Assembler::prefetch_prefix(Address src) {
3560 prefix(src);
3561 emit_int8(0x0F);
3562 }
3563
3564 void Assembler::prefetchnta(Address src) {
3565 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3566 InstructionMark im(this);
3567 prefetch_prefix(src);
3568 emit_int8(0x18);
3569 emit_operand(rax, src); // 0, src
3570 }
3571
3572 void Assembler::prefetchr(Address src) {
3573 assert(VM_Version::supports_3dnow_prefetch(), "must support");
3574 InstructionMark im(this);
3575 prefetch_prefix(src);
3576 emit_int8(0x0D);
3577 emit_operand(rax, src); // 0, src
3578 }
3579
3580 void Assembler::prefetcht0(Address src) {
3581 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3582 InstructionMark im(this);
3583 prefetch_prefix(src);
3584 emit_int8(0x18);
3585 emit_operand(rcx, src); // 1, src
3586 }
3587
3588 void Assembler::prefetcht1(Address src) {
3589 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3590 InstructionMark im(this);
3591 prefetch_prefix(src);
3592 emit_int8(0x18);
3593 emit_operand(rdx, src); // 2, src
3594 }
3595
3596 void Assembler::prefetcht2(Address src) {
3597 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3598 InstructionMark im(this);
3599 prefetch_prefix(src);
3600 emit_int8(0x18);
3601 emit_operand(rbx, src); // 3, src
3602 }
3603
3604 void Assembler::prefetchw(Address src) {
3605 assert(VM_Version::supports_3dnow_prefetch(), "must support");
3606 InstructionMark im(this);
3607 prefetch_prefix(src);
3608 emit_int8(0x0D);
3609 emit_operand(rcx, src); // 1, src
3610 }
3611
3612 void Assembler::prefix(Prefix p) {
3613 emit_int8(p);
3614 }
3615
3616 void Assembler::pshufb(XMMRegister dst, XMMRegister src) {
3617 assert(VM_Version::supports_ssse3(), "");
3618 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3619 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3620 emit_int8(0x00);
3621 emit_int8((unsigned char)(0xC0 | encode));
3622 }
3623
3624 void Assembler::pshufb(XMMRegister dst, Address src) {
3625 assert(VM_Version::supports_ssse3(), "");
3626 InstructionMark im(this);
3627 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3628 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3629 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3630 emit_int8(0x00);
3631 emit_operand(dst, src);
3632 }
3633
3634 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
3635 assert(isByte(mode), "invalid value");
3636 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3637 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_128bit;
3638 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3639 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3640 emit_int8(0x70);
3641 emit_int8((unsigned char)(0xC0 | encode));
3642 emit_int8(mode & 0xFF);
3643 }
3644
3645 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
3646 assert(isByte(mode), "invalid value");
3647 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3648 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3649 InstructionMark im(this);
3650 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3651 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3652 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3653 emit_int8(0x70);
3654 emit_operand(dst, src);
3655 emit_int8(mode & 0xFF);
3656 }
3657
3658 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
3659 assert(isByte(mode), "invalid value");
3660 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3661 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3662 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3663 emit_int8(0x70);
3664 emit_int8((unsigned char)(0xC0 | encode));
3665 emit_int8(mode & 0xFF);
3666 }
3667
3668 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
3669 assert(isByte(mode), "invalid value");
3670 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3671 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3672 InstructionMark im(this);
3673 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3674 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3675 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3676 emit_int8(0x70);
3677 emit_operand(dst, src);
3678 emit_int8(mode & 0xFF);
3679 }
3680
3681 void Assembler::psrldq(XMMRegister dst, int shift) {
3682 // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
3683 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3684 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3685 // XMM3 is for /3 encoding: 66 0F 73 /3 ib
3686 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3687 emit_int8(0x73);
3688 emit_int8((unsigned char)(0xC0 | encode));
3689 emit_int8(shift);
3690 }
3691
3692 void Assembler::pslldq(XMMRegister dst, int shift) {
3693 // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
3694 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3695 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3696 // XMM7 is for /7 encoding: 66 0F 73 /7 ib
3697 int encode = simd_prefix_and_encode(xmm7, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3698 emit_int8(0x73);
3699 emit_int8((unsigned char)(0xC0 | encode));
3700 emit_int8(shift);
3701 }
3702
3703 void Assembler::ptest(XMMRegister dst, Address src) {
3704 assert(VM_Version::supports_sse4_1(), "");
3705 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3706 InstructionMark im(this);
3707 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3708 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3709 emit_int8(0x17);
3710 emit_operand(dst, src);
3711 }
3712
3713 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
3714 assert(VM_Version::supports_sse4_1(), "");
3715 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3716 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3717 emit_int8(0x17);
3718 emit_int8((unsigned char)(0xC0 | encode));
3719 }
3720
3721 void Assembler::vptest(XMMRegister dst, Address src) {
3722 assert(VM_Version::supports_avx(), "");
3723 InstructionMark im(this);
3724 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3725 assert(dst != xnoreg, "sanity");
3726 // swap src<->dst for encoding
3727 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3728 emit_int8(0x17);
3729 emit_operand(dst, src);
3730 }
3731
3732 void Assembler::vptest(XMMRegister dst, XMMRegister src) {
3733 assert(VM_Version::supports_avx(), "");
3734 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3735 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3736 emit_int8(0x17);
3737 emit_int8((unsigned char)(0xC0 | encode));
3738 }
3739
3740 void Assembler::punpcklbw(XMMRegister dst, Address src) {
3741 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3742 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3743 InstructionMark im(this);
3744 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ false, /* uses_vl */ true);
3745 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3746 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3747 emit_int8(0x60);
3748 emit_operand(dst, src);
3749 }
3750
3751 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
3752 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3753 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ false, /* uses_vl */ true);
3754 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3755 emit_int8(0x60);
3756 emit_int8((unsigned char)(0xC0 | encode));
3757 }
3758
3759 void Assembler::punpckldq(XMMRegister dst, Address src) {
3760 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3761 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3762 InstructionMark im(this);
3763 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3764 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3765 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3766 emit_int8(0x62);
3767 emit_operand(dst, src);
3768 }
3769
3770 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) {
3771 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3772 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3773 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3774 emit_int8(0x62);
3775 emit_int8((unsigned char)(0xC0 | encode));
3776 }
3777
3778 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) {
3779 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3780 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3781 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3782 emit_int8(0x6C);
3783 emit_int8((unsigned char)(0xC0 | encode));
3784 }
3785
3786 void Assembler::push(int32_t imm32) {
3787 // in 64bits we push 64bits onto the stack but only
3788 // take a 32bit immediate
3789 emit_int8(0x68);
3790 emit_int32(imm32);
3791 }
3792
3793 void Assembler::push(Register src) {
3794 int encode = prefix_and_encode(src->encoding());
3795
3796 emit_int8(0x50 | encode);
3797 }
3798
3799 void Assembler::pushf() {
3800 emit_int8((unsigned char)0x9C);
3801 }
3802
3803 #ifndef _LP64 // no 32bit push/pop on amd64
3804 void Assembler::pushl(Address src) {
3805 // Note this will push 64bit on 64bit
3806 InstructionMark im(this);
3807 prefix(src);
3808 emit_int8((unsigned char)0xFF);
3809 emit_operand(rsi, src);
3810 }
3811 #endif
3812
3813 void Assembler::rcll(Register dst, int imm8) {
3814 assert(isShiftCount(imm8), "illegal shift count");
3815 int encode = prefix_and_encode(dst->encoding());
3816 if (imm8 == 1) {
3817 emit_int8((unsigned char)0xD1);
3818 emit_int8((unsigned char)(0xD0 | encode));
3819 } else {
3820 emit_int8((unsigned char)0xC1);
3821 emit_int8((unsigned char)0xD0 | encode);
3822 emit_int8(imm8);
3823 }
3824 }
3825
3826 void Assembler::rcpps(XMMRegister dst, XMMRegister src) {
3827 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3828 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3829 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
3830 emit_int8(0x53);
3831 emit_int8((unsigned char)(0xC0 | encode));
3832 }
3833
3834 void Assembler::rcpss(XMMRegister dst, XMMRegister src) {
3835 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3836 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3837 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3838 emit_int8(0x53);
3839 emit_int8((unsigned char)(0xC0 | encode));
3840 }
3841
3842 void Assembler::rdtsc() {
3843 emit_int8((unsigned char)0x0F);
3844 emit_int8((unsigned char)0x31);
3845 }
3846
3847 // copies data from [esi] to [edi] using rcx pointer sized words
3848 // generic
3849 void Assembler::rep_mov() {
3850 emit_int8((unsigned char)0xF3);
3851 // MOVSQ
3852 LP64_ONLY(prefix(REX_W));
3853 emit_int8((unsigned char)0xA5);
3854 }
3855
3856 // sets rcx bytes with rax, value at [edi]
3857 void Assembler::rep_stosb() {
3858 emit_int8((unsigned char)0xF3); // REP
3859 LP64_ONLY(prefix(REX_W));
3860 emit_int8((unsigned char)0xAA); // STOSB
3861 }
3862
3863 // sets rcx pointer sized words with rax, value at [edi]
3864 // generic
3865 void Assembler::rep_stos() {
3866 emit_int8((unsigned char)0xF3); // REP
3867 LP64_ONLY(prefix(REX_W)); // LP64:STOSQ, LP32:STOSD
3868 emit_int8((unsigned char)0xAB);
3869 }
3870
3871 // scans rcx pointer sized words at [edi] for occurance of rax,
3872 // generic
3873 void Assembler::repne_scan() { // repne_scan
3874 emit_int8((unsigned char)0xF2);
3875 // SCASQ
3876 LP64_ONLY(prefix(REX_W));
3877 emit_int8((unsigned char)0xAF);
3878 }
3879
3880 #ifdef _LP64
3881 // scans rcx 4 byte words at [edi] for occurance of rax,
3882 // generic
3883 void Assembler::repne_scanl() { // repne_scan
3884 emit_int8((unsigned char)0xF2);
3885 // SCASL
3886 emit_int8((unsigned char)0xAF);
3887 }
3888 #endif
3889
3890 void Assembler::ret(int imm16) {
3891 if (imm16 == 0) {
3892 emit_int8((unsigned char)0xC3);
3893 } else {
3894 emit_int8((unsigned char)0xC2);
3895 emit_int16(imm16);
3896 }
3897 }
3898
3899 void Assembler::sahf() {
3900 #ifdef _LP64
3901 // Not supported in 64bit mode
3902 ShouldNotReachHere();
3903 #endif
3904 emit_int8((unsigned char)0x9E);
3905 }
3906
3907 void Assembler::sarl(Register dst, int imm8) {
3908 int encode = prefix_and_encode(dst->encoding());
3909 assert(isShiftCount(imm8), "illegal shift count");
3910 if (imm8 == 1) {
3911 emit_int8((unsigned char)0xD1);
3912 emit_int8((unsigned char)(0xF8 | encode));
3913 } else {
3914 emit_int8((unsigned char)0xC1);
3915 emit_int8((unsigned char)(0xF8 | encode));
3916 emit_int8(imm8);
3917 }
3918 }
3919
3920 void Assembler::sarl(Register dst) {
3921 int encode = prefix_and_encode(dst->encoding());
3922 emit_int8((unsigned char)0xD3);
3923 emit_int8((unsigned char)(0xF8 | encode));
3924 }
3925
3926 void Assembler::sbbl(Address dst, int32_t imm32) {
3927 InstructionMark im(this);
3928 prefix(dst);
3929 emit_arith_operand(0x81, rbx, dst, imm32);
3930 }
3931
3932 void Assembler::sbbl(Register dst, int32_t imm32) {
3933 prefix(dst);
3934 emit_arith(0x81, 0xD8, dst, imm32);
3935 }
3936
3937
3938 void Assembler::sbbl(Register dst, Address src) {
3939 InstructionMark im(this);
3940 prefix(src, dst);
3941 emit_int8(0x1B);
3942 emit_operand(dst, src);
3943 }
3944
3945 void Assembler::sbbl(Register dst, Register src) {
3946 (void) prefix_and_encode(dst->encoding(), src->encoding());
3947 emit_arith(0x1B, 0xC0, dst, src);
3948 }
3949
3950 void Assembler::setb(Condition cc, Register dst) {
3951 assert(0 <= cc && cc < 16, "illegal cc");
3952 int encode = prefix_and_encode(dst->encoding(), true);
3953 emit_int8(0x0F);
3954 emit_int8((unsigned char)0x90 | cc);
3955 emit_int8((unsigned char)(0xC0 | encode));
3956 }
3957
3958 void Assembler::palignr(XMMRegister dst, XMMRegister src, int imm8) {
3959 assert(VM_Version::supports_ssse3(), "");
3960 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ false);
3961 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3962 emit_int8((unsigned char)0x0F);
3963 emit_int8((unsigned char)(0xC0 | encode));
3964 emit_int8(imm8);
3965 }
3966
3967 void Assembler::pblendw(XMMRegister dst, XMMRegister src, int imm8) {
3968 assert(VM_Version::supports_sse4_1(), "");
3969 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3970 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3971 emit_int8((unsigned char)0x0E);
3972 emit_int8((unsigned char)(0xC0 | encode));
3973 emit_int8(imm8);
3974 }
3975
3976 void Assembler::sha1rnds4(XMMRegister dst, XMMRegister src, int imm8) {
3977 assert(VM_Version::supports_sha(), "");
3978 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3979 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_3A, &attributes);
3980 emit_int8((unsigned char)0xCC);
3981 emit_int8((unsigned char)(0xC0 | encode));
3982 emit_int8((unsigned char)imm8);
3983 }
3984
3985 void Assembler::sha1nexte(XMMRegister dst, XMMRegister src) {
3986 assert(VM_Version::supports_sha(), "");
3987 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3988 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
3989 emit_int8((unsigned char)0xC8);
3990 emit_int8((unsigned char)(0xC0 | encode));
3991 }
3992
3993 void Assembler::sha1msg1(XMMRegister dst, XMMRegister src) {
3994 assert(VM_Version::supports_sha(), "");
3995 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3996 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
3997 emit_int8((unsigned char)0xC9);
3998 emit_int8((unsigned char)(0xC0 | encode));
3999 }
4000
4001 void Assembler::sha1msg2(XMMRegister dst, XMMRegister src) {
4002 assert(VM_Version::supports_sha(), "");
4003 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4004 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4005 emit_int8((unsigned char)0xCA);
4006 emit_int8((unsigned char)(0xC0 | encode));
4007 }
4008
4009 // xmm0 is implicit additional source to this instruction.
4010 void Assembler::sha256rnds2(XMMRegister dst, XMMRegister src) {
4011 assert(VM_Version::supports_sha(), "");
4012 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4013 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4014 emit_int8((unsigned char)0xCB);
4015 emit_int8((unsigned char)(0xC0 | encode));
4016 }
4017
4018 void Assembler::sha256msg1(XMMRegister dst, XMMRegister src) {
4019 assert(VM_Version::supports_sha(), "");
4020 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4021 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4022 emit_int8((unsigned char)0xCC);
4023 emit_int8((unsigned char)(0xC0 | encode));
4024 }
4025
4026 void Assembler::sha256msg2(XMMRegister dst, XMMRegister src) {
4027 assert(VM_Version::supports_sha(), "");
4028 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4029 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4030 emit_int8((unsigned char)0xCD);
4031 emit_int8((unsigned char)(0xC0 | encode));
4032 }
4033
4034
4035 void Assembler::shll(Register dst, int imm8) {
4036 assert(isShiftCount(imm8), "illegal shift count");
4037 int encode = prefix_and_encode(dst->encoding());
4038 if (imm8 == 1 ) {
4039 emit_int8((unsigned char)0xD1);
4040 emit_int8((unsigned char)(0xE0 | encode));
4041 } else {
4042 emit_int8((unsigned char)0xC1);
4043 emit_int8((unsigned char)(0xE0 | encode));
4044 emit_int8(imm8);
4045 }
4046 }
4047
4048 void Assembler::shll(Register dst) {
4049 int encode = prefix_and_encode(dst->encoding());
4050 emit_int8((unsigned char)0xD3);
4051 emit_int8((unsigned char)(0xE0 | encode));
4052 }
4053
4054 void Assembler::shrl(Register dst, int imm8) {
4055 assert(isShiftCount(imm8), "illegal shift count");
4056 int encode = prefix_and_encode(dst->encoding());
4057 emit_int8((unsigned char)0xC1);
4058 emit_int8((unsigned char)(0xE8 | encode));
4059 emit_int8(imm8);
4060 }
4061
4062 void Assembler::shrl(Register dst) {
4063 int encode = prefix_and_encode(dst->encoding());
4064 emit_int8((unsigned char)0xD3);
4065 emit_int8((unsigned char)(0xE8 | encode));
4066 }
4067
4068 // copies a single word from [esi] to [edi]
4069 void Assembler::smovl() {
4070 emit_int8((unsigned char)0xA5);
4071 }
4072
4073 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
4074 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4075 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4076 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4077 emit_int8(0x51);
4078 emit_int8((unsigned char)(0xC0 | encode));
4079 }
4080
4081 void Assembler::sqrtsd(XMMRegister dst, Address src) {
4082 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4083 InstructionMark im(this);
4084 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4085 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4086 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4087 emit_int8(0x51);
4088 emit_operand(dst, src);
4089 }
4090
4091 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
4092 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4093 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4094 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4095 emit_int8(0x51);
4096 emit_int8((unsigned char)(0xC0 | encode));
4097 }
4098
4099 void Assembler::std() {
4100 emit_int8((unsigned char)0xFD);
4101 }
4102
4103 void Assembler::sqrtss(XMMRegister dst, Address src) {
4104 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4105 InstructionMark im(this);
4106 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4107 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4108 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4109 emit_int8(0x51);
4110 emit_operand(dst, src);
4111 }
4112
4113 void Assembler::stmxcsr( Address dst) {
4114 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4115 InstructionMark im(this);
4116 prefix(dst);
4117 emit_int8(0x0F);
4118 emit_int8((unsigned char)0xAE);
4119 emit_operand(as_Register(3), dst);
4120 }
4121
4122 void Assembler::subl(Address dst, int32_t imm32) {
4123 InstructionMark im(this);
4124 prefix(dst);
4125 emit_arith_operand(0x81, rbp, dst, imm32);
4126 }
4127
4128 void Assembler::subl(Address dst, Register src) {
4129 InstructionMark im(this);
4130 prefix(dst, src);
4131 emit_int8(0x29);
4132 emit_operand(src, dst);
4133 }
4134
4135 void Assembler::subl(Register dst, int32_t imm32) {
4136 prefix(dst);
4137 emit_arith(0x81, 0xE8, dst, imm32);
4138 }
4139
4140 // Force generation of a 4 byte immediate value even if it fits into 8bit
4141 void Assembler::subl_imm32(Register dst, int32_t imm32) {
4142 prefix(dst);
4143 emit_arith_imm32(0x81, 0xE8, dst, imm32);
4144 }
4145
4146 void Assembler::subl(Register dst, Address src) {
4147 InstructionMark im(this);
4148 prefix(src, dst);
4149 emit_int8(0x2B);
4150 emit_operand(dst, src);
4151 }
4152
4153 void Assembler::subl(Register dst, Register src) {
4154 (void) prefix_and_encode(dst->encoding(), src->encoding());
4155 emit_arith(0x2B, 0xC0, dst, src);
4156 }
4157
4158 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
4159 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4160 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4161 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4162 emit_int8(0x5C);
4163 emit_int8((unsigned char)(0xC0 | encode));
4164 }
4165
4166 void Assembler::subsd(XMMRegister dst, Address src) {
4167 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4168 InstructionMark im(this);
4169 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4170 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4171 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4172 emit_int8(0x5C);
4173 emit_operand(dst, src);
4174 }
4175
4176 void Assembler::subss(XMMRegister dst, XMMRegister src) {
4177 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4178 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false , /* uses_vl */ false);
4179 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4180 emit_int8(0x5C);
4181 emit_int8((unsigned char)(0xC0 | encode));
4182 }
4183
4184 void Assembler::subss(XMMRegister dst, Address src) {
4185 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4186 InstructionMark im(this);
4187 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4188 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4189 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4190 emit_int8(0x5C);
4191 emit_operand(dst, src);
4192 }
4193
4194 void Assembler::testb(Register dst, int imm8) {
4195 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
4196 (void) prefix_and_encode(dst->encoding(), true);
4197 emit_arith_b(0xF6, 0xC0, dst, imm8);
4198 }
4199
4200 void Assembler::testb(Address dst, int imm8) {
4201 InstructionMark im(this);
4202 prefix(dst);
4203 emit_int8((unsigned char)0xF6);
4204 emit_operand(rax, dst, 1);
4205 emit_int8(imm8);
4206 }
4207
4208 void Assembler::testl(Register dst, int32_t imm32) {
4209 // not using emit_arith because test
4210 // doesn't support sign-extension of
4211 // 8bit operands
4212 int encode = dst->encoding();
4213 if (encode == 0) {
4214 emit_int8((unsigned char)0xA9);
4215 } else {
4216 encode = prefix_and_encode(encode);
4217 emit_int8((unsigned char)0xF7);
4218 emit_int8((unsigned char)(0xC0 | encode));
4219 }
4220 emit_int32(imm32);
4221 }
4222
4223 void Assembler::testl(Register dst, Register src) {
4224 (void) prefix_and_encode(dst->encoding(), src->encoding());
4225 emit_arith(0x85, 0xC0, dst, src);
4226 }
4227
4228 void Assembler::testl(Register dst, Address src) {
4229 InstructionMark im(this);
4230 prefix(src, dst);
4231 emit_int8((unsigned char)0x85);
4232 emit_operand(dst, src);
4233 }
4234
4235 void Assembler::tzcntl(Register dst, Register src) {
4236 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
4237 emit_int8((unsigned char)0xF3);
4238 int encode = prefix_and_encode(dst->encoding(), src->encoding());
4239 emit_int8(0x0F);
4240 emit_int8((unsigned char)0xBC);
4241 emit_int8((unsigned char)0xC0 | encode);
4242 }
4243
4244 void Assembler::tzcntq(Register dst, Register src) {
4245 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
4246 emit_int8((unsigned char)0xF3);
4247 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4248 emit_int8(0x0F);
4249 emit_int8((unsigned char)0xBC);
4250 emit_int8((unsigned char)(0xC0 | encode));
4251 }
4252
4253 void Assembler::ucomisd(XMMRegister dst, Address src) {
4254 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4255 InstructionMark im(this);
4256 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4257 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4258 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4259 emit_int8(0x2E);
4260 emit_operand(dst, src);
4261 }
4262
4263 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
4264 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4265 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4266 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4267 emit_int8(0x2E);
4268 emit_int8((unsigned char)(0xC0 | encode));
4269 }
4270
4271 void Assembler::ucomiss(XMMRegister dst, Address src) {
4272 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4273 InstructionMark im(this);
4274 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4275 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4276 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4277 emit_int8(0x2E);
4278 emit_operand(dst, src);
4279 }
4280
4281 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
4282 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4283 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4284 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4285 emit_int8(0x2E);
4286 emit_int8((unsigned char)(0xC0 | encode));
4287 }
4288
4289 void Assembler::xabort(int8_t imm8) {
4290 emit_int8((unsigned char)0xC6);
4291 emit_int8((unsigned char)0xF8);
4292 emit_int8((unsigned char)(imm8 & 0xFF));
4293 }
4294
4295 void Assembler::xaddl(Address dst, Register src) {
4296 InstructionMark im(this);
4297 prefix(dst, src);
4298 emit_int8(0x0F);
4299 emit_int8((unsigned char)0xC1);
4300 emit_operand(src, dst);
4301 }
4302
4303 void Assembler::xbegin(Label& abort, relocInfo::relocType rtype) {
4304 InstructionMark im(this);
4305 relocate(rtype);
4306 if (abort.is_bound()) {
4307 address entry = target(abort);
4308 assert(entry != NULL, "abort entry NULL");
4309 intptr_t offset = entry - pc();
4310 emit_int8((unsigned char)0xC7);
4311 emit_int8((unsigned char)0xF8);
4312 emit_int32(offset - 6); // 2 opcode + 4 address
4313 } else {
4314 abort.add_patch_at(code(), locator());
4315 emit_int8((unsigned char)0xC7);
4316 emit_int8((unsigned char)0xF8);
4317 emit_int32(0);
4318 }
4319 }
4320
4321 void Assembler::xchgl(Register dst, Address src) { // xchg
4322 InstructionMark im(this);
4323 prefix(src, dst);
4324 emit_int8((unsigned char)0x87);
4325 emit_operand(dst, src);
4326 }
4327
4328 void Assembler::xchgl(Register dst, Register src) {
4329 int encode = prefix_and_encode(dst->encoding(), src->encoding());
4330 emit_int8((unsigned char)0x87);
4331 emit_int8((unsigned char)(0xC0 | encode));
4332 }
4333
4334 void Assembler::xend() {
4335 emit_int8((unsigned char)0x0F);
4336 emit_int8((unsigned char)0x01);
4337 emit_int8((unsigned char)0xD5);
4338 }
4339
4340 void Assembler::xgetbv() {
4341 emit_int8(0x0F);
4342 emit_int8(0x01);
4343 emit_int8((unsigned char)0xD0);
4344 }
4345
4346 void Assembler::xorl(Register dst, int32_t imm32) {
4347 prefix(dst);
4348 emit_arith(0x81, 0xF0, dst, imm32);
4349 }
4350
4351 void Assembler::xorl(Register dst, Address src) {
4352 InstructionMark im(this);
4353 prefix(src, dst);
4354 emit_int8(0x33);
4355 emit_operand(dst, src);
4356 }
4357
4358 void Assembler::xorl(Register dst, Register src) {
4359 (void) prefix_and_encode(dst->encoding(), src->encoding());
4360 emit_arith(0x33, 0xC0, dst, src);
4361 }
4362
4363 void Assembler::xorb(Register dst, Address src) {
4364 InstructionMark im(this);
4365 prefix(src, dst);
4366 emit_int8(0x32);
4367 emit_operand(dst, src);
4368 }
4369
4370 // AVX 3-operands scalar float-point arithmetic instructions
4371
4372 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) {
4373 assert(VM_Version::supports_avx(), "");
4374 InstructionMark im(this);
4375 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4376 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4377 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4378 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4379 emit_int8(0x58);
4380 emit_operand(dst, src);
4381 }
4382
4383 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4384 assert(VM_Version::supports_avx(), "");
4385 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4386 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4387 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4388 emit_int8(0x58);
4389 emit_int8((unsigned char)(0xC0 | encode));
4390 }
4391
4392 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) {
4393 assert(VM_Version::supports_avx(), "");
4394 InstructionMark im(this);
4395 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4396 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4397 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4398 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4399 emit_int8(0x58);
4400 emit_operand(dst, src);
4401 }
4402
4403 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4404 assert(VM_Version::supports_avx(), "");
4405 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4406 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4407 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4408 emit_int8(0x58);
4409 emit_int8((unsigned char)(0xC0 | encode));
4410 }
4411
4412 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) {
4413 assert(VM_Version::supports_avx(), "");
4414 InstructionMark im(this);
4415 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4416 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4417 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4418 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4419 emit_int8(0x5E);
4420 emit_operand(dst, src);
4421 }
4422
4423 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4424 assert(VM_Version::supports_avx(), "");
4425 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4426 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4427 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4428 emit_int8(0x5E);
4429 emit_int8((unsigned char)(0xC0 | encode));
4430 }
4431
4432 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) {
4433 assert(VM_Version::supports_avx(), "");
4434 InstructionMark im(this);
4435 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4436 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4437 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4438 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4439 emit_int8(0x5E);
4440 emit_operand(dst, src);
4441 }
4442
4443 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4444 assert(VM_Version::supports_avx(), "");
4445 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4446 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4447 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4448 emit_int8(0x5E);
4449 emit_int8((unsigned char)(0xC0 | encode));
4450 }
4451
4452 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) {
4453 assert(VM_Version::supports_avx(), "");
4454 InstructionMark im(this);
4455 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4456 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4457 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4458 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4459 emit_int8(0x59);
4460 emit_operand(dst, src);
4461 }
4462
4463 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4464 assert(VM_Version::supports_avx(), "");
4465 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4466 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4467 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4468 emit_int8(0x59);
4469 emit_int8((unsigned char)(0xC0 | encode));
4470 }
4471
4472 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) {
4473 assert(VM_Version::supports_avx(), "");
4474 InstructionMark im(this);
4475 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4476 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4477 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4478 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4479 emit_int8(0x59);
4480 emit_operand(dst, src);
4481 }
4482
4483 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4484 assert(VM_Version::supports_avx(), "");
4485 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4486 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4487 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4488 emit_int8(0x59);
4489 emit_int8((unsigned char)(0xC0 | encode));
4490 }
4491
4492 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) {
4493 assert(VM_Version::supports_avx(), "");
4494 InstructionMark im(this);
4495 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4496 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4497 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4498 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4499 emit_int8(0x5C);
4500 emit_operand(dst, src);
4501 }
4502
4503 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4504 assert(VM_Version::supports_avx(), "");
4505 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4506 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4507 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4508 emit_int8(0x5C);
4509 emit_int8((unsigned char)(0xC0 | encode));
4510 }
4511
4512 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) {
4513 assert(VM_Version::supports_avx(), "");
4514 InstructionMark im(this);
4515 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4516 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4517 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4518 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4519 emit_int8(0x5C);
4520 emit_operand(dst, src);
4521 }
4522
4523 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4524 assert(VM_Version::supports_avx(), "");
4525 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4526 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4527 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4528 emit_int8(0x5C);
4529 emit_int8((unsigned char)(0xC0 | encode));
4530 }
4531
4532 //====================VECTOR ARITHMETIC=====================================
4533
4534 // Float-point vector arithmetic
4535
4536 void Assembler::addpd(XMMRegister dst, XMMRegister src) {
4537 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4538 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4539 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4540 emit_int8(0x58);
4541 emit_int8((unsigned char)(0xC0 | encode));
4542 }
4543
4544 void Assembler::addpd(XMMRegister dst, Address src) {
4545 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4546 InstructionMark im(this);
4547 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4548 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4549 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4550 emit_int8(0x58);
4551 emit_operand(dst, src);
4552 }
4553
4554
4555 void Assembler::addps(XMMRegister dst, XMMRegister src) {
4556 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4557 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4558 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4559 emit_int8(0x58);
4560 emit_int8((unsigned char)(0xC0 | encode));
4561 }
4562
4563 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4564 assert(VM_Version::supports_avx(), "");
4565 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4566 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4567 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4568 emit_int8(0x58);
4569 emit_int8((unsigned char)(0xC0 | encode));
4570 }
4571
4572 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4573 assert(VM_Version::supports_avx(), "");
4574 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4575 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4576 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4577 emit_int8(0x58);
4578 emit_int8((unsigned char)(0xC0 | encode));
4579 }
4580
4581 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4582 assert(VM_Version::supports_avx(), "");
4583 InstructionMark im(this);
4584 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4585 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4586 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4587 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4588 emit_int8(0x58);
4589 emit_operand(dst, src);
4590 }
4591
4592 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4593 assert(VM_Version::supports_avx(), "");
4594 InstructionMark im(this);
4595 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4596 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4597 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4598 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4599 emit_int8(0x58);
4600 emit_operand(dst, src);
4601 }
4602
4603 void Assembler::subpd(XMMRegister dst, XMMRegister src) {
4604 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4605 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4606 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4607 emit_int8(0x5C);
4608 emit_int8((unsigned char)(0xC0 | encode));
4609 }
4610
4611 void Assembler::subps(XMMRegister dst, XMMRegister src) {
4612 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4613 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4614 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4615 emit_int8(0x5C);
4616 emit_int8((unsigned char)(0xC0 | encode));
4617 }
4618
4619 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4620 assert(VM_Version::supports_avx(), "");
4621 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4622 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4623 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4624 emit_int8(0x5C);
4625 emit_int8((unsigned char)(0xC0 | encode));
4626 }
4627
4628 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4629 assert(VM_Version::supports_avx(), "");
4630 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4631 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4632 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4633 emit_int8(0x5C);
4634 emit_int8((unsigned char)(0xC0 | encode));
4635 }
4636
4637 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4638 assert(VM_Version::supports_avx(), "");
4639 InstructionMark im(this);
4640 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4641 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4642 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4643 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4644 emit_int8(0x5C);
4645 emit_operand(dst, src);
4646 }
4647
4648 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4649 assert(VM_Version::supports_avx(), "");
4650 InstructionMark im(this);
4651 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4652 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4653 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4654 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4655 emit_int8(0x5C);
4656 emit_operand(dst, src);
4657 }
4658
4659 void Assembler::mulpd(XMMRegister dst, XMMRegister src) {
4660 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4661 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4662 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4663 emit_int8(0x59);
4664 emit_int8((unsigned char)(0xC0 | encode));
4665 }
4666
4667 void Assembler::mulpd(XMMRegister dst, Address src) {
4668 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4669 InstructionMark im(this);
4670 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4671 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4672 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4673 emit_int8(0x59);
4674 emit_operand(dst, src);
4675 }
4676
4677 void Assembler::mulps(XMMRegister dst, XMMRegister src) {
4678 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4679 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4680 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4681 emit_int8(0x59);
4682 emit_int8((unsigned char)(0xC0 | encode));
4683 }
4684
4685 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4686 assert(VM_Version::supports_avx(), "");
4687 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4688 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4689 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4690 emit_int8(0x59);
4691 emit_int8((unsigned char)(0xC0 | encode));
4692 }
4693
4694 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4695 assert(VM_Version::supports_avx(), "");
4696 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4697 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4698 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4699 emit_int8(0x59);
4700 emit_int8((unsigned char)(0xC0 | encode));
4701 }
4702
4703 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4704 assert(VM_Version::supports_avx(), "");
4705 InstructionMark im(this);
4706 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4707 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4708 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4709 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4710 emit_int8(0x59);
4711 emit_operand(dst, src);
4712 }
4713
4714 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4715 assert(VM_Version::supports_avx(), "");
4716 InstructionMark im(this);
4717 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4718 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4719 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4720 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4721 emit_int8(0x59);
4722 emit_operand(dst, src);
4723 }
4724
4725 void Assembler::divpd(XMMRegister dst, XMMRegister src) {
4726 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4727 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4728 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4729 emit_int8(0x5E);
4730 emit_int8((unsigned char)(0xC0 | encode));
4731 }
4732
4733 void Assembler::divps(XMMRegister dst, XMMRegister src) {
4734 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4735 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4736 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4737 emit_int8(0x5E);
4738 emit_int8((unsigned char)(0xC0 | encode));
4739 }
4740
4741 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4742 assert(VM_Version::supports_avx(), "");
4743 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4744 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4745 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4746 emit_int8(0x5E);
4747 emit_int8((unsigned char)(0xC0 | encode));
4748 }
4749
4750 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4751 assert(VM_Version::supports_avx(), "");
4752 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4753 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4754 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4755 emit_int8(0x5E);
4756 emit_int8((unsigned char)(0xC0 | encode));
4757 }
4758
4759 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4760 assert(VM_Version::supports_avx(), "");
4761 InstructionMark im(this);
4762 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4763 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4764 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4765 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4766 emit_int8(0x5E);
4767 emit_operand(dst, src);
4768 }
4769
4770 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4771 assert(VM_Version::supports_avx(), "");
4772 InstructionMark im(this);
4773 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4774 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4775 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4776 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4777 emit_int8(0x5E);
4778 emit_operand(dst, src);
4779 }
4780
4781 void Assembler::vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len) {
4782 assert(VM_Version::supports_avx(), "");
4783 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4784 int nds_enc = 0;
4785 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4786 emit_int8(0x51);
4787 emit_int8((unsigned char)(0xC0 | encode));
4788 }
4789
4790 void Assembler::vsqrtpd(XMMRegister dst, Address src, int vector_len) {
4791 assert(VM_Version::supports_avx(), "");
4792 InstructionMark im(this);
4793 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4794 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4795 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4796 emit_int8(0x51);
4797 emit_operand(dst, src);
4798 }
4799
4800 void Assembler::andpd(XMMRegister dst, XMMRegister src) {
4801 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4802 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4803 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4804 emit_int8(0x54);
4805 emit_int8((unsigned char)(0xC0 | encode));
4806 }
4807
4808 void Assembler::andps(XMMRegister dst, XMMRegister src) {
4809 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4810 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4811 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4812 emit_int8(0x54);
4813 emit_int8((unsigned char)(0xC0 | encode));
4814 }
4815
4816 void Assembler::andps(XMMRegister dst, Address src) {
4817 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4818 InstructionMark im(this);
4819 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4820 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4821 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4822 emit_int8(0x54);
4823 emit_operand(dst, src);
4824 }
4825
4826 void Assembler::andpd(XMMRegister dst, Address src) {
4827 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4828 InstructionMark im(this);
4829 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4830 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4831 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4832 emit_int8(0x54);
4833 emit_operand(dst, src);
4834 }
4835
4836 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4837 assert(VM_Version::supports_avx(), "");
4838 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4839 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4840 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4841 emit_int8(0x54);
4842 emit_int8((unsigned char)(0xC0 | encode));
4843 }
4844
4845 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4846 assert(VM_Version::supports_avx(), "");
4847 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4848 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4849 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4850 emit_int8(0x54);
4851 emit_int8((unsigned char)(0xC0 | encode));
4852 }
4853
4854 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4855 assert(VM_Version::supports_avx(), "");
4856 InstructionMark im(this);
4857 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4858 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4859 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4860 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4861 emit_int8(0x54);
4862 emit_operand(dst, src);
4863 }
4864
4865 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4866 assert(VM_Version::supports_avx(), "");
4867 InstructionMark im(this);
4868 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4869 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4870 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4871 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4872 emit_int8(0x54);
4873 emit_operand(dst, src);
4874 }
4875
4876 void Assembler::unpckhpd(XMMRegister dst, XMMRegister src) {
4877 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4878 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4879 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4880 emit_int8(0x15);
4881 emit_int8((unsigned char)(0xC0 | encode));
4882 }
4883
4884 void Assembler::unpcklpd(XMMRegister dst, XMMRegister src) {
4885 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4886 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4887 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4888 emit_int8(0x14);
4889 emit_int8((unsigned char)(0xC0 | encode));
4890 }
4891
4892 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
4893 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4894 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4895 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4896 emit_int8(0x57);
4897 emit_int8((unsigned char)(0xC0 | encode));
4898 }
4899
4900 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
4901 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4902 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4903 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4904 emit_int8(0x57);
4905 emit_int8((unsigned char)(0xC0 | encode));
4906 }
4907
4908 void Assembler::xorpd(XMMRegister dst, Address src) {
4909 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4910 InstructionMark im(this);
4911 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4912 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4913 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4914 emit_int8(0x57);
4915 emit_operand(dst, src);
4916 }
4917
4918 void Assembler::xorps(XMMRegister dst, Address src) {
4919 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4920 InstructionMark im(this);
4921 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4922 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4923 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4924 emit_int8(0x57);
4925 emit_operand(dst, src);
4926 }
4927
4928 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4929 assert(VM_Version::supports_avx(), "");
4930 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4931 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4932 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4933 emit_int8(0x57);
4934 emit_int8((unsigned char)(0xC0 | encode));
4935 }
4936
4937 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4938 assert(VM_Version::supports_avx(), "");
4939 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4940 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4941 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4942 emit_int8(0x57);
4943 emit_int8((unsigned char)(0xC0 | encode));
4944 }
4945
4946 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4947 assert(VM_Version::supports_avx(), "");
4948 InstructionMark im(this);
4949 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4950 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4951 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4952 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4953 emit_int8(0x57);
4954 emit_operand(dst, src);
4955 }
4956
4957 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4958 assert(VM_Version::supports_avx(), "");
4959 InstructionMark im(this);
4960 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4961 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4962 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4963 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4964 emit_int8(0x57);
4965 emit_operand(dst, src);
4966 }
4967
4968 // Integer vector arithmetic
4969 void Assembler::vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4970 assert(VM_Version::supports_avx() && (vector_len == 0) ||
4971 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
4972 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4973 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4974 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4975 emit_int8(0x01);
4976 emit_int8((unsigned char)(0xC0 | encode));
4977 }
4978
4979 void Assembler::vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4980 assert(VM_Version::supports_avx() && (vector_len == 0) ||
4981 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
4982 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4983 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4984 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4985 emit_int8(0x02);
4986 emit_int8((unsigned char)(0xC0 | encode));
4987 }
4988
4989 void Assembler::paddb(XMMRegister dst, XMMRegister src) {
4990 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4991 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4992 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4993 emit_int8((unsigned char)0xFC);
4994 emit_int8((unsigned char)(0xC0 | encode));
4995 }
4996
4997 void Assembler::paddw(XMMRegister dst, XMMRegister src) {
4998 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4999 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5000 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5001 emit_int8((unsigned char)0xFD);
5002 emit_int8((unsigned char)(0xC0 | encode));
5003 }
5004
5005 void Assembler::paddd(XMMRegister dst, XMMRegister src) {
5006 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5007 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5008 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5009 emit_int8((unsigned char)0xFE);
5010 emit_int8((unsigned char)(0xC0 | encode));
5011 }
5012
5013 void Assembler::paddd(XMMRegister dst, Address src) {
5014 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5015 InstructionMark im(this);
5016 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5017 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5018 emit_int8((unsigned char)0xFE);
5019 emit_operand(dst, src);
5020 }
5021
5022 void Assembler::paddq(XMMRegister dst, XMMRegister src) {
5023 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5024 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5025 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5026 emit_int8((unsigned char)0xD4);
5027 emit_int8((unsigned char)(0xC0 | encode));
5028 }
5029
5030 void Assembler::phaddw(XMMRegister dst, XMMRegister src) {
5031 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
5032 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5033 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5034 emit_int8(0x01);
5035 emit_int8((unsigned char)(0xC0 | encode));
5036 }
5037
5038 void Assembler::phaddd(XMMRegister dst, XMMRegister src) {
5039 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
5040 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5041 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5042 emit_int8(0x02);
5043 emit_int8((unsigned char)(0xC0 | encode));
5044 }
5045
5046 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5047 assert(UseAVX > 0, "requires some form of AVX");
5048 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5049 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5050 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5051 emit_int8((unsigned char)0xFC);
5052 emit_int8((unsigned char)(0xC0 | encode));
5053 }
5054
5055 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5056 assert(UseAVX > 0, "requires some form of AVX");
5057 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5058 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5059 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5060 emit_int8((unsigned char)0xFD);
5061 emit_int8((unsigned char)(0xC0 | encode));
5062 }
5063
5064 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5065 assert(UseAVX > 0, "requires some form of AVX");
5066 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5067 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5068 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5069 emit_int8((unsigned char)0xFE);
5070 emit_int8((unsigned char)(0xC0 | encode));
5071 }
5072
5073 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5074 assert(UseAVX > 0, "requires some form of AVX");
5075 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5076 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5077 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5078 emit_int8((unsigned char)0xD4);
5079 emit_int8((unsigned char)(0xC0 | encode));
5080 }
5081
5082 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5083 assert(UseAVX > 0, "requires some form of AVX");
5084 InstructionMark im(this);
5085 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5086 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5087 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5088 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5089 emit_int8((unsigned char)0xFC);
5090 emit_operand(dst, src);
5091 }
5092
5093 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5094 assert(UseAVX > 0, "requires some form of AVX");
5095 InstructionMark im(this);
5096 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5097 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5098 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5099 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5100 emit_int8((unsigned char)0xFD);
5101 emit_operand(dst, src);
5102 }
5103
5104 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5105 assert(UseAVX > 0, "requires some form of AVX");
5106 InstructionMark im(this);
5107 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5108 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5109 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5110 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5111 emit_int8((unsigned char)0xFE);
5112 emit_operand(dst, src);
5113 }
5114
5115 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5116 assert(UseAVX > 0, "requires some form of AVX");
5117 InstructionMark im(this);
5118 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5119 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5120 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5121 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5122 emit_int8((unsigned char)0xD4);
5123 emit_operand(dst, src);
5124 }
5125
5126 void Assembler::psubb(XMMRegister dst, XMMRegister src) {
5127 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5128 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5129 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5130 emit_int8((unsigned char)0xF8);
5131 emit_int8((unsigned char)(0xC0 | encode));
5132 }
5133
5134 void Assembler::psubw(XMMRegister dst, XMMRegister src) {
5135 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5136 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5137 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5138 emit_int8((unsigned char)0xF9);
5139 emit_int8((unsigned char)(0xC0 | encode));
5140 }
5141
5142 void Assembler::psubd(XMMRegister dst, XMMRegister src) {
5143 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5144 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5145 emit_int8((unsigned char)0xFA);
5146 emit_int8((unsigned char)(0xC0 | encode));
5147 }
5148
5149 void Assembler::psubq(XMMRegister dst, XMMRegister src) {
5150 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5151 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5152 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5153 emit_int8((unsigned char)0xFB);
5154 emit_int8((unsigned char)(0xC0 | encode));
5155 }
5156
5157 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5158 assert(UseAVX > 0, "requires some form of AVX");
5159 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5160 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5161 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5162 emit_int8((unsigned char)0xF8);
5163 emit_int8((unsigned char)(0xC0 | encode));
5164 }
5165
5166 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5167 assert(UseAVX > 0, "requires some form of AVX");
5168 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5169 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5170 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5171 emit_int8((unsigned char)0xF9);
5172 emit_int8((unsigned char)(0xC0 | encode));
5173 }
5174
5175 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5176 assert(UseAVX > 0, "requires some form of AVX");
5177 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5178 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5179 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5180 emit_int8((unsigned char)0xFA);
5181 emit_int8((unsigned char)(0xC0 | encode));
5182 }
5183
5184 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5185 assert(UseAVX > 0, "requires some form of AVX");
5186 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5187 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5188 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5189 emit_int8((unsigned char)0xFB);
5190 emit_int8((unsigned char)(0xC0 | encode));
5191 }
5192
5193 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5194 assert(UseAVX > 0, "requires some form of AVX");
5195 InstructionMark im(this);
5196 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5197 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5198 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5199 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5200 emit_int8((unsigned char)0xF8);
5201 emit_operand(dst, src);
5202 }
5203
5204 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5205 assert(UseAVX > 0, "requires some form of AVX");
5206 InstructionMark im(this);
5207 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5208 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5209 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5210 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5211 emit_int8((unsigned char)0xF9);
5212 emit_operand(dst, src);
5213 }
5214
5215 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5216 assert(UseAVX > 0, "requires some form of AVX");
5217 InstructionMark im(this);
5218 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5219 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5220 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5221 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5222 emit_int8((unsigned char)0xFA);
5223 emit_operand(dst, src);
5224 }
5225
5226 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5227 assert(UseAVX > 0, "requires some form of AVX");
5228 InstructionMark im(this);
5229 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5230 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5231 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5232 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5233 emit_int8((unsigned char)0xFB);
5234 emit_operand(dst, src);
5235 }
5236
5237 void Assembler::pmullw(XMMRegister dst, XMMRegister src) {
5238 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5239 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5240 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5241 emit_int8((unsigned char)0xD5);
5242 emit_int8((unsigned char)(0xC0 | encode));
5243 }
5244
5245 void Assembler::pmulld(XMMRegister dst, XMMRegister src) {
5246 assert(VM_Version::supports_sse4_1(), "");
5247 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5248 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5249 emit_int8(0x40);
5250 emit_int8((unsigned char)(0xC0 | encode));
5251 }
5252
5253 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5254 assert(UseAVX > 0, "requires some form of AVX");
5255 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5256 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5257 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5258 emit_int8((unsigned char)0xD5);
5259 emit_int8((unsigned char)(0xC0 | encode));
5260 }
5261
5262 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5263 assert(UseAVX > 0, "requires some form of AVX");
5264 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5265 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5266 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5267 emit_int8(0x40);
5268 emit_int8((unsigned char)(0xC0 | encode));
5269 }
5270
5271 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5272 assert(UseAVX > 2, "requires some form of AVX");
5273 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5274 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5275 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5276 emit_int8(0x40);
5277 emit_int8((unsigned char)(0xC0 | encode));
5278 }
5279
5280 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5281 assert(UseAVX > 0, "requires some form of AVX");
5282 InstructionMark im(this);
5283 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5284 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5285 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5286 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5287 emit_int8((unsigned char)0xD5);
5288 emit_operand(dst, src);
5289 }
5290
5291 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5292 assert(UseAVX > 0, "requires some form of AVX");
5293 InstructionMark im(this);
5294 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5295 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5296 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5297 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5298 emit_int8(0x40);
5299 emit_operand(dst, src);
5300 }
5301
5302 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5303 assert(UseAVX > 0, "requires some form of AVX");
5304 InstructionMark im(this);
5305 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5306 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5307 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5308 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5309 emit_int8(0x40);
5310 emit_operand(dst, src);
5311 }
5312
5313 // Shift packed integers left by specified number of bits.
5314 void Assembler::psllw(XMMRegister dst, int shift) {
5315 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5316 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5317 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
5318 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5319 emit_int8(0x71);
5320 emit_int8((unsigned char)(0xC0 | encode));
5321 emit_int8(shift & 0xFF);
5322 }
5323
5324 void Assembler::pslld(XMMRegister dst, int shift) {
5325 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5326 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5327 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
5328 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5329 emit_int8(0x72);
5330 emit_int8((unsigned char)(0xC0 | encode));
5331 emit_int8(shift & 0xFF);
5332 }
5333
5334 void Assembler::psllq(XMMRegister dst, int shift) {
5335 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5336 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5337 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
5338 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5339 emit_int8(0x73);
5340 emit_int8((unsigned char)(0xC0 | encode));
5341 emit_int8(shift & 0xFF);
5342 }
5343
5344 void Assembler::psllw(XMMRegister dst, XMMRegister shift) {
5345 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5346 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5347 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5348 emit_int8((unsigned char)0xF1);
5349 emit_int8((unsigned char)(0xC0 | encode));
5350 }
5351
5352 void Assembler::pslld(XMMRegister dst, XMMRegister shift) {
5353 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5354 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5355 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5356 emit_int8((unsigned char)0xF2);
5357 emit_int8((unsigned char)(0xC0 | encode));
5358 }
5359
5360 void Assembler::psllq(XMMRegister dst, XMMRegister shift) {
5361 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5362 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5363 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5364 emit_int8((unsigned char)0xF3);
5365 emit_int8((unsigned char)(0xC0 | encode));
5366 }
5367
5368 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5369 assert(UseAVX > 0, "requires some form of AVX");
5370 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5371 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
5372 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5373 emit_int8(0x71);
5374 emit_int8((unsigned char)(0xC0 | encode));
5375 emit_int8(shift & 0xFF);
5376 }
5377
5378 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5379 assert(UseAVX > 0, "requires some form of AVX");
5380 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5381 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5382 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
5383 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5384 emit_int8(0x72);
5385 emit_int8((unsigned char)(0xC0 | encode));
5386 emit_int8(shift & 0xFF);
5387 }
5388
5389 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5390 assert(UseAVX > 0, "requires some form of AVX");
5391 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5392 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
5393 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5394 emit_int8(0x73);
5395 emit_int8((unsigned char)(0xC0 | encode));
5396 emit_int8(shift & 0xFF);
5397 }
5398
5399 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5400 assert(UseAVX > 0, "requires some form of AVX");
5401 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5402 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5403 emit_int8((unsigned char)0xF1);
5404 emit_int8((unsigned char)(0xC0 | encode));
5405 }
5406
5407 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5408 assert(UseAVX > 0, "requires some form of AVX");
5409 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5410 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5411 emit_int8((unsigned char)0xF2);
5412 emit_int8((unsigned char)(0xC0 | encode));
5413 }
5414
5415 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5416 assert(UseAVX > 0, "requires some form of AVX");
5417 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5418 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5419 emit_int8((unsigned char)0xF3);
5420 emit_int8((unsigned char)(0xC0 | encode));
5421 }
5422
5423 // Shift packed integers logically right by specified number of bits.
5424 void Assembler::psrlw(XMMRegister dst, int shift) {
5425 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5426 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5427 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
5428 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5429 emit_int8(0x71);
5430 emit_int8((unsigned char)(0xC0 | encode));
5431 emit_int8(shift & 0xFF);
5432 }
5433
5434 void Assembler::psrld(XMMRegister dst, int shift) {
5435 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5436 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5437 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
5438 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5439 emit_int8(0x72);
5440 emit_int8((unsigned char)(0xC0 | encode));
5441 emit_int8(shift & 0xFF);
5442 }
5443
5444 void Assembler::psrlq(XMMRegister dst, int shift) {
5445 // Do not confuse it with psrldq SSE2 instruction which
5446 // shifts 128 bit value in xmm register by number of bytes.
5447 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5448 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5449 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
5450 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5451 emit_int8(0x73);
5452 emit_int8((unsigned char)(0xC0 | encode));
5453 emit_int8(shift & 0xFF);
5454 }
5455
5456 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) {
5457 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5458 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5459 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5460 emit_int8((unsigned char)0xD1);
5461 emit_int8((unsigned char)(0xC0 | encode));
5462 }
5463
5464 void Assembler::psrld(XMMRegister dst, XMMRegister shift) {
5465 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5466 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5467 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5468 emit_int8((unsigned char)0xD2);
5469 emit_int8((unsigned char)(0xC0 | encode));
5470 }
5471
5472 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) {
5473 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5474 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5475 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5476 emit_int8((unsigned char)0xD3);
5477 emit_int8((unsigned char)(0xC0 | encode));
5478 }
5479
5480 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5481 assert(UseAVX > 0, "requires some form of AVX");
5482 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5483 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
5484 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5485 emit_int8(0x71);
5486 emit_int8((unsigned char)(0xC0 | encode));
5487 emit_int8(shift & 0xFF);
5488 }
5489
5490 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5491 assert(UseAVX > 0, "requires some form of AVX");
5492 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5493 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
5494 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5495 emit_int8(0x72);
5496 emit_int8((unsigned char)(0xC0 | encode));
5497 emit_int8(shift & 0xFF);
5498 }
5499
5500 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5501 assert(UseAVX > 0, "requires some form of AVX");
5502 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5503 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
5504 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5505 emit_int8(0x73);
5506 emit_int8((unsigned char)(0xC0 | encode));
5507 emit_int8(shift & 0xFF);
5508 }
5509
5510 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5511 assert(UseAVX > 0, "requires some form of AVX");
5512 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5513 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5514 emit_int8((unsigned char)0xD1);
5515 emit_int8((unsigned char)(0xC0 | encode));
5516 }
5517
5518 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5519 assert(UseAVX > 0, "requires some form of AVX");
5520 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5521 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5522 emit_int8((unsigned char)0xD2);
5523 emit_int8((unsigned char)(0xC0 | encode));
5524 }
5525
5526 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5527 assert(UseAVX > 0, "requires some form of AVX");
5528 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5529 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5530 emit_int8((unsigned char)0xD3);
5531 emit_int8((unsigned char)(0xC0 | encode));
5532 }
5533
5534 // Shift packed integers arithmetically right by specified number of bits.
5535 void Assembler::psraw(XMMRegister dst, int shift) {
5536 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5537 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5538 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
5539 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5540 emit_int8(0x71);
5541 emit_int8((unsigned char)(0xC0 | encode));
5542 emit_int8(shift & 0xFF);
5543 }
5544
5545 void Assembler::psrad(XMMRegister dst, int shift) {
5546 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5547 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5548 // XMM4 is for /4 encoding: 66 0F 72 /4 ib
5549 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5550 emit_int8(0x72);
5551 emit_int8((unsigned char)(0xC0 | encode));
5552 emit_int8(shift & 0xFF);
5553 }
5554
5555 void Assembler::psraw(XMMRegister dst, XMMRegister shift) {
5556 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5557 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5558 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5559 emit_int8((unsigned char)0xE1);
5560 emit_int8((unsigned char)(0xC0 | encode));
5561 }
5562
5563 void Assembler::psrad(XMMRegister dst, XMMRegister shift) {
5564 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5565 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5566 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5567 emit_int8((unsigned char)0xE2);
5568 emit_int8((unsigned char)(0xC0 | encode));
5569 }
5570
5571 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5572 assert(UseAVX > 0, "requires some form of AVX");
5573 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5574 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
5575 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5576 emit_int8(0x71);
5577 emit_int8((unsigned char)(0xC0 | encode));
5578 emit_int8(shift & 0xFF);
5579 }
5580
5581 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5582 assert(UseAVX > 0, "requires some form of AVX");
5583 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5584 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
5585 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5586 emit_int8(0x72);
5587 emit_int8((unsigned char)(0xC0 | encode));
5588 emit_int8(shift & 0xFF);
5589 }
5590
5591 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5592 assert(UseAVX > 0, "requires some form of AVX");
5593 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5594 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5595 emit_int8((unsigned char)0xE1);
5596 emit_int8((unsigned char)(0xC0 | encode));
5597 }
5598
5599 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5600 assert(UseAVX > 0, "requires some form of AVX");
5601 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5602 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5603 emit_int8((unsigned char)0xE2);
5604 emit_int8((unsigned char)(0xC0 | encode));
5605 }
5606
5607
5608 // logical operations packed integers
5609 void Assembler::pand(XMMRegister dst, XMMRegister src) {
5610 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5611 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5612 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5613 emit_int8((unsigned char)0xDB);
5614 emit_int8((unsigned char)(0xC0 | encode));
5615 }
5616
5617 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5618 assert(UseAVX > 0, "requires some form of AVX");
5619 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5620 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5621 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5622 emit_int8((unsigned char)0xDB);
5623 emit_int8((unsigned char)(0xC0 | encode));
5624 }
5625
5626 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5627 assert(UseAVX > 0, "requires some form of AVX");
5628 InstructionMark im(this);
5629 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5630 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5631 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5632 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5633 emit_int8((unsigned char)0xDB);
5634 emit_operand(dst, src);
5635 }
5636
5637 void Assembler::pandn(XMMRegister dst, XMMRegister src) {
5638 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5639 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5640 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5641 emit_int8((unsigned char)0xDF);
5642 emit_int8((unsigned char)(0xC0 | encode));
5643 }
5644
5645 void Assembler::por(XMMRegister dst, XMMRegister src) {
5646 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5647 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5648 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5649 emit_int8((unsigned char)0xEB);
5650 emit_int8((unsigned char)(0xC0 | encode));
5651 }
5652
5653 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5654 assert(UseAVX > 0, "requires some form of AVX");
5655 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5656 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5657 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5658 emit_int8((unsigned char)0xEB);
5659 emit_int8((unsigned char)(0xC0 | encode));
5660 }
5661
5662 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5663 assert(UseAVX > 0, "requires some form of AVX");
5664 InstructionMark im(this);
5665 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5666 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5667 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5668 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5669 emit_int8((unsigned char)0xEB);
5670 emit_operand(dst, src);
5671 }
5672
5673 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
5674 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5675 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5676 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5677 emit_int8((unsigned char)0xEF);
5678 emit_int8((unsigned char)(0xC0 | encode));
5679 }
5680
5681 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5682 assert(UseAVX > 0, "requires some form of AVX");
5683 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5684 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5685 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5686 emit_int8((unsigned char)0xEF);
5687 emit_int8((unsigned char)(0xC0 | encode));
5688 }
5689
5690 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5691 assert(UseAVX > 0, "requires some form of AVX");
5692 InstructionMark im(this);
5693 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5694 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5695 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5696 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5697 emit_int8((unsigned char)0xEF);
5698 emit_operand(dst, src);
5699 }
5700
5701
5702 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
5703 assert(VM_Version::supports_avx(), "");
5704 assert(imm8 <= 0x01, "imm8: %u", imm8);
5705 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5706 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5707 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5708 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5709 emit_int8(0x18);
5710 emit_int8((unsigned char)(0xC0 | encode));
5711 // 0x00 - insert into lower 128 bits
5712 // 0x01 - insert into upper 128 bits
5713 emit_int8(imm8 & 0x01);
5714 }
5715
5716 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
5717 assert(VM_Version::supports_evex(), "");
5718 assert(imm8 <= 0x01, "imm8: %u", imm8);
5719 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5720 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5721 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5722 emit_int8(0x1A);
5723 emit_int8((unsigned char)(0xC0 | encode));
5724 // 0x00 - insert into lower 256 bits
5725 // 0x01 - insert into upper 256 bits
5726 emit_int8(imm8 & 0x01);
5727 }
5728
5729 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
5730 assert(VM_Version::supports_evex(), "");
5731 assert(dst != xnoreg, "sanity");
5732 assert(imm8 <= 0x01, "imm8: %u", imm8);
5733 InstructionMark im(this);
5734 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5735 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5736 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_64bit);
5737 // swap src<->dst for encoding
5738 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5739 emit_int8(0x1A);
5740 emit_operand(dst, src);
5741 // 0x00 - insert into lower 256 bits
5742 // 0x01 - insert into upper 256 bits
5743 emit_int8(imm8 & 0x01);
5744 }
5745
5746 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
5747 assert(VM_Version::supports_evex(), "");
5748 assert(imm8 <= 0x03, "imm8: %u", imm8);
5749 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5750 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5751 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5752 emit_int8(0x18);
5753 emit_int8((unsigned char)(0xC0 | encode));
5754 // 0x00 - insert into q0 128 bits (0..127)
5755 // 0x01 - insert into q1 128 bits (128..255)
5756 // 0x02 - insert into q2 128 bits (256..383)
5757 // 0x03 - insert into q3 128 bits (384..511)
5758 emit_int8(imm8 & 0x03);
5759 }
5760
5761 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
5762 assert(VM_Version::supports_avx(), "");
5763 assert(dst != xnoreg, "sanity");
5764 assert(imm8 <= 0x03, "imm8: %u", imm8);
5765 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5766 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5767 InstructionMark im(this);
5768 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5769 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5770 // swap src<->dst for encoding
5771 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5772 emit_int8(0x18);
5773 emit_operand(dst, src);
5774 // 0x00 - insert into q0 128 bits (0..127)
5775 // 0x01 - insert into q1 128 bits (128..255)
5776 // 0x02 - insert into q2 128 bits (256..383)
5777 // 0x03 - insert into q3 128 bits (384..511)
5778 emit_int8(imm8 & 0x03);
5779 }
5780
5781 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
5782 assert(VM_Version::supports_avx(), "");
5783 assert(dst != xnoreg, "sanity");
5784 assert(imm8 <= 0x01, "imm8: %u", imm8);
5785 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5786 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5787 InstructionMark im(this);
5788 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5789 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5790 // swap src<->dst for encoding
5791 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5792 emit_int8(0x18);
5793 emit_operand(dst, src);
5794 // 0x00 - insert into lower 128 bits
5795 // 0x01 - insert into upper 128 bits
5796 emit_int8(imm8 & 0x01);
5797 }
5798
5799 void Assembler::vextractf128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
5800 assert(VM_Version::supports_avx(), "");
5801 assert(imm8 <= 0x01, "imm8: %u", imm8);
5802 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5803 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5804 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5805 emit_int8(0x19);
5806 emit_int8((unsigned char)(0xC0 | encode));
5807 // 0x00 - extract from lower 128 bits
5808 // 0x01 - extract from upper 128 bits
5809 emit_int8(imm8 & 0x01);
5810 }
5811
5812 void Assembler::vextractf128(Address dst, XMMRegister src, uint8_t imm8) {
5813 assert(VM_Version::supports_avx(), "");
5814 assert(src != xnoreg, "sanity");
5815 assert(imm8 <= 0x01, "imm8: %u", imm8);
5816 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5817 InstructionMark im(this);
5818 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5819 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5820 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5821 emit_int8(0x19);
5822 emit_operand(src, dst);
5823 // 0x00 - extract from lower 128 bits
5824 // 0x01 - extract from upper 128 bits
5825 emit_int8(imm8 & 0x01);
5826 }
5827
5828 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
5829 assert(VM_Version::supports_avx2(), "");
5830 assert(imm8 <= 0x01, "imm8: %u", imm8);
5831 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5832 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5833 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5834 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5835 emit_int8(0x38);
5836 emit_int8((unsigned char)(0xC0 | encode));
5837 // 0x00 - insert into lower 128 bits
5838 // 0x01 - insert into upper 128 bits
5839 emit_int8(imm8 & 0x01);
5840 }
5841
5842 void Assembler::vinserti64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
5843 assert(VM_Version::supports_evex(), "");
5844 assert(imm8 <= 0x01, "imm8: %u", imm8);
5845 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5846 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5847 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5848 emit_int8(0x38);
5849 emit_int8((unsigned char)(0xC0 | encode));
5850 // 0x00 - insert into lower 256 bits
5851 // 0x01 - insert into upper 256 bits
5852 emit_int8(imm8 & 0x01);
5853 }
5854
5855 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
5856 assert(VM_Version::supports_avx2(), "");
5857 assert(dst != xnoreg, "sanity");
5858 assert(imm8 <= 0x01, "imm8: %u", imm8);
5859 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5860 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5861 InstructionMark im(this);
5862 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5863 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5864 // swap src<->dst for encoding
5865 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5866 emit_int8(0x38);
5867 emit_operand(dst, src);
5868 // 0x00 - insert into lower 128 bits
5869 // 0x01 - insert into upper 128 bits
5870 emit_int8(imm8 & 0x01);
5871 }
5872
5873 void Assembler::vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
5874 assert(VM_Version::supports_avx(), "");
5875 assert(imm8 <= 0x01, "imm8: %u", imm8);
5876 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5877 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5878 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5879 emit_int8(0x39);
5880 emit_int8((unsigned char)(0xC0 | encode));
5881 // 0x00 - extract from lower 128 bits
5882 // 0x01 - extract from upper 128 bits
5883 emit_int8(imm8 & 0x01);
5884 }
5885
5886 void Assembler::vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
5887 assert(VM_Version::supports_avx2(), "");
5888 assert(src != xnoreg, "sanity");
5889 assert(imm8 <= 0x01, "imm8: %u", imm8);
5890 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5891 InstructionMark im(this);
5892 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5893 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5894 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5895 emit_int8(0x39);
5896 emit_operand(src, dst);
5897 // 0x00 - extract from lower 128 bits
5898 // 0x01 - extract from upper 128 bits
5899 emit_int8(imm8 & 0x01);
5900 }
5901
5902 void Assembler::vextracti64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
5903 assert(VM_Version::supports_evex(), "");
5904 assert(imm8 <= 0x01, "imm8: %u", imm8);
5905 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5906 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5907 emit_int8(0x3B);
5908 emit_int8((unsigned char)(0xC0 | encode));
5909 // 0x00 - extract from lower 256 bits
5910 // 0x01 - extract from upper 256 bits
5911 emit_int8(imm8 & 0x01);
5912 }
5913
5914 void Assembler::vextracti64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) {
5915 assert(VM_Version::supports_evex(), "");
5916 assert(imm8 <= 0x03, "imm8: %u", imm8);
5917 InstructionAttr attributes(AVX_512bit, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5918 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5919 emit_int8(0x39);
5920 emit_int8((unsigned char)(0xC0 | encode));
5921 // 0x00 - extract from bits 127:0
5922 // 0x01 - extract from bits 255:128
5923 // 0x02 - extract from bits 383:256
5924 // 0x03 - extract from bits 511:384
5925 emit_int8(imm8 & 0x03);
5926 }
5927
5928 void Assembler::vextractf64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
5929 assert(VM_Version::supports_evex(), "");
5930 assert(imm8 <= 0x01, "imm8: %u", imm8);
5931 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5932 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5933 emit_int8(0x1B);
5934 emit_int8((unsigned char)(0xC0 | encode));
5935 // 0x00 - extract from lower 256 bits
5936 // 0x01 - extract from upper 256 bits
5937 emit_int8(imm8 & 0x01);
5938 }
5939
5940 void Assembler::vextractf64x4(Address dst, XMMRegister src, uint8_t imm8) {
5941 assert(VM_Version::supports_evex(), "");
5942 assert(src != xnoreg, "sanity");
5943 assert(imm8 <= 0x01, "imm8: %u", imm8);
5944 InstructionMark im(this);
5945 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5946 attributes.set_address_attributes(/* tuple_type */ EVEX_T4,/* input_size_in_bits */ EVEX_64bit);
5947 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5948 emit_int8(0x1B);
5949 emit_operand(src, dst);
5950 // 0x00 - extract from lower 256 bits
5951 // 0x01 - extract from upper 256 bits
5952 emit_int8(imm8 & 0x01);
5953 }
5954
5955 void Assembler::vextractf32x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
5956 assert(VM_Version::supports_avx(), "");
5957 assert(imm8 <= 0x03, "imm8: %u", imm8);
5958 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5959 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5960 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5961 emit_int8(0x19);
5962 emit_int8((unsigned char)(0xC0 | encode));
5963 // 0x00 - extract from bits 127:0
5964 // 0x01 - extract from bits 255:128
5965 // 0x02 - extract from bits 383:256
5966 // 0x03 - extract from bits 511:384
5967 emit_int8(imm8 & 0x03);
5968 }
5969
5970 void Assembler::vextractf32x4(Address dst, XMMRegister src, uint8_t imm8) {
5971 assert(VM_Version::supports_evex(), "");
5972 assert(src != xnoreg, "sanity");
5973 assert(imm8 <= 0x03, "imm8: %u", imm8);
5974 InstructionMark im(this);
5975 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5976 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5977 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5978 emit_int8(0x19);
5979 emit_operand(src, dst);
5980 // 0x00 - extract from bits 127:0
5981 // 0x01 - extract from bits 255:128
5982 // 0x02 - extract from bits 383:256
5983 // 0x03 - extract from bits 511:384
5984 emit_int8(imm8 & 0x03);
5985 }
5986
5987 void Assembler::vextractf64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) {
5988 assert(VM_Version::supports_evex(), "");
5989 assert(imm8 <= 0x03, "imm8: %u", imm8);
5990 InstructionAttr attributes(AVX_512bit, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5991 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5992 emit_int8(0x19);
5993 emit_int8((unsigned char)(0xC0 | encode));
5994 // 0x00 - extract from bits 127:0
5995 // 0x01 - extract from bits 255:128
5996 // 0x02 - extract from bits 383:256
5997 // 0x03 - extract from bits 511:384
5998 emit_int8(imm8 & 0x03);
5999 }
6000
6001 // duplicate 4-bytes integer data from src into 8 locations in dest
6002 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src) {
6003 assert(VM_Version::supports_avx2(), "");
6004 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6005 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6006 emit_int8(0x58);
6007 emit_int8((unsigned char)(0xC0 | encode));
6008 }
6009
6010 // duplicate 2-bytes integer data from src into 16 locations in dest
6011 void Assembler::vpbroadcastw(XMMRegister dst, XMMRegister src) {
6012 assert(VM_Version::supports_avx2(), "");
6013 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6014 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6015 emit_int8(0x79);
6016 emit_int8((unsigned char)(0xC0 | encode));
6017 }
6018
6019 // duplicate 1-byte integer data from src into 16||32|64 locations in dest : requires AVX512BW and AVX512VL
6020 void Assembler::evpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len) {
6021 assert(VM_Version::supports_evex(), "");
6022 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6023 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6024 emit_int8(0x78);
6025 emit_int8((unsigned char)(0xC0 | encode));
6026 }
6027
6028 void Assembler::evpbroadcastb(XMMRegister dst, Address src, int vector_len) {
6029 assert(VM_Version::supports_evex(), "");
6030 assert(dst != xnoreg, "sanity");
6031 InstructionMark im(this);
6032 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6033 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
6034 // swap src<->dst for encoding
6035 vex_prefix(src, dst->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6036 emit_int8(0x78);
6037 emit_operand(dst, src);
6038 }
6039
6040 // duplicate 2-byte integer data from src into 8|16||32 locations in dest : requires AVX512BW and AVX512VL
6041 void Assembler::evpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len) {
6042 assert(VM_Version::supports_evex(), "");
6043 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6044 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6045 emit_int8(0x79);
6046 emit_int8((unsigned char)(0xC0 | encode));
6047 }
6048
6049 void Assembler::evpbroadcastw(XMMRegister dst, Address src, int vector_len) {
6050 assert(VM_Version::supports_evex(), "");
6051 assert(dst != xnoreg, "sanity");
6052 InstructionMark im(this);
6053 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6054 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
6055 // swap src<->dst for encoding
6056 vex_prefix(src, dst->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6057 emit_int8(0x79);
6058 emit_operand(dst, src);
6059 }
6060
6061 // duplicate 4-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
6062 void Assembler::evpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len) {
6063 assert(VM_Version::supports_evex(), "");
6064 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6065 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6066 emit_int8(0x58);
6067 emit_int8((unsigned char)(0xC0 | encode));
6068 }
6069
6070 void Assembler::evpbroadcastd(XMMRegister dst, Address src, int vector_len) {
6071 assert(VM_Version::supports_evex(), "");
6072 assert(dst != xnoreg, "sanity");
6073 InstructionMark im(this);
6074 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6075 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
6076 // swap src<->dst for encoding
6077 vex_prefix(src, dst->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6078 emit_int8(0x58);
6079 emit_operand(dst, src);
6080 }
6081
6082 // duplicate 8-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
6083 void Assembler::evpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len) {
6084 assert(VM_Version::supports_evex(), "");
6085 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6086 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6087 emit_int8(0x59);
6088 emit_int8((unsigned char)(0xC0 | encode));
6089 }
6090
6091 void Assembler::evpbroadcastq(XMMRegister dst, Address src, int vector_len) {
6092 assert(VM_Version::supports_evex(), "");
6093 assert(dst != xnoreg, "sanity");
6094 InstructionMark im(this);
6095 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6096 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6097 // swap src<->dst for encoding
6098 vex_prefix(src, dst->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6099 emit_int8(0x59);
6100 emit_operand(dst, src);
6101 }
6102
6103 // duplicate single precision fp from src into 4|8|16 locations in dest : requires AVX512VL
6104 void Assembler::evpbroadcastss(XMMRegister dst, XMMRegister src, int vector_len) {
6105 assert(VM_Version::supports_evex(), "");
6106 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6107 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6108 emit_int8(0x18);
6109 emit_int8((unsigned char)(0xC0 | encode));
6110 }
6111
6112 void Assembler::evpbroadcastss(XMMRegister dst, Address src, int vector_len) {
6113 assert(VM_Version::supports_evex(), "");
6114 assert(dst != xnoreg, "sanity");
6115 InstructionMark im(this);
6116 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6117 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
6118 // swap src<->dst for encoding
6119 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6120 emit_int8(0x18);
6121 emit_operand(dst, src);
6122 }
6123
6124 // duplicate double precision fp from src into 2|4|8 locations in dest : requires AVX512VL
6125 void Assembler::evpbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len) {
6126 assert(VM_Version::supports_evex(), "");
6127 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6128 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6129 emit_int8(0x19);
6130 emit_int8((unsigned char)(0xC0 | encode));
6131 }
6132
6133 void Assembler::evpbroadcastsd(XMMRegister dst, Address src, int vector_len) {
6134 assert(VM_Version::supports_evex(), "");
6135 assert(dst != xnoreg, "sanity");
6136 InstructionMark im(this);
6137 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6138 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6139 // swap src<->dst for encoding
6140 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6141 emit_int8(0x19);
6142 emit_operand(dst, src);
6143 }
6144
6145 // duplicate 1-byte integer data from src into 16||32|64 locations in dest : requires AVX512BW and AVX512VL
6146 void Assembler::evpbroadcastb(XMMRegister dst, Register src, int vector_len) {
6147 assert(VM_Version::supports_evex(), "");
6148 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6149 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6150 emit_int8(0x7A);
6151 emit_int8((unsigned char)(0xC0 | encode));
6152 }
6153
6154 // duplicate 2-byte integer data from src into 8|16||32 locations in dest : requires AVX512BW and AVX512VL
6155 void Assembler::evpbroadcastw(XMMRegister dst, Register src, int vector_len) {
6156 assert(VM_Version::supports_evex(), "");
6157 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6158 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6159 emit_int8(0x7B);
6160 emit_int8((unsigned char)(0xC0 | encode));
6161 }
6162
6163 // duplicate 4-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
6164 void Assembler::evpbroadcastd(XMMRegister dst, Register src, int vector_len) {
6165 assert(VM_Version::supports_evex(), "");
6166 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6167 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6168 emit_int8(0x7C);
6169 emit_int8((unsigned char)(0xC0 | encode));
6170 }
6171
6172 // duplicate 8-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
6173 void Assembler::evpbroadcastq(XMMRegister dst, Register src, int vector_len) {
6174 assert(VM_Version::supports_evex(), "");
6175 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6176 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6177 emit_int8(0x7C);
6178 emit_int8((unsigned char)(0xC0 | encode));
6179 }
6180
6181 // Carry-Less Multiplication Quadword
6182 void Assembler::pclmulqdq(XMMRegister dst, XMMRegister src, int mask) {
6183 assert(VM_Version::supports_clmul(), "");
6184 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6185 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6186 emit_int8(0x44);
6187 emit_int8((unsigned char)(0xC0 | encode));
6188 emit_int8((unsigned char)mask);
6189 }
6190
6191 // Carry-Less Multiplication Quadword
6192 void Assembler::vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask) {
6193 assert(VM_Version::supports_avx() && VM_Version::supports_clmul(), "");
6194 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6195 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
6196 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6197 emit_int8(0x44);
6198 emit_int8((unsigned char)(0xC0 | encode));
6199 emit_int8((unsigned char)mask);
6200 }
6201
6202 void Assembler::vzeroupper() {
6203 assert(VM_Version::supports_avx(), "");
6204 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6205 (void)vex_prefix_and_encode(0, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6206 emit_int8(0x77);
6207 }
6208
6209
6210 #ifndef _LP64
6211 // 32bit only pieces of the assembler
6212
6213 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
6214 // NO PREFIX AS NEVER 64BIT
6215 InstructionMark im(this);
6216 emit_int8((unsigned char)0x81);
6217 emit_int8((unsigned char)(0xF8 | src1->encoding()));
6218 emit_data(imm32, rspec, 0);
6219 }
6220
6221 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
6222 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
6223 InstructionMark im(this);
6224 emit_int8((unsigned char)0x81);
6225 emit_operand(rdi, src1);
6226 emit_data(imm32, rspec, 0);
6227 }
6228
6229 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax,
6230 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded
6231 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise.
6232 void Assembler::cmpxchg8(Address adr) {
6233 InstructionMark im(this);
6234 emit_int8(0x0F);
6235 emit_int8((unsigned char)0xC7);
6236 emit_operand(rcx, adr);
6237 }
6238
6239 void Assembler::decl(Register dst) {
6240 // Don't use it directly. Use MacroAssembler::decrementl() instead.
6241 emit_int8(0x48 | dst->encoding());
6242 }
6243
6244 #endif // _LP64
6245
6246 // 64bit typically doesn't use the x87 but needs to for the trig funcs
6247
6248 void Assembler::fabs() {
6249 emit_int8((unsigned char)0xD9);
6250 emit_int8((unsigned char)0xE1);
6251 }
6252
6253 void Assembler::fadd(int i) {
6254 emit_farith(0xD8, 0xC0, i);
6255 }
6256
6257 void Assembler::fadd_d(Address src) {
6258 InstructionMark im(this);
6259 emit_int8((unsigned char)0xDC);
6260 emit_operand32(rax, src);
6261 }
6262
6263 void Assembler::fadd_s(Address src) {
6264 InstructionMark im(this);
6265 emit_int8((unsigned char)0xD8);
6266 emit_operand32(rax, src);
6267 }
6268
6269 void Assembler::fadda(int i) {
6270 emit_farith(0xDC, 0xC0, i);
6271 }
6272
6273 void Assembler::faddp(int i) {
6274 emit_farith(0xDE, 0xC0, i);
6275 }
6276
6277 void Assembler::fchs() {
6278 emit_int8((unsigned char)0xD9);
6279 emit_int8((unsigned char)0xE0);
6280 }
6281
6282 void Assembler::fcom(int i) {
6283 emit_farith(0xD8, 0xD0, i);
6284 }
6285
6286 void Assembler::fcomp(int i) {
6287 emit_farith(0xD8, 0xD8, i);
6288 }
6289
6290 void Assembler::fcomp_d(Address src) {
6291 InstructionMark im(this);
6292 emit_int8((unsigned char)0xDC);
6293 emit_operand32(rbx, src);
6294 }
6295
6296 void Assembler::fcomp_s(Address src) {
6297 InstructionMark im(this);
6298 emit_int8((unsigned char)0xD8);
6299 emit_operand32(rbx, src);
6300 }
6301
6302 void Assembler::fcompp() {
6303 emit_int8((unsigned char)0xDE);
6304 emit_int8((unsigned char)0xD9);
6305 }
6306
6307 void Assembler::fcos() {
6308 emit_int8((unsigned char)0xD9);
6309 emit_int8((unsigned char)0xFF);
6310 }
6311
6312 void Assembler::fdecstp() {
6313 emit_int8((unsigned char)0xD9);
6314 emit_int8((unsigned char)0xF6);
6315 }
6316
6317 void Assembler::fdiv(int i) {
6318 emit_farith(0xD8, 0xF0, i);
6319 }
6320
6321 void Assembler::fdiv_d(Address src) {
6322 InstructionMark im(this);
6323 emit_int8((unsigned char)0xDC);
6324 emit_operand32(rsi, src);
6325 }
6326
6327 void Assembler::fdiv_s(Address src) {
6328 InstructionMark im(this);
6329 emit_int8((unsigned char)0xD8);
6330 emit_operand32(rsi, src);
6331 }
6332
6333 void Assembler::fdiva(int i) {
6334 emit_farith(0xDC, 0xF8, i);
6335 }
6336
6337 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994)
6338 // is erroneous for some of the floating-point instructions below.
6339
6340 void Assembler::fdivp(int i) {
6341 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong)
6342 }
6343
6344 void Assembler::fdivr(int i) {
6345 emit_farith(0xD8, 0xF8, i);
6346 }
6347
6348 void Assembler::fdivr_d(Address src) {
6349 InstructionMark im(this);
6350 emit_int8((unsigned char)0xDC);
6351 emit_operand32(rdi, src);
6352 }
6353
6354 void Assembler::fdivr_s(Address src) {
6355 InstructionMark im(this);
6356 emit_int8((unsigned char)0xD8);
6357 emit_operand32(rdi, src);
6358 }
6359
6360 void Assembler::fdivra(int i) {
6361 emit_farith(0xDC, 0xF0, i);
6362 }
6363
6364 void Assembler::fdivrp(int i) {
6365 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong)
6366 }
6367
6368 void Assembler::ffree(int i) {
6369 emit_farith(0xDD, 0xC0, i);
6370 }
6371
6372 void Assembler::fild_d(Address adr) {
6373 InstructionMark im(this);
6374 emit_int8((unsigned char)0xDF);
6375 emit_operand32(rbp, adr);
6376 }
6377
6378 void Assembler::fild_s(Address adr) {
6379 InstructionMark im(this);
6380 emit_int8((unsigned char)0xDB);
6381 emit_operand32(rax, adr);
6382 }
6383
6384 void Assembler::fincstp() {
6385 emit_int8((unsigned char)0xD9);
6386 emit_int8((unsigned char)0xF7);
6387 }
6388
6389 void Assembler::finit() {
6390 emit_int8((unsigned char)0x9B);
6391 emit_int8((unsigned char)0xDB);
6392 emit_int8((unsigned char)0xE3);
6393 }
6394
6395 void Assembler::fist_s(Address adr) {
6396 InstructionMark im(this);
6397 emit_int8((unsigned char)0xDB);
6398 emit_operand32(rdx, adr);
6399 }
6400
6401 void Assembler::fistp_d(Address adr) {
6402 InstructionMark im(this);
6403 emit_int8((unsigned char)0xDF);
6404 emit_operand32(rdi, adr);
6405 }
6406
6407 void Assembler::fistp_s(Address adr) {
6408 InstructionMark im(this);
6409 emit_int8((unsigned char)0xDB);
6410 emit_operand32(rbx, adr);
6411 }
6412
6413 void Assembler::fld1() {
6414 emit_int8((unsigned char)0xD9);
6415 emit_int8((unsigned char)0xE8);
6416 }
6417
6418 void Assembler::fld_d(Address adr) {
6419 InstructionMark im(this);
6420 emit_int8((unsigned char)0xDD);
6421 emit_operand32(rax, adr);
6422 }
6423
6424 void Assembler::fld_s(Address adr) {
6425 InstructionMark im(this);
6426 emit_int8((unsigned char)0xD9);
6427 emit_operand32(rax, adr);
6428 }
6429
6430
6431 void Assembler::fld_s(int index) {
6432 emit_farith(0xD9, 0xC0, index);
6433 }
6434
6435 void Assembler::fld_x(Address adr) {
6436 InstructionMark im(this);
6437 emit_int8((unsigned char)0xDB);
6438 emit_operand32(rbp, adr);
6439 }
6440
6441 void Assembler::fldcw(Address src) {
6442 InstructionMark im(this);
6443 emit_int8((unsigned char)0xD9);
6444 emit_operand32(rbp, src);
6445 }
6446
6447 void Assembler::fldenv(Address src) {
6448 InstructionMark im(this);
6449 emit_int8((unsigned char)0xD9);
6450 emit_operand32(rsp, src);
6451 }
6452
6453 void Assembler::fldlg2() {
6454 emit_int8((unsigned char)0xD9);
6455 emit_int8((unsigned char)0xEC);
6456 }
6457
6458 void Assembler::fldln2() {
6459 emit_int8((unsigned char)0xD9);
6460 emit_int8((unsigned char)0xED);
6461 }
6462
6463 void Assembler::fldz() {
6464 emit_int8((unsigned char)0xD9);
6465 emit_int8((unsigned char)0xEE);
6466 }
6467
6468 void Assembler::flog() {
6469 fldln2();
6470 fxch();
6471 fyl2x();
6472 }
6473
6474 void Assembler::flog10() {
6475 fldlg2();
6476 fxch();
6477 fyl2x();
6478 }
6479
6480 void Assembler::fmul(int i) {
6481 emit_farith(0xD8, 0xC8, i);
6482 }
6483
6484 void Assembler::fmul_d(Address src) {
6485 InstructionMark im(this);
6486 emit_int8((unsigned char)0xDC);
6487 emit_operand32(rcx, src);
6488 }
6489
6490 void Assembler::fmul_s(Address src) {
6491 InstructionMark im(this);
6492 emit_int8((unsigned char)0xD8);
6493 emit_operand32(rcx, src);
6494 }
6495
6496 void Assembler::fmula(int i) {
6497 emit_farith(0xDC, 0xC8, i);
6498 }
6499
6500 void Assembler::fmulp(int i) {
6501 emit_farith(0xDE, 0xC8, i);
6502 }
6503
6504 void Assembler::fnsave(Address dst) {
6505 InstructionMark im(this);
6506 emit_int8((unsigned char)0xDD);
6507 emit_operand32(rsi, dst);
6508 }
6509
6510 void Assembler::fnstcw(Address src) {
6511 InstructionMark im(this);
6512 emit_int8((unsigned char)0x9B);
6513 emit_int8((unsigned char)0xD9);
6514 emit_operand32(rdi, src);
6515 }
6516
6517 void Assembler::fnstsw_ax() {
6518 emit_int8((unsigned char)0xDF);
6519 emit_int8((unsigned char)0xE0);
6520 }
6521
6522 void Assembler::fprem() {
6523 emit_int8((unsigned char)0xD9);
6524 emit_int8((unsigned char)0xF8);
6525 }
6526
6527 void Assembler::fprem1() {
6528 emit_int8((unsigned char)0xD9);
6529 emit_int8((unsigned char)0xF5);
6530 }
6531
6532 void Assembler::frstor(Address src) {
6533 InstructionMark im(this);
6534 emit_int8((unsigned char)0xDD);
6535 emit_operand32(rsp, src);
6536 }
6537
6538 void Assembler::fsin() {
6539 emit_int8((unsigned char)0xD9);
6540 emit_int8((unsigned char)0xFE);
6541 }
6542
6543 void Assembler::fsqrt() {
6544 emit_int8((unsigned char)0xD9);
6545 emit_int8((unsigned char)0xFA);
6546 }
6547
6548 void Assembler::fst_d(Address adr) {
6549 InstructionMark im(this);
6550 emit_int8((unsigned char)0xDD);
6551 emit_operand32(rdx, adr);
6552 }
6553
6554 void Assembler::fst_s(Address adr) {
6555 InstructionMark im(this);
6556 emit_int8((unsigned char)0xD9);
6557 emit_operand32(rdx, adr);
6558 }
6559
6560 void Assembler::fstp_d(Address adr) {
6561 InstructionMark im(this);
6562 emit_int8((unsigned char)0xDD);
6563 emit_operand32(rbx, adr);
6564 }
6565
6566 void Assembler::fstp_d(int index) {
6567 emit_farith(0xDD, 0xD8, index);
6568 }
6569
6570 void Assembler::fstp_s(Address adr) {
6571 InstructionMark im(this);
6572 emit_int8((unsigned char)0xD9);
6573 emit_operand32(rbx, adr);
6574 }
6575
6576 void Assembler::fstp_x(Address adr) {
6577 InstructionMark im(this);
6578 emit_int8((unsigned char)0xDB);
6579 emit_operand32(rdi, adr);
6580 }
6581
6582 void Assembler::fsub(int i) {
6583 emit_farith(0xD8, 0xE0, i);
6584 }
6585
6586 void Assembler::fsub_d(Address src) {
6587 InstructionMark im(this);
6588 emit_int8((unsigned char)0xDC);
6589 emit_operand32(rsp, src);
6590 }
6591
6592 void Assembler::fsub_s(Address src) {
6593 InstructionMark im(this);
6594 emit_int8((unsigned char)0xD8);
6595 emit_operand32(rsp, src);
6596 }
6597
6598 void Assembler::fsuba(int i) {
6599 emit_farith(0xDC, 0xE8, i);
6600 }
6601
6602 void Assembler::fsubp(int i) {
6603 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong)
6604 }
6605
6606 void Assembler::fsubr(int i) {
6607 emit_farith(0xD8, 0xE8, i);
6608 }
6609
6610 void Assembler::fsubr_d(Address src) {
6611 InstructionMark im(this);
6612 emit_int8((unsigned char)0xDC);
6613 emit_operand32(rbp, src);
6614 }
6615
6616 void Assembler::fsubr_s(Address src) {
6617 InstructionMark im(this);
6618 emit_int8((unsigned char)0xD8);
6619 emit_operand32(rbp, src);
6620 }
6621
6622 void Assembler::fsubra(int i) {
6623 emit_farith(0xDC, 0xE0, i);
6624 }
6625
6626 void Assembler::fsubrp(int i) {
6627 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong)
6628 }
6629
6630 void Assembler::ftan() {
6631 emit_int8((unsigned char)0xD9);
6632 emit_int8((unsigned char)0xF2);
6633 emit_int8((unsigned char)0xDD);
6634 emit_int8((unsigned char)0xD8);
6635 }
6636
6637 void Assembler::ftst() {
6638 emit_int8((unsigned char)0xD9);
6639 emit_int8((unsigned char)0xE4);
6640 }
6641
6642 void Assembler::fucomi(int i) {
6643 // make sure the instruction is supported (introduced for P6, together with cmov)
6644 guarantee(VM_Version::supports_cmov(), "illegal instruction");
6645 emit_farith(0xDB, 0xE8, i);
6646 }
6647
6648 void Assembler::fucomip(int i) {
6649 // make sure the instruction is supported (introduced for P6, together with cmov)
6650 guarantee(VM_Version::supports_cmov(), "illegal instruction");
6651 emit_farith(0xDF, 0xE8, i);
6652 }
6653
6654 void Assembler::fwait() {
6655 emit_int8((unsigned char)0x9B);
6656 }
6657
6658 void Assembler::fxch(int i) {
6659 emit_farith(0xD9, 0xC8, i);
6660 }
6661
6662 void Assembler::fyl2x() {
6663 emit_int8((unsigned char)0xD9);
6664 emit_int8((unsigned char)0xF1);
6665 }
6666
6667 void Assembler::frndint() {
6668 emit_int8((unsigned char)0xD9);
6669 emit_int8((unsigned char)0xFC);
6670 }
6671
6672 void Assembler::f2xm1() {
6673 emit_int8((unsigned char)0xD9);
6674 emit_int8((unsigned char)0xF0);
6675 }
6676
6677 void Assembler::fldl2e() {
6678 emit_int8((unsigned char)0xD9);
6679 emit_int8((unsigned char)0xEA);
6680 }
6681
6682 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding.
6683 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 };
6684 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding.
6685 static int simd_opc[4] = { 0, 0, 0x38, 0x3A };
6686
6687 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding.
6688 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
6689 if (pre > 0) {
6690 emit_int8(simd_pre[pre]);
6691 }
6692 if (rex_w) {
6693 prefixq(adr, xreg);
6694 } else {
6695 prefix(adr, xreg);
6696 }
6697 if (opc > 0) {
6698 emit_int8(0x0F);
6699 int opc2 = simd_opc[opc];
6700 if (opc2 > 0) {
6701 emit_int8(opc2);
6702 }
6703 }
6704 }
6705
6706 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
6707 if (pre > 0) {
6708 emit_int8(simd_pre[pre]);
6709 }
6710 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) : prefix_and_encode(dst_enc, src_enc);
6711 if (opc > 0) {
6712 emit_int8(0x0F);
6713 int opc2 = simd_opc[opc];
6714 if (opc2 > 0) {
6715 emit_int8(opc2);
6716 }
6717 }
6718 return encode;
6719 }
6720
6721
6722 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc) {
6723 int vector_len = _attributes->get_vector_len();
6724 bool vex_w = _attributes->is_rex_vex_w();
6725 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) {
6726 prefix(VEX_3bytes);
6727
6728 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0);
6729 byte1 = (~byte1) & 0xE0;
6730 byte1 |= opc;
6731 emit_int8(byte1);
6732
6733 int byte2 = ((~nds_enc) & 0xf) << 3;
6734 byte2 |= (vex_w ? VEX_W : 0) | ((vector_len > 0) ? 4 : 0) | pre;
6735 emit_int8(byte2);
6736 } else {
6737 prefix(VEX_2bytes);
6738
6739 int byte1 = vex_r ? VEX_R : 0;
6740 byte1 = (~byte1) & 0x80;
6741 byte1 |= ((~nds_enc) & 0xf) << 3;
6742 byte1 |= ((vector_len > 0 ) ? 4 : 0) | pre;
6743 emit_int8(byte1);
6744 }
6745 }
6746
6747 // This is a 4 byte encoding
6748 void Assembler::evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_r, bool evex_v, int nds_enc, VexSimdPrefix pre, VexOpcode opc){
6749 // EVEX 0x62 prefix
6750 prefix(EVEX_4bytes);
6751 bool vex_w = _attributes->is_rex_vex_w();
6752 int evex_encoding = (vex_w ? VEX_W : 0);
6753 // EVEX.b is not currently used for broadcast of single element or data rounding modes
6754 _attributes->set_evex_encoding(evex_encoding);
6755
6756 // P0: byte 2, initialized to RXBR`00mm
6757 // instead of not'd
6758 int byte2 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0) | (evex_r ? EVEX_Rb : 0);
6759 byte2 = (~byte2) & 0xF0;
6760 // confine opc opcode extensions in mm bits to lower two bits
6761 // of form {0F, 0F_38, 0F_3A}
6762 byte2 |= opc;
6763 emit_int8(byte2);
6764
6765 // P1: byte 3 as Wvvvv1pp
6766 int byte3 = ((~nds_enc) & 0xf) << 3;
6767 // p[10] is always 1
6768 byte3 |= EVEX_F;
6769 byte3 |= (vex_w & 1) << 7;
6770 // confine pre opcode extensions in pp bits to lower two bits
6771 // of form {66, F3, F2}
6772 byte3 |= pre;
6773 emit_int8(byte3);
6774
6775 // P2: byte 4 as zL'Lbv'aaa
6776 int byte4 = (_attributes->is_no_reg_mask()) ? 0 : 1; // kregs are implemented in the low 3 bits as aaa (hard code k1, it will be initialized for now)
6777 // EVEX.v` for extending EVEX.vvvv or VIDX
6778 byte4 |= (evex_v ? 0: EVEX_V);
6779 // third EXEC.b for broadcast actions
6780 byte4 |= (_attributes->is_extended_context() ? EVEX_Rb : 0);
6781 // fourth EVEX.L'L for vector length : 0 is 128, 1 is 256, 2 is 512, currently we do not support 1024
6782 byte4 |= ((_attributes->get_vector_len())& 0x3) << 5;
6783 // last is EVEX.z for zero/merge actions
6784 byte4 |= (_attributes->is_clear_context() ? EVEX_Z : 0);
6785 emit_int8(byte4);
6786 }
6787
6788 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) {
6789 bool vex_r = ((xreg_enc & 8) == 8) ? 1 : 0;
6790 bool vex_b = adr.base_needs_rex();
6791 bool vex_x = adr.index_needs_rex();
6792 set_attributes(attributes);
6793 attributes->set_current_assembler(this);
6794
6795 // if vector length is turned off, revert to AVX for vectors smaller than 512-bit
6796 if ((UseAVX > 2) && _legacy_mode_vl && attributes->uses_vl()) {
6797 switch (attributes->get_vector_len()) {
6798 case AVX_128bit:
6799 case AVX_256bit:
6800 attributes->set_is_legacy_mode();
6801 break;
6802 }
6803 }
6804
6805 if ((UseAVX > 2) && !attributes->is_legacy_mode())
6806 {
6807 bool evex_r = (xreg_enc >= 16);
6808 bool evex_v = (nds_enc >= 16);
6809 attributes->set_is_evex_instruction();
6810 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc);
6811 } else {
6812 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc);
6813 }
6814 }
6815
6816 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) {
6817 bool vex_r = ((dst_enc & 8) == 8) ? 1 : 0;
6818 bool vex_b = ((src_enc & 8) == 8) ? 1 : 0;
6819 bool vex_x = false;
6820 set_attributes(attributes);
6821 attributes->set_current_assembler(this);
6822
6823 // if vector length is turned off, revert to AVX for vectors smaller than 512-bit
6824 if ((UseAVX > 2) && _legacy_mode_vl && attributes->uses_vl()) {
6825 switch (attributes->get_vector_len()) {
6826 case AVX_128bit:
6827 case AVX_256bit:
6828 if ((dst_enc >= 16) | (nds_enc >= 16) | (src_enc >= 16)) {
6829 // up propagate arithmetic instructions to meet RA requirements
6830 attributes->set_vector_len(AVX_512bit);
6831 } else {
6832 attributes->set_is_legacy_mode();
6833 }
6834 break;
6835 }
6836 }
6837
6838 if ((UseAVX > 2) && !attributes->is_legacy_mode())
6839 {
6840 bool evex_r = (dst_enc >= 16);
6841 bool evex_v = (nds_enc >= 16);
6842 // can use vex_x as bank extender on rm encoding
6843 vex_x = (src_enc >= 16);
6844 attributes->set_is_evex_instruction();
6845 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc);
6846 } else {
6847 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc);
6848 }
6849
6850 // return modrm byte components for operands
6851 return (((dst_enc & 7) << 3) | (src_enc & 7));
6852 }
6853
6854
6855 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre,
6856 VexOpcode opc, InstructionAttr *attributes) {
6857 if (UseAVX > 0) {
6858 int xreg_enc = xreg->encoding();
6859 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
6860 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, attributes);
6861 } else {
6862 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding");
6863 rex_prefix(adr, xreg, pre, opc, attributes->is_rex_vex_w());
6864 }
6865 }
6866
6867 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre,
6868 VexOpcode opc, InstructionAttr *attributes) {
6869 int dst_enc = dst->encoding();
6870 int src_enc = src->encoding();
6871 if (UseAVX > 0) {
6872 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
6873 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, attributes);
6874 } else {
6875 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding");
6876 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, attributes->is_rex_vex_w());
6877 }
6878 }
6879
6880 void Assembler::cmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) {
6881 assert(VM_Version::supports_avx(), "");
6882 assert(!VM_Version::supports_evex(), "");
6883 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6884 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6885 emit_int8((unsigned char)0xC2);
6886 emit_int8((unsigned char)(0xC0 | encode));
6887 emit_int8((unsigned char)(0xF & cop));
6888 }
6889
6890 void Assembler::vpblendd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) {
6891 assert(VM_Version::supports_avx(), "");
6892 assert(!VM_Version::supports_evex(), "");
6893 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6894 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
6895 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6896 emit_int8((unsigned char)0x4B);
6897 emit_int8((unsigned char)(0xC0 | encode));
6898 int src2_enc = src2->encoding();
6899 emit_int8((unsigned char)(0xF0 & src2_enc<<4));
6900 }
6901
6902
6903 #ifndef _LP64
6904
6905 void Assembler::incl(Register dst) {
6906 // Don't use it directly. Use MacroAssembler::incrementl() instead.
6907 emit_int8(0x40 | dst->encoding());
6908 }
6909
6910 void Assembler::lea(Register dst, Address src) {
6911 leal(dst, src);
6912 }
6913
6914 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
6915 InstructionMark im(this);
6916 emit_int8((unsigned char)0xC7);
6917 emit_operand(rax, dst);
6918 emit_data((int)imm32, rspec, 0);
6919 }
6920
6921 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
6922 InstructionMark im(this);
6923 int encode = prefix_and_encode(dst->encoding());
6924 emit_int8((unsigned char)(0xB8 | encode));
6925 emit_data((int)imm32, rspec, 0);
6926 }
6927
6928 void Assembler::popa() { // 32bit
6929 emit_int8(0x61);
6930 }
6931
6932 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
6933 InstructionMark im(this);
6934 emit_int8(0x68);
6935 emit_data(imm32, rspec, 0);
6936 }
6937
6938 void Assembler::pusha() { // 32bit
6939 emit_int8(0x60);
6940 }
6941
6942 void Assembler::set_byte_if_not_zero(Register dst) {
6943 emit_int8(0x0F);
6944 emit_int8((unsigned char)0x95);
6945 emit_int8((unsigned char)(0xE0 | dst->encoding()));
6946 }
6947
6948 void Assembler::shldl(Register dst, Register src) {
6949 emit_int8(0x0F);
6950 emit_int8((unsigned char)0xA5);
6951 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
6952 }
6953
6954 // 0F A4 / r ib
6955 void Assembler::shldl(Register dst, Register src, int8_t imm8) {
6956 emit_int8(0x0F);
6957 emit_int8((unsigned char)0xA4);
6958 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
6959 emit_int8(imm8);
6960 }
6961
6962 void Assembler::shrdl(Register dst, Register src) {
6963 emit_int8(0x0F);
6964 emit_int8((unsigned char)0xAD);
6965 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
6966 }
6967
6968 #else // LP64
6969
6970 void Assembler::set_byte_if_not_zero(Register dst) {
6971 int enc = prefix_and_encode(dst->encoding(), true);
6972 emit_int8(0x0F);
6973 emit_int8((unsigned char)0x95);
6974 emit_int8((unsigned char)(0xE0 | enc));
6975 }
6976
6977 // 64bit only pieces of the assembler
6978 // This should only be used by 64bit instructions that can use rip-relative
6979 // it cannot be used by instructions that want an immediate value.
6980
6981 bool Assembler::reachable(AddressLiteral adr) {
6982 int64_t disp;
6983 // None will force a 64bit literal to the code stream. Likely a placeholder
6984 // for something that will be patched later and we need to certain it will
6985 // always be reachable.
6986 if (adr.reloc() == relocInfo::none) {
6987 return false;
6988 }
6989 if (adr.reloc() == relocInfo::internal_word_type) {
6990 // This should be rip relative and easily reachable.
6991 return true;
6992 }
6993 if (adr.reloc() == relocInfo::virtual_call_type ||
6994 adr.reloc() == relocInfo::opt_virtual_call_type ||
6995 adr.reloc() == relocInfo::static_call_type ||
6996 adr.reloc() == relocInfo::static_stub_type ) {
6997 // This should be rip relative within the code cache and easily
6998 // reachable until we get huge code caches. (At which point
6999 // ic code is going to have issues).
7000 return true;
7001 }
7002 if (adr.reloc() != relocInfo::external_word_type &&
7003 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special
7004 adr.reloc() != relocInfo::poll_type && // relocs to identify them
7005 adr.reloc() != relocInfo::runtime_call_type ) {
7006 return false;
7007 }
7008
7009 // Stress the correction code
7010 if (ForceUnreachable) {
7011 // Must be runtimecall reloc, see if it is in the codecache
7012 // Flipping stuff in the codecache to be unreachable causes issues
7013 // with things like inline caches where the additional instructions
7014 // are not handled.
7015 if (CodeCache::find_blob(adr._target) == NULL) {
7016 return false;
7017 }
7018 }
7019 // For external_word_type/runtime_call_type if it is reachable from where we
7020 // are now (possibly a temp buffer) and where we might end up
7021 // anywhere in the codeCache then we are always reachable.
7022 // This would have to change if we ever save/restore shared code
7023 // to be more pessimistic.
7024 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int));
7025 if (!is_simm32(disp)) return false;
7026 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int));
7027 if (!is_simm32(disp)) return false;
7028
7029 disp = (int64_t)adr._target - ((int64_t)pc() + sizeof(int));
7030
7031 // Because rip relative is a disp + address_of_next_instruction and we
7032 // don't know the value of address_of_next_instruction we apply a fudge factor
7033 // to make sure we will be ok no matter the size of the instruction we get placed into.
7034 // We don't have to fudge the checks above here because they are already worst case.
7035
7036 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal
7037 // + 4 because better safe than sorry.
7038 const int fudge = 12 + 4;
7039 if (disp < 0) {
7040 disp -= fudge;
7041 } else {
7042 disp += fudge;
7043 }
7044 return is_simm32(disp);
7045 }
7046
7047 // Check if the polling page is not reachable from the code cache using rip-relative
7048 // addressing.
7049 bool Assembler::is_polling_page_far() {
7050 intptr_t addr = (intptr_t)os::get_polling_page();
7051 return ForceUnreachable ||
7052 !is_simm32(addr - (intptr_t)CodeCache::low_bound()) ||
7053 !is_simm32(addr - (intptr_t)CodeCache::high_bound());
7054 }
7055
7056 void Assembler::emit_data64(jlong data,
7057 relocInfo::relocType rtype,
7058 int format) {
7059 if (rtype == relocInfo::none) {
7060 emit_int64(data);
7061 } else {
7062 emit_data64(data, Relocation::spec_simple(rtype), format);
7063 }
7064 }
7065
7066 void Assembler::emit_data64(jlong data,
7067 RelocationHolder const& rspec,
7068 int format) {
7069 assert(imm_operand == 0, "default format must be immediate in this file");
7070 assert(imm_operand == format, "must be immediate");
7071 assert(inst_mark() != NULL, "must be inside InstructionMark");
7072 // Do not use AbstractAssembler::relocate, which is not intended for
7073 // embedded words. Instead, relocate to the enclosing instruction.
7074 code_section()->relocate(inst_mark(), rspec, format);
7075 #ifdef ASSERT
7076 check_relocation(rspec, format);
7077 #endif
7078 emit_int64(data);
7079 }
7080
7081 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) {
7082 if (reg_enc >= 8) {
7083 prefix(REX_B);
7084 reg_enc -= 8;
7085 } else if (byteinst && reg_enc >= 4) {
7086 prefix(REX);
7087 }
7088 return reg_enc;
7089 }
7090
7091 int Assembler::prefixq_and_encode(int reg_enc) {
7092 if (reg_enc < 8) {
7093 prefix(REX_W);
7094 } else {
7095 prefix(REX_WB);
7096 reg_enc -= 8;
7097 }
7098 return reg_enc;
7099 }
7100
7101 int Assembler::prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte) {
7102 if (dst_enc < 8) {
7103 if (src_enc >= 8) {
7104 prefix(REX_B);
7105 src_enc -= 8;
7106 } else if ((src_is_byte && src_enc >= 4) || (dst_is_byte && dst_enc >= 4)) {
7107 prefix(REX);
7108 }
7109 } else {
7110 if (src_enc < 8) {
7111 prefix(REX_R);
7112 } else {
7113 prefix(REX_RB);
7114 src_enc -= 8;
7115 }
7116 dst_enc -= 8;
7117 }
7118 return dst_enc << 3 | src_enc;
7119 }
7120
7121 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) {
7122 if (dst_enc < 8) {
7123 if (src_enc < 8) {
7124 prefix(REX_W);
7125 } else {
7126 prefix(REX_WB);
7127 src_enc -= 8;
7128 }
7129 } else {
7130 if (src_enc < 8) {
7131 prefix(REX_WR);
7132 } else {
7133 prefix(REX_WRB);
7134 src_enc -= 8;
7135 }
7136 dst_enc -= 8;
7137 }
7138 return dst_enc << 3 | src_enc;
7139 }
7140
7141 void Assembler::prefix(Register reg) {
7142 if (reg->encoding() >= 8) {
7143 prefix(REX_B);
7144 }
7145 }
7146
7147 void Assembler::prefix(Register dst, Register src, Prefix p) {
7148 if (src->encoding() >= 8) {
7149 p = (Prefix)(p | REX_B);
7150 }
7151 if (dst->encoding() >= 8) {
7152 p = (Prefix)( p | REX_R);
7153 }
7154 if (p != Prefix_EMPTY) {
7155 // do not generate an empty prefix
7156 prefix(p);
7157 }
7158 }
7159
7160 void Assembler::prefix(Register dst, Address adr, Prefix p) {
7161 if (adr.base_needs_rex()) {
7162 if (adr.index_needs_rex()) {
7163 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X");
7164 } else {
7165 prefix(REX_B);
7166 }
7167 } else {
7168 if (adr.index_needs_rex()) {
7169 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X");
7170 }
7171 }
7172 if (dst->encoding() >= 8) {
7173 p = (Prefix)(p | REX_R);
7174 }
7175 if (p != Prefix_EMPTY) {
7176 // do not generate an empty prefix
7177 prefix(p);
7178 }
7179 }
7180
7181 void Assembler::prefix(Address adr) {
7182 if (adr.base_needs_rex()) {
7183 if (adr.index_needs_rex()) {
7184 prefix(REX_XB);
7185 } else {
7186 prefix(REX_B);
7187 }
7188 } else {
7189 if (adr.index_needs_rex()) {
7190 prefix(REX_X);
7191 }
7192 }
7193 }
7194
7195 void Assembler::prefixq(Address adr) {
7196 if (adr.base_needs_rex()) {
7197 if (adr.index_needs_rex()) {
7198 prefix(REX_WXB);
7199 } else {
7200 prefix(REX_WB);
7201 }
7202 } else {
7203 if (adr.index_needs_rex()) {
7204 prefix(REX_WX);
7205 } else {
7206 prefix(REX_W);
7207 }
7208 }
7209 }
7210
7211
7212 void Assembler::prefix(Address adr, Register reg, bool byteinst) {
7213 if (reg->encoding() < 8) {
7214 if (adr.base_needs_rex()) {
7215 if (adr.index_needs_rex()) {
7216 prefix(REX_XB);
7217 } else {
7218 prefix(REX_B);
7219 }
7220 } else {
7221 if (adr.index_needs_rex()) {
7222 prefix(REX_X);
7223 } else if (byteinst && reg->encoding() >= 4 ) {
7224 prefix(REX);
7225 }
7226 }
7227 } else {
7228 if (adr.base_needs_rex()) {
7229 if (adr.index_needs_rex()) {
7230 prefix(REX_RXB);
7231 } else {
7232 prefix(REX_RB);
7233 }
7234 } else {
7235 if (adr.index_needs_rex()) {
7236 prefix(REX_RX);
7237 } else {
7238 prefix(REX_R);
7239 }
7240 }
7241 }
7242 }
7243
7244 void Assembler::prefixq(Address adr, Register src) {
7245 if (src->encoding() < 8) {
7246 if (adr.base_needs_rex()) {
7247 if (adr.index_needs_rex()) {
7248 prefix(REX_WXB);
7249 } else {
7250 prefix(REX_WB);
7251 }
7252 } else {
7253 if (adr.index_needs_rex()) {
7254 prefix(REX_WX);
7255 } else {
7256 prefix(REX_W);
7257 }
7258 }
7259 } else {
7260 if (adr.base_needs_rex()) {
7261 if (adr.index_needs_rex()) {
7262 prefix(REX_WRXB);
7263 } else {
7264 prefix(REX_WRB);
7265 }
7266 } else {
7267 if (adr.index_needs_rex()) {
7268 prefix(REX_WRX);
7269 } else {
7270 prefix(REX_WR);
7271 }
7272 }
7273 }
7274 }
7275
7276 void Assembler::prefix(Address adr, XMMRegister reg) {
7277 if (reg->encoding() < 8) {
7278 if (adr.base_needs_rex()) {
7279 if (adr.index_needs_rex()) {
7280 prefix(REX_XB);
7281 } else {
7282 prefix(REX_B);
7283 }
7284 } else {
7285 if (adr.index_needs_rex()) {
7286 prefix(REX_X);
7287 }
7288 }
7289 } else {
7290 if (adr.base_needs_rex()) {
7291 if (adr.index_needs_rex()) {
7292 prefix(REX_RXB);
7293 } else {
7294 prefix(REX_RB);
7295 }
7296 } else {
7297 if (adr.index_needs_rex()) {
7298 prefix(REX_RX);
7299 } else {
7300 prefix(REX_R);
7301 }
7302 }
7303 }
7304 }
7305
7306 void Assembler::prefixq(Address adr, XMMRegister src) {
7307 if (src->encoding() < 8) {
7308 if (adr.base_needs_rex()) {
7309 if (adr.index_needs_rex()) {
7310 prefix(REX_WXB);
7311 } else {
7312 prefix(REX_WB);
7313 }
7314 } else {
7315 if (adr.index_needs_rex()) {
7316 prefix(REX_WX);
7317 } else {
7318 prefix(REX_W);
7319 }
7320 }
7321 } else {
7322 if (adr.base_needs_rex()) {
7323 if (adr.index_needs_rex()) {
7324 prefix(REX_WRXB);
7325 } else {
7326 prefix(REX_WRB);
7327 }
7328 } else {
7329 if (adr.index_needs_rex()) {
7330 prefix(REX_WRX);
7331 } else {
7332 prefix(REX_WR);
7333 }
7334 }
7335 }
7336 }
7337
7338 void Assembler::adcq(Register dst, int32_t imm32) {
7339 (void) prefixq_and_encode(dst->encoding());
7340 emit_arith(0x81, 0xD0, dst, imm32);
7341 }
7342
7343 void Assembler::adcq(Register dst, Address src) {
7344 InstructionMark im(this);
7345 prefixq(src, dst);
7346 emit_int8(0x13);
7347 emit_operand(dst, src);
7348 }
7349
7350 void Assembler::adcq(Register dst, Register src) {
7351 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7352 emit_arith(0x13, 0xC0, dst, src);
7353 }
7354
7355 void Assembler::addq(Address dst, int32_t imm32) {
7356 InstructionMark im(this);
7357 prefixq(dst);
7358 emit_arith_operand(0x81, rax, dst,imm32);
7359 }
7360
7361 void Assembler::addq(Address dst, Register src) {
7362 InstructionMark im(this);
7363 prefixq(dst, src);
7364 emit_int8(0x01);
7365 emit_operand(src, dst);
7366 }
7367
7368 void Assembler::addq(Register dst, int32_t imm32) {
7369 (void) prefixq_and_encode(dst->encoding());
7370 emit_arith(0x81, 0xC0, dst, imm32);
7371 }
7372
7373 void Assembler::addq(Register dst, Address src) {
7374 InstructionMark im(this);
7375 prefixq(src, dst);
7376 emit_int8(0x03);
7377 emit_operand(dst, src);
7378 }
7379
7380 void Assembler::addq(Register dst, Register src) {
7381 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7382 emit_arith(0x03, 0xC0, dst, src);
7383 }
7384
7385 void Assembler::adcxq(Register dst, Register src) {
7386 //assert(VM_Version::supports_adx(), "adx instructions not supported");
7387 emit_int8((unsigned char)0x66);
7388 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7389 emit_int8(0x0F);
7390 emit_int8(0x38);
7391 emit_int8((unsigned char)0xF6);
7392 emit_int8((unsigned char)(0xC0 | encode));
7393 }
7394
7395 void Assembler::adoxq(Register dst, Register src) {
7396 //assert(VM_Version::supports_adx(), "adx instructions not supported");
7397 emit_int8((unsigned char)0xF3);
7398 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7399 emit_int8(0x0F);
7400 emit_int8(0x38);
7401 emit_int8((unsigned char)0xF6);
7402 emit_int8((unsigned char)(0xC0 | encode));
7403 }
7404
7405 void Assembler::andq(Address dst, int32_t imm32) {
7406 InstructionMark im(this);
7407 prefixq(dst);
7408 emit_int8((unsigned char)0x81);
7409 emit_operand(rsp, dst, 4);
7410 emit_int32(imm32);
7411 }
7412
7413 void Assembler::andq(Register dst, int32_t imm32) {
7414 (void) prefixq_and_encode(dst->encoding());
7415 emit_arith(0x81, 0xE0, dst, imm32);
7416 }
7417
7418 void Assembler::andq(Register dst, Address src) {
7419 InstructionMark im(this);
7420 prefixq(src, dst);
7421 emit_int8(0x23);
7422 emit_operand(dst, src);
7423 }
7424
7425 void Assembler::andq(Register dst, Register src) {
7426 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7427 emit_arith(0x23, 0xC0, dst, src);
7428 }
7429
7430 void Assembler::andnq(Register dst, Register src1, Register src2) {
7431 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7432 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7433 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7434 emit_int8((unsigned char)0xF2);
7435 emit_int8((unsigned char)(0xC0 | encode));
7436 }
7437
7438 void Assembler::andnq(Register dst, Register src1, Address src2) {
7439 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7440 InstructionMark im(this);
7441 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7442 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7443 emit_int8((unsigned char)0xF2);
7444 emit_operand(dst, src2);
7445 }
7446
7447 void Assembler::bsfq(Register dst, Register src) {
7448 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7449 emit_int8(0x0F);
7450 emit_int8((unsigned char)0xBC);
7451 emit_int8((unsigned char)(0xC0 | encode));
7452 }
7453
7454 void Assembler::bsrq(Register dst, Register src) {
7455 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7456 emit_int8(0x0F);
7457 emit_int8((unsigned char)0xBD);
7458 emit_int8((unsigned char)(0xC0 | encode));
7459 }
7460
7461 void Assembler::bswapq(Register reg) {
7462 int encode = prefixq_and_encode(reg->encoding());
7463 emit_int8(0x0F);
7464 emit_int8((unsigned char)(0xC8 | encode));
7465 }
7466
7467 void Assembler::blsiq(Register dst, Register src) {
7468 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7469 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7470 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7471 emit_int8((unsigned char)0xF3);
7472 emit_int8((unsigned char)(0xC0 | encode));
7473 }
7474
7475 void Assembler::blsiq(Register dst, Address src) {
7476 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7477 InstructionMark im(this);
7478 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7479 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7480 emit_int8((unsigned char)0xF3);
7481 emit_operand(rbx, src);
7482 }
7483
7484 void Assembler::blsmskq(Register dst, Register src) {
7485 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7486 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7487 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7488 emit_int8((unsigned char)0xF3);
7489 emit_int8((unsigned char)(0xC0 | encode));
7490 }
7491
7492 void Assembler::blsmskq(Register dst, Address src) {
7493 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7494 InstructionMark im(this);
7495 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7496 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7497 emit_int8((unsigned char)0xF3);
7498 emit_operand(rdx, src);
7499 }
7500
7501 void Assembler::blsrq(Register dst, Register src) {
7502 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7503 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7504 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7505 emit_int8((unsigned char)0xF3);
7506 emit_int8((unsigned char)(0xC0 | encode));
7507 }
7508
7509 void Assembler::blsrq(Register dst, Address src) {
7510 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7511 InstructionMark im(this);
7512 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7513 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7514 emit_int8((unsigned char)0xF3);
7515 emit_operand(rcx, src);
7516 }
7517
7518 void Assembler::cdqq() {
7519 prefix(REX_W);
7520 emit_int8((unsigned char)0x99);
7521 }
7522
7523 void Assembler::clflush(Address adr) {
7524 prefix(adr);
7525 emit_int8(0x0F);
7526 emit_int8((unsigned char)0xAE);
7527 emit_operand(rdi, adr);
7528 }
7529
7530 void Assembler::cmovq(Condition cc, Register dst, Register src) {
7531 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7532 emit_int8(0x0F);
7533 emit_int8(0x40 | cc);
7534 emit_int8((unsigned char)(0xC0 | encode));
7535 }
7536
7537 void Assembler::cmovq(Condition cc, Register dst, Address src) {
7538 InstructionMark im(this);
7539 prefixq(src, dst);
7540 emit_int8(0x0F);
7541 emit_int8(0x40 | cc);
7542 emit_operand(dst, src);
7543 }
7544
7545 void Assembler::cmpq(Address dst, int32_t imm32) {
7546 InstructionMark im(this);
7547 prefixq(dst);
7548 emit_int8((unsigned char)0x81);
7549 emit_operand(rdi, dst, 4);
7550 emit_int32(imm32);
7551 }
7552
7553 void Assembler::cmpq(Register dst, int32_t imm32) {
7554 (void) prefixq_and_encode(dst->encoding());
7555 emit_arith(0x81, 0xF8, dst, imm32);
7556 }
7557
7558 void Assembler::cmpq(Address dst, Register src) {
7559 InstructionMark im(this);
7560 prefixq(dst, src);
7561 emit_int8(0x3B);
7562 emit_operand(src, dst);
7563 }
7564
7565 void Assembler::cmpq(Register dst, Register src) {
7566 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7567 emit_arith(0x3B, 0xC0, dst, src);
7568 }
7569
7570 void Assembler::cmpq(Register dst, Address src) {
7571 InstructionMark im(this);
7572 prefixq(src, dst);
7573 emit_int8(0x3B);
7574 emit_operand(dst, src);
7575 }
7576
7577 void Assembler::cmpxchgq(Register reg, Address adr) {
7578 InstructionMark im(this);
7579 prefixq(adr, reg);
7580 emit_int8(0x0F);
7581 emit_int8((unsigned char)0xB1);
7582 emit_operand(reg, adr);
7583 }
7584
7585 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
7586 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7587 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7588 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
7589 emit_int8(0x2A);
7590 emit_int8((unsigned char)(0xC0 | encode));
7591 }
7592
7593 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) {
7594 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7595 InstructionMark im(this);
7596 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7597 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
7598 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
7599 emit_int8(0x2A);
7600 emit_operand(dst, src);
7601 }
7602
7603 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) {
7604 NOT_LP64(assert(VM_Version::supports_sse(), ""));
7605 InstructionMark im(this);
7606 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7607 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
7608 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
7609 emit_int8(0x2A);
7610 emit_operand(dst, src);
7611 }
7612
7613 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
7614 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7615 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7616 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
7617 emit_int8(0x2C);
7618 emit_int8((unsigned char)(0xC0 | encode));
7619 }
7620
7621 void Assembler::cvttss2siq(Register dst, XMMRegister src) {
7622 NOT_LP64(assert(VM_Version::supports_sse(), ""));
7623 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7624 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
7625 emit_int8(0x2C);
7626 emit_int8((unsigned char)(0xC0 | encode));
7627 }
7628
7629 void Assembler::decl(Register dst) {
7630 // Don't use it directly. Use MacroAssembler::decrementl() instead.
7631 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
7632 int encode = prefix_and_encode(dst->encoding());
7633 emit_int8((unsigned char)0xFF);
7634 emit_int8((unsigned char)(0xC8 | encode));
7635 }
7636
7637 void Assembler::decq(Register dst) {
7638 // Don't use it directly. Use MacroAssembler::decrementq() instead.
7639 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
7640 int encode = prefixq_and_encode(dst->encoding());
7641 emit_int8((unsigned char)0xFF);
7642 emit_int8(0xC8 | encode);
7643 }
7644
7645 void Assembler::decq(Address dst) {
7646 // Don't use it directly. Use MacroAssembler::decrementq() instead.
7647 InstructionMark im(this);
7648 prefixq(dst);
7649 emit_int8((unsigned char)0xFF);
7650 emit_operand(rcx, dst);
7651 }
7652
7653 void Assembler::fxrstor(Address src) {
7654 prefixq(src);
7655 emit_int8(0x0F);
7656 emit_int8((unsigned char)0xAE);
7657 emit_operand(as_Register(1), src);
7658 }
7659
7660 void Assembler::xrstor(Address src) {
7661 prefixq(src);
7662 emit_int8(0x0F);
7663 emit_int8((unsigned char)0xAE);
7664 emit_operand(as_Register(5), src);
7665 }
7666
7667 void Assembler::fxsave(Address dst) {
7668 prefixq(dst);
7669 emit_int8(0x0F);
7670 emit_int8((unsigned char)0xAE);
7671 emit_operand(as_Register(0), dst);
7672 }
7673
7674 void Assembler::xsave(Address dst) {
7675 prefixq(dst);
7676 emit_int8(0x0F);
7677 emit_int8((unsigned char)0xAE);
7678 emit_operand(as_Register(4), dst);
7679 }
7680
7681 void Assembler::idivq(Register src) {
7682 int encode = prefixq_and_encode(src->encoding());
7683 emit_int8((unsigned char)0xF7);
7684 emit_int8((unsigned char)(0xF8 | encode));
7685 }
7686
7687 void Assembler::imulq(Register dst, Register src) {
7688 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7689 emit_int8(0x0F);
7690 emit_int8((unsigned char)0xAF);
7691 emit_int8((unsigned char)(0xC0 | encode));
7692 }
7693
7694 void Assembler::imulq(Register dst, Register src, int value) {
7695 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7696 if (is8bit(value)) {
7697 emit_int8(0x6B);
7698 emit_int8((unsigned char)(0xC0 | encode));
7699 emit_int8(value & 0xFF);
7700 } else {
7701 emit_int8(0x69);
7702 emit_int8((unsigned char)(0xC0 | encode));
7703 emit_int32(value);
7704 }
7705 }
7706
7707 void Assembler::imulq(Register dst, Address src) {
7708 InstructionMark im(this);
7709 prefixq(src, dst);
7710 emit_int8(0x0F);
7711 emit_int8((unsigned char) 0xAF);
7712 emit_operand(dst, src);
7713 }
7714
7715 void Assembler::incl(Register dst) {
7716 // Don't use it directly. Use MacroAssembler::incrementl() instead.
7717 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
7718 int encode = prefix_and_encode(dst->encoding());
7719 emit_int8((unsigned char)0xFF);
7720 emit_int8((unsigned char)(0xC0 | encode));
7721 }
7722
7723 void Assembler::incq(Register dst) {
7724 // Don't use it directly. Use MacroAssembler::incrementq() instead.
7725 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
7726 int encode = prefixq_and_encode(dst->encoding());
7727 emit_int8((unsigned char)0xFF);
7728 emit_int8((unsigned char)(0xC0 | encode));
7729 }
7730
7731 void Assembler::incq(Address dst) {
7732 // Don't use it directly. Use MacroAssembler::incrementq() instead.
7733 InstructionMark im(this);
7734 prefixq(dst);
7735 emit_int8((unsigned char)0xFF);
7736 emit_operand(rax, dst);
7737 }
7738
7739 void Assembler::lea(Register dst, Address src) {
7740 leaq(dst, src);
7741 }
7742
7743 void Assembler::leaq(Register dst, Address src) {
7744 InstructionMark im(this);
7745 prefixq(src, dst);
7746 emit_int8((unsigned char)0x8D);
7747 emit_operand(dst, src);
7748 }
7749
7750 void Assembler::mov64(Register dst, int64_t imm64) {
7751 InstructionMark im(this);
7752 int encode = prefixq_and_encode(dst->encoding());
7753 emit_int8((unsigned char)(0xB8 | encode));
7754 emit_int64(imm64);
7755 }
7756
7757 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) {
7758 InstructionMark im(this);
7759 int encode = prefixq_and_encode(dst->encoding());
7760 emit_int8(0xB8 | encode);
7761 emit_data64(imm64, rspec);
7762 }
7763
7764 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) {
7765 InstructionMark im(this);
7766 int encode = prefix_and_encode(dst->encoding());
7767 emit_int8((unsigned char)(0xB8 | encode));
7768 emit_data((int)imm32, rspec, narrow_oop_operand);
7769 }
7770
7771 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) {
7772 InstructionMark im(this);
7773 prefix(dst);
7774 emit_int8((unsigned char)0xC7);
7775 emit_operand(rax, dst, 4);
7776 emit_data((int)imm32, rspec, narrow_oop_operand);
7777 }
7778
7779 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) {
7780 InstructionMark im(this);
7781 int encode = prefix_and_encode(src1->encoding());
7782 emit_int8((unsigned char)0x81);
7783 emit_int8((unsigned char)(0xF8 | encode));
7784 emit_data((int)imm32, rspec, narrow_oop_operand);
7785 }
7786
7787 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) {
7788 InstructionMark im(this);
7789 prefix(src1);
7790 emit_int8((unsigned char)0x81);
7791 emit_operand(rax, src1, 4);
7792 emit_data((int)imm32, rspec, narrow_oop_operand);
7793 }
7794
7795 void Assembler::lzcntq(Register dst, Register src) {
7796 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
7797 emit_int8((unsigned char)0xF3);
7798 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7799 emit_int8(0x0F);
7800 emit_int8((unsigned char)0xBD);
7801 emit_int8((unsigned char)(0xC0 | encode));
7802 }
7803
7804 void Assembler::movdq(XMMRegister dst, Register src) {
7805 // table D-1 says MMX/SSE2
7806 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7807 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7808 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7809 emit_int8(0x6E);
7810 emit_int8((unsigned char)(0xC0 | encode));
7811 }
7812
7813 void Assembler::movdq(Register dst, XMMRegister src) {
7814 // table D-1 says MMX/SSE2
7815 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7816 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7817 // swap src/dst to get correct prefix
7818 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7819 emit_int8(0x7E);
7820 emit_int8((unsigned char)(0xC0 | encode));
7821 }
7822
7823 void Assembler::movq(Register dst, Register src) {
7824 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7825 emit_int8((unsigned char)0x8B);
7826 emit_int8((unsigned char)(0xC0 | encode));
7827 }
7828
7829 void Assembler::movq(Register dst, Address src) {
7830 InstructionMark im(this);
7831 prefixq(src, dst);
7832 emit_int8((unsigned char)0x8B);
7833 emit_operand(dst, src);
7834 }
7835
7836 void Assembler::movq(Address dst, Register src) {
7837 InstructionMark im(this);
7838 prefixq(dst, src);
7839 emit_int8((unsigned char)0x89);
7840 emit_operand(src, dst);
7841 }
7842
7843 void Assembler::movsbq(Register dst, Address src) {
7844 InstructionMark im(this);
7845 prefixq(src, dst);
7846 emit_int8(0x0F);
7847 emit_int8((unsigned char)0xBE);
7848 emit_operand(dst, src);
7849 }
7850
7851 void Assembler::movsbq(Register dst, Register src) {
7852 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7853 emit_int8(0x0F);
7854 emit_int8((unsigned char)0xBE);
7855 emit_int8((unsigned char)(0xC0 | encode));
7856 }
7857
7858 void Assembler::movslq(Register dst, int32_t imm32) {
7859 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx)
7860 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx)
7861 // as a result we shouldn't use until tested at runtime...
7862 ShouldNotReachHere();
7863 InstructionMark im(this);
7864 int encode = prefixq_and_encode(dst->encoding());
7865 emit_int8((unsigned char)(0xC7 | encode));
7866 emit_int32(imm32);
7867 }
7868
7869 void Assembler::movslq(Address dst, int32_t imm32) {
7870 assert(is_simm32(imm32), "lost bits");
7871 InstructionMark im(this);
7872 prefixq(dst);
7873 emit_int8((unsigned char)0xC7);
7874 emit_operand(rax, dst, 4);
7875 emit_int32(imm32);
7876 }
7877
7878 void Assembler::movslq(Register dst, Address src) {
7879 InstructionMark im(this);
7880 prefixq(src, dst);
7881 emit_int8(0x63);
7882 emit_operand(dst, src);
7883 }
7884
7885 void Assembler::movslq(Register dst, Register src) {
7886 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7887 emit_int8(0x63);
7888 emit_int8((unsigned char)(0xC0 | encode));
7889 }
7890
7891 void Assembler::movswq(Register dst, Address src) {
7892 InstructionMark im(this);
7893 prefixq(src, dst);
7894 emit_int8(0x0F);
7895 emit_int8((unsigned char)0xBF);
7896 emit_operand(dst, src);
7897 }
7898
7899 void Assembler::movswq(Register dst, Register src) {
7900 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7901 emit_int8((unsigned char)0x0F);
7902 emit_int8((unsigned char)0xBF);
7903 emit_int8((unsigned char)(0xC0 | encode));
7904 }
7905
7906 void Assembler::movzbq(Register dst, Address src) {
7907 InstructionMark im(this);
7908 prefixq(src, dst);
7909 emit_int8((unsigned char)0x0F);
7910 emit_int8((unsigned char)0xB6);
7911 emit_operand(dst, src);
7912 }
7913
7914 void Assembler::movzbq(Register dst, Register src) {
7915 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7916 emit_int8(0x0F);
7917 emit_int8((unsigned char)0xB6);
7918 emit_int8(0xC0 | encode);
7919 }
7920
7921 void Assembler::movzwq(Register dst, Address src) {
7922 InstructionMark im(this);
7923 prefixq(src, dst);
7924 emit_int8((unsigned char)0x0F);
7925 emit_int8((unsigned char)0xB7);
7926 emit_operand(dst, src);
7927 }
7928
7929 void Assembler::movzwq(Register dst, Register src) {
7930 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7931 emit_int8((unsigned char)0x0F);
7932 emit_int8((unsigned char)0xB7);
7933 emit_int8((unsigned char)(0xC0 | encode));
7934 }
7935
7936 void Assembler::mulq(Address src) {
7937 InstructionMark im(this);
7938 prefixq(src);
7939 emit_int8((unsigned char)0xF7);
7940 emit_operand(rsp, src);
7941 }
7942
7943 void Assembler::mulq(Register src) {
7944 int encode = prefixq_and_encode(src->encoding());
7945 emit_int8((unsigned char)0xF7);
7946 emit_int8((unsigned char)(0xE0 | encode));
7947 }
7948
7949 void Assembler::mulxq(Register dst1, Register dst2, Register src) {
7950 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
7951 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7952 int encode = vex_prefix_and_encode(dst1->encoding(), dst2->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
7953 emit_int8((unsigned char)0xF6);
7954 emit_int8((unsigned char)(0xC0 | encode));
7955 }
7956
7957 void Assembler::negq(Register dst) {
7958 int encode = prefixq_and_encode(dst->encoding());
7959 emit_int8((unsigned char)0xF7);
7960 emit_int8((unsigned char)(0xD8 | encode));
7961 }
7962
7963 void Assembler::notq(Register dst) {
7964 int encode = prefixq_and_encode(dst->encoding());
7965 emit_int8((unsigned char)0xF7);
7966 emit_int8((unsigned char)(0xD0 | encode));
7967 }
7968
7969 void Assembler::orq(Address dst, int32_t imm32) {
7970 InstructionMark im(this);
7971 prefixq(dst);
7972 emit_int8((unsigned char)0x81);
7973 emit_operand(rcx, dst, 4);
7974 emit_int32(imm32);
7975 }
7976
7977 void Assembler::orq(Register dst, int32_t imm32) {
7978 (void) prefixq_and_encode(dst->encoding());
7979 emit_arith(0x81, 0xC8, dst, imm32);
7980 }
7981
7982 void Assembler::orq(Register dst, Address src) {
7983 InstructionMark im(this);
7984 prefixq(src, dst);
7985 emit_int8(0x0B);
7986 emit_operand(dst, src);
7987 }
7988
7989 void Assembler::orq(Register dst, Register src) {
7990 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7991 emit_arith(0x0B, 0xC0, dst, src);
7992 }
7993
7994 void Assembler::popa() { // 64bit
7995 movq(r15, Address(rsp, 0));
7996 movq(r14, Address(rsp, wordSize));
7997 movq(r13, Address(rsp, 2 * wordSize));
7998 movq(r12, Address(rsp, 3 * wordSize));
7999 movq(r11, Address(rsp, 4 * wordSize));
8000 movq(r10, Address(rsp, 5 * wordSize));
8001 movq(r9, Address(rsp, 6 * wordSize));
8002 movq(r8, Address(rsp, 7 * wordSize));
8003 movq(rdi, Address(rsp, 8 * wordSize));
8004 movq(rsi, Address(rsp, 9 * wordSize));
8005 movq(rbp, Address(rsp, 10 * wordSize));
8006 // skip rsp
8007 movq(rbx, Address(rsp, 12 * wordSize));
8008 movq(rdx, Address(rsp, 13 * wordSize));
8009 movq(rcx, Address(rsp, 14 * wordSize));
8010 movq(rax, Address(rsp, 15 * wordSize));
8011
8012 addq(rsp, 16 * wordSize);
8013 }
8014
8015 void Assembler::popcntq(Register dst, Address src) {
8016 assert(VM_Version::supports_popcnt(), "must support");
8017 InstructionMark im(this);
8018 emit_int8((unsigned char)0xF3);
8019 prefixq(src, dst);
8020 emit_int8((unsigned char)0x0F);
8021 emit_int8((unsigned char)0xB8);
8022 emit_operand(dst, src);
8023 }
8024
8025 void Assembler::popcntq(Register dst, Register src) {
8026 assert(VM_Version::supports_popcnt(), "must support");
8027 emit_int8((unsigned char)0xF3);
8028 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8029 emit_int8((unsigned char)0x0F);
8030 emit_int8((unsigned char)0xB8);
8031 emit_int8((unsigned char)(0xC0 | encode));
8032 }
8033
8034 void Assembler::popq(Address dst) {
8035 InstructionMark im(this);
8036 prefixq(dst);
8037 emit_int8((unsigned char)0x8F);
8038 emit_operand(rax, dst);
8039 }
8040
8041 void Assembler::pusha() { // 64bit
8042 // we have to store original rsp. ABI says that 128 bytes
8043 // below rsp are local scratch.
8044 movq(Address(rsp, -5 * wordSize), rsp);
8045
8046 subq(rsp, 16 * wordSize);
8047
8048 movq(Address(rsp, 15 * wordSize), rax);
8049 movq(Address(rsp, 14 * wordSize), rcx);
8050 movq(Address(rsp, 13 * wordSize), rdx);
8051 movq(Address(rsp, 12 * wordSize), rbx);
8052 // skip rsp
8053 movq(Address(rsp, 10 * wordSize), rbp);
8054 movq(Address(rsp, 9 * wordSize), rsi);
8055 movq(Address(rsp, 8 * wordSize), rdi);
8056 movq(Address(rsp, 7 * wordSize), r8);
8057 movq(Address(rsp, 6 * wordSize), r9);
8058 movq(Address(rsp, 5 * wordSize), r10);
8059 movq(Address(rsp, 4 * wordSize), r11);
8060 movq(Address(rsp, 3 * wordSize), r12);
8061 movq(Address(rsp, 2 * wordSize), r13);
8062 movq(Address(rsp, wordSize), r14);
8063 movq(Address(rsp, 0), r15);
8064 }
8065
8066 void Assembler::pushq(Address src) {
8067 InstructionMark im(this);
8068 prefixq(src);
8069 emit_int8((unsigned char)0xFF);
8070 emit_operand(rsi, src);
8071 }
8072
8073 void Assembler::rclq(Register dst, int imm8) {
8074 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8075 int encode = prefixq_and_encode(dst->encoding());
8076 if (imm8 == 1) {
8077 emit_int8((unsigned char)0xD1);
8078 emit_int8((unsigned char)(0xD0 | encode));
8079 } else {
8080 emit_int8((unsigned char)0xC1);
8081 emit_int8((unsigned char)(0xD0 | encode));
8082 emit_int8(imm8);
8083 }
8084 }
8085
8086 void Assembler::rcrq(Register dst, int imm8) {
8087 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8088 int encode = prefixq_and_encode(dst->encoding());
8089 if (imm8 == 1) {
8090 emit_int8((unsigned char)0xD1);
8091 emit_int8((unsigned char)(0xD8 | encode));
8092 } else {
8093 emit_int8((unsigned char)0xC1);
8094 emit_int8((unsigned char)(0xD8 | encode));
8095 emit_int8(imm8);
8096 }
8097 }
8098
8099 void Assembler::rorq(Register dst, int imm8) {
8100 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8101 int encode = prefixq_and_encode(dst->encoding());
8102 if (imm8 == 1) {
8103 emit_int8((unsigned char)0xD1);
8104 emit_int8((unsigned char)(0xC8 | encode));
8105 } else {
8106 emit_int8((unsigned char)0xC1);
8107 emit_int8((unsigned char)(0xc8 | encode));
8108 emit_int8(imm8);
8109 }
8110 }
8111
8112 void Assembler::rorxq(Register dst, Register src, int imm8) {
8113 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
8114 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
8115 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes);
8116 emit_int8((unsigned char)0xF0);
8117 emit_int8((unsigned char)(0xC0 | encode));
8118 emit_int8(imm8);
8119 }
8120
8121 void Assembler::sarq(Register dst, int imm8) {
8122 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8123 int encode = prefixq_and_encode(dst->encoding());
8124 if (imm8 == 1) {
8125 emit_int8((unsigned char)0xD1);
8126 emit_int8((unsigned char)(0xF8 | encode));
8127 } else {
8128 emit_int8((unsigned char)0xC1);
8129 emit_int8((unsigned char)(0xF8 | encode));
8130 emit_int8(imm8);
8131 }
8132 }
8133
8134 void Assembler::sarq(Register dst) {
8135 int encode = prefixq_and_encode(dst->encoding());
8136 emit_int8((unsigned char)0xD3);
8137 emit_int8((unsigned char)(0xF8 | encode));
8138 }
8139
8140 void Assembler::sbbq(Address dst, int32_t imm32) {
8141 InstructionMark im(this);
8142 prefixq(dst);
8143 emit_arith_operand(0x81, rbx, dst, imm32);
8144 }
8145
8146 void Assembler::sbbq(Register dst, int32_t imm32) {
8147 (void) prefixq_and_encode(dst->encoding());
8148 emit_arith(0x81, 0xD8, dst, imm32);
8149 }
8150
8151 void Assembler::sbbq(Register dst, Address src) {
8152 InstructionMark im(this);
8153 prefixq(src, dst);
8154 emit_int8(0x1B);
8155 emit_operand(dst, src);
8156 }
8157
8158 void Assembler::sbbq(Register dst, Register src) {
8159 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8160 emit_arith(0x1B, 0xC0, dst, src);
8161 }
8162
8163 void Assembler::shlq(Register dst, int imm8) {
8164 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8165 int encode = prefixq_and_encode(dst->encoding());
8166 if (imm8 == 1) {
8167 emit_int8((unsigned char)0xD1);
8168 emit_int8((unsigned char)(0xE0 | encode));
8169 } else {
8170 emit_int8((unsigned char)0xC1);
8171 emit_int8((unsigned char)(0xE0 | encode));
8172 emit_int8(imm8);
8173 }
8174 }
8175
8176 void Assembler::shlq(Register dst) {
8177 int encode = prefixq_and_encode(dst->encoding());
8178 emit_int8((unsigned char)0xD3);
8179 emit_int8((unsigned char)(0xE0 | encode));
8180 }
8181
8182 void Assembler::shrq(Register dst, int imm8) {
8183 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8184 int encode = prefixq_and_encode(dst->encoding());
8185 emit_int8((unsigned char)0xC1);
8186 emit_int8((unsigned char)(0xE8 | encode));
8187 emit_int8(imm8);
8188 }
8189
8190 void Assembler::shrq(Register dst) {
8191 int encode = prefixq_and_encode(dst->encoding());
8192 emit_int8((unsigned char)0xD3);
8193 emit_int8(0xE8 | encode);
8194 }
8195
8196 void Assembler::subq(Address dst, int32_t imm32) {
8197 InstructionMark im(this);
8198 prefixq(dst);
8199 emit_arith_operand(0x81, rbp, dst, imm32);
8200 }
8201
8202 void Assembler::subq(Address dst, Register src) {
8203 InstructionMark im(this);
8204 prefixq(dst, src);
8205 emit_int8(0x29);
8206 emit_operand(src, dst);
8207 }
8208
8209 void Assembler::subq(Register dst, int32_t imm32) {
8210 (void) prefixq_and_encode(dst->encoding());
8211 emit_arith(0x81, 0xE8, dst, imm32);
8212 }
8213
8214 // Force generation of a 4 byte immediate value even if it fits into 8bit
8215 void Assembler::subq_imm32(Register dst, int32_t imm32) {
8216 (void) prefixq_and_encode(dst->encoding());
8217 emit_arith_imm32(0x81, 0xE8, dst, imm32);
8218 }
8219
8220 void Assembler::subq(Register dst, Address src) {
8221 InstructionMark im(this);
8222 prefixq(src, dst);
8223 emit_int8(0x2B);
8224 emit_operand(dst, src);
8225 }
8226
8227 void Assembler::subq(Register dst, Register src) {
8228 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8229 emit_arith(0x2B, 0xC0, dst, src);
8230 }
8231
8232 void Assembler::testq(Register dst, int32_t imm32) {
8233 // not using emit_arith because test
8234 // doesn't support sign-extension of
8235 // 8bit operands
8236 int encode = dst->encoding();
8237 if (encode == 0) {
8238 prefix(REX_W);
8239 emit_int8((unsigned char)0xA9);
8240 } else {
8241 encode = prefixq_and_encode(encode);
8242 emit_int8((unsigned char)0xF7);
8243 emit_int8((unsigned char)(0xC0 | encode));
8244 }
8245 emit_int32(imm32);
8246 }
8247
8248 void Assembler::testq(Register dst, Register src) {
8249 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8250 emit_arith(0x85, 0xC0, dst, src);
8251 }
8252
8253 void Assembler::xaddq(Address dst, Register src) {
8254 InstructionMark im(this);
8255 prefixq(dst, src);
8256 emit_int8(0x0F);
8257 emit_int8((unsigned char)0xC1);
8258 emit_operand(src, dst);
8259 }
8260
8261 void Assembler::xchgq(Register dst, Address src) {
8262 InstructionMark im(this);
8263 prefixq(src, dst);
8264 emit_int8((unsigned char)0x87);
8265 emit_operand(dst, src);
8266 }
8267
8268 void Assembler::xchgq(Register dst, Register src) {
8269 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8270 emit_int8((unsigned char)0x87);
8271 emit_int8((unsigned char)(0xc0 | encode));
8272 }
8273
8274 void Assembler::xorq(Register dst, Register src) {
8275 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8276 emit_arith(0x33, 0xC0, dst, src);
8277 }
8278
8279 void Assembler::xorq(Register dst, Address src) {
8280 InstructionMark im(this);
8281 prefixq(src, dst);
8282 emit_int8(0x33);
8283 emit_operand(dst, src);
8284 }
8285
8286 #endif // !LP64