1 /*
   2  * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "asm/assembler.hpp"
  27 #include "asm/assembler.inline.hpp"
  28 #include "gc/shared/cardTableModRefBS.hpp"
  29 #include "gc/shared/collectedHeap.inline.hpp"
  30 #include "interpreter/interpreter.hpp"
  31 #include "memory/resourceArea.hpp"
  32 #include "prims/methodHandles.hpp"
  33 #include "runtime/biasedLocking.hpp"
  34 #include "runtime/interfaceSupport.hpp"
  35 #include "runtime/objectMonitor.hpp"
  36 #include "runtime/os.hpp"
  37 #include "runtime/sharedRuntime.hpp"
  38 #include "runtime/stubRoutines.hpp"
  39 #include "utilities/macros.hpp"
  40 #if INCLUDE_ALL_GCS
  41 #include "gc/g1/g1CollectedHeap.inline.hpp"
  42 #include "gc/g1/g1SATBCardTableModRefBS.hpp"
  43 #include "gc/g1/heapRegion.hpp"
  44 #endif // INCLUDE_ALL_GCS
  45 
  46 #ifdef PRODUCT
  47 #define BLOCK_COMMENT(str) /* nothing */
  48 #define STOP(error) stop(error)
  49 #else
  50 #define BLOCK_COMMENT(str) block_comment(str)
  51 #define STOP(error) block_comment(error); stop(error)
  52 #endif
  53 
  54 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
  55 // Implementation of AddressLiteral
  56 
  57 // A 2-D table for managing compressed displacement(disp8) on EVEX enabled platforms.
  58 unsigned char tuple_table[Assembler::EVEX_ETUP + 1][Assembler::AVX_512bit + 1] = {
  59   // -----------------Table 4.5 -------------------- //
  60   16, 32, 64,  // EVEX_FV(0)
  61   4,  4,  4,   // EVEX_FV(1) - with Evex.b
  62   16, 32, 64,  // EVEX_FV(2) - with Evex.w
  63   8,  8,  8,   // EVEX_FV(3) - with Evex.w and Evex.b
  64   8,  16, 32,  // EVEX_HV(0)
  65   4,  4,  4,   // EVEX_HV(1) - with Evex.b
  66   // -----------------Table 4.6 -------------------- //
  67   16, 32, 64,  // EVEX_FVM(0)
  68   1,  1,  1,   // EVEX_T1S(0)
  69   2,  2,  2,   // EVEX_T1S(1)
  70   4,  4,  4,   // EVEX_T1S(2)
  71   8,  8,  8,   // EVEX_T1S(3)
  72   4,  4,  4,   // EVEX_T1F(0)
  73   8,  8,  8,   // EVEX_T1F(1)
  74   8,  8,  8,   // EVEX_T2(0)
  75   0,  16, 16,  // EVEX_T2(1)
  76   0,  16, 16,  // EVEX_T4(0)
  77   0,  0,  32,  // EVEX_T4(1)
  78   0,  0,  32,  // EVEX_T8(0)
  79   8,  16, 32,  // EVEX_HVM(0)
  80   4,  8,  16,  // EVEX_QVM(0)
  81   2,  4,  8,   // EVEX_OVM(0)
  82   16, 16, 16,  // EVEX_M128(0)
  83   8,  32, 64,  // EVEX_DUP(0)
  84   0,  0,  0    // EVEX_NTUP
  85 };
  86 
  87 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
  88   _is_lval = false;
  89   _target = target;
  90   switch (rtype) {
  91   case relocInfo::oop_type:
  92   case relocInfo::metadata_type:
  93     // Oops are a special case. Normally they would be their own section
  94     // but in cases like icBuffer they are literals in the code stream that
  95     // we don't have a section for. We use none so that we get a literal address
  96     // which is always patchable.
  97     break;
  98   case relocInfo::external_word_type:
  99     _rspec = external_word_Relocation::spec(target);
 100     break;
 101   case relocInfo::internal_word_type:
 102     _rspec = internal_word_Relocation::spec(target);
 103     break;
 104   case relocInfo::opt_virtual_call_type:
 105     _rspec = opt_virtual_call_Relocation::spec();
 106     break;
 107   case relocInfo::static_call_type:
 108     _rspec = static_call_Relocation::spec();
 109     break;
 110   case relocInfo::runtime_call_type:
 111     _rspec = runtime_call_Relocation::spec();
 112     break;
 113   case relocInfo::poll_type:
 114   case relocInfo::poll_return_type:
 115     _rspec = Relocation::spec_simple(rtype);
 116     break;
 117   case relocInfo::none:
 118     break;
 119   default:
 120     ShouldNotReachHere();
 121     break;
 122   }
 123 }
 124 
 125 // Implementation of Address
 126 
 127 #ifdef _LP64
 128 
 129 Address Address::make_array(ArrayAddress adr) {
 130   // Not implementable on 64bit machines
 131   // Should have been handled higher up the call chain.
 132   ShouldNotReachHere();
 133   return Address();
 134 }
 135 
 136 // exceedingly dangerous constructor
 137 Address::Address(int disp, address loc, relocInfo::relocType rtype) {
 138   _base  = noreg;
 139   _index = noreg;
 140   _scale = no_scale;
 141   _disp  = disp;
 142   switch (rtype) {
 143     case relocInfo::external_word_type:
 144       _rspec = external_word_Relocation::spec(loc);
 145       break;
 146     case relocInfo::internal_word_type:
 147       _rspec = internal_word_Relocation::spec(loc);
 148       break;
 149     case relocInfo::runtime_call_type:
 150       // HMM
 151       _rspec = runtime_call_Relocation::spec();
 152       break;
 153     case relocInfo::poll_type:
 154     case relocInfo::poll_return_type:
 155       _rspec = Relocation::spec_simple(rtype);
 156       break;
 157     case relocInfo::none:
 158       break;
 159     default:
 160       ShouldNotReachHere();
 161   }
 162 }
 163 #else // LP64
 164 
 165 Address Address::make_array(ArrayAddress adr) {
 166   AddressLiteral base = adr.base();
 167   Address index = adr.index();
 168   assert(index._disp == 0, "must not have disp"); // maybe it can?
 169   Address array(index._base, index._index, index._scale, (intptr_t) base.target());
 170   array._rspec = base._rspec;
 171   return array;
 172 }
 173 
 174 // exceedingly dangerous constructor
 175 Address::Address(address loc, RelocationHolder spec) {
 176   _base  = noreg;
 177   _index = noreg;
 178   _scale = no_scale;
 179   _disp  = (intptr_t) loc;
 180   _rspec = spec;
 181 }
 182 
 183 #endif // _LP64
 184 
 185 
 186 
 187 // Convert the raw encoding form into the form expected by the constructor for
 188 // Address.  An index of 4 (rsp) corresponds to having no index, so convert
 189 // that to noreg for the Address constructor.
 190 Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) {
 191   RelocationHolder rspec;
 192   if (disp_reloc != relocInfo::none) {
 193     rspec = Relocation::spec_simple(disp_reloc);
 194   }
 195   bool valid_index = index != rsp->encoding();
 196   if (valid_index) {
 197     Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));
 198     madr._rspec = rspec;
 199     return madr;
 200   } else {
 201     Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));
 202     madr._rspec = rspec;
 203     return madr;
 204   }
 205 }
 206 
 207 // Implementation of Assembler
 208 
 209 int AbstractAssembler::code_fill_byte() {
 210   return (u_char)'\xF4'; // hlt
 211 }
 212 
 213 // make this go away someday
 214 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) {
 215   if (rtype == relocInfo::none)
 216     emit_int32(data);
 217   else
 218     emit_data(data, Relocation::spec_simple(rtype), format);
 219 }
 220 
 221 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) {
 222   assert(imm_operand == 0, "default format must be immediate in this file");
 223   assert(inst_mark() != NULL, "must be inside InstructionMark");
 224   if (rspec.type() !=  relocInfo::none) {
 225     #ifdef ASSERT
 226       check_relocation(rspec, format);
 227     #endif
 228     // Do not use AbstractAssembler::relocate, which is not intended for
 229     // embedded words.  Instead, relocate to the enclosing instruction.
 230 
 231     // hack. call32 is too wide for mask so use disp32
 232     if (format == call32_operand)
 233       code_section()->relocate(inst_mark(), rspec, disp32_operand);
 234     else
 235       code_section()->relocate(inst_mark(), rspec, format);
 236   }
 237   emit_int32(data);
 238 }
 239 
 240 static int encode(Register r) {
 241   int enc = r->encoding();
 242   if (enc >= 8) {
 243     enc -= 8;
 244   }
 245   return enc;
 246 }
 247 
 248 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
 249   assert(dst->has_byte_register(), "must have byte register");
 250   assert(isByte(op1) && isByte(op2), "wrong opcode");
 251   assert(isByte(imm8), "not a byte");
 252   assert((op1 & 0x01) == 0, "should be 8bit operation");
 253   emit_int8(op1);
 254   emit_int8(op2 | encode(dst));
 255   emit_int8(imm8);
 256 }
 257 
 258 
 259 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) {
 260   assert(isByte(op1) && isByte(op2), "wrong opcode");
 261   assert((op1 & 0x01) == 1, "should be 32bit operation");
 262   assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
 263   if (is8bit(imm32)) {
 264     emit_int8(op1 | 0x02); // set sign bit
 265     emit_int8(op2 | encode(dst));
 266     emit_int8(imm32 & 0xFF);
 267   } else {
 268     emit_int8(op1);
 269     emit_int8(op2 | encode(dst));
 270     emit_int32(imm32);
 271   }
 272 }
 273 
 274 // Force generation of a 4 byte immediate value even if it fits into 8bit
 275 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) {
 276   assert(isByte(op1) && isByte(op2), "wrong opcode");
 277   assert((op1 & 0x01) == 1, "should be 32bit operation");
 278   assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
 279   emit_int8(op1);
 280   emit_int8(op2 | encode(dst));
 281   emit_int32(imm32);
 282 }
 283 
 284 // immediate-to-memory forms
 285 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) {
 286   assert((op1 & 0x01) == 1, "should be 32bit operation");
 287   assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
 288   if (is8bit(imm32)) {
 289     emit_int8(op1 | 0x02); // set sign bit
 290     emit_operand(rm, adr, 1);
 291     emit_int8(imm32 & 0xFF);
 292   } else {
 293     emit_int8(op1);
 294     emit_operand(rm, adr, 4);
 295     emit_int32(imm32);
 296   }
 297 }
 298 
 299 
 300 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
 301   assert(isByte(op1) && isByte(op2), "wrong opcode");
 302   emit_int8(op1);
 303   emit_int8(op2 | encode(dst) << 3 | encode(src));
 304 }
 305 
 306 
 307 bool Assembler::query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len,
 308                                            int cur_tuple_type, int in_size_in_bits, int cur_encoding) {
 309   int mod_idx = 0;
 310   // We will test if the displacement fits the compressed format and if so
 311   // apply the compression to the displacment iff the result is8bit.
 312   if (VM_Version::supports_evex() && is_evex_inst) {
 313     switch (cur_tuple_type) {
 314     case EVEX_FV:
 315       if ((cur_encoding & VEX_W) == VEX_W) {
 316         mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2;
 317       } else {
 318         mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
 319       }
 320       break;
 321 
 322     case EVEX_HV:
 323       mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
 324       break;
 325 
 326     case EVEX_FVM:
 327       break;
 328 
 329     case EVEX_T1S:
 330       switch (in_size_in_bits) {
 331       case EVEX_8bit:
 332         break;
 333 
 334       case EVEX_16bit:
 335         mod_idx = 1;
 336         break;
 337 
 338       case EVEX_32bit:
 339         mod_idx = 2;
 340         break;
 341 
 342       case EVEX_64bit:
 343         mod_idx = 3;
 344         break;
 345       }
 346       break;
 347 
 348     case EVEX_T1F:
 349     case EVEX_T2:
 350     case EVEX_T4:
 351       mod_idx = (in_size_in_bits == EVEX_64bit) ? 1 : 0;
 352       break;
 353 
 354     case EVEX_T8:
 355       break;
 356 
 357     case EVEX_HVM:
 358       break;
 359 
 360     case EVEX_QVM:
 361       break;
 362 
 363     case EVEX_OVM:
 364       break;
 365 
 366     case EVEX_M128:
 367       break;
 368 
 369     case EVEX_DUP:
 370       break;
 371 
 372     default:
 373       assert(0, "no valid evex tuple_table entry");
 374       break;
 375     }
 376 
 377     if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
 378       int disp_factor = tuple_table[cur_tuple_type + mod_idx][vector_len];
 379       if ((disp % disp_factor) == 0) {
 380         int new_disp = disp / disp_factor;
 381         if ((-0x80 <= new_disp && new_disp < 0x80)) {
 382           disp = new_disp;
 383         }
 384       } else {
 385         return false;
 386       }
 387     }
 388   }
 389   return (-0x80 <= disp && disp < 0x80);
 390 }
 391 
 392 
 393 bool Assembler::emit_compressed_disp_byte(int &disp) {
 394   int mod_idx = 0;
 395   // We will test if the displacement fits the compressed format and if so
 396   // apply the compression to the displacment iff the result is8bit.
 397   if (VM_Version::supports_evex() && (_attributes != NULL) && _attributes->is_evex_instruction()) {
 398     int evex_encoding = _attributes->get_evex_encoding();
 399     int tuple_type = _attributes->get_tuple_type();
 400     switch (tuple_type) {
 401     case EVEX_FV:
 402       if ((evex_encoding & VEX_W) == VEX_W) {
 403         mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2;
 404       } else {
 405         mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
 406       }
 407       break;
 408 
 409     case EVEX_HV:
 410       mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
 411       break;
 412 
 413     case EVEX_FVM:
 414       break;
 415 
 416     case EVEX_T1S:
 417       switch (_attributes->get_input_size()) {
 418       case EVEX_8bit:
 419         break;
 420 
 421       case EVEX_16bit:
 422         mod_idx = 1;
 423         break;
 424 
 425       case EVEX_32bit:
 426         mod_idx = 2;
 427         break;
 428 
 429       case EVEX_64bit:
 430         mod_idx = 3;
 431         break;
 432       }
 433       break;
 434 
 435     case EVEX_T1F:
 436     case EVEX_T2:
 437     case EVEX_T4:
 438       mod_idx = (_attributes->get_input_size() == EVEX_64bit) ? 1 : 0;
 439       break;
 440 
 441     case EVEX_T8:
 442       break;
 443 
 444     case EVEX_HVM:
 445       break;
 446 
 447     case EVEX_QVM:
 448       break;
 449 
 450     case EVEX_OVM:
 451       break;
 452 
 453     case EVEX_M128:
 454       break;
 455 
 456     case EVEX_DUP:
 457       break;
 458 
 459     default:
 460       assert(0, "no valid evex tuple_table entry");
 461       break;
 462     }
 463 
 464     int vector_len = _attributes->get_vector_len();
 465     if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
 466       int disp_factor = tuple_table[tuple_type + mod_idx][vector_len];
 467       if ((disp % disp_factor) == 0) {
 468         int new_disp = disp / disp_factor;
 469         if (is8bit(new_disp)) {
 470           disp = new_disp;
 471         }
 472       } else {
 473         return false;
 474       }
 475     }
 476   }
 477   return is8bit(disp);
 478 }
 479 
 480 
 481 void Assembler::emit_operand(Register reg, Register base, Register index,
 482                              Address::ScaleFactor scale, int disp,
 483                              RelocationHolder const& rspec,
 484                              int rip_relative_correction) {
 485   relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();
 486 
 487   // Encode the registers as needed in the fields they are used in
 488 
 489   int regenc = encode(reg) << 3;
 490   int indexenc = index->is_valid() ? encode(index) << 3 : 0;
 491   int baseenc = base->is_valid() ? encode(base) : 0;
 492 
 493   if (base->is_valid()) {
 494     if (index->is_valid()) {
 495       assert(scale != Address::no_scale, "inconsistent address");
 496       // [base + index*scale + disp]
 497       if (disp == 0 && rtype == relocInfo::none  &&
 498           base != rbp LP64_ONLY(&& base != r13)) {
 499         // [base + index*scale]
 500         // [00 reg 100][ss index base]
 501         assert(index != rsp, "illegal addressing mode");
 502         emit_int8(0x04 | regenc);
 503         emit_int8(scale << 6 | indexenc | baseenc);
 504       } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
 505         // [base + index*scale + imm8]
 506         // [01 reg 100][ss index base] imm8
 507         assert(index != rsp, "illegal addressing mode");
 508         emit_int8(0x44 | regenc);
 509         emit_int8(scale << 6 | indexenc | baseenc);
 510         emit_int8(disp & 0xFF);
 511       } else {
 512         // [base + index*scale + disp32]
 513         // [10 reg 100][ss index base] disp32
 514         assert(index != rsp, "illegal addressing mode");
 515         emit_int8(0x84 | regenc);
 516         emit_int8(scale << 6 | indexenc | baseenc);
 517         emit_data(disp, rspec, disp32_operand);
 518       }
 519     } else if (base == rsp LP64_ONLY(|| base == r12)) {
 520       // [rsp + disp]
 521       if (disp == 0 && rtype == relocInfo::none) {
 522         // [rsp]
 523         // [00 reg 100][00 100 100]
 524         emit_int8(0x04 | regenc);
 525         emit_int8(0x24);
 526       } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
 527         // [rsp + imm8]
 528         // [01 reg 100][00 100 100] disp8
 529         emit_int8(0x44 | regenc);
 530         emit_int8(0x24);
 531         emit_int8(disp & 0xFF);
 532       } else {
 533         // [rsp + imm32]
 534         // [10 reg 100][00 100 100] disp32
 535         emit_int8(0x84 | regenc);
 536         emit_int8(0x24);
 537         emit_data(disp, rspec, disp32_operand);
 538       }
 539     } else {
 540       // [base + disp]
 541       assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode");
 542       if (disp == 0 && rtype == relocInfo::none &&
 543           base != rbp LP64_ONLY(&& base != r13)) {
 544         // [base]
 545         // [00 reg base]
 546         emit_int8(0x00 | regenc | baseenc);
 547       } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
 548         // [base + disp8]
 549         // [01 reg base] disp8
 550         emit_int8(0x40 | regenc | baseenc);
 551         emit_int8(disp & 0xFF);
 552       } else {
 553         // [base + disp32]
 554         // [10 reg base] disp32
 555         emit_int8(0x80 | regenc | baseenc);
 556         emit_data(disp, rspec, disp32_operand);
 557       }
 558     }
 559   } else {
 560     if (index->is_valid()) {
 561       assert(scale != Address::no_scale, "inconsistent address");
 562       // [index*scale + disp]
 563       // [00 reg 100][ss index 101] disp32
 564       assert(index != rsp, "illegal addressing mode");
 565       emit_int8(0x04 | regenc);
 566       emit_int8(scale << 6 | indexenc | 0x05);
 567       emit_data(disp, rspec, disp32_operand);
 568     } else if (rtype != relocInfo::none ) {
 569       // [disp] (64bit) RIP-RELATIVE (32bit) abs
 570       // [00 000 101] disp32
 571 
 572       emit_int8(0x05 | regenc);
 573       // Note that the RIP-rel. correction applies to the generated
 574       // disp field, but _not_ to the target address in the rspec.
 575 
 576       // disp was created by converting the target address minus the pc
 577       // at the start of the instruction. That needs more correction here.
 578       // intptr_t disp = target - next_ip;
 579       assert(inst_mark() != NULL, "must be inside InstructionMark");
 580       address next_ip = pc() + sizeof(int32_t) + rip_relative_correction;
 581       int64_t adjusted = disp;
 582       // Do rip-rel adjustment for 64bit
 583       LP64_ONLY(adjusted -=  (next_ip - inst_mark()));
 584       assert(is_simm32(adjusted),
 585              "must be 32bit offset (RIP relative address)");
 586       emit_data((int32_t) adjusted, rspec, disp32_operand);
 587 
 588     } else {
 589       // 32bit never did this, did everything as the rip-rel/disp code above
 590       // [disp] ABSOLUTE
 591       // [00 reg 100][00 100 101] disp32
 592       emit_int8(0x04 | regenc);
 593       emit_int8(0x25);
 594       emit_data(disp, rspec, disp32_operand);
 595     }
 596   }
 597 }
 598 
 599 void Assembler::emit_operand(XMMRegister reg, Register base, Register index,
 600                              Address::ScaleFactor scale, int disp,
 601                              RelocationHolder const& rspec) {
 602   if (UseAVX > 2) {
 603     int xreg_enc = reg->encoding();
 604     if (xreg_enc > 15) {
 605       XMMRegister new_reg = as_XMMRegister(xreg_enc & 0xf);
 606       emit_operand((Register)new_reg, base, index, scale, disp, rspec);
 607       return;
 608     }
 609   }
 610   emit_operand((Register)reg, base, index, scale, disp, rspec);
 611 }
 612 
 613 // Secret local extension to Assembler::WhichOperand:
 614 #define end_pc_operand (_WhichOperand_limit)
 615 
 616 address Assembler::locate_operand(address inst, WhichOperand which) {
 617   // Decode the given instruction, and return the address of
 618   // an embedded 32-bit operand word.
 619 
 620   // If "which" is disp32_operand, selects the displacement portion
 621   // of an effective address specifier.
 622   // If "which" is imm64_operand, selects the trailing immediate constant.
 623   // If "which" is call32_operand, selects the displacement of a call or jump.
 624   // Caller is responsible for ensuring that there is such an operand,
 625   // and that it is 32/64 bits wide.
 626 
 627   // If "which" is end_pc_operand, find the end of the instruction.
 628 
 629   address ip = inst;
 630   bool is_64bit = false;
 631 
 632   debug_only(bool has_disp32 = false);
 633   int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn
 634 
 635   again_after_prefix:
 636   switch (0xFF & *ip++) {
 637 
 638   // These convenience macros generate groups of "case" labels for the switch.
 639 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3
 640 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \
 641              case (x)+4: case (x)+5: case (x)+6: case (x)+7
 642 #define REP16(x) REP8((x)+0): \
 643               case REP8((x)+8)
 644 
 645   case CS_segment:
 646   case SS_segment:
 647   case DS_segment:
 648   case ES_segment:
 649   case FS_segment:
 650   case GS_segment:
 651     // Seems dubious
 652     LP64_ONLY(assert(false, "shouldn't have that prefix"));
 653     assert(ip == inst+1, "only one prefix allowed");
 654     goto again_after_prefix;
 655 
 656   case 0x67:
 657   case REX:
 658   case REX_B:
 659   case REX_X:
 660   case REX_XB:
 661   case REX_R:
 662   case REX_RB:
 663   case REX_RX:
 664   case REX_RXB:
 665     NOT_LP64(assert(false, "64bit prefixes"));
 666     goto again_after_prefix;
 667 
 668   case REX_W:
 669   case REX_WB:
 670   case REX_WX:
 671   case REX_WXB:
 672   case REX_WR:
 673   case REX_WRB:
 674   case REX_WRX:
 675   case REX_WRXB:
 676     NOT_LP64(assert(false, "64bit prefixes"));
 677     is_64bit = true;
 678     goto again_after_prefix;
 679 
 680   case 0xFF: // pushq a; decl a; incl a; call a; jmp a
 681   case 0x88: // movb a, r
 682   case 0x89: // movl a, r
 683   case 0x8A: // movb r, a
 684   case 0x8B: // movl r, a
 685   case 0x8F: // popl a
 686     debug_only(has_disp32 = true);
 687     break;
 688 
 689   case 0x68: // pushq #32
 690     if (which == end_pc_operand) {
 691       return ip + 4;
 692     }
 693     assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate");
 694     return ip;                  // not produced by emit_operand
 695 
 696   case 0x66: // movw ... (size prefix)
 697     again_after_size_prefix2:
 698     switch (0xFF & *ip++) {
 699     case REX:
 700     case REX_B:
 701     case REX_X:
 702     case REX_XB:
 703     case REX_R:
 704     case REX_RB:
 705     case REX_RX:
 706     case REX_RXB:
 707     case REX_W:
 708     case REX_WB:
 709     case REX_WX:
 710     case REX_WXB:
 711     case REX_WR:
 712     case REX_WRB:
 713     case REX_WRX:
 714     case REX_WRXB:
 715       NOT_LP64(assert(false, "64bit prefix found"));
 716       goto again_after_size_prefix2;
 717     case 0x8B: // movw r, a
 718     case 0x89: // movw a, r
 719       debug_only(has_disp32 = true);
 720       break;
 721     case 0xC7: // movw a, #16
 722       debug_only(has_disp32 = true);
 723       tail_size = 2;  // the imm16
 724       break;
 725     case 0x0F: // several SSE/SSE2 variants
 726       ip--;    // reparse the 0x0F
 727       goto again_after_prefix;
 728     default:
 729       ShouldNotReachHere();
 730     }
 731     break;
 732 
 733   case REP8(0xB8): // movl/q r, #32/#64(oop?)
 734     if (which == end_pc_operand)  return ip + (is_64bit ? 8 : 4);
 735     // these asserts are somewhat nonsensical
 736 #ifndef _LP64
 737     assert(which == imm_operand || which == disp32_operand,
 738            "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip));
 739 #else
 740     assert((which == call32_operand || which == imm_operand) && is_64bit ||
 741            which == narrow_oop_operand && !is_64bit,
 742            "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip));
 743 #endif // _LP64
 744     return ip;
 745 
 746   case 0x69: // imul r, a, #32
 747   case 0xC7: // movl a, #32(oop?)
 748     tail_size = 4;
 749     debug_only(has_disp32 = true); // has both kinds of operands!
 750     break;
 751 
 752   case 0x0F: // movx..., etc.
 753     switch (0xFF & *ip++) {
 754     case 0x3A: // pcmpestri
 755       tail_size = 1;
 756     case 0x38: // ptest, pmovzxbw
 757       ip++; // skip opcode
 758       debug_only(has_disp32 = true); // has both kinds of operands!
 759       break;
 760 
 761     case 0x70: // pshufd r, r/a, #8
 762       debug_only(has_disp32 = true); // has both kinds of operands!
 763     case 0x73: // psrldq r, #8
 764       tail_size = 1;
 765       break;
 766 
 767     case 0x12: // movlps
 768     case 0x28: // movaps
 769     case 0x2E: // ucomiss
 770     case 0x2F: // comiss
 771     case 0x54: // andps
 772     case 0x55: // andnps
 773     case 0x56: // orps
 774     case 0x57: // xorps
 775     case 0x58: // addpd
 776     case 0x59: // mulpd
 777     case 0x6E: // movd
 778     case 0x7E: // movd
 779     case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush
 780     case 0xFE: // paddd
 781       debug_only(has_disp32 = true);
 782       break;
 783 
 784     case 0xAD: // shrd r, a, %cl
 785     case 0xAF: // imul r, a
 786     case 0xBE: // movsbl r, a (movsxb)
 787     case 0xBF: // movswl r, a (movsxw)
 788     case 0xB6: // movzbl r, a (movzxb)
 789     case 0xB7: // movzwl r, a (movzxw)
 790     case REP16(0x40): // cmovl cc, r, a
 791     case 0xB0: // cmpxchgb
 792     case 0xB1: // cmpxchg
 793     case 0xC1: // xaddl
 794     case 0xC7: // cmpxchg8
 795     case REP16(0x90): // setcc a
 796       debug_only(has_disp32 = true);
 797       // fall out of the switch to decode the address
 798       break;
 799 
 800     case 0xC4: // pinsrw r, a, #8
 801       debug_only(has_disp32 = true);
 802     case 0xC5: // pextrw r, r, #8
 803       tail_size = 1;  // the imm8
 804       break;
 805 
 806     case 0xAC: // shrd r, a, #8
 807       debug_only(has_disp32 = true);
 808       tail_size = 1;  // the imm8
 809       break;
 810 
 811     case REP16(0x80): // jcc rdisp32
 812       if (which == end_pc_operand)  return ip + 4;
 813       assert(which == call32_operand, "jcc has no disp32 or imm");
 814       return ip;
 815     default:
 816       ShouldNotReachHere();
 817     }
 818     break;
 819 
 820   case 0x81: // addl a, #32; addl r, #32
 821     // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
 822     // on 32bit in the case of cmpl, the imm might be an oop
 823     tail_size = 4;
 824     debug_only(has_disp32 = true); // has both kinds of operands!
 825     break;
 826 
 827   case 0x83: // addl a, #8; addl r, #8
 828     // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
 829     debug_only(has_disp32 = true); // has both kinds of operands!
 830     tail_size = 1;
 831     break;
 832 
 833   case 0x9B:
 834     switch (0xFF & *ip++) {
 835     case 0xD9: // fnstcw a
 836       debug_only(has_disp32 = true);
 837       break;
 838     default:
 839       ShouldNotReachHere();
 840     }
 841     break;
 842 
 843   case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a
 844   case REP4(0x10): // adc...
 845   case REP4(0x20): // and...
 846   case REP4(0x30): // xor...
 847   case REP4(0x08): // or...
 848   case REP4(0x18): // sbb...
 849   case REP4(0x28): // sub...
 850   case 0xF7: // mull a
 851   case 0x8D: // lea r, a
 852   case 0x87: // xchg r, a
 853   case REP4(0x38): // cmp...
 854   case 0x85: // test r, a
 855     debug_only(has_disp32 = true); // has both kinds of operands!
 856     break;
 857 
 858   case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8
 859   case 0xC6: // movb a, #8
 860   case 0x80: // cmpb a, #8
 861   case 0x6B: // imul r, a, #8
 862     debug_only(has_disp32 = true); // has both kinds of operands!
 863     tail_size = 1; // the imm8
 864     break;
 865 
 866   case 0xC4: // VEX_3bytes
 867   case 0xC5: // VEX_2bytes
 868     assert((UseAVX > 0), "shouldn't have VEX prefix");
 869     assert(ip == inst+1, "no prefixes allowed");
 870     // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions
 871     // but they have prefix 0x0F and processed when 0x0F processed above.
 872     //
 873     // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES
 874     // instructions (these instructions are not supported in 64-bit mode).
 875     // To distinguish them bits [7:6] are set in the VEX second byte since
 876     // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set
 877     // those VEX bits REX and vvvv bits are inverted.
 878     //
 879     // Fortunately C2 doesn't generate these instructions so we don't need
 880     // to check for them in product version.
 881 
 882     // Check second byte
 883     NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions"));
 884 
 885     int vex_opcode;
 886     // First byte
 887     if ((0xFF & *inst) == VEX_3bytes) {
 888       vex_opcode = VEX_OPCODE_MASK & *ip;
 889       ip++; // third byte
 890       is_64bit = ((VEX_W & *ip) == VEX_W);
 891     } else {
 892       vex_opcode = VEX_OPCODE_0F;
 893     }
 894     ip++; // opcode
 895     // To find the end of instruction (which == end_pc_operand).
 896     switch (vex_opcode) {
 897       case VEX_OPCODE_0F:
 898         switch (0xFF & *ip) {
 899         case 0x70: // pshufd r, r/a, #8
 900         case 0x71: // ps[rl|ra|ll]w r, #8
 901         case 0x72: // ps[rl|ra|ll]d r, #8
 902         case 0x73: // ps[rl|ra|ll]q r, #8
 903         case 0xC2: // cmp[ps|pd|ss|sd] r, r, r/a, #8
 904         case 0xC4: // pinsrw r, r, r/a, #8
 905         case 0xC5: // pextrw r/a, r, #8
 906         case 0xC6: // shufp[s|d] r, r, r/a, #8
 907           tail_size = 1;  // the imm8
 908           break;
 909         }
 910         break;
 911       case VEX_OPCODE_0F_3A:
 912         tail_size = 1;
 913         break;
 914     }
 915     ip++; // skip opcode
 916     debug_only(has_disp32 = true); // has both kinds of operands!
 917     break;
 918 
 919   case 0x62: // EVEX_4bytes
 920     assert((UseAVX > 0), "shouldn't have EVEX prefix");
 921     assert(ip == inst+1, "no prefixes allowed");
 922     // no EVEX collisions, all instructions that have 0x62 opcodes
 923     // have EVEX versions and are subopcodes of 0x66
 924     ip++; // skip P0 and exmaine W in P1
 925     is_64bit = ((VEX_W & *ip) == VEX_W);
 926     ip++; // move to P2
 927     ip++; // skip P2, move to opcode
 928     // To find the end of instruction (which == end_pc_operand).
 929     switch (0xFF & *ip) {
 930     case 0x22: // pinsrd r, r/a, #8
 931     case 0x61: // pcmpestri r, r/a, #8
 932     case 0x70: // pshufd r, r/a, #8
 933     case 0x73: // psrldq r, #8
 934       tail_size = 1;  // the imm8
 935       break;
 936     default:
 937       break;
 938     }
 939     ip++; // skip opcode
 940     debug_only(has_disp32 = true); // has both kinds of operands!
 941     break;
 942 
 943   case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
 944   case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
 945   case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a
 946   case 0xDD: // fld_d a; fst_d a; fstp_d a
 947   case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a
 948   case 0xDF: // fild_d a; fistp_d a
 949   case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a
 950   case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a
 951   case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a
 952     debug_only(has_disp32 = true);
 953     break;
 954 
 955   case 0xE8: // call rdisp32
 956   case 0xE9: // jmp  rdisp32
 957     if (which == end_pc_operand)  return ip + 4;
 958     assert(which == call32_operand, "call has no disp32 or imm");
 959     return ip;
 960 
 961   case 0xF0:                    // Lock
 962     assert(os::is_MP(), "only on MP");
 963     goto again_after_prefix;
 964 
 965   case 0xF3:                    // For SSE
 966   case 0xF2:                    // For SSE2
 967     switch (0xFF & *ip++) {
 968     case REX:
 969     case REX_B:
 970     case REX_X:
 971     case REX_XB:
 972     case REX_R:
 973     case REX_RB:
 974     case REX_RX:
 975     case REX_RXB:
 976     case REX_W:
 977     case REX_WB:
 978     case REX_WX:
 979     case REX_WXB:
 980     case REX_WR:
 981     case REX_WRB:
 982     case REX_WRX:
 983     case REX_WRXB:
 984       NOT_LP64(assert(false, "found 64bit prefix"));
 985       ip++;
 986     default:
 987       ip++;
 988     }
 989     debug_only(has_disp32 = true); // has both kinds of operands!
 990     break;
 991 
 992   default:
 993     ShouldNotReachHere();
 994 
 995 #undef REP8
 996 #undef REP16
 997   }
 998 
 999   assert(which != call32_operand, "instruction is not a call, jmp, or jcc");
1000 #ifdef _LP64
1001   assert(which != imm_operand, "instruction is not a movq reg, imm64");
1002 #else
1003   // assert(which != imm_operand || has_imm32, "instruction has no imm32 field");
1004   assert(which != imm_operand || has_disp32, "instruction has no imm32 field");
1005 #endif // LP64
1006   assert(which != disp32_operand || has_disp32, "instruction has no disp32 field");
1007 
1008   // parse the output of emit_operand
1009   int op2 = 0xFF & *ip++;
1010   int base = op2 & 0x07;
1011   int op3 = -1;
1012   const int b100 = 4;
1013   const int b101 = 5;
1014   if (base == b100 && (op2 >> 6) != 3) {
1015     op3 = 0xFF & *ip++;
1016     base = op3 & 0x07;   // refetch the base
1017   }
1018   // now ip points at the disp (if any)
1019 
1020   switch (op2 >> 6) {
1021   case 0:
1022     // [00 reg  100][ss index base]
1023     // [00 reg  100][00   100  esp]
1024     // [00 reg base]
1025     // [00 reg  100][ss index  101][disp32]
1026     // [00 reg  101]               [disp32]
1027 
1028     if (base == b101) {
1029       if (which == disp32_operand)
1030         return ip;              // caller wants the disp32
1031       ip += 4;                  // skip the disp32
1032     }
1033     break;
1034 
1035   case 1:
1036     // [01 reg  100][ss index base][disp8]
1037     // [01 reg  100][00   100  esp][disp8]
1038     // [01 reg base]               [disp8]
1039     ip += 1;                    // skip the disp8
1040     break;
1041 
1042   case 2:
1043     // [10 reg  100][ss index base][disp32]
1044     // [10 reg  100][00   100  esp][disp32]
1045     // [10 reg base]               [disp32]
1046     if (which == disp32_operand)
1047       return ip;                // caller wants the disp32
1048     ip += 4;                    // skip the disp32
1049     break;
1050 
1051   case 3:
1052     // [11 reg base]  (not a memory addressing mode)
1053     break;
1054   }
1055 
1056   if (which == end_pc_operand) {
1057     return ip + tail_size;
1058   }
1059 
1060 #ifdef _LP64
1061   assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32");
1062 #else
1063   assert(which == imm_operand, "instruction has only an imm field");
1064 #endif // LP64
1065   return ip;
1066 }
1067 
1068 address Assembler::locate_next_instruction(address inst) {
1069   // Secretly share code with locate_operand:
1070   return locate_operand(inst, end_pc_operand);
1071 }
1072 
1073 
1074 #ifdef ASSERT
1075 void Assembler::check_relocation(RelocationHolder const& rspec, int format) {
1076   address inst = inst_mark();
1077   assert(inst != NULL && inst < pc(), "must point to beginning of instruction");
1078   address opnd;
1079 
1080   Relocation* r = rspec.reloc();
1081   if (r->type() == relocInfo::none) {
1082     return;
1083   } else if (r->is_call() || format == call32_operand) {
1084     // assert(format == imm32_operand, "cannot specify a nonzero format");
1085     opnd = locate_operand(inst, call32_operand);
1086   } else if (r->is_data()) {
1087     assert(format == imm_operand || format == disp32_operand
1088            LP64_ONLY(|| format == narrow_oop_operand), "format ok");
1089     opnd = locate_operand(inst, (WhichOperand)format);
1090   } else {
1091     assert(format == imm_operand, "cannot specify a format");
1092     return;
1093   }
1094   assert(opnd == pc(), "must put operand where relocs can find it");
1095 }
1096 #endif // ASSERT
1097 
1098 void Assembler::emit_operand32(Register reg, Address adr) {
1099   assert(reg->encoding() < 8, "no extended registers");
1100   assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1101   emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1102                adr._rspec);
1103 }
1104 
1105 void Assembler::emit_operand(Register reg, Address adr,
1106                              int rip_relative_correction) {
1107   emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1108                adr._rspec,
1109                rip_relative_correction);
1110 }
1111 
1112 void Assembler::emit_operand(XMMRegister reg, Address adr) {
1113   emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1114                adr._rspec);
1115 }
1116 
1117 // MMX operations
1118 void Assembler::emit_operand(MMXRegister reg, Address adr) {
1119   assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1120   emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1121 }
1122 
1123 // work around gcc (3.2.1-7a) bug
1124 void Assembler::emit_operand(Address adr, MMXRegister reg) {
1125   assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1126   emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1127 }
1128 
1129 
1130 void Assembler::emit_farith(int b1, int b2, int i) {
1131   assert(isByte(b1) && isByte(b2), "wrong opcode");
1132   assert(0 <= i &&  i < 8, "illegal stack offset");
1133   emit_int8(b1);
1134   emit_int8(b2 + i);
1135 }
1136 
1137 
1138 // Now the Assembler instructions (identical for 32/64 bits)
1139 
1140 void Assembler::adcl(Address dst, int32_t imm32) {
1141   InstructionMark im(this);
1142   prefix(dst);
1143   emit_arith_operand(0x81, rdx, dst, imm32);
1144 }
1145 
1146 void Assembler::adcl(Address dst, Register src) {
1147   InstructionMark im(this);
1148   prefix(dst, src);
1149   emit_int8(0x11);
1150   emit_operand(src, dst);
1151 }
1152 
1153 void Assembler::adcl(Register dst, int32_t imm32) {
1154   prefix(dst);
1155   emit_arith(0x81, 0xD0, dst, imm32);
1156 }
1157 
1158 void Assembler::adcl(Register dst, Address src) {
1159   InstructionMark im(this);
1160   prefix(src, dst);
1161   emit_int8(0x13);
1162   emit_operand(dst, src);
1163 }
1164 
1165 void Assembler::adcl(Register dst, Register src) {
1166   (void) prefix_and_encode(dst->encoding(), src->encoding());
1167   emit_arith(0x13, 0xC0, dst, src);
1168 }
1169 
1170 void Assembler::addl(Address dst, int32_t imm32) {
1171   InstructionMark im(this);
1172   prefix(dst);
1173   emit_arith_operand(0x81, rax, dst, imm32);
1174 }
1175 
1176 void Assembler::addl(Address dst, Register src) {
1177   InstructionMark im(this);
1178   prefix(dst, src);
1179   emit_int8(0x01);
1180   emit_operand(src, dst);
1181 }
1182 
1183 void Assembler::addl(Register dst, int32_t imm32) {
1184   prefix(dst);
1185   emit_arith(0x81, 0xC0, dst, imm32);
1186 }
1187 
1188 void Assembler::addl(Register dst, Address src) {
1189   InstructionMark im(this);
1190   prefix(src, dst);
1191   emit_int8(0x03);
1192   emit_operand(dst, src);
1193 }
1194 
1195 void Assembler::addl(Register dst, Register src) {
1196   (void) prefix_and_encode(dst->encoding(), src->encoding());
1197   emit_arith(0x03, 0xC0, dst, src);
1198 }
1199 
1200 void Assembler::addr_nop_4() {
1201   assert(UseAddressNop, "no CPU support");
1202   // 4 bytes: NOP DWORD PTR [EAX+0]
1203   emit_int8(0x0F);
1204   emit_int8(0x1F);
1205   emit_int8(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
1206   emit_int8(0);    // 8-bits offset (1 byte)
1207 }
1208 
1209 void Assembler::addr_nop_5() {
1210   assert(UseAddressNop, "no CPU support");
1211   // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
1212   emit_int8(0x0F);
1213   emit_int8(0x1F);
1214   emit_int8(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
1215   emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1216   emit_int8(0);    // 8-bits offset (1 byte)
1217 }
1218 
1219 void Assembler::addr_nop_7() {
1220   assert(UseAddressNop, "no CPU support");
1221   // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
1222   emit_int8(0x0F);
1223   emit_int8(0x1F);
1224   emit_int8((unsigned char)0x80);
1225                    // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
1226   emit_int32(0);   // 32-bits offset (4 bytes)
1227 }
1228 
1229 void Assembler::addr_nop_8() {
1230   assert(UseAddressNop, "no CPU support");
1231   // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
1232   emit_int8(0x0F);
1233   emit_int8(0x1F);
1234   emit_int8((unsigned char)0x84);
1235                    // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
1236   emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1237   emit_int32(0);   // 32-bits offset (4 bytes)
1238 }
1239 
1240 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
1241   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1242   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1243   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1244   emit_int8(0x58);
1245   emit_int8((unsigned char)(0xC0 | encode));
1246 }
1247 
1248 void Assembler::addsd(XMMRegister dst, Address src) {
1249   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1250   InstructionMark im(this);
1251   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1252   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1253   simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1254   emit_int8(0x58);
1255   emit_operand(dst, src);
1256 }
1257 
1258 void Assembler::addss(XMMRegister dst, XMMRegister src) {
1259   NOT_LP64(assert(VM_Version::supports_sse(), ""));
1260   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1261   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1262   emit_int8(0x58);
1263   emit_int8((unsigned char)(0xC0 | encode));
1264 }
1265 
1266 void Assembler::addss(XMMRegister dst, Address src) {
1267   NOT_LP64(assert(VM_Version::supports_sse(), ""));
1268   InstructionMark im(this);
1269   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1270   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1271   simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1272   emit_int8(0x58);
1273   emit_operand(dst, src);
1274 }
1275 
1276 void Assembler::aesdec(XMMRegister dst, Address src) {
1277   assert(VM_Version::supports_aes(), "");
1278   InstructionMark im(this);
1279   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1280   simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1281   emit_int8((unsigned char)0xDE);
1282   emit_operand(dst, src);
1283 }
1284 
1285 void Assembler::aesdec(XMMRegister dst, XMMRegister src) {
1286   assert(VM_Version::supports_aes(), "");
1287   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1288   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1289   emit_int8((unsigned char)0xDE);
1290   emit_int8(0xC0 | encode);
1291 }
1292 
1293 void Assembler::aesdeclast(XMMRegister dst, Address src) {
1294   assert(VM_Version::supports_aes(), "");
1295   InstructionMark im(this);
1296   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1297   simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1298   emit_int8((unsigned char)0xDF);
1299   emit_operand(dst, src);
1300 }
1301 
1302 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) {
1303   assert(VM_Version::supports_aes(), "");
1304   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1305   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1306   emit_int8((unsigned char)0xDF);
1307   emit_int8((unsigned char)(0xC0 | encode));
1308 }
1309 
1310 void Assembler::aesenc(XMMRegister dst, Address src) {
1311   assert(VM_Version::supports_aes(), "");
1312   InstructionMark im(this);
1313   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1314   simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1315   emit_int8((unsigned char)0xDC);
1316   emit_operand(dst, src);
1317 }
1318 
1319 void Assembler::aesenc(XMMRegister dst, XMMRegister src) {
1320   assert(VM_Version::supports_aes(), "");
1321   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1322   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1323   emit_int8((unsigned char)0xDC);
1324   emit_int8(0xC0 | encode);
1325 }
1326 
1327 void Assembler::aesenclast(XMMRegister dst, Address src) {
1328   assert(VM_Version::supports_aes(), "");
1329   InstructionMark im(this);
1330   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1331   simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1332   emit_int8((unsigned char)0xDD);
1333   emit_operand(dst, src);
1334 }
1335 
1336 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) {
1337   assert(VM_Version::supports_aes(), "");
1338   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1339   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1340   emit_int8((unsigned char)0xDD);
1341   emit_int8((unsigned char)(0xC0 | encode));
1342 }
1343 
1344 void Assembler::andl(Address dst, int32_t imm32) {
1345   InstructionMark im(this);
1346   prefix(dst);
1347   emit_int8((unsigned char)0x81);
1348   emit_operand(rsp, dst, 4);
1349   emit_int32(imm32);
1350 }
1351 
1352 void Assembler::andl(Register dst, int32_t imm32) {
1353   prefix(dst);
1354   emit_arith(0x81, 0xE0, dst, imm32);
1355 }
1356 
1357 void Assembler::andl(Register dst, Address src) {
1358   InstructionMark im(this);
1359   prefix(src, dst);
1360   emit_int8(0x23);
1361   emit_operand(dst, src);
1362 }
1363 
1364 void Assembler::andl(Register dst, Register src) {
1365   (void) prefix_and_encode(dst->encoding(), src->encoding());
1366   emit_arith(0x23, 0xC0, dst, src);
1367 }
1368 
1369 void Assembler::andnl(Register dst, Register src1, Register src2) {
1370   assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1371   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1372   int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1373   emit_int8((unsigned char)0xF2);
1374   emit_int8((unsigned char)(0xC0 | encode));
1375 }
1376 
1377 void Assembler::andnl(Register dst, Register src1, Address src2) {
1378   assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1379   InstructionMark im(this);
1380   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1381   vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1382   emit_int8((unsigned char)0xF2);
1383   emit_operand(dst, src2);
1384 }
1385 
1386 void Assembler::bsfl(Register dst, Register src) {
1387   int encode = prefix_and_encode(dst->encoding(), src->encoding());
1388   emit_int8(0x0F);
1389   emit_int8((unsigned char)0xBC);
1390   emit_int8((unsigned char)(0xC0 | encode));
1391 }
1392 
1393 void Assembler::bsrl(Register dst, Register src) {
1394   int encode = prefix_and_encode(dst->encoding(), src->encoding());
1395   emit_int8(0x0F);
1396   emit_int8((unsigned char)0xBD);
1397   emit_int8((unsigned char)(0xC0 | encode));
1398 }
1399 
1400 void Assembler::bswapl(Register reg) { // bswap
1401   int encode = prefix_and_encode(reg->encoding());
1402   emit_int8(0x0F);
1403   emit_int8((unsigned char)(0xC8 | encode));
1404 }
1405 
1406 void Assembler::blsil(Register dst, Register src) {
1407   assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1408   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1409   int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1410   emit_int8((unsigned char)0xF3);
1411   emit_int8((unsigned char)(0xC0 | encode));
1412 }
1413 
1414 void Assembler::blsil(Register dst, Address src) {
1415   assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1416   InstructionMark im(this);
1417   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1418   vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1419   emit_int8((unsigned char)0xF3);
1420   emit_operand(rbx, src);
1421 }
1422 
1423 void Assembler::blsmskl(Register dst, Register src) {
1424   assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1425   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1426   int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1427   emit_int8((unsigned char)0xF3);
1428   emit_int8((unsigned char)(0xC0 | encode));
1429 }
1430 
1431 void Assembler::blsmskl(Register dst, Address src) {
1432   assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1433   InstructionMark im(this);
1434   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1435   vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1436   emit_int8((unsigned char)0xF3);
1437   emit_operand(rdx, src);
1438 }
1439 
1440 void Assembler::blsrl(Register dst, Register src) {
1441   assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1442   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1443   int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1444   emit_int8((unsigned char)0xF3);
1445   emit_int8((unsigned char)(0xC0 | encode));
1446 }
1447 
1448 void Assembler::blsrl(Register dst, Address src) {
1449   assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1450   InstructionMark im(this);
1451   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1452   vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1453   emit_int8((unsigned char)0xF3);
1454   emit_operand(rcx, src);
1455 }
1456 
1457 void Assembler::call(Label& L, relocInfo::relocType rtype) {
1458   // suspect disp32 is always good
1459   int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
1460 
1461   if (L.is_bound()) {
1462     const int long_size = 5;
1463     int offs = (int)( target(L) - pc() );
1464     assert(offs <= 0, "assembler error");
1465     InstructionMark im(this);
1466     // 1110 1000 #32-bit disp
1467     emit_int8((unsigned char)0xE8);
1468     emit_data(offs - long_size, rtype, operand);
1469   } else {
1470     InstructionMark im(this);
1471     // 1110 1000 #32-bit disp
1472     L.add_patch_at(code(), locator());
1473 
1474     emit_int8((unsigned char)0xE8);
1475     emit_data(int(0), rtype, operand);
1476   }
1477 }
1478 
1479 void Assembler::call(Register dst) {
1480   int encode = prefix_and_encode(dst->encoding());
1481   emit_int8((unsigned char)0xFF);
1482   emit_int8((unsigned char)(0xD0 | encode));
1483 }
1484 
1485 
1486 void Assembler::call(Address adr) {
1487   InstructionMark im(this);
1488   prefix(adr);
1489   emit_int8((unsigned char)0xFF);
1490   emit_operand(rdx, adr);
1491 }
1492 
1493 void Assembler::call_literal(address entry, RelocationHolder const& rspec) {
1494   assert(entry != NULL, "call most probably wrong");
1495   InstructionMark im(this);
1496   emit_int8((unsigned char)0xE8);
1497   intptr_t disp = entry - (pc() + sizeof(int32_t));
1498   assert(is_simm32(disp), "must be 32bit offset (call2)");
1499   // Technically, should use call32_operand, but this format is
1500   // implied by the fact that we're emitting a call instruction.
1501 
1502   int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand);
1503   emit_data((int) disp, rspec, operand);
1504 }
1505 
1506 void Assembler::cdql() {
1507   emit_int8((unsigned char)0x99);
1508 }
1509 
1510 void Assembler::cld() {
1511   emit_int8((unsigned char)0xFC);
1512 }
1513 
1514 void Assembler::cmovl(Condition cc, Register dst, Register src) {
1515   NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1516   int encode = prefix_and_encode(dst->encoding(), src->encoding());
1517   emit_int8(0x0F);
1518   emit_int8(0x40 | cc);
1519   emit_int8((unsigned char)(0xC0 | encode));
1520 }
1521 
1522 
1523 void Assembler::cmovl(Condition cc, Register dst, Address src) {
1524   NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1525   prefix(src, dst);
1526   emit_int8(0x0F);
1527   emit_int8(0x40 | cc);
1528   emit_operand(dst, src);
1529 }
1530 
1531 void Assembler::cmpb(Address dst, int imm8) {
1532   InstructionMark im(this);
1533   prefix(dst);
1534   emit_int8((unsigned char)0x80);
1535   emit_operand(rdi, dst, 1);
1536   emit_int8(imm8);
1537 }
1538 
1539 void Assembler::cmpl(Address dst, int32_t imm32) {
1540   InstructionMark im(this);
1541   prefix(dst);
1542   emit_int8((unsigned char)0x81);
1543   emit_operand(rdi, dst, 4);
1544   emit_int32(imm32);
1545 }
1546 
1547 void Assembler::cmpl(Register dst, int32_t imm32) {
1548   prefix(dst);
1549   emit_arith(0x81, 0xF8, dst, imm32);
1550 }
1551 
1552 void Assembler::cmpl(Register dst, Register src) {
1553   (void) prefix_and_encode(dst->encoding(), src->encoding());
1554   emit_arith(0x3B, 0xC0, dst, src);
1555 }
1556 
1557 void Assembler::cmpl(Register dst, Address  src) {
1558   InstructionMark im(this);
1559   prefix(src, dst);
1560   emit_int8((unsigned char)0x3B);
1561   emit_operand(dst, src);
1562 }
1563 
1564 void Assembler::cmpw(Address dst, int imm16) {
1565   InstructionMark im(this);
1566   assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers");
1567   emit_int8(0x66);
1568   emit_int8((unsigned char)0x81);
1569   emit_operand(rdi, dst, 2);
1570   emit_int16(imm16);
1571 }
1572 
1573 // The 32-bit cmpxchg compares the value at adr with the contents of rax,
1574 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1575 // The ZF is set if the compared values were equal, and cleared otherwise.
1576 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg
1577   InstructionMark im(this);
1578   prefix(adr, reg);
1579   emit_int8(0x0F);
1580   emit_int8((unsigned char)0xB1);
1581   emit_operand(reg, adr);
1582 }
1583 
1584 // The 8-bit cmpxchg compares the value at adr with the contents of rax,
1585 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1586 // The ZF is set if the compared values were equal, and cleared otherwise.
1587 void Assembler::cmpxchgb(Register reg, Address adr) { // cmpxchg
1588   InstructionMark im(this);
1589   prefix(adr, reg, true);
1590   emit_int8(0x0F);
1591   emit_int8((unsigned char)0xB0);
1592   emit_operand(reg, adr);
1593 }
1594 
1595 void Assembler::comisd(XMMRegister dst, Address src) {
1596   // NOTE: dbx seems to decode this as comiss even though the
1597   // 0x66 is there. Strangly ucomisd comes out correct
1598   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1599   InstructionMark im(this);
1600   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);;
1601   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1602   simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1603   emit_int8(0x2F);
1604   emit_operand(dst, src);
1605 }
1606 
1607 void Assembler::comisd(XMMRegister dst, XMMRegister src) {
1608   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1609   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1610   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1611   emit_int8(0x2F);
1612   emit_int8((unsigned char)(0xC0 | encode));
1613 }
1614 
1615 void Assembler::comiss(XMMRegister dst, Address src) {
1616   NOT_LP64(assert(VM_Version::supports_sse(), ""));
1617   InstructionMark im(this);
1618   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1619   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1620   simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1621   emit_int8(0x2F);
1622   emit_operand(dst, src);
1623 }
1624 
1625 void Assembler::comiss(XMMRegister dst, XMMRegister src) {
1626   NOT_LP64(assert(VM_Version::supports_sse(), ""));
1627   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1628   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1629   emit_int8(0x2F);
1630   emit_int8((unsigned char)(0xC0 | encode));
1631 }
1632 
1633 void Assembler::cpuid() {
1634   emit_int8(0x0F);
1635   emit_int8((unsigned char)0xA2);
1636 }
1637 
1638 // Opcode / Instruction                      Op /  En  64 - Bit Mode     Compat / Leg Mode Description                  Implemented
1639 // F2 0F 38 F0 / r       CRC32 r32, r / m8   RM        Valid             Valid             Accumulate CRC32 on r / m8.  v
1640 // F2 REX 0F 38 F0 / r   CRC32 r32, r / m8*  RM        Valid             N.E.              Accumulate CRC32 on r / m8.  -
1641 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8   RM        Valid             N.E.              Accumulate CRC32 on r / m8.  -
1642 //
1643 // F2 0F 38 F1 / r       CRC32 r32, r / m16  RM        Valid             Valid             Accumulate CRC32 on r / m16. v
1644 //
1645 // F2 0F 38 F1 / r       CRC32 r32, r / m32  RM        Valid             Valid             Accumulate CRC32 on r / m32. v
1646 //
1647 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64  RM        Valid             N.E.              Accumulate CRC32 on r / m64. v
1648 void Assembler::crc32(Register crc, Register v, int8_t sizeInBytes) {
1649   assert(VM_Version::supports_sse4_2(), "");
1650   int8_t w = 0x01;
1651   Prefix p = Prefix_EMPTY;
1652 
1653   emit_int8((int8_t)0xF2);
1654   switch (sizeInBytes) {
1655   case 1:
1656     w = 0;
1657     break;
1658   case 2:
1659   case 4:
1660     break;
1661   LP64_ONLY(case 8:)
1662     // This instruction is not valid in 32 bits
1663     // Note:
1664     // http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
1665     //
1666     // Page B - 72   Vol. 2C says
1667     // qwreg2 to qwreg            1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : 11 qwreg1 qwreg2
1668     // mem64 to qwreg             1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : mod qwreg r / m
1669     //                                                                            F0!!!
1670     // while 3 - 208 Vol. 2A
1671     // F2 REX.W 0F 38 F1 / r       CRC32 r64, r / m64             RM         Valid      N.E.Accumulate CRC32 on r / m64.
1672     //
1673     // the 0 on a last bit is reserved for a different flavor of this instruction :
1674     // F2 REX.W 0F 38 F0 / r       CRC32 r64, r / m8              RM         Valid      N.E.Accumulate CRC32 on r / m8.
1675     p = REX_W;
1676     break;
1677   default:
1678     assert(0, "Unsupported value for a sizeInBytes argument");
1679     break;
1680   }
1681   LP64_ONLY(prefix(crc, v, p);)
1682   emit_int8((int8_t)0x0F);
1683   emit_int8(0x38);
1684   emit_int8((int8_t)(0xF0 | w));
1685   emit_int8(0xC0 | ((crc->encoding() & 0x7) << 3) | (v->encoding() & 7));
1686 }
1687 
1688 void Assembler::crc32(Register crc, Address adr, int8_t sizeInBytes) {
1689   assert(VM_Version::supports_sse4_2(), "");
1690   InstructionMark im(this);
1691   int8_t w = 0x01;
1692   Prefix p = Prefix_EMPTY;
1693 
1694   emit_int8((int8_t)0xF2);
1695   switch (sizeInBytes) {
1696   case 1:
1697     w = 0;
1698     break;
1699   case 2:
1700   case 4:
1701     break;
1702   LP64_ONLY(case 8:)
1703     // This instruction is not valid in 32 bits
1704     p = REX_W;
1705     break;
1706   default:
1707     assert(0, "Unsupported value for a sizeInBytes argument");
1708     break;
1709   }
1710   LP64_ONLY(prefix(crc, adr, p);)
1711   emit_int8((int8_t)0x0F);
1712   emit_int8(0x38);
1713   emit_int8((int8_t)(0xF0 | w));
1714   emit_operand(crc, adr);
1715 }
1716 
1717 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
1718   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1719   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
1720   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1721   emit_int8((unsigned char)0xE6);
1722   emit_int8((unsigned char)(0xC0 | encode));
1723 }
1724 
1725 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
1726   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1727   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
1728   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1729   emit_int8(0x5B);
1730   emit_int8((unsigned char)(0xC0 | encode));
1731 }
1732 
1733 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
1734   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1735   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1736   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1737   emit_int8(0x5A);
1738   emit_int8((unsigned char)(0xC0 | encode));
1739 }
1740 
1741 void Assembler::cvtsd2ss(XMMRegister dst, Address src) {
1742   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1743   InstructionMark im(this);
1744   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1745   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1746   simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1747   emit_int8(0x5A);
1748   emit_operand(dst, src);
1749 }
1750 
1751 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
1752   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1753   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1754   int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1755   emit_int8(0x2A);
1756   emit_int8((unsigned char)(0xC0 | encode));
1757 }
1758 
1759 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) {
1760   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1761   InstructionMark im(this);
1762   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1763   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1764   simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1765   emit_int8(0x2A);
1766   emit_operand(dst, src);
1767 }
1768 
1769 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
1770   NOT_LP64(assert(VM_Version::supports_sse(), ""));
1771   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1772   int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1773   emit_int8(0x2A);
1774   emit_int8((unsigned char)(0xC0 | encode));
1775 }
1776 
1777 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) {
1778   NOT_LP64(assert(VM_Version::supports_sse(), ""));
1779   InstructionMark im(this);
1780   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1781   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1782   simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1783   emit_int8(0x2A);
1784   emit_operand(dst, src);
1785 }
1786 
1787 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
1788   NOT_LP64(assert(VM_Version::supports_sse(), ""));
1789   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1790   int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1791   emit_int8(0x2A);
1792   emit_int8((unsigned char)(0xC0 | encode));
1793 }
1794 
1795 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
1796   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1797   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1798   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1799   emit_int8(0x5A);
1800   emit_int8((unsigned char)(0xC0 | encode));
1801 }
1802 
1803 void Assembler::cvtss2sd(XMMRegister dst, Address src) {
1804   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1805   InstructionMark im(this);
1806   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1807   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1808   simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1809   emit_int8(0x5A);
1810   emit_operand(dst, src);
1811 }
1812 
1813 
1814 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
1815   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1816   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1817   int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1818   emit_int8(0x2C);
1819   emit_int8((unsigned char)(0xC0 | encode));
1820 }
1821 
1822 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
1823   NOT_LP64(assert(VM_Version::supports_sse(), ""));
1824   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1825   int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1826   emit_int8(0x2C);
1827   emit_int8((unsigned char)(0xC0 | encode));
1828 }
1829 
1830 void Assembler::cvttpd2dq(XMMRegister dst, XMMRegister src) {
1831   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1832   int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
1833   InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
1834   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1835   emit_int8((unsigned char)0xE6);
1836   emit_int8((unsigned char)(0xC0 | encode));
1837 }
1838 
1839 void Assembler::decl(Address dst) {
1840   // Don't use it directly. Use MacroAssembler::decrement() instead.
1841   InstructionMark im(this);
1842   prefix(dst);
1843   emit_int8((unsigned char)0xFF);
1844   emit_operand(rcx, dst);
1845 }
1846 
1847 void Assembler::divsd(XMMRegister dst, Address src) {
1848   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1849   InstructionMark im(this);
1850   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1851   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1852   simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1853   emit_int8(0x5E);
1854   emit_operand(dst, src);
1855 }
1856 
1857 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
1858   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1859   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1860   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1861   emit_int8(0x5E);
1862   emit_int8((unsigned char)(0xC0 | encode));
1863 }
1864 
1865 void Assembler::divss(XMMRegister dst, Address src) {
1866   NOT_LP64(assert(VM_Version::supports_sse(), ""));
1867   InstructionMark im(this);
1868   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1869   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1870   simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1871   emit_int8(0x5E);
1872   emit_operand(dst, src);
1873 }
1874 
1875 void Assembler::divss(XMMRegister dst, XMMRegister src) {
1876   NOT_LP64(assert(VM_Version::supports_sse(), ""));
1877   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1878   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1879   emit_int8(0x5E);
1880   emit_int8((unsigned char)(0xC0 | encode));
1881 }
1882 
1883 void Assembler::emms() {
1884   NOT_LP64(assert(VM_Version::supports_mmx(), ""));
1885   emit_int8(0x0F);
1886   emit_int8(0x77);
1887 }
1888 
1889 void Assembler::hlt() {
1890   emit_int8((unsigned char)0xF4);
1891 }
1892 
1893 void Assembler::idivl(Register src) {
1894   int encode = prefix_and_encode(src->encoding());
1895   emit_int8((unsigned char)0xF7);
1896   emit_int8((unsigned char)(0xF8 | encode));
1897 }
1898 
1899 void Assembler::divl(Register src) { // Unsigned
1900   int encode = prefix_and_encode(src->encoding());
1901   emit_int8((unsigned char)0xF7);
1902   emit_int8((unsigned char)(0xF0 | encode));
1903 }
1904 
1905 void Assembler::imull(Register src) {
1906   int encode = prefix_and_encode(src->encoding());
1907   emit_int8((unsigned char)0xF7);
1908   emit_int8((unsigned char)(0xE8 | encode));
1909 }
1910 
1911 void Assembler::imull(Register dst, Register src) {
1912   int encode = prefix_and_encode(dst->encoding(), src->encoding());
1913   emit_int8(0x0F);
1914   emit_int8((unsigned char)0xAF);
1915   emit_int8((unsigned char)(0xC0 | encode));
1916 }
1917 
1918 
1919 void Assembler::imull(Register dst, Register src, int value) {
1920   int encode = prefix_and_encode(dst->encoding(), src->encoding());
1921   if (is8bit(value)) {
1922     emit_int8(0x6B);
1923     emit_int8((unsigned char)(0xC0 | encode));
1924     emit_int8(value & 0xFF);
1925   } else {
1926     emit_int8(0x69);
1927     emit_int8((unsigned char)(0xC0 | encode));
1928     emit_int32(value);
1929   }
1930 }
1931 
1932 void Assembler::imull(Register dst, Address src) {
1933   InstructionMark im(this);
1934   prefix(src, dst);
1935   emit_int8(0x0F);
1936   emit_int8((unsigned char) 0xAF);
1937   emit_operand(dst, src);
1938 }
1939 
1940 
1941 void Assembler::incl(Address dst) {
1942   // Don't use it directly. Use MacroAssembler::increment() instead.
1943   InstructionMark im(this);
1944   prefix(dst);
1945   emit_int8((unsigned char)0xFF);
1946   emit_operand(rax, dst);
1947 }
1948 
1949 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) {
1950   InstructionMark im(this);
1951   assert((0 <= cc) && (cc < 16), "illegal cc");
1952   if (L.is_bound()) {
1953     address dst = target(L);
1954     assert(dst != NULL, "jcc most probably wrong");
1955 
1956     const int short_size = 2;
1957     const int long_size = 6;
1958     intptr_t offs = (intptr_t)dst - (intptr_t)pc();
1959     if (maybe_short && is8bit(offs - short_size)) {
1960       // 0111 tttn #8-bit disp
1961       emit_int8(0x70 | cc);
1962       emit_int8((offs - short_size) & 0xFF);
1963     } else {
1964       // 0000 1111 1000 tttn #32-bit disp
1965       assert(is_simm32(offs - long_size),
1966              "must be 32bit offset (call4)");
1967       emit_int8(0x0F);
1968       emit_int8((unsigned char)(0x80 | cc));
1969       emit_int32(offs - long_size);
1970     }
1971   } else {
1972     // Note: could eliminate cond. jumps to this jump if condition
1973     //       is the same however, seems to be rather unlikely case.
1974     // Note: use jccb() if label to be bound is very close to get
1975     //       an 8-bit displacement
1976     L.add_patch_at(code(), locator());
1977     emit_int8(0x0F);
1978     emit_int8((unsigned char)(0x80 | cc));
1979     emit_int32(0);
1980   }
1981 }
1982 
1983 void Assembler::jccb(Condition cc, Label& L) {
1984   if (L.is_bound()) {
1985     const int short_size = 2;
1986     address entry = target(L);
1987 #ifdef ASSERT
1988     intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
1989     intptr_t delta = short_branch_delta();
1990     if (delta != 0) {
1991       dist += (dist < 0 ? (-delta) :delta);
1992     }
1993     assert(is8bit(dist), "Dispacement too large for a short jmp");
1994 #endif
1995     intptr_t offs = (intptr_t)entry - (intptr_t)pc();
1996     // 0111 tttn #8-bit disp
1997     emit_int8(0x70 | cc);
1998     emit_int8((offs - short_size) & 0xFF);
1999   } else {
2000     InstructionMark im(this);
2001     L.add_patch_at(code(), locator());
2002     emit_int8(0x70 | cc);
2003     emit_int8(0);
2004   }
2005 }
2006 
2007 void Assembler::jmp(Address adr) {
2008   InstructionMark im(this);
2009   prefix(adr);
2010   emit_int8((unsigned char)0xFF);
2011   emit_operand(rsp, adr);
2012 }
2013 
2014 void Assembler::jmp(Label& L, bool maybe_short) {
2015   if (L.is_bound()) {
2016     address entry = target(L);
2017     assert(entry != NULL, "jmp most probably wrong");
2018     InstructionMark im(this);
2019     const int short_size = 2;
2020     const int long_size = 5;
2021     intptr_t offs = entry - pc();
2022     if (maybe_short && is8bit(offs - short_size)) {
2023       emit_int8((unsigned char)0xEB);
2024       emit_int8((offs - short_size) & 0xFF);
2025     } else {
2026       emit_int8((unsigned char)0xE9);
2027       emit_int32(offs - long_size);
2028     }
2029   } else {
2030     // By default, forward jumps are always 32-bit displacements, since
2031     // we can't yet know where the label will be bound.  If you're sure that
2032     // the forward jump will not run beyond 256 bytes, use jmpb to
2033     // force an 8-bit displacement.
2034     InstructionMark im(this);
2035     L.add_patch_at(code(), locator());
2036     emit_int8((unsigned char)0xE9);
2037     emit_int32(0);
2038   }
2039 }
2040 
2041 void Assembler::jmp(Register entry) {
2042   int encode = prefix_and_encode(entry->encoding());
2043   emit_int8((unsigned char)0xFF);
2044   emit_int8((unsigned char)(0xE0 | encode));
2045 }
2046 
2047 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
2048   InstructionMark im(this);
2049   emit_int8((unsigned char)0xE9);
2050   assert(dest != NULL, "must have a target");
2051   intptr_t disp = dest - (pc() + sizeof(int32_t));
2052   assert(is_simm32(disp), "must be 32bit offset (jmp)");
2053   emit_data(disp, rspec.reloc(), call32_operand);
2054 }
2055 
2056 void Assembler::jmpb(Label& L) {
2057   if (L.is_bound()) {
2058     const int short_size = 2;
2059     address entry = target(L);
2060     assert(entry != NULL, "jmp most probably wrong");
2061 #ifdef ASSERT
2062     intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
2063     intptr_t delta = short_branch_delta();
2064     if (delta != 0) {
2065       dist += (dist < 0 ? (-delta) :delta);
2066     }
2067     assert(is8bit(dist), "Dispacement too large for a short jmp");
2068 #endif
2069     intptr_t offs = entry - pc();
2070     emit_int8((unsigned char)0xEB);
2071     emit_int8((offs - short_size) & 0xFF);
2072   } else {
2073     InstructionMark im(this);
2074     L.add_patch_at(code(), locator());
2075     emit_int8((unsigned char)0xEB);
2076     emit_int8(0);
2077   }
2078 }
2079 
2080 void Assembler::ldmxcsr( Address src) {
2081   NOT_LP64(assert(VM_Version::supports_sse(), ""));
2082   InstructionMark im(this);
2083   prefix(src);
2084   emit_int8(0x0F);
2085   emit_int8((unsigned char)0xAE);
2086   emit_operand(as_Register(2), src);
2087 }
2088 
2089 void Assembler::leal(Register dst, Address src) {
2090   InstructionMark im(this);
2091 #ifdef _LP64
2092   emit_int8(0x67); // addr32
2093   prefix(src, dst);
2094 #endif // LP64
2095   emit_int8((unsigned char)0x8D);
2096   emit_operand(dst, src);
2097 }
2098 
2099 void Assembler::lfence() {
2100   emit_int8(0x0F);
2101   emit_int8((unsigned char)0xAE);
2102   emit_int8((unsigned char)0xE8);
2103 }
2104 
2105 void Assembler::lock() {
2106   emit_int8((unsigned char)0xF0);
2107 }
2108 
2109 void Assembler::lzcntl(Register dst, Register src) {
2110   assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
2111   emit_int8((unsigned char)0xF3);
2112   int encode = prefix_and_encode(dst->encoding(), src->encoding());
2113   emit_int8(0x0F);
2114   emit_int8((unsigned char)0xBD);
2115   emit_int8((unsigned char)(0xC0 | encode));
2116 }
2117 
2118 // Emit mfence instruction
2119 void Assembler::mfence() {
2120   NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
2121   emit_int8(0x0F);
2122   emit_int8((unsigned char)0xAE);
2123   emit_int8((unsigned char)0xF0);
2124 }
2125 
2126 void Assembler::mov(Register dst, Register src) {
2127   LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2128 }
2129 
2130 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
2131   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2132   int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2133   InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2134   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2135   emit_int8(0x28);
2136   emit_int8((unsigned char)(0xC0 | encode));
2137 }
2138 
2139 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
2140   NOT_LP64(assert(VM_Version::supports_sse(), ""));
2141   int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2142   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2143   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2144   emit_int8(0x28);
2145   emit_int8((unsigned char)(0xC0 | encode));
2146 }
2147 
2148 void Assembler::movlhps(XMMRegister dst, XMMRegister src) {
2149   NOT_LP64(assert(VM_Version::supports_sse(), ""));
2150   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2151   int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2152   emit_int8(0x16);
2153   emit_int8((unsigned char)(0xC0 | encode));
2154 }
2155 
2156 void Assembler::movb(Register dst, Address src) {
2157   NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
2158   InstructionMark im(this);
2159   prefix(src, dst, true);
2160   emit_int8((unsigned char)0x8A);
2161   emit_operand(dst, src);
2162 }
2163 
2164 void Assembler::movddup(XMMRegister dst, XMMRegister src) {
2165   NOT_LP64(assert(VM_Version::supports_sse3(), ""));
2166   int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_128bit;
2167   InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2168   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2169   emit_int8(0x12);
2170   emit_int8(0xC0 | encode);
2171 }
2172 
2173 void Assembler::kmovbl(KRegister dst, Register src) {
2174   assert(VM_Version::supports_avx512dq(), "");
2175   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2176   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2177   emit_int8((unsigned char)0x92);
2178   emit_int8((unsigned char)(0xC0 | encode));
2179 }
2180 
2181 void Assembler::kmovbl(Register dst, KRegister src) {
2182   assert(VM_Version::supports_avx512dq(), "");
2183   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2184   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2185   emit_int8((unsigned char)0x93);
2186   emit_int8((unsigned char)(0xC0 | encode));
2187 }
2188 
2189 void Assembler::kmovwl(KRegister dst, Register src) {
2190   assert(VM_Version::supports_evex(), "");
2191   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2192   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2193   emit_int8((unsigned char)0x92);
2194   emit_int8((unsigned char)(0xC0 | encode));
2195 }
2196 
2197 void Assembler::kmovwl(Register dst, KRegister src) {
2198   assert(VM_Version::supports_evex(), "");
2199   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2200   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2201   emit_int8((unsigned char)0x93);
2202   emit_int8((unsigned char)(0xC0 | encode));
2203 }
2204 
2205 void Assembler::kmovdl(KRegister dst, Register src) {
2206   assert(VM_Version::supports_avx512bw(), "");
2207   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2208   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2209   emit_int8((unsigned char)0x92);
2210   emit_int8((unsigned char)(0xC0 | encode));
2211 }
2212 
2213 void Assembler::kmovdl(Register dst, KRegister src) {
2214   assert(VM_Version::supports_avx512bw(), "");
2215   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2216   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2217   emit_int8((unsigned char)0x93);
2218   emit_int8((unsigned char)(0xC0 | encode));
2219 }
2220 
2221 void Assembler::kmovql(KRegister dst, KRegister src) {
2222   assert(VM_Version::supports_avx512bw(), "");
2223   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2224   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2225   emit_int8((unsigned char)0x90);
2226   emit_int8((unsigned char)(0xC0 | encode));
2227 }
2228 
2229 void Assembler::kmovql(KRegister dst, Address src) {
2230   assert(VM_Version::supports_avx512bw(), "");
2231   InstructionMark im(this);
2232   InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2233   vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2234   emit_int8((unsigned char)0x90);
2235   emit_operand((Register)dst, src);
2236 }
2237 
2238 void Assembler::kmovql(Address dst, KRegister src) {
2239   assert(VM_Version::supports_avx512bw(), "");
2240   InstructionMark im(this);
2241   InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2242   vex_prefix(dst, 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2243   emit_int8((unsigned char)0x90);
2244   emit_operand((Register)src, dst);
2245 }
2246 
2247 void Assembler::kmovql(KRegister dst, Register src) {
2248   assert(VM_Version::supports_avx512bw(), "");
2249   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2250   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2251   emit_int8((unsigned char)0x92);
2252   emit_int8((unsigned char)(0xC0 | encode));
2253 }
2254 
2255 void Assembler::kmovql(Register dst, KRegister src) {
2256   assert(VM_Version::supports_avx512bw(), "");
2257   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2258   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2259   emit_int8((unsigned char)0x93);
2260   emit_int8((unsigned char)(0xC0 | encode));
2261 }
2262 
2263 // This instruction produces ZF or CF flags
2264 void Assembler::kortestbl(KRegister src1, KRegister src2) {
2265   assert(VM_Version::supports_avx512dq(), "");
2266   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2267   int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2268   emit_int8((unsigned char)0x98);
2269   emit_int8((unsigned char)(0xC0 | encode));
2270 }
2271 
2272 // This instruction produces ZF or CF flags
2273 void Assembler::kortestwl(KRegister src1, KRegister src2) {
2274   assert(VM_Version::supports_evex(), "");
2275   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2276   int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2277   emit_int8((unsigned char)0x98);
2278   emit_int8((unsigned char)(0xC0 | encode));
2279 }
2280 
2281 // This instruction produces ZF or CF flags
2282 void Assembler::kortestdl(KRegister src1, KRegister src2) {
2283   assert(VM_Version::supports_avx512bw(), "");
2284   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2285   int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2286   emit_int8((unsigned char)0x98);
2287   emit_int8((unsigned char)(0xC0 | encode));
2288 }
2289 
2290 // This instruction produces ZF or CF flags
2291 void Assembler::kortestql(KRegister src1, KRegister src2) {
2292   assert(VM_Version::supports_avx512bw(), "");
2293   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2294   int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2295   emit_int8((unsigned char)0x98);
2296   emit_int8((unsigned char)(0xC0 | encode));
2297 }
2298 
2299 void Assembler::movb(Address dst, int imm8) {
2300   InstructionMark im(this);
2301    prefix(dst);
2302   emit_int8((unsigned char)0xC6);
2303   emit_operand(rax, dst, 1);
2304   emit_int8(imm8);
2305 }
2306 
2307 
2308 void Assembler::movb(Address dst, Register src) {
2309   assert(src->has_byte_register(), "must have byte register");
2310   InstructionMark im(this);
2311   prefix(dst, src, true);
2312   emit_int8((unsigned char)0x88);
2313   emit_operand(src, dst);
2314 }
2315 
2316 void Assembler::movdl(XMMRegister dst, Register src) {
2317   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2318   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2319   int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2320   emit_int8(0x6E);
2321   emit_int8((unsigned char)(0xC0 | encode));
2322 }
2323 
2324 void Assembler::movdl(Register dst, XMMRegister src) {
2325   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2326   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2327   // swap src/dst to get correct prefix
2328   int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2329   emit_int8(0x7E);
2330   emit_int8((unsigned char)(0xC0 | encode));
2331 }
2332 
2333 void Assembler::movdl(XMMRegister dst, Address src) {
2334   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2335   InstructionMark im(this);
2336   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2337   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2338   simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2339   emit_int8(0x6E);
2340   emit_operand(dst, src);
2341 }
2342 
2343 void Assembler::movdl(Address dst, XMMRegister src) {
2344   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2345   InstructionMark im(this);
2346   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2347   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2348   simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2349   emit_int8(0x7E);
2350   emit_operand(src, dst);
2351 }
2352 
2353 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
2354   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2355   int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2356   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2357   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2358   emit_int8(0x6F);
2359   emit_int8((unsigned char)(0xC0 | encode));
2360 }
2361 
2362 void Assembler::movdqa(XMMRegister dst, Address src) {
2363   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2364   InstructionMark im(this);
2365   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2366   attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2367   simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2368   emit_int8(0x6F);
2369   emit_operand(dst, src);
2370 }
2371 
2372 void Assembler::movdqu(XMMRegister dst, Address src) {
2373   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2374   InstructionMark im(this);
2375   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2376   attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2377   simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2378   emit_int8(0x6F);
2379   emit_operand(dst, src);
2380 }
2381 
2382 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
2383   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2384   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2385   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2386   emit_int8(0x6F);
2387   emit_int8((unsigned char)(0xC0 | encode));
2388 }
2389 
2390 void Assembler::movdqu(Address dst, XMMRegister src) {
2391   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2392   InstructionMark im(this);
2393   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2394   attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2395   simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2396   emit_int8(0x7F);
2397   emit_operand(src, dst);
2398 }
2399 
2400 // Move Unaligned 256bit Vector
2401 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2402   assert(UseAVX > 0, "");
2403   InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2404   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2405   emit_int8(0x6F);
2406   emit_int8((unsigned char)(0xC0 | encode));
2407 }
2408 
2409 void Assembler::vmovdqu(XMMRegister dst, Address src) {
2410   assert(UseAVX > 0, "");
2411   InstructionMark im(this);
2412   InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2413   attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2414   vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2415   emit_int8(0x6F);
2416   emit_operand(dst, src);
2417 }
2418 
2419 void Assembler::vmovdqu(Address dst, XMMRegister src) {
2420   assert(UseAVX > 0, "");
2421   InstructionMark im(this);
2422   InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2423   attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2424   // swap src<->dst for encoding
2425   assert(src != xnoreg, "sanity");
2426   vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2427   emit_int8(0x7F);
2428   emit_operand(src, dst);
2429 }
2430 
2431 // Move Unaligned EVEX enabled Vector (programmable : 8,16,32,64)
2432 void Assembler::evmovdqub(XMMRegister dst, XMMRegister src, int vector_len) {
2433   assert(VM_Version::supports_evex(), "");
2434   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2435   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2436   emit_int8(0x6F);
2437   emit_int8((unsigned char)(0xC0 | encode));
2438 }
2439 
2440 void Assembler::evmovdqub(XMMRegister dst, Address src, int vector_len) {
2441   assert(VM_Version::supports_evex(), "");
2442   InstructionMark im(this);
2443   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2444   attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2445   vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2446   emit_int8(0x6F);
2447   emit_operand(dst, src);
2448 }
2449 
2450 void Assembler::evmovdqub(Address dst, XMMRegister src, int vector_len) {
2451   assert(VM_Version::supports_evex(), "");
2452   assert(src != xnoreg, "sanity");
2453   InstructionMark im(this);
2454   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2455   attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2456   vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2457   emit_int8(0x7F);
2458   emit_operand(src, dst);
2459 }
2460 
2461 void Assembler::evmovdquw(XMMRegister dst, XMMRegister src, int vector_len) {
2462   assert(VM_Version::supports_evex(), "");
2463   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2464   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2465   emit_int8(0x6F);
2466   emit_int8((unsigned char)(0xC0 | encode));
2467 }
2468 
2469 void Assembler::evmovdquw(XMMRegister dst, Address src, int vector_len) {
2470   assert(VM_Version::supports_evex(), "");
2471   InstructionMark im(this);
2472   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2473   attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2474   vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2475   emit_int8(0x6F);
2476   emit_operand(dst, src);
2477 }
2478 
2479 void Assembler::evmovdquw(Address dst, XMMRegister src, int vector_len) {
2480   assert(VM_Version::supports_evex(), "");
2481   assert(src != xnoreg, "sanity");
2482   InstructionMark im(this);
2483   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2484   attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2485   vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2486   emit_int8(0x7F);
2487   emit_operand(src, dst);
2488 }
2489 void Assembler::evmovdqul(XMMRegister dst, XMMRegister src, int vector_len) {
2490   assert(VM_Version::supports_evex(), "");
2491   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2492   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2493   emit_int8(0x6F);
2494   emit_int8((unsigned char)(0xC0 | encode));
2495 }
2496 
2497 void Assembler::evmovdqul(XMMRegister dst, Address src, int vector_len) {
2498   assert(VM_Version::supports_evex(), "");
2499   InstructionMark im(this);
2500   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false , /* uses_vl */ true);
2501   attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2502   vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2503   emit_int8(0x6F);
2504   emit_operand(dst, src);
2505 }
2506 
2507 void Assembler::evmovdqul(Address dst, XMMRegister src, int vector_len) {
2508   assert(VM_Version::supports_evex(), "");
2509   assert(src != xnoreg, "sanity");
2510   InstructionMark im(this);
2511   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2512   attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2513   vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2514   emit_int8(0x7F);
2515   emit_operand(src, dst);
2516 }
2517 
2518 void Assembler::evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) {
2519   assert(VM_Version::supports_evex(), "");
2520   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2521   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2522   emit_int8(0x6F);
2523   emit_int8((unsigned char)(0xC0 | encode));
2524 }
2525 
2526 void Assembler::evmovdquq(XMMRegister dst, Address src, int vector_len) {
2527   assert(VM_Version::supports_evex(), "");
2528   InstructionMark im(this);
2529   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2530   attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2531   vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2532   emit_int8(0x6F);
2533   emit_operand(dst, src);
2534 }
2535 
2536 void Assembler::evmovdquq(Address dst, XMMRegister src, int vector_len) {
2537   assert(VM_Version::supports_evex(), "");
2538   assert(src != xnoreg, "sanity");
2539   InstructionMark im(this);
2540   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2541   attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2542   vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2543   emit_int8(0x7F);
2544   emit_operand(src, dst);
2545 }
2546 
2547 // Uses zero extension on 64bit
2548 
2549 void Assembler::movl(Register dst, int32_t imm32) {
2550   int encode = prefix_and_encode(dst->encoding());
2551   emit_int8((unsigned char)(0xB8 | encode));
2552   emit_int32(imm32);
2553 }
2554 
2555 void Assembler::movl(Register dst, Register src) {
2556   int encode = prefix_and_encode(dst->encoding(), src->encoding());
2557   emit_int8((unsigned char)0x8B);
2558   emit_int8((unsigned char)(0xC0 | encode));
2559 }
2560 
2561 void Assembler::movl(Register dst, Address src) {
2562   InstructionMark im(this);
2563   prefix(src, dst);
2564   emit_int8((unsigned char)0x8B);
2565   emit_operand(dst, src);
2566 }
2567 
2568 void Assembler::movl(Address dst, int32_t imm32) {
2569   InstructionMark im(this);
2570   prefix(dst);
2571   emit_int8((unsigned char)0xC7);
2572   emit_operand(rax, dst, 4);
2573   emit_int32(imm32);
2574 }
2575 
2576 void Assembler::movl(Address dst, Register src) {
2577   InstructionMark im(this);
2578   prefix(dst, src);
2579   emit_int8((unsigned char)0x89);
2580   emit_operand(src, dst);
2581 }
2582 
2583 // New cpus require to use movsd and movss to avoid partial register stall
2584 // when loading from memory. But for old Opteron use movlpd instead of movsd.
2585 // The selection is done in MacroAssembler::movdbl() and movflt().
2586 void Assembler::movlpd(XMMRegister dst, Address src) {
2587   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2588   InstructionMark im(this);
2589   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2590   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2591   simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2592   emit_int8(0x12);
2593   emit_operand(dst, src);
2594 }
2595 
2596 void Assembler::movq( MMXRegister dst, Address src ) {
2597   assert( VM_Version::supports_mmx(), "" );
2598   emit_int8(0x0F);
2599   emit_int8(0x6F);
2600   emit_operand(dst, src);
2601 }
2602 
2603 void Assembler::movq( Address dst, MMXRegister src ) {
2604   assert( VM_Version::supports_mmx(), "" );
2605   emit_int8(0x0F);
2606   emit_int8(0x7F);
2607   // workaround gcc (3.2.1-7a) bug
2608   // In that version of gcc with only an emit_operand(MMX, Address)
2609   // gcc will tail jump and try and reverse the parameters completely
2610   // obliterating dst in the process. By having a version available
2611   // that doesn't need to swap the args at the tail jump the bug is
2612   // avoided.
2613   emit_operand(dst, src);
2614 }
2615 
2616 void Assembler::movq(XMMRegister dst, Address src) {
2617   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2618   InstructionMark im(this);
2619   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2620   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2621   simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2622   emit_int8(0x7E);
2623   emit_operand(dst, src);
2624 }
2625 
2626 void Assembler::movq(Address dst, XMMRegister src) {
2627   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2628   InstructionMark im(this);
2629   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2630   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2631   simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2632   emit_int8((unsigned char)0xD6);
2633   emit_operand(src, dst);
2634 }
2635 
2636 void Assembler::movsbl(Register dst, Address src) { // movsxb
2637   InstructionMark im(this);
2638   prefix(src, dst);
2639   emit_int8(0x0F);
2640   emit_int8((unsigned char)0xBE);
2641   emit_operand(dst, src);
2642 }
2643 
2644 void Assembler::movsbl(Register dst, Register src) { // movsxb
2645   NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2646   int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
2647   emit_int8(0x0F);
2648   emit_int8((unsigned char)0xBE);
2649   emit_int8((unsigned char)(0xC0 | encode));
2650 }
2651 
2652 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
2653   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2654   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2655   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2656   emit_int8(0x10);
2657   emit_int8((unsigned char)(0xC0 | encode));
2658 }
2659 
2660 void Assembler::movsd(XMMRegister dst, Address src) {
2661   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2662   InstructionMark im(this);
2663   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2664   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2665   simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2666   emit_int8(0x10);
2667   emit_operand(dst, src);
2668 }
2669 
2670 void Assembler::movsd(Address dst, XMMRegister src) {
2671   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2672   InstructionMark im(this);
2673   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2674   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2675   simd_prefix(src, xnoreg, dst, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2676   emit_int8(0x11);
2677   emit_operand(src, dst);
2678 }
2679 
2680 void Assembler::movss(XMMRegister dst, XMMRegister src) {
2681   NOT_LP64(assert(VM_Version::supports_sse(), ""));
2682   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2683   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2684   emit_int8(0x10);
2685   emit_int8((unsigned char)(0xC0 | encode));
2686 }
2687 
2688 void Assembler::movss(XMMRegister dst, Address src) {
2689   NOT_LP64(assert(VM_Version::supports_sse(), ""));
2690   InstructionMark im(this);
2691   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2692   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2693   simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2694   emit_int8(0x10);
2695   emit_operand(dst, src);
2696 }
2697 
2698 void Assembler::movss(Address dst, XMMRegister src) {
2699   NOT_LP64(assert(VM_Version::supports_sse(), ""));
2700   InstructionMark im(this);
2701   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2702   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2703   simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2704   emit_int8(0x11);
2705   emit_operand(src, dst);
2706 }
2707 
2708 void Assembler::movswl(Register dst, Address src) { // movsxw
2709   InstructionMark im(this);
2710   prefix(src, dst);
2711   emit_int8(0x0F);
2712   emit_int8((unsigned char)0xBF);
2713   emit_operand(dst, src);
2714 }
2715 
2716 void Assembler::movswl(Register dst, Register src) { // movsxw
2717   int encode = prefix_and_encode(dst->encoding(), src->encoding());
2718   emit_int8(0x0F);
2719   emit_int8((unsigned char)0xBF);
2720   emit_int8((unsigned char)(0xC0 | encode));
2721 }
2722 
2723 void Assembler::movw(Address dst, int imm16) {
2724   InstructionMark im(this);
2725 
2726   emit_int8(0x66); // switch to 16-bit mode
2727   prefix(dst);
2728   emit_int8((unsigned char)0xC7);
2729   emit_operand(rax, dst, 2);
2730   emit_int16(imm16);
2731 }
2732 
2733 void Assembler::movw(Register dst, Address src) {
2734   InstructionMark im(this);
2735   emit_int8(0x66);
2736   prefix(src, dst);
2737   emit_int8((unsigned char)0x8B);
2738   emit_operand(dst, src);
2739 }
2740 
2741 void Assembler::movw(Address dst, Register src) {
2742   InstructionMark im(this);
2743   emit_int8(0x66);
2744   prefix(dst, src);
2745   emit_int8((unsigned char)0x89);
2746   emit_operand(src, dst);
2747 }
2748 
2749 void Assembler::movzbl(Register dst, Address src) { // movzxb
2750   InstructionMark im(this);
2751   prefix(src, dst);
2752   emit_int8(0x0F);
2753   emit_int8((unsigned char)0xB6);
2754   emit_operand(dst, src);
2755 }
2756 
2757 void Assembler::movzbl(Register dst, Register src) { // movzxb
2758   NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2759   int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
2760   emit_int8(0x0F);
2761   emit_int8((unsigned char)0xB6);
2762   emit_int8(0xC0 | encode);
2763 }
2764 
2765 void Assembler::movzwl(Register dst, Address src) { // movzxw
2766   InstructionMark im(this);
2767   prefix(src, dst);
2768   emit_int8(0x0F);
2769   emit_int8((unsigned char)0xB7);
2770   emit_operand(dst, src);
2771 }
2772 
2773 void Assembler::movzwl(Register dst, Register src) { // movzxw
2774   int encode = prefix_and_encode(dst->encoding(), src->encoding());
2775   emit_int8(0x0F);
2776   emit_int8((unsigned char)0xB7);
2777   emit_int8(0xC0 | encode);
2778 }
2779 
2780 void Assembler::mull(Address src) {
2781   InstructionMark im(this);
2782   prefix(src);
2783   emit_int8((unsigned char)0xF7);
2784   emit_operand(rsp, src);
2785 }
2786 
2787 void Assembler::mull(Register src) {
2788   int encode = prefix_and_encode(src->encoding());
2789   emit_int8((unsigned char)0xF7);
2790   emit_int8((unsigned char)(0xE0 | encode));
2791 }
2792 
2793 void Assembler::mulsd(XMMRegister dst, Address src) {
2794   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2795   InstructionMark im(this);
2796   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2797   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2798   simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2799   emit_int8(0x59);
2800   emit_operand(dst, src);
2801 }
2802 
2803 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
2804   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2805   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2806   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2807   emit_int8(0x59);
2808   emit_int8((unsigned char)(0xC0 | encode));
2809 }
2810 
2811 void Assembler::mulss(XMMRegister dst, Address src) {
2812   NOT_LP64(assert(VM_Version::supports_sse(), ""));
2813   InstructionMark im(this);
2814   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2815   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2816   simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2817   emit_int8(0x59);
2818   emit_operand(dst, src);
2819 }
2820 
2821 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
2822   NOT_LP64(assert(VM_Version::supports_sse(), ""));
2823   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2824   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2825   emit_int8(0x59);
2826   emit_int8((unsigned char)(0xC0 | encode));
2827 }
2828 
2829 void Assembler::negl(Register dst) {
2830   int encode = prefix_and_encode(dst->encoding());
2831   emit_int8((unsigned char)0xF7);
2832   emit_int8((unsigned char)(0xD8 | encode));
2833 }
2834 
2835 void Assembler::nop(int i) {
2836 #ifdef ASSERT
2837   assert(i > 0, " ");
2838   // The fancy nops aren't currently recognized by debuggers making it a
2839   // pain to disassemble code while debugging. If asserts are on clearly
2840   // speed is not an issue so simply use the single byte traditional nop
2841   // to do alignment.
2842 
2843   for (; i > 0 ; i--) emit_int8((unsigned char)0x90);
2844   return;
2845 
2846 #endif // ASSERT
2847 
2848   if (UseAddressNop && VM_Version::is_intel()) {
2849     //
2850     // Using multi-bytes nops "0x0F 0x1F [address]" for Intel
2851     //  1: 0x90
2852     //  2: 0x66 0x90
2853     //  3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2854     //  4: 0x0F 0x1F 0x40 0x00
2855     //  5: 0x0F 0x1F 0x44 0x00 0x00
2856     //  6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2857     //  7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2858     //  8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2859     //  9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2860     // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2861     // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2862 
2863     // The rest coding is Intel specific - don't use consecutive address nops
2864 
2865     // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2866     // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2867     // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2868     // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2869 
2870     while(i >= 15) {
2871       // For Intel don't generate consecutive addess nops (mix with regular nops)
2872       i -= 15;
2873       emit_int8(0x66);   // size prefix
2874       emit_int8(0x66);   // size prefix
2875       emit_int8(0x66);   // size prefix
2876       addr_nop_8();
2877       emit_int8(0x66);   // size prefix
2878       emit_int8(0x66);   // size prefix
2879       emit_int8(0x66);   // size prefix
2880       emit_int8((unsigned char)0x90);
2881                          // nop
2882     }
2883     switch (i) {
2884       case 14:
2885         emit_int8(0x66); // size prefix
2886       case 13:
2887         emit_int8(0x66); // size prefix
2888       case 12:
2889         addr_nop_8();
2890         emit_int8(0x66); // size prefix
2891         emit_int8(0x66); // size prefix
2892         emit_int8(0x66); // size prefix
2893         emit_int8((unsigned char)0x90);
2894                          // nop
2895         break;
2896       case 11:
2897         emit_int8(0x66); // size prefix
2898       case 10:
2899         emit_int8(0x66); // size prefix
2900       case 9:
2901         emit_int8(0x66); // size prefix
2902       case 8:
2903         addr_nop_8();
2904         break;
2905       case 7:
2906         addr_nop_7();
2907         break;
2908       case 6:
2909         emit_int8(0x66); // size prefix
2910       case 5:
2911         addr_nop_5();
2912         break;
2913       case 4:
2914         addr_nop_4();
2915         break;
2916       case 3:
2917         // Don't use "0x0F 0x1F 0x00" - need patching safe padding
2918         emit_int8(0x66); // size prefix
2919       case 2:
2920         emit_int8(0x66); // size prefix
2921       case 1:
2922         emit_int8((unsigned char)0x90);
2923                          // nop
2924         break;
2925       default:
2926         assert(i == 0, " ");
2927     }
2928     return;
2929   }
2930   if (UseAddressNop && VM_Version::is_amd()) {
2931     //
2932     // Using multi-bytes nops "0x0F 0x1F [address]" for AMD.
2933     //  1: 0x90
2934     //  2: 0x66 0x90
2935     //  3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2936     //  4: 0x0F 0x1F 0x40 0x00
2937     //  5: 0x0F 0x1F 0x44 0x00 0x00
2938     //  6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2939     //  7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2940     //  8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2941     //  9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2942     // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2943     // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2944 
2945     // The rest coding is AMD specific - use consecutive address nops
2946 
2947     // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2948     // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2949     // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2950     // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2951     // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2952     //     Size prefixes (0x66) are added for larger sizes
2953 
2954     while(i >= 22) {
2955       i -= 11;
2956       emit_int8(0x66); // size prefix
2957       emit_int8(0x66); // size prefix
2958       emit_int8(0x66); // size prefix
2959       addr_nop_8();
2960     }
2961     // Generate first nop for size between 21-12
2962     switch (i) {
2963       case 21:
2964         i -= 1;
2965         emit_int8(0x66); // size prefix
2966       case 20:
2967       case 19:
2968         i -= 1;
2969         emit_int8(0x66); // size prefix
2970       case 18:
2971       case 17:
2972         i -= 1;
2973         emit_int8(0x66); // size prefix
2974       case 16:
2975       case 15:
2976         i -= 8;
2977         addr_nop_8();
2978         break;
2979       case 14:
2980       case 13:
2981         i -= 7;
2982         addr_nop_7();
2983         break;
2984       case 12:
2985         i -= 6;
2986         emit_int8(0x66); // size prefix
2987         addr_nop_5();
2988         break;
2989       default:
2990         assert(i < 12, " ");
2991     }
2992 
2993     // Generate second nop for size between 11-1
2994     switch (i) {
2995       case 11:
2996         emit_int8(0x66); // size prefix
2997       case 10:
2998         emit_int8(0x66); // size prefix
2999       case 9:
3000         emit_int8(0x66); // size prefix
3001       case 8:
3002         addr_nop_8();
3003         break;
3004       case 7:
3005         addr_nop_7();
3006         break;
3007       case 6:
3008         emit_int8(0x66); // size prefix
3009       case 5:
3010         addr_nop_5();
3011         break;
3012       case 4:
3013         addr_nop_4();
3014         break;
3015       case 3:
3016         // Don't use "0x0F 0x1F 0x00" - need patching safe padding
3017         emit_int8(0x66); // size prefix
3018       case 2:
3019         emit_int8(0x66); // size prefix
3020       case 1:
3021         emit_int8((unsigned char)0x90);
3022                          // nop
3023         break;
3024       default:
3025         assert(i == 0, " ");
3026     }
3027     return;
3028   }
3029 
3030   // Using nops with size prefixes "0x66 0x90".
3031   // From AMD Optimization Guide:
3032   //  1: 0x90
3033   //  2: 0x66 0x90
3034   //  3: 0x66 0x66 0x90
3035   //  4: 0x66 0x66 0x66 0x90
3036   //  5: 0x66 0x66 0x90 0x66 0x90
3037   //  6: 0x66 0x66 0x90 0x66 0x66 0x90
3038   //  7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90
3039   //  8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90
3040   //  9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
3041   // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
3042   //
3043   while(i > 12) {
3044     i -= 4;
3045     emit_int8(0x66); // size prefix
3046     emit_int8(0x66);
3047     emit_int8(0x66);
3048     emit_int8((unsigned char)0x90);
3049                      // nop
3050   }
3051   // 1 - 12 nops
3052   if(i > 8) {
3053     if(i > 9) {
3054       i -= 1;
3055       emit_int8(0x66);
3056     }
3057     i -= 3;
3058     emit_int8(0x66);
3059     emit_int8(0x66);
3060     emit_int8((unsigned char)0x90);
3061   }
3062   // 1 - 8 nops
3063   if(i > 4) {
3064     if(i > 6) {
3065       i -= 1;
3066       emit_int8(0x66);
3067     }
3068     i -= 3;
3069     emit_int8(0x66);
3070     emit_int8(0x66);
3071     emit_int8((unsigned char)0x90);
3072   }
3073   switch (i) {
3074     case 4:
3075       emit_int8(0x66);
3076     case 3:
3077       emit_int8(0x66);
3078     case 2:
3079       emit_int8(0x66);
3080     case 1:
3081       emit_int8((unsigned char)0x90);
3082       break;
3083     default:
3084       assert(i == 0, " ");
3085   }
3086 }
3087 
3088 void Assembler::notl(Register dst) {
3089   int encode = prefix_and_encode(dst->encoding());
3090   emit_int8((unsigned char)0xF7);
3091   emit_int8((unsigned char)(0xD0 | encode));
3092 }
3093 
3094 void Assembler::orl(Address dst, int32_t imm32) {
3095   InstructionMark im(this);
3096   prefix(dst);
3097   emit_arith_operand(0x81, rcx, dst, imm32);
3098 }
3099 
3100 void Assembler::orl(Register dst, int32_t imm32) {
3101   prefix(dst);
3102   emit_arith(0x81, 0xC8, dst, imm32);
3103 }
3104 
3105 void Assembler::orl(Register dst, Address src) {
3106   InstructionMark im(this);
3107   prefix(src, dst);
3108   emit_int8(0x0B);
3109   emit_operand(dst, src);
3110 }
3111 
3112 void Assembler::orl(Register dst, Register src) {
3113   (void) prefix_and_encode(dst->encoding(), src->encoding());
3114   emit_arith(0x0B, 0xC0, dst, src);
3115 }
3116 
3117 void Assembler::orl(Address dst, Register src) {
3118   InstructionMark im(this);
3119   prefix(dst, src);
3120   emit_int8(0x09);
3121   emit_operand(src, dst);
3122 }
3123 
3124 void Assembler::packuswb(XMMRegister dst, Address src) {
3125   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3126   assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3127   InstructionMark im(this);
3128   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3129   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3130   simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3131   emit_int8(0x67);
3132   emit_operand(dst, src);
3133 }
3134 
3135 void Assembler::packuswb(XMMRegister dst, XMMRegister src) {
3136   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3137   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3138   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3139   emit_int8(0x67);
3140   emit_int8((unsigned char)(0xC0 | encode));
3141 }
3142 
3143 void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3144   assert(UseAVX > 0, "some form of AVX must be enabled");
3145   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3146   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3147   int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3148   emit_int8(0x67);
3149   emit_int8((unsigned char)(0xC0 | encode));
3150 }
3151 
3152 void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len) {
3153   assert(VM_Version::supports_avx2(), "");
3154   InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3155   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3156   emit_int8(0x00);
3157   emit_int8(0xC0 | encode);
3158   emit_int8(imm8);
3159 }
3160 
3161 void Assembler::pause() {
3162   emit_int8((unsigned char)0xF3);
3163   emit_int8((unsigned char)0x90);
3164 }
3165 
3166 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3167   assert(VM_Version::supports_sse4_2(), "");
3168   InstructionMark im(this);
3169   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3170   simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3171   emit_int8(0x61);
3172   emit_operand(dst, src);
3173   emit_int8(imm8);
3174 }
3175 
3176 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3177   assert(VM_Version::supports_sse4_2(), "");
3178   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3179   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3180   emit_int8(0x61);
3181   emit_int8((unsigned char)(0xC0 | encode));
3182   emit_int8(imm8);
3183 }
3184 
3185 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3186 void Assembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
3187   assert(VM_Version::supports_sse2(), "");
3188   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3189   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3190   emit_int8(0x74);
3191   emit_int8((unsigned char)(0xC0 | encode));
3192 }
3193 
3194 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3195 void Assembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3196   assert(VM_Version::supports_avx(), "");
3197   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3198   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3199   int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3200   emit_int8(0x74);
3201   emit_int8((unsigned char)(0xC0 | encode));
3202 }
3203 
3204 // In this context, kdst is written the mask used to process the equal components
3205 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3206   assert(VM_Version::supports_avx512bw(), "");
3207   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3208   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3209   int encode = vex_prefix_and_encode(kdst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3210   emit_int8(0x74);
3211   emit_int8((unsigned char)(0xC0 | encode));
3212 }
3213 
3214 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3215   assert(VM_Version::supports_avx512bw(), "");
3216   InstructionMark im(this);
3217   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3218   attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3219   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3220   int dst_enc = kdst->encoding();
3221   vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3222   emit_int8(0x74);
3223   emit_operand(as_Register(dst_enc), src);
3224 }
3225 
3226 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3227 void Assembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3228   assert(VM_Version::supports_sse2(), "");
3229   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3230   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3231   emit_int8(0x75);
3232   emit_int8((unsigned char)(0xC0 | encode));
3233 }
3234 
3235 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3236 void Assembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3237   assert(VM_Version::supports_avx(), "");
3238   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3239   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3240   int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3241   emit_int8(0x75);
3242   emit_int8((unsigned char)(0xC0 | encode));
3243 }
3244 
3245 // In this context, kdst is written the mask used to process the equal components
3246 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3247   assert(VM_Version::supports_avx512bw(), "");
3248   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3249   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3250   int encode = vex_prefix_and_encode(kdst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3251   emit_int8(0x75);
3252   emit_int8((unsigned char)(0xC0 | encode));
3253 }
3254 
3255 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3256   assert(VM_Version::supports_avx512bw(), "");
3257   InstructionMark im(this);
3258   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3259   attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3260   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3261   int dst_enc = kdst->encoding();
3262   vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3263   emit_int8(0x75);
3264   emit_operand(as_Register(dst_enc), src);
3265 }
3266 
3267 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3268 void Assembler::pcmpeqd(XMMRegister dst, XMMRegister src) {
3269   assert(VM_Version::supports_sse2(), "");
3270   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3271   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3272   emit_int8(0x76);
3273   emit_int8((unsigned char)(0xC0 | encode));
3274 }
3275 
3276 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3277 void Assembler::vpcmpeqd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3278   assert(VM_Version::supports_avx(), "");
3279   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3280   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3281   int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3282   emit_int8(0x76);
3283   emit_int8((unsigned char)(0xC0 | encode));
3284 }
3285 
3286 // In this context, kdst is written the mask used to process the equal components
3287 void Assembler::evpcmpeqd(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3288   assert(VM_Version::supports_evex(), "");
3289   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3290   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3291   int encode = vex_prefix_and_encode(kdst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3292   emit_int8(0x76);
3293   emit_int8((unsigned char)(0xC0 | encode));
3294 }
3295 
3296 void Assembler::evpcmpeqd(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3297   assert(VM_Version::supports_evex(), "");
3298   InstructionMark im(this);
3299   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3300   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3301   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3302   int dst_enc = kdst->encoding();
3303   vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3304   emit_int8(0x76);
3305   emit_operand(as_Register(dst_enc), src);
3306 }
3307 
3308 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3309 void Assembler::pcmpeqq(XMMRegister dst, XMMRegister src) {
3310   assert(VM_Version::supports_sse4_1(), "");
3311   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3312   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3313   emit_int8(0x29);
3314   emit_int8((unsigned char)(0xC0 | encode));
3315 }
3316 
3317 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3318 void Assembler::vpcmpeqq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3319   assert(VM_Version::supports_avx(), "");
3320   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3321   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3322   int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3323   emit_int8(0x29);
3324   emit_int8((unsigned char)(0xC0 | encode));
3325 }
3326 
3327 // In this context, kdst is written the mask used to process the equal components
3328 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3329   assert(VM_Version::supports_evex(), "");
3330   InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3331   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3332   int encode = vex_prefix_and_encode(kdst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3333   emit_int8(0x29);
3334   emit_int8((unsigned char)(0xC0 | encode));
3335 }
3336 
3337 // In this context, kdst is written the mask used to process the equal components
3338 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3339   assert(VM_Version::supports_evex(), "");
3340   InstructionMark im(this);
3341   InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3342   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
3343   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3344   int dst_enc = kdst->encoding();
3345   vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3346   emit_int8(0x29);
3347   emit_operand(as_Register(dst_enc), src);
3348 }
3349 
3350 void Assembler::pmovmskb(Register dst, XMMRegister src) {
3351   assert(VM_Version::supports_sse2(), "");
3352   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3353   int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3354   emit_int8((unsigned char)0xD7);
3355   emit_int8((unsigned char)(0xC0 | encode));
3356 }
3357 
3358 void Assembler::vpmovmskb(Register dst, XMMRegister src) {
3359   assert(VM_Version::supports_avx2(), "");
3360   InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3361   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3362   emit_int8((unsigned char)0xD7);
3363   emit_int8((unsigned char)(0xC0 | encode));
3364 }
3365 
3366 void Assembler::pextrd(Register dst, XMMRegister src, int imm8) {
3367   assert(VM_Version::supports_sse4_1(), "");
3368   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3369   int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3370   emit_int8(0x16);
3371   emit_int8((unsigned char)(0xC0 | encode));
3372   emit_int8(imm8);
3373 }
3374 
3375 void Assembler::pextrd(Address dst, XMMRegister src, int imm8) {
3376   assert(VM_Version::supports_sse4_1(), "");
3377   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3378   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3379   simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3380   emit_int8(0x16);
3381   emit_operand(src, dst);
3382   emit_int8(imm8);
3383 }
3384 
3385 void Assembler::pextrq(Register dst, XMMRegister src, int imm8) {
3386   assert(VM_Version::supports_sse4_1(), "");
3387   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3388   int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3389   emit_int8(0x16);
3390   emit_int8((unsigned char)(0xC0 | encode));
3391   emit_int8(imm8);
3392 }
3393 
3394 void Assembler::pextrq(Address dst, XMMRegister src, int imm8) {
3395   assert(VM_Version::supports_sse4_1(), "");
3396   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3397   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3398   simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3399   emit_int8(0x16);
3400   emit_operand(src, dst);
3401   emit_int8(imm8);
3402 }
3403 
3404 void Assembler::pextrw(Register dst, XMMRegister src, int imm8) {
3405   assert(VM_Version::supports_sse2(), "");
3406   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3407   int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3408   emit_int8((unsigned char)0xC5);
3409   emit_int8((unsigned char)(0xC0 | encode));
3410   emit_int8(imm8);
3411 }
3412 
3413 void Assembler::pextrw(Address dst, XMMRegister src, int imm8) {
3414   assert(VM_Version::supports_sse4_1(), "");
3415   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3416   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
3417   simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3418   emit_int8((unsigned char)0x15);
3419   emit_operand(src, dst);
3420   emit_int8(imm8);
3421 }
3422 
3423 void Assembler::pextrb(Address dst, XMMRegister src, int imm8) {
3424   assert(VM_Version::supports_sse4_1(), "");
3425   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3426   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
3427   simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3428   emit_int8(0x14);
3429   emit_operand(src, dst);
3430   emit_int8(imm8);
3431 }
3432 
3433 void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) {
3434   assert(VM_Version::supports_sse4_1(), "");
3435   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3436   int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3437   emit_int8(0x22);
3438   emit_int8((unsigned char)(0xC0 | encode));
3439   emit_int8(imm8);
3440 }
3441 
3442 void Assembler::pinsrd(XMMRegister dst, Address src, int imm8) {
3443   assert(VM_Version::supports_sse4_1(), "");
3444   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3445   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3446   simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3447   emit_int8(0x22);
3448   emit_operand(dst,src);
3449   emit_int8(imm8);
3450 }
3451 
3452 void Assembler::pinsrq(XMMRegister dst, Register src, int imm8) {
3453   assert(VM_Version::supports_sse4_1(), "");
3454   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3455   int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3456   emit_int8(0x22);
3457   emit_int8((unsigned char)(0xC0 | encode));
3458   emit_int8(imm8);
3459 }
3460 
3461 void Assembler::pinsrq(XMMRegister dst, Address src, int imm8) {
3462   assert(VM_Version::supports_sse4_1(), "");
3463   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3464   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3465   simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3466   emit_int8(0x22);
3467   emit_operand(dst, src);
3468   emit_int8(imm8);
3469 }
3470 
3471 void Assembler::pinsrw(XMMRegister dst, Register src, int imm8) {
3472   assert(VM_Version::supports_sse2(), "");
3473   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3474   int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3475   emit_int8((unsigned char)0xC4);
3476   emit_int8((unsigned char)(0xC0 | encode));
3477   emit_int8(imm8);
3478 }
3479 
3480 void Assembler::pinsrw(XMMRegister dst, Address src, int imm8) {
3481   assert(VM_Version::supports_sse2(), "");
3482   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3483   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
3484   simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3485   emit_int8((unsigned char)0xC4);
3486   emit_operand(dst, src);
3487   emit_int8(imm8);
3488 }
3489 
3490 void Assembler::pinsrb(XMMRegister dst, Address src, int imm8) {
3491   assert(VM_Version::supports_sse4_1(), "");
3492   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3493   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
3494   simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3495   emit_int8(0x20);
3496   emit_operand(dst, src);
3497   emit_int8(imm8);
3498 }
3499 
3500 void Assembler::pmovzxbw(XMMRegister dst, Address src) {
3501   assert(VM_Version::supports_sse4_1(), "");
3502   InstructionMark im(this);
3503   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3504   attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3505   simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3506   emit_int8(0x30);
3507   emit_operand(dst, src);
3508 }
3509 
3510 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3511   assert(VM_Version::supports_sse4_1(), "");
3512   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3513   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3514   emit_int8(0x30);
3515   emit_int8((unsigned char)(0xC0 | encode));
3516 }
3517 
3518 void Assembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
3519   assert(VM_Version::supports_avx(), "");
3520   InstructionMark im(this);
3521   assert(dst != xnoreg, "sanity");
3522   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3523   attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3524   vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3525   emit_int8(0x30);
3526   emit_operand(dst, src);
3527 }
3528 
3529 // generic
3530 void Assembler::pop(Register dst) {
3531   int encode = prefix_and_encode(dst->encoding());
3532   emit_int8(0x58 | encode);
3533 }
3534 
3535 void Assembler::popcntl(Register dst, Address src) {
3536   assert(VM_Version::supports_popcnt(), "must support");
3537   InstructionMark im(this);
3538   emit_int8((unsigned char)0xF3);
3539   prefix(src, dst);
3540   emit_int8(0x0F);
3541   emit_int8((unsigned char)0xB8);
3542   emit_operand(dst, src);
3543 }
3544 
3545 void Assembler::popcntl(Register dst, Register src) {
3546   assert(VM_Version::supports_popcnt(), "must support");
3547   emit_int8((unsigned char)0xF3);
3548   int encode = prefix_and_encode(dst->encoding(), src->encoding());
3549   emit_int8(0x0F);
3550   emit_int8((unsigned char)0xB8);
3551   emit_int8((unsigned char)(0xC0 | encode));
3552 }
3553 
3554 void Assembler::popf() {
3555   emit_int8((unsigned char)0x9D);
3556 }
3557 
3558 #ifndef _LP64 // no 32bit push/pop on amd64
3559 void Assembler::popl(Address dst) {
3560   // NOTE: this will adjust stack by 8byte on 64bits
3561   InstructionMark im(this);
3562   prefix(dst);
3563   emit_int8((unsigned char)0x8F);
3564   emit_operand(rax, dst);
3565 }
3566 #endif
3567 
3568 void Assembler::prefetch_prefix(Address src) {
3569   prefix(src);
3570   emit_int8(0x0F);
3571 }
3572 
3573 void Assembler::prefetchnta(Address src) {
3574   NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3575   InstructionMark im(this);
3576   prefetch_prefix(src);
3577   emit_int8(0x18);
3578   emit_operand(rax, src); // 0, src
3579 }
3580 
3581 void Assembler::prefetchr(Address src) {
3582   assert(VM_Version::supports_3dnow_prefetch(), "must support");
3583   InstructionMark im(this);
3584   prefetch_prefix(src);
3585   emit_int8(0x0D);
3586   emit_operand(rax, src); // 0, src
3587 }
3588 
3589 void Assembler::prefetcht0(Address src) {
3590   NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3591   InstructionMark im(this);
3592   prefetch_prefix(src);
3593   emit_int8(0x18);
3594   emit_operand(rcx, src); // 1, src
3595 }
3596 
3597 void Assembler::prefetcht1(Address src) {
3598   NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3599   InstructionMark im(this);
3600   prefetch_prefix(src);
3601   emit_int8(0x18);
3602   emit_operand(rdx, src); // 2, src
3603 }
3604 
3605 void Assembler::prefetcht2(Address src) {
3606   NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3607   InstructionMark im(this);
3608   prefetch_prefix(src);
3609   emit_int8(0x18);
3610   emit_operand(rbx, src); // 3, src
3611 }
3612 
3613 void Assembler::prefetchw(Address src) {
3614   assert(VM_Version::supports_3dnow_prefetch(), "must support");
3615   InstructionMark im(this);
3616   prefetch_prefix(src);
3617   emit_int8(0x0D);
3618   emit_operand(rcx, src); // 1, src
3619 }
3620 
3621 void Assembler::prefix(Prefix p) {
3622   emit_int8(p);
3623 }
3624 
3625 void Assembler::pshufb(XMMRegister dst, XMMRegister src) {
3626   assert(VM_Version::supports_ssse3(), "");
3627   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3628   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3629   emit_int8(0x00);
3630   emit_int8((unsigned char)(0xC0 | encode));
3631 }
3632 
3633 void Assembler::pshufb(XMMRegister dst, Address src) {
3634   assert(VM_Version::supports_ssse3(), "");
3635   InstructionMark im(this);
3636   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3637   attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3638   simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3639   emit_int8(0x00);
3640   emit_operand(dst, src);
3641 }
3642 
3643 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
3644   assert(isByte(mode), "invalid value");
3645   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3646   int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_128bit;
3647   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3648   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3649   emit_int8(0x70);
3650   emit_int8((unsigned char)(0xC0 | encode));
3651   emit_int8(mode & 0xFF);
3652 }
3653 
3654 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
3655   assert(isByte(mode), "invalid value");
3656   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3657   assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3658   InstructionMark im(this);
3659   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3660   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3661   simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3662   emit_int8(0x70);
3663   emit_operand(dst, src);
3664   emit_int8(mode & 0xFF);
3665 }
3666 
3667 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
3668   assert(isByte(mode), "invalid value");
3669   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3670   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3671   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3672   emit_int8(0x70);
3673   emit_int8((unsigned char)(0xC0 | encode));
3674   emit_int8(mode & 0xFF);
3675 }
3676 
3677 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
3678   assert(isByte(mode), "invalid value");
3679   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3680   assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3681   InstructionMark im(this);
3682   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3683   attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3684   simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3685   emit_int8(0x70);
3686   emit_operand(dst, src);
3687   emit_int8(mode & 0xFF);
3688 }
3689 
3690 void Assembler::psrldq(XMMRegister dst, int shift) {
3691   // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
3692   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3693   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3694   // XMM3 is for /3 encoding: 66 0F 73 /3 ib
3695   int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3696   emit_int8(0x73);
3697   emit_int8((unsigned char)(0xC0 | encode));
3698   emit_int8(shift);
3699 }
3700 
3701 void Assembler::pslldq(XMMRegister dst, int shift) {
3702   // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
3703   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3704   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3705   // XMM7 is for /7 encoding: 66 0F 73 /7 ib
3706   int encode = simd_prefix_and_encode(xmm7, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3707   emit_int8(0x73);
3708   emit_int8((unsigned char)(0xC0 | encode));
3709   emit_int8(shift);
3710 }
3711 
3712 void Assembler::ptest(XMMRegister dst, Address src) {
3713   assert(VM_Version::supports_sse4_1(), "");
3714   assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3715   InstructionMark im(this);
3716   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3717   simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3718   emit_int8(0x17);
3719   emit_operand(dst, src);
3720 }
3721 
3722 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
3723   assert(VM_Version::supports_sse4_1(), "");
3724   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3725   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3726   emit_int8(0x17);
3727   emit_int8((unsigned char)(0xC0 | encode));
3728 }
3729 
3730 void Assembler::vptest(XMMRegister dst, Address src) {
3731   assert(VM_Version::supports_avx(), "");
3732   InstructionMark im(this);
3733   InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3734   assert(dst != xnoreg, "sanity");
3735   // swap src<->dst for encoding
3736   vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3737   emit_int8(0x17);
3738   emit_operand(dst, src);
3739 }
3740 
3741 void Assembler::vptest(XMMRegister dst, XMMRegister src) {
3742   assert(VM_Version::supports_avx(), "");
3743   InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3744   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3745   emit_int8(0x17);
3746   emit_int8((unsigned char)(0xC0 | encode));
3747 }
3748 
3749 void Assembler::punpcklbw(XMMRegister dst, Address src) {
3750   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3751   assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3752   InstructionMark im(this);
3753   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ false, /* uses_vl */ true);
3754   attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3755   simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3756   emit_int8(0x60);
3757   emit_operand(dst, src);
3758 }
3759 
3760 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
3761   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3762   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ false, /* uses_vl */ true);
3763   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3764   emit_int8(0x60);
3765   emit_int8((unsigned char)(0xC0 | encode));
3766 }
3767 
3768 void Assembler::punpckldq(XMMRegister dst, Address src) {
3769   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3770   assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3771   InstructionMark im(this);
3772   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3773   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3774   simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3775   emit_int8(0x62);
3776   emit_operand(dst, src);
3777 }
3778 
3779 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) {
3780   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3781   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3782   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3783   emit_int8(0x62);
3784   emit_int8((unsigned char)(0xC0 | encode));
3785 }
3786 
3787 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) {
3788   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3789   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3790   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3791   emit_int8(0x6C);
3792   emit_int8((unsigned char)(0xC0 | encode));
3793 }
3794 
3795 void Assembler::push(int32_t imm32) {
3796   // in 64bits we push 64bits onto the stack but only
3797   // take a 32bit immediate
3798   emit_int8(0x68);
3799   emit_int32(imm32);
3800 }
3801 
3802 void Assembler::push(Register src) {
3803   int encode = prefix_and_encode(src->encoding());
3804 
3805   emit_int8(0x50 | encode);
3806 }
3807 
3808 void Assembler::pushf() {
3809   emit_int8((unsigned char)0x9C);
3810 }
3811 
3812 #ifndef _LP64 // no 32bit push/pop on amd64
3813 void Assembler::pushl(Address src) {
3814   // Note this will push 64bit on 64bit
3815   InstructionMark im(this);
3816   prefix(src);
3817   emit_int8((unsigned char)0xFF);
3818   emit_operand(rsi, src);
3819 }
3820 #endif
3821 
3822 void Assembler::rcll(Register dst, int imm8) {
3823   assert(isShiftCount(imm8), "illegal shift count");
3824   int encode = prefix_and_encode(dst->encoding());
3825   if (imm8 == 1) {
3826     emit_int8((unsigned char)0xD1);
3827     emit_int8((unsigned char)(0xD0 | encode));
3828   } else {
3829     emit_int8((unsigned char)0xC1);
3830     emit_int8((unsigned char)0xD0 | encode);
3831     emit_int8(imm8);
3832   }
3833 }
3834 
3835 void Assembler::rcpps(XMMRegister dst, XMMRegister src) {
3836   NOT_LP64(assert(VM_Version::supports_sse(), ""));
3837   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3838   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
3839   emit_int8(0x53);
3840   emit_int8((unsigned char)(0xC0 | encode));
3841 }
3842 
3843 void Assembler::rcpss(XMMRegister dst, XMMRegister src) {
3844   NOT_LP64(assert(VM_Version::supports_sse(), ""));
3845   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3846   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3847   emit_int8(0x53);
3848   emit_int8((unsigned char)(0xC0 | encode));
3849 }
3850 
3851 void Assembler::rdtsc() {
3852   emit_int8((unsigned char)0x0F);
3853   emit_int8((unsigned char)0x31);
3854 }
3855 
3856 // copies data from [esi] to [edi] using rcx pointer sized words
3857 // generic
3858 void Assembler::rep_mov() {
3859   emit_int8((unsigned char)0xF3);
3860   // MOVSQ
3861   LP64_ONLY(prefix(REX_W));
3862   emit_int8((unsigned char)0xA5);
3863 }
3864 
3865 // sets rcx bytes with rax, value at [edi]
3866 void Assembler::rep_stosb() {
3867   emit_int8((unsigned char)0xF3); // REP
3868   LP64_ONLY(prefix(REX_W));
3869   emit_int8((unsigned char)0xAA); // STOSB
3870 }
3871 
3872 // sets rcx pointer sized words with rax, value at [edi]
3873 // generic
3874 void Assembler::rep_stos() {
3875   emit_int8((unsigned char)0xF3); // REP
3876   LP64_ONLY(prefix(REX_W));       // LP64:STOSQ, LP32:STOSD
3877   emit_int8((unsigned char)0xAB);
3878 }
3879 
3880 // scans rcx pointer sized words at [edi] for occurance of rax,
3881 // generic
3882 void Assembler::repne_scan() { // repne_scan
3883   emit_int8((unsigned char)0xF2);
3884   // SCASQ
3885   LP64_ONLY(prefix(REX_W));
3886   emit_int8((unsigned char)0xAF);
3887 }
3888 
3889 #ifdef _LP64
3890 // scans rcx 4 byte words at [edi] for occurance of rax,
3891 // generic
3892 void Assembler::repne_scanl() { // repne_scan
3893   emit_int8((unsigned char)0xF2);
3894   // SCASL
3895   emit_int8((unsigned char)0xAF);
3896 }
3897 #endif
3898 
3899 void Assembler::ret(int imm16) {
3900   if (imm16 == 0) {
3901     emit_int8((unsigned char)0xC3);
3902   } else {
3903     emit_int8((unsigned char)0xC2);
3904     emit_int16(imm16);
3905   }
3906 }
3907 
3908 void Assembler::sahf() {
3909 #ifdef _LP64
3910   // Not supported in 64bit mode
3911   ShouldNotReachHere();
3912 #endif
3913   emit_int8((unsigned char)0x9E);
3914 }
3915 
3916 void Assembler::sarl(Register dst, int imm8) {
3917   int encode = prefix_and_encode(dst->encoding());
3918   assert(isShiftCount(imm8), "illegal shift count");
3919   if (imm8 == 1) {
3920     emit_int8((unsigned char)0xD1);
3921     emit_int8((unsigned char)(0xF8 | encode));
3922   } else {
3923     emit_int8((unsigned char)0xC1);
3924     emit_int8((unsigned char)(0xF8 | encode));
3925     emit_int8(imm8);
3926   }
3927 }
3928 
3929 void Assembler::sarl(Register dst) {
3930   int encode = prefix_and_encode(dst->encoding());
3931   emit_int8((unsigned char)0xD3);
3932   emit_int8((unsigned char)(0xF8 | encode));
3933 }
3934 
3935 void Assembler::sbbl(Address dst, int32_t imm32) {
3936   InstructionMark im(this);
3937   prefix(dst);
3938   emit_arith_operand(0x81, rbx, dst, imm32);
3939 }
3940 
3941 void Assembler::sbbl(Register dst, int32_t imm32) {
3942   prefix(dst);
3943   emit_arith(0x81, 0xD8, dst, imm32);
3944 }
3945 
3946 
3947 void Assembler::sbbl(Register dst, Address src) {
3948   InstructionMark im(this);
3949   prefix(src, dst);
3950   emit_int8(0x1B);
3951   emit_operand(dst, src);
3952 }
3953 
3954 void Assembler::sbbl(Register dst, Register src) {
3955   (void) prefix_and_encode(dst->encoding(), src->encoding());
3956   emit_arith(0x1B, 0xC0, dst, src);
3957 }
3958 
3959 void Assembler::setb(Condition cc, Register dst) {
3960   assert(0 <= cc && cc < 16, "illegal cc");
3961   int encode = prefix_and_encode(dst->encoding(), true);
3962   emit_int8(0x0F);
3963   emit_int8((unsigned char)0x90 | cc);
3964   emit_int8((unsigned char)(0xC0 | encode));
3965 }
3966 
3967 void Assembler::palignr(XMMRegister dst, XMMRegister src, int imm8) {
3968   assert(VM_Version::supports_ssse3(), "");
3969   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ false);
3970   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3971   emit_int8((unsigned char)0x0F);
3972   emit_int8((unsigned char)(0xC0 | encode));
3973   emit_int8(imm8);
3974 }
3975 
3976 void Assembler::pblendw(XMMRegister dst, XMMRegister src, int imm8) {
3977   assert(VM_Version::supports_sse4_1(), "");
3978   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3979   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3980   emit_int8((unsigned char)0x0E);
3981   emit_int8((unsigned char)(0xC0 | encode));
3982   emit_int8(imm8);
3983 }
3984 
3985 void Assembler::sha1rnds4(XMMRegister dst, XMMRegister src, int imm8) {
3986   assert(VM_Version::supports_sha(), "");
3987   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3988   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_3A, &attributes);
3989   emit_int8((unsigned char)0xCC);
3990   emit_int8((unsigned char)(0xC0 | encode));
3991   emit_int8((unsigned char)imm8);
3992 }
3993 
3994 void Assembler::sha1nexte(XMMRegister dst, XMMRegister src) {
3995   assert(VM_Version::supports_sha(), "");
3996   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3997   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
3998   emit_int8((unsigned char)0xC8);
3999   emit_int8((unsigned char)(0xC0 | encode));
4000 }
4001 
4002 void Assembler::sha1msg1(XMMRegister dst, XMMRegister src) {
4003   assert(VM_Version::supports_sha(), "");
4004   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4005   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4006   emit_int8((unsigned char)0xC9);
4007   emit_int8((unsigned char)(0xC0 | encode));
4008 }
4009 
4010 void Assembler::sha1msg2(XMMRegister dst, XMMRegister src) {
4011   assert(VM_Version::supports_sha(), "");
4012   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4013   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4014   emit_int8((unsigned char)0xCA);
4015   emit_int8((unsigned char)(0xC0 | encode));
4016 }
4017 
4018 // xmm0 is implicit additional source to this instruction.
4019 void Assembler::sha256rnds2(XMMRegister dst, XMMRegister src) {
4020   assert(VM_Version::supports_sha(), "");
4021   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4022   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4023   emit_int8((unsigned char)0xCB);
4024   emit_int8((unsigned char)(0xC0 | encode));
4025 }
4026 
4027 void Assembler::sha256msg1(XMMRegister dst, XMMRegister src) {
4028   assert(VM_Version::supports_sha(), "");
4029   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4030   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4031   emit_int8((unsigned char)0xCC);
4032   emit_int8((unsigned char)(0xC0 | encode));
4033 }
4034 
4035 void Assembler::sha256msg2(XMMRegister dst, XMMRegister src) {
4036   assert(VM_Version::supports_sha(), "");
4037   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4038   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4039   emit_int8((unsigned char)0xCD);
4040   emit_int8((unsigned char)(0xC0 | encode));
4041 }
4042 
4043 
4044 void Assembler::shll(Register dst, int imm8) {
4045   assert(isShiftCount(imm8), "illegal shift count");
4046   int encode = prefix_and_encode(dst->encoding());
4047   if (imm8 == 1 ) {
4048     emit_int8((unsigned char)0xD1);
4049     emit_int8((unsigned char)(0xE0 | encode));
4050   } else {
4051     emit_int8((unsigned char)0xC1);
4052     emit_int8((unsigned char)(0xE0 | encode));
4053     emit_int8(imm8);
4054   }
4055 }
4056 
4057 void Assembler::shll(Register dst) {
4058   int encode = prefix_and_encode(dst->encoding());
4059   emit_int8((unsigned char)0xD3);
4060   emit_int8((unsigned char)(0xE0 | encode));
4061 }
4062 
4063 void Assembler::shrl(Register dst, int imm8) {
4064   assert(isShiftCount(imm8), "illegal shift count");
4065   int encode = prefix_and_encode(dst->encoding());
4066   emit_int8((unsigned char)0xC1);
4067   emit_int8((unsigned char)(0xE8 | encode));
4068   emit_int8(imm8);
4069 }
4070 
4071 void Assembler::shrl(Register dst) {
4072   int encode = prefix_and_encode(dst->encoding());
4073   emit_int8((unsigned char)0xD3);
4074   emit_int8((unsigned char)(0xE8 | encode));
4075 }
4076 
4077 // copies a single word from [esi] to [edi]
4078 void Assembler::smovl() {
4079   emit_int8((unsigned char)0xA5);
4080 }
4081 
4082 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
4083   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4084   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4085   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4086   emit_int8(0x51);
4087   emit_int8((unsigned char)(0xC0 | encode));
4088 }
4089 
4090 void Assembler::sqrtsd(XMMRegister dst, Address src) {
4091   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4092   InstructionMark im(this);
4093   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4094   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4095   simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4096   emit_int8(0x51);
4097   emit_operand(dst, src);
4098 }
4099 
4100 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
4101   NOT_LP64(assert(VM_Version::supports_sse(), ""));
4102   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4103   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4104   emit_int8(0x51);
4105   emit_int8((unsigned char)(0xC0 | encode));
4106 }
4107 
4108 void Assembler::std() {
4109   emit_int8((unsigned char)0xFD);
4110 }
4111 
4112 void Assembler::sqrtss(XMMRegister dst, Address src) {
4113   NOT_LP64(assert(VM_Version::supports_sse(), ""));
4114   InstructionMark im(this);
4115   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4116   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4117   simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4118   emit_int8(0x51);
4119   emit_operand(dst, src);
4120 }
4121 
4122 void Assembler::stmxcsr( Address dst) {
4123   NOT_LP64(assert(VM_Version::supports_sse(), ""));
4124   InstructionMark im(this);
4125   prefix(dst);
4126   emit_int8(0x0F);
4127   emit_int8((unsigned char)0xAE);
4128   emit_operand(as_Register(3), dst);
4129 }
4130 
4131 void Assembler::subl(Address dst, int32_t imm32) {
4132   InstructionMark im(this);
4133   prefix(dst);
4134   emit_arith_operand(0x81, rbp, dst, imm32);
4135 }
4136 
4137 void Assembler::subl(Address dst, Register src) {
4138   InstructionMark im(this);
4139   prefix(dst, src);
4140   emit_int8(0x29);
4141   emit_operand(src, dst);
4142 }
4143 
4144 void Assembler::subl(Register dst, int32_t imm32) {
4145   prefix(dst);
4146   emit_arith(0x81, 0xE8, dst, imm32);
4147 }
4148 
4149 // Force generation of a 4 byte immediate value even if it fits into 8bit
4150 void Assembler::subl_imm32(Register dst, int32_t imm32) {
4151   prefix(dst);
4152   emit_arith_imm32(0x81, 0xE8, dst, imm32);
4153 }
4154 
4155 void Assembler::subl(Register dst, Address src) {
4156   InstructionMark im(this);
4157   prefix(src, dst);
4158   emit_int8(0x2B);
4159   emit_operand(dst, src);
4160 }
4161 
4162 void Assembler::subl(Register dst, Register src) {
4163   (void) prefix_and_encode(dst->encoding(), src->encoding());
4164   emit_arith(0x2B, 0xC0, dst, src);
4165 }
4166 
4167 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
4168   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4169   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4170   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4171   emit_int8(0x5C);
4172   emit_int8((unsigned char)(0xC0 | encode));
4173 }
4174 
4175 void Assembler::subsd(XMMRegister dst, Address src) {
4176   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4177   InstructionMark im(this);
4178   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4179   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4180   simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4181   emit_int8(0x5C);
4182   emit_operand(dst, src);
4183 }
4184 
4185 void Assembler::subss(XMMRegister dst, XMMRegister src) {
4186   NOT_LP64(assert(VM_Version::supports_sse(), ""));
4187   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false , /* uses_vl */ false);
4188   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4189   emit_int8(0x5C);
4190   emit_int8((unsigned char)(0xC0 | encode));
4191 }
4192 
4193 void Assembler::subss(XMMRegister dst, Address src) {
4194   NOT_LP64(assert(VM_Version::supports_sse(), ""));
4195   InstructionMark im(this);
4196   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4197   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4198   simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4199   emit_int8(0x5C);
4200   emit_operand(dst, src);
4201 }
4202 
4203 void Assembler::testb(Register dst, int imm8) {
4204   NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
4205   (void) prefix_and_encode(dst->encoding(), true);
4206   emit_arith_b(0xF6, 0xC0, dst, imm8);
4207 }
4208 
4209 void Assembler::testb(Address dst, int imm8) {
4210   InstructionMark im(this);
4211   prefix(dst);
4212   emit_int8((unsigned char)0xF6);
4213   emit_operand(rax, dst, 1);
4214   emit_int8(imm8);
4215 }
4216 
4217 void Assembler::testl(Register dst, int32_t imm32) {
4218   // not using emit_arith because test
4219   // doesn't support sign-extension of
4220   // 8bit operands
4221   int encode = dst->encoding();
4222   if (encode == 0) {
4223     emit_int8((unsigned char)0xA9);
4224   } else {
4225     encode = prefix_and_encode(encode);
4226     emit_int8((unsigned char)0xF7);
4227     emit_int8((unsigned char)(0xC0 | encode));
4228   }
4229   emit_int32(imm32);
4230 }
4231 
4232 void Assembler::testl(Register dst, Register src) {
4233   (void) prefix_and_encode(dst->encoding(), src->encoding());
4234   emit_arith(0x85, 0xC0, dst, src);
4235 }
4236 
4237 void Assembler::testl(Register dst, Address src) {
4238   InstructionMark im(this);
4239   prefix(src, dst);
4240   emit_int8((unsigned char)0x85);
4241   emit_operand(dst, src);
4242 }
4243 
4244 void Assembler::tzcntl(Register dst, Register src) {
4245   assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
4246   emit_int8((unsigned char)0xF3);
4247   int encode = prefix_and_encode(dst->encoding(), src->encoding());
4248   emit_int8(0x0F);
4249   emit_int8((unsigned char)0xBC);
4250   emit_int8((unsigned char)0xC0 | encode);
4251 }
4252 
4253 void Assembler::tzcntq(Register dst, Register src) {
4254   assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
4255   emit_int8((unsigned char)0xF3);
4256   int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4257   emit_int8(0x0F);
4258   emit_int8((unsigned char)0xBC);
4259   emit_int8((unsigned char)(0xC0 | encode));
4260 }
4261 
4262 void Assembler::ucomisd(XMMRegister dst, Address src) {
4263   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4264   InstructionMark im(this);
4265   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4266   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4267   simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4268   emit_int8(0x2E);
4269   emit_operand(dst, src);
4270 }
4271 
4272 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
4273   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4274   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4275   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4276   emit_int8(0x2E);
4277   emit_int8((unsigned char)(0xC0 | encode));
4278 }
4279 
4280 void Assembler::ucomiss(XMMRegister dst, Address src) {
4281   NOT_LP64(assert(VM_Version::supports_sse(), ""));
4282   InstructionMark im(this);
4283   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4284   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4285   simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4286   emit_int8(0x2E);
4287   emit_operand(dst, src);
4288 }
4289 
4290 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
4291   NOT_LP64(assert(VM_Version::supports_sse(), ""));
4292   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4293   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4294   emit_int8(0x2E);
4295   emit_int8((unsigned char)(0xC0 | encode));
4296 }
4297 
4298 void Assembler::xabort(int8_t imm8) {
4299   emit_int8((unsigned char)0xC6);
4300   emit_int8((unsigned char)0xF8);
4301   emit_int8((unsigned char)(imm8 & 0xFF));
4302 }
4303 
4304 void Assembler::xaddl(Address dst, Register src) {
4305   InstructionMark im(this);
4306   prefix(dst, src);
4307   emit_int8(0x0F);
4308   emit_int8((unsigned char)0xC1);
4309   emit_operand(src, dst);
4310 }
4311 
4312 void Assembler::xbegin(Label& abort, relocInfo::relocType rtype) {
4313   InstructionMark im(this);
4314   relocate(rtype);
4315   if (abort.is_bound()) {
4316     address entry = target(abort);
4317     assert(entry != NULL, "abort entry NULL");
4318     intptr_t offset = entry - pc();
4319     emit_int8((unsigned char)0xC7);
4320     emit_int8((unsigned char)0xF8);
4321     emit_int32(offset - 6); // 2 opcode + 4 address
4322   } else {
4323     abort.add_patch_at(code(), locator());
4324     emit_int8((unsigned char)0xC7);
4325     emit_int8((unsigned char)0xF8);
4326     emit_int32(0);
4327   }
4328 }
4329 
4330 void Assembler::xchgl(Register dst, Address src) { // xchg
4331   InstructionMark im(this);
4332   prefix(src, dst);
4333   emit_int8((unsigned char)0x87);
4334   emit_operand(dst, src);
4335 }
4336 
4337 void Assembler::xchgl(Register dst, Register src) {
4338   int encode = prefix_and_encode(dst->encoding(), src->encoding());
4339   emit_int8((unsigned char)0x87);
4340   emit_int8((unsigned char)(0xC0 | encode));
4341 }
4342 
4343 void Assembler::xend() {
4344   emit_int8((unsigned char)0x0F);
4345   emit_int8((unsigned char)0x01);
4346   emit_int8((unsigned char)0xD5);
4347 }
4348 
4349 void Assembler::xgetbv() {
4350   emit_int8(0x0F);
4351   emit_int8(0x01);
4352   emit_int8((unsigned char)0xD0);
4353 }
4354 
4355 void Assembler::xorl(Register dst, int32_t imm32) {
4356   prefix(dst);
4357   emit_arith(0x81, 0xF0, dst, imm32);
4358 }
4359 
4360 void Assembler::xorl(Register dst, Address src) {
4361   InstructionMark im(this);
4362   prefix(src, dst);
4363   emit_int8(0x33);
4364   emit_operand(dst, src);
4365 }
4366 
4367 void Assembler::xorl(Register dst, Register src) {
4368   (void) prefix_and_encode(dst->encoding(), src->encoding());
4369   emit_arith(0x33, 0xC0, dst, src);
4370 }
4371 
4372 void Assembler::xorb(Register dst, Address src) {
4373   InstructionMark im(this);
4374   prefix(src, dst);
4375   emit_int8(0x32);
4376   emit_operand(dst, src);
4377 }
4378 
4379 // AVX 3-operands scalar float-point arithmetic instructions
4380 
4381 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) {
4382   assert(VM_Version::supports_avx(), "");
4383   InstructionMark im(this);
4384   InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4385   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4386   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4387   vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4388   emit_int8(0x58);
4389   emit_operand(dst, src);
4390 }
4391 
4392 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4393   assert(VM_Version::supports_avx(), "");
4394   InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4395   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4396   int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4397   emit_int8(0x58);
4398   emit_int8((unsigned char)(0xC0 | encode));
4399 }
4400 
4401 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) {
4402   assert(VM_Version::supports_avx(), "");
4403   InstructionMark im(this);
4404   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4405   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4406   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4407   vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4408   emit_int8(0x58);
4409   emit_operand(dst, src);
4410 }
4411 
4412 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4413   assert(VM_Version::supports_avx(), "");
4414   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4415   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4416   int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4417   emit_int8(0x58);
4418   emit_int8((unsigned char)(0xC0 | encode));
4419 }
4420 
4421 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) {
4422   assert(VM_Version::supports_avx(), "");
4423   InstructionMark im(this);
4424   InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4425   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4426   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4427   vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4428   emit_int8(0x5E);
4429   emit_operand(dst, src);
4430 }
4431 
4432 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4433   assert(VM_Version::supports_avx(), "");
4434   InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4435   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4436   int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4437   emit_int8(0x5E);
4438   emit_int8((unsigned char)(0xC0 | encode));
4439 }
4440 
4441 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) {
4442   assert(VM_Version::supports_avx(), "");
4443   InstructionMark im(this);
4444   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4445   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4446   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4447   vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4448   emit_int8(0x5E);
4449   emit_operand(dst, src);
4450 }
4451 
4452 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4453   assert(VM_Version::supports_avx(), "");
4454   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4455   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4456   int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4457   emit_int8(0x5E);
4458   emit_int8((unsigned char)(0xC0 | encode));
4459 }
4460 
4461 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) {
4462   assert(VM_Version::supports_avx(), "");
4463   InstructionMark im(this);
4464   InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4465   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4466   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4467   vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4468   emit_int8(0x59);
4469   emit_operand(dst, src);
4470 }
4471 
4472 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4473   assert(VM_Version::supports_avx(), "");
4474   InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4475   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4476   int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4477   emit_int8(0x59);
4478   emit_int8((unsigned char)(0xC0 | encode));
4479 }
4480 
4481 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) {
4482   assert(VM_Version::supports_avx(), "");
4483   InstructionMark im(this);
4484   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4485   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4486   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4487   vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4488   emit_int8(0x59);
4489   emit_operand(dst, src);
4490 }
4491 
4492 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4493   assert(VM_Version::supports_avx(), "");
4494   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4495   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4496   int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4497   emit_int8(0x59);
4498   emit_int8((unsigned char)(0xC0 | encode));
4499 }
4500 
4501 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) {
4502   assert(VM_Version::supports_avx(), "");
4503   InstructionMark im(this);
4504   InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4505   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4506   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4507   vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4508   emit_int8(0x5C);
4509   emit_operand(dst, src);
4510 }
4511 
4512 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4513   assert(VM_Version::supports_avx(), "");
4514   InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4515   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4516   int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4517   emit_int8(0x5C);
4518   emit_int8((unsigned char)(0xC0 | encode));
4519 }
4520 
4521 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) {
4522   assert(VM_Version::supports_avx(), "");
4523   InstructionMark im(this);
4524   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4525   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4526   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4527   vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4528   emit_int8(0x5C);
4529   emit_operand(dst, src);
4530 }
4531 
4532 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4533   assert(VM_Version::supports_avx(), "");
4534   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4535   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4536   int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4537   emit_int8(0x5C);
4538   emit_int8((unsigned char)(0xC0 | encode));
4539 }
4540 
4541 //====================VECTOR ARITHMETIC=====================================
4542 
4543 // Float-point vector arithmetic
4544 
4545 void Assembler::addpd(XMMRegister dst, XMMRegister src) {
4546   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4547   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4548   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4549   emit_int8(0x58);
4550   emit_int8((unsigned char)(0xC0 | encode));
4551 }
4552 
4553 void Assembler::addpd(XMMRegister dst, Address src) {
4554   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4555   InstructionMark im(this);
4556   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4557   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4558   simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4559   emit_int8(0x58);
4560   emit_operand(dst, src);
4561 }
4562 
4563 
4564 void Assembler::addps(XMMRegister dst, XMMRegister src) {
4565   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4566   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4567   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4568   emit_int8(0x58);
4569   emit_int8((unsigned char)(0xC0 | encode));
4570 }
4571 
4572 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4573   assert(VM_Version::supports_avx(), "");
4574   InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4575   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4576   int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4577   emit_int8(0x58);
4578   emit_int8((unsigned char)(0xC0 | encode));
4579 }
4580 
4581 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4582   assert(VM_Version::supports_avx(), "");
4583   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4584   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4585   int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4586   emit_int8(0x58);
4587   emit_int8((unsigned char)(0xC0 | encode));
4588 }
4589 
4590 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4591   assert(VM_Version::supports_avx(), "");
4592   InstructionMark im(this);
4593   InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4594   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4595   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4596   vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4597   emit_int8(0x58);
4598   emit_operand(dst, src);
4599 }
4600 
4601 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4602   assert(VM_Version::supports_avx(), "");
4603   InstructionMark im(this);
4604   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4605   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4606   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4607   vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4608   emit_int8(0x58);
4609   emit_operand(dst, src);
4610 }
4611 
4612 void Assembler::subpd(XMMRegister dst, XMMRegister src) {
4613   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4614   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4615   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4616   emit_int8(0x5C);
4617   emit_int8((unsigned char)(0xC0 | encode));
4618 }
4619 
4620 void Assembler::subps(XMMRegister dst, XMMRegister src) {
4621   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4622   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4623   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4624   emit_int8(0x5C);
4625   emit_int8((unsigned char)(0xC0 | encode));
4626 }
4627 
4628 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4629   assert(VM_Version::supports_avx(), "");
4630   InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4631   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4632   int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4633   emit_int8(0x5C);
4634   emit_int8((unsigned char)(0xC0 | encode));
4635 }
4636 
4637 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4638   assert(VM_Version::supports_avx(), "");
4639   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4640   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4641   int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4642   emit_int8(0x5C);
4643   emit_int8((unsigned char)(0xC0 | encode));
4644 }
4645 
4646 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4647   assert(VM_Version::supports_avx(), "");
4648   InstructionMark im(this);
4649   InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4650   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4651   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4652   vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4653   emit_int8(0x5C);
4654   emit_operand(dst, src);
4655 }
4656 
4657 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4658   assert(VM_Version::supports_avx(), "");
4659   InstructionMark im(this);
4660   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4661   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4662   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4663   vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4664   emit_int8(0x5C);
4665   emit_operand(dst, src);
4666 }
4667 
4668 void Assembler::mulpd(XMMRegister dst, XMMRegister src) {
4669   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4670   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4671   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4672   emit_int8(0x59);
4673   emit_int8((unsigned char)(0xC0 | encode));
4674 }
4675 
4676 void Assembler::mulpd(XMMRegister dst, Address src) {
4677   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4678   InstructionMark im(this);
4679   InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4680   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4681   simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4682   emit_int8(0x59);
4683   emit_operand(dst, src);
4684 }
4685 
4686 void Assembler::mulps(XMMRegister dst, XMMRegister src) {
4687   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4688   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4689   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4690   emit_int8(0x59);
4691   emit_int8((unsigned char)(0xC0 | encode));
4692 }
4693 
4694 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4695   assert(VM_Version::supports_avx(), "");
4696   InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4697   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4698   int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4699   emit_int8(0x59);
4700   emit_int8((unsigned char)(0xC0 | encode));
4701 }
4702 
4703 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4704   assert(VM_Version::supports_avx(), "");
4705   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4706   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4707   int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4708   emit_int8(0x59);
4709   emit_int8((unsigned char)(0xC0 | encode));
4710 }
4711 
4712 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4713   assert(VM_Version::supports_avx(), "");
4714   InstructionMark im(this);
4715   InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4716   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4717   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4718   vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4719   emit_int8(0x59);
4720   emit_operand(dst, src);
4721 }
4722 
4723 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4724   assert(VM_Version::supports_avx(), "");
4725   InstructionMark im(this);
4726   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4727   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4728   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4729   vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4730   emit_int8(0x59);
4731   emit_operand(dst, src);
4732 }
4733 
4734 void Assembler::divpd(XMMRegister dst, XMMRegister src) {
4735   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4736   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4737   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4738   emit_int8(0x5E);
4739   emit_int8((unsigned char)(0xC0 | encode));
4740 }
4741 
4742 void Assembler::divps(XMMRegister dst, XMMRegister src) {
4743   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4744   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4745   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4746   emit_int8(0x5E);
4747   emit_int8((unsigned char)(0xC0 | encode));
4748 }
4749 
4750 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4751   assert(VM_Version::supports_avx(), "");
4752   InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4753   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4754   int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4755   emit_int8(0x5E);
4756   emit_int8((unsigned char)(0xC0 | encode));
4757 }
4758 
4759 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4760   assert(VM_Version::supports_avx(), "");
4761   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4762   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4763   int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4764   emit_int8(0x5E);
4765   emit_int8((unsigned char)(0xC0 | encode));
4766 }
4767 
4768 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4769   assert(VM_Version::supports_avx(), "");
4770   InstructionMark im(this);
4771   InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4772   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4773   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4774   vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4775   emit_int8(0x5E);
4776   emit_operand(dst, src);
4777 }
4778 
4779 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4780   assert(VM_Version::supports_avx(), "");
4781   InstructionMark im(this);
4782   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4783   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4784   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4785   vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4786   emit_int8(0x5E);
4787   emit_operand(dst, src);
4788 }
4789 
4790 void Assembler::vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len) {
4791   assert(VM_Version::supports_avx(), "");
4792   InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4793   int nds_enc = 0;
4794   int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4795   emit_int8(0x51);
4796   emit_int8((unsigned char)(0xC0 | encode));
4797 }
4798 
4799 void Assembler::vsqrtpd(XMMRegister dst, Address src, int vector_len) {
4800   assert(VM_Version::supports_avx(), "");
4801   InstructionMark im(this);
4802   InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4803   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4804   vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4805   emit_int8(0x51);
4806   emit_operand(dst, src);
4807 }
4808 
4809 void Assembler::andpd(XMMRegister dst, XMMRegister src) {
4810   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4811   InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4812   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4813   emit_int8(0x54);
4814   emit_int8((unsigned char)(0xC0 | encode));
4815 }
4816 
4817 void Assembler::andps(XMMRegister dst, XMMRegister src) {
4818   NOT_LP64(assert(VM_Version::supports_sse(), ""));
4819   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4820   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4821   emit_int8(0x54);
4822   emit_int8((unsigned char)(0xC0 | encode));
4823 }
4824 
4825 void Assembler::andps(XMMRegister dst, Address src) {
4826   NOT_LP64(assert(VM_Version::supports_sse(), ""));
4827   InstructionMark im(this);
4828   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4829   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4830   simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4831   emit_int8(0x54);
4832   emit_operand(dst, src);
4833 }
4834 
4835 void Assembler::andpd(XMMRegister dst, Address src) {
4836   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4837   InstructionMark im(this);
4838   InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4839   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4840   simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4841   emit_int8(0x54);
4842   emit_operand(dst, src);
4843 }
4844 
4845 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4846   assert(VM_Version::supports_avx(), "");
4847   InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4848   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4849   int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4850   emit_int8(0x54);
4851   emit_int8((unsigned char)(0xC0 | encode));
4852 }
4853 
4854 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4855   assert(VM_Version::supports_avx(), "");
4856   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4857   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4858   int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4859   emit_int8(0x54);
4860   emit_int8((unsigned char)(0xC0 | encode));
4861 }
4862 
4863 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4864   assert(VM_Version::supports_avx(), "");
4865   InstructionMark im(this);
4866   InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4867   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4868   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4869   vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4870   emit_int8(0x54);
4871   emit_operand(dst, src);
4872 }
4873 
4874 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4875   assert(VM_Version::supports_avx(), "");
4876   InstructionMark im(this);
4877   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4878   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4879   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4880   vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4881   emit_int8(0x54);
4882   emit_operand(dst, src);
4883 }
4884 
4885 void Assembler::unpckhpd(XMMRegister dst, XMMRegister src) {
4886   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4887   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4888   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4889   emit_int8(0x15);
4890   emit_int8((unsigned char)(0xC0 | encode));
4891 }
4892 
4893 void Assembler::unpcklpd(XMMRegister dst, XMMRegister src) {
4894   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4895   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4896   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4897   emit_int8(0x14);
4898   emit_int8((unsigned char)(0xC0 | encode));
4899 }
4900 
4901 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
4902   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4903   InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4904   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4905   emit_int8(0x57);
4906   emit_int8((unsigned char)(0xC0 | encode));
4907 }
4908 
4909 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
4910   NOT_LP64(assert(VM_Version::supports_sse(), ""));
4911   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4912   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4913   emit_int8(0x57);
4914   emit_int8((unsigned char)(0xC0 | encode));
4915 }
4916 
4917 void Assembler::xorpd(XMMRegister dst, Address src) {
4918   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4919   InstructionMark im(this);
4920   InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4921   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4922   simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4923   emit_int8(0x57);
4924   emit_operand(dst, src);
4925 }
4926 
4927 void Assembler::xorps(XMMRegister dst, Address src) {
4928   NOT_LP64(assert(VM_Version::supports_sse(), ""));
4929   InstructionMark im(this);
4930   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4931   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4932   simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4933   emit_int8(0x57);
4934   emit_operand(dst, src);
4935 }
4936 
4937 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4938   assert(VM_Version::supports_avx(), "");
4939   InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4940   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4941   int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4942   emit_int8(0x57);
4943   emit_int8((unsigned char)(0xC0 | encode));
4944 }
4945 
4946 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4947   assert(VM_Version::supports_avx(), "");
4948   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4949   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4950   int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4951   emit_int8(0x57);
4952   emit_int8((unsigned char)(0xC0 | encode));
4953 }
4954 
4955 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4956   assert(VM_Version::supports_avx(), "");
4957   InstructionMark im(this);
4958   InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4959   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4960   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4961   vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4962   emit_int8(0x57);
4963   emit_operand(dst, src);
4964 }
4965 
4966 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4967   assert(VM_Version::supports_avx(), "");
4968   InstructionMark im(this);
4969   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4970   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4971   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4972   vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4973   emit_int8(0x57);
4974   emit_operand(dst, src);
4975 }
4976 
4977 // Integer vector arithmetic
4978 void Assembler::vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4979   assert(VM_Version::supports_avx() && (vector_len == 0) ||
4980          VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
4981   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4982   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4983   int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4984   emit_int8(0x01);
4985   emit_int8((unsigned char)(0xC0 | encode));
4986 }
4987 
4988 void Assembler::vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4989   assert(VM_Version::supports_avx() && (vector_len == 0) ||
4990          VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
4991   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4992   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4993   int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4994   emit_int8(0x02);
4995   emit_int8((unsigned char)(0xC0 | encode));
4996 }
4997 
4998 void Assembler::paddb(XMMRegister dst, XMMRegister src) {
4999   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5000   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5001   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5002   emit_int8((unsigned char)0xFC);
5003   emit_int8((unsigned char)(0xC0 | encode));
5004 }
5005 
5006 void Assembler::paddw(XMMRegister dst, XMMRegister src) {
5007   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5008   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5009   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5010   emit_int8((unsigned char)0xFD);
5011   emit_int8((unsigned char)(0xC0 | encode));
5012 }
5013 
5014 void Assembler::paddd(XMMRegister dst, XMMRegister src) {
5015   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5016   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5017   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5018   emit_int8((unsigned char)0xFE);
5019   emit_int8((unsigned char)(0xC0 | encode));
5020 }
5021 
5022 void Assembler::paddd(XMMRegister dst, Address src) {
5023   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5024   InstructionMark im(this);
5025   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5026   simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5027   emit_int8((unsigned char)0xFE);
5028   emit_operand(dst, src);
5029 }
5030 
5031 void Assembler::paddq(XMMRegister dst, XMMRegister src) {
5032   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5033   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5034   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5035   emit_int8((unsigned char)0xD4);
5036   emit_int8((unsigned char)(0xC0 | encode));
5037 }
5038 
5039 void Assembler::phaddw(XMMRegister dst, XMMRegister src) {
5040   assert(VM_Version::supports_sse3(), "");
5041   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5042   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5043   emit_int8(0x01);
5044   emit_int8((unsigned char)(0xC0 | encode));
5045 }
5046 
5047 void Assembler::phaddd(XMMRegister dst, XMMRegister src) {
5048   assert(VM_Version::supports_sse3(), "");
5049   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5050   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5051   emit_int8(0x02);
5052   emit_int8((unsigned char)(0xC0 | encode));
5053 }
5054 
5055 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5056   assert(UseAVX > 0, "requires some form of AVX");
5057   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5058   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5059   int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5060   emit_int8((unsigned char)0xFC);
5061   emit_int8((unsigned char)(0xC0 | encode));
5062 }
5063 
5064 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5065   assert(UseAVX > 0, "requires some form of AVX");
5066   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5067   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5068   int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5069   emit_int8((unsigned char)0xFD);
5070   emit_int8((unsigned char)(0xC0 | encode));
5071 }
5072 
5073 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5074   assert(UseAVX > 0, "requires some form of AVX");
5075   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5076   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5077   int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5078   emit_int8((unsigned char)0xFE);
5079   emit_int8((unsigned char)(0xC0 | encode));
5080 }
5081 
5082 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5083   assert(UseAVX > 0, "requires some form of AVX");
5084   InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5085   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5086   int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5087   emit_int8((unsigned char)0xD4);
5088   emit_int8((unsigned char)(0xC0 | encode));
5089 }
5090 
5091 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5092   assert(UseAVX > 0, "requires some form of AVX");
5093   InstructionMark im(this);
5094   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5095   attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5096   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5097   vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5098   emit_int8((unsigned char)0xFC);
5099   emit_operand(dst, src);
5100 }
5101 
5102 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5103   assert(UseAVX > 0, "requires some form of AVX");
5104   InstructionMark im(this);
5105   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5106   attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5107   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5108   vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5109   emit_int8((unsigned char)0xFD);
5110   emit_operand(dst, src);
5111 }
5112 
5113 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5114   assert(UseAVX > 0, "requires some form of AVX");
5115   InstructionMark im(this);
5116   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5117   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5118   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5119   vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5120   emit_int8((unsigned char)0xFE);
5121   emit_operand(dst, src);
5122 }
5123 
5124 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5125   assert(UseAVX > 0, "requires some form of AVX");
5126   InstructionMark im(this);
5127   InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5128   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5129   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5130   vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5131   emit_int8((unsigned char)0xD4);
5132   emit_operand(dst, src);
5133 }
5134 
5135 void Assembler::psubb(XMMRegister dst, XMMRegister src) {
5136   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5137   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5138   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5139   emit_int8((unsigned char)0xF8);
5140   emit_int8((unsigned char)(0xC0 | encode));
5141 }
5142 
5143 void Assembler::psubw(XMMRegister dst, XMMRegister src) {
5144   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5145   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5146   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5147   emit_int8((unsigned char)0xF9);
5148   emit_int8((unsigned char)(0xC0 | encode));
5149 }
5150 
5151 void Assembler::psubd(XMMRegister dst, XMMRegister src) {
5152   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5153   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5154   emit_int8((unsigned char)0xFA);
5155   emit_int8((unsigned char)(0xC0 | encode));
5156 }
5157 
5158 void Assembler::psubq(XMMRegister dst, XMMRegister src) {
5159   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5160   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5161   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5162   emit_int8((unsigned char)0xFB);
5163   emit_int8((unsigned char)(0xC0 | encode));
5164 }
5165 
5166 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5167   assert(UseAVX > 0, "requires some form of AVX");
5168   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5169   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5170   int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5171   emit_int8((unsigned char)0xF8);
5172   emit_int8((unsigned char)(0xC0 | encode));
5173 }
5174 
5175 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5176   assert(UseAVX > 0, "requires some form of AVX");
5177   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5178   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5179   int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5180   emit_int8((unsigned char)0xF9);
5181   emit_int8((unsigned char)(0xC0 | encode));
5182 }
5183 
5184 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5185   assert(UseAVX > 0, "requires some form of AVX");
5186   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5187   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5188   int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5189   emit_int8((unsigned char)0xFA);
5190   emit_int8((unsigned char)(0xC0 | encode));
5191 }
5192 
5193 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5194   assert(UseAVX > 0, "requires some form of AVX");
5195   InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5196   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5197   int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5198   emit_int8((unsigned char)0xFB);
5199   emit_int8((unsigned char)(0xC0 | encode));
5200 }
5201 
5202 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5203   assert(UseAVX > 0, "requires some form of AVX");
5204   InstructionMark im(this);
5205   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5206   attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5207   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5208   vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5209   emit_int8((unsigned char)0xF8);
5210   emit_operand(dst, src);
5211 }
5212 
5213 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5214   assert(UseAVX > 0, "requires some form of AVX");
5215   InstructionMark im(this);
5216   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5217   attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5218   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5219   vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5220   emit_int8((unsigned char)0xF9);
5221   emit_operand(dst, src);
5222 }
5223 
5224 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5225   assert(UseAVX > 0, "requires some form of AVX");
5226   InstructionMark im(this);
5227   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5228   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5229   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5230   vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5231   emit_int8((unsigned char)0xFA);
5232   emit_operand(dst, src);
5233 }
5234 
5235 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5236   assert(UseAVX > 0, "requires some form of AVX");
5237   InstructionMark im(this);
5238   InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5239   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5240   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5241   vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5242   emit_int8((unsigned char)0xFB);
5243   emit_operand(dst, src);
5244 }
5245 
5246 void Assembler::pmullw(XMMRegister dst, XMMRegister src) {
5247   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5248   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5249   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5250   emit_int8((unsigned char)0xD5);
5251   emit_int8((unsigned char)(0xC0 | encode));
5252 }
5253 
5254 void Assembler::pmulld(XMMRegister dst, XMMRegister src) {
5255   assert(VM_Version::supports_sse4_1(), "");
5256   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5257   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5258   emit_int8(0x40);
5259   emit_int8((unsigned char)(0xC0 | encode));
5260 }
5261 
5262 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5263   assert(UseAVX > 0, "requires some form of AVX");
5264   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5265   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5266   int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5267   emit_int8((unsigned char)0xD5);
5268   emit_int8((unsigned char)(0xC0 | encode));
5269 }
5270 
5271 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5272   assert(UseAVX > 0, "requires some form of AVX");
5273   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5274   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5275   int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5276   emit_int8(0x40);
5277   emit_int8((unsigned char)(0xC0 | encode));
5278 }
5279 
5280 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5281   assert(UseAVX > 2, "requires some form of AVX");
5282   InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5283   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5284   int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5285   emit_int8(0x40);
5286   emit_int8((unsigned char)(0xC0 | encode));
5287 }
5288 
5289 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5290   assert(UseAVX > 0, "requires some form of AVX");
5291   InstructionMark im(this);
5292   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5293   attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5294   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5295   vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5296   emit_int8((unsigned char)0xD5);
5297   emit_operand(dst, src);
5298 }
5299 
5300 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5301   assert(UseAVX > 0, "requires some form of AVX");
5302   InstructionMark im(this);
5303   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5304   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5305   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5306   vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5307   emit_int8(0x40);
5308   emit_operand(dst, src);
5309 }
5310 
5311 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5312   assert(UseAVX > 0, "requires some form of AVX");
5313   InstructionMark im(this);
5314   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5315   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5316   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5317   vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5318   emit_int8(0x40);
5319   emit_operand(dst, src);
5320 }
5321 
5322 // Shift packed integers left by specified number of bits.
5323 void Assembler::psllw(XMMRegister dst, int shift) {
5324   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5325   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5326   // XMM6 is for /6 encoding: 66 0F 71 /6 ib
5327   int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5328   emit_int8(0x71);
5329   emit_int8((unsigned char)(0xC0 | encode));
5330   emit_int8(shift & 0xFF);
5331 }
5332 
5333 void Assembler::pslld(XMMRegister dst, int shift) {
5334   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5335   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5336   // XMM6 is for /6 encoding: 66 0F 72 /6 ib
5337   int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5338   emit_int8(0x72);
5339   emit_int8((unsigned char)(0xC0 | encode));
5340   emit_int8(shift & 0xFF);
5341 }
5342 
5343 void Assembler::psllq(XMMRegister dst, int shift) {
5344   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5345   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5346   // XMM6 is for /6 encoding: 66 0F 73 /6 ib
5347   int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5348   emit_int8(0x73);
5349   emit_int8((unsigned char)(0xC0 | encode));
5350   emit_int8(shift & 0xFF);
5351 }
5352 
5353 void Assembler::psllw(XMMRegister dst, XMMRegister shift) {
5354   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5355   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5356   int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5357   emit_int8((unsigned char)0xF1);
5358   emit_int8((unsigned char)(0xC0 | encode));
5359 }
5360 
5361 void Assembler::pslld(XMMRegister dst, XMMRegister shift) {
5362   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5363   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5364   int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5365   emit_int8((unsigned char)0xF2);
5366   emit_int8((unsigned char)(0xC0 | encode));
5367 }
5368 
5369 void Assembler::psllq(XMMRegister dst, XMMRegister shift) {
5370   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5371   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5372   int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5373   emit_int8((unsigned char)0xF3);
5374   emit_int8((unsigned char)(0xC0 | encode));
5375 }
5376 
5377 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5378   assert(UseAVX > 0, "requires some form of AVX");
5379   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5380   // XMM6 is for /6 encoding: 66 0F 71 /6 ib
5381   int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5382   emit_int8(0x71);
5383   emit_int8((unsigned char)(0xC0 | encode));
5384   emit_int8(shift & 0xFF);
5385 }
5386 
5387 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5388   assert(UseAVX > 0, "requires some form of AVX");
5389   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5390   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5391   // XMM6 is for /6 encoding: 66 0F 72 /6 ib
5392   int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5393   emit_int8(0x72);
5394   emit_int8((unsigned char)(0xC0 | encode));
5395   emit_int8(shift & 0xFF);
5396 }
5397 
5398 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5399   assert(UseAVX > 0, "requires some form of AVX");
5400   InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5401   // XMM6 is for /6 encoding: 66 0F 73 /6 ib
5402   int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5403   emit_int8(0x73);
5404   emit_int8((unsigned char)(0xC0 | encode));
5405   emit_int8(shift & 0xFF);
5406 }
5407 
5408 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5409   assert(UseAVX > 0, "requires some form of AVX");
5410   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5411   int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5412   emit_int8((unsigned char)0xF1);
5413   emit_int8((unsigned char)(0xC0 | encode));
5414 }
5415 
5416 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5417   assert(UseAVX > 0, "requires some form of AVX");
5418   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5419   int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5420   emit_int8((unsigned char)0xF2);
5421   emit_int8((unsigned char)(0xC0 | encode));
5422 }
5423 
5424 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5425   assert(UseAVX > 0, "requires some form of AVX");
5426   InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5427   int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5428   emit_int8((unsigned char)0xF3);
5429   emit_int8((unsigned char)(0xC0 | encode));
5430 }
5431 
5432 // Shift packed integers logically right by specified number of bits.
5433 void Assembler::psrlw(XMMRegister dst, int shift) {
5434   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5435   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5436   // XMM2 is for /2 encoding: 66 0F 71 /2 ib
5437   int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5438   emit_int8(0x71);
5439   emit_int8((unsigned char)(0xC0 | encode));
5440   emit_int8(shift & 0xFF);
5441 }
5442 
5443 void Assembler::psrld(XMMRegister dst, int shift) {
5444   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5445   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5446   // XMM2 is for /2 encoding: 66 0F 72 /2 ib
5447   int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5448   emit_int8(0x72);
5449   emit_int8((unsigned char)(0xC0 | encode));
5450   emit_int8(shift & 0xFF);
5451 }
5452 
5453 void Assembler::psrlq(XMMRegister dst, int shift) {
5454   // Do not confuse it with psrldq SSE2 instruction which
5455   // shifts 128 bit value in xmm register by number of bytes.
5456   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5457   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5458   // XMM2 is for /2 encoding: 66 0F 73 /2 ib
5459   int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5460   emit_int8(0x73);
5461   emit_int8((unsigned char)(0xC0 | encode));
5462   emit_int8(shift & 0xFF);
5463 }
5464 
5465 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) {
5466   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5467   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5468   int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5469   emit_int8((unsigned char)0xD1);
5470   emit_int8((unsigned char)(0xC0 | encode));
5471 }
5472 
5473 void Assembler::psrld(XMMRegister dst, XMMRegister shift) {
5474   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5475   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5476   int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5477   emit_int8((unsigned char)0xD2);
5478   emit_int8((unsigned char)(0xC0 | encode));
5479 }
5480 
5481 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) {
5482   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5483   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5484   int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5485   emit_int8((unsigned char)0xD3);
5486   emit_int8((unsigned char)(0xC0 | encode));
5487 }
5488 
5489 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5490   assert(UseAVX > 0, "requires some form of AVX");
5491   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5492   // XMM2 is for /2 encoding: 66 0F 71 /2 ib
5493   int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5494   emit_int8(0x71);
5495   emit_int8((unsigned char)(0xC0 | encode));
5496   emit_int8(shift & 0xFF);
5497 }
5498 
5499 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5500   assert(UseAVX > 0, "requires some form of AVX");
5501   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5502   // XMM2 is for /2 encoding: 66 0F 72 /2 ib
5503   int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5504   emit_int8(0x72);
5505   emit_int8((unsigned char)(0xC0 | encode));
5506   emit_int8(shift & 0xFF);
5507 }
5508 
5509 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5510   assert(UseAVX > 0, "requires some form of AVX");
5511   InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5512   // XMM2 is for /2 encoding: 66 0F 73 /2 ib
5513   int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5514   emit_int8(0x73);
5515   emit_int8((unsigned char)(0xC0 | encode));
5516   emit_int8(shift & 0xFF);
5517 }
5518 
5519 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5520   assert(UseAVX > 0, "requires some form of AVX");
5521   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5522   int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5523   emit_int8((unsigned char)0xD1);
5524   emit_int8((unsigned char)(0xC0 | encode));
5525 }
5526 
5527 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5528   assert(UseAVX > 0, "requires some form of AVX");
5529   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5530   int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5531   emit_int8((unsigned char)0xD2);
5532   emit_int8((unsigned char)(0xC0 | encode));
5533 }
5534 
5535 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5536   assert(UseAVX > 0, "requires some form of AVX");
5537   InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5538   int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5539   emit_int8((unsigned char)0xD3);
5540   emit_int8((unsigned char)(0xC0 | encode));
5541 }
5542 
5543 // Shift packed integers arithmetically right by specified number of bits.
5544 void Assembler::psraw(XMMRegister dst, int shift) {
5545   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5546   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5547   // XMM4 is for /4 encoding: 66 0F 71 /4 ib
5548   int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5549   emit_int8(0x71);
5550   emit_int8((unsigned char)(0xC0 | encode));
5551   emit_int8(shift & 0xFF);
5552 }
5553 
5554 void Assembler::psrad(XMMRegister dst, int shift) {
5555   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5556   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5557   // XMM4 is for /4 encoding: 66 0F 72 /4 ib
5558   int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5559   emit_int8(0x72);
5560   emit_int8((unsigned char)(0xC0 | encode));
5561   emit_int8(shift & 0xFF);
5562 }
5563 
5564 void Assembler::psraw(XMMRegister dst, XMMRegister shift) {
5565   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5566   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5567   int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5568   emit_int8((unsigned char)0xE1);
5569   emit_int8((unsigned char)(0xC0 | encode));
5570 }
5571 
5572 void Assembler::psrad(XMMRegister dst, XMMRegister shift) {
5573   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5574   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5575   int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5576   emit_int8((unsigned char)0xE2);
5577   emit_int8((unsigned char)(0xC0 | encode));
5578 }
5579 
5580 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5581   assert(UseAVX > 0, "requires some form of AVX");
5582   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5583   // XMM4 is for /4 encoding: 66 0F 71 /4 ib
5584   int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5585   emit_int8(0x71);
5586   emit_int8((unsigned char)(0xC0 | encode));
5587   emit_int8(shift & 0xFF);
5588 }
5589 
5590 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5591   assert(UseAVX > 0, "requires some form of AVX");
5592   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5593   // XMM4 is for /4 encoding: 66 0F 71 /4 ib
5594   int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5595   emit_int8(0x72);
5596   emit_int8((unsigned char)(0xC0 | encode));
5597   emit_int8(shift & 0xFF);
5598 }
5599 
5600 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5601   assert(UseAVX > 0, "requires some form of AVX");
5602   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5603   int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5604   emit_int8((unsigned char)0xE1);
5605   emit_int8((unsigned char)(0xC0 | encode));
5606 }
5607 
5608 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5609   assert(UseAVX > 0, "requires some form of AVX");
5610   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5611   int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5612   emit_int8((unsigned char)0xE2);
5613   emit_int8((unsigned char)(0xC0 | encode));
5614 }
5615 
5616 
5617 // logical operations packed integers
5618 void Assembler::pand(XMMRegister dst, XMMRegister src) {
5619   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5620   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5621   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5622   emit_int8((unsigned char)0xDB);
5623   emit_int8((unsigned char)(0xC0 | encode));
5624 }
5625 
5626 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5627   assert(UseAVX > 0, "requires some form of AVX");
5628   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5629   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5630   int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5631   emit_int8((unsigned char)0xDB);
5632   emit_int8((unsigned char)(0xC0 | encode));
5633 }
5634 
5635 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5636   assert(UseAVX > 0, "requires some form of AVX");
5637   InstructionMark im(this);
5638   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5639   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5640   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5641   vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5642   emit_int8((unsigned char)0xDB);
5643   emit_operand(dst, src);
5644 }
5645 
5646 void Assembler::pandn(XMMRegister dst, XMMRegister src) {
5647   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5648   InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5649   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5650   emit_int8((unsigned char)0xDF);
5651   emit_int8((unsigned char)(0xC0 | encode));
5652 }
5653 
5654 void Assembler::por(XMMRegister dst, XMMRegister src) {
5655   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5656   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5657   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5658   emit_int8((unsigned char)0xEB);
5659   emit_int8((unsigned char)(0xC0 | encode));
5660 }
5661 
5662 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5663   assert(UseAVX > 0, "requires some form of AVX");
5664   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5665   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5666   int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5667   emit_int8((unsigned char)0xEB);
5668   emit_int8((unsigned char)(0xC0 | encode));
5669 }
5670 
5671 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5672   assert(UseAVX > 0, "requires some form of AVX");
5673   InstructionMark im(this);
5674   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5675   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5676   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5677   vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5678   emit_int8((unsigned char)0xEB);
5679   emit_operand(dst, src);
5680 }
5681 
5682 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
5683   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5684   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5685   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5686   emit_int8((unsigned char)0xEF);
5687   emit_int8((unsigned char)(0xC0 | encode));
5688 }
5689 
5690 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5691   assert(UseAVX > 0, "requires some form of AVX");
5692   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5693   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5694   int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5695   emit_int8((unsigned char)0xEF);
5696   emit_int8((unsigned char)(0xC0 | encode));
5697 }
5698 
5699 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5700   assert(UseAVX > 0, "requires some form of AVX");
5701   InstructionMark im(this);
5702   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5703   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5704   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5705   vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5706   emit_int8((unsigned char)0xEF);
5707   emit_operand(dst, src);
5708 }
5709 
5710 
5711 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
5712   assert(VM_Version::supports_avx(), "");
5713   assert(imm8 <= 0x01, "imm8: %u", imm8);
5714   int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5715   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5716   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5717   int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5718   emit_int8(0x18);
5719   emit_int8((unsigned char)(0xC0 | encode));
5720   // 0x00 - insert into lower 128 bits
5721   // 0x01 - insert into upper 128 bits
5722   emit_int8(imm8 & 0x01);
5723 }
5724 
5725 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
5726   assert(VM_Version::supports_evex(), "");
5727   assert(imm8 <= 0x01, "imm8: %u", imm8);
5728   InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5729   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5730   int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5731   emit_int8(0x1A);
5732   emit_int8((unsigned char)(0xC0 | encode));
5733   // 0x00 - insert into lower 256 bits
5734   // 0x01 - insert into upper 256 bits
5735   emit_int8(imm8 & 0x01);
5736 }
5737 
5738 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
5739   assert(VM_Version::supports_evex(), "");
5740   assert(dst != xnoreg, "sanity");
5741   assert(imm8 <= 0x01, "imm8: %u", imm8);
5742   InstructionMark im(this);
5743   InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5744   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5745   attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_64bit);
5746   // swap src<->dst for encoding
5747   vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5748   emit_int8(0x1A);
5749   emit_operand(dst, src);
5750   // 0x00 - insert into lower 256 bits
5751   // 0x01 - insert into upper 256 bits
5752   emit_int8(imm8 & 0x01);
5753 }
5754 
5755 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
5756   assert(VM_Version::supports_evex(), "");
5757   assert(imm8 <= 0x03, "imm8: %u", imm8);
5758   InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5759   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5760   int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5761   emit_int8(0x18);
5762   emit_int8((unsigned char)(0xC0 | encode));
5763   // 0x00 - insert into q0 128 bits (0..127)
5764   // 0x01 - insert into q1 128 bits (128..255)
5765   // 0x02 - insert into q2 128 bits (256..383)
5766   // 0x03 - insert into q3 128 bits (384..511)
5767   emit_int8(imm8 & 0x03);
5768 }
5769 
5770 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
5771   assert(VM_Version::supports_avx(), "");
5772   assert(dst != xnoreg, "sanity");
5773   assert(imm8 <= 0x03, "imm8: %u", imm8);
5774   int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5775   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5776   InstructionMark im(this);
5777   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5778   attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5779   // swap src<->dst for encoding
5780   vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5781   emit_int8(0x18);
5782   emit_operand(dst, src);
5783   // 0x00 - insert into q0 128 bits (0..127)
5784   // 0x01 - insert into q1 128 bits (128..255)
5785   // 0x02 - insert into q2 128 bits (256..383)
5786   // 0x03 - insert into q3 128 bits (384..511)
5787   emit_int8(imm8 & 0x03);
5788 }
5789 
5790 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
5791   assert(VM_Version::supports_avx(), "");
5792   assert(dst != xnoreg, "sanity");
5793   assert(imm8 <= 0x01, "imm8: %u", imm8);
5794   int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5795   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5796   InstructionMark im(this);
5797   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5798   attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5799   // swap src<->dst for encoding
5800   vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5801   emit_int8(0x18);
5802   emit_operand(dst, src);
5803   // 0x00 - insert into lower 128 bits
5804   // 0x01 - insert into upper 128 bits
5805   emit_int8(imm8 & 0x01);
5806 }
5807 
5808 void Assembler::vextractf128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
5809   assert(VM_Version::supports_avx(), "");
5810   assert(imm8 <= 0x01, "imm8: %u", imm8);
5811   int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5812   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5813   int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5814   emit_int8(0x19);
5815   emit_int8((unsigned char)(0xC0 | encode));
5816   // 0x00 - extract from lower 128 bits
5817   // 0x01 - extract from upper 128 bits
5818   emit_int8(imm8 & 0x01);
5819 }
5820 
5821 void Assembler::vextractf128(Address dst, XMMRegister src, uint8_t imm8) {
5822   assert(VM_Version::supports_avx(), "");
5823   assert(src != xnoreg, "sanity");
5824   assert(imm8 <= 0x01, "imm8: %u", imm8);
5825   int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5826   InstructionMark im(this);
5827   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5828   attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5829   vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5830   emit_int8(0x19);
5831   emit_operand(src, dst);
5832   // 0x00 - extract from lower 128 bits
5833   // 0x01 - extract from upper 128 bits
5834   emit_int8(imm8 & 0x01);
5835 }
5836 
5837 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
5838   assert(VM_Version::supports_avx2(), "");
5839   assert(imm8 <= 0x01, "imm8: %u", imm8);
5840   int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5841   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5842   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5843   int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5844   emit_int8(0x38);
5845   emit_int8((unsigned char)(0xC0 | encode));
5846   // 0x00 - insert into lower 128 bits
5847   // 0x01 - insert into upper 128 bits
5848   emit_int8(imm8 & 0x01);
5849 }
5850 
5851 void Assembler::vinserti64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
5852   assert(VM_Version::supports_evex(), "");
5853   assert(imm8 <= 0x01, "imm8: %u", imm8);
5854   InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5855   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5856   int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5857   emit_int8(0x38);
5858   emit_int8((unsigned char)(0xC0 | encode));
5859   // 0x00 - insert into lower 256 bits
5860   // 0x01 - insert into upper 256 bits
5861   emit_int8(imm8 & 0x01);
5862 }
5863 
5864 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
5865   assert(VM_Version::supports_avx2(), "");
5866   assert(dst != xnoreg, "sanity");
5867   assert(imm8 <= 0x01, "imm8: %u", imm8);
5868   int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5869   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5870   InstructionMark im(this);
5871   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5872   attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5873   // swap src<->dst for encoding
5874   vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5875   emit_int8(0x38);
5876   emit_operand(dst, src);
5877   // 0x00 - insert into lower 128 bits
5878   // 0x01 - insert into upper 128 bits
5879   emit_int8(imm8 & 0x01);
5880 }
5881 
5882 void Assembler::vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
5883   assert(VM_Version::supports_avx(), "");
5884   assert(imm8 <= 0x01, "imm8: %u", imm8);
5885   int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5886   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5887   int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5888   emit_int8(0x39);
5889   emit_int8((unsigned char)(0xC0 | encode));
5890   // 0x00 - extract from lower 128 bits
5891   // 0x01 - extract from upper 128 bits
5892   emit_int8(imm8 & 0x01);
5893 }
5894 
5895 void Assembler::vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
5896   assert(VM_Version::supports_avx2(), "");
5897   assert(src != xnoreg, "sanity");
5898   assert(imm8 <= 0x01, "imm8: %u", imm8);
5899   int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5900   InstructionMark im(this);
5901   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5902   attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5903   vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5904   emit_int8(0x39);
5905   emit_operand(src, dst);
5906   // 0x00 - extract from lower 128 bits
5907   // 0x01 - extract from upper 128 bits
5908   emit_int8(imm8 & 0x01);
5909 }
5910 
5911 void Assembler::vextracti64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
5912   assert(VM_Version::supports_evex(), "");
5913   assert(imm8 <= 0x01, "imm8: %u", imm8);
5914   InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5915   int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5916   emit_int8(0x3B);
5917   emit_int8((unsigned char)(0xC0 | encode));
5918   // 0x00 - extract from lower 256 bits
5919   // 0x01 - extract from upper 256 bits
5920   emit_int8(imm8 & 0x01);
5921 }
5922 
5923 void Assembler::vextracti64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) {
5924   assert(VM_Version::supports_evex(), "");
5925   assert(imm8 <= 0x03, "imm8: %u", imm8);
5926   InstructionAttr attributes(AVX_512bit, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5927   int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5928   emit_int8(0x39);
5929   emit_int8((unsigned char)(0xC0 | encode));
5930   // 0x00 - extract from bits 127:0
5931   // 0x01 - extract from bits 255:128
5932   // 0x02 - extract from bits 383:256
5933   // 0x03 - extract from bits 511:384
5934   emit_int8(imm8 & 0x03);
5935 }
5936 
5937 void Assembler::vextractf64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
5938   assert(VM_Version::supports_evex(), "");
5939   assert(imm8 <= 0x01, "imm8: %u", imm8);
5940   InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5941   int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5942   emit_int8(0x1B);
5943   emit_int8((unsigned char)(0xC0 | encode));
5944   // 0x00 - extract from lower 256 bits
5945   // 0x01 - extract from upper 256 bits
5946   emit_int8(imm8 & 0x01);
5947 }
5948 
5949 void Assembler::vextractf64x4(Address dst, XMMRegister src, uint8_t imm8) {
5950   assert(VM_Version::supports_evex(), "");
5951   assert(src != xnoreg, "sanity");
5952   assert(imm8 <= 0x01, "imm8: %u", imm8);
5953   InstructionMark im(this);
5954   InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5955   attributes.set_address_attributes(/* tuple_type */ EVEX_T4,/* input_size_in_bits */  EVEX_64bit);
5956   vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5957   emit_int8(0x1B);
5958   emit_operand(src, dst);
5959   // 0x00 - extract from lower 256 bits
5960   // 0x01 - extract from upper 256 bits
5961   emit_int8(imm8 & 0x01);
5962 }
5963 
5964 void Assembler::vextractf32x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
5965   assert(VM_Version::supports_avx(), "");
5966   assert(imm8 <= 0x03, "imm8: %u", imm8);
5967   int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5968   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5969   int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5970   emit_int8(0x19);
5971   emit_int8((unsigned char)(0xC0 | encode));
5972   // 0x00 - extract from bits 127:0
5973   // 0x01 - extract from bits 255:128
5974   // 0x02 - extract from bits 383:256
5975   // 0x03 - extract from bits 511:384
5976   emit_int8(imm8 & 0x03);
5977 }
5978 
5979 void Assembler::vextractf32x4(Address dst, XMMRegister src, uint8_t imm8) {
5980   assert(VM_Version::supports_evex(), "");
5981   assert(src != xnoreg, "sanity");
5982   assert(imm8 <= 0x03, "imm8: %u", imm8);
5983   InstructionMark im(this);
5984   InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5985   attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5986   vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5987   emit_int8(0x19);
5988   emit_operand(src, dst);
5989   // 0x00 - extract from bits 127:0
5990   // 0x01 - extract from bits 255:128
5991   // 0x02 - extract from bits 383:256
5992   // 0x03 - extract from bits 511:384
5993   emit_int8(imm8 & 0x03);
5994 }
5995 
5996 void Assembler::vextractf64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) {
5997   assert(VM_Version::supports_evex(), "");
5998   assert(imm8 <= 0x03, "imm8: %u", imm8);
5999   InstructionAttr attributes(AVX_512bit, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6000   int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6001   emit_int8(0x19);
6002   emit_int8((unsigned char)(0xC0 | encode));
6003   // 0x00 - extract from bits 127:0
6004   // 0x01 - extract from bits 255:128
6005   // 0x02 - extract from bits 383:256
6006   // 0x03 - extract from bits 511:384
6007   emit_int8(imm8 & 0x03);
6008 }
6009 
6010 // duplicate 4-bytes integer data from src into 8 locations in dest
6011 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src) {
6012   assert(VM_Version::supports_avx2(), "");
6013   InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6014   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6015   emit_int8(0x58);
6016   emit_int8((unsigned char)(0xC0 | encode));
6017 }
6018 
6019 // duplicate 2-bytes integer data from src into 16 locations in dest
6020 void Assembler::vpbroadcastw(XMMRegister dst, XMMRegister src) {
6021   assert(VM_Version::supports_avx2(), "");
6022   InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6023   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6024   emit_int8(0x79);
6025   emit_int8((unsigned char)(0xC0 | encode));
6026 }
6027 
6028 // duplicate 1-byte integer data from src into 16||32|64 locations in dest : requires AVX512BW and AVX512VL
6029 void Assembler::evpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len) {
6030   assert(VM_Version::supports_evex(), "");
6031   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6032   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6033   emit_int8(0x78);
6034   emit_int8((unsigned char)(0xC0 | encode));
6035 }
6036 
6037 void Assembler::evpbroadcastb(XMMRegister dst, Address src, int vector_len) {
6038   assert(VM_Version::supports_evex(), "");
6039   assert(dst != xnoreg, "sanity");
6040   InstructionMark im(this);
6041   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6042   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
6043   // swap src<->dst for encoding
6044   vex_prefix(src, dst->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6045   emit_int8(0x78);
6046   emit_operand(dst, src);
6047 }
6048 
6049 // duplicate 2-byte integer data from src into 8|16||32 locations in dest : requires AVX512BW and AVX512VL
6050 void Assembler::evpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len) {
6051   assert(VM_Version::supports_evex(), "");
6052   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6053   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6054   emit_int8(0x79);
6055   emit_int8((unsigned char)(0xC0 | encode));
6056 }
6057 
6058 void Assembler::evpbroadcastw(XMMRegister dst, Address src, int vector_len) {
6059   assert(VM_Version::supports_evex(), "");
6060   assert(dst != xnoreg, "sanity");
6061   InstructionMark im(this);
6062   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6063   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
6064   // swap src<->dst for encoding
6065   vex_prefix(src, dst->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6066   emit_int8(0x79);
6067   emit_operand(dst, src);
6068 }
6069 
6070 // duplicate 4-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
6071 void Assembler::evpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len) {
6072   assert(VM_Version::supports_evex(), "");
6073   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6074   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6075   emit_int8(0x58);
6076   emit_int8((unsigned char)(0xC0 | encode));
6077 }
6078 
6079 void Assembler::evpbroadcastd(XMMRegister dst, Address src, int vector_len) {
6080   assert(VM_Version::supports_evex(), "");
6081   assert(dst != xnoreg, "sanity");
6082   InstructionMark im(this);
6083   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6084   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
6085   // swap src<->dst for encoding
6086   vex_prefix(src, dst->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6087   emit_int8(0x58);
6088   emit_operand(dst, src);
6089 }
6090 
6091 // duplicate 8-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
6092 void Assembler::evpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len) {
6093   assert(VM_Version::supports_evex(), "");
6094   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6095   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6096   emit_int8(0x59);
6097   emit_int8((unsigned char)(0xC0 | encode));
6098 }
6099 
6100 void Assembler::evpbroadcastq(XMMRegister dst, Address src, int vector_len) {
6101   assert(VM_Version::supports_evex(), "");
6102   assert(dst != xnoreg, "sanity");
6103   InstructionMark im(this);
6104   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6105   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6106   // swap src<->dst for encoding
6107   vex_prefix(src, dst->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6108   emit_int8(0x59);
6109   emit_operand(dst, src);
6110 }
6111 
6112 // duplicate single precision fp from src into 4|8|16 locations in dest : requires AVX512VL
6113 void Assembler::evpbroadcastss(XMMRegister dst, XMMRegister src, int vector_len) {
6114   assert(VM_Version::supports_evex(), "");
6115   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6116   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6117   emit_int8(0x18);
6118   emit_int8((unsigned char)(0xC0 | encode));
6119 }
6120 
6121 void Assembler::evpbroadcastss(XMMRegister dst, Address src, int vector_len) {
6122   assert(VM_Version::supports_evex(), "");
6123   assert(dst != xnoreg, "sanity");
6124   InstructionMark im(this);
6125   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6126   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
6127   // swap src<->dst for encoding
6128   vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6129   emit_int8(0x18);
6130   emit_operand(dst, src);
6131 }
6132 
6133 // duplicate double precision fp from src into 2|4|8 locations in dest : requires AVX512VL
6134 void Assembler::evpbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len) {
6135   assert(VM_Version::supports_evex(), "");
6136   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6137   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6138   emit_int8(0x19);
6139   emit_int8((unsigned char)(0xC0 | encode));
6140 }
6141 
6142 void Assembler::evpbroadcastsd(XMMRegister dst, Address src, int vector_len) {
6143   assert(VM_Version::supports_evex(), "");
6144   assert(dst != xnoreg, "sanity");
6145   InstructionMark im(this);
6146   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6147   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6148   // swap src<->dst for encoding
6149   vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6150   emit_int8(0x19);
6151   emit_operand(dst, src);
6152 }
6153 
6154 // duplicate 1-byte integer data from src into 16||32|64 locations in dest : requires AVX512BW and AVX512VL
6155 void Assembler::evpbroadcastb(XMMRegister dst, Register src, int vector_len) {
6156   assert(VM_Version::supports_evex(), "");
6157   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6158   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6159   emit_int8(0x7A);
6160   emit_int8((unsigned char)(0xC0 | encode));
6161 }
6162 
6163 // duplicate 2-byte integer data from src into 8|16||32 locations in dest : requires AVX512BW and AVX512VL
6164 void Assembler::evpbroadcastw(XMMRegister dst, Register src, int vector_len) {
6165   assert(VM_Version::supports_evex(), "");
6166   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6167   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6168   emit_int8(0x7B);
6169   emit_int8((unsigned char)(0xC0 | encode));
6170 }
6171 
6172 // duplicate 4-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
6173 void Assembler::evpbroadcastd(XMMRegister dst, Register src, int vector_len) {
6174   assert(VM_Version::supports_evex(), "");
6175   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6176   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6177   emit_int8(0x7C);
6178   emit_int8((unsigned char)(0xC0 | encode));
6179 }
6180 
6181 // duplicate 8-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
6182 void Assembler::evpbroadcastq(XMMRegister dst, Register src, int vector_len) {
6183   assert(VM_Version::supports_evex(), "");
6184   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6185   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6186   emit_int8(0x7C);
6187   emit_int8((unsigned char)(0xC0 | encode));
6188 }
6189 
6190 // Carry-Less Multiplication Quadword
6191 void Assembler::pclmulqdq(XMMRegister dst, XMMRegister src, int mask) {
6192   assert(VM_Version::supports_clmul(), "");
6193   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6194   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6195   emit_int8(0x44);
6196   emit_int8((unsigned char)(0xC0 | encode));
6197   emit_int8((unsigned char)mask);
6198 }
6199 
6200 // Carry-Less Multiplication Quadword
6201 void Assembler::vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask) {
6202   assert(VM_Version::supports_avx() && VM_Version::supports_clmul(), "");
6203   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6204   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
6205   int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6206   emit_int8(0x44);
6207   emit_int8((unsigned char)(0xC0 | encode));
6208   emit_int8((unsigned char)mask);
6209 }
6210 
6211 void Assembler::vzeroupper() {
6212   assert(VM_Version::supports_avx(), "");
6213   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6214   (void)vex_prefix_and_encode(0, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6215   emit_int8(0x77);
6216 }
6217 
6218 
6219 #ifndef _LP64
6220 // 32bit only pieces of the assembler
6221 
6222 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
6223   // NO PREFIX AS NEVER 64BIT
6224   InstructionMark im(this);
6225   emit_int8((unsigned char)0x81);
6226   emit_int8((unsigned char)(0xF8 | src1->encoding()));
6227   emit_data(imm32, rspec, 0);
6228 }
6229 
6230 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
6231   // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
6232   InstructionMark im(this);
6233   emit_int8((unsigned char)0x81);
6234   emit_operand(rdi, src1);
6235   emit_data(imm32, rspec, 0);
6236 }
6237 
6238 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax,
6239 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded
6240 // into rdx:rax.  The ZF is set if the compared values were equal, and cleared otherwise.
6241 void Assembler::cmpxchg8(Address adr) {
6242   InstructionMark im(this);
6243   emit_int8(0x0F);
6244   emit_int8((unsigned char)0xC7);
6245   emit_operand(rcx, adr);
6246 }
6247 
6248 void Assembler::decl(Register dst) {
6249   // Don't use it directly. Use MacroAssembler::decrementl() instead.
6250  emit_int8(0x48 | dst->encoding());
6251 }
6252 
6253 #endif // _LP64
6254 
6255 // 64bit typically doesn't use the x87 but needs to for the trig funcs
6256 
6257 void Assembler::fabs() {
6258   emit_int8((unsigned char)0xD9);
6259   emit_int8((unsigned char)0xE1);
6260 }
6261 
6262 void Assembler::fadd(int i) {
6263   emit_farith(0xD8, 0xC0, i);
6264 }
6265 
6266 void Assembler::fadd_d(Address src) {
6267   InstructionMark im(this);
6268   emit_int8((unsigned char)0xDC);
6269   emit_operand32(rax, src);
6270 }
6271 
6272 void Assembler::fadd_s(Address src) {
6273   InstructionMark im(this);
6274   emit_int8((unsigned char)0xD8);
6275   emit_operand32(rax, src);
6276 }
6277 
6278 void Assembler::fadda(int i) {
6279   emit_farith(0xDC, 0xC0, i);
6280 }
6281 
6282 void Assembler::faddp(int i) {
6283   emit_farith(0xDE, 0xC0, i);
6284 }
6285 
6286 void Assembler::fchs() {
6287   emit_int8((unsigned char)0xD9);
6288   emit_int8((unsigned char)0xE0);
6289 }
6290 
6291 void Assembler::fcom(int i) {
6292   emit_farith(0xD8, 0xD0, i);
6293 }
6294 
6295 void Assembler::fcomp(int i) {
6296   emit_farith(0xD8, 0xD8, i);
6297 }
6298 
6299 void Assembler::fcomp_d(Address src) {
6300   InstructionMark im(this);
6301   emit_int8((unsigned char)0xDC);
6302   emit_operand32(rbx, src);
6303 }
6304 
6305 void Assembler::fcomp_s(Address src) {
6306   InstructionMark im(this);
6307   emit_int8((unsigned char)0xD8);
6308   emit_operand32(rbx, src);
6309 }
6310 
6311 void Assembler::fcompp() {
6312   emit_int8((unsigned char)0xDE);
6313   emit_int8((unsigned char)0xD9);
6314 }
6315 
6316 void Assembler::fcos() {
6317   emit_int8((unsigned char)0xD9);
6318   emit_int8((unsigned char)0xFF);
6319 }
6320 
6321 void Assembler::fdecstp() {
6322   emit_int8((unsigned char)0xD9);
6323   emit_int8((unsigned char)0xF6);
6324 }
6325 
6326 void Assembler::fdiv(int i) {
6327   emit_farith(0xD8, 0xF0, i);
6328 }
6329 
6330 void Assembler::fdiv_d(Address src) {
6331   InstructionMark im(this);
6332   emit_int8((unsigned char)0xDC);
6333   emit_operand32(rsi, src);
6334 }
6335 
6336 void Assembler::fdiv_s(Address src) {
6337   InstructionMark im(this);
6338   emit_int8((unsigned char)0xD8);
6339   emit_operand32(rsi, src);
6340 }
6341 
6342 void Assembler::fdiva(int i) {
6343   emit_farith(0xDC, 0xF8, i);
6344 }
6345 
6346 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994)
6347 //       is erroneous for some of the floating-point instructions below.
6348 
6349 void Assembler::fdivp(int i) {
6350   emit_farith(0xDE, 0xF8, i);                    // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong)
6351 }
6352 
6353 void Assembler::fdivr(int i) {
6354   emit_farith(0xD8, 0xF8, i);
6355 }
6356 
6357 void Assembler::fdivr_d(Address src) {
6358   InstructionMark im(this);
6359   emit_int8((unsigned char)0xDC);
6360   emit_operand32(rdi, src);
6361 }
6362 
6363 void Assembler::fdivr_s(Address src) {
6364   InstructionMark im(this);
6365   emit_int8((unsigned char)0xD8);
6366   emit_operand32(rdi, src);
6367 }
6368 
6369 void Assembler::fdivra(int i) {
6370   emit_farith(0xDC, 0xF0, i);
6371 }
6372 
6373 void Assembler::fdivrp(int i) {
6374   emit_farith(0xDE, 0xF0, i);                    // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong)
6375 }
6376 
6377 void Assembler::ffree(int i) {
6378   emit_farith(0xDD, 0xC0, i);
6379 }
6380 
6381 void Assembler::fild_d(Address adr) {
6382   InstructionMark im(this);
6383   emit_int8((unsigned char)0xDF);
6384   emit_operand32(rbp, adr);
6385 }
6386 
6387 void Assembler::fild_s(Address adr) {
6388   InstructionMark im(this);
6389   emit_int8((unsigned char)0xDB);
6390   emit_operand32(rax, adr);
6391 }
6392 
6393 void Assembler::fincstp() {
6394   emit_int8((unsigned char)0xD9);
6395   emit_int8((unsigned char)0xF7);
6396 }
6397 
6398 void Assembler::finit() {
6399   emit_int8((unsigned char)0x9B);
6400   emit_int8((unsigned char)0xDB);
6401   emit_int8((unsigned char)0xE3);
6402 }
6403 
6404 void Assembler::fist_s(Address adr) {
6405   InstructionMark im(this);
6406   emit_int8((unsigned char)0xDB);
6407   emit_operand32(rdx, adr);
6408 }
6409 
6410 void Assembler::fistp_d(Address adr) {
6411   InstructionMark im(this);
6412   emit_int8((unsigned char)0xDF);
6413   emit_operand32(rdi, adr);
6414 }
6415 
6416 void Assembler::fistp_s(Address adr) {
6417   InstructionMark im(this);
6418   emit_int8((unsigned char)0xDB);
6419   emit_operand32(rbx, adr);
6420 }
6421 
6422 void Assembler::fld1() {
6423   emit_int8((unsigned char)0xD9);
6424   emit_int8((unsigned char)0xE8);
6425 }
6426 
6427 void Assembler::fld_d(Address adr) {
6428   InstructionMark im(this);
6429   emit_int8((unsigned char)0xDD);
6430   emit_operand32(rax, adr);
6431 }
6432 
6433 void Assembler::fld_s(Address adr) {
6434   InstructionMark im(this);
6435   emit_int8((unsigned char)0xD9);
6436   emit_operand32(rax, adr);
6437 }
6438 
6439 
6440 void Assembler::fld_s(int index) {
6441   emit_farith(0xD9, 0xC0, index);
6442 }
6443 
6444 void Assembler::fld_x(Address adr) {
6445   InstructionMark im(this);
6446   emit_int8((unsigned char)0xDB);
6447   emit_operand32(rbp, adr);
6448 }
6449 
6450 void Assembler::fldcw(Address src) {
6451   InstructionMark im(this);
6452   emit_int8((unsigned char)0xD9);
6453   emit_operand32(rbp, src);
6454 }
6455 
6456 void Assembler::fldenv(Address src) {
6457   InstructionMark im(this);
6458   emit_int8((unsigned char)0xD9);
6459   emit_operand32(rsp, src);
6460 }
6461 
6462 void Assembler::fldlg2() {
6463   emit_int8((unsigned char)0xD9);
6464   emit_int8((unsigned char)0xEC);
6465 }
6466 
6467 void Assembler::fldln2() {
6468   emit_int8((unsigned char)0xD9);
6469   emit_int8((unsigned char)0xED);
6470 }
6471 
6472 void Assembler::fldz() {
6473   emit_int8((unsigned char)0xD9);
6474   emit_int8((unsigned char)0xEE);
6475 }
6476 
6477 void Assembler::flog() {
6478   fldln2();
6479   fxch();
6480   fyl2x();
6481 }
6482 
6483 void Assembler::flog10() {
6484   fldlg2();
6485   fxch();
6486   fyl2x();
6487 }
6488 
6489 void Assembler::fmul(int i) {
6490   emit_farith(0xD8, 0xC8, i);
6491 }
6492 
6493 void Assembler::fmul_d(Address src) {
6494   InstructionMark im(this);
6495   emit_int8((unsigned char)0xDC);
6496   emit_operand32(rcx, src);
6497 }
6498 
6499 void Assembler::fmul_s(Address src) {
6500   InstructionMark im(this);
6501   emit_int8((unsigned char)0xD8);
6502   emit_operand32(rcx, src);
6503 }
6504 
6505 void Assembler::fmula(int i) {
6506   emit_farith(0xDC, 0xC8, i);
6507 }
6508 
6509 void Assembler::fmulp(int i) {
6510   emit_farith(0xDE, 0xC8, i);
6511 }
6512 
6513 void Assembler::fnsave(Address dst) {
6514   InstructionMark im(this);
6515   emit_int8((unsigned char)0xDD);
6516   emit_operand32(rsi, dst);
6517 }
6518 
6519 void Assembler::fnstcw(Address src) {
6520   InstructionMark im(this);
6521   emit_int8((unsigned char)0x9B);
6522   emit_int8((unsigned char)0xD9);
6523   emit_operand32(rdi, src);
6524 }
6525 
6526 void Assembler::fnstsw_ax() {
6527   emit_int8((unsigned char)0xDF);
6528   emit_int8((unsigned char)0xE0);
6529 }
6530 
6531 void Assembler::fprem() {
6532   emit_int8((unsigned char)0xD9);
6533   emit_int8((unsigned char)0xF8);
6534 }
6535 
6536 void Assembler::fprem1() {
6537   emit_int8((unsigned char)0xD9);
6538   emit_int8((unsigned char)0xF5);
6539 }
6540 
6541 void Assembler::frstor(Address src) {
6542   InstructionMark im(this);
6543   emit_int8((unsigned char)0xDD);
6544   emit_operand32(rsp, src);
6545 }
6546 
6547 void Assembler::fsin() {
6548   emit_int8((unsigned char)0xD9);
6549   emit_int8((unsigned char)0xFE);
6550 }
6551 
6552 void Assembler::fsqrt() {
6553   emit_int8((unsigned char)0xD9);
6554   emit_int8((unsigned char)0xFA);
6555 }
6556 
6557 void Assembler::fst_d(Address adr) {
6558   InstructionMark im(this);
6559   emit_int8((unsigned char)0xDD);
6560   emit_operand32(rdx, adr);
6561 }
6562 
6563 void Assembler::fst_s(Address adr) {
6564   InstructionMark im(this);
6565   emit_int8((unsigned char)0xD9);
6566   emit_operand32(rdx, adr);
6567 }
6568 
6569 void Assembler::fstp_d(Address adr) {
6570   InstructionMark im(this);
6571   emit_int8((unsigned char)0xDD);
6572   emit_operand32(rbx, adr);
6573 }
6574 
6575 void Assembler::fstp_d(int index) {
6576   emit_farith(0xDD, 0xD8, index);
6577 }
6578 
6579 void Assembler::fstp_s(Address adr) {
6580   InstructionMark im(this);
6581   emit_int8((unsigned char)0xD9);
6582   emit_operand32(rbx, adr);
6583 }
6584 
6585 void Assembler::fstp_x(Address adr) {
6586   InstructionMark im(this);
6587   emit_int8((unsigned char)0xDB);
6588   emit_operand32(rdi, adr);
6589 }
6590 
6591 void Assembler::fsub(int i) {
6592   emit_farith(0xD8, 0xE0, i);
6593 }
6594 
6595 void Assembler::fsub_d(Address src) {
6596   InstructionMark im(this);
6597   emit_int8((unsigned char)0xDC);
6598   emit_operand32(rsp, src);
6599 }
6600 
6601 void Assembler::fsub_s(Address src) {
6602   InstructionMark im(this);
6603   emit_int8((unsigned char)0xD8);
6604   emit_operand32(rsp, src);
6605 }
6606 
6607 void Assembler::fsuba(int i) {
6608   emit_farith(0xDC, 0xE8, i);
6609 }
6610 
6611 void Assembler::fsubp(int i) {
6612   emit_farith(0xDE, 0xE8, i);                    // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong)
6613 }
6614 
6615 void Assembler::fsubr(int i) {
6616   emit_farith(0xD8, 0xE8, i);
6617 }
6618 
6619 void Assembler::fsubr_d(Address src) {
6620   InstructionMark im(this);
6621   emit_int8((unsigned char)0xDC);
6622   emit_operand32(rbp, src);
6623 }
6624 
6625 void Assembler::fsubr_s(Address src) {
6626   InstructionMark im(this);
6627   emit_int8((unsigned char)0xD8);
6628   emit_operand32(rbp, src);
6629 }
6630 
6631 void Assembler::fsubra(int i) {
6632   emit_farith(0xDC, 0xE0, i);
6633 }
6634 
6635 void Assembler::fsubrp(int i) {
6636   emit_farith(0xDE, 0xE0, i);                    // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong)
6637 }
6638 
6639 void Assembler::ftan() {
6640   emit_int8((unsigned char)0xD9);
6641   emit_int8((unsigned char)0xF2);
6642   emit_int8((unsigned char)0xDD);
6643   emit_int8((unsigned char)0xD8);
6644 }
6645 
6646 void Assembler::ftst() {
6647   emit_int8((unsigned char)0xD9);
6648   emit_int8((unsigned char)0xE4);
6649 }
6650 
6651 void Assembler::fucomi(int i) {
6652   // make sure the instruction is supported (introduced for P6, together with cmov)
6653   guarantee(VM_Version::supports_cmov(), "illegal instruction");
6654   emit_farith(0xDB, 0xE8, i);
6655 }
6656 
6657 void Assembler::fucomip(int i) {
6658   // make sure the instruction is supported (introduced for P6, together with cmov)
6659   guarantee(VM_Version::supports_cmov(), "illegal instruction");
6660   emit_farith(0xDF, 0xE8, i);
6661 }
6662 
6663 void Assembler::fwait() {
6664   emit_int8((unsigned char)0x9B);
6665 }
6666 
6667 void Assembler::fxch(int i) {
6668   emit_farith(0xD9, 0xC8, i);
6669 }
6670 
6671 void Assembler::fyl2x() {
6672   emit_int8((unsigned char)0xD9);
6673   emit_int8((unsigned char)0xF1);
6674 }
6675 
6676 void Assembler::frndint() {
6677   emit_int8((unsigned char)0xD9);
6678   emit_int8((unsigned char)0xFC);
6679 }
6680 
6681 void Assembler::f2xm1() {
6682   emit_int8((unsigned char)0xD9);
6683   emit_int8((unsigned char)0xF0);
6684 }
6685 
6686 void Assembler::fldl2e() {
6687   emit_int8((unsigned char)0xD9);
6688   emit_int8((unsigned char)0xEA);
6689 }
6690 
6691 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding.
6692 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 };
6693 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding.
6694 static int simd_opc[4] = { 0,    0, 0x38, 0x3A };
6695 
6696 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding.
6697 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
6698   if (pre > 0) {
6699     emit_int8(simd_pre[pre]);
6700   }
6701   if (rex_w) {
6702     prefixq(adr, xreg);
6703   } else {
6704     prefix(adr, xreg);
6705   }
6706   if (opc > 0) {
6707     emit_int8(0x0F);
6708     int opc2 = simd_opc[opc];
6709     if (opc2 > 0) {
6710       emit_int8(opc2);
6711     }
6712   }
6713 }
6714 
6715 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
6716   if (pre > 0) {
6717     emit_int8(simd_pre[pre]);
6718   }
6719   int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) : prefix_and_encode(dst_enc, src_enc);
6720   if (opc > 0) {
6721     emit_int8(0x0F);
6722     int opc2 = simd_opc[opc];
6723     if (opc2 > 0) {
6724       emit_int8(opc2);
6725     }
6726   }
6727   return encode;
6728 }
6729 
6730 
6731 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc) {
6732   int vector_len = _attributes->get_vector_len();
6733   bool vex_w = _attributes->is_rex_vex_w();
6734   if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) {
6735     prefix(VEX_3bytes);
6736 
6737     int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0);
6738     byte1 = (~byte1) & 0xE0;
6739     byte1 |= opc;
6740     emit_int8(byte1);
6741 
6742     int byte2 = ((~nds_enc) & 0xf) << 3;
6743     byte2 |= (vex_w ? VEX_W : 0) | ((vector_len > 0) ? 4 : 0) | pre;
6744     emit_int8(byte2);
6745   } else {
6746     prefix(VEX_2bytes);
6747 
6748     int byte1 = vex_r ? VEX_R : 0;
6749     byte1 = (~byte1) & 0x80;
6750     byte1 |= ((~nds_enc) & 0xf) << 3;
6751     byte1 |= ((vector_len > 0 ) ? 4 : 0) | pre;
6752     emit_int8(byte1);
6753   }
6754 }
6755 
6756 // This is a 4 byte encoding
6757 void Assembler::evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_r, bool evex_v, int nds_enc, VexSimdPrefix pre, VexOpcode opc){
6758   // EVEX 0x62 prefix
6759   prefix(EVEX_4bytes);
6760   bool vex_w = _attributes->is_rex_vex_w();
6761   int evex_encoding = (vex_w ? VEX_W : 0);
6762   // EVEX.b is not currently used for broadcast of single element or data rounding modes
6763   _attributes->set_evex_encoding(evex_encoding);
6764 
6765   // P0: byte 2, initialized to RXBR`00mm
6766   // instead of not'd
6767   int byte2 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0) | (evex_r ? EVEX_Rb : 0);
6768   byte2 = (~byte2) & 0xF0;
6769   // confine opc opcode extensions in mm bits to lower two bits
6770   // of form {0F, 0F_38, 0F_3A}
6771   byte2 |= opc;
6772   emit_int8(byte2);
6773 
6774   // P1: byte 3 as Wvvvv1pp
6775   int byte3 = ((~nds_enc) & 0xf) << 3;
6776   // p[10] is always 1
6777   byte3 |= EVEX_F;
6778   byte3 |= (vex_w & 1) << 7;
6779   // confine pre opcode extensions in pp bits to lower two bits
6780   // of form {66, F3, F2}
6781   byte3 |= pre;
6782   emit_int8(byte3);
6783 
6784   // P2: byte 4 as zL'Lbv'aaa
6785   int byte4 = (_attributes->is_no_reg_mask()) ? 0 : 1; // kregs are implemented in the low 3 bits as aaa (hard code k1, it will be initialized for now)
6786   // EVEX.v` for extending EVEX.vvvv or VIDX
6787   byte4 |= (evex_v ? 0: EVEX_V);
6788   // third EXEC.b for broadcast actions
6789   byte4 |= (_attributes->is_extended_context() ? EVEX_Rb : 0);
6790   // fourth EVEX.L'L for vector length : 0 is 128, 1 is 256, 2 is 512, currently we do not support 1024
6791   byte4 |= ((_attributes->get_vector_len())& 0x3) << 5;
6792   // last is EVEX.z for zero/merge actions
6793   byte4 |= (_attributes->is_clear_context() ? EVEX_Z : 0);
6794   emit_int8(byte4);
6795 }
6796 
6797 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) {
6798   bool vex_r = ((xreg_enc & 8) == 8) ? 1 : 0;
6799   bool vex_b = adr.base_needs_rex();
6800   bool vex_x = adr.index_needs_rex();
6801   set_attributes(attributes);
6802   attributes->set_current_assembler(this);
6803 
6804   // if vector length is turned off, revert to AVX for vectors smaller than 512-bit
6805   if ((UseAVX > 2) && _legacy_mode_vl && attributes->uses_vl()) {
6806     switch (attributes->get_vector_len()) {
6807     case AVX_128bit:
6808     case AVX_256bit:
6809       attributes->set_is_legacy_mode();
6810       break;
6811     }
6812   }
6813 
6814   if ((UseAVX > 2) && !attributes->is_legacy_mode())
6815   {
6816     bool evex_r = (xreg_enc >= 16);
6817     bool evex_v = (nds_enc >= 16);
6818     attributes->set_is_evex_instruction();
6819     evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc);
6820   } else {
6821     vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc);
6822   }
6823 }
6824 
6825 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) {
6826   bool vex_r = ((dst_enc & 8) == 8) ? 1 : 0;
6827   bool vex_b = ((src_enc & 8) == 8) ? 1 : 0;
6828   bool vex_x = false;
6829   set_attributes(attributes);
6830   attributes->set_current_assembler(this);
6831 
6832   // if vector length is turned off, revert to AVX for vectors smaller than 512-bit
6833   if ((UseAVX > 2) && _legacy_mode_vl && attributes->uses_vl()) {
6834     switch (attributes->get_vector_len()) {
6835     case AVX_128bit:
6836     case AVX_256bit:
6837       if ((dst_enc >= 16) | (nds_enc >= 16) | (src_enc >= 16)) {
6838         // up propagate arithmetic instructions to meet RA requirements
6839         attributes->set_vector_len(AVX_512bit);
6840       } else {
6841         attributes->set_is_legacy_mode();
6842       }
6843       break;
6844     }
6845   }
6846 
6847   if ((UseAVX > 2) && !attributes->is_legacy_mode())
6848   {
6849     bool evex_r = (dst_enc >= 16);
6850     bool evex_v = (nds_enc >= 16);
6851     // can use vex_x as bank extender on rm encoding
6852     vex_x = (src_enc >= 16);
6853     attributes->set_is_evex_instruction();
6854     evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc);
6855   } else {
6856     vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc);
6857   }
6858 
6859   // return modrm byte components for operands
6860   return (((dst_enc & 7) << 3) | (src_enc & 7));
6861 }
6862 
6863 
6864 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre,
6865                             VexOpcode opc, InstructionAttr *attributes) {
6866   if (UseAVX > 0) {
6867     int xreg_enc = xreg->encoding();
6868     int nds_enc = nds->is_valid() ? nds->encoding() : 0;
6869     vex_prefix(adr, nds_enc, xreg_enc, pre, opc, attributes);
6870   } else {
6871     assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding");
6872     rex_prefix(adr, xreg, pre, opc, attributes->is_rex_vex_w());
6873   }
6874 }
6875 
6876 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre,
6877                                       VexOpcode opc, InstructionAttr *attributes) {
6878   int dst_enc = dst->encoding();
6879   int src_enc = src->encoding();
6880   if (UseAVX > 0) {
6881     int nds_enc = nds->is_valid() ? nds->encoding() : 0;
6882     return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, attributes);
6883   } else {
6884     assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding");
6885     return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, attributes->is_rex_vex_w());
6886   }
6887 }
6888 
6889 void Assembler::cmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) {
6890   assert(VM_Version::supports_avx(), "");
6891   assert(!VM_Version::supports_evex(), "");
6892   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6893   int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6894   emit_int8((unsigned char)0xC2);
6895   emit_int8((unsigned char)(0xC0 | encode));
6896   emit_int8((unsigned char)(0xF & cop));
6897 }
6898 
6899 void Assembler::vpblendd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) {
6900   assert(VM_Version::supports_avx(), "");
6901   assert(!VM_Version::supports_evex(), "");
6902   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6903   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
6904   int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6905   emit_int8((unsigned char)0x4B);
6906   emit_int8((unsigned char)(0xC0 | encode));
6907   int src2_enc = src2->encoding();
6908   emit_int8((unsigned char)(0xF0 & src2_enc<<4));
6909 }
6910 
6911 
6912 #ifndef _LP64
6913 
6914 void Assembler::incl(Register dst) {
6915   // Don't use it directly. Use MacroAssembler::incrementl() instead.
6916   emit_int8(0x40 | dst->encoding());
6917 }
6918 
6919 void Assembler::lea(Register dst, Address src) {
6920   leal(dst, src);
6921 }
6922 
6923 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
6924   InstructionMark im(this);
6925   emit_int8((unsigned char)0xC7);
6926   emit_operand(rax, dst);
6927   emit_data((int)imm32, rspec, 0);
6928 }
6929 
6930 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
6931   InstructionMark im(this);
6932   int encode = prefix_and_encode(dst->encoding());
6933   emit_int8((unsigned char)(0xB8 | encode));
6934   emit_data((int)imm32, rspec, 0);
6935 }
6936 
6937 void Assembler::popa() { // 32bit
6938   emit_int8(0x61);
6939 }
6940 
6941 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
6942   InstructionMark im(this);
6943   emit_int8(0x68);
6944   emit_data(imm32, rspec, 0);
6945 }
6946 
6947 void Assembler::pusha() { // 32bit
6948   emit_int8(0x60);
6949 }
6950 
6951 void Assembler::set_byte_if_not_zero(Register dst) {
6952   emit_int8(0x0F);
6953   emit_int8((unsigned char)0x95);
6954   emit_int8((unsigned char)(0xE0 | dst->encoding()));
6955 }
6956 
6957 void Assembler::shldl(Register dst, Register src) {
6958   emit_int8(0x0F);
6959   emit_int8((unsigned char)0xA5);
6960   emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
6961 }
6962 
6963 // 0F A4 / r ib
6964 void Assembler::shldl(Register dst, Register src, int8_t imm8) {
6965   emit_int8(0x0F);
6966   emit_int8((unsigned char)0xA4);
6967   emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
6968   emit_int8(imm8);
6969 }
6970 
6971 void Assembler::shrdl(Register dst, Register src) {
6972   emit_int8(0x0F);
6973   emit_int8((unsigned char)0xAD);
6974   emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
6975 }
6976 
6977 #else // LP64
6978 
6979 void Assembler::set_byte_if_not_zero(Register dst) {
6980   int enc = prefix_and_encode(dst->encoding(), true);
6981   emit_int8(0x0F);
6982   emit_int8((unsigned char)0x95);
6983   emit_int8((unsigned char)(0xE0 | enc));
6984 }
6985 
6986 // 64bit only pieces of the assembler
6987 // This should only be used by 64bit instructions that can use rip-relative
6988 // it cannot be used by instructions that want an immediate value.
6989 
6990 bool Assembler::reachable(AddressLiteral adr) {
6991   int64_t disp;
6992   // None will force a 64bit literal to the code stream. Likely a placeholder
6993   // for something that will be patched later and we need to certain it will
6994   // always be reachable.
6995   if (adr.reloc() == relocInfo::none) {
6996     return false;
6997   }
6998   if (adr.reloc() == relocInfo::internal_word_type) {
6999     // This should be rip relative and easily reachable.
7000     return true;
7001   }
7002   if (adr.reloc() == relocInfo::virtual_call_type ||
7003       adr.reloc() == relocInfo::opt_virtual_call_type ||
7004       adr.reloc() == relocInfo::static_call_type ||
7005       adr.reloc() == relocInfo::static_stub_type ) {
7006     // This should be rip relative within the code cache and easily
7007     // reachable until we get huge code caches. (At which point
7008     // ic code is going to have issues).
7009     return true;
7010   }
7011   if (adr.reloc() != relocInfo::external_word_type &&
7012       adr.reloc() != relocInfo::poll_return_type &&  // these are really external_word but need special
7013       adr.reloc() != relocInfo::poll_type &&         // relocs to identify them
7014       adr.reloc() != relocInfo::runtime_call_type ) {
7015     return false;
7016   }
7017 
7018   // Stress the correction code
7019   if (ForceUnreachable) {
7020     // Must be runtimecall reloc, see if it is in the codecache
7021     // Flipping stuff in the codecache to be unreachable causes issues
7022     // with things like inline caches where the additional instructions
7023     // are not handled.
7024     if (CodeCache::find_blob(adr._target) == NULL) {
7025       return false;
7026     }
7027   }
7028   // For external_word_type/runtime_call_type if it is reachable from where we
7029   // are now (possibly a temp buffer) and where we might end up
7030   // anywhere in the codeCache then we are always reachable.
7031   // This would have to change if we ever save/restore shared code
7032   // to be more pessimistic.
7033   disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int));
7034   if (!is_simm32(disp)) return false;
7035   disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int));
7036   if (!is_simm32(disp)) return false;
7037 
7038   disp = (int64_t)adr._target - ((int64_t)pc() + sizeof(int));
7039 
7040   // Because rip relative is a disp + address_of_next_instruction and we
7041   // don't know the value of address_of_next_instruction we apply a fudge factor
7042   // to make sure we will be ok no matter the size of the instruction we get placed into.
7043   // We don't have to fudge the checks above here because they are already worst case.
7044 
7045   // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal
7046   // + 4 because better safe than sorry.
7047   const int fudge = 12 + 4;
7048   if (disp < 0) {
7049     disp -= fudge;
7050   } else {
7051     disp += fudge;
7052   }
7053   return is_simm32(disp);
7054 }
7055 
7056 // Check if the polling page is not reachable from the code cache using rip-relative
7057 // addressing.
7058 bool Assembler::is_polling_page_far() {
7059   intptr_t addr = (intptr_t)os::get_polling_page();
7060   return ForceUnreachable ||
7061          !is_simm32(addr - (intptr_t)CodeCache::low_bound()) ||
7062          !is_simm32(addr - (intptr_t)CodeCache::high_bound());
7063 }
7064 
7065 void Assembler::emit_data64(jlong data,
7066                             relocInfo::relocType rtype,
7067                             int format) {
7068   if (rtype == relocInfo::none) {
7069     emit_int64(data);
7070   } else {
7071     emit_data64(data, Relocation::spec_simple(rtype), format);
7072   }
7073 }
7074 
7075 void Assembler::emit_data64(jlong data,
7076                             RelocationHolder const& rspec,
7077                             int format) {
7078   assert(imm_operand == 0, "default format must be immediate in this file");
7079   assert(imm_operand == format, "must be immediate");
7080   assert(inst_mark() != NULL, "must be inside InstructionMark");
7081   // Do not use AbstractAssembler::relocate, which is not intended for
7082   // embedded words.  Instead, relocate to the enclosing instruction.
7083   code_section()->relocate(inst_mark(), rspec, format);
7084 #ifdef ASSERT
7085   check_relocation(rspec, format);
7086 #endif
7087   emit_int64(data);
7088 }
7089 
7090 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) {
7091   if (reg_enc >= 8) {
7092     prefix(REX_B);
7093     reg_enc -= 8;
7094   } else if (byteinst && reg_enc >= 4) {
7095     prefix(REX);
7096   }
7097   return reg_enc;
7098 }
7099 
7100 int Assembler::prefixq_and_encode(int reg_enc) {
7101   if (reg_enc < 8) {
7102     prefix(REX_W);
7103   } else {
7104     prefix(REX_WB);
7105     reg_enc -= 8;
7106   }
7107   return reg_enc;
7108 }
7109 
7110 int Assembler::prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte) {
7111   if (dst_enc < 8) {
7112     if (src_enc >= 8) {
7113       prefix(REX_B);
7114       src_enc -= 8;
7115     } else if ((src_is_byte && src_enc >= 4) || (dst_is_byte && dst_enc >= 4)) {
7116       prefix(REX);
7117     }
7118   } else {
7119     if (src_enc < 8) {
7120       prefix(REX_R);
7121     } else {
7122       prefix(REX_RB);
7123       src_enc -= 8;
7124     }
7125     dst_enc -= 8;
7126   }
7127   return dst_enc << 3 | src_enc;
7128 }
7129 
7130 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) {
7131   if (dst_enc < 8) {
7132     if (src_enc < 8) {
7133       prefix(REX_W);
7134     } else {
7135       prefix(REX_WB);
7136       src_enc -= 8;
7137     }
7138   } else {
7139     if (src_enc < 8) {
7140       prefix(REX_WR);
7141     } else {
7142       prefix(REX_WRB);
7143       src_enc -= 8;
7144     }
7145     dst_enc -= 8;
7146   }
7147   return dst_enc << 3 | src_enc;
7148 }
7149 
7150 void Assembler::prefix(Register reg) {
7151   if (reg->encoding() >= 8) {
7152     prefix(REX_B);
7153   }
7154 }
7155 
7156 void Assembler::prefix(Register dst, Register src, Prefix p) {
7157   if (src->encoding() >= 8) {
7158     p = (Prefix)(p | REX_B);
7159   }
7160   if (dst->encoding() >= 8) {
7161     p = (Prefix)( p | REX_R);
7162   }
7163   if (p != Prefix_EMPTY) {
7164     // do not generate an empty prefix
7165     prefix(p);
7166   }
7167 }
7168 
7169 void Assembler::prefix(Register dst, Address adr, Prefix p) {
7170   if (adr.base_needs_rex()) {
7171     if (adr.index_needs_rex()) {
7172       assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X");
7173     } else {
7174       prefix(REX_B);
7175     }
7176   } else {
7177     if (adr.index_needs_rex()) {
7178       assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X");
7179     }
7180   }
7181   if (dst->encoding() >= 8) {
7182     p = (Prefix)(p | REX_R);
7183   }
7184   if (p != Prefix_EMPTY) {
7185     // do not generate an empty prefix
7186     prefix(p);
7187   }
7188 }
7189 
7190 void Assembler::prefix(Address adr) {
7191   if (adr.base_needs_rex()) {
7192     if (adr.index_needs_rex()) {
7193       prefix(REX_XB);
7194     } else {
7195       prefix(REX_B);
7196     }
7197   } else {
7198     if (adr.index_needs_rex()) {
7199       prefix(REX_X);
7200     }
7201   }
7202 }
7203 
7204 void Assembler::prefixq(Address adr) {
7205   if (adr.base_needs_rex()) {
7206     if (adr.index_needs_rex()) {
7207       prefix(REX_WXB);
7208     } else {
7209       prefix(REX_WB);
7210     }
7211   } else {
7212     if (adr.index_needs_rex()) {
7213       prefix(REX_WX);
7214     } else {
7215       prefix(REX_W);
7216     }
7217   }
7218 }
7219 
7220 
7221 void Assembler::prefix(Address adr, Register reg, bool byteinst) {
7222   if (reg->encoding() < 8) {
7223     if (adr.base_needs_rex()) {
7224       if (adr.index_needs_rex()) {
7225         prefix(REX_XB);
7226       } else {
7227         prefix(REX_B);
7228       }
7229     } else {
7230       if (adr.index_needs_rex()) {
7231         prefix(REX_X);
7232       } else if (byteinst && reg->encoding() >= 4 ) {
7233         prefix(REX);
7234       }
7235     }
7236   } else {
7237     if (adr.base_needs_rex()) {
7238       if (adr.index_needs_rex()) {
7239         prefix(REX_RXB);
7240       } else {
7241         prefix(REX_RB);
7242       }
7243     } else {
7244       if (adr.index_needs_rex()) {
7245         prefix(REX_RX);
7246       } else {
7247         prefix(REX_R);
7248       }
7249     }
7250   }
7251 }
7252 
7253 void Assembler::prefixq(Address adr, Register src) {
7254   if (src->encoding() < 8) {
7255     if (adr.base_needs_rex()) {
7256       if (adr.index_needs_rex()) {
7257         prefix(REX_WXB);
7258       } else {
7259         prefix(REX_WB);
7260       }
7261     } else {
7262       if (adr.index_needs_rex()) {
7263         prefix(REX_WX);
7264       } else {
7265         prefix(REX_W);
7266       }
7267     }
7268   } else {
7269     if (adr.base_needs_rex()) {
7270       if (adr.index_needs_rex()) {
7271         prefix(REX_WRXB);
7272       } else {
7273         prefix(REX_WRB);
7274       }
7275     } else {
7276       if (adr.index_needs_rex()) {
7277         prefix(REX_WRX);
7278       } else {
7279         prefix(REX_WR);
7280       }
7281     }
7282   }
7283 }
7284 
7285 void Assembler::prefix(Address adr, XMMRegister reg) {
7286   if (reg->encoding() < 8) {
7287     if (adr.base_needs_rex()) {
7288       if (adr.index_needs_rex()) {
7289         prefix(REX_XB);
7290       } else {
7291         prefix(REX_B);
7292       }
7293     } else {
7294       if (adr.index_needs_rex()) {
7295         prefix(REX_X);
7296       }
7297     }
7298   } else {
7299     if (adr.base_needs_rex()) {
7300       if (adr.index_needs_rex()) {
7301         prefix(REX_RXB);
7302       } else {
7303         prefix(REX_RB);
7304       }
7305     } else {
7306       if (adr.index_needs_rex()) {
7307         prefix(REX_RX);
7308       } else {
7309         prefix(REX_R);
7310       }
7311     }
7312   }
7313 }
7314 
7315 void Assembler::prefixq(Address adr, XMMRegister src) {
7316   if (src->encoding() < 8) {
7317     if (adr.base_needs_rex()) {
7318       if (adr.index_needs_rex()) {
7319         prefix(REX_WXB);
7320       } else {
7321         prefix(REX_WB);
7322       }
7323     } else {
7324       if (adr.index_needs_rex()) {
7325         prefix(REX_WX);
7326       } else {
7327         prefix(REX_W);
7328       }
7329     }
7330   } else {
7331     if (adr.base_needs_rex()) {
7332       if (adr.index_needs_rex()) {
7333         prefix(REX_WRXB);
7334       } else {
7335         prefix(REX_WRB);
7336       }
7337     } else {
7338       if (adr.index_needs_rex()) {
7339         prefix(REX_WRX);
7340       } else {
7341         prefix(REX_WR);
7342       }
7343     }
7344   }
7345 }
7346 
7347 void Assembler::adcq(Register dst, int32_t imm32) {
7348   (void) prefixq_and_encode(dst->encoding());
7349   emit_arith(0x81, 0xD0, dst, imm32);
7350 }
7351 
7352 void Assembler::adcq(Register dst, Address src) {
7353   InstructionMark im(this);
7354   prefixq(src, dst);
7355   emit_int8(0x13);
7356   emit_operand(dst, src);
7357 }
7358 
7359 void Assembler::adcq(Register dst, Register src) {
7360   (void) prefixq_and_encode(dst->encoding(), src->encoding());
7361   emit_arith(0x13, 0xC0, dst, src);
7362 }
7363 
7364 void Assembler::addq(Address dst, int32_t imm32) {
7365   InstructionMark im(this);
7366   prefixq(dst);
7367   emit_arith_operand(0x81, rax, dst,imm32);
7368 }
7369 
7370 void Assembler::addq(Address dst, Register src) {
7371   InstructionMark im(this);
7372   prefixq(dst, src);
7373   emit_int8(0x01);
7374   emit_operand(src, dst);
7375 }
7376 
7377 void Assembler::addq(Register dst, int32_t imm32) {
7378   (void) prefixq_and_encode(dst->encoding());
7379   emit_arith(0x81, 0xC0, dst, imm32);
7380 }
7381 
7382 void Assembler::addq(Register dst, Address src) {
7383   InstructionMark im(this);
7384   prefixq(src, dst);
7385   emit_int8(0x03);
7386   emit_operand(dst, src);
7387 }
7388 
7389 void Assembler::addq(Register dst, Register src) {
7390   (void) prefixq_and_encode(dst->encoding(), src->encoding());
7391   emit_arith(0x03, 0xC0, dst, src);
7392 }
7393 
7394 void Assembler::adcxq(Register dst, Register src) {
7395   //assert(VM_Version::supports_adx(), "adx instructions not supported");
7396   emit_int8((unsigned char)0x66);
7397   int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7398   emit_int8(0x0F);
7399   emit_int8(0x38);
7400   emit_int8((unsigned char)0xF6);
7401   emit_int8((unsigned char)(0xC0 | encode));
7402 }
7403 
7404 void Assembler::adoxq(Register dst, Register src) {
7405   //assert(VM_Version::supports_adx(), "adx instructions not supported");
7406   emit_int8((unsigned char)0xF3);
7407   int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7408   emit_int8(0x0F);
7409   emit_int8(0x38);
7410   emit_int8((unsigned char)0xF6);
7411   emit_int8((unsigned char)(0xC0 | encode));
7412 }
7413 
7414 void Assembler::andq(Address dst, int32_t imm32) {
7415   InstructionMark im(this);
7416   prefixq(dst);
7417   emit_int8((unsigned char)0x81);
7418   emit_operand(rsp, dst, 4);
7419   emit_int32(imm32);
7420 }
7421 
7422 void Assembler::andq(Register dst, int32_t imm32) {
7423   (void) prefixq_and_encode(dst->encoding());
7424   emit_arith(0x81, 0xE0, dst, imm32);
7425 }
7426 
7427 void Assembler::andq(Register dst, Address src) {
7428   InstructionMark im(this);
7429   prefixq(src, dst);
7430   emit_int8(0x23);
7431   emit_operand(dst, src);
7432 }
7433 
7434 void Assembler::andq(Register dst, Register src) {
7435   (void) prefixq_and_encode(dst->encoding(), src->encoding());
7436   emit_arith(0x23, 0xC0, dst, src);
7437 }
7438 
7439 void Assembler::andnq(Register dst, Register src1, Register src2) {
7440   assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7441   InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7442   int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7443   emit_int8((unsigned char)0xF2);
7444   emit_int8((unsigned char)(0xC0 | encode));
7445 }
7446 
7447 void Assembler::andnq(Register dst, Register src1, Address src2) {
7448   assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7449   InstructionMark im(this);
7450   InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7451   vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7452   emit_int8((unsigned char)0xF2);
7453   emit_operand(dst, src2);
7454 }
7455 
7456 void Assembler::bsfq(Register dst, Register src) {
7457   int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7458   emit_int8(0x0F);
7459   emit_int8((unsigned char)0xBC);
7460   emit_int8((unsigned char)(0xC0 | encode));
7461 }
7462 
7463 void Assembler::bsrq(Register dst, Register src) {
7464   int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7465   emit_int8(0x0F);
7466   emit_int8((unsigned char)0xBD);
7467   emit_int8((unsigned char)(0xC0 | encode));
7468 }
7469 
7470 void Assembler::bswapq(Register reg) {
7471   int encode = prefixq_and_encode(reg->encoding());
7472   emit_int8(0x0F);
7473   emit_int8((unsigned char)(0xC8 | encode));
7474 }
7475 
7476 void Assembler::blsiq(Register dst, Register src) {
7477   assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7478   InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7479   int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7480   emit_int8((unsigned char)0xF3);
7481   emit_int8((unsigned char)(0xC0 | encode));
7482 }
7483 
7484 void Assembler::blsiq(Register dst, Address src) {
7485   assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7486   InstructionMark im(this);
7487   InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7488   vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7489   emit_int8((unsigned char)0xF3);
7490   emit_operand(rbx, src);
7491 }
7492 
7493 void Assembler::blsmskq(Register dst, Register src) {
7494   assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7495   InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7496   int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7497   emit_int8((unsigned char)0xF3);
7498   emit_int8((unsigned char)(0xC0 | encode));
7499 }
7500 
7501 void Assembler::blsmskq(Register dst, Address src) {
7502   assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7503   InstructionMark im(this);
7504   InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7505   vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7506   emit_int8((unsigned char)0xF3);
7507   emit_operand(rdx, src);
7508 }
7509 
7510 void Assembler::blsrq(Register dst, Register src) {
7511   assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7512   InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7513   int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7514   emit_int8((unsigned char)0xF3);
7515   emit_int8((unsigned char)(0xC0 | encode));
7516 }
7517 
7518 void Assembler::blsrq(Register dst, Address src) {
7519   assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7520   InstructionMark im(this);
7521   InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7522   vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7523   emit_int8((unsigned char)0xF3);
7524   emit_operand(rcx, src);
7525 }
7526 
7527 void Assembler::cdqq() {
7528   prefix(REX_W);
7529   emit_int8((unsigned char)0x99);
7530 }
7531 
7532 void Assembler::clflush(Address adr) {
7533   prefix(adr);
7534   emit_int8(0x0F);
7535   emit_int8((unsigned char)0xAE);
7536   emit_operand(rdi, adr);
7537 }
7538 
7539 void Assembler::cmovq(Condition cc, Register dst, Register src) {
7540   int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7541   emit_int8(0x0F);
7542   emit_int8(0x40 | cc);
7543   emit_int8((unsigned char)(0xC0 | encode));
7544 }
7545 
7546 void Assembler::cmovq(Condition cc, Register dst, Address src) {
7547   InstructionMark im(this);
7548   prefixq(src, dst);
7549   emit_int8(0x0F);
7550   emit_int8(0x40 | cc);
7551   emit_operand(dst, src);
7552 }
7553 
7554 void Assembler::cmpq(Address dst, int32_t imm32) {
7555   InstructionMark im(this);
7556   prefixq(dst);
7557   emit_int8((unsigned char)0x81);
7558   emit_operand(rdi, dst, 4);
7559   emit_int32(imm32);
7560 }
7561 
7562 void Assembler::cmpq(Register dst, int32_t imm32) {
7563   (void) prefixq_and_encode(dst->encoding());
7564   emit_arith(0x81, 0xF8, dst, imm32);
7565 }
7566 
7567 void Assembler::cmpq(Address dst, Register src) {
7568   InstructionMark im(this);
7569   prefixq(dst, src);
7570   emit_int8(0x3B);
7571   emit_operand(src, dst);
7572 }
7573 
7574 void Assembler::cmpq(Register dst, Register src) {
7575   (void) prefixq_and_encode(dst->encoding(), src->encoding());
7576   emit_arith(0x3B, 0xC0, dst, src);
7577 }
7578 
7579 void Assembler::cmpq(Register dst, Address  src) {
7580   InstructionMark im(this);
7581   prefixq(src, dst);
7582   emit_int8(0x3B);
7583   emit_operand(dst, src);
7584 }
7585 
7586 void Assembler::cmpxchgq(Register reg, Address adr) {
7587   InstructionMark im(this);
7588   prefixq(adr, reg);
7589   emit_int8(0x0F);
7590   emit_int8((unsigned char)0xB1);
7591   emit_operand(reg, adr);
7592 }
7593 
7594 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
7595   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7596   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7597   int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
7598   emit_int8(0x2A);
7599   emit_int8((unsigned char)(0xC0 | encode));
7600 }
7601 
7602 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) {
7603   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7604   InstructionMark im(this);
7605   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7606   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
7607   simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
7608   emit_int8(0x2A);
7609   emit_operand(dst, src);
7610 }
7611 
7612 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) {
7613   NOT_LP64(assert(VM_Version::supports_sse(), ""));
7614   InstructionMark im(this);
7615   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7616   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
7617   simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
7618   emit_int8(0x2A);
7619   emit_operand(dst, src);
7620 }
7621 
7622 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
7623   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7624   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7625   int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
7626   emit_int8(0x2C);
7627   emit_int8((unsigned char)(0xC0 | encode));
7628 }
7629 
7630 void Assembler::cvttss2siq(Register dst, XMMRegister src) {
7631   NOT_LP64(assert(VM_Version::supports_sse(), ""));
7632   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7633   int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
7634   emit_int8(0x2C);
7635   emit_int8((unsigned char)(0xC0 | encode));
7636 }
7637 
7638 void Assembler::decl(Register dst) {
7639   // Don't use it directly. Use MacroAssembler::decrementl() instead.
7640   // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
7641   int encode = prefix_and_encode(dst->encoding());
7642   emit_int8((unsigned char)0xFF);
7643   emit_int8((unsigned char)(0xC8 | encode));
7644 }
7645 
7646 void Assembler::decq(Register dst) {
7647   // Don't use it directly. Use MacroAssembler::decrementq() instead.
7648   // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
7649   int encode = prefixq_and_encode(dst->encoding());
7650   emit_int8((unsigned char)0xFF);
7651   emit_int8(0xC8 | encode);
7652 }
7653 
7654 void Assembler::decq(Address dst) {
7655   // Don't use it directly. Use MacroAssembler::decrementq() instead.
7656   InstructionMark im(this);
7657   prefixq(dst);
7658   emit_int8((unsigned char)0xFF);
7659   emit_operand(rcx, dst);
7660 }
7661 
7662 void Assembler::fxrstor(Address src) {
7663   prefixq(src);
7664   emit_int8(0x0F);
7665   emit_int8((unsigned char)0xAE);
7666   emit_operand(as_Register(1), src);
7667 }
7668 
7669 void Assembler::xrstor(Address src) {
7670   prefixq(src);
7671   emit_int8(0x0F);
7672   emit_int8((unsigned char)0xAE);
7673   emit_operand(as_Register(5), src);
7674 }
7675 
7676 void Assembler::fxsave(Address dst) {
7677   prefixq(dst);
7678   emit_int8(0x0F);
7679   emit_int8((unsigned char)0xAE);
7680   emit_operand(as_Register(0), dst);
7681 }
7682 
7683 void Assembler::xsave(Address dst) {
7684   prefixq(dst);
7685   emit_int8(0x0F);
7686   emit_int8((unsigned char)0xAE);
7687   emit_operand(as_Register(4), dst);
7688 }
7689 
7690 void Assembler::idivq(Register src) {
7691   int encode = prefixq_and_encode(src->encoding());
7692   emit_int8((unsigned char)0xF7);
7693   emit_int8((unsigned char)(0xF8 | encode));
7694 }
7695 
7696 void Assembler::imulq(Register dst, Register src) {
7697   int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7698   emit_int8(0x0F);
7699   emit_int8((unsigned char)0xAF);
7700   emit_int8((unsigned char)(0xC0 | encode));
7701 }
7702 
7703 void Assembler::imulq(Register dst, Register src, int value) {
7704   int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7705   if (is8bit(value)) {
7706     emit_int8(0x6B);
7707     emit_int8((unsigned char)(0xC0 | encode));
7708     emit_int8(value & 0xFF);
7709   } else {
7710     emit_int8(0x69);
7711     emit_int8((unsigned char)(0xC0 | encode));
7712     emit_int32(value);
7713   }
7714 }
7715 
7716 void Assembler::imulq(Register dst, Address src) {
7717   InstructionMark im(this);
7718   prefixq(src, dst);
7719   emit_int8(0x0F);
7720   emit_int8((unsigned char) 0xAF);
7721   emit_operand(dst, src);
7722 }
7723 
7724 void Assembler::incl(Register dst) {
7725   // Don't use it directly. Use MacroAssembler::incrementl() instead.
7726   // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
7727   int encode = prefix_and_encode(dst->encoding());
7728   emit_int8((unsigned char)0xFF);
7729   emit_int8((unsigned char)(0xC0 | encode));
7730 }
7731 
7732 void Assembler::incq(Register dst) {
7733   // Don't use it directly. Use MacroAssembler::incrementq() instead.
7734   // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
7735   int encode = prefixq_and_encode(dst->encoding());
7736   emit_int8((unsigned char)0xFF);
7737   emit_int8((unsigned char)(0xC0 | encode));
7738 }
7739 
7740 void Assembler::incq(Address dst) {
7741   // Don't use it directly. Use MacroAssembler::incrementq() instead.
7742   InstructionMark im(this);
7743   prefixq(dst);
7744   emit_int8((unsigned char)0xFF);
7745   emit_operand(rax, dst);
7746 }
7747 
7748 void Assembler::lea(Register dst, Address src) {
7749   leaq(dst, src);
7750 }
7751 
7752 void Assembler::leaq(Register dst, Address src) {
7753   InstructionMark im(this);
7754   prefixq(src, dst);
7755   emit_int8((unsigned char)0x8D);
7756   emit_operand(dst, src);
7757 }
7758 
7759 void Assembler::mov64(Register dst, int64_t imm64) {
7760   InstructionMark im(this);
7761   int encode = prefixq_and_encode(dst->encoding());
7762   emit_int8((unsigned char)(0xB8 | encode));
7763   emit_int64(imm64);
7764 }
7765 
7766 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) {
7767   InstructionMark im(this);
7768   int encode = prefixq_and_encode(dst->encoding());
7769   emit_int8(0xB8 | encode);
7770   emit_data64(imm64, rspec);
7771 }
7772 
7773 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) {
7774   InstructionMark im(this);
7775   int encode = prefix_and_encode(dst->encoding());
7776   emit_int8((unsigned char)(0xB8 | encode));
7777   emit_data((int)imm32, rspec, narrow_oop_operand);
7778 }
7779 
7780 void Assembler::mov_narrow_oop(Address dst, int32_t imm32,  RelocationHolder const& rspec) {
7781   InstructionMark im(this);
7782   prefix(dst);
7783   emit_int8((unsigned char)0xC7);
7784   emit_operand(rax, dst, 4);
7785   emit_data((int)imm32, rspec, narrow_oop_operand);
7786 }
7787 
7788 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) {
7789   InstructionMark im(this);
7790   int encode = prefix_and_encode(src1->encoding());
7791   emit_int8((unsigned char)0x81);
7792   emit_int8((unsigned char)(0xF8 | encode));
7793   emit_data((int)imm32, rspec, narrow_oop_operand);
7794 }
7795 
7796 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) {
7797   InstructionMark im(this);
7798   prefix(src1);
7799   emit_int8((unsigned char)0x81);
7800   emit_operand(rax, src1, 4);
7801   emit_data((int)imm32, rspec, narrow_oop_operand);
7802 }
7803 
7804 void Assembler::lzcntq(Register dst, Register src) {
7805   assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
7806   emit_int8((unsigned char)0xF3);
7807   int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7808   emit_int8(0x0F);
7809   emit_int8((unsigned char)0xBD);
7810   emit_int8((unsigned char)(0xC0 | encode));
7811 }
7812 
7813 void Assembler::movdq(XMMRegister dst, Register src) {
7814   // table D-1 says MMX/SSE2
7815   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7816   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7817   int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7818   emit_int8(0x6E);
7819   emit_int8((unsigned char)(0xC0 | encode));
7820 }
7821 
7822 void Assembler::movdq(Register dst, XMMRegister src) {
7823   // table D-1 says MMX/SSE2
7824   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7825   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7826   // swap src/dst to get correct prefix
7827   int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7828   emit_int8(0x7E);
7829   emit_int8((unsigned char)(0xC0 | encode));
7830 }
7831 
7832 void Assembler::movq(Register dst, Register src) {
7833   int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7834   emit_int8((unsigned char)0x8B);
7835   emit_int8((unsigned char)(0xC0 | encode));
7836 }
7837 
7838 void Assembler::movq(Register dst, Address src) {
7839   InstructionMark im(this);
7840   prefixq(src, dst);
7841   emit_int8((unsigned char)0x8B);
7842   emit_operand(dst, src);
7843 }
7844 
7845 void Assembler::movq(Address dst, Register src) {
7846   InstructionMark im(this);
7847   prefixq(dst, src);
7848   emit_int8((unsigned char)0x89);
7849   emit_operand(src, dst);
7850 }
7851 
7852 void Assembler::movsbq(Register dst, Address src) {
7853   InstructionMark im(this);
7854   prefixq(src, dst);
7855   emit_int8(0x0F);
7856   emit_int8((unsigned char)0xBE);
7857   emit_operand(dst, src);
7858 }
7859 
7860 void Assembler::movsbq(Register dst, Register src) {
7861   int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7862   emit_int8(0x0F);
7863   emit_int8((unsigned char)0xBE);
7864   emit_int8((unsigned char)(0xC0 | encode));
7865 }
7866 
7867 void Assembler::movslq(Register dst, int32_t imm32) {
7868   // dbx shows movslq(rcx, 3) as movq     $0x0000000049000000,(%rbx)
7869   // and movslq(r8, 3); as movl     $0x0000000048000000,(%rbx)
7870   // as a result we shouldn't use until tested at runtime...
7871   ShouldNotReachHere();
7872   InstructionMark im(this);
7873   int encode = prefixq_and_encode(dst->encoding());
7874   emit_int8((unsigned char)(0xC7 | encode));
7875   emit_int32(imm32);
7876 }
7877 
7878 void Assembler::movslq(Address dst, int32_t imm32) {
7879   assert(is_simm32(imm32), "lost bits");
7880   InstructionMark im(this);
7881   prefixq(dst);
7882   emit_int8((unsigned char)0xC7);
7883   emit_operand(rax, dst, 4);
7884   emit_int32(imm32);
7885 }
7886 
7887 void Assembler::movslq(Register dst, Address src) {
7888   InstructionMark im(this);
7889   prefixq(src, dst);
7890   emit_int8(0x63);
7891   emit_operand(dst, src);
7892 }
7893 
7894 void Assembler::movslq(Register dst, Register src) {
7895   int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7896   emit_int8(0x63);
7897   emit_int8((unsigned char)(0xC0 | encode));
7898 }
7899 
7900 void Assembler::movswq(Register dst, Address src) {
7901   InstructionMark im(this);
7902   prefixq(src, dst);
7903   emit_int8(0x0F);
7904   emit_int8((unsigned char)0xBF);
7905   emit_operand(dst, src);
7906 }
7907 
7908 void Assembler::movswq(Register dst, Register src) {
7909   int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7910   emit_int8((unsigned char)0x0F);
7911   emit_int8((unsigned char)0xBF);
7912   emit_int8((unsigned char)(0xC0 | encode));
7913 }
7914 
7915 void Assembler::movzbq(Register dst, Address src) {
7916   InstructionMark im(this);
7917   prefixq(src, dst);
7918   emit_int8((unsigned char)0x0F);
7919   emit_int8((unsigned char)0xB6);
7920   emit_operand(dst, src);
7921 }
7922 
7923 void Assembler::movzbq(Register dst, Register src) {
7924   int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7925   emit_int8(0x0F);
7926   emit_int8((unsigned char)0xB6);
7927   emit_int8(0xC0 | encode);
7928 }
7929 
7930 void Assembler::movzwq(Register dst, Address src) {
7931   InstructionMark im(this);
7932   prefixq(src, dst);
7933   emit_int8((unsigned char)0x0F);
7934   emit_int8((unsigned char)0xB7);
7935   emit_operand(dst, src);
7936 }
7937 
7938 void Assembler::movzwq(Register dst, Register src) {
7939   int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7940   emit_int8((unsigned char)0x0F);
7941   emit_int8((unsigned char)0xB7);
7942   emit_int8((unsigned char)(0xC0 | encode));
7943 }
7944 
7945 void Assembler::mulq(Address src) {
7946   InstructionMark im(this);
7947   prefixq(src);
7948   emit_int8((unsigned char)0xF7);
7949   emit_operand(rsp, src);
7950 }
7951 
7952 void Assembler::mulq(Register src) {
7953   int encode = prefixq_and_encode(src->encoding());
7954   emit_int8((unsigned char)0xF7);
7955   emit_int8((unsigned char)(0xE0 | encode));
7956 }
7957 
7958 void Assembler::mulxq(Register dst1, Register dst2, Register src) {
7959   assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
7960   InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7961   int encode = vex_prefix_and_encode(dst1->encoding(), dst2->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
7962   emit_int8((unsigned char)0xF6);
7963   emit_int8((unsigned char)(0xC0 | encode));
7964 }
7965 
7966 void Assembler::negq(Register dst) {
7967   int encode = prefixq_and_encode(dst->encoding());
7968   emit_int8((unsigned char)0xF7);
7969   emit_int8((unsigned char)(0xD8 | encode));
7970 }
7971 
7972 void Assembler::notq(Register dst) {
7973   int encode = prefixq_and_encode(dst->encoding());
7974   emit_int8((unsigned char)0xF7);
7975   emit_int8((unsigned char)(0xD0 | encode));
7976 }
7977 
7978 void Assembler::orq(Address dst, int32_t imm32) {
7979   InstructionMark im(this);
7980   prefixq(dst);
7981   emit_int8((unsigned char)0x81);
7982   emit_operand(rcx, dst, 4);
7983   emit_int32(imm32);
7984 }
7985 
7986 void Assembler::orq(Register dst, int32_t imm32) {
7987   (void) prefixq_and_encode(dst->encoding());
7988   emit_arith(0x81, 0xC8, dst, imm32);
7989 }
7990 
7991 void Assembler::orq(Register dst, Address src) {
7992   InstructionMark im(this);
7993   prefixq(src, dst);
7994   emit_int8(0x0B);
7995   emit_operand(dst, src);
7996 }
7997 
7998 void Assembler::orq(Register dst, Register src) {
7999   (void) prefixq_and_encode(dst->encoding(), src->encoding());
8000   emit_arith(0x0B, 0xC0, dst, src);
8001 }
8002 
8003 void Assembler::popa() { // 64bit
8004   movq(r15, Address(rsp, 0));
8005   movq(r14, Address(rsp, wordSize));
8006   movq(r13, Address(rsp, 2 * wordSize));
8007   movq(r12, Address(rsp, 3 * wordSize));
8008   movq(r11, Address(rsp, 4 * wordSize));
8009   movq(r10, Address(rsp, 5 * wordSize));
8010   movq(r9,  Address(rsp, 6 * wordSize));
8011   movq(r8,  Address(rsp, 7 * wordSize));
8012   movq(rdi, Address(rsp, 8 * wordSize));
8013   movq(rsi, Address(rsp, 9 * wordSize));
8014   movq(rbp, Address(rsp, 10 * wordSize));
8015   // skip rsp
8016   movq(rbx, Address(rsp, 12 * wordSize));
8017   movq(rdx, Address(rsp, 13 * wordSize));
8018   movq(rcx, Address(rsp, 14 * wordSize));
8019   movq(rax, Address(rsp, 15 * wordSize));
8020 
8021   addq(rsp, 16 * wordSize);
8022 }
8023 
8024 void Assembler::popcntq(Register dst, Address src) {
8025   assert(VM_Version::supports_popcnt(), "must support");
8026   InstructionMark im(this);
8027   emit_int8((unsigned char)0xF3);
8028   prefixq(src, dst);
8029   emit_int8((unsigned char)0x0F);
8030   emit_int8((unsigned char)0xB8);
8031   emit_operand(dst, src);
8032 }
8033 
8034 void Assembler::popcntq(Register dst, Register src) {
8035   assert(VM_Version::supports_popcnt(), "must support");
8036   emit_int8((unsigned char)0xF3);
8037   int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8038   emit_int8((unsigned char)0x0F);
8039   emit_int8((unsigned char)0xB8);
8040   emit_int8((unsigned char)(0xC0 | encode));
8041 }
8042 
8043 void Assembler::popq(Address dst) {
8044   InstructionMark im(this);
8045   prefixq(dst);
8046   emit_int8((unsigned char)0x8F);
8047   emit_operand(rax, dst);
8048 }
8049 
8050 void Assembler::pusha() { // 64bit
8051   // we have to store original rsp.  ABI says that 128 bytes
8052   // below rsp are local scratch.
8053   movq(Address(rsp, -5 * wordSize), rsp);
8054 
8055   subq(rsp, 16 * wordSize);
8056 
8057   movq(Address(rsp, 15 * wordSize), rax);
8058   movq(Address(rsp, 14 * wordSize), rcx);
8059   movq(Address(rsp, 13 * wordSize), rdx);
8060   movq(Address(rsp, 12 * wordSize), rbx);
8061   // skip rsp
8062   movq(Address(rsp, 10 * wordSize), rbp);
8063   movq(Address(rsp, 9 * wordSize), rsi);
8064   movq(Address(rsp, 8 * wordSize), rdi);
8065   movq(Address(rsp, 7 * wordSize), r8);
8066   movq(Address(rsp, 6 * wordSize), r9);
8067   movq(Address(rsp, 5 * wordSize), r10);
8068   movq(Address(rsp, 4 * wordSize), r11);
8069   movq(Address(rsp, 3 * wordSize), r12);
8070   movq(Address(rsp, 2 * wordSize), r13);
8071   movq(Address(rsp, wordSize), r14);
8072   movq(Address(rsp, 0), r15);
8073 }
8074 
8075 void Assembler::pushq(Address src) {
8076   InstructionMark im(this);
8077   prefixq(src);
8078   emit_int8((unsigned char)0xFF);
8079   emit_operand(rsi, src);
8080 }
8081 
8082 void Assembler::rclq(Register dst, int imm8) {
8083   assert(isShiftCount(imm8 >> 1), "illegal shift count");
8084   int encode = prefixq_and_encode(dst->encoding());
8085   if (imm8 == 1) {
8086     emit_int8((unsigned char)0xD1);
8087     emit_int8((unsigned char)(0xD0 | encode));
8088   } else {
8089     emit_int8((unsigned char)0xC1);
8090     emit_int8((unsigned char)(0xD0 | encode));
8091     emit_int8(imm8);
8092   }
8093 }
8094 
8095 void Assembler::rcrq(Register dst, int imm8) {
8096   assert(isShiftCount(imm8 >> 1), "illegal shift count");
8097   int encode = prefixq_and_encode(dst->encoding());
8098   if (imm8 == 1) {
8099     emit_int8((unsigned char)0xD1);
8100     emit_int8((unsigned char)(0xD8 | encode));
8101   } else {
8102     emit_int8((unsigned char)0xC1);
8103     emit_int8((unsigned char)(0xD8 | encode));
8104     emit_int8(imm8);
8105   }
8106 }
8107 
8108 void Assembler::rorq(Register dst, int imm8) {
8109   assert(isShiftCount(imm8 >> 1), "illegal shift count");
8110   int encode = prefixq_and_encode(dst->encoding());
8111   if (imm8 == 1) {
8112     emit_int8((unsigned char)0xD1);
8113     emit_int8((unsigned char)(0xC8 | encode));
8114   } else {
8115     emit_int8((unsigned char)0xC1);
8116     emit_int8((unsigned char)(0xc8 | encode));
8117     emit_int8(imm8);
8118   }
8119 }
8120 
8121 void Assembler::rorxq(Register dst, Register src, int imm8) {
8122   assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
8123   InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
8124   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes);
8125   emit_int8((unsigned char)0xF0);
8126   emit_int8((unsigned char)(0xC0 | encode));
8127   emit_int8(imm8);
8128 }
8129 
8130 void Assembler::sarq(Register dst, int imm8) {
8131   assert(isShiftCount(imm8 >> 1), "illegal shift count");
8132   int encode = prefixq_and_encode(dst->encoding());
8133   if (imm8 == 1) {
8134     emit_int8((unsigned char)0xD1);
8135     emit_int8((unsigned char)(0xF8 | encode));
8136   } else {
8137     emit_int8((unsigned char)0xC1);
8138     emit_int8((unsigned char)(0xF8 | encode));
8139     emit_int8(imm8);
8140   }
8141 }
8142 
8143 void Assembler::sarq(Register dst) {
8144   int encode = prefixq_and_encode(dst->encoding());
8145   emit_int8((unsigned char)0xD3);
8146   emit_int8((unsigned char)(0xF8 | encode));
8147 }
8148 
8149 void Assembler::sbbq(Address dst, int32_t imm32) {
8150   InstructionMark im(this);
8151   prefixq(dst);
8152   emit_arith_operand(0x81, rbx, dst, imm32);
8153 }
8154 
8155 void Assembler::sbbq(Register dst, int32_t imm32) {
8156   (void) prefixq_and_encode(dst->encoding());
8157   emit_arith(0x81, 0xD8, dst, imm32);
8158 }
8159 
8160 void Assembler::sbbq(Register dst, Address src) {
8161   InstructionMark im(this);
8162   prefixq(src, dst);
8163   emit_int8(0x1B);
8164   emit_operand(dst, src);
8165 }
8166 
8167 void Assembler::sbbq(Register dst, Register src) {
8168   (void) prefixq_and_encode(dst->encoding(), src->encoding());
8169   emit_arith(0x1B, 0xC0, dst, src);
8170 }
8171 
8172 void Assembler::shlq(Register dst, int imm8) {
8173   assert(isShiftCount(imm8 >> 1), "illegal shift count");
8174   int encode = prefixq_and_encode(dst->encoding());
8175   if (imm8 == 1) {
8176     emit_int8((unsigned char)0xD1);
8177     emit_int8((unsigned char)(0xE0 | encode));
8178   } else {
8179     emit_int8((unsigned char)0xC1);
8180     emit_int8((unsigned char)(0xE0 | encode));
8181     emit_int8(imm8);
8182   }
8183 }
8184 
8185 void Assembler::shlq(Register dst) {
8186   int encode = prefixq_and_encode(dst->encoding());
8187   emit_int8((unsigned char)0xD3);
8188   emit_int8((unsigned char)(0xE0 | encode));
8189 }
8190 
8191 void Assembler::shrq(Register dst, int imm8) {
8192   assert(isShiftCount(imm8 >> 1), "illegal shift count");
8193   int encode = prefixq_and_encode(dst->encoding());
8194   emit_int8((unsigned char)0xC1);
8195   emit_int8((unsigned char)(0xE8 | encode));
8196   emit_int8(imm8);
8197 }
8198 
8199 void Assembler::shrq(Register dst) {
8200   int encode = prefixq_and_encode(dst->encoding());
8201   emit_int8((unsigned char)0xD3);
8202   emit_int8(0xE8 | encode);
8203 }
8204 
8205 void Assembler::subq(Address dst, int32_t imm32) {
8206   InstructionMark im(this);
8207   prefixq(dst);
8208   emit_arith_operand(0x81, rbp, dst, imm32);
8209 }
8210 
8211 void Assembler::subq(Address dst, Register src) {
8212   InstructionMark im(this);
8213   prefixq(dst, src);
8214   emit_int8(0x29);
8215   emit_operand(src, dst);
8216 }
8217 
8218 void Assembler::subq(Register dst, int32_t imm32) {
8219   (void) prefixq_and_encode(dst->encoding());
8220   emit_arith(0x81, 0xE8, dst, imm32);
8221 }
8222 
8223 // Force generation of a 4 byte immediate value even if it fits into 8bit
8224 void Assembler::subq_imm32(Register dst, int32_t imm32) {
8225   (void) prefixq_and_encode(dst->encoding());
8226   emit_arith_imm32(0x81, 0xE8, dst, imm32);
8227 }
8228 
8229 void Assembler::subq(Register dst, Address src) {
8230   InstructionMark im(this);
8231   prefixq(src, dst);
8232   emit_int8(0x2B);
8233   emit_operand(dst, src);
8234 }
8235 
8236 void Assembler::subq(Register dst, Register src) {
8237   (void) prefixq_and_encode(dst->encoding(), src->encoding());
8238   emit_arith(0x2B, 0xC0, dst, src);
8239 }
8240 
8241 void Assembler::testq(Register dst, int32_t imm32) {
8242   // not using emit_arith because test
8243   // doesn't support sign-extension of
8244   // 8bit operands
8245   int encode = dst->encoding();
8246   if (encode == 0) {
8247     prefix(REX_W);
8248     emit_int8((unsigned char)0xA9);
8249   } else {
8250     encode = prefixq_and_encode(encode);
8251     emit_int8((unsigned char)0xF7);
8252     emit_int8((unsigned char)(0xC0 | encode));
8253   }
8254   emit_int32(imm32);
8255 }
8256 
8257 void Assembler::testq(Register dst, Register src) {
8258   (void) prefixq_and_encode(dst->encoding(), src->encoding());
8259   emit_arith(0x85, 0xC0, dst, src);
8260 }
8261 
8262 void Assembler::xaddq(Address dst, Register src) {
8263   InstructionMark im(this);
8264   prefixq(dst, src);
8265   emit_int8(0x0F);
8266   emit_int8((unsigned char)0xC1);
8267   emit_operand(src, dst);
8268 }
8269 
8270 void Assembler::xchgq(Register dst, Address src) {
8271   InstructionMark im(this);
8272   prefixq(src, dst);
8273   emit_int8((unsigned char)0x87);
8274   emit_operand(dst, src);
8275 }
8276 
8277 void Assembler::xchgq(Register dst, Register src) {
8278   int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8279   emit_int8((unsigned char)0x87);
8280   emit_int8((unsigned char)(0xc0 | encode));
8281 }
8282 
8283 void Assembler::xorq(Register dst, Register src) {
8284   (void) prefixq_and_encode(dst->encoding(), src->encoding());
8285   emit_arith(0x33, 0xC0, dst, src);
8286 }
8287 
8288 void Assembler::xorq(Register dst, Address src) {
8289   InstructionMark im(this);
8290   prefixq(src, dst);
8291   emit_int8(0x33);
8292   emit_operand(dst, src);
8293 }
8294 
8295 #endif // !LP64