1810 emit_operand(dst, src);
1811 }
1812
1813
1814 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
1815 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1816 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1817 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1818 emit_int8(0x2C);
1819 emit_int8((unsigned char)(0xC0 | encode));
1820 }
1821
1822 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
1823 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1824 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1825 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1826 emit_int8(0x2C);
1827 emit_int8((unsigned char)(0xC0 | encode));
1828 }
1829
1830 void Assembler::decl(Address dst) {
1831 // Don't use it directly. Use MacroAssembler::decrement() instead.
1832 InstructionMark im(this);
1833 prefix(dst);
1834 emit_int8((unsigned char)0xFF);
1835 emit_operand(rcx, dst);
1836 }
1837
1838 void Assembler::divsd(XMMRegister dst, Address src) {
1839 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1840 InstructionMark im(this);
1841 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1842 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1843 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1844 emit_int8(0x5E);
1845 emit_operand(dst, src);
1846 }
1847
1848 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
1849 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5011 }
5012
5013 void Assembler::paddd(XMMRegister dst, Address src) {
5014 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5015 InstructionMark im(this);
5016 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5017 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5018 emit_int8((unsigned char)0xFE);
5019 emit_operand(dst, src);
5020 }
5021
5022 void Assembler::paddq(XMMRegister dst, XMMRegister src) {
5023 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5024 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5025 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5026 emit_int8((unsigned char)0xD4);
5027 emit_int8((unsigned char)(0xC0 | encode));
5028 }
5029
5030 void Assembler::phaddw(XMMRegister dst, XMMRegister src) {
5031 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
5032 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5033 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5034 emit_int8(0x01);
5035 emit_int8((unsigned char)(0xC0 | encode));
5036 }
5037
5038 void Assembler::phaddd(XMMRegister dst, XMMRegister src) {
5039 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
5040 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5041 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5042 emit_int8(0x02);
5043 emit_int8((unsigned char)(0xC0 | encode));
5044 }
5045
5046 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5047 assert(UseAVX > 0, "requires some form of AVX");
5048 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5049 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5050 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5051 emit_int8((unsigned char)0xFC);
5052 emit_int8((unsigned char)(0xC0 | encode));
5053 }
5054
5055 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5056 assert(UseAVX > 0, "requires some form of AVX");
5057 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5058 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5059 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
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1810 emit_operand(dst, src);
1811 }
1812
1813
1814 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
1815 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1816 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1817 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1818 emit_int8(0x2C);
1819 emit_int8((unsigned char)(0xC0 | encode));
1820 }
1821
1822 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
1823 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1824 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1825 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1826 emit_int8(0x2C);
1827 emit_int8((unsigned char)(0xC0 | encode));
1828 }
1829
1830 void Assembler::cvttpd2dq(XMMRegister dst, XMMRegister src) {
1831 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1832 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
1833 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
1834 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1835 emit_int8((unsigned char)0xE6);
1836 emit_int8((unsigned char)(0xC0 | encode));
1837 }
1838
1839 void Assembler::decl(Address dst) {
1840 // Don't use it directly. Use MacroAssembler::decrement() instead.
1841 InstructionMark im(this);
1842 prefix(dst);
1843 emit_int8((unsigned char)0xFF);
1844 emit_operand(rcx, dst);
1845 }
1846
1847 void Assembler::divsd(XMMRegister dst, Address src) {
1848 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1849 InstructionMark im(this);
1850 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1851 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1852 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1853 emit_int8(0x5E);
1854 emit_operand(dst, src);
1855 }
1856
1857 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
1858 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5020 }
5021
5022 void Assembler::paddd(XMMRegister dst, Address src) {
5023 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5024 InstructionMark im(this);
5025 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5026 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5027 emit_int8((unsigned char)0xFE);
5028 emit_operand(dst, src);
5029 }
5030
5031 void Assembler::paddq(XMMRegister dst, XMMRegister src) {
5032 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5033 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5034 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5035 emit_int8((unsigned char)0xD4);
5036 emit_int8((unsigned char)(0xC0 | encode));
5037 }
5038
5039 void Assembler::phaddw(XMMRegister dst, XMMRegister src) {
5040 assert(VM_Version::supports_sse3(), "");
5041 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5042 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5043 emit_int8(0x01);
5044 emit_int8((unsigned char)(0xC0 | encode));
5045 }
5046
5047 void Assembler::phaddd(XMMRegister dst, XMMRegister src) {
5048 assert(VM_Version::supports_sse3(), "");
5049 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5050 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5051 emit_int8(0x02);
5052 emit_int8((unsigned char)(0xC0 | encode));
5053 }
5054
5055 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5056 assert(UseAVX > 0, "requires some form of AVX");
5057 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5058 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5059 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5060 emit_int8((unsigned char)0xFC);
5061 emit_int8((unsigned char)(0xC0 | encode));
5062 }
5063
5064 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5065 assert(UseAVX > 0, "requires some form of AVX");
5066 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5067 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5068 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
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