1 /*
2 * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef CPU_X86_VM_ASSEMBLER_X86_HPP
26 #define CPU_X86_VM_ASSEMBLER_X86_HPP
27
28 #include "asm/register.hpp"
29 #include "vm_version_x86.hpp"
30
31 class BiasedLockingCounters;
32
33 // Contains all the definitions needed for x86 assembly code generation.
34
35 // Calling convention
36 class Argument VALUE_OBJ_CLASS_SPEC {
37 public:
38 enum {
39 #ifdef _LP64
40 #ifdef _WIN64
41 n_int_register_parameters_c = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...)
42 n_float_register_parameters_c = 4, // xmm0 - xmm3 (c_farg0, c_farg1, ... )
43 #else
44 n_int_register_parameters_c = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...)
45 n_float_register_parameters_c = 8, // xmm0 - xmm7 (c_farg0, c_farg1, ... )
46 #endif // _WIN64
47 n_int_register_parameters_j = 6, // j_rarg0, j_rarg1, ...
48 n_float_register_parameters_j = 8 // j_farg0, j_farg1, ...
49 #else
50 n_register_parameters = 0 // 0 registers used to pass arguments
51 #endif // _LP64
52 };
53 };
54
55
56 #ifdef _LP64
57 // Symbolically name the register arguments used by the c calling convention.
58 // Windows is different from linux/solaris. So much for standards...
59
60 #ifdef _WIN64
61
62 REGISTER_DECLARATION(Register, c_rarg0, rcx);
63 REGISTER_DECLARATION(Register, c_rarg1, rdx);
64 REGISTER_DECLARATION(Register, c_rarg2, r8);
65 REGISTER_DECLARATION(Register, c_rarg3, r9);
66
67 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
68 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
69 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
70 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
71
72 #else
73
74 REGISTER_DECLARATION(Register, c_rarg0, rdi);
75 REGISTER_DECLARATION(Register, c_rarg1, rsi);
76 REGISTER_DECLARATION(Register, c_rarg2, rdx);
77 REGISTER_DECLARATION(Register, c_rarg3, rcx);
78 REGISTER_DECLARATION(Register, c_rarg4, r8);
79 REGISTER_DECLARATION(Register, c_rarg5, r9);
80
81 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
82 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
83 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
84 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
85 REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4);
86 REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5);
87 REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6);
88 REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7);
89
90 #endif // _WIN64
91
92 // Symbolically name the register arguments used by the Java calling convention.
93 // We have control over the convention for java so we can do what we please.
94 // What pleases us is to offset the java calling convention so that when
95 // we call a suitable jni method the arguments are lined up and we don't
96 // have to do little shuffling. A suitable jni method is non-static and a
97 // small number of arguments (two fewer args on windows)
98 //
99 // |-------------------------------------------------------|
100 // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 |
101 // |-------------------------------------------------------|
102 // | rcx rdx r8 r9 rdi* rsi* | windows (* not a c_rarg)
103 // | rdi rsi rdx rcx r8 r9 | solaris/linux
104 // |-------------------------------------------------------|
105 // | j_rarg5 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 |
106 // |-------------------------------------------------------|
107
108 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);
109 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);
110 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);
111 // Windows runs out of register args here
112 #ifdef _WIN64
113 REGISTER_DECLARATION(Register, j_rarg3, rdi);
114 REGISTER_DECLARATION(Register, j_rarg4, rsi);
115 #else
116 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);
117 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);
118 #endif /* _WIN64 */
119 REGISTER_DECLARATION(Register, j_rarg5, c_rarg0);
120
121 REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0);
122 REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1);
123 REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2);
124 REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3);
125 REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4);
126 REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5);
127 REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6);
128 REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7);
129
130 REGISTER_DECLARATION(Register, rscratch1, r10); // volatile
131 REGISTER_DECLARATION(Register, rscratch2, r11); // volatile
132
133 REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved
134 REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved
135
136 #else
137 // rscratch1 will apear in 32bit code that is dead but of course must compile
138 // Using noreg ensures if the dead code is incorrectly live and executed it
139 // will cause an assertion failure
140 #define rscratch1 noreg
141 #define rscratch2 noreg
142
143 #endif // _LP64
144
145 // JSR 292
146 // On x86, the SP does not have to be saved when invoking method handle intrinsics
147 // or compiled lambda forms. We indicate that by setting rbp_mh_SP_save to noreg.
148 REGISTER_DECLARATION(Register, rbp_mh_SP_save, noreg);
149
150 // Address is an abstraction used to represent a memory location
151 // using any of the amd64 addressing modes with one object.
152 //
153 // Note: A register location is represented via a Register, not
154 // via an address for efficiency & simplicity reasons.
155
156 class ArrayAddress;
157
158 class Address VALUE_OBJ_CLASS_SPEC {
159 public:
160 enum ScaleFactor {
161 no_scale = -1,
162 times_1 = 0,
163 times_2 = 1,
164 times_4 = 2,
165 times_8 = 3,
166 times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4)
167 };
168 static ScaleFactor times(int size) {
169 assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size");
170 if (size == 8) return times_8;
171 if (size == 4) return times_4;
172 if (size == 2) return times_2;
173 return times_1;
174 }
175 static int scale_size(ScaleFactor scale) {
176 assert(scale != no_scale, "");
177 assert(((1 << (int)times_1) == 1 &&
178 (1 << (int)times_2) == 2 &&
179 (1 << (int)times_4) == 4 &&
180 (1 << (int)times_8) == 8), "");
181 return (1 << (int)scale);
182 }
183
184 private:
185 Register _base;
186 Register _index;
187 ScaleFactor _scale;
188 int _disp;
189 RelocationHolder _rspec;
190
191 // Easily misused constructors make them private
192 // %%% can we make these go away?
193 NOT_LP64(Address(address loc, RelocationHolder spec);)
194 Address(int disp, address loc, relocInfo::relocType rtype);
195 Address(int disp, address loc, RelocationHolder spec);
196
197 public:
198
199 int disp() { return _disp; }
200 // creation
201 Address()
202 : _base(noreg),
203 _index(noreg),
204 _scale(no_scale),
205 _disp(0) {
206 }
207
208 // No default displacement otherwise Register can be implicitly
209 // converted to 0(Register) which is quite a different animal.
210
211 Address(Register base, int disp)
212 : _base(base),
213 _index(noreg),
214 _scale(no_scale),
215 _disp(disp) {
216 }
217
218 Address(Register base, Register index, ScaleFactor scale, int disp = 0)
219 : _base (base),
220 _index(index),
221 _scale(scale),
222 _disp (disp) {
223 assert(!index->is_valid() == (scale == Address::no_scale),
224 "inconsistent address");
225 }
226
227 Address(Register base, RegisterOrConstant index, ScaleFactor scale = times_1, int disp = 0)
228 : _base (base),
229 _index(index.register_or_noreg()),
230 _scale(scale),
231 _disp (disp + (index.constant_or_zero() * scale_size(scale))) {
232 if (!index.is_register()) scale = Address::no_scale;
233 assert(!_index->is_valid() == (scale == Address::no_scale),
234 "inconsistent address");
235 }
236
237 Address plus_disp(int disp) const {
238 Address a = (*this);
239 a._disp += disp;
240 return a;
241 }
242 Address plus_disp(RegisterOrConstant disp, ScaleFactor scale = times_1) const {
243 Address a = (*this);
244 a._disp += disp.constant_or_zero() * scale_size(scale);
245 if (disp.is_register()) {
246 assert(!a.index()->is_valid(), "competing indexes");
247 a._index = disp.as_register();
248 a._scale = scale;
249 }
250 return a;
251 }
252 bool is_same_address(Address a) const {
253 // disregard _rspec
254 return _base == a._base && _disp == a._disp && _index == a._index && _scale == a._scale;
255 }
256
257 // The following two overloads are used in connection with the
258 // ByteSize type (see sizes.hpp). They simplify the use of
259 // ByteSize'd arguments in assembly code. Note that their equivalent
260 // for the optimized build are the member functions with int disp
261 // argument since ByteSize is mapped to an int type in that case.
262 //
263 // Note: DO NOT introduce similar overloaded functions for WordSize
264 // arguments as in the optimized mode, both ByteSize and WordSize
265 // are mapped to the same type and thus the compiler cannot make a
266 // distinction anymore (=> compiler errors).
267
268 #ifdef ASSERT
269 Address(Register base, ByteSize disp)
270 : _base(base),
271 _index(noreg),
272 _scale(no_scale),
273 _disp(in_bytes(disp)) {
274 }
275
276 Address(Register base, Register index, ScaleFactor scale, ByteSize disp)
277 : _base(base),
278 _index(index),
279 _scale(scale),
280 _disp(in_bytes(disp)) {
281 assert(!index->is_valid() == (scale == Address::no_scale),
282 "inconsistent address");
283 }
284
285 Address(Register base, RegisterOrConstant index, ScaleFactor scale, ByteSize disp)
286 : _base (base),
287 _index(index.register_or_noreg()),
288 _scale(scale),
289 _disp (in_bytes(disp) + (index.constant_or_zero() * scale_size(scale))) {
290 if (!index.is_register()) scale = Address::no_scale;
291 assert(!_index->is_valid() == (scale == Address::no_scale),
292 "inconsistent address");
293 }
294
295 #endif // ASSERT
296
297 // accessors
298 bool uses(Register reg) const { return _base == reg || _index == reg; }
299 Register base() const { return _base; }
300 Register index() const { return _index; }
301 ScaleFactor scale() const { return _scale; }
302 int disp() const { return _disp; }
303
304 // Convert the raw encoding form into the form expected by the constructor for
305 // Address. An index of 4 (rsp) corresponds to having no index, so convert
306 // that to noreg for the Address constructor.
307 static Address make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc);
308
309 static Address make_array(ArrayAddress);
310
311 private:
312 bool base_needs_rex() const {
313 return _base != noreg && _base->encoding() >= 8;
314 }
315
316 bool index_needs_rex() const {
317 return _index != noreg &&_index->encoding() >= 8;
318 }
319
320 relocInfo::relocType reloc() const { return _rspec.type(); }
321
322 friend class Assembler;
323 friend class MacroAssembler;
324 friend class LIR_Assembler; // base/index/scale/disp
325 };
326
327 //
328 // AddressLiteral has been split out from Address because operands of this type
329 // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out
330 // the few instructions that need to deal with address literals are unique and the
331 // MacroAssembler does not have to implement every instruction in the Assembler
332 // in order to search for address literals that may need special handling depending
333 // on the instruction and the platform. As small step on the way to merging i486/amd64
334 // directories.
335 //
336 class AddressLiteral VALUE_OBJ_CLASS_SPEC {
337 friend class ArrayAddress;
338 RelocationHolder _rspec;
339 // Typically we use AddressLiterals we want to use their rval
340 // However in some situations we want the lval (effect address) of the item.
341 // We provide a special factory for making those lvals.
342 bool _is_lval;
343
344 // If the target is far we'll need to load the ea of this to
345 // a register to reach it. Otherwise if near we can do rip
346 // relative addressing.
347
348 address _target;
349
350 protected:
351 // creation
352 AddressLiteral()
353 : _is_lval(false),
354 _target(NULL)
355 {}
356
357 public:
358
359
360 AddressLiteral(address target, relocInfo::relocType rtype);
361
362 AddressLiteral(address target, RelocationHolder const& rspec)
363 : _rspec(rspec),
364 _is_lval(false),
365 _target(target)
366 {}
367
368 AddressLiteral addr() {
369 AddressLiteral ret = *this;
370 ret._is_lval = true;
371 return ret;
372 }
373
374
375 private:
376
377 address target() { return _target; }
378 bool is_lval() { return _is_lval; }
379
380 relocInfo::relocType reloc() const { return _rspec.type(); }
381 const RelocationHolder& rspec() const { return _rspec; }
382
383 friend class Assembler;
384 friend class MacroAssembler;
385 friend class Address;
386 friend class LIR_Assembler;
387 };
388
389 // Convience classes
390 class RuntimeAddress: public AddressLiteral {
391
392 public:
393
394 RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {}
395
396 };
397
398 class ExternalAddress: public AddressLiteral {
399 private:
400 static relocInfo::relocType reloc_for_target(address target) {
401 // Sometimes ExternalAddress is used for values which aren't
402 // exactly addresses, like the card table base.
403 // external_word_type can't be used for values in the first page
404 // so just skip the reloc in that case.
405 return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;
406 }
407
408 public:
409
410 ExternalAddress(address target) : AddressLiteral(target, reloc_for_target(target)) {}
411
412 };
413
414 class InternalAddress: public AddressLiteral {
415
416 public:
417
418 InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {}
419
420 };
421
422 // x86 can do array addressing as a single operation since disp can be an absolute
423 // address amd64 can't. We create a class that expresses the concept but does extra
424 // magic on amd64 to get the final result
425
426 class ArrayAddress VALUE_OBJ_CLASS_SPEC {
427 private:
428
429 AddressLiteral _base;
430 Address _index;
431
432 public:
433
434 ArrayAddress() {};
435 ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {};
436 AddressLiteral base() { return _base; }
437 Address index() { return _index; }
438
439 };
440
441 class InstructionAttr;
442
443 // 64-bit refect the fxsave size which is 512 bytes and the new xsave area on EVEX which is another 2176 bytes
444 // See fxsave and xsave(EVEX enabled) documentation for layout
445 const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY(2688 / wordSize);
446
447 // The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction
448 // level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write
449 // is what you get. The Assembler is generating code into a CodeBuffer.
450
451 class Assembler : public AbstractAssembler {
452 friend class AbstractAssembler; // for the non-virtual hack
453 friend class LIR_Assembler; // as_Address()
454 friend class StubGenerator;
455
456 public:
457 enum Condition { // The x86 condition codes used for conditional jumps/moves.
458 zero = 0x4,
459 notZero = 0x5,
460 equal = 0x4,
461 notEqual = 0x5,
462 less = 0xc,
463 lessEqual = 0xe,
464 greater = 0xf,
465 greaterEqual = 0xd,
466 below = 0x2,
467 belowEqual = 0x6,
468 above = 0x7,
469 aboveEqual = 0x3,
470 overflow = 0x0,
471 noOverflow = 0x1,
472 carrySet = 0x2,
473 carryClear = 0x3,
474 negative = 0x8,
475 positive = 0x9,
476 parity = 0xa,
477 noParity = 0xb
478 };
479
480 enum Prefix {
481 // segment overrides
482 CS_segment = 0x2e,
483 SS_segment = 0x36,
484 DS_segment = 0x3e,
485 ES_segment = 0x26,
486 FS_segment = 0x64,
487 GS_segment = 0x65,
488
489 REX = 0x40,
490
491 REX_B = 0x41,
492 REX_X = 0x42,
493 REX_XB = 0x43,
494 REX_R = 0x44,
495 REX_RB = 0x45,
496 REX_RX = 0x46,
497 REX_RXB = 0x47,
498
499 REX_W = 0x48,
500
501 REX_WB = 0x49,
502 REX_WX = 0x4A,
503 REX_WXB = 0x4B,
504 REX_WR = 0x4C,
505 REX_WRB = 0x4D,
506 REX_WRX = 0x4E,
507 REX_WRXB = 0x4F,
508
509 VEX_3bytes = 0xC4,
510 VEX_2bytes = 0xC5,
511 EVEX_4bytes = 0x62,
512 Prefix_EMPTY = 0x0
513 };
514
515 enum VexPrefix {
516 VEX_B = 0x20,
517 VEX_X = 0x40,
518 VEX_R = 0x80,
519 VEX_W = 0x80
520 };
521
522 enum ExexPrefix {
523 EVEX_F = 0x04,
524 EVEX_V = 0x08,
525 EVEX_Rb = 0x10,
526 EVEX_X = 0x40,
527 EVEX_Z = 0x80
528 };
529
530 enum VexSimdPrefix {
531 VEX_SIMD_NONE = 0x0,
532 VEX_SIMD_66 = 0x1,
533 VEX_SIMD_F3 = 0x2,
534 VEX_SIMD_F2 = 0x3
535 };
536
537 enum VexOpcode {
538 VEX_OPCODE_NONE = 0x0,
539 VEX_OPCODE_0F = 0x1,
540 VEX_OPCODE_0F_38 = 0x2,
541 VEX_OPCODE_0F_3A = 0x3,
542 VEX_OPCODE_MASK = 0x1F
543 };
544
545 enum AvxVectorLen {
546 AVX_128bit = 0x0,
547 AVX_256bit = 0x1,
548 AVX_512bit = 0x2,
549 AVX_NoVec = 0x4
550 };
551
552 enum EvexTupleType {
553 EVEX_FV = 0,
554 EVEX_HV = 4,
555 EVEX_FVM = 6,
556 EVEX_T1S = 7,
557 EVEX_T1F = 11,
558 EVEX_T2 = 13,
559 EVEX_T4 = 15,
560 EVEX_T8 = 17,
561 EVEX_HVM = 18,
562 EVEX_QVM = 19,
563 EVEX_OVM = 20,
564 EVEX_M128 = 21,
565 EVEX_DUP = 22,
566 EVEX_ETUP = 23
567 };
568
569 enum EvexInputSizeInBits {
570 EVEX_8bit = 0,
571 EVEX_16bit = 1,
572 EVEX_32bit = 2,
573 EVEX_64bit = 3,
574 EVEX_NObit = 4
575 };
576
577 enum WhichOperand {
578 // input to locate_operand, and format code for relocations
579 imm_operand = 0, // embedded 32-bit|64-bit immediate operand
580 disp32_operand = 1, // embedded 32-bit displacement or address
581 call32_operand = 2, // embedded 32-bit self-relative displacement
582 #ifndef _LP64
583 _WhichOperand_limit = 3
584 #else
585 narrow_oop_operand = 3, // embedded 32-bit immediate narrow oop
586 _WhichOperand_limit = 4
587 #endif
588 };
589
590
591
592 // NOTE: The general philopsophy of the declarations here is that 64bit versions
593 // of instructions are freely declared without the need for wrapping them an ifdef.
594 // (Some dangerous instructions are ifdef's out of inappropriate jvm's.)
595 // In the .cpp file the implementations are wrapped so that they are dropped out
596 // of the resulting jvm. This is done mostly to keep the footprint of MINIMAL
597 // to the size it was prior to merging up the 32bit and 64bit assemblers.
598 //
599 // This does mean you'll get a linker/runtime error if you use a 64bit only instruction
600 // in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down.
601
602 private:
603
604 bool _legacy_mode_bw;
605 bool _legacy_mode_dq;
606 bool _legacy_mode_vl;
607 bool _legacy_mode_vlbw;
608
609 class InstructionAttr *_attributes;
610
611 // 64bit prefixes
612 int prefix_and_encode(int reg_enc, bool byteinst = false);
613 int prefixq_and_encode(int reg_enc);
614
615 int prefix_and_encode(int dst_enc, int src_enc) {
616 return prefix_and_encode(dst_enc, false, src_enc, false);
617 }
618 int prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte);
619 int prefixq_and_encode(int dst_enc, int src_enc);
620
621 void prefix(Register reg);
622 void prefix(Register dst, Register src, Prefix p);
623 void prefix(Register dst, Address adr, Prefix p);
624 void prefix(Address adr);
625 void prefixq(Address adr);
626
627 void prefix(Address adr, Register reg, bool byteinst = false);
628 void prefix(Address adr, XMMRegister reg);
629 void prefixq(Address adr, Register reg);
630 void prefixq(Address adr, XMMRegister reg);
631
632 void prefetch_prefix(Address src);
633
634 void rex_prefix(Address adr, XMMRegister xreg,
635 VexSimdPrefix pre, VexOpcode opc, bool rex_w);
636 int rex_prefix_and_encode(int dst_enc, int src_enc,
637 VexSimdPrefix pre, VexOpcode opc, bool rex_w);
638
639 void vex_prefix(bool vex_r, bool vex_b, bool vex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc);
640
641 void evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_r, bool evex_v,
642 int nds_enc, VexSimdPrefix pre, VexOpcode opc);
643
644 void vex_prefix(Address adr, int nds_enc, int xreg_enc,
645 VexSimdPrefix pre, VexOpcode opc,
646 InstructionAttr *attributes);
647
648 int vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc,
649 VexSimdPrefix pre, VexOpcode opc,
650 InstructionAttr *attributes);
651
652 void simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre,
653 VexOpcode opc, InstructionAttr *attributes);
654
655 int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre,
656 VexOpcode opc, InstructionAttr *attributes);
657
658 // Helper functions for groups of instructions
659 void emit_arith_b(int op1, int op2, Register dst, int imm8);
660
661 void emit_arith(int op1, int op2, Register dst, int32_t imm32);
662 // Force generation of a 4 byte immediate value even if it fits into 8bit
663 void emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32);
664 void emit_arith(int op1, int op2, Register dst, Register src);
665
666 bool emit_compressed_disp_byte(int &disp);
667
668 void emit_operand(Register reg,
669 Register base, Register index, Address::ScaleFactor scale,
670 int disp,
671 RelocationHolder const& rspec,
672 int rip_relative_correction = 0);
673
674 void emit_operand(Register reg, Address adr, int rip_relative_correction = 0);
675
676 // operands that only take the original 32bit registers
677 void emit_operand32(Register reg, Address adr);
678
679 void emit_operand(XMMRegister reg,
680 Register base, Register index, Address::ScaleFactor scale,
681 int disp,
682 RelocationHolder const& rspec);
683
684 void emit_operand(XMMRegister reg, Address adr);
685
686 void emit_operand(MMXRegister reg, Address adr);
687
688 // workaround gcc (3.2.1-7) bug
689 void emit_operand(Address adr, MMXRegister reg);
690
691
692 // Immediate-to-memory forms
693 void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32);
694
695 void emit_farith(int b1, int b2, int i);
696
697
698 protected:
699 #ifdef ASSERT
700 void check_relocation(RelocationHolder const& rspec, int format);
701 #endif
702
703 void emit_data(jint data, relocInfo::relocType rtype, int format);
704 void emit_data(jint data, RelocationHolder const& rspec, int format);
705 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
706 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
707
708 bool reachable(AddressLiteral adr) NOT_LP64({ return true;});
709
710 // These are all easily abused and hence protected
711
712 // 32BIT ONLY SECTION
713 #ifndef _LP64
714 // Make these disappear in 64bit mode since they would never be correct
715 void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
716 void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
717
718 void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
719 void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
720
721 void push_literal32(int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
722 #else
723 // 64BIT ONLY SECTION
724 void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec); // 64BIT ONLY
725
726 void cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec);
727 void cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec);
728
729 void mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec);
730 void mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec);
731 #endif // _LP64
732
733 // These are unique in that we are ensured by the caller that the 32bit
734 // relative in these instructions will always be able to reach the potentially
735 // 64bit address described by entry. Since they can take a 64bit address they
736 // don't have the 32 suffix like the other instructions in this class.
737
738 void call_literal(address entry, RelocationHolder const& rspec);
739 void jmp_literal(address entry, RelocationHolder const& rspec);
740
741 // Avoid using directly section
742 // Instructions in this section are actually usable by anyone without danger
743 // of failure but have performance issues that are addressed my enhanced
744 // instructions which will do the proper thing base on the particular cpu.
745 // We protect them because we don't trust you...
746
747 // Don't use next inc() and dec() methods directly. INC & DEC instructions
748 // could cause a partial flag stall since they don't set CF flag.
749 // Use MacroAssembler::decrement() & MacroAssembler::increment() methods
750 // which call inc() & dec() or add() & sub() in accordance with
751 // the product flag UseIncDec value.
752
753 void decl(Register dst);
754 void decl(Address dst);
755 void decq(Register dst);
756 void decq(Address dst);
757
758 void incl(Register dst);
759 void incl(Address dst);
760 void incq(Register dst);
761 void incq(Address dst);
762
763 // New cpus require use of movsd and movss to avoid partial register stall
764 // when loading from memory. But for old Opteron use movlpd instead of movsd.
765 // The selection is done in MacroAssembler::movdbl() and movflt().
766
767 // Move Scalar Single-Precision Floating-Point Values
768 void movss(XMMRegister dst, Address src);
769 void movss(XMMRegister dst, XMMRegister src);
770 void movss(Address dst, XMMRegister src);
771
772 // Move Scalar Double-Precision Floating-Point Values
773 void movsd(XMMRegister dst, Address src);
774 void movsd(XMMRegister dst, XMMRegister src);
775 void movsd(Address dst, XMMRegister src);
776 void movlpd(XMMRegister dst, Address src);
777
778 // New cpus require use of movaps and movapd to avoid partial register stall
779 // when moving between registers.
780 void movaps(XMMRegister dst, XMMRegister src);
781 void movapd(XMMRegister dst, XMMRegister src);
782
783 // End avoid using directly
784
785
786 // Instruction prefixes
787 void prefix(Prefix p);
788
789 public:
790
791 // Creation
792 Assembler(CodeBuffer* code) : AbstractAssembler(code) {
793 init_attributes();
794 }
795
796 // Decoding
797 static address locate_operand(address inst, WhichOperand which);
798 static address locate_next_instruction(address inst);
799
800 // Utilities
801 static bool is_polling_page_far() NOT_LP64({ return false;});
802 static bool query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len,
803 int cur_tuple_type, int in_size_in_bits, int cur_encoding);
804
805 // Generic instructions
806 // Does 32bit or 64bit as needed for the platform. In some sense these
807 // belong in macro assembler but there is no need for both varieties to exist
808
809 void init_attributes(void) {
810 _legacy_mode_bw = (VM_Version::supports_avx512bw() == false);
811 _legacy_mode_dq = (VM_Version::supports_avx512dq() == false);
812 _legacy_mode_vl = (VM_Version::supports_avx512vl() == false);
813 _legacy_mode_vlbw = (VM_Version::supports_avx512vlbw() == false);
814 _attributes = NULL;
815 }
816
817 void set_attributes(InstructionAttr *attributes) { _attributes = attributes; }
818 void clear_attributes(void) { _attributes = NULL; }
819
820 void lea(Register dst, Address src);
821
822 void mov(Register dst, Register src);
823
824 void pusha();
825 void popa();
826
827 void pushf();
828 void popf();
829
830 void push(int32_t imm32);
831
832 void push(Register src);
833
834 void pop(Register dst);
835
836 // These are dummies to prevent surprise implicit conversions to Register
837 void push(void* v);
838 void pop(void* v);
839
840 // These do register sized moves/scans
841 void rep_mov();
842 void rep_stos();
843 void rep_stosb();
844 void repne_scan();
845 #ifdef _LP64
846 void repne_scanl();
847 #endif
848
849 // Vanilla instructions in lexical order
850
851 void adcl(Address dst, int32_t imm32);
852 void adcl(Address dst, Register src);
853 void adcl(Register dst, int32_t imm32);
854 void adcl(Register dst, Address src);
855 void adcl(Register dst, Register src);
856
857 void adcq(Register dst, int32_t imm32);
858 void adcq(Register dst, Address src);
859 void adcq(Register dst, Register src);
860
861 void addl(Address dst, int32_t imm32);
862 void addl(Address dst, Register src);
863 void addl(Register dst, int32_t imm32);
864 void addl(Register dst, Address src);
865 void addl(Register dst, Register src);
866
867 void addq(Address dst, int32_t imm32);
868 void addq(Address dst, Register src);
869 void addq(Register dst, int32_t imm32);
870 void addq(Register dst, Address src);
871 void addq(Register dst, Register src);
872
873 #ifdef _LP64
874 //Add Unsigned Integers with Carry Flag
875 void adcxq(Register dst, Register src);
876
877 //Add Unsigned Integers with Overflow Flag
878 void adoxq(Register dst, Register src);
879 #endif
880
881 void addr_nop_4();
882 void addr_nop_5();
883 void addr_nop_7();
884 void addr_nop_8();
885
886 // Add Scalar Double-Precision Floating-Point Values
887 void addsd(XMMRegister dst, Address src);
888 void addsd(XMMRegister dst, XMMRegister src);
889
890 // Add Scalar Single-Precision Floating-Point Values
891 void addss(XMMRegister dst, Address src);
892 void addss(XMMRegister dst, XMMRegister src);
893
894 // AES instructions
895 void aesdec(XMMRegister dst, Address src);
896 void aesdec(XMMRegister dst, XMMRegister src);
897 void aesdeclast(XMMRegister dst, Address src);
898 void aesdeclast(XMMRegister dst, XMMRegister src);
899 void aesenc(XMMRegister dst, Address src);
900 void aesenc(XMMRegister dst, XMMRegister src);
901 void aesenclast(XMMRegister dst, Address src);
902 void aesenclast(XMMRegister dst, XMMRegister src);
903
904
905 void andl(Address dst, int32_t imm32);
906 void andl(Register dst, int32_t imm32);
907 void andl(Register dst, Address src);
908 void andl(Register dst, Register src);
909
910 void andq(Address dst, int32_t imm32);
911 void andq(Register dst, int32_t imm32);
912 void andq(Register dst, Address src);
913 void andq(Register dst, Register src);
914
915 // BMI instructions
916 void andnl(Register dst, Register src1, Register src2);
917 void andnl(Register dst, Register src1, Address src2);
918 void andnq(Register dst, Register src1, Register src2);
919 void andnq(Register dst, Register src1, Address src2);
920
921 void blsil(Register dst, Register src);
922 void blsil(Register dst, Address src);
923 void blsiq(Register dst, Register src);
924 void blsiq(Register dst, Address src);
925
926 void blsmskl(Register dst, Register src);
927 void blsmskl(Register dst, Address src);
928 void blsmskq(Register dst, Register src);
929 void blsmskq(Register dst, Address src);
930
931 void blsrl(Register dst, Register src);
932 void blsrl(Register dst, Address src);
933 void blsrq(Register dst, Register src);
934 void blsrq(Register dst, Address src);
935
936 void bsfl(Register dst, Register src);
937 void bsrl(Register dst, Register src);
938
939 #ifdef _LP64
940 void bsfq(Register dst, Register src);
941 void bsrq(Register dst, Register src);
942 #endif
943
944 void bswapl(Register reg);
945
946 void bswapq(Register reg);
947
948 void call(Label& L, relocInfo::relocType rtype);
949 void call(Register reg); // push pc; pc <- reg
950 void call(Address adr); // push pc; pc <- adr
951
952 void cdql();
953
954 void cdqq();
955
956 void cld();
957
958 void clflush(Address adr);
959
960 void cmovl(Condition cc, Register dst, Register src);
961 void cmovl(Condition cc, Register dst, Address src);
962
963 void cmovq(Condition cc, Register dst, Register src);
964 void cmovq(Condition cc, Register dst, Address src);
965
966
967 void cmpb(Address dst, int imm8);
968
969 void cmpl(Address dst, int32_t imm32);
970
971 void cmpl(Register dst, int32_t imm32);
972 void cmpl(Register dst, Register src);
973 void cmpl(Register dst, Address src);
974
975 void cmpq(Address dst, int32_t imm32);
976 void cmpq(Address dst, Register src);
977
978 void cmpq(Register dst, int32_t imm32);
979 void cmpq(Register dst, Register src);
980 void cmpq(Register dst, Address src);
981
982 // these are dummies used to catch attempting to convert NULL to Register
983 void cmpl(Register dst, void* junk); // dummy
984 void cmpq(Register dst, void* junk); // dummy
985
986 void cmpw(Address dst, int imm16);
987
988 void cmpxchg8 (Address adr);
989
990 void cmpxchgb(Register reg, Address adr);
991 void cmpxchgl(Register reg, Address adr);
992
993 void cmpxchgq(Register reg, Address adr);
994
995 // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
996 void comisd(XMMRegister dst, Address src);
997 void comisd(XMMRegister dst, XMMRegister src);
998
999 // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
1000 void comiss(XMMRegister dst, Address src);
1001 void comiss(XMMRegister dst, XMMRegister src);
1002
1003 // Identify processor type and features
1004 void cpuid();
1005
1006 // CRC32C
1007 void crc32(Register crc, Register v, int8_t sizeInBytes);
1008 void crc32(Register crc, Address adr, int8_t sizeInBytes);
1009
1010 // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
1011 void cvtsd2ss(XMMRegister dst, XMMRegister src);
1012 void cvtsd2ss(XMMRegister dst, Address src);
1013
1014 // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
1015 void cvtsi2sdl(XMMRegister dst, Register src);
1016 void cvtsi2sdl(XMMRegister dst, Address src);
1017 void cvtsi2sdq(XMMRegister dst, Register src);
1018 void cvtsi2sdq(XMMRegister dst, Address src);
1019
1020 // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value
1021 void cvtsi2ssl(XMMRegister dst, Register src);
1022 void cvtsi2ssl(XMMRegister dst, Address src);
1023 void cvtsi2ssq(XMMRegister dst, Register src);
1024 void cvtsi2ssq(XMMRegister dst, Address src);
1025
1026 // Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value
1027 void cvtdq2pd(XMMRegister dst, XMMRegister src);
1028
1029 // Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value
1030 void cvtdq2ps(XMMRegister dst, XMMRegister src);
1031
1032 // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
1033 void cvtss2sd(XMMRegister dst, XMMRegister src);
1034 void cvtss2sd(XMMRegister dst, Address src);
1035
1036 // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
1037 void cvttsd2sil(Register dst, Address src);
1038 void cvttsd2sil(Register dst, XMMRegister src);
1039 void cvttsd2siq(Register dst, XMMRegister src);
1040
1041 // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer
1042 void cvttss2sil(Register dst, XMMRegister src);
1043 void cvttss2siq(Register dst, XMMRegister src);
1044
1045 void cvttpd2dq(XMMRegister dst, XMMRegister src);
1046
1047 // Divide Scalar Double-Precision Floating-Point Values
1048 void divsd(XMMRegister dst, Address src);
1049 void divsd(XMMRegister dst, XMMRegister src);
1050
1051 // Divide Scalar Single-Precision Floating-Point Values
1052 void divss(XMMRegister dst, Address src);
1053 void divss(XMMRegister dst, XMMRegister src);
1054
1055 void emms();
1056
1057 void fabs();
1058
1059 void fadd(int i);
1060
1061 void fadd_d(Address src);
1062 void fadd_s(Address src);
1063
1064 // "Alternate" versions of x87 instructions place result down in FPU
1065 // stack instead of on TOS
1066
1067 void fadda(int i); // "alternate" fadd
1068 void faddp(int i = 1);
1069
1070 void fchs();
1071
1072 void fcom(int i);
1073
1074 void fcomp(int i = 1);
1075 void fcomp_d(Address src);
1076 void fcomp_s(Address src);
1077
1078 void fcompp();
1079
1080 void fcos();
1081
1082 void fdecstp();
1083
1084 void fdiv(int i);
1085 void fdiv_d(Address src);
1086 void fdivr_s(Address src);
1087 void fdiva(int i); // "alternate" fdiv
1088 void fdivp(int i = 1);
1089
1090 void fdivr(int i);
1091 void fdivr_d(Address src);
1092 void fdiv_s(Address src);
1093
1094 void fdivra(int i); // "alternate" reversed fdiv
1095
1096 void fdivrp(int i = 1);
1097
1098 void ffree(int i = 0);
1099
1100 void fild_d(Address adr);
1101 void fild_s(Address adr);
1102
1103 void fincstp();
1104
1105 void finit();
1106
1107 void fist_s (Address adr);
1108 void fistp_d(Address adr);
1109 void fistp_s(Address adr);
1110
1111 void fld1();
1112
1113 void fld_d(Address adr);
1114 void fld_s(Address adr);
1115 void fld_s(int index);
1116 void fld_x(Address adr); // extended-precision (80-bit) format
1117
1118 void fldcw(Address src);
1119
1120 void fldenv(Address src);
1121
1122 void fldlg2();
1123
1124 void fldln2();
1125
1126 void fldz();
1127
1128 void flog();
1129 void flog10();
1130
1131 void fmul(int i);
1132
1133 void fmul_d(Address src);
1134 void fmul_s(Address src);
1135
1136 void fmula(int i); // "alternate" fmul
1137
1138 void fmulp(int i = 1);
1139
1140 void fnsave(Address dst);
1141
1142 void fnstcw(Address src);
1143
1144 void fnstsw_ax();
1145
1146 void fprem();
1147 void fprem1();
1148
1149 void frstor(Address src);
1150
1151 void fsin();
1152
1153 void fsqrt();
1154
1155 void fst_d(Address adr);
1156 void fst_s(Address adr);
1157
1158 void fstp_d(Address adr);
1159 void fstp_d(int index);
1160 void fstp_s(Address adr);
1161 void fstp_x(Address adr); // extended-precision (80-bit) format
1162
1163 void fsub(int i);
1164 void fsub_d(Address src);
1165 void fsub_s(Address src);
1166
1167 void fsuba(int i); // "alternate" fsub
1168
1169 void fsubp(int i = 1);
1170
1171 void fsubr(int i);
1172 void fsubr_d(Address src);
1173 void fsubr_s(Address src);
1174
1175 void fsubra(int i); // "alternate" reversed fsub
1176
1177 void fsubrp(int i = 1);
1178
1179 void ftan();
1180
1181 void ftst();
1182
1183 void fucomi(int i = 1);
1184 void fucomip(int i = 1);
1185
1186 void fwait();
1187
1188 void fxch(int i = 1);
1189
1190 void fxrstor(Address src);
1191 void xrstor(Address src);
1192
1193 void fxsave(Address dst);
1194 void xsave(Address dst);
1195
1196 void fyl2x();
1197 void frndint();
1198 void f2xm1();
1199 void fldl2e();
1200
1201 void hlt();
1202
1203 void idivl(Register src);
1204 void divl(Register src); // Unsigned division
1205
1206 #ifdef _LP64
1207 void idivq(Register src);
1208 #endif
1209
1210 void imull(Register src);
1211 void imull(Register dst, Register src);
1212 void imull(Register dst, Register src, int value);
1213 void imull(Register dst, Address src);
1214
1215 #ifdef _LP64
1216 void imulq(Register dst, Register src);
1217 void imulq(Register dst, Register src, int value);
1218 void imulq(Register dst, Address src);
1219 #endif
1220
1221 // jcc is the generic conditional branch generator to run-
1222 // time routines, jcc is used for branches to labels. jcc
1223 // takes a branch opcode (cc) and a label (L) and generates
1224 // either a backward branch or a forward branch and links it
1225 // to the label fixup chain. Usage:
1226 //
1227 // Label L; // unbound label
1228 // jcc(cc, L); // forward branch to unbound label
1229 // bind(L); // bind label to the current pc
1230 // jcc(cc, L); // backward branch to bound label
1231 // bind(L); // illegal: a label may be bound only once
1232 //
1233 // Note: The same Label can be used for forward and backward branches
1234 // but it may be bound only once.
1235
1236 void jcc(Condition cc, Label& L, bool maybe_short = true);
1237
1238 // Conditional jump to a 8-bit offset to L.
1239 // WARNING: be very careful using this for forward jumps. If the label is
1240 // not bound within an 8-bit offset of this instruction, a run-time error
1241 // will occur.
1242 void jccb(Condition cc, Label& L);
1243
1244 void jmp(Address entry); // pc <- entry
1245
1246 // Label operations & relative jumps (PPUM Appendix D)
1247 void jmp(Label& L, bool maybe_short = true); // unconditional jump to L
1248
1249 void jmp(Register entry); // pc <- entry
1250
1251 // Unconditional 8-bit offset jump to L.
1252 // WARNING: be very careful using this for forward jumps. If the label is
1253 // not bound within an 8-bit offset of this instruction, a run-time error
1254 // will occur.
1255 void jmpb(Label& L);
1256
1257 void ldmxcsr( Address src );
1258
1259 void leal(Register dst, Address src);
1260
1261 void leaq(Register dst, Address src);
1262
1263 void lfence();
1264
1265 void lock();
1266
1267 void lzcntl(Register dst, Register src);
1268
1269 #ifdef _LP64
1270 void lzcntq(Register dst, Register src);
1271 #endif
1272
1273 enum Membar_mask_bits {
1274 StoreStore = 1 << 3,
1275 LoadStore = 1 << 2,
1276 StoreLoad = 1 << 1,
1277 LoadLoad = 1 << 0
1278 };
1279
1280 // Serializes memory and blows flags
1281 void membar(Membar_mask_bits order_constraint) {
1282 if (os::is_MP()) {
1283 // We only have to handle StoreLoad
1284 if (order_constraint & StoreLoad) {
1285 // All usable chips support "locked" instructions which suffice
1286 // as barriers, and are much faster than the alternative of
1287 // using cpuid instruction. We use here a locked add [esp-C],0.
1288 // This is conveniently otherwise a no-op except for blowing
1289 // flags, and introducing a false dependency on target memory
1290 // location. We can't do anything with flags, but we can avoid
1291 // memory dependencies in the current method by locked-adding
1292 // somewhere else on the stack. Doing [esp+C] will collide with
1293 // something on stack in current method, hence we go for [esp-C].
1294 // It is convenient since it is almost always in data cache, for
1295 // any small C. We need to step back from SP to avoid data
1296 // dependencies with other things on below SP (callee-saves, for
1297 // example). Without a clear way to figure out the minimal safe
1298 // distance from SP, it makes sense to step back the complete
1299 // cache line, as this will also avoid possible second-order effects
1300 // with locked ops against the cache line. Our choice of offset
1301 // is bounded by x86 operand encoding, which should stay within
1302 // [-128; +127] to have the 8-byte displacement encoding.
1303 //
1304 // Any change to this code may need to revisit other places in
1305 // the code where this idiom is used, in particular the
1306 // orderAccess code.
1307
1308 int offset = -VM_Version::L1_line_size();
1309 if (offset < -128) {
1310 offset = -128;
1311 }
1312
1313 lock();
1314 addl(Address(rsp, offset), 0);// Assert the lock# signal here
1315 }
1316 }
1317 }
1318
1319 void mfence();
1320
1321 // Moves
1322
1323 void mov64(Register dst, int64_t imm64);
1324
1325 void movb(Address dst, Register src);
1326 void movb(Address dst, int imm8);
1327 void movb(Register dst, Address src);
1328
1329 void movddup(XMMRegister dst, XMMRegister src);
1330
1331 void kmovbl(KRegister dst, Register src);
1332 void kmovbl(Register dst, KRegister src);
1333 void kmovwl(KRegister dst, Register src);
1334 void kmovwl(Register dst, KRegister src);
1335 void kmovdl(KRegister dst, Register src);
1336 void kmovdl(Register dst, KRegister src);
1337 void kmovql(KRegister dst, KRegister src);
1338 void kmovql(Address dst, KRegister src);
1339 void kmovql(KRegister dst, Address src);
1340 void kmovql(KRegister dst, Register src);
1341 void kmovql(Register dst, KRegister src);
1342
1343 void kortestbl(KRegister dst, KRegister src);
1344 void kortestwl(KRegister dst, KRegister src);
1345 void kortestdl(KRegister dst, KRegister src);
1346 void kortestql(KRegister dst, KRegister src);
1347
1348 void movdl(XMMRegister dst, Register src);
1349 void movdl(Register dst, XMMRegister src);
1350 void movdl(XMMRegister dst, Address src);
1351 void movdl(Address dst, XMMRegister src);
1352
1353 // Move Double Quadword
1354 void movdq(XMMRegister dst, Register src);
1355 void movdq(Register dst, XMMRegister src);
1356
1357 // Move Aligned Double Quadword
1358 void movdqa(XMMRegister dst, XMMRegister src);
1359 void movdqa(XMMRegister dst, Address src);
1360
1361 // Move Unaligned Double Quadword
1362 void movdqu(Address dst, XMMRegister src);
1363 void movdqu(XMMRegister dst, Address src);
1364 void movdqu(XMMRegister dst, XMMRegister src);
1365
1366 // Move Unaligned 256bit Vector
1367 void vmovdqu(Address dst, XMMRegister src);
1368 void vmovdqu(XMMRegister dst, Address src);
1369 void vmovdqu(XMMRegister dst, XMMRegister src);
1370
1371 // Move Unaligned 512bit Vector
1372 void evmovdqub(Address dst, XMMRegister src, int vector_len);
1373 void evmovdqub(XMMRegister dst, Address src, int vector_len);
1374 void evmovdqub(XMMRegister dst, XMMRegister src, int vector_len);
1375 void evmovdquw(Address dst, XMMRegister src, int vector_len);
1376 void evmovdquw(XMMRegister dst, Address src, int vector_len);
1377 void evmovdquw(XMMRegister dst, XMMRegister src, int vector_len);
1378 void evmovdqul(Address dst, XMMRegister src, int vector_len);
1379 void evmovdqul(XMMRegister dst, Address src, int vector_len);
1380 void evmovdqul(XMMRegister dst, XMMRegister src, int vector_len);
1381 void evmovdquq(Address dst, XMMRegister src, int vector_len);
1382 void evmovdquq(XMMRegister dst, Address src, int vector_len);
1383 void evmovdquq(XMMRegister dst, XMMRegister src, int vector_len);
1384
1385 // Move lower 64bit to high 64bit in 128bit register
1386 void movlhps(XMMRegister dst, XMMRegister src);
1387
1388 void movl(Register dst, int32_t imm32);
1389 void movl(Address dst, int32_t imm32);
1390 void movl(Register dst, Register src);
1391 void movl(Register dst, Address src);
1392 void movl(Address dst, Register src);
1393
1394 // These dummies prevent using movl from converting a zero (like NULL) into Register
1395 // by giving the compiler two choices it can't resolve
1396
1397 void movl(Address dst, void* junk);
1398 void movl(Register dst, void* junk);
1399
1400 #ifdef _LP64
1401 void movq(Register dst, Register src);
1402 void movq(Register dst, Address src);
1403 void movq(Address dst, Register src);
1404 #endif
1405
1406 void movq(Address dst, MMXRegister src );
1407 void movq(MMXRegister dst, Address src );
1408
1409 #ifdef _LP64
1410 // These dummies prevent using movq from converting a zero (like NULL) into Register
1411 // by giving the compiler two choices it can't resolve
1412
1413 void movq(Address dst, void* dummy);
1414 void movq(Register dst, void* dummy);
1415 #endif
1416
1417 // Move Quadword
1418 void movq(Address dst, XMMRegister src);
1419 void movq(XMMRegister dst, Address src);
1420
1421 void movsbl(Register dst, Address src);
1422 void movsbl(Register dst, Register src);
1423
1424 #ifdef _LP64
1425 void movsbq(Register dst, Address src);
1426 void movsbq(Register dst, Register src);
1427
1428 // Move signed 32bit immediate to 64bit extending sign
1429 void movslq(Address dst, int32_t imm64);
1430 void movslq(Register dst, int32_t imm64);
1431
1432 void movslq(Register dst, Address src);
1433 void movslq(Register dst, Register src);
1434 void movslq(Register dst, void* src); // Dummy declaration to cause NULL to be ambiguous
1435 #endif
1436
1437 void movswl(Register dst, Address src);
1438 void movswl(Register dst, Register src);
1439
1440 #ifdef _LP64
1441 void movswq(Register dst, Address src);
1442 void movswq(Register dst, Register src);
1443 #endif
1444
1445 void movw(Address dst, int imm16);
1446 void movw(Register dst, Address src);
1447 void movw(Address dst, Register src);
1448
1449 void movzbl(Register dst, Address src);
1450 void movzbl(Register dst, Register src);
1451
1452 #ifdef _LP64
1453 void movzbq(Register dst, Address src);
1454 void movzbq(Register dst, Register src);
1455 #endif
1456
1457 void movzwl(Register dst, Address src);
1458 void movzwl(Register dst, Register src);
1459
1460 #ifdef _LP64
1461 void movzwq(Register dst, Address src);
1462 void movzwq(Register dst, Register src);
1463 #endif
1464
1465 // Unsigned multiply with RAX destination register
1466 void mull(Address src);
1467 void mull(Register src);
1468
1469 #ifdef _LP64
1470 void mulq(Address src);
1471 void mulq(Register src);
1472 void mulxq(Register dst1, Register dst2, Register src);
1473 #endif
1474
1475 // Multiply Scalar Double-Precision Floating-Point Values
1476 void mulsd(XMMRegister dst, Address src);
1477 void mulsd(XMMRegister dst, XMMRegister src);
1478
1479 // Multiply Scalar Single-Precision Floating-Point Values
1480 void mulss(XMMRegister dst, Address src);
1481 void mulss(XMMRegister dst, XMMRegister src);
1482
1483 void negl(Register dst);
1484
1485 #ifdef _LP64
1486 void negq(Register dst);
1487 #endif
1488
1489 void nop(int i = 1);
1490
1491 void notl(Register dst);
1492
1493 #ifdef _LP64
1494 void notq(Register dst);
1495 #endif
1496
1497 void orl(Address dst, int32_t imm32);
1498 void orl(Register dst, int32_t imm32);
1499 void orl(Register dst, Address src);
1500 void orl(Register dst, Register src);
1501 void orl(Address dst, Register src);
1502
1503 void orq(Address dst, int32_t imm32);
1504 void orq(Register dst, int32_t imm32);
1505 void orq(Register dst, Address src);
1506 void orq(Register dst, Register src);
1507
1508 // Pack with unsigned saturation
1509 void packuswb(XMMRegister dst, XMMRegister src);
1510 void packuswb(XMMRegister dst, Address src);
1511 void vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1512
1513 // Pemutation of 64bit words
1514 void vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len);
1515 void vpermq(XMMRegister dst, XMMRegister src, int imm8);
1516
1517 void pause();
1518
1519 // SSE4.2 string instructions
1520 void pcmpestri(XMMRegister xmm1, XMMRegister xmm2, int imm8);
1521 void pcmpestri(XMMRegister xmm1, Address src, int imm8);
1522
1523 void pcmpeqb(XMMRegister dst, XMMRegister src);
1524 void vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1525 void evpcmpeqb(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len);
1526 void evpcmpeqb(KRegister kdst, XMMRegister nds, Address src, int vector_len);
1527
1528 void pcmpeqw(XMMRegister dst, XMMRegister src);
1529 void vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1530 void evpcmpeqw(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len);
1531 void evpcmpeqw(KRegister kdst, XMMRegister nds, Address src, int vector_len);
1532
1533 void pcmpeqd(XMMRegister dst, XMMRegister src);
1534 void vpcmpeqd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1535 void evpcmpeqd(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len);
1536 void evpcmpeqd(KRegister kdst, XMMRegister nds, Address src, int vector_len);
1537
1538 void pcmpeqq(XMMRegister dst, XMMRegister src);
1539 void vpcmpeqq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1540 void evpcmpeqq(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len);
1541 void evpcmpeqq(KRegister kdst, XMMRegister nds, Address src, int vector_len);
1542
1543 void pmovmskb(Register dst, XMMRegister src);
1544 void vpmovmskb(Register dst, XMMRegister src);
1545
1546 // SSE 4.1 extract
1547 void pextrd(Register dst, XMMRegister src, int imm8);
1548 void pextrq(Register dst, XMMRegister src, int imm8);
1549 void pextrd(Address dst, XMMRegister src, int imm8);
1550 void pextrq(Address dst, XMMRegister src, int imm8);
1551 void pextrb(Address dst, XMMRegister src, int imm8);
1552 // SSE 2 extract
1553 void pextrw(Register dst, XMMRegister src, int imm8);
1554 void pextrw(Address dst, XMMRegister src, int imm8);
1555
1556 // SSE 4.1 insert
1557 void pinsrd(XMMRegister dst, Register src, int imm8);
1558 void pinsrq(XMMRegister dst, Register src, int imm8);
1559 void pinsrd(XMMRegister dst, Address src, int imm8);
1560 void pinsrq(XMMRegister dst, Address src, int imm8);
1561 void pinsrb(XMMRegister dst, Address src, int imm8);
1562 // SSE 2 insert
1563 void pinsrw(XMMRegister dst, Register src, int imm8);
1564 void pinsrw(XMMRegister dst, Address src, int imm8);
1565
1566 // SSE4.1 packed move
1567 void pmovzxbw(XMMRegister dst, XMMRegister src);
1568 void pmovzxbw(XMMRegister dst, Address src);
1569
1570 void vpmovzxbw(XMMRegister dst, Address src, int vector_len);
1571
1572 #ifndef _LP64 // no 32bit push/pop on amd64
1573 void popl(Address dst);
1574 #endif
1575
1576 #ifdef _LP64
1577 void popq(Address dst);
1578 #endif
1579
1580 void popcntl(Register dst, Address src);
1581 void popcntl(Register dst, Register src);
1582
1583 #ifdef _LP64
1584 void popcntq(Register dst, Address src);
1585 void popcntq(Register dst, Register src);
1586 #endif
1587
1588 // Prefetches (SSE, SSE2, 3DNOW only)
1589
1590 void prefetchnta(Address src);
1591 void prefetchr(Address src);
1592 void prefetcht0(Address src);
1593 void prefetcht1(Address src);
1594 void prefetcht2(Address src);
1595 void prefetchw(Address src);
1596
1597 // Shuffle Bytes
1598 void pshufb(XMMRegister dst, XMMRegister src);
1599 void pshufb(XMMRegister dst, Address src);
1600
1601 // Shuffle Packed Doublewords
1602 void pshufd(XMMRegister dst, XMMRegister src, int mode);
1603 void pshufd(XMMRegister dst, Address src, int mode);
1604
1605 // Shuffle Packed Low Words
1606 void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1607 void pshuflw(XMMRegister dst, Address src, int mode);
1608
1609 // Shift Right by bytes Logical DoubleQuadword Immediate
1610 void psrldq(XMMRegister dst, int shift);
1611 // Shift Left by bytes Logical DoubleQuadword Immediate
1612 void pslldq(XMMRegister dst, int shift);
1613
1614 // Logical Compare 128bit
1615 void ptest(XMMRegister dst, XMMRegister src);
1616 void ptest(XMMRegister dst, Address src);
1617 // Logical Compare 256bit
1618 void vptest(XMMRegister dst, XMMRegister src);
1619 void vptest(XMMRegister dst, Address src);
1620
1621 // Interleave Low Bytes
1622 void punpcklbw(XMMRegister dst, XMMRegister src);
1623 void punpcklbw(XMMRegister dst, Address src);
1624
1625 // Interleave Low Doublewords
1626 void punpckldq(XMMRegister dst, XMMRegister src);
1627 void punpckldq(XMMRegister dst, Address src);
1628
1629 // Interleave Low Quadwords
1630 void punpcklqdq(XMMRegister dst, XMMRegister src);
1631
1632 #ifndef _LP64 // no 32bit push/pop on amd64
1633 void pushl(Address src);
1634 #endif
1635
1636 void pushq(Address src);
1637
1638 void rcll(Register dst, int imm8);
1639
1640 void rclq(Register dst, int imm8);
1641
1642 void rcrq(Register dst, int imm8);
1643
1644 void rcpps(XMMRegister dst, XMMRegister src);
1645
1646 void rcpss(XMMRegister dst, XMMRegister src);
1647
1648 void rdtsc();
1649
1650 void ret(int imm16);
1651
1652 #ifdef _LP64
1653 void rorq(Register dst, int imm8);
1654 void rorxq(Register dst, Register src, int imm8);
1655 #endif
1656
1657 void sahf();
1658
1659 void sarl(Register dst, int imm8);
1660 void sarl(Register dst);
1661
1662 void sarq(Register dst, int imm8);
1663 void sarq(Register dst);
1664
1665 void sbbl(Address dst, int32_t imm32);
1666 void sbbl(Register dst, int32_t imm32);
1667 void sbbl(Register dst, Address src);
1668 void sbbl(Register dst, Register src);
1669
1670 void sbbq(Address dst, int32_t imm32);
1671 void sbbq(Register dst, int32_t imm32);
1672 void sbbq(Register dst, Address src);
1673 void sbbq(Register dst, Register src);
1674
1675 void setb(Condition cc, Register dst);
1676
1677 void palignr(XMMRegister dst, XMMRegister src, int imm8);
1678 void pblendw(XMMRegister dst, XMMRegister src, int imm8);
1679
1680 void sha1rnds4(XMMRegister dst, XMMRegister src, int imm8);
1681 void sha1nexte(XMMRegister dst, XMMRegister src);
1682 void sha1msg1(XMMRegister dst, XMMRegister src);
1683 void sha1msg2(XMMRegister dst, XMMRegister src);
1684 // xmm0 is implicit additional source to the following instruction.
1685 void sha256rnds2(XMMRegister dst, XMMRegister src);
1686 void sha256msg1(XMMRegister dst, XMMRegister src);
1687 void sha256msg2(XMMRegister dst, XMMRegister src);
1688
1689 void shldl(Register dst, Register src);
1690 void shldl(Register dst, Register src, int8_t imm8);
1691
1692 void shll(Register dst, int imm8);
1693 void shll(Register dst);
1694
1695 void shlq(Register dst, int imm8);
1696 void shlq(Register dst);
1697
1698 void shrdl(Register dst, Register src);
1699
1700 void shrl(Register dst, int imm8);
1701 void shrl(Register dst);
1702
1703 void shrq(Register dst, int imm8);
1704 void shrq(Register dst);
1705
1706 void smovl(); // QQQ generic?
1707
1708 // Compute Square Root of Scalar Double-Precision Floating-Point Value
1709 void sqrtsd(XMMRegister dst, Address src);
1710 void sqrtsd(XMMRegister dst, XMMRegister src);
1711
1712 // Compute Square Root of Scalar Single-Precision Floating-Point Value
1713 void sqrtss(XMMRegister dst, Address src);
1714 void sqrtss(XMMRegister dst, XMMRegister src);
1715
1716 void std();
1717
1718 void stmxcsr( Address dst );
1719
1720 void subl(Address dst, int32_t imm32);
1721 void subl(Address dst, Register src);
1722 void subl(Register dst, int32_t imm32);
1723 void subl(Register dst, Address src);
1724 void subl(Register dst, Register src);
1725
1726 void subq(Address dst, int32_t imm32);
1727 void subq(Address dst, Register src);
1728 void subq(Register dst, int32_t imm32);
1729 void subq(Register dst, Address src);
1730 void subq(Register dst, Register src);
1731
1732 // Force generation of a 4 byte immediate value even if it fits into 8bit
1733 void subl_imm32(Register dst, int32_t imm32);
1734 void subq_imm32(Register dst, int32_t imm32);
1735
1736 // Subtract Scalar Double-Precision Floating-Point Values
1737 void subsd(XMMRegister dst, Address src);
1738 void subsd(XMMRegister dst, XMMRegister src);
1739
1740 // Subtract Scalar Single-Precision Floating-Point Values
1741 void subss(XMMRegister dst, Address src);
1742 void subss(XMMRegister dst, XMMRegister src);
1743
1744 void testb(Register dst, int imm8);
1745 void testb(Address dst, int imm8);
1746
1747 void testl(Register dst, int32_t imm32);
1748 void testl(Register dst, Register src);
1749 void testl(Register dst, Address src);
1750
1751 void testq(Register dst, int32_t imm32);
1752 void testq(Register dst, Register src);
1753
1754 // BMI - count trailing zeros
1755 void tzcntl(Register dst, Register src);
1756 void tzcntq(Register dst, Register src);
1757
1758 // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
1759 void ucomisd(XMMRegister dst, Address src);
1760 void ucomisd(XMMRegister dst, XMMRegister src);
1761
1762 // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
1763 void ucomiss(XMMRegister dst, Address src);
1764 void ucomiss(XMMRegister dst, XMMRegister src);
1765
1766 void xabort(int8_t imm8);
1767
1768 void xaddl(Address dst, Register src);
1769
1770 void xaddq(Address dst, Register src);
1771
1772 void xbegin(Label& abort, relocInfo::relocType rtype = relocInfo::none);
1773
1774 void xchgl(Register reg, Address adr);
1775 void xchgl(Register dst, Register src);
1776
1777 void xchgq(Register reg, Address adr);
1778 void xchgq(Register dst, Register src);
1779
1780 void xend();
1781
1782 // Get Value of Extended Control Register
1783 void xgetbv();
1784
1785 void xorl(Register dst, int32_t imm32);
1786 void xorl(Register dst, Address src);
1787 void xorl(Register dst, Register src);
1788
1789 void xorb(Register dst, Address src);
1790
1791 void xorq(Register dst, Address src);
1792 void xorq(Register dst, Register src);
1793
1794 void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0
1795
1796 // AVX 3-operands scalar instructions (encoded with VEX prefix)
1797
1798 void vaddsd(XMMRegister dst, XMMRegister nds, Address src);
1799 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1800 void vaddss(XMMRegister dst, XMMRegister nds, Address src);
1801 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1802 void vdivsd(XMMRegister dst, XMMRegister nds, Address src);
1803 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1804 void vdivss(XMMRegister dst, XMMRegister nds, Address src);
1805 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1806 void vmulsd(XMMRegister dst, XMMRegister nds, Address src);
1807 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1808 void vmulss(XMMRegister dst, XMMRegister nds, Address src);
1809 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1810 void vsubsd(XMMRegister dst, XMMRegister nds, Address src);
1811 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1812 void vsubss(XMMRegister dst, XMMRegister nds, Address src);
1813 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1814
1815
1816 //====================VECTOR ARITHMETIC=====================================
1817
1818 // Add Packed Floating-Point Values
1819 void addpd(XMMRegister dst, XMMRegister src);
1820 void addpd(XMMRegister dst, Address src);
1821 void addps(XMMRegister dst, XMMRegister src);
1822 void vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1823 void vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1824 void vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1825 void vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1826
1827 // Subtract Packed Floating-Point Values
1828 void subpd(XMMRegister dst, XMMRegister src);
1829 void subps(XMMRegister dst, XMMRegister src);
1830 void vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1831 void vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1832 void vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1833 void vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1834
1835 // Multiply Packed Floating-Point Values
1836 void mulpd(XMMRegister dst, XMMRegister src);
1837 void mulpd(XMMRegister dst, Address src);
1838 void mulps(XMMRegister dst, XMMRegister src);
1839 void vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1840 void vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1841 void vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1842 void vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1843
1844 // Divide Packed Floating-Point Values
1845 void divpd(XMMRegister dst, XMMRegister src);
1846 void divps(XMMRegister dst, XMMRegister src);
1847 void vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1848 void vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1849 void vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1850 void vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1851
1852 // Sqrt Packed Floating-Point Values - Double precision only
1853 void vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len);
1854 void vsqrtpd(XMMRegister dst, Address src, int vector_len);
1855
1856 // Bitwise Logical AND of Packed Floating-Point Values
1857 void andpd(XMMRegister dst, XMMRegister src);
1858 void andps(XMMRegister dst, XMMRegister src);
1859 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1860 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1861 void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1862 void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1863
1864 void unpckhpd(XMMRegister dst, XMMRegister src);
1865 void unpcklpd(XMMRegister dst, XMMRegister src);
1866
1867 // Bitwise Logical XOR of Packed Floating-Point Values
1868 void xorpd(XMMRegister dst, XMMRegister src);
1869 void xorps(XMMRegister dst, XMMRegister src);
1870 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1871 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1872 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1873 void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1874
1875 // Add horizontal packed integers
1876 void vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1877 void vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1878 void phaddw(XMMRegister dst, XMMRegister src);
1879 void phaddd(XMMRegister dst, XMMRegister src);
1880
1881 // Add packed integers
1882 void paddb(XMMRegister dst, XMMRegister src);
1883 void paddw(XMMRegister dst, XMMRegister src);
1884 void paddd(XMMRegister dst, XMMRegister src);
1885 void paddd(XMMRegister dst, Address src);
1886 void paddq(XMMRegister dst, XMMRegister src);
1887 void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1888 void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1889 void vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1890 void vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1891 void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1892 void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1893 void vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1894 void vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1895
1896 // Sub packed integers
1897 void psubb(XMMRegister dst, XMMRegister src);
1898 void psubw(XMMRegister dst, XMMRegister src);
1899 void psubd(XMMRegister dst, XMMRegister src);
1900 void psubq(XMMRegister dst, XMMRegister src);
1901 void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1902 void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1903 void vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1904 void vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1905 void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1906 void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1907 void vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1908 void vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1909
1910 // Multiply packed integers (only shorts and ints)
1911 void pmullw(XMMRegister dst, XMMRegister src);
1912 void pmulld(XMMRegister dst, XMMRegister src);
1913 void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1914 void vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1915 void vpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1916 void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1917 void vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1918 void vpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1919
1920 // Shift left packed integers
1921 void psllw(XMMRegister dst, int shift);
1922 void pslld(XMMRegister dst, int shift);
1923 void psllq(XMMRegister dst, int shift);
1924 void psllw(XMMRegister dst, XMMRegister shift);
1925 void pslld(XMMRegister dst, XMMRegister shift);
1926 void psllq(XMMRegister dst, XMMRegister shift);
1927 void vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len);
1928 void vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len);
1929 void vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
1930 void vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
1931 void vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
1932 void vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
1933
1934 // Logical shift right packed integers
1935 void psrlw(XMMRegister dst, int shift);
1936 void psrld(XMMRegister dst, int shift);
1937 void psrlq(XMMRegister dst, int shift);
1938 void psrlw(XMMRegister dst, XMMRegister shift);
1939 void psrld(XMMRegister dst, XMMRegister shift);
1940 void psrlq(XMMRegister dst, XMMRegister shift);
1941 void vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len);
1942 void vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len);
1943 void vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
1944 void vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
1945 void vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
1946 void vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
1947
1948 // Arithmetic shift right packed integers (only shorts and ints, no instructions for longs)
1949 void psraw(XMMRegister dst, int shift);
1950 void psrad(XMMRegister dst, int shift);
1951 void psraw(XMMRegister dst, XMMRegister shift);
1952 void psrad(XMMRegister dst, XMMRegister shift);
1953 void vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len);
1954 void vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len);
1955 void vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
1956 void vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
1957
1958 // And packed integers
1959 void pand(XMMRegister dst, XMMRegister src);
1960 void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1961 void vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1962
1963 // Andn packed integers
1964 void pandn(XMMRegister dst, XMMRegister src);
1965
1966 // Or packed integers
1967 void por(XMMRegister dst, XMMRegister src);
1968 void vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1969 void vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1970
1971 // Xor packed integers
1972 void pxor(XMMRegister dst, XMMRegister src);
1973 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1974 void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1975
1976 // 128bit copy from/to 256bit (YMM) vector registers
1977 void vinsertf128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
1978 void vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
1979 void vextractf128(XMMRegister dst, XMMRegister src, uint8_t imm8);
1980 void vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8);
1981 void vinsertf128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
1982 void vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
1983 void vextractf128(Address dst, XMMRegister src, uint8_t imm8);
1984 void vextracti128(Address dst, XMMRegister src, uint8_t imm8);
1985
1986 // 256bit copy from/to 512bit (ZMM) vector registers
1987 void vinserti64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
1988 void vinsertf64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
1989 void vextracti64x4(XMMRegister dst, XMMRegister src, uint8_t imm8);
1990 void vextractf64x4(XMMRegister dst, XMMRegister src, uint8_t imm8);
1991 void vextractf64x4(Address dst, XMMRegister src, uint8_t imm8);
1992 void vinsertf64x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
1993
1994 // 128bit copy from/to 256bit (YMM) or 512bit (ZMM) vector registers
1995 void vextracti64x2(XMMRegister dst, XMMRegister src, uint8_t imm8);
1996 void vextractf64x2(XMMRegister dst, XMMRegister src, uint8_t imm8);
1997 void vextractf32x4(XMMRegister dst, XMMRegister src, uint8_t imm8);
1998 void vextractf32x4(Address dst, XMMRegister src, uint8_t imm8);
1999 void vinsertf32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2000 void vinsertf32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
2001
2002 // duplicate 4-bytes integer data from src into 8 locations in dest
2003 void vpbroadcastd(XMMRegister dst, XMMRegister src);
2004
2005 // duplicate 2-bytes integer data from src into 16 locations in dest
2006 void vpbroadcastw(XMMRegister dst, XMMRegister src);
2007
2008 // duplicate n-bytes integer data from src into vector_len locations in dest
2009 void evpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len);
2010 void evpbroadcastb(XMMRegister dst, Address src, int vector_len);
2011 void evpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len);
2012 void evpbroadcastw(XMMRegister dst, Address src, int vector_len);
2013 void evpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len);
2014 void evpbroadcastd(XMMRegister dst, Address src, int vector_len);
2015 void evpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len);
2016 void evpbroadcastq(XMMRegister dst, Address src, int vector_len);
2017
2018 void evpbroadcastss(XMMRegister dst, XMMRegister src, int vector_len);
2019 void evpbroadcastss(XMMRegister dst, Address src, int vector_len);
2020 void evpbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len);
2021 void evpbroadcastsd(XMMRegister dst, Address src, int vector_len);
2022
2023 void evpbroadcastb(XMMRegister dst, Register src, int vector_len);
2024 void evpbroadcastw(XMMRegister dst, Register src, int vector_len);
2025 void evpbroadcastd(XMMRegister dst, Register src, int vector_len);
2026 void evpbroadcastq(XMMRegister dst, Register src, int vector_len);
2027
2028 // Carry-Less Multiplication Quadword
2029 void pclmulqdq(XMMRegister dst, XMMRegister src, int mask);
2030 void vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask);
2031
2032 // AVX instruction which is used to clear upper 128 bits of YMM registers and
2033 // to avoid transaction penalty between AVX and SSE states. There is no
2034 // penalty if legacy SSE instructions are encoded using VEX prefix because
2035 // they always clear upper 128 bits. It should be used before calling
2036 // runtime code and native libraries.
2037 void vzeroupper();
2038
2039 // AVX support for vectorized conditional move (double). The following two instructions used only coupled.
2040 void cmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len);
2041 void vpblendd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len);
2042
2043
2044 protected:
2045 // Next instructions require address alignment 16 bytes SSE mode.
2046 // They should be called only from corresponding MacroAssembler instructions.
2047 void andpd(XMMRegister dst, Address src);
2048 void andps(XMMRegister dst, Address src);
2049 void xorpd(XMMRegister dst, Address src);
2050 void xorps(XMMRegister dst, Address src);
2051
2052 };
2053
2054 // The Intel x86/Amd64 Assembler attributes: All fields enclosed here are to guide encoding level decisions.
2055 // Specific set functions are for specialized use, else defaults or whatever was supplied to object construction
2056 // are applied.
2057 class InstructionAttr {
2058 public:
2059 InstructionAttr(
2060 int vector_len, // The length of vector to be applied in encoding - for both AVX and EVEX
2061 bool rex_vex_w, // Width of data: if 32-bits or less, false, else if 64-bit or specially defined, true
2062 bool legacy_mode, // Details if either this instruction is conditionally encoded to AVX or earlier if true else possibly EVEX
2063 bool no_reg_mask, // when true, k0 is used when EVEX encoding is chosen, else k1 is used under the same condition
2064 bool uses_vl) // This instruction may have legacy constraints based on vector length for EVEX
2065 :
2066 _avx_vector_len(vector_len),
2067 _rex_vex_w(rex_vex_w),
2068 _legacy_mode(legacy_mode),
2069 _no_reg_mask(no_reg_mask),
2070 _uses_vl(uses_vl),
2071 _tuple_type(Assembler::EVEX_ETUP),
2072 _input_size_in_bits(Assembler::EVEX_NObit),
2073 _is_evex_instruction(false),
2074 _evex_encoding(0),
2075 _is_clear_context(false),
2076 _is_extended_context(false),
2077 _current_assembler(NULL) {
2078 if (UseAVX < 3) _legacy_mode = true;
2079 }
2080
2081 ~InstructionAttr() {
2082 if (_current_assembler != NULL) {
2083 _current_assembler->clear_attributes();
2084 }
2085 _current_assembler = NULL;
2086 }
2087
2088 private:
2089 int _avx_vector_len;
2090 bool _rex_vex_w;
2091 bool _legacy_mode;
2092 bool _no_reg_mask;
2093 bool _uses_vl;
2094 int _tuple_type;
2095 int _input_size_in_bits;
2096 bool _is_evex_instruction;
2097 int _evex_encoding;
2098 bool _is_clear_context;
2099 bool _is_extended_context;
2100
2101 Assembler *_current_assembler;
2102
2103 public:
2104 // query functions for field accessors
2105 int get_vector_len(void) const { return _avx_vector_len; }
2106 bool is_rex_vex_w(void) const { return _rex_vex_w; }
2107 bool is_legacy_mode(void) const { return _legacy_mode; }
2108 bool is_no_reg_mask(void) const { return _no_reg_mask; }
2109 bool uses_vl(void) const { return _uses_vl; }
2110 int get_tuple_type(void) const { return _tuple_type; }
2111 int get_input_size(void) const { return _input_size_in_bits; }
2112 int is_evex_instruction(void) const { return _is_evex_instruction; }
2113 int get_evex_encoding(void) const { return _evex_encoding; }
2114 bool is_clear_context(void) const { return _is_clear_context; }
2115 bool is_extended_context(void) const { return _is_extended_context; }
2116
2117 // Set the vector len manually
2118 void set_vector_len(int vector_len) { _avx_vector_len = vector_len; }
2119
2120 // Set the instruction to be encoded in AVX mode
2121 void set_is_legacy_mode(void) { _legacy_mode = true; }
2122
2123 // Set the current instuction to be encoded as an EVEX instuction
2124 void set_is_evex_instruction(void) { _is_evex_instruction = true; }
2125
2126 // Internal encoding data used in compressed immediate offset programming
2127 void set_evex_encoding(int value) { _evex_encoding = value; }
2128
2129 // Set the Evex.Z field to be used to clear all non directed XMM/YMM/ZMM components
2130 void set_is_clear_context(void) { _is_clear_context = true; }
2131
2132 // Map back to current asembler so that we can manage object level assocation
2133 void set_current_assembler(Assembler *current_assembler) { _current_assembler = current_assembler; }
2134
2135 // Address modifiers used for compressed displacement calculation
2136 void set_address_attributes(int tuple_type, int input_size_in_bits) {
2137 if (VM_Version::supports_evex()) {
2138 _tuple_type = tuple_type;
2139 _input_size_in_bits = input_size_in_bits;
2140 }
2141 }
2142
2143 };
2144
2145 #endif // CPU_X86_VM_ASSEMBLER_X86_HPP