9802 format %{ "SUB ESP,8\t # DMOD\n"
9803 "\tMOVSD [ESP+0],$src1\n"
9804 "\tFLD_D [ESP+0]\n"
9805 "\tMOVSD [ESP+0],$src0\n"
9806 "\tFLD_D [ESP+0]\n"
9807 "loop:\tFPREM\n"
9808 "\tFWAIT\n"
9809 "\tFNSTSW AX\n"
9810 "\tSAHF\n"
9811 "\tJP loop\n"
9812 "\tFSTP_D [ESP+0]\n"
9813 "\tMOVSD $dst,[ESP+0]\n"
9814 "\tADD ESP,8\n"
9815 "\tFSTP ST0\t # Restore FPU Stack"
9816 %}
9817 ins_cost(250);
9818 ins_encode( Push_ModD_encoding(src0, src1), emitModDPR(), Push_ResultD(dst), PopFPU);
9819 ins_pipe( pipe_slow );
9820 %}
9821
9822 instruct tanDPR_reg(regDPR1 dst, regDPR1 src) %{
9823 predicate (UseSSE<=1);
9824 match(Set dst(TanD src));
9825 format %{ "DTAN $dst" %}
9826 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan
9827 Opcode(0xDD), Opcode(0xD8)); // fstp st
9828 ins_pipe( pipe_slow );
9829 %}
9830
9831 instruct tanD_reg(regD dst, eFlagsReg cr) %{
9832 predicate (UseSSE>=2);
9833 match(Set dst(TanD dst));
9834 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9835 format %{ "DTAN $dst" %}
9836 ins_encode( Push_SrcD(dst),
9837 Opcode(0xD9), Opcode(0xF2), // fptan
9838 Opcode(0xDD), Opcode(0xD8), // fstp st
9839 Push_ResultD(dst) );
9840 ins_pipe( pipe_slow );
9841 %}
9842
9843 instruct atanDPR_reg(regDPR dst, regDPR src) %{
9844 predicate (UseSSE<=1);
9845 match(Set dst(AtanD dst src));
9846 format %{ "DATA $dst,$src" %}
9847 opcode(0xD9, 0xF3);
9848 ins_encode( Push_Reg_DPR(src),
9849 OpcP, OpcS, RegOpc(dst) );
9850 ins_pipe( pipe_slow );
9851 %}
9852
9853 instruct atanD_reg(regD dst, regD src, eFlagsReg cr) %{
9854 predicate (UseSSE>=2);
9855 match(Set dst(AtanD dst src));
9856 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9857 format %{ "DATA $dst,$src" %}
9858 opcode(0xD9, 0xF3);
9859 ins_encode( Push_SrcD(src),
9860 OpcP, OpcS, Push_ResultD(dst) );
9861 ins_pipe( pipe_slow );
9862 %}
9863
9864 instruct sqrtDPR_reg(regDPR dst, regDPR src) %{
9865 predicate (UseSSE<=1);
9866 match(Set dst (SqrtD src));
9867 format %{ "DSQRT $dst,$src" %}
9868 opcode(0xFA, 0xD9);
9869 ins_encode( Push_Reg_DPR(src),
9870 OpcS, OpcP, Pop_Reg_DPR(dst) );
9871 ins_pipe( pipe_slow );
9872 %}
9873
9874 instruct log10DPR_reg(regDPR1 dst, regDPR1 src) %{
9875 predicate (UseSSE<=1);
9876 // The source Double operand on FPU stack
9877 match(Set dst (Log10D src));
9878 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
9879 // fxch ; swap ST(0) with ST(1)
9880 // fyl2x ; compute log_10(2) * log_2(x)
9881 format %{ "FLDLG2 \t\t\t#Log10\n\t"
9882 "FXCH \n\t"
9883 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
9884 %}
9885 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
9886 Opcode(0xD9), Opcode(0xC9), // fxch
9887 Opcode(0xD9), Opcode(0xF1)); // fyl2x
9888
9889 ins_pipe( pipe_slow );
9890 %}
9891
9892 instruct log10D_reg(regD dst, regD src, eFlagsReg cr) %{
9893 predicate (UseSSE>=2);
9894 effect(KILL cr);
9895 match(Set dst (Log10D src));
9896 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
9897 // fyl2x ; compute log_10(2) * log_2(x)
9898 format %{ "FLDLG2 \t\t\t#Log10\n\t"
9899 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
9900 %}
9901 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
9902 Push_SrcD(src),
9903 Opcode(0xD9), Opcode(0xF1), // fyl2x
9904 Push_ResultD(dst));
9905
9906 ins_pipe( pipe_slow );
9907 %}
9908
9909 //-------------Float Instructions-------------------------------
9910 // Float Math
9911
9912 // Code for float compare:
9913 // fcompp();
9914 // fwait(); fnstsw_ax();
9915 // sahf();
9916 // movl(dst, unordered_result);
9917 // jcc(Assembler::parity, exit);
9918 // movl(dst, less_result);
9919 // jcc(Assembler::below, exit);
9920 // movl(dst, equal_result);
9921 // jcc(Assembler::equal, exit);
9922 // movl(dst, greater_result);
9923 // exit:
9924
9925 // P6 version of float compare, sets condition codes in EFLAGS
|
9802 format %{ "SUB ESP,8\t # DMOD\n"
9803 "\tMOVSD [ESP+0],$src1\n"
9804 "\tFLD_D [ESP+0]\n"
9805 "\tMOVSD [ESP+0],$src0\n"
9806 "\tFLD_D [ESP+0]\n"
9807 "loop:\tFPREM\n"
9808 "\tFWAIT\n"
9809 "\tFNSTSW AX\n"
9810 "\tSAHF\n"
9811 "\tJP loop\n"
9812 "\tFSTP_D [ESP+0]\n"
9813 "\tMOVSD $dst,[ESP+0]\n"
9814 "\tADD ESP,8\n"
9815 "\tFSTP ST0\t # Restore FPU Stack"
9816 %}
9817 ins_cost(250);
9818 ins_encode( Push_ModD_encoding(src0, src1), emitModDPR(), Push_ResultD(dst), PopFPU);
9819 ins_pipe( pipe_slow );
9820 %}
9821
9822 instruct atanDPR_reg(regDPR dst, regDPR src) %{
9823 predicate (UseSSE<=1);
9824 match(Set dst(AtanD dst src));
9825 format %{ "DATA $dst,$src" %}
9826 opcode(0xD9, 0xF3);
9827 ins_encode( Push_Reg_DPR(src),
9828 OpcP, OpcS, RegOpc(dst) );
9829 ins_pipe( pipe_slow );
9830 %}
9831
9832 instruct atanD_reg(regD dst, regD src, eFlagsReg cr) %{
9833 predicate (UseSSE>=2);
9834 match(Set dst(AtanD dst src));
9835 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9836 format %{ "DATA $dst,$src" %}
9837 opcode(0xD9, 0xF3);
9838 ins_encode( Push_SrcD(src),
9839 OpcP, OpcS, Push_ResultD(dst) );
9840 ins_pipe( pipe_slow );
9841 %}
9842
9843 instruct sqrtDPR_reg(regDPR dst, regDPR src) %{
9844 predicate (UseSSE<=1);
9845 match(Set dst (SqrtD src));
9846 format %{ "DSQRT $dst,$src" %}
9847 opcode(0xFA, 0xD9);
9848 ins_encode( Push_Reg_DPR(src),
9849 OpcS, OpcP, Pop_Reg_DPR(dst) );
9850 ins_pipe( pipe_slow );
9851 %}
9852
9853 //-------------Float Instructions-------------------------------
9854 // Float Math
9855
9856 // Code for float compare:
9857 // fcompp();
9858 // fwait(); fnstsw_ax();
9859 // sahf();
9860 // movl(dst, unordered_result);
9861 // jcc(Assembler::parity, exit);
9862 // movl(dst, less_result);
9863 // jcc(Assembler::below, exit);
9864 // movl(dst, equal_result);
9865 // jcc(Assembler::equal, exit);
9866 // movl(dst, greater_result);
9867 // exit:
9868
9869 // P6 version of float compare, sets condition codes in EFLAGS
|