1810 emit_operand(dst, src);
1811 }
1812
1813
1814 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
1815 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1816 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1817 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1818 emit_int8(0x2C);
1819 emit_int8((unsigned char)(0xC0 | encode));
1820 }
1821
1822 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
1823 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1824 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1825 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1826 emit_int8(0x2C);
1827 emit_int8((unsigned char)(0xC0 | encode));
1828 }
1829
1830 void Assembler::decl(Address dst) {
1831 // Don't use it directly. Use MacroAssembler::decrement() instead.
1832 InstructionMark im(this);
1833 prefix(dst);
1834 emit_int8((unsigned char)0xFF);
1835 emit_operand(rcx, dst);
1836 }
1837
1838 void Assembler::divsd(XMMRegister dst, Address src) {
1839 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1840 InstructionMark im(this);
1841 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1842 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1843 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1844 emit_int8(0x5E);
1845 emit_operand(dst, src);
1846 }
1847
1848 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
1849 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5032 }
5033
5034 void Assembler::paddd(XMMRegister dst, Address src) {
5035 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5036 InstructionMark im(this);
5037 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5038 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5039 emit_int8((unsigned char)0xFE);
5040 emit_operand(dst, src);
5041 }
5042
5043 void Assembler::paddq(XMMRegister dst, XMMRegister src) {
5044 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5045 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5046 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5047 emit_int8((unsigned char)0xD4);
5048 emit_int8((unsigned char)(0xC0 | encode));
5049 }
5050
5051 void Assembler::phaddw(XMMRegister dst, XMMRegister src) {
5052 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
5053 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5054 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5055 emit_int8(0x01);
5056 emit_int8((unsigned char)(0xC0 | encode));
5057 }
5058
5059 void Assembler::phaddd(XMMRegister dst, XMMRegister src) {
5060 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
5061 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5062 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5063 emit_int8(0x02);
5064 emit_int8((unsigned char)(0xC0 | encode));
5065 }
5066
5067 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5068 assert(UseAVX > 0, "requires some form of AVX");
5069 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5070 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5071 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5072 emit_int8((unsigned char)0xFC);
5073 emit_int8((unsigned char)(0xC0 | encode));
5074 }
5075
5076 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5077 assert(UseAVX > 0, "requires some form of AVX");
5078 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5079 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5080 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
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1810 emit_operand(dst, src);
1811 }
1812
1813
1814 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
1815 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1816 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1817 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1818 emit_int8(0x2C);
1819 emit_int8((unsigned char)(0xC0 | encode));
1820 }
1821
1822 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
1823 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1824 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1825 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1826 emit_int8(0x2C);
1827 emit_int8((unsigned char)(0xC0 | encode));
1828 }
1829
1830 void Assembler::cvttpd2dq(XMMRegister dst, XMMRegister src) {
1831 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1832 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
1833 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
1834 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1835 emit_int8((unsigned char)0xE6);
1836 emit_int8((unsigned char)(0xC0 | encode));
1837 }
1838
1839 void Assembler::decl(Address dst) {
1840 // Don't use it directly. Use MacroAssembler::decrement() instead.
1841 InstructionMark im(this);
1842 prefix(dst);
1843 emit_int8((unsigned char)0xFF);
1844 emit_operand(rcx, dst);
1845 }
1846
1847 void Assembler::divsd(XMMRegister dst, Address src) {
1848 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1849 InstructionMark im(this);
1850 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1851 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1852 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1853 emit_int8(0x5E);
1854 emit_operand(dst, src);
1855 }
1856
1857 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
1858 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5041 }
5042
5043 void Assembler::paddd(XMMRegister dst, Address src) {
5044 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5045 InstructionMark im(this);
5046 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5047 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5048 emit_int8((unsigned char)0xFE);
5049 emit_operand(dst, src);
5050 }
5051
5052 void Assembler::paddq(XMMRegister dst, XMMRegister src) {
5053 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5054 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5055 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5056 emit_int8((unsigned char)0xD4);
5057 emit_int8((unsigned char)(0xC0 | encode));
5058 }
5059
5060 void Assembler::phaddw(XMMRegister dst, XMMRegister src) {
5061 assert(VM_Version::supports_sse3(), "");
5062 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5063 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5064 emit_int8(0x01);
5065 emit_int8((unsigned char)(0xC0 | encode));
5066 }
5067
5068 void Assembler::phaddd(XMMRegister dst, XMMRegister src) {
5069 assert(VM_Version::supports_sse3(), "");
5070 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5071 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5072 emit_int8(0x02);
5073 emit_int8((unsigned char)(0xC0 | encode));
5074 }
5075
5076 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5077 assert(UseAVX > 0, "requires some form of AVX");
5078 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5079 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5080 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5081 emit_int8((unsigned char)0xFC);
5082 emit_int8((unsigned char)(0xC0 | encode));
5083 }
5084
5085 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5086 assert(UseAVX > 0, "requires some form of AVX");
5087 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5088 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5089 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
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