1 /* 2 * Copyright (c) 2000, 2015, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "c1/c1_InstructionPrinter.hpp" 27 #include "c1/c1_LIR.hpp" 28 #include "c1/c1_LIRAssembler.hpp" 29 #include "c1/c1_ValueStack.hpp" 30 #include "ci/ciInstance.hpp" 31 #include "runtime/sharedRuntime.hpp" 32 33 Register LIR_OprDesc::as_register() const { 34 return FrameMap::cpu_rnr2reg(cpu_regnr()); 35 } 36 37 Register LIR_OprDesc::as_register_lo() const { 38 return FrameMap::cpu_rnr2reg(cpu_regnrLo()); 39 } 40 41 Register LIR_OprDesc::as_register_hi() const { 42 return FrameMap::cpu_rnr2reg(cpu_regnrHi()); 43 } 44 45 #if defined(X86) 46 47 XMMRegister LIR_OprDesc::as_xmm_float_reg() const { 48 return FrameMap::nr2xmmreg(xmm_regnr()); 49 } 50 51 XMMRegister LIR_OprDesc::as_xmm_double_reg() const { 52 assert(xmm_regnrLo() == xmm_regnrHi(), "assumed in calculation"); 53 return FrameMap::nr2xmmreg(xmm_regnrLo()); 54 } 55 56 #endif // X86 57 58 #if defined(SPARC) || defined(PPC32) 59 60 FloatRegister LIR_OprDesc::as_float_reg() const { 61 return FrameMap::nr2floatreg(fpu_regnr()); 62 } 63 64 FloatRegister LIR_OprDesc::as_double_reg() const { 65 return FrameMap::nr2floatreg(fpu_regnrHi()); 66 } 67 68 #endif 69 70 #if defined(ARM) || defined(AARCH64) || defined(PPC64) 71 72 FloatRegister LIR_OprDesc::as_float_reg() const { 73 return as_FloatRegister(fpu_regnr()); 74 } 75 76 FloatRegister LIR_OprDesc::as_double_reg() const { 77 return as_FloatRegister(fpu_regnrLo()); 78 } 79 80 #endif 81 82 83 LIR_Opr LIR_OprFact::illegalOpr = LIR_OprFact::illegal(); 84 85 LIR_Opr LIR_OprFact::value_type(ValueType* type) { 86 ValueTag tag = type->tag(); 87 switch (tag) { 88 case metaDataTag : { 89 ClassConstant* c = type->as_ClassConstant(); 90 if (c != NULL && !c->value()->is_loaded()) { 91 return LIR_OprFact::metadataConst(NULL); 92 } else if (c != NULL) { 93 return LIR_OprFact::metadataConst(c->value()->constant_encoding()); 94 } else { 95 MethodConstant* m = type->as_MethodConstant(); 96 assert (m != NULL, "not a class or a method?"); 97 return LIR_OprFact::metadataConst(m->value()->constant_encoding()); 98 } 99 } 100 case objectTag : { 101 return LIR_OprFact::oopConst(type->as_ObjectType()->encoding()); 102 } 103 case addressTag: return LIR_OprFact::addressConst(type->as_AddressConstant()->value()); 104 case intTag : return LIR_OprFact::intConst(type->as_IntConstant()->value()); 105 case floatTag : return LIR_OprFact::floatConst(type->as_FloatConstant()->value()); 106 case longTag : return LIR_OprFact::longConst(type->as_LongConstant()->value()); 107 case doubleTag : return LIR_OprFact::doubleConst(type->as_DoubleConstant()->value()); 108 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1); 109 } 110 } 111 112 113 LIR_Opr LIR_OprFact::dummy_value_type(ValueType* type) { 114 switch (type->tag()) { 115 case objectTag: return LIR_OprFact::oopConst(NULL); 116 case addressTag:return LIR_OprFact::addressConst(0); 117 case intTag: return LIR_OprFact::intConst(0); 118 case floatTag: return LIR_OprFact::floatConst(0.0); 119 case longTag: return LIR_OprFact::longConst(0); 120 case doubleTag: return LIR_OprFact::doubleConst(0.0); 121 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1); 122 } 123 return illegalOpr; 124 } 125 126 127 128 //--------------------------------------------------- 129 130 131 LIR_Address::Scale LIR_Address::scale(BasicType type) { 132 int elem_size = type2aelembytes(type); 133 switch (elem_size) { 134 case 1: return LIR_Address::times_1; 135 case 2: return LIR_Address::times_2; 136 case 4: return LIR_Address::times_4; 137 case 8: return LIR_Address::times_8; 138 } 139 ShouldNotReachHere(); 140 return LIR_Address::times_1; 141 } 142 143 144 #ifndef PRODUCT 145 void LIR_Address::verify0() const { 146 #if defined(SPARC) || defined(PPC) 147 assert(scale() == times_1, "Scaled addressing mode not available on SPARC/PPC and should not be used"); 148 assert(disp() == 0 || index()->is_illegal(), "can't have both"); 149 #endif 150 #ifdef _LP64 151 assert(base()->is_cpu_register(), "wrong base operand"); 152 #ifndef AARCH64 153 assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand"); 154 #else 155 assert(index()->is_illegal() || index()->is_double_cpu() || index()->is_single_cpu(), "wrong index operand"); 156 #endif 157 assert(base()->type() == T_OBJECT || base()->type() == T_LONG || base()->type() == T_METADATA, 158 "wrong type for addresses"); 159 #else 160 assert(base()->is_single_cpu(), "wrong base operand"); 161 assert(index()->is_illegal() || index()->is_single_cpu(), "wrong index operand"); 162 assert(base()->type() == T_OBJECT || base()->type() == T_INT || base()->type() == T_METADATA, 163 "wrong type for addresses"); 164 #endif 165 } 166 #endif 167 168 169 //--------------------------------------------------- 170 171 char LIR_OprDesc::type_char(BasicType t) { 172 switch (t) { 173 case T_ARRAY: 174 t = T_OBJECT; 175 case T_BOOLEAN: 176 case T_CHAR: 177 case T_FLOAT: 178 case T_DOUBLE: 179 case T_BYTE: 180 case T_SHORT: 181 case T_INT: 182 case T_LONG: 183 case T_OBJECT: 184 case T_ADDRESS: 185 case T_VOID: 186 return ::type2char(t); 187 case T_METADATA: 188 return 'M'; 189 case T_ILLEGAL: 190 return '?'; 191 192 default: 193 ShouldNotReachHere(); 194 return '?'; 195 } 196 } 197 198 #ifndef PRODUCT 199 void LIR_OprDesc::validate_type() const { 200 201 #ifdef ASSERT 202 if (!is_pointer() && !is_illegal()) { 203 OprKind kindfield = kind_field(); // Factored out because of compiler bug, see 8002160 204 switch (as_BasicType(type_field())) { 205 case T_LONG: 206 assert((kindfield == cpu_register || kindfield == stack_value) && 207 size_field() == double_size, "must match"); 208 break; 209 case T_FLOAT: 210 // FP return values can be also in CPU registers on ARM and PPC32 (softfp ABI) 211 assert((kindfield == fpu_register || kindfield == stack_value 212 ARM_ONLY(|| kindfield == cpu_register) 213 PPC32_ONLY(|| kindfield == cpu_register) ) && 214 size_field() == single_size, "must match"); 215 break; 216 case T_DOUBLE: 217 // FP return values can be also in CPU registers on ARM and PPC32 (softfp ABI) 218 assert((kindfield == fpu_register || kindfield == stack_value 219 ARM_ONLY(|| kindfield == cpu_register) 220 PPC32_ONLY(|| kindfield == cpu_register) ) && 221 size_field() == double_size, "must match"); 222 break; 223 case T_BOOLEAN: 224 case T_CHAR: 225 case T_BYTE: 226 case T_SHORT: 227 case T_INT: 228 case T_ADDRESS: 229 case T_OBJECT: 230 case T_METADATA: 231 case T_ARRAY: 232 assert((kindfield == cpu_register || kindfield == stack_value) && 233 size_field() == single_size, "must match"); 234 break; 235 236 case T_ILLEGAL: 237 // XXX TKR also means unknown right now 238 // assert(is_illegal(), "must match"); 239 break; 240 241 default: 242 ShouldNotReachHere(); 243 } 244 } 245 #endif 246 247 } 248 #endif // PRODUCT 249 250 251 bool LIR_OprDesc::is_oop() const { 252 if (is_pointer()) { 253 return pointer()->is_oop_pointer(); 254 } else { 255 OprType t= type_field(); 256 assert(t != unknown_type, "not set"); 257 return t == object_type; 258 } 259 } 260 261 262 263 void LIR_Op2::verify() const { 264 #ifdef ASSERT 265 switch (code()) { 266 case lir_cmove: 267 case lir_xchg: 268 break; 269 270 default: 271 assert(!result_opr()->is_register() || !result_opr()->is_oop_register(), 272 "can't produce oops from arith"); 273 } 274 275 if (TwoOperandLIRForm) { 276 switch (code()) { 277 case lir_add: 278 case lir_sub: 279 case lir_mul: 280 case lir_mul_strictfp: 281 case lir_div: 282 case lir_div_strictfp: 283 case lir_rem: 284 case lir_logic_and: 285 case lir_logic_or: 286 case lir_logic_xor: 287 case lir_shl: 288 case lir_shr: 289 assert(in_opr1() == result_opr(), "opr1 and result must match"); 290 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid"); 291 break; 292 293 // special handling for lir_ushr because of write barriers 294 case lir_ushr: 295 assert(in_opr1() == result_opr() || in_opr2()->is_constant(), "opr1 and result must match or shift count is constant"); 296 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid"); 297 break; 298 299 } 300 } 301 #endif 302 } 303 304 305 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block) 306 : LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL) 307 , _cond(cond) 308 , _type(type) 309 , _label(block->label()) 310 , _block(block) 311 , _ublock(NULL) 312 , _stub(NULL) { 313 } 314 315 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, CodeStub* stub) : 316 LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL) 317 , _cond(cond) 318 , _type(type) 319 , _label(stub->entry()) 320 , _block(NULL) 321 , _ublock(NULL) 322 , _stub(stub) { 323 } 324 325 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block, BlockBegin* ublock) 326 : LIR_Op(lir_cond_float_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL) 327 , _cond(cond) 328 , _type(type) 329 , _label(block->label()) 330 , _block(block) 331 , _ublock(ublock) 332 , _stub(NULL) 333 { 334 } 335 336 void LIR_OpBranch::change_block(BlockBegin* b) { 337 assert(_block != NULL, "must have old block"); 338 assert(_block->label() == label(), "must be equal"); 339 340 _block = b; 341 _label = b->label(); 342 } 343 344 void LIR_OpBranch::change_ublock(BlockBegin* b) { 345 assert(_ublock != NULL, "must have old block"); 346 _ublock = b; 347 } 348 349 void LIR_OpBranch::negate_cond() { 350 switch (_cond) { 351 case lir_cond_equal: _cond = lir_cond_notEqual; break; 352 case lir_cond_notEqual: _cond = lir_cond_equal; break; 353 case lir_cond_less: _cond = lir_cond_greaterEqual; break; 354 case lir_cond_lessEqual: _cond = lir_cond_greater; break; 355 case lir_cond_greaterEqual: _cond = lir_cond_less; break; 356 case lir_cond_greater: _cond = lir_cond_lessEqual; break; 357 default: ShouldNotReachHere(); 358 } 359 } 360 361 362 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr result, LIR_Opr object, ciKlass* klass, 363 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, 364 bool fast_check, CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch, 365 CodeStub* stub) 366 367 : LIR_Op(code, result, NULL) 368 , _object(object) 369 , _array(LIR_OprFact::illegalOpr) 370 , _klass(klass) 371 , _tmp1(tmp1) 372 , _tmp2(tmp2) 373 , _tmp3(tmp3) 374 , _fast_check(fast_check) 375 , _stub(stub) 376 , _info_for_patch(info_for_patch) 377 , _info_for_exception(info_for_exception) 378 , _profiled_method(NULL) 379 , _profiled_bci(-1) 380 , _should_profile(false) 381 { 382 if (code == lir_checkcast) { 383 assert(info_for_exception != NULL, "checkcast throws exceptions"); 384 } else if (code == lir_instanceof) { 385 assert(info_for_exception == NULL, "instanceof throws no exceptions"); 386 } else { 387 ShouldNotReachHere(); 388 } 389 } 390 391 392 393 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, CodeEmitInfo* info_for_exception) 394 : LIR_Op(code, LIR_OprFact::illegalOpr, NULL) 395 , _object(object) 396 , _array(array) 397 , _klass(NULL) 398 , _tmp1(tmp1) 399 , _tmp2(tmp2) 400 , _tmp3(tmp3) 401 , _fast_check(false) 402 , _stub(NULL) 403 , _info_for_patch(NULL) 404 , _info_for_exception(info_for_exception) 405 , _profiled_method(NULL) 406 , _profiled_bci(-1) 407 , _should_profile(false) 408 { 409 if (code == lir_store_check) { 410 _stub = new ArrayStoreExceptionStub(object, info_for_exception); 411 assert(info_for_exception != NULL, "store_check throws exceptions"); 412 } else { 413 ShouldNotReachHere(); 414 } 415 } 416 417 418 LIR_OpArrayCopy::LIR_OpArrayCopy(LIR_Opr src, LIR_Opr src_pos, LIR_Opr dst, LIR_Opr dst_pos, LIR_Opr length, 419 LIR_Opr tmp, ciArrayKlass* expected_type, int flags, CodeEmitInfo* info) 420 : LIR_Op(lir_arraycopy, LIR_OprFact::illegalOpr, info) 421 , _tmp(tmp) 422 , _src(src) 423 , _src_pos(src_pos) 424 , _dst(dst) 425 , _dst_pos(dst_pos) 426 , _flags(flags) 427 , _expected_type(expected_type) 428 , _length(length) { 429 _stub = new ArrayCopyStub(this); 430 } 431 432 LIR_OpUpdateCRC32::LIR_OpUpdateCRC32(LIR_Opr crc, LIR_Opr val, LIR_Opr res) 433 : LIR_Op(lir_updatecrc32, res, NULL) 434 , _crc(crc) 435 , _val(val) { 436 } 437 438 //-------------------verify-------------------------- 439 440 void LIR_Op1::verify() const { 441 switch(code()) { 442 case lir_move: 443 assert(in_opr()->is_valid() && result_opr()->is_valid(), "must be"); 444 break; 445 case lir_null_check: 446 assert(in_opr()->is_register(), "must be"); 447 break; 448 case lir_return: 449 assert(in_opr()->is_register() || in_opr()->is_illegal(), "must be"); 450 break; 451 } 452 } 453 454 void LIR_OpRTCall::verify() const { 455 assert(strcmp(Runtime1::name_for_address(addr()), "<unknown function>") != 0, "unknown function"); 456 } 457 458 //-------------------visits-------------------------- 459 460 // complete rework of LIR instruction visitor. 461 // The virtual call for each instruction type is replaced by a big 462 // switch that adds the operands for each instruction 463 464 void LIR_OpVisitState::visit(LIR_Op* op) { 465 // copy information from the LIR_Op 466 reset(); 467 set_op(op); 468 469 switch (op->code()) { 470 471 // LIR_Op0 472 case lir_word_align: // result and info always invalid 473 case lir_backwardbranch_target: // result and info always invalid 474 case lir_build_frame: // result and info always invalid 475 case lir_fpop_raw: // result and info always invalid 476 case lir_24bit_FPU: // result and info always invalid 477 case lir_reset_FPU: // result and info always invalid 478 case lir_breakpoint: // result and info always invalid 479 case lir_membar: // result and info always invalid 480 case lir_membar_acquire: // result and info always invalid 481 case lir_membar_release: // result and info always invalid 482 case lir_membar_loadload: // result and info always invalid 483 case lir_membar_storestore: // result and info always invalid 484 case lir_membar_loadstore: // result and info always invalid 485 case lir_membar_storeload: // result and info always invalid 486 { 487 assert(op->as_Op0() != NULL, "must be"); 488 assert(op->_info == NULL, "info not used by this instruction"); 489 assert(op->_result->is_illegal(), "not used"); 490 break; 491 } 492 493 case lir_nop: // may have info, result always invalid 494 case lir_std_entry: // may have result, info always invalid 495 case lir_osr_entry: // may have result, info always invalid 496 case lir_get_thread: // may have result, info always invalid 497 { 498 assert(op->as_Op0() != NULL, "must be"); 499 if (op->_info != NULL) do_info(op->_info); 500 if (op->_result->is_valid()) do_output(op->_result); 501 break; 502 } 503 504 505 // LIR_OpLabel 506 case lir_label: // result and info always invalid 507 { 508 assert(op->as_OpLabel() != NULL, "must be"); 509 assert(op->_info == NULL, "info not used by this instruction"); 510 assert(op->_result->is_illegal(), "not used"); 511 break; 512 } 513 514 515 // LIR_Op1 516 case lir_fxch: // input always valid, result and info always invalid 517 case lir_fld: // input always valid, result and info always invalid 518 case lir_ffree: // input always valid, result and info always invalid 519 case lir_push: // input always valid, result and info always invalid 520 case lir_pop: // input always valid, result and info always invalid 521 case lir_return: // input always valid, result and info always invalid 522 case lir_leal: // input and result always valid, info always invalid 523 case lir_neg: // input and result always valid, info always invalid 524 case lir_monaddr: // input and result always valid, info always invalid 525 case lir_null_check: // input and info always valid, result always invalid 526 case lir_move: // input and result always valid, may have info 527 case lir_pack64: // input and result always valid 528 case lir_unpack64: // input and result always valid 529 { 530 assert(op->as_Op1() != NULL, "must be"); 531 LIR_Op1* op1 = (LIR_Op1*)op; 532 533 if (op1->_info) do_info(op1->_info); 534 if (op1->_opr->is_valid()) do_input(op1->_opr); 535 if (op1->_result->is_valid()) do_output(op1->_result); 536 537 break; 538 } 539 540 case lir_safepoint: 541 { 542 assert(op->as_Op1() != NULL, "must be"); 543 LIR_Op1* op1 = (LIR_Op1*)op; 544 545 assert(op1->_info != NULL, ""); do_info(op1->_info); 546 if (op1->_opr->is_valid()) do_temp(op1->_opr); // safepoints on SPARC need temporary register 547 assert(op1->_result->is_illegal(), "safepoint does not produce value"); 548 549 break; 550 } 551 552 // LIR_OpConvert; 553 case lir_convert: // input and result always valid, info always invalid 554 { 555 assert(op->as_OpConvert() != NULL, "must be"); 556 LIR_OpConvert* opConvert = (LIR_OpConvert*)op; 557 558 assert(opConvert->_info == NULL, "must be"); 559 if (opConvert->_opr->is_valid()) do_input(opConvert->_opr); 560 if (opConvert->_result->is_valid()) do_output(opConvert->_result); 561 #ifdef PPC32 562 if (opConvert->_tmp1->is_valid()) do_temp(opConvert->_tmp1); 563 if (opConvert->_tmp2->is_valid()) do_temp(opConvert->_tmp2); 564 #endif 565 do_stub(opConvert->_stub); 566 567 break; 568 } 569 570 // LIR_OpBranch; 571 case lir_branch: // may have info, input and result register always invalid 572 case lir_cond_float_branch: // may have info, input and result register always invalid 573 { 574 assert(op->as_OpBranch() != NULL, "must be"); 575 LIR_OpBranch* opBranch = (LIR_OpBranch*)op; 576 577 if (opBranch->_info != NULL) do_info(opBranch->_info); 578 assert(opBranch->_result->is_illegal(), "not used"); 579 if (opBranch->_stub != NULL) opBranch->stub()->visit(this); 580 581 break; 582 } 583 584 585 // LIR_OpAllocObj 586 case lir_alloc_object: 587 { 588 assert(op->as_OpAllocObj() != NULL, "must be"); 589 LIR_OpAllocObj* opAllocObj = (LIR_OpAllocObj*)op; 590 591 if (opAllocObj->_info) do_info(opAllocObj->_info); 592 if (opAllocObj->_opr->is_valid()) { do_input(opAllocObj->_opr); 593 do_temp(opAllocObj->_opr); 594 } 595 if (opAllocObj->_tmp1->is_valid()) do_temp(opAllocObj->_tmp1); 596 if (opAllocObj->_tmp2->is_valid()) do_temp(opAllocObj->_tmp2); 597 if (opAllocObj->_tmp3->is_valid()) do_temp(opAllocObj->_tmp3); 598 if (opAllocObj->_tmp4->is_valid()) do_temp(opAllocObj->_tmp4); 599 if (opAllocObj->_result->is_valid()) do_output(opAllocObj->_result); 600 do_stub(opAllocObj->_stub); 601 break; 602 } 603 604 605 // LIR_OpRoundFP; 606 case lir_roundfp: { 607 assert(op->as_OpRoundFP() != NULL, "must be"); 608 LIR_OpRoundFP* opRoundFP = (LIR_OpRoundFP*)op; 609 610 assert(op->_info == NULL, "info not used by this instruction"); 611 assert(opRoundFP->_tmp->is_illegal(), "not used"); 612 do_input(opRoundFP->_opr); 613 do_output(opRoundFP->_result); 614 615 break; 616 } 617 618 619 // LIR_Op2 620 case lir_cmp: 621 case lir_cmp_l2i: 622 case lir_ucmp_fd2i: 623 case lir_cmp_fd2i: 624 case lir_add: 625 case lir_sub: 626 case lir_mul: 627 case lir_div: 628 case lir_rem: 629 case lir_sqrt: 630 case lir_abs: 631 case lir_logic_and: 632 case lir_logic_or: 633 case lir_logic_xor: 634 case lir_shl: 635 case lir_shr: 636 case lir_ushr: 637 case lir_xadd: 638 case lir_xchg: 639 case lir_assert: 640 { 641 assert(op->as_Op2() != NULL, "must be"); 642 LIR_Op2* op2 = (LIR_Op2*)op; 643 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() && 644 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used"); 645 646 if (op2->_info) do_info(op2->_info); 647 if (op2->_opr1->is_valid()) do_input(op2->_opr1); 648 if (op2->_opr2->is_valid()) do_input(op2->_opr2); 649 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1); 650 if (op2->_result->is_valid()) do_output(op2->_result); 651 if (op->code() == lir_xchg || op->code() == lir_xadd) { 652 // on ARM and PPC, return value is loaded first so could 653 // destroy inputs. On other platforms that implement those 654 // (x86, sparc), the extra constrainsts are harmless. 655 if (op2->_opr1->is_valid()) do_temp(op2->_opr1); 656 if (op2->_opr2->is_valid()) do_temp(op2->_opr2); 657 } 658 659 break; 660 } 661 662 // special handling for cmove: right input operand must not be equal 663 // to the result operand, otherwise the backend fails 664 case lir_cmove: 665 { 666 assert(op->as_Op2() != NULL, "must be"); 667 LIR_Op2* op2 = (LIR_Op2*)op; 668 669 assert(op2->_info == NULL && op2->_tmp1->is_illegal() && op2->_tmp2->is_illegal() && 670 op2->_tmp3->is_illegal() && op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used"); 671 assert(op2->_opr1->is_valid() && op2->_opr2->is_valid() && op2->_result->is_valid(), "used"); 672 673 do_input(op2->_opr1); 674 do_input(op2->_opr2); 675 do_temp(op2->_opr2); 676 do_output(op2->_result); 677 678 break; 679 } 680 681 // vspecial handling for strict operations: register input operands 682 // as temp to guarantee that they do not overlap with other 683 // registers 684 case lir_mul_strictfp: 685 case lir_div_strictfp: 686 { 687 assert(op->as_Op2() != NULL, "must be"); 688 LIR_Op2* op2 = (LIR_Op2*)op; 689 690 assert(op2->_info == NULL, "not used"); 691 assert(op2->_opr1->is_valid(), "used"); 692 assert(op2->_opr2->is_valid(), "used"); 693 assert(op2->_result->is_valid(), "used"); 694 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() && 695 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used"); 696 697 do_input(op2->_opr1); do_temp(op2->_opr1); 698 do_input(op2->_opr2); do_temp(op2->_opr2); 699 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1); 700 do_output(op2->_result); 701 702 break; 703 } 704 705 case lir_throw: { 706 assert(op->as_Op2() != NULL, "must be"); 707 LIR_Op2* op2 = (LIR_Op2*)op; 708 709 if (op2->_info) do_info(op2->_info); 710 if (op2->_opr1->is_valid()) do_temp(op2->_opr1); 711 if (op2->_opr2->is_valid()) do_input(op2->_opr2); // exception object is input parameter 712 assert(op2->_result->is_illegal(), "no result"); 713 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() && 714 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used"); 715 716 break; 717 } 718 719 case lir_unwind: { 720 assert(op->as_Op1() != NULL, "must be"); 721 LIR_Op1* op1 = (LIR_Op1*)op; 722 723 assert(op1->_info == NULL, "no info"); 724 assert(op1->_opr->is_valid(), "exception oop"); do_input(op1->_opr); 725 assert(op1->_result->is_illegal(), "no result"); 726 727 break; 728 } 729 730 // LIR_Op3 731 case lir_idiv: 732 case lir_irem: { 733 assert(op->as_Op3() != NULL, "must be"); 734 LIR_Op3* op3= (LIR_Op3*)op; 735 736 if (op3->_info) do_info(op3->_info); 737 if (op3->_opr1->is_valid()) do_input(op3->_opr1); 738 739 // second operand is input and temp, so ensure that second operand 740 // and third operand get not the same register 741 if (op3->_opr2->is_valid()) do_input(op3->_opr2); 742 if (op3->_opr2->is_valid()) do_temp(op3->_opr2); 743 if (op3->_opr3->is_valid()) do_temp(op3->_opr3); 744 745 if (op3->_result->is_valid()) do_output(op3->_result); 746 747 break; 748 } 749 750 751 // LIR_OpJavaCall 752 case lir_static_call: 753 case lir_optvirtual_call: 754 case lir_icvirtual_call: 755 case lir_virtual_call: 756 case lir_dynamic_call: { 757 LIR_OpJavaCall* opJavaCall = op->as_OpJavaCall(); 758 assert(opJavaCall != NULL, "must be"); 759 760 if (opJavaCall->_receiver->is_valid()) do_input(opJavaCall->_receiver); 761 762 // only visit register parameters 763 int n = opJavaCall->_arguments->length(); 764 for (int i = opJavaCall->_receiver->is_valid() ? 1 : 0; i < n; i++) { 765 if (!opJavaCall->_arguments->at(i)->is_pointer()) { 766 do_input(*opJavaCall->_arguments->adr_at(i)); 767 } 768 } 769 770 if (opJavaCall->_info) do_info(opJavaCall->_info); 771 if (FrameMap::method_handle_invoke_SP_save_opr() != LIR_OprFact::illegalOpr && 772 opJavaCall->is_method_handle_invoke()) { 773 opJavaCall->_method_handle_invoke_SP_save_opr = FrameMap::method_handle_invoke_SP_save_opr(); 774 do_temp(opJavaCall->_method_handle_invoke_SP_save_opr); 775 } 776 do_call(); 777 if (opJavaCall->_result->is_valid()) do_output(opJavaCall->_result); 778 779 break; 780 } 781 782 783 // LIR_OpRTCall 784 case lir_rtcall: { 785 assert(op->as_OpRTCall() != NULL, "must be"); 786 LIR_OpRTCall* opRTCall = (LIR_OpRTCall*)op; 787 788 // only visit register parameters 789 int n = opRTCall->_arguments->length(); 790 for (int i = 0; i < n; i++) { 791 if (!opRTCall->_arguments->at(i)->is_pointer()) { 792 do_input(*opRTCall->_arguments->adr_at(i)); 793 } 794 } 795 if (opRTCall->_info) do_info(opRTCall->_info); 796 if (opRTCall->_tmp->is_valid()) do_temp(opRTCall->_tmp); 797 do_call(); 798 if (opRTCall->_result->is_valid()) do_output(opRTCall->_result); 799 800 break; 801 } 802 803 804 // LIR_OpArrayCopy 805 case lir_arraycopy: { 806 assert(op->as_OpArrayCopy() != NULL, "must be"); 807 LIR_OpArrayCopy* opArrayCopy = (LIR_OpArrayCopy*)op; 808 809 assert(opArrayCopy->_result->is_illegal(), "unused"); 810 assert(opArrayCopy->_src->is_valid(), "used"); do_input(opArrayCopy->_src); do_temp(opArrayCopy->_src); 811 assert(opArrayCopy->_src_pos->is_valid(), "used"); do_input(opArrayCopy->_src_pos); do_temp(opArrayCopy->_src_pos); 812 assert(opArrayCopy->_dst->is_valid(), "used"); do_input(opArrayCopy->_dst); do_temp(opArrayCopy->_dst); 813 assert(opArrayCopy->_dst_pos->is_valid(), "used"); do_input(opArrayCopy->_dst_pos); do_temp(opArrayCopy->_dst_pos); 814 assert(opArrayCopy->_length->is_valid(), "used"); do_input(opArrayCopy->_length); do_temp(opArrayCopy->_length); 815 assert(opArrayCopy->_tmp->is_valid(), "used"); do_temp(opArrayCopy->_tmp); 816 if (opArrayCopy->_info) do_info(opArrayCopy->_info); 817 818 // the implementation of arraycopy always has a call into the runtime 819 do_call(); 820 821 break; 822 } 823 824 825 // LIR_OpUpdateCRC32 826 case lir_updatecrc32: { 827 assert(op->as_OpUpdateCRC32() != NULL, "must be"); 828 LIR_OpUpdateCRC32* opUp = (LIR_OpUpdateCRC32*)op; 829 830 assert(opUp->_crc->is_valid(), "used"); do_input(opUp->_crc); do_temp(opUp->_crc); 831 assert(opUp->_val->is_valid(), "used"); do_input(opUp->_val); do_temp(opUp->_val); 832 assert(opUp->_result->is_valid(), "used"); do_output(opUp->_result); 833 assert(opUp->_info == NULL, "no info for LIR_OpUpdateCRC32"); 834 835 break; 836 } 837 838 839 // LIR_OpLock 840 case lir_lock: 841 case lir_unlock: { 842 assert(op->as_OpLock() != NULL, "must be"); 843 LIR_OpLock* opLock = (LIR_OpLock*)op; 844 845 if (opLock->_info) do_info(opLock->_info); 846 847 // TODO: check if these operands really have to be temp 848 // (or if input is sufficient). This may have influence on the oop map! 849 assert(opLock->_lock->is_valid(), "used"); do_temp(opLock->_lock); 850 assert(opLock->_hdr->is_valid(), "used"); do_temp(opLock->_hdr); 851 assert(opLock->_obj->is_valid(), "used"); do_temp(opLock->_obj); 852 853 if (opLock->_scratch->is_valid()) do_temp(opLock->_scratch); 854 assert(opLock->_result->is_illegal(), "unused"); 855 856 do_stub(opLock->_stub); 857 858 break; 859 } 860 861 862 // LIR_OpDelay 863 case lir_delay_slot: { 864 assert(op->as_OpDelay() != NULL, "must be"); 865 LIR_OpDelay* opDelay = (LIR_OpDelay*)op; 866 867 visit(opDelay->delay_op()); 868 break; 869 } 870 871 // LIR_OpTypeCheck 872 case lir_instanceof: 873 case lir_checkcast: 874 case lir_store_check: { 875 assert(op->as_OpTypeCheck() != NULL, "must be"); 876 LIR_OpTypeCheck* opTypeCheck = (LIR_OpTypeCheck*)op; 877 878 if (opTypeCheck->_info_for_exception) do_info(opTypeCheck->_info_for_exception); 879 if (opTypeCheck->_info_for_patch) do_info(opTypeCheck->_info_for_patch); 880 if (opTypeCheck->_object->is_valid()) do_input(opTypeCheck->_object); 881 if (op->code() == lir_store_check && opTypeCheck->_object->is_valid()) { 882 do_temp(opTypeCheck->_object); 883 } 884 if (opTypeCheck->_array->is_valid()) do_input(opTypeCheck->_array); 885 if (opTypeCheck->_tmp1->is_valid()) do_temp(opTypeCheck->_tmp1); 886 if (opTypeCheck->_tmp2->is_valid()) do_temp(opTypeCheck->_tmp2); 887 if (opTypeCheck->_tmp3->is_valid()) do_temp(opTypeCheck->_tmp3); 888 if (opTypeCheck->_result->is_valid()) do_output(opTypeCheck->_result); 889 do_stub(opTypeCheck->_stub); 890 break; 891 } 892 893 // LIR_OpCompareAndSwap 894 case lir_cas_long: 895 case lir_cas_obj: 896 case lir_cas_int: { 897 assert(op->as_OpCompareAndSwap() != NULL, "must be"); 898 LIR_OpCompareAndSwap* opCompareAndSwap = (LIR_OpCompareAndSwap*)op; 899 900 assert(opCompareAndSwap->_addr->is_valid(), "used"); 901 assert(opCompareAndSwap->_cmp_value->is_valid(), "used"); 902 assert(opCompareAndSwap->_new_value->is_valid(), "used"); 903 if (opCompareAndSwap->_info) do_info(opCompareAndSwap->_info); 904 do_input(opCompareAndSwap->_addr); 905 do_temp(opCompareAndSwap->_addr); 906 do_input(opCompareAndSwap->_cmp_value); 907 do_temp(opCompareAndSwap->_cmp_value); 908 do_input(opCompareAndSwap->_new_value); 909 do_temp(opCompareAndSwap->_new_value); 910 if (opCompareAndSwap->_tmp1->is_valid()) do_temp(opCompareAndSwap->_tmp1); 911 if (opCompareAndSwap->_tmp2->is_valid()) do_temp(opCompareAndSwap->_tmp2); 912 if (opCompareAndSwap->_result->is_valid()) do_output(opCompareAndSwap->_result); 913 914 break; 915 } 916 917 918 // LIR_OpAllocArray; 919 case lir_alloc_array: { 920 assert(op->as_OpAllocArray() != NULL, "must be"); 921 LIR_OpAllocArray* opAllocArray = (LIR_OpAllocArray*)op; 922 923 if (opAllocArray->_info) do_info(opAllocArray->_info); 924 if (opAllocArray->_klass->is_valid()) do_input(opAllocArray->_klass); do_temp(opAllocArray->_klass); 925 if (opAllocArray->_len->is_valid()) do_input(opAllocArray->_len); do_temp(opAllocArray->_len); 926 if (opAllocArray->_tmp1->is_valid()) do_temp(opAllocArray->_tmp1); 927 if (opAllocArray->_tmp2->is_valid()) do_temp(opAllocArray->_tmp2); 928 if (opAllocArray->_tmp3->is_valid()) do_temp(opAllocArray->_tmp3); 929 if (opAllocArray->_tmp4->is_valid()) do_temp(opAllocArray->_tmp4); 930 if (opAllocArray->_result->is_valid()) do_output(opAllocArray->_result); 931 do_stub(opAllocArray->_stub); 932 break; 933 } 934 935 // LIR_OpProfileCall: 936 case lir_profile_call: { 937 assert(op->as_OpProfileCall() != NULL, "must be"); 938 LIR_OpProfileCall* opProfileCall = (LIR_OpProfileCall*)op; 939 940 if (opProfileCall->_recv->is_valid()) do_temp(opProfileCall->_recv); 941 assert(opProfileCall->_mdo->is_valid(), "used"); do_temp(opProfileCall->_mdo); 942 assert(opProfileCall->_tmp1->is_valid(), "used"); do_temp(opProfileCall->_tmp1); 943 break; 944 } 945 946 // LIR_OpProfileType: 947 case lir_profile_type: { 948 assert(op->as_OpProfileType() != NULL, "must be"); 949 LIR_OpProfileType* opProfileType = (LIR_OpProfileType*)op; 950 951 do_input(opProfileType->_mdp); do_temp(opProfileType->_mdp); 952 do_input(opProfileType->_obj); 953 do_temp(opProfileType->_tmp); 954 break; 955 } 956 default: 957 ShouldNotReachHere(); 958 } 959 } 960 961 962 void LIR_OpVisitState::do_stub(CodeStub* stub) { 963 if (stub != NULL) { 964 stub->visit(this); 965 } 966 } 967 968 XHandlers* LIR_OpVisitState::all_xhandler() { 969 XHandlers* result = NULL; 970 971 int i; 972 for (i = 0; i < info_count(); i++) { 973 if (info_at(i)->exception_handlers() != NULL) { 974 result = info_at(i)->exception_handlers(); 975 break; 976 } 977 } 978 979 #ifdef ASSERT 980 for (i = 0; i < info_count(); i++) { 981 assert(info_at(i)->exception_handlers() == NULL || 982 info_at(i)->exception_handlers() == result, 983 "only one xhandler list allowed per LIR-operation"); 984 } 985 #endif 986 987 if (result != NULL) { 988 return result; 989 } else { 990 return new XHandlers(); 991 } 992 993 return result; 994 } 995 996 997 #ifdef ASSERT 998 bool LIR_OpVisitState::no_operands(LIR_Op* op) { 999 visit(op); 1000 1001 return opr_count(inputMode) == 0 && 1002 opr_count(outputMode) == 0 && 1003 opr_count(tempMode) == 0 && 1004 info_count() == 0 && 1005 !has_call() && 1006 !has_slow_case(); 1007 } 1008 #endif 1009 1010 //--------------------------------------------------- 1011 1012 1013 void LIR_OpJavaCall::emit_code(LIR_Assembler* masm) { 1014 masm->emit_call(this); 1015 } 1016 1017 void LIR_OpRTCall::emit_code(LIR_Assembler* masm) { 1018 masm->emit_rtcall(this); 1019 } 1020 1021 void LIR_OpLabel::emit_code(LIR_Assembler* masm) { 1022 masm->emit_opLabel(this); 1023 } 1024 1025 void LIR_OpArrayCopy::emit_code(LIR_Assembler* masm) { 1026 masm->emit_arraycopy(this); 1027 masm->append_code_stub(stub()); 1028 } 1029 1030 void LIR_OpUpdateCRC32::emit_code(LIR_Assembler* masm) { 1031 masm->emit_updatecrc32(this); 1032 } 1033 1034 void LIR_Op0::emit_code(LIR_Assembler* masm) { 1035 masm->emit_op0(this); 1036 } 1037 1038 void LIR_Op1::emit_code(LIR_Assembler* masm) { 1039 masm->emit_op1(this); 1040 } 1041 1042 void LIR_OpAllocObj::emit_code(LIR_Assembler* masm) { 1043 masm->emit_alloc_obj(this); 1044 masm->append_code_stub(stub()); 1045 } 1046 1047 void LIR_OpBranch::emit_code(LIR_Assembler* masm) { 1048 masm->emit_opBranch(this); 1049 if (stub()) { 1050 masm->append_code_stub(stub()); 1051 } 1052 } 1053 1054 void LIR_OpConvert::emit_code(LIR_Assembler* masm) { 1055 masm->emit_opConvert(this); 1056 if (stub() != NULL) { 1057 masm->append_code_stub(stub()); 1058 } 1059 } 1060 1061 void LIR_Op2::emit_code(LIR_Assembler* masm) { 1062 masm->emit_op2(this); 1063 } 1064 1065 void LIR_OpAllocArray::emit_code(LIR_Assembler* masm) { 1066 masm->emit_alloc_array(this); 1067 masm->append_code_stub(stub()); 1068 } 1069 1070 void LIR_OpTypeCheck::emit_code(LIR_Assembler* masm) { 1071 masm->emit_opTypeCheck(this); 1072 if (stub()) { 1073 masm->append_code_stub(stub()); 1074 } 1075 } 1076 1077 void LIR_OpCompareAndSwap::emit_code(LIR_Assembler* masm) { 1078 masm->emit_compare_and_swap(this); 1079 } 1080 1081 void LIR_Op3::emit_code(LIR_Assembler* masm) { 1082 masm->emit_op3(this); 1083 } 1084 1085 void LIR_OpLock::emit_code(LIR_Assembler* masm) { 1086 masm->emit_lock(this); 1087 if (stub()) { 1088 masm->append_code_stub(stub()); 1089 } 1090 } 1091 1092 #ifdef ASSERT 1093 void LIR_OpAssert::emit_code(LIR_Assembler* masm) { 1094 masm->emit_assert(this); 1095 } 1096 #endif 1097 1098 void LIR_OpDelay::emit_code(LIR_Assembler* masm) { 1099 masm->emit_delay(this); 1100 } 1101 1102 void LIR_OpProfileCall::emit_code(LIR_Assembler* masm) { 1103 masm->emit_profile_call(this); 1104 } 1105 1106 void LIR_OpProfileType::emit_code(LIR_Assembler* masm) { 1107 masm->emit_profile_type(this); 1108 } 1109 1110 // LIR_List 1111 LIR_List::LIR_List(Compilation* compilation, BlockBegin* block) 1112 : _operations(8) 1113 , _compilation(compilation) 1114 #ifndef PRODUCT 1115 , _block(block) 1116 #endif 1117 #ifdef ASSERT 1118 , _file(NULL) 1119 , _line(0) 1120 #endif 1121 { } 1122 1123 1124 #ifdef ASSERT 1125 void LIR_List::set_file_and_line(const char * file, int line) { 1126 const char * f = strrchr(file, '/'); 1127 if (f == NULL) f = strrchr(file, '\\'); 1128 if (f == NULL) { 1129 f = file; 1130 } else { 1131 f++; 1132 } 1133 _file = f; 1134 _line = line; 1135 } 1136 #endif 1137 1138 1139 void LIR_List::append(LIR_InsertionBuffer* buffer) { 1140 assert(this == buffer->lir_list(), "wrong lir list"); 1141 const int n = _operations.length(); 1142 1143 if (buffer->number_of_ops() > 0) { 1144 // increase size of instructions list 1145 _operations.at_grow(n + buffer->number_of_ops() - 1, NULL); 1146 // insert ops from buffer into instructions list 1147 int op_index = buffer->number_of_ops() - 1; 1148 int ip_index = buffer->number_of_insertion_points() - 1; 1149 int from_index = n - 1; 1150 int to_index = _operations.length() - 1; 1151 for (; ip_index >= 0; ip_index --) { 1152 int index = buffer->index_at(ip_index); 1153 // make room after insertion point 1154 while (index < from_index) { 1155 _operations.at_put(to_index --, _operations.at(from_index --)); 1156 } 1157 // insert ops from buffer 1158 for (int i = buffer->count_at(ip_index); i > 0; i --) { 1159 _operations.at_put(to_index --, buffer->op_at(op_index --)); 1160 } 1161 } 1162 } 1163 1164 buffer->finish(); 1165 } 1166 1167 1168 void LIR_List::oop2reg_patch(jobject o, LIR_Opr reg, CodeEmitInfo* info) { 1169 assert(reg->type() == T_OBJECT, "bad reg"); 1170 append(new LIR_Op1(lir_move, LIR_OprFact::oopConst(o), reg, T_OBJECT, lir_patch_normal, info)); 1171 } 1172 1173 void LIR_List::klass2reg_patch(Metadata* o, LIR_Opr reg, CodeEmitInfo* info) { 1174 assert(reg->type() == T_METADATA, "bad reg"); 1175 append(new LIR_Op1(lir_move, LIR_OprFact::metadataConst(o), reg, T_METADATA, lir_patch_normal, info)); 1176 } 1177 1178 void LIR_List::load(LIR_Address* addr, LIR_Opr src, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1179 append(new LIR_Op1( 1180 lir_move, 1181 LIR_OprFact::address(addr), 1182 src, 1183 addr->type(), 1184 patch_code, 1185 info)); 1186 } 1187 1188 1189 void LIR_List::volatile_load_mem_reg(LIR_Address* address, LIR_Opr dst, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1190 append(new LIR_Op1( 1191 lir_move, 1192 LIR_OprFact::address(address), 1193 dst, 1194 address->type(), 1195 patch_code, 1196 info, lir_move_volatile)); 1197 } 1198 1199 void LIR_List::volatile_load_unsafe_reg(LIR_Opr base, LIR_Opr offset, LIR_Opr dst, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1200 append(new LIR_Op1( 1201 lir_move, 1202 LIR_OprFact::address(new LIR_Address(base, offset, type)), 1203 dst, 1204 type, 1205 patch_code, 1206 info, lir_move_volatile)); 1207 } 1208 1209 1210 void LIR_List::store_mem_int(jint v, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1211 append(new LIR_Op1( 1212 lir_move, 1213 LIR_OprFact::intConst(v), 1214 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)), 1215 type, 1216 patch_code, 1217 info)); 1218 } 1219 1220 1221 void LIR_List::store_mem_oop(jobject o, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1222 append(new LIR_Op1( 1223 lir_move, 1224 LIR_OprFact::oopConst(o), 1225 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)), 1226 type, 1227 patch_code, 1228 info)); 1229 } 1230 1231 1232 void LIR_List::store(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1233 append(new LIR_Op1( 1234 lir_move, 1235 src, 1236 LIR_OprFact::address(addr), 1237 addr->type(), 1238 patch_code, 1239 info)); 1240 } 1241 1242 1243 void LIR_List::volatile_store_mem_reg(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1244 append(new LIR_Op1( 1245 lir_move, 1246 src, 1247 LIR_OprFact::address(addr), 1248 addr->type(), 1249 patch_code, 1250 info, 1251 lir_move_volatile)); 1252 } 1253 1254 void LIR_List::volatile_store_unsafe_reg(LIR_Opr src, LIR_Opr base, LIR_Opr offset, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1255 append(new LIR_Op1( 1256 lir_move, 1257 src, 1258 LIR_OprFact::address(new LIR_Address(base, offset, type)), 1259 type, 1260 patch_code, 1261 info, lir_move_volatile)); 1262 } 1263 1264 1265 void LIR_List::idiv(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) { 1266 append(new LIR_Op3( 1267 lir_idiv, 1268 left, 1269 right, 1270 tmp, 1271 res, 1272 info)); 1273 } 1274 1275 1276 void LIR_List::idiv(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) { 1277 append(new LIR_Op3( 1278 lir_idiv, 1279 left, 1280 LIR_OprFact::intConst(right), 1281 tmp, 1282 res, 1283 info)); 1284 } 1285 1286 1287 void LIR_List::irem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) { 1288 append(new LIR_Op3( 1289 lir_irem, 1290 left, 1291 right, 1292 tmp, 1293 res, 1294 info)); 1295 } 1296 1297 1298 void LIR_List::irem(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) { 1299 append(new LIR_Op3( 1300 lir_irem, 1301 left, 1302 LIR_OprFact::intConst(right), 1303 tmp, 1304 res, 1305 info)); 1306 } 1307 1308 1309 void LIR_List::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) { 1310 append(new LIR_Op2( 1311 lir_cmp, 1312 condition, 1313 LIR_OprFact::address(new LIR_Address(base, disp, T_INT)), 1314 LIR_OprFact::intConst(c), 1315 info)); 1316 } 1317 1318 1319 void LIR_List::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Address* addr, CodeEmitInfo* info) { 1320 append(new LIR_Op2( 1321 lir_cmp, 1322 condition, 1323 reg, 1324 LIR_OprFact::address(addr), 1325 info)); 1326 } 1327 1328 void LIR_List::allocate_object(LIR_Opr dst, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4, 1329 int header_size, int object_size, LIR_Opr klass, bool init_check, CodeStub* stub) { 1330 append(new LIR_OpAllocObj( 1331 klass, 1332 dst, 1333 t1, 1334 t2, 1335 t3, 1336 t4, 1337 header_size, 1338 object_size, 1339 init_check, 1340 stub)); 1341 } 1342 1343 void LIR_List::allocate_array(LIR_Opr dst, LIR_Opr len, LIR_Opr t1,LIR_Opr t2, LIR_Opr t3,LIR_Opr t4, BasicType type, LIR_Opr klass, CodeStub* stub) { 1344 append(new LIR_OpAllocArray( 1345 klass, 1346 len, 1347 dst, 1348 t1, 1349 t2, 1350 t3, 1351 t4, 1352 type, 1353 stub)); 1354 } 1355 1356 void LIR_List::shift_left(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) { 1357 append(new LIR_Op2( 1358 lir_shl, 1359 value, 1360 count, 1361 dst, 1362 tmp)); 1363 } 1364 1365 void LIR_List::shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) { 1366 append(new LIR_Op2( 1367 lir_shr, 1368 value, 1369 count, 1370 dst, 1371 tmp)); 1372 } 1373 1374 1375 void LIR_List::unsigned_shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) { 1376 append(new LIR_Op2( 1377 lir_ushr, 1378 value, 1379 count, 1380 dst, 1381 tmp)); 1382 } 1383 1384 void LIR_List::fcmp2int(LIR_Opr left, LIR_Opr right, LIR_Opr dst, bool is_unordered_less) { 1385 append(new LIR_Op2(is_unordered_less ? lir_ucmp_fd2i : lir_cmp_fd2i, 1386 left, 1387 right, 1388 dst)); 1389 } 1390 1391 void LIR_List::lock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub, CodeEmitInfo* info) { 1392 append(new LIR_OpLock( 1393 lir_lock, 1394 hdr, 1395 obj, 1396 lock, 1397 scratch, 1398 stub, 1399 info)); 1400 } 1401 1402 void LIR_List::unlock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub) { 1403 append(new LIR_OpLock( 1404 lir_unlock, 1405 hdr, 1406 obj, 1407 lock, 1408 scratch, 1409 stub, 1410 NULL)); 1411 } 1412 1413 1414 void check_LIR() { 1415 // cannot do the proper checking as PRODUCT and other modes return different results 1416 // guarantee(sizeof(LIR_OprDesc) == wordSize, "may not have a v-table"); 1417 } 1418 1419 1420 1421 void LIR_List::checkcast (LIR_Opr result, LIR_Opr object, ciKlass* klass, 1422 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check, 1423 CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch, CodeStub* stub, 1424 ciMethod* profiled_method, int profiled_bci) { 1425 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_checkcast, result, object, klass, 1426 tmp1, tmp2, tmp3, fast_check, info_for_exception, info_for_patch, stub); 1427 if (profiled_method != NULL) { 1428 c->set_profiled_method(profiled_method); 1429 c->set_profiled_bci(profiled_bci); 1430 c->set_should_profile(true); 1431 } 1432 append(c); 1433 } 1434 1435 void LIR_List::instanceof(LIR_Opr result, LIR_Opr object, ciKlass* klass, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check, CodeEmitInfo* info_for_patch, ciMethod* profiled_method, int profiled_bci) { 1436 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_instanceof, result, object, klass, tmp1, tmp2, tmp3, fast_check, NULL, info_for_patch, NULL); 1437 if (profiled_method != NULL) { 1438 c->set_profiled_method(profiled_method); 1439 c->set_profiled_bci(profiled_bci); 1440 c->set_should_profile(true); 1441 } 1442 append(c); 1443 } 1444 1445 1446 void LIR_List::store_check(LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, 1447 CodeEmitInfo* info_for_exception, ciMethod* profiled_method, int profiled_bci) { 1448 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_store_check, object, array, tmp1, tmp2, tmp3, info_for_exception); 1449 if (profiled_method != NULL) { 1450 c->set_profiled_method(profiled_method); 1451 c->set_profiled_bci(profiled_bci); 1452 c->set_should_profile(true); 1453 } 1454 append(c); 1455 } 1456 1457 1458 void LIR_List::cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, 1459 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) { 1460 append(new LIR_OpCompareAndSwap(lir_cas_long, addr, cmp_value, new_value, t1, t2, result)); 1461 } 1462 1463 void LIR_List::cas_obj(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, 1464 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) { 1465 append(new LIR_OpCompareAndSwap(lir_cas_obj, addr, cmp_value, new_value, t1, t2, result)); 1466 } 1467 1468 void LIR_List::cas_int(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, 1469 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) { 1470 append(new LIR_OpCompareAndSwap(lir_cas_int, addr, cmp_value, new_value, t1, t2, result)); 1471 } 1472 1473 1474 #ifdef PRODUCT 1475 1476 void print_LIR(BlockList* blocks) { 1477 } 1478 1479 #else 1480 // LIR_OprDesc 1481 void LIR_OprDesc::print() const { 1482 print(tty); 1483 } 1484 1485 void LIR_OprDesc::print(outputStream* out) const { 1486 if (is_illegal()) { 1487 return; 1488 } 1489 1490 out->print("["); 1491 if (is_pointer()) { 1492 pointer()->print_value_on(out); 1493 } else if (is_single_stack()) { 1494 out->print("stack:%d", single_stack_ix()); 1495 } else if (is_double_stack()) { 1496 out->print("dbl_stack:%d",double_stack_ix()); 1497 } else if (is_virtual()) { 1498 out->print("R%d", vreg_number()); 1499 } else if (is_single_cpu()) { 1500 out->print("%s", as_register()->name()); 1501 } else if (is_double_cpu()) { 1502 out->print("%s", as_register_hi()->name()); 1503 out->print("%s", as_register_lo()->name()); 1504 #if defined(X86) 1505 } else if (is_single_xmm()) { 1506 out->print("%s", as_xmm_float_reg()->name()); 1507 } else if (is_double_xmm()) { 1508 out->print("%s", as_xmm_double_reg()->name()); 1509 } else if (is_single_fpu()) { 1510 out->print("fpu%d", fpu_regnr()); 1511 } else if (is_double_fpu()) { 1512 out->print("fpu%d", fpu_regnrLo()); 1513 #elif defined(AARCH64) 1514 } else if (is_single_fpu()) { 1515 out->print("fpu%d", fpu_regnr()); 1516 } else if (is_double_fpu()) { 1517 out->print("fpu%d", fpu_regnrLo()); 1518 #elif defined(ARM) 1519 } else if (is_single_fpu()) { 1520 out->print("s%d", fpu_regnr()); 1521 } else if (is_double_fpu()) { 1522 out->print("d%d", fpu_regnrLo() >> 1); 1523 #else 1524 } else if (is_single_fpu()) { 1525 out->print("%s", as_float_reg()->name()); 1526 } else if (is_double_fpu()) { 1527 out->print("%s", as_double_reg()->name()); 1528 #endif 1529 1530 } else if (is_illegal()) { 1531 out->print("-"); 1532 } else { 1533 out->print("Unknown Operand"); 1534 } 1535 if (!is_illegal()) { 1536 out->print("|%c", type_char()); 1537 } 1538 if (is_register() && is_last_use()) { 1539 out->print("(last_use)"); 1540 } 1541 out->print("]"); 1542 } 1543 1544 1545 // LIR_Address 1546 void LIR_Const::print_value_on(outputStream* out) const { 1547 switch (type()) { 1548 case T_ADDRESS:out->print("address:%d",as_jint()); break; 1549 case T_INT: out->print("int:%d", as_jint()); break; 1550 case T_LONG: out->print("lng:" JLONG_FORMAT, as_jlong()); break; 1551 case T_FLOAT: out->print("flt:%f", as_jfloat()); break; 1552 case T_DOUBLE: out->print("dbl:%f", as_jdouble()); break; 1553 case T_OBJECT: out->print("obj:" INTPTR_FORMAT, p2i(as_jobject())); break; 1554 case T_METADATA: out->print("metadata:" INTPTR_FORMAT, p2i(as_metadata()));break; 1555 default: out->print("%3d:0x" UINT64_FORMAT_X, type(), (uint64_t)as_jlong()); break; 1556 } 1557 } 1558 1559 // LIR_Address 1560 void LIR_Address::print_value_on(outputStream* out) const { 1561 out->print("Base:"); _base->print(out); 1562 if (!_index->is_illegal()) { 1563 out->print(" Index:"); _index->print(out); 1564 switch (scale()) { 1565 case times_1: break; 1566 case times_2: out->print(" * 2"); break; 1567 case times_4: out->print(" * 4"); break; 1568 case times_8: out->print(" * 8"); break; 1569 } 1570 } 1571 out->print(" Disp: " INTX_FORMAT, _disp); 1572 } 1573 1574 // debug output of block header without InstructionPrinter 1575 // (because phi functions are not necessary for LIR) 1576 static void print_block(BlockBegin* x) { 1577 // print block id 1578 BlockEnd* end = x->end(); 1579 tty->print("B%d ", x->block_id()); 1580 1581 // print flags 1582 if (x->is_set(BlockBegin::std_entry_flag)) tty->print("std "); 1583 if (x->is_set(BlockBegin::osr_entry_flag)) tty->print("osr "); 1584 if (x->is_set(BlockBegin::exception_entry_flag)) tty->print("ex "); 1585 if (x->is_set(BlockBegin::subroutine_entry_flag)) tty->print("jsr "); 1586 if (x->is_set(BlockBegin::backward_branch_target_flag)) tty->print("bb "); 1587 if (x->is_set(BlockBegin::linear_scan_loop_header_flag)) tty->print("lh "); 1588 if (x->is_set(BlockBegin::linear_scan_loop_end_flag)) tty->print("le "); 1589 1590 // print block bci range 1591 tty->print("[%d, %d] ", x->bci(), (end == NULL ? -1 : end->printable_bci())); 1592 1593 // print predecessors and successors 1594 if (x->number_of_preds() > 0) { 1595 tty->print("preds: "); 1596 for (int i = 0; i < x->number_of_preds(); i ++) { 1597 tty->print("B%d ", x->pred_at(i)->block_id()); 1598 } 1599 } 1600 1601 if (x->number_of_sux() > 0) { 1602 tty->print("sux: "); 1603 for (int i = 0; i < x->number_of_sux(); i ++) { 1604 tty->print("B%d ", x->sux_at(i)->block_id()); 1605 } 1606 } 1607 1608 // print exception handlers 1609 if (x->number_of_exception_handlers() > 0) { 1610 tty->print("xhandler: "); 1611 for (int i = 0; i < x->number_of_exception_handlers(); i++) { 1612 tty->print("B%d ", x->exception_handler_at(i)->block_id()); 1613 } 1614 } 1615 1616 tty->cr(); 1617 } 1618 1619 void print_LIR(BlockList* blocks) { 1620 tty->print_cr("LIR:"); 1621 int i; 1622 for (i = 0; i < blocks->length(); i++) { 1623 BlockBegin* bb = blocks->at(i); 1624 print_block(bb); 1625 tty->print("__id_Instruction___________________________________________"); tty->cr(); 1626 bb->lir()->print_instructions(); 1627 } 1628 } 1629 1630 void LIR_List::print_instructions() { 1631 for (int i = 0; i < _operations.length(); i++) { 1632 _operations.at(i)->print(); tty->cr(); 1633 } 1634 tty->cr(); 1635 } 1636 1637 // LIR_Ops printing routines 1638 // LIR_Op 1639 void LIR_Op::print_on(outputStream* out) const { 1640 if (id() != -1 || PrintCFGToFile) { 1641 out->print("%4d ", id()); 1642 } else { 1643 out->print(" "); 1644 } 1645 out->print("%s ", name()); 1646 print_instr(out); 1647 if (info() != NULL) out->print(" [bci:%d]", info()->stack()->bci()); 1648 #ifdef ASSERT 1649 if (Verbose && _file != NULL) { 1650 out->print(" (%s:%d)", _file, _line); 1651 } 1652 #endif 1653 } 1654 1655 const char * LIR_Op::name() const { 1656 const char* s = NULL; 1657 switch(code()) { 1658 // LIR_Op0 1659 case lir_membar: s = "membar"; break; 1660 case lir_membar_acquire: s = "membar_acquire"; break; 1661 case lir_membar_release: s = "membar_release"; break; 1662 case lir_membar_loadload: s = "membar_loadload"; break; 1663 case lir_membar_storestore: s = "membar_storestore"; break; 1664 case lir_membar_loadstore: s = "membar_loadstore"; break; 1665 case lir_membar_storeload: s = "membar_storeload"; break; 1666 case lir_word_align: s = "word_align"; break; 1667 case lir_label: s = "label"; break; 1668 case lir_nop: s = "nop"; break; 1669 case lir_backwardbranch_target: s = "backbranch"; break; 1670 case lir_std_entry: s = "std_entry"; break; 1671 case lir_osr_entry: s = "osr_entry"; break; 1672 case lir_build_frame: s = "build_frm"; break; 1673 case lir_fpop_raw: s = "fpop_raw"; break; 1674 case lir_24bit_FPU: s = "24bit_FPU"; break; 1675 case lir_reset_FPU: s = "reset_FPU"; break; 1676 case lir_breakpoint: s = "breakpoint"; break; 1677 case lir_get_thread: s = "get_thread"; break; 1678 // LIR_Op1 1679 case lir_fxch: s = "fxch"; break; 1680 case lir_fld: s = "fld"; break; 1681 case lir_ffree: s = "ffree"; break; 1682 case lir_push: s = "push"; break; 1683 case lir_pop: s = "pop"; break; 1684 case lir_null_check: s = "null_check"; break; 1685 case lir_return: s = "return"; break; 1686 case lir_safepoint: s = "safepoint"; break; 1687 case lir_neg: s = "neg"; break; 1688 case lir_leal: s = "leal"; break; 1689 case lir_branch: s = "branch"; break; 1690 case lir_cond_float_branch: s = "flt_cond_br"; break; 1691 case lir_move: s = "move"; break; 1692 case lir_roundfp: s = "roundfp"; break; 1693 case lir_rtcall: s = "rtcall"; break; 1694 case lir_throw: s = "throw"; break; 1695 case lir_unwind: s = "unwind"; break; 1696 case lir_convert: s = "convert"; break; 1697 case lir_alloc_object: s = "alloc_obj"; break; 1698 case lir_monaddr: s = "mon_addr"; break; 1699 case lir_pack64: s = "pack64"; break; 1700 case lir_unpack64: s = "unpack64"; break; 1701 // LIR_Op2 1702 case lir_cmp: s = "cmp"; break; 1703 case lir_cmp_l2i: s = "cmp_l2i"; break; 1704 case lir_ucmp_fd2i: s = "ucomp_fd2i"; break; 1705 case lir_cmp_fd2i: s = "comp_fd2i"; break; 1706 case lir_cmove: s = "cmove"; break; 1707 case lir_add: s = "add"; break; 1708 case lir_sub: s = "sub"; break; 1709 case lir_mul: s = "mul"; break; 1710 case lir_mul_strictfp: s = "mul_strictfp"; break; 1711 case lir_div: s = "div"; break; 1712 case lir_div_strictfp: s = "div_strictfp"; break; 1713 case lir_rem: s = "rem"; break; 1714 case lir_abs: s = "abs"; break; 1715 case lir_sqrt: s = "sqrt"; break; 1716 case lir_logic_and: s = "logic_and"; break; 1717 case lir_logic_or: s = "logic_or"; break; 1718 case lir_logic_xor: s = "logic_xor"; break; 1719 case lir_shl: s = "shift_left"; break; 1720 case lir_shr: s = "shift_right"; break; 1721 case lir_ushr: s = "ushift_right"; break; 1722 case lir_alloc_array: s = "alloc_array"; break; 1723 case lir_xadd: s = "xadd"; break; 1724 case lir_xchg: s = "xchg"; break; 1725 // LIR_Op3 1726 case lir_idiv: s = "idiv"; break; 1727 case lir_irem: s = "irem"; break; 1728 // LIR_OpJavaCall 1729 case lir_static_call: s = "static"; break; 1730 case lir_optvirtual_call: s = "optvirtual"; break; 1731 case lir_icvirtual_call: s = "icvirtual"; break; 1732 case lir_virtual_call: s = "virtual"; break; 1733 case lir_dynamic_call: s = "dynamic"; break; 1734 // LIR_OpArrayCopy 1735 case lir_arraycopy: s = "arraycopy"; break; 1736 // LIR_OpUpdateCRC32 1737 case lir_updatecrc32: s = "updatecrc32"; break; 1738 // LIR_OpLock 1739 case lir_lock: s = "lock"; break; 1740 case lir_unlock: s = "unlock"; break; 1741 // LIR_OpDelay 1742 case lir_delay_slot: s = "delay"; break; 1743 // LIR_OpTypeCheck 1744 case lir_instanceof: s = "instanceof"; break; 1745 case lir_checkcast: s = "checkcast"; break; 1746 case lir_store_check: s = "store_check"; break; 1747 // LIR_OpCompareAndSwap 1748 case lir_cas_long: s = "cas_long"; break; 1749 case lir_cas_obj: s = "cas_obj"; break; 1750 case lir_cas_int: s = "cas_int"; break; 1751 // LIR_OpProfileCall 1752 case lir_profile_call: s = "profile_call"; break; 1753 // LIR_OpProfileType 1754 case lir_profile_type: s = "profile_type"; break; 1755 // LIR_OpAssert 1756 #ifdef ASSERT 1757 case lir_assert: s = "assert"; break; 1758 #endif 1759 case lir_none: ShouldNotReachHere();break; 1760 default: s = "illegal_op"; break; 1761 } 1762 return s; 1763 } 1764 1765 // LIR_OpJavaCall 1766 void LIR_OpJavaCall::print_instr(outputStream* out) const { 1767 out->print("call: "); 1768 out->print("[addr: " INTPTR_FORMAT "]", p2i(address())); 1769 if (receiver()->is_valid()) { 1770 out->print(" [recv: "); receiver()->print(out); out->print("]"); 1771 } 1772 if (result_opr()->is_valid()) { 1773 out->print(" [result: "); result_opr()->print(out); out->print("]"); 1774 } 1775 } 1776 1777 // LIR_OpLabel 1778 void LIR_OpLabel::print_instr(outputStream* out) const { 1779 out->print("[label:" INTPTR_FORMAT "]", p2i(_label)); 1780 } 1781 1782 // LIR_OpArrayCopy 1783 void LIR_OpArrayCopy::print_instr(outputStream* out) const { 1784 src()->print(out); out->print(" "); 1785 src_pos()->print(out); out->print(" "); 1786 dst()->print(out); out->print(" "); 1787 dst_pos()->print(out); out->print(" "); 1788 length()->print(out); out->print(" "); 1789 tmp()->print(out); out->print(" "); 1790 } 1791 1792 // LIR_OpUpdateCRC32 1793 void LIR_OpUpdateCRC32::print_instr(outputStream* out) const { 1794 crc()->print(out); out->print(" "); 1795 val()->print(out); out->print(" "); 1796 result_opr()->print(out); out->print(" "); 1797 } 1798 1799 // LIR_OpCompareAndSwap 1800 void LIR_OpCompareAndSwap::print_instr(outputStream* out) const { 1801 addr()->print(out); out->print(" "); 1802 cmp_value()->print(out); out->print(" "); 1803 new_value()->print(out); out->print(" "); 1804 tmp1()->print(out); out->print(" "); 1805 tmp2()->print(out); out->print(" "); 1806 1807 } 1808 1809 // LIR_Op0 1810 void LIR_Op0::print_instr(outputStream* out) const { 1811 result_opr()->print(out); 1812 } 1813 1814 // LIR_Op1 1815 const char * LIR_Op1::name() const { 1816 if (code() == lir_move) { 1817 switch (move_kind()) { 1818 case lir_move_normal: 1819 return "move"; 1820 case lir_move_unaligned: 1821 return "unaligned move"; 1822 case lir_move_volatile: 1823 return "volatile_move"; 1824 case lir_move_wide: 1825 return "wide_move"; 1826 default: 1827 ShouldNotReachHere(); 1828 return "illegal_op"; 1829 } 1830 } else { 1831 return LIR_Op::name(); 1832 } 1833 } 1834 1835 1836 void LIR_Op1::print_instr(outputStream* out) const { 1837 _opr->print(out); out->print(" "); 1838 result_opr()->print(out); out->print(" "); 1839 print_patch_code(out, patch_code()); 1840 } 1841 1842 1843 // LIR_Op1 1844 void LIR_OpRTCall::print_instr(outputStream* out) const { 1845 intx a = (intx)addr(); 1846 out->print("%s", Runtime1::name_for_address(addr())); 1847 out->print(" "); 1848 tmp()->print(out); 1849 } 1850 1851 void LIR_Op1::print_patch_code(outputStream* out, LIR_PatchCode code) { 1852 switch(code) { 1853 case lir_patch_none: break; 1854 case lir_patch_low: out->print("[patch_low]"); break; 1855 case lir_patch_high: out->print("[patch_high]"); break; 1856 case lir_patch_normal: out->print("[patch_normal]"); break; 1857 default: ShouldNotReachHere(); 1858 } 1859 } 1860 1861 // LIR_OpBranch 1862 void LIR_OpBranch::print_instr(outputStream* out) const { 1863 print_condition(out, cond()); out->print(" "); 1864 if (block() != NULL) { 1865 out->print("[B%d] ", block()->block_id()); 1866 } else if (stub() != NULL) { 1867 out->print("["); 1868 stub()->print_name(out); 1869 out->print(": " INTPTR_FORMAT "]", p2i(stub())); 1870 if (stub()->info() != NULL) out->print(" [bci:%d]", stub()->info()->stack()->bci()); 1871 } else { 1872 out->print("[label:" INTPTR_FORMAT "] ", p2i(label())); 1873 } 1874 if (ublock() != NULL) { 1875 out->print("unordered: [B%d] ", ublock()->block_id()); 1876 } 1877 } 1878 1879 void LIR_Op::print_condition(outputStream* out, LIR_Condition cond) { 1880 switch(cond) { 1881 case lir_cond_equal: out->print("[EQ]"); break; 1882 case lir_cond_notEqual: out->print("[NE]"); break; 1883 case lir_cond_less: out->print("[LT]"); break; 1884 case lir_cond_lessEqual: out->print("[LE]"); break; 1885 case lir_cond_greaterEqual: out->print("[GE]"); break; 1886 case lir_cond_greater: out->print("[GT]"); break; 1887 case lir_cond_belowEqual: out->print("[BE]"); break; 1888 case lir_cond_aboveEqual: out->print("[AE]"); break; 1889 case lir_cond_always: out->print("[AL]"); break; 1890 default: out->print("[%d]",cond); break; 1891 } 1892 } 1893 1894 // LIR_OpConvert 1895 void LIR_OpConvert::print_instr(outputStream* out) const { 1896 print_bytecode(out, bytecode()); 1897 in_opr()->print(out); out->print(" "); 1898 result_opr()->print(out); out->print(" "); 1899 #ifdef PPC32 1900 if(tmp1()->is_valid()) { 1901 tmp1()->print(out); out->print(" "); 1902 tmp2()->print(out); out->print(" "); 1903 } 1904 #endif 1905 } 1906 1907 void LIR_OpConvert::print_bytecode(outputStream* out, Bytecodes::Code code) { 1908 switch(code) { 1909 case Bytecodes::_d2f: out->print("[d2f] "); break; 1910 case Bytecodes::_d2i: out->print("[d2i] "); break; 1911 case Bytecodes::_d2l: out->print("[d2l] "); break; 1912 case Bytecodes::_f2d: out->print("[f2d] "); break; 1913 case Bytecodes::_f2i: out->print("[f2i] "); break; 1914 case Bytecodes::_f2l: out->print("[f2l] "); break; 1915 case Bytecodes::_i2b: out->print("[i2b] "); break; 1916 case Bytecodes::_i2c: out->print("[i2c] "); break; 1917 case Bytecodes::_i2d: out->print("[i2d] "); break; 1918 case Bytecodes::_i2f: out->print("[i2f] "); break; 1919 case Bytecodes::_i2l: out->print("[i2l] "); break; 1920 case Bytecodes::_i2s: out->print("[i2s] "); break; 1921 case Bytecodes::_l2i: out->print("[l2i] "); break; 1922 case Bytecodes::_l2f: out->print("[l2f] "); break; 1923 case Bytecodes::_l2d: out->print("[l2d] "); break; 1924 default: 1925 out->print("[?%d]",code); 1926 break; 1927 } 1928 } 1929 1930 void LIR_OpAllocObj::print_instr(outputStream* out) const { 1931 klass()->print(out); out->print(" "); 1932 obj()->print(out); out->print(" "); 1933 tmp1()->print(out); out->print(" "); 1934 tmp2()->print(out); out->print(" "); 1935 tmp3()->print(out); out->print(" "); 1936 tmp4()->print(out); out->print(" "); 1937 out->print("[hdr:%d]", header_size()); out->print(" "); 1938 out->print("[obj:%d]", object_size()); out->print(" "); 1939 out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry())); 1940 } 1941 1942 void LIR_OpRoundFP::print_instr(outputStream* out) const { 1943 _opr->print(out); out->print(" "); 1944 tmp()->print(out); out->print(" "); 1945 result_opr()->print(out); out->print(" "); 1946 } 1947 1948 // LIR_Op2 1949 void LIR_Op2::print_instr(outputStream* out) const { 1950 if (code() == lir_cmove || code() == lir_cmp) { 1951 print_condition(out, condition()); out->print(" "); 1952 } 1953 in_opr1()->print(out); out->print(" "); 1954 in_opr2()->print(out); out->print(" "); 1955 if (tmp1_opr()->is_valid()) { tmp1_opr()->print(out); out->print(" "); } 1956 if (tmp2_opr()->is_valid()) { tmp2_opr()->print(out); out->print(" "); } 1957 if (tmp3_opr()->is_valid()) { tmp3_opr()->print(out); out->print(" "); } 1958 if (tmp4_opr()->is_valid()) { tmp4_opr()->print(out); out->print(" "); } 1959 if (tmp5_opr()->is_valid()) { tmp5_opr()->print(out); out->print(" "); } 1960 result_opr()->print(out); 1961 } 1962 1963 void LIR_OpAllocArray::print_instr(outputStream* out) const { 1964 klass()->print(out); out->print(" "); 1965 len()->print(out); out->print(" "); 1966 obj()->print(out); out->print(" "); 1967 tmp1()->print(out); out->print(" "); 1968 tmp2()->print(out); out->print(" "); 1969 tmp3()->print(out); out->print(" "); 1970 tmp4()->print(out); out->print(" "); 1971 out->print("[type:0x%x]", type()); out->print(" "); 1972 out->print("[label:" INTPTR_FORMAT "]", p2i(stub()->entry())); 1973 } 1974 1975 1976 void LIR_OpTypeCheck::print_instr(outputStream* out) const { 1977 object()->print(out); out->print(" "); 1978 if (code() == lir_store_check) { 1979 array()->print(out); out->print(" "); 1980 } 1981 if (code() != lir_store_check) { 1982 klass()->print_name_on(out); out->print(" "); 1983 if (fast_check()) out->print("fast_check "); 1984 } 1985 tmp1()->print(out); out->print(" "); 1986 tmp2()->print(out); out->print(" "); 1987 tmp3()->print(out); out->print(" "); 1988 result_opr()->print(out); out->print(" "); 1989 if (info_for_exception() != NULL) out->print(" [bci:%d]", info_for_exception()->stack()->bci()); 1990 } 1991 1992 1993 // LIR_Op3 1994 void LIR_Op3::print_instr(outputStream* out) const { 1995 in_opr1()->print(out); out->print(" "); 1996 in_opr2()->print(out); out->print(" "); 1997 in_opr3()->print(out); out->print(" "); 1998 result_opr()->print(out); 1999 } 2000 2001 2002 void LIR_OpLock::print_instr(outputStream* out) const { 2003 hdr_opr()->print(out); out->print(" "); 2004 obj_opr()->print(out); out->print(" "); 2005 lock_opr()->print(out); out->print(" "); 2006 if (_scratch->is_valid()) { 2007 _scratch->print(out); out->print(" "); 2008 } 2009 out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry())); 2010 } 2011 2012 #ifdef ASSERT 2013 void LIR_OpAssert::print_instr(outputStream* out) const { 2014 print_condition(out, condition()); out->print(" "); 2015 in_opr1()->print(out); out->print(" "); 2016 in_opr2()->print(out); out->print(", \""); 2017 out->print("%s", msg()); out->print("\""); 2018 } 2019 #endif 2020 2021 2022 void LIR_OpDelay::print_instr(outputStream* out) const { 2023 _op->print_on(out); 2024 } 2025 2026 2027 // LIR_OpProfileCall 2028 void LIR_OpProfileCall::print_instr(outputStream* out) const { 2029 profiled_method()->name()->print_symbol_on(out); 2030 out->print("."); 2031 profiled_method()->holder()->name()->print_symbol_on(out); 2032 out->print(" @ %d ", profiled_bci()); 2033 mdo()->print(out); out->print(" "); 2034 recv()->print(out); out->print(" "); 2035 tmp1()->print(out); out->print(" "); 2036 } 2037 2038 // LIR_OpProfileType 2039 void LIR_OpProfileType::print_instr(outputStream* out) const { 2040 out->print("exact = "); 2041 if (exact_klass() == NULL) { 2042 out->print("unknown"); 2043 } else { 2044 exact_klass()->print_name_on(out); 2045 } 2046 out->print(" current = "); ciTypeEntries::print_ciklass(out, current_klass()); 2047 out->print(" "); 2048 mdp()->print(out); out->print(" "); 2049 obj()->print(out); out->print(" "); 2050 tmp()->print(out); out->print(" "); 2051 } 2052 2053 #endif // PRODUCT 2054 2055 // Implementation of LIR_InsertionBuffer 2056 2057 void LIR_InsertionBuffer::append(int index, LIR_Op* op) { 2058 assert(_index_and_count.length() % 2 == 0, "must have a count for each index"); 2059 2060 int i = number_of_insertion_points() - 1; 2061 if (i < 0 || index_at(i) < index) { 2062 append_new(index, 1); 2063 } else { 2064 assert(index_at(i) == index, "can append LIR_Ops in ascending order only"); 2065 assert(count_at(i) > 0, "check"); 2066 set_count_at(i, count_at(i) + 1); 2067 } 2068 _ops.push(op); 2069 2070 DEBUG_ONLY(verify()); 2071 } 2072 2073 #ifdef ASSERT 2074 void LIR_InsertionBuffer::verify() { 2075 int sum = 0; 2076 int prev_idx = -1; 2077 2078 for (int i = 0; i < number_of_insertion_points(); i++) { 2079 assert(prev_idx < index_at(i), "index must be ordered ascending"); 2080 sum += count_at(i); 2081 } 2082 assert(sum == number_of_ops(), "wrong total sum"); 2083 } 2084 #endif