1 /*
2 * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "gc/shared/cardTableModRefBS.hpp"
29 #include "gc/shared/collectedHeap.inline.hpp"
30 #include "interpreter/interpreter.hpp"
31 #include "memory/resourceArea.hpp"
32 #include "prims/methodHandles.hpp"
33 #include "runtime/biasedLocking.hpp"
34 #include "runtime/interfaceSupport.hpp"
35 #include "runtime/objectMonitor.hpp"
36 #include "runtime/os.hpp"
37 #include "runtime/sharedRuntime.hpp"
38 #include "runtime/stubRoutines.hpp"
39 #include "utilities/macros.hpp"
40 #if INCLUDE_ALL_GCS
41 #include "gc/g1/g1CollectedHeap.inline.hpp"
42 #include "gc/g1/g1SATBCardTableModRefBS.hpp"
43 #include "gc/g1/heapRegion.hpp"
44 #endif // INCLUDE_ALL_GCS
45
46 #ifdef PRODUCT
47 #define BLOCK_COMMENT(str) /* nothing */
48 #define STOP(error) stop(error)
49 #else
50 #define BLOCK_COMMENT(str) block_comment(str)
51 #define STOP(error) block_comment(error); stop(error)
52 #endif
53
54 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
55 // Implementation of AddressLiteral
56
57 // A 2-D table for managing compressed displacement(disp8) on EVEX enabled platforms.
58 unsigned char tuple_table[Assembler::EVEX_ETUP + 1][Assembler::AVX_512bit + 1] = {
59 // -----------------Table 4.5 -------------------- //
60 16, 32, 64, // EVEX_FV(0)
61 4, 4, 4, // EVEX_FV(1) - with Evex.b
62 16, 32, 64, // EVEX_FV(2) - with Evex.w
63 8, 8, 8, // EVEX_FV(3) - with Evex.w and Evex.b
64 8, 16, 32, // EVEX_HV(0)
65 4, 4, 4, // EVEX_HV(1) - with Evex.b
66 // -----------------Table 4.6 -------------------- //
67 16, 32, 64, // EVEX_FVM(0)
68 1, 1, 1, // EVEX_T1S(0)
69 2, 2, 2, // EVEX_T1S(1)
70 4, 4, 4, // EVEX_T1S(2)
71 8, 8, 8, // EVEX_T1S(3)
72 4, 4, 4, // EVEX_T1F(0)
73 8, 8, 8, // EVEX_T1F(1)
74 8, 8, 8, // EVEX_T2(0)
75 0, 16, 16, // EVEX_T2(1)
76 0, 16, 16, // EVEX_T4(0)
77 0, 0, 32, // EVEX_T4(1)
78 0, 0, 32, // EVEX_T8(0)
79 8, 16, 32, // EVEX_HVM(0)
80 4, 8, 16, // EVEX_QVM(0)
81 2, 4, 8, // EVEX_OVM(0)
82 16, 16, 16, // EVEX_M128(0)
83 8, 32, 64, // EVEX_DUP(0)
84 0, 0, 0 // EVEX_NTUP
85 };
86
87 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
88 _is_lval = false;
89 _target = target;
90 switch (rtype) {
91 case relocInfo::oop_type:
92 case relocInfo::metadata_type:
93 // Oops are a special case. Normally they would be their own section
94 // but in cases like icBuffer they are literals in the code stream that
95 // we don't have a section for. We use none so that we get a literal address
96 // which is always patchable.
97 break;
98 case relocInfo::external_word_type:
99 _rspec = external_word_Relocation::spec(target);
100 break;
101 case relocInfo::internal_word_type:
102 _rspec = internal_word_Relocation::spec(target);
103 break;
104 case relocInfo::opt_virtual_call_type:
105 _rspec = opt_virtual_call_Relocation::spec();
106 break;
107 case relocInfo::static_call_type:
108 _rspec = static_call_Relocation::spec();
109 break;
110 case relocInfo::runtime_call_type:
111 _rspec = runtime_call_Relocation::spec();
112 break;
113 case relocInfo::poll_type:
114 case relocInfo::poll_return_type:
115 _rspec = Relocation::spec_simple(rtype);
116 break;
117 case relocInfo::none:
118 break;
119 default:
120 ShouldNotReachHere();
121 break;
122 }
123 }
124
125 // Implementation of Address
126
127 #ifdef _LP64
128
129 Address Address::make_array(ArrayAddress adr) {
130 // Not implementable on 64bit machines
131 // Should have been handled higher up the call chain.
132 ShouldNotReachHere();
133 return Address();
134 }
135
136 // exceedingly dangerous constructor
137 Address::Address(int disp, address loc, relocInfo::relocType rtype) {
138 _base = noreg;
139 _index = noreg;
140 _scale = no_scale;
141 _disp = disp;
142 switch (rtype) {
143 case relocInfo::external_word_type:
144 _rspec = external_word_Relocation::spec(loc);
145 break;
146 case relocInfo::internal_word_type:
147 _rspec = internal_word_Relocation::spec(loc);
148 break;
149 case relocInfo::runtime_call_type:
150 // HMM
151 _rspec = runtime_call_Relocation::spec();
152 break;
153 case relocInfo::poll_type:
154 case relocInfo::poll_return_type:
155 _rspec = Relocation::spec_simple(rtype);
156 break;
157 case relocInfo::none:
158 break;
159 default:
160 ShouldNotReachHere();
161 }
162 }
163 #else // LP64
164
165 Address Address::make_array(ArrayAddress adr) {
166 AddressLiteral base = adr.base();
167 Address index = adr.index();
168 assert(index._disp == 0, "must not have disp"); // maybe it can?
169 Address array(index._base, index._index, index._scale, (intptr_t) base.target());
170 array._rspec = base._rspec;
171 return array;
172 }
173
174 // exceedingly dangerous constructor
175 Address::Address(address loc, RelocationHolder spec) {
176 _base = noreg;
177 _index = noreg;
178 _scale = no_scale;
179 _disp = (intptr_t) loc;
180 _rspec = spec;
181 }
182
183 #endif // _LP64
184
185
186
187 // Convert the raw encoding form into the form expected by the constructor for
188 // Address. An index of 4 (rsp) corresponds to having no index, so convert
189 // that to noreg for the Address constructor.
190 Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) {
191 RelocationHolder rspec;
192 if (disp_reloc != relocInfo::none) {
193 rspec = Relocation::spec_simple(disp_reloc);
194 }
195 bool valid_index = index != rsp->encoding();
196 if (valid_index) {
197 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));
198 madr._rspec = rspec;
199 return madr;
200 } else {
201 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));
202 madr._rspec = rspec;
203 return madr;
204 }
205 }
206
207 // Implementation of Assembler
208
209 int AbstractAssembler::code_fill_byte() {
210 return (u_char)'\xF4'; // hlt
211 }
212
213 // make this go away someday
214 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) {
215 if (rtype == relocInfo::none)
216 emit_int32(data);
217 else
218 emit_data(data, Relocation::spec_simple(rtype), format);
219 }
220
221 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) {
222 assert(imm_operand == 0, "default format must be immediate in this file");
223 assert(inst_mark() != NULL, "must be inside InstructionMark");
224 if (rspec.type() != relocInfo::none) {
225 #ifdef ASSERT
226 check_relocation(rspec, format);
227 #endif
228 // Do not use AbstractAssembler::relocate, which is not intended for
229 // embedded words. Instead, relocate to the enclosing instruction.
230
231 // hack. call32 is too wide for mask so use disp32
232 if (format == call32_operand)
233 code_section()->relocate(inst_mark(), rspec, disp32_operand);
234 else
235 code_section()->relocate(inst_mark(), rspec, format);
236 }
237 emit_int32(data);
238 }
239
240 static int encode(Register r) {
241 int enc = r->encoding();
242 if (enc >= 8) {
243 enc -= 8;
244 }
245 return enc;
246 }
247
248 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
249 assert(dst->has_byte_register(), "must have byte register");
250 assert(isByte(op1) && isByte(op2), "wrong opcode");
251 assert(isByte(imm8), "not a byte");
252 assert((op1 & 0x01) == 0, "should be 8bit operation");
253 emit_int8(op1);
254 emit_int8(op2 | encode(dst));
255 emit_int8(imm8);
256 }
257
258
259 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) {
260 assert(isByte(op1) && isByte(op2), "wrong opcode");
261 assert((op1 & 0x01) == 1, "should be 32bit operation");
262 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
263 if (is8bit(imm32)) {
264 emit_int8(op1 | 0x02); // set sign bit
265 emit_int8(op2 | encode(dst));
266 emit_int8(imm32 & 0xFF);
267 } else {
268 emit_int8(op1);
269 emit_int8(op2 | encode(dst));
270 emit_int32(imm32);
271 }
272 }
273
274 // Force generation of a 4 byte immediate value even if it fits into 8bit
275 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) {
276 assert(isByte(op1) && isByte(op2), "wrong opcode");
277 assert((op1 & 0x01) == 1, "should be 32bit operation");
278 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
279 emit_int8(op1);
280 emit_int8(op2 | encode(dst));
281 emit_int32(imm32);
282 }
283
284 // immediate-to-memory forms
285 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) {
286 assert((op1 & 0x01) == 1, "should be 32bit operation");
287 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
288 if (is8bit(imm32)) {
289 emit_int8(op1 | 0x02); // set sign bit
290 emit_operand(rm, adr, 1);
291 emit_int8(imm32 & 0xFF);
292 } else {
293 emit_int8(op1);
294 emit_operand(rm, adr, 4);
295 emit_int32(imm32);
296 }
297 }
298
299
300 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
301 assert(isByte(op1) && isByte(op2), "wrong opcode");
302 emit_int8(op1);
303 emit_int8(op2 | encode(dst) << 3 | encode(src));
304 }
305
306
307 bool Assembler::query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len,
308 int cur_tuple_type, int in_size_in_bits, int cur_encoding) {
309 int mod_idx = 0;
310 // We will test if the displacement fits the compressed format and if so
311 // apply the compression to the displacment iff the result is8bit.
312 if (VM_Version::supports_evex() && is_evex_inst) {
313 switch (cur_tuple_type) {
314 case EVEX_FV:
315 if ((cur_encoding & VEX_W) == VEX_W) {
316 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2;
317 } else {
318 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
319 }
320 break;
321
322 case EVEX_HV:
323 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
324 break;
325
326 case EVEX_FVM:
327 break;
328
329 case EVEX_T1S:
330 switch (in_size_in_bits) {
331 case EVEX_8bit:
332 break;
333
334 case EVEX_16bit:
335 mod_idx = 1;
336 break;
337
338 case EVEX_32bit:
339 mod_idx = 2;
340 break;
341
342 case EVEX_64bit:
343 mod_idx = 3;
344 break;
345 }
346 break;
347
348 case EVEX_T1F:
349 case EVEX_T2:
350 case EVEX_T4:
351 mod_idx = (in_size_in_bits == EVEX_64bit) ? 1 : 0;
352 break;
353
354 case EVEX_T8:
355 break;
356
357 case EVEX_HVM:
358 break;
359
360 case EVEX_QVM:
361 break;
362
363 case EVEX_OVM:
364 break;
365
366 case EVEX_M128:
367 break;
368
369 case EVEX_DUP:
370 break;
371
372 default:
373 assert(0, "no valid evex tuple_table entry");
374 break;
375 }
376
377 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
378 int disp_factor = tuple_table[cur_tuple_type + mod_idx][vector_len];
379 if ((disp % disp_factor) == 0) {
380 int new_disp = disp / disp_factor;
381 if ((-0x80 <= new_disp && new_disp < 0x80)) {
382 disp = new_disp;
383 }
384 } else {
385 return false;
386 }
387 }
388 }
389 return (-0x80 <= disp && disp < 0x80);
390 }
391
392
393 bool Assembler::emit_compressed_disp_byte(int &disp) {
394 int mod_idx = 0;
395 // We will test if the displacement fits the compressed format and if so
396 // apply the compression to the displacment iff the result is8bit.
397 if (VM_Version::supports_evex() && _attributes && _attributes->is_evex_instruction()) {
398 int evex_encoding = _attributes->get_evex_encoding();
399 int tuple_type = _attributes->get_tuple_type();
400 switch (tuple_type) {
401 case EVEX_FV:
402 if ((evex_encoding & VEX_W) == VEX_W) {
403 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2;
404 } else {
405 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
406 }
407 break;
408
409 case EVEX_HV:
410 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
411 break;
412
413 case EVEX_FVM:
414 break;
415
416 case EVEX_T1S:
417 switch (_attributes->get_input_size()) {
418 case EVEX_8bit:
419 break;
420
421 case EVEX_16bit:
422 mod_idx = 1;
423 break;
424
425 case EVEX_32bit:
426 mod_idx = 2;
427 break;
428
429 case EVEX_64bit:
430 mod_idx = 3;
431 break;
432 }
433 break;
434
435 case EVEX_T1F:
436 case EVEX_T2:
437 case EVEX_T4:
438 mod_idx = (_attributes->get_input_size() == EVEX_64bit) ? 1 : 0;
439 break;
440
441 case EVEX_T8:
442 break;
443
444 case EVEX_HVM:
445 break;
446
447 case EVEX_QVM:
448 break;
449
450 case EVEX_OVM:
451 break;
452
453 case EVEX_M128:
454 break;
455
456 case EVEX_DUP:
457 break;
458
459 default:
460 assert(0, "no valid evex tuple_table entry");
461 break;
462 }
463
464 int vector_len = _attributes->get_vector_len();
465 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
466 int disp_factor = tuple_table[tuple_type + mod_idx][vector_len];
467 if ((disp % disp_factor) == 0) {
468 int new_disp = disp / disp_factor;
469 if (is8bit(new_disp)) {
470 disp = new_disp;
471 }
472 } else {
473 return false;
474 }
475 }
476 }
477 return is8bit(disp);
478 }
479
480
481 void Assembler::emit_operand(Register reg, Register base, Register index,
482 Address::ScaleFactor scale, int disp,
483 RelocationHolder const& rspec,
484 int rip_relative_correction) {
485 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();
486
487 // Encode the registers as needed in the fields they are used in
488
489 int regenc = encode(reg) << 3;
490 int indexenc = index->is_valid() ? encode(index) << 3 : 0;
491 int baseenc = base->is_valid() ? encode(base) : 0;
492
493 if (base->is_valid()) {
494 if (index->is_valid()) {
495 assert(scale != Address::no_scale, "inconsistent address");
496 // [base + index*scale + disp]
497 if (disp == 0 && rtype == relocInfo::none &&
498 base != rbp LP64_ONLY(&& base != r13)) {
499 // [base + index*scale]
500 // [00 reg 100][ss index base]
501 assert(index != rsp, "illegal addressing mode");
502 emit_int8(0x04 | regenc);
503 emit_int8(scale << 6 | indexenc | baseenc);
504 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
505 // [base + index*scale + imm8]
506 // [01 reg 100][ss index base] imm8
507 assert(index != rsp, "illegal addressing mode");
508 emit_int8(0x44 | regenc);
509 emit_int8(scale << 6 | indexenc | baseenc);
510 emit_int8(disp & 0xFF);
511 } else {
512 // [base + index*scale + disp32]
513 // [10 reg 100][ss index base] disp32
514 assert(index != rsp, "illegal addressing mode");
515 emit_int8(0x84 | regenc);
516 emit_int8(scale << 6 | indexenc | baseenc);
517 emit_data(disp, rspec, disp32_operand);
518 }
519 } else if (base == rsp LP64_ONLY(|| base == r12)) {
520 // [rsp + disp]
521 if (disp == 0 && rtype == relocInfo::none) {
522 // [rsp]
523 // [00 reg 100][00 100 100]
524 emit_int8(0x04 | regenc);
525 emit_int8(0x24);
526 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
527 // [rsp + imm8]
528 // [01 reg 100][00 100 100] disp8
529 emit_int8(0x44 | regenc);
530 emit_int8(0x24);
531 emit_int8(disp & 0xFF);
532 } else {
533 // [rsp + imm32]
534 // [10 reg 100][00 100 100] disp32
535 emit_int8(0x84 | regenc);
536 emit_int8(0x24);
537 emit_data(disp, rspec, disp32_operand);
538 }
539 } else {
540 // [base + disp]
541 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode");
542 if (disp == 0 && rtype == relocInfo::none &&
543 base != rbp LP64_ONLY(&& base != r13)) {
544 // [base]
545 // [00 reg base]
546 emit_int8(0x00 | regenc | baseenc);
547 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
548 // [base + disp8]
549 // [01 reg base] disp8
550 emit_int8(0x40 | regenc | baseenc);
551 emit_int8(disp & 0xFF);
552 } else {
553 // [base + disp32]
554 // [10 reg base] disp32
555 emit_int8(0x80 | regenc | baseenc);
556 emit_data(disp, rspec, disp32_operand);
557 }
558 }
559 } else {
560 if (index->is_valid()) {
561 assert(scale != Address::no_scale, "inconsistent address");
562 // [index*scale + disp]
563 // [00 reg 100][ss index 101] disp32
564 assert(index != rsp, "illegal addressing mode");
565 emit_int8(0x04 | regenc);
566 emit_int8(scale << 6 | indexenc | 0x05);
567 emit_data(disp, rspec, disp32_operand);
568 } else if (rtype != relocInfo::none ) {
569 // [disp] (64bit) RIP-RELATIVE (32bit) abs
570 // [00 000 101] disp32
571
572 emit_int8(0x05 | regenc);
573 // Note that the RIP-rel. correction applies to the generated
574 // disp field, but _not_ to the target address in the rspec.
575
576 // disp was created by converting the target address minus the pc
577 // at the start of the instruction. That needs more correction here.
578 // intptr_t disp = target - next_ip;
579 assert(inst_mark() != NULL, "must be inside InstructionMark");
580 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction;
581 int64_t adjusted = disp;
582 // Do rip-rel adjustment for 64bit
583 LP64_ONLY(adjusted -= (next_ip - inst_mark()));
584 assert(is_simm32(adjusted),
585 "must be 32bit offset (RIP relative address)");
586 emit_data((int32_t) adjusted, rspec, disp32_operand);
587
588 } else {
589 // 32bit never did this, did everything as the rip-rel/disp code above
590 // [disp] ABSOLUTE
591 // [00 reg 100][00 100 101] disp32
592 emit_int8(0x04 | regenc);
593 emit_int8(0x25);
594 emit_data(disp, rspec, disp32_operand);
595 }
596 }
597 }
598
599 void Assembler::emit_operand(XMMRegister reg, Register base, Register index,
600 Address::ScaleFactor scale, int disp,
601 RelocationHolder const& rspec) {
602 if (UseAVX > 2) {
603 int xreg_enc = reg->encoding();
604 if (xreg_enc > 15) {
605 XMMRegister new_reg = as_XMMRegister(xreg_enc & 0xf);
606 emit_operand((Register)new_reg, base, index, scale, disp, rspec);
607 return;
608 }
609 }
610 emit_operand((Register)reg, base, index, scale, disp, rspec);
611 }
612
613 // Secret local extension to Assembler::WhichOperand:
614 #define end_pc_operand (_WhichOperand_limit)
615
616 address Assembler::locate_operand(address inst, WhichOperand which) {
617 // Decode the given instruction, and return the address of
618 // an embedded 32-bit operand word.
619
620 // If "which" is disp32_operand, selects the displacement portion
621 // of an effective address specifier.
622 // If "which" is imm64_operand, selects the trailing immediate constant.
623 // If "which" is call32_operand, selects the displacement of a call or jump.
624 // Caller is responsible for ensuring that there is such an operand,
625 // and that it is 32/64 bits wide.
626
627 // If "which" is end_pc_operand, find the end of the instruction.
628
629 address ip = inst;
630 bool is_64bit = false;
631
632 debug_only(bool has_disp32 = false);
633 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn
634
635 again_after_prefix:
636 switch (0xFF & *ip++) {
637
638 // These convenience macros generate groups of "case" labels for the switch.
639 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3
640 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \
641 case (x)+4: case (x)+5: case (x)+6: case (x)+7
642 #define REP16(x) REP8((x)+0): \
643 case REP8((x)+8)
644
645 case CS_segment:
646 case SS_segment:
647 case DS_segment:
648 case ES_segment:
649 case FS_segment:
650 case GS_segment:
651 // Seems dubious
652 LP64_ONLY(assert(false, "shouldn't have that prefix"));
653 assert(ip == inst+1, "only one prefix allowed");
654 goto again_after_prefix;
655
656 case 0x67:
657 case REX:
658 case REX_B:
659 case REX_X:
660 case REX_XB:
661 case REX_R:
662 case REX_RB:
663 case REX_RX:
664 case REX_RXB:
665 NOT_LP64(assert(false, "64bit prefixes"));
666 goto again_after_prefix;
667
668 case REX_W:
669 case REX_WB:
670 case REX_WX:
671 case REX_WXB:
672 case REX_WR:
673 case REX_WRB:
674 case REX_WRX:
675 case REX_WRXB:
676 NOT_LP64(assert(false, "64bit prefixes"));
677 is_64bit = true;
678 goto again_after_prefix;
679
680 case 0xFF: // pushq a; decl a; incl a; call a; jmp a
681 case 0x88: // movb a, r
682 case 0x89: // movl a, r
683 case 0x8A: // movb r, a
684 case 0x8B: // movl r, a
685 case 0x8F: // popl a
686 debug_only(has_disp32 = true);
687 break;
688
689 case 0x68: // pushq #32
690 if (which == end_pc_operand) {
691 return ip + 4;
692 }
693 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate");
694 return ip; // not produced by emit_operand
695
696 case 0x66: // movw ... (size prefix)
697 again_after_size_prefix2:
698 switch (0xFF & *ip++) {
699 case REX:
700 case REX_B:
701 case REX_X:
702 case REX_XB:
703 case REX_R:
704 case REX_RB:
705 case REX_RX:
706 case REX_RXB:
707 case REX_W:
708 case REX_WB:
709 case REX_WX:
710 case REX_WXB:
711 case REX_WR:
712 case REX_WRB:
713 case REX_WRX:
714 case REX_WRXB:
715 NOT_LP64(assert(false, "64bit prefix found"));
716 goto again_after_size_prefix2;
717 case 0x8B: // movw r, a
718 case 0x89: // movw a, r
719 debug_only(has_disp32 = true);
720 break;
721 case 0xC7: // movw a, #16
722 debug_only(has_disp32 = true);
723 tail_size = 2; // the imm16
724 break;
725 case 0x0F: // several SSE/SSE2 variants
726 ip--; // reparse the 0x0F
727 goto again_after_prefix;
728 default:
729 ShouldNotReachHere();
730 }
731 break;
732
733 case REP8(0xB8): // movl/q r, #32/#64(oop?)
734 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4);
735 // these asserts are somewhat nonsensical
736 #ifndef _LP64
737 assert(which == imm_operand || which == disp32_operand,
738 "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip));
739 #else
740 assert((which == call32_operand || which == imm_operand) && is_64bit ||
741 which == narrow_oop_operand && !is_64bit,
742 "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip));
743 #endif // _LP64
744 return ip;
745
746 case 0x69: // imul r, a, #32
747 case 0xC7: // movl a, #32(oop?)
748 tail_size = 4;
749 debug_only(has_disp32 = true); // has both kinds of operands!
750 break;
751
752 case 0x0F: // movx..., etc.
753 switch (0xFF & *ip++) {
754 case 0x3A: // pcmpestri
755 tail_size = 1;
756 case 0x38: // ptest, pmovzxbw
757 ip++; // skip opcode
758 debug_only(has_disp32 = true); // has both kinds of operands!
759 break;
760
761 case 0x70: // pshufd r, r/a, #8
762 debug_only(has_disp32 = true); // has both kinds of operands!
763 case 0x73: // psrldq r, #8
764 tail_size = 1;
765 break;
766
767 case 0x12: // movlps
768 case 0x28: // movaps
769 case 0x2E: // ucomiss
770 case 0x2F: // comiss
771 case 0x54: // andps
772 case 0x55: // andnps
773 case 0x56: // orps
774 case 0x57: // xorps
775 case 0x58: // addpd
776 case 0x59: // mulpd
777 case 0x6E: // movd
778 case 0x7E: // movd
779 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush
780 case 0xFE: // paddd
781 debug_only(has_disp32 = true);
782 break;
783
784 case 0xAD: // shrd r, a, %cl
785 case 0xAF: // imul r, a
786 case 0xBE: // movsbl r, a (movsxb)
787 case 0xBF: // movswl r, a (movsxw)
788 case 0xB6: // movzbl r, a (movzxb)
789 case 0xB7: // movzwl r, a (movzxw)
790 case REP16(0x40): // cmovl cc, r, a
791 case 0xB0: // cmpxchgb
792 case 0xB1: // cmpxchg
793 case 0xC1: // xaddl
794 case 0xC7: // cmpxchg8
795 case REP16(0x90): // setcc a
796 debug_only(has_disp32 = true);
797 // fall out of the switch to decode the address
798 break;
799
800 case 0xC4: // pinsrw r, a, #8
801 debug_only(has_disp32 = true);
802 case 0xC5: // pextrw r, r, #8
803 tail_size = 1; // the imm8
804 break;
805
806 case 0xAC: // shrd r, a, #8
807 debug_only(has_disp32 = true);
808 tail_size = 1; // the imm8
809 break;
810
811 case REP16(0x80): // jcc rdisp32
812 if (which == end_pc_operand) return ip + 4;
813 assert(which == call32_operand, "jcc has no disp32 or imm");
814 return ip;
815 default:
816 ShouldNotReachHere();
817 }
818 break;
819
820 case 0x81: // addl a, #32; addl r, #32
821 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
822 // on 32bit in the case of cmpl, the imm might be an oop
823 tail_size = 4;
824 debug_only(has_disp32 = true); // has both kinds of operands!
825 break;
826
827 case 0x83: // addl a, #8; addl r, #8
828 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
829 debug_only(has_disp32 = true); // has both kinds of operands!
830 tail_size = 1;
831 break;
832
833 case 0x9B:
834 switch (0xFF & *ip++) {
835 case 0xD9: // fnstcw a
836 debug_only(has_disp32 = true);
837 break;
838 default:
839 ShouldNotReachHere();
840 }
841 break;
842
843 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a
844 case REP4(0x10): // adc...
845 case REP4(0x20): // and...
846 case REP4(0x30): // xor...
847 case REP4(0x08): // or...
848 case REP4(0x18): // sbb...
849 case REP4(0x28): // sub...
850 case 0xF7: // mull a
851 case 0x8D: // lea r, a
852 case 0x87: // xchg r, a
853 case REP4(0x38): // cmp...
854 case 0x85: // test r, a
855 debug_only(has_disp32 = true); // has both kinds of operands!
856 break;
857
858 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8
859 case 0xC6: // movb a, #8
860 case 0x80: // cmpb a, #8
861 case 0x6B: // imul r, a, #8
862 debug_only(has_disp32 = true); // has both kinds of operands!
863 tail_size = 1; // the imm8
864 break;
865
866 case 0xC4: // VEX_3bytes
867 case 0xC5: // VEX_2bytes
868 assert((UseAVX > 0), "shouldn't have VEX prefix");
869 assert(ip == inst+1, "no prefixes allowed");
870 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions
871 // but they have prefix 0x0F and processed when 0x0F processed above.
872 //
873 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES
874 // instructions (these instructions are not supported in 64-bit mode).
875 // To distinguish them bits [7:6] are set in the VEX second byte since
876 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set
877 // those VEX bits REX and vvvv bits are inverted.
878 //
879 // Fortunately C2 doesn't generate these instructions so we don't need
880 // to check for them in product version.
881
882 // Check second byte
883 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions"));
884
885 int vex_opcode;
886 // First byte
887 if ((0xFF & *inst) == VEX_3bytes) {
888 vex_opcode = VEX_OPCODE_MASK & *ip;
889 ip++; // third byte
890 is_64bit = ((VEX_W & *ip) == VEX_W);
891 } else {
892 vex_opcode = VEX_OPCODE_0F;
893 }
894 ip++; // opcode
895 // To find the end of instruction (which == end_pc_operand).
896 switch (vex_opcode) {
897 case VEX_OPCODE_0F:
898 switch (0xFF & *ip) {
899 case 0x70: // pshufd r, r/a, #8
900 case 0x71: // ps[rl|ra|ll]w r, #8
901 case 0x72: // ps[rl|ra|ll]d r, #8
902 case 0x73: // ps[rl|ra|ll]q r, #8
903 case 0xC2: // cmp[ps|pd|ss|sd] r, r, r/a, #8
904 case 0xC4: // pinsrw r, r, r/a, #8
905 case 0xC5: // pextrw r/a, r, #8
906 case 0xC6: // shufp[s|d] r, r, r/a, #8
907 tail_size = 1; // the imm8
908 break;
909 }
910 break;
911 case VEX_OPCODE_0F_3A:
912 tail_size = 1;
913 break;
914 }
915 ip++; // skip opcode
916 debug_only(has_disp32 = true); // has both kinds of operands!
917 break;
918
919 case 0x62: // EVEX_4bytes
920 assert((UseAVX > 0), "shouldn't have EVEX prefix");
921 assert(ip == inst+1, "no prefixes allowed");
922 // no EVEX collisions, all instructions that have 0x62 opcodes
923 // have EVEX versions and are subopcodes of 0x66
924 ip++; // skip P0 and exmaine W in P1
925 is_64bit = ((VEX_W & *ip) == VEX_W);
926 ip++; // move to P2
927 ip++; // skip P2, move to opcode
928 // To find the end of instruction (which == end_pc_operand).
929 switch (0xFF & *ip) {
930 case 0x22: // pinsrd r, r/a, #8
931 case 0x61: // pcmpestri r, r/a, #8
932 case 0x70: // pshufd r, r/a, #8
933 case 0x73: // psrldq r, #8
934 tail_size = 1; // the imm8
935 break;
936 default:
937 break;
938 }
939 ip++; // skip opcode
940 debug_only(has_disp32 = true); // has both kinds of operands!
941 break;
942
943 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
944 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
945 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a
946 case 0xDD: // fld_d a; fst_d a; fstp_d a
947 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a
948 case 0xDF: // fild_d a; fistp_d a
949 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a
950 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a
951 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a
952 debug_only(has_disp32 = true);
953 break;
954
955 case 0xE8: // call rdisp32
956 case 0xE9: // jmp rdisp32
957 if (which == end_pc_operand) return ip + 4;
958 assert(which == call32_operand, "call has no disp32 or imm");
959 return ip;
960
961 case 0xF0: // Lock
962 assert(os::is_MP(), "only on MP");
963 goto again_after_prefix;
964
965 case 0xF3: // For SSE
966 case 0xF2: // For SSE2
967 switch (0xFF & *ip++) {
968 case REX:
969 case REX_B:
970 case REX_X:
971 case REX_XB:
972 case REX_R:
973 case REX_RB:
974 case REX_RX:
975 case REX_RXB:
976 case REX_W:
977 case REX_WB:
978 case REX_WX:
979 case REX_WXB:
980 case REX_WR:
981 case REX_WRB:
982 case REX_WRX:
983 case REX_WRXB:
984 NOT_LP64(assert(false, "found 64bit prefix"));
985 ip++;
986 default:
987 ip++;
988 }
989 debug_only(has_disp32 = true); // has both kinds of operands!
990 break;
991
992 default:
993 ShouldNotReachHere();
994
995 #undef REP8
996 #undef REP16
997 }
998
999 assert(which != call32_operand, "instruction is not a call, jmp, or jcc");
1000 #ifdef _LP64
1001 assert(which != imm_operand, "instruction is not a movq reg, imm64");
1002 #else
1003 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field");
1004 assert(which != imm_operand || has_disp32, "instruction has no imm32 field");
1005 #endif // LP64
1006 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field");
1007
1008 // parse the output of emit_operand
1009 int op2 = 0xFF & *ip++;
1010 int base = op2 & 0x07;
1011 int op3 = -1;
1012 const int b100 = 4;
1013 const int b101 = 5;
1014 if (base == b100 && (op2 >> 6) != 3) {
1015 op3 = 0xFF & *ip++;
1016 base = op3 & 0x07; // refetch the base
1017 }
1018 // now ip points at the disp (if any)
1019
1020 switch (op2 >> 6) {
1021 case 0:
1022 // [00 reg 100][ss index base]
1023 // [00 reg 100][00 100 esp]
1024 // [00 reg base]
1025 // [00 reg 100][ss index 101][disp32]
1026 // [00 reg 101] [disp32]
1027
1028 if (base == b101) {
1029 if (which == disp32_operand)
1030 return ip; // caller wants the disp32
1031 ip += 4; // skip the disp32
1032 }
1033 break;
1034
1035 case 1:
1036 // [01 reg 100][ss index base][disp8]
1037 // [01 reg 100][00 100 esp][disp8]
1038 // [01 reg base] [disp8]
1039 ip += 1; // skip the disp8
1040 break;
1041
1042 case 2:
1043 // [10 reg 100][ss index base][disp32]
1044 // [10 reg 100][00 100 esp][disp32]
1045 // [10 reg base] [disp32]
1046 if (which == disp32_operand)
1047 return ip; // caller wants the disp32
1048 ip += 4; // skip the disp32
1049 break;
1050
1051 case 3:
1052 // [11 reg base] (not a memory addressing mode)
1053 break;
1054 }
1055
1056 if (which == end_pc_operand) {
1057 return ip + tail_size;
1058 }
1059
1060 #ifdef _LP64
1061 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32");
1062 #else
1063 assert(which == imm_operand, "instruction has only an imm field");
1064 #endif // LP64
1065 return ip;
1066 }
1067
1068 address Assembler::locate_next_instruction(address inst) {
1069 // Secretly share code with locate_operand:
1070 return locate_operand(inst, end_pc_operand);
1071 }
1072
1073
1074 #ifdef ASSERT
1075 void Assembler::check_relocation(RelocationHolder const& rspec, int format) {
1076 address inst = inst_mark();
1077 assert(inst != NULL && inst < pc(), "must point to beginning of instruction");
1078 address opnd;
1079
1080 Relocation* r = rspec.reloc();
1081 if (r->type() == relocInfo::none) {
1082 return;
1083 } else if (r->is_call() || format == call32_operand) {
1084 // assert(format == imm32_operand, "cannot specify a nonzero format");
1085 opnd = locate_operand(inst, call32_operand);
1086 } else if (r->is_data()) {
1087 assert(format == imm_operand || format == disp32_operand
1088 LP64_ONLY(|| format == narrow_oop_operand), "format ok");
1089 opnd = locate_operand(inst, (WhichOperand)format);
1090 } else {
1091 assert(format == imm_operand, "cannot specify a format");
1092 return;
1093 }
1094 assert(opnd == pc(), "must put operand where relocs can find it");
1095 }
1096 #endif // ASSERT
1097
1098 void Assembler::emit_operand32(Register reg, Address adr) {
1099 assert(reg->encoding() < 8, "no extended registers");
1100 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1101 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1102 adr._rspec);
1103 }
1104
1105 void Assembler::emit_operand(Register reg, Address adr,
1106 int rip_relative_correction) {
1107 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1108 adr._rspec,
1109 rip_relative_correction);
1110 }
1111
1112 void Assembler::emit_operand(XMMRegister reg, Address adr) {
1113 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1114 adr._rspec);
1115 }
1116
1117 // MMX operations
1118 void Assembler::emit_operand(MMXRegister reg, Address adr) {
1119 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1120 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1121 }
1122
1123 // work around gcc (3.2.1-7a) bug
1124 void Assembler::emit_operand(Address adr, MMXRegister reg) {
1125 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1126 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1127 }
1128
1129
1130 void Assembler::emit_farith(int b1, int b2, int i) {
1131 assert(isByte(b1) && isByte(b2), "wrong opcode");
1132 assert(0 <= i && i < 8, "illegal stack offset");
1133 emit_int8(b1);
1134 emit_int8(b2 + i);
1135 }
1136
1137
1138 // Now the Assembler instructions (identical for 32/64 bits)
1139
1140 void Assembler::adcl(Address dst, int32_t imm32) {
1141 InstructionMark im(this);
1142 prefix(dst);
1143 emit_arith_operand(0x81, rdx, dst, imm32);
1144 }
1145
1146 void Assembler::adcl(Address dst, Register src) {
1147 InstructionMark im(this);
1148 prefix(dst, src);
1149 emit_int8(0x11);
1150 emit_operand(src, dst);
1151 }
1152
1153 void Assembler::adcl(Register dst, int32_t imm32) {
1154 prefix(dst);
1155 emit_arith(0x81, 0xD0, dst, imm32);
1156 }
1157
1158 void Assembler::adcl(Register dst, Address src) {
1159 InstructionMark im(this);
1160 prefix(src, dst);
1161 emit_int8(0x13);
1162 emit_operand(dst, src);
1163 }
1164
1165 void Assembler::adcl(Register dst, Register src) {
1166 (void) prefix_and_encode(dst->encoding(), src->encoding());
1167 emit_arith(0x13, 0xC0, dst, src);
1168 }
1169
1170 void Assembler::addl(Address dst, int32_t imm32) {
1171 InstructionMark im(this);
1172 prefix(dst);
1173 emit_arith_operand(0x81, rax, dst, imm32);
1174 }
1175
1176 void Assembler::addl(Address dst, Register src) {
1177 InstructionMark im(this);
1178 prefix(dst, src);
1179 emit_int8(0x01);
1180 emit_operand(src, dst);
1181 }
1182
1183 void Assembler::addl(Register dst, int32_t imm32) {
1184 prefix(dst);
1185 emit_arith(0x81, 0xC0, dst, imm32);
1186 }
1187
1188 void Assembler::addl(Register dst, Address src) {
1189 InstructionMark im(this);
1190 prefix(src, dst);
1191 emit_int8(0x03);
1192 emit_operand(dst, src);
1193 }
1194
1195 void Assembler::addl(Register dst, Register src) {
1196 (void) prefix_and_encode(dst->encoding(), src->encoding());
1197 emit_arith(0x03, 0xC0, dst, src);
1198 }
1199
1200 void Assembler::addr_nop_4() {
1201 assert(UseAddressNop, "no CPU support");
1202 // 4 bytes: NOP DWORD PTR [EAX+0]
1203 emit_int8(0x0F);
1204 emit_int8(0x1F);
1205 emit_int8(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
1206 emit_int8(0); // 8-bits offset (1 byte)
1207 }
1208
1209 void Assembler::addr_nop_5() {
1210 assert(UseAddressNop, "no CPU support");
1211 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
1212 emit_int8(0x0F);
1213 emit_int8(0x1F);
1214 emit_int8(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
1215 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1216 emit_int8(0); // 8-bits offset (1 byte)
1217 }
1218
1219 void Assembler::addr_nop_7() {
1220 assert(UseAddressNop, "no CPU support");
1221 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
1222 emit_int8(0x0F);
1223 emit_int8(0x1F);
1224 emit_int8((unsigned char)0x80);
1225 // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
1226 emit_int32(0); // 32-bits offset (4 bytes)
1227 }
1228
1229 void Assembler::addr_nop_8() {
1230 assert(UseAddressNop, "no CPU support");
1231 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
1232 emit_int8(0x0F);
1233 emit_int8(0x1F);
1234 emit_int8((unsigned char)0x84);
1235 // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
1236 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1237 emit_int32(0); // 32-bits offset (4 bytes)
1238 }
1239
1240 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
1241 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1242 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1243 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1244 emit_int8(0x58);
1245 emit_int8((unsigned char)(0xC0 | encode));
1246 }
1247
1248 void Assembler::addsd(XMMRegister dst, Address src) {
1249 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1250 InstructionMark im(this);
1251 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1252 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1253 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1254 emit_int8(0x58);
1255 emit_operand(dst, src);
1256 }
1257
1258 void Assembler::addss(XMMRegister dst, XMMRegister src) {
1259 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1260 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1261 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1262 emit_int8(0x58);
1263 emit_int8((unsigned char)(0xC0 | encode));
1264 }
1265
1266 void Assembler::addss(XMMRegister dst, Address src) {
1267 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1268 InstructionMark im(this);
1269 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1270 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1271 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1272 emit_int8(0x58);
1273 emit_operand(dst, src);
1274 }
1275
1276 void Assembler::aesdec(XMMRegister dst, Address src) {
1277 assert(VM_Version::supports_aes(), "");
1278 InstructionMark im(this);
1279 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1280 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1281 emit_int8((unsigned char)0xDE);
1282 emit_operand(dst, src);
1283 }
1284
1285 void Assembler::aesdec(XMMRegister dst, XMMRegister src) {
1286 assert(VM_Version::supports_aes(), "");
1287 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1288 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1289 emit_int8((unsigned char)0xDE);
1290 emit_int8(0xC0 | encode);
1291 }
1292
1293 void Assembler::aesdeclast(XMMRegister dst, Address src) {
1294 assert(VM_Version::supports_aes(), "");
1295 InstructionMark im(this);
1296 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1297 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1298 emit_int8((unsigned char)0xDF);
1299 emit_operand(dst, src);
1300 }
1301
1302 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) {
1303 assert(VM_Version::supports_aes(), "");
1304 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1305 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1306 emit_int8((unsigned char)0xDF);
1307 emit_int8((unsigned char)(0xC0 | encode));
1308 }
1309
1310 void Assembler::aesenc(XMMRegister dst, Address src) {
1311 assert(VM_Version::supports_aes(), "");
1312 InstructionMark im(this);
1313 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1314 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1315 emit_int8((unsigned char)0xDC);
1316 emit_operand(dst, src);
1317 }
1318
1319 void Assembler::aesenc(XMMRegister dst, XMMRegister src) {
1320 assert(VM_Version::supports_aes(), "");
1321 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1322 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1323 emit_int8((unsigned char)0xDC);
1324 emit_int8(0xC0 | encode);
1325 }
1326
1327 void Assembler::aesenclast(XMMRegister dst, Address src) {
1328 assert(VM_Version::supports_aes(), "");
1329 InstructionMark im(this);
1330 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1331 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1332 emit_int8((unsigned char)0xDD);
1333 emit_operand(dst, src);
1334 }
1335
1336 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) {
1337 assert(VM_Version::supports_aes(), "");
1338 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1339 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1340 emit_int8((unsigned char)0xDD);
1341 emit_int8((unsigned char)(0xC0 | encode));
1342 }
1343
1344 void Assembler::andl(Address dst, int32_t imm32) {
1345 InstructionMark im(this);
1346 prefix(dst);
1347 emit_int8((unsigned char)0x81);
1348 emit_operand(rsp, dst, 4);
1349 emit_int32(imm32);
1350 }
1351
1352 void Assembler::andl(Register dst, int32_t imm32) {
1353 prefix(dst);
1354 emit_arith(0x81, 0xE0, dst, imm32);
1355 }
1356
1357 void Assembler::andl(Register dst, Address src) {
1358 InstructionMark im(this);
1359 prefix(src, dst);
1360 emit_int8(0x23);
1361 emit_operand(dst, src);
1362 }
1363
1364 void Assembler::andl(Register dst, Register src) {
1365 (void) prefix_and_encode(dst->encoding(), src->encoding());
1366 emit_arith(0x23, 0xC0, dst, src);
1367 }
1368
1369 void Assembler::andnl(Register dst, Register src1, Register src2) {
1370 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1371 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1372 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1373 emit_int8((unsigned char)0xF2);
1374 emit_int8((unsigned char)(0xC0 | encode));
1375 }
1376
1377 void Assembler::andnl(Register dst, Register src1, Address src2) {
1378 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1379 InstructionMark im(this);
1380 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1381 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1382 emit_int8((unsigned char)0xF2);
1383 emit_operand(dst, src2);
1384 }
1385
1386 void Assembler::bsfl(Register dst, Register src) {
1387 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1388 emit_int8(0x0F);
1389 emit_int8((unsigned char)0xBC);
1390 emit_int8((unsigned char)(0xC0 | encode));
1391 }
1392
1393 void Assembler::bsrl(Register dst, Register src) {
1394 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1395 emit_int8(0x0F);
1396 emit_int8((unsigned char)0xBD);
1397 emit_int8((unsigned char)(0xC0 | encode));
1398 }
1399
1400 void Assembler::bswapl(Register reg) { // bswap
1401 int encode = prefix_and_encode(reg->encoding());
1402 emit_int8(0x0F);
1403 emit_int8((unsigned char)(0xC8 | encode));
1404 }
1405
1406 void Assembler::blsil(Register dst, Register src) {
1407 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1408 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1409 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1410 emit_int8((unsigned char)0xF3);
1411 emit_int8((unsigned char)(0xC0 | encode));
1412 }
1413
1414 void Assembler::blsil(Register dst, Address src) {
1415 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1416 InstructionMark im(this);
1417 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1418 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1419 emit_int8((unsigned char)0xF3);
1420 emit_operand(rbx, src);
1421 }
1422
1423 void Assembler::blsmskl(Register dst, Register src) {
1424 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1425 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1426 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1427 emit_int8((unsigned char)0xF3);
1428 emit_int8((unsigned char)(0xC0 | encode));
1429 }
1430
1431 void Assembler::blsmskl(Register dst, Address src) {
1432 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1433 InstructionMark im(this);
1434 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1435 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1436 emit_int8((unsigned char)0xF3);
1437 emit_operand(rdx, src);
1438 }
1439
1440 void Assembler::blsrl(Register dst, Register src) {
1441 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1442 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1443 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1444 emit_int8((unsigned char)0xF3);
1445 emit_int8((unsigned char)(0xC0 | encode));
1446 }
1447
1448 void Assembler::blsrl(Register dst, Address src) {
1449 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1450 InstructionMark im(this);
1451 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1452 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1453 emit_int8((unsigned char)0xF3);
1454 emit_operand(rcx, src);
1455 }
1456
1457 void Assembler::call(Label& L, relocInfo::relocType rtype) {
1458 // suspect disp32 is always good
1459 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
1460
1461 if (L.is_bound()) {
1462 const int long_size = 5;
1463 int offs = (int)( target(L) - pc() );
1464 assert(offs <= 0, "assembler error");
1465 InstructionMark im(this);
1466 // 1110 1000 #32-bit disp
1467 emit_int8((unsigned char)0xE8);
1468 emit_data(offs - long_size, rtype, operand);
1469 } else {
1470 InstructionMark im(this);
1471 // 1110 1000 #32-bit disp
1472 L.add_patch_at(code(), locator());
1473
1474 emit_int8((unsigned char)0xE8);
1475 emit_data(int(0), rtype, operand);
1476 }
1477 }
1478
1479 void Assembler::call(Register dst) {
1480 int encode = prefix_and_encode(dst->encoding());
1481 emit_int8((unsigned char)0xFF);
1482 emit_int8((unsigned char)(0xD0 | encode));
1483 }
1484
1485
1486 void Assembler::call(Address adr) {
1487 InstructionMark im(this);
1488 prefix(adr);
1489 emit_int8((unsigned char)0xFF);
1490 emit_operand(rdx, adr);
1491 }
1492
1493 void Assembler::call_literal(address entry, RelocationHolder const& rspec) {
1494 assert(entry != NULL, "call most probably wrong");
1495 InstructionMark im(this);
1496 emit_int8((unsigned char)0xE8);
1497 intptr_t disp = entry - (pc() + sizeof(int32_t));
1498 assert(is_simm32(disp), "must be 32bit offset (call2)");
1499 // Technically, should use call32_operand, but this format is
1500 // implied by the fact that we're emitting a call instruction.
1501
1502 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand);
1503 emit_data((int) disp, rspec, operand);
1504 }
1505
1506 void Assembler::cdql() {
1507 emit_int8((unsigned char)0x99);
1508 }
1509
1510 void Assembler::cld() {
1511 emit_int8((unsigned char)0xFC);
1512 }
1513
1514 void Assembler::cmovl(Condition cc, Register dst, Register src) {
1515 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1516 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1517 emit_int8(0x0F);
1518 emit_int8(0x40 | cc);
1519 emit_int8((unsigned char)(0xC0 | encode));
1520 }
1521
1522
1523 void Assembler::cmovl(Condition cc, Register dst, Address src) {
1524 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1525 prefix(src, dst);
1526 emit_int8(0x0F);
1527 emit_int8(0x40 | cc);
1528 emit_operand(dst, src);
1529 }
1530
1531 void Assembler::cmpb(Address dst, int imm8) {
1532 InstructionMark im(this);
1533 prefix(dst);
1534 emit_int8((unsigned char)0x80);
1535 emit_operand(rdi, dst, 1);
1536 emit_int8(imm8);
1537 }
1538
1539 void Assembler::cmpl(Address dst, int32_t imm32) {
1540 InstructionMark im(this);
1541 prefix(dst);
1542 emit_int8((unsigned char)0x81);
1543 emit_operand(rdi, dst, 4);
1544 emit_int32(imm32);
1545 }
1546
1547 void Assembler::cmpl(Register dst, int32_t imm32) {
1548 prefix(dst);
1549 emit_arith(0x81, 0xF8, dst, imm32);
1550 }
1551
1552 void Assembler::cmpl(Register dst, Register src) {
1553 (void) prefix_and_encode(dst->encoding(), src->encoding());
1554 emit_arith(0x3B, 0xC0, dst, src);
1555 }
1556
1557 void Assembler::cmpl(Register dst, Address src) {
1558 InstructionMark im(this);
1559 prefix(src, dst);
1560 emit_int8((unsigned char)0x3B);
1561 emit_operand(dst, src);
1562 }
1563
1564 void Assembler::cmpw(Address dst, int imm16) {
1565 InstructionMark im(this);
1566 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers");
1567 emit_int8(0x66);
1568 emit_int8((unsigned char)0x81);
1569 emit_operand(rdi, dst, 2);
1570 emit_int16(imm16);
1571 }
1572
1573 // The 32-bit cmpxchg compares the value at adr with the contents of rax,
1574 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1575 // The ZF is set if the compared values were equal, and cleared otherwise.
1576 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg
1577 InstructionMark im(this);
1578 prefix(adr, reg);
1579 emit_int8(0x0F);
1580 emit_int8((unsigned char)0xB1);
1581 emit_operand(reg, adr);
1582 }
1583
1584 // The 8-bit cmpxchg compares the value at adr with the contents of rax,
1585 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1586 // The ZF is set if the compared values were equal, and cleared otherwise.
1587 void Assembler::cmpxchgb(Register reg, Address adr) { // cmpxchg
1588 InstructionMark im(this);
1589 prefix(adr, reg, true);
1590 emit_int8(0x0F);
1591 emit_int8((unsigned char)0xB0);
1592 emit_operand(reg, adr);
1593 }
1594
1595 void Assembler::comisd(XMMRegister dst, Address src) {
1596 // NOTE: dbx seems to decode this as comiss even though the
1597 // 0x66 is there. Strangly ucomisd comes out correct
1598 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1599 InstructionMark im(this);
1600 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);;
1601 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1602 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1603 emit_int8(0x2F);
1604 emit_operand(dst, src);
1605 }
1606
1607 void Assembler::comisd(XMMRegister dst, XMMRegister src) {
1608 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1609 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1610 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1611 emit_int8(0x2F);
1612 emit_int8((unsigned char)(0xC0 | encode));
1613 }
1614
1615 void Assembler::comiss(XMMRegister dst, Address src) {
1616 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1617 InstructionMark im(this);
1618 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1619 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1620 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1621 emit_int8(0x2F);
1622 emit_operand(dst, src);
1623 }
1624
1625 void Assembler::comiss(XMMRegister dst, XMMRegister src) {
1626 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1627 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1628 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1629 emit_int8(0x2F);
1630 emit_int8((unsigned char)(0xC0 | encode));
1631 }
1632
1633 void Assembler::cpuid() {
1634 emit_int8(0x0F);
1635 emit_int8((unsigned char)0xA2);
1636 }
1637
1638 // Opcode / Instruction Op / En 64 - Bit Mode Compat / Leg Mode Description Implemented
1639 // F2 0F 38 F0 / r CRC32 r32, r / m8 RM Valid Valid Accumulate CRC32 on r / m8. v
1640 // F2 REX 0F 38 F0 / r CRC32 r32, r / m8* RM Valid N.E. Accumulate CRC32 on r / m8. -
1641 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E. Accumulate CRC32 on r / m8. -
1642 //
1643 // F2 0F 38 F1 / r CRC32 r32, r / m16 RM Valid Valid Accumulate CRC32 on r / m16. v
1644 //
1645 // F2 0F 38 F1 / r CRC32 r32, r / m32 RM Valid Valid Accumulate CRC32 on r / m32. v
1646 //
1647 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E. Accumulate CRC32 on r / m64. v
1648 void Assembler::crc32(Register crc, Register v, int8_t sizeInBytes) {
1649 assert(VM_Version::supports_sse4_2(), "");
1650 int8_t w = 0x01;
1651 Prefix p = Prefix_EMPTY;
1652
1653 emit_int8((int8_t)0xF2);
1654 switch (sizeInBytes) {
1655 case 1:
1656 w = 0;
1657 break;
1658 case 2:
1659 case 4:
1660 break;
1661 LP64_ONLY(case 8:)
1662 // This instruction is not valid in 32 bits
1663 // Note:
1664 // http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
1665 //
1666 // Page B - 72 Vol. 2C says
1667 // qwreg2 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : 11 qwreg1 qwreg2
1668 // mem64 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : mod qwreg r / m
1669 // F0!!!
1670 // while 3 - 208 Vol. 2A
1671 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E.Accumulate CRC32 on r / m64.
1672 //
1673 // the 0 on a last bit is reserved for a different flavor of this instruction :
1674 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E.Accumulate CRC32 on r / m8.
1675 p = REX_W;
1676 break;
1677 default:
1678 assert(0, "Unsupported value for a sizeInBytes argument");
1679 break;
1680 }
1681 LP64_ONLY(prefix(crc, v, p);)
1682 emit_int8((int8_t)0x0F);
1683 emit_int8(0x38);
1684 emit_int8((int8_t)(0xF0 | w));
1685 emit_int8(0xC0 | ((crc->encoding() & 0x7) << 3) | (v->encoding() & 7));
1686 }
1687
1688 void Assembler::crc32(Register crc, Address adr, int8_t sizeInBytes) {
1689 assert(VM_Version::supports_sse4_2(), "");
1690 InstructionMark im(this);
1691 int8_t w = 0x01;
1692 Prefix p = Prefix_EMPTY;
1693
1694 emit_int8((int8_t)0xF2);
1695 switch (sizeInBytes) {
1696 case 1:
1697 w = 0;
1698 break;
1699 case 2:
1700 case 4:
1701 break;
1702 LP64_ONLY(case 8:)
1703 // This instruction is not valid in 32 bits
1704 p = REX_W;
1705 break;
1706 default:
1707 assert(0, "Unsupported value for a sizeInBytes argument");
1708 break;
1709 }
1710 LP64_ONLY(prefix(crc, adr, p);)
1711 emit_int8((int8_t)0x0F);
1712 emit_int8(0x38);
1713 emit_int8((int8_t)(0xF0 | w));
1714 emit_operand(crc, adr);
1715 }
1716
1717 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
1718 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1719 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
1720 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1721 emit_int8((unsigned char)0xE6);
1722 emit_int8((unsigned char)(0xC0 | encode));
1723 }
1724
1725 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
1726 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1727 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
1728 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1729 emit_int8(0x5B);
1730 emit_int8((unsigned char)(0xC0 | encode));
1731 }
1732
1733 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
1734 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1735 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1736 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1737 emit_int8(0x5A);
1738 emit_int8((unsigned char)(0xC0 | encode));
1739 }
1740
1741 void Assembler::cvtsd2ss(XMMRegister dst, Address src) {
1742 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1743 InstructionMark im(this);
1744 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1745 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1746 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1747 emit_int8(0x5A);
1748 emit_operand(dst, src);
1749 }
1750
1751 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
1752 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1753 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1754 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1755 emit_int8(0x2A);
1756 emit_int8((unsigned char)(0xC0 | encode));
1757 }
1758
1759 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) {
1760 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1761 InstructionMark im(this);
1762 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1763 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1764 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1765 emit_int8(0x2A);
1766 emit_operand(dst, src);
1767 }
1768
1769 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
1770 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1771 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1772 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1773 emit_int8(0x2A);
1774 emit_int8((unsigned char)(0xC0 | encode));
1775 }
1776
1777 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) {
1778 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1779 InstructionMark im(this);
1780 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1781 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1782 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1783 emit_int8(0x2A);
1784 emit_operand(dst, src);
1785 }
1786
1787 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
1788 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1789 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1790 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1791 emit_int8(0x2A);
1792 emit_int8((unsigned char)(0xC0 | encode));
1793 }
1794
1795 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
1796 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1797 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1798 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1799 emit_int8(0x5A);
1800 emit_int8((unsigned char)(0xC0 | encode));
1801 }
1802
1803 void Assembler::cvtss2sd(XMMRegister dst, Address src) {
1804 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1805 InstructionMark im(this);
1806 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1807 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1808 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1809 emit_int8(0x5A);
1810 emit_operand(dst, src);
1811 }
1812
1813
1814 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
1815 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1816 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1817 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1818 emit_int8(0x2C);
1819 emit_int8((unsigned char)(0xC0 | encode));
1820 }
1821
1822 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
1823 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1824 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1825 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1826 emit_int8(0x2C);
1827 emit_int8((unsigned char)(0xC0 | encode));
1828 }
1829
1830 void Assembler::decl(Address dst) {
1831 // Don't use it directly. Use MacroAssembler::decrement() instead.
1832 InstructionMark im(this);
1833 prefix(dst);
1834 emit_int8((unsigned char)0xFF);
1835 emit_operand(rcx, dst);
1836 }
1837
1838 void Assembler::divsd(XMMRegister dst, Address src) {
1839 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1840 InstructionMark im(this);
1841 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1842 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1843 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1844 emit_int8(0x5E);
1845 emit_operand(dst, src);
1846 }
1847
1848 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
1849 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1850 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1851 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1852 emit_int8(0x5E);
1853 emit_int8((unsigned char)(0xC0 | encode));
1854 }
1855
1856 void Assembler::divss(XMMRegister dst, Address src) {
1857 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1858 InstructionMark im(this);
1859 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1860 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1861 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1862 emit_int8(0x5E);
1863 emit_operand(dst, src);
1864 }
1865
1866 void Assembler::divss(XMMRegister dst, XMMRegister src) {
1867 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1868 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1869 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1870 emit_int8(0x5E);
1871 emit_int8((unsigned char)(0xC0 | encode));
1872 }
1873
1874 void Assembler::emms() {
1875 NOT_LP64(assert(VM_Version::supports_mmx(), ""));
1876 emit_int8(0x0F);
1877 emit_int8(0x77);
1878 }
1879
1880 void Assembler::hlt() {
1881 emit_int8((unsigned char)0xF4);
1882 }
1883
1884 void Assembler::idivl(Register src) {
1885 int encode = prefix_and_encode(src->encoding());
1886 emit_int8((unsigned char)0xF7);
1887 emit_int8((unsigned char)(0xF8 | encode));
1888 }
1889
1890 void Assembler::divl(Register src) { // Unsigned
1891 int encode = prefix_and_encode(src->encoding());
1892 emit_int8((unsigned char)0xF7);
1893 emit_int8((unsigned char)(0xF0 | encode));
1894 }
1895
1896 void Assembler::imull(Register src) {
1897 int encode = prefix_and_encode(src->encoding());
1898 emit_int8((unsigned char)0xF7);
1899 emit_int8((unsigned char)(0xE8 | encode));
1900 }
1901
1902 void Assembler::imull(Register dst, Register src) {
1903 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1904 emit_int8(0x0F);
1905 emit_int8((unsigned char)0xAF);
1906 emit_int8((unsigned char)(0xC0 | encode));
1907 }
1908
1909
1910 void Assembler::imull(Register dst, Register src, int value) {
1911 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1912 if (is8bit(value)) {
1913 emit_int8(0x6B);
1914 emit_int8((unsigned char)(0xC0 | encode));
1915 emit_int8(value & 0xFF);
1916 } else {
1917 emit_int8(0x69);
1918 emit_int8((unsigned char)(0xC0 | encode));
1919 emit_int32(value);
1920 }
1921 }
1922
1923 void Assembler::imull(Register dst, Address src) {
1924 InstructionMark im(this);
1925 prefix(src, dst);
1926 emit_int8(0x0F);
1927 emit_int8((unsigned char) 0xAF);
1928 emit_operand(dst, src);
1929 }
1930
1931
1932 void Assembler::incl(Address dst) {
1933 // Don't use it directly. Use MacroAssembler::increment() instead.
1934 InstructionMark im(this);
1935 prefix(dst);
1936 emit_int8((unsigned char)0xFF);
1937 emit_operand(rax, dst);
1938 }
1939
1940 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) {
1941 InstructionMark im(this);
1942 assert((0 <= cc) && (cc < 16), "illegal cc");
1943 if (L.is_bound()) {
1944 address dst = target(L);
1945 assert(dst != NULL, "jcc most probably wrong");
1946
1947 const int short_size = 2;
1948 const int long_size = 6;
1949 intptr_t offs = (intptr_t)dst - (intptr_t)pc();
1950 if (maybe_short && is8bit(offs - short_size)) {
1951 // 0111 tttn #8-bit disp
1952 emit_int8(0x70 | cc);
1953 emit_int8((offs - short_size) & 0xFF);
1954 } else {
1955 // 0000 1111 1000 tttn #32-bit disp
1956 assert(is_simm32(offs - long_size),
1957 "must be 32bit offset (call4)");
1958 emit_int8(0x0F);
1959 emit_int8((unsigned char)(0x80 | cc));
1960 emit_int32(offs - long_size);
1961 }
1962 } else {
1963 // Note: could eliminate cond. jumps to this jump if condition
1964 // is the same however, seems to be rather unlikely case.
1965 // Note: use jccb() if label to be bound is very close to get
1966 // an 8-bit displacement
1967 L.add_patch_at(code(), locator());
1968 emit_int8(0x0F);
1969 emit_int8((unsigned char)(0x80 | cc));
1970 emit_int32(0);
1971 }
1972 }
1973
1974 void Assembler::jccb(Condition cc, Label& L) {
1975 if (L.is_bound()) {
1976 const int short_size = 2;
1977 address entry = target(L);
1978 #ifdef ASSERT
1979 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
1980 intptr_t delta = short_branch_delta();
1981 if (delta != 0) {
1982 dist += (dist < 0 ? (-delta) :delta);
1983 }
1984 assert(is8bit(dist), "Dispacement too large for a short jmp");
1985 #endif
1986 intptr_t offs = (intptr_t)entry - (intptr_t)pc();
1987 // 0111 tttn #8-bit disp
1988 emit_int8(0x70 | cc);
1989 emit_int8((offs - short_size) & 0xFF);
1990 } else {
1991 InstructionMark im(this);
1992 L.add_patch_at(code(), locator());
1993 emit_int8(0x70 | cc);
1994 emit_int8(0);
1995 }
1996 }
1997
1998 void Assembler::jmp(Address adr) {
1999 InstructionMark im(this);
2000 prefix(adr);
2001 emit_int8((unsigned char)0xFF);
2002 emit_operand(rsp, adr);
2003 }
2004
2005 void Assembler::jmp(Label& L, bool maybe_short) {
2006 if (L.is_bound()) {
2007 address entry = target(L);
2008 assert(entry != NULL, "jmp most probably wrong");
2009 InstructionMark im(this);
2010 const int short_size = 2;
2011 const int long_size = 5;
2012 intptr_t offs = entry - pc();
2013 if (maybe_short && is8bit(offs - short_size)) {
2014 emit_int8((unsigned char)0xEB);
2015 emit_int8((offs - short_size) & 0xFF);
2016 } else {
2017 emit_int8((unsigned char)0xE9);
2018 emit_int32(offs - long_size);
2019 }
2020 } else {
2021 // By default, forward jumps are always 32-bit displacements, since
2022 // we can't yet know where the label will be bound. If you're sure that
2023 // the forward jump will not run beyond 256 bytes, use jmpb to
2024 // force an 8-bit displacement.
2025 InstructionMark im(this);
2026 L.add_patch_at(code(), locator());
2027 emit_int8((unsigned char)0xE9);
2028 emit_int32(0);
2029 }
2030 }
2031
2032 void Assembler::jmp(Register entry) {
2033 int encode = prefix_and_encode(entry->encoding());
2034 emit_int8((unsigned char)0xFF);
2035 emit_int8((unsigned char)(0xE0 | encode));
2036 }
2037
2038 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
2039 InstructionMark im(this);
2040 emit_int8((unsigned char)0xE9);
2041 assert(dest != NULL, "must have a target");
2042 intptr_t disp = dest - (pc() + sizeof(int32_t));
2043 assert(is_simm32(disp), "must be 32bit offset (jmp)");
2044 emit_data(disp, rspec.reloc(), call32_operand);
2045 }
2046
2047 void Assembler::jmpb(Label& L) {
2048 if (L.is_bound()) {
2049 const int short_size = 2;
2050 address entry = target(L);
2051 assert(entry != NULL, "jmp most probably wrong");
2052 #ifdef ASSERT
2053 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
2054 intptr_t delta = short_branch_delta();
2055 if (delta != 0) {
2056 dist += (dist < 0 ? (-delta) :delta);
2057 }
2058 assert(is8bit(dist), "Dispacement too large for a short jmp");
2059 #endif
2060 intptr_t offs = entry - pc();
2061 emit_int8((unsigned char)0xEB);
2062 emit_int8((offs - short_size) & 0xFF);
2063 } else {
2064 InstructionMark im(this);
2065 L.add_patch_at(code(), locator());
2066 emit_int8((unsigned char)0xEB);
2067 emit_int8(0);
2068 }
2069 }
2070
2071 void Assembler::ldmxcsr( Address src) {
2072 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2073 InstructionMark im(this);
2074 prefix(src);
2075 emit_int8(0x0F);
2076 emit_int8((unsigned char)0xAE);
2077 emit_operand(as_Register(2), src);
2078 }
2079
2080 void Assembler::leal(Register dst, Address src) {
2081 InstructionMark im(this);
2082 #ifdef _LP64
2083 emit_int8(0x67); // addr32
2084 prefix(src, dst);
2085 #endif // LP64
2086 emit_int8((unsigned char)0x8D);
2087 emit_operand(dst, src);
2088 }
2089
2090 void Assembler::lfence() {
2091 emit_int8(0x0F);
2092 emit_int8((unsigned char)0xAE);
2093 emit_int8((unsigned char)0xE8);
2094 }
2095
2096 void Assembler::lock() {
2097 emit_int8((unsigned char)0xF0);
2098 }
2099
2100 void Assembler::lzcntl(Register dst, Register src) {
2101 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
2102 emit_int8((unsigned char)0xF3);
2103 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2104 emit_int8(0x0F);
2105 emit_int8((unsigned char)0xBD);
2106 emit_int8((unsigned char)(0xC0 | encode));
2107 }
2108
2109 // Emit mfence instruction
2110 void Assembler::mfence() {
2111 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
2112 emit_int8(0x0F);
2113 emit_int8((unsigned char)0xAE);
2114 emit_int8((unsigned char)0xF0);
2115 }
2116
2117 void Assembler::mov(Register dst, Register src) {
2118 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2119 }
2120
2121 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
2122 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2123 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2124 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2125 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2126 emit_int8(0x28);
2127 emit_int8((unsigned char)(0xC0 | encode));
2128 }
2129
2130 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
2131 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2132 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2133 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2134 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2135 emit_int8(0x28);
2136 emit_int8((unsigned char)(0xC0 | encode));
2137 }
2138
2139 void Assembler::movlhps(XMMRegister dst, XMMRegister src) {
2140 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2141 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2142 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2143 emit_int8(0x16);
2144 emit_int8((unsigned char)(0xC0 | encode));
2145 }
2146
2147 void Assembler::movb(Register dst, Address src) {
2148 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
2149 InstructionMark im(this);
2150 prefix(src, dst, true);
2151 emit_int8((unsigned char)0x8A);
2152 emit_operand(dst, src);
2153 }
2154
2155 void Assembler::movddup(XMMRegister dst, XMMRegister src) {
2156 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
2157 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2158 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2159 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2160 emit_int8(0x12);
2161 emit_int8(0xC0 | encode);
2162 }
2163
2164 void Assembler::kmovbl(KRegister dst, Register src) {
2165 assert(VM_Version::supports_avx512dq(), "");
2166 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2167 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2168 emit_int8((unsigned char)0x92);
2169 emit_int8((unsigned char)(0xC0 | encode));
2170 }
2171
2172 void Assembler::kmovbl(Register dst, KRegister src) {
2173 assert(VM_Version::supports_avx512dq(), "");
2174 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2175 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2176 emit_int8((unsigned char)0x93);
2177 emit_int8((unsigned char)(0xC0 | encode));
2178 }
2179
2180 void Assembler::kmovwl(KRegister dst, Register src) {
2181 assert(VM_Version::supports_evex(), "");
2182 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2183 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2184 emit_int8((unsigned char)0x92);
2185 emit_int8((unsigned char)(0xC0 | encode));
2186 }
2187
2188 void Assembler::kmovwl(Register dst, KRegister src) {
2189 assert(VM_Version::supports_evex(), "");
2190 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2191 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2192 emit_int8((unsigned char)0x93);
2193 emit_int8((unsigned char)(0xC0 | encode));
2194 }
2195
2196 void Assembler::kmovdl(KRegister dst, Register src) {
2197 assert(VM_Version::supports_avx512bw(), "");
2198 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2199 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2200 emit_int8((unsigned char)0x92);
2201 emit_int8((unsigned char)(0xC0 | encode));
2202 }
2203
2204 void Assembler::kmovdl(Register dst, KRegister src) {
2205 assert(VM_Version::supports_avx512bw(), "");
2206 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2207 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2208 emit_int8((unsigned char)0x93);
2209 emit_int8((unsigned char)(0xC0 | encode));
2210 }
2211
2212 void Assembler::kmovql(KRegister dst, KRegister src) {
2213 assert(VM_Version::supports_avx512bw(), "");
2214 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2215 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2216 emit_int8((unsigned char)0x90);
2217 emit_int8((unsigned char)(0xC0 | encode));
2218 }
2219
2220 void Assembler::kmovql(KRegister dst, Address src) {
2221 assert(VM_Version::supports_avx512bw(), "");
2222 InstructionMark im(this);
2223 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2224 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2225 emit_int8((unsigned char)0x90);
2226 emit_operand((Register)dst, src);
2227 }
2228
2229 void Assembler::kmovql(Address dst, KRegister src) {
2230 assert(VM_Version::supports_avx512bw(), "");
2231 InstructionMark im(this);
2232 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2233 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2234 emit_int8((unsigned char)0x90);
2235 emit_operand((Register)src, dst);
2236 }
2237
2238 void Assembler::kmovql(KRegister dst, Register src) {
2239 assert(VM_Version::supports_avx512bw(), "");
2240 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2241 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2242 emit_int8((unsigned char)0x92);
2243 emit_int8((unsigned char)(0xC0 | encode));
2244 }
2245
2246 void Assembler::kmovql(Register dst, KRegister src) {
2247 assert(VM_Version::supports_avx512bw(), "");
2248 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2249 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2250 emit_int8((unsigned char)0x93);
2251 emit_int8((unsigned char)(0xC0 | encode));
2252 }
2253
2254 // This instruction produces ZF or CF flags
2255 void Assembler::kortestbl(KRegister src1, KRegister src2) {
2256 assert(VM_Version::supports_avx512dq(), "");
2257 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2258 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2259 emit_int8((unsigned char)0x98);
2260 emit_int8((unsigned char)(0xC0 | encode));
2261 }
2262
2263 // This instruction produces ZF or CF flags
2264 void Assembler::kortestwl(KRegister src1, KRegister src2) {
2265 assert(VM_Version::supports_evex(), "");
2266 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2267 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2268 emit_int8((unsigned char)0x98);
2269 emit_int8((unsigned char)(0xC0 | encode));
2270 }
2271
2272 // This instruction produces ZF or CF flags
2273 void Assembler::kortestdl(KRegister src1, KRegister src2) {
2274 assert(VM_Version::supports_avx512bw(), "");
2275 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2276 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2277 emit_int8((unsigned char)0x98);
2278 emit_int8((unsigned char)(0xC0 | encode));
2279 }
2280
2281 // This instruction produces ZF or CF flags
2282 void Assembler::kortestql(KRegister src1, KRegister src2) {
2283 assert(VM_Version::supports_avx512bw(), "");
2284 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2285 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2286 emit_int8((unsigned char)0x98);
2287 emit_int8((unsigned char)(0xC0 | encode));
2288 }
2289
2290 void Assembler::movb(Address dst, int imm8) {
2291 InstructionMark im(this);
2292 prefix(dst);
2293 emit_int8((unsigned char)0xC6);
2294 emit_operand(rax, dst, 1);
2295 emit_int8(imm8);
2296 }
2297
2298
2299 void Assembler::movb(Address dst, Register src) {
2300 assert(src->has_byte_register(), "must have byte register");
2301 InstructionMark im(this);
2302 prefix(dst, src, true);
2303 emit_int8((unsigned char)0x88);
2304 emit_operand(src, dst);
2305 }
2306
2307 void Assembler::movdl(XMMRegister dst, Register src) {
2308 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2309 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2310 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2311 emit_int8(0x6E);
2312 emit_int8((unsigned char)(0xC0 | encode));
2313 }
2314
2315 void Assembler::movdl(Register dst, XMMRegister src) {
2316 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2317 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2318 // swap src/dst to get correct prefix
2319 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2320 emit_int8(0x7E);
2321 emit_int8((unsigned char)(0xC0 | encode));
2322 }
2323
2324 void Assembler::movdl(XMMRegister dst, Address src) {
2325 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2326 InstructionMark im(this);
2327 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2328 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2329 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2330 emit_int8(0x6E);
2331 emit_operand(dst, src);
2332 }
2333
2334 void Assembler::movdl(Address dst, XMMRegister src) {
2335 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2336 InstructionMark im(this);
2337 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2338 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2339 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2340 emit_int8(0x7E);
2341 emit_operand(src, dst);
2342 }
2343
2344 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
2345 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2346 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2347 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2348 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2349 emit_int8(0x6F);
2350 emit_int8((unsigned char)(0xC0 | encode));
2351 }
2352
2353 void Assembler::movdqa(XMMRegister dst, Address src) {
2354 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2355 InstructionMark im(this);
2356 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2357 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2358 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2359 emit_int8(0x6F);
2360 emit_operand(dst, src);
2361 }
2362
2363 void Assembler::movdqu(XMMRegister dst, Address src) {
2364 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2365 InstructionMark im(this);
2366 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2367 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2368 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2369 emit_int8(0x6F);
2370 emit_operand(dst, src);
2371 }
2372
2373 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
2374 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2375 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2376 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2377 emit_int8(0x6F);
2378 emit_int8((unsigned char)(0xC0 | encode));
2379 }
2380
2381 void Assembler::movdqu(Address dst, XMMRegister src) {
2382 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2383 InstructionMark im(this);
2384 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2385 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2386 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2387 emit_int8(0x7F);
2388 emit_operand(src, dst);
2389 }
2390
2391 // Move Unaligned 256bit Vector
2392 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2393 assert(UseAVX > 0, "");
2394 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2395 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2396 emit_int8(0x6F);
2397 emit_int8((unsigned char)(0xC0 | encode));
2398 }
2399
2400 void Assembler::vmovdqu(XMMRegister dst, Address src) {
2401 assert(UseAVX > 0, "");
2402 InstructionMark im(this);
2403 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2404 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2405 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2406 emit_int8(0x6F);
2407 emit_operand(dst, src);
2408 }
2409
2410 void Assembler::vmovdqu(Address dst, XMMRegister src) {
2411 assert(UseAVX > 0, "");
2412 InstructionMark im(this);
2413 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2414 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2415 // swap src<->dst for encoding
2416 assert(src != xnoreg, "sanity");
2417 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2418 emit_int8(0x7F);
2419 emit_operand(src, dst);
2420 }
2421
2422 // Move Unaligned EVEX enabled Vector (programmable : 8,16,32,64)
2423 void Assembler::evmovdqub(XMMRegister dst, XMMRegister src, int vector_len) {
2424 assert(VM_Version::supports_evex(), "");
2425 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2426 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2427 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2428 emit_int8(0x6F);
2429 emit_int8((unsigned char)(0xC0 | encode));
2430 }
2431
2432 void Assembler::evmovdqub(XMMRegister dst, Address src, int vector_len) {
2433 assert(VM_Version::supports_evex(), "");
2434 InstructionMark im(this);
2435 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2436 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2437 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2438 vex_prefix(src, 0, dst->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2439 emit_int8(0x6F);
2440 emit_operand(dst, src);
2441 }
2442
2443 void Assembler::evmovdqub(Address dst, XMMRegister src, int vector_len) {
2444 assert(VM_Version::supports_evex(), "");
2445 assert(src != xnoreg, "sanity");
2446 InstructionMark im(this);
2447 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2448 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2449 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2450 vex_prefix(dst, 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2451 emit_int8(0x7F);
2452 emit_operand(src, dst);
2453 }
2454
2455 void Assembler::evmovdquw(XMMRegister dst, XMMRegister src, int vector_len) {
2456 assert(VM_Version::supports_evex(), "");
2457 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2458 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2459 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2460 emit_int8(0x6F);
2461 emit_int8((unsigned char)(0xC0 | encode));
2462 }
2463
2464 void Assembler::evmovdquw(XMMRegister dst, Address src, int vector_len) {
2465 assert(VM_Version::supports_evex(), "");
2466 InstructionMark im(this);
2467 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2468 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2469 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2470 vex_prefix(src, 0, dst->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2471 emit_int8(0x6F);
2472 emit_operand(dst, src);
2473 }
2474
2475 void Assembler::evmovdquw(Address dst, XMMRegister src, int vector_len) {
2476 assert(VM_Version::supports_evex(), "");
2477 assert(src != xnoreg, "sanity");
2478 InstructionMark im(this);
2479 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2480 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2481 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2482 vex_prefix(dst, 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2483 emit_int8(0x7F);
2484 emit_operand(src, dst);
2485 }
2486
2487 void Assembler::evmovdqul(XMMRegister dst, XMMRegister src, int vector_len) {
2488 assert(VM_Version::supports_evex(), "");
2489 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2490 attributes.set_is_evex_instruction();
2491 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2492 emit_int8(0x6F);
2493 emit_int8((unsigned char)(0xC0 | encode));
2494 }
2495
2496 void Assembler::evmovdqul(XMMRegister dst, Address src, int vector_len) {
2497 assert(VM_Version::supports_evex(), "");
2498 InstructionMark im(this);
2499 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false , /* uses_vl */ true);
2500 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2501 attributes.set_is_evex_instruction();
2502 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2503 emit_int8(0x6F);
2504 emit_operand(dst, src);
2505 }
2506
2507 void Assembler::evmovdqul(Address dst, XMMRegister src, int vector_len) {
2508 assert(VM_Version::supports_evex(), "");
2509 assert(src != xnoreg, "sanity");
2510 InstructionMark im(this);
2511 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2512 attributes.set_is_evex_instruction();
2513 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2514 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2515 emit_int8(0x7F);
2516 emit_operand(src, dst);
2517 }
2518
2519 void Assembler::evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) {
2520 assert(VM_Version::supports_evex(), "");
2521 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2522 attributes.set_is_evex_instruction();
2523 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2524 emit_int8(0x6F);
2525 emit_int8((unsigned char)(0xC0 | encode));
2526 }
2527
2528 void Assembler::evmovdquq(XMMRegister dst, Address src, int vector_len) {
2529 assert(VM_Version::supports_evex(), "");
2530 InstructionMark im(this);
2531 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2532 attributes.set_is_evex_instruction();
2533 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2534 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2535 emit_int8(0x6F);
2536 emit_operand(dst, src);
2537 }
2538
2539 void Assembler::evmovdquq(Address dst, XMMRegister src, int vector_len) {
2540 assert(VM_Version::supports_evex(), "");
2541 assert(src != xnoreg, "sanity");
2542 InstructionMark im(this);
2543 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2544 attributes.set_is_evex_instruction();
2545 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2546 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2547 emit_int8(0x7F);
2548 emit_operand(src, dst);
2549 }
2550
2551 // Uses zero extension on 64bit
2552
2553 void Assembler::movl(Register dst, int32_t imm32) {
2554 int encode = prefix_and_encode(dst->encoding());
2555 emit_int8((unsigned char)(0xB8 | encode));
2556 emit_int32(imm32);
2557 }
2558
2559 void Assembler::movl(Register dst, Register src) {
2560 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2561 emit_int8((unsigned char)0x8B);
2562 emit_int8((unsigned char)(0xC0 | encode));
2563 }
2564
2565 void Assembler::movl(Register dst, Address src) {
2566 InstructionMark im(this);
2567 prefix(src, dst);
2568 emit_int8((unsigned char)0x8B);
2569 emit_operand(dst, src);
2570 }
2571
2572 void Assembler::movl(Address dst, int32_t imm32) {
2573 InstructionMark im(this);
2574 prefix(dst);
2575 emit_int8((unsigned char)0xC7);
2576 emit_operand(rax, dst, 4);
2577 emit_int32(imm32);
2578 }
2579
2580 void Assembler::movl(Address dst, Register src) {
2581 InstructionMark im(this);
2582 prefix(dst, src);
2583 emit_int8((unsigned char)0x89);
2584 emit_operand(src, dst);
2585 }
2586
2587 // New cpus require to use movsd and movss to avoid partial register stall
2588 // when loading from memory. But for old Opteron use movlpd instead of movsd.
2589 // The selection is done in MacroAssembler::movdbl() and movflt().
2590 void Assembler::movlpd(XMMRegister dst, Address src) {
2591 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2592 InstructionMark im(this);
2593 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2594 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2595 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2596 emit_int8(0x12);
2597 emit_operand(dst, src);
2598 }
2599
2600 void Assembler::movq( MMXRegister dst, Address src ) {
2601 assert( VM_Version::supports_mmx(), "" );
2602 emit_int8(0x0F);
2603 emit_int8(0x6F);
2604 emit_operand(dst, src);
2605 }
2606
2607 void Assembler::movq( Address dst, MMXRegister src ) {
2608 assert( VM_Version::supports_mmx(), "" );
2609 emit_int8(0x0F);
2610 emit_int8(0x7F);
2611 // workaround gcc (3.2.1-7a) bug
2612 // In that version of gcc with only an emit_operand(MMX, Address)
2613 // gcc will tail jump and try and reverse the parameters completely
2614 // obliterating dst in the process. By having a version available
2615 // that doesn't need to swap the args at the tail jump the bug is
2616 // avoided.
2617 emit_operand(dst, src);
2618 }
2619
2620 void Assembler::movq(XMMRegister dst, Address src) {
2621 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2622 InstructionMark im(this);
2623 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2624 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2625 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2626 emit_int8(0x7E);
2627 emit_operand(dst, src);
2628 }
2629
2630 void Assembler::movq(Address dst, XMMRegister src) {
2631 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2632 InstructionMark im(this);
2633 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2634 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2635 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2636 emit_int8((unsigned char)0xD6);
2637 emit_operand(src, dst);
2638 }
2639
2640 void Assembler::movsbl(Register dst, Address src) { // movsxb
2641 InstructionMark im(this);
2642 prefix(src, dst);
2643 emit_int8(0x0F);
2644 emit_int8((unsigned char)0xBE);
2645 emit_operand(dst, src);
2646 }
2647
2648 void Assembler::movsbl(Register dst, Register src) { // movsxb
2649 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2650 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
2651 emit_int8(0x0F);
2652 emit_int8((unsigned char)0xBE);
2653 emit_int8((unsigned char)(0xC0 | encode));
2654 }
2655
2656 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
2657 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2658 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2659 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2660 emit_int8(0x10);
2661 emit_int8((unsigned char)(0xC0 | encode));
2662 }
2663
2664 void Assembler::movsd(XMMRegister dst, Address src) {
2665 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2666 InstructionMark im(this);
2667 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2668 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2669 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2670 emit_int8(0x10);
2671 emit_operand(dst, src);
2672 }
2673
2674 void Assembler::movsd(Address dst, XMMRegister src) {
2675 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2676 InstructionMark im(this);
2677 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2678 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2679 simd_prefix(src, xnoreg, dst, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2680 emit_int8(0x11);
2681 emit_operand(src, dst);
2682 }
2683
2684 void Assembler::movss(XMMRegister dst, XMMRegister src) {
2685 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2686 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2687 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2688 emit_int8(0x10);
2689 emit_int8((unsigned char)(0xC0 | encode));
2690 }
2691
2692 void Assembler::movss(XMMRegister dst, Address src) {
2693 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2694 InstructionMark im(this);
2695 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2696 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2697 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2698 emit_int8(0x10);
2699 emit_operand(dst, src);
2700 }
2701
2702 void Assembler::movss(Address dst, XMMRegister src) {
2703 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2704 InstructionMark im(this);
2705 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2706 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2707 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2708 emit_int8(0x11);
2709 emit_operand(src, dst);
2710 }
2711
2712 void Assembler::movswl(Register dst, Address src) { // movsxw
2713 InstructionMark im(this);
2714 prefix(src, dst);
2715 emit_int8(0x0F);
2716 emit_int8((unsigned char)0xBF);
2717 emit_operand(dst, src);
2718 }
2719
2720 void Assembler::movswl(Register dst, Register src) { // movsxw
2721 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2722 emit_int8(0x0F);
2723 emit_int8((unsigned char)0xBF);
2724 emit_int8((unsigned char)(0xC0 | encode));
2725 }
2726
2727 void Assembler::movw(Address dst, int imm16) {
2728 InstructionMark im(this);
2729
2730 emit_int8(0x66); // switch to 16-bit mode
2731 prefix(dst);
2732 emit_int8((unsigned char)0xC7);
2733 emit_operand(rax, dst, 2);
2734 emit_int16(imm16);
2735 }
2736
2737 void Assembler::movw(Register dst, Address src) {
2738 InstructionMark im(this);
2739 emit_int8(0x66);
2740 prefix(src, dst);
2741 emit_int8((unsigned char)0x8B);
2742 emit_operand(dst, src);
2743 }
2744
2745 void Assembler::movw(Address dst, Register src) {
2746 InstructionMark im(this);
2747 emit_int8(0x66);
2748 prefix(dst, src);
2749 emit_int8((unsigned char)0x89);
2750 emit_operand(src, dst);
2751 }
2752
2753 void Assembler::movzbl(Register dst, Address src) { // movzxb
2754 InstructionMark im(this);
2755 prefix(src, dst);
2756 emit_int8(0x0F);
2757 emit_int8((unsigned char)0xB6);
2758 emit_operand(dst, src);
2759 }
2760
2761 void Assembler::movzbl(Register dst, Register src) { // movzxb
2762 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2763 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
2764 emit_int8(0x0F);
2765 emit_int8((unsigned char)0xB6);
2766 emit_int8(0xC0 | encode);
2767 }
2768
2769 void Assembler::movzwl(Register dst, Address src) { // movzxw
2770 InstructionMark im(this);
2771 prefix(src, dst);
2772 emit_int8(0x0F);
2773 emit_int8((unsigned char)0xB7);
2774 emit_operand(dst, src);
2775 }
2776
2777 void Assembler::movzwl(Register dst, Register src) { // movzxw
2778 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2779 emit_int8(0x0F);
2780 emit_int8((unsigned char)0xB7);
2781 emit_int8(0xC0 | encode);
2782 }
2783
2784 void Assembler::mull(Address src) {
2785 InstructionMark im(this);
2786 prefix(src);
2787 emit_int8((unsigned char)0xF7);
2788 emit_operand(rsp, src);
2789 }
2790
2791 void Assembler::mull(Register src) {
2792 int encode = prefix_and_encode(src->encoding());
2793 emit_int8((unsigned char)0xF7);
2794 emit_int8((unsigned char)(0xE0 | encode));
2795 }
2796
2797 void Assembler::mulsd(XMMRegister dst, Address src) {
2798 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2799 InstructionMark im(this);
2800 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2801 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2802 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2803 emit_int8(0x59);
2804 emit_operand(dst, src);
2805 }
2806
2807 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
2808 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2809 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2810 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2811 emit_int8(0x59);
2812 emit_int8((unsigned char)(0xC0 | encode));
2813 }
2814
2815 void Assembler::mulss(XMMRegister dst, Address src) {
2816 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2817 InstructionMark im(this);
2818 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2819 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2820 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2821 emit_int8(0x59);
2822 emit_operand(dst, src);
2823 }
2824
2825 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
2826 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2827 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2828 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2829 emit_int8(0x59);
2830 emit_int8((unsigned char)(0xC0 | encode));
2831 }
2832
2833 void Assembler::negl(Register dst) {
2834 int encode = prefix_and_encode(dst->encoding());
2835 emit_int8((unsigned char)0xF7);
2836 emit_int8((unsigned char)(0xD8 | encode));
2837 }
2838
2839 void Assembler::nop(int i) {
2840 #ifdef ASSERT
2841 assert(i > 0, " ");
2842 // The fancy nops aren't currently recognized by debuggers making it a
2843 // pain to disassemble code while debugging. If asserts are on clearly
2844 // speed is not an issue so simply use the single byte traditional nop
2845 // to do alignment.
2846
2847 for (; i > 0 ; i--) emit_int8((unsigned char)0x90);
2848 return;
2849
2850 #endif // ASSERT
2851
2852 if (UseAddressNop && VM_Version::is_intel()) {
2853 //
2854 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel
2855 // 1: 0x90
2856 // 2: 0x66 0x90
2857 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2858 // 4: 0x0F 0x1F 0x40 0x00
2859 // 5: 0x0F 0x1F 0x44 0x00 0x00
2860 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2861 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2862 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2863 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2864 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2865 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2866
2867 // The rest coding is Intel specific - don't use consecutive address nops
2868
2869 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2870 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2871 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2872 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2873
2874 while(i >= 15) {
2875 // For Intel don't generate consecutive addess nops (mix with regular nops)
2876 i -= 15;
2877 emit_int8(0x66); // size prefix
2878 emit_int8(0x66); // size prefix
2879 emit_int8(0x66); // size prefix
2880 addr_nop_8();
2881 emit_int8(0x66); // size prefix
2882 emit_int8(0x66); // size prefix
2883 emit_int8(0x66); // size prefix
2884 emit_int8((unsigned char)0x90);
2885 // nop
2886 }
2887 switch (i) {
2888 case 14:
2889 emit_int8(0x66); // size prefix
2890 case 13:
2891 emit_int8(0x66); // size prefix
2892 case 12:
2893 addr_nop_8();
2894 emit_int8(0x66); // size prefix
2895 emit_int8(0x66); // size prefix
2896 emit_int8(0x66); // size prefix
2897 emit_int8((unsigned char)0x90);
2898 // nop
2899 break;
2900 case 11:
2901 emit_int8(0x66); // size prefix
2902 case 10:
2903 emit_int8(0x66); // size prefix
2904 case 9:
2905 emit_int8(0x66); // size prefix
2906 case 8:
2907 addr_nop_8();
2908 break;
2909 case 7:
2910 addr_nop_7();
2911 break;
2912 case 6:
2913 emit_int8(0x66); // size prefix
2914 case 5:
2915 addr_nop_5();
2916 break;
2917 case 4:
2918 addr_nop_4();
2919 break;
2920 case 3:
2921 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
2922 emit_int8(0x66); // size prefix
2923 case 2:
2924 emit_int8(0x66); // size prefix
2925 case 1:
2926 emit_int8((unsigned char)0x90);
2927 // nop
2928 break;
2929 default:
2930 assert(i == 0, " ");
2931 }
2932 return;
2933 }
2934 if (UseAddressNop && VM_Version::is_amd()) {
2935 //
2936 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD.
2937 // 1: 0x90
2938 // 2: 0x66 0x90
2939 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2940 // 4: 0x0F 0x1F 0x40 0x00
2941 // 5: 0x0F 0x1F 0x44 0x00 0x00
2942 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2943 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2944 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2945 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2946 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2947 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2948
2949 // The rest coding is AMD specific - use consecutive address nops
2950
2951 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2952 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2953 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2954 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2955 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2956 // Size prefixes (0x66) are added for larger sizes
2957
2958 while(i >= 22) {
2959 i -= 11;
2960 emit_int8(0x66); // size prefix
2961 emit_int8(0x66); // size prefix
2962 emit_int8(0x66); // size prefix
2963 addr_nop_8();
2964 }
2965 // Generate first nop for size between 21-12
2966 switch (i) {
2967 case 21:
2968 i -= 1;
2969 emit_int8(0x66); // size prefix
2970 case 20:
2971 case 19:
2972 i -= 1;
2973 emit_int8(0x66); // size prefix
2974 case 18:
2975 case 17:
2976 i -= 1;
2977 emit_int8(0x66); // size prefix
2978 case 16:
2979 case 15:
2980 i -= 8;
2981 addr_nop_8();
2982 break;
2983 case 14:
2984 case 13:
2985 i -= 7;
2986 addr_nop_7();
2987 break;
2988 case 12:
2989 i -= 6;
2990 emit_int8(0x66); // size prefix
2991 addr_nop_5();
2992 break;
2993 default:
2994 assert(i < 12, " ");
2995 }
2996
2997 // Generate second nop for size between 11-1
2998 switch (i) {
2999 case 11:
3000 emit_int8(0x66); // size prefix
3001 case 10:
3002 emit_int8(0x66); // size prefix
3003 case 9:
3004 emit_int8(0x66); // size prefix
3005 case 8:
3006 addr_nop_8();
3007 break;
3008 case 7:
3009 addr_nop_7();
3010 break;
3011 case 6:
3012 emit_int8(0x66); // size prefix
3013 case 5:
3014 addr_nop_5();
3015 break;
3016 case 4:
3017 addr_nop_4();
3018 break;
3019 case 3:
3020 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
3021 emit_int8(0x66); // size prefix
3022 case 2:
3023 emit_int8(0x66); // size prefix
3024 case 1:
3025 emit_int8((unsigned char)0x90);
3026 // nop
3027 break;
3028 default:
3029 assert(i == 0, " ");
3030 }
3031 return;
3032 }
3033
3034 // Using nops with size prefixes "0x66 0x90".
3035 // From AMD Optimization Guide:
3036 // 1: 0x90
3037 // 2: 0x66 0x90
3038 // 3: 0x66 0x66 0x90
3039 // 4: 0x66 0x66 0x66 0x90
3040 // 5: 0x66 0x66 0x90 0x66 0x90
3041 // 6: 0x66 0x66 0x90 0x66 0x66 0x90
3042 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90
3043 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90
3044 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
3045 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
3046 //
3047 while(i > 12) {
3048 i -= 4;
3049 emit_int8(0x66); // size prefix
3050 emit_int8(0x66);
3051 emit_int8(0x66);
3052 emit_int8((unsigned char)0x90);
3053 // nop
3054 }
3055 // 1 - 12 nops
3056 if(i > 8) {
3057 if(i > 9) {
3058 i -= 1;
3059 emit_int8(0x66);
3060 }
3061 i -= 3;
3062 emit_int8(0x66);
3063 emit_int8(0x66);
3064 emit_int8((unsigned char)0x90);
3065 }
3066 // 1 - 8 nops
3067 if(i > 4) {
3068 if(i > 6) {
3069 i -= 1;
3070 emit_int8(0x66);
3071 }
3072 i -= 3;
3073 emit_int8(0x66);
3074 emit_int8(0x66);
3075 emit_int8((unsigned char)0x90);
3076 }
3077 switch (i) {
3078 case 4:
3079 emit_int8(0x66);
3080 case 3:
3081 emit_int8(0x66);
3082 case 2:
3083 emit_int8(0x66);
3084 case 1:
3085 emit_int8((unsigned char)0x90);
3086 break;
3087 default:
3088 assert(i == 0, " ");
3089 }
3090 }
3091
3092 void Assembler::notl(Register dst) {
3093 int encode = prefix_and_encode(dst->encoding());
3094 emit_int8((unsigned char)0xF7);
3095 emit_int8((unsigned char)(0xD0 | encode));
3096 }
3097
3098 void Assembler::orl(Address dst, int32_t imm32) {
3099 InstructionMark im(this);
3100 prefix(dst);
3101 emit_arith_operand(0x81, rcx, dst, imm32);
3102 }
3103
3104 void Assembler::orl(Register dst, int32_t imm32) {
3105 prefix(dst);
3106 emit_arith(0x81, 0xC8, dst, imm32);
3107 }
3108
3109 void Assembler::orl(Register dst, Address src) {
3110 InstructionMark im(this);
3111 prefix(src, dst);
3112 emit_int8(0x0B);
3113 emit_operand(dst, src);
3114 }
3115
3116 void Assembler::orl(Register dst, Register src) {
3117 (void) prefix_and_encode(dst->encoding(), src->encoding());
3118 emit_arith(0x0B, 0xC0, dst, src);
3119 }
3120
3121 void Assembler::orl(Address dst, Register src) {
3122 InstructionMark im(this);
3123 prefix(dst, src);
3124 emit_int8(0x09);
3125 emit_operand(src, dst);
3126 }
3127
3128 void Assembler::packuswb(XMMRegister dst, Address src) {
3129 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3130 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3131 InstructionMark im(this);
3132 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3133 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3134 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3135 emit_int8(0x67);
3136 emit_operand(dst, src);
3137 }
3138
3139 void Assembler::packuswb(XMMRegister dst, XMMRegister src) {
3140 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3141 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3142 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3143 emit_int8(0x67);
3144 emit_int8((unsigned char)(0xC0 | encode));
3145 }
3146
3147 void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3148 assert(UseAVX > 0, "some form of AVX must be enabled");
3149 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3150 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3151 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3152 emit_int8(0x67);
3153 emit_int8((unsigned char)(0xC0 | encode));
3154 }
3155
3156 void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len) {
3157 assert(VM_Version::supports_avx2(), "");
3158 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3159 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3160 emit_int8(0x00);
3161 emit_int8(0xC0 | encode);
3162 emit_int8(imm8);
3163 }
3164
3165 void Assembler::pause() {
3166 emit_int8((unsigned char)0xF3);
3167 emit_int8((unsigned char)0x90);
3168 }
3169
3170 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3171 assert(VM_Version::supports_sse4_2(), "");
3172 InstructionMark im(this);
3173 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3174 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3175 emit_int8(0x61);
3176 emit_operand(dst, src);
3177 emit_int8(imm8);
3178 }
3179
3180 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3181 assert(VM_Version::supports_sse4_2(), "");
3182 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3183 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3184 emit_int8(0x61);
3185 emit_int8((unsigned char)(0xC0 | encode));
3186 emit_int8(imm8);
3187 }
3188
3189 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3190 void Assembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
3191 assert(VM_Version::supports_sse2(), "");
3192 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3193 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3194 emit_int8(0x74);
3195 emit_int8((unsigned char)(0xC0 | encode));
3196 }
3197
3198 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3199 void Assembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3200 assert(VM_Version::supports_avx(), "");
3201 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3202 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3203 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3204 emit_int8(0x74);
3205 emit_int8((unsigned char)(0xC0 | encode));
3206 }
3207
3208 // In this context, kdst is written the mask used to process the equal components
3209 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3210 assert(VM_Version::supports_avx512bw(), "");
3211 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3212 attributes.set_is_evex_instruction();
3213 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3214 int encode = vex_prefix_and_encode(kdst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3215 emit_int8(0x74);
3216 emit_int8((unsigned char)(0xC0 | encode));
3217 }
3218
3219 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3220 assert(VM_Version::supports_avx512bw(), "");
3221 InstructionMark im(this);
3222 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3223 attributes.set_is_evex_instruction();
3224 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3225 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3226 int dst_enc = kdst->encoding();
3227 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3228 emit_int8(0x74);
3229 emit_operand(as_Register(dst_enc), src);
3230 }
3231
3232 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3233 void Assembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3234 assert(VM_Version::supports_sse2(), "");
3235 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3236 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3237 emit_int8(0x75);
3238 emit_int8((unsigned char)(0xC0 | encode));
3239 }
3240
3241 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3242 void Assembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3243 assert(VM_Version::supports_avx(), "");
3244 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3245 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3246 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3247 emit_int8(0x75);
3248 emit_int8((unsigned char)(0xC0 | encode));
3249 }
3250
3251 // In this context, kdst is written the mask used to process the equal components
3252 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3253 assert(VM_Version::supports_avx512bw(), "");
3254 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3255 attributes.set_is_evex_instruction();
3256 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3257 int encode = vex_prefix_and_encode(kdst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3258 emit_int8(0x75);
3259 emit_int8((unsigned char)(0xC0 | encode));
3260 }
3261
3262 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3263 assert(VM_Version::supports_avx512bw(), "");
3264 InstructionMark im(this);
3265 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3266 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3267 attributes.set_is_evex_instruction();
3268 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3269 int dst_enc = kdst->encoding();
3270 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3271 emit_int8(0x75);
3272 emit_operand(as_Register(dst_enc), src);
3273 }
3274
3275 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3276 void Assembler::pcmpeqd(XMMRegister dst, XMMRegister src) {
3277 assert(VM_Version::supports_sse2(), "");
3278 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3279 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3280 emit_int8(0x76);
3281 emit_int8((unsigned char)(0xC0 | encode));
3282 }
3283
3284 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3285 void Assembler::vpcmpeqd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3286 assert(VM_Version::supports_avx(), "");
3287 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3288 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3289 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3290 emit_int8(0x76);
3291 emit_int8((unsigned char)(0xC0 | encode));
3292 }
3293
3294 // In this context, kdst is written the mask used to process the equal components
3295 void Assembler::evpcmpeqd(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3296 assert(VM_Version::supports_evex(), "");
3297 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3298 attributes.set_is_evex_instruction();
3299 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3300 int encode = vex_prefix_and_encode(kdst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3301 emit_int8(0x76);
3302 emit_int8((unsigned char)(0xC0 | encode));
3303 }
3304
3305 void Assembler::evpcmpeqd(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3306 assert(VM_Version::supports_evex(), "");
3307 InstructionMark im(this);
3308 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3309 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3310 attributes.set_is_evex_instruction();
3311 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3312 int dst_enc = kdst->encoding();
3313 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3314 emit_int8(0x76);
3315 emit_operand(as_Register(dst_enc), src);
3316 }
3317
3318 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3319 void Assembler::pcmpeqq(XMMRegister dst, XMMRegister src) {
3320 assert(VM_Version::supports_sse4_1(), "");
3321 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3322 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3323 emit_int8(0x29);
3324 emit_int8((unsigned char)(0xC0 | encode));
3325 }
3326
3327 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3328 void Assembler::vpcmpeqq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3329 assert(VM_Version::supports_avx(), "");
3330 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3331 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3332 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3333 emit_int8(0x29);
3334 emit_int8((unsigned char)(0xC0 | encode));
3335 }
3336
3337 // In this context, kdst is written the mask used to process the equal components
3338 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3339 assert(VM_Version::supports_evex(), "");
3340 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3341 attributes.set_is_evex_instruction();
3342 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3343 int encode = vex_prefix_and_encode(kdst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3344 emit_int8(0x29);
3345 emit_int8((unsigned char)(0xC0 | encode));
3346 }
3347
3348 // In this context, kdst is written the mask used to process the equal components
3349 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3350 assert(VM_Version::supports_evex(), "");
3351 InstructionMark im(this);
3352 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3353 attributes.set_is_evex_instruction();
3354 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
3355 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3356 int dst_enc = kdst->encoding();
3357 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3358 emit_int8(0x29);
3359 emit_operand(as_Register(dst_enc), src);
3360 }
3361
3362 void Assembler::pmovmskb(Register dst, XMMRegister src) {
3363 assert(VM_Version::supports_sse2(), "");
3364 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3365 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3366 emit_int8((unsigned char)0xD7);
3367 emit_int8((unsigned char)(0xC0 | encode));
3368 }
3369
3370 void Assembler::vpmovmskb(Register dst, XMMRegister src) {
3371 assert(VM_Version::supports_avx2(), "");
3372 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3373 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3374 emit_int8((unsigned char)0xD7);
3375 emit_int8((unsigned char)(0xC0 | encode));
3376 }
3377
3378 void Assembler::pextrd(Register dst, XMMRegister src, int imm8) {
3379 assert(VM_Version::supports_sse4_1(), "");
3380 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3381 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3382 emit_int8(0x16);
3383 emit_int8((unsigned char)(0xC0 | encode));
3384 emit_int8(imm8);
3385 }
3386
3387 void Assembler::pextrd(Address dst, XMMRegister src, int imm8) {
3388 assert(VM_Version::supports_sse4_1(), "");
3389 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3390 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3391 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3392 emit_int8(0x16);
3393 emit_operand(src, dst);
3394 emit_int8(imm8);
3395 }
3396
3397 void Assembler::pextrq(Register dst, XMMRegister src, int imm8) {
3398 assert(VM_Version::supports_sse4_1(), "");
3399 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3400 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3401 emit_int8(0x16);
3402 emit_int8((unsigned char)(0xC0 | encode));
3403 emit_int8(imm8);
3404 }
3405
3406 void Assembler::pextrq(Address dst, XMMRegister src, int imm8) {
3407 assert(VM_Version::supports_sse4_1(), "");
3408 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3409 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3410 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3411 emit_int8(0x16);
3412 emit_operand(src, dst);
3413 emit_int8(imm8);
3414 }
3415
3416 void Assembler::pextrw(Register dst, XMMRegister src, int imm8) {
3417 assert(VM_Version::supports_sse2(), "");
3418 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3419 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3420 emit_int8((unsigned char)0xC5);
3421 emit_int8((unsigned char)(0xC0 | encode));
3422 emit_int8(imm8);
3423 }
3424
3425 void Assembler::pextrw(Address dst, XMMRegister src, int imm8) {
3426 assert(VM_Version::supports_sse4_1(), "");
3427 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3428 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
3429 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3430 emit_int8((unsigned char)0x15);
3431 emit_operand(src, dst);
3432 emit_int8(imm8);
3433 }
3434
3435 void Assembler::pextrb(Address dst, XMMRegister src, int imm8) {
3436 assert(VM_Version::supports_sse4_1(), "");
3437 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3438 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
3439 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3440 emit_int8(0x14);
3441 emit_operand(src, dst);
3442 emit_int8(imm8);
3443 }
3444
3445 void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) {
3446 assert(VM_Version::supports_sse4_1(), "");
3447 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3448 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3449 emit_int8(0x22);
3450 emit_int8((unsigned char)(0xC0 | encode));
3451 emit_int8(imm8);
3452 }
3453
3454 void Assembler::pinsrd(XMMRegister dst, Address src, int imm8) {
3455 assert(VM_Version::supports_sse4_1(), "");
3456 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3457 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3458 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3459 emit_int8(0x22);
3460 emit_operand(dst,src);
3461 emit_int8(imm8);
3462 }
3463
3464 void Assembler::pinsrq(XMMRegister dst, Register src, int imm8) {
3465 assert(VM_Version::supports_sse4_1(), "");
3466 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3467 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3468 emit_int8(0x22);
3469 emit_int8((unsigned char)(0xC0 | encode));
3470 emit_int8(imm8);
3471 }
3472
3473 void Assembler::pinsrq(XMMRegister dst, Address src, int imm8) {
3474 assert(VM_Version::supports_sse4_1(), "");
3475 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3476 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3477 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3478 emit_int8(0x22);
3479 emit_operand(dst, src);
3480 emit_int8(imm8);
3481 }
3482
3483 void Assembler::pinsrw(XMMRegister dst, Register src, int imm8) {
3484 assert(VM_Version::supports_sse2(), "");
3485 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3486 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3487 emit_int8((unsigned char)0xC4);
3488 emit_int8((unsigned char)(0xC0 | encode));
3489 emit_int8(imm8);
3490 }
3491
3492 void Assembler::pinsrw(XMMRegister dst, Address src, int imm8) {
3493 assert(VM_Version::supports_sse2(), "");
3494 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3495 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
3496 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3497 emit_int8((unsigned char)0xC4);
3498 emit_operand(dst, src);
3499 emit_int8(imm8);
3500 }
3501
3502 void Assembler::pinsrb(XMMRegister dst, Address src, int imm8) {
3503 assert(VM_Version::supports_sse4_1(), "");
3504 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3505 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
3506 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3507 emit_int8(0x20);
3508 emit_operand(dst, src);
3509 emit_int8(imm8);
3510 }
3511
3512 void Assembler::pmovzxbw(XMMRegister dst, Address src) {
3513 assert(VM_Version::supports_sse4_1(), "");
3514 InstructionMark im(this);
3515 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3516 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3517 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3518 emit_int8(0x30);
3519 emit_operand(dst, src);
3520 }
3521
3522 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3523 assert(VM_Version::supports_sse4_1(), "");
3524 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3525 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3526 emit_int8(0x30);
3527 emit_int8((unsigned char)(0xC0 | encode));
3528 }
3529
3530 void Assembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
3531 assert(VM_Version::supports_avx(), "");
3532 InstructionMark im(this);
3533 assert(dst != xnoreg, "sanity");
3534 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3535 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3536 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3537 emit_int8(0x30);
3538 emit_operand(dst, src);
3539 }
3540
3541 // generic
3542 void Assembler::pop(Register dst) {
3543 int encode = prefix_and_encode(dst->encoding());
3544 emit_int8(0x58 | encode);
3545 }
3546
3547 void Assembler::popcntl(Register dst, Address src) {
3548 assert(VM_Version::supports_popcnt(), "must support");
3549 InstructionMark im(this);
3550 emit_int8((unsigned char)0xF3);
3551 prefix(src, dst);
3552 emit_int8(0x0F);
3553 emit_int8((unsigned char)0xB8);
3554 emit_operand(dst, src);
3555 }
3556
3557 void Assembler::popcntl(Register dst, Register src) {
3558 assert(VM_Version::supports_popcnt(), "must support");
3559 emit_int8((unsigned char)0xF3);
3560 int encode = prefix_and_encode(dst->encoding(), src->encoding());
3561 emit_int8(0x0F);
3562 emit_int8((unsigned char)0xB8);
3563 emit_int8((unsigned char)(0xC0 | encode));
3564 }
3565
3566 void Assembler::popf() {
3567 emit_int8((unsigned char)0x9D);
3568 }
3569
3570 #ifndef _LP64 // no 32bit push/pop on amd64
3571 void Assembler::popl(Address dst) {
3572 // NOTE: this will adjust stack by 8byte on 64bits
3573 InstructionMark im(this);
3574 prefix(dst);
3575 emit_int8((unsigned char)0x8F);
3576 emit_operand(rax, dst);
3577 }
3578 #endif
3579
3580 void Assembler::prefetch_prefix(Address src) {
3581 prefix(src);
3582 emit_int8(0x0F);
3583 }
3584
3585 void Assembler::prefetchnta(Address src) {
3586 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3587 InstructionMark im(this);
3588 prefetch_prefix(src);
3589 emit_int8(0x18);
3590 emit_operand(rax, src); // 0, src
3591 }
3592
3593 void Assembler::prefetchr(Address src) {
3594 assert(VM_Version::supports_3dnow_prefetch(), "must support");
3595 InstructionMark im(this);
3596 prefetch_prefix(src);
3597 emit_int8(0x0D);
3598 emit_operand(rax, src); // 0, src
3599 }
3600
3601 void Assembler::prefetcht0(Address src) {
3602 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3603 InstructionMark im(this);
3604 prefetch_prefix(src);
3605 emit_int8(0x18);
3606 emit_operand(rcx, src); // 1, src
3607 }
3608
3609 void Assembler::prefetcht1(Address src) {
3610 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3611 InstructionMark im(this);
3612 prefetch_prefix(src);
3613 emit_int8(0x18);
3614 emit_operand(rdx, src); // 2, src
3615 }
3616
3617 void Assembler::prefetcht2(Address src) {
3618 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3619 InstructionMark im(this);
3620 prefetch_prefix(src);
3621 emit_int8(0x18);
3622 emit_operand(rbx, src); // 3, src
3623 }
3624
3625 void Assembler::prefetchw(Address src) {
3626 assert(VM_Version::supports_3dnow_prefetch(), "must support");
3627 InstructionMark im(this);
3628 prefetch_prefix(src);
3629 emit_int8(0x0D);
3630 emit_operand(rcx, src); // 1, src
3631 }
3632
3633 void Assembler::prefix(Prefix p) {
3634 emit_int8(p);
3635 }
3636
3637 void Assembler::pshufb(XMMRegister dst, XMMRegister src) {
3638 assert(VM_Version::supports_ssse3(), "");
3639 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3640 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3641 emit_int8(0x00);
3642 emit_int8((unsigned char)(0xC0 | encode));
3643 }
3644
3645 void Assembler::pshufb(XMMRegister dst, Address src) {
3646 assert(VM_Version::supports_ssse3(), "");
3647 InstructionMark im(this);
3648 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3649 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3650 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3651 emit_int8(0x00);
3652 emit_operand(dst, src);
3653 }
3654
3655 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
3656 assert(isByte(mode), "invalid value");
3657 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3658 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
3659 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3660 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3661 emit_int8(0x70);
3662 emit_int8((unsigned char)(0xC0 | encode));
3663 emit_int8(mode & 0xFF);
3664 }
3665
3666 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
3667 assert(isByte(mode), "invalid value");
3668 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3669 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3670 InstructionMark im(this);
3671 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3672 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3673 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3674 emit_int8(0x70);
3675 emit_operand(dst, src);
3676 emit_int8(mode & 0xFF);
3677 }
3678
3679 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
3680 assert(isByte(mode), "invalid value");
3681 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3682 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3683 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3684 emit_int8(0x70);
3685 emit_int8((unsigned char)(0xC0 | encode));
3686 emit_int8(mode & 0xFF);
3687 }
3688
3689 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
3690 assert(isByte(mode), "invalid value");
3691 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3692 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3693 InstructionMark im(this);
3694 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3695 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3696 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3697 emit_int8(0x70);
3698 emit_operand(dst, src);
3699 emit_int8(mode & 0xFF);
3700 }
3701
3702 void Assembler::psrldq(XMMRegister dst, int shift) {
3703 // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
3704 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3705 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3706 // XMM3 is for /3 encoding: 66 0F 73 /3 ib
3707 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3708 emit_int8(0x73);
3709 emit_int8((unsigned char)(0xC0 | encode));
3710 emit_int8(shift);
3711 }
3712
3713 void Assembler::pslldq(XMMRegister dst, int shift) {
3714 // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
3715 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3716 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3717 // XMM7 is for /7 encoding: 66 0F 73 /7 ib
3718 int encode = simd_prefix_and_encode(xmm7, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3719 emit_int8(0x73);
3720 emit_int8((unsigned char)(0xC0 | encode));
3721 emit_int8(shift);
3722 }
3723
3724 void Assembler::ptest(XMMRegister dst, Address src) {
3725 assert(VM_Version::supports_sse4_1(), "");
3726 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3727 InstructionMark im(this);
3728 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3729 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3730 emit_int8(0x17);
3731 emit_operand(dst, src);
3732 }
3733
3734 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
3735 assert(VM_Version::supports_sse4_1(), "");
3736 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3737 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3738 emit_int8(0x17);
3739 emit_int8((unsigned char)(0xC0 | encode));
3740 }
3741
3742 void Assembler::vptest(XMMRegister dst, Address src) {
3743 assert(VM_Version::supports_avx(), "");
3744 InstructionMark im(this);
3745 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3746 assert(dst != xnoreg, "sanity");
3747 // swap src<->dst for encoding
3748 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3749 emit_int8(0x17);
3750 emit_operand(dst, src);
3751 }
3752
3753 void Assembler::vptest(XMMRegister dst, XMMRegister src) {
3754 assert(VM_Version::supports_avx(), "");
3755 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3756 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3757 emit_int8(0x17);
3758 emit_int8((unsigned char)(0xC0 | encode));
3759 }
3760
3761 void Assembler::punpcklbw(XMMRegister dst, Address src) {
3762 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3763 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3764 InstructionMark im(this);
3765 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ false, /* uses_vl */ true);
3766 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3767 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3768 emit_int8(0x60);
3769 emit_operand(dst, src);
3770 }
3771
3772 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
3773 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3774 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ false, /* uses_vl */ true);
3775 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3776 emit_int8(0x60);
3777 emit_int8((unsigned char)(0xC0 | encode));
3778 }
3779
3780 void Assembler::punpckldq(XMMRegister dst, Address src) {
3781 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3782 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3783 InstructionMark im(this);
3784 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3785 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3786 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3787 emit_int8(0x62);
3788 emit_operand(dst, src);
3789 }
3790
3791 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) {
3792 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3793 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3794 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3795 emit_int8(0x62);
3796 emit_int8((unsigned char)(0xC0 | encode));
3797 }
3798
3799 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) {
3800 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3801 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3802 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3803 emit_int8(0x6C);
3804 emit_int8((unsigned char)(0xC0 | encode));
3805 }
3806
3807 void Assembler::push(int32_t imm32) {
3808 // in 64bits we push 64bits onto the stack but only
3809 // take a 32bit immediate
3810 emit_int8(0x68);
3811 emit_int32(imm32);
3812 }
3813
3814 void Assembler::push(Register src) {
3815 int encode = prefix_and_encode(src->encoding());
3816
3817 emit_int8(0x50 | encode);
3818 }
3819
3820 void Assembler::pushf() {
3821 emit_int8((unsigned char)0x9C);
3822 }
3823
3824 #ifndef _LP64 // no 32bit push/pop on amd64
3825 void Assembler::pushl(Address src) {
3826 // Note this will push 64bit on 64bit
3827 InstructionMark im(this);
3828 prefix(src);
3829 emit_int8((unsigned char)0xFF);
3830 emit_operand(rsi, src);
3831 }
3832 #endif
3833
3834 void Assembler::rcll(Register dst, int imm8) {
3835 assert(isShiftCount(imm8), "illegal shift count");
3836 int encode = prefix_and_encode(dst->encoding());
3837 if (imm8 == 1) {
3838 emit_int8((unsigned char)0xD1);
3839 emit_int8((unsigned char)(0xD0 | encode));
3840 } else {
3841 emit_int8((unsigned char)0xC1);
3842 emit_int8((unsigned char)0xD0 | encode);
3843 emit_int8(imm8);
3844 }
3845 }
3846
3847 void Assembler::rcpps(XMMRegister dst, XMMRegister src) {
3848 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3849 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3850 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
3851 emit_int8(0x53);
3852 emit_int8((unsigned char)(0xC0 | encode));
3853 }
3854
3855 void Assembler::rcpss(XMMRegister dst, XMMRegister src) {
3856 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3857 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3858 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3859 emit_int8(0x53);
3860 emit_int8((unsigned char)(0xC0 | encode));
3861 }
3862
3863 void Assembler::rdtsc() {
3864 emit_int8((unsigned char)0x0F);
3865 emit_int8((unsigned char)0x31);
3866 }
3867
3868 // copies data from [esi] to [edi] using rcx pointer sized words
3869 // generic
3870 void Assembler::rep_mov() {
3871 emit_int8((unsigned char)0xF3);
3872 // MOVSQ
3873 LP64_ONLY(prefix(REX_W));
3874 emit_int8((unsigned char)0xA5);
3875 }
3876
3877 // sets rcx bytes with rax, value at [edi]
3878 void Assembler::rep_stosb() {
3879 emit_int8((unsigned char)0xF3); // REP
3880 LP64_ONLY(prefix(REX_W));
3881 emit_int8((unsigned char)0xAA); // STOSB
3882 }
3883
3884 // sets rcx pointer sized words with rax, value at [edi]
3885 // generic
3886 void Assembler::rep_stos() {
3887 emit_int8((unsigned char)0xF3); // REP
3888 LP64_ONLY(prefix(REX_W)); // LP64:STOSQ, LP32:STOSD
3889 emit_int8((unsigned char)0xAB);
3890 }
3891
3892 // scans rcx pointer sized words at [edi] for occurance of rax,
3893 // generic
3894 void Assembler::repne_scan() { // repne_scan
3895 emit_int8((unsigned char)0xF2);
3896 // SCASQ
3897 LP64_ONLY(prefix(REX_W));
3898 emit_int8((unsigned char)0xAF);
3899 }
3900
3901 #ifdef _LP64
3902 // scans rcx 4 byte words at [edi] for occurance of rax,
3903 // generic
3904 void Assembler::repne_scanl() { // repne_scan
3905 emit_int8((unsigned char)0xF2);
3906 // SCASL
3907 emit_int8((unsigned char)0xAF);
3908 }
3909 #endif
3910
3911 void Assembler::ret(int imm16) {
3912 if (imm16 == 0) {
3913 emit_int8((unsigned char)0xC3);
3914 } else {
3915 emit_int8((unsigned char)0xC2);
3916 emit_int16(imm16);
3917 }
3918 }
3919
3920 void Assembler::sahf() {
3921 #ifdef _LP64
3922 // Not supported in 64bit mode
3923 ShouldNotReachHere();
3924 #endif
3925 emit_int8((unsigned char)0x9E);
3926 }
3927
3928 void Assembler::sarl(Register dst, int imm8) {
3929 int encode = prefix_and_encode(dst->encoding());
3930 assert(isShiftCount(imm8), "illegal shift count");
3931 if (imm8 == 1) {
3932 emit_int8((unsigned char)0xD1);
3933 emit_int8((unsigned char)(0xF8 | encode));
3934 } else {
3935 emit_int8((unsigned char)0xC1);
3936 emit_int8((unsigned char)(0xF8 | encode));
3937 emit_int8(imm8);
3938 }
3939 }
3940
3941 void Assembler::sarl(Register dst) {
3942 int encode = prefix_and_encode(dst->encoding());
3943 emit_int8((unsigned char)0xD3);
3944 emit_int8((unsigned char)(0xF8 | encode));
3945 }
3946
3947 void Assembler::sbbl(Address dst, int32_t imm32) {
3948 InstructionMark im(this);
3949 prefix(dst);
3950 emit_arith_operand(0x81, rbx, dst, imm32);
3951 }
3952
3953 void Assembler::sbbl(Register dst, int32_t imm32) {
3954 prefix(dst);
3955 emit_arith(0x81, 0xD8, dst, imm32);
3956 }
3957
3958
3959 void Assembler::sbbl(Register dst, Address src) {
3960 InstructionMark im(this);
3961 prefix(src, dst);
3962 emit_int8(0x1B);
3963 emit_operand(dst, src);
3964 }
3965
3966 void Assembler::sbbl(Register dst, Register src) {
3967 (void) prefix_and_encode(dst->encoding(), src->encoding());
3968 emit_arith(0x1B, 0xC0, dst, src);
3969 }
3970
3971 void Assembler::setb(Condition cc, Register dst) {
3972 assert(0 <= cc && cc < 16, "illegal cc");
3973 int encode = prefix_and_encode(dst->encoding(), true);
3974 emit_int8(0x0F);
3975 emit_int8((unsigned char)0x90 | cc);
3976 emit_int8((unsigned char)(0xC0 | encode));
3977 }
3978
3979 void Assembler::palignr(XMMRegister dst, XMMRegister src, int imm8) {
3980 assert(VM_Version::supports_ssse3(), "");
3981 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ false);
3982 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3983 emit_int8((unsigned char)0x0F);
3984 emit_int8((unsigned char)(0xC0 | encode));
3985 emit_int8(imm8);
3986 }
3987
3988 void Assembler::pblendw(XMMRegister dst, XMMRegister src, int imm8) {
3989 assert(VM_Version::supports_sse4_1(), "");
3990 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3991 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3992 emit_int8((unsigned char)0x0E);
3993 emit_int8((unsigned char)(0xC0 | encode));
3994 emit_int8(imm8);
3995 }
3996
3997 void Assembler::sha1rnds4(XMMRegister dst, XMMRegister src, int imm8) {
3998 assert(VM_Version::supports_sha(), "");
3999 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4000 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_3A, &attributes);
4001 emit_int8((unsigned char)0xCC);
4002 emit_int8((unsigned char)(0xC0 | encode));
4003 emit_int8((unsigned char)imm8);
4004 }
4005
4006 void Assembler::sha1nexte(XMMRegister dst, XMMRegister src) {
4007 assert(VM_Version::supports_sha(), "");
4008 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4009 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4010 emit_int8((unsigned char)0xC8);
4011 emit_int8((unsigned char)(0xC0 | encode));
4012 }
4013
4014 void Assembler::sha1msg1(XMMRegister dst, XMMRegister src) {
4015 assert(VM_Version::supports_sha(), "");
4016 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4017 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4018 emit_int8((unsigned char)0xC9);
4019 emit_int8((unsigned char)(0xC0 | encode));
4020 }
4021
4022 void Assembler::sha1msg2(XMMRegister dst, XMMRegister src) {
4023 assert(VM_Version::supports_sha(), "");
4024 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4025 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4026 emit_int8((unsigned char)0xCA);
4027 emit_int8((unsigned char)(0xC0 | encode));
4028 }
4029
4030 // xmm0 is implicit additional source to this instruction.
4031 void Assembler::sha256rnds2(XMMRegister dst, XMMRegister src) {
4032 assert(VM_Version::supports_sha(), "");
4033 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4034 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4035 emit_int8((unsigned char)0xCB);
4036 emit_int8((unsigned char)(0xC0 | encode));
4037 }
4038
4039 void Assembler::sha256msg1(XMMRegister dst, XMMRegister src) {
4040 assert(VM_Version::supports_sha(), "");
4041 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4042 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4043 emit_int8((unsigned char)0xCC);
4044 emit_int8((unsigned char)(0xC0 | encode));
4045 }
4046
4047 void Assembler::sha256msg2(XMMRegister dst, XMMRegister src) {
4048 assert(VM_Version::supports_sha(), "");
4049 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4050 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4051 emit_int8((unsigned char)0xCD);
4052 emit_int8((unsigned char)(0xC0 | encode));
4053 }
4054
4055
4056 void Assembler::shll(Register dst, int imm8) {
4057 assert(isShiftCount(imm8), "illegal shift count");
4058 int encode = prefix_and_encode(dst->encoding());
4059 if (imm8 == 1 ) {
4060 emit_int8((unsigned char)0xD1);
4061 emit_int8((unsigned char)(0xE0 | encode));
4062 } else {
4063 emit_int8((unsigned char)0xC1);
4064 emit_int8((unsigned char)(0xE0 | encode));
4065 emit_int8(imm8);
4066 }
4067 }
4068
4069 void Assembler::shll(Register dst) {
4070 int encode = prefix_and_encode(dst->encoding());
4071 emit_int8((unsigned char)0xD3);
4072 emit_int8((unsigned char)(0xE0 | encode));
4073 }
4074
4075 void Assembler::shrl(Register dst, int imm8) {
4076 assert(isShiftCount(imm8), "illegal shift count");
4077 int encode = prefix_and_encode(dst->encoding());
4078 emit_int8((unsigned char)0xC1);
4079 emit_int8((unsigned char)(0xE8 | encode));
4080 emit_int8(imm8);
4081 }
4082
4083 void Assembler::shrl(Register dst) {
4084 int encode = prefix_and_encode(dst->encoding());
4085 emit_int8((unsigned char)0xD3);
4086 emit_int8((unsigned char)(0xE8 | encode));
4087 }
4088
4089 // copies a single word from [esi] to [edi]
4090 void Assembler::smovl() {
4091 emit_int8((unsigned char)0xA5);
4092 }
4093
4094 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
4095 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4096 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4097 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4098 emit_int8(0x51);
4099 emit_int8((unsigned char)(0xC0 | encode));
4100 }
4101
4102 void Assembler::sqrtsd(XMMRegister dst, Address src) {
4103 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4104 InstructionMark im(this);
4105 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4106 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4107 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4108 emit_int8(0x51);
4109 emit_operand(dst, src);
4110 }
4111
4112 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
4113 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4114 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4115 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4116 emit_int8(0x51);
4117 emit_int8((unsigned char)(0xC0 | encode));
4118 }
4119
4120 void Assembler::std() {
4121 emit_int8((unsigned char)0xFD);
4122 }
4123
4124 void Assembler::sqrtss(XMMRegister dst, Address src) {
4125 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4126 InstructionMark im(this);
4127 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4128 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4129 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4130 emit_int8(0x51);
4131 emit_operand(dst, src);
4132 }
4133
4134 void Assembler::stmxcsr( Address dst) {
4135 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4136 InstructionMark im(this);
4137 prefix(dst);
4138 emit_int8(0x0F);
4139 emit_int8((unsigned char)0xAE);
4140 emit_operand(as_Register(3), dst);
4141 }
4142
4143 void Assembler::subl(Address dst, int32_t imm32) {
4144 InstructionMark im(this);
4145 prefix(dst);
4146 emit_arith_operand(0x81, rbp, dst, imm32);
4147 }
4148
4149 void Assembler::subl(Address dst, Register src) {
4150 InstructionMark im(this);
4151 prefix(dst, src);
4152 emit_int8(0x29);
4153 emit_operand(src, dst);
4154 }
4155
4156 void Assembler::subl(Register dst, int32_t imm32) {
4157 prefix(dst);
4158 emit_arith(0x81, 0xE8, dst, imm32);
4159 }
4160
4161 // Force generation of a 4 byte immediate value even if it fits into 8bit
4162 void Assembler::subl_imm32(Register dst, int32_t imm32) {
4163 prefix(dst);
4164 emit_arith_imm32(0x81, 0xE8, dst, imm32);
4165 }
4166
4167 void Assembler::subl(Register dst, Address src) {
4168 InstructionMark im(this);
4169 prefix(src, dst);
4170 emit_int8(0x2B);
4171 emit_operand(dst, src);
4172 }
4173
4174 void Assembler::subl(Register dst, Register src) {
4175 (void) prefix_and_encode(dst->encoding(), src->encoding());
4176 emit_arith(0x2B, 0xC0, dst, src);
4177 }
4178
4179 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
4180 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4181 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4182 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4183 emit_int8(0x5C);
4184 emit_int8((unsigned char)(0xC0 | encode));
4185 }
4186
4187 void Assembler::subsd(XMMRegister dst, Address src) {
4188 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4189 InstructionMark im(this);
4190 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4191 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4192 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4193 emit_int8(0x5C);
4194 emit_operand(dst, src);
4195 }
4196
4197 void Assembler::subss(XMMRegister dst, XMMRegister src) {
4198 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4199 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false , /* uses_vl */ false);
4200 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4201 emit_int8(0x5C);
4202 emit_int8((unsigned char)(0xC0 | encode));
4203 }
4204
4205 void Assembler::subss(XMMRegister dst, Address src) {
4206 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4207 InstructionMark im(this);
4208 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4209 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4210 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4211 emit_int8(0x5C);
4212 emit_operand(dst, src);
4213 }
4214
4215 void Assembler::testb(Register dst, int imm8) {
4216 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
4217 (void) prefix_and_encode(dst->encoding(), true);
4218 emit_arith_b(0xF6, 0xC0, dst, imm8);
4219 }
4220
4221 void Assembler::testb(Address dst, int imm8) {
4222 InstructionMark im(this);
4223 prefix(dst);
4224 emit_int8((unsigned char)0xF6);
4225 emit_operand(rax, dst, 1);
4226 emit_int8(imm8);
4227 }
4228
4229 void Assembler::testl(Register dst, int32_t imm32) {
4230 // not using emit_arith because test
4231 // doesn't support sign-extension of
4232 // 8bit operands
4233 int encode = dst->encoding();
4234 if (encode == 0) {
4235 emit_int8((unsigned char)0xA9);
4236 } else {
4237 encode = prefix_and_encode(encode);
4238 emit_int8((unsigned char)0xF7);
4239 emit_int8((unsigned char)(0xC0 | encode));
4240 }
4241 emit_int32(imm32);
4242 }
4243
4244 void Assembler::testl(Register dst, Register src) {
4245 (void) prefix_and_encode(dst->encoding(), src->encoding());
4246 emit_arith(0x85, 0xC0, dst, src);
4247 }
4248
4249 void Assembler::testl(Register dst, Address src) {
4250 InstructionMark im(this);
4251 prefix(src, dst);
4252 emit_int8((unsigned char)0x85);
4253 emit_operand(dst, src);
4254 }
4255
4256 void Assembler::tzcntl(Register dst, Register src) {
4257 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
4258 emit_int8((unsigned char)0xF3);
4259 int encode = prefix_and_encode(dst->encoding(), src->encoding());
4260 emit_int8(0x0F);
4261 emit_int8((unsigned char)0xBC);
4262 emit_int8((unsigned char)0xC0 | encode);
4263 }
4264
4265 void Assembler::tzcntq(Register dst, Register src) {
4266 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
4267 emit_int8((unsigned char)0xF3);
4268 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4269 emit_int8(0x0F);
4270 emit_int8((unsigned char)0xBC);
4271 emit_int8((unsigned char)(0xC0 | encode));
4272 }
4273
4274 void Assembler::ucomisd(XMMRegister dst, Address src) {
4275 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4276 InstructionMark im(this);
4277 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4278 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4279 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4280 emit_int8(0x2E);
4281 emit_operand(dst, src);
4282 }
4283
4284 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
4285 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4286 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4287 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4288 emit_int8(0x2E);
4289 emit_int8((unsigned char)(0xC0 | encode));
4290 }
4291
4292 void Assembler::ucomiss(XMMRegister dst, Address src) {
4293 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4294 InstructionMark im(this);
4295 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4296 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4297 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4298 emit_int8(0x2E);
4299 emit_operand(dst, src);
4300 }
4301
4302 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
4303 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4304 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4305 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4306 emit_int8(0x2E);
4307 emit_int8((unsigned char)(0xC0 | encode));
4308 }
4309
4310 void Assembler::xabort(int8_t imm8) {
4311 emit_int8((unsigned char)0xC6);
4312 emit_int8((unsigned char)0xF8);
4313 emit_int8((unsigned char)(imm8 & 0xFF));
4314 }
4315
4316 void Assembler::xaddl(Address dst, Register src) {
4317 InstructionMark im(this);
4318 prefix(dst, src);
4319 emit_int8(0x0F);
4320 emit_int8((unsigned char)0xC1);
4321 emit_operand(src, dst);
4322 }
4323
4324 void Assembler::xbegin(Label& abort, relocInfo::relocType rtype) {
4325 InstructionMark im(this);
4326 relocate(rtype);
4327 if (abort.is_bound()) {
4328 address entry = target(abort);
4329 assert(entry != NULL, "abort entry NULL");
4330 intptr_t offset = entry - pc();
4331 emit_int8((unsigned char)0xC7);
4332 emit_int8((unsigned char)0xF8);
4333 emit_int32(offset - 6); // 2 opcode + 4 address
4334 } else {
4335 abort.add_patch_at(code(), locator());
4336 emit_int8((unsigned char)0xC7);
4337 emit_int8((unsigned char)0xF8);
4338 emit_int32(0);
4339 }
4340 }
4341
4342 void Assembler::xchgl(Register dst, Address src) { // xchg
4343 InstructionMark im(this);
4344 prefix(src, dst);
4345 emit_int8((unsigned char)0x87);
4346 emit_operand(dst, src);
4347 }
4348
4349 void Assembler::xchgl(Register dst, Register src) {
4350 int encode = prefix_and_encode(dst->encoding(), src->encoding());
4351 emit_int8((unsigned char)0x87);
4352 emit_int8((unsigned char)(0xC0 | encode));
4353 }
4354
4355 void Assembler::xend() {
4356 emit_int8((unsigned char)0x0F);
4357 emit_int8((unsigned char)0x01);
4358 emit_int8((unsigned char)0xD5);
4359 }
4360
4361 void Assembler::xgetbv() {
4362 emit_int8(0x0F);
4363 emit_int8(0x01);
4364 emit_int8((unsigned char)0xD0);
4365 }
4366
4367 void Assembler::xorl(Register dst, int32_t imm32) {
4368 prefix(dst);
4369 emit_arith(0x81, 0xF0, dst, imm32);
4370 }
4371
4372 void Assembler::xorl(Register dst, Address src) {
4373 InstructionMark im(this);
4374 prefix(src, dst);
4375 emit_int8(0x33);
4376 emit_operand(dst, src);
4377 }
4378
4379 void Assembler::xorl(Register dst, Register src) {
4380 (void) prefix_and_encode(dst->encoding(), src->encoding());
4381 emit_arith(0x33, 0xC0, dst, src);
4382 }
4383
4384 void Assembler::xorb(Register dst, Address src) {
4385 InstructionMark im(this);
4386 prefix(src, dst);
4387 emit_int8(0x32);
4388 emit_operand(dst, src);
4389 }
4390
4391 // AVX 3-operands scalar float-point arithmetic instructions
4392
4393 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) {
4394 assert(VM_Version::supports_avx(), "");
4395 InstructionMark im(this);
4396 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4397 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4398 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4399 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4400 emit_int8(0x58);
4401 emit_operand(dst, src);
4402 }
4403
4404 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4405 assert(VM_Version::supports_avx(), "");
4406 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4407 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4408 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4409 emit_int8(0x58);
4410 emit_int8((unsigned char)(0xC0 | encode));
4411 }
4412
4413 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) {
4414 assert(VM_Version::supports_avx(), "");
4415 InstructionMark im(this);
4416 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4417 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4418 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4419 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4420 emit_int8(0x58);
4421 emit_operand(dst, src);
4422 }
4423
4424 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4425 assert(VM_Version::supports_avx(), "");
4426 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4427 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4428 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4429 emit_int8(0x58);
4430 emit_int8((unsigned char)(0xC0 | encode));
4431 }
4432
4433 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) {
4434 assert(VM_Version::supports_avx(), "");
4435 InstructionMark im(this);
4436 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4437 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4438 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4439 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4440 emit_int8(0x5E);
4441 emit_operand(dst, src);
4442 }
4443
4444 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4445 assert(VM_Version::supports_avx(), "");
4446 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4447 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4448 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4449 emit_int8(0x5E);
4450 emit_int8((unsigned char)(0xC0 | encode));
4451 }
4452
4453 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) {
4454 assert(VM_Version::supports_avx(), "");
4455 InstructionMark im(this);
4456 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4457 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4458 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4459 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4460 emit_int8(0x5E);
4461 emit_operand(dst, src);
4462 }
4463
4464 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4465 assert(VM_Version::supports_avx(), "");
4466 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4467 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4468 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4469 emit_int8(0x5E);
4470 emit_int8((unsigned char)(0xC0 | encode));
4471 }
4472
4473 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) {
4474 assert(VM_Version::supports_avx(), "");
4475 InstructionMark im(this);
4476 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4477 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4478 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4479 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4480 emit_int8(0x59);
4481 emit_operand(dst, src);
4482 }
4483
4484 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4485 assert(VM_Version::supports_avx(), "");
4486 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4487 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4488 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4489 emit_int8(0x59);
4490 emit_int8((unsigned char)(0xC0 | encode));
4491 }
4492
4493 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) {
4494 assert(VM_Version::supports_avx(), "");
4495 InstructionMark im(this);
4496 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4497 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4498 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4499 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4500 emit_int8(0x59);
4501 emit_operand(dst, src);
4502 }
4503
4504 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4505 assert(VM_Version::supports_avx(), "");
4506 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4507 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4508 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4509 emit_int8(0x59);
4510 emit_int8((unsigned char)(0xC0 | encode));
4511 }
4512
4513 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) {
4514 assert(VM_Version::supports_avx(), "");
4515 InstructionMark im(this);
4516 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4517 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4518 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4519 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4520 emit_int8(0x5C);
4521 emit_operand(dst, src);
4522 }
4523
4524 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4525 assert(VM_Version::supports_avx(), "");
4526 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4527 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4528 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4529 emit_int8(0x5C);
4530 emit_int8((unsigned char)(0xC0 | encode));
4531 }
4532
4533 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) {
4534 assert(VM_Version::supports_avx(), "");
4535 InstructionMark im(this);
4536 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4537 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4538 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4539 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4540 emit_int8(0x5C);
4541 emit_operand(dst, src);
4542 }
4543
4544 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4545 assert(VM_Version::supports_avx(), "");
4546 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4547 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4548 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4549 emit_int8(0x5C);
4550 emit_int8((unsigned char)(0xC0 | encode));
4551 }
4552
4553 //====================VECTOR ARITHMETIC=====================================
4554
4555 // Float-point vector arithmetic
4556
4557 void Assembler::addpd(XMMRegister dst, XMMRegister src) {
4558 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4559 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4560 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4561 emit_int8(0x58);
4562 emit_int8((unsigned char)(0xC0 | encode));
4563 }
4564
4565 void Assembler::addpd(XMMRegister dst, Address src) {
4566 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4567 InstructionMark im(this);
4568 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4569 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4570 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4571 emit_int8(0x58);
4572 emit_operand(dst, src);
4573 }
4574
4575
4576 void Assembler::addps(XMMRegister dst, XMMRegister src) {
4577 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4578 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4579 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4580 emit_int8(0x58);
4581 emit_int8((unsigned char)(0xC0 | encode));
4582 }
4583
4584 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4585 assert(VM_Version::supports_avx(), "");
4586 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4587 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4588 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4589 emit_int8(0x58);
4590 emit_int8((unsigned char)(0xC0 | encode));
4591 }
4592
4593 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4594 assert(VM_Version::supports_avx(), "");
4595 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4596 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4597 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4598 emit_int8(0x58);
4599 emit_int8((unsigned char)(0xC0 | encode));
4600 }
4601
4602 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4603 assert(VM_Version::supports_avx(), "");
4604 InstructionMark im(this);
4605 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4606 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4607 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4608 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4609 emit_int8(0x58);
4610 emit_operand(dst, src);
4611 }
4612
4613 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4614 assert(VM_Version::supports_avx(), "");
4615 InstructionMark im(this);
4616 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4617 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4618 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4619 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4620 emit_int8(0x58);
4621 emit_operand(dst, src);
4622 }
4623
4624 void Assembler::subpd(XMMRegister dst, XMMRegister src) {
4625 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4626 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4627 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4628 emit_int8(0x5C);
4629 emit_int8((unsigned char)(0xC0 | encode));
4630 }
4631
4632 void Assembler::subps(XMMRegister dst, XMMRegister src) {
4633 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4634 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4635 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4636 emit_int8(0x5C);
4637 emit_int8((unsigned char)(0xC0 | encode));
4638 }
4639
4640 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4641 assert(VM_Version::supports_avx(), "");
4642 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4643 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4644 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4645 emit_int8(0x5C);
4646 emit_int8((unsigned char)(0xC0 | encode));
4647 }
4648
4649 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4650 assert(VM_Version::supports_avx(), "");
4651 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4652 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4653 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4654 emit_int8(0x5C);
4655 emit_int8((unsigned char)(0xC0 | encode));
4656 }
4657
4658 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4659 assert(VM_Version::supports_avx(), "");
4660 InstructionMark im(this);
4661 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4662 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4663 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4664 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4665 emit_int8(0x5C);
4666 emit_operand(dst, src);
4667 }
4668
4669 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4670 assert(VM_Version::supports_avx(), "");
4671 InstructionMark im(this);
4672 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4673 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4674 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4675 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4676 emit_int8(0x5C);
4677 emit_operand(dst, src);
4678 }
4679
4680 void Assembler::mulpd(XMMRegister dst, XMMRegister src) {
4681 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4682 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4683 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4684 emit_int8(0x59);
4685 emit_int8((unsigned char)(0xC0 | encode));
4686 }
4687
4688 void Assembler::mulpd(XMMRegister dst, Address src) {
4689 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4690 InstructionMark im(this);
4691 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4692 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4693 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4694 emit_int8(0x59);
4695 emit_operand(dst, src);
4696 }
4697
4698 void Assembler::mulps(XMMRegister dst, XMMRegister src) {
4699 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4700 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4701 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4702 emit_int8(0x59);
4703 emit_int8((unsigned char)(0xC0 | encode));
4704 }
4705
4706 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4707 assert(VM_Version::supports_avx(), "");
4708 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4709 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4710 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4711 emit_int8(0x59);
4712 emit_int8((unsigned char)(0xC0 | encode));
4713 }
4714
4715 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4716 assert(VM_Version::supports_avx(), "");
4717 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4718 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4719 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4720 emit_int8(0x59);
4721 emit_int8((unsigned char)(0xC0 | encode));
4722 }
4723
4724 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4725 assert(VM_Version::supports_avx(), "");
4726 InstructionMark im(this);
4727 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4728 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4729 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4730 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4731 emit_int8(0x59);
4732 emit_operand(dst, src);
4733 }
4734
4735 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4736 assert(VM_Version::supports_avx(), "");
4737 InstructionMark im(this);
4738 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4739 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4740 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4741 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4742 emit_int8(0x59);
4743 emit_operand(dst, src);
4744 }
4745
4746 void Assembler::divpd(XMMRegister dst, XMMRegister src) {
4747 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4748 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4749 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4750 emit_int8(0x5E);
4751 emit_int8((unsigned char)(0xC0 | encode));
4752 }
4753
4754 void Assembler::divps(XMMRegister dst, XMMRegister src) {
4755 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4756 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4757 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4758 emit_int8(0x5E);
4759 emit_int8((unsigned char)(0xC0 | encode));
4760 }
4761
4762 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4763 assert(VM_Version::supports_avx(), "");
4764 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4765 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4766 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4767 emit_int8(0x5E);
4768 emit_int8((unsigned char)(0xC0 | encode));
4769 }
4770
4771 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4772 assert(VM_Version::supports_avx(), "");
4773 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4774 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4775 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4776 emit_int8(0x5E);
4777 emit_int8((unsigned char)(0xC0 | encode));
4778 }
4779
4780 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4781 assert(VM_Version::supports_avx(), "");
4782 InstructionMark im(this);
4783 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4784 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4785 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4786 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4787 emit_int8(0x5E);
4788 emit_operand(dst, src);
4789 }
4790
4791 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4792 assert(VM_Version::supports_avx(), "");
4793 InstructionMark im(this);
4794 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4795 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4796 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4797 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4798 emit_int8(0x5E);
4799 emit_operand(dst, src);
4800 }
4801
4802 void Assembler::vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len) {
4803 assert(VM_Version::supports_avx(), "");
4804 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4805 int nds_enc = 0;
4806 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4807 emit_int8(0x51);
4808 emit_int8((unsigned char)(0xC0 | encode));
4809 }
4810
4811 void Assembler::vsqrtpd(XMMRegister dst, Address src, int vector_len) {
4812 assert(VM_Version::supports_avx(), "");
4813 InstructionMark im(this);
4814 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4815 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4816 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4817 emit_int8(0x51);
4818 emit_operand(dst, src);
4819 }
4820
4821 void Assembler::andpd(XMMRegister dst, XMMRegister src) {
4822 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4823 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4824 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4825 emit_int8(0x54);
4826 emit_int8((unsigned char)(0xC0 | encode));
4827 }
4828
4829 void Assembler::andps(XMMRegister dst, XMMRegister src) {
4830 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4831 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4832 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4833 emit_int8(0x54);
4834 emit_int8((unsigned char)(0xC0 | encode));
4835 }
4836
4837 void Assembler::andps(XMMRegister dst, Address src) {
4838 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4839 InstructionMark im(this);
4840 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4841 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4842 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4843 emit_int8(0x54);
4844 emit_operand(dst, src);
4845 }
4846
4847 void Assembler::andpd(XMMRegister dst, Address src) {
4848 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4849 InstructionMark im(this);
4850 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4851 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4852 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4853 emit_int8(0x54);
4854 emit_operand(dst, src);
4855 }
4856
4857 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4858 assert(VM_Version::supports_avx(), "");
4859 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4860 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4861 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4862 emit_int8(0x54);
4863 emit_int8((unsigned char)(0xC0 | encode));
4864 }
4865
4866 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4867 assert(VM_Version::supports_avx(), "");
4868 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4869 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4870 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4871 emit_int8(0x54);
4872 emit_int8((unsigned char)(0xC0 | encode));
4873 }
4874
4875 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4876 assert(VM_Version::supports_avx(), "");
4877 InstructionMark im(this);
4878 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4879 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4880 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4881 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4882 emit_int8(0x54);
4883 emit_operand(dst, src);
4884 }
4885
4886 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4887 assert(VM_Version::supports_avx(), "");
4888 InstructionMark im(this);
4889 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4890 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4891 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4892 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4893 emit_int8(0x54);
4894 emit_operand(dst, src);
4895 }
4896
4897 void Assembler::unpckhpd(XMMRegister dst, XMMRegister src) {
4898 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4899 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4900 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4901 emit_int8(0x15);
4902 emit_int8((unsigned char)(0xC0 | encode));
4903 }
4904
4905 void Assembler::unpcklpd(XMMRegister dst, XMMRegister src) {
4906 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4907 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4908 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4909 emit_int8(0x14);
4910 emit_int8((unsigned char)(0xC0 | encode));
4911 }
4912
4913 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
4914 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4915 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4916 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4917 emit_int8(0x57);
4918 emit_int8((unsigned char)(0xC0 | encode));
4919 }
4920
4921 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
4922 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4923 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4924 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4925 emit_int8(0x57);
4926 emit_int8((unsigned char)(0xC0 | encode));
4927 }
4928
4929 void Assembler::xorpd(XMMRegister dst, Address src) {
4930 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4931 InstructionMark im(this);
4932 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4933 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4934 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4935 emit_int8(0x57);
4936 emit_operand(dst, src);
4937 }
4938
4939 void Assembler::xorps(XMMRegister dst, Address src) {
4940 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4941 InstructionMark im(this);
4942 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4943 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4944 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4945 emit_int8(0x57);
4946 emit_operand(dst, src);
4947 }
4948
4949 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4950 assert(VM_Version::supports_avx(), "");
4951 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4952 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4953 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4954 emit_int8(0x57);
4955 emit_int8((unsigned char)(0xC0 | encode));
4956 }
4957
4958 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4959 assert(VM_Version::supports_avx(), "");
4960 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4961 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4962 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4963 emit_int8(0x57);
4964 emit_int8((unsigned char)(0xC0 | encode));
4965 }
4966
4967 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4968 assert(VM_Version::supports_avx(), "");
4969 InstructionMark im(this);
4970 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4971 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4972 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4973 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4974 emit_int8(0x57);
4975 emit_operand(dst, src);
4976 }
4977
4978 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4979 assert(VM_Version::supports_avx(), "");
4980 InstructionMark im(this);
4981 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4982 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4983 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4984 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4985 emit_int8(0x57);
4986 emit_operand(dst, src);
4987 }
4988
4989 // Integer vector arithmetic
4990 void Assembler::vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4991 assert(VM_Version::supports_avx() && (vector_len == 0) ||
4992 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
4993 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4994 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4995 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4996 emit_int8(0x01);
4997 emit_int8((unsigned char)(0xC0 | encode));
4998 }
4999
5000 void Assembler::vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5001 assert(VM_Version::supports_avx() && (vector_len == 0) ||
5002 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
5003 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5004 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5005 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5006 emit_int8(0x02);
5007 emit_int8((unsigned char)(0xC0 | encode));
5008 }
5009
5010 void Assembler::paddb(XMMRegister dst, XMMRegister src) {
5011 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5012 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5013 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5014 emit_int8((unsigned char)0xFC);
5015 emit_int8((unsigned char)(0xC0 | encode));
5016 }
5017
5018 void Assembler::paddw(XMMRegister dst, XMMRegister src) {
5019 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5020 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5021 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5022 emit_int8((unsigned char)0xFD);
5023 emit_int8((unsigned char)(0xC0 | encode));
5024 }
5025
5026 void Assembler::paddd(XMMRegister dst, XMMRegister src) {
5027 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5028 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5029 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5030 emit_int8((unsigned char)0xFE);
5031 emit_int8((unsigned char)(0xC0 | encode));
5032 }
5033
5034 void Assembler::paddd(XMMRegister dst, Address src) {
5035 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5036 InstructionMark im(this);
5037 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5038 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5039 emit_int8((unsigned char)0xFE);
5040 emit_operand(dst, src);
5041 }
5042
5043 void Assembler::paddq(XMMRegister dst, XMMRegister src) {
5044 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5045 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5046 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5047 emit_int8((unsigned char)0xD4);
5048 emit_int8((unsigned char)(0xC0 | encode));
5049 }
5050
5051 void Assembler::phaddw(XMMRegister dst, XMMRegister src) {
5052 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
5053 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5054 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5055 emit_int8(0x01);
5056 emit_int8((unsigned char)(0xC0 | encode));
5057 }
5058
5059 void Assembler::phaddd(XMMRegister dst, XMMRegister src) {
5060 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
5061 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5062 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5063 emit_int8(0x02);
5064 emit_int8((unsigned char)(0xC0 | encode));
5065 }
5066
5067 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5068 assert(UseAVX > 0, "requires some form of AVX");
5069 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5070 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5071 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5072 emit_int8((unsigned char)0xFC);
5073 emit_int8((unsigned char)(0xC0 | encode));
5074 }
5075
5076 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5077 assert(UseAVX > 0, "requires some form of AVX");
5078 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5079 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5080 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5081 emit_int8((unsigned char)0xFD);
5082 emit_int8((unsigned char)(0xC0 | encode));
5083 }
5084
5085 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5086 assert(UseAVX > 0, "requires some form of AVX");
5087 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5088 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5089 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5090 emit_int8((unsigned char)0xFE);
5091 emit_int8((unsigned char)(0xC0 | encode));
5092 }
5093
5094 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5095 assert(UseAVX > 0, "requires some form of AVX");
5096 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5097 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5098 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5099 emit_int8((unsigned char)0xD4);
5100 emit_int8((unsigned char)(0xC0 | encode));
5101 }
5102
5103 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5104 assert(UseAVX > 0, "requires some form of AVX");
5105 InstructionMark im(this);
5106 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5107 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5108 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5109 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5110 emit_int8((unsigned char)0xFC);
5111 emit_operand(dst, src);
5112 }
5113
5114 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5115 assert(UseAVX > 0, "requires some form of AVX");
5116 InstructionMark im(this);
5117 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5118 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5119 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5120 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5121 emit_int8((unsigned char)0xFD);
5122 emit_operand(dst, src);
5123 }
5124
5125 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5126 assert(UseAVX > 0, "requires some form of AVX");
5127 InstructionMark im(this);
5128 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5129 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5130 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5131 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5132 emit_int8((unsigned char)0xFE);
5133 emit_operand(dst, src);
5134 }
5135
5136 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5137 assert(UseAVX > 0, "requires some form of AVX");
5138 InstructionMark im(this);
5139 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5140 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5141 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5142 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5143 emit_int8((unsigned char)0xD4);
5144 emit_operand(dst, src);
5145 }
5146
5147 void Assembler::psubb(XMMRegister dst, XMMRegister src) {
5148 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5149 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5150 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5151 emit_int8((unsigned char)0xF8);
5152 emit_int8((unsigned char)(0xC0 | encode));
5153 }
5154
5155 void Assembler::psubw(XMMRegister dst, XMMRegister src) {
5156 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5157 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5158 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5159 emit_int8((unsigned char)0xF9);
5160 emit_int8((unsigned char)(0xC0 | encode));
5161 }
5162
5163 void Assembler::psubd(XMMRegister dst, XMMRegister src) {
5164 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5165 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5166 emit_int8((unsigned char)0xFA);
5167 emit_int8((unsigned char)(0xC0 | encode));
5168 }
5169
5170 void Assembler::psubq(XMMRegister dst, XMMRegister src) {
5171 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5172 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5173 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5174 emit_int8((unsigned char)0xFB);
5175 emit_int8((unsigned char)(0xC0 | encode));
5176 }
5177
5178 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5179 assert(UseAVX > 0, "requires some form of AVX");
5180 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5181 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5182 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5183 emit_int8((unsigned char)0xF8);
5184 emit_int8((unsigned char)(0xC0 | encode));
5185 }
5186
5187 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5188 assert(UseAVX > 0, "requires some form of AVX");
5189 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5190 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5191 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5192 emit_int8((unsigned char)0xF9);
5193 emit_int8((unsigned char)(0xC0 | encode));
5194 }
5195
5196 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5197 assert(UseAVX > 0, "requires some form of AVX");
5198 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5199 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5200 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5201 emit_int8((unsigned char)0xFA);
5202 emit_int8((unsigned char)(0xC0 | encode));
5203 }
5204
5205 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5206 assert(UseAVX > 0, "requires some form of AVX");
5207 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5208 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5209 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5210 emit_int8((unsigned char)0xFB);
5211 emit_int8((unsigned char)(0xC0 | encode));
5212 }
5213
5214 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5215 assert(UseAVX > 0, "requires some form of AVX");
5216 InstructionMark im(this);
5217 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5218 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5219 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5220 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5221 emit_int8((unsigned char)0xF8);
5222 emit_operand(dst, src);
5223 }
5224
5225 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5226 assert(UseAVX > 0, "requires some form of AVX");
5227 InstructionMark im(this);
5228 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5229 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5230 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5231 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5232 emit_int8((unsigned char)0xF9);
5233 emit_operand(dst, src);
5234 }
5235
5236 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5237 assert(UseAVX > 0, "requires some form of AVX");
5238 InstructionMark im(this);
5239 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5240 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5241 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5242 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5243 emit_int8((unsigned char)0xFA);
5244 emit_operand(dst, src);
5245 }
5246
5247 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5248 assert(UseAVX > 0, "requires some form of AVX");
5249 InstructionMark im(this);
5250 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5251 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5252 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5253 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5254 emit_int8((unsigned char)0xFB);
5255 emit_operand(dst, src);
5256 }
5257
5258 void Assembler::pmullw(XMMRegister dst, XMMRegister src) {
5259 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5260 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5261 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5262 emit_int8((unsigned char)0xD5);
5263 emit_int8((unsigned char)(0xC0 | encode));
5264 }
5265
5266 void Assembler::pmulld(XMMRegister dst, XMMRegister src) {
5267 assert(VM_Version::supports_sse4_1(), "");
5268 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5269 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5270 emit_int8(0x40);
5271 emit_int8((unsigned char)(0xC0 | encode));
5272 }
5273
5274 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5275 assert(UseAVX > 0, "requires some form of AVX");
5276 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5277 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5278 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5279 emit_int8((unsigned char)0xD5);
5280 emit_int8((unsigned char)(0xC0 | encode));
5281 }
5282
5283 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5284 assert(UseAVX > 0, "requires some form of AVX");
5285 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5286 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5287 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5288 emit_int8(0x40);
5289 emit_int8((unsigned char)(0xC0 | encode));
5290 }
5291
5292 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5293 assert(UseAVX > 2, "requires some form of AVX");
5294 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5295 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5296 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5297 emit_int8(0x40);
5298 emit_int8((unsigned char)(0xC0 | encode));
5299 }
5300
5301 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5302 assert(UseAVX > 0, "requires some form of AVX");
5303 InstructionMark im(this);
5304 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5305 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5306 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5307 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5308 emit_int8((unsigned char)0xD5);
5309 emit_operand(dst, src);
5310 }
5311
5312 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5313 assert(UseAVX > 0, "requires some form of AVX");
5314 InstructionMark im(this);
5315 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5316 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5317 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5318 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5319 emit_int8(0x40);
5320 emit_operand(dst, src);
5321 }
5322
5323 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5324 assert(UseAVX > 0, "requires some form of AVX");
5325 InstructionMark im(this);
5326 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5327 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5328 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5329 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5330 emit_int8(0x40);
5331 emit_operand(dst, src);
5332 }
5333
5334 // Shift packed integers left by specified number of bits.
5335 void Assembler::psllw(XMMRegister dst, int shift) {
5336 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5337 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5338 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
5339 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5340 emit_int8(0x71);
5341 emit_int8((unsigned char)(0xC0 | encode));
5342 emit_int8(shift & 0xFF);
5343 }
5344
5345 void Assembler::pslld(XMMRegister dst, int shift) {
5346 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5347 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5348 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
5349 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5350 emit_int8(0x72);
5351 emit_int8((unsigned char)(0xC0 | encode));
5352 emit_int8(shift & 0xFF);
5353 }
5354
5355 void Assembler::psllq(XMMRegister dst, int shift) {
5356 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5357 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5358 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
5359 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5360 emit_int8(0x73);
5361 emit_int8((unsigned char)(0xC0 | encode));
5362 emit_int8(shift & 0xFF);
5363 }
5364
5365 void Assembler::psllw(XMMRegister dst, XMMRegister shift) {
5366 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5367 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5368 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5369 emit_int8((unsigned char)0xF1);
5370 emit_int8((unsigned char)(0xC0 | encode));
5371 }
5372
5373 void Assembler::pslld(XMMRegister dst, XMMRegister shift) {
5374 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5375 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5376 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5377 emit_int8((unsigned char)0xF2);
5378 emit_int8((unsigned char)(0xC0 | encode));
5379 }
5380
5381 void Assembler::psllq(XMMRegister dst, XMMRegister shift) {
5382 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5383 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5384 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5385 emit_int8((unsigned char)0xF3);
5386 emit_int8((unsigned char)(0xC0 | encode));
5387 }
5388
5389 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5390 assert(UseAVX > 0, "requires some form of AVX");
5391 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5392 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
5393 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5394 emit_int8(0x71);
5395 emit_int8((unsigned char)(0xC0 | encode));
5396 emit_int8(shift & 0xFF);
5397 }
5398
5399 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5400 assert(UseAVX > 0, "requires some form of AVX");
5401 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5402 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5403 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
5404 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5405 emit_int8(0x72);
5406 emit_int8((unsigned char)(0xC0 | encode));
5407 emit_int8(shift & 0xFF);
5408 }
5409
5410 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5411 assert(UseAVX > 0, "requires some form of AVX");
5412 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5413 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
5414 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5415 emit_int8(0x73);
5416 emit_int8((unsigned char)(0xC0 | encode));
5417 emit_int8(shift & 0xFF);
5418 }
5419
5420 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5421 assert(UseAVX > 0, "requires some form of AVX");
5422 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5423 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5424 emit_int8((unsigned char)0xF1);
5425 emit_int8((unsigned char)(0xC0 | encode));
5426 }
5427
5428 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5429 assert(UseAVX > 0, "requires some form of AVX");
5430 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5431 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5432 emit_int8((unsigned char)0xF2);
5433 emit_int8((unsigned char)(0xC0 | encode));
5434 }
5435
5436 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5437 assert(UseAVX > 0, "requires some form of AVX");
5438 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5439 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5440 emit_int8((unsigned char)0xF3);
5441 emit_int8((unsigned char)(0xC0 | encode));
5442 }
5443
5444 // Shift packed integers logically right by specified number of bits.
5445 void Assembler::psrlw(XMMRegister dst, int shift) {
5446 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5447 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5448 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
5449 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5450 emit_int8(0x71);
5451 emit_int8((unsigned char)(0xC0 | encode));
5452 emit_int8(shift & 0xFF);
5453 }
5454
5455 void Assembler::psrld(XMMRegister dst, int shift) {
5456 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5457 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5458 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
5459 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5460 emit_int8(0x72);
5461 emit_int8((unsigned char)(0xC0 | encode));
5462 emit_int8(shift & 0xFF);
5463 }
5464
5465 void Assembler::psrlq(XMMRegister dst, int shift) {
5466 // Do not confuse it with psrldq SSE2 instruction which
5467 // shifts 128 bit value in xmm register by number of bytes.
5468 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5469 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5470 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
5471 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5472 emit_int8(0x73);
5473 emit_int8((unsigned char)(0xC0 | encode));
5474 emit_int8(shift & 0xFF);
5475 }
5476
5477 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) {
5478 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5479 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5480 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5481 emit_int8((unsigned char)0xD1);
5482 emit_int8((unsigned char)(0xC0 | encode));
5483 }
5484
5485 void Assembler::psrld(XMMRegister dst, XMMRegister shift) {
5486 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5487 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5488 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5489 emit_int8((unsigned char)0xD2);
5490 emit_int8((unsigned char)(0xC0 | encode));
5491 }
5492
5493 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) {
5494 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5495 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5496 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5497 emit_int8((unsigned char)0xD3);
5498 emit_int8((unsigned char)(0xC0 | encode));
5499 }
5500
5501 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5502 assert(UseAVX > 0, "requires some form of AVX");
5503 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5504 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
5505 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5506 emit_int8(0x71);
5507 emit_int8((unsigned char)(0xC0 | encode));
5508 emit_int8(shift & 0xFF);
5509 }
5510
5511 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5512 assert(UseAVX > 0, "requires some form of AVX");
5513 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5514 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
5515 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5516 emit_int8(0x72);
5517 emit_int8((unsigned char)(0xC0 | encode));
5518 emit_int8(shift & 0xFF);
5519 }
5520
5521 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5522 assert(UseAVX > 0, "requires some form of AVX");
5523 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5524 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
5525 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5526 emit_int8(0x73);
5527 emit_int8((unsigned char)(0xC0 | encode));
5528 emit_int8(shift & 0xFF);
5529 }
5530
5531 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5532 assert(UseAVX > 0, "requires some form of AVX");
5533 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5534 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5535 emit_int8((unsigned char)0xD1);
5536 emit_int8((unsigned char)(0xC0 | encode));
5537 }
5538
5539 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5540 assert(UseAVX > 0, "requires some form of AVX");
5541 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5542 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5543 emit_int8((unsigned char)0xD2);
5544 emit_int8((unsigned char)(0xC0 | encode));
5545 }
5546
5547 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5548 assert(UseAVX > 0, "requires some form of AVX");
5549 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5550 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5551 emit_int8((unsigned char)0xD3);
5552 emit_int8((unsigned char)(0xC0 | encode));
5553 }
5554
5555 // Shift packed integers arithmetically right by specified number of bits.
5556 void Assembler::psraw(XMMRegister dst, int shift) {
5557 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5558 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5559 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
5560 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5561 emit_int8(0x71);
5562 emit_int8((unsigned char)(0xC0 | encode));
5563 emit_int8(shift & 0xFF);
5564 }
5565
5566 void Assembler::psrad(XMMRegister dst, int shift) {
5567 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5568 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5569 // XMM4 is for /4 encoding: 66 0F 72 /4 ib
5570 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5571 emit_int8(0x72);
5572 emit_int8((unsigned char)(0xC0 | encode));
5573 emit_int8(shift & 0xFF);
5574 }
5575
5576 void Assembler::psraw(XMMRegister dst, XMMRegister shift) {
5577 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5578 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5579 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5580 emit_int8((unsigned char)0xE1);
5581 emit_int8((unsigned char)(0xC0 | encode));
5582 }
5583
5584 void Assembler::psrad(XMMRegister dst, XMMRegister shift) {
5585 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5586 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5587 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5588 emit_int8((unsigned char)0xE2);
5589 emit_int8((unsigned char)(0xC0 | encode));
5590 }
5591
5592 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5593 assert(UseAVX > 0, "requires some form of AVX");
5594 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5595 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
5596 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5597 emit_int8(0x71);
5598 emit_int8((unsigned char)(0xC0 | encode));
5599 emit_int8(shift & 0xFF);
5600 }
5601
5602 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5603 assert(UseAVX > 0, "requires some form of AVX");
5604 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5605 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
5606 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5607 emit_int8(0x72);
5608 emit_int8((unsigned char)(0xC0 | encode));
5609 emit_int8(shift & 0xFF);
5610 }
5611
5612 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5613 assert(UseAVX > 0, "requires some form of AVX");
5614 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5615 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5616 emit_int8((unsigned char)0xE1);
5617 emit_int8((unsigned char)(0xC0 | encode));
5618 }
5619
5620 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5621 assert(UseAVX > 0, "requires some form of AVX");
5622 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5623 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5624 emit_int8((unsigned char)0xE2);
5625 emit_int8((unsigned char)(0xC0 | encode));
5626 }
5627
5628
5629 // logical operations packed integers
5630 void Assembler::pand(XMMRegister dst, XMMRegister src) {
5631 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5632 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5633 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5634 emit_int8((unsigned char)0xDB);
5635 emit_int8((unsigned char)(0xC0 | encode));
5636 }
5637
5638 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5639 assert(UseAVX > 0, "requires some form of AVX");
5640 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5641 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5642 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5643 emit_int8((unsigned char)0xDB);
5644 emit_int8((unsigned char)(0xC0 | encode));
5645 }
5646
5647 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5648 assert(UseAVX > 0, "requires some form of AVX");
5649 InstructionMark im(this);
5650 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5651 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5652 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5653 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5654 emit_int8((unsigned char)0xDB);
5655 emit_operand(dst, src);
5656 }
5657
5658 void Assembler::pandn(XMMRegister dst, XMMRegister src) {
5659 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5660 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5661 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5662 emit_int8((unsigned char)0xDF);
5663 emit_int8((unsigned char)(0xC0 | encode));
5664 }
5665
5666 void Assembler::por(XMMRegister dst, XMMRegister src) {
5667 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5668 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5669 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5670 emit_int8((unsigned char)0xEB);
5671 emit_int8((unsigned char)(0xC0 | encode));
5672 }
5673
5674 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5675 assert(UseAVX > 0, "requires some form of AVX");
5676 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5677 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5678 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5679 emit_int8((unsigned char)0xEB);
5680 emit_int8((unsigned char)(0xC0 | encode));
5681 }
5682
5683 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5684 assert(UseAVX > 0, "requires some form of AVX");
5685 InstructionMark im(this);
5686 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5687 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5688 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5689 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5690 emit_int8((unsigned char)0xEB);
5691 emit_operand(dst, src);
5692 }
5693
5694 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
5695 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5696 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5697 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5698 emit_int8((unsigned char)0xEF);
5699 emit_int8((unsigned char)(0xC0 | encode));
5700 }
5701
5702 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5703 assert(UseAVX > 0, "requires some form of AVX");
5704 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5705 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5706 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5707 emit_int8((unsigned char)0xEF);
5708 emit_int8((unsigned char)(0xC0 | encode));
5709 }
5710
5711 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5712 assert(UseAVX > 0, "requires some form of AVX");
5713 InstructionMark im(this);
5714 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5715 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5716 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5717 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5718 emit_int8((unsigned char)0xEF);
5719 emit_operand(dst, src);
5720 }
5721
5722
5723 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
5724 assert(VM_Version::supports_avx(), "");
5725 assert(imm8 <= 0x01, "imm8: %u", imm8);
5726 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
5727 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5728 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5729 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5730 emit_int8(0x18);
5731 emit_int8((unsigned char)(0xC0 | encode));
5732 // 0x00 - insert into lower 128 bits
5733 // 0x01 - insert into upper 128 bits
5734 emit_int8(imm8 & 0x01);
5735 }
5736
5737 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
5738 assert(VM_Version::supports_evex(), "");
5739 assert(imm8 <= 0x01, "imm8: %u", imm8);
5740 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5741 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5742 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5743 emit_int8(0x1A);
5744 emit_int8((unsigned char)(0xC0 | encode));
5745 // 0x00 - insert into lower 256 bits
5746 // 0x01 - insert into upper 256 bits
5747 emit_int8(imm8 & 0x01);
5748 }
5749
5750 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
5751 assert(VM_Version::supports_evex(), "");
5752 assert(dst != xnoreg, "sanity");
5753 assert(imm8 <= 0x01, "imm8: %u", imm8);
5754 InstructionMark im(this);
5755 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5756 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5757 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_64bit);
5758 // swap src<->dst for encoding
5759 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5760 emit_int8(0x1A);
5761 emit_operand(dst, src);
5762 // 0x00 - insert into lower 256 bits
5763 // 0x01 - insert into upper 256 bits
5764 emit_int8(imm8 & 0x01);
5765 }
5766
5767 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
5768 assert(VM_Version::supports_evex(), "");
5769 assert(imm8 <= 0x03, "imm8: %u", imm8);
5770 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5771 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5772 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5773 emit_int8(0x18);
5774 emit_int8((unsigned char)(0xC0 | encode));
5775 // 0x00 - insert into q0 128 bits (0..127)
5776 // 0x01 - insert into q1 128 bits (128..255)
5777 // 0x02 - insert into q2 128 bits (256..383)
5778 // 0x03 - insert into q3 128 bits (384..511)
5779 emit_int8(imm8 & 0x03);
5780 }
5781
5782 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
5783 assert(VM_Version::supports_avx(), "");
5784 assert(dst != xnoreg, "sanity");
5785 assert(imm8 <= 0x03, "imm8: %u", imm8);
5786 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5787 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5788 InstructionMark im(this);
5789 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5790 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5791 // swap src<->dst for encoding
5792 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5793 emit_int8(0x18);
5794 emit_operand(dst, src);
5795 // 0x00 - insert into q0 128 bits (0..127)
5796 // 0x01 - insert into q1 128 bits (128..255)
5797 // 0x02 - insert into q2 128 bits (256..383)
5798 // 0x03 - insert into q3 128 bits (384..511)
5799 emit_int8(imm8 & 0x03);
5800 }
5801
5802 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
5803 assert(VM_Version::supports_avx(), "");
5804 assert(dst != xnoreg, "sanity");
5805 assert(imm8 <= 0x01, "imm8: %u", imm8);
5806 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
5807 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5808 InstructionMark im(this);
5809 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5810 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5811 // swap src<->dst for encoding
5812 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5813 emit_int8(0x18);
5814 emit_operand(dst, src);
5815 // 0x00 - insert into lower 128 bits
5816 // 0x01 - insert into upper 128 bits
5817 emit_int8(imm8 & 0x01);
5818 }
5819
5820 void Assembler::vextractf128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
5821 assert(VM_Version::supports_avx(), "");
5822 assert(imm8 <= 0x01, "imm8: %u", imm8);
5823 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
5824 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5825 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5826 emit_int8(0x19);
5827 emit_int8((unsigned char)(0xC0 | encode));
5828 // 0x00 - extract from lower 128 bits
5829 // 0x01 - extract from upper 128 bits
5830 emit_int8(imm8 & 0x01);
5831 }
5832
5833 void Assembler::vextractf128(Address dst, XMMRegister src, uint8_t imm8) {
5834 assert(VM_Version::supports_avx(), "");
5835 assert(src != xnoreg, "sanity");
5836 assert(imm8 <= 0x01, "imm8: %u", imm8);
5837 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
5838 InstructionMark im(this);
5839 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5840 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5841 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5842 emit_int8(0x19);
5843 emit_operand(src, dst);
5844 // 0x00 - extract from lower 128 bits
5845 // 0x01 - extract from upper 128 bits
5846 emit_int8(imm8 & 0x01);
5847 }
5848
5849 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
5850 assert(VM_Version::supports_avx2(), "");
5851 assert(imm8 <= 0x01, "imm8: %u", imm8);
5852 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
5853 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5854 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5855 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5856 emit_int8(0x38);
5857 emit_int8((unsigned char)(0xC0 | encode));
5858 // 0x00 - insert into lower 128 bits
5859 // 0x01 - insert into upper 128 bits
5860 emit_int8(imm8 & 0x01);
5861 }
5862
5863 void Assembler::vinserti64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
5864 assert(VM_Version::supports_evex(), "");
5865 assert(imm8 <= 0x01, "imm8: %u", imm8);
5866 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5867 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5868 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5869 emit_int8(0x38);
5870 emit_int8((unsigned char)(0xC0 | encode));
5871 // 0x00 - insert into lower 256 bits
5872 // 0x01 - insert into upper 256 bits
5873 emit_int8(imm8 & 0x01);
5874 }
5875
5876 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
5877 assert(VM_Version::supports_avx2(), "");
5878 assert(dst != xnoreg, "sanity");
5879 assert(imm8 <= 0x01, "imm8: %u", imm8);
5880 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
5881 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5882 InstructionMark im(this);
5883 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5884 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5885 // swap src<->dst for encoding
5886 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5887 emit_int8(0x38);
5888 emit_operand(dst, src);
5889 // 0x00 - insert into lower 128 bits
5890 // 0x01 - insert into upper 128 bits
5891 emit_int8(imm8 & 0x01);
5892 }
5893
5894 void Assembler::vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
5895 assert(VM_Version::supports_avx(), "");
5896 assert(imm8 <= 0x01, "imm8: %u", imm8);
5897 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
5898 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5899 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5900 emit_int8(0x39);
5901 emit_int8((unsigned char)(0xC0 | encode));
5902 // 0x00 - extract from lower 128 bits
5903 // 0x01 - extract from upper 128 bits
5904 emit_int8(imm8 & 0x01);
5905 }
5906
5907 void Assembler::vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
5908 assert(VM_Version::supports_avx2(), "");
5909 assert(src != xnoreg, "sanity");
5910 assert(imm8 <= 0x01, "imm8: %u", imm8);
5911 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
5912 InstructionMark im(this);
5913 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5914 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5915 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5916 emit_int8(0x39);
5917 emit_operand(src, dst);
5918 // 0x00 - extract from lower 128 bits
5919 // 0x01 - extract from upper 128 bits
5920 emit_int8(imm8 & 0x01);
5921 }
5922
5923 void Assembler::vextracti64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
5924 assert(VM_Version::supports_evex(), "");
5925 assert(imm8 <= 0x01, "imm8: %u", imm8);
5926 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5927 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5928 emit_int8(0x3B);
5929 emit_int8((unsigned char)(0xC0 | encode));
5930 // 0x00 - extract from lower 256 bits
5931 // 0x01 - extract from upper 256 bits
5932 emit_int8(imm8 & 0x01);
5933 }
5934
5935 void Assembler::vextracti64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) {
5936 assert(VM_Version::supports_evex(), "");
5937 assert(imm8 <= 0x03, "imm8: %u", imm8);
5938 InstructionAttr attributes(AVX_512bit, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5939 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5940 emit_int8(0x39);
5941 emit_int8((unsigned char)(0xC0 | encode));
5942 // 0x00 - extract from bits 127:0
5943 // 0x01 - extract from bits 255:128
5944 // 0x02 - extract from bits 383:256
5945 // 0x03 - extract from bits 511:384
5946 emit_int8(imm8 & 0x03);
5947 }
5948
5949 void Assembler::vextractf64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
5950 assert(VM_Version::supports_evex(), "");
5951 assert(imm8 <= 0x01, "imm8: %u", imm8);
5952 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5953 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5954 emit_int8(0x1B);
5955 emit_int8((unsigned char)(0xC0 | encode));
5956 // 0x00 - extract from lower 256 bits
5957 // 0x01 - extract from upper 256 bits
5958 emit_int8(imm8 & 0x01);
5959 }
5960
5961 void Assembler::vextractf64x4(Address dst, XMMRegister src, uint8_t imm8) {
5962 assert(VM_Version::supports_evex(), "");
5963 assert(src != xnoreg, "sanity");
5964 assert(imm8 <= 0x01, "imm8: %u", imm8);
5965 InstructionMark im(this);
5966 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5967 attributes.set_address_attributes(/* tuple_type */ EVEX_T4,/* input_size_in_bits */ EVEX_64bit);
5968 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5969 emit_int8(0x1B);
5970 emit_operand(src, dst);
5971 // 0x00 - extract from lower 256 bits
5972 // 0x01 - extract from upper 256 bits
5973 emit_int8(imm8 & 0x01);
5974 }
5975
5976 void Assembler::vextractf32x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
5977 assert(VM_Version::supports_avx(), "");
5978 assert(imm8 <= 0x03, "imm8: %u", imm8);
5979 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5980 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5981 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5982 emit_int8(0x19);
5983 emit_int8((unsigned char)(0xC0 | encode));
5984 // 0x00 - extract from bits 127:0
5985 // 0x01 - extract from bits 255:128
5986 // 0x02 - extract from bits 383:256
5987 // 0x03 - extract from bits 511:384
5988 emit_int8(imm8 & 0x03);
5989 }
5990
5991 void Assembler::vextractf32x4(Address dst, XMMRegister src, uint8_t imm8) {
5992 assert(VM_Version::supports_evex(), "");
5993 assert(src != xnoreg, "sanity");
5994 assert(imm8 <= 0x03, "imm8: %u", imm8);
5995 InstructionMark im(this);
5996 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5997 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5998 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5999 emit_int8(0x19);
6000 emit_operand(src, dst);
6001 // 0x00 - extract from bits 127:0
6002 // 0x01 - extract from bits 255:128
6003 // 0x02 - extract from bits 383:256
6004 // 0x03 - extract from bits 511:384
6005 emit_int8(imm8 & 0x03);
6006 }
6007
6008 void Assembler::vextractf64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6009 assert(VM_Version::supports_evex(), "");
6010 assert(imm8 <= 0x03, "imm8: %u", imm8);
6011 InstructionAttr attributes(AVX_512bit, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6012 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6013 emit_int8(0x19);
6014 emit_int8((unsigned char)(0xC0 | encode));
6015 // 0x00 - extract from bits 127:0
6016 // 0x01 - extract from bits 255:128
6017 // 0x02 - extract from bits 383:256
6018 // 0x03 - extract from bits 511:384
6019 emit_int8(imm8 & 0x03);
6020 }
6021
6022 // duplicate 4-bytes integer data from src into 8 locations in dest
6023 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src) {
6024 assert(VM_Version::supports_avx2(), "");
6025 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6026 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6027 emit_int8(0x58);
6028 emit_int8((unsigned char)(0xC0 | encode));
6029 }
6030
6031 // duplicate 2-bytes integer data from src into 16 locations in dest
6032 void Assembler::vpbroadcastw(XMMRegister dst, XMMRegister src) {
6033 assert(VM_Version::supports_avx2(), "");
6034 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6035 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6036 emit_int8(0x79);
6037 emit_int8((unsigned char)(0xC0 | encode));
6038 }
6039
6040 // duplicate 1-byte integer data from src into 16||32|64 locations in dest : requires AVX512BW and AVX512VL
6041 void Assembler::evpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len) {
6042 assert(VM_Version::supports_evex(), "");
6043 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6044 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6045 emit_int8(0x78);
6046 emit_int8((unsigned char)(0xC0 | encode));
6047 }
6048
6049 void Assembler::evpbroadcastb(XMMRegister dst, Address src, int vector_len) {
6050 assert(VM_Version::supports_evex(), "");
6051 assert(dst != xnoreg, "sanity");
6052 InstructionMark im(this);
6053 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6054 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
6055 // swap src<->dst for encoding
6056 vex_prefix(src, dst->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6057 emit_int8(0x78);
6058 emit_operand(dst, src);
6059 }
6060
6061 // duplicate 2-byte integer data from src into 8|16||32 locations in dest : requires AVX512BW and AVX512VL
6062 void Assembler::evpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len) {
6063 assert(VM_Version::supports_evex(), "");
6064 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6065 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6066 emit_int8(0x79);
6067 emit_int8((unsigned char)(0xC0 | encode));
6068 }
6069
6070 void Assembler::evpbroadcastw(XMMRegister dst, Address src, int vector_len) {
6071 assert(VM_Version::supports_evex(), "");
6072 assert(dst != xnoreg, "sanity");
6073 InstructionMark im(this);
6074 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6075 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
6076 // swap src<->dst for encoding
6077 vex_prefix(src, dst->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6078 emit_int8(0x79);
6079 emit_operand(dst, src);
6080 }
6081
6082 // duplicate 4-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
6083 void Assembler::evpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len) {
6084 assert(VM_Version::supports_evex(), "");
6085 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6086 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6087 emit_int8(0x58);
6088 emit_int8((unsigned char)(0xC0 | encode));
6089 }
6090
6091 void Assembler::evpbroadcastd(XMMRegister dst, Address src, int vector_len) {
6092 assert(VM_Version::supports_evex(), "");
6093 assert(dst != xnoreg, "sanity");
6094 InstructionMark im(this);
6095 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6096 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
6097 // swap src<->dst for encoding
6098 vex_prefix(src, dst->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6099 emit_int8(0x58);
6100 emit_operand(dst, src);
6101 }
6102
6103 // duplicate 8-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
6104 void Assembler::evpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len) {
6105 assert(VM_Version::supports_evex(), "");
6106 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6107 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6108 emit_int8(0x59);
6109 emit_int8((unsigned char)(0xC0 | encode));
6110 }
6111
6112 void Assembler::evpbroadcastq(XMMRegister dst, Address src, int vector_len) {
6113 assert(VM_Version::supports_evex(), "");
6114 assert(dst != xnoreg, "sanity");
6115 InstructionMark im(this);
6116 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6117 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6118 // swap src<->dst for encoding
6119 vex_prefix(src, dst->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6120 emit_int8(0x59);
6121 emit_operand(dst, src);
6122 }
6123
6124 // duplicate single precision fp from src into 4|8|16 locations in dest : requires AVX512VL
6125 void Assembler::evpbroadcastss(XMMRegister dst, XMMRegister src, int vector_len) {
6126 assert(VM_Version::supports_evex(), "");
6127 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6128 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6129 emit_int8(0x18);
6130 emit_int8((unsigned char)(0xC0 | encode));
6131 }
6132
6133 void Assembler::evpbroadcastss(XMMRegister dst, Address src, int vector_len) {
6134 assert(VM_Version::supports_evex(), "");
6135 assert(dst != xnoreg, "sanity");
6136 InstructionMark im(this);
6137 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6138 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
6139 // swap src<->dst for encoding
6140 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6141 emit_int8(0x18);
6142 emit_operand(dst, src);
6143 }
6144
6145 // duplicate double precision fp from src into 2|4|8 locations in dest : requires AVX512VL
6146 void Assembler::evpbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len) {
6147 assert(VM_Version::supports_evex(), "");
6148 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6149 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6150 emit_int8(0x19);
6151 emit_int8((unsigned char)(0xC0 | encode));
6152 }
6153
6154 void Assembler::evpbroadcastsd(XMMRegister dst, Address src, int vector_len) {
6155 assert(VM_Version::supports_evex(), "");
6156 assert(dst != xnoreg, "sanity");
6157 InstructionMark im(this);
6158 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6159 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6160 // swap src<->dst for encoding
6161 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6162 emit_int8(0x19);
6163 emit_operand(dst, src);
6164 }
6165
6166 // duplicate 1-byte integer data from src into 16||32|64 locations in dest : requires AVX512BW and AVX512VL
6167 void Assembler::evpbroadcastb(XMMRegister dst, Register src, int vector_len) {
6168 assert(VM_Version::supports_evex(), "");
6169 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6170 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6171 if (attributes.is_evex_instruction()) {
6172 emit_int8(0x7A);
6173 } else {
6174 emit_int8(0x78);
6175 }
6176 emit_int8((unsigned char)(0xC0 | encode));
6177 }
6178
6179 // duplicate 2-byte integer data from src into 8|16||32 locations in dest : requires AVX512BW and AVX512VL
6180 void Assembler::evpbroadcastw(XMMRegister dst, Register src, int vector_len) {
6181 assert(VM_Version::supports_evex(), "");
6182 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6183 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6184 if (attributes.is_evex_instruction()) {
6185 emit_int8(0x7B);
6186 } else {
6187 emit_int8(0x79);
6188 }
6189 emit_int8((unsigned char)(0xC0 | encode));
6190 }
6191
6192 // duplicate 4-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
6193 void Assembler::evpbroadcastd(XMMRegister dst, Register src, int vector_len) {
6194 assert(VM_Version::supports_evex(), "");
6195 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6196 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6197 if (attributes.is_evex_instruction()) {
6198 emit_int8(0x7C);
6199 } else {
6200 emit_int8(0x58);
6201 }
6202 emit_int8((unsigned char)(0xC0 | encode));
6203 }
6204
6205 // duplicate 8-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
6206 void Assembler::evpbroadcastq(XMMRegister dst, Register src, int vector_len) {
6207 assert(VM_Version::supports_evex(), "");
6208 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6209 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6210 if (attributes.is_evex_instruction()) {
6211 emit_int8(0x7C);
6212 } else {
6213 emit_int8(0x59);
6214 }
6215 emit_int8((unsigned char)(0xC0 | encode));
6216 }
6217
6218 // Carry-Less Multiplication Quadword
6219 void Assembler::pclmulqdq(XMMRegister dst, XMMRegister src, int mask) {
6220 assert(VM_Version::supports_clmul(), "");
6221 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6222 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6223 emit_int8(0x44);
6224 emit_int8((unsigned char)(0xC0 | encode));
6225 emit_int8((unsigned char)mask);
6226 }
6227
6228 // Carry-Less Multiplication Quadword
6229 void Assembler::vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask) {
6230 assert(VM_Version::supports_avx() && VM_Version::supports_clmul(), "");
6231 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6232 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
6233 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6234 emit_int8(0x44);
6235 emit_int8((unsigned char)(0xC0 | encode));
6236 emit_int8((unsigned char)mask);
6237 }
6238
6239 void Assembler::vzeroupper() {
6240 assert(VM_Version::supports_avx(), "");
6241 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6242 (void)vex_prefix_and_encode(0, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6243 emit_int8(0x77);
6244 }
6245
6246
6247 #ifndef _LP64
6248 // 32bit only pieces of the assembler
6249
6250 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
6251 // NO PREFIX AS NEVER 64BIT
6252 InstructionMark im(this);
6253 emit_int8((unsigned char)0x81);
6254 emit_int8((unsigned char)(0xF8 | src1->encoding()));
6255 emit_data(imm32, rspec, 0);
6256 }
6257
6258 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
6259 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
6260 InstructionMark im(this);
6261 emit_int8((unsigned char)0x81);
6262 emit_operand(rdi, src1);
6263 emit_data(imm32, rspec, 0);
6264 }
6265
6266 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax,
6267 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded
6268 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise.
6269 void Assembler::cmpxchg8(Address adr) {
6270 InstructionMark im(this);
6271 emit_int8(0x0F);
6272 emit_int8((unsigned char)0xC7);
6273 emit_operand(rcx, adr);
6274 }
6275
6276 void Assembler::decl(Register dst) {
6277 // Don't use it directly. Use MacroAssembler::decrementl() instead.
6278 emit_int8(0x48 | dst->encoding());
6279 }
6280
6281 #endif // _LP64
6282
6283 // 64bit typically doesn't use the x87 but needs to for the trig funcs
6284
6285 void Assembler::fabs() {
6286 emit_int8((unsigned char)0xD9);
6287 emit_int8((unsigned char)0xE1);
6288 }
6289
6290 void Assembler::fadd(int i) {
6291 emit_farith(0xD8, 0xC0, i);
6292 }
6293
6294 void Assembler::fadd_d(Address src) {
6295 InstructionMark im(this);
6296 emit_int8((unsigned char)0xDC);
6297 emit_operand32(rax, src);
6298 }
6299
6300 void Assembler::fadd_s(Address src) {
6301 InstructionMark im(this);
6302 emit_int8((unsigned char)0xD8);
6303 emit_operand32(rax, src);
6304 }
6305
6306 void Assembler::fadda(int i) {
6307 emit_farith(0xDC, 0xC0, i);
6308 }
6309
6310 void Assembler::faddp(int i) {
6311 emit_farith(0xDE, 0xC0, i);
6312 }
6313
6314 void Assembler::fchs() {
6315 emit_int8((unsigned char)0xD9);
6316 emit_int8((unsigned char)0xE0);
6317 }
6318
6319 void Assembler::fcom(int i) {
6320 emit_farith(0xD8, 0xD0, i);
6321 }
6322
6323 void Assembler::fcomp(int i) {
6324 emit_farith(0xD8, 0xD8, i);
6325 }
6326
6327 void Assembler::fcomp_d(Address src) {
6328 InstructionMark im(this);
6329 emit_int8((unsigned char)0xDC);
6330 emit_operand32(rbx, src);
6331 }
6332
6333 void Assembler::fcomp_s(Address src) {
6334 InstructionMark im(this);
6335 emit_int8((unsigned char)0xD8);
6336 emit_operand32(rbx, src);
6337 }
6338
6339 void Assembler::fcompp() {
6340 emit_int8((unsigned char)0xDE);
6341 emit_int8((unsigned char)0xD9);
6342 }
6343
6344 void Assembler::fcos() {
6345 emit_int8((unsigned char)0xD9);
6346 emit_int8((unsigned char)0xFF);
6347 }
6348
6349 void Assembler::fdecstp() {
6350 emit_int8((unsigned char)0xD9);
6351 emit_int8((unsigned char)0xF6);
6352 }
6353
6354 void Assembler::fdiv(int i) {
6355 emit_farith(0xD8, 0xF0, i);
6356 }
6357
6358 void Assembler::fdiv_d(Address src) {
6359 InstructionMark im(this);
6360 emit_int8((unsigned char)0xDC);
6361 emit_operand32(rsi, src);
6362 }
6363
6364 void Assembler::fdiv_s(Address src) {
6365 InstructionMark im(this);
6366 emit_int8((unsigned char)0xD8);
6367 emit_operand32(rsi, src);
6368 }
6369
6370 void Assembler::fdiva(int i) {
6371 emit_farith(0xDC, 0xF8, i);
6372 }
6373
6374 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994)
6375 // is erroneous for some of the floating-point instructions below.
6376
6377 void Assembler::fdivp(int i) {
6378 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong)
6379 }
6380
6381 void Assembler::fdivr(int i) {
6382 emit_farith(0xD8, 0xF8, i);
6383 }
6384
6385 void Assembler::fdivr_d(Address src) {
6386 InstructionMark im(this);
6387 emit_int8((unsigned char)0xDC);
6388 emit_operand32(rdi, src);
6389 }
6390
6391 void Assembler::fdivr_s(Address src) {
6392 InstructionMark im(this);
6393 emit_int8((unsigned char)0xD8);
6394 emit_operand32(rdi, src);
6395 }
6396
6397 void Assembler::fdivra(int i) {
6398 emit_farith(0xDC, 0xF0, i);
6399 }
6400
6401 void Assembler::fdivrp(int i) {
6402 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong)
6403 }
6404
6405 void Assembler::ffree(int i) {
6406 emit_farith(0xDD, 0xC0, i);
6407 }
6408
6409 void Assembler::fild_d(Address adr) {
6410 InstructionMark im(this);
6411 emit_int8((unsigned char)0xDF);
6412 emit_operand32(rbp, adr);
6413 }
6414
6415 void Assembler::fild_s(Address adr) {
6416 InstructionMark im(this);
6417 emit_int8((unsigned char)0xDB);
6418 emit_operand32(rax, adr);
6419 }
6420
6421 void Assembler::fincstp() {
6422 emit_int8((unsigned char)0xD9);
6423 emit_int8((unsigned char)0xF7);
6424 }
6425
6426 void Assembler::finit() {
6427 emit_int8((unsigned char)0x9B);
6428 emit_int8((unsigned char)0xDB);
6429 emit_int8((unsigned char)0xE3);
6430 }
6431
6432 void Assembler::fist_s(Address adr) {
6433 InstructionMark im(this);
6434 emit_int8((unsigned char)0xDB);
6435 emit_operand32(rdx, adr);
6436 }
6437
6438 void Assembler::fistp_d(Address adr) {
6439 InstructionMark im(this);
6440 emit_int8((unsigned char)0xDF);
6441 emit_operand32(rdi, adr);
6442 }
6443
6444 void Assembler::fistp_s(Address adr) {
6445 InstructionMark im(this);
6446 emit_int8((unsigned char)0xDB);
6447 emit_operand32(rbx, adr);
6448 }
6449
6450 void Assembler::fld1() {
6451 emit_int8((unsigned char)0xD9);
6452 emit_int8((unsigned char)0xE8);
6453 }
6454
6455 void Assembler::fld_d(Address adr) {
6456 InstructionMark im(this);
6457 emit_int8((unsigned char)0xDD);
6458 emit_operand32(rax, adr);
6459 }
6460
6461 void Assembler::fld_s(Address adr) {
6462 InstructionMark im(this);
6463 emit_int8((unsigned char)0xD9);
6464 emit_operand32(rax, adr);
6465 }
6466
6467
6468 void Assembler::fld_s(int index) {
6469 emit_farith(0xD9, 0xC0, index);
6470 }
6471
6472 void Assembler::fld_x(Address adr) {
6473 InstructionMark im(this);
6474 emit_int8((unsigned char)0xDB);
6475 emit_operand32(rbp, adr);
6476 }
6477
6478 void Assembler::fldcw(Address src) {
6479 InstructionMark im(this);
6480 emit_int8((unsigned char)0xD9);
6481 emit_operand32(rbp, src);
6482 }
6483
6484 void Assembler::fldenv(Address src) {
6485 InstructionMark im(this);
6486 emit_int8((unsigned char)0xD9);
6487 emit_operand32(rsp, src);
6488 }
6489
6490 void Assembler::fldlg2() {
6491 emit_int8((unsigned char)0xD9);
6492 emit_int8((unsigned char)0xEC);
6493 }
6494
6495 void Assembler::fldln2() {
6496 emit_int8((unsigned char)0xD9);
6497 emit_int8((unsigned char)0xED);
6498 }
6499
6500 void Assembler::fldz() {
6501 emit_int8((unsigned char)0xD9);
6502 emit_int8((unsigned char)0xEE);
6503 }
6504
6505 void Assembler::flog() {
6506 fldln2();
6507 fxch();
6508 fyl2x();
6509 }
6510
6511 void Assembler::flog10() {
6512 fldlg2();
6513 fxch();
6514 fyl2x();
6515 }
6516
6517 void Assembler::fmul(int i) {
6518 emit_farith(0xD8, 0xC8, i);
6519 }
6520
6521 void Assembler::fmul_d(Address src) {
6522 InstructionMark im(this);
6523 emit_int8((unsigned char)0xDC);
6524 emit_operand32(rcx, src);
6525 }
6526
6527 void Assembler::fmul_s(Address src) {
6528 InstructionMark im(this);
6529 emit_int8((unsigned char)0xD8);
6530 emit_operand32(rcx, src);
6531 }
6532
6533 void Assembler::fmula(int i) {
6534 emit_farith(0xDC, 0xC8, i);
6535 }
6536
6537 void Assembler::fmulp(int i) {
6538 emit_farith(0xDE, 0xC8, i);
6539 }
6540
6541 void Assembler::fnsave(Address dst) {
6542 InstructionMark im(this);
6543 emit_int8((unsigned char)0xDD);
6544 emit_operand32(rsi, dst);
6545 }
6546
6547 void Assembler::fnstcw(Address src) {
6548 InstructionMark im(this);
6549 emit_int8((unsigned char)0x9B);
6550 emit_int8((unsigned char)0xD9);
6551 emit_operand32(rdi, src);
6552 }
6553
6554 void Assembler::fnstsw_ax() {
6555 emit_int8((unsigned char)0xDF);
6556 emit_int8((unsigned char)0xE0);
6557 }
6558
6559 void Assembler::fprem() {
6560 emit_int8((unsigned char)0xD9);
6561 emit_int8((unsigned char)0xF8);
6562 }
6563
6564 void Assembler::fprem1() {
6565 emit_int8((unsigned char)0xD9);
6566 emit_int8((unsigned char)0xF5);
6567 }
6568
6569 void Assembler::frstor(Address src) {
6570 InstructionMark im(this);
6571 emit_int8((unsigned char)0xDD);
6572 emit_operand32(rsp, src);
6573 }
6574
6575 void Assembler::fsin() {
6576 emit_int8((unsigned char)0xD9);
6577 emit_int8((unsigned char)0xFE);
6578 }
6579
6580 void Assembler::fsqrt() {
6581 emit_int8((unsigned char)0xD9);
6582 emit_int8((unsigned char)0xFA);
6583 }
6584
6585 void Assembler::fst_d(Address adr) {
6586 InstructionMark im(this);
6587 emit_int8((unsigned char)0xDD);
6588 emit_operand32(rdx, adr);
6589 }
6590
6591 void Assembler::fst_s(Address adr) {
6592 InstructionMark im(this);
6593 emit_int8((unsigned char)0xD9);
6594 emit_operand32(rdx, adr);
6595 }
6596
6597 void Assembler::fstp_d(Address adr) {
6598 InstructionMark im(this);
6599 emit_int8((unsigned char)0xDD);
6600 emit_operand32(rbx, adr);
6601 }
6602
6603 void Assembler::fstp_d(int index) {
6604 emit_farith(0xDD, 0xD8, index);
6605 }
6606
6607 void Assembler::fstp_s(Address adr) {
6608 InstructionMark im(this);
6609 emit_int8((unsigned char)0xD9);
6610 emit_operand32(rbx, adr);
6611 }
6612
6613 void Assembler::fstp_x(Address adr) {
6614 InstructionMark im(this);
6615 emit_int8((unsigned char)0xDB);
6616 emit_operand32(rdi, adr);
6617 }
6618
6619 void Assembler::fsub(int i) {
6620 emit_farith(0xD8, 0xE0, i);
6621 }
6622
6623 void Assembler::fsub_d(Address src) {
6624 InstructionMark im(this);
6625 emit_int8((unsigned char)0xDC);
6626 emit_operand32(rsp, src);
6627 }
6628
6629 void Assembler::fsub_s(Address src) {
6630 InstructionMark im(this);
6631 emit_int8((unsigned char)0xD8);
6632 emit_operand32(rsp, src);
6633 }
6634
6635 void Assembler::fsuba(int i) {
6636 emit_farith(0xDC, 0xE8, i);
6637 }
6638
6639 void Assembler::fsubp(int i) {
6640 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong)
6641 }
6642
6643 void Assembler::fsubr(int i) {
6644 emit_farith(0xD8, 0xE8, i);
6645 }
6646
6647 void Assembler::fsubr_d(Address src) {
6648 InstructionMark im(this);
6649 emit_int8((unsigned char)0xDC);
6650 emit_operand32(rbp, src);
6651 }
6652
6653 void Assembler::fsubr_s(Address src) {
6654 InstructionMark im(this);
6655 emit_int8((unsigned char)0xD8);
6656 emit_operand32(rbp, src);
6657 }
6658
6659 void Assembler::fsubra(int i) {
6660 emit_farith(0xDC, 0xE0, i);
6661 }
6662
6663 void Assembler::fsubrp(int i) {
6664 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong)
6665 }
6666
6667 void Assembler::ftan() {
6668 emit_int8((unsigned char)0xD9);
6669 emit_int8((unsigned char)0xF2);
6670 emit_int8((unsigned char)0xDD);
6671 emit_int8((unsigned char)0xD8);
6672 }
6673
6674 void Assembler::ftst() {
6675 emit_int8((unsigned char)0xD9);
6676 emit_int8((unsigned char)0xE4);
6677 }
6678
6679 void Assembler::fucomi(int i) {
6680 // make sure the instruction is supported (introduced for P6, together with cmov)
6681 guarantee(VM_Version::supports_cmov(), "illegal instruction");
6682 emit_farith(0xDB, 0xE8, i);
6683 }
6684
6685 void Assembler::fucomip(int i) {
6686 // make sure the instruction is supported (introduced for P6, together with cmov)
6687 guarantee(VM_Version::supports_cmov(), "illegal instruction");
6688 emit_farith(0xDF, 0xE8, i);
6689 }
6690
6691 void Assembler::fwait() {
6692 emit_int8((unsigned char)0x9B);
6693 }
6694
6695 void Assembler::fxch(int i) {
6696 emit_farith(0xD9, 0xC8, i);
6697 }
6698
6699 void Assembler::fyl2x() {
6700 emit_int8((unsigned char)0xD9);
6701 emit_int8((unsigned char)0xF1);
6702 }
6703
6704 void Assembler::frndint() {
6705 emit_int8((unsigned char)0xD9);
6706 emit_int8((unsigned char)0xFC);
6707 }
6708
6709 void Assembler::f2xm1() {
6710 emit_int8((unsigned char)0xD9);
6711 emit_int8((unsigned char)0xF0);
6712 }
6713
6714 void Assembler::fldl2e() {
6715 emit_int8((unsigned char)0xD9);
6716 emit_int8((unsigned char)0xEA);
6717 }
6718
6719 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding.
6720 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 };
6721 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding.
6722 static int simd_opc[4] = { 0, 0, 0x38, 0x3A };
6723
6724 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding.
6725 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
6726 if (pre > 0) {
6727 emit_int8(simd_pre[pre]);
6728 }
6729 if (rex_w) {
6730 prefixq(adr, xreg);
6731 } else {
6732 prefix(adr, xreg);
6733 }
6734 if (opc > 0) {
6735 emit_int8(0x0F);
6736 int opc2 = simd_opc[opc];
6737 if (opc2 > 0) {
6738 emit_int8(opc2);
6739 }
6740 }
6741 }
6742
6743 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
6744 if (pre > 0) {
6745 emit_int8(simd_pre[pre]);
6746 }
6747 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) : prefix_and_encode(dst_enc, src_enc);
6748 if (opc > 0) {
6749 emit_int8(0x0F);
6750 int opc2 = simd_opc[opc];
6751 if (opc2 > 0) {
6752 emit_int8(opc2);
6753 }
6754 }
6755 return encode;
6756 }
6757
6758
6759 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc) {
6760 int vector_len = _attributes->get_vector_len();
6761 bool vex_w = _attributes->is_rex_vex_w();
6762 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) {
6763 prefix(VEX_3bytes);
6764
6765 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0);
6766 byte1 = (~byte1) & 0xE0;
6767 byte1 |= opc;
6768 emit_int8(byte1);
6769
6770 int byte2 = ((~nds_enc) & 0xf) << 3;
6771 byte2 |= (vex_w ? VEX_W : 0) | ((vector_len > 0) ? 4 : 0) | pre;
6772 emit_int8(byte2);
6773 } else {
6774 prefix(VEX_2bytes);
6775
6776 int byte1 = vex_r ? VEX_R : 0;
6777 byte1 = (~byte1) & 0x80;
6778 byte1 |= ((~nds_enc) & 0xf) << 3;
6779 byte1 |= ((vector_len > 0 ) ? 4 : 0) | pre;
6780 emit_int8(byte1);
6781 }
6782 }
6783
6784 // This is a 4 byte encoding
6785 void Assembler::evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_r, bool evex_v, int nds_enc, VexSimdPrefix pre, VexOpcode opc){
6786 // EVEX 0x62 prefix
6787 prefix(EVEX_4bytes);
6788 bool vex_w = _attributes->is_rex_vex_w();
6789 int evex_encoding = (vex_w ? VEX_W : 0);
6790 // EVEX.b is not currently used for broadcast of single element or data rounding modes
6791 _attributes->set_evex_encoding(evex_encoding);
6792
6793 // P0: byte 2, initialized to RXBR`00mm
6794 // instead of not'd
6795 int byte2 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0) | (evex_r ? EVEX_Rb : 0);
6796 byte2 = (~byte2) & 0xF0;
6797 // confine opc opcode extensions in mm bits to lower two bits
6798 // of form {0F, 0F_38, 0F_3A}
6799 byte2 |= opc;
6800 emit_int8(byte2);
6801
6802 // P1: byte 3 as Wvvvv1pp
6803 int byte3 = ((~nds_enc) & 0xf) << 3;
6804 // p[10] is always 1
6805 byte3 |= EVEX_F;
6806 byte3 |= (vex_w & 1) << 7;
6807 // confine pre opcode extensions in pp bits to lower two bits
6808 // of form {66, F3, F2}
6809 byte3 |= pre;
6810 emit_int8(byte3);
6811
6812 // P2: byte 4 as zL'Lbv'aaa
6813 int byte4 = (_attributes->is_no_reg_mask()) ? 0 : 1; // kregs are implemented in the low 3 bits as aaa (hard code k1, it will be initialized for now)
6814 // EVEX.v` for extending EVEX.vvvv or VIDX
6815 byte4 |= (evex_v ? 0: EVEX_V);
6816 // third EXEC.b for broadcast actions
6817 byte4 |= (_attributes->is_extended_context() ? EVEX_Rb : 0);
6818 // fourth EVEX.L'L for vector length : 0 is 128, 1 is 256, 2 is 512, currently we do not support 1024
6819 byte4 |= ((_attributes->get_vector_len())& 0x3) << 5;
6820 // last is EVEX.z for zero/merge actions
6821 byte4 |= (_attributes->is_clear_context() ? EVEX_Z : 0);
6822 emit_int8(byte4);
6823 }
6824
6825 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) {
6826 bool vex_r = ((xreg_enc & 8) == 8) ? 1 : 0;
6827 bool vex_b = adr.base_needs_rex();
6828 bool vex_x = adr.index_needs_rex();
6829 set_attributes(attributes);
6830 attributes->set_current_assembler(this);
6831
6832 // if vector length is turned off, revert to AVX for vectors smaller than 512-bit
6833 if (UseAVX > 2 && _legacy_mode_vl && attributes->uses_vl()) {
6834 switch (attributes->get_vector_len()) {
6835 case AVX_128bit:
6836 case AVX_256bit:
6837 attributes->set_is_legacy_mode();
6838 break;
6839 }
6840 }
6841
6842 // For pure EVEX check and see if this instruction
6843 // is allowed in legacy mode and has resources which will
6844 // fit in it. Pure EVEX instructions will use set_is_evex_instruction in their definition,
6845 // else that field is set when we encode to EVEX
6846 if (UseAVX > 2 && !attributes->is_legacy_mode() &&
6847 !_is_managed && !attributes->is_evex_instruction()) {
6848 if (!_legacy_mode_vl && attributes->get_vector_len() != AVX_512bit) {
6849 bool check_register_bank = NOT_IA32(true) IA32_ONLY(false);
6850 if (check_register_bank) {
6851 // check nds_enc and xreg_enc for upper bank usage
6852 if (nds_enc < 16 && xreg_enc < 16) {
6853 attributes->set_is_legacy_mode();
6854 }
6855 } else {
6856 attributes->set_is_legacy_mode();
6857 }
6858 }
6859 }
6860
6861 _is_managed = false;
6862 if (UseAVX > 2 && !attributes->is_legacy_mode())
6863 {
6864 bool evex_r = (xreg_enc >= 16);
6865 bool evex_v = (nds_enc >= 16);
6866 attributes->set_is_evex_instruction();
6867 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc);
6868 } else {
6869 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc);
6870 }
6871 }
6872
6873 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) {
6874 bool vex_r = ((dst_enc & 8) == 8) ? 1 : 0;
6875 bool vex_b = ((src_enc & 8) == 8) ? 1 : 0;
6876 bool vex_x = false;
6877 set_attributes(attributes);
6878 attributes->set_current_assembler(this);
6879 bool check_register_bank = NOT_IA32(true) IA32_ONLY(false);
6880
6881 // if vector length is turned off, revert to AVX for vectors smaller than 512-bit
6882 if (UseAVX > 2 && _legacy_mode_vl && attributes->uses_vl()) {
6883 switch (attributes->get_vector_len()) {
6884 case AVX_128bit:
6885 case AVX_256bit:
6886 if (check_register_bank) {
6887 if (dst_enc >= 16 || nds_enc >= 16 || src_enc >= 16) {
6888 // up propagate arithmetic instructions to meet RA requirements
6889 attributes->set_vector_len(AVX_512bit);
6890 } else {
6891 attributes->set_is_legacy_mode();
6892 }
6893 } else {
6894 attributes->set_is_legacy_mode();
6895 }
6896 break;
6897 }
6898 }
6899
6900 // For pure EVEX check and see if this instruction
6901 // is allowed in legacy mode and has resources which will
6902 // fit in it. Pure EVEX instructions will use set_is_evex_instruction in their definition,
6903 // else that field is set when we encode to EVEX
6904 if (UseAVX > 2 && !attributes->is_legacy_mode() &&
6905 !_is_managed && !attributes->is_evex_instruction()) {
6906 if (!_legacy_mode_vl && attributes->get_vector_len() != AVX_512bit) {
6907 if (check_register_bank) {
6908 // check dst_enc, nds_enc and src_enc for upper bank usage
6909 if (dst_enc < 16 && nds_enc < 16 && src_enc < 16) {
6910 attributes->set_is_legacy_mode();
6911 }
6912 } else {
6913 attributes->set_is_legacy_mode();
6914 }
6915 }
6916 }
6917
6918 _is_managed = false;
6919 if (UseAVX > 2 && !attributes->is_legacy_mode())
6920 {
6921 bool evex_r = (dst_enc >= 16);
6922 bool evex_v = (nds_enc >= 16);
6923 // can use vex_x as bank extender on rm encoding
6924 vex_x = (src_enc >= 16);
6925 attributes->set_is_evex_instruction();
6926 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc);
6927 } else {
6928 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc);
6929 }
6930
6931 // return modrm byte components for operands
6932 return (((dst_enc & 7) << 3) | (src_enc & 7));
6933 }
6934
6935
6936 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre,
6937 VexOpcode opc, InstructionAttr *attributes) {
6938 if (UseAVX > 0) {
6939 int xreg_enc = xreg->encoding();
6940 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
6941 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, attributes);
6942 } else {
6943 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding");
6944 rex_prefix(adr, xreg, pre, opc, attributes->is_rex_vex_w());
6945 }
6946 }
6947
6948 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre,
6949 VexOpcode opc, InstructionAttr *attributes) {
6950 int dst_enc = dst->encoding();
6951 int src_enc = src->encoding();
6952 if (UseAVX > 0) {
6953 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
6954 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, attributes);
6955 } else {
6956 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding");
6957 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, attributes->is_rex_vex_w());
6958 }
6959 }
6960
6961 void Assembler::cmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) {
6962 assert(VM_Version::supports_avx(), "");
6963 assert(!VM_Version::supports_evex(), "");
6964 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6965 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6966 emit_int8((unsigned char)0xC2);
6967 emit_int8((unsigned char)(0xC0 | encode));
6968 emit_int8((unsigned char)(0xF & cop));
6969 }
6970
6971 void Assembler::vpblendd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) {
6972 assert(VM_Version::supports_avx(), "");
6973 assert(!VM_Version::supports_evex(), "");
6974 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6975 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
6976 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6977 emit_int8((unsigned char)0x4B);
6978 emit_int8((unsigned char)(0xC0 | encode));
6979 int src2_enc = src2->encoding();
6980 emit_int8((unsigned char)(0xF0 & src2_enc<<4));
6981 }
6982
6983
6984 #ifndef _LP64
6985
6986 void Assembler::incl(Register dst) {
6987 // Don't use it directly. Use MacroAssembler::incrementl() instead.
6988 emit_int8(0x40 | dst->encoding());
6989 }
6990
6991 void Assembler::lea(Register dst, Address src) {
6992 leal(dst, src);
6993 }
6994
6995 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
6996 InstructionMark im(this);
6997 emit_int8((unsigned char)0xC7);
6998 emit_operand(rax, dst);
6999 emit_data((int)imm32, rspec, 0);
7000 }
7001
7002 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
7003 InstructionMark im(this);
7004 int encode = prefix_and_encode(dst->encoding());
7005 emit_int8((unsigned char)(0xB8 | encode));
7006 emit_data((int)imm32, rspec, 0);
7007 }
7008
7009 void Assembler::popa() { // 32bit
7010 emit_int8(0x61);
7011 }
7012
7013 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
7014 InstructionMark im(this);
7015 emit_int8(0x68);
7016 emit_data(imm32, rspec, 0);
7017 }
7018
7019 void Assembler::pusha() { // 32bit
7020 emit_int8(0x60);
7021 }
7022
7023 void Assembler::set_byte_if_not_zero(Register dst) {
7024 emit_int8(0x0F);
7025 emit_int8((unsigned char)0x95);
7026 emit_int8((unsigned char)(0xE0 | dst->encoding()));
7027 }
7028
7029 void Assembler::shldl(Register dst, Register src) {
7030 emit_int8(0x0F);
7031 emit_int8((unsigned char)0xA5);
7032 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
7033 }
7034
7035 // 0F A4 / r ib
7036 void Assembler::shldl(Register dst, Register src, int8_t imm8) {
7037 emit_int8(0x0F);
7038 emit_int8((unsigned char)0xA4);
7039 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
7040 emit_int8(imm8);
7041 }
7042
7043 void Assembler::shrdl(Register dst, Register src) {
7044 emit_int8(0x0F);
7045 emit_int8((unsigned char)0xAD);
7046 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
7047 }
7048
7049 #else // LP64
7050
7051 void Assembler::set_byte_if_not_zero(Register dst) {
7052 int enc = prefix_and_encode(dst->encoding(), true);
7053 emit_int8(0x0F);
7054 emit_int8((unsigned char)0x95);
7055 emit_int8((unsigned char)(0xE0 | enc));
7056 }
7057
7058 // 64bit only pieces of the assembler
7059 // This should only be used by 64bit instructions that can use rip-relative
7060 // it cannot be used by instructions that want an immediate value.
7061
7062 bool Assembler::reachable(AddressLiteral adr) {
7063 int64_t disp;
7064 // None will force a 64bit literal to the code stream. Likely a placeholder
7065 // for something that will be patched later and we need to certain it will
7066 // always be reachable.
7067 if (adr.reloc() == relocInfo::none) {
7068 return false;
7069 }
7070 if (adr.reloc() == relocInfo::internal_word_type) {
7071 // This should be rip relative and easily reachable.
7072 return true;
7073 }
7074 if (adr.reloc() == relocInfo::virtual_call_type ||
7075 adr.reloc() == relocInfo::opt_virtual_call_type ||
7076 adr.reloc() == relocInfo::static_call_type ||
7077 adr.reloc() == relocInfo::static_stub_type ) {
7078 // This should be rip relative within the code cache and easily
7079 // reachable until we get huge code caches. (At which point
7080 // ic code is going to have issues).
7081 return true;
7082 }
7083 if (adr.reloc() != relocInfo::external_word_type &&
7084 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special
7085 adr.reloc() != relocInfo::poll_type && // relocs to identify them
7086 adr.reloc() != relocInfo::runtime_call_type ) {
7087 return false;
7088 }
7089
7090 // Stress the correction code
7091 if (ForceUnreachable) {
7092 // Must be runtimecall reloc, see if it is in the codecache
7093 // Flipping stuff in the codecache to be unreachable causes issues
7094 // with things like inline caches where the additional instructions
7095 // are not handled.
7096 if (CodeCache::find_blob(adr._target) == NULL) {
7097 return false;
7098 }
7099 }
7100 // For external_word_type/runtime_call_type if it is reachable from where we
7101 // are now (possibly a temp buffer) and where we might end up
7102 // anywhere in the codeCache then we are always reachable.
7103 // This would have to change if we ever save/restore shared code
7104 // to be more pessimistic.
7105 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int));
7106 if (!is_simm32(disp)) return false;
7107 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int));
7108 if (!is_simm32(disp)) return false;
7109
7110 disp = (int64_t)adr._target - ((int64_t)pc() + sizeof(int));
7111
7112 // Because rip relative is a disp + address_of_next_instruction and we
7113 // don't know the value of address_of_next_instruction we apply a fudge factor
7114 // to make sure we will be ok no matter the size of the instruction we get placed into.
7115 // We don't have to fudge the checks above here because they are already worst case.
7116
7117 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal
7118 // + 4 because better safe than sorry.
7119 const int fudge = 12 + 4;
7120 if (disp < 0) {
7121 disp -= fudge;
7122 } else {
7123 disp += fudge;
7124 }
7125 return is_simm32(disp);
7126 }
7127
7128 // Check if the polling page is not reachable from the code cache using rip-relative
7129 // addressing.
7130 bool Assembler::is_polling_page_far() {
7131 intptr_t addr = (intptr_t)os::get_polling_page();
7132 return ForceUnreachable ||
7133 !is_simm32(addr - (intptr_t)CodeCache::low_bound()) ||
7134 !is_simm32(addr - (intptr_t)CodeCache::high_bound());
7135 }
7136
7137 void Assembler::emit_data64(jlong data,
7138 relocInfo::relocType rtype,
7139 int format) {
7140 if (rtype == relocInfo::none) {
7141 emit_int64(data);
7142 } else {
7143 emit_data64(data, Relocation::spec_simple(rtype), format);
7144 }
7145 }
7146
7147 void Assembler::emit_data64(jlong data,
7148 RelocationHolder const& rspec,
7149 int format) {
7150 assert(imm_operand == 0, "default format must be immediate in this file");
7151 assert(imm_operand == format, "must be immediate");
7152 assert(inst_mark() != NULL, "must be inside InstructionMark");
7153 // Do not use AbstractAssembler::relocate, which is not intended for
7154 // embedded words. Instead, relocate to the enclosing instruction.
7155 code_section()->relocate(inst_mark(), rspec, format);
7156 #ifdef ASSERT
7157 check_relocation(rspec, format);
7158 #endif
7159 emit_int64(data);
7160 }
7161
7162 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) {
7163 if (reg_enc >= 8) {
7164 prefix(REX_B);
7165 reg_enc -= 8;
7166 } else if (byteinst && reg_enc >= 4) {
7167 prefix(REX);
7168 }
7169 return reg_enc;
7170 }
7171
7172 int Assembler::prefixq_and_encode(int reg_enc) {
7173 if (reg_enc < 8) {
7174 prefix(REX_W);
7175 } else {
7176 prefix(REX_WB);
7177 reg_enc -= 8;
7178 }
7179 return reg_enc;
7180 }
7181
7182 int Assembler::prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte) {
7183 if (dst_enc < 8) {
7184 if (src_enc >= 8) {
7185 prefix(REX_B);
7186 src_enc -= 8;
7187 } else if ((src_is_byte && src_enc >= 4) || (dst_is_byte && dst_enc >= 4)) {
7188 prefix(REX);
7189 }
7190 } else {
7191 if (src_enc < 8) {
7192 prefix(REX_R);
7193 } else {
7194 prefix(REX_RB);
7195 src_enc -= 8;
7196 }
7197 dst_enc -= 8;
7198 }
7199 return dst_enc << 3 | src_enc;
7200 }
7201
7202 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) {
7203 if (dst_enc < 8) {
7204 if (src_enc < 8) {
7205 prefix(REX_W);
7206 } else {
7207 prefix(REX_WB);
7208 src_enc -= 8;
7209 }
7210 } else {
7211 if (src_enc < 8) {
7212 prefix(REX_WR);
7213 } else {
7214 prefix(REX_WRB);
7215 src_enc -= 8;
7216 }
7217 dst_enc -= 8;
7218 }
7219 return dst_enc << 3 | src_enc;
7220 }
7221
7222 void Assembler::prefix(Register reg) {
7223 if (reg->encoding() >= 8) {
7224 prefix(REX_B);
7225 }
7226 }
7227
7228 void Assembler::prefix(Register dst, Register src, Prefix p) {
7229 if (src->encoding() >= 8) {
7230 p = (Prefix)(p | REX_B);
7231 }
7232 if (dst->encoding() >= 8) {
7233 p = (Prefix)( p | REX_R);
7234 }
7235 if (p != Prefix_EMPTY) {
7236 // do not generate an empty prefix
7237 prefix(p);
7238 }
7239 }
7240
7241 void Assembler::prefix(Register dst, Address adr, Prefix p) {
7242 if (adr.base_needs_rex()) {
7243 if (adr.index_needs_rex()) {
7244 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X");
7245 } else {
7246 prefix(REX_B);
7247 }
7248 } else {
7249 if (adr.index_needs_rex()) {
7250 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X");
7251 }
7252 }
7253 if (dst->encoding() >= 8) {
7254 p = (Prefix)(p | REX_R);
7255 }
7256 if (p != Prefix_EMPTY) {
7257 // do not generate an empty prefix
7258 prefix(p);
7259 }
7260 }
7261
7262 void Assembler::prefix(Address adr) {
7263 if (adr.base_needs_rex()) {
7264 if (adr.index_needs_rex()) {
7265 prefix(REX_XB);
7266 } else {
7267 prefix(REX_B);
7268 }
7269 } else {
7270 if (adr.index_needs_rex()) {
7271 prefix(REX_X);
7272 }
7273 }
7274 }
7275
7276 void Assembler::prefixq(Address adr) {
7277 if (adr.base_needs_rex()) {
7278 if (adr.index_needs_rex()) {
7279 prefix(REX_WXB);
7280 } else {
7281 prefix(REX_WB);
7282 }
7283 } else {
7284 if (adr.index_needs_rex()) {
7285 prefix(REX_WX);
7286 } else {
7287 prefix(REX_W);
7288 }
7289 }
7290 }
7291
7292
7293 void Assembler::prefix(Address adr, Register reg, bool byteinst) {
7294 if (reg->encoding() < 8) {
7295 if (adr.base_needs_rex()) {
7296 if (adr.index_needs_rex()) {
7297 prefix(REX_XB);
7298 } else {
7299 prefix(REX_B);
7300 }
7301 } else {
7302 if (adr.index_needs_rex()) {
7303 prefix(REX_X);
7304 } else if (byteinst && reg->encoding() >= 4 ) {
7305 prefix(REX);
7306 }
7307 }
7308 } else {
7309 if (adr.base_needs_rex()) {
7310 if (adr.index_needs_rex()) {
7311 prefix(REX_RXB);
7312 } else {
7313 prefix(REX_RB);
7314 }
7315 } else {
7316 if (adr.index_needs_rex()) {
7317 prefix(REX_RX);
7318 } else {
7319 prefix(REX_R);
7320 }
7321 }
7322 }
7323 }
7324
7325 void Assembler::prefixq(Address adr, Register src) {
7326 if (src->encoding() < 8) {
7327 if (adr.base_needs_rex()) {
7328 if (adr.index_needs_rex()) {
7329 prefix(REX_WXB);
7330 } else {
7331 prefix(REX_WB);
7332 }
7333 } else {
7334 if (adr.index_needs_rex()) {
7335 prefix(REX_WX);
7336 } else {
7337 prefix(REX_W);
7338 }
7339 }
7340 } else {
7341 if (adr.base_needs_rex()) {
7342 if (adr.index_needs_rex()) {
7343 prefix(REX_WRXB);
7344 } else {
7345 prefix(REX_WRB);
7346 }
7347 } else {
7348 if (adr.index_needs_rex()) {
7349 prefix(REX_WRX);
7350 } else {
7351 prefix(REX_WR);
7352 }
7353 }
7354 }
7355 }
7356
7357 void Assembler::prefix(Address adr, XMMRegister reg) {
7358 if (reg->encoding() < 8) {
7359 if (adr.base_needs_rex()) {
7360 if (adr.index_needs_rex()) {
7361 prefix(REX_XB);
7362 } else {
7363 prefix(REX_B);
7364 }
7365 } else {
7366 if (adr.index_needs_rex()) {
7367 prefix(REX_X);
7368 }
7369 }
7370 } else {
7371 if (adr.base_needs_rex()) {
7372 if (adr.index_needs_rex()) {
7373 prefix(REX_RXB);
7374 } else {
7375 prefix(REX_RB);
7376 }
7377 } else {
7378 if (adr.index_needs_rex()) {
7379 prefix(REX_RX);
7380 } else {
7381 prefix(REX_R);
7382 }
7383 }
7384 }
7385 }
7386
7387 void Assembler::prefixq(Address adr, XMMRegister src) {
7388 if (src->encoding() < 8) {
7389 if (adr.base_needs_rex()) {
7390 if (adr.index_needs_rex()) {
7391 prefix(REX_WXB);
7392 } else {
7393 prefix(REX_WB);
7394 }
7395 } else {
7396 if (adr.index_needs_rex()) {
7397 prefix(REX_WX);
7398 } else {
7399 prefix(REX_W);
7400 }
7401 }
7402 } else {
7403 if (adr.base_needs_rex()) {
7404 if (adr.index_needs_rex()) {
7405 prefix(REX_WRXB);
7406 } else {
7407 prefix(REX_WRB);
7408 }
7409 } else {
7410 if (adr.index_needs_rex()) {
7411 prefix(REX_WRX);
7412 } else {
7413 prefix(REX_WR);
7414 }
7415 }
7416 }
7417 }
7418
7419 void Assembler::adcq(Register dst, int32_t imm32) {
7420 (void) prefixq_and_encode(dst->encoding());
7421 emit_arith(0x81, 0xD0, dst, imm32);
7422 }
7423
7424 void Assembler::adcq(Register dst, Address src) {
7425 InstructionMark im(this);
7426 prefixq(src, dst);
7427 emit_int8(0x13);
7428 emit_operand(dst, src);
7429 }
7430
7431 void Assembler::adcq(Register dst, Register src) {
7432 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7433 emit_arith(0x13, 0xC0, dst, src);
7434 }
7435
7436 void Assembler::addq(Address dst, int32_t imm32) {
7437 InstructionMark im(this);
7438 prefixq(dst);
7439 emit_arith_operand(0x81, rax, dst,imm32);
7440 }
7441
7442 void Assembler::addq(Address dst, Register src) {
7443 InstructionMark im(this);
7444 prefixq(dst, src);
7445 emit_int8(0x01);
7446 emit_operand(src, dst);
7447 }
7448
7449 void Assembler::addq(Register dst, int32_t imm32) {
7450 (void) prefixq_and_encode(dst->encoding());
7451 emit_arith(0x81, 0xC0, dst, imm32);
7452 }
7453
7454 void Assembler::addq(Register dst, Address src) {
7455 InstructionMark im(this);
7456 prefixq(src, dst);
7457 emit_int8(0x03);
7458 emit_operand(dst, src);
7459 }
7460
7461 void Assembler::addq(Register dst, Register src) {
7462 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7463 emit_arith(0x03, 0xC0, dst, src);
7464 }
7465
7466 void Assembler::adcxq(Register dst, Register src) {
7467 //assert(VM_Version::supports_adx(), "adx instructions not supported");
7468 emit_int8((unsigned char)0x66);
7469 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7470 emit_int8(0x0F);
7471 emit_int8(0x38);
7472 emit_int8((unsigned char)0xF6);
7473 emit_int8((unsigned char)(0xC0 | encode));
7474 }
7475
7476 void Assembler::adoxq(Register dst, Register src) {
7477 //assert(VM_Version::supports_adx(), "adx instructions not supported");
7478 emit_int8((unsigned char)0xF3);
7479 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7480 emit_int8(0x0F);
7481 emit_int8(0x38);
7482 emit_int8((unsigned char)0xF6);
7483 emit_int8((unsigned char)(0xC0 | encode));
7484 }
7485
7486 void Assembler::andq(Address dst, int32_t imm32) {
7487 InstructionMark im(this);
7488 prefixq(dst);
7489 emit_int8((unsigned char)0x81);
7490 emit_operand(rsp, dst, 4);
7491 emit_int32(imm32);
7492 }
7493
7494 void Assembler::andq(Register dst, int32_t imm32) {
7495 (void) prefixq_and_encode(dst->encoding());
7496 emit_arith(0x81, 0xE0, dst, imm32);
7497 }
7498
7499 void Assembler::andq(Register dst, Address src) {
7500 InstructionMark im(this);
7501 prefixq(src, dst);
7502 emit_int8(0x23);
7503 emit_operand(dst, src);
7504 }
7505
7506 void Assembler::andq(Register dst, Register src) {
7507 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7508 emit_arith(0x23, 0xC0, dst, src);
7509 }
7510
7511 void Assembler::andnq(Register dst, Register src1, Register src2) {
7512 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7513 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7514 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7515 emit_int8((unsigned char)0xF2);
7516 emit_int8((unsigned char)(0xC0 | encode));
7517 }
7518
7519 void Assembler::andnq(Register dst, Register src1, Address src2) {
7520 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7521 InstructionMark im(this);
7522 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7523 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7524 emit_int8((unsigned char)0xF2);
7525 emit_operand(dst, src2);
7526 }
7527
7528 void Assembler::bsfq(Register dst, Register src) {
7529 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7530 emit_int8(0x0F);
7531 emit_int8((unsigned char)0xBC);
7532 emit_int8((unsigned char)(0xC0 | encode));
7533 }
7534
7535 void Assembler::bsrq(Register dst, Register src) {
7536 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7537 emit_int8(0x0F);
7538 emit_int8((unsigned char)0xBD);
7539 emit_int8((unsigned char)(0xC0 | encode));
7540 }
7541
7542 void Assembler::bswapq(Register reg) {
7543 int encode = prefixq_and_encode(reg->encoding());
7544 emit_int8(0x0F);
7545 emit_int8((unsigned char)(0xC8 | encode));
7546 }
7547
7548 void Assembler::blsiq(Register dst, Register src) {
7549 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7550 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7551 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7552 emit_int8((unsigned char)0xF3);
7553 emit_int8((unsigned char)(0xC0 | encode));
7554 }
7555
7556 void Assembler::blsiq(Register dst, Address src) {
7557 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7558 InstructionMark im(this);
7559 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7560 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7561 emit_int8((unsigned char)0xF3);
7562 emit_operand(rbx, src);
7563 }
7564
7565 void Assembler::blsmskq(Register dst, Register src) {
7566 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7567 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7568 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7569 emit_int8((unsigned char)0xF3);
7570 emit_int8((unsigned char)(0xC0 | encode));
7571 }
7572
7573 void Assembler::blsmskq(Register dst, Address src) {
7574 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7575 InstructionMark im(this);
7576 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7577 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7578 emit_int8((unsigned char)0xF3);
7579 emit_operand(rdx, src);
7580 }
7581
7582 void Assembler::blsrq(Register dst, Register src) {
7583 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7584 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7585 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7586 emit_int8((unsigned char)0xF3);
7587 emit_int8((unsigned char)(0xC0 | encode));
7588 }
7589
7590 void Assembler::blsrq(Register dst, Address src) {
7591 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7592 InstructionMark im(this);
7593 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7594 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7595 emit_int8((unsigned char)0xF3);
7596 emit_operand(rcx, src);
7597 }
7598
7599 void Assembler::cdqq() {
7600 prefix(REX_W);
7601 emit_int8((unsigned char)0x99);
7602 }
7603
7604 void Assembler::clflush(Address adr) {
7605 prefix(adr);
7606 emit_int8(0x0F);
7607 emit_int8((unsigned char)0xAE);
7608 emit_operand(rdi, adr);
7609 }
7610
7611 void Assembler::cmovq(Condition cc, Register dst, Register src) {
7612 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7613 emit_int8(0x0F);
7614 emit_int8(0x40 | cc);
7615 emit_int8((unsigned char)(0xC0 | encode));
7616 }
7617
7618 void Assembler::cmovq(Condition cc, Register dst, Address src) {
7619 InstructionMark im(this);
7620 prefixq(src, dst);
7621 emit_int8(0x0F);
7622 emit_int8(0x40 | cc);
7623 emit_operand(dst, src);
7624 }
7625
7626 void Assembler::cmpq(Address dst, int32_t imm32) {
7627 InstructionMark im(this);
7628 prefixq(dst);
7629 emit_int8((unsigned char)0x81);
7630 emit_operand(rdi, dst, 4);
7631 emit_int32(imm32);
7632 }
7633
7634 void Assembler::cmpq(Register dst, int32_t imm32) {
7635 (void) prefixq_and_encode(dst->encoding());
7636 emit_arith(0x81, 0xF8, dst, imm32);
7637 }
7638
7639 void Assembler::cmpq(Address dst, Register src) {
7640 InstructionMark im(this);
7641 prefixq(dst, src);
7642 emit_int8(0x3B);
7643 emit_operand(src, dst);
7644 }
7645
7646 void Assembler::cmpq(Register dst, Register src) {
7647 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7648 emit_arith(0x3B, 0xC0, dst, src);
7649 }
7650
7651 void Assembler::cmpq(Register dst, Address src) {
7652 InstructionMark im(this);
7653 prefixq(src, dst);
7654 emit_int8(0x3B);
7655 emit_operand(dst, src);
7656 }
7657
7658 void Assembler::cmpxchgq(Register reg, Address adr) {
7659 InstructionMark im(this);
7660 prefixq(adr, reg);
7661 emit_int8(0x0F);
7662 emit_int8((unsigned char)0xB1);
7663 emit_operand(reg, adr);
7664 }
7665
7666 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
7667 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7668 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7669 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
7670 emit_int8(0x2A);
7671 emit_int8((unsigned char)(0xC0 | encode));
7672 }
7673
7674 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) {
7675 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7676 InstructionMark im(this);
7677 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7678 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
7679 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
7680 emit_int8(0x2A);
7681 emit_operand(dst, src);
7682 }
7683
7684 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) {
7685 NOT_LP64(assert(VM_Version::supports_sse(), ""));
7686 InstructionMark im(this);
7687 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7688 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
7689 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
7690 emit_int8(0x2A);
7691 emit_operand(dst, src);
7692 }
7693
7694 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
7695 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7696 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7697 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
7698 emit_int8(0x2C);
7699 emit_int8((unsigned char)(0xC0 | encode));
7700 }
7701
7702 void Assembler::cvttss2siq(Register dst, XMMRegister src) {
7703 NOT_LP64(assert(VM_Version::supports_sse(), ""));
7704 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7705 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
7706 emit_int8(0x2C);
7707 emit_int8((unsigned char)(0xC0 | encode));
7708 }
7709
7710 void Assembler::decl(Register dst) {
7711 // Don't use it directly. Use MacroAssembler::decrementl() instead.
7712 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
7713 int encode = prefix_and_encode(dst->encoding());
7714 emit_int8((unsigned char)0xFF);
7715 emit_int8((unsigned char)(0xC8 | encode));
7716 }
7717
7718 void Assembler::decq(Register dst) {
7719 // Don't use it directly. Use MacroAssembler::decrementq() instead.
7720 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
7721 int encode = prefixq_and_encode(dst->encoding());
7722 emit_int8((unsigned char)0xFF);
7723 emit_int8(0xC8 | encode);
7724 }
7725
7726 void Assembler::decq(Address dst) {
7727 // Don't use it directly. Use MacroAssembler::decrementq() instead.
7728 InstructionMark im(this);
7729 prefixq(dst);
7730 emit_int8((unsigned char)0xFF);
7731 emit_operand(rcx, dst);
7732 }
7733
7734 void Assembler::fxrstor(Address src) {
7735 prefixq(src);
7736 emit_int8(0x0F);
7737 emit_int8((unsigned char)0xAE);
7738 emit_operand(as_Register(1), src);
7739 }
7740
7741 void Assembler::xrstor(Address src) {
7742 prefixq(src);
7743 emit_int8(0x0F);
7744 emit_int8((unsigned char)0xAE);
7745 emit_operand(as_Register(5), src);
7746 }
7747
7748 void Assembler::fxsave(Address dst) {
7749 prefixq(dst);
7750 emit_int8(0x0F);
7751 emit_int8((unsigned char)0xAE);
7752 emit_operand(as_Register(0), dst);
7753 }
7754
7755 void Assembler::xsave(Address dst) {
7756 prefixq(dst);
7757 emit_int8(0x0F);
7758 emit_int8((unsigned char)0xAE);
7759 emit_operand(as_Register(4), dst);
7760 }
7761
7762 void Assembler::idivq(Register src) {
7763 int encode = prefixq_and_encode(src->encoding());
7764 emit_int8((unsigned char)0xF7);
7765 emit_int8((unsigned char)(0xF8 | encode));
7766 }
7767
7768 void Assembler::imulq(Register dst, Register src) {
7769 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7770 emit_int8(0x0F);
7771 emit_int8((unsigned char)0xAF);
7772 emit_int8((unsigned char)(0xC0 | encode));
7773 }
7774
7775 void Assembler::imulq(Register dst, Register src, int value) {
7776 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7777 if (is8bit(value)) {
7778 emit_int8(0x6B);
7779 emit_int8((unsigned char)(0xC0 | encode));
7780 emit_int8(value & 0xFF);
7781 } else {
7782 emit_int8(0x69);
7783 emit_int8((unsigned char)(0xC0 | encode));
7784 emit_int32(value);
7785 }
7786 }
7787
7788 void Assembler::imulq(Register dst, Address src) {
7789 InstructionMark im(this);
7790 prefixq(src, dst);
7791 emit_int8(0x0F);
7792 emit_int8((unsigned char) 0xAF);
7793 emit_operand(dst, src);
7794 }
7795
7796 void Assembler::incl(Register dst) {
7797 // Don't use it directly. Use MacroAssembler::incrementl() instead.
7798 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
7799 int encode = prefix_and_encode(dst->encoding());
7800 emit_int8((unsigned char)0xFF);
7801 emit_int8((unsigned char)(0xC0 | encode));
7802 }
7803
7804 void Assembler::incq(Register dst) {
7805 // Don't use it directly. Use MacroAssembler::incrementq() instead.
7806 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
7807 int encode = prefixq_and_encode(dst->encoding());
7808 emit_int8((unsigned char)0xFF);
7809 emit_int8((unsigned char)(0xC0 | encode));
7810 }
7811
7812 void Assembler::incq(Address dst) {
7813 // Don't use it directly. Use MacroAssembler::incrementq() instead.
7814 InstructionMark im(this);
7815 prefixq(dst);
7816 emit_int8((unsigned char)0xFF);
7817 emit_operand(rax, dst);
7818 }
7819
7820 void Assembler::lea(Register dst, Address src) {
7821 leaq(dst, src);
7822 }
7823
7824 void Assembler::leaq(Register dst, Address src) {
7825 InstructionMark im(this);
7826 prefixq(src, dst);
7827 emit_int8((unsigned char)0x8D);
7828 emit_operand(dst, src);
7829 }
7830
7831 void Assembler::mov64(Register dst, int64_t imm64) {
7832 InstructionMark im(this);
7833 int encode = prefixq_and_encode(dst->encoding());
7834 emit_int8((unsigned char)(0xB8 | encode));
7835 emit_int64(imm64);
7836 }
7837
7838 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) {
7839 InstructionMark im(this);
7840 int encode = prefixq_and_encode(dst->encoding());
7841 emit_int8(0xB8 | encode);
7842 emit_data64(imm64, rspec);
7843 }
7844
7845 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) {
7846 InstructionMark im(this);
7847 int encode = prefix_and_encode(dst->encoding());
7848 emit_int8((unsigned char)(0xB8 | encode));
7849 emit_data((int)imm32, rspec, narrow_oop_operand);
7850 }
7851
7852 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) {
7853 InstructionMark im(this);
7854 prefix(dst);
7855 emit_int8((unsigned char)0xC7);
7856 emit_operand(rax, dst, 4);
7857 emit_data((int)imm32, rspec, narrow_oop_operand);
7858 }
7859
7860 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) {
7861 InstructionMark im(this);
7862 int encode = prefix_and_encode(src1->encoding());
7863 emit_int8((unsigned char)0x81);
7864 emit_int8((unsigned char)(0xF8 | encode));
7865 emit_data((int)imm32, rspec, narrow_oop_operand);
7866 }
7867
7868 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) {
7869 InstructionMark im(this);
7870 prefix(src1);
7871 emit_int8((unsigned char)0x81);
7872 emit_operand(rax, src1, 4);
7873 emit_data((int)imm32, rspec, narrow_oop_operand);
7874 }
7875
7876 void Assembler::lzcntq(Register dst, Register src) {
7877 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
7878 emit_int8((unsigned char)0xF3);
7879 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7880 emit_int8(0x0F);
7881 emit_int8((unsigned char)0xBD);
7882 emit_int8((unsigned char)(0xC0 | encode));
7883 }
7884
7885 void Assembler::movdq(XMMRegister dst, Register src) {
7886 // table D-1 says MMX/SSE2
7887 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7888 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7889 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7890 emit_int8(0x6E);
7891 emit_int8((unsigned char)(0xC0 | encode));
7892 }
7893
7894 void Assembler::movdq(Register dst, XMMRegister src) {
7895 // table D-1 says MMX/SSE2
7896 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7897 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7898 // swap src/dst to get correct prefix
7899 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7900 emit_int8(0x7E);
7901 emit_int8((unsigned char)(0xC0 | encode));
7902 }
7903
7904 void Assembler::movq(Register dst, Register src) {
7905 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7906 emit_int8((unsigned char)0x8B);
7907 emit_int8((unsigned char)(0xC0 | encode));
7908 }
7909
7910 void Assembler::movq(Register dst, Address src) {
7911 InstructionMark im(this);
7912 prefixq(src, dst);
7913 emit_int8((unsigned char)0x8B);
7914 emit_operand(dst, src);
7915 }
7916
7917 void Assembler::movq(Address dst, Register src) {
7918 InstructionMark im(this);
7919 prefixq(dst, src);
7920 emit_int8((unsigned char)0x89);
7921 emit_operand(src, dst);
7922 }
7923
7924 void Assembler::movsbq(Register dst, Address src) {
7925 InstructionMark im(this);
7926 prefixq(src, dst);
7927 emit_int8(0x0F);
7928 emit_int8((unsigned char)0xBE);
7929 emit_operand(dst, src);
7930 }
7931
7932 void Assembler::movsbq(Register dst, Register src) {
7933 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7934 emit_int8(0x0F);
7935 emit_int8((unsigned char)0xBE);
7936 emit_int8((unsigned char)(0xC0 | encode));
7937 }
7938
7939 void Assembler::movslq(Register dst, int32_t imm32) {
7940 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx)
7941 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx)
7942 // as a result we shouldn't use until tested at runtime...
7943 ShouldNotReachHere();
7944 InstructionMark im(this);
7945 int encode = prefixq_and_encode(dst->encoding());
7946 emit_int8((unsigned char)(0xC7 | encode));
7947 emit_int32(imm32);
7948 }
7949
7950 void Assembler::movslq(Address dst, int32_t imm32) {
7951 assert(is_simm32(imm32), "lost bits");
7952 InstructionMark im(this);
7953 prefixq(dst);
7954 emit_int8((unsigned char)0xC7);
7955 emit_operand(rax, dst, 4);
7956 emit_int32(imm32);
7957 }
7958
7959 void Assembler::movslq(Register dst, Address src) {
7960 InstructionMark im(this);
7961 prefixq(src, dst);
7962 emit_int8(0x63);
7963 emit_operand(dst, src);
7964 }
7965
7966 void Assembler::movslq(Register dst, Register src) {
7967 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7968 emit_int8(0x63);
7969 emit_int8((unsigned char)(0xC0 | encode));
7970 }
7971
7972 void Assembler::movswq(Register dst, Address src) {
7973 InstructionMark im(this);
7974 prefixq(src, dst);
7975 emit_int8(0x0F);
7976 emit_int8((unsigned char)0xBF);
7977 emit_operand(dst, src);
7978 }
7979
7980 void Assembler::movswq(Register dst, Register src) {
7981 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7982 emit_int8((unsigned char)0x0F);
7983 emit_int8((unsigned char)0xBF);
7984 emit_int8((unsigned char)(0xC0 | encode));
7985 }
7986
7987 void Assembler::movzbq(Register dst, Address src) {
7988 InstructionMark im(this);
7989 prefixq(src, dst);
7990 emit_int8((unsigned char)0x0F);
7991 emit_int8((unsigned char)0xB6);
7992 emit_operand(dst, src);
7993 }
7994
7995 void Assembler::movzbq(Register dst, Register src) {
7996 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7997 emit_int8(0x0F);
7998 emit_int8((unsigned char)0xB6);
7999 emit_int8(0xC0 | encode);
8000 }
8001
8002 void Assembler::movzwq(Register dst, Address src) {
8003 InstructionMark im(this);
8004 prefixq(src, dst);
8005 emit_int8((unsigned char)0x0F);
8006 emit_int8((unsigned char)0xB7);
8007 emit_operand(dst, src);
8008 }
8009
8010 void Assembler::movzwq(Register dst, Register src) {
8011 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8012 emit_int8((unsigned char)0x0F);
8013 emit_int8((unsigned char)0xB7);
8014 emit_int8((unsigned char)(0xC0 | encode));
8015 }
8016
8017 void Assembler::mulq(Address src) {
8018 InstructionMark im(this);
8019 prefixq(src);
8020 emit_int8((unsigned char)0xF7);
8021 emit_operand(rsp, src);
8022 }
8023
8024 void Assembler::mulq(Register src) {
8025 int encode = prefixq_and_encode(src->encoding());
8026 emit_int8((unsigned char)0xF7);
8027 emit_int8((unsigned char)(0xE0 | encode));
8028 }
8029
8030 void Assembler::mulxq(Register dst1, Register dst2, Register src) {
8031 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
8032 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
8033 int encode = vex_prefix_and_encode(dst1->encoding(), dst2->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
8034 emit_int8((unsigned char)0xF6);
8035 emit_int8((unsigned char)(0xC0 | encode));
8036 }
8037
8038 void Assembler::negq(Register dst) {
8039 int encode = prefixq_and_encode(dst->encoding());
8040 emit_int8((unsigned char)0xF7);
8041 emit_int8((unsigned char)(0xD8 | encode));
8042 }
8043
8044 void Assembler::notq(Register dst) {
8045 int encode = prefixq_and_encode(dst->encoding());
8046 emit_int8((unsigned char)0xF7);
8047 emit_int8((unsigned char)(0xD0 | encode));
8048 }
8049
8050 void Assembler::orq(Address dst, int32_t imm32) {
8051 InstructionMark im(this);
8052 prefixq(dst);
8053 emit_int8((unsigned char)0x81);
8054 emit_operand(rcx, dst, 4);
8055 emit_int32(imm32);
8056 }
8057
8058 void Assembler::orq(Register dst, int32_t imm32) {
8059 (void) prefixq_and_encode(dst->encoding());
8060 emit_arith(0x81, 0xC8, dst, imm32);
8061 }
8062
8063 void Assembler::orq(Register dst, Address src) {
8064 InstructionMark im(this);
8065 prefixq(src, dst);
8066 emit_int8(0x0B);
8067 emit_operand(dst, src);
8068 }
8069
8070 void Assembler::orq(Register dst, Register src) {
8071 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8072 emit_arith(0x0B, 0xC0, dst, src);
8073 }
8074
8075 void Assembler::popa() { // 64bit
8076 movq(r15, Address(rsp, 0));
8077 movq(r14, Address(rsp, wordSize));
8078 movq(r13, Address(rsp, 2 * wordSize));
8079 movq(r12, Address(rsp, 3 * wordSize));
8080 movq(r11, Address(rsp, 4 * wordSize));
8081 movq(r10, Address(rsp, 5 * wordSize));
8082 movq(r9, Address(rsp, 6 * wordSize));
8083 movq(r8, Address(rsp, 7 * wordSize));
8084 movq(rdi, Address(rsp, 8 * wordSize));
8085 movq(rsi, Address(rsp, 9 * wordSize));
8086 movq(rbp, Address(rsp, 10 * wordSize));
8087 // skip rsp
8088 movq(rbx, Address(rsp, 12 * wordSize));
8089 movq(rdx, Address(rsp, 13 * wordSize));
8090 movq(rcx, Address(rsp, 14 * wordSize));
8091 movq(rax, Address(rsp, 15 * wordSize));
8092
8093 addq(rsp, 16 * wordSize);
8094 }
8095
8096 void Assembler::popcntq(Register dst, Address src) {
8097 assert(VM_Version::supports_popcnt(), "must support");
8098 InstructionMark im(this);
8099 emit_int8((unsigned char)0xF3);
8100 prefixq(src, dst);
8101 emit_int8((unsigned char)0x0F);
8102 emit_int8((unsigned char)0xB8);
8103 emit_operand(dst, src);
8104 }
8105
8106 void Assembler::popcntq(Register dst, Register src) {
8107 assert(VM_Version::supports_popcnt(), "must support");
8108 emit_int8((unsigned char)0xF3);
8109 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8110 emit_int8((unsigned char)0x0F);
8111 emit_int8((unsigned char)0xB8);
8112 emit_int8((unsigned char)(0xC0 | encode));
8113 }
8114
8115 void Assembler::popq(Address dst) {
8116 InstructionMark im(this);
8117 prefixq(dst);
8118 emit_int8((unsigned char)0x8F);
8119 emit_operand(rax, dst);
8120 }
8121
8122 void Assembler::pusha() { // 64bit
8123 // we have to store original rsp. ABI says that 128 bytes
8124 // below rsp are local scratch.
8125 movq(Address(rsp, -5 * wordSize), rsp);
8126
8127 subq(rsp, 16 * wordSize);
8128
8129 movq(Address(rsp, 15 * wordSize), rax);
8130 movq(Address(rsp, 14 * wordSize), rcx);
8131 movq(Address(rsp, 13 * wordSize), rdx);
8132 movq(Address(rsp, 12 * wordSize), rbx);
8133 // skip rsp
8134 movq(Address(rsp, 10 * wordSize), rbp);
8135 movq(Address(rsp, 9 * wordSize), rsi);
8136 movq(Address(rsp, 8 * wordSize), rdi);
8137 movq(Address(rsp, 7 * wordSize), r8);
8138 movq(Address(rsp, 6 * wordSize), r9);
8139 movq(Address(rsp, 5 * wordSize), r10);
8140 movq(Address(rsp, 4 * wordSize), r11);
8141 movq(Address(rsp, 3 * wordSize), r12);
8142 movq(Address(rsp, 2 * wordSize), r13);
8143 movq(Address(rsp, wordSize), r14);
8144 movq(Address(rsp, 0), r15);
8145 }
8146
8147 void Assembler::pushq(Address src) {
8148 InstructionMark im(this);
8149 prefixq(src);
8150 emit_int8((unsigned char)0xFF);
8151 emit_operand(rsi, src);
8152 }
8153
8154 void Assembler::rclq(Register dst, int imm8) {
8155 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8156 int encode = prefixq_and_encode(dst->encoding());
8157 if (imm8 == 1) {
8158 emit_int8((unsigned char)0xD1);
8159 emit_int8((unsigned char)(0xD0 | encode));
8160 } else {
8161 emit_int8((unsigned char)0xC1);
8162 emit_int8((unsigned char)(0xD0 | encode));
8163 emit_int8(imm8);
8164 }
8165 }
8166
8167 void Assembler::rcrq(Register dst, int imm8) {
8168 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8169 int encode = prefixq_and_encode(dst->encoding());
8170 if (imm8 == 1) {
8171 emit_int8((unsigned char)0xD1);
8172 emit_int8((unsigned char)(0xD8 | encode));
8173 } else {
8174 emit_int8((unsigned char)0xC1);
8175 emit_int8((unsigned char)(0xD8 | encode));
8176 emit_int8(imm8);
8177 }
8178 }
8179
8180 void Assembler::rorq(Register dst, int imm8) {
8181 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8182 int encode = prefixq_and_encode(dst->encoding());
8183 if (imm8 == 1) {
8184 emit_int8((unsigned char)0xD1);
8185 emit_int8((unsigned char)(0xC8 | encode));
8186 } else {
8187 emit_int8((unsigned char)0xC1);
8188 emit_int8((unsigned char)(0xc8 | encode));
8189 emit_int8(imm8);
8190 }
8191 }
8192
8193 void Assembler::rorxq(Register dst, Register src, int imm8) {
8194 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
8195 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
8196 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes);
8197 emit_int8((unsigned char)0xF0);
8198 emit_int8((unsigned char)(0xC0 | encode));
8199 emit_int8(imm8);
8200 }
8201
8202 void Assembler::sarq(Register dst, int imm8) {
8203 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8204 int encode = prefixq_and_encode(dst->encoding());
8205 if (imm8 == 1) {
8206 emit_int8((unsigned char)0xD1);
8207 emit_int8((unsigned char)(0xF8 | encode));
8208 } else {
8209 emit_int8((unsigned char)0xC1);
8210 emit_int8((unsigned char)(0xF8 | encode));
8211 emit_int8(imm8);
8212 }
8213 }
8214
8215 void Assembler::sarq(Register dst) {
8216 int encode = prefixq_and_encode(dst->encoding());
8217 emit_int8((unsigned char)0xD3);
8218 emit_int8((unsigned char)(0xF8 | encode));
8219 }
8220
8221 void Assembler::sbbq(Address dst, int32_t imm32) {
8222 InstructionMark im(this);
8223 prefixq(dst);
8224 emit_arith_operand(0x81, rbx, dst, imm32);
8225 }
8226
8227 void Assembler::sbbq(Register dst, int32_t imm32) {
8228 (void) prefixq_and_encode(dst->encoding());
8229 emit_arith(0x81, 0xD8, dst, imm32);
8230 }
8231
8232 void Assembler::sbbq(Register dst, Address src) {
8233 InstructionMark im(this);
8234 prefixq(src, dst);
8235 emit_int8(0x1B);
8236 emit_operand(dst, src);
8237 }
8238
8239 void Assembler::sbbq(Register dst, Register src) {
8240 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8241 emit_arith(0x1B, 0xC0, dst, src);
8242 }
8243
8244 void Assembler::shlq(Register dst, int imm8) {
8245 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8246 int encode = prefixq_and_encode(dst->encoding());
8247 if (imm8 == 1) {
8248 emit_int8((unsigned char)0xD1);
8249 emit_int8((unsigned char)(0xE0 | encode));
8250 } else {
8251 emit_int8((unsigned char)0xC1);
8252 emit_int8((unsigned char)(0xE0 | encode));
8253 emit_int8(imm8);
8254 }
8255 }
8256
8257 void Assembler::shlq(Register dst) {
8258 int encode = prefixq_and_encode(dst->encoding());
8259 emit_int8((unsigned char)0xD3);
8260 emit_int8((unsigned char)(0xE0 | encode));
8261 }
8262
8263 void Assembler::shrq(Register dst, int imm8) {
8264 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8265 int encode = prefixq_and_encode(dst->encoding());
8266 emit_int8((unsigned char)0xC1);
8267 emit_int8((unsigned char)(0xE8 | encode));
8268 emit_int8(imm8);
8269 }
8270
8271 void Assembler::shrq(Register dst) {
8272 int encode = prefixq_and_encode(dst->encoding());
8273 emit_int8((unsigned char)0xD3);
8274 emit_int8(0xE8 | encode);
8275 }
8276
8277 void Assembler::subq(Address dst, int32_t imm32) {
8278 InstructionMark im(this);
8279 prefixq(dst);
8280 emit_arith_operand(0x81, rbp, dst, imm32);
8281 }
8282
8283 void Assembler::subq(Address dst, Register src) {
8284 InstructionMark im(this);
8285 prefixq(dst, src);
8286 emit_int8(0x29);
8287 emit_operand(src, dst);
8288 }
8289
8290 void Assembler::subq(Register dst, int32_t imm32) {
8291 (void) prefixq_and_encode(dst->encoding());
8292 emit_arith(0x81, 0xE8, dst, imm32);
8293 }
8294
8295 // Force generation of a 4 byte immediate value even if it fits into 8bit
8296 void Assembler::subq_imm32(Register dst, int32_t imm32) {
8297 (void) prefixq_and_encode(dst->encoding());
8298 emit_arith_imm32(0x81, 0xE8, dst, imm32);
8299 }
8300
8301 void Assembler::subq(Register dst, Address src) {
8302 InstructionMark im(this);
8303 prefixq(src, dst);
8304 emit_int8(0x2B);
8305 emit_operand(dst, src);
8306 }
8307
8308 void Assembler::subq(Register dst, Register src) {
8309 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8310 emit_arith(0x2B, 0xC0, dst, src);
8311 }
8312
8313 void Assembler::testq(Register dst, int32_t imm32) {
8314 // not using emit_arith because test
8315 // doesn't support sign-extension of
8316 // 8bit operands
8317 int encode = dst->encoding();
8318 if (encode == 0) {
8319 prefix(REX_W);
8320 emit_int8((unsigned char)0xA9);
8321 } else {
8322 encode = prefixq_and_encode(encode);
8323 emit_int8((unsigned char)0xF7);
8324 emit_int8((unsigned char)(0xC0 | encode));
8325 }
8326 emit_int32(imm32);
8327 }
8328
8329 void Assembler::testq(Register dst, Register src) {
8330 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8331 emit_arith(0x85, 0xC0, dst, src);
8332 }
8333
8334 void Assembler::xaddq(Address dst, Register src) {
8335 InstructionMark im(this);
8336 prefixq(dst, src);
8337 emit_int8(0x0F);
8338 emit_int8((unsigned char)0xC1);
8339 emit_operand(src, dst);
8340 }
8341
8342 void Assembler::xchgq(Register dst, Address src) {
8343 InstructionMark im(this);
8344 prefixq(src, dst);
8345 emit_int8((unsigned char)0x87);
8346 emit_operand(dst, src);
8347 }
8348
8349 void Assembler::xchgq(Register dst, Register src) {
8350 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8351 emit_int8((unsigned char)0x87);
8352 emit_int8((unsigned char)(0xc0 | encode));
8353 }
8354
8355 void Assembler::xorq(Register dst, Register src) {
8356 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8357 emit_arith(0x33, 0xC0, dst, src);
8358 }
8359
8360 void Assembler::xorq(Register dst, Address src) {
8361 InstructionMark im(this);
8362 prefixq(src, dst);
8363 emit_int8(0x33);
8364 emit_operand(dst, src);
8365 }
8366
8367 #endif // !LP64