1 /*
2 * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "gc/shared/cardTableModRefBS.hpp"
29 #include "gc/shared/collectedHeap.inline.hpp"
30 #include "interpreter/interpreter.hpp"
31 #include "memory/resourceArea.hpp"
32 #include "prims/methodHandles.hpp"
33 #include "runtime/biasedLocking.hpp"
34 #include "runtime/interfaceSupport.hpp"
35 #include "runtime/objectMonitor.hpp"
36 #include "runtime/os.hpp"
37 #include "runtime/sharedRuntime.hpp"
38 #include "runtime/stubRoutines.hpp"
39 #include "utilities/macros.hpp"
40 #if INCLUDE_ALL_GCS
41 #include "gc/g1/g1CollectedHeap.inline.hpp"
42 #include "gc/g1/g1SATBCardTableModRefBS.hpp"
43 #include "gc/g1/heapRegion.hpp"
44 #endif // INCLUDE_ALL_GCS
45
46 #ifdef PRODUCT
47 #define BLOCK_COMMENT(str) /* nothing */
48 #define STOP(error) stop(error)
49 #else
50 #define BLOCK_COMMENT(str) block_comment(str)
51 #define STOP(error) block_comment(error); stop(error)
52 #endif
53
54 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
55 // Implementation of AddressLiteral
56
57 // A 2-D table for managing compressed displacement(disp8) on EVEX enabled platforms.
58 unsigned char tuple_table[Assembler::EVEX_ETUP + 1][Assembler::AVX_512bit + 1] = {
59 // -----------------Table 4.5 -------------------- //
60 16, 32, 64, // EVEX_FV(0)
61 4, 4, 4, // EVEX_FV(1) - with Evex.b
62 16, 32, 64, // EVEX_FV(2) - with Evex.w
63 8, 8, 8, // EVEX_FV(3) - with Evex.w and Evex.b
64 8, 16, 32, // EVEX_HV(0)
65 4, 4, 4, // EVEX_HV(1) - with Evex.b
66 // -----------------Table 4.6 -------------------- //
67 16, 32, 64, // EVEX_FVM(0)
68 1, 1, 1, // EVEX_T1S(0)
69 2, 2, 2, // EVEX_T1S(1)
70 4, 4, 4, // EVEX_T1S(2)
71 8, 8, 8, // EVEX_T1S(3)
72 4, 4, 4, // EVEX_T1F(0)
73 8, 8, 8, // EVEX_T1F(1)
74 8, 8, 8, // EVEX_T2(0)
75 0, 16, 16, // EVEX_T2(1)
76 0, 16, 16, // EVEX_T4(0)
77 0, 0, 32, // EVEX_T4(1)
78 0, 0, 32, // EVEX_T8(0)
79 8, 16, 32, // EVEX_HVM(0)
80 4, 8, 16, // EVEX_QVM(0)
81 2, 4, 8, // EVEX_OVM(0)
82 16, 16, 16, // EVEX_M128(0)
83 8, 32, 64, // EVEX_DUP(0)
84 0, 0, 0 // EVEX_NTUP
85 };
86
87 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
88 _is_lval = false;
89 _target = target;
90 switch (rtype) {
91 case relocInfo::oop_type:
92 case relocInfo::metadata_type:
93 // Oops are a special case. Normally they would be their own section
94 // but in cases like icBuffer they are literals in the code stream that
95 // we don't have a section for. We use none so that we get a literal address
96 // which is always patchable.
97 break;
98 case relocInfo::external_word_type:
99 _rspec = external_word_Relocation::spec(target);
100 break;
101 case relocInfo::internal_word_type:
102 _rspec = internal_word_Relocation::spec(target);
103 break;
104 case relocInfo::opt_virtual_call_type:
105 _rspec = opt_virtual_call_Relocation::spec();
106 break;
107 case relocInfo::static_call_type:
108 _rspec = static_call_Relocation::spec();
109 break;
110 case relocInfo::runtime_call_type:
111 _rspec = runtime_call_Relocation::spec();
112 break;
113 case relocInfo::poll_type:
114 case relocInfo::poll_return_type:
115 _rspec = Relocation::spec_simple(rtype);
116 break;
117 case relocInfo::none:
118 break;
119 default:
120 ShouldNotReachHere();
121 break;
122 }
123 }
124
125 // Implementation of Address
126
127 #ifdef _LP64
128
129 Address Address::make_array(ArrayAddress adr) {
130 // Not implementable on 64bit machines
131 // Should have been handled higher up the call chain.
132 ShouldNotReachHere();
133 return Address();
134 }
135
136 // exceedingly dangerous constructor
137 Address::Address(int disp, address loc, relocInfo::relocType rtype) {
138 _base = noreg;
139 _index = noreg;
140 _scale = no_scale;
141 _disp = disp;
142 switch (rtype) {
143 case relocInfo::external_word_type:
144 _rspec = external_word_Relocation::spec(loc);
145 break;
146 case relocInfo::internal_word_type:
147 _rspec = internal_word_Relocation::spec(loc);
148 break;
149 case relocInfo::runtime_call_type:
150 // HMM
151 _rspec = runtime_call_Relocation::spec();
152 break;
153 case relocInfo::poll_type:
154 case relocInfo::poll_return_type:
155 _rspec = Relocation::spec_simple(rtype);
156 break;
157 case relocInfo::none:
158 break;
159 default:
160 ShouldNotReachHere();
161 }
162 }
163 #else // LP64
164
165 Address Address::make_array(ArrayAddress adr) {
166 AddressLiteral base = adr.base();
167 Address index = adr.index();
168 assert(index._disp == 0, "must not have disp"); // maybe it can?
169 Address array(index._base, index._index, index._scale, (intptr_t) base.target());
170 array._rspec = base._rspec;
171 return array;
172 }
173
174 // exceedingly dangerous constructor
175 Address::Address(address loc, RelocationHolder spec) {
176 _base = noreg;
177 _index = noreg;
178 _scale = no_scale;
179 _disp = (intptr_t) loc;
180 _rspec = spec;
181 }
182
183 #endif // _LP64
184
185
186
187 // Convert the raw encoding form into the form expected by the constructor for
188 // Address. An index of 4 (rsp) corresponds to having no index, so convert
189 // that to noreg for the Address constructor.
190 Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) {
191 RelocationHolder rspec;
192 if (disp_reloc != relocInfo::none) {
193 rspec = Relocation::spec_simple(disp_reloc);
194 }
195 bool valid_index = index != rsp->encoding();
196 if (valid_index) {
197 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));
198 madr._rspec = rspec;
199 return madr;
200 } else {
201 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));
202 madr._rspec = rspec;
203 return madr;
204 }
205 }
206
207 // Implementation of Assembler
208
209 int AbstractAssembler::code_fill_byte() {
210 return (u_char)'\xF4'; // hlt
211 }
212
213 // make this go away someday
214 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) {
215 if (rtype == relocInfo::none)
216 emit_int32(data);
217 else
218 emit_data(data, Relocation::spec_simple(rtype), format);
219 }
220
221 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) {
222 assert(imm_operand == 0, "default format must be immediate in this file");
223 assert(inst_mark() != NULL, "must be inside InstructionMark");
224 if (rspec.type() != relocInfo::none) {
225 #ifdef ASSERT
226 check_relocation(rspec, format);
227 #endif
228 // Do not use AbstractAssembler::relocate, which is not intended for
229 // embedded words. Instead, relocate to the enclosing instruction.
230
231 // hack. call32 is too wide for mask so use disp32
232 if (format == call32_operand)
233 code_section()->relocate(inst_mark(), rspec, disp32_operand);
234 else
235 code_section()->relocate(inst_mark(), rspec, format);
236 }
237 emit_int32(data);
238 }
239
240 static int encode(Register r) {
241 int enc = r->encoding();
242 if (enc >= 8) {
243 enc -= 8;
244 }
245 return enc;
246 }
247
248 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
249 assert(dst->has_byte_register(), "must have byte register");
250 assert(isByte(op1) && isByte(op2), "wrong opcode");
251 assert(isByte(imm8), "not a byte");
252 assert((op1 & 0x01) == 0, "should be 8bit operation");
253 emit_int8(op1);
254 emit_int8(op2 | encode(dst));
255 emit_int8(imm8);
256 }
257
258
259 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) {
260 assert(isByte(op1) && isByte(op2), "wrong opcode");
261 assert((op1 & 0x01) == 1, "should be 32bit operation");
262 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
263 if (is8bit(imm32)) {
264 emit_int8(op1 | 0x02); // set sign bit
265 emit_int8(op2 | encode(dst));
266 emit_int8(imm32 & 0xFF);
267 } else {
268 emit_int8(op1);
269 emit_int8(op2 | encode(dst));
270 emit_int32(imm32);
271 }
272 }
273
274 // Force generation of a 4 byte immediate value even if it fits into 8bit
275 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) {
276 assert(isByte(op1) && isByte(op2), "wrong opcode");
277 assert((op1 & 0x01) == 1, "should be 32bit operation");
278 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
279 emit_int8(op1);
280 emit_int8(op2 | encode(dst));
281 emit_int32(imm32);
282 }
283
284 // immediate-to-memory forms
285 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) {
286 assert((op1 & 0x01) == 1, "should be 32bit operation");
287 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
288 if (is8bit(imm32)) {
289 emit_int8(op1 | 0x02); // set sign bit
290 emit_operand(rm, adr, 1);
291 emit_int8(imm32 & 0xFF);
292 } else {
293 emit_int8(op1);
294 emit_operand(rm, adr, 4);
295 emit_int32(imm32);
296 }
297 }
298
299
300 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
301 assert(isByte(op1) && isByte(op2), "wrong opcode");
302 emit_int8(op1);
303 emit_int8(op2 | encode(dst) << 3 | encode(src));
304 }
305
306
307 bool Assembler::query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len,
308 int cur_tuple_type, int in_size_in_bits, int cur_encoding) {
309 int mod_idx = 0;
310 // We will test if the displacement fits the compressed format and if so
311 // apply the compression to the displacment iff the result is8bit.
312 if (VM_Version::supports_evex() && is_evex_inst) {
313 switch (cur_tuple_type) {
314 case EVEX_FV:
315 if ((cur_encoding & VEX_W) == VEX_W) {
316 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2;
317 } else {
318 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
319 }
320 break;
321
322 case EVEX_HV:
323 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
324 break;
325
326 case EVEX_FVM:
327 break;
328
329 case EVEX_T1S:
330 switch (in_size_in_bits) {
331 case EVEX_8bit:
332 break;
333
334 case EVEX_16bit:
335 mod_idx = 1;
336 break;
337
338 case EVEX_32bit:
339 mod_idx = 2;
340 break;
341
342 case EVEX_64bit:
343 mod_idx = 3;
344 break;
345 }
346 break;
347
348 case EVEX_T1F:
349 case EVEX_T2:
350 case EVEX_T4:
351 mod_idx = (in_size_in_bits == EVEX_64bit) ? 1 : 0;
352 break;
353
354 case EVEX_T8:
355 break;
356
357 case EVEX_HVM:
358 break;
359
360 case EVEX_QVM:
361 break;
362
363 case EVEX_OVM:
364 break;
365
366 case EVEX_M128:
367 break;
368
369 case EVEX_DUP:
370 break;
371
372 default:
373 assert(0, "no valid evex tuple_table entry");
374 break;
375 }
376
377 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
378 int disp_factor = tuple_table[cur_tuple_type + mod_idx][vector_len];
379 if ((disp % disp_factor) == 0) {
380 int new_disp = disp / disp_factor;
381 if ((-0x80 <= new_disp && new_disp < 0x80)) {
382 disp = new_disp;
383 }
384 } else {
385 return false;
386 }
387 }
388 }
389 return (-0x80 <= disp && disp < 0x80);
390 }
391
392
393 bool Assembler::emit_compressed_disp_byte(int &disp) {
394 int mod_idx = 0;
395 // We will test if the displacement fits the compressed format and if so
396 // apply the compression to the displacment iff the result is8bit.
397 if (VM_Version::supports_evex() && _attributes && _attributes->is_evex_instruction()) {
398 int evex_encoding = _attributes->get_evex_encoding();
399 int tuple_type = _attributes->get_tuple_type();
400 switch (tuple_type) {
401 case EVEX_FV:
402 if ((evex_encoding & VEX_W) == VEX_W) {
403 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2;
404 } else {
405 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
406 }
407 break;
408
409 case EVEX_HV:
410 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
411 break;
412
413 case EVEX_FVM:
414 break;
415
416 case EVEX_T1S:
417 switch (_attributes->get_input_size()) {
418 case EVEX_8bit:
419 break;
420
421 case EVEX_16bit:
422 mod_idx = 1;
423 break;
424
425 case EVEX_32bit:
426 mod_idx = 2;
427 break;
428
429 case EVEX_64bit:
430 mod_idx = 3;
431 break;
432 }
433 break;
434
435 case EVEX_T1F:
436 case EVEX_T2:
437 case EVEX_T4:
438 mod_idx = (_attributes->get_input_size() == EVEX_64bit) ? 1 : 0;
439 break;
440
441 case EVEX_T8:
442 break;
443
444 case EVEX_HVM:
445 break;
446
447 case EVEX_QVM:
448 break;
449
450 case EVEX_OVM:
451 break;
452
453 case EVEX_M128:
454 break;
455
456 case EVEX_DUP:
457 break;
458
459 default:
460 assert(0, "no valid evex tuple_table entry");
461 break;
462 }
463
464 int vector_len = _attributes->get_vector_len();
465 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
466 int disp_factor = tuple_table[tuple_type + mod_idx][vector_len];
467 if ((disp % disp_factor) == 0) {
468 int new_disp = disp / disp_factor;
469 if (is8bit(new_disp)) {
470 disp = new_disp;
471 }
472 } else {
473 return false;
474 }
475 }
476 }
477 return is8bit(disp);
478 }
479
480
481 void Assembler::emit_operand(Register reg, Register base, Register index,
482 Address::ScaleFactor scale, int disp,
483 RelocationHolder const& rspec,
484 int rip_relative_correction) {
485 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();
486
487 // Encode the registers as needed in the fields they are used in
488
489 int regenc = encode(reg) << 3;
490 int indexenc = index->is_valid() ? encode(index) << 3 : 0;
491 int baseenc = base->is_valid() ? encode(base) : 0;
492
493 if (base->is_valid()) {
494 if (index->is_valid()) {
495 assert(scale != Address::no_scale, "inconsistent address");
496 // [base + index*scale + disp]
497 if (disp == 0 && rtype == relocInfo::none &&
498 base != rbp LP64_ONLY(&& base != r13)) {
499 // [base + index*scale]
500 // [00 reg 100][ss index base]
501 assert(index != rsp, "illegal addressing mode");
502 emit_int8(0x04 | regenc);
503 emit_int8(scale << 6 | indexenc | baseenc);
504 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
505 // [base + index*scale + imm8]
506 // [01 reg 100][ss index base] imm8
507 assert(index != rsp, "illegal addressing mode");
508 emit_int8(0x44 | regenc);
509 emit_int8(scale << 6 | indexenc | baseenc);
510 emit_int8(disp & 0xFF);
511 } else {
512 // [base + index*scale + disp32]
513 // [10 reg 100][ss index base] disp32
514 assert(index != rsp, "illegal addressing mode");
515 emit_int8(0x84 | regenc);
516 emit_int8(scale << 6 | indexenc | baseenc);
517 emit_data(disp, rspec, disp32_operand);
518 }
519 } else if (base == rsp LP64_ONLY(|| base == r12)) {
520 // [rsp + disp]
521 if (disp == 0 && rtype == relocInfo::none) {
522 // [rsp]
523 // [00 reg 100][00 100 100]
524 emit_int8(0x04 | regenc);
525 emit_int8(0x24);
526 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
527 // [rsp + imm8]
528 // [01 reg 100][00 100 100] disp8
529 emit_int8(0x44 | regenc);
530 emit_int8(0x24);
531 emit_int8(disp & 0xFF);
532 } else {
533 // [rsp + imm32]
534 // [10 reg 100][00 100 100] disp32
535 emit_int8(0x84 | regenc);
536 emit_int8(0x24);
537 emit_data(disp, rspec, disp32_operand);
538 }
539 } else {
540 // [base + disp]
541 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode");
542 if (disp == 0 && rtype == relocInfo::none &&
543 base != rbp LP64_ONLY(&& base != r13)) {
544 // [base]
545 // [00 reg base]
546 emit_int8(0x00 | regenc | baseenc);
547 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
548 // [base + disp8]
549 // [01 reg base] disp8
550 emit_int8(0x40 | regenc | baseenc);
551 emit_int8(disp & 0xFF);
552 } else {
553 // [base + disp32]
554 // [10 reg base] disp32
555 emit_int8(0x80 | regenc | baseenc);
556 emit_data(disp, rspec, disp32_operand);
557 }
558 }
559 } else {
560 if (index->is_valid()) {
561 assert(scale != Address::no_scale, "inconsistent address");
562 // [index*scale + disp]
563 // [00 reg 100][ss index 101] disp32
564 assert(index != rsp, "illegal addressing mode");
565 emit_int8(0x04 | regenc);
566 emit_int8(scale << 6 | indexenc | 0x05);
567 emit_data(disp, rspec, disp32_operand);
568 } else if (rtype != relocInfo::none ) {
569 // [disp] (64bit) RIP-RELATIVE (32bit) abs
570 // [00 000 101] disp32
571
572 emit_int8(0x05 | regenc);
573 // Note that the RIP-rel. correction applies to the generated
574 // disp field, but _not_ to the target address in the rspec.
575
576 // disp was created by converting the target address minus the pc
577 // at the start of the instruction. That needs more correction here.
578 // intptr_t disp = target - next_ip;
579 assert(inst_mark() != NULL, "must be inside InstructionMark");
580 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction;
581 int64_t adjusted = disp;
582 // Do rip-rel adjustment for 64bit
583 LP64_ONLY(adjusted -= (next_ip - inst_mark()));
584 assert(is_simm32(adjusted),
585 "must be 32bit offset (RIP relative address)");
586 emit_data((int32_t) adjusted, rspec, disp32_operand);
587
588 } else {
589 // 32bit never did this, did everything as the rip-rel/disp code above
590 // [disp] ABSOLUTE
591 // [00 reg 100][00 100 101] disp32
592 emit_int8(0x04 | regenc);
593 emit_int8(0x25);
594 emit_data(disp, rspec, disp32_operand);
595 }
596 }
597 }
598
599 void Assembler::emit_operand(XMMRegister reg, Register base, Register index,
600 Address::ScaleFactor scale, int disp,
601 RelocationHolder const& rspec) {
602 if (UseAVX > 2) {
603 int xreg_enc = reg->encoding();
604 if (xreg_enc > 15) {
605 XMMRegister new_reg = as_XMMRegister(xreg_enc & 0xf);
606 emit_operand((Register)new_reg, base, index, scale, disp, rspec);
607 return;
608 }
609 }
610 emit_operand((Register)reg, base, index, scale, disp, rspec);
611 }
612
613 // Secret local extension to Assembler::WhichOperand:
614 #define end_pc_operand (_WhichOperand_limit)
615
616 address Assembler::locate_operand(address inst, WhichOperand which) {
617 // Decode the given instruction, and return the address of
618 // an embedded 32-bit operand word.
619
620 // If "which" is disp32_operand, selects the displacement portion
621 // of an effective address specifier.
622 // If "which" is imm64_operand, selects the trailing immediate constant.
623 // If "which" is call32_operand, selects the displacement of a call or jump.
624 // Caller is responsible for ensuring that there is such an operand,
625 // and that it is 32/64 bits wide.
626
627 // If "which" is end_pc_operand, find the end of the instruction.
628
629 address ip = inst;
630 bool is_64bit = false;
631
632 debug_only(bool has_disp32 = false);
633 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn
634
635 again_after_prefix:
636 switch (0xFF & *ip++) {
637
638 // These convenience macros generate groups of "case" labels for the switch.
639 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3
640 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \
641 case (x)+4: case (x)+5: case (x)+6: case (x)+7
642 #define REP16(x) REP8((x)+0): \
643 case REP8((x)+8)
644
645 case CS_segment:
646 case SS_segment:
647 case DS_segment:
648 case ES_segment:
649 case FS_segment:
650 case GS_segment:
651 // Seems dubious
652 LP64_ONLY(assert(false, "shouldn't have that prefix"));
653 assert(ip == inst+1, "only one prefix allowed");
654 goto again_after_prefix;
655
656 case 0x67:
657 case REX:
658 case REX_B:
659 case REX_X:
660 case REX_XB:
661 case REX_R:
662 case REX_RB:
663 case REX_RX:
664 case REX_RXB:
665 NOT_LP64(assert(false, "64bit prefixes"));
666 goto again_after_prefix;
667
668 case REX_W:
669 case REX_WB:
670 case REX_WX:
671 case REX_WXB:
672 case REX_WR:
673 case REX_WRB:
674 case REX_WRX:
675 case REX_WRXB:
676 NOT_LP64(assert(false, "64bit prefixes"));
677 is_64bit = true;
678 goto again_after_prefix;
679
680 case 0xFF: // pushq a; decl a; incl a; call a; jmp a
681 case 0x88: // movb a, r
682 case 0x89: // movl a, r
683 case 0x8A: // movb r, a
684 case 0x8B: // movl r, a
685 case 0x8F: // popl a
686 debug_only(has_disp32 = true);
687 break;
688
689 case 0x68: // pushq #32
690 if (which == end_pc_operand) {
691 return ip + 4;
692 }
693 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate");
694 return ip; // not produced by emit_operand
695
696 case 0x66: // movw ... (size prefix)
697 again_after_size_prefix2:
698 switch (0xFF & *ip++) {
699 case REX:
700 case REX_B:
701 case REX_X:
702 case REX_XB:
703 case REX_R:
704 case REX_RB:
705 case REX_RX:
706 case REX_RXB:
707 case REX_W:
708 case REX_WB:
709 case REX_WX:
710 case REX_WXB:
711 case REX_WR:
712 case REX_WRB:
713 case REX_WRX:
714 case REX_WRXB:
715 NOT_LP64(assert(false, "64bit prefix found"));
716 goto again_after_size_prefix2;
717 case 0x8B: // movw r, a
718 case 0x89: // movw a, r
719 debug_only(has_disp32 = true);
720 break;
721 case 0xC7: // movw a, #16
722 debug_only(has_disp32 = true);
723 tail_size = 2; // the imm16
724 break;
725 case 0x0F: // several SSE/SSE2 variants
726 ip--; // reparse the 0x0F
727 goto again_after_prefix;
728 default:
729 ShouldNotReachHere();
730 }
731 break;
732
733 case REP8(0xB8): // movl/q r, #32/#64(oop?)
734 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4);
735 // these asserts are somewhat nonsensical
736 #ifndef _LP64
737 assert(which == imm_operand || which == disp32_operand,
738 "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip));
739 #else
740 assert((which == call32_operand || which == imm_operand) && is_64bit ||
741 which == narrow_oop_operand && !is_64bit,
742 "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip));
743 #endif // _LP64
744 return ip;
745
746 case 0x69: // imul r, a, #32
747 case 0xC7: // movl a, #32(oop?)
748 tail_size = 4;
749 debug_only(has_disp32 = true); // has both kinds of operands!
750 break;
751
752 case 0x0F: // movx..., etc.
753 switch (0xFF & *ip++) {
754 case 0x3A: // pcmpestri
755 tail_size = 1;
756 case 0x38: // ptest, pmovzxbw
757 ip++; // skip opcode
758 debug_only(has_disp32 = true); // has both kinds of operands!
759 break;
760
761 case 0x70: // pshufd r, r/a, #8
762 debug_only(has_disp32 = true); // has both kinds of operands!
763 case 0x73: // psrldq r, #8
764 tail_size = 1;
765 break;
766
767 case 0x12: // movlps
768 case 0x28: // movaps
769 case 0x2E: // ucomiss
770 case 0x2F: // comiss
771 case 0x54: // andps
772 case 0x55: // andnps
773 case 0x56: // orps
774 case 0x57: // xorps
775 case 0x58: // addpd
776 case 0x59: // mulpd
777 case 0x6E: // movd
778 case 0x7E: // movd
779 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush
780 case 0xFE: // paddd
781 debug_only(has_disp32 = true);
782 break;
783
784 case 0xAD: // shrd r, a, %cl
785 case 0xAF: // imul r, a
786 case 0xBE: // movsbl r, a (movsxb)
787 case 0xBF: // movswl r, a (movsxw)
788 case 0xB6: // movzbl r, a (movzxb)
789 case 0xB7: // movzwl r, a (movzxw)
790 case REP16(0x40): // cmovl cc, r, a
791 case 0xB0: // cmpxchgb
792 case 0xB1: // cmpxchg
793 case 0xC1: // xaddl
794 case 0xC7: // cmpxchg8
795 case REP16(0x90): // setcc a
796 debug_only(has_disp32 = true);
797 // fall out of the switch to decode the address
798 break;
799
800 case 0xC4: // pinsrw r, a, #8
801 debug_only(has_disp32 = true);
802 case 0xC5: // pextrw r, r, #8
803 tail_size = 1; // the imm8
804 break;
805
806 case 0xAC: // shrd r, a, #8
807 debug_only(has_disp32 = true);
808 tail_size = 1; // the imm8
809 break;
810
811 case REP16(0x80): // jcc rdisp32
812 if (which == end_pc_operand) return ip + 4;
813 assert(which == call32_operand, "jcc has no disp32 or imm");
814 return ip;
815 default:
816 ShouldNotReachHere();
817 }
818 break;
819
820 case 0x81: // addl a, #32; addl r, #32
821 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
822 // on 32bit in the case of cmpl, the imm might be an oop
823 tail_size = 4;
824 debug_only(has_disp32 = true); // has both kinds of operands!
825 break;
826
827 case 0x83: // addl a, #8; addl r, #8
828 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
829 debug_only(has_disp32 = true); // has both kinds of operands!
830 tail_size = 1;
831 break;
832
833 case 0x9B:
834 switch (0xFF & *ip++) {
835 case 0xD9: // fnstcw a
836 debug_only(has_disp32 = true);
837 break;
838 default:
839 ShouldNotReachHere();
840 }
841 break;
842
843 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a
844 case REP4(0x10): // adc...
845 case REP4(0x20): // and...
846 case REP4(0x30): // xor...
847 case REP4(0x08): // or...
848 case REP4(0x18): // sbb...
849 case REP4(0x28): // sub...
850 case 0xF7: // mull a
851 case 0x8D: // lea r, a
852 case 0x87: // xchg r, a
853 case REP4(0x38): // cmp...
854 case 0x85: // test r, a
855 debug_only(has_disp32 = true); // has both kinds of operands!
856 break;
857
858 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8
859 case 0xC6: // movb a, #8
860 case 0x80: // cmpb a, #8
861 case 0x6B: // imul r, a, #8
862 debug_only(has_disp32 = true); // has both kinds of operands!
863 tail_size = 1; // the imm8
864 break;
865
866 case 0xC4: // VEX_3bytes
867 case 0xC5: // VEX_2bytes
868 assert((UseAVX > 0), "shouldn't have VEX prefix");
869 assert(ip == inst+1, "no prefixes allowed");
870 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions
871 // but they have prefix 0x0F and processed when 0x0F processed above.
872 //
873 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES
874 // instructions (these instructions are not supported in 64-bit mode).
875 // To distinguish them bits [7:6] are set in the VEX second byte since
876 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set
877 // those VEX bits REX and vvvv bits are inverted.
878 //
879 // Fortunately C2 doesn't generate these instructions so we don't need
880 // to check for them in product version.
881
882 // Check second byte
883 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions"));
884
885 int vex_opcode;
886 // First byte
887 if ((0xFF & *inst) == VEX_3bytes) {
888 vex_opcode = VEX_OPCODE_MASK & *ip;
889 ip++; // third byte
890 is_64bit = ((VEX_W & *ip) == VEX_W);
891 } else {
892 vex_opcode = VEX_OPCODE_0F;
893 }
894 ip++; // opcode
895 // To find the end of instruction (which == end_pc_operand).
896 switch (vex_opcode) {
897 case VEX_OPCODE_0F:
898 switch (0xFF & *ip) {
899 case 0x70: // pshufd r, r/a, #8
900 case 0x71: // ps[rl|ra|ll]w r, #8
901 case 0x72: // ps[rl|ra|ll]d r, #8
902 case 0x73: // ps[rl|ra|ll]q r, #8
903 case 0xC2: // cmp[ps|pd|ss|sd] r, r, r/a, #8
904 case 0xC4: // pinsrw r, r, r/a, #8
905 case 0xC5: // pextrw r/a, r, #8
906 case 0xC6: // shufp[s|d] r, r, r/a, #8
907 tail_size = 1; // the imm8
908 break;
909 }
910 break;
911 case VEX_OPCODE_0F_3A:
912 tail_size = 1;
913 break;
914 }
915 ip++; // skip opcode
916 debug_only(has_disp32 = true); // has both kinds of operands!
917 break;
918
919 case 0x62: // EVEX_4bytes
920 assert((UseAVX > 0), "shouldn't have EVEX prefix");
921 assert(ip == inst+1, "no prefixes allowed");
922 // no EVEX collisions, all instructions that have 0x62 opcodes
923 // have EVEX versions and are subopcodes of 0x66
924 ip++; // skip P0 and exmaine W in P1
925 is_64bit = ((VEX_W & *ip) == VEX_W);
926 ip++; // move to P2
927 ip++; // skip P2, move to opcode
928 // To find the end of instruction (which == end_pc_operand).
929 switch (0xFF & *ip) {
930 case 0x22: // pinsrd r, r/a, #8
931 case 0x61: // pcmpestri r, r/a, #8
932 case 0x70: // pshufd r, r/a, #8
933 case 0x73: // psrldq r, #8
934 tail_size = 1; // the imm8
935 break;
936 default:
937 break;
938 }
939 ip++; // skip opcode
940 debug_only(has_disp32 = true); // has both kinds of operands!
941 break;
942
943 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
944 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
945 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a
946 case 0xDD: // fld_d a; fst_d a; fstp_d a
947 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a
948 case 0xDF: // fild_d a; fistp_d a
949 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a
950 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a
951 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a
952 debug_only(has_disp32 = true);
953 break;
954
955 case 0xE8: // call rdisp32
956 case 0xE9: // jmp rdisp32
957 if (which == end_pc_operand) return ip + 4;
958 assert(which == call32_operand, "call has no disp32 or imm");
959 return ip;
960
961 case 0xF0: // Lock
962 assert(os::is_MP(), "only on MP");
963 goto again_after_prefix;
964
965 case 0xF3: // For SSE
966 case 0xF2: // For SSE2
967 switch (0xFF & *ip++) {
968 case REX:
969 case REX_B:
970 case REX_X:
971 case REX_XB:
972 case REX_R:
973 case REX_RB:
974 case REX_RX:
975 case REX_RXB:
976 case REX_W:
977 case REX_WB:
978 case REX_WX:
979 case REX_WXB:
980 case REX_WR:
981 case REX_WRB:
982 case REX_WRX:
983 case REX_WRXB:
984 NOT_LP64(assert(false, "found 64bit prefix"));
985 ip++;
986 default:
987 ip++;
988 }
989 debug_only(has_disp32 = true); // has both kinds of operands!
990 break;
991
992 default:
993 ShouldNotReachHere();
994
995 #undef REP8
996 #undef REP16
997 }
998
999 assert(which != call32_operand, "instruction is not a call, jmp, or jcc");
1000 #ifdef _LP64
1001 assert(which != imm_operand, "instruction is not a movq reg, imm64");
1002 #else
1003 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field");
1004 assert(which != imm_operand || has_disp32, "instruction has no imm32 field");
1005 #endif // LP64
1006 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field");
1007
1008 // parse the output of emit_operand
1009 int op2 = 0xFF & *ip++;
1010 int base = op2 & 0x07;
1011 int op3 = -1;
1012 const int b100 = 4;
1013 const int b101 = 5;
1014 if (base == b100 && (op2 >> 6) != 3) {
1015 op3 = 0xFF & *ip++;
1016 base = op3 & 0x07; // refetch the base
1017 }
1018 // now ip points at the disp (if any)
1019
1020 switch (op2 >> 6) {
1021 case 0:
1022 // [00 reg 100][ss index base]
1023 // [00 reg 100][00 100 esp]
1024 // [00 reg base]
1025 // [00 reg 100][ss index 101][disp32]
1026 // [00 reg 101] [disp32]
1027
1028 if (base == b101) {
1029 if (which == disp32_operand)
1030 return ip; // caller wants the disp32
1031 ip += 4; // skip the disp32
1032 }
1033 break;
1034
1035 case 1:
1036 // [01 reg 100][ss index base][disp8]
1037 // [01 reg 100][00 100 esp][disp8]
1038 // [01 reg base] [disp8]
1039 ip += 1; // skip the disp8
1040 break;
1041
1042 case 2:
1043 // [10 reg 100][ss index base][disp32]
1044 // [10 reg 100][00 100 esp][disp32]
1045 // [10 reg base] [disp32]
1046 if (which == disp32_operand)
1047 return ip; // caller wants the disp32
1048 ip += 4; // skip the disp32
1049 break;
1050
1051 case 3:
1052 // [11 reg base] (not a memory addressing mode)
1053 break;
1054 }
1055
1056 if (which == end_pc_operand) {
1057 return ip + tail_size;
1058 }
1059
1060 #ifdef _LP64
1061 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32");
1062 #else
1063 assert(which == imm_operand, "instruction has only an imm field");
1064 #endif // LP64
1065 return ip;
1066 }
1067
1068 address Assembler::locate_next_instruction(address inst) {
1069 // Secretly share code with locate_operand:
1070 return locate_operand(inst, end_pc_operand);
1071 }
1072
1073
1074 #ifdef ASSERT
1075 void Assembler::check_relocation(RelocationHolder const& rspec, int format) {
1076 address inst = inst_mark();
1077 assert(inst != NULL && inst < pc(), "must point to beginning of instruction");
1078 address opnd;
1079
1080 Relocation* r = rspec.reloc();
1081 if (r->type() == relocInfo::none) {
1082 return;
1083 } else if (r->is_call() || format == call32_operand) {
1084 // assert(format == imm32_operand, "cannot specify a nonzero format");
1085 opnd = locate_operand(inst, call32_operand);
1086 } else if (r->is_data()) {
1087 assert(format == imm_operand || format == disp32_operand
1088 LP64_ONLY(|| format == narrow_oop_operand), "format ok");
1089 opnd = locate_operand(inst, (WhichOperand)format);
1090 } else {
1091 assert(format == imm_operand, "cannot specify a format");
1092 return;
1093 }
1094 assert(opnd == pc(), "must put operand where relocs can find it");
1095 }
1096 #endif // ASSERT
1097
1098 void Assembler::emit_operand32(Register reg, Address adr) {
1099 assert(reg->encoding() < 8, "no extended registers");
1100 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1101 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1102 adr._rspec);
1103 }
1104
1105 void Assembler::emit_operand(Register reg, Address adr,
1106 int rip_relative_correction) {
1107 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1108 adr._rspec,
1109 rip_relative_correction);
1110 }
1111
1112 void Assembler::emit_operand(XMMRegister reg, Address adr) {
1113 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1114 adr._rspec);
1115 }
1116
1117 // MMX operations
1118 void Assembler::emit_operand(MMXRegister reg, Address adr) {
1119 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1120 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1121 }
1122
1123 // work around gcc (3.2.1-7a) bug
1124 void Assembler::emit_operand(Address adr, MMXRegister reg) {
1125 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1126 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1127 }
1128
1129
1130 void Assembler::emit_farith(int b1, int b2, int i) {
1131 assert(isByte(b1) && isByte(b2), "wrong opcode");
1132 assert(0 <= i && i < 8, "illegal stack offset");
1133 emit_int8(b1);
1134 emit_int8(b2 + i);
1135 }
1136
1137
1138 // Now the Assembler instructions (identical for 32/64 bits)
1139
1140 void Assembler::adcl(Address dst, int32_t imm32) {
1141 InstructionMark im(this);
1142 prefix(dst);
1143 emit_arith_operand(0x81, rdx, dst, imm32);
1144 }
1145
1146 void Assembler::adcl(Address dst, Register src) {
1147 InstructionMark im(this);
1148 prefix(dst, src);
1149 emit_int8(0x11);
1150 emit_operand(src, dst);
1151 }
1152
1153 void Assembler::adcl(Register dst, int32_t imm32) {
1154 prefix(dst);
1155 emit_arith(0x81, 0xD0, dst, imm32);
1156 }
1157
1158 void Assembler::adcl(Register dst, Address src) {
1159 InstructionMark im(this);
1160 prefix(src, dst);
1161 emit_int8(0x13);
1162 emit_operand(dst, src);
1163 }
1164
1165 void Assembler::adcl(Register dst, Register src) {
1166 (void) prefix_and_encode(dst->encoding(), src->encoding());
1167 emit_arith(0x13, 0xC0, dst, src);
1168 }
1169
1170 void Assembler::addl(Address dst, int32_t imm32) {
1171 InstructionMark im(this);
1172 prefix(dst);
1173 emit_arith_operand(0x81, rax, dst, imm32);
1174 }
1175
1176 void Assembler::addl(Address dst, Register src) {
1177 InstructionMark im(this);
1178 prefix(dst, src);
1179 emit_int8(0x01);
1180 emit_operand(src, dst);
1181 }
1182
1183 void Assembler::addl(Register dst, int32_t imm32) {
1184 prefix(dst);
1185 emit_arith(0x81, 0xC0, dst, imm32);
1186 }
1187
1188 void Assembler::addl(Register dst, Address src) {
1189 InstructionMark im(this);
1190 prefix(src, dst);
1191 emit_int8(0x03);
1192 emit_operand(dst, src);
1193 }
1194
1195 void Assembler::addl(Register dst, Register src) {
1196 (void) prefix_and_encode(dst->encoding(), src->encoding());
1197 emit_arith(0x03, 0xC0, dst, src);
1198 }
1199
1200 void Assembler::addr_nop_4() {
1201 assert(UseAddressNop, "no CPU support");
1202 // 4 bytes: NOP DWORD PTR [EAX+0]
1203 emit_int8(0x0F);
1204 emit_int8(0x1F);
1205 emit_int8(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
1206 emit_int8(0); // 8-bits offset (1 byte)
1207 }
1208
1209 void Assembler::addr_nop_5() {
1210 assert(UseAddressNop, "no CPU support");
1211 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
1212 emit_int8(0x0F);
1213 emit_int8(0x1F);
1214 emit_int8(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
1215 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1216 emit_int8(0); // 8-bits offset (1 byte)
1217 }
1218
1219 void Assembler::addr_nop_7() {
1220 assert(UseAddressNop, "no CPU support");
1221 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
1222 emit_int8(0x0F);
1223 emit_int8(0x1F);
1224 emit_int8((unsigned char)0x80);
1225 // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
1226 emit_int32(0); // 32-bits offset (4 bytes)
1227 }
1228
1229 void Assembler::addr_nop_8() {
1230 assert(UseAddressNop, "no CPU support");
1231 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
1232 emit_int8(0x0F);
1233 emit_int8(0x1F);
1234 emit_int8((unsigned char)0x84);
1235 // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
1236 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1237 emit_int32(0); // 32-bits offset (4 bytes)
1238 }
1239
1240 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
1241 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1242 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1243 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1244 emit_int8(0x58);
1245 emit_int8((unsigned char)(0xC0 | encode));
1246 }
1247
1248 void Assembler::addsd(XMMRegister dst, Address src) {
1249 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1250 InstructionMark im(this);
1251 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1252 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1253 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1254 emit_int8(0x58);
1255 emit_operand(dst, src);
1256 }
1257
1258 void Assembler::addss(XMMRegister dst, XMMRegister src) {
1259 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1260 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1261 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1262 emit_int8(0x58);
1263 emit_int8((unsigned char)(0xC0 | encode));
1264 }
1265
1266 void Assembler::addss(XMMRegister dst, Address src) {
1267 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1268 InstructionMark im(this);
1269 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1270 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1271 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1272 emit_int8(0x58);
1273 emit_operand(dst, src);
1274 }
1275
1276 void Assembler::aesdec(XMMRegister dst, Address src) {
1277 assert(VM_Version::supports_aes(), "");
1278 InstructionMark im(this);
1279 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1280 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1281 emit_int8((unsigned char)0xDE);
1282 emit_operand(dst, src);
1283 }
1284
1285 void Assembler::aesdec(XMMRegister dst, XMMRegister src) {
1286 assert(VM_Version::supports_aes(), "");
1287 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1288 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1289 emit_int8((unsigned char)0xDE);
1290 emit_int8(0xC0 | encode);
1291 }
1292
1293 void Assembler::aesdeclast(XMMRegister dst, Address src) {
1294 assert(VM_Version::supports_aes(), "");
1295 InstructionMark im(this);
1296 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1297 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1298 emit_int8((unsigned char)0xDF);
1299 emit_operand(dst, src);
1300 }
1301
1302 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) {
1303 assert(VM_Version::supports_aes(), "");
1304 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1305 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1306 emit_int8((unsigned char)0xDF);
1307 emit_int8((unsigned char)(0xC0 | encode));
1308 }
1309
1310 void Assembler::aesenc(XMMRegister dst, Address src) {
1311 assert(VM_Version::supports_aes(), "");
1312 InstructionMark im(this);
1313 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1314 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1315 emit_int8((unsigned char)0xDC);
1316 emit_operand(dst, src);
1317 }
1318
1319 void Assembler::aesenc(XMMRegister dst, XMMRegister src) {
1320 assert(VM_Version::supports_aes(), "");
1321 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1322 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1323 emit_int8((unsigned char)0xDC);
1324 emit_int8(0xC0 | encode);
1325 }
1326
1327 void Assembler::aesenclast(XMMRegister dst, Address src) {
1328 assert(VM_Version::supports_aes(), "");
1329 InstructionMark im(this);
1330 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1331 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1332 emit_int8((unsigned char)0xDD);
1333 emit_operand(dst, src);
1334 }
1335
1336 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) {
1337 assert(VM_Version::supports_aes(), "");
1338 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1339 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1340 emit_int8((unsigned char)0xDD);
1341 emit_int8((unsigned char)(0xC0 | encode));
1342 }
1343
1344 void Assembler::andl(Address dst, int32_t imm32) {
1345 InstructionMark im(this);
1346 prefix(dst);
1347 emit_int8((unsigned char)0x81);
1348 emit_operand(rsp, dst, 4);
1349 emit_int32(imm32);
1350 }
1351
1352 void Assembler::andl(Register dst, int32_t imm32) {
1353 prefix(dst);
1354 emit_arith(0x81, 0xE0, dst, imm32);
1355 }
1356
1357 void Assembler::andl(Register dst, Address src) {
1358 InstructionMark im(this);
1359 prefix(src, dst);
1360 emit_int8(0x23);
1361 emit_operand(dst, src);
1362 }
1363
1364 void Assembler::andl(Register dst, Register src) {
1365 (void) prefix_and_encode(dst->encoding(), src->encoding());
1366 emit_arith(0x23, 0xC0, dst, src);
1367 }
1368
1369 void Assembler::andnl(Register dst, Register src1, Register src2) {
1370 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1371 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1372 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1373 emit_int8((unsigned char)0xF2);
1374 emit_int8((unsigned char)(0xC0 | encode));
1375 }
1376
1377 void Assembler::andnl(Register dst, Register src1, Address src2) {
1378 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1379 InstructionMark im(this);
1380 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1381 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1382 emit_int8((unsigned char)0xF2);
1383 emit_operand(dst, src2);
1384 }
1385
1386 void Assembler::bsfl(Register dst, Register src) {
1387 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1388 emit_int8(0x0F);
1389 emit_int8((unsigned char)0xBC);
1390 emit_int8((unsigned char)(0xC0 | encode));
1391 }
1392
1393 void Assembler::bsrl(Register dst, Register src) {
1394 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1395 emit_int8(0x0F);
1396 emit_int8((unsigned char)0xBD);
1397 emit_int8((unsigned char)(0xC0 | encode));
1398 }
1399
1400 void Assembler::bswapl(Register reg) { // bswap
1401 int encode = prefix_and_encode(reg->encoding());
1402 emit_int8(0x0F);
1403 emit_int8((unsigned char)(0xC8 | encode));
1404 }
1405
1406 void Assembler::blsil(Register dst, Register src) {
1407 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1408 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1409 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1410 emit_int8((unsigned char)0xF3);
1411 emit_int8((unsigned char)(0xC0 | encode));
1412 }
1413
1414 void Assembler::blsil(Register dst, Address src) {
1415 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1416 InstructionMark im(this);
1417 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1418 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1419 emit_int8((unsigned char)0xF3);
1420 emit_operand(rbx, src);
1421 }
1422
1423 void Assembler::blsmskl(Register dst, Register src) {
1424 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1425 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1426 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1427 emit_int8((unsigned char)0xF3);
1428 emit_int8((unsigned char)(0xC0 | encode));
1429 }
1430
1431 void Assembler::blsmskl(Register dst, Address src) {
1432 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1433 InstructionMark im(this);
1434 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1435 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1436 emit_int8((unsigned char)0xF3);
1437 emit_operand(rdx, src);
1438 }
1439
1440 void Assembler::blsrl(Register dst, Register src) {
1441 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1442 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1443 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1444 emit_int8((unsigned char)0xF3);
1445 emit_int8((unsigned char)(0xC0 | encode));
1446 }
1447
1448 void Assembler::blsrl(Register dst, Address src) {
1449 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1450 InstructionMark im(this);
1451 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1452 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1453 emit_int8((unsigned char)0xF3);
1454 emit_operand(rcx, src);
1455 }
1456
1457 void Assembler::call(Label& L, relocInfo::relocType rtype) {
1458 // suspect disp32 is always good
1459 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
1460
1461 if (L.is_bound()) {
1462 const int long_size = 5;
1463 int offs = (int)( target(L) - pc() );
1464 assert(offs <= 0, "assembler error");
1465 InstructionMark im(this);
1466 // 1110 1000 #32-bit disp
1467 emit_int8((unsigned char)0xE8);
1468 emit_data(offs - long_size, rtype, operand);
1469 } else {
1470 InstructionMark im(this);
1471 // 1110 1000 #32-bit disp
1472 L.add_patch_at(code(), locator());
1473
1474 emit_int8((unsigned char)0xE8);
1475 emit_data(int(0), rtype, operand);
1476 }
1477 }
1478
1479 void Assembler::call(Register dst) {
1480 int encode = prefix_and_encode(dst->encoding());
1481 emit_int8((unsigned char)0xFF);
1482 emit_int8((unsigned char)(0xD0 | encode));
1483 }
1484
1485
1486 void Assembler::call(Address adr) {
1487 InstructionMark im(this);
1488 prefix(adr);
1489 emit_int8((unsigned char)0xFF);
1490 emit_operand(rdx, adr);
1491 }
1492
1493 void Assembler::call_literal(address entry, RelocationHolder const& rspec) {
1494 assert(entry != NULL, "call most probably wrong");
1495 InstructionMark im(this);
1496 emit_int8((unsigned char)0xE8);
1497 intptr_t disp = entry - (pc() + sizeof(int32_t));
1498 assert(is_simm32(disp), "must be 32bit offset (call2)");
1499 // Technically, should use call32_operand, but this format is
1500 // implied by the fact that we're emitting a call instruction.
1501
1502 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand);
1503 emit_data((int) disp, rspec, operand);
1504 }
1505
1506 void Assembler::cdql() {
1507 emit_int8((unsigned char)0x99);
1508 }
1509
1510 void Assembler::cld() {
1511 emit_int8((unsigned char)0xFC);
1512 }
1513
1514 void Assembler::cmovl(Condition cc, Register dst, Register src) {
1515 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1516 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1517 emit_int8(0x0F);
1518 emit_int8(0x40 | cc);
1519 emit_int8((unsigned char)(0xC0 | encode));
1520 }
1521
1522
1523 void Assembler::cmovl(Condition cc, Register dst, Address src) {
1524 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1525 prefix(src, dst);
1526 emit_int8(0x0F);
1527 emit_int8(0x40 | cc);
1528 emit_operand(dst, src);
1529 }
1530
1531 void Assembler::cmpb(Address dst, int imm8) {
1532 InstructionMark im(this);
1533 prefix(dst);
1534 emit_int8((unsigned char)0x80);
1535 emit_operand(rdi, dst, 1);
1536 emit_int8(imm8);
1537 }
1538
1539 void Assembler::cmpl(Address dst, int32_t imm32) {
1540 InstructionMark im(this);
1541 prefix(dst);
1542 emit_int8((unsigned char)0x81);
1543 emit_operand(rdi, dst, 4);
1544 emit_int32(imm32);
1545 }
1546
1547 void Assembler::cmpl(Register dst, int32_t imm32) {
1548 prefix(dst);
1549 emit_arith(0x81, 0xF8, dst, imm32);
1550 }
1551
1552 void Assembler::cmpl(Register dst, Register src) {
1553 (void) prefix_and_encode(dst->encoding(), src->encoding());
1554 emit_arith(0x3B, 0xC0, dst, src);
1555 }
1556
1557 void Assembler::cmpl(Register dst, Address src) {
1558 InstructionMark im(this);
1559 prefix(src, dst);
1560 emit_int8((unsigned char)0x3B);
1561 emit_operand(dst, src);
1562 }
1563
1564 void Assembler::cmpw(Address dst, int imm16) {
1565 InstructionMark im(this);
1566 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers");
1567 emit_int8(0x66);
1568 emit_int8((unsigned char)0x81);
1569 emit_operand(rdi, dst, 2);
1570 emit_int16(imm16);
1571 }
1572
1573 // The 32-bit cmpxchg compares the value at adr with the contents of rax,
1574 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1575 // The ZF is set if the compared values were equal, and cleared otherwise.
1576 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg
1577 InstructionMark im(this);
1578 prefix(adr, reg);
1579 emit_int8(0x0F);
1580 emit_int8((unsigned char)0xB1);
1581 emit_operand(reg, adr);
1582 }
1583
1584 // The 8-bit cmpxchg compares the value at adr with the contents of rax,
1585 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1586 // The ZF is set if the compared values were equal, and cleared otherwise.
1587 void Assembler::cmpxchgb(Register reg, Address adr) { // cmpxchg
1588 InstructionMark im(this);
1589 prefix(adr, reg, true);
1590 emit_int8(0x0F);
1591 emit_int8((unsigned char)0xB0);
1592 emit_operand(reg, adr);
1593 }
1594
1595 void Assembler::comisd(XMMRegister dst, Address src) {
1596 // NOTE: dbx seems to decode this as comiss even though the
1597 // 0x66 is there. Strangly ucomisd comes out correct
1598 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1599 InstructionMark im(this);
1600 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);;
1601 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1602 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1603 emit_int8(0x2F);
1604 emit_operand(dst, src);
1605 }
1606
1607 void Assembler::comisd(XMMRegister dst, XMMRegister src) {
1608 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1609 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1610 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1611 emit_int8(0x2F);
1612 emit_int8((unsigned char)(0xC0 | encode));
1613 }
1614
1615 void Assembler::comiss(XMMRegister dst, Address src) {
1616 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1617 InstructionMark im(this);
1618 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1619 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1620 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1621 emit_int8(0x2F);
1622 emit_operand(dst, src);
1623 }
1624
1625 void Assembler::comiss(XMMRegister dst, XMMRegister src) {
1626 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1627 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1628 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1629 emit_int8(0x2F);
1630 emit_int8((unsigned char)(0xC0 | encode));
1631 }
1632
1633 void Assembler::cpuid() {
1634 emit_int8(0x0F);
1635 emit_int8((unsigned char)0xA2);
1636 }
1637
1638 // Opcode / Instruction Op / En 64 - Bit Mode Compat / Leg Mode Description Implemented
1639 // F2 0F 38 F0 / r CRC32 r32, r / m8 RM Valid Valid Accumulate CRC32 on r / m8. v
1640 // F2 REX 0F 38 F0 / r CRC32 r32, r / m8* RM Valid N.E. Accumulate CRC32 on r / m8. -
1641 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E. Accumulate CRC32 on r / m8. -
1642 //
1643 // F2 0F 38 F1 / r CRC32 r32, r / m16 RM Valid Valid Accumulate CRC32 on r / m16. v
1644 //
1645 // F2 0F 38 F1 / r CRC32 r32, r / m32 RM Valid Valid Accumulate CRC32 on r / m32. v
1646 //
1647 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E. Accumulate CRC32 on r / m64. v
1648 void Assembler::crc32(Register crc, Register v, int8_t sizeInBytes) {
1649 assert(VM_Version::supports_sse4_2(), "");
1650 int8_t w = 0x01;
1651 Prefix p = Prefix_EMPTY;
1652
1653 emit_int8((int8_t)0xF2);
1654 switch (sizeInBytes) {
1655 case 1:
1656 w = 0;
1657 break;
1658 case 2:
1659 case 4:
1660 break;
1661 LP64_ONLY(case 8:)
1662 // This instruction is not valid in 32 bits
1663 // Note:
1664 // http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
1665 //
1666 // Page B - 72 Vol. 2C says
1667 // qwreg2 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : 11 qwreg1 qwreg2
1668 // mem64 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : mod qwreg r / m
1669 // F0!!!
1670 // while 3 - 208 Vol. 2A
1671 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E.Accumulate CRC32 on r / m64.
1672 //
1673 // the 0 on a last bit is reserved for a different flavor of this instruction :
1674 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E.Accumulate CRC32 on r / m8.
1675 p = REX_W;
1676 break;
1677 default:
1678 assert(0, "Unsupported value for a sizeInBytes argument");
1679 break;
1680 }
1681 LP64_ONLY(prefix(crc, v, p);)
1682 emit_int8((int8_t)0x0F);
1683 emit_int8(0x38);
1684 emit_int8((int8_t)(0xF0 | w));
1685 emit_int8(0xC0 | ((crc->encoding() & 0x7) << 3) | (v->encoding() & 7));
1686 }
1687
1688 void Assembler::crc32(Register crc, Address adr, int8_t sizeInBytes) {
1689 assert(VM_Version::supports_sse4_2(), "");
1690 InstructionMark im(this);
1691 int8_t w = 0x01;
1692 Prefix p = Prefix_EMPTY;
1693
1694 emit_int8((int8_t)0xF2);
1695 switch (sizeInBytes) {
1696 case 1:
1697 w = 0;
1698 break;
1699 case 2:
1700 case 4:
1701 break;
1702 LP64_ONLY(case 8:)
1703 // This instruction is not valid in 32 bits
1704 p = REX_W;
1705 break;
1706 default:
1707 assert(0, "Unsupported value for a sizeInBytes argument");
1708 break;
1709 }
1710 LP64_ONLY(prefix(crc, adr, p);)
1711 emit_int8((int8_t)0x0F);
1712 emit_int8(0x38);
1713 emit_int8((int8_t)(0xF0 | w));
1714 emit_operand(crc, adr);
1715 }
1716
1717 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
1718 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1719 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
1720 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1721 emit_int8((unsigned char)0xE6);
1722 emit_int8((unsigned char)(0xC0 | encode));
1723 }
1724
1725 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
1726 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1727 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
1728 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1729 emit_int8(0x5B);
1730 emit_int8((unsigned char)(0xC0 | encode));
1731 }
1732
1733 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
1734 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1735 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1736 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1737 emit_int8(0x5A);
1738 emit_int8((unsigned char)(0xC0 | encode));
1739 }
1740
1741 void Assembler::cvtsd2ss(XMMRegister dst, Address src) {
1742 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1743 InstructionMark im(this);
1744 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1745 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1746 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1747 emit_int8(0x5A);
1748 emit_operand(dst, src);
1749 }
1750
1751 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
1752 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1753 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1754 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1755 emit_int8(0x2A);
1756 emit_int8((unsigned char)(0xC0 | encode));
1757 }
1758
1759 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) {
1760 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1761 InstructionMark im(this);
1762 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1763 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1764 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1765 emit_int8(0x2A);
1766 emit_operand(dst, src);
1767 }
1768
1769 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
1770 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1771 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1772 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1773 emit_int8(0x2A);
1774 emit_int8((unsigned char)(0xC0 | encode));
1775 }
1776
1777 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) {
1778 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1779 InstructionMark im(this);
1780 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1781 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1782 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1783 emit_int8(0x2A);
1784 emit_operand(dst, src);
1785 }
1786
1787 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
1788 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1789 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1790 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1791 emit_int8(0x2A);
1792 emit_int8((unsigned char)(0xC0 | encode));
1793 }
1794
1795 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
1796 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1797 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1798 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1799 emit_int8(0x5A);
1800 emit_int8((unsigned char)(0xC0 | encode));
1801 }
1802
1803 void Assembler::cvtss2sd(XMMRegister dst, Address src) {
1804 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1805 InstructionMark im(this);
1806 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1807 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1808 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1809 emit_int8(0x5A);
1810 emit_operand(dst, src);
1811 }
1812
1813
1814 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
1815 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1816 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1817 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1818 emit_int8(0x2C);
1819 emit_int8((unsigned char)(0xC0 | encode));
1820 }
1821
1822 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
1823 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1824 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1825 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1826 emit_int8(0x2C);
1827 emit_int8((unsigned char)(0xC0 | encode));
1828 }
1829
1830 void Assembler::cvttpd2dq(XMMRegister dst, XMMRegister src) {
1831 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1832 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
1833 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
1834 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1835 emit_int8((unsigned char)0xE6);
1836 emit_int8((unsigned char)(0xC0 | encode));
1837 }
1838
1839 void Assembler::decl(Address dst) {
1840 // Don't use it directly. Use MacroAssembler::decrement() instead.
1841 InstructionMark im(this);
1842 prefix(dst);
1843 emit_int8((unsigned char)0xFF);
1844 emit_operand(rcx, dst);
1845 }
1846
1847 void Assembler::divsd(XMMRegister dst, Address src) {
1848 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1849 InstructionMark im(this);
1850 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1851 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1852 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1853 emit_int8(0x5E);
1854 emit_operand(dst, src);
1855 }
1856
1857 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
1858 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1859 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1860 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1861 emit_int8(0x5E);
1862 emit_int8((unsigned char)(0xC0 | encode));
1863 }
1864
1865 void Assembler::divss(XMMRegister dst, Address src) {
1866 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1867 InstructionMark im(this);
1868 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1869 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1870 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1871 emit_int8(0x5E);
1872 emit_operand(dst, src);
1873 }
1874
1875 void Assembler::divss(XMMRegister dst, XMMRegister src) {
1876 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1877 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1878 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1879 emit_int8(0x5E);
1880 emit_int8((unsigned char)(0xC0 | encode));
1881 }
1882
1883 void Assembler::emms() {
1884 NOT_LP64(assert(VM_Version::supports_mmx(), ""));
1885 emit_int8(0x0F);
1886 emit_int8(0x77);
1887 }
1888
1889 void Assembler::hlt() {
1890 emit_int8((unsigned char)0xF4);
1891 }
1892
1893 void Assembler::idivl(Register src) {
1894 int encode = prefix_and_encode(src->encoding());
1895 emit_int8((unsigned char)0xF7);
1896 emit_int8((unsigned char)(0xF8 | encode));
1897 }
1898
1899 void Assembler::divl(Register src) { // Unsigned
1900 int encode = prefix_and_encode(src->encoding());
1901 emit_int8((unsigned char)0xF7);
1902 emit_int8((unsigned char)(0xF0 | encode));
1903 }
1904
1905 void Assembler::imull(Register src) {
1906 int encode = prefix_and_encode(src->encoding());
1907 emit_int8((unsigned char)0xF7);
1908 emit_int8((unsigned char)(0xE8 | encode));
1909 }
1910
1911 void Assembler::imull(Register dst, Register src) {
1912 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1913 emit_int8(0x0F);
1914 emit_int8((unsigned char)0xAF);
1915 emit_int8((unsigned char)(0xC0 | encode));
1916 }
1917
1918
1919 void Assembler::imull(Register dst, Register src, int value) {
1920 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1921 if (is8bit(value)) {
1922 emit_int8(0x6B);
1923 emit_int8((unsigned char)(0xC0 | encode));
1924 emit_int8(value & 0xFF);
1925 } else {
1926 emit_int8(0x69);
1927 emit_int8((unsigned char)(0xC0 | encode));
1928 emit_int32(value);
1929 }
1930 }
1931
1932 void Assembler::imull(Register dst, Address src) {
1933 InstructionMark im(this);
1934 prefix(src, dst);
1935 emit_int8(0x0F);
1936 emit_int8((unsigned char) 0xAF);
1937 emit_operand(dst, src);
1938 }
1939
1940
1941 void Assembler::incl(Address dst) {
1942 // Don't use it directly. Use MacroAssembler::increment() instead.
1943 InstructionMark im(this);
1944 prefix(dst);
1945 emit_int8((unsigned char)0xFF);
1946 emit_operand(rax, dst);
1947 }
1948
1949 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) {
1950 InstructionMark im(this);
1951 assert((0 <= cc) && (cc < 16), "illegal cc");
1952 if (L.is_bound()) {
1953 address dst = target(L);
1954 assert(dst != NULL, "jcc most probably wrong");
1955
1956 const int short_size = 2;
1957 const int long_size = 6;
1958 intptr_t offs = (intptr_t)dst - (intptr_t)pc();
1959 if (maybe_short && is8bit(offs - short_size)) {
1960 // 0111 tttn #8-bit disp
1961 emit_int8(0x70 | cc);
1962 emit_int8((offs - short_size) & 0xFF);
1963 } else {
1964 // 0000 1111 1000 tttn #32-bit disp
1965 assert(is_simm32(offs - long_size),
1966 "must be 32bit offset (call4)");
1967 emit_int8(0x0F);
1968 emit_int8((unsigned char)(0x80 | cc));
1969 emit_int32(offs - long_size);
1970 }
1971 } else {
1972 // Note: could eliminate cond. jumps to this jump if condition
1973 // is the same however, seems to be rather unlikely case.
1974 // Note: use jccb() if label to be bound is very close to get
1975 // an 8-bit displacement
1976 L.add_patch_at(code(), locator());
1977 emit_int8(0x0F);
1978 emit_int8((unsigned char)(0x80 | cc));
1979 emit_int32(0);
1980 }
1981 }
1982
1983 void Assembler::jccb(Condition cc, Label& L) {
1984 if (L.is_bound()) {
1985 const int short_size = 2;
1986 address entry = target(L);
1987 #ifdef ASSERT
1988 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
1989 intptr_t delta = short_branch_delta();
1990 if (delta != 0) {
1991 dist += (dist < 0 ? (-delta) :delta);
1992 }
1993 assert(is8bit(dist), "Dispacement too large for a short jmp");
1994 #endif
1995 intptr_t offs = (intptr_t)entry - (intptr_t)pc();
1996 // 0111 tttn #8-bit disp
1997 emit_int8(0x70 | cc);
1998 emit_int8((offs - short_size) & 0xFF);
1999 } else {
2000 InstructionMark im(this);
2001 L.add_patch_at(code(), locator());
2002 emit_int8(0x70 | cc);
2003 emit_int8(0);
2004 }
2005 }
2006
2007 void Assembler::jmp(Address adr) {
2008 InstructionMark im(this);
2009 prefix(adr);
2010 emit_int8((unsigned char)0xFF);
2011 emit_operand(rsp, adr);
2012 }
2013
2014 void Assembler::jmp(Label& L, bool maybe_short) {
2015 if (L.is_bound()) {
2016 address entry = target(L);
2017 assert(entry != NULL, "jmp most probably wrong");
2018 InstructionMark im(this);
2019 const int short_size = 2;
2020 const int long_size = 5;
2021 intptr_t offs = entry - pc();
2022 if (maybe_short && is8bit(offs - short_size)) {
2023 emit_int8((unsigned char)0xEB);
2024 emit_int8((offs - short_size) & 0xFF);
2025 } else {
2026 emit_int8((unsigned char)0xE9);
2027 emit_int32(offs - long_size);
2028 }
2029 } else {
2030 // By default, forward jumps are always 32-bit displacements, since
2031 // we can't yet know where the label will be bound. If you're sure that
2032 // the forward jump will not run beyond 256 bytes, use jmpb to
2033 // force an 8-bit displacement.
2034 InstructionMark im(this);
2035 L.add_patch_at(code(), locator());
2036 emit_int8((unsigned char)0xE9);
2037 emit_int32(0);
2038 }
2039 }
2040
2041 void Assembler::jmp(Register entry) {
2042 int encode = prefix_and_encode(entry->encoding());
2043 emit_int8((unsigned char)0xFF);
2044 emit_int8((unsigned char)(0xE0 | encode));
2045 }
2046
2047 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
2048 InstructionMark im(this);
2049 emit_int8((unsigned char)0xE9);
2050 assert(dest != NULL, "must have a target");
2051 intptr_t disp = dest - (pc() + sizeof(int32_t));
2052 assert(is_simm32(disp), "must be 32bit offset (jmp)");
2053 emit_data(disp, rspec.reloc(), call32_operand);
2054 }
2055
2056 void Assembler::jmpb(Label& L) {
2057 if (L.is_bound()) {
2058 const int short_size = 2;
2059 address entry = target(L);
2060 assert(entry != NULL, "jmp most probably wrong");
2061 #ifdef ASSERT
2062 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
2063 intptr_t delta = short_branch_delta();
2064 if (delta != 0) {
2065 dist += (dist < 0 ? (-delta) :delta);
2066 }
2067 assert(is8bit(dist), "Dispacement too large for a short jmp");
2068 #endif
2069 intptr_t offs = entry - pc();
2070 emit_int8((unsigned char)0xEB);
2071 emit_int8((offs - short_size) & 0xFF);
2072 } else {
2073 InstructionMark im(this);
2074 L.add_patch_at(code(), locator());
2075 emit_int8((unsigned char)0xEB);
2076 emit_int8(0);
2077 }
2078 }
2079
2080 void Assembler::ldmxcsr( Address src) {
2081 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2082 InstructionMark im(this);
2083 prefix(src);
2084 emit_int8(0x0F);
2085 emit_int8((unsigned char)0xAE);
2086 emit_operand(as_Register(2), src);
2087 }
2088
2089 void Assembler::leal(Register dst, Address src) {
2090 InstructionMark im(this);
2091 #ifdef _LP64
2092 emit_int8(0x67); // addr32
2093 prefix(src, dst);
2094 #endif // LP64
2095 emit_int8((unsigned char)0x8D);
2096 emit_operand(dst, src);
2097 }
2098
2099 void Assembler::lfence() {
2100 emit_int8(0x0F);
2101 emit_int8((unsigned char)0xAE);
2102 emit_int8((unsigned char)0xE8);
2103 }
2104
2105 void Assembler::lock() {
2106 emit_int8((unsigned char)0xF0);
2107 }
2108
2109 void Assembler::lzcntl(Register dst, Register src) {
2110 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
2111 emit_int8((unsigned char)0xF3);
2112 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2113 emit_int8(0x0F);
2114 emit_int8((unsigned char)0xBD);
2115 emit_int8((unsigned char)(0xC0 | encode));
2116 }
2117
2118 // Emit mfence instruction
2119 void Assembler::mfence() {
2120 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
2121 emit_int8(0x0F);
2122 emit_int8((unsigned char)0xAE);
2123 emit_int8((unsigned char)0xF0);
2124 }
2125
2126 void Assembler::mov(Register dst, Register src) {
2127 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2128 }
2129
2130 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
2131 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2132 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2133 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2134 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2135 emit_int8(0x28);
2136 emit_int8((unsigned char)(0xC0 | encode));
2137 }
2138
2139 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
2140 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2141 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2142 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2143 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2144 emit_int8(0x28);
2145 emit_int8((unsigned char)(0xC0 | encode));
2146 }
2147
2148 void Assembler::movlhps(XMMRegister dst, XMMRegister src) {
2149 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2150 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2151 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2152 emit_int8(0x16);
2153 emit_int8((unsigned char)(0xC0 | encode));
2154 }
2155
2156 void Assembler::movb(Register dst, Address src) {
2157 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
2158 InstructionMark im(this);
2159 prefix(src, dst, true);
2160 emit_int8((unsigned char)0x8A);
2161 emit_operand(dst, src);
2162 }
2163
2164 void Assembler::movddup(XMMRegister dst, XMMRegister src) {
2165 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
2166 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2167 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2168 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2169 emit_int8(0x12);
2170 emit_int8(0xC0 | encode);
2171 }
2172
2173 void Assembler::kmovbl(KRegister dst, Register src) {
2174 assert(VM_Version::supports_avx512dq(), "");
2175 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2176 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2177 emit_int8((unsigned char)0x92);
2178 emit_int8((unsigned char)(0xC0 | encode));
2179 }
2180
2181 void Assembler::kmovbl(Register dst, KRegister src) {
2182 assert(VM_Version::supports_avx512dq(), "");
2183 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2184 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2185 emit_int8((unsigned char)0x93);
2186 emit_int8((unsigned char)(0xC0 | encode));
2187 }
2188
2189 void Assembler::kmovwl(KRegister dst, Register src) {
2190 assert(VM_Version::supports_evex(), "");
2191 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2192 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2193 emit_int8((unsigned char)0x92);
2194 emit_int8((unsigned char)(0xC0 | encode));
2195 }
2196
2197 void Assembler::kmovwl(Register dst, KRegister src) {
2198 assert(VM_Version::supports_evex(), "");
2199 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2200 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2201 emit_int8((unsigned char)0x93);
2202 emit_int8((unsigned char)(0xC0 | encode));
2203 }
2204
2205 void Assembler::kmovdl(KRegister dst, Register src) {
2206 assert(VM_Version::supports_avx512bw(), "");
2207 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2208 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2209 emit_int8((unsigned char)0x92);
2210 emit_int8((unsigned char)(0xC0 | encode));
2211 }
2212
2213 void Assembler::kmovdl(Register dst, KRegister src) {
2214 assert(VM_Version::supports_avx512bw(), "");
2215 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2216 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2217 emit_int8((unsigned char)0x93);
2218 emit_int8((unsigned char)(0xC0 | encode));
2219 }
2220
2221 void Assembler::kmovql(KRegister dst, KRegister src) {
2222 assert(VM_Version::supports_avx512bw(), "");
2223 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2224 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2225 emit_int8((unsigned char)0x90);
2226 emit_int8((unsigned char)(0xC0 | encode));
2227 }
2228
2229 void Assembler::kmovql(KRegister dst, Address src) {
2230 assert(VM_Version::supports_avx512bw(), "");
2231 InstructionMark im(this);
2232 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2233 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2234 emit_int8((unsigned char)0x90);
2235 emit_operand((Register)dst, src);
2236 }
2237
2238 void Assembler::kmovql(Address dst, KRegister src) {
2239 assert(VM_Version::supports_avx512bw(), "");
2240 InstructionMark im(this);
2241 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2242 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2243 emit_int8((unsigned char)0x90);
2244 emit_operand((Register)src, dst);
2245 }
2246
2247 void Assembler::kmovql(KRegister dst, Register src) {
2248 assert(VM_Version::supports_avx512bw(), "");
2249 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2250 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2251 emit_int8((unsigned char)0x92);
2252 emit_int8((unsigned char)(0xC0 | encode));
2253 }
2254
2255 void Assembler::kmovql(Register dst, KRegister src) {
2256 assert(VM_Version::supports_avx512bw(), "");
2257 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2258 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2259 emit_int8((unsigned char)0x93);
2260 emit_int8((unsigned char)(0xC0 | encode));
2261 }
2262
2263 // This instruction produces ZF or CF flags
2264 void Assembler::kortestbl(KRegister src1, KRegister src2) {
2265 assert(VM_Version::supports_avx512dq(), "");
2266 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2267 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2268 emit_int8((unsigned char)0x98);
2269 emit_int8((unsigned char)(0xC0 | encode));
2270 }
2271
2272 // This instruction produces ZF or CF flags
2273 void Assembler::kortestwl(KRegister src1, KRegister src2) {
2274 assert(VM_Version::supports_evex(), "");
2275 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2276 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2277 emit_int8((unsigned char)0x98);
2278 emit_int8((unsigned char)(0xC0 | encode));
2279 }
2280
2281 // This instruction produces ZF or CF flags
2282 void Assembler::kortestdl(KRegister src1, KRegister src2) {
2283 assert(VM_Version::supports_avx512bw(), "");
2284 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2285 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2286 emit_int8((unsigned char)0x98);
2287 emit_int8((unsigned char)(0xC0 | encode));
2288 }
2289
2290 // This instruction produces ZF or CF flags
2291 void Assembler::kortestql(KRegister src1, KRegister src2) {
2292 assert(VM_Version::supports_avx512bw(), "");
2293 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2294 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2295 emit_int8((unsigned char)0x98);
2296 emit_int8((unsigned char)(0xC0 | encode));
2297 }
2298
2299 void Assembler::movb(Address dst, int imm8) {
2300 InstructionMark im(this);
2301 prefix(dst);
2302 emit_int8((unsigned char)0xC6);
2303 emit_operand(rax, dst, 1);
2304 emit_int8(imm8);
2305 }
2306
2307
2308 void Assembler::movb(Address dst, Register src) {
2309 assert(src->has_byte_register(), "must have byte register");
2310 InstructionMark im(this);
2311 prefix(dst, src, true);
2312 emit_int8((unsigned char)0x88);
2313 emit_operand(src, dst);
2314 }
2315
2316 void Assembler::movdl(XMMRegister dst, Register src) {
2317 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2318 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2319 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2320 emit_int8(0x6E);
2321 emit_int8((unsigned char)(0xC0 | encode));
2322 }
2323
2324 void Assembler::movdl(Register dst, XMMRegister src) {
2325 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2326 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2327 // swap src/dst to get correct prefix
2328 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2329 emit_int8(0x7E);
2330 emit_int8((unsigned char)(0xC0 | encode));
2331 }
2332
2333 void Assembler::movdl(XMMRegister dst, Address src) {
2334 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2335 InstructionMark im(this);
2336 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2337 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2338 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2339 emit_int8(0x6E);
2340 emit_operand(dst, src);
2341 }
2342
2343 void Assembler::movdl(Address dst, XMMRegister src) {
2344 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2345 InstructionMark im(this);
2346 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2347 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2348 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2349 emit_int8(0x7E);
2350 emit_operand(src, dst);
2351 }
2352
2353 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
2354 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2355 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2356 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2357 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2358 emit_int8(0x6F);
2359 emit_int8((unsigned char)(0xC0 | encode));
2360 }
2361
2362 void Assembler::movdqa(XMMRegister dst, Address src) {
2363 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2364 InstructionMark im(this);
2365 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2366 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2367 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2368 emit_int8(0x6F);
2369 emit_operand(dst, src);
2370 }
2371
2372 void Assembler::movdqu(XMMRegister dst, Address src) {
2373 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2374 InstructionMark im(this);
2375 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2376 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2377 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2378 emit_int8(0x6F);
2379 emit_operand(dst, src);
2380 }
2381
2382 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
2383 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2384 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2385 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2386 emit_int8(0x6F);
2387 emit_int8((unsigned char)(0xC0 | encode));
2388 }
2389
2390 void Assembler::movdqu(Address dst, XMMRegister src) {
2391 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2392 InstructionMark im(this);
2393 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2394 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2395 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2396 emit_int8(0x7F);
2397 emit_operand(src, dst);
2398 }
2399
2400 // Move Unaligned 256bit Vector
2401 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2402 assert(UseAVX > 0, "");
2403 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2404 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2405 emit_int8(0x6F);
2406 emit_int8((unsigned char)(0xC0 | encode));
2407 }
2408
2409 void Assembler::vmovdqu(XMMRegister dst, Address src) {
2410 assert(UseAVX > 0, "");
2411 InstructionMark im(this);
2412 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2413 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2414 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2415 emit_int8(0x6F);
2416 emit_operand(dst, src);
2417 }
2418
2419 void Assembler::vmovdqu(Address dst, XMMRegister src) {
2420 assert(UseAVX > 0, "");
2421 InstructionMark im(this);
2422 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2423 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2424 // swap src<->dst for encoding
2425 assert(src != xnoreg, "sanity");
2426 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2427 emit_int8(0x7F);
2428 emit_operand(src, dst);
2429 }
2430
2431 // Move Unaligned EVEX enabled Vector (programmable : 8,16,32,64)
2432 void Assembler::evmovdqub(XMMRegister dst, XMMRegister src, int vector_len) {
2433 assert(VM_Version::supports_evex(), "");
2434 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2435 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2436 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2437 emit_int8(0x6F);
2438 emit_int8((unsigned char)(0xC0 | encode));
2439 }
2440
2441 void Assembler::evmovdqub(XMMRegister dst, Address src, int vector_len) {
2442 assert(VM_Version::supports_evex(), "");
2443 InstructionMark im(this);
2444 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2445 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2446 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2447 vex_prefix(src, 0, dst->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2448 emit_int8(0x6F);
2449 emit_operand(dst, src);
2450 }
2451
2452 void Assembler::evmovdqub(Address dst, XMMRegister src, int vector_len) {
2453 assert(VM_Version::supports_evex(), "");
2454 assert(src != xnoreg, "sanity");
2455 InstructionMark im(this);
2456 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2457 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2458 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2459 vex_prefix(dst, 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2460 emit_int8(0x7F);
2461 emit_operand(src, dst);
2462 }
2463
2464 void Assembler::evmovdquw(XMMRegister dst, XMMRegister src, int vector_len) {
2465 assert(VM_Version::supports_evex(), "");
2466 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2467 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2468 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2469 emit_int8(0x6F);
2470 emit_int8((unsigned char)(0xC0 | encode));
2471 }
2472
2473 void Assembler::evmovdquw(XMMRegister dst, Address src, int vector_len) {
2474 assert(VM_Version::supports_evex(), "");
2475 InstructionMark im(this);
2476 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2477 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2478 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2479 vex_prefix(src, 0, dst->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2480 emit_int8(0x6F);
2481 emit_operand(dst, src);
2482 }
2483
2484 void Assembler::evmovdquw(Address dst, XMMRegister src, int vector_len) {
2485 assert(VM_Version::supports_evex(), "");
2486 assert(src != xnoreg, "sanity");
2487 InstructionMark im(this);
2488 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2489 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2490 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2491 vex_prefix(dst, 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2492 emit_int8(0x7F);
2493 emit_operand(src, dst);
2494 }
2495
2496 void Assembler::evmovdqul(XMMRegister dst, XMMRegister src, int vector_len) {
2497 assert(VM_Version::supports_evex(), "");
2498 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2499 attributes.set_is_evex_instruction();
2500 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2501 emit_int8(0x6F);
2502 emit_int8((unsigned char)(0xC0 | encode));
2503 }
2504
2505 void Assembler::evmovdqul(XMMRegister dst, Address src, int vector_len) {
2506 assert(VM_Version::supports_evex(), "");
2507 InstructionMark im(this);
2508 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false , /* uses_vl */ true);
2509 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2510 attributes.set_is_evex_instruction();
2511 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2512 emit_int8(0x6F);
2513 emit_operand(dst, src);
2514 }
2515
2516 void Assembler::evmovdqul(Address dst, XMMRegister src, int vector_len) {
2517 assert(VM_Version::supports_evex(), "");
2518 assert(src != xnoreg, "sanity");
2519 InstructionMark im(this);
2520 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2521 attributes.set_is_evex_instruction();
2522 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2523 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2524 emit_int8(0x7F);
2525 emit_operand(src, dst);
2526 }
2527
2528 void Assembler::evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) {
2529 assert(VM_Version::supports_evex(), "");
2530 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2531 attributes.set_is_evex_instruction();
2532 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2533 emit_int8(0x6F);
2534 emit_int8((unsigned char)(0xC0 | encode));
2535 }
2536
2537 void Assembler::evmovdquq(XMMRegister dst, Address src, int vector_len) {
2538 assert(VM_Version::supports_evex(), "");
2539 InstructionMark im(this);
2540 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2541 attributes.set_is_evex_instruction();
2542 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2543 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2544 emit_int8(0x6F);
2545 emit_operand(dst, src);
2546 }
2547
2548 void Assembler::evmovdquq(Address dst, XMMRegister src, int vector_len) {
2549 assert(VM_Version::supports_evex(), "");
2550 assert(src != xnoreg, "sanity");
2551 InstructionMark im(this);
2552 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2553 attributes.set_is_evex_instruction();
2554 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2555 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2556 emit_int8(0x7F);
2557 emit_operand(src, dst);
2558 }
2559
2560 // Uses zero extension on 64bit
2561
2562 void Assembler::movl(Register dst, int32_t imm32) {
2563 int encode = prefix_and_encode(dst->encoding());
2564 emit_int8((unsigned char)(0xB8 | encode));
2565 emit_int32(imm32);
2566 }
2567
2568 void Assembler::movl(Register dst, Register src) {
2569 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2570 emit_int8((unsigned char)0x8B);
2571 emit_int8((unsigned char)(0xC0 | encode));
2572 }
2573
2574 void Assembler::movl(Register dst, Address src) {
2575 InstructionMark im(this);
2576 prefix(src, dst);
2577 emit_int8((unsigned char)0x8B);
2578 emit_operand(dst, src);
2579 }
2580
2581 void Assembler::movl(Address dst, int32_t imm32) {
2582 InstructionMark im(this);
2583 prefix(dst);
2584 emit_int8((unsigned char)0xC7);
2585 emit_operand(rax, dst, 4);
2586 emit_int32(imm32);
2587 }
2588
2589 void Assembler::movl(Address dst, Register src) {
2590 InstructionMark im(this);
2591 prefix(dst, src);
2592 emit_int8((unsigned char)0x89);
2593 emit_operand(src, dst);
2594 }
2595
2596 // New cpus require to use movsd and movss to avoid partial register stall
2597 // when loading from memory. But for old Opteron use movlpd instead of movsd.
2598 // The selection is done in MacroAssembler::movdbl() and movflt().
2599 void Assembler::movlpd(XMMRegister dst, Address src) {
2600 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2601 InstructionMark im(this);
2602 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2603 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2604 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2605 emit_int8(0x12);
2606 emit_operand(dst, src);
2607 }
2608
2609 void Assembler::movq( MMXRegister dst, Address src ) {
2610 assert( VM_Version::supports_mmx(), "" );
2611 emit_int8(0x0F);
2612 emit_int8(0x6F);
2613 emit_operand(dst, src);
2614 }
2615
2616 void Assembler::movq( Address dst, MMXRegister src ) {
2617 assert( VM_Version::supports_mmx(), "" );
2618 emit_int8(0x0F);
2619 emit_int8(0x7F);
2620 // workaround gcc (3.2.1-7a) bug
2621 // In that version of gcc with only an emit_operand(MMX, Address)
2622 // gcc will tail jump and try and reverse the parameters completely
2623 // obliterating dst in the process. By having a version available
2624 // that doesn't need to swap the args at the tail jump the bug is
2625 // avoided.
2626 emit_operand(dst, src);
2627 }
2628
2629 void Assembler::movq(XMMRegister dst, Address src) {
2630 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2631 InstructionMark im(this);
2632 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2633 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2634 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2635 emit_int8(0x7E);
2636 emit_operand(dst, src);
2637 }
2638
2639 void Assembler::movq(Address dst, XMMRegister src) {
2640 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2641 InstructionMark im(this);
2642 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2643 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2644 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2645 emit_int8((unsigned char)0xD6);
2646 emit_operand(src, dst);
2647 }
2648
2649 void Assembler::movsbl(Register dst, Address src) { // movsxb
2650 InstructionMark im(this);
2651 prefix(src, dst);
2652 emit_int8(0x0F);
2653 emit_int8((unsigned char)0xBE);
2654 emit_operand(dst, src);
2655 }
2656
2657 void Assembler::movsbl(Register dst, Register src) { // movsxb
2658 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2659 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
2660 emit_int8(0x0F);
2661 emit_int8((unsigned char)0xBE);
2662 emit_int8((unsigned char)(0xC0 | encode));
2663 }
2664
2665 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
2666 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2667 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2668 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2669 emit_int8(0x10);
2670 emit_int8((unsigned char)(0xC0 | encode));
2671 }
2672
2673 void Assembler::movsd(XMMRegister dst, Address src) {
2674 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2675 InstructionMark im(this);
2676 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2677 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2678 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2679 emit_int8(0x10);
2680 emit_operand(dst, src);
2681 }
2682
2683 void Assembler::movsd(Address dst, XMMRegister src) {
2684 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2685 InstructionMark im(this);
2686 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2687 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2688 simd_prefix(src, xnoreg, dst, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2689 emit_int8(0x11);
2690 emit_operand(src, dst);
2691 }
2692
2693 void Assembler::movss(XMMRegister dst, XMMRegister src) {
2694 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2695 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2696 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2697 emit_int8(0x10);
2698 emit_int8((unsigned char)(0xC0 | encode));
2699 }
2700
2701 void Assembler::movss(XMMRegister dst, Address src) {
2702 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2703 InstructionMark im(this);
2704 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2705 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2706 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2707 emit_int8(0x10);
2708 emit_operand(dst, src);
2709 }
2710
2711 void Assembler::movss(Address dst, XMMRegister src) {
2712 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2713 InstructionMark im(this);
2714 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2715 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2716 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2717 emit_int8(0x11);
2718 emit_operand(src, dst);
2719 }
2720
2721 void Assembler::movswl(Register dst, Address src) { // movsxw
2722 InstructionMark im(this);
2723 prefix(src, dst);
2724 emit_int8(0x0F);
2725 emit_int8((unsigned char)0xBF);
2726 emit_operand(dst, src);
2727 }
2728
2729 void Assembler::movswl(Register dst, Register src) { // movsxw
2730 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2731 emit_int8(0x0F);
2732 emit_int8((unsigned char)0xBF);
2733 emit_int8((unsigned char)(0xC0 | encode));
2734 }
2735
2736 void Assembler::movw(Address dst, int imm16) {
2737 InstructionMark im(this);
2738
2739 emit_int8(0x66); // switch to 16-bit mode
2740 prefix(dst);
2741 emit_int8((unsigned char)0xC7);
2742 emit_operand(rax, dst, 2);
2743 emit_int16(imm16);
2744 }
2745
2746 void Assembler::movw(Register dst, Address src) {
2747 InstructionMark im(this);
2748 emit_int8(0x66);
2749 prefix(src, dst);
2750 emit_int8((unsigned char)0x8B);
2751 emit_operand(dst, src);
2752 }
2753
2754 void Assembler::movw(Address dst, Register src) {
2755 InstructionMark im(this);
2756 emit_int8(0x66);
2757 prefix(dst, src);
2758 emit_int8((unsigned char)0x89);
2759 emit_operand(src, dst);
2760 }
2761
2762 void Assembler::movzbl(Register dst, Address src) { // movzxb
2763 InstructionMark im(this);
2764 prefix(src, dst);
2765 emit_int8(0x0F);
2766 emit_int8((unsigned char)0xB6);
2767 emit_operand(dst, src);
2768 }
2769
2770 void Assembler::movzbl(Register dst, Register src) { // movzxb
2771 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2772 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
2773 emit_int8(0x0F);
2774 emit_int8((unsigned char)0xB6);
2775 emit_int8(0xC0 | encode);
2776 }
2777
2778 void Assembler::movzwl(Register dst, Address src) { // movzxw
2779 InstructionMark im(this);
2780 prefix(src, dst);
2781 emit_int8(0x0F);
2782 emit_int8((unsigned char)0xB7);
2783 emit_operand(dst, src);
2784 }
2785
2786 void Assembler::movzwl(Register dst, Register src) { // movzxw
2787 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2788 emit_int8(0x0F);
2789 emit_int8((unsigned char)0xB7);
2790 emit_int8(0xC0 | encode);
2791 }
2792
2793 void Assembler::mull(Address src) {
2794 InstructionMark im(this);
2795 prefix(src);
2796 emit_int8((unsigned char)0xF7);
2797 emit_operand(rsp, src);
2798 }
2799
2800 void Assembler::mull(Register src) {
2801 int encode = prefix_and_encode(src->encoding());
2802 emit_int8((unsigned char)0xF7);
2803 emit_int8((unsigned char)(0xE0 | encode));
2804 }
2805
2806 void Assembler::mulsd(XMMRegister dst, Address src) {
2807 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2808 InstructionMark im(this);
2809 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2810 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2811 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2812 emit_int8(0x59);
2813 emit_operand(dst, src);
2814 }
2815
2816 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
2817 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2818 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2819 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2820 emit_int8(0x59);
2821 emit_int8((unsigned char)(0xC0 | encode));
2822 }
2823
2824 void Assembler::mulss(XMMRegister dst, Address src) {
2825 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2826 InstructionMark im(this);
2827 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2828 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2829 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2830 emit_int8(0x59);
2831 emit_operand(dst, src);
2832 }
2833
2834 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
2835 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2836 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2837 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2838 emit_int8(0x59);
2839 emit_int8((unsigned char)(0xC0 | encode));
2840 }
2841
2842 void Assembler::negl(Register dst) {
2843 int encode = prefix_and_encode(dst->encoding());
2844 emit_int8((unsigned char)0xF7);
2845 emit_int8((unsigned char)(0xD8 | encode));
2846 }
2847
2848 void Assembler::nop(int i) {
2849 #ifdef ASSERT
2850 assert(i > 0, " ");
2851 // The fancy nops aren't currently recognized by debuggers making it a
2852 // pain to disassemble code while debugging. If asserts are on clearly
2853 // speed is not an issue so simply use the single byte traditional nop
2854 // to do alignment.
2855
2856 for (; i > 0 ; i--) emit_int8((unsigned char)0x90);
2857 return;
2858
2859 #endif // ASSERT
2860
2861 if (UseAddressNop && VM_Version::is_intel()) {
2862 //
2863 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel
2864 // 1: 0x90
2865 // 2: 0x66 0x90
2866 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2867 // 4: 0x0F 0x1F 0x40 0x00
2868 // 5: 0x0F 0x1F 0x44 0x00 0x00
2869 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2870 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2871 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2872 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2873 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2874 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2875
2876 // The rest coding is Intel specific - don't use consecutive address nops
2877
2878 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2879 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2880 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2881 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2882
2883 while(i >= 15) {
2884 // For Intel don't generate consecutive addess nops (mix with regular nops)
2885 i -= 15;
2886 emit_int8(0x66); // size prefix
2887 emit_int8(0x66); // size prefix
2888 emit_int8(0x66); // size prefix
2889 addr_nop_8();
2890 emit_int8(0x66); // size prefix
2891 emit_int8(0x66); // size prefix
2892 emit_int8(0x66); // size prefix
2893 emit_int8((unsigned char)0x90);
2894 // nop
2895 }
2896 switch (i) {
2897 case 14:
2898 emit_int8(0x66); // size prefix
2899 case 13:
2900 emit_int8(0x66); // size prefix
2901 case 12:
2902 addr_nop_8();
2903 emit_int8(0x66); // size prefix
2904 emit_int8(0x66); // size prefix
2905 emit_int8(0x66); // size prefix
2906 emit_int8((unsigned char)0x90);
2907 // nop
2908 break;
2909 case 11:
2910 emit_int8(0x66); // size prefix
2911 case 10:
2912 emit_int8(0x66); // size prefix
2913 case 9:
2914 emit_int8(0x66); // size prefix
2915 case 8:
2916 addr_nop_8();
2917 break;
2918 case 7:
2919 addr_nop_7();
2920 break;
2921 case 6:
2922 emit_int8(0x66); // size prefix
2923 case 5:
2924 addr_nop_5();
2925 break;
2926 case 4:
2927 addr_nop_4();
2928 break;
2929 case 3:
2930 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
2931 emit_int8(0x66); // size prefix
2932 case 2:
2933 emit_int8(0x66); // size prefix
2934 case 1:
2935 emit_int8((unsigned char)0x90);
2936 // nop
2937 break;
2938 default:
2939 assert(i == 0, " ");
2940 }
2941 return;
2942 }
2943 if (UseAddressNop && VM_Version::is_amd()) {
2944 //
2945 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD.
2946 // 1: 0x90
2947 // 2: 0x66 0x90
2948 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2949 // 4: 0x0F 0x1F 0x40 0x00
2950 // 5: 0x0F 0x1F 0x44 0x00 0x00
2951 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2952 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2953 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2954 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2955 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2956 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2957
2958 // The rest coding is AMD specific - use consecutive address nops
2959
2960 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2961 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2962 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2963 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2964 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2965 // Size prefixes (0x66) are added for larger sizes
2966
2967 while(i >= 22) {
2968 i -= 11;
2969 emit_int8(0x66); // size prefix
2970 emit_int8(0x66); // size prefix
2971 emit_int8(0x66); // size prefix
2972 addr_nop_8();
2973 }
2974 // Generate first nop for size between 21-12
2975 switch (i) {
2976 case 21:
2977 i -= 1;
2978 emit_int8(0x66); // size prefix
2979 case 20:
2980 case 19:
2981 i -= 1;
2982 emit_int8(0x66); // size prefix
2983 case 18:
2984 case 17:
2985 i -= 1;
2986 emit_int8(0x66); // size prefix
2987 case 16:
2988 case 15:
2989 i -= 8;
2990 addr_nop_8();
2991 break;
2992 case 14:
2993 case 13:
2994 i -= 7;
2995 addr_nop_7();
2996 break;
2997 case 12:
2998 i -= 6;
2999 emit_int8(0x66); // size prefix
3000 addr_nop_5();
3001 break;
3002 default:
3003 assert(i < 12, " ");
3004 }
3005
3006 // Generate second nop for size between 11-1
3007 switch (i) {
3008 case 11:
3009 emit_int8(0x66); // size prefix
3010 case 10:
3011 emit_int8(0x66); // size prefix
3012 case 9:
3013 emit_int8(0x66); // size prefix
3014 case 8:
3015 addr_nop_8();
3016 break;
3017 case 7:
3018 addr_nop_7();
3019 break;
3020 case 6:
3021 emit_int8(0x66); // size prefix
3022 case 5:
3023 addr_nop_5();
3024 break;
3025 case 4:
3026 addr_nop_4();
3027 break;
3028 case 3:
3029 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
3030 emit_int8(0x66); // size prefix
3031 case 2:
3032 emit_int8(0x66); // size prefix
3033 case 1:
3034 emit_int8((unsigned char)0x90);
3035 // nop
3036 break;
3037 default:
3038 assert(i == 0, " ");
3039 }
3040 return;
3041 }
3042
3043 // Using nops with size prefixes "0x66 0x90".
3044 // From AMD Optimization Guide:
3045 // 1: 0x90
3046 // 2: 0x66 0x90
3047 // 3: 0x66 0x66 0x90
3048 // 4: 0x66 0x66 0x66 0x90
3049 // 5: 0x66 0x66 0x90 0x66 0x90
3050 // 6: 0x66 0x66 0x90 0x66 0x66 0x90
3051 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90
3052 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90
3053 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
3054 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
3055 //
3056 while(i > 12) {
3057 i -= 4;
3058 emit_int8(0x66); // size prefix
3059 emit_int8(0x66);
3060 emit_int8(0x66);
3061 emit_int8((unsigned char)0x90);
3062 // nop
3063 }
3064 // 1 - 12 nops
3065 if(i > 8) {
3066 if(i > 9) {
3067 i -= 1;
3068 emit_int8(0x66);
3069 }
3070 i -= 3;
3071 emit_int8(0x66);
3072 emit_int8(0x66);
3073 emit_int8((unsigned char)0x90);
3074 }
3075 // 1 - 8 nops
3076 if(i > 4) {
3077 if(i > 6) {
3078 i -= 1;
3079 emit_int8(0x66);
3080 }
3081 i -= 3;
3082 emit_int8(0x66);
3083 emit_int8(0x66);
3084 emit_int8((unsigned char)0x90);
3085 }
3086 switch (i) {
3087 case 4:
3088 emit_int8(0x66);
3089 case 3:
3090 emit_int8(0x66);
3091 case 2:
3092 emit_int8(0x66);
3093 case 1:
3094 emit_int8((unsigned char)0x90);
3095 break;
3096 default:
3097 assert(i == 0, " ");
3098 }
3099 }
3100
3101 void Assembler::notl(Register dst) {
3102 int encode = prefix_and_encode(dst->encoding());
3103 emit_int8((unsigned char)0xF7);
3104 emit_int8((unsigned char)(0xD0 | encode));
3105 }
3106
3107 void Assembler::orl(Address dst, int32_t imm32) {
3108 InstructionMark im(this);
3109 prefix(dst);
3110 emit_arith_operand(0x81, rcx, dst, imm32);
3111 }
3112
3113 void Assembler::orl(Register dst, int32_t imm32) {
3114 prefix(dst);
3115 emit_arith(0x81, 0xC8, dst, imm32);
3116 }
3117
3118 void Assembler::orl(Register dst, Address src) {
3119 InstructionMark im(this);
3120 prefix(src, dst);
3121 emit_int8(0x0B);
3122 emit_operand(dst, src);
3123 }
3124
3125 void Assembler::orl(Register dst, Register src) {
3126 (void) prefix_and_encode(dst->encoding(), src->encoding());
3127 emit_arith(0x0B, 0xC0, dst, src);
3128 }
3129
3130 void Assembler::orl(Address dst, Register src) {
3131 InstructionMark im(this);
3132 prefix(dst, src);
3133 emit_int8(0x09);
3134 emit_operand(src, dst);
3135 }
3136
3137 void Assembler::packuswb(XMMRegister dst, Address src) {
3138 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3139 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3140 InstructionMark im(this);
3141 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3142 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3143 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3144 emit_int8(0x67);
3145 emit_operand(dst, src);
3146 }
3147
3148 void Assembler::packuswb(XMMRegister dst, XMMRegister src) {
3149 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3150 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3151 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3152 emit_int8(0x67);
3153 emit_int8((unsigned char)(0xC0 | encode));
3154 }
3155
3156 void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3157 assert(UseAVX > 0, "some form of AVX must be enabled");
3158 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3159 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3160 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3161 emit_int8(0x67);
3162 emit_int8((unsigned char)(0xC0 | encode));
3163 }
3164
3165 void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len) {
3166 assert(VM_Version::supports_avx2(), "");
3167 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3168 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3169 emit_int8(0x00);
3170 emit_int8(0xC0 | encode);
3171 emit_int8(imm8);
3172 }
3173
3174 void Assembler::pause() {
3175 emit_int8((unsigned char)0xF3);
3176 emit_int8((unsigned char)0x90);
3177 }
3178
3179 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3180 assert(VM_Version::supports_sse4_2(), "");
3181 InstructionMark im(this);
3182 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3183 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3184 emit_int8(0x61);
3185 emit_operand(dst, src);
3186 emit_int8(imm8);
3187 }
3188
3189 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3190 assert(VM_Version::supports_sse4_2(), "");
3191 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3192 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3193 emit_int8(0x61);
3194 emit_int8((unsigned char)(0xC0 | encode));
3195 emit_int8(imm8);
3196 }
3197
3198 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3199 void Assembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
3200 assert(VM_Version::supports_sse2(), "");
3201 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3202 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3203 emit_int8(0x74);
3204 emit_int8((unsigned char)(0xC0 | encode));
3205 }
3206
3207 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3208 void Assembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3209 assert(VM_Version::supports_avx(), "");
3210 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3211 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3212 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3213 emit_int8(0x74);
3214 emit_int8((unsigned char)(0xC0 | encode));
3215 }
3216
3217 // In this context, kdst is written the mask used to process the equal components
3218 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3219 assert(VM_Version::supports_avx512bw(), "");
3220 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3221 attributes.set_is_evex_instruction();
3222 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3223 int encode = vex_prefix_and_encode(kdst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3224 emit_int8(0x74);
3225 emit_int8((unsigned char)(0xC0 | encode));
3226 }
3227
3228 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3229 assert(VM_Version::supports_avx512bw(), "");
3230 InstructionMark im(this);
3231 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3232 attributes.set_is_evex_instruction();
3233 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3234 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3235 int dst_enc = kdst->encoding();
3236 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3237 emit_int8(0x74);
3238 emit_operand(as_Register(dst_enc), src);
3239 }
3240
3241 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3242 void Assembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3243 assert(VM_Version::supports_sse2(), "");
3244 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3245 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3246 emit_int8(0x75);
3247 emit_int8((unsigned char)(0xC0 | encode));
3248 }
3249
3250 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3251 void Assembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3252 assert(VM_Version::supports_avx(), "");
3253 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3254 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3255 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3256 emit_int8(0x75);
3257 emit_int8((unsigned char)(0xC0 | encode));
3258 }
3259
3260 // In this context, kdst is written the mask used to process the equal components
3261 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3262 assert(VM_Version::supports_avx512bw(), "");
3263 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3264 attributes.set_is_evex_instruction();
3265 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3266 int encode = vex_prefix_and_encode(kdst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3267 emit_int8(0x75);
3268 emit_int8((unsigned char)(0xC0 | encode));
3269 }
3270
3271 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3272 assert(VM_Version::supports_avx512bw(), "");
3273 InstructionMark im(this);
3274 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3275 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3276 attributes.set_is_evex_instruction();
3277 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3278 int dst_enc = kdst->encoding();
3279 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3280 emit_int8(0x75);
3281 emit_operand(as_Register(dst_enc), src);
3282 }
3283
3284 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3285 void Assembler::pcmpeqd(XMMRegister dst, XMMRegister src) {
3286 assert(VM_Version::supports_sse2(), "");
3287 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3288 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3289 emit_int8(0x76);
3290 emit_int8((unsigned char)(0xC0 | encode));
3291 }
3292
3293 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3294 void Assembler::vpcmpeqd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3295 assert(VM_Version::supports_avx(), "");
3296 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3297 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3298 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3299 emit_int8(0x76);
3300 emit_int8((unsigned char)(0xC0 | encode));
3301 }
3302
3303 // In this context, kdst is written the mask used to process the equal components
3304 void Assembler::evpcmpeqd(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3305 assert(VM_Version::supports_evex(), "");
3306 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3307 attributes.set_is_evex_instruction();
3308 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3309 int encode = vex_prefix_and_encode(kdst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3310 emit_int8(0x76);
3311 emit_int8((unsigned char)(0xC0 | encode));
3312 }
3313
3314 void Assembler::evpcmpeqd(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3315 assert(VM_Version::supports_evex(), "");
3316 InstructionMark im(this);
3317 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3318 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3319 attributes.set_is_evex_instruction();
3320 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3321 int dst_enc = kdst->encoding();
3322 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3323 emit_int8(0x76);
3324 emit_operand(as_Register(dst_enc), src);
3325 }
3326
3327 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3328 void Assembler::pcmpeqq(XMMRegister dst, XMMRegister src) {
3329 assert(VM_Version::supports_sse4_1(), "");
3330 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3331 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3332 emit_int8(0x29);
3333 emit_int8((unsigned char)(0xC0 | encode));
3334 }
3335
3336 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3337 void Assembler::vpcmpeqq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3338 assert(VM_Version::supports_avx(), "");
3339 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3340 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3341 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3342 emit_int8(0x29);
3343 emit_int8((unsigned char)(0xC0 | encode));
3344 }
3345
3346 // In this context, kdst is written the mask used to process the equal components
3347 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3348 assert(VM_Version::supports_evex(), "");
3349 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3350 attributes.set_is_evex_instruction();
3351 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3352 int encode = vex_prefix_and_encode(kdst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3353 emit_int8(0x29);
3354 emit_int8((unsigned char)(0xC0 | encode));
3355 }
3356
3357 // In this context, kdst is written the mask used to process the equal components
3358 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3359 assert(VM_Version::supports_evex(), "");
3360 InstructionMark im(this);
3361 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3362 attributes.set_is_evex_instruction();
3363 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
3364 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3365 int dst_enc = kdst->encoding();
3366 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3367 emit_int8(0x29);
3368 emit_operand(as_Register(dst_enc), src);
3369 }
3370
3371 void Assembler::pmovmskb(Register dst, XMMRegister src) {
3372 assert(VM_Version::supports_sse2(), "");
3373 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3374 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3375 emit_int8((unsigned char)0xD7);
3376 emit_int8((unsigned char)(0xC0 | encode));
3377 }
3378
3379 void Assembler::vpmovmskb(Register dst, XMMRegister src) {
3380 assert(VM_Version::supports_avx2(), "");
3381 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3382 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3383 emit_int8((unsigned char)0xD7);
3384 emit_int8((unsigned char)(0xC0 | encode));
3385 }
3386
3387 void Assembler::pextrd(Register dst, XMMRegister src, int imm8) {
3388 assert(VM_Version::supports_sse4_1(), "");
3389 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3390 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3391 emit_int8(0x16);
3392 emit_int8((unsigned char)(0xC0 | encode));
3393 emit_int8(imm8);
3394 }
3395
3396 void Assembler::pextrd(Address dst, XMMRegister src, int imm8) {
3397 assert(VM_Version::supports_sse4_1(), "");
3398 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3399 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3400 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3401 emit_int8(0x16);
3402 emit_operand(src, dst);
3403 emit_int8(imm8);
3404 }
3405
3406 void Assembler::pextrq(Register dst, XMMRegister src, int imm8) {
3407 assert(VM_Version::supports_sse4_1(), "");
3408 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3409 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3410 emit_int8(0x16);
3411 emit_int8((unsigned char)(0xC0 | encode));
3412 emit_int8(imm8);
3413 }
3414
3415 void Assembler::pextrq(Address dst, XMMRegister src, int imm8) {
3416 assert(VM_Version::supports_sse4_1(), "");
3417 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3418 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3419 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3420 emit_int8(0x16);
3421 emit_operand(src, dst);
3422 emit_int8(imm8);
3423 }
3424
3425 void Assembler::pextrw(Register dst, XMMRegister src, int imm8) {
3426 assert(VM_Version::supports_sse2(), "");
3427 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3428 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3429 emit_int8((unsigned char)0xC5);
3430 emit_int8((unsigned char)(0xC0 | encode));
3431 emit_int8(imm8);
3432 }
3433
3434 void Assembler::pextrw(Address dst, XMMRegister src, int imm8) {
3435 assert(VM_Version::supports_sse4_1(), "");
3436 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3437 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
3438 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3439 emit_int8((unsigned char)0x15);
3440 emit_operand(src, dst);
3441 emit_int8(imm8);
3442 }
3443
3444 void Assembler::pextrb(Address dst, XMMRegister src, int imm8) {
3445 assert(VM_Version::supports_sse4_1(), "");
3446 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3447 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
3448 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3449 emit_int8(0x14);
3450 emit_operand(src, dst);
3451 emit_int8(imm8);
3452 }
3453
3454 void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) {
3455 assert(VM_Version::supports_sse4_1(), "");
3456 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3457 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3458 emit_int8(0x22);
3459 emit_int8((unsigned char)(0xC0 | encode));
3460 emit_int8(imm8);
3461 }
3462
3463 void Assembler::pinsrd(XMMRegister dst, Address src, int imm8) {
3464 assert(VM_Version::supports_sse4_1(), "");
3465 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3466 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3467 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3468 emit_int8(0x22);
3469 emit_operand(dst,src);
3470 emit_int8(imm8);
3471 }
3472
3473 void Assembler::pinsrq(XMMRegister dst, Register src, int imm8) {
3474 assert(VM_Version::supports_sse4_1(), "");
3475 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3476 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3477 emit_int8(0x22);
3478 emit_int8((unsigned char)(0xC0 | encode));
3479 emit_int8(imm8);
3480 }
3481
3482 void Assembler::pinsrq(XMMRegister dst, Address src, int imm8) {
3483 assert(VM_Version::supports_sse4_1(), "");
3484 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3485 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3486 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3487 emit_int8(0x22);
3488 emit_operand(dst, src);
3489 emit_int8(imm8);
3490 }
3491
3492 void Assembler::pinsrw(XMMRegister dst, Register src, int imm8) {
3493 assert(VM_Version::supports_sse2(), "");
3494 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3495 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3496 emit_int8((unsigned char)0xC4);
3497 emit_int8((unsigned char)(0xC0 | encode));
3498 emit_int8(imm8);
3499 }
3500
3501 void Assembler::pinsrw(XMMRegister dst, Address src, int imm8) {
3502 assert(VM_Version::supports_sse2(), "");
3503 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3504 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
3505 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3506 emit_int8((unsigned char)0xC4);
3507 emit_operand(dst, src);
3508 emit_int8(imm8);
3509 }
3510
3511 void Assembler::pinsrb(XMMRegister dst, Address src, int imm8) {
3512 assert(VM_Version::supports_sse4_1(), "");
3513 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3514 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
3515 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3516 emit_int8(0x20);
3517 emit_operand(dst, src);
3518 emit_int8(imm8);
3519 }
3520
3521 void Assembler::pmovzxbw(XMMRegister dst, Address src) {
3522 assert(VM_Version::supports_sse4_1(), "");
3523 InstructionMark im(this);
3524 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3525 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3526 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3527 emit_int8(0x30);
3528 emit_operand(dst, src);
3529 }
3530
3531 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3532 assert(VM_Version::supports_sse4_1(), "");
3533 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3534 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3535 emit_int8(0x30);
3536 emit_int8((unsigned char)(0xC0 | encode));
3537 }
3538
3539 void Assembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
3540 assert(VM_Version::supports_avx(), "");
3541 InstructionMark im(this);
3542 assert(dst != xnoreg, "sanity");
3543 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3544 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3545 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3546 emit_int8(0x30);
3547 emit_operand(dst, src);
3548 }
3549
3550 // generic
3551 void Assembler::pop(Register dst) {
3552 int encode = prefix_and_encode(dst->encoding());
3553 emit_int8(0x58 | encode);
3554 }
3555
3556 void Assembler::popcntl(Register dst, Address src) {
3557 assert(VM_Version::supports_popcnt(), "must support");
3558 InstructionMark im(this);
3559 emit_int8((unsigned char)0xF3);
3560 prefix(src, dst);
3561 emit_int8(0x0F);
3562 emit_int8((unsigned char)0xB8);
3563 emit_operand(dst, src);
3564 }
3565
3566 void Assembler::popcntl(Register dst, Register src) {
3567 assert(VM_Version::supports_popcnt(), "must support");
3568 emit_int8((unsigned char)0xF3);
3569 int encode = prefix_and_encode(dst->encoding(), src->encoding());
3570 emit_int8(0x0F);
3571 emit_int8((unsigned char)0xB8);
3572 emit_int8((unsigned char)(0xC0 | encode));
3573 }
3574
3575 void Assembler::popf() {
3576 emit_int8((unsigned char)0x9D);
3577 }
3578
3579 #ifndef _LP64 // no 32bit push/pop on amd64
3580 void Assembler::popl(Address dst) {
3581 // NOTE: this will adjust stack by 8byte on 64bits
3582 InstructionMark im(this);
3583 prefix(dst);
3584 emit_int8((unsigned char)0x8F);
3585 emit_operand(rax, dst);
3586 }
3587 #endif
3588
3589 void Assembler::prefetch_prefix(Address src) {
3590 prefix(src);
3591 emit_int8(0x0F);
3592 }
3593
3594 void Assembler::prefetchnta(Address src) {
3595 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3596 InstructionMark im(this);
3597 prefetch_prefix(src);
3598 emit_int8(0x18);
3599 emit_operand(rax, src); // 0, src
3600 }
3601
3602 void Assembler::prefetchr(Address src) {
3603 assert(VM_Version::supports_3dnow_prefetch(), "must support");
3604 InstructionMark im(this);
3605 prefetch_prefix(src);
3606 emit_int8(0x0D);
3607 emit_operand(rax, src); // 0, src
3608 }
3609
3610 void Assembler::prefetcht0(Address src) {
3611 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3612 InstructionMark im(this);
3613 prefetch_prefix(src);
3614 emit_int8(0x18);
3615 emit_operand(rcx, src); // 1, src
3616 }
3617
3618 void Assembler::prefetcht1(Address src) {
3619 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3620 InstructionMark im(this);
3621 prefetch_prefix(src);
3622 emit_int8(0x18);
3623 emit_operand(rdx, src); // 2, src
3624 }
3625
3626 void Assembler::prefetcht2(Address src) {
3627 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3628 InstructionMark im(this);
3629 prefetch_prefix(src);
3630 emit_int8(0x18);
3631 emit_operand(rbx, src); // 3, src
3632 }
3633
3634 void Assembler::prefetchw(Address src) {
3635 assert(VM_Version::supports_3dnow_prefetch(), "must support");
3636 InstructionMark im(this);
3637 prefetch_prefix(src);
3638 emit_int8(0x0D);
3639 emit_operand(rcx, src); // 1, src
3640 }
3641
3642 void Assembler::prefix(Prefix p) {
3643 emit_int8(p);
3644 }
3645
3646 void Assembler::pshufb(XMMRegister dst, XMMRegister src) {
3647 assert(VM_Version::supports_ssse3(), "");
3648 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3649 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3650 emit_int8(0x00);
3651 emit_int8((unsigned char)(0xC0 | encode));
3652 }
3653
3654 void Assembler::pshufb(XMMRegister dst, Address src) {
3655 assert(VM_Version::supports_ssse3(), "");
3656 InstructionMark im(this);
3657 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3658 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3659 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3660 emit_int8(0x00);
3661 emit_operand(dst, src);
3662 }
3663
3664 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
3665 assert(isByte(mode), "invalid value");
3666 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3667 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
3668 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3669 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3670 emit_int8(0x70);
3671 emit_int8((unsigned char)(0xC0 | encode));
3672 emit_int8(mode & 0xFF);
3673 }
3674
3675 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
3676 assert(isByte(mode), "invalid value");
3677 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3678 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3679 InstructionMark im(this);
3680 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3681 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3682 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3683 emit_int8(0x70);
3684 emit_operand(dst, src);
3685 emit_int8(mode & 0xFF);
3686 }
3687
3688 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
3689 assert(isByte(mode), "invalid value");
3690 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3691 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3692 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3693 emit_int8(0x70);
3694 emit_int8((unsigned char)(0xC0 | encode));
3695 emit_int8(mode & 0xFF);
3696 }
3697
3698 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
3699 assert(isByte(mode), "invalid value");
3700 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3701 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3702 InstructionMark im(this);
3703 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3704 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3705 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3706 emit_int8(0x70);
3707 emit_operand(dst, src);
3708 emit_int8(mode & 0xFF);
3709 }
3710
3711 void Assembler::psrldq(XMMRegister dst, int shift) {
3712 // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
3713 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3714 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3715 // XMM3 is for /3 encoding: 66 0F 73 /3 ib
3716 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3717 emit_int8(0x73);
3718 emit_int8((unsigned char)(0xC0 | encode));
3719 emit_int8(shift);
3720 }
3721
3722 void Assembler::pslldq(XMMRegister dst, int shift) {
3723 // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
3724 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3725 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3726 // XMM7 is for /7 encoding: 66 0F 73 /7 ib
3727 int encode = simd_prefix_and_encode(xmm7, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3728 emit_int8(0x73);
3729 emit_int8((unsigned char)(0xC0 | encode));
3730 emit_int8(shift);
3731 }
3732
3733 void Assembler::ptest(XMMRegister dst, Address src) {
3734 assert(VM_Version::supports_sse4_1(), "");
3735 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3736 InstructionMark im(this);
3737 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3738 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3739 emit_int8(0x17);
3740 emit_operand(dst, src);
3741 }
3742
3743 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
3744 assert(VM_Version::supports_sse4_1(), "");
3745 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3746 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3747 emit_int8(0x17);
3748 emit_int8((unsigned char)(0xC0 | encode));
3749 }
3750
3751 void Assembler::vptest(XMMRegister dst, Address src) {
3752 assert(VM_Version::supports_avx(), "");
3753 InstructionMark im(this);
3754 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3755 assert(dst != xnoreg, "sanity");
3756 // swap src<->dst for encoding
3757 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3758 emit_int8(0x17);
3759 emit_operand(dst, src);
3760 }
3761
3762 void Assembler::vptest(XMMRegister dst, XMMRegister src) {
3763 assert(VM_Version::supports_avx(), "");
3764 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3765 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3766 emit_int8(0x17);
3767 emit_int8((unsigned char)(0xC0 | encode));
3768 }
3769
3770 void Assembler::punpcklbw(XMMRegister dst, Address src) {
3771 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3772 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3773 InstructionMark im(this);
3774 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ false, /* uses_vl */ true);
3775 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3776 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3777 emit_int8(0x60);
3778 emit_operand(dst, src);
3779 }
3780
3781 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
3782 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3783 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ false, /* uses_vl */ true);
3784 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3785 emit_int8(0x60);
3786 emit_int8((unsigned char)(0xC0 | encode));
3787 }
3788
3789 void Assembler::punpckldq(XMMRegister dst, Address src) {
3790 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3791 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3792 InstructionMark im(this);
3793 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3794 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3795 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3796 emit_int8(0x62);
3797 emit_operand(dst, src);
3798 }
3799
3800 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) {
3801 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3802 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3803 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3804 emit_int8(0x62);
3805 emit_int8((unsigned char)(0xC0 | encode));
3806 }
3807
3808 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) {
3809 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3810 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3811 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3812 emit_int8(0x6C);
3813 emit_int8((unsigned char)(0xC0 | encode));
3814 }
3815
3816 void Assembler::push(int32_t imm32) {
3817 // in 64bits we push 64bits onto the stack but only
3818 // take a 32bit immediate
3819 emit_int8(0x68);
3820 emit_int32(imm32);
3821 }
3822
3823 void Assembler::push(Register src) {
3824 int encode = prefix_and_encode(src->encoding());
3825
3826 emit_int8(0x50 | encode);
3827 }
3828
3829 void Assembler::pushf() {
3830 emit_int8((unsigned char)0x9C);
3831 }
3832
3833 #ifndef _LP64 // no 32bit push/pop on amd64
3834 void Assembler::pushl(Address src) {
3835 // Note this will push 64bit on 64bit
3836 InstructionMark im(this);
3837 prefix(src);
3838 emit_int8((unsigned char)0xFF);
3839 emit_operand(rsi, src);
3840 }
3841 #endif
3842
3843 void Assembler::rcll(Register dst, int imm8) {
3844 assert(isShiftCount(imm8), "illegal shift count");
3845 int encode = prefix_and_encode(dst->encoding());
3846 if (imm8 == 1) {
3847 emit_int8((unsigned char)0xD1);
3848 emit_int8((unsigned char)(0xD0 | encode));
3849 } else {
3850 emit_int8((unsigned char)0xC1);
3851 emit_int8((unsigned char)0xD0 | encode);
3852 emit_int8(imm8);
3853 }
3854 }
3855
3856 void Assembler::rcpps(XMMRegister dst, XMMRegister src) {
3857 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3858 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3859 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
3860 emit_int8(0x53);
3861 emit_int8((unsigned char)(0xC0 | encode));
3862 }
3863
3864 void Assembler::rcpss(XMMRegister dst, XMMRegister src) {
3865 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3866 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3867 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3868 emit_int8(0x53);
3869 emit_int8((unsigned char)(0xC0 | encode));
3870 }
3871
3872 void Assembler::rdtsc() {
3873 emit_int8((unsigned char)0x0F);
3874 emit_int8((unsigned char)0x31);
3875 }
3876
3877 // copies data from [esi] to [edi] using rcx pointer sized words
3878 // generic
3879 void Assembler::rep_mov() {
3880 emit_int8((unsigned char)0xF3);
3881 // MOVSQ
3882 LP64_ONLY(prefix(REX_W));
3883 emit_int8((unsigned char)0xA5);
3884 }
3885
3886 // sets rcx bytes with rax, value at [edi]
3887 void Assembler::rep_stosb() {
3888 emit_int8((unsigned char)0xF3); // REP
3889 LP64_ONLY(prefix(REX_W));
3890 emit_int8((unsigned char)0xAA); // STOSB
3891 }
3892
3893 // sets rcx pointer sized words with rax, value at [edi]
3894 // generic
3895 void Assembler::rep_stos() {
3896 emit_int8((unsigned char)0xF3); // REP
3897 LP64_ONLY(prefix(REX_W)); // LP64:STOSQ, LP32:STOSD
3898 emit_int8((unsigned char)0xAB);
3899 }
3900
3901 // scans rcx pointer sized words at [edi] for occurance of rax,
3902 // generic
3903 void Assembler::repne_scan() { // repne_scan
3904 emit_int8((unsigned char)0xF2);
3905 // SCASQ
3906 LP64_ONLY(prefix(REX_W));
3907 emit_int8((unsigned char)0xAF);
3908 }
3909
3910 #ifdef _LP64
3911 // scans rcx 4 byte words at [edi] for occurance of rax,
3912 // generic
3913 void Assembler::repne_scanl() { // repne_scan
3914 emit_int8((unsigned char)0xF2);
3915 // SCASL
3916 emit_int8((unsigned char)0xAF);
3917 }
3918 #endif
3919
3920 void Assembler::ret(int imm16) {
3921 if (imm16 == 0) {
3922 emit_int8((unsigned char)0xC3);
3923 } else {
3924 emit_int8((unsigned char)0xC2);
3925 emit_int16(imm16);
3926 }
3927 }
3928
3929 void Assembler::sahf() {
3930 #ifdef _LP64
3931 // Not supported in 64bit mode
3932 ShouldNotReachHere();
3933 #endif
3934 emit_int8((unsigned char)0x9E);
3935 }
3936
3937 void Assembler::sarl(Register dst, int imm8) {
3938 int encode = prefix_and_encode(dst->encoding());
3939 assert(isShiftCount(imm8), "illegal shift count");
3940 if (imm8 == 1) {
3941 emit_int8((unsigned char)0xD1);
3942 emit_int8((unsigned char)(0xF8 | encode));
3943 } else {
3944 emit_int8((unsigned char)0xC1);
3945 emit_int8((unsigned char)(0xF8 | encode));
3946 emit_int8(imm8);
3947 }
3948 }
3949
3950 void Assembler::sarl(Register dst) {
3951 int encode = prefix_and_encode(dst->encoding());
3952 emit_int8((unsigned char)0xD3);
3953 emit_int8((unsigned char)(0xF8 | encode));
3954 }
3955
3956 void Assembler::sbbl(Address dst, int32_t imm32) {
3957 InstructionMark im(this);
3958 prefix(dst);
3959 emit_arith_operand(0x81, rbx, dst, imm32);
3960 }
3961
3962 void Assembler::sbbl(Register dst, int32_t imm32) {
3963 prefix(dst);
3964 emit_arith(0x81, 0xD8, dst, imm32);
3965 }
3966
3967
3968 void Assembler::sbbl(Register dst, Address src) {
3969 InstructionMark im(this);
3970 prefix(src, dst);
3971 emit_int8(0x1B);
3972 emit_operand(dst, src);
3973 }
3974
3975 void Assembler::sbbl(Register dst, Register src) {
3976 (void) prefix_and_encode(dst->encoding(), src->encoding());
3977 emit_arith(0x1B, 0xC0, dst, src);
3978 }
3979
3980 void Assembler::setb(Condition cc, Register dst) {
3981 assert(0 <= cc && cc < 16, "illegal cc");
3982 int encode = prefix_and_encode(dst->encoding(), true);
3983 emit_int8(0x0F);
3984 emit_int8((unsigned char)0x90 | cc);
3985 emit_int8((unsigned char)(0xC0 | encode));
3986 }
3987
3988 void Assembler::palignr(XMMRegister dst, XMMRegister src, int imm8) {
3989 assert(VM_Version::supports_ssse3(), "");
3990 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ false);
3991 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3992 emit_int8((unsigned char)0x0F);
3993 emit_int8((unsigned char)(0xC0 | encode));
3994 emit_int8(imm8);
3995 }
3996
3997 void Assembler::pblendw(XMMRegister dst, XMMRegister src, int imm8) {
3998 assert(VM_Version::supports_sse4_1(), "");
3999 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4000 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4001 emit_int8((unsigned char)0x0E);
4002 emit_int8((unsigned char)(0xC0 | encode));
4003 emit_int8(imm8);
4004 }
4005
4006 void Assembler::sha1rnds4(XMMRegister dst, XMMRegister src, int imm8) {
4007 assert(VM_Version::supports_sha(), "");
4008 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4009 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_3A, &attributes);
4010 emit_int8((unsigned char)0xCC);
4011 emit_int8((unsigned char)(0xC0 | encode));
4012 emit_int8((unsigned char)imm8);
4013 }
4014
4015 void Assembler::sha1nexte(XMMRegister dst, XMMRegister src) {
4016 assert(VM_Version::supports_sha(), "");
4017 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4018 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4019 emit_int8((unsigned char)0xC8);
4020 emit_int8((unsigned char)(0xC0 | encode));
4021 }
4022
4023 void Assembler::sha1msg1(XMMRegister dst, XMMRegister src) {
4024 assert(VM_Version::supports_sha(), "");
4025 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4026 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4027 emit_int8((unsigned char)0xC9);
4028 emit_int8((unsigned char)(0xC0 | encode));
4029 }
4030
4031 void Assembler::sha1msg2(XMMRegister dst, XMMRegister src) {
4032 assert(VM_Version::supports_sha(), "");
4033 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4034 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4035 emit_int8((unsigned char)0xCA);
4036 emit_int8((unsigned char)(0xC0 | encode));
4037 }
4038
4039 // xmm0 is implicit additional source to this instruction.
4040 void Assembler::sha256rnds2(XMMRegister dst, XMMRegister src) {
4041 assert(VM_Version::supports_sha(), "");
4042 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4043 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4044 emit_int8((unsigned char)0xCB);
4045 emit_int8((unsigned char)(0xC0 | encode));
4046 }
4047
4048 void Assembler::sha256msg1(XMMRegister dst, XMMRegister src) {
4049 assert(VM_Version::supports_sha(), "");
4050 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4051 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4052 emit_int8((unsigned char)0xCC);
4053 emit_int8((unsigned char)(0xC0 | encode));
4054 }
4055
4056 void Assembler::sha256msg2(XMMRegister dst, XMMRegister src) {
4057 assert(VM_Version::supports_sha(), "");
4058 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4059 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4060 emit_int8((unsigned char)0xCD);
4061 emit_int8((unsigned char)(0xC0 | encode));
4062 }
4063
4064
4065 void Assembler::shll(Register dst, int imm8) {
4066 assert(isShiftCount(imm8), "illegal shift count");
4067 int encode = prefix_and_encode(dst->encoding());
4068 if (imm8 == 1 ) {
4069 emit_int8((unsigned char)0xD1);
4070 emit_int8((unsigned char)(0xE0 | encode));
4071 } else {
4072 emit_int8((unsigned char)0xC1);
4073 emit_int8((unsigned char)(0xE0 | encode));
4074 emit_int8(imm8);
4075 }
4076 }
4077
4078 void Assembler::shll(Register dst) {
4079 int encode = prefix_and_encode(dst->encoding());
4080 emit_int8((unsigned char)0xD3);
4081 emit_int8((unsigned char)(0xE0 | encode));
4082 }
4083
4084 void Assembler::shrl(Register dst, int imm8) {
4085 assert(isShiftCount(imm8), "illegal shift count");
4086 int encode = prefix_and_encode(dst->encoding());
4087 emit_int8((unsigned char)0xC1);
4088 emit_int8((unsigned char)(0xE8 | encode));
4089 emit_int8(imm8);
4090 }
4091
4092 void Assembler::shrl(Register dst) {
4093 int encode = prefix_and_encode(dst->encoding());
4094 emit_int8((unsigned char)0xD3);
4095 emit_int8((unsigned char)(0xE8 | encode));
4096 }
4097
4098 // copies a single word from [esi] to [edi]
4099 void Assembler::smovl() {
4100 emit_int8((unsigned char)0xA5);
4101 }
4102
4103 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
4104 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4105 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4106 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4107 emit_int8(0x51);
4108 emit_int8((unsigned char)(0xC0 | encode));
4109 }
4110
4111 void Assembler::sqrtsd(XMMRegister dst, Address src) {
4112 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4113 InstructionMark im(this);
4114 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4115 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4116 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4117 emit_int8(0x51);
4118 emit_operand(dst, src);
4119 }
4120
4121 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
4122 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4123 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4124 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4125 emit_int8(0x51);
4126 emit_int8((unsigned char)(0xC0 | encode));
4127 }
4128
4129 void Assembler::std() {
4130 emit_int8((unsigned char)0xFD);
4131 }
4132
4133 void Assembler::sqrtss(XMMRegister dst, Address src) {
4134 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4135 InstructionMark im(this);
4136 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4137 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4138 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4139 emit_int8(0x51);
4140 emit_operand(dst, src);
4141 }
4142
4143 void Assembler::stmxcsr( Address dst) {
4144 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4145 InstructionMark im(this);
4146 prefix(dst);
4147 emit_int8(0x0F);
4148 emit_int8((unsigned char)0xAE);
4149 emit_operand(as_Register(3), dst);
4150 }
4151
4152 void Assembler::subl(Address dst, int32_t imm32) {
4153 InstructionMark im(this);
4154 prefix(dst);
4155 emit_arith_operand(0x81, rbp, dst, imm32);
4156 }
4157
4158 void Assembler::subl(Address dst, Register src) {
4159 InstructionMark im(this);
4160 prefix(dst, src);
4161 emit_int8(0x29);
4162 emit_operand(src, dst);
4163 }
4164
4165 void Assembler::subl(Register dst, int32_t imm32) {
4166 prefix(dst);
4167 emit_arith(0x81, 0xE8, dst, imm32);
4168 }
4169
4170 // Force generation of a 4 byte immediate value even if it fits into 8bit
4171 void Assembler::subl_imm32(Register dst, int32_t imm32) {
4172 prefix(dst);
4173 emit_arith_imm32(0x81, 0xE8, dst, imm32);
4174 }
4175
4176 void Assembler::subl(Register dst, Address src) {
4177 InstructionMark im(this);
4178 prefix(src, dst);
4179 emit_int8(0x2B);
4180 emit_operand(dst, src);
4181 }
4182
4183 void Assembler::subl(Register dst, Register src) {
4184 (void) prefix_and_encode(dst->encoding(), src->encoding());
4185 emit_arith(0x2B, 0xC0, dst, src);
4186 }
4187
4188 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
4189 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4190 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4191 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4192 emit_int8(0x5C);
4193 emit_int8((unsigned char)(0xC0 | encode));
4194 }
4195
4196 void Assembler::subsd(XMMRegister dst, Address src) {
4197 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4198 InstructionMark im(this);
4199 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4200 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4201 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4202 emit_int8(0x5C);
4203 emit_operand(dst, src);
4204 }
4205
4206 void Assembler::subss(XMMRegister dst, XMMRegister src) {
4207 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4208 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false , /* uses_vl */ false);
4209 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4210 emit_int8(0x5C);
4211 emit_int8((unsigned char)(0xC0 | encode));
4212 }
4213
4214 void Assembler::subss(XMMRegister dst, Address src) {
4215 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4216 InstructionMark im(this);
4217 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4218 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4219 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4220 emit_int8(0x5C);
4221 emit_operand(dst, src);
4222 }
4223
4224 void Assembler::testb(Register dst, int imm8) {
4225 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
4226 (void) prefix_and_encode(dst->encoding(), true);
4227 emit_arith_b(0xF6, 0xC0, dst, imm8);
4228 }
4229
4230 void Assembler::testb(Address dst, int imm8) {
4231 InstructionMark im(this);
4232 prefix(dst);
4233 emit_int8((unsigned char)0xF6);
4234 emit_operand(rax, dst, 1);
4235 emit_int8(imm8);
4236 }
4237
4238 void Assembler::testl(Register dst, int32_t imm32) {
4239 // not using emit_arith because test
4240 // doesn't support sign-extension of
4241 // 8bit operands
4242 int encode = dst->encoding();
4243 if (encode == 0) {
4244 emit_int8((unsigned char)0xA9);
4245 } else {
4246 encode = prefix_and_encode(encode);
4247 emit_int8((unsigned char)0xF7);
4248 emit_int8((unsigned char)(0xC0 | encode));
4249 }
4250 emit_int32(imm32);
4251 }
4252
4253 void Assembler::testl(Register dst, Register src) {
4254 (void) prefix_and_encode(dst->encoding(), src->encoding());
4255 emit_arith(0x85, 0xC0, dst, src);
4256 }
4257
4258 void Assembler::testl(Register dst, Address src) {
4259 InstructionMark im(this);
4260 prefix(src, dst);
4261 emit_int8((unsigned char)0x85);
4262 emit_operand(dst, src);
4263 }
4264
4265 void Assembler::tzcntl(Register dst, Register src) {
4266 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
4267 emit_int8((unsigned char)0xF3);
4268 int encode = prefix_and_encode(dst->encoding(), src->encoding());
4269 emit_int8(0x0F);
4270 emit_int8((unsigned char)0xBC);
4271 emit_int8((unsigned char)0xC0 | encode);
4272 }
4273
4274 void Assembler::tzcntq(Register dst, Register src) {
4275 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
4276 emit_int8((unsigned char)0xF3);
4277 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4278 emit_int8(0x0F);
4279 emit_int8((unsigned char)0xBC);
4280 emit_int8((unsigned char)(0xC0 | encode));
4281 }
4282
4283 void Assembler::ucomisd(XMMRegister dst, Address src) {
4284 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4285 InstructionMark im(this);
4286 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4287 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4288 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4289 emit_int8(0x2E);
4290 emit_operand(dst, src);
4291 }
4292
4293 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
4294 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4295 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4296 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4297 emit_int8(0x2E);
4298 emit_int8((unsigned char)(0xC0 | encode));
4299 }
4300
4301 void Assembler::ucomiss(XMMRegister dst, Address src) {
4302 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4303 InstructionMark im(this);
4304 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4305 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4306 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4307 emit_int8(0x2E);
4308 emit_operand(dst, src);
4309 }
4310
4311 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
4312 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4313 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4314 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4315 emit_int8(0x2E);
4316 emit_int8((unsigned char)(0xC0 | encode));
4317 }
4318
4319 void Assembler::xabort(int8_t imm8) {
4320 emit_int8((unsigned char)0xC6);
4321 emit_int8((unsigned char)0xF8);
4322 emit_int8((unsigned char)(imm8 & 0xFF));
4323 }
4324
4325 void Assembler::xaddl(Address dst, Register src) {
4326 InstructionMark im(this);
4327 prefix(dst, src);
4328 emit_int8(0x0F);
4329 emit_int8((unsigned char)0xC1);
4330 emit_operand(src, dst);
4331 }
4332
4333 void Assembler::xbegin(Label& abort, relocInfo::relocType rtype) {
4334 InstructionMark im(this);
4335 relocate(rtype);
4336 if (abort.is_bound()) {
4337 address entry = target(abort);
4338 assert(entry != NULL, "abort entry NULL");
4339 intptr_t offset = entry - pc();
4340 emit_int8((unsigned char)0xC7);
4341 emit_int8((unsigned char)0xF8);
4342 emit_int32(offset - 6); // 2 opcode + 4 address
4343 } else {
4344 abort.add_patch_at(code(), locator());
4345 emit_int8((unsigned char)0xC7);
4346 emit_int8((unsigned char)0xF8);
4347 emit_int32(0);
4348 }
4349 }
4350
4351 void Assembler::xchgl(Register dst, Address src) { // xchg
4352 InstructionMark im(this);
4353 prefix(src, dst);
4354 emit_int8((unsigned char)0x87);
4355 emit_operand(dst, src);
4356 }
4357
4358 void Assembler::xchgl(Register dst, Register src) {
4359 int encode = prefix_and_encode(dst->encoding(), src->encoding());
4360 emit_int8((unsigned char)0x87);
4361 emit_int8((unsigned char)(0xC0 | encode));
4362 }
4363
4364 void Assembler::xend() {
4365 emit_int8((unsigned char)0x0F);
4366 emit_int8((unsigned char)0x01);
4367 emit_int8((unsigned char)0xD5);
4368 }
4369
4370 void Assembler::xgetbv() {
4371 emit_int8(0x0F);
4372 emit_int8(0x01);
4373 emit_int8((unsigned char)0xD0);
4374 }
4375
4376 void Assembler::xorl(Register dst, int32_t imm32) {
4377 prefix(dst);
4378 emit_arith(0x81, 0xF0, dst, imm32);
4379 }
4380
4381 void Assembler::xorl(Register dst, Address src) {
4382 InstructionMark im(this);
4383 prefix(src, dst);
4384 emit_int8(0x33);
4385 emit_operand(dst, src);
4386 }
4387
4388 void Assembler::xorl(Register dst, Register src) {
4389 (void) prefix_and_encode(dst->encoding(), src->encoding());
4390 emit_arith(0x33, 0xC0, dst, src);
4391 }
4392
4393 void Assembler::xorb(Register dst, Address src) {
4394 InstructionMark im(this);
4395 prefix(src, dst);
4396 emit_int8(0x32);
4397 emit_operand(dst, src);
4398 }
4399
4400 // AVX 3-operands scalar float-point arithmetic instructions
4401
4402 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) {
4403 assert(VM_Version::supports_avx(), "");
4404 InstructionMark im(this);
4405 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4406 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4407 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4408 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4409 emit_int8(0x58);
4410 emit_operand(dst, src);
4411 }
4412
4413 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4414 assert(VM_Version::supports_avx(), "");
4415 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4416 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4417 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4418 emit_int8(0x58);
4419 emit_int8((unsigned char)(0xC0 | encode));
4420 }
4421
4422 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) {
4423 assert(VM_Version::supports_avx(), "");
4424 InstructionMark im(this);
4425 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4426 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4427 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4428 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4429 emit_int8(0x58);
4430 emit_operand(dst, src);
4431 }
4432
4433 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4434 assert(VM_Version::supports_avx(), "");
4435 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4436 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4437 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4438 emit_int8(0x58);
4439 emit_int8((unsigned char)(0xC0 | encode));
4440 }
4441
4442 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) {
4443 assert(VM_Version::supports_avx(), "");
4444 InstructionMark im(this);
4445 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4446 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4447 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4448 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4449 emit_int8(0x5E);
4450 emit_operand(dst, src);
4451 }
4452
4453 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4454 assert(VM_Version::supports_avx(), "");
4455 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4456 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4457 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4458 emit_int8(0x5E);
4459 emit_int8((unsigned char)(0xC0 | encode));
4460 }
4461
4462 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) {
4463 assert(VM_Version::supports_avx(), "");
4464 InstructionMark im(this);
4465 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4466 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4467 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4468 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4469 emit_int8(0x5E);
4470 emit_operand(dst, src);
4471 }
4472
4473 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4474 assert(VM_Version::supports_avx(), "");
4475 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4476 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4477 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4478 emit_int8(0x5E);
4479 emit_int8((unsigned char)(0xC0 | encode));
4480 }
4481
4482 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) {
4483 assert(VM_Version::supports_avx(), "");
4484 InstructionMark im(this);
4485 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4486 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4487 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4488 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4489 emit_int8(0x59);
4490 emit_operand(dst, src);
4491 }
4492
4493 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4494 assert(VM_Version::supports_avx(), "");
4495 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4496 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4497 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4498 emit_int8(0x59);
4499 emit_int8((unsigned char)(0xC0 | encode));
4500 }
4501
4502 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) {
4503 assert(VM_Version::supports_avx(), "");
4504 InstructionMark im(this);
4505 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4506 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4507 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4508 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4509 emit_int8(0x59);
4510 emit_operand(dst, src);
4511 }
4512
4513 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4514 assert(VM_Version::supports_avx(), "");
4515 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4516 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4517 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4518 emit_int8(0x59);
4519 emit_int8((unsigned char)(0xC0 | encode));
4520 }
4521
4522 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) {
4523 assert(VM_Version::supports_avx(), "");
4524 InstructionMark im(this);
4525 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4526 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4527 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4528 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4529 emit_int8(0x5C);
4530 emit_operand(dst, src);
4531 }
4532
4533 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4534 assert(VM_Version::supports_avx(), "");
4535 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4536 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4537 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4538 emit_int8(0x5C);
4539 emit_int8((unsigned char)(0xC0 | encode));
4540 }
4541
4542 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) {
4543 assert(VM_Version::supports_avx(), "");
4544 InstructionMark im(this);
4545 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4546 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4547 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4548 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4549 emit_int8(0x5C);
4550 emit_operand(dst, src);
4551 }
4552
4553 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4554 assert(VM_Version::supports_avx(), "");
4555 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4556 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4557 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4558 emit_int8(0x5C);
4559 emit_int8((unsigned char)(0xC0 | encode));
4560 }
4561
4562 //====================VECTOR ARITHMETIC=====================================
4563
4564 // Float-point vector arithmetic
4565
4566 void Assembler::addpd(XMMRegister dst, XMMRegister src) {
4567 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4568 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4569 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4570 emit_int8(0x58);
4571 emit_int8((unsigned char)(0xC0 | encode));
4572 }
4573
4574 void Assembler::addpd(XMMRegister dst, Address src) {
4575 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4576 InstructionMark im(this);
4577 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4578 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4579 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4580 emit_int8(0x58);
4581 emit_operand(dst, src);
4582 }
4583
4584
4585 void Assembler::addps(XMMRegister dst, XMMRegister src) {
4586 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4587 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4588 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4589 emit_int8(0x58);
4590 emit_int8((unsigned char)(0xC0 | encode));
4591 }
4592
4593 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4594 assert(VM_Version::supports_avx(), "");
4595 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4596 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4597 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4598 emit_int8(0x58);
4599 emit_int8((unsigned char)(0xC0 | encode));
4600 }
4601
4602 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4603 assert(VM_Version::supports_avx(), "");
4604 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4605 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4606 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4607 emit_int8(0x58);
4608 emit_int8((unsigned char)(0xC0 | encode));
4609 }
4610
4611 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4612 assert(VM_Version::supports_avx(), "");
4613 InstructionMark im(this);
4614 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4615 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4616 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4617 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4618 emit_int8(0x58);
4619 emit_operand(dst, src);
4620 }
4621
4622 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4623 assert(VM_Version::supports_avx(), "");
4624 InstructionMark im(this);
4625 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4626 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4627 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4628 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4629 emit_int8(0x58);
4630 emit_operand(dst, src);
4631 }
4632
4633 void Assembler::subpd(XMMRegister dst, XMMRegister src) {
4634 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4635 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4636 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4637 emit_int8(0x5C);
4638 emit_int8((unsigned char)(0xC0 | encode));
4639 }
4640
4641 void Assembler::subps(XMMRegister dst, XMMRegister src) {
4642 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4643 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4644 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4645 emit_int8(0x5C);
4646 emit_int8((unsigned char)(0xC0 | encode));
4647 }
4648
4649 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4650 assert(VM_Version::supports_avx(), "");
4651 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4652 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4653 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4654 emit_int8(0x5C);
4655 emit_int8((unsigned char)(0xC0 | encode));
4656 }
4657
4658 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4659 assert(VM_Version::supports_avx(), "");
4660 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4661 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4662 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4663 emit_int8(0x5C);
4664 emit_int8((unsigned char)(0xC0 | encode));
4665 }
4666
4667 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4668 assert(VM_Version::supports_avx(), "");
4669 InstructionMark im(this);
4670 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4671 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4672 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4673 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4674 emit_int8(0x5C);
4675 emit_operand(dst, src);
4676 }
4677
4678 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4679 assert(VM_Version::supports_avx(), "");
4680 InstructionMark im(this);
4681 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4682 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4683 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4684 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4685 emit_int8(0x5C);
4686 emit_operand(dst, src);
4687 }
4688
4689 void Assembler::mulpd(XMMRegister dst, XMMRegister src) {
4690 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4691 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4692 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4693 emit_int8(0x59);
4694 emit_int8((unsigned char)(0xC0 | encode));
4695 }
4696
4697 void Assembler::mulpd(XMMRegister dst, Address src) {
4698 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4699 InstructionMark im(this);
4700 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4701 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4702 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4703 emit_int8(0x59);
4704 emit_operand(dst, src);
4705 }
4706
4707 void Assembler::mulps(XMMRegister dst, XMMRegister src) {
4708 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4709 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4710 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4711 emit_int8(0x59);
4712 emit_int8((unsigned char)(0xC0 | encode));
4713 }
4714
4715 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4716 assert(VM_Version::supports_avx(), "");
4717 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4718 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4719 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4720 emit_int8(0x59);
4721 emit_int8((unsigned char)(0xC0 | encode));
4722 }
4723
4724 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4725 assert(VM_Version::supports_avx(), "");
4726 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4727 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4728 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4729 emit_int8(0x59);
4730 emit_int8((unsigned char)(0xC0 | encode));
4731 }
4732
4733 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4734 assert(VM_Version::supports_avx(), "");
4735 InstructionMark im(this);
4736 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4737 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4738 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4739 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4740 emit_int8(0x59);
4741 emit_operand(dst, src);
4742 }
4743
4744 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4745 assert(VM_Version::supports_avx(), "");
4746 InstructionMark im(this);
4747 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4748 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4749 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4750 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4751 emit_int8(0x59);
4752 emit_operand(dst, src);
4753 }
4754
4755 void Assembler::divpd(XMMRegister dst, XMMRegister src) {
4756 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4757 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4758 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4759 emit_int8(0x5E);
4760 emit_int8((unsigned char)(0xC0 | encode));
4761 }
4762
4763 void Assembler::divps(XMMRegister dst, XMMRegister src) {
4764 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4765 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4766 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4767 emit_int8(0x5E);
4768 emit_int8((unsigned char)(0xC0 | encode));
4769 }
4770
4771 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4772 assert(VM_Version::supports_avx(), "");
4773 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4774 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4775 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4776 emit_int8(0x5E);
4777 emit_int8((unsigned char)(0xC0 | encode));
4778 }
4779
4780 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4781 assert(VM_Version::supports_avx(), "");
4782 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4783 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4784 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4785 emit_int8(0x5E);
4786 emit_int8((unsigned char)(0xC0 | encode));
4787 }
4788
4789 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4790 assert(VM_Version::supports_avx(), "");
4791 InstructionMark im(this);
4792 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4793 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4794 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4795 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4796 emit_int8(0x5E);
4797 emit_operand(dst, src);
4798 }
4799
4800 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4801 assert(VM_Version::supports_avx(), "");
4802 InstructionMark im(this);
4803 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4804 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4805 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4806 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4807 emit_int8(0x5E);
4808 emit_operand(dst, src);
4809 }
4810
4811 void Assembler::vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len) {
4812 assert(VM_Version::supports_avx(), "");
4813 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4814 int nds_enc = 0;
4815 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4816 emit_int8(0x51);
4817 emit_int8((unsigned char)(0xC0 | encode));
4818 }
4819
4820 void Assembler::vsqrtpd(XMMRegister dst, Address src, int vector_len) {
4821 assert(VM_Version::supports_avx(), "");
4822 InstructionMark im(this);
4823 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4824 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4825 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4826 emit_int8(0x51);
4827 emit_operand(dst, src);
4828 }
4829
4830 void Assembler::andpd(XMMRegister dst, XMMRegister src) {
4831 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4832 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4833 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4834 emit_int8(0x54);
4835 emit_int8((unsigned char)(0xC0 | encode));
4836 }
4837
4838 void Assembler::andps(XMMRegister dst, XMMRegister src) {
4839 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4840 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4841 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4842 emit_int8(0x54);
4843 emit_int8((unsigned char)(0xC0 | encode));
4844 }
4845
4846 void Assembler::andps(XMMRegister dst, Address src) {
4847 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4848 InstructionMark im(this);
4849 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4850 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4851 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4852 emit_int8(0x54);
4853 emit_operand(dst, src);
4854 }
4855
4856 void Assembler::andpd(XMMRegister dst, Address src) {
4857 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4858 InstructionMark im(this);
4859 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4860 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4861 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4862 emit_int8(0x54);
4863 emit_operand(dst, src);
4864 }
4865
4866 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4867 assert(VM_Version::supports_avx(), "");
4868 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4869 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4870 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4871 emit_int8(0x54);
4872 emit_int8((unsigned char)(0xC0 | encode));
4873 }
4874
4875 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4876 assert(VM_Version::supports_avx(), "");
4877 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4878 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4879 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4880 emit_int8(0x54);
4881 emit_int8((unsigned char)(0xC0 | encode));
4882 }
4883
4884 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4885 assert(VM_Version::supports_avx(), "");
4886 InstructionMark im(this);
4887 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4888 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4889 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4890 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4891 emit_int8(0x54);
4892 emit_operand(dst, src);
4893 }
4894
4895 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4896 assert(VM_Version::supports_avx(), "");
4897 InstructionMark im(this);
4898 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4899 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4900 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4901 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4902 emit_int8(0x54);
4903 emit_operand(dst, src);
4904 }
4905
4906 void Assembler::unpckhpd(XMMRegister dst, XMMRegister src) {
4907 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4908 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4909 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4910 emit_int8(0x15);
4911 emit_int8((unsigned char)(0xC0 | encode));
4912 }
4913
4914 void Assembler::unpcklpd(XMMRegister dst, XMMRegister src) {
4915 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4916 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4917 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4918 emit_int8(0x14);
4919 emit_int8((unsigned char)(0xC0 | encode));
4920 }
4921
4922 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
4923 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4924 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4925 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4926 emit_int8(0x57);
4927 emit_int8((unsigned char)(0xC0 | encode));
4928 }
4929
4930 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
4931 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4932 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4933 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4934 emit_int8(0x57);
4935 emit_int8((unsigned char)(0xC0 | encode));
4936 }
4937
4938 void Assembler::xorpd(XMMRegister dst, Address src) {
4939 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4940 InstructionMark im(this);
4941 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4942 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4943 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4944 emit_int8(0x57);
4945 emit_operand(dst, src);
4946 }
4947
4948 void Assembler::xorps(XMMRegister dst, Address src) {
4949 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4950 InstructionMark im(this);
4951 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4952 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4953 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4954 emit_int8(0x57);
4955 emit_operand(dst, src);
4956 }
4957
4958 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4959 assert(VM_Version::supports_avx(), "");
4960 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4961 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4962 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4963 emit_int8(0x57);
4964 emit_int8((unsigned char)(0xC0 | encode));
4965 }
4966
4967 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4968 assert(VM_Version::supports_avx(), "");
4969 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4970 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4971 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4972 emit_int8(0x57);
4973 emit_int8((unsigned char)(0xC0 | encode));
4974 }
4975
4976 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4977 assert(VM_Version::supports_avx(), "");
4978 InstructionMark im(this);
4979 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4980 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4981 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4982 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4983 emit_int8(0x57);
4984 emit_operand(dst, src);
4985 }
4986
4987 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4988 assert(VM_Version::supports_avx(), "");
4989 InstructionMark im(this);
4990 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4991 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4992 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4993 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4994 emit_int8(0x57);
4995 emit_operand(dst, src);
4996 }
4997
4998 // Integer vector arithmetic
4999 void Assembler::vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5000 assert(VM_Version::supports_avx() && (vector_len == 0) ||
5001 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
5002 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5003 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5004 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5005 emit_int8(0x01);
5006 emit_int8((unsigned char)(0xC0 | encode));
5007 }
5008
5009 void Assembler::vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5010 assert(VM_Version::supports_avx() && (vector_len == 0) ||
5011 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
5012 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5013 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5014 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5015 emit_int8(0x02);
5016 emit_int8((unsigned char)(0xC0 | encode));
5017 }
5018
5019 void Assembler::paddb(XMMRegister dst, XMMRegister src) {
5020 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5021 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5022 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5023 emit_int8((unsigned char)0xFC);
5024 emit_int8((unsigned char)(0xC0 | encode));
5025 }
5026
5027 void Assembler::paddw(XMMRegister dst, XMMRegister src) {
5028 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5029 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5030 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5031 emit_int8((unsigned char)0xFD);
5032 emit_int8((unsigned char)(0xC0 | encode));
5033 }
5034
5035 void Assembler::paddd(XMMRegister dst, XMMRegister src) {
5036 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5037 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5038 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5039 emit_int8((unsigned char)0xFE);
5040 emit_int8((unsigned char)(0xC0 | encode));
5041 }
5042
5043 void Assembler::paddd(XMMRegister dst, Address src) {
5044 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5045 InstructionMark im(this);
5046 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5047 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5048 emit_int8((unsigned char)0xFE);
5049 emit_operand(dst, src);
5050 }
5051
5052 void Assembler::paddq(XMMRegister dst, XMMRegister src) {
5053 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5054 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5055 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5056 emit_int8((unsigned char)0xD4);
5057 emit_int8((unsigned char)(0xC0 | encode));
5058 }
5059
5060 void Assembler::phaddw(XMMRegister dst, XMMRegister src) {
5061 assert(VM_Version::supports_sse3(), "");
5062 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5063 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5064 emit_int8(0x01);
5065 emit_int8((unsigned char)(0xC0 | encode));
5066 }
5067
5068 void Assembler::phaddd(XMMRegister dst, XMMRegister src) {
5069 assert(VM_Version::supports_sse3(), "");
5070 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5071 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5072 emit_int8(0x02);
5073 emit_int8((unsigned char)(0xC0 | encode));
5074 }
5075
5076 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5077 assert(UseAVX > 0, "requires some form of AVX");
5078 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5079 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5080 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5081 emit_int8((unsigned char)0xFC);
5082 emit_int8((unsigned char)(0xC0 | encode));
5083 }
5084
5085 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5086 assert(UseAVX > 0, "requires some form of AVX");
5087 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5088 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5089 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5090 emit_int8((unsigned char)0xFD);
5091 emit_int8((unsigned char)(0xC0 | encode));
5092 }
5093
5094 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5095 assert(UseAVX > 0, "requires some form of AVX");
5096 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5097 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5098 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5099 emit_int8((unsigned char)0xFE);
5100 emit_int8((unsigned char)(0xC0 | encode));
5101 }
5102
5103 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5104 assert(UseAVX > 0, "requires some form of AVX");
5105 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5106 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5107 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5108 emit_int8((unsigned char)0xD4);
5109 emit_int8((unsigned char)(0xC0 | encode));
5110 }
5111
5112 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5113 assert(UseAVX > 0, "requires some form of AVX");
5114 InstructionMark im(this);
5115 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5116 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5117 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5118 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5119 emit_int8((unsigned char)0xFC);
5120 emit_operand(dst, src);
5121 }
5122
5123 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5124 assert(UseAVX > 0, "requires some form of AVX");
5125 InstructionMark im(this);
5126 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5127 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5128 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5129 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5130 emit_int8((unsigned char)0xFD);
5131 emit_operand(dst, src);
5132 }
5133
5134 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5135 assert(UseAVX > 0, "requires some form of AVX");
5136 InstructionMark im(this);
5137 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5138 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5139 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5140 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5141 emit_int8((unsigned char)0xFE);
5142 emit_operand(dst, src);
5143 }
5144
5145 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5146 assert(UseAVX > 0, "requires some form of AVX");
5147 InstructionMark im(this);
5148 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5149 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5150 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5151 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5152 emit_int8((unsigned char)0xD4);
5153 emit_operand(dst, src);
5154 }
5155
5156 void Assembler::psubb(XMMRegister dst, XMMRegister src) {
5157 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5158 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5159 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5160 emit_int8((unsigned char)0xF8);
5161 emit_int8((unsigned char)(0xC0 | encode));
5162 }
5163
5164 void Assembler::psubw(XMMRegister dst, XMMRegister src) {
5165 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5166 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5167 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5168 emit_int8((unsigned char)0xF9);
5169 emit_int8((unsigned char)(0xC0 | encode));
5170 }
5171
5172 void Assembler::psubd(XMMRegister dst, XMMRegister src) {
5173 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5174 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5175 emit_int8((unsigned char)0xFA);
5176 emit_int8((unsigned char)(0xC0 | encode));
5177 }
5178
5179 void Assembler::psubq(XMMRegister dst, XMMRegister src) {
5180 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5181 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5182 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5183 emit_int8((unsigned char)0xFB);
5184 emit_int8((unsigned char)(0xC0 | encode));
5185 }
5186
5187 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5188 assert(UseAVX > 0, "requires some form of AVX");
5189 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5190 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5191 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5192 emit_int8((unsigned char)0xF8);
5193 emit_int8((unsigned char)(0xC0 | encode));
5194 }
5195
5196 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5197 assert(UseAVX > 0, "requires some form of AVX");
5198 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5199 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5200 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5201 emit_int8((unsigned char)0xF9);
5202 emit_int8((unsigned char)(0xC0 | encode));
5203 }
5204
5205 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5206 assert(UseAVX > 0, "requires some form of AVX");
5207 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5208 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5209 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5210 emit_int8((unsigned char)0xFA);
5211 emit_int8((unsigned char)(0xC0 | encode));
5212 }
5213
5214 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5215 assert(UseAVX > 0, "requires some form of AVX");
5216 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5217 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5218 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5219 emit_int8((unsigned char)0xFB);
5220 emit_int8((unsigned char)(0xC0 | encode));
5221 }
5222
5223 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5224 assert(UseAVX > 0, "requires some form of AVX");
5225 InstructionMark im(this);
5226 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5227 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5228 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5229 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5230 emit_int8((unsigned char)0xF8);
5231 emit_operand(dst, src);
5232 }
5233
5234 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5235 assert(UseAVX > 0, "requires some form of AVX");
5236 InstructionMark im(this);
5237 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5238 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5239 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5240 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5241 emit_int8((unsigned char)0xF9);
5242 emit_operand(dst, src);
5243 }
5244
5245 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5246 assert(UseAVX > 0, "requires some form of AVX");
5247 InstructionMark im(this);
5248 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5249 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5250 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5251 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5252 emit_int8((unsigned char)0xFA);
5253 emit_operand(dst, src);
5254 }
5255
5256 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5257 assert(UseAVX > 0, "requires some form of AVX");
5258 InstructionMark im(this);
5259 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5260 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5261 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5262 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5263 emit_int8((unsigned char)0xFB);
5264 emit_operand(dst, src);
5265 }
5266
5267 void Assembler::pmullw(XMMRegister dst, XMMRegister src) {
5268 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5269 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5270 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5271 emit_int8((unsigned char)0xD5);
5272 emit_int8((unsigned char)(0xC0 | encode));
5273 }
5274
5275 void Assembler::pmulld(XMMRegister dst, XMMRegister src) {
5276 assert(VM_Version::supports_sse4_1(), "");
5277 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5278 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5279 emit_int8(0x40);
5280 emit_int8((unsigned char)(0xC0 | encode));
5281 }
5282
5283 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5284 assert(UseAVX > 0, "requires some form of AVX");
5285 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5286 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5287 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5288 emit_int8((unsigned char)0xD5);
5289 emit_int8((unsigned char)(0xC0 | encode));
5290 }
5291
5292 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5293 assert(UseAVX > 0, "requires some form of AVX");
5294 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5295 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5296 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5297 emit_int8(0x40);
5298 emit_int8((unsigned char)(0xC0 | encode));
5299 }
5300
5301 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5302 assert(UseAVX > 2, "requires some form of AVX");
5303 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5304 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5305 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5306 emit_int8(0x40);
5307 emit_int8((unsigned char)(0xC0 | encode));
5308 }
5309
5310 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5311 assert(UseAVX > 0, "requires some form of AVX");
5312 InstructionMark im(this);
5313 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5314 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5315 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5316 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5317 emit_int8((unsigned char)0xD5);
5318 emit_operand(dst, src);
5319 }
5320
5321 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5322 assert(UseAVX > 0, "requires some form of AVX");
5323 InstructionMark im(this);
5324 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5325 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5326 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5327 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5328 emit_int8(0x40);
5329 emit_operand(dst, src);
5330 }
5331
5332 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5333 assert(UseAVX > 0, "requires some form of AVX");
5334 InstructionMark im(this);
5335 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5336 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5337 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5338 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5339 emit_int8(0x40);
5340 emit_operand(dst, src);
5341 }
5342
5343 // Shift packed integers left by specified number of bits.
5344 void Assembler::psllw(XMMRegister dst, int shift) {
5345 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5346 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5347 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
5348 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5349 emit_int8(0x71);
5350 emit_int8((unsigned char)(0xC0 | encode));
5351 emit_int8(shift & 0xFF);
5352 }
5353
5354 void Assembler::pslld(XMMRegister dst, int shift) {
5355 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5356 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5357 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
5358 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5359 emit_int8(0x72);
5360 emit_int8((unsigned char)(0xC0 | encode));
5361 emit_int8(shift & 0xFF);
5362 }
5363
5364 void Assembler::psllq(XMMRegister dst, int shift) {
5365 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5366 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5367 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
5368 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5369 emit_int8(0x73);
5370 emit_int8((unsigned char)(0xC0 | encode));
5371 emit_int8(shift & 0xFF);
5372 }
5373
5374 void Assembler::psllw(XMMRegister dst, XMMRegister shift) {
5375 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5376 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5377 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5378 emit_int8((unsigned char)0xF1);
5379 emit_int8((unsigned char)(0xC0 | encode));
5380 }
5381
5382 void Assembler::pslld(XMMRegister dst, XMMRegister shift) {
5383 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5384 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5385 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5386 emit_int8((unsigned char)0xF2);
5387 emit_int8((unsigned char)(0xC0 | encode));
5388 }
5389
5390 void Assembler::psllq(XMMRegister dst, XMMRegister shift) {
5391 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5392 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5393 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5394 emit_int8((unsigned char)0xF3);
5395 emit_int8((unsigned char)(0xC0 | encode));
5396 }
5397
5398 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5399 assert(UseAVX > 0, "requires some form of AVX");
5400 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5401 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
5402 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5403 emit_int8(0x71);
5404 emit_int8((unsigned char)(0xC0 | encode));
5405 emit_int8(shift & 0xFF);
5406 }
5407
5408 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5409 assert(UseAVX > 0, "requires some form of AVX");
5410 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5411 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5412 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
5413 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5414 emit_int8(0x72);
5415 emit_int8((unsigned char)(0xC0 | encode));
5416 emit_int8(shift & 0xFF);
5417 }
5418
5419 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5420 assert(UseAVX > 0, "requires some form of AVX");
5421 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5422 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
5423 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5424 emit_int8(0x73);
5425 emit_int8((unsigned char)(0xC0 | encode));
5426 emit_int8(shift & 0xFF);
5427 }
5428
5429 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5430 assert(UseAVX > 0, "requires some form of AVX");
5431 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5432 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5433 emit_int8((unsigned char)0xF1);
5434 emit_int8((unsigned char)(0xC0 | encode));
5435 }
5436
5437 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5438 assert(UseAVX > 0, "requires some form of AVX");
5439 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5440 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5441 emit_int8((unsigned char)0xF2);
5442 emit_int8((unsigned char)(0xC0 | encode));
5443 }
5444
5445 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5446 assert(UseAVX > 0, "requires some form of AVX");
5447 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5448 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5449 emit_int8((unsigned char)0xF3);
5450 emit_int8((unsigned char)(0xC0 | encode));
5451 }
5452
5453 // Shift packed integers logically right by specified number of bits.
5454 void Assembler::psrlw(XMMRegister dst, int shift) {
5455 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5456 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5457 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
5458 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5459 emit_int8(0x71);
5460 emit_int8((unsigned char)(0xC0 | encode));
5461 emit_int8(shift & 0xFF);
5462 }
5463
5464 void Assembler::psrld(XMMRegister dst, int shift) {
5465 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5466 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5467 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
5468 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5469 emit_int8(0x72);
5470 emit_int8((unsigned char)(0xC0 | encode));
5471 emit_int8(shift & 0xFF);
5472 }
5473
5474 void Assembler::psrlq(XMMRegister dst, int shift) {
5475 // Do not confuse it with psrldq SSE2 instruction which
5476 // shifts 128 bit value in xmm register by number of bytes.
5477 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5478 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5479 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
5480 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5481 emit_int8(0x73);
5482 emit_int8((unsigned char)(0xC0 | encode));
5483 emit_int8(shift & 0xFF);
5484 }
5485
5486 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) {
5487 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5488 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5489 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5490 emit_int8((unsigned char)0xD1);
5491 emit_int8((unsigned char)(0xC0 | encode));
5492 }
5493
5494 void Assembler::psrld(XMMRegister dst, XMMRegister shift) {
5495 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5496 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5497 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5498 emit_int8((unsigned char)0xD2);
5499 emit_int8((unsigned char)(0xC0 | encode));
5500 }
5501
5502 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) {
5503 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5504 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5505 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5506 emit_int8((unsigned char)0xD3);
5507 emit_int8((unsigned char)(0xC0 | encode));
5508 }
5509
5510 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5511 assert(UseAVX > 0, "requires some form of AVX");
5512 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5513 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
5514 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5515 emit_int8(0x71);
5516 emit_int8((unsigned char)(0xC0 | encode));
5517 emit_int8(shift & 0xFF);
5518 }
5519
5520 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5521 assert(UseAVX > 0, "requires some form of AVX");
5522 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5523 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
5524 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5525 emit_int8(0x72);
5526 emit_int8((unsigned char)(0xC0 | encode));
5527 emit_int8(shift & 0xFF);
5528 }
5529
5530 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5531 assert(UseAVX > 0, "requires some form of AVX");
5532 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5533 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
5534 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5535 emit_int8(0x73);
5536 emit_int8((unsigned char)(0xC0 | encode));
5537 emit_int8(shift & 0xFF);
5538 }
5539
5540 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5541 assert(UseAVX > 0, "requires some form of AVX");
5542 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5543 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5544 emit_int8((unsigned char)0xD1);
5545 emit_int8((unsigned char)(0xC0 | encode));
5546 }
5547
5548 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5549 assert(UseAVX > 0, "requires some form of AVX");
5550 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5551 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5552 emit_int8((unsigned char)0xD2);
5553 emit_int8((unsigned char)(0xC0 | encode));
5554 }
5555
5556 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5557 assert(UseAVX > 0, "requires some form of AVX");
5558 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5559 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5560 emit_int8((unsigned char)0xD3);
5561 emit_int8((unsigned char)(0xC0 | encode));
5562 }
5563
5564 // Shift packed integers arithmetically right by specified number of bits.
5565 void Assembler::psraw(XMMRegister dst, int shift) {
5566 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5567 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5568 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
5569 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5570 emit_int8(0x71);
5571 emit_int8((unsigned char)(0xC0 | encode));
5572 emit_int8(shift & 0xFF);
5573 }
5574
5575 void Assembler::psrad(XMMRegister dst, int shift) {
5576 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5577 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5578 // XMM4 is for /4 encoding: 66 0F 72 /4 ib
5579 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5580 emit_int8(0x72);
5581 emit_int8((unsigned char)(0xC0 | encode));
5582 emit_int8(shift & 0xFF);
5583 }
5584
5585 void Assembler::psraw(XMMRegister dst, XMMRegister shift) {
5586 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5587 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5588 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5589 emit_int8((unsigned char)0xE1);
5590 emit_int8((unsigned char)(0xC0 | encode));
5591 }
5592
5593 void Assembler::psrad(XMMRegister dst, XMMRegister shift) {
5594 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5595 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5596 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5597 emit_int8((unsigned char)0xE2);
5598 emit_int8((unsigned char)(0xC0 | encode));
5599 }
5600
5601 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5602 assert(UseAVX > 0, "requires some form of AVX");
5603 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5604 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
5605 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5606 emit_int8(0x71);
5607 emit_int8((unsigned char)(0xC0 | encode));
5608 emit_int8(shift & 0xFF);
5609 }
5610
5611 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5612 assert(UseAVX > 0, "requires some form of AVX");
5613 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5614 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
5615 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5616 emit_int8(0x72);
5617 emit_int8((unsigned char)(0xC0 | encode));
5618 emit_int8(shift & 0xFF);
5619 }
5620
5621 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5622 assert(UseAVX > 0, "requires some form of AVX");
5623 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5624 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5625 emit_int8((unsigned char)0xE1);
5626 emit_int8((unsigned char)(0xC0 | encode));
5627 }
5628
5629 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5630 assert(UseAVX > 0, "requires some form of AVX");
5631 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5632 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5633 emit_int8((unsigned char)0xE2);
5634 emit_int8((unsigned char)(0xC0 | encode));
5635 }
5636
5637
5638 // logical operations packed integers
5639 void Assembler::pand(XMMRegister dst, XMMRegister src) {
5640 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5641 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5642 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5643 emit_int8((unsigned char)0xDB);
5644 emit_int8((unsigned char)(0xC0 | encode));
5645 }
5646
5647 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5648 assert(UseAVX > 0, "requires some form of AVX");
5649 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5650 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5651 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5652 emit_int8((unsigned char)0xDB);
5653 emit_int8((unsigned char)(0xC0 | encode));
5654 }
5655
5656 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5657 assert(UseAVX > 0, "requires some form of AVX");
5658 InstructionMark im(this);
5659 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5660 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5661 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5662 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5663 emit_int8((unsigned char)0xDB);
5664 emit_operand(dst, src);
5665 }
5666
5667 void Assembler::pandn(XMMRegister dst, XMMRegister src) {
5668 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5669 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5670 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5671 emit_int8((unsigned char)0xDF);
5672 emit_int8((unsigned char)(0xC0 | encode));
5673 }
5674
5675 void Assembler::por(XMMRegister dst, XMMRegister src) {
5676 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5677 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5678 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5679 emit_int8((unsigned char)0xEB);
5680 emit_int8((unsigned char)(0xC0 | encode));
5681 }
5682
5683 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5684 assert(UseAVX > 0, "requires some form of AVX");
5685 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5686 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5687 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5688 emit_int8((unsigned char)0xEB);
5689 emit_int8((unsigned char)(0xC0 | encode));
5690 }
5691
5692 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5693 assert(UseAVX > 0, "requires some form of AVX");
5694 InstructionMark im(this);
5695 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5696 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5697 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5698 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5699 emit_int8((unsigned char)0xEB);
5700 emit_operand(dst, src);
5701 }
5702
5703 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
5704 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5705 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5706 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5707 emit_int8((unsigned char)0xEF);
5708 emit_int8((unsigned char)(0xC0 | encode));
5709 }
5710
5711 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5712 assert(UseAVX > 0, "requires some form of AVX");
5713 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5714 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5715 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5716 emit_int8((unsigned char)0xEF);
5717 emit_int8((unsigned char)(0xC0 | encode));
5718 }
5719
5720 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5721 assert(UseAVX > 0, "requires some form of AVX");
5722 InstructionMark im(this);
5723 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5724 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5725 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5726 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5727 emit_int8((unsigned char)0xEF);
5728 emit_operand(dst, src);
5729 }
5730
5731
5732 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
5733 assert(VM_Version::supports_avx(), "");
5734 assert(imm8 <= 0x01, "imm8: %u", imm8);
5735 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
5736 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5737 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5738 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5739 emit_int8(0x18);
5740 emit_int8((unsigned char)(0xC0 | encode));
5741 // 0x00 - insert into lower 128 bits
5742 // 0x01 - insert into upper 128 bits
5743 emit_int8(imm8 & 0x01);
5744 }
5745
5746 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
5747 assert(VM_Version::supports_evex(), "");
5748 assert(imm8 <= 0x01, "imm8: %u", imm8);
5749 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5750 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5751 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5752 emit_int8(0x1A);
5753 emit_int8((unsigned char)(0xC0 | encode));
5754 // 0x00 - insert into lower 256 bits
5755 // 0x01 - insert into upper 256 bits
5756 emit_int8(imm8 & 0x01);
5757 }
5758
5759 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
5760 assert(VM_Version::supports_evex(), "");
5761 assert(dst != xnoreg, "sanity");
5762 assert(imm8 <= 0x01, "imm8: %u", imm8);
5763 InstructionMark im(this);
5764 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5765 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5766 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_64bit);
5767 // swap src<->dst for encoding
5768 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5769 emit_int8(0x1A);
5770 emit_operand(dst, src);
5771 // 0x00 - insert into lower 256 bits
5772 // 0x01 - insert into upper 256 bits
5773 emit_int8(imm8 & 0x01);
5774 }
5775
5776 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
5777 assert(VM_Version::supports_evex(), "");
5778 assert(imm8 <= 0x03, "imm8: %u", imm8);
5779 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5780 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5781 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5782 emit_int8(0x18);
5783 emit_int8((unsigned char)(0xC0 | encode));
5784 // 0x00 - insert into q0 128 bits (0..127)
5785 // 0x01 - insert into q1 128 bits (128..255)
5786 // 0x02 - insert into q2 128 bits (256..383)
5787 // 0x03 - insert into q3 128 bits (384..511)
5788 emit_int8(imm8 & 0x03);
5789 }
5790
5791 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
5792 assert(VM_Version::supports_avx(), "");
5793 assert(dst != xnoreg, "sanity");
5794 assert(imm8 <= 0x03, "imm8: %u", imm8);
5795 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5796 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5797 InstructionMark im(this);
5798 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5799 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5800 // swap src<->dst for encoding
5801 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5802 emit_int8(0x18);
5803 emit_operand(dst, src);
5804 // 0x00 - insert into q0 128 bits (0..127)
5805 // 0x01 - insert into q1 128 bits (128..255)
5806 // 0x02 - insert into q2 128 bits (256..383)
5807 // 0x03 - insert into q3 128 bits (384..511)
5808 emit_int8(imm8 & 0x03);
5809 }
5810
5811 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
5812 assert(VM_Version::supports_avx(), "");
5813 assert(dst != xnoreg, "sanity");
5814 assert(imm8 <= 0x01, "imm8: %u", imm8);
5815 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
5816 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5817 InstructionMark im(this);
5818 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5819 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5820 // swap src<->dst for encoding
5821 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5822 emit_int8(0x18);
5823 emit_operand(dst, src);
5824 // 0x00 - insert into lower 128 bits
5825 // 0x01 - insert into upper 128 bits
5826 emit_int8(imm8 & 0x01);
5827 }
5828
5829 void Assembler::vextractf128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
5830 assert(VM_Version::supports_avx(), "");
5831 assert(imm8 <= 0x01, "imm8: %u", imm8);
5832 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
5833 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5834 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5835 emit_int8(0x19);
5836 emit_int8((unsigned char)(0xC0 | encode));
5837 // 0x00 - extract from lower 128 bits
5838 // 0x01 - extract from upper 128 bits
5839 emit_int8(imm8 & 0x01);
5840 }
5841
5842 void Assembler::vextractf128(Address dst, XMMRegister src, uint8_t imm8) {
5843 assert(VM_Version::supports_avx(), "");
5844 assert(src != xnoreg, "sanity");
5845 assert(imm8 <= 0x01, "imm8: %u", imm8);
5846 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
5847 InstructionMark im(this);
5848 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5849 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5850 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5851 emit_int8(0x19);
5852 emit_operand(src, dst);
5853 // 0x00 - extract from lower 128 bits
5854 // 0x01 - extract from upper 128 bits
5855 emit_int8(imm8 & 0x01);
5856 }
5857
5858 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
5859 assert(VM_Version::supports_avx2(), "");
5860 assert(imm8 <= 0x01, "imm8: %u", imm8);
5861 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
5862 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5863 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5864 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5865 emit_int8(0x38);
5866 emit_int8((unsigned char)(0xC0 | encode));
5867 // 0x00 - insert into lower 128 bits
5868 // 0x01 - insert into upper 128 bits
5869 emit_int8(imm8 & 0x01);
5870 }
5871
5872 void Assembler::vinserti64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
5873 assert(VM_Version::supports_evex(), "");
5874 assert(imm8 <= 0x01, "imm8: %u", imm8);
5875 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5876 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5877 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5878 emit_int8(0x38);
5879 emit_int8((unsigned char)(0xC0 | encode));
5880 // 0x00 - insert into lower 256 bits
5881 // 0x01 - insert into upper 256 bits
5882 emit_int8(imm8 & 0x01);
5883 }
5884
5885 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
5886 assert(VM_Version::supports_avx2(), "");
5887 assert(dst != xnoreg, "sanity");
5888 assert(imm8 <= 0x01, "imm8: %u", imm8);
5889 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
5890 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5891 InstructionMark im(this);
5892 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5893 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5894 // swap src<->dst for encoding
5895 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5896 emit_int8(0x38);
5897 emit_operand(dst, src);
5898 // 0x00 - insert into lower 128 bits
5899 // 0x01 - insert into upper 128 bits
5900 emit_int8(imm8 & 0x01);
5901 }
5902
5903 void Assembler::vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
5904 assert(VM_Version::supports_avx(), "");
5905 assert(imm8 <= 0x01, "imm8: %u", imm8);
5906 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
5907 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5908 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5909 emit_int8(0x39);
5910 emit_int8((unsigned char)(0xC0 | encode));
5911 // 0x00 - extract from lower 128 bits
5912 // 0x01 - extract from upper 128 bits
5913 emit_int8(imm8 & 0x01);
5914 }
5915
5916 void Assembler::vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
5917 assert(VM_Version::supports_avx2(), "");
5918 assert(src != xnoreg, "sanity");
5919 assert(imm8 <= 0x01, "imm8: %u", imm8);
5920 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
5921 InstructionMark im(this);
5922 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5923 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5924 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5925 emit_int8(0x39);
5926 emit_operand(src, dst);
5927 // 0x00 - extract from lower 128 bits
5928 // 0x01 - extract from upper 128 bits
5929 emit_int8(imm8 & 0x01);
5930 }
5931
5932 void Assembler::vextracti64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
5933 assert(VM_Version::supports_evex(), "");
5934 assert(imm8 <= 0x01, "imm8: %u", imm8);
5935 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5936 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5937 emit_int8(0x3B);
5938 emit_int8((unsigned char)(0xC0 | encode));
5939 // 0x00 - extract from lower 256 bits
5940 // 0x01 - extract from upper 256 bits
5941 emit_int8(imm8 & 0x01);
5942 }
5943
5944 void Assembler::vextracti64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) {
5945 assert(VM_Version::supports_evex(), "");
5946 assert(imm8 <= 0x03, "imm8: %u", imm8);
5947 InstructionAttr attributes(AVX_512bit, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5948 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5949 emit_int8(0x39);
5950 emit_int8((unsigned char)(0xC0 | encode));
5951 // 0x00 - extract from bits 127:0
5952 // 0x01 - extract from bits 255:128
5953 // 0x02 - extract from bits 383:256
5954 // 0x03 - extract from bits 511:384
5955 emit_int8(imm8 & 0x03);
5956 }
5957
5958 void Assembler::vextractf64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
5959 assert(VM_Version::supports_evex(), "");
5960 assert(imm8 <= 0x01, "imm8: %u", imm8);
5961 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5962 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5963 emit_int8(0x1B);
5964 emit_int8((unsigned char)(0xC0 | encode));
5965 // 0x00 - extract from lower 256 bits
5966 // 0x01 - extract from upper 256 bits
5967 emit_int8(imm8 & 0x01);
5968 }
5969
5970 void Assembler::vextractf64x4(Address dst, XMMRegister src, uint8_t imm8) {
5971 assert(VM_Version::supports_evex(), "");
5972 assert(src != xnoreg, "sanity");
5973 assert(imm8 <= 0x01, "imm8: %u", imm8);
5974 InstructionMark im(this);
5975 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5976 attributes.set_address_attributes(/* tuple_type */ EVEX_T4,/* input_size_in_bits */ EVEX_64bit);
5977 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5978 emit_int8(0x1B);
5979 emit_operand(src, dst);
5980 // 0x00 - extract from lower 256 bits
5981 // 0x01 - extract from upper 256 bits
5982 emit_int8(imm8 & 0x01);
5983 }
5984
5985 void Assembler::vextractf32x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
5986 assert(VM_Version::supports_avx(), "");
5987 assert(imm8 <= 0x03, "imm8: %u", imm8);
5988 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5989 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5990 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5991 emit_int8(0x19);
5992 emit_int8((unsigned char)(0xC0 | encode));
5993 // 0x00 - extract from bits 127:0
5994 // 0x01 - extract from bits 255:128
5995 // 0x02 - extract from bits 383:256
5996 // 0x03 - extract from bits 511:384
5997 emit_int8(imm8 & 0x03);
5998 }
5999
6000 void Assembler::vextractf32x4(Address dst, XMMRegister src, uint8_t imm8) {
6001 assert(VM_Version::supports_evex(), "");
6002 assert(src != xnoreg, "sanity");
6003 assert(imm8 <= 0x03, "imm8: %u", imm8);
6004 InstructionMark im(this);
6005 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6006 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6007 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6008 emit_int8(0x19);
6009 emit_operand(src, dst);
6010 // 0x00 - extract from bits 127:0
6011 // 0x01 - extract from bits 255:128
6012 // 0x02 - extract from bits 383:256
6013 // 0x03 - extract from bits 511:384
6014 emit_int8(imm8 & 0x03);
6015 }
6016
6017 void Assembler::vextractf64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6018 assert(VM_Version::supports_evex(), "");
6019 assert(imm8 <= 0x03, "imm8: %u", imm8);
6020 InstructionAttr attributes(AVX_512bit, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6021 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6022 emit_int8(0x19);
6023 emit_int8((unsigned char)(0xC0 | encode));
6024 // 0x00 - extract from bits 127:0
6025 // 0x01 - extract from bits 255:128
6026 // 0x02 - extract from bits 383:256
6027 // 0x03 - extract from bits 511:384
6028 emit_int8(imm8 & 0x03);
6029 }
6030
6031 // duplicate 4-bytes integer data from src into 8 locations in dest
6032 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src) {
6033 assert(VM_Version::supports_avx2(), "");
6034 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6035 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6036 emit_int8(0x58);
6037 emit_int8((unsigned char)(0xC0 | encode));
6038 }
6039
6040 // duplicate 2-bytes integer data from src into 16 locations in dest
6041 void Assembler::vpbroadcastw(XMMRegister dst, XMMRegister src) {
6042 assert(VM_Version::supports_avx2(), "");
6043 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6044 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6045 emit_int8(0x79);
6046 emit_int8((unsigned char)(0xC0 | encode));
6047 }
6048
6049 // duplicate 1-byte integer data from src into 16||32|64 locations in dest : requires AVX512BW and AVX512VL
6050 void Assembler::evpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len) {
6051 assert(VM_Version::supports_evex(), "");
6052 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6053 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6054 emit_int8(0x78);
6055 emit_int8((unsigned char)(0xC0 | encode));
6056 }
6057
6058 void Assembler::evpbroadcastb(XMMRegister dst, Address src, int vector_len) {
6059 assert(VM_Version::supports_evex(), "");
6060 assert(dst != xnoreg, "sanity");
6061 InstructionMark im(this);
6062 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6063 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
6064 // swap src<->dst for encoding
6065 vex_prefix(src, dst->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6066 emit_int8(0x78);
6067 emit_operand(dst, src);
6068 }
6069
6070 // duplicate 2-byte integer data from src into 8|16||32 locations in dest : requires AVX512BW and AVX512VL
6071 void Assembler::evpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len) {
6072 assert(VM_Version::supports_evex(), "");
6073 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6074 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6075 emit_int8(0x79);
6076 emit_int8((unsigned char)(0xC0 | encode));
6077 }
6078
6079 void Assembler::evpbroadcastw(XMMRegister dst, Address src, int vector_len) {
6080 assert(VM_Version::supports_evex(), "");
6081 assert(dst != xnoreg, "sanity");
6082 InstructionMark im(this);
6083 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6084 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
6085 // swap src<->dst for encoding
6086 vex_prefix(src, dst->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6087 emit_int8(0x79);
6088 emit_operand(dst, src);
6089 }
6090
6091 // duplicate 4-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
6092 void Assembler::evpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len) {
6093 assert(VM_Version::supports_evex(), "");
6094 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6095 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6096 emit_int8(0x58);
6097 emit_int8((unsigned char)(0xC0 | encode));
6098 }
6099
6100 void Assembler::evpbroadcastd(XMMRegister dst, Address src, int vector_len) {
6101 assert(VM_Version::supports_evex(), "");
6102 assert(dst != xnoreg, "sanity");
6103 InstructionMark im(this);
6104 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6105 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
6106 // swap src<->dst for encoding
6107 vex_prefix(src, dst->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6108 emit_int8(0x58);
6109 emit_operand(dst, src);
6110 }
6111
6112 // duplicate 8-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
6113 void Assembler::evpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len) {
6114 assert(VM_Version::supports_evex(), "");
6115 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6116 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6117 emit_int8(0x59);
6118 emit_int8((unsigned char)(0xC0 | encode));
6119 }
6120
6121 void Assembler::evpbroadcastq(XMMRegister dst, Address src, int vector_len) {
6122 assert(VM_Version::supports_evex(), "");
6123 assert(dst != xnoreg, "sanity");
6124 InstructionMark im(this);
6125 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6126 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6127 // swap src<->dst for encoding
6128 vex_prefix(src, dst->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6129 emit_int8(0x59);
6130 emit_operand(dst, src);
6131 }
6132
6133 // duplicate single precision fp from src into 4|8|16 locations in dest : requires AVX512VL
6134 void Assembler::evpbroadcastss(XMMRegister dst, XMMRegister src, int vector_len) {
6135 assert(VM_Version::supports_evex(), "");
6136 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6137 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6138 emit_int8(0x18);
6139 emit_int8((unsigned char)(0xC0 | encode));
6140 }
6141
6142 void Assembler::evpbroadcastss(XMMRegister dst, Address src, int vector_len) {
6143 assert(VM_Version::supports_evex(), "");
6144 assert(dst != xnoreg, "sanity");
6145 InstructionMark im(this);
6146 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6147 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
6148 // swap src<->dst for encoding
6149 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6150 emit_int8(0x18);
6151 emit_operand(dst, src);
6152 }
6153
6154 // duplicate double precision fp from src into 2|4|8 locations in dest : requires AVX512VL
6155 void Assembler::evpbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len) {
6156 assert(VM_Version::supports_evex(), "");
6157 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6158 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6159 emit_int8(0x19);
6160 emit_int8((unsigned char)(0xC0 | encode));
6161 }
6162
6163 void Assembler::evpbroadcastsd(XMMRegister dst, Address src, int vector_len) {
6164 assert(VM_Version::supports_evex(), "");
6165 assert(dst != xnoreg, "sanity");
6166 InstructionMark im(this);
6167 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6168 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6169 // swap src<->dst for encoding
6170 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6171 emit_int8(0x19);
6172 emit_operand(dst, src);
6173 }
6174
6175 // duplicate 1-byte integer data from src into 16||32|64 locations in dest : requires AVX512BW and AVX512VL
6176 void Assembler::evpbroadcastb(XMMRegister dst, Register src, int vector_len) {
6177 assert(VM_Version::supports_evex(), "");
6178 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6179 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6180 if (attributes.is_evex_instruction()) {
6181 emit_int8(0x7A);
6182 } else {
6183 emit_int8(0x78);
6184 }
6185 emit_int8((unsigned char)(0xC0 | encode));
6186 }
6187
6188 // duplicate 2-byte integer data from src into 8|16||32 locations in dest : requires AVX512BW and AVX512VL
6189 void Assembler::evpbroadcastw(XMMRegister dst, Register src, int vector_len) {
6190 assert(VM_Version::supports_evex(), "");
6191 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6192 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6193 if (attributes.is_evex_instruction()) {
6194 emit_int8(0x7B);
6195 } else {
6196 emit_int8(0x79);
6197 }
6198 emit_int8((unsigned char)(0xC0 | encode));
6199 }
6200
6201 // duplicate 4-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
6202 void Assembler::evpbroadcastd(XMMRegister dst, Register src, int vector_len) {
6203 assert(VM_Version::supports_evex(), "");
6204 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6205 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6206 if (attributes.is_evex_instruction()) {
6207 emit_int8(0x7C);
6208 } else {
6209 emit_int8(0x58);
6210 }
6211 emit_int8((unsigned char)(0xC0 | encode));
6212 }
6213
6214 // duplicate 8-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
6215 void Assembler::evpbroadcastq(XMMRegister dst, Register src, int vector_len) {
6216 assert(VM_Version::supports_evex(), "");
6217 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6218 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6219 if (attributes.is_evex_instruction()) {
6220 emit_int8(0x7C);
6221 } else {
6222 emit_int8(0x59);
6223 }
6224 emit_int8((unsigned char)(0xC0 | encode));
6225 }
6226
6227 // Carry-Less Multiplication Quadword
6228 void Assembler::pclmulqdq(XMMRegister dst, XMMRegister src, int mask) {
6229 assert(VM_Version::supports_clmul(), "");
6230 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6231 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6232 emit_int8(0x44);
6233 emit_int8((unsigned char)(0xC0 | encode));
6234 emit_int8((unsigned char)mask);
6235 }
6236
6237 // Carry-Less Multiplication Quadword
6238 void Assembler::vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask) {
6239 assert(VM_Version::supports_avx() && VM_Version::supports_clmul(), "");
6240 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6241 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
6242 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6243 emit_int8(0x44);
6244 emit_int8((unsigned char)(0xC0 | encode));
6245 emit_int8((unsigned char)mask);
6246 }
6247
6248 void Assembler::vzeroupper() {
6249 assert(VM_Version::supports_avx(), "");
6250 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6251 (void)vex_prefix_and_encode(0, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6252 emit_int8(0x77);
6253 }
6254
6255
6256 #ifndef _LP64
6257 // 32bit only pieces of the assembler
6258
6259 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
6260 // NO PREFIX AS NEVER 64BIT
6261 InstructionMark im(this);
6262 emit_int8((unsigned char)0x81);
6263 emit_int8((unsigned char)(0xF8 | src1->encoding()));
6264 emit_data(imm32, rspec, 0);
6265 }
6266
6267 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
6268 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
6269 InstructionMark im(this);
6270 emit_int8((unsigned char)0x81);
6271 emit_operand(rdi, src1);
6272 emit_data(imm32, rspec, 0);
6273 }
6274
6275 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax,
6276 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded
6277 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise.
6278 void Assembler::cmpxchg8(Address adr) {
6279 InstructionMark im(this);
6280 emit_int8(0x0F);
6281 emit_int8((unsigned char)0xC7);
6282 emit_operand(rcx, adr);
6283 }
6284
6285 void Assembler::decl(Register dst) {
6286 // Don't use it directly. Use MacroAssembler::decrementl() instead.
6287 emit_int8(0x48 | dst->encoding());
6288 }
6289
6290 #endif // _LP64
6291
6292 // 64bit typically doesn't use the x87 but needs to for the trig funcs
6293
6294 void Assembler::fabs() {
6295 emit_int8((unsigned char)0xD9);
6296 emit_int8((unsigned char)0xE1);
6297 }
6298
6299 void Assembler::fadd(int i) {
6300 emit_farith(0xD8, 0xC0, i);
6301 }
6302
6303 void Assembler::fadd_d(Address src) {
6304 InstructionMark im(this);
6305 emit_int8((unsigned char)0xDC);
6306 emit_operand32(rax, src);
6307 }
6308
6309 void Assembler::fadd_s(Address src) {
6310 InstructionMark im(this);
6311 emit_int8((unsigned char)0xD8);
6312 emit_operand32(rax, src);
6313 }
6314
6315 void Assembler::fadda(int i) {
6316 emit_farith(0xDC, 0xC0, i);
6317 }
6318
6319 void Assembler::faddp(int i) {
6320 emit_farith(0xDE, 0xC0, i);
6321 }
6322
6323 void Assembler::fchs() {
6324 emit_int8((unsigned char)0xD9);
6325 emit_int8((unsigned char)0xE0);
6326 }
6327
6328 void Assembler::fcom(int i) {
6329 emit_farith(0xD8, 0xD0, i);
6330 }
6331
6332 void Assembler::fcomp(int i) {
6333 emit_farith(0xD8, 0xD8, i);
6334 }
6335
6336 void Assembler::fcomp_d(Address src) {
6337 InstructionMark im(this);
6338 emit_int8((unsigned char)0xDC);
6339 emit_operand32(rbx, src);
6340 }
6341
6342 void Assembler::fcomp_s(Address src) {
6343 InstructionMark im(this);
6344 emit_int8((unsigned char)0xD8);
6345 emit_operand32(rbx, src);
6346 }
6347
6348 void Assembler::fcompp() {
6349 emit_int8((unsigned char)0xDE);
6350 emit_int8((unsigned char)0xD9);
6351 }
6352
6353 void Assembler::fcos() {
6354 emit_int8((unsigned char)0xD9);
6355 emit_int8((unsigned char)0xFF);
6356 }
6357
6358 void Assembler::fdecstp() {
6359 emit_int8((unsigned char)0xD9);
6360 emit_int8((unsigned char)0xF6);
6361 }
6362
6363 void Assembler::fdiv(int i) {
6364 emit_farith(0xD8, 0xF0, i);
6365 }
6366
6367 void Assembler::fdiv_d(Address src) {
6368 InstructionMark im(this);
6369 emit_int8((unsigned char)0xDC);
6370 emit_operand32(rsi, src);
6371 }
6372
6373 void Assembler::fdiv_s(Address src) {
6374 InstructionMark im(this);
6375 emit_int8((unsigned char)0xD8);
6376 emit_operand32(rsi, src);
6377 }
6378
6379 void Assembler::fdiva(int i) {
6380 emit_farith(0xDC, 0xF8, i);
6381 }
6382
6383 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994)
6384 // is erroneous for some of the floating-point instructions below.
6385
6386 void Assembler::fdivp(int i) {
6387 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong)
6388 }
6389
6390 void Assembler::fdivr(int i) {
6391 emit_farith(0xD8, 0xF8, i);
6392 }
6393
6394 void Assembler::fdivr_d(Address src) {
6395 InstructionMark im(this);
6396 emit_int8((unsigned char)0xDC);
6397 emit_operand32(rdi, src);
6398 }
6399
6400 void Assembler::fdivr_s(Address src) {
6401 InstructionMark im(this);
6402 emit_int8((unsigned char)0xD8);
6403 emit_operand32(rdi, src);
6404 }
6405
6406 void Assembler::fdivra(int i) {
6407 emit_farith(0xDC, 0xF0, i);
6408 }
6409
6410 void Assembler::fdivrp(int i) {
6411 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong)
6412 }
6413
6414 void Assembler::ffree(int i) {
6415 emit_farith(0xDD, 0xC0, i);
6416 }
6417
6418 void Assembler::fild_d(Address adr) {
6419 InstructionMark im(this);
6420 emit_int8((unsigned char)0xDF);
6421 emit_operand32(rbp, adr);
6422 }
6423
6424 void Assembler::fild_s(Address adr) {
6425 InstructionMark im(this);
6426 emit_int8((unsigned char)0xDB);
6427 emit_operand32(rax, adr);
6428 }
6429
6430 void Assembler::fincstp() {
6431 emit_int8((unsigned char)0xD9);
6432 emit_int8((unsigned char)0xF7);
6433 }
6434
6435 void Assembler::finit() {
6436 emit_int8((unsigned char)0x9B);
6437 emit_int8((unsigned char)0xDB);
6438 emit_int8((unsigned char)0xE3);
6439 }
6440
6441 void Assembler::fist_s(Address adr) {
6442 InstructionMark im(this);
6443 emit_int8((unsigned char)0xDB);
6444 emit_operand32(rdx, adr);
6445 }
6446
6447 void Assembler::fistp_d(Address adr) {
6448 InstructionMark im(this);
6449 emit_int8((unsigned char)0xDF);
6450 emit_operand32(rdi, adr);
6451 }
6452
6453 void Assembler::fistp_s(Address adr) {
6454 InstructionMark im(this);
6455 emit_int8((unsigned char)0xDB);
6456 emit_operand32(rbx, adr);
6457 }
6458
6459 void Assembler::fld1() {
6460 emit_int8((unsigned char)0xD9);
6461 emit_int8((unsigned char)0xE8);
6462 }
6463
6464 void Assembler::fld_d(Address adr) {
6465 InstructionMark im(this);
6466 emit_int8((unsigned char)0xDD);
6467 emit_operand32(rax, adr);
6468 }
6469
6470 void Assembler::fld_s(Address adr) {
6471 InstructionMark im(this);
6472 emit_int8((unsigned char)0xD9);
6473 emit_operand32(rax, adr);
6474 }
6475
6476
6477 void Assembler::fld_s(int index) {
6478 emit_farith(0xD9, 0xC0, index);
6479 }
6480
6481 void Assembler::fld_x(Address adr) {
6482 InstructionMark im(this);
6483 emit_int8((unsigned char)0xDB);
6484 emit_operand32(rbp, adr);
6485 }
6486
6487 void Assembler::fldcw(Address src) {
6488 InstructionMark im(this);
6489 emit_int8((unsigned char)0xD9);
6490 emit_operand32(rbp, src);
6491 }
6492
6493 void Assembler::fldenv(Address src) {
6494 InstructionMark im(this);
6495 emit_int8((unsigned char)0xD9);
6496 emit_operand32(rsp, src);
6497 }
6498
6499 void Assembler::fldlg2() {
6500 emit_int8((unsigned char)0xD9);
6501 emit_int8((unsigned char)0xEC);
6502 }
6503
6504 void Assembler::fldln2() {
6505 emit_int8((unsigned char)0xD9);
6506 emit_int8((unsigned char)0xED);
6507 }
6508
6509 void Assembler::fldz() {
6510 emit_int8((unsigned char)0xD9);
6511 emit_int8((unsigned char)0xEE);
6512 }
6513
6514 void Assembler::flog() {
6515 fldln2();
6516 fxch();
6517 fyl2x();
6518 }
6519
6520 void Assembler::flog10() {
6521 fldlg2();
6522 fxch();
6523 fyl2x();
6524 }
6525
6526 void Assembler::fmul(int i) {
6527 emit_farith(0xD8, 0xC8, i);
6528 }
6529
6530 void Assembler::fmul_d(Address src) {
6531 InstructionMark im(this);
6532 emit_int8((unsigned char)0xDC);
6533 emit_operand32(rcx, src);
6534 }
6535
6536 void Assembler::fmul_s(Address src) {
6537 InstructionMark im(this);
6538 emit_int8((unsigned char)0xD8);
6539 emit_operand32(rcx, src);
6540 }
6541
6542 void Assembler::fmula(int i) {
6543 emit_farith(0xDC, 0xC8, i);
6544 }
6545
6546 void Assembler::fmulp(int i) {
6547 emit_farith(0xDE, 0xC8, i);
6548 }
6549
6550 void Assembler::fnsave(Address dst) {
6551 InstructionMark im(this);
6552 emit_int8((unsigned char)0xDD);
6553 emit_operand32(rsi, dst);
6554 }
6555
6556 void Assembler::fnstcw(Address src) {
6557 InstructionMark im(this);
6558 emit_int8((unsigned char)0x9B);
6559 emit_int8((unsigned char)0xD9);
6560 emit_operand32(rdi, src);
6561 }
6562
6563 void Assembler::fnstsw_ax() {
6564 emit_int8((unsigned char)0xDF);
6565 emit_int8((unsigned char)0xE0);
6566 }
6567
6568 void Assembler::fprem() {
6569 emit_int8((unsigned char)0xD9);
6570 emit_int8((unsigned char)0xF8);
6571 }
6572
6573 void Assembler::fprem1() {
6574 emit_int8((unsigned char)0xD9);
6575 emit_int8((unsigned char)0xF5);
6576 }
6577
6578 void Assembler::frstor(Address src) {
6579 InstructionMark im(this);
6580 emit_int8((unsigned char)0xDD);
6581 emit_operand32(rsp, src);
6582 }
6583
6584 void Assembler::fsin() {
6585 emit_int8((unsigned char)0xD9);
6586 emit_int8((unsigned char)0xFE);
6587 }
6588
6589 void Assembler::fsqrt() {
6590 emit_int8((unsigned char)0xD9);
6591 emit_int8((unsigned char)0xFA);
6592 }
6593
6594 void Assembler::fst_d(Address adr) {
6595 InstructionMark im(this);
6596 emit_int8((unsigned char)0xDD);
6597 emit_operand32(rdx, adr);
6598 }
6599
6600 void Assembler::fst_s(Address adr) {
6601 InstructionMark im(this);
6602 emit_int8((unsigned char)0xD9);
6603 emit_operand32(rdx, adr);
6604 }
6605
6606 void Assembler::fstp_d(Address adr) {
6607 InstructionMark im(this);
6608 emit_int8((unsigned char)0xDD);
6609 emit_operand32(rbx, adr);
6610 }
6611
6612 void Assembler::fstp_d(int index) {
6613 emit_farith(0xDD, 0xD8, index);
6614 }
6615
6616 void Assembler::fstp_s(Address adr) {
6617 InstructionMark im(this);
6618 emit_int8((unsigned char)0xD9);
6619 emit_operand32(rbx, adr);
6620 }
6621
6622 void Assembler::fstp_x(Address adr) {
6623 InstructionMark im(this);
6624 emit_int8((unsigned char)0xDB);
6625 emit_operand32(rdi, adr);
6626 }
6627
6628 void Assembler::fsub(int i) {
6629 emit_farith(0xD8, 0xE0, i);
6630 }
6631
6632 void Assembler::fsub_d(Address src) {
6633 InstructionMark im(this);
6634 emit_int8((unsigned char)0xDC);
6635 emit_operand32(rsp, src);
6636 }
6637
6638 void Assembler::fsub_s(Address src) {
6639 InstructionMark im(this);
6640 emit_int8((unsigned char)0xD8);
6641 emit_operand32(rsp, src);
6642 }
6643
6644 void Assembler::fsuba(int i) {
6645 emit_farith(0xDC, 0xE8, i);
6646 }
6647
6648 void Assembler::fsubp(int i) {
6649 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong)
6650 }
6651
6652 void Assembler::fsubr(int i) {
6653 emit_farith(0xD8, 0xE8, i);
6654 }
6655
6656 void Assembler::fsubr_d(Address src) {
6657 InstructionMark im(this);
6658 emit_int8((unsigned char)0xDC);
6659 emit_operand32(rbp, src);
6660 }
6661
6662 void Assembler::fsubr_s(Address src) {
6663 InstructionMark im(this);
6664 emit_int8((unsigned char)0xD8);
6665 emit_operand32(rbp, src);
6666 }
6667
6668 void Assembler::fsubra(int i) {
6669 emit_farith(0xDC, 0xE0, i);
6670 }
6671
6672 void Assembler::fsubrp(int i) {
6673 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong)
6674 }
6675
6676 void Assembler::ftan() {
6677 emit_int8((unsigned char)0xD9);
6678 emit_int8((unsigned char)0xF2);
6679 emit_int8((unsigned char)0xDD);
6680 emit_int8((unsigned char)0xD8);
6681 }
6682
6683 void Assembler::ftst() {
6684 emit_int8((unsigned char)0xD9);
6685 emit_int8((unsigned char)0xE4);
6686 }
6687
6688 void Assembler::fucomi(int i) {
6689 // make sure the instruction is supported (introduced for P6, together with cmov)
6690 guarantee(VM_Version::supports_cmov(), "illegal instruction");
6691 emit_farith(0xDB, 0xE8, i);
6692 }
6693
6694 void Assembler::fucomip(int i) {
6695 // make sure the instruction is supported (introduced for P6, together with cmov)
6696 guarantee(VM_Version::supports_cmov(), "illegal instruction");
6697 emit_farith(0xDF, 0xE8, i);
6698 }
6699
6700 void Assembler::fwait() {
6701 emit_int8((unsigned char)0x9B);
6702 }
6703
6704 void Assembler::fxch(int i) {
6705 emit_farith(0xD9, 0xC8, i);
6706 }
6707
6708 void Assembler::fyl2x() {
6709 emit_int8((unsigned char)0xD9);
6710 emit_int8((unsigned char)0xF1);
6711 }
6712
6713 void Assembler::frndint() {
6714 emit_int8((unsigned char)0xD9);
6715 emit_int8((unsigned char)0xFC);
6716 }
6717
6718 void Assembler::f2xm1() {
6719 emit_int8((unsigned char)0xD9);
6720 emit_int8((unsigned char)0xF0);
6721 }
6722
6723 void Assembler::fldl2e() {
6724 emit_int8((unsigned char)0xD9);
6725 emit_int8((unsigned char)0xEA);
6726 }
6727
6728 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding.
6729 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 };
6730 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding.
6731 static int simd_opc[4] = { 0, 0, 0x38, 0x3A };
6732
6733 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding.
6734 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
6735 if (pre > 0) {
6736 emit_int8(simd_pre[pre]);
6737 }
6738 if (rex_w) {
6739 prefixq(adr, xreg);
6740 } else {
6741 prefix(adr, xreg);
6742 }
6743 if (opc > 0) {
6744 emit_int8(0x0F);
6745 int opc2 = simd_opc[opc];
6746 if (opc2 > 0) {
6747 emit_int8(opc2);
6748 }
6749 }
6750 }
6751
6752 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
6753 if (pre > 0) {
6754 emit_int8(simd_pre[pre]);
6755 }
6756 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) : prefix_and_encode(dst_enc, src_enc);
6757 if (opc > 0) {
6758 emit_int8(0x0F);
6759 int opc2 = simd_opc[opc];
6760 if (opc2 > 0) {
6761 emit_int8(opc2);
6762 }
6763 }
6764 return encode;
6765 }
6766
6767
6768 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc) {
6769 int vector_len = _attributes->get_vector_len();
6770 bool vex_w = _attributes->is_rex_vex_w();
6771 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) {
6772 prefix(VEX_3bytes);
6773
6774 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0);
6775 byte1 = (~byte1) & 0xE0;
6776 byte1 |= opc;
6777 emit_int8(byte1);
6778
6779 int byte2 = ((~nds_enc) & 0xf) << 3;
6780 byte2 |= (vex_w ? VEX_W : 0) | ((vector_len > 0) ? 4 : 0) | pre;
6781 emit_int8(byte2);
6782 } else {
6783 prefix(VEX_2bytes);
6784
6785 int byte1 = vex_r ? VEX_R : 0;
6786 byte1 = (~byte1) & 0x80;
6787 byte1 |= ((~nds_enc) & 0xf) << 3;
6788 byte1 |= ((vector_len > 0 ) ? 4 : 0) | pre;
6789 emit_int8(byte1);
6790 }
6791 }
6792
6793 // This is a 4 byte encoding
6794 void Assembler::evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_r, bool evex_v, int nds_enc, VexSimdPrefix pre, VexOpcode opc){
6795 // EVEX 0x62 prefix
6796 prefix(EVEX_4bytes);
6797 bool vex_w = _attributes->is_rex_vex_w();
6798 int evex_encoding = (vex_w ? VEX_W : 0);
6799 // EVEX.b is not currently used for broadcast of single element or data rounding modes
6800 _attributes->set_evex_encoding(evex_encoding);
6801
6802 // P0: byte 2, initialized to RXBR`00mm
6803 // instead of not'd
6804 int byte2 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0) | (evex_r ? EVEX_Rb : 0);
6805 byte2 = (~byte2) & 0xF0;
6806 // confine opc opcode extensions in mm bits to lower two bits
6807 // of form {0F, 0F_38, 0F_3A}
6808 byte2 |= opc;
6809 emit_int8(byte2);
6810
6811 // P1: byte 3 as Wvvvv1pp
6812 int byte3 = ((~nds_enc) & 0xf) << 3;
6813 // p[10] is always 1
6814 byte3 |= EVEX_F;
6815 byte3 |= (vex_w & 1) << 7;
6816 // confine pre opcode extensions in pp bits to lower two bits
6817 // of form {66, F3, F2}
6818 byte3 |= pre;
6819 emit_int8(byte3);
6820
6821 // P2: byte 4 as zL'Lbv'aaa
6822 int byte4 = (_attributes->is_no_reg_mask()) ? 0 : 1; // kregs are implemented in the low 3 bits as aaa (hard code k1, it will be initialized for now)
6823 // EVEX.v` for extending EVEX.vvvv or VIDX
6824 byte4 |= (evex_v ? 0: EVEX_V);
6825 // third EXEC.b for broadcast actions
6826 byte4 |= (_attributes->is_extended_context() ? EVEX_Rb : 0);
6827 // fourth EVEX.L'L for vector length : 0 is 128, 1 is 256, 2 is 512, currently we do not support 1024
6828 byte4 |= ((_attributes->get_vector_len())& 0x3) << 5;
6829 // last is EVEX.z for zero/merge actions
6830 byte4 |= (_attributes->is_clear_context() ? EVEX_Z : 0);
6831 emit_int8(byte4);
6832 }
6833
6834 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) {
6835 bool vex_r = ((xreg_enc & 8) == 8) ? 1 : 0;
6836 bool vex_b = adr.base_needs_rex();
6837 bool vex_x = adr.index_needs_rex();
6838 set_attributes(attributes);
6839 attributes->set_current_assembler(this);
6840
6841 // if vector length is turned off, revert to AVX for vectors smaller than 512-bit
6842 if (UseAVX > 2 && _legacy_mode_vl && attributes->uses_vl()) {
6843 switch (attributes->get_vector_len()) {
6844 case AVX_128bit:
6845 case AVX_256bit:
6846 attributes->set_is_legacy_mode();
6847 break;
6848 }
6849 }
6850
6851 // For pure EVEX check and see if this instruction
6852 // is allowed in legacy mode and has resources which will
6853 // fit in it. Pure EVEX instructions will use set_is_evex_instruction in their definition,
6854 // else that field is set when we encode to EVEX
6855 if (UseAVX > 2 && !attributes->is_legacy_mode() &&
6856 !_is_managed && !attributes->is_evex_instruction()) {
6857 if (!_legacy_mode_vl && attributes->get_vector_len() != AVX_512bit) {
6858 bool check_register_bank = NOT_IA32(true) IA32_ONLY(false);
6859 if (check_register_bank) {
6860 // check nds_enc and xreg_enc for upper bank usage
6861 if (nds_enc < 16 && xreg_enc < 16) {
6862 attributes->set_is_legacy_mode();
6863 }
6864 } else {
6865 attributes->set_is_legacy_mode();
6866 }
6867 }
6868 }
6869
6870 _is_managed = false;
6871 if (UseAVX > 2 && !attributes->is_legacy_mode())
6872 {
6873 bool evex_r = (xreg_enc >= 16);
6874 bool evex_v = (nds_enc >= 16);
6875 attributes->set_is_evex_instruction();
6876 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc);
6877 } else {
6878 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc);
6879 }
6880 }
6881
6882 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) {
6883 bool vex_r = ((dst_enc & 8) == 8) ? 1 : 0;
6884 bool vex_b = ((src_enc & 8) == 8) ? 1 : 0;
6885 bool vex_x = false;
6886 set_attributes(attributes);
6887 attributes->set_current_assembler(this);
6888 bool check_register_bank = NOT_IA32(true) IA32_ONLY(false);
6889
6890 // if vector length is turned off, revert to AVX for vectors smaller than 512-bit
6891 if (UseAVX > 2 && _legacy_mode_vl && attributes->uses_vl()) {
6892 switch (attributes->get_vector_len()) {
6893 case AVX_128bit:
6894 case AVX_256bit:
6895 if (check_register_bank) {
6896 if (dst_enc >= 16 || nds_enc >= 16 || src_enc >= 16) {
6897 // up propagate arithmetic instructions to meet RA requirements
6898 attributes->set_vector_len(AVX_512bit);
6899 } else {
6900 attributes->set_is_legacy_mode();
6901 }
6902 } else {
6903 attributes->set_is_legacy_mode();
6904 }
6905 break;
6906 }
6907 }
6908
6909 // For pure EVEX check and see if this instruction
6910 // is allowed in legacy mode and has resources which will
6911 // fit in it. Pure EVEX instructions will use set_is_evex_instruction in their definition,
6912 // else that field is set when we encode to EVEX
6913 if (UseAVX > 2 && !attributes->is_legacy_mode() &&
6914 !_is_managed && !attributes->is_evex_instruction()) {
6915 if (!_legacy_mode_vl && attributes->get_vector_len() != AVX_512bit) {
6916 if (check_register_bank) {
6917 // check dst_enc, nds_enc and src_enc for upper bank usage
6918 if (dst_enc < 16 && nds_enc < 16 && src_enc < 16) {
6919 attributes->set_is_legacy_mode();
6920 }
6921 } else {
6922 attributes->set_is_legacy_mode();
6923 }
6924 }
6925 }
6926
6927 _is_managed = false;
6928 if (UseAVX > 2 && !attributes->is_legacy_mode())
6929 {
6930 bool evex_r = (dst_enc >= 16);
6931 bool evex_v = (nds_enc >= 16);
6932 // can use vex_x as bank extender on rm encoding
6933 vex_x = (src_enc >= 16);
6934 attributes->set_is_evex_instruction();
6935 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc);
6936 } else {
6937 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc);
6938 }
6939
6940 // return modrm byte components for operands
6941 return (((dst_enc & 7) << 3) | (src_enc & 7));
6942 }
6943
6944
6945 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre,
6946 VexOpcode opc, InstructionAttr *attributes) {
6947 if (UseAVX > 0) {
6948 int xreg_enc = xreg->encoding();
6949 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
6950 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, attributes);
6951 } else {
6952 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding");
6953 rex_prefix(adr, xreg, pre, opc, attributes->is_rex_vex_w());
6954 }
6955 }
6956
6957 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre,
6958 VexOpcode opc, InstructionAttr *attributes) {
6959 int dst_enc = dst->encoding();
6960 int src_enc = src->encoding();
6961 if (UseAVX > 0) {
6962 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
6963 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, attributes);
6964 } else {
6965 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding");
6966 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, attributes->is_rex_vex_w());
6967 }
6968 }
6969
6970 void Assembler::cmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) {
6971 assert(VM_Version::supports_avx(), "");
6972 assert(!VM_Version::supports_evex(), "");
6973 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6974 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6975 emit_int8((unsigned char)0xC2);
6976 emit_int8((unsigned char)(0xC0 | encode));
6977 emit_int8((unsigned char)(0xF & cop));
6978 }
6979
6980 void Assembler::vpblendd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) {
6981 assert(VM_Version::supports_avx(), "");
6982 assert(!VM_Version::supports_evex(), "");
6983 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6984 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
6985 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6986 emit_int8((unsigned char)0x4B);
6987 emit_int8((unsigned char)(0xC0 | encode));
6988 int src2_enc = src2->encoding();
6989 emit_int8((unsigned char)(0xF0 & src2_enc<<4));
6990 }
6991
6992
6993 #ifndef _LP64
6994
6995 void Assembler::incl(Register dst) {
6996 // Don't use it directly. Use MacroAssembler::incrementl() instead.
6997 emit_int8(0x40 | dst->encoding());
6998 }
6999
7000 void Assembler::lea(Register dst, Address src) {
7001 leal(dst, src);
7002 }
7003
7004 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
7005 InstructionMark im(this);
7006 emit_int8((unsigned char)0xC7);
7007 emit_operand(rax, dst);
7008 emit_data((int)imm32, rspec, 0);
7009 }
7010
7011 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
7012 InstructionMark im(this);
7013 int encode = prefix_and_encode(dst->encoding());
7014 emit_int8((unsigned char)(0xB8 | encode));
7015 emit_data((int)imm32, rspec, 0);
7016 }
7017
7018 void Assembler::popa() { // 32bit
7019 emit_int8(0x61);
7020 }
7021
7022 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
7023 InstructionMark im(this);
7024 emit_int8(0x68);
7025 emit_data(imm32, rspec, 0);
7026 }
7027
7028 void Assembler::pusha() { // 32bit
7029 emit_int8(0x60);
7030 }
7031
7032 void Assembler::set_byte_if_not_zero(Register dst) {
7033 emit_int8(0x0F);
7034 emit_int8((unsigned char)0x95);
7035 emit_int8((unsigned char)(0xE0 | dst->encoding()));
7036 }
7037
7038 void Assembler::shldl(Register dst, Register src) {
7039 emit_int8(0x0F);
7040 emit_int8((unsigned char)0xA5);
7041 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
7042 }
7043
7044 // 0F A4 / r ib
7045 void Assembler::shldl(Register dst, Register src, int8_t imm8) {
7046 emit_int8(0x0F);
7047 emit_int8((unsigned char)0xA4);
7048 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
7049 emit_int8(imm8);
7050 }
7051
7052 void Assembler::shrdl(Register dst, Register src) {
7053 emit_int8(0x0F);
7054 emit_int8((unsigned char)0xAD);
7055 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
7056 }
7057
7058 #else // LP64
7059
7060 void Assembler::set_byte_if_not_zero(Register dst) {
7061 int enc = prefix_and_encode(dst->encoding(), true);
7062 emit_int8(0x0F);
7063 emit_int8((unsigned char)0x95);
7064 emit_int8((unsigned char)(0xE0 | enc));
7065 }
7066
7067 // 64bit only pieces of the assembler
7068 // This should only be used by 64bit instructions that can use rip-relative
7069 // it cannot be used by instructions that want an immediate value.
7070
7071 bool Assembler::reachable(AddressLiteral adr) {
7072 int64_t disp;
7073 // None will force a 64bit literal to the code stream. Likely a placeholder
7074 // for something that will be patched later and we need to certain it will
7075 // always be reachable.
7076 if (adr.reloc() == relocInfo::none) {
7077 return false;
7078 }
7079 if (adr.reloc() == relocInfo::internal_word_type) {
7080 // This should be rip relative and easily reachable.
7081 return true;
7082 }
7083 if (adr.reloc() == relocInfo::virtual_call_type ||
7084 adr.reloc() == relocInfo::opt_virtual_call_type ||
7085 adr.reloc() == relocInfo::static_call_type ||
7086 adr.reloc() == relocInfo::static_stub_type ) {
7087 // This should be rip relative within the code cache and easily
7088 // reachable until we get huge code caches. (At which point
7089 // ic code is going to have issues).
7090 return true;
7091 }
7092 if (adr.reloc() != relocInfo::external_word_type &&
7093 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special
7094 adr.reloc() != relocInfo::poll_type && // relocs to identify them
7095 adr.reloc() != relocInfo::runtime_call_type ) {
7096 return false;
7097 }
7098
7099 // Stress the correction code
7100 if (ForceUnreachable) {
7101 // Must be runtimecall reloc, see if it is in the codecache
7102 // Flipping stuff in the codecache to be unreachable causes issues
7103 // with things like inline caches where the additional instructions
7104 // are not handled.
7105 if (CodeCache::find_blob(adr._target) == NULL) {
7106 return false;
7107 }
7108 }
7109 // For external_word_type/runtime_call_type if it is reachable from where we
7110 // are now (possibly a temp buffer) and where we might end up
7111 // anywhere in the codeCache then we are always reachable.
7112 // This would have to change if we ever save/restore shared code
7113 // to be more pessimistic.
7114 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int));
7115 if (!is_simm32(disp)) return false;
7116 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int));
7117 if (!is_simm32(disp)) return false;
7118
7119 disp = (int64_t)adr._target - ((int64_t)pc() + sizeof(int));
7120
7121 // Because rip relative is a disp + address_of_next_instruction and we
7122 // don't know the value of address_of_next_instruction we apply a fudge factor
7123 // to make sure we will be ok no matter the size of the instruction we get placed into.
7124 // We don't have to fudge the checks above here because they are already worst case.
7125
7126 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal
7127 // + 4 because better safe than sorry.
7128 const int fudge = 12 + 4;
7129 if (disp < 0) {
7130 disp -= fudge;
7131 } else {
7132 disp += fudge;
7133 }
7134 return is_simm32(disp);
7135 }
7136
7137 // Check if the polling page is not reachable from the code cache using rip-relative
7138 // addressing.
7139 bool Assembler::is_polling_page_far() {
7140 intptr_t addr = (intptr_t)os::get_polling_page();
7141 return ForceUnreachable ||
7142 !is_simm32(addr - (intptr_t)CodeCache::low_bound()) ||
7143 !is_simm32(addr - (intptr_t)CodeCache::high_bound());
7144 }
7145
7146 void Assembler::emit_data64(jlong data,
7147 relocInfo::relocType rtype,
7148 int format) {
7149 if (rtype == relocInfo::none) {
7150 emit_int64(data);
7151 } else {
7152 emit_data64(data, Relocation::spec_simple(rtype), format);
7153 }
7154 }
7155
7156 void Assembler::emit_data64(jlong data,
7157 RelocationHolder const& rspec,
7158 int format) {
7159 assert(imm_operand == 0, "default format must be immediate in this file");
7160 assert(imm_operand == format, "must be immediate");
7161 assert(inst_mark() != NULL, "must be inside InstructionMark");
7162 // Do not use AbstractAssembler::relocate, which is not intended for
7163 // embedded words. Instead, relocate to the enclosing instruction.
7164 code_section()->relocate(inst_mark(), rspec, format);
7165 #ifdef ASSERT
7166 check_relocation(rspec, format);
7167 #endif
7168 emit_int64(data);
7169 }
7170
7171 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) {
7172 if (reg_enc >= 8) {
7173 prefix(REX_B);
7174 reg_enc -= 8;
7175 } else if (byteinst && reg_enc >= 4) {
7176 prefix(REX);
7177 }
7178 return reg_enc;
7179 }
7180
7181 int Assembler::prefixq_and_encode(int reg_enc) {
7182 if (reg_enc < 8) {
7183 prefix(REX_W);
7184 } else {
7185 prefix(REX_WB);
7186 reg_enc -= 8;
7187 }
7188 return reg_enc;
7189 }
7190
7191 int Assembler::prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte) {
7192 if (dst_enc < 8) {
7193 if (src_enc >= 8) {
7194 prefix(REX_B);
7195 src_enc -= 8;
7196 } else if ((src_is_byte && src_enc >= 4) || (dst_is_byte && dst_enc >= 4)) {
7197 prefix(REX);
7198 }
7199 } else {
7200 if (src_enc < 8) {
7201 prefix(REX_R);
7202 } else {
7203 prefix(REX_RB);
7204 src_enc -= 8;
7205 }
7206 dst_enc -= 8;
7207 }
7208 return dst_enc << 3 | src_enc;
7209 }
7210
7211 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) {
7212 if (dst_enc < 8) {
7213 if (src_enc < 8) {
7214 prefix(REX_W);
7215 } else {
7216 prefix(REX_WB);
7217 src_enc -= 8;
7218 }
7219 } else {
7220 if (src_enc < 8) {
7221 prefix(REX_WR);
7222 } else {
7223 prefix(REX_WRB);
7224 src_enc -= 8;
7225 }
7226 dst_enc -= 8;
7227 }
7228 return dst_enc << 3 | src_enc;
7229 }
7230
7231 void Assembler::prefix(Register reg) {
7232 if (reg->encoding() >= 8) {
7233 prefix(REX_B);
7234 }
7235 }
7236
7237 void Assembler::prefix(Register dst, Register src, Prefix p) {
7238 if (src->encoding() >= 8) {
7239 p = (Prefix)(p | REX_B);
7240 }
7241 if (dst->encoding() >= 8) {
7242 p = (Prefix)( p | REX_R);
7243 }
7244 if (p != Prefix_EMPTY) {
7245 // do not generate an empty prefix
7246 prefix(p);
7247 }
7248 }
7249
7250 void Assembler::prefix(Register dst, Address adr, Prefix p) {
7251 if (adr.base_needs_rex()) {
7252 if (adr.index_needs_rex()) {
7253 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X");
7254 } else {
7255 prefix(REX_B);
7256 }
7257 } else {
7258 if (adr.index_needs_rex()) {
7259 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X");
7260 }
7261 }
7262 if (dst->encoding() >= 8) {
7263 p = (Prefix)(p | REX_R);
7264 }
7265 if (p != Prefix_EMPTY) {
7266 // do not generate an empty prefix
7267 prefix(p);
7268 }
7269 }
7270
7271 void Assembler::prefix(Address adr) {
7272 if (adr.base_needs_rex()) {
7273 if (adr.index_needs_rex()) {
7274 prefix(REX_XB);
7275 } else {
7276 prefix(REX_B);
7277 }
7278 } else {
7279 if (adr.index_needs_rex()) {
7280 prefix(REX_X);
7281 }
7282 }
7283 }
7284
7285 void Assembler::prefixq(Address adr) {
7286 if (adr.base_needs_rex()) {
7287 if (adr.index_needs_rex()) {
7288 prefix(REX_WXB);
7289 } else {
7290 prefix(REX_WB);
7291 }
7292 } else {
7293 if (adr.index_needs_rex()) {
7294 prefix(REX_WX);
7295 } else {
7296 prefix(REX_W);
7297 }
7298 }
7299 }
7300
7301
7302 void Assembler::prefix(Address adr, Register reg, bool byteinst) {
7303 if (reg->encoding() < 8) {
7304 if (adr.base_needs_rex()) {
7305 if (adr.index_needs_rex()) {
7306 prefix(REX_XB);
7307 } else {
7308 prefix(REX_B);
7309 }
7310 } else {
7311 if (adr.index_needs_rex()) {
7312 prefix(REX_X);
7313 } else if (byteinst && reg->encoding() >= 4 ) {
7314 prefix(REX);
7315 }
7316 }
7317 } else {
7318 if (adr.base_needs_rex()) {
7319 if (adr.index_needs_rex()) {
7320 prefix(REX_RXB);
7321 } else {
7322 prefix(REX_RB);
7323 }
7324 } else {
7325 if (adr.index_needs_rex()) {
7326 prefix(REX_RX);
7327 } else {
7328 prefix(REX_R);
7329 }
7330 }
7331 }
7332 }
7333
7334 void Assembler::prefixq(Address adr, Register src) {
7335 if (src->encoding() < 8) {
7336 if (adr.base_needs_rex()) {
7337 if (adr.index_needs_rex()) {
7338 prefix(REX_WXB);
7339 } else {
7340 prefix(REX_WB);
7341 }
7342 } else {
7343 if (adr.index_needs_rex()) {
7344 prefix(REX_WX);
7345 } else {
7346 prefix(REX_W);
7347 }
7348 }
7349 } else {
7350 if (adr.base_needs_rex()) {
7351 if (adr.index_needs_rex()) {
7352 prefix(REX_WRXB);
7353 } else {
7354 prefix(REX_WRB);
7355 }
7356 } else {
7357 if (adr.index_needs_rex()) {
7358 prefix(REX_WRX);
7359 } else {
7360 prefix(REX_WR);
7361 }
7362 }
7363 }
7364 }
7365
7366 void Assembler::prefix(Address adr, XMMRegister reg) {
7367 if (reg->encoding() < 8) {
7368 if (adr.base_needs_rex()) {
7369 if (adr.index_needs_rex()) {
7370 prefix(REX_XB);
7371 } else {
7372 prefix(REX_B);
7373 }
7374 } else {
7375 if (adr.index_needs_rex()) {
7376 prefix(REX_X);
7377 }
7378 }
7379 } else {
7380 if (adr.base_needs_rex()) {
7381 if (adr.index_needs_rex()) {
7382 prefix(REX_RXB);
7383 } else {
7384 prefix(REX_RB);
7385 }
7386 } else {
7387 if (adr.index_needs_rex()) {
7388 prefix(REX_RX);
7389 } else {
7390 prefix(REX_R);
7391 }
7392 }
7393 }
7394 }
7395
7396 void Assembler::prefixq(Address adr, XMMRegister src) {
7397 if (src->encoding() < 8) {
7398 if (adr.base_needs_rex()) {
7399 if (adr.index_needs_rex()) {
7400 prefix(REX_WXB);
7401 } else {
7402 prefix(REX_WB);
7403 }
7404 } else {
7405 if (adr.index_needs_rex()) {
7406 prefix(REX_WX);
7407 } else {
7408 prefix(REX_W);
7409 }
7410 }
7411 } else {
7412 if (adr.base_needs_rex()) {
7413 if (adr.index_needs_rex()) {
7414 prefix(REX_WRXB);
7415 } else {
7416 prefix(REX_WRB);
7417 }
7418 } else {
7419 if (adr.index_needs_rex()) {
7420 prefix(REX_WRX);
7421 } else {
7422 prefix(REX_WR);
7423 }
7424 }
7425 }
7426 }
7427
7428 void Assembler::adcq(Register dst, int32_t imm32) {
7429 (void) prefixq_and_encode(dst->encoding());
7430 emit_arith(0x81, 0xD0, dst, imm32);
7431 }
7432
7433 void Assembler::adcq(Register dst, Address src) {
7434 InstructionMark im(this);
7435 prefixq(src, dst);
7436 emit_int8(0x13);
7437 emit_operand(dst, src);
7438 }
7439
7440 void Assembler::adcq(Register dst, Register src) {
7441 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7442 emit_arith(0x13, 0xC0, dst, src);
7443 }
7444
7445 void Assembler::addq(Address dst, int32_t imm32) {
7446 InstructionMark im(this);
7447 prefixq(dst);
7448 emit_arith_operand(0x81, rax, dst,imm32);
7449 }
7450
7451 void Assembler::addq(Address dst, Register src) {
7452 InstructionMark im(this);
7453 prefixq(dst, src);
7454 emit_int8(0x01);
7455 emit_operand(src, dst);
7456 }
7457
7458 void Assembler::addq(Register dst, int32_t imm32) {
7459 (void) prefixq_and_encode(dst->encoding());
7460 emit_arith(0x81, 0xC0, dst, imm32);
7461 }
7462
7463 void Assembler::addq(Register dst, Address src) {
7464 InstructionMark im(this);
7465 prefixq(src, dst);
7466 emit_int8(0x03);
7467 emit_operand(dst, src);
7468 }
7469
7470 void Assembler::addq(Register dst, Register src) {
7471 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7472 emit_arith(0x03, 0xC0, dst, src);
7473 }
7474
7475 void Assembler::adcxq(Register dst, Register src) {
7476 //assert(VM_Version::supports_adx(), "adx instructions not supported");
7477 emit_int8((unsigned char)0x66);
7478 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7479 emit_int8(0x0F);
7480 emit_int8(0x38);
7481 emit_int8((unsigned char)0xF6);
7482 emit_int8((unsigned char)(0xC0 | encode));
7483 }
7484
7485 void Assembler::adoxq(Register dst, Register src) {
7486 //assert(VM_Version::supports_adx(), "adx instructions not supported");
7487 emit_int8((unsigned char)0xF3);
7488 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7489 emit_int8(0x0F);
7490 emit_int8(0x38);
7491 emit_int8((unsigned char)0xF6);
7492 emit_int8((unsigned char)(0xC0 | encode));
7493 }
7494
7495 void Assembler::andq(Address dst, int32_t imm32) {
7496 InstructionMark im(this);
7497 prefixq(dst);
7498 emit_int8((unsigned char)0x81);
7499 emit_operand(rsp, dst, 4);
7500 emit_int32(imm32);
7501 }
7502
7503 void Assembler::andq(Register dst, int32_t imm32) {
7504 (void) prefixq_and_encode(dst->encoding());
7505 emit_arith(0x81, 0xE0, dst, imm32);
7506 }
7507
7508 void Assembler::andq(Register dst, Address src) {
7509 InstructionMark im(this);
7510 prefixq(src, dst);
7511 emit_int8(0x23);
7512 emit_operand(dst, src);
7513 }
7514
7515 void Assembler::andq(Register dst, Register src) {
7516 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7517 emit_arith(0x23, 0xC0, dst, src);
7518 }
7519
7520 void Assembler::andnq(Register dst, Register src1, Register src2) {
7521 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7522 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7523 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7524 emit_int8((unsigned char)0xF2);
7525 emit_int8((unsigned char)(0xC0 | encode));
7526 }
7527
7528 void Assembler::andnq(Register dst, Register src1, Address src2) {
7529 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7530 InstructionMark im(this);
7531 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7532 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7533 emit_int8((unsigned char)0xF2);
7534 emit_operand(dst, src2);
7535 }
7536
7537 void Assembler::bsfq(Register dst, Register src) {
7538 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7539 emit_int8(0x0F);
7540 emit_int8((unsigned char)0xBC);
7541 emit_int8((unsigned char)(0xC0 | encode));
7542 }
7543
7544 void Assembler::bsrq(Register dst, Register src) {
7545 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7546 emit_int8(0x0F);
7547 emit_int8((unsigned char)0xBD);
7548 emit_int8((unsigned char)(0xC0 | encode));
7549 }
7550
7551 void Assembler::bswapq(Register reg) {
7552 int encode = prefixq_and_encode(reg->encoding());
7553 emit_int8(0x0F);
7554 emit_int8((unsigned char)(0xC8 | encode));
7555 }
7556
7557 void Assembler::blsiq(Register dst, Register src) {
7558 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7559 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7560 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7561 emit_int8((unsigned char)0xF3);
7562 emit_int8((unsigned char)(0xC0 | encode));
7563 }
7564
7565 void Assembler::blsiq(Register dst, Address src) {
7566 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7567 InstructionMark im(this);
7568 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7569 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7570 emit_int8((unsigned char)0xF3);
7571 emit_operand(rbx, src);
7572 }
7573
7574 void Assembler::blsmskq(Register dst, Register src) {
7575 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7576 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7577 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7578 emit_int8((unsigned char)0xF3);
7579 emit_int8((unsigned char)(0xC0 | encode));
7580 }
7581
7582 void Assembler::blsmskq(Register dst, Address src) {
7583 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7584 InstructionMark im(this);
7585 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7586 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7587 emit_int8((unsigned char)0xF3);
7588 emit_operand(rdx, src);
7589 }
7590
7591 void Assembler::blsrq(Register dst, Register src) {
7592 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7593 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7594 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7595 emit_int8((unsigned char)0xF3);
7596 emit_int8((unsigned char)(0xC0 | encode));
7597 }
7598
7599 void Assembler::blsrq(Register dst, Address src) {
7600 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7601 InstructionMark im(this);
7602 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7603 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7604 emit_int8((unsigned char)0xF3);
7605 emit_operand(rcx, src);
7606 }
7607
7608 void Assembler::cdqq() {
7609 prefix(REX_W);
7610 emit_int8((unsigned char)0x99);
7611 }
7612
7613 void Assembler::clflush(Address adr) {
7614 prefix(adr);
7615 emit_int8(0x0F);
7616 emit_int8((unsigned char)0xAE);
7617 emit_operand(rdi, adr);
7618 }
7619
7620 void Assembler::cmovq(Condition cc, Register dst, Register src) {
7621 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7622 emit_int8(0x0F);
7623 emit_int8(0x40 | cc);
7624 emit_int8((unsigned char)(0xC0 | encode));
7625 }
7626
7627 void Assembler::cmovq(Condition cc, Register dst, Address src) {
7628 InstructionMark im(this);
7629 prefixq(src, dst);
7630 emit_int8(0x0F);
7631 emit_int8(0x40 | cc);
7632 emit_operand(dst, src);
7633 }
7634
7635 void Assembler::cmpq(Address dst, int32_t imm32) {
7636 InstructionMark im(this);
7637 prefixq(dst);
7638 emit_int8((unsigned char)0x81);
7639 emit_operand(rdi, dst, 4);
7640 emit_int32(imm32);
7641 }
7642
7643 void Assembler::cmpq(Register dst, int32_t imm32) {
7644 (void) prefixq_and_encode(dst->encoding());
7645 emit_arith(0x81, 0xF8, dst, imm32);
7646 }
7647
7648 void Assembler::cmpq(Address dst, Register src) {
7649 InstructionMark im(this);
7650 prefixq(dst, src);
7651 emit_int8(0x3B);
7652 emit_operand(src, dst);
7653 }
7654
7655 void Assembler::cmpq(Register dst, Register src) {
7656 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7657 emit_arith(0x3B, 0xC0, dst, src);
7658 }
7659
7660 void Assembler::cmpq(Register dst, Address src) {
7661 InstructionMark im(this);
7662 prefixq(src, dst);
7663 emit_int8(0x3B);
7664 emit_operand(dst, src);
7665 }
7666
7667 void Assembler::cmpxchgq(Register reg, Address adr) {
7668 InstructionMark im(this);
7669 prefixq(adr, reg);
7670 emit_int8(0x0F);
7671 emit_int8((unsigned char)0xB1);
7672 emit_operand(reg, adr);
7673 }
7674
7675 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
7676 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7677 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7678 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
7679 emit_int8(0x2A);
7680 emit_int8((unsigned char)(0xC0 | encode));
7681 }
7682
7683 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) {
7684 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7685 InstructionMark im(this);
7686 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7687 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
7688 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
7689 emit_int8(0x2A);
7690 emit_operand(dst, src);
7691 }
7692
7693 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) {
7694 NOT_LP64(assert(VM_Version::supports_sse(), ""));
7695 InstructionMark im(this);
7696 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7697 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
7698 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
7699 emit_int8(0x2A);
7700 emit_operand(dst, src);
7701 }
7702
7703 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
7704 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7705 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7706 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
7707 emit_int8(0x2C);
7708 emit_int8((unsigned char)(0xC0 | encode));
7709 }
7710
7711 void Assembler::cvttss2siq(Register dst, XMMRegister src) {
7712 NOT_LP64(assert(VM_Version::supports_sse(), ""));
7713 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7714 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
7715 emit_int8(0x2C);
7716 emit_int8((unsigned char)(0xC0 | encode));
7717 }
7718
7719 void Assembler::decl(Register dst) {
7720 // Don't use it directly. Use MacroAssembler::decrementl() instead.
7721 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
7722 int encode = prefix_and_encode(dst->encoding());
7723 emit_int8((unsigned char)0xFF);
7724 emit_int8((unsigned char)(0xC8 | encode));
7725 }
7726
7727 void Assembler::decq(Register dst) {
7728 // Don't use it directly. Use MacroAssembler::decrementq() instead.
7729 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
7730 int encode = prefixq_and_encode(dst->encoding());
7731 emit_int8((unsigned char)0xFF);
7732 emit_int8(0xC8 | encode);
7733 }
7734
7735 void Assembler::decq(Address dst) {
7736 // Don't use it directly. Use MacroAssembler::decrementq() instead.
7737 InstructionMark im(this);
7738 prefixq(dst);
7739 emit_int8((unsigned char)0xFF);
7740 emit_operand(rcx, dst);
7741 }
7742
7743 void Assembler::fxrstor(Address src) {
7744 prefixq(src);
7745 emit_int8(0x0F);
7746 emit_int8((unsigned char)0xAE);
7747 emit_operand(as_Register(1), src);
7748 }
7749
7750 void Assembler::xrstor(Address src) {
7751 prefixq(src);
7752 emit_int8(0x0F);
7753 emit_int8((unsigned char)0xAE);
7754 emit_operand(as_Register(5), src);
7755 }
7756
7757 void Assembler::fxsave(Address dst) {
7758 prefixq(dst);
7759 emit_int8(0x0F);
7760 emit_int8((unsigned char)0xAE);
7761 emit_operand(as_Register(0), dst);
7762 }
7763
7764 void Assembler::xsave(Address dst) {
7765 prefixq(dst);
7766 emit_int8(0x0F);
7767 emit_int8((unsigned char)0xAE);
7768 emit_operand(as_Register(4), dst);
7769 }
7770
7771 void Assembler::idivq(Register src) {
7772 int encode = prefixq_and_encode(src->encoding());
7773 emit_int8((unsigned char)0xF7);
7774 emit_int8((unsigned char)(0xF8 | encode));
7775 }
7776
7777 void Assembler::imulq(Register dst, Register src) {
7778 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7779 emit_int8(0x0F);
7780 emit_int8((unsigned char)0xAF);
7781 emit_int8((unsigned char)(0xC0 | encode));
7782 }
7783
7784 void Assembler::imulq(Register dst, Register src, int value) {
7785 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7786 if (is8bit(value)) {
7787 emit_int8(0x6B);
7788 emit_int8((unsigned char)(0xC0 | encode));
7789 emit_int8(value & 0xFF);
7790 } else {
7791 emit_int8(0x69);
7792 emit_int8((unsigned char)(0xC0 | encode));
7793 emit_int32(value);
7794 }
7795 }
7796
7797 void Assembler::imulq(Register dst, Address src) {
7798 InstructionMark im(this);
7799 prefixq(src, dst);
7800 emit_int8(0x0F);
7801 emit_int8((unsigned char) 0xAF);
7802 emit_operand(dst, src);
7803 }
7804
7805 void Assembler::incl(Register dst) {
7806 // Don't use it directly. Use MacroAssembler::incrementl() instead.
7807 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
7808 int encode = prefix_and_encode(dst->encoding());
7809 emit_int8((unsigned char)0xFF);
7810 emit_int8((unsigned char)(0xC0 | encode));
7811 }
7812
7813 void Assembler::incq(Register dst) {
7814 // Don't use it directly. Use MacroAssembler::incrementq() instead.
7815 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
7816 int encode = prefixq_and_encode(dst->encoding());
7817 emit_int8((unsigned char)0xFF);
7818 emit_int8((unsigned char)(0xC0 | encode));
7819 }
7820
7821 void Assembler::incq(Address dst) {
7822 // Don't use it directly. Use MacroAssembler::incrementq() instead.
7823 InstructionMark im(this);
7824 prefixq(dst);
7825 emit_int8((unsigned char)0xFF);
7826 emit_operand(rax, dst);
7827 }
7828
7829 void Assembler::lea(Register dst, Address src) {
7830 leaq(dst, src);
7831 }
7832
7833 void Assembler::leaq(Register dst, Address src) {
7834 InstructionMark im(this);
7835 prefixq(src, dst);
7836 emit_int8((unsigned char)0x8D);
7837 emit_operand(dst, src);
7838 }
7839
7840 void Assembler::mov64(Register dst, int64_t imm64) {
7841 InstructionMark im(this);
7842 int encode = prefixq_and_encode(dst->encoding());
7843 emit_int8((unsigned char)(0xB8 | encode));
7844 emit_int64(imm64);
7845 }
7846
7847 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) {
7848 InstructionMark im(this);
7849 int encode = prefixq_and_encode(dst->encoding());
7850 emit_int8(0xB8 | encode);
7851 emit_data64(imm64, rspec);
7852 }
7853
7854 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) {
7855 InstructionMark im(this);
7856 int encode = prefix_and_encode(dst->encoding());
7857 emit_int8((unsigned char)(0xB8 | encode));
7858 emit_data((int)imm32, rspec, narrow_oop_operand);
7859 }
7860
7861 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) {
7862 InstructionMark im(this);
7863 prefix(dst);
7864 emit_int8((unsigned char)0xC7);
7865 emit_operand(rax, dst, 4);
7866 emit_data((int)imm32, rspec, narrow_oop_operand);
7867 }
7868
7869 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) {
7870 InstructionMark im(this);
7871 int encode = prefix_and_encode(src1->encoding());
7872 emit_int8((unsigned char)0x81);
7873 emit_int8((unsigned char)(0xF8 | encode));
7874 emit_data((int)imm32, rspec, narrow_oop_operand);
7875 }
7876
7877 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) {
7878 InstructionMark im(this);
7879 prefix(src1);
7880 emit_int8((unsigned char)0x81);
7881 emit_operand(rax, src1, 4);
7882 emit_data((int)imm32, rspec, narrow_oop_operand);
7883 }
7884
7885 void Assembler::lzcntq(Register dst, Register src) {
7886 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
7887 emit_int8((unsigned char)0xF3);
7888 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7889 emit_int8(0x0F);
7890 emit_int8((unsigned char)0xBD);
7891 emit_int8((unsigned char)(0xC0 | encode));
7892 }
7893
7894 void Assembler::movdq(XMMRegister dst, Register src) {
7895 // table D-1 says MMX/SSE2
7896 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7897 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7898 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7899 emit_int8(0x6E);
7900 emit_int8((unsigned char)(0xC0 | encode));
7901 }
7902
7903 void Assembler::movdq(Register dst, XMMRegister src) {
7904 // table D-1 says MMX/SSE2
7905 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7906 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7907 // swap src/dst to get correct prefix
7908 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7909 emit_int8(0x7E);
7910 emit_int8((unsigned char)(0xC0 | encode));
7911 }
7912
7913 void Assembler::movq(Register dst, Register src) {
7914 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7915 emit_int8((unsigned char)0x8B);
7916 emit_int8((unsigned char)(0xC0 | encode));
7917 }
7918
7919 void Assembler::movq(Register dst, Address src) {
7920 InstructionMark im(this);
7921 prefixq(src, dst);
7922 emit_int8((unsigned char)0x8B);
7923 emit_operand(dst, src);
7924 }
7925
7926 void Assembler::movq(Address dst, Register src) {
7927 InstructionMark im(this);
7928 prefixq(dst, src);
7929 emit_int8((unsigned char)0x89);
7930 emit_operand(src, dst);
7931 }
7932
7933 void Assembler::movsbq(Register dst, Address src) {
7934 InstructionMark im(this);
7935 prefixq(src, dst);
7936 emit_int8(0x0F);
7937 emit_int8((unsigned char)0xBE);
7938 emit_operand(dst, src);
7939 }
7940
7941 void Assembler::movsbq(Register dst, Register src) {
7942 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7943 emit_int8(0x0F);
7944 emit_int8((unsigned char)0xBE);
7945 emit_int8((unsigned char)(0xC0 | encode));
7946 }
7947
7948 void Assembler::movslq(Register dst, int32_t imm32) {
7949 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx)
7950 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx)
7951 // as a result we shouldn't use until tested at runtime...
7952 ShouldNotReachHere();
7953 InstructionMark im(this);
7954 int encode = prefixq_and_encode(dst->encoding());
7955 emit_int8((unsigned char)(0xC7 | encode));
7956 emit_int32(imm32);
7957 }
7958
7959 void Assembler::movslq(Address dst, int32_t imm32) {
7960 assert(is_simm32(imm32), "lost bits");
7961 InstructionMark im(this);
7962 prefixq(dst);
7963 emit_int8((unsigned char)0xC7);
7964 emit_operand(rax, dst, 4);
7965 emit_int32(imm32);
7966 }
7967
7968 void Assembler::movslq(Register dst, Address src) {
7969 InstructionMark im(this);
7970 prefixq(src, dst);
7971 emit_int8(0x63);
7972 emit_operand(dst, src);
7973 }
7974
7975 void Assembler::movslq(Register dst, Register src) {
7976 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7977 emit_int8(0x63);
7978 emit_int8((unsigned char)(0xC0 | encode));
7979 }
7980
7981 void Assembler::movswq(Register dst, Address src) {
7982 InstructionMark im(this);
7983 prefixq(src, dst);
7984 emit_int8(0x0F);
7985 emit_int8((unsigned char)0xBF);
7986 emit_operand(dst, src);
7987 }
7988
7989 void Assembler::movswq(Register dst, Register src) {
7990 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7991 emit_int8((unsigned char)0x0F);
7992 emit_int8((unsigned char)0xBF);
7993 emit_int8((unsigned char)(0xC0 | encode));
7994 }
7995
7996 void Assembler::movzbq(Register dst, Address src) {
7997 InstructionMark im(this);
7998 prefixq(src, dst);
7999 emit_int8((unsigned char)0x0F);
8000 emit_int8((unsigned char)0xB6);
8001 emit_operand(dst, src);
8002 }
8003
8004 void Assembler::movzbq(Register dst, Register src) {
8005 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8006 emit_int8(0x0F);
8007 emit_int8((unsigned char)0xB6);
8008 emit_int8(0xC0 | encode);
8009 }
8010
8011 void Assembler::movzwq(Register dst, Address src) {
8012 InstructionMark im(this);
8013 prefixq(src, dst);
8014 emit_int8((unsigned char)0x0F);
8015 emit_int8((unsigned char)0xB7);
8016 emit_operand(dst, src);
8017 }
8018
8019 void Assembler::movzwq(Register dst, Register src) {
8020 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8021 emit_int8((unsigned char)0x0F);
8022 emit_int8((unsigned char)0xB7);
8023 emit_int8((unsigned char)(0xC0 | encode));
8024 }
8025
8026 void Assembler::mulq(Address src) {
8027 InstructionMark im(this);
8028 prefixq(src);
8029 emit_int8((unsigned char)0xF7);
8030 emit_operand(rsp, src);
8031 }
8032
8033 void Assembler::mulq(Register src) {
8034 int encode = prefixq_and_encode(src->encoding());
8035 emit_int8((unsigned char)0xF7);
8036 emit_int8((unsigned char)(0xE0 | encode));
8037 }
8038
8039 void Assembler::mulxq(Register dst1, Register dst2, Register src) {
8040 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
8041 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
8042 int encode = vex_prefix_and_encode(dst1->encoding(), dst2->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
8043 emit_int8((unsigned char)0xF6);
8044 emit_int8((unsigned char)(0xC0 | encode));
8045 }
8046
8047 void Assembler::negq(Register dst) {
8048 int encode = prefixq_and_encode(dst->encoding());
8049 emit_int8((unsigned char)0xF7);
8050 emit_int8((unsigned char)(0xD8 | encode));
8051 }
8052
8053 void Assembler::notq(Register dst) {
8054 int encode = prefixq_and_encode(dst->encoding());
8055 emit_int8((unsigned char)0xF7);
8056 emit_int8((unsigned char)(0xD0 | encode));
8057 }
8058
8059 void Assembler::orq(Address dst, int32_t imm32) {
8060 InstructionMark im(this);
8061 prefixq(dst);
8062 emit_int8((unsigned char)0x81);
8063 emit_operand(rcx, dst, 4);
8064 emit_int32(imm32);
8065 }
8066
8067 void Assembler::orq(Register dst, int32_t imm32) {
8068 (void) prefixq_and_encode(dst->encoding());
8069 emit_arith(0x81, 0xC8, dst, imm32);
8070 }
8071
8072 void Assembler::orq(Register dst, Address src) {
8073 InstructionMark im(this);
8074 prefixq(src, dst);
8075 emit_int8(0x0B);
8076 emit_operand(dst, src);
8077 }
8078
8079 void Assembler::orq(Register dst, Register src) {
8080 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8081 emit_arith(0x0B, 0xC0, dst, src);
8082 }
8083
8084 void Assembler::popa() { // 64bit
8085 movq(r15, Address(rsp, 0));
8086 movq(r14, Address(rsp, wordSize));
8087 movq(r13, Address(rsp, 2 * wordSize));
8088 movq(r12, Address(rsp, 3 * wordSize));
8089 movq(r11, Address(rsp, 4 * wordSize));
8090 movq(r10, Address(rsp, 5 * wordSize));
8091 movq(r9, Address(rsp, 6 * wordSize));
8092 movq(r8, Address(rsp, 7 * wordSize));
8093 movq(rdi, Address(rsp, 8 * wordSize));
8094 movq(rsi, Address(rsp, 9 * wordSize));
8095 movq(rbp, Address(rsp, 10 * wordSize));
8096 // skip rsp
8097 movq(rbx, Address(rsp, 12 * wordSize));
8098 movq(rdx, Address(rsp, 13 * wordSize));
8099 movq(rcx, Address(rsp, 14 * wordSize));
8100 movq(rax, Address(rsp, 15 * wordSize));
8101
8102 addq(rsp, 16 * wordSize);
8103 }
8104
8105 void Assembler::popcntq(Register dst, Address src) {
8106 assert(VM_Version::supports_popcnt(), "must support");
8107 InstructionMark im(this);
8108 emit_int8((unsigned char)0xF3);
8109 prefixq(src, dst);
8110 emit_int8((unsigned char)0x0F);
8111 emit_int8((unsigned char)0xB8);
8112 emit_operand(dst, src);
8113 }
8114
8115 void Assembler::popcntq(Register dst, Register src) {
8116 assert(VM_Version::supports_popcnt(), "must support");
8117 emit_int8((unsigned char)0xF3);
8118 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8119 emit_int8((unsigned char)0x0F);
8120 emit_int8((unsigned char)0xB8);
8121 emit_int8((unsigned char)(0xC0 | encode));
8122 }
8123
8124 void Assembler::popq(Address dst) {
8125 InstructionMark im(this);
8126 prefixq(dst);
8127 emit_int8((unsigned char)0x8F);
8128 emit_operand(rax, dst);
8129 }
8130
8131 void Assembler::pusha() { // 64bit
8132 // we have to store original rsp. ABI says that 128 bytes
8133 // below rsp are local scratch.
8134 movq(Address(rsp, -5 * wordSize), rsp);
8135
8136 subq(rsp, 16 * wordSize);
8137
8138 movq(Address(rsp, 15 * wordSize), rax);
8139 movq(Address(rsp, 14 * wordSize), rcx);
8140 movq(Address(rsp, 13 * wordSize), rdx);
8141 movq(Address(rsp, 12 * wordSize), rbx);
8142 // skip rsp
8143 movq(Address(rsp, 10 * wordSize), rbp);
8144 movq(Address(rsp, 9 * wordSize), rsi);
8145 movq(Address(rsp, 8 * wordSize), rdi);
8146 movq(Address(rsp, 7 * wordSize), r8);
8147 movq(Address(rsp, 6 * wordSize), r9);
8148 movq(Address(rsp, 5 * wordSize), r10);
8149 movq(Address(rsp, 4 * wordSize), r11);
8150 movq(Address(rsp, 3 * wordSize), r12);
8151 movq(Address(rsp, 2 * wordSize), r13);
8152 movq(Address(rsp, wordSize), r14);
8153 movq(Address(rsp, 0), r15);
8154 }
8155
8156 void Assembler::pushq(Address src) {
8157 InstructionMark im(this);
8158 prefixq(src);
8159 emit_int8((unsigned char)0xFF);
8160 emit_operand(rsi, src);
8161 }
8162
8163 void Assembler::rclq(Register dst, int imm8) {
8164 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8165 int encode = prefixq_and_encode(dst->encoding());
8166 if (imm8 == 1) {
8167 emit_int8((unsigned char)0xD1);
8168 emit_int8((unsigned char)(0xD0 | encode));
8169 } else {
8170 emit_int8((unsigned char)0xC1);
8171 emit_int8((unsigned char)(0xD0 | encode));
8172 emit_int8(imm8);
8173 }
8174 }
8175
8176 void Assembler::rcrq(Register dst, int imm8) {
8177 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8178 int encode = prefixq_and_encode(dst->encoding());
8179 if (imm8 == 1) {
8180 emit_int8((unsigned char)0xD1);
8181 emit_int8((unsigned char)(0xD8 | encode));
8182 } else {
8183 emit_int8((unsigned char)0xC1);
8184 emit_int8((unsigned char)(0xD8 | encode));
8185 emit_int8(imm8);
8186 }
8187 }
8188
8189 void Assembler::rorq(Register dst, int imm8) {
8190 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8191 int encode = prefixq_and_encode(dst->encoding());
8192 if (imm8 == 1) {
8193 emit_int8((unsigned char)0xD1);
8194 emit_int8((unsigned char)(0xC8 | encode));
8195 } else {
8196 emit_int8((unsigned char)0xC1);
8197 emit_int8((unsigned char)(0xc8 | encode));
8198 emit_int8(imm8);
8199 }
8200 }
8201
8202 void Assembler::rorxq(Register dst, Register src, int imm8) {
8203 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
8204 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
8205 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes);
8206 emit_int8((unsigned char)0xF0);
8207 emit_int8((unsigned char)(0xC0 | encode));
8208 emit_int8(imm8);
8209 }
8210
8211 void Assembler::sarq(Register dst, int imm8) {
8212 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8213 int encode = prefixq_and_encode(dst->encoding());
8214 if (imm8 == 1) {
8215 emit_int8((unsigned char)0xD1);
8216 emit_int8((unsigned char)(0xF8 | encode));
8217 } else {
8218 emit_int8((unsigned char)0xC1);
8219 emit_int8((unsigned char)(0xF8 | encode));
8220 emit_int8(imm8);
8221 }
8222 }
8223
8224 void Assembler::sarq(Register dst) {
8225 int encode = prefixq_and_encode(dst->encoding());
8226 emit_int8((unsigned char)0xD3);
8227 emit_int8((unsigned char)(0xF8 | encode));
8228 }
8229
8230 void Assembler::sbbq(Address dst, int32_t imm32) {
8231 InstructionMark im(this);
8232 prefixq(dst);
8233 emit_arith_operand(0x81, rbx, dst, imm32);
8234 }
8235
8236 void Assembler::sbbq(Register dst, int32_t imm32) {
8237 (void) prefixq_and_encode(dst->encoding());
8238 emit_arith(0x81, 0xD8, dst, imm32);
8239 }
8240
8241 void Assembler::sbbq(Register dst, Address src) {
8242 InstructionMark im(this);
8243 prefixq(src, dst);
8244 emit_int8(0x1B);
8245 emit_operand(dst, src);
8246 }
8247
8248 void Assembler::sbbq(Register dst, Register src) {
8249 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8250 emit_arith(0x1B, 0xC0, dst, src);
8251 }
8252
8253 void Assembler::shlq(Register dst, int imm8) {
8254 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8255 int encode = prefixq_and_encode(dst->encoding());
8256 if (imm8 == 1) {
8257 emit_int8((unsigned char)0xD1);
8258 emit_int8((unsigned char)(0xE0 | encode));
8259 } else {
8260 emit_int8((unsigned char)0xC1);
8261 emit_int8((unsigned char)(0xE0 | encode));
8262 emit_int8(imm8);
8263 }
8264 }
8265
8266 void Assembler::shlq(Register dst) {
8267 int encode = prefixq_and_encode(dst->encoding());
8268 emit_int8((unsigned char)0xD3);
8269 emit_int8((unsigned char)(0xE0 | encode));
8270 }
8271
8272 void Assembler::shrq(Register dst, int imm8) {
8273 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8274 int encode = prefixq_and_encode(dst->encoding());
8275 emit_int8((unsigned char)0xC1);
8276 emit_int8((unsigned char)(0xE8 | encode));
8277 emit_int8(imm8);
8278 }
8279
8280 void Assembler::shrq(Register dst) {
8281 int encode = prefixq_and_encode(dst->encoding());
8282 emit_int8((unsigned char)0xD3);
8283 emit_int8(0xE8 | encode);
8284 }
8285
8286 void Assembler::subq(Address dst, int32_t imm32) {
8287 InstructionMark im(this);
8288 prefixq(dst);
8289 emit_arith_operand(0x81, rbp, dst, imm32);
8290 }
8291
8292 void Assembler::subq(Address dst, Register src) {
8293 InstructionMark im(this);
8294 prefixq(dst, src);
8295 emit_int8(0x29);
8296 emit_operand(src, dst);
8297 }
8298
8299 void Assembler::subq(Register dst, int32_t imm32) {
8300 (void) prefixq_and_encode(dst->encoding());
8301 emit_arith(0x81, 0xE8, dst, imm32);
8302 }
8303
8304 // Force generation of a 4 byte immediate value even if it fits into 8bit
8305 void Assembler::subq_imm32(Register dst, int32_t imm32) {
8306 (void) prefixq_and_encode(dst->encoding());
8307 emit_arith_imm32(0x81, 0xE8, dst, imm32);
8308 }
8309
8310 void Assembler::subq(Register dst, Address src) {
8311 InstructionMark im(this);
8312 prefixq(src, dst);
8313 emit_int8(0x2B);
8314 emit_operand(dst, src);
8315 }
8316
8317 void Assembler::subq(Register dst, Register src) {
8318 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8319 emit_arith(0x2B, 0xC0, dst, src);
8320 }
8321
8322 void Assembler::testq(Register dst, int32_t imm32) {
8323 // not using emit_arith because test
8324 // doesn't support sign-extension of
8325 // 8bit operands
8326 int encode = dst->encoding();
8327 if (encode == 0) {
8328 prefix(REX_W);
8329 emit_int8((unsigned char)0xA9);
8330 } else {
8331 encode = prefixq_and_encode(encode);
8332 emit_int8((unsigned char)0xF7);
8333 emit_int8((unsigned char)(0xC0 | encode));
8334 }
8335 emit_int32(imm32);
8336 }
8337
8338 void Assembler::testq(Register dst, Register src) {
8339 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8340 emit_arith(0x85, 0xC0, dst, src);
8341 }
8342
8343 void Assembler::xaddq(Address dst, Register src) {
8344 InstructionMark im(this);
8345 prefixq(dst, src);
8346 emit_int8(0x0F);
8347 emit_int8((unsigned char)0xC1);
8348 emit_operand(src, dst);
8349 }
8350
8351 void Assembler::xchgq(Register dst, Address src) {
8352 InstructionMark im(this);
8353 prefixq(src, dst);
8354 emit_int8((unsigned char)0x87);
8355 emit_operand(dst, src);
8356 }
8357
8358 void Assembler::xchgq(Register dst, Register src) {
8359 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8360 emit_int8((unsigned char)0x87);
8361 emit_int8((unsigned char)(0xc0 | encode));
8362 }
8363
8364 void Assembler::xorq(Register dst, Register src) {
8365 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8366 emit_arith(0x33, 0xC0, dst, src);
8367 }
8368
8369 void Assembler::xorq(Register dst, Address src) {
8370 InstructionMark im(this);
8371 prefixq(src, dst);
8372 emit_int8(0x33);
8373 emit_operand(dst, src);
8374 }
8375
8376 #endif // !LP64