31
32 #ifdef _MSC_VER
33 #define ALIGNED_(x) __declspec(align(x))
34 #else
35 #define ALIGNED_(x) __attribute__ ((aligned(x)))
36 #endif
37
38 // Implementation of the platform-specific part of StubRoutines - for
39 // a description of how to extend it, see the stubRoutines.hpp file.
40
41 address StubRoutines::x86::_verify_mxcsr_entry = NULL;
42 address StubRoutines::x86::_key_shuffle_mask_addr = NULL;
43 address StubRoutines::x86::_counter_shuffle_mask_addr = NULL;
44 address StubRoutines::x86::_ghash_long_swap_mask_addr = NULL;
45 address StubRoutines::x86::_ghash_byte_swap_mask_addr = NULL;
46 address StubRoutines::x86::_upper_word_mask_addr = NULL;
47 address StubRoutines::x86::_shuffle_byte_flip_mask_addr = NULL;
48 address StubRoutines::x86::_k256_adr = NULL;
49 address StubRoutines::x86::_pshuffle_byte_flip_mask_addr = NULL;
50
51 uint64_t StubRoutines::x86::_crc_by128_masks[] =
52 {
53 /* The fields in this structure are arranged so that they can be
54 * picked up two at a time with 128-bit loads.
55 *
56 * Because of flipped bit order for this CRC polynomials
57 * the constant for X**N is left-shifted by 1. This is because
58 * a 64 x 64 polynomial multiply produces a 127-bit result
59 * but the highest term is always aligned to bit 0 in the container.
60 * Pre-shifting by one fixes this, at the cost of potentially making
61 * the 32-bit constant no longer fit in a 32-bit container (thus the
62 * use of uint64_t, though this is also the size used by the carry-
63 * less multiply instruction.
64 *
65 * In addition, the flipped bit order and highest-term-at-least-bit
66 * multiply changes the constants used. The 96-bit result will be
67 * aligned to the high-term end of the target 128-bit container,
68 * not the low-term end; that is, instead of a 512-bit or 576-bit fold,
69 * instead it is a 480 (=512-32) or 544 (=512+64-32) bit fold.
70 *
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31
32 #ifdef _MSC_VER
33 #define ALIGNED_(x) __declspec(align(x))
34 #else
35 #define ALIGNED_(x) __attribute__ ((aligned(x)))
36 #endif
37
38 // Implementation of the platform-specific part of StubRoutines - for
39 // a description of how to extend it, see the stubRoutines.hpp file.
40
41 address StubRoutines::x86::_verify_mxcsr_entry = NULL;
42 address StubRoutines::x86::_key_shuffle_mask_addr = NULL;
43 address StubRoutines::x86::_counter_shuffle_mask_addr = NULL;
44 address StubRoutines::x86::_ghash_long_swap_mask_addr = NULL;
45 address StubRoutines::x86::_ghash_byte_swap_mask_addr = NULL;
46 address StubRoutines::x86::_upper_word_mask_addr = NULL;
47 address StubRoutines::x86::_shuffle_byte_flip_mask_addr = NULL;
48 address StubRoutines::x86::_k256_adr = NULL;
49 address StubRoutines::x86::_pshuffle_byte_flip_mask_addr = NULL;
50
51 //tables common for sin and cos
52 address StubRoutines::x86::_ONEHALF_adr = NULL;
53 address StubRoutines::x86::_P_2_adr = NULL;
54 address StubRoutines::x86::_SC_4_adr = NULL;
55 address StubRoutines::x86::_Ctable_adr = NULL;
56 address StubRoutines::x86::_SC_2_adr = NULL;
57 address StubRoutines::x86::_SC_3_adr = NULL;
58 address StubRoutines::x86::_SC_1_adr = NULL;
59 address StubRoutines::x86::_PI_INV_TABLE_adr = NULL;
60 address StubRoutines::x86::_PI_4_adr = NULL;
61 address StubRoutines::x86::_PI32INV_adr = NULL;
62 address StubRoutines::x86::_SIGN_MASK_adr = NULL;
63 address StubRoutines::x86::_P_1_adr = NULL;
64 address StubRoutines::x86::_P_3_adr = NULL;
65 address StubRoutines::x86::_NEG_ZERO_adr = NULL;
66
67 //tables common for sincos and tancot
68 address StubRoutines::x86::_L_2il0floatpacket_0_adr = NULL;
69 address StubRoutines::x86::_Pi4Inv_adr = NULL;
70 address StubRoutines::x86::_Pi4x3_adr = NULL;
71 address StubRoutines::x86::_Pi4x4_adr = NULL;
72 address StubRoutines::x86::_ones_adr = NULL;
73
74 uint64_t StubRoutines::x86::_crc_by128_masks[] =
75 {
76 /* The fields in this structure are arranged so that they can be
77 * picked up two at a time with 128-bit loads.
78 *
79 * Because of flipped bit order for this CRC polynomials
80 * the constant for X**N is left-shifted by 1. This is because
81 * a 64 x 64 polynomial multiply produces a 127-bit result
82 * but the highest term is always aligned to bit 0 in the container.
83 * Pre-shifting by one fixes this, at the cost of potentially making
84 * the 32-bit constant no longer fit in a 32-bit container (thus the
85 * use of uint64_t, though this is also the size used by the carry-
86 * less multiply instruction.
87 *
88 * In addition, the flipped bit order and highest-term-at-least-bit
89 * multiply changes the constants used. The 96-bit result will be
90 * aligned to the high-term end of the target 128-bit container,
91 * not the low-term end; that is, instead of a 512-bit or 576-bit fold,
92 * instead it is a 480 (=512-32) or 544 (=512+64-32) bit fold.
93 *
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