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src/share/vm/c1/c1_LIR.cpp

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 710       if (op2->_opr1->is_valid())         do_temp(op2->_opr1);
 711       if (op2->_opr2->is_valid())         do_input(op2->_opr2); // exception object is input parameter
 712       assert(op2->_result->is_illegal(), "no result");
 713       assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
 714              op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
 715 
 716       break;
 717     }
 718 
 719     case lir_unwind: {
 720       assert(op->as_Op1() != NULL, "must be");
 721       LIR_Op1* op1 = (LIR_Op1*)op;
 722 
 723       assert(op1->_info == NULL, "no info");
 724       assert(op1->_opr->is_valid(), "exception oop");         do_input(op1->_opr);
 725       assert(op1->_result->is_illegal(), "no result");
 726 
 727       break;
 728     }
 729 
 730 
 731     case lir_tan:
 732     case lir_log10: {
 733       assert(op->as_Op2() != NULL, "must be");
 734       LIR_Op2* op2 = (LIR_Op2*)op;
 735 
 736       // On x86 tan/sin/cos need two temporary fpu stack slots and
 737       // log/log10 need one so handle opr2 and tmp as temp inputs.
 738       // Register input operand as temp to guarantee that it doesn't
 739       // overlap with the input.
 740       assert(op2->_info == NULL, "not used");
 741       assert(op2->_tmp5->is_illegal(), "not used");
 742       assert(op2->_opr1->is_valid(), "used");
 743       do_input(op2->_opr1); do_temp(op2->_opr1);
 744 
 745       if (op2->_opr2->is_valid())         do_temp(op2->_opr2);
 746       if (op2->_tmp1->is_valid())         do_temp(op2->_tmp1);
 747       if (op2->_tmp2->is_valid())         do_temp(op2->_tmp2);
 748       if (op2->_tmp3->is_valid())         do_temp(op2->_tmp3);
 749       if (op2->_tmp4->is_valid())         do_temp(op2->_tmp4);
 750       if (op2->_result->is_valid())       do_output(op2->_result);
 751 
 752       break;
 753     }
 754 
 755 // LIR_Op3
 756     case lir_idiv:
 757     case lir_irem: {
 758       assert(op->as_Op3() != NULL, "must be");
 759       LIR_Op3* op3= (LIR_Op3*)op;
 760 
 761       if (op3->_info)                     do_info(op3->_info);
 762       if (op3->_opr1->is_valid())         do_input(op3->_opr1);
 763 
 764       // second operand is input and temp, so ensure that second operand
 765       // and third operand get not the same register
 766       if (op3->_opr2->is_valid())         do_input(op3->_opr2);
 767       if (op3->_opr2->is_valid())         do_temp(op3->_opr2);
 768       if (op3->_opr3->is_valid())         do_temp(op3->_opr3);
 769 
 770       if (op3->_result->is_valid())       do_output(op3->_result);
 771 
 772       break;
 773     }
 774 


1721      case lir_convert:               s = "convert";       break;
1722      case lir_alloc_object:          s = "alloc_obj";     break;
1723      case lir_monaddr:               s = "mon_addr";      break;
1724      case lir_pack64:                s = "pack64";        break;
1725      case lir_unpack64:              s = "unpack64";      break;
1726      // LIR_Op2
1727      case lir_cmp:                   s = "cmp";           break;
1728      case lir_cmp_l2i:               s = "cmp_l2i";       break;
1729      case lir_ucmp_fd2i:             s = "ucomp_fd2i";    break;
1730      case lir_cmp_fd2i:              s = "comp_fd2i";     break;
1731      case lir_cmove:                 s = "cmove";         break;
1732      case lir_add:                   s = "add";           break;
1733      case lir_sub:                   s = "sub";           break;
1734      case lir_mul:                   s = "mul";           break;
1735      case lir_mul_strictfp:          s = "mul_strictfp";  break;
1736      case lir_div:                   s = "div";           break;
1737      case lir_div_strictfp:          s = "div_strictfp";  break;
1738      case lir_rem:                   s = "rem";           break;
1739      case lir_abs:                   s = "abs";           break;
1740      case lir_sqrt:                  s = "sqrt";          break;
1741      case lir_tan:                   s = "tan";           break;
1742      case lir_log10:                 s = "log10";         break;
1743      case lir_logic_and:             s = "logic_and";     break;
1744      case lir_logic_or:              s = "logic_or";      break;
1745      case lir_logic_xor:             s = "logic_xor";     break;
1746      case lir_shl:                   s = "shift_left";    break;
1747      case lir_shr:                   s = "shift_right";   break;
1748      case lir_ushr:                  s = "ushift_right";  break;
1749      case lir_alloc_array:           s = "alloc_array";   break;
1750      case lir_xadd:                  s = "xadd";          break;
1751      case lir_xchg:                  s = "xchg";          break;
1752      // LIR_Op3
1753      case lir_idiv:                  s = "idiv";          break;
1754      case lir_irem:                  s = "irem";          break;
1755      // LIR_OpJavaCall
1756      case lir_static_call:           s = "static";        break;
1757      case lir_optvirtual_call:       s = "optvirtual";    break;
1758      case lir_icvirtual_call:        s = "icvirtual";     break;
1759      case lir_virtual_call:          s = "virtual";       break;
1760      case lir_dynamic_call:          s = "dynamic";       break;
1761      // LIR_OpArrayCopy
1762      case lir_arraycopy:             s = "arraycopy";     break;




 710       if (op2->_opr1->is_valid())         do_temp(op2->_opr1);
 711       if (op2->_opr2->is_valid())         do_input(op2->_opr2); // exception object is input parameter
 712       assert(op2->_result->is_illegal(), "no result");
 713       assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
 714              op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
 715 
 716       break;
 717     }
 718 
 719     case lir_unwind: {
 720       assert(op->as_Op1() != NULL, "must be");
 721       LIR_Op1* op1 = (LIR_Op1*)op;
 722 
 723       assert(op1->_info == NULL, "no info");
 724       assert(op1->_opr->is_valid(), "exception oop");         do_input(op1->_opr);
 725       assert(op1->_result->is_illegal(), "no result");
 726 
 727       break;
 728     }
 729 

























 730 // LIR_Op3
 731     case lir_idiv:
 732     case lir_irem: {
 733       assert(op->as_Op3() != NULL, "must be");
 734       LIR_Op3* op3= (LIR_Op3*)op;
 735 
 736       if (op3->_info)                     do_info(op3->_info);
 737       if (op3->_opr1->is_valid())         do_input(op3->_opr1);
 738 
 739       // second operand is input and temp, so ensure that second operand
 740       // and third operand get not the same register
 741       if (op3->_opr2->is_valid())         do_input(op3->_opr2);
 742       if (op3->_opr2->is_valid())         do_temp(op3->_opr2);
 743       if (op3->_opr3->is_valid())         do_temp(op3->_opr3);
 744 
 745       if (op3->_result->is_valid())       do_output(op3->_result);
 746 
 747       break;
 748     }
 749 


1696      case lir_convert:               s = "convert";       break;
1697      case lir_alloc_object:          s = "alloc_obj";     break;
1698      case lir_monaddr:               s = "mon_addr";      break;
1699      case lir_pack64:                s = "pack64";        break;
1700      case lir_unpack64:              s = "unpack64";      break;
1701      // LIR_Op2
1702      case lir_cmp:                   s = "cmp";           break;
1703      case lir_cmp_l2i:               s = "cmp_l2i";       break;
1704      case lir_ucmp_fd2i:             s = "ucomp_fd2i";    break;
1705      case lir_cmp_fd2i:              s = "comp_fd2i";     break;
1706      case lir_cmove:                 s = "cmove";         break;
1707      case lir_add:                   s = "add";           break;
1708      case lir_sub:                   s = "sub";           break;
1709      case lir_mul:                   s = "mul";           break;
1710      case lir_mul_strictfp:          s = "mul_strictfp";  break;
1711      case lir_div:                   s = "div";           break;
1712      case lir_div_strictfp:          s = "div_strictfp";  break;
1713      case lir_rem:                   s = "rem";           break;
1714      case lir_abs:                   s = "abs";           break;
1715      case lir_sqrt:                  s = "sqrt";          break;


1716      case lir_logic_and:             s = "logic_and";     break;
1717      case lir_logic_or:              s = "logic_or";      break;
1718      case lir_logic_xor:             s = "logic_xor";     break;
1719      case lir_shl:                   s = "shift_left";    break;
1720      case lir_shr:                   s = "shift_right";   break;
1721      case lir_ushr:                  s = "ushift_right";  break;
1722      case lir_alloc_array:           s = "alloc_array";   break;
1723      case lir_xadd:                  s = "xadd";          break;
1724      case lir_xchg:                  s = "xchg";          break;
1725      // LIR_Op3
1726      case lir_idiv:                  s = "idiv";          break;
1727      case lir_irem:                  s = "irem";          break;
1728      // LIR_OpJavaCall
1729      case lir_static_call:           s = "static";        break;
1730      case lir_optvirtual_call:       s = "optvirtual";    break;
1731      case lir_icvirtual_call:        s = "icvirtual";     break;
1732      case lir_virtual_call:          s = "virtual";       break;
1733      case lir_dynamic_call:          s = "dynamic";       break;
1734      // LIR_OpArrayCopy
1735      case lir_arraycopy:             s = "arraycopy";     break;


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