1 /* 2 * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "asm/assembler.hpp" 27 #include "asm/assembler.inline.hpp" 28 #include "gc/shared/cardTableBarrierSet.hpp" 29 #include "gc/shared/collectedHeap.inline.hpp" 30 #include "interpreter/interpreter.hpp" 31 #include "memory/resourceArea.hpp" 32 #include "prims/methodHandles.hpp" 33 #include "runtime/biasedLocking.hpp" 34 #include "runtime/objectMonitor.hpp" 35 #include "runtime/os.hpp" 36 #include "runtime/sharedRuntime.hpp" 37 #include "runtime/stubRoutines.hpp" 38 #include "utilities/macros.hpp" 39 40 #ifdef PRODUCT 41 #define BLOCK_COMMENT(str) /* nothing */ 42 #define STOP(error) stop(error) 43 #else 44 #define BLOCK_COMMENT(str) block_comment(str) 45 #define STOP(error) block_comment(error); stop(error) 46 #endif 47 48 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":") 49 // Implementation of AddressLiteral 50 51 // A 2-D table for managing compressed displacement(disp8) on EVEX enabled platforms. 52 unsigned char tuple_table[Assembler::EVEX_ETUP + 1][Assembler::AVX_512bit + 1] = { 53 // -----------------Table 4.5 -------------------- // 54 16, 32, 64, // EVEX_FV(0) 55 4, 4, 4, // EVEX_FV(1) - with Evex.b 56 16, 32, 64, // EVEX_FV(2) - with Evex.w 57 8, 8, 8, // EVEX_FV(3) - with Evex.w and Evex.b 58 8, 16, 32, // EVEX_HV(0) 59 4, 4, 4, // EVEX_HV(1) - with Evex.b 60 // -----------------Table 4.6 -------------------- // 61 16, 32, 64, // EVEX_FVM(0) 62 1, 1, 1, // EVEX_T1S(0) 63 2, 2, 2, // EVEX_T1S(1) 64 4, 4, 4, // EVEX_T1S(2) 65 8, 8, 8, // EVEX_T1S(3) 66 4, 4, 4, // EVEX_T1F(0) 67 8, 8, 8, // EVEX_T1F(1) 68 8, 8, 8, // EVEX_T2(0) 69 0, 16, 16, // EVEX_T2(1) 70 0, 16, 16, // EVEX_T4(0) 71 0, 0, 32, // EVEX_T4(1) 72 0, 0, 32, // EVEX_T8(0) 73 8, 16, 32, // EVEX_HVM(0) 74 4, 8, 16, // EVEX_QVM(0) 75 2, 4, 8, // EVEX_OVM(0) 76 16, 16, 16, // EVEX_M128(0) 77 8, 32, 64, // EVEX_DUP(0) 78 0, 0, 0 // EVEX_NTUP 79 }; 80 81 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) { 82 _is_lval = false; 83 _target = target; 84 switch (rtype) { 85 case relocInfo::oop_type: 86 case relocInfo::metadata_type: 87 // Oops are a special case. Normally they would be their own section 88 // but in cases like icBuffer they are literals in the code stream that 89 // we don't have a section for. We use none so that we get a literal address 90 // which is always patchable. 91 break; 92 case relocInfo::external_word_type: 93 _rspec = external_word_Relocation::spec(target); 94 break; 95 case relocInfo::internal_word_type: 96 _rspec = internal_word_Relocation::spec(target); 97 break; 98 case relocInfo::opt_virtual_call_type: 99 _rspec = opt_virtual_call_Relocation::spec(); 100 break; 101 case relocInfo::static_call_type: 102 _rspec = static_call_Relocation::spec(); 103 break; 104 case relocInfo::runtime_call_type: 105 _rspec = runtime_call_Relocation::spec(); 106 break; 107 case relocInfo::poll_type: 108 case relocInfo::poll_return_type: 109 _rspec = Relocation::spec_simple(rtype); 110 break; 111 case relocInfo::none: 112 break; 113 default: 114 ShouldNotReachHere(); 115 break; 116 } 117 } 118 119 // Implementation of Address 120 121 #ifdef _LP64 122 123 Address Address::make_array(ArrayAddress adr) { 124 // Not implementable on 64bit machines 125 // Should have been handled higher up the call chain. 126 ShouldNotReachHere(); 127 return Address(); 128 } 129 130 // exceedingly dangerous constructor 131 Address::Address(int disp, address loc, relocInfo::relocType rtype) { 132 _base = noreg; 133 _index = noreg; 134 _scale = no_scale; 135 _disp = disp; 136 _xmmindex = xnoreg; 137 _isxmmindex = false; 138 switch (rtype) { 139 case relocInfo::external_word_type: 140 _rspec = external_word_Relocation::spec(loc); 141 break; 142 case relocInfo::internal_word_type: 143 _rspec = internal_word_Relocation::spec(loc); 144 break; 145 case relocInfo::runtime_call_type: 146 // HMM 147 _rspec = runtime_call_Relocation::spec(); 148 break; 149 case relocInfo::poll_type: 150 case relocInfo::poll_return_type: 151 _rspec = Relocation::spec_simple(rtype); 152 break; 153 case relocInfo::none: 154 break; 155 default: 156 ShouldNotReachHere(); 157 } 158 } 159 #else // LP64 160 161 Address Address::make_array(ArrayAddress adr) { 162 AddressLiteral base = adr.base(); 163 Address index = adr.index(); 164 assert(index._disp == 0, "must not have disp"); // maybe it can? 165 Address array(index._base, index._index, index._scale, (intptr_t) base.target()); 166 array._rspec = base._rspec; 167 return array; 168 } 169 170 // exceedingly dangerous constructor 171 Address::Address(address loc, RelocationHolder spec) { 172 _base = noreg; 173 _index = noreg; 174 _scale = no_scale; 175 _disp = (intptr_t) loc; 176 _rspec = spec; 177 _xmmindex = xnoreg; 178 _isxmmindex = false; 179 } 180 181 #endif // _LP64 182 183 184 185 // Convert the raw encoding form into the form expected by the constructor for 186 // Address. An index of 4 (rsp) corresponds to having no index, so convert 187 // that to noreg for the Address constructor. 188 Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) { 189 RelocationHolder rspec; 190 if (disp_reloc != relocInfo::none) { 191 rspec = Relocation::spec_simple(disp_reloc); 192 } 193 bool valid_index = index != rsp->encoding(); 194 if (valid_index) { 195 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp)); 196 madr._rspec = rspec; 197 return madr; 198 } else { 199 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp)); 200 madr._rspec = rspec; 201 return madr; 202 } 203 } 204 205 // Implementation of Assembler 206 207 int AbstractAssembler::code_fill_byte() { 208 return (u_char)'\xF4'; // hlt 209 } 210 211 // make this go away someday 212 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) { 213 if (rtype == relocInfo::none) 214 emit_int32(data); 215 else 216 emit_data(data, Relocation::spec_simple(rtype), format); 217 } 218 219 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) { 220 assert(imm_operand == 0, "default format must be immediate in this file"); 221 assert(inst_mark() != NULL, "must be inside InstructionMark"); 222 if (rspec.type() != relocInfo::none) { 223 #ifdef ASSERT 224 check_relocation(rspec, format); 225 #endif 226 // Do not use AbstractAssembler::relocate, which is not intended for 227 // embedded words. Instead, relocate to the enclosing instruction. 228 229 // hack. call32 is too wide for mask so use disp32 230 if (format == call32_operand) 231 code_section()->relocate(inst_mark(), rspec, disp32_operand); 232 else 233 code_section()->relocate(inst_mark(), rspec, format); 234 } 235 emit_int32(data); 236 } 237 238 static int encode(Register r) { 239 int enc = r->encoding(); 240 if (enc >= 8) { 241 enc -= 8; 242 } 243 return enc; 244 } 245 246 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) { 247 assert(dst->has_byte_register(), "must have byte register"); 248 assert(isByte(op1) && isByte(op2), "wrong opcode"); 249 assert(isByte(imm8), "not a byte"); 250 assert((op1 & 0x01) == 0, "should be 8bit operation"); 251 emit_int8(op1); 252 emit_int8(op2 | encode(dst)); 253 emit_int8(imm8); 254 } 255 256 257 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) { 258 assert(isByte(op1) && isByte(op2), "wrong opcode"); 259 assert((op1 & 0x01) == 1, "should be 32bit operation"); 260 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); 261 if (is8bit(imm32)) { 262 emit_int8(op1 | 0x02); // set sign bit 263 emit_int8(op2 | encode(dst)); 264 emit_int8(imm32 & 0xFF); 265 } else { 266 emit_int8(op1); 267 emit_int8(op2 | encode(dst)); 268 emit_int32(imm32); 269 } 270 } 271 272 // Force generation of a 4 byte immediate value even if it fits into 8bit 273 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) { 274 assert(isByte(op1) && isByte(op2), "wrong opcode"); 275 assert((op1 & 0x01) == 1, "should be 32bit operation"); 276 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); 277 emit_int8(op1); 278 emit_int8(op2 | encode(dst)); 279 emit_int32(imm32); 280 } 281 282 // immediate-to-memory forms 283 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) { 284 assert((op1 & 0x01) == 1, "should be 32bit operation"); 285 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); 286 if (is8bit(imm32)) { 287 emit_int8(op1 | 0x02); // set sign bit 288 emit_operand(rm, adr, 1); 289 emit_int8(imm32 & 0xFF); 290 } else { 291 emit_int8(op1); 292 emit_operand(rm, adr, 4); 293 emit_int32(imm32); 294 } 295 } 296 297 298 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) { 299 assert(isByte(op1) && isByte(op2), "wrong opcode"); 300 emit_int8(op1); 301 emit_int8(op2 | encode(dst) << 3 | encode(src)); 302 } 303 304 305 bool Assembler::query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len, 306 int cur_tuple_type, int in_size_in_bits, int cur_encoding) { 307 int mod_idx = 0; 308 // We will test if the displacement fits the compressed format and if so 309 // apply the compression to the displacment iff the result is8bit. 310 if (VM_Version::supports_evex() && is_evex_inst) { 311 switch (cur_tuple_type) { 312 case EVEX_FV: 313 if ((cur_encoding & VEX_W) == VEX_W) { 314 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2; 315 } else { 316 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0; 317 } 318 break; 319 320 case EVEX_HV: 321 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0; 322 break; 323 324 case EVEX_FVM: 325 break; 326 327 case EVEX_T1S: 328 switch (in_size_in_bits) { 329 case EVEX_8bit: 330 break; 331 332 case EVEX_16bit: 333 mod_idx = 1; 334 break; 335 336 case EVEX_32bit: 337 mod_idx = 2; 338 break; 339 340 case EVEX_64bit: 341 mod_idx = 3; 342 break; 343 } 344 break; 345 346 case EVEX_T1F: 347 case EVEX_T2: 348 case EVEX_T4: 349 mod_idx = (in_size_in_bits == EVEX_64bit) ? 1 : 0; 350 break; 351 352 case EVEX_T8: 353 break; 354 355 case EVEX_HVM: 356 break; 357 358 case EVEX_QVM: 359 break; 360 361 case EVEX_OVM: 362 break; 363 364 case EVEX_M128: 365 break; 366 367 case EVEX_DUP: 368 break; 369 370 default: 371 assert(0, "no valid evex tuple_table entry"); 372 break; 373 } 374 375 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) { 376 int disp_factor = tuple_table[cur_tuple_type + mod_idx][vector_len]; 377 if ((disp % disp_factor) == 0) { 378 int new_disp = disp / disp_factor; 379 if ((-0x80 <= new_disp && new_disp < 0x80)) { 380 disp = new_disp; 381 } 382 } else { 383 return false; 384 } 385 } 386 } 387 return (-0x80 <= disp && disp < 0x80); 388 } 389 390 391 bool Assembler::emit_compressed_disp_byte(int &disp) { 392 int mod_idx = 0; 393 // We will test if the displacement fits the compressed format and if so 394 // apply the compression to the displacment iff the result is8bit. 395 if (VM_Version::supports_evex() && _attributes && _attributes->is_evex_instruction()) { 396 int evex_encoding = _attributes->get_evex_encoding(); 397 int tuple_type = _attributes->get_tuple_type(); 398 switch (tuple_type) { 399 case EVEX_FV: 400 if ((evex_encoding & VEX_W) == VEX_W) { 401 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2; 402 } else { 403 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0; 404 } 405 break; 406 407 case EVEX_HV: 408 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0; 409 break; 410 411 case EVEX_FVM: 412 break; 413 414 case EVEX_T1S: 415 switch (_attributes->get_input_size()) { 416 case EVEX_8bit: 417 break; 418 419 case EVEX_16bit: 420 mod_idx = 1; 421 break; 422 423 case EVEX_32bit: 424 mod_idx = 2; 425 break; 426 427 case EVEX_64bit: 428 mod_idx = 3; 429 break; 430 } 431 break; 432 433 case EVEX_T1F: 434 case EVEX_T2: 435 case EVEX_T4: 436 mod_idx = (_attributes->get_input_size() == EVEX_64bit) ? 1 : 0; 437 break; 438 439 case EVEX_T8: 440 break; 441 442 case EVEX_HVM: 443 break; 444 445 case EVEX_QVM: 446 break; 447 448 case EVEX_OVM: 449 break; 450 451 case EVEX_M128: 452 break; 453 454 case EVEX_DUP: 455 break; 456 457 default: 458 assert(0, "no valid evex tuple_table entry"); 459 break; 460 } 461 462 int vector_len = _attributes->get_vector_len(); 463 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) { 464 int disp_factor = tuple_table[tuple_type + mod_idx][vector_len]; 465 if ((disp % disp_factor) == 0) { 466 int new_disp = disp / disp_factor; 467 if (is8bit(new_disp)) { 468 disp = new_disp; 469 } 470 } else { 471 return false; 472 } 473 } 474 } 475 return is8bit(disp); 476 } 477 478 479 void Assembler::emit_operand(Register reg, Register base, Register index, 480 Address::ScaleFactor scale, int disp, 481 RelocationHolder const& rspec, 482 int rip_relative_correction) { 483 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type(); 484 485 // Encode the registers as needed in the fields they are used in 486 487 int regenc = encode(reg) << 3; 488 int indexenc = index->is_valid() ? encode(index) << 3 : 0; 489 int baseenc = base->is_valid() ? encode(base) : 0; 490 491 if (base->is_valid()) { 492 if (index->is_valid()) { 493 assert(scale != Address::no_scale, "inconsistent address"); 494 // [base + index*scale + disp] 495 if (disp == 0 && rtype == relocInfo::none && 496 base != rbp LP64_ONLY(&& base != r13)) { 497 // [base + index*scale] 498 // [00 reg 100][ss index base] 499 assert(index != rsp, "illegal addressing mode"); 500 emit_int8(0x04 | regenc); 501 emit_int8(scale << 6 | indexenc | baseenc); 502 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) { 503 // [base + index*scale + imm8] 504 // [01 reg 100][ss index base] imm8 505 assert(index != rsp, "illegal addressing mode"); 506 emit_int8(0x44 | regenc); 507 emit_int8(scale << 6 | indexenc | baseenc); 508 emit_int8(disp & 0xFF); 509 } else { 510 // [base + index*scale + disp32] 511 // [10 reg 100][ss index base] disp32 512 assert(index != rsp, "illegal addressing mode"); 513 emit_int8(0x84 | regenc); 514 emit_int8(scale << 6 | indexenc | baseenc); 515 emit_data(disp, rspec, disp32_operand); 516 } 517 } else if (base == rsp LP64_ONLY(|| base == r12)) { 518 // [rsp + disp] 519 if (disp == 0 && rtype == relocInfo::none) { 520 // [rsp] 521 // [00 reg 100][00 100 100] 522 emit_int8(0x04 | regenc); 523 emit_int8(0x24); 524 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) { 525 // [rsp + imm8] 526 // [01 reg 100][00 100 100] disp8 527 emit_int8(0x44 | regenc); 528 emit_int8(0x24); 529 emit_int8(disp & 0xFF); 530 } else { 531 // [rsp + imm32] 532 // [10 reg 100][00 100 100] disp32 533 emit_int8(0x84 | regenc); 534 emit_int8(0x24); 535 emit_data(disp, rspec, disp32_operand); 536 } 537 } else { 538 // [base + disp] 539 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode"); 540 if (disp == 0 && rtype == relocInfo::none && 541 base != rbp LP64_ONLY(&& base != r13)) { 542 // [base] 543 // [00 reg base] 544 emit_int8(0x00 | regenc | baseenc); 545 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) { 546 // [base + disp8] 547 // [01 reg base] disp8 548 emit_int8(0x40 | regenc | baseenc); 549 emit_int8(disp & 0xFF); 550 } else { 551 // [base + disp32] 552 // [10 reg base] disp32 553 emit_int8(0x80 | regenc | baseenc); 554 emit_data(disp, rspec, disp32_operand); 555 } 556 } 557 } else { 558 if (index->is_valid()) { 559 assert(scale != Address::no_scale, "inconsistent address"); 560 // [index*scale + disp] 561 // [00 reg 100][ss index 101] disp32 562 assert(index != rsp, "illegal addressing mode"); 563 emit_int8(0x04 | regenc); 564 emit_int8(scale << 6 | indexenc | 0x05); 565 emit_data(disp, rspec, disp32_operand); 566 } else if (rtype != relocInfo::none ) { 567 // [disp] (64bit) RIP-RELATIVE (32bit) abs 568 // [00 000 101] disp32 569 570 emit_int8(0x05 | regenc); 571 // Note that the RIP-rel. correction applies to the generated 572 // disp field, but _not_ to the target address in the rspec. 573 574 // disp was created by converting the target address minus the pc 575 // at the start of the instruction. That needs more correction here. 576 // intptr_t disp = target - next_ip; 577 assert(inst_mark() != NULL, "must be inside InstructionMark"); 578 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction; 579 int64_t adjusted = disp; 580 // Do rip-rel adjustment for 64bit 581 LP64_ONLY(adjusted -= (next_ip - inst_mark())); 582 assert(is_simm32(adjusted), 583 "must be 32bit offset (RIP relative address)"); 584 emit_data((int32_t) adjusted, rspec, disp32_operand); 585 586 } else { 587 // 32bit never did this, did everything as the rip-rel/disp code above 588 // [disp] ABSOLUTE 589 // [00 reg 100][00 100 101] disp32 590 emit_int8(0x04 | regenc); 591 emit_int8(0x25); 592 emit_data(disp, rspec, disp32_operand); 593 } 594 } 595 } 596 597 void Assembler::emit_operand(XMMRegister reg, Register base, Register index, 598 Address::ScaleFactor scale, int disp, 599 RelocationHolder const& rspec) { 600 if (UseAVX > 2) { 601 int xreg_enc = reg->encoding(); 602 if (xreg_enc > 15) { 603 XMMRegister new_reg = as_XMMRegister(xreg_enc & 0xf); 604 emit_operand((Register)new_reg, base, index, scale, disp, rspec); 605 return; 606 } 607 } 608 emit_operand((Register)reg, base, index, scale, disp, rspec); 609 } 610 611 void Assembler::emit_operand(XMMRegister reg, Register base, XMMRegister index, 612 Address::ScaleFactor scale, int disp, 613 RelocationHolder const& rspec) { 614 if (UseAVX > 2) { 615 int xreg_enc = reg->encoding(); 616 int xmmindex_enc = index->encoding(); 617 XMMRegister new_reg = as_XMMRegister(xreg_enc & 0xf); 618 XMMRegister new_index = as_XMMRegister(xmmindex_enc & 0xf); 619 emit_operand((Register)new_reg, base, (Register)new_index, scale, disp, rspec); 620 } else { 621 emit_operand((Register)reg, base, (Register)index, scale, disp, rspec); 622 } 623 } 624 625 626 // Secret local extension to Assembler::WhichOperand: 627 #define end_pc_operand (_WhichOperand_limit) 628 629 address Assembler::locate_operand(address inst, WhichOperand which) { 630 // Decode the given instruction, and return the address of 631 // an embedded 32-bit operand word. 632 633 // If "which" is disp32_operand, selects the displacement portion 634 // of an effective address specifier. 635 // If "which" is imm64_operand, selects the trailing immediate constant. 636 // If "which" is call32_operand, selects the displacement of a call or jump. 637 // Caller is responsible for ensuring that there is such an operand, 638 // and that it is 32/64 bits wide. 639 640 // If "which" is end_pc_operand, find the end of the instruction. 641 642 address ip = inst; 643 bool is_64bit = false; 644 645 debug_only(bool has_disp32 = false); 646 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn 647 648 again_after_prefix: 649 switch (0xFF & *ip++) { 650 651 // These convenience macros generate groups of "case" labels for the switch. 652 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3 653 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \ 654 case (x)+4: case (x)+5: case (x)+6: case (x)+7 655 #define REP16(x) REP8((x)+0): \ 656 case REP8((x)+8) 657 658 case CS_segment: 659 case SS_segment: 660 case DS_segment: 661 case ES_segment: 662 case FS_segment: 663 case GS_segment: 664 // Seems dubious 665 LP64_ONLY(assert(false, "shouldn't have that prefix")); 666 assert(ip == inst+1, "only one prefix allowed"); 667 goto again_after_prefix; 668 669 case 0x67: 670 case REX: 671 case REX_B: 672 case REX_X: 673 case REX_XB: 674 case REX_R: 675 case REX_RB: 676 case REX_RX: 677 case REX_RXB: 678 NOT_LP64(assert(false, "64bit prefixes")); 679 goto again_after_prefix; 680 681 case REX_W: 682 case REX_WB: 683 case REX_WX: 684 case REX_WXB: 685 case REX_WR: 686 case REX_WRB: 687 case REX_WRX: 688 case REX_WRXB: 689 NOT_LP64(assert(false, "64bit prefixes")); 690 is_64bit = true; 691 goto again_after_prefix; 692 693 case 0xFF: // pushq a; decl a; incl a; call a; jmp a 694 case 0x88: // movb a, r 695 case 0x89: // movl a, r 696 case 0x8A: // movb r, a 697 case 0x8B: // movl r, a 698 case 0x8F: // popl a 699 debug_only(has_disp32 = true); 700 break; 701 702 case 0x68: // pushq #32 703 if (which == end_pc_operand) { 704 return ip + 4; 705 } 706 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate"); 707 return ip; // not produced by emit_operand 708 709 case 0x66: // movw ... (size prefix) 710 again_after_size_prefix2: 711 switch (0xFF & *ip++) { 712 case REX: 713 case REX_B: 714 case REX_X: 715 case REX_XB: 716 case REX_R: 717 case REX_RB: 718 case REX_RX: 719 case REX_RXB: 720 case REX_W: 721 case REX_WB: 722 case REX_WX: 723 case REX_WXB: 724 case REX_WR: 725 case REX_WRB: 726 case REX_WRX: 727 case REX_WRXB: 728 NOT_LP64(assert(false, "64bit prefix found")); 729 goto again_after_size_prefix2; 730 case 0x8B: // movw r, a 731 case 0x89: // movw a, r 732 debug_only(has_disp32 = true); 733 break; 734 case 0xC7: // movw a, #16 735 debug_only(has_disp32 = true); 736 tail_size = 2; // the imm16 737 break; 738 case 0x0F: // several SSE/SSE2 variants 739 ip--; // reparse the 0x0F 740 goto again_after_prefix; 741 default: 742 ShouldNotReachHere(); 743 } 744 break; 745 746 case REP8(0xB8): // movl/q r, #32/#64(oop?) 747 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4); 748 // these asserts are somewhat nonsensical 749 #ifndef _LP64 750 assert(which == imm_operand || which == disp32_operand, 751 "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip)); 752 #else 753 assert((which == call32_operand || which == imm_operand) && is_64bit || 754 which == narrow_oop_operand && !is_64bit, 755 "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip)); 756 #endif // _LP64 757 return ip; 758 759 case 0x69: // imul r, a, #32 760 case 0xC7: // movl a, #32(oop?) 761 tail_size = 4; 762 debug_only(has_disp32 = true); // has both kinds of operands! 763 break; 764 765 case 0x0F: // movx..., etc. 766 switch (0xFF & *ip++) { 767 case 0x3A: // pcmpestri 768 tail_size = 1; 769 case 0x38: // ptest, pmovzxbw 770 ip++; // skip opcode 771 debug_only(has_disp32 = true); // has both kinds of operands! 772 break; 773 774 case 0x70: // pshufd r, r/a, #8 775 debug_only(has_disp32 = true); // has both kinds of operands! 776 case 0x73: // psrldq r, #8 777 tail_size = 1; 778 break; 779 780 case 0x12: // movlps 781 case 0x28: // movaps 782 case 0x2E: // ucomiss 783 case 0x2F: // comiss 784 case 0x54: // andps 785 case 0x55: // andnps 786 case 0x56: // orps 787 case 0x57: // xorps 788 case 0x58: // addpd 789 case 0x59: // mulpd 790 case 0x6E: // movd 791 case 0x7E: // movd 792 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush 793 case 0xFE: // paddd 794 debug_only(has_disp32 = true); 795 break; 796 797 case 0xAD: // shrd r, a, %cl 798 case 0xAF: // imul r, a 799 case 0xBE: // movsbl r, a (movsxb) 800 case 0xBF: // movswl r, a (movsxw) 801 case 0xB6: // movzbl r, a (movzxb) 802 case 0xB7: // movzwl r, a (movzxw) 803 case REP16(0x40): // cmovl cc, r, a 804 case 0xB0: // cmpxchgb 805 case 0xB1: // cmpxchg 806 case 0xC1: // xaddl 807 case 0xC7: // cmpxchg8 808 case REP16(0x90): // setcc a 809 debug_only(has_disp32 = true); 810 // fall out of the switch to decode the address 811 break; 812 813 case 0xC4: // pinsrw r, a, #8 814 debug_only(has_disp32 = true); 815 case 0xC5: // pextrw r, r, #8 816 tail_size = 1; // the imm8 817 break; 818 819 case 0xAC: // shrd r, a, #8 820 debug_only(has_disp32 = true); 821 tail_size = 1; // the imm8 822 break; 823 824 case REP16(0x80): // jcc rdisp32 825 if (which == end_pc_operand) return ip + 4; 826 assert(which == call32_operand, "jcc has no disp32 or imm"); 827 return ip; 828 default: 829 ShouldNotReachHere(); 830 } 831 break; 832 833 case 0x81: // addl a, #32; addl r, #32 834 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl 835 // on 32bit in the case of cmpl, the imm might be an oop 836 tail_size = 4; 837 debug_only(has_disp32 = true); // has both kinds of operands! 838 break; 839 840 case 0x83: // addl a, #8; addl r, #8 841 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl 842 debug_only(has_disp32 = true); // has both kinds of operands! 843 tail_size = 1; 844 break; 845 846 case 0x9B: 847 switch (0xFF & *ip++) { 848 case 0xD9: // fnstcw a 849 debug_only(has_disp32 = true); 850 break; 851 default: 852 ShouldNotReachHere(); 853 } 854 break; 855 856 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a 857 case REP4(0x10): // adc... 858 case REP4(0x20): // and... 859 case REP4(0x30): // xor... 860 case REP4(0x08): // or... 861 case REP4(0x18): // sbb... 862 case REP4(0x28): // sub... 863 case 0xF7: // mull a 864 case 0x8D: // lea r, a 865 case 0x87: // xchg r, a 866 case REP4(0x38): // cmp... 867 case 0x85: // test r, a 868 debug_only(has_disp32 = true); // has both kinds of operands! 869 break; 870 871 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8 872 case 0xC6: // movb a, #8 873 case 0x80: // cmpb a, #8 874 case 0x6B: // imul r, a, #8 875 debug_only(has_disp32 = true); // has both kinds of operands! 876 tail_size = 1; // the imm8 877 break; 878 879 case 0xC4: // VEX_3bytes 880 case 0xC5: // VEX_2bytes 881 assert((UseAVX > 0), "shouldn't have VEX prefix"); 882 assert(ip == inst+1, "no prefixes allowed"); 883 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions 884 // but they have prefix 0x0F and processed when 0x0F processed above. 885 // 886 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES 887 // instructions (these instructions are not supported in 64-bit mode). 888 // To distinguish them bits [7:6] are set in the VEX second byte since 889 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set 890 // those VEX bits REX and vvvv bits are inverted. 891 // 892 // Fortunately C2 doesn't generate these instructions so we don't need 893 // to check for them in product version. 894 895 // Check second byte 896 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions")); 897 898 int vex_opcode; 899 // First byte 900 if ((0xFF & *inst) == VEX_3bytes) { 901 vex_opcode = VEX_OPCODE_MASK & *ip; 902 ip++; // third byte 903 is_64bit = ((VEX_W & *ip) == VEX_W); 904 } else { 905 vex_opcode = VEX_OPCODE_0F; 906 } 907 ip++; // opcode 908 // To find the end of instruction (which == end_pc_operand). 909 switch (vex_opcode) { 910 case VEX_OPCODE_0F: 911 switch (0xFF & *ip) { 912 case 0x70: // pshufd r, r/a, #8 913 case 0x71: // ps[rl|ra|ll]w r, #8 914 case 0x72: // ps[rl|ra|ll]d r, #8 915 case 0x73: // ps[rl|ra|ll]q r, #8 916 case 0xC2: // cmp[ps|pd|ss|sd] r, r, r/a, #8 917 case 0xC4: // pinsrw r, r, r/a, #8 918 case 0xC5: // pextrw r/a, r, #8 919 case 0xC6: // shufp[s|d] r, r, r/a, #8 920 tail_size = 1; // the imm8 921 break; 922 } 923 break; 924 case VEX_OPCODE_0F_3A: 925 tail_size = 1; 926 break; 927 } 928 ip++; // skip opcode 929 debug_only(has_disp32 = true); // has both kinds of operands! 930 break; 931 932 case 0x62: // EVEX_4bytes 933 assert(VM_Version::supports_evex(), "shouldn't have EVEX prefix"); 934 assert(ip == inst+1, "no prefixes allowed"); 935 // no EVEX collisions, all instructions that have 0x62 opcodes 936 // have EVEX versions and are subopcodes of 0x66 937 ip++; // skip P0 and exmaine W in P1 938 is_64bit = ((VEX_W & *ip) == VEX_W); 939 ip++; // move to P2 940 ip++; // skip P2, move to opcode 941 // To find the end of instruction (which == end_pc_operand). 942 switch (0xFF & *ip) { 943 case 0x22: // pinsrd r, r/a, #8 944 case 0x61: // pcmpestri r, r/a, #8 945 case 0x70: // pshufd r, r/a, #8 946 case 0x73: // psrldq r, #8 947 tail_size = 1; // the imm8 948 break; 949 default: 950 break; 951 } 952 ip++; // skip opcode 953 debug_only(has_disp32 = true); // has both kinds of operands! 954 break; 955 956 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1 957 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl 958 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a 959 case 0xDD: // fld_d a; fst_d a; fstp_d a 960 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a 961 case 0xDF: // fild_d a; fistp_d a 962 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a 963 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a 964 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a 965 debug_only(has_disp32 = true); 966 break; 967 968 case 0xE8: // call rdisp32 969 case 0xE9: // jmp rdisp32 970 if (which == end_pc_operand) return ip + 4; 971 assert(which == call32_operand, "call has no disp32 or imm"); 972 return ip; 973 974 case 0xF0: // Lock 975 assert(os::is_MP(), "only on MP"); 976 goto again_after_prefix; 977 978 case 0xF3: // For SSE 979 case 0xF2: // For SSE2 980 switch (0xFF & *ip++) { 981 case REX: 982 case REX_B: 983 case REX_X: 984 case REX_XB: 985 case REX_R: 986 case REX_RB: 987 case REX_RX: 988 case REX_RXB: 989 case REX_W: 990 case REX_WB: 991 case REX_WX: 992 case REX_WXB: 993 case REX_WR: 994 case REX_WRB: 995 case REX_WRX: 996 case REX_WRXB: 997 NOT_LP64(assert(false, "found 64bit prefix")); 998 ip++; 999 default: 1000 ip++; 1001 } 1002 debug_only(has_disp32 = true); // has both kinds of operands! 1003 break; 1004 1005 default: 1006 ShouldNotReachHere(); 1007 1008 #undef REP8 1009 #undef REP16 1010 } 1011 1012 assert(which != call32_operand, "instruction is not a call, jmp, or jcc"); 1013 #ifdef _LP64 1014 assert(which != imm_operand, "instruction is not a movq reg, imm64"); 1015 #else 1016 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field"); 1017 assert(which != imm_operand || has_disp32, "instruction has no imm32 field"); 1018 #endif // LP64 1019 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field"); 1020 1021 // parse the output of emit_operand 1022 int op2 = 0xFF & *ip++; 1023 int base = op2 & 0x07; 1024 int op3 = -1; 1025 const int b100 = 4; 1026 const int b101 = 5; 1027 if (base == b100 && (op2 >> 6) != 3) { 1028 op3 = 0xFF & *ip++; 1029 base = op3 & 0x07; // refetch the base 1030 } 1031 // now ip points at the disp (if any) 1032 1033 switch (op2 >> 6) { 1034 case 0: 1035 // [00 reg 100][ss index base] 1036 // [00 reg 100][00 100 esp] 1037 // [00 reg base] 1038 // [00 reg 100][ss index 101][disp32] 1039 // [00 reg 101] [disp32] 1040 1041 if (base == b101) { 1042 if (which == disp32_operand) 1043 return ip; // caller wants the disp32 1044 ip += 4; // skip the disp32 1045 } 1046 break; 1047 1048 case 1: 1049 // [01 reg 100][ss index base][disp8] 1050 // [01 reg 100][00 100 esp][disp8] 1051 // [01 reg base] [disp8] 1052 ip += 1; // skip the disp8 1053 break; 1054 1055 case 2: 1056 // [10 reg 100][ss index base][disp32] 1057 // [10 reg 100][00 100 esp][disp32] 1058 // [10 reg base] [disp32] 1059 if (which == disp32_operand) 1060 return ip; // caller wants the disp32 1061 ip += 4; // skip the disp32 1062 break; 1063 1064 case 3: 1065 // [11 reg base] (not a memory addressing mode) 1066 break; 1067 } 1068 1069 if (which == end_pc_operand) { 1070 return ip + tail_size; 1071 } 1072 1073 #ifdef _LP64 1074 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32"); 1075 #else 1076 assert(which == imm_operand, "instruction has only an imm field"); 1077 #endif // LP64 1078 return ip; 1079 } 1080 1081 address Assembler::locate_next_instruction(address inst) { 1082 // Secretly share code with locate_operand: 1083 return locate_operand(inst, end_pc_operand); 1084 } 1085 1086 1087 #ifdef ASSERT 1088 void Assembler::check_relocation(RelocationHolder const& rspec, int format) { 1089 address inst = inst_mark(); 1090 assert(inst != NULL && inst < pc(), "must point to beginning of instruction"); 1091 address opnd; 1092 1093 Relocation* r = rspec.reloc(); 1094 if (r->type() == relocInfo::none) { 1095 return; 1096 } else if (r->is_call() || format == call32_operand) { 1097 // assert(format == imm32_operand, "cannot specify a nonzero format"); 1098 opnd = locate_operand(inst, call32_operand); 1099 } else if (r->is_data()) { 1100 assert(format == imm_operand || format == disp32_operand 1101 LP64_ONLY(|| format == narrow_oop_operand), "format ok"); 1102 opnd = locate_operand(inst, (WhichOperand)format); 1103 } else { 1104 assert(format == imm_operand, "cannot specify a format"); 1105 return; 1106 } 1107 assert(opnd == pc(), "must put operand where relocs can find it"); 1108 } 1109 #endif // ASSERT 1110 1111 void Assembler::emit_operand32(Register reg, Address adr) { 1112 assert(reg->encoding() < 8, "no extended registers"); 1113 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); 1114 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, 1115 adr._rspec); 1116 } 1117 1118 void Assembler::emit_operand(Register reg, Address adr, 1119 int rip_relative_correction) { 1120 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, 1121 adr._rspec, 1122 rip_relative_correction); 1123 } 1124 1125 void Assembler::emit_operand(XMMRegister reg, Address adr) { 1126 if (adr.isxmmindex()) { 1127 emit_operand(reg, adr._base, adr._xmmindex, adr._scale, adr._disp, adr._rspec); 1128 } else { 1129 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, 1130 adr._rspec); 1131 } 1132 } 1133 1134 // MMX operations 1135 void Assembler::emit_operand(MMXRegister reg, Address adr) { 1136 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); 1137 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec); 1138 } 1139 1140 // work around gcc (3.2.1-7a) bug 1141 void Assembler::emit_operand(Address adr, MMXRegister reg) { 1142 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); 1143 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec); 1144 } 1145 1146 1147 void Assembler::emit_farith(int b1, int b2, int i) { 1148 assert(isByte(b1) && isByte(b2), "wrong opcode"); 1149 assert(0 <= i && i < 8, "illegal stack offset"); 1150 emit_int8(b1); 1151 emit_int8(b2 + i); 1152 } 1153 1154 1155 // Now the Assembler instructions (identical for 32/64 bits) 1156 1157 void Assembler::adcl(Address dst, int32_t imm32) { 1158 InstructionMark im(this); 1159 prefix(dst); 1160 emit_arith_operand(0x81, rdx, dst, imm32); 1161 } 1162 1163 void Assembler::adcl(Address dst, Register src) { 1164 InstructionMark im(this); 1165 prefix(dst, src); 1166 emit_int8(0x11); 1167 emit_operand(src, dst); 1168 } 1169 1170 void Assembler::adcl(Register dst, int32_t imm32) { 1171 prefix(dst); 1172 emit_arith(0x81, 0xD0, dst, imm32); 1173 } 1174 1175 void Assembler::adcl(Register dst, Address src) { 1176 InstructionMark im(this); 1177 prefix(src, dst); 1178 emit_int8(0x13); 1179 emit_operand(dst, src); 1180 } 1181 1182 void Assembler::adcl(Register dst, Register src) { 1183 (void) prefix_and_encode(dst->encoding(), src->encoding()); 1184 emit_arith(0x13, 0xC0, dst, src); 1185 } 1186 1187 void Assembler::addl(Address dst, int32_t imm32) { 1188 InstructionMark im(this); 1189 prefix(dst); 1190 emit_arith_operand(0x81, rax, dst, imm32); 1191 } 1192 1193 void Assembler::addb(Address dst, int imm8) { 1194 InstructionMark im(this); 1195 prefix(dst); 1196 emit_int8((unsigned char)0x80); 1197 emit_operand(rax, dst, 1); 1198 emit_int8(imm8); 1199 } 1200 1201 void Assembler::addw(Address dst, int imm16) { 1202 InstructionMark im(this); 1203 emit_int8(0x66); 1204 prefix(dst); 1205 emit_int8((unsigned char)0x81); 1206 emit_operand(rax, dst, 2); 1207 emit_int16(imm16); 1208 } 1209 1210 void Assembler::addl(Address dst, Register src) { 1211 InstructionMark im(this); 1212 prefix(dst, src); 1213 emit_int8(0x01); 1214 emit_operand(src, dst); 1215 } 1216 1217 void Assembler::addl(Register dst, int32_t imm32) { 1218 prefix(dst); 1219 emit_arith(0x81, 0xC0, dst, imm32); 1220 } 1221 1222 void Assembler::addl(Register dst, Address src) { 1223 InstructionMark im(this); 1224 prefix(src, dst); 1225 emit_int8(0x03); 1226 emit_operand(dst, src); 1227 } 1228 1229 void Assembler::addl(Register dst, Register src) { 1230 (void) prefix_and_encode(dst->encoding(), src->encoding()); 1231 emit_arith(0x03, 0xC0, dst, src); 1232 } 1233 1234 void Assembler::addr_nop_4() { 1235 assert(UseAddressNop, "no CPU support"); 1236 // 4 bytes: NOP DWORD PTR [EAX+0] 1237 emit_int8(0x0F); 1238 emit_int8(0x1F); 1239 emit_int8(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc); 1240 emit_int8(0); // 8-bits offset (1 byte) 1241 } 1242 1243 void Assembler::addr_nop_5() { 1244 assert(UseAddressNop, "no CPU support"); 1245 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset 1246 emit_int8(0x0F); 1247 emit_int8(0x1F); 1248 emit_int8(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4); 1249 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc); 1250 emit_int8(0); // 8-bits offset (1 byte) 1251 } 1252 1253 void Assembler::addr_nop_7() { 1254 assert(UseAddressNop, "no CPU support"); 1255 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset 1256 emit_int8(0x0F); 1257 emit_int8(0x1F); 1258 emit_int8((unsigned char)0x80); 1259 // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc); 1260 emit_int32(0); // 32-bits offset (4 bytes) 1261 } 1262 1263 void Assembler::addr_nop_8() { 1264 assert(UseAddressNop, "no CPU support"); 1265 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset 1266 emit_int8(0x0F); 1267 emit_int8(0x1F); 1268 emit_int8((unsigned char)0x84); 1269 // emit_rm(cbuf, 0x2, EAX_enc, 0x4); 1270 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc); 1271 emit_int32(0); // 32-bits offset (4 bytes) 1272 } 1273 1274 void Assembler::addsd(XMMRegister dst, XMMRegister src) { 1275 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1276 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1277 attributes.set_rex_vex_w_reverted(); 1278 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 1279 emit_int8(0x58); 1280 emit_int8((unsigned char)(0xC0 | encode)); 1281 } 1282 1283 void Assembler::addsd(XMMRegister dst, Address src) { 1284 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1285 InstructionMark im(this); 1286 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1287 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 1288 attributes.set_rex_vex_w_reverted(); 1289 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 1290 emit_int8(0x58); 1291 emit_operand(dst, src); 1292 } 1293 1294 void Assembler::addss(XMMRegister dst, XMMRegister src) { 1295 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1296 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1297 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 1298 emit_int8(0x58); 1299 emit_int8((unsigned char)(0xC0 | encode)); 1300 } 1301 1302 void Assembler::addss(XMMRegister dst, Address src) { 1303 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1304 InstructionMark im(this); 1305 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1306 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 1307 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 1308 emit_int8(0x58); 1309 emit_operand(dst, src); 1310 } 1311 1312 void Assembler::aesdec(XMMRegister dst, Address src) { 1313 assert(VM_Version::supports_aes(), ""); 1314 InstructionMark im(this); 1315 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 1316 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 1317 emit_int8((unsigned char)0xDE); 1318 emit_operand(dst, src); 1319 } 1320 1321 void Assembler::aesdec(XMMRegister dst, XMMRegister src) { 1322 assert(VM_Version::supports_aes(), ""); 1323 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 1324 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 1325 emit_int8((unsigned char)0xDE); 1326 emit_int8(0xC0 | encode); 1327 } 1328 1329 void Assembler::vaesdec(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 1330 assert(VM_Version::supports_vaes(), ""); 1331 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 1332 attributes.set_is_evex_instruction(); 1333 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 1334 emit_int8((unsigned char)0xDE); 1335 emit_int8((unsigned char)(0xC0 | encode)); 1336 } 1337 1338 1339 void Assembler::aesdeclast(XMMRegister dst, Address src) { 1340 assert(VM_Version::supports_aes(), ""); 1341 InstructionMark im(this); 1342 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 1343 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 1344 emit_int8((unsigned char)0xDF); 1345 emit_operand(dst, src); 1346 } 1347 1348 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) { 1349 assert(VM_Version::supports_aes(), ""); 1350 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 1351 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 1352 emit_int8((unsigned char)0xDF); 1353 emit_int8((unsigned char)(0xC0 | encode)); 1354 } 1355 1356 void Assembler::vaesdeclast(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 1357 assert(VM_Version::supports_vaes(), ""); 1358 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 1359 attributes.set_is_evex_instruction(); 1360 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 1361 emit_int8((unsigned char)0xDF); 1362 emit_int8((unsigned char)(0xC0 | encode)); 1363 } 1364 1365 void Assembler::aesenc(XMMRegister dst, Address src) { 1366 assert(VM_Version::supports_aes(), ""); 1367 InstructionMark im(this); 1368 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 1369 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 1370 emit_int8((unsigned char)0xDC); 1371 emit_operand(dst, src); 1372 } 1373 1374 void Assembler::aesenc(XMMRegister dst, XMMRegister src) { 1375 assert(VM_Version::supports_aes(), ""); 1376 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 1377 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 1378 emit_int8((unsigned char)0xDC); 1379 emit_int8(0xC0 | encode); 1380 } 1381 1382 void Assembler::aesenclast(XMMRegister dst, Address src) { 1383 assert(VM_Version::supports_aes(), ""); 1384 InstructionMark im(this); 1385 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 1386 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 1387 emit_int8((unsigned char)0xDD); 1388 emit_operand(dst, src); 1389 } 1390 1391 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) { 1392 assert(VM_Version::supports_aes(), ""); 1393 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 1394 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 1395 emit_int8((unsigned char)0xDD); 1396 emit_int8((unsigned char)(0xC0 | encode)); 1397 } 1398 1399 void Assembler::andl(Address dst, int32_t imm32) { 1400 InstructionMark im(this); 1401 prefix(dst); 1402 emit_int8((unsigned char)0x81); 1403 emit_operand(rsp, dst, 4); 1404 emit_int32(imm32); 1405 } 1406 1407 void Assembler::andl(Register dst, int32_t imm32) { 1408 prefix(dst); 1409 emit_arith(0x81, 0xE0, dst, imm32); 1410 } 1411 1412 void Assembler::andl(Register dst, Address src) { 1413 InstructionMark im(this); 1414 prefix(src, dst); 1415 emit_int8(0x23); 1416 emit_operand(dst, src); 1417 } 1418 1419 void Assembler::andl(Register dst, Register src) { 1420 (void) prefix_and_encode(dst->encoding(), src->encoding()); 1421 emit_arith(0x23, 0xC0, dst, src); 1422 } 1423 1424 void Assembler::andnl(Register dst, Register src1, Register src2) { 1425 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 1426 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 1427 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 1428 emit_int8((unsigned char)0xF2); 1429 emit_int8((unsigned char)(0xC0 | encode)); 1430 } 1431 1432 void Assembler::andnl(Register dst, Register src1, Address src2) { 1433 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 1434 InstructionMark im(this); 1435 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 1436 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 1437 emit_int8((unsigned char)0xF2); 1438 emit_operand(dst, src2); 1439 } 1440 1441 void Assembler::bsfl(Register dst, Register src) { 1442 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 1443 emit_int8(0x0F); 1444 emit_int8((unsigned char)0xBC); 1445 emit_int8((unsigned char)(0xC0 | encode)); 1446 } 1447 1448 void Assembler::bsrl(Register dst, Register src) { 1449 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 1450 emit_int8(0x0F); 1451 emit_int8((unsigned char)0xBD); 1452 emit_int8((unsigned char)(0xC0 | encode)); 1453 } 1454 1455 void Assembler::bswapl(Register reg) { // bswap 1456 int encode = prefix_and_encode(reg->encoding()); 1457 emit_int8(0x0F); 1458 emit_int8((unsigned char)(0xC8 | encode)); 1459 } 1460 1461 void Assembler::blsil(Register dst, Register src) { 1462 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 1463 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 1464 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 1465 emit_int8((unsigned char)0xF3); 1466 emit_int8((unsigned char)(0xC0 | encode)); 1467 } 1468 1469 void Assembler::blsil(Register dst, Address src) { 1470 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 1471 InstructionMark im(this); 1472 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 1473 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 1474 emit_int8((unsigned char)0xF3); 1475 emit_operand(rbx, src); 1476 } 1477 1478 void Assembler::blsmskl(Register dst, Register src) { 1479 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 1480 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 1481 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 1482 emit_int8((unsigned char)0xF3); 1483 emit_int8((unsigned char)(0xC0 | encode)); 1484 } 1485 1486 void Assembler::blsmskl(Register dst, Address src) { 1487 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 1488 InstructionMark im(this); 1489 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 1490 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 1491 emit_int8((unsigned char)0xF3); 1492 emit_operand(rdx, src); 1493 } 1494 1495 void Assembler::blsrl(Register dst, Register src) { 1496 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 1497 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 1498 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 1499 emit_int8((unsigned char)0xF3); 1500 emit_int8((unsigned char)(0xC0 | encode)); 1501 } 1502 1503 void Assembler::blsrl(Register dst, Address src) { 1504 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 1505 InstructionMark im(this); 1506 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 1507 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 1508 emit_int8((unsigned char)0xF3); 1509 emit_operand(rcx, src); 1510 } 1511 1512 void Assembler::call(Label& L, relocInfo::relocType rtype) { 1513 // suspect disp32 is always good 1514 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand); 1515 1516 if (L.is_bound()) { 1517 const int long_size = 5; 1518 int offs = (int)( target(L) - pc() ); 1519 assert(offs <= 0, "assembler error"); 1520 InstructionMark im(this); 1521 // 1110 1000 #32-bit disp 1522 emit_int8((unsigned char)0xE8); 1523 emit_data(offs - long_size, rtype, operand); 1524 } else { 1525 InstructionMark im(this); 1526 // 1110 1000 #32-bit disp 1527 L.add_patch_at(code(), locator()); 1528 1529 emit_int8((unsigned char)0xE8); 1530 emit_data(int(0), rtype, operand); 1531 } 1532 } 1533 1534 void Assembler::call(Register dst) { 1535 int encode = prefix_and_encode(dst->encoding()); 1536 emit_int8((unsigned char)0xFF); 1537 emit_int8((unsigned char)(0xD0 | encode)); 1538 } 1539 1540 1541 void Assembler::call(Address adr) { 1542 InstructionMark im(this); 1543 prefix(adr); 1544 emit_int8((unsigned char)0xFF); 1545 emit_operand(rdx, adr); 1546 } 1547 1548 void Assembler::call_literal(address entry, RelocationHolder const& rspec) { 1549 InstructionMark im(this); 1550 emit_int8((unsigned char)0xE8); 1551 intptr_t disp = entry - (pc() + sizeof(int32_t)); 1552 // Entry is NULL in case of a scratch emit. 1553 assert(entry == NULL || is_simm32(disp), "disp=" INTPTR_FORMAT " must be 32bit offset (call2)", disp); 1554 // Technically, should use call32_operand, but this format is 1555 // implied by the fact that we're emitting a call instruction. 1556 1557 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand); 1558 emit_data((int) disp, rspec, operand); 1559 } 1560 1561 void Assembler::cdql() { 1562 emit_int8((unsigned char)0x99); 1563 } 1564 1565 void Assembler::cld() { 1566 emit_int8((unsigned char)0xFC); 1567 } 1568 1569 void Assembler::cmovl(Condition cc, Register dst, Register src) { 1570 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction")); 1571 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 1572 emit_int8(0x0F); 1573 emit_int8(0x40 | cc); 1574 emit_int8((unsigned char)(0xC0 | encode)); 1575 } 1576 1577 1578 void Assembler::cmovl(Condition cc, Register dst, Address src) { 1579 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction")); 1580 prefix(src, dst); 1581 emit_int8(0x0F); 1582 emit_int8(0x40 | cc); 1583 emit_operand(dst, src); 1584 } 1585 1586 void Assembler::cmpb(Address dst, int imm8) { 1587 InstructionMark im(this); 1588 prefix(dst); 1589 emit_int8((unsigned char)0x80); 1590 emit_operand(rdi, dst, 1); 1591 emit_int8(imm8); 1592 } 1593 1594 void Assembler::cmpl(Address dst, int32_t imm32) { 1595 InstructionMark im(this); 1596 prefix(dst); 1597 emit_int8((unsigned char)0x81); 1598 emit_operand(rdi, dst, 4); 1599 emit_int32(imm32); 1600 } 1601 1602 void Assembler::cmpl(Register dst, int32_t imm32) { 1603 prefix(dst); 1604 emit_arith(0x81, 0xF8, dst, imm32); 1605 } 1606 1607 void Assembler::cmpl(Register dst, Register src) { 1608 (void) prefix_and_encode(dst->encoding(), src->encoding()); 1609 emit_arith(0x3B, 0xC0, dst, src); 1610 } 1611 1612 void Assembler::cmpl(Register dst, Address src) { 1613 InstructionMark im(this); 1614 prefix(src, dst); 1615 emit_int8((unsigned char)0x3B); 1616 emit_operand(dst, src); 1617 } 1618 1619 void Assembler::cmpw(Address dst, int imm16) { 1620 InstructionMark im(this); 1621 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers"); 1622 emit_int8(0x66); 1623 emit_int8((unsigned char)0x81); 1624 emit_operand(rdi, dst, 2); 1625 emit_int16(imm16); 1626 } 1627 1628 // The 32-bit cmpxchg compares the value at adr with the contents of rax, 1629 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,. 1630 // The ZF is set if the compared values were equal, and cleared otherwise. 1631 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg 1632 InstructionMark im(this); 1633 prefix(adr, reg); 1634 emit_int8(0x0F); 1635 emit_int8((unsigned char)0xB1); 1636 emit_operand(reg, adr); 1637 } 1638 1639 // The 8-bit cmpxchg compares the value at adr with the contents of rax, 1640 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,. 1641 // The ZF is set if the compared values were equal, and cleared otherwise. 1642 void Assembler::cmpxchgb(Register reg, Address adr) { // cmpxchg 1643 InstructionMark im(this); 1644 prefix(adr, reg, true); 1645 emit_int8(0x0F); 1646 emit_int8((unsigned char)0xB0); 1647 emit_operand(reg, adr); 1648 } 1649 1650 void Assembler::comisd(XMMRegister dst, Address src) { 1651 // NOTE: dbx seems to decode this as comiss even though the 1652 // 0x66 is there. Strangly ucomisd comes out correct 1653 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1654 InstructionMark im(this); 1655 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);; 1656 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 1657 attributes.set_rex_vex_w_reverted(); 1658 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 1659 emit_int8(0x2F); 1660 emit_operand(dst, src); 1661 } 1662 1663 void Assembler::comisd(XMMRegister dst, XMMRegister src) { 1664 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1665 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1666 attributes.set_rex_vex_w_reverted(); 1667 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 1668 emit_int8(0x2F); 1669 emit_int8((unsigned char)(0xC0 | encode)); 1670 } 1671 1672 void Assembler::comiss(XMMRegister dst, Address src) { 1673 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1674 InstructionMark im(this); 1675 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1676 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 1677 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 1678 emit_int8(0x2F); 1679 emit_operand(dst, src); 1680 } 1681 1682 void Assembler::comiss(XMMRegister dst, XMMRegister src) { 1683 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1684 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1685 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 1686 emit_int8(0x2F); 1687 emit_int8((unsigned char)(0xC0 | encode)); 1688 } 1689 1690 void Assembler::cpuid() { 1691 emit_int8(0x0F); 1692 emit_int8((unsigned char)0xA2); 1693 } 1694 1695 // Opcode / Instruction Op / En 64 - Bit Mode Compat / Leg Mode Description Implemented 1696 // F2 0F 38 F0 / r CRC32 r32, r / m8 RM Valid Valid Accumulate CRC32 on r / m8. v 1697 // F2 REX 0F 38 F0 / r CRC32 r32, r / m8* RM Valid N.E. Accumulate CRC32 on r / m8. - 1698 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E. Accumulate CRC32 on r / m8. - 1699 // 1700 // F2 0F 38 F1 / r CRC32 r32, r / m16 RM Valid Valid Accumulate CRC32 on r / m16. v 1701 // 1702 // F2 0F 38 F1 / r CRC32 r32, r / m32 RM Valid Valid Accumulate CRC32 on r / m32. v 1703 // 1704 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E. Accumulate CRC32 on r / m64. v 1705 void Assembler::crc32(Register crc, Register v, int8_t sizeInBytes) { 1706 assert(VM_Version::supports_sse4_2(), ""); 1707 int8_t w = 0x01; 1708 Prefix p = Prefix_EMPTY; 1709 1710 emit_int8((int8_t)0xF2); 1711 switch (sizeInBytes) { 1712 case 1: 1713 w = 0; 1714 break; 1715 case 2: 1716 case 4: 1717 break; 1718 LP64_ONLY(case 8:) 1719 // This instruction is not valid in 32 bits 1720 // Note: 1721 // http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf 1722 // 1723 // Page B - 72 Vol. 2C says 1724 // qwreg2 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : 11 qwreg1 qwreg2 1725 // mem64 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : mod qwreg r / m 1726 // F0!!! 1727 // while 3 - 208 Vol. 2A 1728 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E.Accumulate CRC32 on r / m64. 1729 // 1730 // the 0 on a last bit is reserved for a different flavor of this instruction : 1731 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E.Accumulate CRC32 on r / m8. 1732 p = REX_W; 1733 break; 1734 default: 1735 assert(0, "Unsupported value for a sizeInBytes argument"); 1736 break; 1737 } 1738 LP64_ONLY(prefix(crc, v, p);) 1739 emit_int8((int8_t)0x0F); 1740 emit_int8(0x38); 1741 emit_int8((int8_t)(0xF0 | w)); 1742 emit_int8(0xC0 | ((crc->encoding() & 0x7) << 3) | (v->encoding() & 7)); 1743 } 1744 1745 void Assembler::crc32(Register crc, Address adr, int8_t sizeInBytes) { 1746 assert(VM_Version::supports_sse4_2(), ""); 1747 InstructionMark im(this); 1748 int8_t w = 0x01; 1749 Prefix p = Prefix_EMPTY; 1750 1751 emit_int8((int8_t)0xF2); 1752 switch (sizeInBytes) { 1753 case 1: 1754 w = 0; 1755 break; 1756 case 2: 1757 case 4: 1758 break; 1759 LP64_ONLY(case 8:) 1760 // This instruction is not valid in 32 bits 1761 p = REX_W; 1762 break; 1763 default: 1764 assert(0, "Unsupported value for a sizeInBytes argument"); 1765 break; 1766 } 1767 LP64_ONLY(prefix(crc, adr, p);) 1768 emit_int8((int8_t)0x0F); 1769 emit_int8(0x38); 1770 emit_int8((int8_t)(0xF0 | w)); 1771 emit_operand(crc, adr); 1772 } 1773 1774 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) { 1775 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1776 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 1777 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 1778 emit_int8((unsigned char)0xE6); 1779 emit_int8((unsigned char)(0xC0 | encode)); 1780 } 1781 1782 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) { 1783 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1784 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 1785 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 1786 emit_int8(0x5B); 1787 emit_int8((unsigned char)(0xC0 | encode)); 1788 } 1789 1790 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) { 1791 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1792 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1793 attributes.set_rex_vex_w_reverted(); 1794 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 1795 emit_int8(0x5A); 1796 emit_int8((unsigned char)(0xC0 | encode)); 1797 } 1798 1799 void Assembler::cvtsd2ss(XMMRegister dst, Address src) { 1800 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1801 InstructionMark im(this); 1802 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1803 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 1804 attributes.set_rex_vex_w_reverted(); 1805 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 1806 emit_int8(0x5A); 1807 emit_operand(dst, src); 1808 } 1809 1810 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) { 1811 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1812 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1813 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 1814 emit_int8(0x2A); 1815 emit_int8((unsigned char)(0xC0 | encode)); 1816 } 1817 1818 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) { 1819 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1820 InstructionMark im(this); 1821 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1822 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 1823 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 1824 emit_int8(0x2A); 1825 emit_operand(dst, src); 1826 } 1827 1828 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) { 1829 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1830 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1831 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 1832 emit_int8(0x2A); 1833 emit_int8((unsigned char)(0xC0 | encode)); 1834 } 1835 1836 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) { 1837 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1838 InstructionMark im(this); 1839 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1840 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 1841 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 1842 emit_int8(0x2A); 1843 emit_operand(dst, src); 1844 } 1845 1846 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) { 1847 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1848 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1849 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 1850 emit_int8(0x2A); 1851 emit_int8((unsigned char)(0xC0 | encode)); 1852 } 1853 1854 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) { 1855 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1856 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1857 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 1858 emit_int8(0x5A); 1859 emit_int8((unsigned char)(0xC0 | encode)); 1860 } 1861 1862 void Assembler::cvtss2sd(XMMRegister dst, Address src) { 1863 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1864 InstructionMark im(this); 1865 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1866 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 1867 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 1868 emit_int8(0x5A); 1869 emit_operand(dst, src); 1870 } 1871 1872 1873 void Assembler::cvttsd2sil(Register dst, XMMRegister src) { 1874 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1875 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1876 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 1877 emit_int8(0x2C); 1878 emit_int8((unsigned char)(0xC0 | encode)); 1879 } 1880 1881 void Assembler::cvttss2sil(Register dst, XMMRegister src) { 1882 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1883 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1884 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 1885 emit_int8(0x2C); 1886 emit_int8((unsigned char)(0xC0 | encode)); 1887 } 1888 1889 void Assembler::cvttpd2dq(XMMRegister dst, XMMRegister src) { 1890 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1891 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit; 1892 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 1893 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 1894 emit_int8((unsigned char)0xE6); 1895 emit_int8((unsigned char)(0xC0 | encode)); 1896 } 1897 1898 void Assembler::decl(Address dst) { 1899 // Don't use it directly. Use MacroAssembler::decrement() instead. 1900 InstructionMark im(this); 1901 prefix(dst); 1902 emit_int8((unsigned char)0xFF); 1903 emit_operand(rcx, dst); 1904 } 1905 1906 void Assembler::divsd(XMMRegister dst, Address src) { 1907 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1908 InstructionMark im(this); 1909 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1910 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 1911 attributes.set_rex_vex_w_reverted(); 1912 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 1913 emit_int8(0x5E); 1914 emit_operand(dst, src); 1915 } 1916 1917 void Assembler::divsd(XMMRegister dst, XMMRegister src) { 1918 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1919 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1920 attributes.set_rex_vex_w_reverted(); 1921 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 1922 emit_int8(0x5E); 1923 emit_int8((unsigned char)(0xC0 | encode)); 1924 } 1925 1926 void Assembler::divss(XMMRegister dst, Address src) { 1927 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1928 InstructionMark im(this); 1929 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1930 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 1931 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 1932 emit_int8(0x5E); 1933 emit_operand(dst, src); 1934 } 1935 1936 void Assembler::divss(XMMRegister dst, XMMRegister src) { 1937 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1938 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1939 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 1940 emit_int8(0x5E); 1941 emit_int8((unsigned char)(0xC0 | encode)); 1942 } 1943 1944 void Assembler::emms() { 1945 NOT_LP64(assert(VM_Version::supports_mmx(), "")); 1946 emit_int8(0x0F); 1947 emit_int8(0x77); 1948 } 1949 1950 void Assembler::hlt() { 1951 emit_int8((unsigned char)0xF4); 1952 } 1953 1954 void Assembler::idivl(Register src) { 1955 int encode = prefix_and_encode(src->encoding()); 1956 emit_int8((unsigned char)0xF7); 1957 emit_int8((unsigned char)(0xF8 | encode)); 1958 } 1959 1960 void Assembler::divl(Register src) { // Unsigned 1961 int encode = prefix_and_encode(src->encoding()); 1962 emit_int8((unsigned char)0xF7); 1963 emit_int8((unsigned char)(0xF0 | encode)); 1964 } 1965 1966 void Assembler::imull(Register src) { 1967 int encode = prefix_and_encode(src->encoding()); 1968 emit_int8((unsigned char)0xF7); 1969 emit_int8((unsigned char)(0xE8 | encode)); 1970 } 1971 1972 void Assembler::imull(Register dst, Register src) { 1973 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 1974 emit_int8(0x0F); 1975 emit_int8((unsigned char)0xAF); 1976 emit_int8((unsigned char)(0xC0 | encode)); 1977 } 1978 1979 1980 void Assembler::imull(Register dst, Register src, int value) { 1981 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 1982 if (is8bit(value)) { 1983 emit_int8(0x6B); 1984 emit_int8((unsigned char)(0xC0 | encode)); 1985 emit_int8(value & 0xFF); 1986 } else { 1987 emit_int8(0x69); 1988 emit_int8((unsigned char)(0xC0 | encode)); 1989 emit_int32(value); 1990 } 1991 } 1992 1993 void Assembler::imull(Register dst, Address src) { 1994 InstructionMark im(this); 1995 prefix(src, dst); 1996 emit_int8(0x0F); 1997 emit_int8((unsigned char) 0xAF); 1998 emit_operand(dst, src); 1999 } 2000 2001 2002 void Assembler::incl(Address dst) { 2003 // Don't use it directly. Use MacroAssembler::increment() instead. 2004 InstructionMark im(this); 2005 prefix(dst); 2006 emit_int8((unsigned char)0xFF); 2007 emit_operand(rax, dst); 2008 } 2009 2010 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) { 2011 InstructionMark im(this); 2012 assert((0 <= cc) && (cc < 16), "illegal cc"); 2013 if (L.is_bound()) { 2014 address dst = target(L); 2015 assert(dst != NULL, "jcc most probably wrong"); 2016 2017 const int short_size = 2; 2018 const int long_size = 6; 2019 intptr_t offs = (intptr_t)dst - (intptr_t)pc(); 2020 if (maybe_short && is8bit(offs - short_size)) { 2021 // 0111 tttn #8-bit disp 2022 emit_int8(0x70 | cc); 2023 emit_int8((offs - short_size) & 0xFF); 2024 } else { 2025 // 0000 1111 1000 tttn #32-bit disp 2026 assert(is_simm32(offs - long_size), 2027 "must be 32bit offset (call4)"); 2028 emit_int8(0x0F); 2029 emit_int8((unsigned char)(0x80 | cc)); 2030 emit_int32(offs - long_size); 2031 } 2032 } else { 2033 // Note: could eliminate cond. jumps to this jump if condition 2034 // is the same however, seems to be rather unlikely case. 2035 // Note: use jccb() if label to be bound is very close to get 2036 // an 8-bit displacement 2037 L.add_patch_at(code(), locator()); 2038 emit_int8(0x0F); 2039 emit_int8((unsigned char)(0x80 | cc)); 2040 emit_int32(0); 2041 } 2042 } 2043 2044 void Assembler::jccb_0(Condition cc, Label& L, const char* file, int line) { 2045 if (L.is_bound()) { 2046 const int short_size = 2; 2047 address entry = target(L); 2048 #ifdef ASSERT 2049 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size); 2050 intptr_t delta = short_branch_delta(); 2051 if (delta != 0) { 2052 dist += (dist < 0 ? (-delta) :delta); 2053 } 2054 assert(is8bit(dist), "Dispacement too large for a short jmp at %s:%d", file, line); 2055 #endif 2056 intptr_t offs = (intptr_t)entry - (intptr_t)pc(); 2057 // 0111 tttn #8-bit disp 2058 emit_int8(0x70 | cc); 2059 emit_int8((offs - short_size) & 0xFF); 2060 } else { 2061 InstructionMark im(this); 2062 L.add_patch_at(code(), locator(), file, line); 2063 emit_int8(0x70 | cc); 2064 emit_int8(0); 2065 } 2066 } 2067 2068 void Assembler::jmp(Address adr) { 2069 InstructionMark im(this); 2070 prefix(adr); 2071 emit_int8((unsigned char)0xFF); 2072 emit_operand(rsp, adr); 2073 } 2074 2075 void Assembler::jmp(Label& L, bool maybe_short) { 2076 if (L.is_bound()) { 2077 address entry = target(L); 2078 assert(entry != NULL, "jmp most probably wrong"); 2079 InstructionMark im(this); 2080 const int short_size = 2; 2081 const int long_size = 5; 2082 intptr_t offs = entry - pc(); 2083 if (maybe_short && is8bit(offs - short_size)) { 2084 emit_int8((unsigned char)0xEB); 2085 emit_int8((offs - short_size) & 0xFF); 2086 } else { 2087 emit_int8((unsigned char)0xE9); 2088 emit_int32(offs - long_size); 2089 } 2090 } else { 2091 // By default, forward jumps are always 32-bit displacements, since 2092 // we can't yet know where the label will be bound. If you're sure that 2093 // the forward jump will not run beyond 256 bytes, use jmpb to 2094 // force an 8-bit displacement. 2095 InstructionMark im(this); 2096 L.add_patch_at(code(), locator()); 2097 emit_int8((unsigned char)0xE9); 2098 emit_int32(0); 2099 } 2100 } 2101 2102 void Assembler::jmp(Register entry) { 2103 int encode = prefix_and_encode(entry->encoding()); 2104 emit_int8((unsigned char)0xFF); 2105 emit_int8((unsigned char)(0xE0 | encode)); 2106 } 2107 2108 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) { 2109 InstructionMark im(this); 2110 emit_int8((unsigned char)0xE9); 2111 assert(dest != NULL, "must have a target"); 2112 intptr_t disp = dest - (pc() + sizeof(int32_t)); 2113 assert(is_simm32(disp), "must be 32bit offset (jmp)"); 2114 emit_data(disp, rspec.reloc(), call32_operand); 2115 } 2116 2117 void Assembler::jmpb_0(Label& L, const char* file, int line) { 2118 if (L.is_bound()) { 2119 const int short_size = 2; 2120 address entry = target(L); 2121 assert(entry != NULL, "jmp most probably wrong"); 2122 #ifdef ASSERT 2123 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size); 2124 intptr_t delta = short_branch_delta(); 2125 if (delta != 0) { 2126 dist += (dist < 0 ? (-delta) :delta); 2127 } 2128 assert(is8bit(dist), "Dispacement too large for a short jmp at %s:%d", file, line); 2129 #endif 2130 intptr_t offs = entry - pc(); 2131 emit_int8((unsigned char)0xEB); 2132 emit_int8((offs - short_size) & 0xFF); 2133 } else { 2134 InstructionMark im(this); 2135 L.add_patch_at(code(), locator(), file, line); 2136 emit_int8((unsigned char)0xEB); 2137 emit_int8(0); 2138 } 2139 } 2140 2141 void Assembler::ldmxcsr( Address src) { 2142 if (UseAVX > 0 ) { 2143 InstructionMark im(this); 2144 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2145 vex_prefix(src, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2146 emit_int8((unsigned char)0xAE); 2147 emit_operand(as_Register(2), src); 2148 } else { 2149 NOT_LP64(assert(VM_Version::supports_sse(), "")); 2150 InstructionMark im(this); 2151 prefix(src); 2152 emit_int8(0x0F); 2153 emit_int8((unsigned char)0xAE); 2154 emit_operand(as_Register(2), src); 2155 } 2156 } 2157 2158 void Assembler::leal(Register dst, Address src) { 2159 InstructionMark im(this); 2160 #ifdef _LP64 2161 emit_int8(0x67); // addr32 2162 prefix(src, dst); 2163 #endif // LP64 2164 emit_int8((unsigned char)0x8D); 2165 emit_operand(dst, src); 2166 } 2167 2168 void Assembler::lfence() { 2169 emit_int8(0x0F); 2170 emit_int8((unsigned char)0xAE); 2171 emit_int8((unsigned char)0xE8); 2172 } 2173 2174 void Assembler::lock() { 2175 emit_int8((unsigned char)0xF0); 2176 } 2177 2178 void Assembler::lzcntl(Register dst, Register src) { 2179 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR"); 2180 emit_int8((unsigned char)0xF3); 2181 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 2182 emit_int8(0x0F); 2183 emit_int8((unsigned char)0xBD); 2184 emit_int8((unsigned char)(0xC0 | encode)); 2185 } 2186 2187 // Emit mfence instruction 2188 void Assembler::mfence() { 2189 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");) 2190 emit_int8(0x0F); 2191 emit_int8((unsigned char)0xAE); 2192 emit_int8((unsigned char)0xF0); 2193 } 2194 2195 void Assembler::mov(Register dst, Register src) { 2196 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); 2197 } 2198 2199 void Assembler::movapd(XMMRegister dst, XMMRegister src) { 2200 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2201 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit; 2202 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2203 attributes.set_rex_vex_w_reverted(); 2204 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2205 emit_int8(0x28); 2206 emit_int8((unsigned char)(0xC0 | encode)); 2207 } 2208 2209 void Assembler::movaps(XMMRegister dst, XMMRegister src) { 2210 NOT_LP64(assert(VM_Version::supports_sse(), "")); 2211 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit; 2212 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2213 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2214 emit_int8(0x28); 2215 emit_int8((unsigned char)(0xC0 | encode)); 2216 } 2217 2218 void Assembler::movlhps(XMMRegister dst, XMMRegister src) { 2219 NOT_LP64(assert(VM_Version::supports_sse(), "")); 2220 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 2221 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2222 emit_int8(0x16); 2223 emit_int8((unsigned char)(0xC0 | encode)); 2224 } 2225 2226 void Assembler::movb(Register dst, Address src) { 2227 NOT_LP64(assert(dst->has_byte_register(), "must have byte register")); 2228 InstructionMark im(this); 2229 prefix(src, dst, true); 2230 emit_int8((unsigned char)0x8A); 2231 emit_operand(dst, src); 2232 } 2233 2234 void Assembler::movddup(XMMRegister dst, XMMRegister src) { 2235 NOT_LP64(assert(VM_Version::supports_sse3(), "")); 2236 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit; 2237 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2238 attributes.set_rex_vex_w_reverted(); 2239 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2240 emit_int8(0x12); 2241 emit_int8(0xC0 | encode); 2242 } 2243 2244 void Assembler::kmovbl(KRegister dst, Register src) { 2245 assert(VM_Version::supports_avx512dq(), ""); 2246 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2247 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2248 emit_int8((unsigned char)0x92); 2249 emit_int8((unsigned char)(0xC0 | encode)); 2250 } 2251 2252 void Assembler::kmovbl(Register dst, KRegister src) { 2253 assert(VM_Version::supports_avx512dq(), ""); 2254 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2255 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2256 emit_int8((unsigned char)0x93); 2257 emit_int8((unsigned char)(0xC0 | encode)); 2258 } 2259 2260 void Assembler::kmovwl(KRegister dst, Register src) { 2261 assert(VM_Version::supports_evex(), ""); 2262 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2263 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2264 emit_int8((unsigned char)0x92); 2265 emit_int8((unsigned char)(0xC0 | encode)); 2266 } 2267 2268 void Assembler::kmovwl(Register dst, KRegister src) { 2269 assert(VM_Version::supports_evex(), ""); 2270 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2271 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2272 emit_int8((unsigned char)0x93); 2273 emit_int8((unsigned char)(0xC0 | encode)); 2274 } 2275 2276 void Assembler::kmovwl(KRegister dst, Address src) { 2277 assert(VM_Version::supports_evex(), ""); 2278 InstructionMark im(this); 2279 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2280 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2281 emit_int8((unsigned char)0x90); 2282 emit_operand((Register)dst, src); 2283 } 2284 2285 void Assembler::kmovdl(KRegister dst, Register src) { 2286 assert(VM_Version::supports_avx512bw(), ""); 2287 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2288 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2289 emit_int8((unsigned char)0x92); 2290 emit_int8((unsigned char)(0xC0 | encode)); 2291 } 2292 2293 void Assembler::kmovdl(Register dst, KRegister src) { 2294 assert(VM_Version::supports_avx512bw(), ""); 2295 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2296 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2297 emit_int8((unsigned char)0x93); 2298 emit_int8((unsigned char)(0xC0 | encode)); 2299 } 2300 2301 void Assembler::kmovql(KRegister dst, KRegister src) { 2302 assert(VM_Version::supports_avx512bw(), ""); 2303 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2304 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2305 emit_int8((unsigned char)0x90); 2306 emit_int8((unsigned char)(0xC0 | encode)); 2307 } 2308 2309 void Assembler::kmovql(KRegister dst, Address src) { 2310 assert(VM_Version::supports_avx512bw(), ""); 2311 InstructionMark im(this); 2312 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2313 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2314 emit_int8((unsigned char)0x90); 2315 emit_operand((Register)dst, src); 2316 } 2317 2318 void Assembler::kmovql(Address dst, KRegister src) { 2319 assert(VM_Version::supports_avx512bw(), ""); 2320 InstructionMark im(this); 2321 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2322 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2323 emit_int8((unsigned char)0x90); 2324 emit_operand((Register)src, dst); 2325 } 2326 2327 void Assembler::kmovql(KRegister dst, Register src) { 2328 assert(VM_Version::supports_avx512bw(), ""); 2329 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2330 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2331 emit_int8((unsigned char)0x92); 2332 emit_int8((unsigned char)(0xC0 | encode)); 2333 } 2334 2335 void Assembler::kmovql(Register dst, KRegister src) { 2336 assert(VM_Version::supports_avx512bw(), ""); 2337 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2338 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2339 emit_int8((unsigned char)0x93); 2340 emit_int8((unsigned char)(0xC0 | encode)); 2341 } 2342 2343 void Assembler::knotwl(KRegister dst, KRegister src) { 2344 assert(VM_Version::supports_evex(), ""); 2345 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2346 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2347 emit_int8((unsigned char)0x44); 2348 emit_int8((unsigned char)(0xC0 | encode)); 2349 } 2350 2351 // This instruction produces ZF or CF flags 2352 void Assembler::kortestbl(KRegister src1, KRegister src2) { 2353 assert(VM_Version::supports_avx512dq(), ""); 2354 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2355 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2356 emit_int8((unsigned char)0x98); 2357 emit_int8((unsigned char)(0xC0 | encode)); 2358 } 2359 2360 // This instruction produces ZF or CF flags 2361 void Assembler::kortestwl(KRegister src1, KRegister src2) { 2362 assert(VM_Version::supports_evex(), ""); 2363 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2364 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2365 emit_int8((unsigned char)0x98); 2366 emit_int8((unsigned char)(0xC0 | encode)); 2367 } 2368 2369 // This instruction produces ZF or CF flags 2370 void Assembler::kortestdl(KRegister src1, KRegister src2) { 2371 assert(VM_Version::supports_avx512bw(), ""); 2372 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2373 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2374 emit_int8((unsigned char)0x98); 2375 emit_int8((unsigned char)(0xC0 | encode)); 2376 } 2377 2378 // This instruction produces ZF or CF flags 2379 void Assembler::kortestql(KRegister src1, KRegister src2) { 2380 assert(VM_Version::supports_avx512bw(), ""); 2381 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2382 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2383 emit_int8((unsigned char)0x98); 2384 emit_int8((unsigned char)(0xC0 | encode)); 2385 } 2386 2387 // This instruction produces ZF or CF flags 2388 void Assembler::ktestql(KRegister src1, KRegister src2) { 2389 assert(VM_Version::supports_avx512bw(), ""); 2390 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2391 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2392 emit_int8((unsigned char)0x99); 2393 emit_int8((unsigned char)(0xC0 | encode)); 2394 } 2395 2396 void Assembler::ktestq(KRegister src1, KRegister src2) { 2397 assert(VM_Version::supports_avx512bw(), ""); 2398 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2399 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2400 emit_int8((unsigned char)0x99); 2401 emit_int8((unsigned char)(0xC0 | encode)); 2402 } 2403 2404 void Assembler::ktestd(KRegister src1, KRegister src2) { 2405 assert(VM_Version::supports_avx512bw(), ""); 2406 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2407 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2408 emit_int8((unsigned char)0x99); 2409 emit_int8((unsigned char)(0xC0 | encode)); 2410 } 2411 2412 void Assembler::movb(Address dst, int imm8) { 2413 InstructionMark im(this); 2414 prefix(dst); 2415 emit_int8((unsigned char)0xC6); 2416 emit_operand(rax, dst, 1); 2417 emit_int8(imm8); 2418 } 2419 2420 2421 void Assembler::movb(Address dst, Register src) { 2422 assert(src->has_byte_register(), "must have byte register"); 2423 InstructionMark im(this); 2424 prefix(dst, src, true); 2425 emit_int8((unsigned char)0x88); 2426 emit_operand(src, dst); 2427 } 2428 2429 void Assembler::movdl(XMMRegister dst, Register src) { 2430 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2431 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2432 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2433 emit_int8(0x6E); 2434 emit_int8((unsigned char)(0xC0 | encode)); 2435 } 2436 2437 void Assembler::movdl(Register dst, XMMRegister src) { 2438 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2439 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2440 // swap src/dst to get correct prefix 2441 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2442 emit_int8(0x7E); 2443 emit_int8((unsigned char)(0xC0 | encode)); 2444 } 2445 2446 void Assembler::movdl(XMMRegister dst, Address src) { 2447 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2448 InstructionMark im(this); 2449 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2450 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 2451 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2452 emit_int8(0x6E); 2453 emit_operand(dst, src); 2454 } 2455 2456 void Assembler::movdl(Address dst, XMMRegister src) { 2457 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2458 InstructionMark im(this); 2459 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2460 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 2461 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2462 emit_int8(0x7E); 2463 emit_operand(src, dst); 2464 } 2465 2466 void Assembler::movdqa(XMMRegister dst, XMMRegister src) { 2467 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2468 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2469 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2470 emit_int8(0x6F); 2471 emit_int8((unsigned char)(0xC0 | encode)); 2472 } 2473 2474 void Assembler::movdqa(XMMRegister dst, Address src) { 2475 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2476 InstructionMark im(this); 2477 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2478 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2479 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2480 emit_int8(0x6F); 2481 emit_operand(dst, src); 2482 } 2483 2484 void Assembler::movdqu(XMMRegister dst, Address src) { 2485 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2486 InstructionMark im(this); 2487 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2488 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2489 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2490 emit_int8(0x6F); 2491 emit_operand(dst, src); 2492 } 2493 2494 void Assembler::movdqu(XMMRegister dst, XMMRegister src) { 2495 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2496 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2497 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2498 emit_int8(0x6F); 2499 emit_int8((unsigned char)(0xC0 | encode)); 2500 } 2501 2502 void Assembler::movdqu(Address dst, XMMRegister src) { 2503 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2504 InstructionMark im(this); 2505 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2506 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2507 attributes.reset_is_clear_context(); 2508 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2509 emit_int8(0x7F); 2510 emit_operand(src, dst); 2511 } 2512 2513 // Move Unaligned 256bit Vector 2514 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) { 2515 assert(UseAVX > 0, ""); 2516 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2517 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2518 emit_int8(0x6F); 2519 emit_int8((unsigned char)(0xC0 | encode)); 2520 } 2521 2522 void Assembler::vmovdqu(XMMRegister dst, Address src) { 2523 assert(UseAVX > 0, ""); 2524 InstructionMark im(this); 2525 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2526 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2527 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2528 emit_int8(0x6F); 2529 emit_operand(dst, src); 2530 } 2531 2532 void Assembler::vmovdqu(Address dst, XMMRegister src) { 2533 assert(UseAVX > 0, ""); 2534 InstructionMark im(this); 2535 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2536 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2537 attributes.reset_is_clear_context(); 2538 // swap src<->dst for encoding 2539 assert(src != xnoreg, "sanity"); 2540 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2541 emit_int8(0x7F); 2542 emit_operand(src, dst); 2543 } 2544 2545 // Move Unaligned EVEX enabled Vector (programmable : 8,16,32,64) 2546 void Assembler::evmovdqub(XMMRegister dst, XMMRegister src, int vector_len) { 2547 assert(VM_Version::supports_evex(), ""); 2548 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 2549 attributes.set_is_evex_instruction(); 2550 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3; 2551 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes); 2552 emit_int8(0x6F); 2553 emit_int8((unsigned char)(0xC0 | encode)); 2554 } 2555 2556 void Assembler::evmovdqub(XMMRegister dst, Address src, int vector_len) { 2557 assert(VM_Version::supports_evex(), ""); 2558 InstructionMark im(this); 2559 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 2560 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3; 2561 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2562 attributes.set_is_evex_instruction(); 2563 vex_prefix(src, 0, dst->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes); 2564 emit_int8(0x6F); 2565 emit_operand(dst, src); 2566 } 2567 2568 void Assembler::evmovdqub(Address dst, XMMRegister src, int vector_len) { 2569 assert(VM_Version::supports_evex(), ""); 2570 assert(src != xnoreg, "sanity"); 2571 InstructionMark im(this); 2572 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 2573 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3; 2574 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2575 attributes.set_is_evex_instruction(); 2576 vex_prefix(dst, 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes); 2577 emit_int8(0x7F); 2578 emit_operand(src, dst); 2579 } 2580 2581 void Assembler::evmovdqub(XMMRegister dst, KRegister mask, Address src, int vector_len) { 2582 assert(VM_Version::supports_avx512vlbw(), ""); 2583 assert(is_vector_masking(), ""); // For stub code use only 2584 InstructionMark im(this); 2585 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2586 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2587 attributes.set_embedded_opmask_register_specifier(mask); 2588 attributes.set_is_evex_instruction(); 2589 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2590 emit_int8(0x6F); 2591 emit_operand(dst, src); 2592 } 2593 2594 void Assembler::evmovdquw(XMMRegister dst, Address src, int vector_len) { 2595 assert(VM_Version::supports_evex(), ""); 2596 InstructionMark im(this); 2597 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 2598 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2599 attributes.set_is_evex_instruction(); 2600 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3; 2601 vex_prefix(src, 0, dst->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes); 2602 emit_int8(0x6F); 2603 emit_operand(dst, src); 2604 } 2605 2606 void Assembler::evmovdquw(XMMRegister dst, KRegister mask, Address src, int vector_len) { 2607 assert(is_vector_masking(), ""); 2608 assert(VM_Version::supports_avx512vlbw(), ""); 2609 InstructionMark im(this); 2610 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2611 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2612 attributes.set_embedded_opmask_register_specifier(mask); 2613 attributes.set_is_evex_instruction(); 2614 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2615 emit_int8(0x6F); 2616 emit_operand(dst, src); 2617 } 2618 2619 void Assembler::evmovdquw(Address dst, XMMRegister src, int vector_len) { 2620 assert(VM_Version::supports_evex(), ""); 2621 assert(src != xnoreg, "sanity"); 2622 InstructionMark im(this); 2623 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 2624 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2625 attributes.set_is_evex_instruction(); 2626 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3; 2627 vex_prefix(dst, 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes); 2628 emit_int8(0x7F); 2629 emit_operand(src, dst); 2630 } 2631 2632 void Assembler::evmovdquw(Address dst, KRegister mask, XMMRegister src, int vector_len) { 2633 assert(VM_Version::supports_avx512vlbw(), ""); 2634 assert(src != xnoreg, "sanity"); 2635 InstructionMark im(this); 2636 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2637 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2638 attributes.reset_is_clear_context(); 2639 attributes.set_embedded_opmask_register_specifier(mask); 2640 attributes.set_is_evex_instruction(); 2641 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2642 emit_int8(0x7F); 2643 emit_operand(src, dst); 2644 } 2645 2646 void Assembler::evmovdqul(XMMRegister dst, XMMRegister src, int vector_len) { 2647 assert(VM_Version::supports_evex(), ""); 2648 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2649 attributes.set_is_evex_instruction(); 2650 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2651 emit_int8(0x6F); 2652 emit_int8((unsigned char)(0xC0 | encode)); 2653 } 2654 2655 void Assembler::evmovdqul(XMMRegister dst, Address src, int vector_len) { 2656 assert(VM_Version::supports_evex(), ""); 2657 InstructionMark im(this); 2658 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false , /* uses_vl */ true); 2659 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2660 attributes.set_is_evex_instruction(); 2661 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2662 emit_int8(0x6F); 2663 emit_operand(dst, src); 2664 } 2665 2666 void Assembler::evmovdqul(Address dst, XMMRegister src, int vector_len) { 2667 assert(VM_Version::supports_evex(), ""); 2668 assert(src != xnoreg, "sanity"); 2669 InstructionMark im(this); 2670 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2671 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2672 attributes.reset_is_clear_context(); 2673 attributes.set_is_evex_instruction(); 2674 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2675 emit_int8(0x7F); 2676 emit_operand(src, dst); 2677 } 2678 2679 void Assembler::evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) { 2680 assert(VM_Version::supports_evex(), ""); 2681 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2682 attributes.set_is_evex_instruction(); 2683 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2684 emit_int8(0x6F); 2685 emit_int8((unsigned char)(0xC0 | encode)); 2686 } 2687 2688 void Assembler::evmovdquq(XMMRegister dst, Address src, int vector_len) { 2689 assert(VM_Version::supports_evex(), ""); 2690 InstructionMark im(this); 2691 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2692 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2693 attributes.set_is_evex_instruction(); 2694 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2695 emit_int8(0x6F); 2696 emit_operand(dst, src); 2697 } 2698 2699 void Assembler::evmovdquq(Address dst, XMMRegister src, int vector_len) { 2700 assert(VM_Version::supports_evex(), ""); 2701 assert(src != xnoreg, "sanity"); 2702 InstructionMark im(this); 2703 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2704 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2705 attributes.reset_is_clear_context(); 2706 attributes.set_is_evex_instruction(); 2707 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2708 emit_int8(0x7F); 2709 emit_operand(src, dst); 2710 } 2711 2712 // Uses zero extension on 64bit 2713 2714 void Assembler::movl(Register dst, int32_t imm32) { 2715 int encode = prefix_and_encode(dst->encoding()); 2716 emit_int8((unsigned char)(0xB8 | encode)); 2717 emit_int32(imm32); 2718 } 2719 2720 void Assembler::movl(Register dst, Register src) { 2721 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 2722 emit_int8((unsigned char)0x8B); 2723 emit_int8((unsigned char)(0xC0 | encode)); 2724 } 2725 2726 void Assembler::movl(Register dst, Address src) { 2727 InstructionMark im(this); 2728 prefix(src, dst); 2729 emit_int8((unsigned char)0x8B); 2730 emit_operand(dst, src); 2731 } 2732 2733 void Assembler::movl(Address dst, int32_t imm32) { 2734 InstructionMark im(this); 2735 prefix(dst); 2736 emit_int8((unsigned char)0xC7); 2737 emit_operand(rax, dst, 4); 2738 emit_int32(imm32); 2739 } 2740 2741 void Assembler::movl(Address dst, Register src) { 2742 InstructionMark im(this); 2743 prefix(dst, src); 2744 emit_int8((unsigned char)0x89); 2745 emit_operand(src, dst); 2746 } 2747 2748 // New cpus require to use movsd and movss to avoid partial register stall 2749 // when loading from memory. But for old Opteron use movlpd instead of movsd. 2750 // The selection is done in MacroAssembler::movdbl() and movflt(). 2751 void Assembler::movlpd(XMMRegister dst, Address src) { 2752 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2753 InstructionMark im(this); 2754 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 2755 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 2756 attributes.set_rex_vex_w_reverted(); 2757 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2758 emit_int8(0x12); 2759 emit_operand(dst, src); 2760 } 2761 2762 void Assembler::movq( MMXRegister dst, Address src ) { 2763 assert( VM_Version::supports_mmx(), "" ); 2764 emit_int8(0x0F); 2765 emit_int8(0x6F); 2766 emit_operand(dst, src); 2767 } 2768 2769 void Assembler::movq( Address dst, MMXRegister src ) { 2770 assert( VM_Version::supports_mmx(), "" ); 2771 emit_int8(0x0F); 2772 emit_int8(0x7F); 2773 // workaround gcc (3.2.1-7a) bug 2774 // In that version of gcc with only an emit_operand(MMX, Address) 2775 // gcc will tail jump and try and reverse the parameters completely 2776 // obliterating dst in the process. By having a version available 2777 // that doesn't need to swap the args at the tail jump the bug is 2778 // avoided. 2779 emit_operand(dst, src); 2780 } 2781 2782 void Assembler::movq(XMMRegister dst, Address src) { 2783 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2784 InstructionMark im(this); 2785 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2786 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 2787 attributes.set_rex_vex_w_reverted(); 2788 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2789 emit_int8(0x7E); 2790 emit_operand(dst, src); 2791 } 2792 2793 void Assembler::movq(Address dst, XMMRegister src) { 2794 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2795 InstructionMark im(this); 2796 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2797 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 2798 attributes.set_rex_vex_w_reverted(); 2799 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2800 emit_int8((unsigned char)0xD6); 2801 emit_operand(src, dst); 2802 } 2803 2804 void Assembler::movsbl(Register dst, Address src) { // movsxb 2805 InstructionMark im(this); 2806 prefix(src, dst); 2807 emit_int8(0x0F); 2808 emit_int8((unsigned char)0xBE); 2809 emit_operand(dst, src); 2810 } 2811 2812 void Assembler::movsbl(Register dst, Register src) { // movsxb 2813 NOT_LP64(assert(src->has_byte_register(), "must have byte register")); 2814 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true); 2815 emit_int8(0x0F); 2816 emit_int8((unsigned char)0xBE); 2817 emit_int8((unsigned char)(0xC0 | encode)); 2818 } 2819 2820 void Assembler::movsd(XMMRegister dst, XMMRegister src) { 2821 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2822 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2823 attributes.set_rex_vex_w_reverted(); 2824 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2825 emit_int8(0x10); 2826 emit_int8((unsigned char)(0xC0 | encode)); 2827 } 2828 2829 void Assembler::movsd(XMMRegister dst, Address src) { 2830 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2831 InstructionMark im(this); 2832 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2833 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 2834 attributes.set_rex_vex_w_reverted(); 2835 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2836 emit_int8(0x10); 2837 emit_operand(dst, src); 2838 } 2839 2840 void Assembler::movsd(Address dst, XMMRegister src) { 2841 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2842 InstructionMark im(this); 2843 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2844 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 2845 attributes.reset_is_clear_context(); 2846 attributes.set_rex_vex_w_reverted(); 2847 simd_prefix(src, xnoreg, dst, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2848 emit_int8(0x11); 2849 emit_operand(src, dst); 2850 } 2851 2852 void Assembler::movss(XMMRegister dst, XMMRegister src) { 2853 NOT_LP64(assert(VM_Version::supports_sse(), "")); 2854 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2855 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2856 emit_int8(0x10); 2857 emit_int8((unsigned char)(0xC0 | encode)); 2858 } 2859 2860 void Assembler::movss(XMMRegister dst, Address src) { 2861 NOT_LP64(assert(VM_Version::supports_sse(), "")); 2862 InstructionMark im(this); 2863 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2864 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 2865 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2866 emit_int8(0x10); 2867 emit_operand(dst, src); 2868 } 2869 2870 void Assembler::movss(Address dst, XMMRegister src) { 2871 NOT_LP64(assert(VM_Version::supports_sse(), "")); 2872 InstructionMark im(this); 2873 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2874 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 2875 attributes.reset_is_clear_context(); 2876 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2877 emit_int8(0x11); 2878 emit_operand(src, dst); 2879 } 2880 2881 void Assembler::movswl(Register dst, Address src) { // movsxw 2882 InstructionMark im(this); 2883 prefix(src, dst); 2884 emit_int8(0x0F); 2885 emit_int8((unsigned char)0xBF); 2886 emit_operand(dst, src); 2887 } 2888 2889 void Assembler::movswl(Register dst, Register src) { // movsxw 2890 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 2891 emit_int8(0x0F); 2892 emit_int8((unsigned char)0xBF); 2893 emit_int8((unsigned char)(0xC0 | encode)); 2894 } 2895 2896 void Assembler::movw(Address dst, int imm16) { 2897 InstructionMark im(this); 2898 2899 emit_int8(0x66); // switch to 16-bit mode 2900 prefix(dst); 2901 emit_int8((unsigned char)0xC7); 2902 emit_operand(rax, dst, 2); 2903 emit_int16(imm16); 2904 } 2905 2906 void Assembler::movw(Register dst, Address src) { 2907 InstructionMark im(this); 2908 emit_int8(0x66); 2909 prefix(src, dst); 2910 emit_int8((unsigned char)0x8B); 2911 emit_operand(dst, src); 2912 } 2913 2914 void Assembler::movw(Address dst, Register src) { 2915 InstructionMark im(this); 2916 emit_int8(0x66); 2917 prefix(dst, src); 2918 emit_int8((unsigned char)0x89); 2919 emit_operand(src, dst); 2920 } 2921 2922 void Assembler::movzbl(Register dst, Address src) { // movzxb 2923 InstructionMark im(this); 2924 prefix(src, dst); 2925 emit_int8(0x0F); 2926 emit_int8((unsigned char)0xB6); 2927 emit_operand(dst, src); 2928 } 2929 2930 void Assembler::movzbl(Register dst, Register src) { // movzxb 2931 NOT_LP64(assert(src->has_byte_register(), "must have byte register")); 2932 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true); 2933 emit_int8(0x0F); 2934 emit_int8((unsigned char)0xB6); 2935 emit_int8(0xC0 | encode); 2936 } 2937 2938 void Assembler::movzwl(Register dst, Address src) { // movzxw 2939 InstructionMark im(this); 2940 prefix(src, dst); 2941 emit_int8(0x0F); 2942 emit_int8((unsigned char)0xB7); 2943 emit_operand(dst, src); 2944 } 2945 2946 void Assembler::movzwl(Register dst, Register src) { // movzxw 2947 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 2948 emit_int8(0x0F); 2949 emit_int8((unsigned char)0xB7); 2950 emit_int8(0xC0 | encode); 2951 } 2952 2953 void Assembler::mull(Address src) { 2954 InstructionMark im(this); 2955 prefix(src); 2956 emit_int8((unsigned char)0xF7); 2957 emit_operand(rsp, src); 2958 } 2959 2960 void Assembler::mull(Register src) { 2961 int encode = prefix_and_encode(src->encoding()); 2962 emit_int8((unsigned char)0xF7); 2963 emit_int8((unsigned char)(0xE0 | encode)); 2964 } 2965 2966 void Assembler::mulsd(XMMRegister dst, Address src) { 2967 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2968 InstructionMark im(this); 2969 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2970 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 2971 attributes.set_rex_vex_w_reverted(); 2972 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2973 emit_int8(0x59); 2974 emit_operand(dst, src); 2975 } 2976 2977 void Assembler::mulsd(XMMRegister dst, XMMRegister src) { 2978 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2979 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2980 attributes.set_rex_vex_w_reverted(); 2981 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2982 emit_int8(0x59); 2983 emit_int8((unsigned char)(0xC0 | encode)); 2984 } 2985 2986 void Assembler::mulss(XMMRegister dst, Address src) { 2987 NOT_LP64(assert(VM_Version::supports_sse(), "")); 2988 InstructionMark im(this); 2989 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2990 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 2991 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2992 emit_int8(0x59); 2993 emit_operand(dst, src); 2994 } 2995 2996 void Assembler::mulss(XMMRegister dst, XMMRegister src) { 2997 NOT_LP64(assert(VM_Version::supports_sse(), "")); 2998 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2999 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 3000 emit_int8(0x59); 3001 emit_int8((unsigned char)(0xC0 | encode)); 3002 } 3003 3004 void Assembler::negl(Register dst) { 3005 int encode = prefix_and_encode(dst->encoding()); 3006 emit_int8((unsigned char)0xF7); 3007 emit_int8((unsigned char)(0xD8 | encode)); 3008 } 3009 3010 void Assembler::nop(int i) { 3011 #ifdef ASSERT 3012 assert(i > 0, " "); 3013 // The fancy nops aren't currently recognized by debuggers making it a 3014 // pain to disassemble code while debugging. If asserts are on clearly 3015 // speed is not an issue so simply use the single byte traditional nop 3016 // to do alignment. 3017 3018 for (; i > 0 ; i--) emit_int8((unsigned char)0x90); 3019 return; 3020 3021 #endif // ASSERT 3022 3023 if (UseAddressNop && VM_Version::is_intel()) { 3024 // 3025 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel 3026 // 1: 0x90 3027 // 2: 0x66 0x90 3028 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding) 3029 // 4: 0x0F 0x1F 0x40 0x00 3030 // 5: 0x0F 0x1F 0x44 0x00 0x00 3031 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00 3032 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 3033 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 3034 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 3035 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 3036 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 3037 3038 // The rest coding is Intel specific - don't use consecutive address nops 3039 3040 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 3041 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 3042 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 3043 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 3044 3045 while(i >= 15) { 3046 // For Intel don't generate consecutive addess nops (mix with regular nops) 3047 i -= 15; 3048 emit_int8(0x66); // size prefix 3049 emit_int8(0x66); // size prefix 3050 emit_int8(0x66); // size prefix 3051 addr_nop_8(); 3052 emit_int8(0x66); // size prefix 3053 emit_int8(0x66); // size prefix 3054 emit_int8(0x66); // size prefix 3055 emit_int8((unsigned char)0x90); 3056 // nop 3057 } 3058 switch (i) { 3059 case 14: 3060 emit_int8(0x66); // size prefix 3061 case 13: 3062 emit_int8(0x66); // size prefix 3063 case 12: 3064 addr_nop_8(); 3065 emit_int8(0x66); // size prefix 3066 emit_int8(0x66); // size prefix 3067 emit_int8(0x66); // size prefix 3068 emit_int8((unsigned char)0x90); 3069 // nop 3070 break; 3071 case 11: 3072 emit_int8(0x66); // size prefix 3073 case 10: 3074 emit_int8(0x66); // size prefix 3075 case 9: 3076 emit_int8(0x66); // size prefix 3077 case 8: 3078 addr_nop_8(); 3079 break; 3080 case 7: 3081 addr_nop_7(); 3082 break; 3083 case 6: 3084 emit_int8(0x66); // size prefix 3085 case 5: 3086 addr_nop_5(); 3087 break; 3088 case 4: 3089 addr_nop_4(); 3090 break; 3091 case 3: 3092 // Don't use "0x0F 0x1F 0x00" - need patching safe padding 3093 emit_int8(0x66); // size prefix 3094 case 2: 3095 emit_int8(0x66); // size prefix 3096 case 1: 3097 emit_int8((unsigned char)0x90); 3098 // nop 3099 break; 3100 default: 3101 assert(i == 0, " "); 3102 } 3103 return; 3104 } 3105 if (UseAddressNop && VM_Version::is_amd()) { 3106 // 3107 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD. 3108 // 1: 0x90 3109 // 2: 0x66 0x90 3110 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding) 3111 // 4: 0x0F 0x1F 0x40 0x00 3112 // 5: 0x0F 0x1F 0x44 0x00 0x00 3113 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00 3114 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 3115 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 3116 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 3117 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 3118 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 3119 3120 // The rest coding is AMD specific - use consecutive address nops 3121 3122 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00 3123 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00 3124 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 3125 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 3126 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 3127 // Size prefixes (0x66) are added for larger sizes 3128 3129 while(i >= 22) { 3130 i -= 11; 3131 emit_int8(0x66); // size prefix 3132 emit_int8(0x66); // size prefix 3133 emit_int8(0x66); // size prefix 3134 addr_nop_8(); 3135 } 3136 // Generate first nop for size between 21-12 3137 switch (i) { 3138 case 21: 3139 i -= 1; 3140 emit_int8(0x66); // size prefix 3141 case 20: 3142 case 19: 3143 i -= 1; 3144 emit_int8(0x66); // size prefix 3145 case 18: 3146 case 17: 3147 i -= 1; 3148 emit_int8(0x66); // size prefix 3149 case 16: 3150 case 15: 3151 i -= 8; 3152 addr_nop_8(); 3153 break; 3154 case 14: 3155 case 13: 3156 i -= 7; 3157 addr_nop_7(); 3158 break; 3159 case 12: 3160 i -= 6; 3161 emit_int8(0x66); // size prefix 3162 addr_nop_5(); 3163 break; 3164 default: 3165 assert(i < 12, " "); 3166 } 3167 3168 // Generate second nop for size between 11-1 3169 switch (i) { 3170 case 11: 3171 emit_int8(0x66); // size prefix 3172 case 10: 3173 emit_int8(0x66); // size prefix 3174 case 9: 3175 emit_int8(0x66); // size prefix 3176 case 8: 3177 addr_nop_8(); 3178 break; 3179 case 7: 3180 addr_nop_7(); 3181 break; 3182 case 6: 3183 emit_int8(0x66); // size prefix 3184 case 5: 3185 addr_nop_5(); 3186 break; 3187 case 4: 3188 addr_nop_4(); 3189 break; 3190 case 3: 3191 // Don't use "0x0F 0x1F 0x00" - need patching safe padding 3192 emit_int8(0x66); // size prefix 3193 case 2: 3194 emit_int8(0x66); // size prefix 3195 case 1: 3196 emit_int8((unsigned char)0x90); 3197 // nop 3198 break; 3199 default: 3200 assert(i == 0, " "); 3201 } 3202 return; 3203 } 3204 3205 if (UseAddressNop && VM_Version::is_zx()) { 3206 // 3207 // Using multi-bytes nops "0x0F 0x1F [address]" for ZX 3208 // 1: 0x90 3209 // 2: 0x66 0x90 3210 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding) 3211 // 4: 0x0F 0x1F 0x40 0x00 3212 // 5: 0x0F 0x1F 0x44 0x00 0x00 3213 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00 3214 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 3215 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 3216 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 3217 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 3218 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 3219 3220 // The rest coding is ZX specific - don't use consecutive address nops 3221 3222 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 3223 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 3224 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 3225 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 3226 3227 while (i >= 15) { 3228 // For ZX don't generate consecutive addess nops (mix with regular nops) 3229 i -= 15; 3230 emit_int8(0x66); // size prefix 3231 emit_int8(0x66); // size prefix 3232 emit_int8(0x66); // size prefix 3233 addr_nop_8(); 3234 emit_int8(0x66); // size prefix 3235 emit_int8(0x66); // size prefix 3236 emit_int8(0x66); // size prefix 3237 emit_int8((unsigned char)0x90); 3238 // nop 3239 } 3240 switch (i) { 3241 case 14: 3242 emit_int8(0x66); // size prefix 3243 case 13: 3244 emit_int8(0x66); // size prefix 3245 case 12: 3246 addr_nop_8(); 3247 emit_int8(0x66); // size prefix 3248 emit_int8(0x66); // size prefix 3249 emit_int8(0x66); // size prefix 3250 emit_int8((unsigned char)0x90); 3251 // nop 3252 break; 3253 case 11: 3254 emit_int8(0x66); // size prefix 3255 case 10: 3256 emit_int8(0x66); // size prefix 3257 case 9: 3258 emit_int8(0x66); // size prefix 3259 case 8: 3260 addr_nop_8(); 3261 break; 3262 case 7: 3263 addr_nop_7(); 3264 break; 3265 case 6: 3266 emit_int8(0x66); // size prefix 3267 case 5: 3268 addr_nop_5(); 3269 break; 3270 case 4: 3271 addr_nop_4(); 3272 break; 3273 case 3: 3274 // Don't use "0x0F 0x1F 0x00" - need patching safe padding 3275 emit_int8(0x66); // size prefix 3276 case 2: 3277 emit_int8(0x66); // size prefix 3278 case 1: 3279 emit_int8((unsigned char)0x90); 3280 // nop 3281 break; 3282 default: 3283 assert(i == 0, " "); 3284 } 3285 return; 3286 } 3287 3288 // Using nops with size prefixes "0x66 0x90". 3289 // From AMD Optimization Guide: 3290 // 1: 0x90 3291 // 2: 0x66 0x90 3292 // 3: 0x66 0x66 0x90 3293 // 4: 0x66 0x66 0x66 0x90 3294 // 5: 0x66 0x66 0x90 0x66 0x90 3295 // 6: 0x66 0x66 0x90 0x66 0x66 0x90 3296 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 3297 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90 3298 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90 3299 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90 3300 // 3301 while(i > 12) { 3302 i -= 4; 3303 emit_int8(0x66); // size prefix 3304 emit_int8(0x66); 3305 emit_int8(0x66); 3306 emit_int8((unsigned char)0x90); 3307 // nop 3308 } 3309 // 1 - 12 nops 3310 if(i > 8) { 3311 if(i > 9) { 3312 i -= 1; 3313 emit_int8(0x66); 3314 } 3315 i -= 3; 3316 emit_int8(0x66); 3317 emit_int8(0x66); 3318 emit_int8((unsigned char)0x90); 3319 } 3320 // 1 - 8 nops 3321 if(i > 4) { 3322 if(i > 6) { 3323 i -= 1; 3324 emit_int8(0x66); 3325 } 3326 i -= 3; 3327 emit_int8(0x66); 3328 emit_int8(0x66); 3329 emit_int8((unsigned char)0x90); 3330 } 3331 switch (i) { 3332 case 4: 3333 emit_int8(0x66); 3334 case 3: 3335 emit_int8(0x66); 3336 case 2: 3337 emit_int8(0x66); 3338 case 1: 3339 emit_int8((unsigned char)0x90); 3340 break; 3341 default: 3342 assert(i == 0, " "); 3343 } 3344 } 3345 3346 void Assembler::notl(Register dst) { 3347 int encode = prefix_and_encode(dst->encoding()); 3348 emit_int8((unsigned char)0xF7); 3349 emit_int8((unsigned char)(0xD0 | encode)); 3350 } 3351 3352 void Assembler::orl(Address dst, int32_t imm32) { 3353 InstructionMark im(this); 3354 prefix(dst); 3355 emit_arith_operand(0x81, rcx, dst, imm32); 3356 } 3357 3358 void Assembler::orl(Register dst, int32_t imm32) { 3359 prefix(dst); 3360 emit_arith(0x81, 0xC8, dst, imm32); 3361 } 3362 3363 void Assembler::orl(Register dst, Address src) { 3364 InstructionMark im(this); 3365 prefix(src, dst); 3366 emit_int8(0x0B); 3367 emit_operand(dst, src); 3368 } 3369 3370 void Assembler::orl(Register dst, Register src) { 3371 (void) prefix_and_encode(dst->encoding(), src->encoding()); 3372 emit_arith(0x0B, 0xC0, dst, src); 3373 } 3374 3375 void Assembler::orl(Address dst, Register src) { 3376 InstructionMark im(this); 3377 prefix(dst, src); 3378 emit_int8(0x09); 3379 emit_operand(src, dst); 3380 } 3381 3382 void Assembler::orb(Address dst, int imm8) { 3383 InstructionMark im(this); 3384 prefix(dst); 3385 emit_int8((unsigned char)0x80); 3386 emit_operand(rcx, dst, 1); 3387 emit_int8(imm8); 3388 } 3389 3390 void Assembler::packuswb(XMMRegister dst, Address src) { 3391 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 3392 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); 3393 InstructionMark im(this); 3394 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 3395 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 3396 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3397 emit_int8(0x67); 3398 emit_operand(dst, src); 3399 } 3400 3401 void Assembler::packuswb(XMMRegister dst, XMMRegister src) { 3402 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 3403 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 3404 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3405 emit_int8(0x67); 3406 emit_int8((unsigned char)(0xC0 | encode)); 3407 } 3408 3409 void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 3410 assert(UseAVX > 0, "some form of AVX must be enabled"); 3411 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 3412 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3413 emit_int8(0x67); 3414 emit_int8((unsigned char)(0xC0 | encode)); 3415 } 3416 3417 void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len) { 3418 assert(VM_Version::supports_avx2(), ""); 3419 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 3420 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3421 emit_int8(0x00); 3422 emit_int8(0xC0 | encode); 3423 emit_int8(imm8); 3424 } 3425 3426 void Assembler::vperm2i128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) { 3427 assert(VM_Version::supports_avx2(), ""); 3428 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 3429 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3430 emit_int8(0x46); 3431 emit_int8(0xC0 | encode); 3432 emit_int8(imm8); 3433 } 3434 3435 void Assembler::vperm2f128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) { 3436 assert(VM_Version::supports_avx(), ""); 3437 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 3438 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3439 emit_int8(0x06); 3440 emit_int8(0xC0 | encode); 3441 emit_int8(imm8); 3442 } 3443 3444 void Assembler::evpermi2q(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 3445 assert(VM_Version::supports_evex(), ""); 3446 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 3447 attributes.set_is_evex_instruction(); 3448 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 3449 emit_int8(0x76); 3450 emit_int8((unsigned char)(0xC0 | encode)); 3451 } 3452 3453 3454 void Assembler::pause() { 3455 emit_int8((unsigned char)0xF3); 3456 emit_int8((unsigned char)0x90); 3457 } 3458 3459 void Assembler::ud2() { 3460 emit_int8(0x0F); 3461 emit_int8(0x0B); 3462 } 3463 3464 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) { 3465 assert(VM_Version::supports_sse4_2(), ""); 3466 InstructionMark im(this); 3467 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 3468 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3469 emit_int8(0x61); 3470 emit_operand(dst, src); 3471 emit_int8(imm8); 3472 } 3473 3474 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) { 3475 assert(VM_Version::supports_sse4_2(), ""); 3476 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 3477 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3478 emit_int8(0x61); 3479 emit_int8((unsigned char)(0xC0 | encode)); 3480 emit_int8(imm8); 3481 } 3482 3483 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst 3484 void Assembler::pcmpeqb(XMMRegister dst, XMMRegister src) { 3485 assert(VM_Version::supports_sse2(), ""); 3486 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 3487 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3488 emit_int8(0x74); 3489 emit_int8((unsigned char)(0xC0 | encode)); 3490 } 3491 3492 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst 3493 void Assembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 3494 assert(VM_Version::supports_avx(), ""); 3495 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 3496 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3497 emit_int8(0x74); 3498 emit_int8((unsigned char)(0xC0 | encode)); 3499 } 3500 3501 // In this context, kdst is written the mask used to process the equal components 3502 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) { 3503 assert(VM_Version::supports_avx512bw(), ""); 3504 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 3505 attributes.set_is_evex_instruction(); 3506 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3507 emit_int8(0x74); 3508 emit_int8((unsigned char)(0xC0 | encode)); 3509 } 3510 3511 void Assembler::evpcmpgtb(KRegister kdst, XMMRegister nds, Address src, int vector_len) { 3512 assert(VM_Version::supports_avx512vlbw(), ""); 3513 InstructionMark im(this); 3514 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 3515 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 3516 attributes.set_is_evex_instruction(); 3517 int dst_enc = kdst->encoding(); 3518 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3519 emit_int8(0x64); 3520 emit_operand(as_Register(dst_enc), src); 3521 } 3522 3523 void Assembler::evpcmpgtb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len) { 3524 assert(is_vector_masking(), ""); 3525 assert(VM_Version::supports_avx512vlbw(), ""); 3526 InstructionMark im(this); 3527 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 3528 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 3529 attributes.reset_is_clear_context(); 3530 attributes.set_embedded_opmask_register_specifier(mask); 3531 attributes.set_is_evex_instruction(); 3532 int dst_enc = kdst->encoding(); 3533 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3534 emit_int8(0x64); 3535 emit_operand(as_Register(dst_enc), src); 3536 } 3537 3538 void Assembler::evpcmpuw(KRegister kdst, XMMRegister nds, XMMRegister src, ComparisonPredicate vcc, int vector_len) { 3539 assert(VM_Version::supports_avx512vlbw(), ""); 3540 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 3541 attributes.set_is_evex_instruction(); 3542 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3543 emit_int8(0x3E); 3544 emit_int8((unsigned char)(0xC0 | encode)); 3545 emit_int8(vcc); 3546 } 3547 3548 void Assembler::evpcmpuw(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, ComparisonPredicate vcc, int vector_len) { 3549 assert(is_vector_masking(), ""); 3550 assert(VM_Version::supports_avx512vlbw(), ""); 3551 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 3552 attributes.reset_is_clear_context(); 3553 attributes.set_embedded_opmask_register_specifier(mask); 3554 attributes.set_is_evex_instruction(); 3555 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3556 emit_int8(0x3E); 3557 emit_int8((unsigned char)(0xC0 | encode)); 3558 emit_int8(vcc); 3559 } 3560 3561 void Assembler::evpcmpuw(KRegister kdst, XMMRegister nds, Address src, ComparisonPredicate vcc, int vector_len) { 3562 assert(VM_Version::supports_avx512vlbw(), ""); 3563 InstructionMark im(this); 3564 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 3565 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 3566 attributes.set_is_evex_instruction(); 3567 int dst_enc = kdst->encoding(); 3568 vex_prefix(src, nds->encoding(), kdst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3569 emit_int8(0x3E); 3570 emit_operand(as_Register(dst_enc), src); 3571 emit_int8(vcc); 3572 } 3573 3574 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, Address src, int vector_len) { 3575 assert(VM_Version::supports_avx512bw(), ""); 3576 InstructionMark im(this); 3577 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 3578 attributes.set_is_evex_instruction(); 3579 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 3580 int dst_enc = kdst->encoding(); 3581 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3582 emit_int8(0x74); 3583 emit_operand(as_Register(dst_enc), src); 3584 } 3585 3586 void Assembler::evpcmpeqb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len) { 3587 assert(VM_Version::supports_avx512vlbw(), ""); 3588 assert(is_vector_masking(), ""); // For stub code use only 3589 InstructionMark im(this); 3590 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_reg_mask */ false, /* uses_vl */ true); 3591 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 3592 attributes.reset_is_clear_context(); 3593 attributes.set_embedded_opmask_register_specifier(mask); 3594 attributes.set_is_evex_instruction(); 3595 vex_prefix(src, nds->encoding(), kdst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3596 emit_int8(0x74); 3597 emit_operand(as_Register(kdst->encoding()), src); 3598 } 3599 3600 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst 3601 void Assembler::pcmpeqw(XMMRegister dst, XMMRegister src) { 3602 assert(VM_Version::supports_sse2(), ""); 3603 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 3604 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3605 emit_int8(0x75); 3606 emit_int8((unsigned char)(0xC0 | encode)); 3607 } 3608 3609 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst 3610 void Assembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 3611 assert(VM_Version::supports_avx(), ""); 3612 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 3613 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3614 emit_int8(0x75); 3615 emit_int8((unsigned char)(0xC0 | encode)); 3616 } 3617 3618 // In this context, kdst is written the mask used to process the equal components 3619 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) { 3620 assert(VM_Version::supports_avx512bw(), ""); 3621 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 3622 attributes.set_is_evex_instruction(); 3623 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3624 emit_int8(0x75); 3625 emit_int8((unsigned char)(0xC0 | encode)); 3626 } 3627 3628 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, Address src, int vector_len) { 3629 assert(VM_Version::supports_avx512bw(), ""); 3630 InstructionMark im(this); 3631 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 3632 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 3633 attributes.set_is_evex_instruction(); 3634 int dst_enc = kdst->encoding(); 3635 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3636 emit_int8(0x75); 3637 emit_operand(as_Register(dst_enc), src); 3638 } 3639 3640 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst 3641 void Assembler::pcmpeqd(XMMRegister dst, XMMRegister src) { 3642 assert(VM_Version::supports_sse2(), ""); 3643 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 3644 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3645 emit_int8(0x76); 3646 emit_int8((unsigned char)(0xC0 | encode)); 3647 } 3648 3649 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst 3650 void Assembler::vpcmpeqd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 3651 assert(VM_Version::supports_avx(), ""); 3652 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 3653 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3654 emit_int8(0x76); 3655 emit_int8((unsigned char)(0xC0 | encode)); 3656 } 3657 3658 // In this context, kdst is written the mask used to process the equal components 3659 void Assembler::evpcmpeqd(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) { 3660 assert(VM_Version::supports_evex(), ""); 3661 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 3662 attributes.set_is_evex_instruction(); 3663 attributes.reset_is_clear_context(); 3664 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3665 emit_int8(0x76); 3666 emit_int8((unsigned char)(0xC0 | encode)); 3667 } 3668 3669 void Assembler::evpcmpeqd(KRegister kdst, XMMRegister nds, Address src, int vector_len) { 3670 assert(VM_Version::supports_evex(), ""); 3671 InstructionMark im(this); 3672 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 3673 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 3674 attributes.reset_is_clear_context(); 3675 attributes.set_is_evex_instruction(); 3676 int dst_enc = kdst->encoding(); 3677 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3678 emit_int8(0x76); 3679 emit_operand(as_Register(dst_enc), src); 3680 } 3681 3682 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst 3683 void Assembler::pcmpeqq(XMMRegister dst, XMMRegister src) { 3684 assert(VM_Version::supports_sse4_1(), ""); 3685 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 3686 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 3687 emit_int8(0x29); 3688 emit_int8((unsigned char)(0xC0 | encode)); 3689 } 3690 3691 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst 3692 void Assembler::vpcmpeqq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 3693 assert(VM_Version::supports_avx(), ""); 3694 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 3695 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 3696 emit_int8(0x29); 3697 emit_int8((unsigned char)(0xC0 | encode)); 3698 } 3699 3700 // In this context, kdst is written the mask used to process the equal components 3701 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) { 3702 assert(VM_Version::supports_evex(), ""); 3703 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 3704 attributes.reset_is_clear_context(); 3705 attributes.set_is_evex_instruction(); 3706 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 3707 emit_int8(0x29); 3708 emit_int8((unsigned char)(0xC0 | encode)); 3709 } 3710 3711 // In this context, kdst is written the mask used to process the equal components 3712 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, Address src, int vector_len) { 3713 assert(VM_Version::supports_evex(), ""); 3714 InstructionMark im(this); 3715 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 3716 attributes.reset_is_clear_context(); 3717 attributes.set_is_evex_instruction(); 3718 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 3719 int dst_enc = kdst->encoding(); 3720 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 3721 emit_int8(0x29); 3722 emit_operand(as_Register(dst_enc), src); 3723 } 3724 3725 void Assembler::pmovmskb(Register dst, XMMRegister src) { 3726 assert(VM_Version::supports_sse2(), ""); 3727 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 3728 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3729 emit_int8((unsigned char)0xD7); 3730 emit_int8((unsigned char)(0xC0 | encode)); 3731 } 3732 3733 void Assembler::vpmovmskb(Register dst, XMMRegister src) { 3734 assert(VM_Version::supports_avx2(), ""); 3735 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 3736 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3737 emit_int8((unsigned char)0xD7); 3738 emit_int8((unsigned char)(0xC0 | encode)); 3739 } 3740 3741 void Assembler::pextrd(Register dst, XMMRegister src, int imm8) { 3742 assert(VM_Version::supports_sse4_1(), ""); 3743 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true); 3744 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3745 emit_int8(0x16); 3746 emit_int8((unsigned char)(0xC0 | encode)); 3747 emit_int8(imm8); 3748 } 3749 3750 void Assembler::pextrd(Address dst, XMMRegister src, int imm8) { 3751 assert(VM_Version::supports_sse4_1(), ""); 3752 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true); 3753 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 3754 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3755 emit_int8(0x16); 3756 emit_operand(src, dst); 3757 emit_int8(imm8); 3758 } 3759 3760 void Assembler::pextrq(Register dst, XMMRegister src, int imm8) { 3761 assert(VM_Version::supports_sse4_1(), ""); 3762 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true); 3763 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3764 emit_int8(0x16); 3765 emit_int8((unsigned char)(0xC0 | encode)); 3766 emit_int8(imm8); 3767 } 3768 3769 void Assembler::pextrq(Address dst, XMMRegister src, int imm8) { 3770 assert(VM_Version::supports_sse4_1(), ""); 3771 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true); 3772 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 3773 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3774 emit_int8(0x16); 3775 emit_operand(src, dst); 3776 emit_int8(imm8); 3777 } 3778 3779 void Assembler::pextrw(Register dst, XMMRegister src, int imm8) { 3780 assert(VM_Version::supports_sse2(), ""); 3781 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 3782 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3783 emit_int8((unsigned char)0xC5); 3784 emit_int8((unsigned char)(0xC0 | encode)); 3785 emit_int8(imm8); 3786 } 3787 3788 void Assembler::pextrw(Address dst, XMMRegister src, int imm8) { 3789 assert(VM_Version::supports_sse4_1(), ""); 3790 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 3791 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit); 3792 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3793 emit_int8((unsigned char)0x15); 3794 emit_operand(src, dst); 3795 emit_int8(imm8); 3796 } 3797 3798 void Assembler::pextrb(Address dst, XMMRegister src, int imm8) { 3799 assert(VM_Version::supports_sse4_1(), ""); 3800 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 3801 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit); 3802 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3803 emit_int8(0x14); 3804 emit_operand(src, dst); 3805 emit_int8(imm8); 3806 } 3807 3808 void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) { 3809 assert(VM_Version::supports_sse4_1(), ""); 3810 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true); 3811 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3812 emit_int8(0x22); 3813 emit_int8((unsigned char)(0xC0 | encode)); 3814 emit_int8(imm8); 3815 } 3816 3817 void Assembler::pinsrd(XMMRegister dst, Address src, int imm8) { 3818 assert(VM_Version::supports_sse4_1(), ""); 3819 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true); 3820 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 3821 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3822 emit_int8(0x22); 3823 emit_operand(dst,src); 3824 emit_int8(imm8); 3825 } 3826 3827 void Assembler::pinsrq(XMMRegister dst, Register src, int imm8) { 3828 assert(VM_Version::supports_sse4_1(), ""); 3829 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true); 3830 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3831 emit_int8(0x22); 3832 emit_int8((unsigned char)(0xC0 | encode)); 3833 emit_int8(imm8); 3834 } 3835 3836 void Assembler::pinsrq(XMMRegister dst, Address src, int imm8) { 3837 assert(VM_Version::supports_sse4_1(), ""); 3838 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true); 3839 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 3840 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3841 emit_int8(0x22); 3842 emit_operand(dst, src); 3843 emit_int8(imm8); 3844 } 3845 3846 void Assembler::pinsrw(XMMRegister dst, Register src, int imm8) { 3847 assert(VM_Version::supports_sse2(), ""); 3848 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 3849 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3850 emit_int8((unsigned char)0xC4); 3851 emit_int8((unsigned char)(0xC0 | encode)); 3852 emit_int8(imm8); 3853 } 3854 3855 void Assembler::pinsrw(XMMRegister dst, Address src, int imm8) { 3856 assert(VM_Version::supports_sse2(), ""); 3857 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 3858 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit); 3859 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3860 emit_int8((unsigned char)0xC4); 3861 emit_operand(dst, src); 3862 emit_int8(imm8); 3863 } 3864 3865 void Assembler::pinsrb(XMMRegister dst, Address src, int imm8) { 3866 assert(VM_Version::supports_sse4_1(), ""); 3867 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 3868 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit); 3869 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3870 emit_int8(0x20); 3871 emit_operand(dst, src); 3872 emit_int8(imm8); 3873 } 3874 3875 void Assembler::pmovzxbw(XMMRegister dst, Address src) { 3876 assert(VM_Version::supports_sse4_1(), ""); 3877 InstructionMark im(this); 3878 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 3879 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit); 3880 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 3881 emit_int8(0x30); 3882 emit_operand(dst, src); 3883 } 3884 3885 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) { 3886 assert(VM_Version::supports_sse4_1(), ""); 3887 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 3888 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 3889 emit_int8(0x30); 3890 emit_int8((unsigned char)(0xC0 | encode)); 3891 } 3892 3893 void Assembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) { 3894 assert(VM_Version::supports_avx(), ""); 3895 InstructionMark im(this); 3896 assert(dst != xnoreg, "sanity"); 3897 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 3898 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit); 3899 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 3900 emit_int8(0x30); 3901 emit_operand(dst, src); 3902 } 3903 3904 void Assembler::vpmovzxbw(XMMRegister dst, XMMRegister src, int vector_len) { 3905 assert(vector_len == AVX_128bit? VM_Version::supports_avx() : 3906 vector_len == AVX_256bit? VM_Version::supports_avx2() : 3907 vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0, ""); 3908 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 3909 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 3910 emit_int8(0x30); 3911 emit_int8((unsigned char) (0xC0 | encode)); 3912 } 3913 3914 3915 void Assembler::evpmovzxbw(XMMRegister dst, KRegister mask, Address src, int vector_len) { 3916 assert(is_vector_masking(), ""); 3917 assert(VM_Version::supports_avx512vlbw(), ""); 3918 assert(dst != xnoreg, "sanity"); 3919 InstructionMark im(this); 3920 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 3921 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit); 3922 attributes.set_embedded_opmask_register_specifier(mask); 3923 attributes.set_is_evex_instruction(); 3924 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 3925 emit_int8(0x30); 3926 emit_operand(dst, src); 3927 } 3928 void Assembler::evpmovwb(Address dst, XMMRegister src, int vector_len) { 3929 assert(VM_Version::supports_avx512vlbw(), ""); 3930 assert(src != xnoreg, "sanity"); 3931 InstructionMark im(this); 3932 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 3933 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit); 3934 attributes.set_is_evex_instruction(); 3935 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes); 3936 emit_int8(0x30); 3937 emit_operand(src, dst); 3938 } 3939 3940 void Assembler::evpmovwb(Address dst, KRegister mask, XMMRegister src, int vector_len) { 3941 assert(is_vector_masking(), ""); 3942 assert(VM_Version::supports_avx512vlbw(), ""); 3943 assert(src != xnoreg, "sanity"); 3944 InstructionMark im(this); 3945 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 3946 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit); 3947 attributes.reset_is_clear_context(); 3948 attributes.set_embedded_opmask_register_specifier(mask); 3949 attributes.set_is_evex_instruction(); 3950 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes); 3951 emit_int8(0x30); 3952 emit_operand(src, dst); 3953 } 3954 3955 void Assembler::evpmovdb(Address dst, XMMRegister src, int vector_len) { 3956 assert(VM_Version::supports_evex(), ""); 3957 assert(src != xnoreg, "sanity"); 3958 InstructionMark im(this); 3959 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 3960 attributes.set_address_attributes(/* tuple_type */ EVEX_QVM, /* input_size_in_bits */ EVEX_NObit); 3961 attributes.set_is_evex_instruction(); 3962 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes); 3963 emit_int8(0x31); 3964 emit_operand(src, dst); 3965 } 3966 3967 void Assembler::vpmovzxwd(XMMRegister dst, XMMRegister src, int vector_len) { 3968 assert(vector_len == AVX_128bit? VM_Version::supports_avx() : 3969 vector_len == AVX_256bit? VM_Version::supports_avx2() : 3970 vector_len == AVX_512bit? VM_Version::supports_evex() : 0, " "); 3971 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 3972 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 3973 emit_int8(0x33); 3974 emit_int8((unsigned char)(0xC0 | encode)); 3975 } 3976 3977 // generic 3978 void Assembler::pop(Register dst) { 3979 int encode = prefix_and_encode(dst->encoding()); 3980 emit_int8(0x58 | encode); 3981 } 3982 3983 void Assembler::popcntl(Register dst, Address src) { 3984 assert(VM_Version::supports_popcnt(), "must support"); 3985 InstructionMark im(this); 3986 emit_int8((unsigned char)0xF3); 3987 prefix(src, dst); 3988 emit_int8(0x0F); 3989 emit_int8((unsigned char)0xB8); 3990 emit_operand(dst, src); 3991 } 3992 3993 void Assembler::popcntl(Register dst, Register src) { 3994 assert(VM_Version::supports_popcnt(), "must support"); 3995 emit_int8((unsigned char)0xF3); 3996 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 3997 emit_int8(0x0F); 3998 emit_int8((unsigned char)0xB8); 3999 emit_int8((unsigned char)(0xC0 | encode)); 4000 } 4001 4002 void Assembler::vpopcntd(XMMRegister dst, XMMRegister src, int vector_len) { 4003 assert(VM_Version::supports_vpopcntdq(), "must support vpopcntdq feature"); 4004 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 4005 attributes.set_is_evex_instruction(); 4006 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 4007 emit_int8(0x55); 4008 emit_int8((unsigned char)(0xC0 | encode)); 4009 } 4010 4011 void Assembler::popf() { 4012 emit_int8((unsigned char)0x9D); 4013 } 4014 4015 #ifndef _LP64 // no 32bit push/pop on amd64 4016 void Assembler::popl(Address dst) { 4017 // NOTE: this will adjust stack by 8byte on 64bits 4018 InstructionMark im(this); 4019 prefix(dst); 4020 emit_int8((unsigned char)0x8F); 4021 emit_operand(rax, dst); 4022 } 4023 #endif 4024 4025 void Assembler::prefetch_prefix(Address src) { 4026 prefix(src); 4027 emit_int8(0x0F); 4028 } 4029 4030 void Assembler::prefetchnta(Address src) { 4031 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); 4032 InstructionMark im(this); 4033 prefetch_prefix(src); 4034 emit_int8(0x18); 4035 emit_operand(rax, src); // 0, src 4036 } 4037 4038 void Assembler::prefetchr(Address src) { 4039 assert(VM_Version::supports_3dnow_prefetch(), "must support"); 4040 InstructionMark im(this); 4041 prefetch_prefix(src); 4042 emit_int8(0x0D); 4043 emit_operand(rax, src); // 0, src 4044 } 4045 4046 void Assembler::prefetcht0(Address src) { 4047 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); 4048 InstructionMark im(this); 4049 prefetch_prefix(src); 4050 emit_int8(0x18); 4051 emit_operand(rcx, src); // 1, src 4052 } 4053 4054 void Assembler::prefetcht1(Address src) { 4055 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); 4056 InstructionMark im(this); 4057 prefetch_prefix(src); 4058 emit_int8(0x18); 4059 emit_operand(rdx, src); // 2, src 4060 } 4061 4062 void Assembler::prefetcht2(Address src) { 4063 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); 4064 InstructionMark im(this); 4065 prefetch_prefix(src); 4066 emit_int8(0x18); 4067 emit_operand(rbx, src); // 3, src 4068 } 4069 4070 void Assembler::prefetchw(Address src) { 4071 assert(VM_Version::supports_3dnow_prefetch(), "must support"); 4072 InstructionMark im(this); 4073 prefetch_prefix(src); 4074 emit_int8(0x0D); 4075 emit_operand(rcx, src); // 1, src 4076 } 4077 4078 void Assembler::prefix(Prefix p) { 4079 emit_int8(p); 4080 } 4081 4082 void Assembler::pshufb(XMMRegister dst, XMMRegister src) { 4083 assert(VM_Version::supports_ssse3(), ""); 4084 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 4085 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 4086 emit_int8(0x00); 4087 emit_int8((unsigned char)(0xC0 | encode)); 4088 } 4089 4090 void Assembler::vpshufb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4091 assert(vector_len == AVX_128bit? VM_Version::supports_avx() : 4092 vector_len == AVX_256bit? VM_Version::supports_avx2() : 4093 0, ""); 4094 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 4095 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 4096 emit_int8(0x00); 4097 emit_int8((unsigned char)(0xC0 | encode)); 4098 } 4099 4100 void Assembler::pshufb(XMMRegister dst, Address src) { 4101 assert(VM_Version::supports_ssse3(), ""); 4102 InstructionMark im(this); 4103 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 4104 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 4105 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 4106 emit_int8(0x00); 4107 emit_operand(dst, src); 4108 } 4109 4110 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) { 4111 assert(isByte(mode), "invalid value"); 4112 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4113 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit; 4114 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 4115 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4116 emit_int8(0x70); 4117 emit_int8((unsigned char)(0xC0 | encode)); 4118 emit_int8(mode & 0xFF); 4119 } 4120 4121 void Assembler::vpshufd(XMMRegister dst, XMMRegister src, int mode, int vector_len) { 4122 assert(vector_len == AVX_128bit? VM_Version::supports_avx() : 4123 vector_len == AVX_256bit? VM_Version::supports_avx2() : 4124 0, ""); 4125 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4126 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 4127 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4128 emit_int8(0x70); 4129 emit_int8((unsigned char)(0xC0 | encode)); 4130 emit_int8(mode & 0xFF); 4131 } 4132 4133 void Assembler::pshufd(XMMRegister dst, Address src, int mode) { 4134 assert(isByte(mode), "invalid value"); 4135 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4136 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); 4137 InstructionMark im(this); 4138 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 4139 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 4140 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4141 emit_int8(0x70); 4142 emit_operand(dst, src); 4143 emit_int8(mode & 0xFF); 4144 } 4145 4146 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) { 4147 assert(isByte(mode), "invalid value"); 4148 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4149 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 4150 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 4151 emit_int8(0x70); 4152 emit_int8((unsigned char)(0xC0 | encode)); 4153 emit_int8(mode & 0xFF); 4154 } 4155 4156 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) { 4157 assert(isByte(mode), "invalid value"); 4158 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4159 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); 4160 InstructionMark im(this); 4161 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 4162 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 4163 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 4164 emit_int8(0x70); 4165 emit_operand(dst, src); 4166 emit_int8(mode & 0xFF); 4167 } 4168 void Assembler::evshufi64x2(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) { 4169 assert(VM_Version::supports_evex(), "requires EVEX support"); 4170 assert(vector_len == Assembler::AVX_256bit || vector_len == Assembler::AVX_512bit, ""); 4171 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 4172 attributes.set_is_evex_instruction(); 4173 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 4174 emit_int8(0x43); 4175 emit_int8((unsigned char)(0xC0 | encode)); 4176 emit_int8(imm8 & 0xFF); 4177 } 4178 4179 void Assembler::psrldq(XMMRegister dst, int shift) { 4180 // Shift left 128 bit value in dst XMMRegister by shift number of bytes. 4181 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4182 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 4183 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4184 emit_int8(0x73); 4185 emit_int8((unsigned char)(0xC0 | encode)); 4186 emit_int8(shift); 4187 } 4188 4189 void Assembler::pslldq(XMMRegister dst, int shift) { 4190 // Shift left 128 bit value in dst XMMRegister by shift number of bytes. 4191 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4192 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 4193 // XMM7 is for /7 encoding: 66 0F 73 /7 ib 4194 int encode = simd_prefix_and_encode(xmm7, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4195 emit_int8(0x73); 4196 emit_int8((unsigned char)(0xC0 | encode)); 4197 emit_int8(shift); 4198 } 4199 4200 void Assembler::ptest(XMMRegister dst, Address src) { 4201 assert(VM_Version::supports_sse4_1(), ""); 4202 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); 4203 InstructionMark im(this); 4204 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 4205 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 4206 emit_int8(0x17); 4207 emit_operand(dst, src); 4208 } 4209 4210 void Assembler::ptest(XMMRegister dst, XMMRegister src) { 4211 assert(VM_Version::supports_sse4_1(), ""); 4212 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 4213 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 4214 emit_int8(0x17); 4215 emit_int8((unsigned char)(0xC0 | encode)); 4216 } 4217 4218 void Assembler::vptest(XMMRegister dst, Address src) { 4219 assert(VM_Version::supports_avx(), ""); 4220 InstructionMark im(this); 4221 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 4222 assert(dst != xnoreg, "sanity"); 4223 // swap src<->dst for encoding 4224 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 4225 emit_int8(0x17); 4226 emit_operand(dst, src); 4227 } 4228 4229 void Assembler::vptest(XMMRegister dst, XMMRegister src) { 4230 assert(VM_Version::supports_avx(), ""); 4231 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 4232 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 4233 emit_int8(0x17); 4234 emit_int8((unsigned char)(0xC0 | encode)); 4235 } 4236 4237 void Assembler::punpcklbw(XMMRegister dst, Address src) { 4238 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4239 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); 4240 InstructionMark im(this); 4241 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ false, /* uses_vl */ true); 4242 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 4243 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4244 emit_int8(0x60); 4245 emit_operand(dst, src); 4246 } 4247 4248 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) { 4249 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4250 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ false, /* uses_vl */ true); 4251 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4252 emit_int8(0x60); 4253 emit_int8((unsigned char)(0xC0 | encode)); 4254 } 4255 4256 void Assembler::punpckldq(XMMRegister dst, Address src) { 4257 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4258 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); 4259 InstructionMark im(this); 4260 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 4261 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 4262 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4263 emit_int8(0x62); 4264 emit_operand(dst, src); 4265 } 4266 4267 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) { 4268 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4269 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 4270 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4271 emit_int8(0x62); 4272 emit_int8((unsigned char)(0xC0 | encode)); 4273 } 4274 4275 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) { 4276 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4277 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 4278 attributes.set_rex_vex_w_reverted(); 4279 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4280 emit_int8(0x6C); 4281 emit_int8((unsigned char)(0xC0 | encode)); 4282 } 4283 4284 void Assembler::push(int32_t imm32) { 4285 // in 64bits we push 64bits onto the stack but only 4286 // take a 32bit immediate 4287 emit_int8(0x68); 4288 emit_int32(imm32); 4289 } 4290 4291 void Assembler::push(Register src) { 4292 int encode = prefix_and_encode(src->encoding()); 4293 4294 emit_int8(0x50 | encode); 4295 } 4296 4297 void Assembler::pushf() { 4298 emit_int8((unsigned char)0x9C); 4299 } 4300 4301 #ifndef _LP64 // no 32bit push/pop on amd64 4302 void Assembler::pushl(Address src) { 4303 // Note this will push 64bit on 64bit 4304 InstructionMark im(this); 4305 prefix(src); 4306 emit_int8((unsigned char)0xFF); 4307 emit_operand(rsi, src); 4308 } 4309 #endif 4310 4311 void Assembler::rcll(Register dst, int imm8) { 4312 assert(isShiftCount(imm8), "illegal shift count"); 4313 int encode = prefix_and_encode(dst->encoding()); 4314 if (imm8 == 1) { 4315 emit_int8((unsigned char)0xD1); 4316 emit_int8((unsigned char)(0xD0 | encode)); 4317 } else { 4318 emit_int8((unsigned char)0xC1); 4319 emit_int8((unsigned char)0xD0 | encode); 4320 emit_int8(imm8); 4321 } 4322 } 4323 4324 void Assembler::rcpps(XMMRegister dst, XMMRegister src) { 4325 NOT_LP64(assert(VM_Version::supports_sse(), "")); 4326 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 4327 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 4328 emit_int8(0x53); 4329 emit_int8((unsigned char)(0xC0 | encode)); 4330 } 4331 4332 void Assembler::rcpss(XMMRegister dst, XMMRegister src) { 4333 NOT_LP64(assert(VM_Version::supports_sse(), "")); 4334 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 4335 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 4336 emit_int8(0x53); 4337 emit_int8((unsigned char)(0xC0 | encode)); 4338 } 4339 4340 void Assembler::rdtsc() { 4341 emit_int8((unsigned char)0x0F); 4342 emit_int8((unsigned char)0x31); 4343 } 4344 4345 // copies data from [esi] to [edi] using rcx pointer sized words 4346 // generic 4347 void Assembler::rep_mov() { 4348 emit_int8((unsigned char)0xF3); 4349 // MOVSQ 4350 LP64_ONLY(prefix(REX_W)); 4351 emit_int8((unsigned char)0xA5); 4352 } 4353 4354 // sets rcx bytes with rax, value at [edi] 4355 void Assembler::rep_stosb() { 4356 emit_int8((unsigned char)0xF3); // REP 4357 LP64_ONLY(prefix(REX_W)); 4358 emit_int8((unsigned char)0xAA); // STOSB 4359 } 4360 4361 // sets rcx pointer sized words with rax, value at [edi] 4362 // generic 4363 void Assembler::rep_stos() { 4364 emit_int8((unsigned char)0xF3); // REP 4365 LP64_ONLY(prefix(REX_W)); // LP64:STOSQ, LP32:STOSD 4366 emit_int8((unsigned char)0xAB); 4367 } 4368 4369 // scans rcx pointer sized words at [edi] for occurance of rax, 4370 // generic 4371 void Assembler::repne_scan() { // repne_scan 4372 emit_int8((unsigned char)0xF2); 4373 // SCASQ 4374 LP64_ONLY(prefix(REX_W)); 4375 emit_int8((unsigned char)0xAF); 4376 } 4377 4378 #ifdef _LP64 4379 // scans rcx 4 byte words at [edi] for occurance of rax, 4380 // generic 4381 void Assembler::repne_scanl() { // repne_scan 4382 emit_int8((unsigned char)0xF2); 4383 // SCASL 4384 emit_int8((unsigned char)0xAF); 4385 } 4386 #endif 4387 4388 void Assembler::ret(int imm16) { 4389 if (imm16 == 0) { 4390 emit_int8((unsigned char)0xC3); 4391 } else { 4392 emit_int8((unsigned char)0xC2); 4393 emit_int16(imm16); 4394 } 4395 } 4396 4397 void Assembler::sahf() { 4398 #ifdef _LP64 4399 // Not supported in 64bit mode 4400 ShouldNotReachHere(); 4401 #endif 4402 emit_int8((unsigned char)0x9E); 4403 } 4404 4405 void Assembler::sarl(Register dst, int imm8) { 4406 int encode = prefix_and_encode(dst->encoding()); 4407 assert(isShiftCount(imm8), "illegal shift count"); 4408 if (imm8 == 1) { 4409 emit_int8((unsigned char)0xD1); 4410 emit_int8((unsigned char)(0xF8 | encode)); 4411 } else { 4412 emit_int8((unsigned char)0xC1); 4413 emit_int8((unsigned char)(0xF8 | encode)); 4414 emit_int8(imm8); 4415 } 4416 } 4417 4418 void Assembler::sarl(Register dst) { 4419 int encode = prefix_and_encode(dst->encoding()); 4420 emit_int8((unsigned char)0xD3); 4421 emit_int8((unsigned char)(0xF8 | encode)); 4422 } 4423 4424 void Assembler::sbbl(Address dst, int32_t imm32) { 4425 InstructionMark im(this); 4426 prefix(dst); 4427 emit_arith_operand(0x81, rbx, dst, imm32); 4428 } 4429 4430 void Assembler::sbbl(Register dst, int32_t imm32) { 4431 prefix(dst); 4432 emit_arith(0x81, 0xD8, dst, imm32); 4433 } 4434 4435 4436 void Assembler::sbbl(Register dst, Address src) { 4437 InstructionMark im(this); 4438 prefix(src, dst); 4439 emit_int8(0x1B); 4440 emit_operand(dst, src); 4441 } 4442 4443 void Assembler::sbbl(Register dst, Register src) { 4444 (void) prefix_and_encode(dst->encoding(), src->encoding()); 4445 emit_arith(0x1B, 0xC0, dst, src); 4446 } 4447 4448 void Assembler::setb(Condition cc, Register dst) { 4449 assert(0 <= cc && cc < 16, "illegal cc"); 4450 int encode = prefix_and_encode(dst->encoding(), true); 4451 emit_int8(0x0F); 4452 emit_int8((unsigned char)0x90 | cc); 4453 emit_int8((unsigned char)(0xC0 | encode)); 4454 } 4455 4456 void Assembler::palignr(XMMRegister dst, XMMRegister src, int imm8) { 4457 assert(VM_Version::supports_ssse3(), ""); 4458 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true); 4459 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 4460 emit_int8((unsigned char)0x0F); 4461 emit_int8((unsigned char)(0xC0 | encode)); 4462 emit_int8(imm8); 4463 } 4464 4465 void Assembler::vpalignr(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) { 4466 assert(vector_len == AVX_128bit? VM_Version::supports_avx() : 4467 vector_len == AVX_256bit? VM_Version::supports_avx2() : 4468 0, ""); 4469 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true); 4470 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 4471 emit_int8((unsigned char)0x0F); 4472 emit_int8((unsigned char)(0xC0 | encode)); 4473 emit_int8(imm8); 4474 } 4475 4476 void Assembler::evalignq(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) { 4477 assert(VM_Version::supports_evex(), ""); 4478 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 4479 attributes.set_is_evex_instruction(); 4480 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 4481 emit_int8(0x3); 4482 emit_int8((unsigned char)(0xC0 | encode)); 4483 emit_int8(imm8); 4484 } 4485 4486 void Assembler::pblendw(XMMRegister dst, XMMRegister src, int imm8) { 4487 assert(VM_Version::supports_sse4_1(), ""); 4488 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 4489 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 4490 emit_int8((unsigned char)0x0E); 4491 emit_int8((unsigned char)(0xC0 | encode)); 4492 emit_int8(imm8); 4493 } 4494 4495 void Assembler::sha1rnds4(XMMRegister dst, XMMRegister src, int imm8) { 4496 assert(VM_Version::supports_sha(), ""); 4497 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3A, /* rex_w */ false); 4498 emit_int8((unsigned char)0xCC); 4499 emit_int8((unsigned char)(0xC0 | encode)); 4500 emit_int8((unsigned char)imm8); 4501 } 4502 4503 void Assembler::sha1nexte(XMMRegister dst, XMMRegister src) { 4504 assert(VM_Version::supports_sha(), ""); 4505 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false); 4506 emit_int8((unsigned char)0xC8); 4507 emit_int8((unsigned char)(0xC0 | encode)); 4508 } 4509 4510 void Assembler::sha1msg1(XMMRegister dst, XMMRegister src) { 4511 assert(VM_Version::supports_sha(), ""); 4512 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false); 4513 emit_int8((unsigned char)0xC9); 4514 emit_int8((unsigned char)(0xC0 | encode)); 4515 } 4516 4517 void Assembler::sha1msg2(XMMRegister dst, XMMRegister src) { 4518 assert(VM_Version::supports_sha(), ""); 4519 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false); 4520 emit_int8((unsigned char)0xCA); 4521 emit_int8((unsigned char)(0xC0 | encode)); 4522 } 4523 4524 // xmm0 is implicit additional source to this instruction. 4525 void Assembler::sha256rnds2(XMMRegister dst, XMMRegister src) { 4526 assert(VM_Version::supports_sha(), ""); 4527 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false); 4528 emit_int8((unsigned char)0xCB); 4529 emit_int8((unsigned char)(0xC0 | encode)); 4530 } 4531 4532 void Assembler::sha256msg1(XMMRegister dst, XMMRegister src) { 4533 assert(VM_Version::supports_sha(), ""); 4534 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false); 4535 emit_int8((unsigned char)0xCC); 4536 emit_int8((unsigned char)(0xC0 | encode)); 4537 } 4538 4539 void Assembler::sha256msg2(XMMRegister dst, XMMRegister src) { 4540 assert(VM_Version::supports_sha(), ""); 4541 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false); 4542 emit_int8((unsigned char)0xCD); 4543 emit_int8((unsigned char)(0xC0 | encode)); 4544 } 4545 4546 4547 void Assembler::shll(Register dst, int imm8) { 4548 assert(isShiftCount(imm8), "illegal shift count"); 4549 int encode = prefix_and_encode(dst->encoding()); 4550 if (imm8 == 1 ) { 4551 emit_int8((unsigned char)0xD1); 4552 emit_int8((unsigned char)(0xE0 | encode)); 4553 } else { 4554 emit_int8((unsigned char)0xC1); 4555 emit_int8((unsigned char)(0xE0 | encode)); 4556 emit_int8(imm8); 4557 } 4558 } 4559 4560 void Assembler::shll(Register dst) { 4561 int encode = prefix_and_encode(dst->encoding()); 4562 emit_int8((unsigned char)0xD3); 4563 emit_int8((unsigned char)(0xE0 | encode)); 4564 } 4565 4566 void Assembler::shrl(Register dst, int imm8) { 4567 assert(isShiftCount(imm8), "illegal shift count"); 4568 int encode = prefix_and_encode(dst->encoding()); 4569 emit_int8((unsigned char)0xC1); 4570 emit_int8((unsigned char)(0xE8 | encode)); 4571 emit_int8(imm8); 4572 } 4573 4574 void Assembler::shrl(Register dst) { 4575 int encode = prefix_and_encode(dst->encoding()); 4576 emit_int8((unsigned char)0xD3); 4577 emit_int8((unsigned char)(0xE8 | encode)); 4578 } 4579 4580 // copies a single word from [esi] to [edi] 4581 void Assembler::smovl() { 4582 emit_int8((unsigned char)0xA5); 4583 } 4584 4585 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) { 4586 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4587 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4588 attributes.set_rex_vex_w_reverted(); 4589 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 4590 emit_int8(0x51); 4591 emit_int8((unsigned char)(0xC0 | encode)); 4592 } 4593 4594 void Assembler::sqrtsd(XMMRegister dst, Address src) { 4595 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4596 InstructionMark im(this); 4597 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4598 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 4599 attributes.set_rex_vex_w_reverted(); 4600 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 4601 emit_int8(0x51); 4602 emit_operand(dst, src); 4603 } 4604 4605 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) { 4606 NOT_LP64(assert(VM_Version::supports_sse(), "")); 4607 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4608 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 4609 emit_int8(0x51); 4610 emit_int8((unsigned char)(0xC0 | encode)); 4611 } 4612 4613 void Assembler::std() { 4614 emit_int8((unsigned char)0xFD); 4615 } 4616 4617 void Assembler::sqrtss(XMMRegister dst, Address src) { 4618 NOT_LP64(assert(VM_Version::supports_sse(), "")); 4619 InstructionMark im(this); 4620 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4621 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 4622 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 4623 emit_int8(0x51); 4624 emit_operand(dst, src); 4625 } 4626 4627 void Assembler::stmxcsr( Address dst) { 4628 if (UseAVX > 0 ) { 4629 assert(VM_Version::supports_avx(), ""); 4630 InstructionMark im(this); 4631 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 4632 vex_prefix(dst, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 4633 emit_int8((unsigned char)0xAE); 4634 emit_operand(as_Register(3), dst); 4635 } else { 4636 NOT_LP64(assert(VM_Version::supports_sse(), "")); 4637 InstructionMark im(this); 4638 prefix(dst); 4639 emit_int8(0x0F); 4640 emit_int8((unsigned char)0xAE); 4641 emit_operand(as_Register(3), dst); 4642 } 4643 } 4644 4645 void Assembler::subl(Address dst, int32_t imm32) { 4646 InstructionMark im(this); 4647 prefix(dst); 4648 emit_arith_operand(0x81, rbp, dst, imm32); 4649 } 4650 4651 void Assembler::subl(Address dst, Register src) { 4652 InstructionMark im(this); 4653 prefix(dst, src); 4654 emit_int8(0x29); 4655 emit_operand(src, dst); 4656 } 4657 4658 void Assembler::subl(Register dst, int32_t imm32) { 4659 prefix(dst); 4660 emit_arith(0x81, 0xE8, dst, imm32); 4661 } 4662 4663 // Force generation of a 4 byte immediate value even if it fits into 8bit 4664 void Assembler::subl_imm32(Register dst, int32_t imm32) { 4665 prefix(dst); 4666 emit_arith_imm32(0x81, 0xE8, dst, imm32); 4667 } 4668 4669 void Assembler::subl(Register dst, Address src) { 4670 InstructionMark im(this); 4671 prefix(src, dst); 4672 emit_int8(0x2B); 4673 emit_operand(dst, src); 4674 } 4675 4676 void Assembler::subl(Register dst, Register src) { 4677 (void) prefix_and_encode(dst->encoding(), src->encoding()); 4678 emit_arith(0x2B, 0xC0, dst, src); 4679 } 4680 4681 void Assembler::subsd(XMMRegister dst, XMMRegister src) { 4682 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4683 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4684 attributes.set_rex_vex_w_reverted(); 4685 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 4686 emit_int8(0x5C); 4687 emit_int8((unsigned char)(0xC0 | encode)); 4688 } 4689 4690 void Assembler::subsd(XMMRegister dst, Address src) { 4691 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4692 InstructionMark im(this); 4693 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4694 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 4695 attributes.set_rex_vex_w_reverted(); 4696 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 4697 emit_int8(0x5C); 4698 emit_operand(dst, src); 4699 } 4700 4701 void Assembler::subss(XMMRegister dst, XMMRegister src) { 4702 NOT_LP64(assert(VM_Version::supports_sse(), "")); 4703 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true , /* uses_vl */ false); 4704 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 4705 emit_int8(0x5C); 4706 emit_int8((unsigned char)(0xC0 | encode)); 4707 } 4708 4709 void Assembler::subss(XMMRegister dst, Address src) { 4710 NOT_LP64(assert(VM_Version::supports_sse(), "")); 4711 InstructionMark im(this); 4712 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4713 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 4714 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 4715 emit_int8(0x5C); 4716 emit_operand(dst, src); 4717 } 4718 4719 void Assembler::testb(Register dst, int imm8) { 4720 NOT_LP64(assert(dst->has_byte_register(), "must have byte register")); 4721 (void) prefix_and_encode(dst->encoding(), true); 4722 emit_arith_b(0xF6, 0xC0, dst, imm8); 4723 } 4724 4725 void Assembler::testb(Address dst, int imm8) { 4726 InstructionMark im(this); 4727 prefix(dst); 4728 emit_int8((unsigned char)0xF6); 4729 emit_operand(rax, dst, 1); 4730 emit_int8(imm8); 4731 } 4732 4733 void Assembler::testl(Register dst, int32_t imm32) { 4734 // not using emit_arith because test 4735 // doesn't support sign-extension of 4736 // 8bit operands 4737 int encode = dst->encoding(); 4738 if (encode == 0) { 4739 emit_int8((unsigned char)0xA9); 4740 } else { 4741 encode = prefix_and_encode(encode); 4742 emit_int8((unsigned char)0xF7); 4743 emit_int8((unsigned char)(0xC0 | encode)); 4744 } 4745 emit_int32(imm32); 4746 } 4747 4748 void Assembler::testl(Register dst, Register src) { 4749 (void) prefix_and_encode(dst->encoding(), src->encoding()); 4750 emit_arith(0x85, 0xC0, dst, src); 4751 } 4752 4753 void Assembler::testl(Register dst, Address src) { 4754 InstructionMark im(this); 4755 prefix(src, dst); 4756 emit_int8((unsigned char)0x85); 4757 emit_operand(dst, src); 4758 } 4759 4760 void Assembler::tzcntl(Register dst, Register src) { 4761 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported"); 4762 emit_int8((unsigned char)0xF3); 4763 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 4764 emit_int8(0x0F); 4765 emit_int8((unsigned char)0xBC); 4766 emit_int8((unsigned char)0xC0 | encode); 4767 } 4768 4769 void Assembler::tzcntq(Register dst, Register src) { 4770 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported"); 4771 emit_int8((unsigned char)0xF3); 4772 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 4773 emit_int8(0x0F); 4774 emit_int8((unsigned char)0xBC); 4775 emit_int8((unsigned char)(0xC0 | encode)); 4776 } 4777 4778 void Assembler::ucomisd(XMMRegister dst, Address src) { 4779 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4780 InstructionMark im(this); 4781 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4782 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 4783 attributes.set_rex_vex_w_reverted(); 4784 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4785 emit_int8(0x2E); 4786 emit_operand(dst, src); 4787 } 4788 4789 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) { 4790 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4791 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4792 attributes.set_rex_vex_w_reverted(); 4793 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4794 emit_int8(0x2E); 4795 emit_int8((unsigned char)(0xC0 | encode)); 4796 } 4797 4798 void Assembler::ucomiss(XMMRegister dst, Address src) { 4799 NOT_LP64(assert(VM_Version::supports_sse(), "")); 4800 InstructionMark im(this); 4801 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4802 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 4803 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 4804 emit_int8(0x2E); 4805 emit_operand(dst, src); 4806 } 4807 4808 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) { 4809 NOT_LP64(assert(VM_Version::supports_sse(), "")); 4810 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4811 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 4812 emit_int8(0x2E); 4813 emit_int8((unsigned char)(0xC0 | encode)); 4814 } 4815 4816 void Assembler::xabort(int8_t imm8) { 4817 emit_int8((unsigned char)0xC6); 4818 emit_int8((unsigned char)0xF8); 4819 emit_int8((unsigned char)(imm8 & 0xFF)); 4820 } 4821 4822 void Assembler::xaddb(Address dst, Register src) { 4823 InstructionMark im(this); 4824 prefix(dst, src, true); 4825 emit_int8(0x0F); 4826 emit_int8((unsigned char)0xC0); 4827 emit_operand(src, dst); 4828 } 4829 4830 void Assembler::xaddw(Address dst, Register src) { 4831 InstructionMark im(this); 4832 emit_int8(0x66); 4833 prefix(dst, src); 4834 emit_int8(0x0F); 4835 emit_int8((unsigned char)0xC1); 4836 emit_operand(src, dst); 4837 } 4838 4839 void Assembler::xaddl(Address dst, Register src) { 4840 InstructionMark im(this); 4841 prefix(dst, src); 4842 emit_int8(0x0F); 4843 emit_int8((unsigned char)0xC1); 4844 emit_operand(src, dst); 4845 } 4846 4847 void Assembler::xbegin(Label& abort, relocInfo::relocType rtype) { 4848 InstructionMark im(this); 4849 relocate(rtype); 4850 if (abort.is_bound()) { 4851 address entry = target(abort); 4852 assert(entry != NULL, "abort entry NULL"); 4853 intptr_t offset = entry - pc(); 4854 emit_int8((unsigned char)0xC7); 4855 emit_int8((unsigned char)0xF8); 4856 emit_int32(offset - 6); // 2 opcode + 4 address 4857 } else { 4858 abort.add_patch_at(code(), locator()); 4859 emit_int8((unsigned char)0xC7); 4860 emit_int8((unsigned char)0xF8); 4861 emit_int32(0); 4862 } 4863 } 4864 4865 void Assembler::xchgb(Register dst, Address src) { // xchg 4866 InstructionMark im(this); 4867 prefix(src, dst, true); 4868 emit_int8((unsigned char)0x86); 4869 emit_operand(dst, src); 4870 } 4871 4872 void Assembler::xchgw(Register dst, Address src) { // xchg 4873 InstructionMark im(this); 4874 emit_int8(0x66); 4875 prefix(src, dst); 4876 emit_int8((unsigned char)0x87); 4877 emit_operand(dst, src); 4878 } 4879 4880 void Assembler::xchgl(Register dst, Address src) { // xchg 4881 InstructionMark im(this); 4882 prefix(src, dst); 4883 emit_int8((unsigned char)0x87); 4884 emit_operand(dst, src); 4885 } 4886 4887 void Assembler::xchgl(Register dst, Register src) { 4888 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 4889 emit_int8((unsigned char)0x87); 4890 emit_int8((unsigned char)(0xC0 | encode)); 4891 } 4892 4893 void Assembler::xend() { 4894 emit_int8((unsigned char)0x0F); 4895 emit_int8((unsigned char)0x01); 4896 emit_int8((unsigned char)0xD5); 4897 } 4898 4899 void Assembler::xgetbv() { 4900 emit_int8(0x0F); 4901 emit_int8(0x01); 4902 emit_int8((unsigned char)0xD0); 4903 } 4904 4905 void Assembler::xorl(Register dst, int32_t imm32) { 4906 prefix(dst); 4907 emit_arith(0x81, 0xF0, dst, imm32); 4908 } 4909 4910 void Assembler::xorl(Register dst, Address src) { 4911 InstructionMark im(this); 4912 prefix(src, dst); 4913 emit_int8(0x33); 4914 emit_operand(dst, src); 4915 } 4916 4917 void Assembler::xorl(Register dst, Register src) { 4918 (void) prefix_and_encode(dst->encoding(), src->encoding()); 4919 emit_arith(0x33, 0xC0, dst, src); 4920 } 4921 4922 void Assembler::xorb(Register dst, Address src) { 4923 InstructionMark im(this); 4924 prefix(src, dst); 4925 emit_int8(0x32); 4926 emit_operand(dst, src); 4927 } 4928 4929 // AVX 3-operands scalar float-point arithmetic instructions 4930 4931 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) { 4932 assert(VM_Version::supports_avx(), ""); 4933 InstructionMark im(this); 4934 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4935 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 4936 attributes.set_rex_vex_w_reverted(); 4937 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 4938 emit_int8(0x58); 4939 emit_operand(dst, src); 4940 } 4941 4942 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { 4943 assert(VM_Version::supports_avx(), ""); 4944 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4945 attributes.set_rex_vex_w_reverted(); 4946 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 4947 emit_int8(0x58); 4948 emit_int8((unsigned char)(0xC0 | encode)); 4949 } 4950 4951 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) { 4952 assert(VM_Version::supports_avx(), ""); 4953 InstructionMark im(this); 4954 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4955 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 4956 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 4957 emit_int8(0x58); 4958 emit_operand(dst, src); 4959 } 4960 4961 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { 4962 assert(VM_Version::supports_avx(), ""); 4963 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4964 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 4965 emit_int8(0x58); 4966 emit_int8((unsigned char)(0xC0 | encode)); 4967 } 4968 4969 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) { 4970 assert(VM_Version::supports_avx(), ""); 4971 InstructionMark im(this); 4972 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4973 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 4974 attributes.set_rex_vex_w_reverted(); 4975 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 4976 emit_int8(0x5E); 4977 emit_operand(dst, src); 4978 } 4979 4980 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { 4981 assert(VM_Version::supports_avx(), ""); 4982 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4983 attributes.set_rex_vex_w_reverted(); 4984 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 4985 emit_int8(0x5E); 4986 emit_int8((unsigned char)(0xC0 | encode)); 4987 } 4988 4989 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) { 4990 assert(VM_Version::supports_avx(), ""); 4991 InstructionMark im(this); 4992 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4993 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 4994 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 4995 emit_int8(0x5E); 4996 emit_operand(dst, src); 4997 } 4998 4999 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { 5000 assert(VM_Version::supports_avx(), ""); 5001 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 5002 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 5003 emit_int8(0x5E); 5004 emit_int8((unsigned char)(0xC0 | encode)); 5005 } 5006 5007 void Assembler::vfmadd231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) { 5008 assert(VM_Version::supports_fma(), ""); 5009 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 5010 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 5011 emit_int8((unsigned char)0xB9); 5012 emit_int8((unsigned char)(0xC0 | encode)); 5013 } 5014 5015 void Assembler::vfmadd231ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) { 5016 assert(VM_Version::supports_fma(), ""); 5017 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 5018 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 5019 emit_int8((unsigned char)0xB9); 5020 emit_int8((unsigned char)(0xC0 | encode)); 5021 } 5022 5023 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) { 5024 assert(VM_Version::supports_avx(), ""); 5025 InstructionMark im(this); 5026 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 5027 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 5028 attributes.set_rex_vex_w_reverted(); 5029 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 5030 emit_int8(0x59); 5031 emit_operand(dst, src); 5032 } 5033 5034 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { 5035 assert(VM_Version::supports_avx(), ""); 5036 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 5037 attributes.set_rex_vex_w_reverted(); 5038 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 5039 emit_int8(0x59); 5040 emit_int8((unsigned char)(0xC0 | encode)); 5041 } 5042 5043 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) { 5044 assert(VM_Version::supports_avx(), ""); 5045 InstructionMark im(this); 5046 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 5047 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 5048 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 5049 emit_int8(0x59); 5050 emit_operand(dst, src); 5051 } 5052 5053 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { 5054 assert(VM_Version::supports_avx(), ""); 5055 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 5056 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 5057 emit_int8(0x59); 5058 emit_int8((unsigned char)(0xC0 | encode)); 5059 } 5060 5061 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) { 5062 assert(VM_Version::supports_avx(), ""); 5063 InstructionMark im(this); 5064 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 5065 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 5066 attributes.set_rex_vex_w_reverted(); 5067 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 5068 emit_int8(0x5C); 5069 emit_operand(dst, src); 5070 } 5071 5072 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { 5073 assert(VM_Version::supports_avx(), ""); 5074 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 5075 attributes.set_rex_vex_w_reverted(); 5076 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 5077 emit_int8(0x5C); 5078 emit_int8((unsigned char)(0xC0 | encode)); 5079 } 5080 5081 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) { 5082 assert(VM_Version::supports_avx(), ""); 5083 InstructionMark im(this); 5084 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 5085 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 5086 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 5087 emit_int8(0x5C); 5088 emit_operand(dst, src); 5089 } 5090 5091 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { 5092 assert(VM_Version::supports_avx(), ""); 5093 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 5094 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 5095 emit_int8(0x5C); 5096 emit_int8((unsigned char)(0xC0 | encode)); 5097 } 5098 5099 //====================VECTOR ARITHMETIC===================================== 5100 5101 // Float-point vector arithmetic 5102 5103 void Assembler::addpd(XMMRegister dst, XMMRegister src) { 5104 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5105 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5106 attributes.set_rex_vex_w_reverted(); 5107 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5108 emit_int8(0x58); 5109 emit_int8((unsigned char)(0xC0 | encode)); 5110 } 5111 5112 void Assembler::addpd(XMMRegister dst, Address src) { 5113 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5114 InstructionMark im(this); 5115 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5116 attributes.set_rex_vex_w_reverted(); 5117 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5118 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5119 emit_int8(0x58); 5120 emit_operand(dst, src); 5121 } 5122 5123 5124 void Assembler::addps(XMMRegister dst, XMMRegister src) { 5125 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5126 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5127 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5128 emit_int8(0x58); 5129 emit_int8((unsigned char)(0xC0 | encode)); 5130 } 5131 5132 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5133 assert(VM_Version::supports_avx(), ""); 5134 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5135 attributes.set_rex_vex_w_reverted(); 5136 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5137 emit_int8(0x58); 5138 emit_int8((unsigned char)(0xC0 | encode)); 5139 } 5140 5141 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5142 assert(VM_Version::supports_avx(), ""); 5143 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5144 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5145 emit_int8(0x58); 5146 emit_int8((unsigned char)(0xC0 | encode)); 5147 } 5148 5149 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5150 assert(VM_Version::supports_avx(), ""); 5151 InstructionMark im(this); 5152 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5153 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5154 attributes.set_rex_vex_w_reverted(); 5155 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5156 emit_int8(0x58); 5157 emit_operand(dst, src); 5158 } 5159 5160 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5161 assert(VM_Version::supports_avx(), ""); 5162 InstructionMark im(this); 5163 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5164 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 5165 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5166 emit_int8(0x58); 5167 emit_operand(dst, src); 5168 } 5169 5170 void Assembler::subpd(XMMRegister dst, XMMRegister src) { 5171 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5172 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5173 attributes.set_rex_vex_w_reverted(); 5174 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5175 emit_int8(0x5C); 5176 emit_int8((unsigned char)(0xC0 | encode)); 5177 } 5178 5179 void Assembler::subps(XMMRegister dst, XMMRegister src) { 5180 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5181 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5182 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5183 emit_int8(0x5C); 5184 emit_int8((unsigned char)(0xC0 | encode)); 5185 } 5186 5187 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5188 assert(VM_Version::supports_avx(), ""); 5189 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5190 attributes.set_rex_vex_w_reverted(); 5191 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5192 emit_int8(0x5C); 5193 emit_int8((unsigned char)(0xC0 | encode)); 5194 } 5195 5196 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5197 assert(VM_Version::supports_avx(), ""); 5198 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5199 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5200 emit_int8(0x5C); 5201 emit_int8((unsigned char)(0xC0 | encode)); 5202 } 5203 5204 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5205 assert(VM_Version::supports_avx(), ""); 5206 InstructionMark im(this); 5207 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5208 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5209 attributes.set_rex_vex_w_reverted(); 5210 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5211 emit_int8(0x5C); 5212 emit_operand(dst, src); 5213 } 5214 5215 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5216 assert(VM_Version::supports_avx(), ""); 5217 InstructionMark im(this); 5218 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5219 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 5220 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5221 emit_int8(0x5C); 5222 emit_operand(dst, src); 5223 } 5224 5225 void Assembler::mulpd(XMMRegister dst, XMMRegister src) { 5226 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5227 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5228 attributes.set_rex_vex_w_reverted(); 5229 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5230 emit_int8(0x59); 5231 emit_int8((unsigned char)(0xC0 | encode)); 5232 } 5233 5234 void Assembler::mulpd(XMMRegister dst, Address src) { 5235 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5236 InstructionMark im(this); 5237 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5238 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5239 attributes.set_rex_vex_w_reverted(); 5240 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5241 emit_int8(0x59); 5242 emit_operand(dst, src); 5243 } 5244 5245 void Assembler::mulps(XMMRegister dst, XMMRegister src) { 5246 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5247 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5248 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5249 emit_int8(0x59); 5250 emit_int8((unsigned char)(0xC0 | encode)); 5251 } 5252 5253 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5254 assert(VM_Version::supports_avx(), ""); 5255 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5256 attributes.set_rex_vex_w_reverted(); 5257 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5258 emit_int8(0x59); 5259 emit_int8((unsigned char)(0xC0 | encode)); 5260 } 5261 5262 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5263 assert(VM_Version::supports_avx(), ""); 5264 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5265 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5266 emit_int8(0x59); 5267 emit_int8((unsigned char)(0xC0 | encode)); 5268 } 5269 5270 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5271 assert(VM_Version::supports_avx(), ""); 5272 InstructionMark im(this); 5273 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5274 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5275 attributes.set_rex_vex_w_reverted(); 5276 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5277 emit_int8(0x59); 5278 emit_operand(dst, src); 5279 } 5280 5281 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5282 assert(VM_Version::supports_avx(), ""); 5283 InstructionMark im(this); 5284 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5285 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 5286 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5287 emit_int8(0x59); 5288 emit_operand(dst, src); 5289 } 5290 5291 void Assembler::vfmadd231pd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len) { 5292 assert(VM_Version::supports_fma(), ""); 5293 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5294 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 5295 emit_int8((unsigned char)0xB8); 5296 emit_int8((unsigned char)(0xC0 | encode)); 5297 } 5298 5299 void Assembler::vfmadd231ps(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len) { 5300 assert(VM_Version::supports_fma(), ""); 5301 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5302 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 5303 emit_int8((unsigned char)0xB8); 5304 emit_int8((unsigned char)(0xC0 | encode)); 5305 } 5306 5307 void Assembler::vfmadd231pd(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) { 5308 assert(VM_Version::supports_fma(), ""); 5309 InstructionMark im(this); 5310 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5311 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5312 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 5313 emit_int8((unsigned char)0xB8); 5314 emit_operand(dst, src2); 5315 } 5316 5317 void Assembler::vfmadd231ps(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) { 5318 assert(VM_Version::supports_fma(), ""); 5319 InstructionMark im(this); 5320 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5321 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 5322 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 5323 emit_int8((unsigned char)0xB8); 5324 emit_operand(dst, src2); 5325 } 5326 5327 void Assembler::divpd(XMMRegister dst, XMMRegister src) { 5328 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5329 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5330 attributes.set_rex_vex_w_reverted(); 5331 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5332 emit_int8(0x5E); 5333 emit_int8((unsigned char)(0xC0 | encode)); 5334 } 5335 5336 void Assembler::divps(XMMRegister dst, XMMRegister src) { 5337 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5338 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5339 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5340 emit_int8(0x5E); 5341 emit_int8((unsigned char)(0xC0 | encode)); 5342 } 5343 5344 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5345 assert(VM_Version::supports_avx(), ""); 5346 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5347 attributes.set_rex_vex_w_reverted(); 5348 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5349 emit_int8(0x5E); 5350 emit_int8((unsigned char)(0xC0 | encode)); 5351 } 5352 5353 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5354 assert(VM_Version::supports_avx(), ""); 5355 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5356 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5357 emit_int8(0x5E); 5358 emit_int8((unsigned char)(0xC0 | encode)); 5359 } 5360 5361 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5362 assert(VM_Version::supports_avx(), ""); 5363 InstructionMark im(this); 5364 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5365 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5366 attributes.set_rex_vex_w_reverted(); 5367 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5368 emit_int8(0x5E); 5369 emit_operand(dst, src); 5370 } 5371 5372 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5373 assert(VM_Version::supports_avx(), ""); 5374 InstructionMark im(this); 5375 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5376 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 5377 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5378 emit_int8(0x5E); 5379 emit_operand(dst, src); 5380 } 5381 5382 void Assembler::vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len) { 5383 assert(VM_Version::supports_avx(), ""); 5384 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5385 attributes.set_rex_vex_w_reverted(); 5386 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5387 emit_int8(0x51); 5388 emit_int8((unsigned char)(0xC0 | encode)); 5389 } 5390 5391 void Assembler::vsqrtpd(XMMRegister dst, Address src, int vector_len) { 5392 assert(VM_Version::supports_avx(), ""); 5393 InstructionMark im(this); 5394 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5395 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5396 attributes.set_rex_vex_w_reverted(); 5397 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5398 emit_int8(0x51); 5399 emit_operand(dst, src); 5400 } 5401 5402 void Assembler::vsqrtps(XMMRegister dst, XMMRegister src, int vector_len) { 5403 assert(VM_Version::supports_avx(), ""); 5404 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5405 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5406 emit_int8(0x51); 5407 emit_int8((unsigned char)(0xC0 | encode)); 5408 } 5409 5410 void Assembler::vsqrtps(XMMRegister dst, Address src, int vector_len) { 5411 assert(VM_Version::supports_avx(), ""); 5412 InstructionMark im(this); 5413 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5414 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5415 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5416 emit_int8(0x51); 5417 emit_operand(dst, src); 5418 } 5419 5420 void Assembler::andpd(XMMRegister dst, XMMRegister src) { 5421 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5422 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5423 attributes.set_rex_vex_w_reverted(); 5424 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5425 emit_int8(0x54); 5426 emit_int8((unsigned char)(0xC0 | encode)); 5427 } 5428 5429 void Assembler::andps(XMMRegister dst, XMMRegister src) { 5430 NOT_LP64(assert(VM_Version::supports_sse(), "")); 5431 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5432 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5433 emit_int8(0x54); 5434 emit_int8((unsigned char)(0xC0 | encode)); 5435 } 5436 5437 void Assembler::andps(XMMRegister dst, Address src) { 5438 NOT_LP64(assert(VM_Version::supports_sse(), "")); 5439 InstructionMark im(this); 5440 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5441 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 5442 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5443 emit_int8(0x54); 5444 emit_operand(dst, src); 5445 } 5446 5447 void Assembler::andpd(XMMRegister dst, Address src) { 5448 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5449 InstructionMark im(this); 5450 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5451 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5452 attributes.set_rex_vex_w_reverted(); 5453 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5454 emit_int8(0x54); 5455 emit_operand(dst, src); 5456 } 5457 5458 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5459 assert(VM_Version::supports_avx(), ""); 5460 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5461 attributes.set_rex_vex_w_reverted(); 5462 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5463 emit_int8(0x54); 5464 emit_int8((unsigned char)(0xC0 | encode)); 5465 } 5466 5467 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5468 assert(VM_Version::supports_avx(), ""); 5469 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5470 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5471 emit_int8(0x54); 5472 emit_int8((unsigned char)(0xC0 | encode)); 5473 } 5474 5475 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5476 assert(VM_Version::supports_avx(), ""); 5477 InstructionMark im(this); 5478 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5479 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5480 attributes.set_rex_vex_w_reverted(); 5481 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5482 emit_int8(0x54); 5483 emit_operand(dst, src); 5484 } 5485 5486 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5487 assert(VM_Version::supports_avx(), ""); 5488 InstructionMark im(this); 5489 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5490 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 5491 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5492 emit_int8(0x54); 5493 emit_operand(dst, src); 5494 } 5495 5496 void Assembler::unpckhpd(XMMRegister dst, XMMRegister src) { 5497 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5498 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5499 attributes.set_rex_vex_w_reverted(); 5500 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5501 emit_int8(0x15); 5502 emit_int8((unsigned char)(0xC0 | encode)); 5503 } 5504 5505 void Assembler::unpcklpd(XMMRegister dst, XMMRegister src) { 5506 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5507 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5508 attributes.set_rex_vex_w_reverted(); 5509 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5510 emit_int8(0x14); 5511 emit_int8((unsigned char)(0xC0 | encode)); 5512 } 5513 5514 void Assembler::xorpd(XMMRegister dst, XMMRegister src) { 5515 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5516 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5517 attributes.set_rex_vex_w_reverted(); 5518 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5519 emit_int8(0x57); 5520 emit_int8((unsigned char)(0xC0 | encode)); 5521 } 5522 5523 void Assembler::xorps(XMMRegister dst, XMMRegister src) { 5524 NOT_LP64(assert(VM_Version::supports_sse(), "")); 5525 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5526 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5527 emit_int8(0x57); 5528 emit_int8((unsigned char)(0xC0 | encode)); 5529 } 5530 5531 void Assembler::xorpd(XMMRegister dst, Address src) { 5532 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5533 InstructionMark im(this); 5534 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5535 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5536 attributes.set_rex_vex_w_reverted(); 5537 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5538 emit_int8(0x57); 5539 emit_operand(dst, src); 5540 } 5541 5542 void Assembler::xorps(XMMRegister dst, Address src) { 5543 NOT_LP64(assert(VM_Version::supports_sse(), "")); 5544 InstructionMark im(this); 5545 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5546 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 5547 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5548 emit_int8(0x57); 5549 emit_operand(dst, src); 5550 } 5551 5552 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5553 assert(VM_Version::supports_avx(), ""); 5554 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5555 attributes.set_rex_vex_w_reverted(); 5556 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5557 emit_int8(0x57); 5558 emit_int8((unsigned char)(0xC0 | encode)); 5559 } 5560 5561 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5562 assert(VM_Version::supports_avx(), ""); 5563 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5564 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5565 emit_int8(0x57); 5566 emit_int8((unsigned char)(0xC0 | encode)); 5567 } 5568 5569 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5570 assert(VM_Version::supports_avx(), ""); 5571 InstructionMark im(this); 5572 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5573 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5574 attributes.set_rex_vex_w_reverted(); 5575 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5576 emit_int8(0x57); 5577 emit_operand(dst, src); 5578 } 5579 5580 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5581 assert(VM_Version::supports_avx(), ""); 5582 InstructionMark im(this); 5583 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5584 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 5585 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5586 emit_int8(0x57); 5587 emit_operand(dst, src); 5588 } 5589 5590 // Integer vector arithmetic 5591 void Assembler::vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5592 assert(VM_Version::supports_avx() && (vector_len == 0) || 5593 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); 5594 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true); 5595 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 5596 emit_int8(0x01); 5597 emit_int8((unsigned char)(0xC0 | encode)); 5598 } 5599 5600 void Assembler::vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5601 assert(VM_Version::supports_avx() && (vector_len == 0) || 5602 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); 5603 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ true); 5604 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 5605 emit_int8(0x02); 5606 emit_int8((unsigned char)(0xC0 | encode)); 5607 } 5608 5609 void Assembler::paddb(XMMRegister dst, XMMRegister src) { 5610 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5611 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5612 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5613 emit_int8((unsigned char)0xFC); 5614 emit_int8((unsigned char)(0xC0 | encode)); 5615 } 5616 5617 void Assembler::paddw(XMMRegister dst, XMMRegister src) { 5618 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5619 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5620 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5621 emit_int8((unsigned char)0xFD); 5622 emit_int8((unsigned char)(0xC0 | encode)); 5623 } 5624 5625 void Assembler::paddd(XMMRegister dst, XMMRegister src) { 5626 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5627 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5628 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5629 emit_int8((unsigned char)0xFE); 5630 emit_int8((unsigned char)(0xC0 | encode)); 5631 } 5632 5633 void Assembler::paddd(XMMRegister dst, Address src) { 5634 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5635 InstructionMark im(this); 5636 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5637 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5638 emit_int8((unsigned char)0xFE); 5639 emit_operand(dst, src); 5640 } 5641 5642 void Assembler::paddq(XMMRegister dst, XMMRegister src) { 5643 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5644 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5645 attributes.set_rex_vex_w_reverted(); 5646 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5647 emit_int8((unsigned char)0xD4); 5648 emit_int8((unsigned char)(0xC0 | encode)); 5649 } 5650 5651 void Assembler::phaddw(XMMRegister dst, XMMRegister src) { 5652 assert(VM_Version::supports_sse3(), ""); 5653 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true); 5654 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 5655 emit_int8(0x01); 5656 emit_int8((unsigned char)(0xC0 | encode)); 5657 } 5658 5659 void Assembler::phaddd(XMMRegister dst, XMMRegister src) { 5660 assert(VM_Version::supports_sse3(), ""); 5661 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ true); 5662 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 5663 emit_int8(0x02); 5664 emit_int8((unsigned char)(0xC0 | encode)); 5665 } 5666 5667 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5668 assert(UseAVX > 0, "requires some form of AVX"); 5669 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5670 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5671 emit_int8((unsigned char)0xFC); 5672 emit_int8((unsigned char)(0xC0 | encode)); 5673 } 5674 5675 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5676 assert(UseAVX > 0, "requires some form of AVX"); 5677 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5678 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5679 emit_int8((unsigned char)0xFD); 5680 emit_int8((unsigned char)(0xC0 | encode)); 5681 } 5682 5683 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5684 assert(UseAVX > 0, "requires some form of AVX"); 5685 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5686 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5687 emit_int8((unsigned char)0xFE); 5688 emit_int8((unsigned char)(0xC0 | encode)); 5689 } 5690 5691 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5692 assert(UseAVX > 0, "requires some form of AVX"); 5693 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5694 attributes.set_rex_vex_w_reverted(); 5695 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5696 emit_int8((unsigned char)0xD4); 5697 emit_int8((unsigned char)(0xC0 | encode)); 5698 } 5699 5700 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5701 assert(UseAVX > 0, "requires some form of AVX"); 5702 InstructionMark im(this); 5703 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5704 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 5705 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5706 emit_int8((unsigned char)0xFC); 5707 emit_operand(dst, src); 5708 } 5709 5710 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5711 assert(UseAVX > 0, "requires some form of AVX"); 5712 InstructionMark im(this); 5713 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5714 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 5715 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5716 emit_int8((unsigned char)0xFD); 5717 emit_operand(dst, src); 5718 } 5719 5720 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5721 assert(UseAVX > 0, "requires some form of AVX"); 5722 InstructionMark im(this); 5723 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5724 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 5725 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5726 emit_int8((unsigned char)0xFE); 5727 emit_operand(dst, src); 5728 } 5729 5730 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5731 assert(UseAVX > 0, "requires some form of AVX"); 5732 InstructionMark im(this); 5733 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5734 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5735 attributes.set_rex_vex_w_reverted(); 5736 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5737 emit_int8((unsigned char)0xD4); 5738 emit_operand(dst, src); 5739 } 5740 5741 void Assembler::psubb(XMMRegister dst, XMMRegister src) { 5742 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5743 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5744 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5745 emit_int8((unsigned char)0xF8); 5746 emit_int8((unsigned char)(0xC0 | encode)); 5747 } 5748 5749 void Assembler::psubw(XMMRegister dst, XMMRegister src) { 5750 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5751 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5752 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5753 emit_int8((unsigned char)0xF9); 5754 emit_int8((unsigned char)(0xC0 | encode)); 5755 } 5756 5757 void Assembler::psubd(XMMRegister dst, XMMRegister src) { 5758 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5759 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5760 emit_int8((unsigned char)0xFA); 5761 emit_int8((unsigned char)(0xC0 | encode)); 5762 } 5763 5764 void Assembler::psubq(XMMRegister dst, XMMRegister src) { 5765 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5766 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5767 attributes.set_rex_vex_w_reverted(); 5768 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5769 emit_int8((unsigned char)0xFB); 5770 emit_int8((unsigned char)(0xC0 | encode)); 5771 } 5772 5773 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5774 assert(UseAVX > 0, "requires some form of AVX"); 5775 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5776 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5777 emit_int8((unsigned char)0xF8); 5778 emit_int8((unsigned char)(0xC0 | encode)); 5779 } 5780 5781 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5782 assert(UseAVX > 0, "requires some form of AVX"); 5783 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5784 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5785 emit_int8((unsigned char)0xF9); 5786 emit_int8((unsigned char)(0xC0 | encode)); 5787 } 5788 5789 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5790 assert(UseAVX > 0, "requires some form of AVX"); 5791 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5792 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5793 emit_int8((unsigned char)0xFA); 5794 emit_int8((unsigned char)(0xC0 | encode)); 5795 } 5796 5797 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5798 assert(UseAVX > 0, "requires some form of AVX"); 5799 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5800 attributes.set_rex_vex_w_reverted(); 5801 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5802 emit_int8((unsigned char)0xFB); 5803 emit_int8((unsigned char)(0xC0 | encode)); 5804 } 5805 5806 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5807 assert(UseAVX > 0, "requires some form of AVX"); 5808 InstructionMark im(this); 5809 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5810 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 5811 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5812 emit_int8((unsigned char)0xF8); 5813 emit_operand(dst, src); 5814 } 5815 5816 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5817 assert(UseAVX > 0, "requires some form of AVX"); 5818 InstructionMark im(this); 5819 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5820 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 5821 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5822 emit_int8((unsigned char)0xF9); 5823 emit_operand(dst, src); 5824 } 5825 5826 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5827 assert(UseAVX > 0, "requires some form of AVX"); 5828 InstructionMark im(this); 5829 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5830 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 5831 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5832 emit_int8((unsigned char)0xFA); 5833 emit_operand(dst, src); 5834 } 5835 5836 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5837 assert(UseAVX > 0, "requires some form of AVX"); 5838 InstructionMark im(this); 5839 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5840 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5841 attributes.set_rex_vex_w_reverted(); 5842 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5843 emit_int8((unsigned char)0xFB); 5844 emit_operand(dst, src); 5845 } 5846 5847 void Assembler::pmullw(XMMRegister dst, XMMRegister src) { 5848 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5849 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5850 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5851 emit_int8((unsigned char)0xD5); 5852 emit_int8((unsigned char)(0xC0 | encode)); 5853 } 5854 5855 void Assembler::pmulld(XMMRegister dst, XMMRegister src) { 5856 assert(VM_Version::supports_sse4_1(), ""); 5857 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5858 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 5859 emit_int8(0x40); 5860 emit_int8((unsigned char)(0xC0 | encode)); 5861 } 5862 5863 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5864 assert(UseAVX > 0, "requires some form of AVX"); 5865 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5866 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5867 emit_int8((unsigned char)0xD5); 5868 emit_int8((unsigned char)(0xC0 | encode)); 5869 } 5870 5871 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5872 assert(UseAVX > 0, "requires some form of AVX"); 5873 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5874 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 5875 emit_int8(0x40); 5876 emit_int8((unsigned char)(0xC0 | encode)); 5877 } 5878 5879 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5880 assert(UseAVX > 2, "requires some form of EVEX"); 5881 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5882 attributes.set_is_evex_instruction(); 5883 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 5884 emit_int8(0x40); 5885 emit_int8((unsigned char)(0xC0 | encode)); 5886 } 5887 5888 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5889 assert(UseAVX > 0, "requires some form of AVX"); 5890 InstructionMark im(this); 5891 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5892 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 5893 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5894 emit_int8((unsigned char)0xD5); 5895 emit_operand(dst, src); 5896 } 5897 5898 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5899 assert(UseAVX > 0, "requires some form of AVX"); 5900 InstructionMark im(this); 5901 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5902 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 5903 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 5904 emit_int8(0x40); 5905 emit_operand(dst, src); 5906 } 5907 5908 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5909 assert(UseAVX > 2, "requires some form of EVEX"); 5910 InstructionMark im(this); 5911 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5912 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5913 attributes.set_is_evex_instruction(); 5914 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 5915 emit_int8(0x40); 5916 emit_operand(dst, src); 5917 } 5918 5919 // Shift packed integers left by specified number of bits. 5920 void Assembler::psllw(XMMRegister dst, int shift) { 5921 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5922 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5923 // XMM6 is for /6 encoding: 66 0F 71 /6 ib 5924 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5925 emit_int8(0x71); 5926 emit_int8((unsigned char)(0xC0 | encode)); 5927 emit_int8(shift & 0xFF); 5928 } 5929 5930 void Assembler::pslld(XMMRegister dst, int shift) { 5931 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5932 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5933 // XMM6 is for /6 encoding: 66 0F 72 /6 ib 5934 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5935 emit_int8(0x72); 5936 emit_int8((unsigned char)(0xC0 | encode)); 5937 emit_int8(shift & 0xFF); 5938 } 5939 5940 void Assembler::psllq(XMMRegister dst, int shift) { 5941 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5942 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5943 // XMM6 is for /6 encoding: 66 0F 73 /6 ib 5944 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5945 emit_int8(0x73); 5946 emit_int8((unsigned char)(0xC0 | encode)); 5947 emit_int8(shift & 0xFF); 5948 } 5949 5950 void Assembler::psllw(XMMRegister dst, XMMRegister shift) { 5951 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5952 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5953 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5954 emit_int8((unsigned char)0xF1); 5955 emit_int8((unsigned char)(0xC0 | encode)); 5956 } 5957 5958 void Assembler::pslld(XMMRegister dst, XMMRegister shift) { 5959 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5960 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5961 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5962 emit_int8((unsigned char)0xF2); 5963 emit_int8((unsigned char)(0xC0 | encode)); 5964 } 5965 5966 void Assembler::psllq(XMMRegister dst, XMMRegister shift) { 5967 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5968 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5969 attributes.set_rex_vex_w_reverted(); 5970 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5971 emit_int8((unsigned char)0xF3); 5972 emit_int8((unsigned char)(0xC0 | encode)); 5973 } 5974 5975 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len) { 5976 assert(UseAVX > 0, "requires some form of AVX"); 5977 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5978 // XMM6 is for /6 encoding: 66 0F 71 /6 ib 5979 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5980 emit_int8(0x71); 5981 emit_int8((unsigned char)(0xC0 | encode)); 5982 emit_int8(shift & 0xFF); 5983 } 5984 5985 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len) { 5986 assert(UseAVX > 0, "requires some form of AVX"); 5987 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5988 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5989 // XMM6 is for /6 encoding: 66 0F 72 /6 ib 5990 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5991 emit_int8(0x72); 5992 emit_int8((unsigned char)(0xC0 | encode)); 5993 emit_int8(shift & 0xFF); 5994 } 5995 5996 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len) { 5997 assert(UseAVX > 0, "requires some form of AVX"); 5998 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5999 attributes.set_rex_vex_w_reverted(); 6000 // XMM6 is for /6 encoding: 66 0F 73 /6 ib 6001 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6002 emit_int8(0x73); 6003 emit_int8((unsigned char)(0xC0 | encode)); 6004 emit_int8(shift & 0xFF); 6005 } 6006 6007 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { 6008 assert(UseAVX > 0, "requires some form of AVX"); 6009 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 6010 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6011 emit_int8((unsigned char)0xF1); 6012 emit_int8((unsigned char)(0xC0 | encode)); 6013 } 6014 6015 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { 6016 assert(UseAVX > 0, "requires some form of AVX"); 6017 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6018 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6019 emit_int8((unsigned char)0xF2); 6020 emit_int8((unsigned char)(0xC0 | encode)); 6021 } 6022 6023 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { 6024 assert(UseAVX > 0, "requires some form of AVX"); 6025 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6026 attributes.set_rex_vex_w_reverted(); 6027 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6028 emit_int8((unsigned char)0xF3); 6029 emit_int8((unsigned char)(0xC0 | encode)); 6030 } 6031 6032 // Shift packed integers logically right by specified number of bits. 6033 void Assembler::psrlw(XMMRegister dst, int shift) { 6034 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 6035 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 6036 // XMM2 is for /2 encoding: 66 0F 71 /2 ib 6037 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6038 emit_int8(0x71); 6039 emit_int8((unsigned char)(0xC0 | encode)); 6040 emit_int8(shift & 0xFF); 6041 } 6042 6043 void Assembler::psrld(XMMRegister dst, int shift) { 6044 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 6045 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6046 // XMM2 is for /2 encoding: 66 0F 72 /2 ib 6047 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6048 emit_int8(0x72); 6049 emit_int8((unsigned char)(0xC0 | encode)); 6050 emit_int8(shift & 0xFF); 6051 } 6052 6053 void Assembler::psrlq(XMMRegister dst, int shift) { 6054 // Do not confuse it with psrldq SSE2 instruction which 6055 // shifts 128 bit value in xmm register by number of bytes. 6056 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 6057 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6058 attributes.set_rex_vex_w_reverted(); 6059 // XMM2 is for /2 encoding: 66 0F 73 /2 ib 6060 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6061 emit_int8(0x73); 6062 emit_int8((unsigned char)(0xC0 | encode)); 6063 emit_int8(shift & 0xFF); 6064 } 6065 6066 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) { 6067 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 6068 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 6069 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6070 emit_int8((unsigned char)0xD1); 6071 emit_int8((unsigned char)(0xC0 | encode)); 6072 } 6073 6074 void Assembler::psrld(XMMRegister dst, XMMRegister shift) { 6075 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 6076 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6077 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6078 emit_int8((unsigned char)0xD2); 6079 emit_int8((unsigned char)(0xC0 | encode)); 6080 } 6081 6082 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) { 6083 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 6084 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6085 attributes.set_rex_vex_w_reverted(); 6086 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6087 emit_int8((unsigned char)0xD3); 6088 emit_int8((unsigned char)(0xC0 | encode)); 6089 } 6090 6091 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len) { 6092 assert(UseAVX > 0, "requires some form of AVX"); 6093 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 6094 // XMM2 is for /2 encoding: 66 0F 71 /2 ib 6095 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6096 emit_int8(0x71); 6097 emit_int8((unsigned char)(0xC0 | encode)); 6098 emit_int8(shift & 0xFF); 6099 } 6100 6101 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len) { 6102 assert(UseAVX > 0, "requires some form of AVX"); 6103 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6104 // XMM2 is for /2 encoding: 66 0F 72 /2 ib 6105 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6106 emit_int8(0x72); 6107 emit_int8((unsigned char)(0xC0 | encode)); 6108 emit_int8(shift & 0xFF); 6109 } 6110 6111 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len) { 6112 assert(UseAVX > 0, "requires some form of AVX"); 6113 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6114 attributes.set_rex_vex_w_reverted(); 6115 // XMM2 is for /2 encoding: 66 0F 73 /2 ib 6116 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6117 emit_int8(0x73); 6118 emit_int8((unsigned char)(0xC0 | encode)); 6119 emit_int8(shift & 0xFF); 6120 } 6121 6122 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { 6123 assert(UseAVX > 0, "requires some form of AVX"); 6124 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 6125 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6126 emit_int8((unsigned char)0xD1); 6127 emit_int8((unsigned char)(0xC0 | encode)); 6128 } 6129 6130 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { 6131 assert(UseAVX > 0, "requires some form of AVX"); 6132 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6133 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6134 emit_int8((unsigned char)0xD2); 6135 emit_int8((unsigned char)(0xC0 | encode)); 6136 } 6137 6138 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { 6139 assert(UseAVX > 0, "requires some form of AVX"); 6140 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6141 attributes.set_rex_vex_w_reverted(); 6142 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6143 emit_int8((unsigned char)0xD3); 6144 emit_int8((unsigned char)(0xC0 | encode)); 6145 } 6146 6147 void Assembler::evpsrlvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 6148 assert(VM_Version::supports_avx512bw(), ""); 6149 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6150 attributes.set_is_evex_instruction(); 6151 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6152 emit_int8(0x10); 6153 emit_int8((unsigned char)(0xC0 | encode)); 6154 } 6155 6156 void Assembler::evpsllvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 6157 assert(VM_Version::supports_avx512bw(), ""); 6158 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6159 attributes.set_is_evex_instruction(); 6160 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6161 emit_int8(0x12); 6162 emit_int8((unsigned char)(0xC0 | encode)); 6163 } 6164 6165 // Shift packed integers arithmetically right by specified number of bits. 6166 void Assembler::psraw(XMMRegister dst, int shift) { 6167 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 6168 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 6169 // XMM4 is for /4 encoding: 66 0F 71 /4 ib 6170 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6171 emit_int8(0x71); 6172 emit_int8((unsigned char)(0xC0 | encode)); 6173 emit_int8(shift & 0xFF); 6174 } 6175 6176 void Assembler::psrad(XMMRegister dst, int shift) { 6177 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 6178 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6179 // XMM4 is for /4 encoding: 66 0F 72 /4 ib 6180 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6181 emit_int8(0x72); 6182 emit_int8((unsigned char)(0xC0 | encode)); 6183 emit_int8(shift & 0xFF); 6184 } 6185 6186 void Assembler::psraw(XMMRegister dst, XMMRegister shift) { 6187 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 6188 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 6189 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6190 emit_int8((unsigned char)0xE1); 6191 emit_int8((unsigned char)(0xC0 | encode)); 6192 } 6193 6194 void Assembler::psrad(XMMRegister dst, XMMRegister shift) { 6195 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 6196 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6197 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6198 emit_int8((unsigned char)0xE2); 6199 emit_int8((unsigned char)(0xC0 | encode)); 6200 } 6201 6202 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len) { 6203 assert(UseAVX > 0, "requires some form of AVX"); 6204 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 6205 // XMM4 is for /4 encoding: 66 0F 71 /4 ib 6206 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6207 emit_int8(0x71); 6208 emit_int8((unsigned char)(0xC0 | encode)); 6209 emit_int8(shift & 0xFF); 6210 } 6211 6212 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len) { 6213 assert(UseAVX > 0, "requires some form of AVX"); 6214 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6215 // XMM4 is for /4 encoding: 66 0F 71 /4 ib 6216 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6217 emit_int8(0x72); 6218 emit_int8((unsigned char)(0xC0 | encode)); 6219 emit_int8(shift & 0xFF); 6220 } 6221 6222 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { 6223 assert(UseAVX > 0, "requires some form of AVX"); 6224 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 6225 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6226 emit_int8((unsigned char)0xE1); 6227 emit_int8((unsigned char)(0xC0 | encode)); 6228 } 6229 6230 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { 6231 assert(UseAVX > 0, "requires some form of AVX"); 6232 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6233 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6234 emit_int8((unsigned char)0xE2); 6235 emit_int8((unsigned char)(0xC0 | encode)); 6236 } 6237 6238 6239 // logical operations packed integers 6240 void Assembler::pand(XMMRegister dst, XMMRegister src) { 6241 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 6242 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6243 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6244 emit_int8((unsigned char)0xDB); 6245 emit_int8((unsigned char)(0xC0 | encode)); 6246 } 6247 6248 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 6249 assert(UseAVX > 0, "requires some form of AVX"); 6250 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6251 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6252 emit_int8((unsigned char)0xDB); 6253 emit_int8((unsigned char)(0xC0 | encode)); 6254 } 6255 6256 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 6257 assert(UseAVX > 0, "requires some form of AVX"); 6258 InstructionMark im(this); 6259 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6260 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 6261 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6262 emit_int8((unsigned char)0xDB); 6263 emit_operand(dst, src); 6264 } 6265 6266 void Assembler::vpandq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 6267 assert(VM_Version::supports_evex(), ""); 6268 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6269 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6270 emit_int8((unsigned char)0xDB); 6271 emit_int8((unsigned char)(0xC0 | encode)); 6272 } 6273 6274 6275 void Assembler::pandn(XMMRegister dst, XMMRegister src) { 6276 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 6277 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6278 attributes.set_rex_vex_w_reverted(); 6279 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6280 emit_int8((unsigned char)0xDF); 6281 emit_int8((unsigned char)(0xC0 | encode)); 6282 } 6283 6284 void Assembler::por(XMMRegister dst, XMMRegister src) { 6285 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 6286 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6287 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6288 emit_int8((unsigned char)0xEB); 6289 emit_int8((unsigned char)(0xC0 | encode)); 6290 } 6291 6292 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 6293 assert(UseAVX > 0, "requires some form of AVX"); 6294 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6295 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6296 emit_int8((unsigned char)0xEB); 6297 emit_int8((unsigned char)(0xC0 | encode)); 6298 } 6299 6300 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 6301 assert(UseAVX > 0, "requires some form of AVX"); 6302 InstructionMark im(this); 6303 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6304 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 6305 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6306 emit_int8((unsigned char)0xEB); 6307 emit_operand(dst, src); 6308 } 6309 6310 void Assembler::vporq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 6311 assert(VM_Version::supports_evex(), ""); 6312 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6313 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6314 emit_int8((unsigned char)0xEB); 6315 emit_int8((unsigned char)(0xC0 | encode)); 6316 } 6317 6318 6319 void Assembler::pxor(XMMRegister dst, XMMRegister src) { 6320 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 6321 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6322 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6323 emit_int8((unsigned char)0xEF); 6324 emit_int8((unsigned char)(0xC0 | encode)); 6325 } 6326 6327 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 6328 assert(UseAVX > 0, "requires some form of AVX"); 6329 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6330 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6331 emit_int8((unsigned char)0xEF); 6332 emit_int8((unsigned char)(0xC0 | encode)); 6333 } 6334 6335 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 6336 assert(UseAVX > 0, "requires some form of AVX"); 6337 InstructionMark im(this); 6338 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6339 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 6340 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6341 emit_int8((unsigned char)0xEF); 6342 emit_operand(dst, src); 6343 } 6344 6345 void Assembler::evpxorq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 6346 assert(VM_Version::supports_evex(), "requires EVEX support"); 6347 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6348 attributes.set_is_evex_instruction(); 6349 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6350 emit_int8((unsigned char)0xEF); 6351 emit_int8((unsigned char)(0xC0 | encode)); 6352 } 6353 6354 void Assembler::evpxorq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 6355 assert(VM_Version::supports_evex(), "requires EVEX support"); 6356 assert(dst != xnoreg, "sanity"); 6357 InstructionMark im(this); 6358 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6359 attributes.set_is_evex_instruction(); 6360 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 6361 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6362 emit_int8((unsigned char)0xEF); 6363 emit_operand(dst, src); 6364 } 6365 6366 6367 // vinserti forms 6368 6369 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) { 6370 assert(VM_Version::supports_avx2(), ""); 6371 assert(imm8 <= 0x01, "imm8: %u", imm8); 6372 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6373 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6374 emit_int8(0x38); 6375 emit_int8((unsigned char)(0xC0 | encode)); 6376 // 0x00 - insert into lower 128 bits 6377 // 0x01 - insert into upper 128 bits 6378 emit_int8(imm8 & 0x01); 6379 } 6380 6381 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) { 6382 assert(VM_Version::supports_avx2(), ""); 6383 assert(dst != xnoreg, "sanity"); 6384 assert(imm8 <= 0x01, "imm8: %u", imm8); 6385 InstructionMark im(this); 6386 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6387 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit); 6388 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6389 emit_int8(0x38); 6390 emit_operand(dst, src); 6391 // 0x00 - insert into lower 128 bits 6392 // 0x01 - insert into upper 128 bits 6393 emit_int8(imm8 & 0x01); 6394 } 6395 6396 void Assembler::vinserti32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) { 6397 assert(VM_Version::supports_evex(), ""); 6398 assert(imm8 <= 0x03, "imm8: %u", imm8); 6399 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6400 attributes.set_is_evex_instruction(); 6401 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6402 emit_int8(0x38); 6403 emit_int8((unsigned char)(0xC0 | encode)); 6404 // 0x00 - insert into q0 128 bits (0..127) 6405 // 0x01 - insert into q1 128 bits (128..255) 6406 // 0x02 - insert into q2 128 bits (256..383) 6407 // 0x03 - insert into q3 128 bits (384..511) 6408 emit_int8(imm8 & 0x03); 6409 } 6410 6411 void Assembler::vinserti32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) { 6412 assert(VM_Version::supports_avx(), ""); 6413 assert(dst != xnoreg, "sanity"); 6414 assert(imm8 <= 0x03, "imm8: %u", imm8); 6415 InstructionMark im(this); 6416 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6417 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit); 6418 attributes.set_is_evex_instruction(); 6419 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6420 emit_int8(0x18); 6421 emit_operand(dst, src); 6422 // 0x00 - insert into q0 128 bits (0..127) 6423 // 0x01 - insert into q1 128 bits (128..255) 6424 // 0x02 - insert into q2 128 bits (256..383) 6425 // 0x03 - insert into q3 128 bits (384..511) 6426 emit_int8(imm8 & 0x03); 6427 } 6428 6429 void Assembler::vinserti64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) { 6430 assert(VM_Version::supports_evex(), ""); 6431 assert(imm8 <= 0x01, "imm8: %u", imm8); 6432 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6433 attributes.set_is_evex_instruction(); 6434 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6435 emit_int8(0x3A); 6436 emit_int8((unsigned char)(0xC0 | encode)); 6437 // 0x00 - insert into lower 256 bits 6438 // 0x01 - insert into upper 256 bits 6439 emit_int8(imm8 & 0x01); 6440 } 6441 6442 6443 // vinsertf forms 6444 6445 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) { 6446 assert(VM_Version::supports_avx(), ""); 6447 assert(imm8 <= 0x01, "imm8: %u", imm8); 6448 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6449 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6450 emit_int8(0x18); 6451 emit_int8((unsigned char)(0xC0 | encode)); 6452 // 0x00 - insert into lower 128 bits 6453 // 0x01 - insert into upper 128 bits 6454 emit_int8(imm8 & 0x01); 6455 } 6456 6457 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) { 6458 assert(VM_Version::supports_avx(), ""); 6459 assert(dst != xnoreg, "sanity"); 6460 assert(imm8 <= 0x01, "imm8: %u", imm8); 6461 InstructionMark im(this); 6462 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6463 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit); 6464 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6465 emit_int8(0x18); 6466 emit_operand(dst, src); 6467 // 0x00 - insert into lower 128 bits 6468 // 0x01 - insert into upper 128 bits 6469 emit_int8(imm8 & 0x01); 6470 } 6471 6472 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) { 6473 assert(VM_Version::supports_avx2(), ""); 6474 assert(imm8 <= 0x03, "imm8: %u", imm8); 6475 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6476 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6477 emit_int8(0x18); 6478 emit_int8((unsigned char)(0xC0 | encode)); 6479 // 0x00 - insert into q0 128 bits (0..127) 6480 // 0x01 - insert into q1 128 bits (128..255) 6481 // 0x02 - insert into q0 128 bits (256..383) 6482 // 0x03 - insert into q1 128 bits (384..512) 6483 emit_int8(imm8 & 0x03); 6484 } 6485 6486 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) { 6487 assert(VM_Version::supports_avx(), ""); 6488 assert(dst != xnoreg, "sanity"); 6489 assert(imm8 <= 0x03, "imm8: %u", imm8); 6490 InstructionMark im(this); 6491 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6492 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit); 6493 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6494 emit_int8(0x18); 6495 emit_operand(dst, src); 6496 // 0x00 - insert into q0 128 bits (0..127) 6497 // 0x01 - insert into q1 128 bits (128..255) 6498 // 0x02 - insert into q0 128 bits (256..383) 6499 // 0x03 - insert into q1 128 bits (384..512) 6500 emit_int8(imm8 & 0x03); 6501 } 6502 6503 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) { 6504 assert(VM_Version::supports_evex(), ""); 6505 assert(imm8 <= 0x01, "imm8: %u", imm8); 6506 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6507 attributes.set_is_evex_instruction(); 6508 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6509 emit_int8(0x1A); 6510 emit_int8((unsigned char)(0xC0 | encode)); 6511 // 0x00 - insert into lower 256 bits 6512 // 0x01 - insert into upper 256 bits 6513 emit_int8(imm8 & 0x01); 6514 } 6515 6516 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) { 6517 assert(VM_Version::supports_evex(), ""); 6518 assert(dst != xnoreg, "sanity"); 6519 assert(imm8 <= 0x01, "imm8: %u", imm8); 6520 InstructionMark im(this); 6521 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6522 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_64bit); 6523 attributes.set_is_evex_instruction(); 6524 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6525 emit_int8(0x1A); 6526 emit_operand(dst, src); 6527 // 0x00 - insert into lower 256 bits 6528 // 0x01 - insert into upper 256 bits 6529 emit_int8(imm8 & 0x01); 6530 } 6531 6532 6533 // vextracti forms 6534 6535 void Assembler::vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) { 6536 assert(VM_Version::supports_avx2(), ""); 6537 assert(imm8 <= 0x01, "imm8: %u", imm8); 6538 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6539 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6540 emit_int8(0x39); 6541 emit_int8((unsigned char)(0xC0 | encode)); 6542 // 0x00 - extract from lower 128 bits 6543 // 0x01 - extract from upper 128 bits 6544 emit_int8(imm8 & 0x01); 6545 } 6546 6547 void Assembler::vextracti128(Address dst, XMMRegister src, uint8_t imm8) { 6548 assert(VM_Version::supports_avx2(), ""); 6549 assert(src != xnoreg, "sanity"); 6550 assert(imm8 <= 0x01, "imm8: %u", imm8); 6551 InstructionMark im(this); 6552 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6553 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit); 6554 attributes.reset_is_clear_context(); 6555 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6556 emit_int8(0x39); 6557 emit_operand(src, dst); 6558 // 0x00 - extract from lower 128 bits 6559 // 0x01 - extract from upper 128 bits 6560 emit_int8(imm8 & 0x01); 6561 } 6562 6563 void Assembler::vextracti32x4(XMMRegister dst, XMMRegister src, uint8_t imm8) { 6564 assert(VM_Version::supports_evex(), ""); 6565 assert(imm8 <= 0x03, "imm8: %u", imm8); 6566 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6567 attributes.set_is_evex_instruction(); 6568 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6569 emit_int8(0x39); 6570 emit_int8((unsigned char)(0xC0 | encode)); 6571 // 0x00 - extract from bits 127:0 6572 // 0x01 - extract from bits 255:128 6573 // 0x02 - extract from bits 383:256 6574 // 0x03 - extract from bits 511:384 6575 emit_int8(imm8 & 0x03); 6576 } 6577 6578 void Assembler::vextracti32x4(Address dst, XMMRegister src, uint8_t imm8) { 6579 assert(VM_Version::supports_evex(), ""); 6580 assert(src != xnoreg, "sanity"); 6581 assert(imm8 <= 0x03, "imm8: %u", imm8); 6582 InstructionMark im(this); 6583 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6584 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit); 6585 attributes.reset_is_clear_context(); 6586 attributes.set_is_evex_instruction(); 6587 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6588 emit_int8(0x39); 6589 emit_operand(src, dst); 6590 // 0x00 - extract from bits 127:0 6591 // 0x01 - extract from bits 255:128 6592 // 0x02 - extract from bits 383:256 6593 // 0x03 - extract from bits 511:384 6594 emit_int8(imm8 & 0x03); 6595 } 6596 6597 void Assembler::vextracti64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) { 6598 assert(VM_Version::supports_avx512dq(), ""); 6599 assert(imm8 <= 0x03, "imm8: %u", imm8); 6600 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6601 attributes.set_is_evex_instruction(); 6602 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6603 emit_int8(0x39); 6604 emit_int8((unsigned char)(0xC0 | encode)); 6605 // 0x00 - extract from bits 127:0 6606 // 0x01 - extract from bits 255:128 6607 // 0x02 - extract from bits 383:256 6608 // 0x03 - extract from bits 511:384 6609 emit_int8(imm8 & 0x03); 6610 } 6611 6612 void Assembler::vextracti64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) { 6613 assert(VM_Version::supports_evex(), ""); 6614 assert(imm8 <= 0x01, "imm8: %u", imm8); 6615 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6616 attributes.set_is_evex_instruction(); 6617 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6618 emit_int8(0x3B); 6619 emit_int8((unsigned char)(0xC0 | encode)); 6620 // 0x00 - extract from lower 256 bits 6621 // 0x01 - extract from upper 256 bits 6622 emit_int8(imm8 & 0x01); 6623 } 6624 6625 void Assembler::vextracti64x4(Address dst, XMMRegister src, uint8_t imm8) { 6626 assert(VM_Version::supports_evex(), ""); 6627 assert(src != xnoreg, "sanity"); 6628 assert(imm8 <= 0x01, "imm8: %u", imm8); 6629 InstructionMark im(this); 6630 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6631 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_64bit); 6632 attributes.reset_is_clear_context(); 6633 attributes.set_is_evex_instruction(); 6634 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6635 emit_int8(0x38); 6636 emit_operand(src, dst); 6637 // 0x00 - extract from lower 256 bits 6638 // 0x01 - extract from upper 256 bits 6639 emit_int8(imm8 & 0x01); 6640 } 6641 // vextractf forms 6642 6643 void Assembler::vextractf128(XMMRegister dst, XMMRegister src, uint8_t imm8) { 6644 assert(VM_Version::supports_avx(), ""); 6645 assert(imm8 <= 0x01, "imm8: %u", imm8); 6646 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6647 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6648 emit_int8(0x19); 6649 emit_int8((unsigned char)(0xC0 | encode)); 6650 // 0x00 - extract from lower 128 bits 6651 // 0x01 - extract from upper 128 bits 6652 emit_int8(imm8 & 0x01); 6653 } 6654 6655 void Assembler::vextractf128(Address dst, XMMRegister src, uint8_t imm8) { 6656 assert(VM_Version::supports_avx(), ""); 6657 assert(src != xnoreg, "sanity"); 6658 assert(imm8 <= 0x01, "imm8: %u", imm8); 6659 InstructionMark im(this); 6660 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6661 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit); 6662 attributes.reset_is_clear_context(); 6663 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6664 emit_int8(0x19); 6665 emit_operand(src, dst); 6666 // 0x00 - extract from lower 128 bits 6667 // 0x01 - extract from upper 128 bits 6668 emit_int8(imm8 & 0x01); 6669 } 6670 6671 void Assembler::vextractf32x4(XMMRegister dst, XMMRegister src, uint8_t imm8) { 6672 assert(VM_Version::supports_evex(), ""); 6673 assert(imm8 <= 0x03, "imm8: %u", imm8); 6674 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6675 attributes.set_is_evex_instruction(); 6676 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6677 emit_int8(0x19); 6678 emit_int8((unsigned char)(0xC0 | encode)); 6679 // 0x00 - extract from bits 127:0 6680 // 0x01 - extract from bits 255:128 6681 // 0x02 - extract from bits 383:256 6682 // 0x03 - extract from bits 511:384 6683 emit_int8(imm8 & 0x03); 6684 } 6685 6686 void Assembler::vextractf32x4(Address dst, XMMRegister src, uint8_t imm8) { 6687 assert(VM_Version::supports_evex(), ""); 6688 assert(src != xnoreg, "sanity"); 6689 assert(imm8 <= 0x03, "imm8: %u", imm8); 6690 InstructionMark im(this); 6691 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6692 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit); 6693 attributes.reset_is_clear_context(); 6694 attributes.set_is_evex_instruction(); 6695 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6696 emit_int8(0x19); 6697 emit_operand(src, dst); 6698 // 0x00 - extract from bits 127:0 6699 // 0x01 - extract from bits 255:128 6700 // 0x02 - extract from bits 383:256 6701 // 0x03 - extract from bits 511:384 6702 emit_int8(imm8 & 0x03); 6703 } 6704 6705 void Assembler::vextractf64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) { 6706 assert(VM_Version::supports_avx512dq(), ""); 6707 assert(imm8 <= 0x03, "imm8: %u", imm8); 6708 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6709 attributes.set_is_evex_instruction(); 6710 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6711 emit_int8(0x19); 6712 emit_int8((unsigned char)(0xC0 | encode)); 6713 // 0x00 - extract from bits 127:0 6714 // 0x01 - extract from bits 255:128 6715 // 0x02 - extract from bits 383:256 6716 // 0x03 - extract from bits 511:384 6717 emit_int8(imm8 & 0x03); 6718 } 6719 6720 void Assembler::vextractf64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) { 6721 assert(VM_Version::supports_evex(), ""); 6722 assert(imm8 <= 0x01, "imm8: %u", imm8); 6723 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6724 attributes.set_is_evex_instruction(); 6725 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6726 emit_int8(0x1B); 6727 emit_int8((unsigned char)(0xC0 | encode)); 6728 // 0x00 - extract from lower 256 bits 6729 // 0x01 - extract from upper 256 bits 6730 emit_int8(imm8 & 0x01); 6731 } 6732 6733 void Assembler::vextractf64x4(Address dst, XMMRegister src, uint8_t imm8) { 6734 assert(VM_Version::supports_evex(), ""); 6735 assert(src != xnoreg, "sanity"); 6736 assert(imm8 <= 0x01, "imm8: %u", imm8); 6737 InstructionMark im(this); 6738 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6739 attributes.set_address_attributes(/* tuple_type */ EVEX_T4,/* input_size_in_bits */ EVEX_64bit); 6740 attributes.reset_is_clear_context(); 6741 attributes.set_is_evex_instruction(); 6742 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6743 emit_int8(0x1B); 6744 emit_operand(src, dst); 6745 // 0x00 - extract from lower 256 bits 6746 // 0x01 - extract from upper 256 bits 6747 emit_int8(imm8 & 0x01); 6748 } 6749 6750 // duplicate 1-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL 6751 void Assembler::vpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len) { 6752 assert(VM_Version::supports_avx2(), ""); 6753 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 6754 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6755 emit_int8(0x78); 6756 emit_int8((unsigned char)(0xC0 | encode)); 6757 } 6758 6759 void Assembler::vpbroadcastb(XMMRegister dst, Address src, int vector_len) { 6760 assert(VM_Version::supports_avx2(), ""); 6761 assert(dst != xnoreg, "sanity"); 6762 InstructionMark im(this); 6763 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 6764 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit); 6765 // swap src<->dst for encoding 6766 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6767 emit_int8(0x78); 6768 emit_operand(dst, src); 6769 } 6770 6771 // duplicate 2-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL 6772 void Assembler::vpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len) { 6773 assert(VM_Version::supports_avx2(), ""); 6774 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 6775 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6776 emit_int8(0x79); 6777 emit_int8((unsigned char)(0xC0 | encode)); 6778 } 6779 6780 void Assembler::vpbroadcastw(XMMRegister dst, Address src, int vector_len) { 6781 assert(VM_Version::supports_avx2(), ""); 6782 assert(dst != xnoreg, "sanity"); 6783 InstructionMark im(this); 6784 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 6785 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit); 6786 // swap src<->dst for encoding 6787 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6788 emit_int8(0x79); 6789 emit_operand(dst, src); 6790 } 6791 6792 // xmm/mem sourced byte/word/dword/qword replicate 6793 6794 // duplicate 4-byte integer data from src into programmed locations in dest : requires AVX512VL 6795 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len) { 6796 assert(UseAVX >= 2, ""); 6797 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6798 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6799 emit_int8(0x58); 6800 emit_int8((unsigned char)(0xC0 | encode)); 6801 } 6802 6803 void Assembler::vpbroadcastd(XMMRegister dst, Address src, int vector_len) { 6804 assert(VM_Version::supports_avx2(), ""); 6805 assert(dst != xnoreg, "sanity"); 6806 InstructionMark im(this); 6807 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6808 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 6809 // swap src<->dst for encoding 6810 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6811 emit_int8(0x58); 6812 emit_operand(dst, src); 6813 } 6814 6815 // duplicate 8-byte integer data from src into programmed locations in dest : requires AVX512VL 6816 void Assembler::vpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len) { 6817 assert(VM_Version::supports_avx2(), ""); 6818 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6819 attributes.set_rex_vex_w_reverted(); 6820 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6821 emit_int8(0x59); 6822 emit_int8((unsigned char)(0xC0 | encode)); 6823 } 6824 6825 void Assembler::vpbroadcastq(XMMRegister dst, Address src, int vector_len) { 6826 assert(VM_Version::supports_avx2(), ""); 6827 assert(dst != xnoreg, "sanity"); 6828 InstructionMark im(this); 6829 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6830 attributes.set_rex_vex_w_reverted(); 6831 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 6832 // swap src<->dst for encoding 6833 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6834 emit_int8(0x59); 6835 emit_operand(dst, src); 6836 } 6837 void Assembler::evbroadcasti64x2(XMMRegister dst, XMMRegister src, int vector_len) { 6838 assert(vector_len != Assembler::AVX_128bit, ""); 6839 assert(VM_Version::supports_avx512dq(), ""); 6840 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6841 attributes.set_rex_vex_w_reverted(); 6842 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6843 emit_int8(0x5A); 6844 emit_int8((unsigned char)(0xC0 | encode)); 6845 } 6846 6847 void Assembler::evbroadcasti64x2(XMMRegister dst, Address src, int vector_len) { 6848 assert(vector_len != Assembler::AVX_128bit, ""); 6849 assert(VM_Version::supports_avx512dq(), ""); 6850 assert(dst != xnoreg, "sanity"); 6851 InstructionMark im(this); 6852 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6853 attributes.set_rex_vex_w_reverted(); 6854 attributes.set_address_attributes(/* tuple_type */ EVEX_T2, /* input_size_in_bits */ EVEX_64bit); 6855 // swap src<->dst for encoding 6856 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6857 emit_int8(0x5A); 6858 emit_operand(dst, src); 6859 } 6860 6861 // scalar single/double precision replicate 6862 6863 // duplicate single precision data from src into programmed locations in dest : requires AVX512VL 6864 void Assembler::vpbroadcastss(XMMRegister dst, XMMRegister src, int vector_len) { 6865 assert(VM_Version::supports_avx(), ""); 6866 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6867 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6868 emit_int8(0x18); 6869 emit_int8((unsigned char)(0xC0 | encode)); 6870 } 6871 6872 void Assembler::vpbroadcastss(XMMRegister dst, Address src, int vector_len) { 6873 assert(VM_Version::supports_avx(), ""); 6874 assert(dst != xnoreg, "sanity"); 6875 InstructionMark im(this); 6876 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6877 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 6878 // swap src<->dst for encoding 6879 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6880 emit_int8(0x18); 6881 emit_operand(dst, src); 6882 } 6883 6884 // duplicate double precision data from src into programmed locations in dest : requires AVX512VL 6885 void Assembler::vpbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len) { 6886 assert(VM_Version::supports_avx(), ""); 6887 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6888 attributes.set_rex_vex_w_reverted(); 6889 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6890 emit_int8(0x19); 6891 emit_int8((unsigned char)(0xC0 | encode)); 6892 } 6893 6894 void Assembler::vpbroadcastsd(XMMRegister dst, Address src, int vector_len) { 6895 assert(VM_Version::supports_avx(), ""); 6896 assert(dst != xnoreg, "sanity"); 6897 InstructionMark im(this); 6898 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6899 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 6900 attributes.set_rex_vex_w_reverted(); 6901 // swap src<->dst for encoding 6902 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6903 emit_int8(0x19); 6904 emit_operand(dst, src); 6905 } 6906 6907 6908 // gpr source broadcast forms 6909 6910 // duplicate 1-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL 6911 void Assembler::evpbroadcastb(XMMRegister dst, Register src, int vector_len) { 6912 assert(VM_Version::supports_avx512bw(), ""); 6913 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 6914 attributes.set_is_evex_instruction(); 6915 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6916 emit_int8(0x7A); 6917 emit_int8((unsigned char)(0xC0 | encode)); 6918 } 6919 6920 // duplicate 2-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL 6921 void Assembler::evpbroadcastw(XMMRegister dst, Register src, int vector_len) { 6922 assert(VM_Version::supports_avx512bw(), ""); 6923 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 6924 attributes.set_is_evex_instruction(); 6925 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6926 emit_int8(0x7B); 6927 emit_int8((unsigned char)(0xC0 | encode)); 6928 } 6929 6930 // duplicate 4-byte integer data from src into programmed locations in dest : requires AVX512VL 6931 void Assembler::evpbroadcastd(XMMRegister dst, Register src, int vector_len) { 6932 assert(VM_Version::supports_evex(), ""); 6933 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6934 attributes.set_is_evex_instruction(); 6935 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6936 emit_int8(0x7C); 6937 emit_int8((unsigned char)(0xC0 | encode)); 6938 } 6939 6940 // duplicate 8-byte integer data from src into programmed locations in dest : requires AVX512VL 6941 void Assembler::evpbroadcastq(XMMRegister dst, Register src, int vector_len) { 6942 assert(VM_Version::supports_evex(), ""); 6943 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6944 attributes.set_is_evex_instruction(); 6945 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6946 emit_int8(0x7C); 6947 emit_int8((unsigned char)(0xC0 | encode)); 6948 } 6949 6950 void Assembler::evpgatherdd(XMMRegister dst, KRegister mask, Address src, int vector_len) { 6951 assert(VM_Version::supports_evex(), ""); 6952 assert(dst != xnoreg, "sanity"); 6953 InstructionMark im(this); 6954 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6955 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 6956 attributes.reset_is_clear_context(); 6957 attributes.set_embedded_opmask_register_specifier(mask); 6958 attributes.set_is_evex_instruction(); 6959 // swap src<->dst for encoding 6960 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6961 emit_int8((unsigned char)0x90); 6962 emit_operand(dst, src); 6963 } 6964 6965 // Carry-Less Multiplication Quadword 6966 void Assembler::pclmulqdq(XMMRegister dst, XMMRegister src, int mask) { 6967 assert(VM_Version::supports_clmul(), ""); 6968 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ true); 6969 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6970 emit_int8(0x44); 6971 emit_int8((unsigned char)(0xC0 | encode)); 6972 emit_int8((unsigned char)mask); 6973 } 6974 6975 // Carry-Less Multiplication Quadword 6976 void Assembler::vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask) { 6977 assert(VM_Version::supports_avx() && VM_Version::supports_clmul(), ""); 6978 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ true); 6979 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6980 emit_int8(0x44); 6981 emit_int8((unsigned char)(0xC0 | encode)); 6982 emit_int8((unsigned char)mask); 6983 } 6984 6985 void Assembler::evpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask, int vector_len) { 6986 assert(VM_Version::supports_vpclmulqdq(), "Requires vector carryless multiplication support"); 6987 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6988 attributes.set_is_evex_instruction(); 6989 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6990 emit_int8(0x44); 6991 emit_int8((unsigned char)(0xC0 | encode)); 6992 emit_int8((unsigned char)mask); 6993 } 6994 6995 void Assembler::vzeroupper() { 6996 if (VM_Version::supports_vzeroupper()) { 6997 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 6998 (void)vex_prefix_and_encode(0, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 6999 emit_int8(0x77); 7000 } 7001 } 7002 7003 #ifndef _LP64 7004 // 32bit only pieces of the assembler 7005 7006 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) { 7007 // NO PREFIX AS NEVER 64BIT 7008 InstructionMark im(this); 7009 emit_int8((unsigned char)0x81); 7010 emit_int8((unsigned char)(0xF8 | src1->encoding())); 7011 emit_data(imm32, rspec, 0); 7012 } 7013 7014 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) { 7015 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs 7016 InstructionMark im(this); 7017 emit_int8((unsigned char)0x81); 7018 emit_operand(rdi, src1); 7019 emit_data(imm32, rspec, 0); 7020 } 7021 7022 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax, 7023 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded 7024 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise. 7025 void Assembler::cmpxchg8(Address adr) { 7026 InstructionMark im(this); 7027 emit_int8(0x0F); 7028 emit_int8((unsigned char)0xC7); 7029 emit_operand(rcx, adr); 7030 } 7031 7032 void Assembler::decl(Register dst) { 7033 // Don't use it directly. Use MacroAssembler::decrementl() instead. 7034 emit_int8(0x48 | dst->encoding()); 7035 } 7036 7037 #endif // _LP64 7038 7039 // 64bit typically doesn't use the x87 but needs to for the trig funcs 7040 7041 void Assembler::fabs() { 7042 emit_int8((unsigned char)0xD9); 7043 emit_int8((unsigned char)0xE1); 7044 } 7045 7046 void Assembler::fadd(int i) { 7047 emit_farith(0xD8, 0xC0, i); 7048 } 7049 7050 void Assembler::fadd_d(Address src) { 7051 InstructionMark im(this); 7052 emit_int8((unsigned char)0xDC); 7053 emit_operand32(rax, src); 7054 } 7055 7056 void Assembler::fadd_s(Address src) { 7057 InstructionMark im(this); 7058 emit_int8((unsigned char)0xD8); 7059 emit_operand32(rax, src); 7060 } 7061 7062 void Assembler::fadda(int i) { 7063 emit_farith(0xDC, 0xC0, i); 7064 } 7065 7066 void Assembler::faddp(int i) { 7067 emit_farith(0xDE, 0xC0, i); 7068 } 7069 7070 void Assembler::fchs() { 7071 emit_int8((unsigned char)0xD9); 7072 emit_int8((unsigned char)0xE0); 7073 } 7074 7075 void Assembler::fcom(int i) { 7076 emit_farith(0xD8, 0xD0, i); 7077 } 7078 7079 void Assembler::fcomp(int i) { 7080 emit_farith(0xD8, 0xD8, i); 7081 } 7082 7083 void Assembler::fcomp_d(Address src) { 7084 InstructionMark im(this); 7085 emit_int8((unsigned char)0xDC); 7086 emit_operand32(rbx, src); 7087 } 7088 7089 void Assembler::fcomp_s(Address src) { 7090 InstructionMark im(this); 7091 emit_int8((unsigned char)0xD8); 7092 emit_operand32(rbx, src); 7093 } 7094 7095 void Assembler::fcompp() { 7096 emit_int8((unsigned char)0xDE); 7097 emit_int8((unsigned char)0xD9); 7098 } 7099 7100 void Assembler::fcos() { 7101 emit_int8((unsigned char)0xD9); 7102 emit_int8((unsigned char)0xFF); 7103 } 7104 7105 void Assembler::fdecstp() { 7106 emit_int8((unsigned char)0xD9); 7107 emit_int8((unsigned char)0xF6); 7108 } 7109 7110 void Assembler::fdiv(int i) { 7111 emit_farith(0xD8, 0xF0, i); 7112 } 7113 7114 void Assembler::fdiv_d(Address src) { 7115 InstructionMark im(this); 7116 emit_int8((unsigned char)0xDC); 7117 emit_operand32(rsi, src); 7118 } 7119 7120 void Assembler::fdiv_s(Address src) { 7121 InstructionMark im(this); 7122 emit_int8((unsigned char)0xD8); 7123 emit_operand32(rsi, src); 7124 } 7125 7126 void Assembler::fdiva(int i) { 7127 emit_farith(0xDC, 0xF8, i); 7128 } 7129 7130 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994) 7131 // is erroneous for some of the floating-point instructions below. 7132 7133 void Assembler::fdivp(int i) { 7134 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong) 7135 } 7136 7137 void Assembler::fdivr(int i) { 7138 emit_farith(0xD8, 0xF8, i); 7139 } 7140 7141 void Assembler::fdivr_d(Address src) { 7142 InstructionMark im(this); 7143 emit_int8((unsigned char)0xDC); 7144 emit_operand32(rdi, src); 7145 } 7146 7147 void Assembler::fdivr_s(Address src) { 7148 InstructionMark im(this); 7149 emit_int8((unsigned char)0xD8); 7150 emit_operand32(rdi, src); 7151 } 7152 7153 void Assembler::fdivra(int i) { 7154 emit_farith(0xDC, 0xF0, i); 7155 } 7156 7157 void Assembler::fdivrp(int i) { 7158 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong) 7159 } 7160 7161 void Assembler::ffree(int i) { 7162 emit_farith(0xDD, 0xC0, i); 7163 } 7164 7165 void Assembler::fild_d(Address adr) { 7166 InstructionMark im(this); 7167 emit_int8((unsigned char)0xDF); 7168 emit_operand32(rbp, adr); 7169 } 7170 7171 void Assembler::fild_s(Address adr) { 7172 InstructionMark im(this); 7173 emit_int8((unsigned char)0xDB); 7174 emit_operand32(rax, adr); 7175 } 7176 7177 void Assembler::fincstp() { 7178 emit_int8((unsigned char)0xD9); 7179 emit_int8((unsigned char)0xF7); 7180 } 7181 7182 void Assembler::finit() { 7183 emit_int8((unsigned char)0x9B); 7184 emit_int8((unsigned char)0xDB); 7185 emit_int8((unsigned char)0xE3); 7186 } 7187 7188 void Assembler::fist_s(Address adr) { 7189 InstructionMark im(this); 7190 emit_int8((unsigned char)0xDB); 7191 emit_operand32(rdx, adr); 7192 } 7193 7194 void Assembler::fistp_d(Address adr) { 7195 InstructionMark im(this); 7196 emit_int8((unsigned char)0xDF); 7197 emit_operand32(rdi, adr); 7198 } 7199 7200 void Assembler::fistp_s(Address adr) { 7201 InstructionMark im(this); 7202 emit_int8((unsigned char)0xDB); 7203 emit_operand32(rbx, adr); 7204 } 7205 7206 void Assembler::fld1() { 7207 emit_int8((unsigned char)0xD9); 7208 emit_int8((unsigned char)0xE8); 7209 } 7210 7211 void Assembler::fld_d(Address adr) { 7212 InstructionMark im(this); 7213 emit_int8((unsigned char)0xDD); 7214 emit_operand32(rax, adr); 7215 } 7216 7217 void Assembler::fld_s(Address adr) { 7218 InstructionMark im(this); 7219 emit_int8((unsigned char)0xD9); 7220 emit_operand32(rax, adr); 7221 } 7222 7223 7224 void Assembler::fld_s(int index) { 7225 emit_farith(0xD9, 0xC0, index); 7226 } 7227 7228 void Assembler::fld_x(Address adr) { 7229 InstructionMark im(this); 7230 emit_int8((unsigned char)0xDB); 7231 emit_operand32(rbp, adr); 7232 } 7233 7234 void Assembler::fldcw(Address src) { 7235 InstructionMark im(this); 7236 emit_int8((unsigned char)0xD9); 7237 emit_operand32(rbp, src); 7238 } 7239 7240 void Assembler::fldenv(Address src) { 7241 InstructionMark im(this); 7242 emit_int8((unsigned char)0xD9); 7243 emit_operand32(rsp, src); 7244 } 7245 7246 void Assembler::fldlg2() { 7247 emit_int8((unsigned char)0xD9); 7248 emit_int8((unsigned char)0xEC); 7249 } 7250 7251 void Assembler::fldln2() { 7252 emit_int8((unsigned char)0xD9); 7253 emit_int8((unsigned char)0xED); 7254 } 7255 7256 void Assembler::fldz() { 7257 emit_int8((unsigned char)0xD9); 7258 emit_int8((unsigned char)0xEE); 7259 } 7260 7261 void Assembler::flog() { 7262 fldln2(); 7263 fxch(); 7264 fyl2x(); 7265 } 7266 7267 void Assembler::flog10() { 7268 fldlg2(); 7269 fxch(); 7270 fyl2x(); 7271 } 7272 7273 void Assembler::fmul(int i) { 7274 emit_farith(0xD8, 0xC8, i); 7275 } 7276 7277 void Assembler::fmul_d(Address src) { 7278 InstructionMark im(this); 7279 emit_int8((unsigned char)0xDC); 7280 emit_operand32(rcx, src); 7281 } 7282 7283 void Assembler::fmul_s(Address src) { 7284 InstructionMark im(this); 7285 emit_int8((unsigned char)0xD8); 7286 emit_operand32(rcx, src); 7287 } 7288 7289 void Assembler::fmula(int i) { 7290 emit_farith(0xDC, 0xC8, i); 7291 } 7292 7293 void Assembler::fmulp(int i) { 7294 emit_farith(0xDE, 0xC8, i); 7295 } 7296 7297 void Assembler::fnsave(Address dst) { 7298 InstructionMark im(this); 7299 emit_int8((unsigned char)0xDD); 7300 emit_operand32(rsi, dst); 7301 } 7302 7303 void Assembler::fnstcw(Address src) { 7304 InstructionMark im(this); 7305 emit_int8((unsigned char)0x9B); 7306 emit_int8((unsigned char)0xD9); 7307 emit_operand32(rdi, src); 7308 } 7309 7310 void Assembler::fnstsw_ax() { 7311 emit_int8((unsigned char)0xDF); 7312 emit_int8((unsigned char)0xE0); 7313 } 7314 7315 void Assembler::fprem() { 7316 emit_int8((unsigned char)0xD9); 7317 emit_int8((unsigned char)0xF8); 7318 } 7319 7320 void Assembler::fprem1() { 7321 emit_int8((unsigned char)0xD9); 7322 emit_int8((unsigned char)0xF5); 7323 } 7324 7325 void Assembler::frstor(Address src) { 7326 InstructionMark im(this); 7327 emit_int8((unsigned char)0xDD); 7328 emit_operand32(rsp, src); 7329 } 7330 7331 void Assembler::fsin() { 7332 emit_int8((unsigned char)0xD9); 7333 emit_int8((unsigned char)0xFE); 7334 } 7335 7336 void Assembler::fsqrt() { 7337 emit_int8((unsigned char)0xD9); 7338 emit_int8((unsigned char)0xFA); 7339 } 7340 7341 void Assembler::fst_d(Address adr) { 7342 InstructionMark im(this); 7343 emit_int8((unsigned char)0xDD); 7344 emit_operand32(rdx, adr); 7345 } 7346 7347 void Assembler::fst_s(Address adr) { 7348 InstructionMark im(this); 7349 emit_int8((unsigned char)0xD9); 7350 emit_operand32(rdx, adr); 7351 } 7352 7353 void Assembler::fstp_d(Address adr) { 7354 InstructionMark im(this); 7355 emit_int8((unsigned char)0xDD); 7356 emit_operand32(rbx, adr); 7357 } 7358 7359 void Assembler::fstp_d(int index) { 7360 emit_farith(0xDD, 0xD8, index); 7361 } 7362 7363 void Assembler::fstp_s(Address adr) { 7364 InstructionMark im(this); 7365 emit_int8((unsigned char)0xD9); 7366 emit_operand32(rbx, adr); 7367 } 7368 7369 void Assembler::fstp_x(Address adr) { 7370 InstructionMark im(this); 7371 emit_int8((unsigned char)0xDB); 7372 emit_operand32(rdi, adr); 7373 } 7374 7375 void Assembler::fsub(int i) { 7376 emit_farith(0xD8, 0xE0, i); 7377 } 7378 7379 void Assembler::fsub_d(Address src) { 7380 InstructionMark im(this); 7381 emit_int8((unsigned char)0xDC); 7382 emit_operand32(rsp, src); 7383 } 7384 7385 void Assembler::fsub_s(Address src) { 7386 InstructionMark im(this); 7387 emit_int8((unsigned char)0xD8); 7388 emit_operand32(rsp, src); 7389 } 7390 7391 void Assembler::fsuba(int i) { 7392 emit_farith(0xDC, 0xE8, i); 7393 } 7394 7395 void Assembler::fsubp(int i) { 7396 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong) 7397 } 7398 7399 void Assembler::fsubr(int i) { 7400 emit_farith(0xD8, 0xE8, i); 7401 } 7402 7403 void Assembler::fsubr_d(Address src) { 7404 InstructionMark im(this); 7405 emit_int8((unsigned char)0xDC); 7406 emit_operand32(rbp, src); 7407 } 7408 7409 void Assembler::fsubr_s(Address src) { 7410 InstructionMark im(this); 7411 emit_int8((unsigned char)0xD8); 7412 emit_operand32(rbp, src); 7413 } 7414 7415 void Assembler::fsubra(int i) { 7416 emit_farith(0xDC, 0xE0, i); 7417 } 7418 7419 void Assembler::fsubrp(int i) { 7420 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong) 7421 } 7422 7423 void Assembler::ftan() { 7424 emit_int8((unsigned char)0xD9); 7425 emit_int8((unsigned char)0xF2); 7426 emit_int8((unsigned char)0xDD); 7427 emit_int8((unsigned char)0xD8); 7428 } 7429 7430 void Assembler::ftst() { 7431 emit_int8((unsigned char)0xD9); 7432 emit_int8((unsigned char)0xE4); 7433 } 7434 7435 void Assembler::fucomi(int i) { 7436 // make sure the instruction is supported (introduced for P6, together with cmov) 7437 guarantee(VM_Version::supports_cmov(), "illegal instruction"); 7438 emit_farith(0xDB, 0xE8, i); 7439 } 7440 7441 void Assembler::fucomip(int i) { 7442 // make sure the instruction is supported (introduced for P6, together with cmov) 7443 guarantee(VM_Version::supports_cmov(), "illegal instruction"); 7444 emit_farith(0xDF, 0xE8, i); 7445 } 7446 7447 void Assembler::fwait() { 7448 emit_int8((unsigned char)0x9B); 7449 } 7450 7451 void Assembler::fxch(int i) { 7452 emit_farith(0xD9, 0xC8, i); 7453 } 7454 7455 void Assembler::fyl2x() { 7456 emit_int8((unsigned char)0xD9); 7457 emit_int8((unsigned char)0xF1); 7458 } 7459 7460 void Assembler::frndint() { 7461 emit_int8((unsigned char)0xD9); 7462 emit_int8((unsigned char)0xFC); 7463 } 7464 7465 void Assembler::f2xm1() { 7466 emit_int8((unsigned char)0xD9); 7467 emit_int8((unsigned char)0xF0); 7468 } 7469 7470 void Assembler::fldl2e() { 7471 emit_int8((unsigned char)0xD9); 7472 emit_int8((unsigned char)0xEA); 7473 } 7474 7475 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding. 7476 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 }; 7477 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding. 7478 static int simd_opc[4] = { 0, 0, 0x38, 0x3A }; 7479 7480 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding. 7481 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) { 7482 if (pre > 0) { 7483 emit_int8(simd_pre[pre]); 7484 } 7485 if (rex_w) { 7486 prefixq(adr, xreg); 7487 } else { 7488 prefix(adr, xreg); 7489 } 7490 if (opc > 0) { 7491 emit_int8(0x0F); 7492 int opc2 = simd_opc[opc]; 7493 if (opc2 > 0) { 7494 emit_int8(opc2); 7495 } 7496 } 7497 } 7498 7499 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) { 7500 if (pre > 0) { 7501 emit_int8(simd_pre[pre]); 7502 } 7503 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) : prefix_and_encode(dst_enc, src_enc); 7504 if (opc > 0) { 7505 emit_int8(0x0F); 7506 int opc2 = simd_opc[opc]; 7507 if (opc2 > 0) { 7508 emit_int8(opc2); 7509 } 7510 } 7511 return encode; 7512 } 7513 7514 7515 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc) { 7516 int vector_len = _attributes->get_vector_len(); 7517 bool vex_w = _attributes->is_rex_vex_w(); 7518 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) { 7519 prefix(VEX_3bytes); 7520 7521 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0); 7522 byte1 = (~byte1) & 0xE0; 7523 byte1 |= opc; 7524 emit_int8(byte1); 7525 7526 int byte2 = ((~nds_enc) & 0xf) << 3; 7527 byte2 |= (vex_w ? VEX_W : 0) | ((vector_len > 0) ? 4 : 0) | pre; 7528 emit_int8(byte2); 7529 } else { 7530 prefix(VEX_2bytes); 7531 7532 int byte1 = vex_r ? VEX_R : 0; 7533 byte1 = (~byte1) & 0x80; 7534 byte1 |= ((~nds_enc) & 0xf) << 3; 7535 byte1 |= ((vector_len > 0 ) ? 4 : 0) | pre; 7536 emit_int8(byte1); 7537 } 7538 } 7539 7540 // This is a 4 byte encoding 7541 void Assembler::evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_r, bool evex_v, int nds_enc, VexSimdPrefix pre, VexOpcode opc){ 7542 // EVEX 0x62 prefix 7543 prefix(EVEX_4bytes); 7544 bool vex_w = _attributes->is_rex_vex_w(); 7545 int evex_encoding = (vex_w ? VEX_W : 0); 7546 // EVEX.b is not currently used for broadcast of single element or data rounding modes 7547 _attributes->set_evex_encoding(evex_encoding); 7548 7549 // P0: byte 2, initialized to RXBR`00mm 7550 // instead of not'd 7551 int byte2 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0) | (evex_r ? EVEX_Rb : 0); 7552 byte2 = (~byte2) & 0xF0; 7553 // confine opc opcode extensions in mm bits to lower two bits 7554 // of form {0F, 0F_38, 0F_3A} 7555 byte2 |= opc; 7556 emit_int8(byte2); 7557 7558 // P1: byte 3 as Wvvvv1pp 7559 int byte3 = ((~nds_enc) & 0xf) << 3; 7560 // p[10] is always 1 7561 byte3 |= EVEX_F; 7562 byte3 |= (vex_w & 1) << 7; 7563 // confine pre opcode extensions in pp bits to lower two bits 7564 // of form {66, F3, F2} 7565 byte3 |= pre; 7566 emit_int8(byte3); 7567 7568 // P2: byte 4 as zL'Lbv'aaa 7569 // kregs are implemented in the low 3 bits as aaa (hard code k1, it will be initialized for now) 7570 int byte4 = (_attributes->is_no_reg_mask()) ? 7571 0 : 7572 _attributes->get_embedded_opmask_register_specifier(); 7573 // EVEX.v` for extending EVEX.vvvv or VIDX 7574 byte4 |= (evex_v ? 0: EVEX_V); 7575 // third EXEC.b for broadcast actions 7576 byte4 |= (_attributes->is_extended_context() ? EVEX_Rb : 0); 7577 // fourth EVEX.L'L for vector length : 0 is 128, 1 is 256, 2 is 512, currently we do not support 1024 7578 byte4 |= ((_attributes->get_vector_len())& 0x3) << 5; 7579 // last is EVEX.z for zero/merge actions 7580 if (_attributes->is_no_reg_mask() == false) { 7581 byte4 |= (_attributes->is_clear_context() ? EVEX_Z : 0); 7582 } 7583 emit_int8(byte4); 7584 } 7585 7586 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) { 7587 bool vex_r = ((xreg_enc & 8) == 8) ? 1 : 0; 7588 bool vex_b = adr.base_needs_rex(); 7589 bool vex_x; 7590 if (adr.isxmmindex()) { 7591 vex_x = adr.xmmindex_needs_rex(); 7592 } else { 7593 vex_x = adr.index_needs_rex(); 7594 } 7595 set_attributes(attributes); 7596 attributes->set_current_assembler(this); 7597 7598 // For EVEX instruction (which is not marked as pure EVEX instruction) check and see if this instruction 7599 // is allowed in legacy mode and has resources which will fit in it. 7600 // Pure EVEX instructions will have is_evex_instruction set in their definition. 7601 if (!attributes->is_legacy_mode()) { 7602 if (UseAVX > 2 && !attributes->is_evex_instruction() && !_is_managed) { 7603 if ((attributes->get_vector_len() != AVX_512bit) && (nds_enc < 16) && (xreg_enc < 16)) { 7604 attributes->set_is_legacy_mode(); 7605 } 7606 } 7607 } 7608 7609 if (UseAVX > 2) { 7610 assert(((!attributes->uses_vl()) || 7611 (attributes->get_vector_len() == AVX_512bit) || 7612 (!_legacy_mode_vl) || 7613 (attributes->is_legacy_mode())),"XMM register should be 0-15"); 7614 assert(((nds_enc < 16 && xreg_enc < 16) || (!attributes->is_legacy_mode())),"XMM register should be 0-15"); 7615 } 7616 7617 _is_managed = false; 7618 if (UseAVX > 2 && !attributes->is_legacy_mode()) 7619 { 7620 bool evex_r = (xreg_enc >= 16); 7621 bool evex_v; 7622 // EVEX.V' is set to true when VSIB is used as we may need to use higher order XMM registers (16-31) 7623 if (adr.isxmmindex()) { 7624 evex_v = ((adr._xmmindex->encoding() > 15) ? true : false); 7625 } else { 7626 evex_v = (nds_enc >= 16); 7627 } 7628 attributes->set_is_evex_instruction(); 7629 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc); 7630 } else { 7631 if (UseAVX > 2 && attributes->is_rex_vex_w_reverted()) { 7632 attributes->set_rex_vex_w(false); 7633 } 7634 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc); 7635 } 7636 } 7637 7638 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) { 7639 bool vex_r = ((dst_enc & 8) == 8) ? 1 : 0; 7640 bool vex_b = ((src_enc & 8) == 8) ? 1 : 0; 7641 bool vex_x = false; 7642 set_attributes(attributes); 7643 attributes->set_current_assembler(this); 7644 7645 // For EVEX instruction (which is not marked as pure EVEX instruction) check and see if this instruction 7646 // is allowed in legacy mode and has resources which will fit in it. 7647 // Pure EVEX instructions will have is_evex_instruction set in their definition. 7648 if (!attributes->is_legacy_mode()) { 7649 if (UseAVX > 2 && !attributes->is_evex_instruction() && !_is_managed) { 7650 if ((!attributes->uses_vl() || (attributes->get_vector_len() != AVX_512bit)) && 7651 (dst_enc < 16) && (nds_enc < 16) && (src_enc < 16)) { 7652 attributes->set_is_legacy_mode(); 7653 } 7654 } 7655 } 7656 7657 if (UseAVX > 2) { 7658 // All the scalar fp instructions (with uses_vl as false) can have legacy_mode as false 7659 // Instruction with uses_vl true are vector instructions 7660 // All the vector instructions with AVX_512bit length can have legacy_mode as false 7661 // All the vector instructions with < AVX_512bit length can have legacy_mode as false if AVX512vl() is supported 7662 // Rest all should have legacy_mode set as true 7663 assert(((!attributes->uses_vl()) || 7664 (attributes->get_vector_len() == AVX_512bit) || 7665 (!_legacy_mode_vl) || 7666 (attributes->is_legacy_mode())),"XMM register should be 0-15"); 7667 // Instruction with legacy_mode true should have dst, nds and src < 15 7668 assert(((dst_enc < 16 && nds_enc < 16 && src_enc < 16) || (!attributes->is_legacy_mode())),"XMM register should be 0-15"); 7669 } 7670 7671 _is_managed = false; 7672 if (UseAVX > 2 && !attributes->is_legacy_mode()) 7673 { 7674 bool evex_r = (dst_enc >= 16); 7675 bool evex_v = (nds_enc >= 16); 7676 // can use vex_x as bank extender on rm encoding 7677 vex_x = (src_enc >= 16); 7678 attributes->set_is_evex_instruction(); 7679 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc); 7680 } else { 7681 if (UseAVX > 2 && attributes->is_rex_vex_w_reverted()) { 7682 attributes->set_rex_vex_w(false); 7683 } 7684 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc); 7685 } 7686 7687 // return modrm byte components for operands 7688 return (((dst_enc & 7) << 3) | (src_enc & 7)); 7689 } 7690 7691 7692 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre, 7693 VexOpcode opc, InstructionAttr *attributes) { 7694 if (UseAVX > 0) { 7695 int xreg_enc = xreg->encoding(); 7696 int nds_enc = nds->is_valid() ? nds->encoding() : 0; 7697 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, attributes); 7698 } else { 7699 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding"); 7700 rex_prefix(adr, xreg, pre, opc, attributes->is_rex_vex_w()); 7701 } 7702 } 7703 7704 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre, 7705 VexOpcode opc, InstructionAttr *attributes) { 7706 int dst_enc = dst->encoding(); 7707 int src_enc = src->encoding(); 7708 if (UseAVX > 0) { 7709 int nds_enc = nds->is_valid() ? nds->encoding() : 0; 7710 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, attributes); 7711 } else { 7712 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding"); 7713 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, attributes->is_rex_vex_w()); 7714 } 7715 } 7716 7717 void Assembler::cmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) { 7718 assert(VM_Version::supports_avx(), ""); 7719 assert(!VM_Version::supports_evex(), ""); 7720 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ true); 7721 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 7722 emit_int8((unsigned char)0xC2); 7723 emit_int8((unsigned char)(0xC0 | encode)); 7724 emit_int8((unsigned char)(0xF & cop)); 7725 } 7726 7727 void Assembler::blendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) { 7728 assert(VM_Version::supports_avx(), ""); 7729 assert(!VM_Version::supports_evex(), ""); 7730 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ true); 7731 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 7732 emit_int8((unsigned char)0x4B); 7733 emit_int8((unsigned char)(0xC0 | encode)); 7734 int src2_enc = src2->encoding(); 7735 emit_int8((unsigned char)(0xF0 & src2_enc<<4)); 7736 } 7737 7738 void Assembler::cmpps(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) { 7739 assert(VM_Version::supports_avx(), ""); 7740 assert(!VM_Version::supports_evex(), ""); 7741 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ true); 7742 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 7743 emit_int8((unsigned char)0xC2); 7744 emit_int8((unsigned char)(0xC0 | encode)); 7745 emit_int8((unsigned char)(0xF & cop)); 7746 } 7747 7748 void Assembler::blendvps(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) { 7749 assert(VM_Version::supports_avx(), ""); 7750 assert(!VM_Version::supports_evex(), ""); 7751 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ true); 7752 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 7753 emit_int8((unsigned char)0x4A); 7754 emit_int8((unsigned char)(0xC0 | encode)); 7755 int src2_enc = src2->encoding(); 7756 emit_int8((unsigned char)(0xF0 & src2_enc<<4)); 7757 } 7758 7759 void Assembler::vpblendd(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) { 7760 assert(VM_Version::supports_avx2(), ""); 7761 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ true); 7762 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 7763 emit_int8((unsigned char)0x02); 7764 emit_int8((unsigned char)(0xC0 | encode)); 7765 emit_int8((unsigned char)imm8); 7766 } 7767 7768 void Assembler::shlxl(Register dst, Register src1, Register src2) { 7769 assert(VM_Version::supports_bmi2(), ""); 7770 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true); 7771 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 7772 emit_int8((unsigned char)0xF7); 7773 emit_int8((unsigned char)(0xC0 | encode)); 7774 } 7775 7776 void Assembler::shlxq(Register dst, Register src1, Register src2) { 7777 assert(VM_Version::supports_bmi2(), ""); 7778 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true); 7779 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 7780 emit_int8((unsigned char)0xF7); 7781 emit_int8((unsigned char)(0xC0 | encode)); 7782 } 7783 7784 #ifndef _LP64 7785 7786 void Assembler::incl(Register dst) { 7787 // Don't use it directly. Use MacroAssembler::incrementl() instead. 7788 emit_int8(0x40 | dst->encoding()); 7789 } 7790 7791 void Assembler::lea(Register dst, Address src) { 7792 leal(dst, src); 7793 } 7794 7795 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) { 7796 InstructionMark im(this); 7797 emit_int8((unsigned char)0xC7); 7798 emit_operand(rax, dst); 7799 emit_data((int)imm32, rspec, 0); 7800 } 7801 7802 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) { 7803 InstructionMark im(this); 7804 int encode = prefix_and_encode(dst->encoding()); 7805 emit_int8((unsigned char)(0xB8 | encode)); 7806 emit_data((int)imm32, rspec, 0); 7807 } 7808 7809 void Assembler::popa() { // 32bit 7810 emit_int8(0x61); 7811 } 7812 7813 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) { 7814 InstructionMark im(this); 7815 emit_int8(0x68); 7816 emit_data(imm32, rspec, 0); 7817 } 7818 7819 void Assembler::pusha() { // 32bit 7820 emit_int8(0x60); 7821 } 7822 7823 void Assembler::set_byte_if_not_zero(Register dst) { 7824 emit_int8(0x0F); 7825 emit_int8((unsigned char)0x95); 7826 emit_int8((unsigned char)(0xE0 | dst->encoding())); 7827 } 7828 7829 void Assembler::shldl(Register dst, Register src) { 7830 emit_int8(0x0F); 7831 emit_int8((unsigned char)0xA5); 7832 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding())); 7833 } 7834 7835 // 0F A4 / r ib 7836 void Assembler::shldl(Register dst, Register src, int8_t imm8) { 7837 emit_int8(0x0F); 7838 emit_int8((unsigned char)0xA4); 7839 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding())); 7840 emit_int8(imm8); 7841 } 7842 7843 void Assembler::shrdl(Register dst, Register src) { 7844 emit_int8(0x0F); 7845 emit_int8((unsigned char)0xAD); 7846 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding())); 7847 } 7848 7849 #else // LP64 7850 7851 void Assembler::set_byte_if_not_zero(Register dst) { 7852 int enc = prefix_and_encode(dst->encoding(), true); 7853 emit_int8(0x0F); 7854 emit_int8((unsigned char)0x95); 7855 emit_int8((unsigned char)(0xE0 | enc)); 7856 } 7857 7858 // 64bit only pieces of the assembler 7859 // This should only be used by 64bit instructions that can use rip-relative 7860 // it cannot be used by instructions that want an immediate value. 7861 7862 bool Assembler::reachable(AddressLiteral adr) { 7863 int64_t disp; 7864 // None will force a 64bit literal to the code stream. Likely a placeholder 7865 // for something that will be patched later and we need to certain it will 7866 // always be reachable. 7867 if (adr.reloc() == relocInfo::none) { 7868 return false; 7869 } 7870 if (adr.reloc() == relocInfo::internal_word_type) { 7871 // This should be rip relative and easily reachable. 7872 return true; 7873 } 7874 if (adr.reloc() == relocInfo::virtual_call_type || 7875 adr.reloc() == relocInfo::opt_virtual_call_type || 7876 adr.reloc() == relocInfo::static_call_type || 7877 adr.reloc() == relocInfo::static_stub_type ) { 7878 // This should be rip relative within the code cache and easily 7879 // reachable until we get huge code caches. (At which point 7880 // ic code is going to have issues). 7881 return true; 7882 } 7883 if (adr.reloc() != relocInfo::external_word_type && 7884 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special 7885 adr.reloc() != relocInfo::poll_type && // relocs to identify them 7886 adr.reloc() != relocInfo::runtime_call_type ) { 7887 return false; 7888 } 7889 7890 // Stress the correction code 7891 if (ForceUnreachable) { 7892 // Must be runtimecall reloc, see if it is in the codecache 7893 // Flipping stuff in the codecache to be unreachable causes issues 7894 // with things like inline caches where the additional instructions 7895 // are not handled. 7896 if (CodeCache::find_blob(adr._target) == NULL) { 7897 return false; 7898 } 7899 } 7900 // For external_word_type/runtime_call_type if it is reachable from where we 7901 // are now (possibly a temp buffer) and where we might end up 7902 // anywhere in the codeCache then we are always reachable. 7903 // This would have to change if we ever save/restore shared code 7904 // to be more pessimistic. 7905 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int)); 7906 if (!is_simm32(disp)) return false; 7907 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int)); 7908 if (!is_simm32(disp)) return false; 7909 7910 disp = (int64_t)adr._target - ((int64_t)pc() + sizeof(int)); 7911 7912 // Because rip relative is a disp + address_of_next_instruction and we 7913 // don't know the value of address_of_next_instruction we apply a fudge factor 7914 // to make sure we will be ok no matter the size of the instruction we get placed into. 7915 // We don't have to fudge the checks above here because they are already worst case. 7916 7917 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal 7918 // + 4 because better safe than sorry. 7919 const int fudge = 12 + 4; 7920 if (disp < 0) { 7921 disp -= fudge; 7922 } else { 7923 disp += fudge; 7924 } 7925 return is_simm32(disp); 7926 } 7927 7928 // Check if the polling page is not reachable from the code cache using rip-relative 7929 // addressing. 7930 bool Assembler::is_polling_page_far() { 7931 intptr_t addr = (intptr_t)os::get_polling_page(); 7932 return ForceUnreachable || 7933 !is_simm32(addr - (intptr_t)CodeCache::low_bound()) || 7934 !is_simm32(addr - (intptr_t)CodeCache::high_bound()); 7935 } 7936 7937 void Assembler::emit_data64(jlong data, 7938 relocInfo::relocType rtype, 7939 int format) { 7940 if (rtype == relocInfo::none) { 7941 emit_int64(data); 7942 } else { 7943 emit_data64(data, Relocation::spec_simple(rtype), format); 7944 } 7945 } 7946 7947 void Assembler::emit_data64(jlong data, 7948 RelocationHolder const& rspec, 7949 int format) { 7950 assert(imm_operand == 0, "default format must be immediate in this file"); 7951 assert(imm_operand == format, "must be immediate"); 7952 assert(inst_mark() != NULL, "must be inside InstructionMark"); 7953 // Do not use AbstractAssembler::relocate, which is not intended for 7954 // embedded words. Instead, relocate to the enclosing instruction. 7955 code_section()->relocate(inst_mark(), rspec, format); 7956 #ifdef ASSERT 7957 check_relocation(rspec, format); 7958 #endif 7959 emit_int64(data); 7960 } 7961 7962 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) { 7963 if (reg_enc >= 8) { 7964 prefix(REX_B); 7965 reg_enc -= 8; 7966 } else if (byteinst && reg_enc >= 4) { 7967 prefix(REX); 7968 } 7969 return reg_enc; 7970 } 7971 7972 int Assembler::prefixq_and_encode(int reg_enc) { 7973 if (reg_enc < 8) { 7974 prefix(REX_W); 7975 } else { 7976 prefix(REX_WB); 7977 reg_enc -= 8; 7978 } 7979 return reg_enc; 7980 } 7981 7982 int Assembler::prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte) { 7983 if (dst_enc < 8) { 7984 if (src_enc >= 8) { 7985 prefix(REX_B); 7986 src_enc -= 8; 7987 } else if ((src_is_byte && src_enc >= 4) || (dst_is_byte && dst_enc >= 4)) { 7988 prefix(REX); 7989 } 7990 } else { 7991 if (src_enc < 8) { 7992 prefix(REX_R); 7993 } else { 7994 prefix(REX_RB); 7995 src_enc -= 8; 7996 } 7997 dst_enc -= 8; 7998 } 7999 return dst_enc << 3 | src_enc; 8000 } 8001 8002 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) { 8003 if (dst_enc < 8) { 8004 if (src_enc < 8) { 8005 prefix(REX_W); 8006 } else { 8007 prefix(REX_WB); 8008 src_enc -= 8; 8009 } 8010 } else { 8011 if (src_enc < 8) { 8012 prefix(REX_WR); 8013 } else { 8014 prefix(REX_WRB); 8015 src_enc -= 8; 8016 } 8017 dst_enc -= 8; 8018 } 8019 return dst_enc << 3 | src_enc; 8020 } 8021 8022 void Assembler::prefix(Register reg) { 8023 if (reg->encoding() >= 8) { 8024 prefix(REX_B); 8025 } 8026 } 8027 8028 void Assembler::prefix(Register dst, Register src, Prefix p) { 8029 if (src->encoding() >= 8) { 8030 p = (Prefix)(p | REX_B); 8031 } 8032 if (dst->encoding() >= 8) { 8033 p = (Prefix)( p | REX_R); 8034 } 8035 if (p != Prefix_EMPTY) { 8036 // do not generate an empty prefix 8037 prefix(p); 8038 } 8039 } 8040 8041 void Assembler::prefix(Register dst, Address adr, Prefix p) { 8042 if (adr.base_needs_rex()) { 8043 if (adr.index_needs_rex()) { 8044 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X"); 8045 } else { 8046 prefix(REX_B); 8047 } 8048 } else { 8049 if (adr.index_needs_rex()) { 8050 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X"); 8051 } 8052 } 8053 if (dst->encoding() >= 8) { 8054 p = (Prefix)(p | REX_R); 8055 } 8056 if (p != Prefix_EMPTY) { 8057 // do not generate an empty prefix 8058 prefix(p); 8059 } 8060 } 8061 8062 void Assembler::prefix(Address adr) { 8063 if (adr.base_needs_rex()) { 8064 if (adr.index_needs_rex()) { 8065 prefix(REX_XB); 8066 } else { 8067 prefix(REX_B); 8068 } 8069 } else { 8070 if (adr.index_needs_rex()) { 8071 prefix(REX_X); 8072 } 8073 } 8074 } 8075 8076 void Assembler::prefixq(Address adr) { 8077 if (adr.base_needs_rex()) { 8078 if (adr.index_needs_rex()) { 8079 prefix(REX_WXB); 8080 } else { 8081 prefix(REX_WB); 8082 } 8083 } else { 8084 if (adr.index_needs_rex()) { 8085 prefix(REX_WX); 8086 } else { 8087 prefix(REX_W); 8088 } 8089 } 8090 } 8091 8092 8093 void Assembler::prefix(Address adr, Register reg, bool byteinst) { 8094 if (reg->encoding() < 8) { 8095 if (adr.base_needs_rex()) { 8096 if (adr.index_needs_rex()) { 8097 prefix(REX_XB); 8098 } else { 8099 prefix(REX_B); 8100 } 8101 } else { 8102 if (adr.index_needs_rex()) { 8103 prefix(REX_X); 8104 } else if (byteinst && reg->encoding() >= 4 ) { 8105 prefix(REX); 8106 } 8107 } 8108 } else { 8109 if (adr.base_needs_rex()) { 8110 if (adr.index_needs_rex()) { 8111 prefix(REX_RXB); 8112 } else { 8113 prefix(REX_RB); 8114 } 8115 } else { 8116 if (adr.index_needs_rex()) { 8117 prefix(REX_RX); 8118 } else { 8119 prefix(REX_R); 8120 } 8121 } 8122 } 8123 } 8124 8125 void Assembler::prefixq(Address adr, Register src) { 8126 if (src->encoding() < 8) { 8127 if (adr.base_needs_rex()) { 8128 if (adr.index_needs_rex()) { 8129 prefix(REX_WXB); 8130 } else { 8131 prefix(REX_WB); 8132 } 8133 } else { 8134 if (adr.index_needs_rex()) { 8135 prefix(REX_WX); 8136 } else { 8137 prefix(REX_W); 8138 } 8139 } 8140 } else { 8141 if (adr.base_needs_rex()) { 8142 if (adr.index_needs_rex()) { 8143 prefix(REX_WRXB); 8144 } else { 8145 prefix(REX_WRB); 8146 } 8147 } else { 8148 if (adr.index_needs_rex()) { 8149 prefix(REX_WRX); 8150 } else { 8151 prefix(REX_WR); 8152 } 8153 } 8154 } 8155 } 8156 8157 void Assembler::prefix(Address adr, XMMRegister reg) { 8158 if (reg->encoding() < 8) { 8159 if (adr.base_needs_rex()) { 8160 if (adr.index_needs_rex()) { 8161 prefix(REX_XB); 8162 } else { 8163 prefix(REX_B); 8164 } 8165 } else { 8166 if (adr.index_needs_rex()) { 8167 prefix(REX_X); 8168 } 8169 } 8170 } else { 8171 if (adr.base_needs_rex()) { 8172 if (adr.index_needs_rex()) { 8173 prefix(REX_RXB); 8174 } else { 8175 prefix(REX_RB); 8176 } 8177 } else { 8178 if (adr.index_needs_rex()) { 8179 prefix(REX_RX); 8180 } else { 8181 prefix(REX_R); 8182 } 8183 } 8184 } 8185 } 8186 8187 void Assembler::prefixq(Address adr, XMMRegister src) { 8188 if (src->encoding() < 8) { 8189 if (adr.base_needs_rex()) { 8190 if (adr.index_needs_rex()) { 8191 prefix(REX_WXB); 8192 } else { 8193 prefix(REX_WB); 8194 } 8195 } else { 8196 if (adr.index_needs_rex()) { 8197 prefix(REX_WX); 8198 } else { 8199 prefix(REX_W); 8200 } 8201 } 8202 } else { 8203 if (adr.base_needs_rex()) { 8204 if (adr.index_needs_rex()) { 8205 prefix(REX_WRXB); 8206 } else { 8207 prefix(REX_WRB); 8208 } 8209 } else { 8210 if (adr.index_needs_rex()) { 8211 prefix(REX_WRX); 8212 } else { 8213 prefix(REX_WR); 8214 } 8215 } 8216 } 8217 } 8218 8219 void Assembler::adcq(Register dst, int32_t imm32) { 8220 (void) prefixq_and_encode(dst->encoding()); 8221 emit_arith(0x81, 0xD0, dst, imm32); 8222 } 8223 8224 void Assembler::adcq(Register dst, Address src) { 8225 InstructionMark im(this); 8226 prefixq(src, dst); 8227 emit_int8(0x13); 8228 emit_operand(dst, src); 8229 } 8230 8231 void Assembler::adcq(Register dst, Register src) { 8232 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 8233 emit_arith(0x13, 0xC0, dst, src); 8234 } 8235 8236 void Assembler::addq(Address dst, int32_t imm32) { 8237 InstructionMark im(this); 8238 prefixq(dst); 8239 emit_arith_operand(0x81, rax, dst,imm32); 8240 } 8241 8242 void Assembler::addq(Address dst, Register src) { 8243 InstructionMark im(this); 8244 prefixq(dst, src); 8245 emit_int8(0x01); 8246 emit_operand(src, dst); 8247 } 8248 8249 void Assembler::addq(Register dst, int32_t imm32) { 8250 (void) prefixq_and_encode(dst->encoding()); 8251 emit_arith(0x81, 0xC0, dst, imm32); 8252 } 8253 8254 void Assembler::addq(Register dst, Address src) { 8255 InstructionMark im(this); 8256 prefixq(src, dst); 8257 emit_int8(0x03); 8258 emit_operand(dst, src); 8259 } 8260 8261 void Assembler::addq(Register dst, Register src) { 8262 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 8263 emit_arith(0x03, 0xC0, dst, src); 8264 } 8265 8266 void Assembler::adcxq(Register dst, Register src) { 8267 //assert(VM_Version::supports_adx(), "adx instructions not supported"); 8268 emit_int8((unsigned char)0x66); 8269 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 8270 emit_int8(0x0F); 8271 emit_int8(0x38); 8272 emit_int8((unsigned char)0xF6); 8273 emit_int8((unsigned char)(0xC0 | encode)); 8274 } 8275 8276 void Assembler::adoxq(Register dst, Register src) { 8277 //assert(VM_Version::supports_adx(), "adx instructions not supported"); 8278 emit_int8((unsigned char)0xF3); 8279 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 8280 emit_int8(0x0F); 8281 emit_int8(0x38); 8282 emit_int8((unsigned char)0xF6); 8283 emit_int8((unsigned char)(0xC0 | encode)); 8284 } 8285 8286 void Assembler::andq(Address dst, int32_t imm32) { 8287 InstructionMark im(this); 8288 prefixq(dst); 8289 emit_int8((unsigned char)0x81); 8290 emit_operand(rsp, dst, 4); 8291 emit_int32(imm32); 8292 } 8293 8294 void Assembler::andq(Register dst, int32_t imm32) { 8295 (void) prefixq_and_encode(dst->encoding()); 8296 emit_arith(0x81, 0xE0, dst, imm32); 8297 } 8298 8299 void Assembler::andq(Register dst, Address src) { 8300 InstructionMark im(this); 8301 prefixq(src, dst); 8302 emit_int8(0x23); 8303 emit_operand(dst, src); 8304 } 8305 8306 void Assembler::andq(Register dst, Register src) { 8307 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 8308 emit_arith(0x23, 0xC0, dst, src); 8309 } 8310 8311 void Assembler::andnq(Register dst, Register src1, Register src2) { 8312 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 8313 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 8314 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 8315 emit_int8((unsigned char)0xF2); 8316 emit_int8((unsigned char)(0xC0 | encode)); 8317 } 8318 8319 void Assembler::andnq(Register dst, Register src1, Address src2) { 8320 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 8321 InstructionMark im(this); 8322 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 8323 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 8324 emit_int8((unsigned char)0xF2); 8325 emit_operand(dst, src2); 8326 } 8327 8328 void Assembler::bsfq(Register dst, Register src) { 8329 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 8330 emit_int8(0x0F); 8331 emit_int8((unsigned char)0xBC); 8332 emit_int8((unsigned char)(0xC0 | encode)); 8333 } 8334 8335 void Assembler::bsrq(Register dst, Register src) { 8336 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 8337 emit_int8(0x0F); 8338 emit_int8((unsigned char)0xBD); 8339 emit_int8((unsigned char)(0xC0 | encode)); 8340 } 8341 8342 void Assembler::bswapq(Register reg) { 8343 int encode = prefixq_and_encode(reg->encoding()); 8344 emit_int8(0x0F); 8345 emit_int8((unsigned char)(0xC8 | encode)); 8346 } 8347 8348 void Assembler::blsiq(Register dst, Register src) { 8349 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 8350 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 8351 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 8352 emit_int8((unsigned char)0xF3); 8353 emit_int8((unsigned char)(0xC0 | encode)); 8354 } 8355 8356 void Assembler::blsiq(Register dst, Address src) { 8357 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 8358 InstructionMark im(this); 8359 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 8360 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 8361 emit_int8((unsigned char)0xF3); 8362 emit_operand(rbx, src); 8363 } 8364 8365 void Assembler::blsmskq(Register dst, Register src) { 8366 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 8367 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 8368 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 8369 emit_int8((unsigned char)0xF3); 8370 emit_int8((unsigned char)(0xC0 | encode)); 8371 } 8372 8373 void Assembler::blsmskq(Register dst, Address src) { 8374 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 8375 InstructionMark im(this); 8376 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 8377 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 8378 emit_int8((unsigned char)0xF3); 8379 emit_operand(rdx, src); 8380 } 8381 8382 void Assembler::blsrq(Register dst, Register src) { 8383 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 8384 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 8385 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 8386 emit_int8((unsigned char)0xF3); 8387 emit_int8((unsigned char)(0xC0 | encode)); 8388 } 8389 8390 void Assembler::blsrq(Register dst, Address src) { 8391 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 8392 InstructionMark im(this); 8393 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 8394 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 8395 emit_int8((unsigned char)0xF3); 8396 emit_operand(rcx, src); 8397 } 8398 8399 void Assembler::cdqq() { 8400 prefix(REX_W); 8401 emit_int8((unsigned char)0x99); 8402 } 8403 8404 void Assembler::clflush(Address adr) { 8405 prefix(adr); 8406 emit_int8(0x0F); 8407 emit_int8((unsigned char)0xAE); 8408 emit_operand(rdi, adr); 8409 } 8410 8411 void Assembler::cmovq(Condition cc, Register dst, Register src) { 8412 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 8413 emit_int8(0x0F); 8414 emit_int8(0x40 | cc); 8415 emit_int8((unsigned char)(0xC0 | encode)); 8416 } 8417 8418 void Assembler::cmovq(Condition cc, Register dst, Address src) { 8419 InstructionMark im(this); 8420 prefixq(src, dst); 8421 emit_int8(0x0F); 8422 emit_int8(0x40 | cc); 8423 emit_operand(dst, src); 8424 } 8425 8426 void Assembler::cmpq(Address dst, int32_t imm32) { 8427 InstructionMark im(this); 8428 prefixq(dst); 8429 emit_int8((unsigned char)0x81); 8430 emit_operand(rdi, dst, 4); 8431 emit_int32(imm32); 8432 } 8433 8434 void Assembler::cmpq(Register dst, int32_t imm32) { 8435 (void) prefixq_and_encode(dst->encoding()); 8436 emit_arith(0x81, 0xF8, dst, imm32); 8437 } 8438 8439 void Assembler::cmpq(Address dst, Register src) { 8440 InstructionMark im(this); 8441 prefixq(dst, src); 8442 emit_int8(0x3B); 8443 emit_operand(src, dst); 8444 } 8445 8446 void Assembler::cmpq(Register dst, Register src) { 8447 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 8448 emit_arith(0x3B, 0xC0, dst, src); 8449 } 8450 8451 void Assembler::cmpq(Register dst, Address src) { 8452 InstructionMark im(this); 8453 prefixq(src, dst); 8454 emit_int8(0x3B); 8455 emit_operand(dst, src); 8456 } 8457 8458 void Assembler::cmpxchgq(Register reg, Address adr) { 8459 InstructionMark im(this); 8460 prefixq(adr, reg); 8461 emit_int8(0x0F); 8462 emit_int8((unsigned char)0xB1); 8463 emit_operand(reg, adr); 8464 } 8465 8466 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) { 8467 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 8468 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 8469 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 8470 emit_int8(0x2A); 8471 emit_int8((unsigned char)(0xC0 | encode)); 8472 } 8473 8474 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) { 8475 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 8476 InstructionMark im(this); 8477 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 8478 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 8479 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 8480 emit_int8(0x2A); 8481 emit_operand(dst, src); 8482 } 8483 8484 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) { 8485 NOT_LP64(assert(VM_Version::supports_sse(), "")); 8486 InstructionMark im(this); 8487 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 8488 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 8489 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 8490 emit_int8(0x2A); 8491 emit_operand(dst, src); 8492 } 8493 8494 void Assembler::cvttsd2siq(Register dst, XMMRegister src) { 8495 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 8496 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 8497 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 8498 emit_int8(0x2C); 8499 emit_int8((unsigned char)(0xC0 | encode)); 8500 } 8501 8502 void Assembler::cvttss2siq(Register dst, XMMRegister src) { 8503 NOT_LP64(assert(VM_Version::supports_sse(), "")); 8504 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 8505 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 8506 emit_int8(0x2C); 8507 emit_int8((unsigned char)(0xC0 | encode)); 8508 } 8509 8510 void Assembler::decl(Register dst) { 8511 // Don't use it directly. Use MacroAssembler::decrementl() instead. 8512 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode) 8513 int encode = prefix_and_encode(dst->encoding()); 8514 emit_int8((unsigned char)0xFF); 8515 emit_int8((unsigned char)(0xC8 | encode)); 8516 } 8517 8518 void Assembler::decq(Register dst) { 8519 // Don't use it directly. Use MacroAssembler::decrementq() instead. 8520 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) 8521 int encode = prefixq_and_encode(dst->encoding()); 8522 emit_int8((unsigned char)0xFF); 8523 emit_int8(0xC8 | encode); 8524 } 8525 8526 void Assembler::decq(Address dst) { 8527 // Don't use it directly. Use MacroAssembler::decrementq() instead. 8528 InstructionMark im(this); 8529 prefixq(dst); 8530 emit_int8((unsigned char)0xFF); 8531 emit_operand(rcx, dst); 8532 } 8533 8534 void Assembler::fxrstor(Address src) { 8535 prefixq(src); 8536 emit_int8(0x0F); 8537 emit_int8((unsigned char)0xAE); 8538 emit_operand(as_Register(1), src); 8539 } 8540 8541 void Assembler::xrstor(Address src) { 8542 prefixq(src); 8543 emit_int8(0x0F); 8544 emit_int8((unsigned char)0xAE); 8545 emit_operand(as_Register(5), src); 8546 } 8547 8548 void Assembler::fxsave(Address dst) { 8549 prefixq(dst); 8550 emit_int8(0x0F); 8551 emit_int8((unsigned char)0xAE); 8552 emit_operand(as_Register(0), dst); 8553 } 8554 8555 void Assembler::xsave(Address dst) { 8556 prefixq(dst); 8557 emit_int8(0x0F); 8558 emit_int8((unsigned char)0xAE); 8559 emit_operand(as_Register(4), dst); 8560 } 8561 8562 void Assembler::idivq(Register src) { 8563 int encode = prefixq_and_encode(src->encoding()); 8564 emit_int8((unsigned char)0xF7); 8565 emit_int8((unsigned char)(0xF8 | encode)); 8566 } 8567 8568 void Assembler::imulq(Register dst, Register src) { 8569 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 8570 emit_int8(0x0F); 8571 emit_int8((unsigned char)0xAF); 8572 emit_int8((unsigned char)(0xC0 | encode)); 8573 } 8574 8575 void Assembler::imulq(Register dst, Register src, int value) { 8576 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 8577 if (is8bit(value)) { 8578 emit_int8(0x6B); 8579 emit_int8((unsigned char)(0xC0 | encode)); 8580 emit_int8(value & 0xFF); 8581 } else { 8582 emit_int8(0x69); 8583 emit_int8((unsigned char)(0xC0 | encode)); 8584 emit_int32(value); 8585 } 8586 } 8587 8588 void Assembler::imulq(Register dst, Address src) { 8589 InstructionMark im(this); 8590 prefixq(src, dst); 8591 emit_int8(0x0F); 8592 emit_int8((unsigned char) 0xAF); 8593 emit_operand(dst, src); 8594 } 8595 8596 void Assembler::incl(Register dst) { 8597 // Don't use it directly. Use MacroAssembler::incrementl() instead. 8598 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) 8599 int encode = prefix_and_encode(dst->encoding()); 8600 emit_int8((unsigned char)0xFF); 8601 emit_int8((unsigned char)(0xC0 | encode)); 8602 } 8603 8604 void Assembler::incq(Register dst) { 8605 // Don't use it directly. Use MacroAssembler::incrementq() instead. 8606 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) 8607 int encode = prefixq_and_encode(dst->encoding()); 8608 emit_int8((unsigned char)0xFF); 8609 emit_int8((unsigned char)(0xC0 | encode)); 8610 } 8611 8612 void Assembler::incq(Address dst) { 8613 // Don't use it directly. Use MacroAssembler::incrementq() instead. 8614 InstructionMark im(this); 8615 prefixq(dst); 8616 emit_int8((unsigned char)0xFF); 8617 emit_operand(rax, dst); 8618 } 8619 8620 void Assembler::lea(Register dst, Address src) { 8621 leaq(dst, src); 8622 } 8623 8624 void Assembler::leaq(Register dst, Address src) { 8625 InstructionMark im(this); 8626 prefixq(src, dst); 8627 emit_int8((unsigned char)0x8D); 8628 emit_operand(dst, src); 8629 } 8630 8631 void Assembler::mov64(Register dst, int64_t imm64) { 8632 InstructionMark im(this); 8633 int encode = prefixq_and_encode(dst->encoding()); 8634 emit_int8((unsigned char)(0xB8 | encode)); 8635 emit_int64(imm64); 8636 } 8637 8638 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) { 8639 InstructionMark im(this); 8640 int encode = prefixq_and_encode(dst->encoding()); 8641 emit_int8(0xB8 | encode); 8642 emit_data64(imm64, rspec); 8643 } 8644 8645 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) { 8646 InstructionMark im(this); 8647 int encode = prefix_and_encode(dst->encoding()); 8648 emit_int8((unsigned char)(0xB8 | encode)); 8649 emit_data((int)imm32, rspec, narrow_oop_operand); 8650 } 8651 8652 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) { 8653 InstructionMark im(this); 8654 prefix(dst); 8655 emit_int8((unsigned char)0xC7); 8656 emit_operand(rax, dst, 4); 8657 emit_data((int)imm32, rspec, narrow_oop_operand); 8658 } 8659 8660 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) { 8661 InstructionMark im(this); 8662 int encode = prefix_and_encode(src1->encoding()); 8663 emit_int8((unsigned char)0x81); 8664 emit_int8((unsigned char)(0xF8 | encode)); 8665 emit_data((int)imm32, rspec, narrow_oop_operand); 8666 } 8667 8668 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) { 8669 InstructionMark im(this); 8670 prefix(src1); 8671 emit_int8((unsigned char)0x81); 8672 emit_operand(rax, src1, 4); 8673 emit_data((int)imm32, rspec, narrow_oop_operand); 8674 } 8675 8676 void Assembler::lzcntq(Register dst, Register src) { 8677 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR"); 8678 emit_int8((unsigned char)0xF3); 8679 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 8680 emit_int8(0x0F); 8681 emit_int8((unsigned char)0xBD); 8682 emit_int8((unsigned char)(0xC0 | encode)); 8683 } 8684 8685 void Assembler::movdq(XMMRegister dst, Register src) { 8686 // table D-1 says MMX/SSE2 8687 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 8688 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 8689 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 8690 emit_int8(0x6E); 8691 emit_int8((unsigned char)(0xC0 | encode)); 8692 } 8693 8694 void Assembler::movdq(Register dst, XMMRegister src) { 8695 // table D-1 says MMX/SSE2 8696 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 8697 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 8698 // swap src/dst to get correct prefix 8699 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 8700 emit_int8(0x7E); 8701 emit_int8((unsigned char)(0xC0 | encode)); 8702 } 8703 8704 void Assembler::movq(Register dst, Register src) { 8705 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 8706 emit_int8((unsigned char)0x8B); 8707 emit_int8((unsigned char)(0xC0 | encode)); 8708 } 8709 8710 void Assembler::movq(Register dst, Address src) { 8711 InstructionMark im(this); 8712 prefixq(src, dst); 8713 emit_int8((unsigned char)0x8B); 8714 emit_operand(dst, src); 8715 } 8716 8717 void Assembler::movq(Address dst, Register src) { 8718 InstructionMark im(this); 8719 prefixq(dst, src); 8720 emit_int8((unsigned char)0x89); 8721 emit_operand(src, dst); 8722 } 8723 8724 void Assembler::movsbq(Register dst, Address src) { 8725 InstructionMark im(this); 8726 prefixq(src, dst); 8727 emit_int8(0x0F); 8728 emit_int8((unsigned char)0xBE); 8729 emit_operand(dst, src); 8730 } 8731 8732 void Assembler::movsbq(Register dst, Register src) { 8733 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 8734 emit_int8(0x0F); 8735 emit_int8((unsigned char)0xBE); 8736 emit_int8((unsigned char)(0xC0 | encode)); 8737 } 8738 8739 void Assembler::movslq(Register dst, int32_t imm32) { 8740 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx) 8741 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx) 8742 // as a result we shouldn't use until tested at runtime... 8743 ShouldNotReachHere(); 8744 InstructionMark im(this); 8745 int encode = prefixq_and_encode(dst->encoding()); 8746 emit_int8((unsigned char)(0xC7 | encode)); 8747 emit_int32(imm32); 8748 } 8749 8750 void Assembler::movslq(Address dst, int32_t imm32) { 8751 assert(is_simm32(imm32), "lost bits"); 8752 InstructionMark im(this); 8753 prefixq(dst); 8754 emit_int8((unsigned char)0xC7); 8755 emit_operand(rax, dst, 4); 8756 emit_int32(imm32); 8757 } 8758 8759 void Assembler::movslq(Register dst, Address src) { 8760 InstructionMark im(this); 8761 prefixq(src, dst); 8762 emit_int8(0x63); 8763 emit_operand(dst, src); 8764 } 8765 8766 void Assembler::movslq(Register dst, Register src) { 8767 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 8768 emit_int8(0x63); 8769 emit_int8((unsigned char)(0xC0 | encode)); 8770 } 8771 8772 void Assembler::movswq(Register dst, Address src) { 8773 InstructionMark im(this); 8774 prefixq(src, dst); 8775 emit_int8(0x0F); 8776 emit_int8((unsigned char)0xBF); 8777 emit_operand(dst, src); 8778 } 8779 8780 void Assembler::movswq(Register dst, Register src) { 8781 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 8782 emit_int8((unsigned char)0x0F); 8783 emit_int8((unsigned char)0xBF); 8784 emit_int8((unsigned char)(0xC0 | encode)); 8785 } 8786 8787 void Assembler::movzbq(Register dst, Address src) { 8788 InstructionMark im(this); 8789 prefixq(src, dst); 8790 emit_int8((unsigned char)0x0F); 8791 emit_int8((unsigned char)0xB6); 8792 emit_operand(dst, src); 8793 } 8794 8795 void Assembler::movzbq(Register dst, Register src) { 8796 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 8797 emit_int8(0x0F); 8798 emit_int8((unsigned char)0xB6); 8799 emit_int8(0xC0 | encode); 8800 } 8801 8802 void Assembler::movzwq(Register dst, Address src) { 8803 InstructionMark im(this); 8804 prefixq(src, dst); 8805 emit_int8((unsigned char)0x0F); 8806 emit_int8((unsigned char)0xB7); 8807 emit_operand(dst, src); 8808 } 8809 8810 void Assembler::movzwq(Register dst, Register src) { 8811 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 8812 emit_int8((unsigned char)0x0F); 8813 emit_int8((unsigned char)0xB7); 8814 emit_int8((unsigned char)(0xC0 | encode)); 8815 } 8816 8817 void Assembler::mulq(Address src) { 8818 InstructionMark im(this); 8819 prefixq(src); 8820 emit_int8((unsigned char)0xF7); 8821 emit_operand(rsp, src); 8822 } 8823 8824 void Assembler::mulq(Register src) { 8825 int encode = prefixq_and_encode(src->encoding()); 8826 emit_int8((unsigned char)0xF7); 8827 emit_int8((unsigned char)(0xE0 | encode)); 8828 } 8829 8830 void Assembler::mulxq(Register dst1, Register dst2, Register src) { 8831 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported"); 8832 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 8833 int encode = vex_prefix_and_encode(dst1->encoding(), dst2->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes); 8834 emit_int8((unsigned char)0xF6); 8835 emit_int8((unsigned char)(0xC0 | encode)); 8836 } 8837 8838 void Assembler::negq(Register dst) { 8839 int encode = prefixq_and_encode(dst->encoding()); 8840 emit_int8((unsigned char)0xF7); 8841 emit_int8((unsigned char)(0xD8 | encode)); 8842 } 8843 8844 void Assembler::notq(Register dst) { 8845 int encode = prefixq_and_encode(dst->encoding()); 8846 emit_int8((unsigned char)0xF7); 8847 emit_int8((unsigned char)(0xD0 | encode)); 8848 } 8849 8850 void Assembler::orq(Address dst, int32_t imm32) { 8851 InstructionMark im(this); 8852 prefixq(dst); 8853 emit_int8((unsigned char)0x81); 8854 emit_operand(rcx, dst, 4); 8855 emit_int32(imm32); 8856 } 8857 8858 void Assembler::orq(Register dst, int32_t imm32) { 8859 (void) prefixq_and_encode(dst->encoding()); 8860 emit_arith(0x81, 0xC8, dst, imm32); 8861 } 8862 8863 void Assembler::orq(Register dst, Address src) { 8864 InstructionMark im(this); 8865 prefixq(src, dst); 8866 emit_int8(0x0B); 8867 emit_operand(dst, src); 8868 } 8869 8870 void Assembler::orq(Register dst, Register src) { 8871 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 8872 emit_arith(0x0B, 0xC0, dst, src); 8873 } 8874 8875 void Assembler::popa() { // 64bit 8876 movq(r15, Address(rsp, 0)); 8877 movq(r14, Address(rsp, wordSize)); 8878 movq(r13, Address(rsp, 2 * wordSize)); 8879 movq(r12, Address(rsp, 3 * wordSize)); 8880 movq(r11, Address(rsp, 4 * wordSize)); 8881 movq(r10, Address(rsp, 5 * wordSize)); 8882 movq(r9, Address(rsp, 6 * wordSize)); 8883 movq(r8, Address(rsp, 7 * wordSize)); 8884 movq(rdi, Address(rsp, 8 * wordSize)); 8885 movq(rsi, Address(rsp, 9 * wordSize)); 8886 movq(rbp, Address(rsp, 10 * wordSize)); 8887 // skip rsp 8888 movq(rbx, Address(rsp, 12 * wordSize)); 8889 movq(rdx, Address(rsp, 13 * wordSize)); 8890 movq(rcx, Address(rsp, 14 * wordSize)); 8891 movq(rax, Address(rsp, 15 * wordSize)); 8892 8893 addq(rsp, 16 * wordSize); 8894 } 8895 8896 void Assembler::popcntq(Register dst, Address src) { 8897 assert(VM_Version::supports_popcnt(), "must support"); 8898 InstructionMark im(this); 8899 emit_int8((unsigned char)0xF3); 8900 prefixq(src, dst); 8901 emit_int8((unsigned char)0x0F); 8902 emit_int8((unsigned char)0xB8); 8903 emit_operand(dst, src); 8904 } 8905 8906 void Assembler::popcntq(Register dst, Register src) { 8907 assert(VM_Version::supports_popcnt(), "must support"); 8908 emit_int8((unsigned char)0xF3); 8909 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 8910 emit_int8((unsigned char)0x0F); 8911 emit_int8((unsigned char)0xB8); 8912 emit_int8((unsigned char)(0xC0 | encode)); 8913 } 8914 8915 void Assembler::popq(Address dst) { 8916 InstructionMark im(this); 8917 prefixq(dst); 8918 emit_int8((unsigned char)0x8F); 8919 emit_operand(rax, dst); 8920 } 8921 8922 void Assembler::pusha() { // 64bit 8923 // we have to store original rsp. ABI says that 128 bytes 8924 // below rsp are local scratch. 8925 movq(Address(rsp, -5 * wordSize), rsp); 8926 8927 subq(rsp, 16 * wordSize); 8928 8929 movq(Address(rsp, 15 * wordSize), rax); 8930 movq(Address(rsp, 14 * wordSize), rcx); 8931 movq(Address(rsp, 13 * wordSize), rdx); 8932 movq(Address(rsp, 12 * wordSize), rbx); 8933 // skip rsp 8934 movq(Address(rsp, 10 * wordSize), rbp); 8935 movq(Address(rsp, 9 * wordSize), rsi); 8936 movq(Address(rsp, 8 * wordSize), rdi); 8937 movq(Address(rsp, 7 * wordSize), r8); 8938 movq(Address(rsp, 6 * wordSize), r9); 8939 movq(Address(rsp, 5 * wordSize), r10); 8940 movq(Address(rsp, 4 * wordSize), r11); 8941 movq(Address(rsp, 3 * wordSize), r12); 8942 movq(Address(rsp, 2 * wordSize), r13); 8943 movq(Address(rsp, wordSize), r14); 8944 movq(Address(rsp, 0), r15); 8945 } 8946 8947 void Assembler::pushq(Address src) { 8948 InstructionMark im(this); 8949 prefixq(src); 8950 emit_int8((unsigned char)0xFF); 8951 emit_operand(rsi, src); 8952 } 8953 8954 void Assembler::rclq(Register dst, int imm8) { 8955 assert(isShiftCount(imm8 >> 1), "illegal shift count"); 8956 int encode = prefixq_and_encode(dst->encoding()); 8957 if (imm8 == 1) { 8958 emit_int8((unsigned char)0xD1); 8959 emit_int8((unsigned char)(0xD0 | encode)); 8960 } else { 8961 emit_int8((unsigned char)0xC1); 8962 emit_int8((unsigned char)(0xD0 | encode)); 8963 emit_int8(imm8); 8964 } 8965 } 8966 8967 void Assembler::rcrq(Register dst, int imm8) { 8968 assert(isShiftCount(imm8 >> 1), "illegal shift count"); 8969 int encode = prefixq_and_encode(dst->encoding()); 8970 if (imm8 == 1) { 8971 emit_int8((unsigned char)0xD1); 8972 emit_int8((unsigned char)(0xD8 | encode)); 8973 } else { 8974 emit_int8((unsigned char)0xC1); 8975 emit_int8((unsigned char)(0xD8 | encode)); 8976 emit_int8(imm8); 8977 } 8978 } 8979 8980 void Assembler::rorq(Register dst, int imm8) { 8981 assert(isShiftCount(imm8 >> 1), "illegal shift count"); 8982 int encode = prefixq_and_encode(dst->encoding()); 8983 if (imm8 == 1) { 8984 emit_int8((unsigned char)0xD1); 8985 emit_int8((unsigned char)(0xC8 | encode)); 8986 } else { 8987 emit_int8((unsigned char)0xC1); 8988 emit_int8((unsigned char)(0xc8 | encode)); 8989 emit_int8(imm8); 8990 } 8991 } 8992 8993 void Assembler::rorxq(Register dst, Register src, int imm8) { 8994 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported"); 8995 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 8996 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes); 8997 emit_int8((unsigned char)0xF0); 8998 emit_int8((unsigned char)(0xC0 | encode)); 8999 emit_int8(imm8); 9000 } 9001 9002 void Assembler::rorxd(Register dst, Register src, int imm8) { 9003 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported"); 9004 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 9005 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes); 9006 emit_int8((unsigned char)0xF0); 9007 emit_int8((unsigned char)(0xC0 | encode)); 9008 emit_int8(imm8); 9009 } 9010 9011 void Assembler::sarq(Register dst, int imm8) { 9012 assert(isShiftCount(imm8 >> 1), "illegal shift count"); 9013 int encode = prefixq_and_encode(dst->encoding()); 9014 if (imm8 == 1) { 9015 emit_int8((unsigned char)0xD1); 9016 emit_int8((unsigned char)(0xF8 | encode)); 9017 } else { 9018 emit_int8((unsigned char)0xC1); 9019 emit_int8((unsigned char)(0xF8 | encode)); 9020 emit_int8(imm8); 9021 } 9022 } 9023 9024 void Assembler::sarq(Register dst) { 9025 int encode = prefixq_and_encode(dst->encoding()); 9026 emit_int8((unsigned char)0xD3); 9027 emit_int8((unsigned char)(0xF8 | encode)); 9028 } 9029 9030 void Assembler::sbbq(Address dst, int32_t imm32) { 9031 InstructionMark im(this); 9032 prefixq(dst); 9033 emit_arith_operand(0x81, rbx, dst, imm32); 9034 } 9035 9036 void Assembler::sbbq(Register dst, int32_t imm32) { 9037 (void) prefixq_and_encode(dst->encoding()); 9038 emit_arith(0x81, 0xD8, dst, imm32); 9039 } 9040 9041 void Assembler::sbbq(Register dst, Address src) { 9042 InstructionMark im(this); 9043 prefixq(src, dst); 9044 emit_int8(0x1B); 9045 emit_operand(dst, src); 9046 } 9047 9048 void Assembler::sbbq(Register dst, Register src) { 9049 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 9050 emit_arith(0x1B, 0xC0, dst, src); 9051 } 9052 9053 void Assembler::shlq(Register dst, int imm8) { 9054 assert(isShiftCount(imm8 >> 1), "illegal shift count"); 9055 int encode = prefixq_and_encode(dst->encoding()); 9056 if (imm8 == 1) { 9057 emit_int8((unsigned char)0xD1); 9058 emit_int8((unsigned char)(0xE0 | encode)); 9059 } else { 9060 emit_int8((unsigned char)0xC1); 9061 emit_int8((unsigned char)(0xE0 | encode)); 9062 emit_int8(imm8); 9063 } 9064 } 9065 9066 void Assembler::shlq(Register dst) { 9067 int encode = prefixq_and_encode(dst->encoding()); 9068 emit_int8((unsigned char)0xD3); 9069 emit_int8((unsigned char)(0xE0 | encode)); 9070 } 9071 9072 void Assembler::shrq(Register dst, int imm8) { 9073 assert(isShiftCount(imm8 >> 1), "illegal shift count"); 9074 int encode = prefixq_and_encode(dst->encoding()); 9075 emit_int8((unsigned char)0xC1); 9076 emit_int8((unsigned char)(0xE8 | encode)); 9077 emit_int8(imm8); 9078 } 9079 9080 void Assembler::shrq(Register dst) { 9081 int encode = prefixq_and_encode(dst->encoding()); 9082 emit_int8((unsigned char)0xD3); 9083 emit_int8(0xE8 | encode); 9084 } 9085 9086 void Assembler::subq(Address dst, int32_t imm32) { 9087 InstructionMark im(this); 9088 prefixq(dst); 9089 emit_arith_operand(0x81, rbp, dst, imm32); 9090 } 9091 9092 void Assembler::subq(Address dst, Register src) { 9093 InstructionMark im(this); 9094 prefixq(dst, src); 9095 emit_int8(0x29); 9096 emit_operand(src, dst); 9097 } 9098 9099 void Assembler::subq(Register dst, int32_t imm32) { 9100 (void) prefixq_and_encode(dst->encoding()); 9101 emit_arith(0x81, 0xE8, dst, imm32); 9102 } 9103 9104 // Force generation of a 4 byte immediate value even if it fits into 8bit 9105 void Assembler::subq_imm32(Register dst, int32_t imm32) { 9106 (void) prefixq_and_encode(dst->encoding()); 9107 emit_arith_imm32(0x81, 0xE8, dst, imm32); 9108 } 9109 9110 void Assembler::subq(Register dst, Address src) { 9111 InstructionMark im(this); 9112 prefixq(src, dst); 9113 emit_int8(0x2B); 9114 emit_operand(dst, src); 9115 } 9116 9117 void Assembler::subq(Register dst, Register src) { 9118 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 9119 emit_arith(0x2B, 0xC0, dst, src); 9120 } 9121 9122 void Assembler::testq(Register dst, int32_t imm32) { 9123 // not using emit_arith because test 9124 // doesn't support sign-extension of 9125 // 8bit operands 9126 int encode = dst->encoding(); 9127 if (encode == 0) { 9128 prefix(REX_W); 9129 emit_int8((unsigned char)0xA9); 9130 } else { 9131 encode = prefixq_and_encode(encode); 9132 emit_int8((unsigned char)0xF7); 9133 emit_int8((unsigned char)(0xC0 | encode)); 9134 } 9135 emit_int32(imm32); 9136 } 9137 9138 void Assembler::testq(Register dst, Register src) { 9139 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 9140 emit_arith(0x85, 0xC0, dst, src); 9141 } 9142 9143 void Assembler::testq(Register dst, Address src) { 9144 InstructionMark im(this); 9145 prefixq(src, dst); 9146 emit_int8((unsigned char)0x85); 9147 emit_operand(dst, src); 9148 } 9149 9150 void Assembler::xaddq(Address dst, Register src) { 9151 InstructionMark im(this); 9152 prefixq(dst, src); 9153 emit_int8(0x0F); 9154 emit_int8((unsigned char)0xC1); 9155 emit_operand(src, dst); 9156 } 9157 9158 void Assembler::xchgq(Register dst, Address src) { 9159 InstructionMark im(this); 9160 prefixq(src, dst); 9161 emit_int8((unsigned char)0x87); 9162 emit_operand(dst, src); 9163 } 9164 9165 void Assembler::xchgq(Register dst, Register src) { 9166 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 9167 emit_int8((unsigned char)0x87); 9168 emit_int8((unsigned char)(0xc0 | encode)); 9169 } 9170 9171 void Assembler::xorq(Register dst, Register src) { 9172 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 9173 emit_arith(0x33, 0xC0, dst, src); 9174 } 9175 9176 void Assembler::xorq(Register dst, Address src) { 9177 InstructionMark im(this); 9178 prefixq(src, dst); 9179 emit_int8(0x33); 9180 emit_operand(dst, src); 9181 } 9182 9183 #endif // !LP64