1 /*
2 * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "jvm.h"
27 #include "asm/assembler.hpp"
28 #include "asm/assembler.inline.hpp"
29 #include "compiler/disassembler.hpp"
30 #include "gc/shared/barrierSet.hpp"
31 #include "gc/shared/barrierSetAssembler.hpp"
32 #include "gc/shared/collectedHeap.inline.hpp"
33 #include "interpreter/interpreter.hpp"
34 #include "memory/resourceArea.hpp"
35 #include "memory/universe.hpp"
36 #include "oops/accessDecorators.hpp"
37 #include "oops/klass.inline.hpp"
38 #include "prims/methodHandles.hpp"
39 #include "runtime/biasedLocking.hpp"
40 #include "runtime/flags/flagSetting.hpp"
41 #include "runtime/interfaceSupport.inline.hpp"
42 #include "runtime/objectMonitor.hpp"
43 #include "runtime/os.hpp"
44 #include "runtime/safepoint.hpp"
45 #include "runtime/safepointMechanism.hpp"
46 #include "runtime/sharedRuntime.hpp"
47 #include "runtime/stubRoutines.hpp"
48 #include "runtime/thread.hpp"
49 #include "utilities/macros.hpp"
50 #include "crc32c.h"
51 #ifdef COMPILER2
52 #include "opto/intrinsicnode.hpp"
53 #endif
54
55 #ifdef PRODUCT
56 #define BLOCK_COMMENT(str) /* nothing */
57 #define STOP(error) stop(error)
58 #else
59 #define BLOCK_COMMENT(str) block_comment(str)
60 #define STOP(error) block_comment(error); stop(error)
61 #endif
62
63 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
64
65 #ifdef ASSERT
66 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
67 #endif
68
69 static Assembler::Condition reverse[] = {
70 Assembler::noOverflow /* overflow = 0x0 */ ,
71 Assembler::overflow /* noOverflow = 0x1 */ ,
72 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
73 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
74 Assembler::notZero /* zero = 0x4, equal = 0x4 */ ,
75 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ ,
76 Assembler::above /* belowEqual = 0x6 */ ,
77 Assembler::belowEqual /* above = 0x7 */ ,
78 Assembler::positive /* negative = 0x8 */ ,
79 Assembler::negative /* positive = 0x9 */ ,
80 Assembler::noParity /* parity = 0xa */ ,
81 Assembler::parity /* noParity = 0xb */ ,
82 Assembler::greaterEqual /* less = 0xc */ ,
83 Assembler::less /* greaterEqual = 0xd */ ,
84 Assembler::greater /* lessEqual = 0xe */ ,
85 Assembler::lessEqual /* greater = 0xf, */
86
87 };
88
89
90 // Implementation of MacroAssembler
91
92 // First all the versions that have distinct versions depending on 32/64 bit
93 // Unless the difference is trivial (1 line or so).
94
95 #ifndef _LP64
96
97 // 32bit versions
98
99 Address MacroAssembler::as_Address(AddressLiteral adr) {
100 return Address(adr.target(), adr.rspec());
101 }
102
103 Address MacroAssembler::as_Address(ArrayAddress adr) {
104 return Address::make_array(adr);
105 }
106
107 void MacroAssembler::call_VM_leaf_base(address entry_point,
108 int number_of_arguments) {
109 call(RuntimeAddress(entry_point));
110 increment(rsp, number_of_arguments * wordSize);
111 }
112
113 void MacroAssembler::cmpklass(Address src1, Metadata* obj) {
114 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
115 }
116
117 void MacroAssembler::cmpklass(Register src1, Metadata* obj) {
118 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
119 }
120
121 void MacroAssembler::cmpoop_raw(Address src1, jobject obj) {
122 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
123 }
124
125 void MacroAssembler::cmpoop_raw(Register src1, jobject obj) {
126 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
127 }
128
129 void MacroAssembler::cmpoop(Address src1, jobject obj) {
130 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
131 bs->obj_equals(this, src1, obj);
132 }
133
134 void MacroAssembler::cmpoop(Register src1, jobject obj) {
135 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
136 bs->obj_equals(this, src1, obj);
137 }
138
139 void MacroAssembler::extend_sign(Register hi, Register lo) {
140 // According to Intel Doc. AP-526, "Integer Divide", p.18.
141 if (VM_Version::is_P6() && hi == rdx && lo == rax) {
142 cdql();
143 } else {
144 movl(hi, lo);
145 sarl(hi, 31);
146 }
147 }
148
149 void MacroAssembler::jC2(Register tmp, Label& L) {
150 // set parity bit if FPU flag C2 is set (via rax)
151 save_rax(tmp);
152 fwait(); fnstsw_ax();
153 sahf();
154 restore_rax(tmp);
155 // branch
156 jcc(Assembler::parity, L);
157 }
158
159 void MacroAssembler::jnC2(Register tmp, Label& L) {
160 // set parity bit if FPU flag C2 is set (via rax)
161 save_rax(tmp);
162 fwait(); fnstsw_ax();
163 sahf();
164 restore_rax(tmp);
165 // branch
166 jcc(Assembler::noParity, L);
167 }
168
169 // 32bit can do a case table jump in one instruction but we no longer allow the base
170 // to be installed in the Address class
171 void MacroAssembler::jump(ArrayAddress entry) {
172 jmp(as_Address(entry));
173 }
174
175 // Note: y_lo will be destroyed
176 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
177 // Long compare for Java (semantics as described in JVM spec.)
178 Label high, low, done;
179
180 cmpl(x_hi, y_hi);
181 jcc(Assembler::less, low);
182 jcc(Assembler::greater, high);
183 // x_hi is the return register
184 xorl(x_hi, x_hi);
185 cmpl(x_lo, y_lo);
186 jcc(Assembler::below, low);
187 jcc(Assembler::equal, done);
188
189 bind(high);
190 xorl(x_hi, x_hi);
191 increment(x_hi);
192 jmp(done);
193
194 bind(low);
195 xorl(x_hi, x_hi);
196 decrementl(x_hi);
197
198 bind(done);
199 }
200
201 void MacroAssembler::lea(Register dst, AddressLiteral src) {
202 mov_literal32(dst, (int32_t)src.target(), src.rspec());
203 }
204
205 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
206 // leal(dst, as_Address(adr));
207 // see note in movl as to why we must use a move
208 mov_literal32(dst, (int32_t) adr.target(), adr.rspec());
209 }
210
211 void MacroAssembler::leave() {
212 mov(rsp, rbp);
213 pop(rbp);
214 }
215
216 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
217 // Multiplication of two Java long values stored on the stack
218 // as illustrated below. Result is in rdx:rax.
219 //
220 // rsp ---> [ ?? ] \ \
221 // .... | y_rsp_offset |
222 // [ y_lo ] / (in bytes) | x_rsp_offset
223 // [ y_hi ] | (in bytes)
224 // .... |
225 // [ x_lo ] /
226 // [ x_hi ]
227 // ....
228 //
229 // Basic idea: lo(result) = lo(x_lo * y_lo)
230 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
231 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
232 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
233 Label quick;
234 // load x_hi, y_hi and check if quick
235 // multiplication is possible
236 movl(rbx, x_hi);
237 movl(rcx, y_hi);
238 movl(rax, rbx);
239 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0
240 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply
241 // do full multiplication
242 // 1st step
243 mull(y_lo); // x_hi * y_lo
244 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx,
245 // 2nd step
246 movl(rax, x_lo);
247 mull(rcx); // x_lo * y_hi
248 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx,
249 // 3rd step
250 bind(quick); // note: rbx, = 0 if quick multiply!
251 movl(rax, x_lo);
252 mull(y_lo); // x_lo * y_lo
253 addl(rdx, rbx); // correct hi(x_lo * y_lo)
254 }
255
256 void MacroAssembler::lneg(Register hi, Register lo) {
257 negl(lo);
258 adcl(hi, 0);
259 negl(hi);
260 }
261
262 void MacroAssembler::lshl(Register hi, Register lo) {
263 // Java shift left long support (semantics as described in JVM spec., p.305)
264 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
265 // shift value is in rcx !
266 assert(hi != rcx, "must not use rcx");
267 assert(lo != rcx, "must not use rcx");
268 const Register s = rcx; // shift count
269 const int n = BitsPerWord;
270 Label L;
271 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
272 cmpl(s, n); // if (s < n)
273 jcc(Assembler::less, L); // else (s >= n)
274 movl(hi, lo); // x := x << n
275 xorl(lo, lo);
276 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
277 bind(L); // s (mod n) < n
278 shldl(hi, lo); // x := x << s
279 shll(lo);
280 }
281
282
283 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
284 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
285 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
286 assert(hi != rcx, "must not use rcx");
287 assert(lo != rcx, "must not use rcx");
288 const Register s = rcx; // shift count
289 const int n = BitsPerWord;
290 Label L;
291 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
292 cmpl(s, n); // if (s < n)
293 jcc(Assembler::less, L); // else (s >= n)
294 movl(lo, hi); // x := x >> n
295 if (sign_extension) sarl(hi, 31);
296 else xorl(hi, hi);
297 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
298 bind(L); // s (mod n) < n
299 shrdl(lo, hi); // x := x >> s
300 if (sign_extension) sarl(hi);
301 else shrl(hi);
302 }
303
304 void MacroAssembler::movoop(Register dst, jobject obj) {
305 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
306 }
307
308 void MacroAssembler::movoop(Address dst, jobject obj) {
309 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
310 }
311
312 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
313 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
314 }
315
316 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
317 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
318 }
319
320 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
321 // scratch register is not used,
322 // it is defined to match parameters of 64-bit version of this method.
323 if (src.is_lval()) {
324 mov_literal32(dst, (intptr_t)src.target(), src.rspec());
325 } else {
326 movl(dst, as_Address(src));
327 }
328 }
329
330 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
331 movl(as_Address(dst), src);
332 }
333
334 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
335 movl(dst, as_Address(src));
336 }
337
338 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
339 void MacroAssembler::movptr(Address dst, intptr_t src) {
340 movl(dst, src);
341 }
342
343
344 void MacroAssembler::pop_callee_saved_registers() {
345 pop(rcx);
346 pop(rdx);
347 pop(rdi);
348 pop(rsi);
349 }
350
351 void MacroAssembler::pop_fTOS() {
352 fld_d(Address(rsp, 0));
353 addl(rsp, 2 * wordSize);
354 }
355
356 void MacroAssembler::push_callee_saved_registers() {
357 push(rsi);
358 push(rdi);
359 push(rdx);
360 push(rcx);
361 }
362
363 void MacroAssembler::push_fTOS() {
364 subl(rsp, 2 * wordSize);
365 fstp_d(Address(rsp, 0));
366 }
367
368
369 void MacroAssembler::pushoop(jobject obj) {
370 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
371 }
372
373 void MacroAssembler::pushklass(Metadata* obj) {
374 push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate());
375 }
376
377 void MacroAssembler::pushptr(AddressLiteral src) {
378 if (src.is_lval()) {
379 push_literal32((int32_t)src.target(), src.rspec());
380 } else {
381 pushl(as_Address(src));
382 }
383 }
384
385 void MacroAssembler::set_word_if_not_zero(Register dst) {
386 xorl(dst, dst);
387 set_byte_if_not_zero(dst);
388 }
389
390 static void pass_arg0(MacroAssembler* masm, Register arg) {
391 masm->push(arg);
392 }
393
394 static void pass_arg1(MacroAssembler* masm, Register arg) {
395 masm->push(arg);
396 }
397
398 static void pass_arg2(MacroAssembler* masm, Register arg) {
399 masm->push(arg);
400 }
401
402 static void pass_arg3(MacroAssembler* masm, Register arg) {
403 masm->push(arg);
404 }
405
406 #ifndef PRODUCT
407 extern "C" void findpc(intptr_t x);
408 #endif
409
410 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
411 // In order to get locks to work, we need to fake a in_VM state
412 JavaThread* thread = JavaThread::current();
413 JavaThreadState saved_state = thread->thread_state();
414 thread->set_thread_state(_thread_in_vm);
415 if (ShowMessageBoxOnError) {
416 JavaThread* thread = JavaThread::current();
417 JavaThreadState saved_state = thread->thread_state();
418 thread->set_thread_state(_thread_in_vm);
419 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
420 ttyLocker ttyl;
421 BytecodeCounter::print();
422 }
423 // To see where a verify_oop failed, get $ebx+40/X for this frame.
424 // This is the value of eip which points to where verify_oop will return.
425 if (os::message_box(msg, "Execution stopped, print registers?")) {
426 print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip);
427 BREAKPOINT;
428 }
429 } else {
430 ttyLocker ttyl;
431 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg);
432 }
433 // Don't assert holding the ttyLock
434 assert(false, "DEBUG MESSAGE: %s", msg);
435 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
436 }
437
438 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) {
439 ttyLocker ttyl;
440 FlagSetting fs(Debugging, true);
441 tty->print_cr("eip = 0x%08x", eip);
442 #ifndef PRODUCT
443 if ((WizardMode || Verbose) && PrintMiscellaneous) {
444 tty->cr();
445 findpc(eip);
446 tty->cr();
447 }
448 #endif
449 #define PRINT_REG(rax) \
450 { tty->print("%s = ", #rax); os::print_location(tty, rax); }
451 PRINT_REG(rax);
452 PRINT_REG(rbx);
453 PRINT_REG(rcx);
454 PRINT_REG(rdx);
455 PRINT_REG(rdi);
456 PRINT_REG(rsi);
457 PRINT_REG(rbp);
458 PRINT_REG(rsp);
459 #undef PRINT_REG
460 // Print some words near top of staack.
461 int* dump_sp = (int*) rsp;
462 for (int col1 = 0; col1 < 8; col1++) {
463 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
464 os::print_location(tty, *dump_sp++);
465 }
466 for (int row = 0; row < 16; row++) {
467 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
468 for (int col = 0; col < 8; col++) {
469 tty->print(" 0x%08x", *dump_sp++);
470 }
471 tty->cr();
472 }
473 // Print some instructions around pc:
474 Disassembler::decode((address)eip-64, (address)eip);
475 tty->print_cr("--------");
476 Disassembler::decode((address)eip, (address)eip+32);
477 }
478
479 void MacroAssembler::stop(const char* msg) {
480 ExternalAddress message((address)msg);
481 // push address of message
482 pushptr(message.addr());
483 { Label L; call(L, relocInfo::none); bind(L); } // push eip
484 pusha(); // push registers
485 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
486 hlt();
487 }
488
489 void MacroAssembler::warn(const char* msg) {
490 push_CPU_state();
491
492 ExternalAddress message((address) msg);
493 // push address of message
494 pushptr(message.addr());
495
496 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
497 addl(rsp, wordSize); // discard argument
498 pop_CPU_state();
499 }
500
501 void MacroAssembler::print_state() {
502 { Label L; call(L, relocInfo::none); bind(L); } // push eip
503 pusha(); // push registers
504
505 push_CPU_state();
506 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32)));
507 pop_CPU_state();
508
509 popa();
510 addl(rsp, wordSize);
511 }
512
513 #else // _LP64
514
515 // 64 bit versions
516
517 Address MacroAssembler::as_Address(AddressLiteral adr) {
518 // amd64 always does this as a pc-rel
519 // we can be absolute or disp based on the instruction type
520 // jmp/call are displacements others are absolute
521 assert(!adr.is_lval(), "must be rval");
522 assert(reachable(adr), "must be");
523 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc());
524
525 }
526
527 Address MacroAssembler::as_Address(ArrayAddress adr) {
528 AddressLiteral base = adr.base();
529 lea(rscratch1, base);
530 Address index = adr.index();
531 assert(index._disp == 0, "must not have disp"); // maybe it can?
532 Address array(rscratch1, index._index, index._scale, index._disp);
533 return array;
534 }
535
536 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
537 Label L, E;
538
539 #ifdef _WIN64
540 // Windows always allocates space for it's register args
541 assert(num_args <= 4, "only register arguments supported");
542 subq(rsp, frame::arg_reg_save_area_bytes);
543 #endif
544
545 // Align stack if necessary
546 testl(rsp, 15);
547 jcc(Assembler::zero, L);
548
549 subq(rsp, 8);
550 {
551 call(RuntimeAddress(entry_point));
552 }
553 addq(rsp, 8);
554 jmp(E);
555
556 bind(L);
557 {
558 call(RuntimeAddress(entry_point));
559 }
560
561 bind(E);
562
563 #ifdef _WIN64
564 // restore stack pointer
565 addq(rsp, frame::arg_reg_save_area_bytes);
566 #endif
567
568 }
569
570 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) {
571 assert(!src2.is_lval(), "should use cmpptr");
572
573 if (reachable(src2)) {
574 cmpq(src1, as_Address(src2));
575 } else {
576 lea(rscratch1, src2);
577 Assembler::cmpq(src1, Address(rscratch1, 0));
578 }
579 }
580
581 int MacroAssembler::corrected_idivq(Register reg) {
582 // Full implementation of Java ldiv and lrem; checks for special
583 // case as described in JVM spec., p.243 & p.271. The function
584 // returns the (pc) offset of the idivl instruction - may be needed
585 // for implicit exceptions.
586 //
587 // normal case special case
588 //
589 // input : rax: dividend min_long
590 // reg: divisor (may not be eax/edx) -1
591 //
592 // output: rax: quotient (= rax idiv reg) min_long
593 // rdx: remainder (= rax irem reg) 0
594 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
595 static const int64_t min_long = 0x8000000000000000;
596 Label normal_case, special_case;
597
598 // check for special case
599 cmp64(rax, ExternalAddress((address) &min_long));
600 jcc(Assembler::notEqual, normal_case);
601 xorl(rdx, rdx); // prepare rdx for possible special case (where
602 // remainder = 0)
603 cmpq(reg, -1);
604 jcc(Assembler::equal, special_case);
605
606 // handle normal case
607 bind(normal_case);
608 cdqq();
609 int idivq_offset = offset();
610 idivq(reg);
611
612 // normal and special case exit
613 bind(special_case);
614
615 return idivq_offset;
616 }
617
618 void MacroAssembler::decrementq(Register reg, int value) {
619 if (value == min_jint) { subq(reg, value); return; }
620 if (value < 0) { incrementq(reg, -value); return; }
621 if (value == 0) { ; return; }
622 if (value == 1 && UseIncDec) { decq(reg) ; return; }
623 /* else */ { subq(reg, value) ; return; }
624 }
625
626 void MacroAssembler::decrementq(Address dst, int value) {
627 if (value == min_jint) { subq(dst, value); return; }
628 if (value < 0) { incrementq(dst, -value); return; }
629 if (value == 0) { ; return; }
630 if (value == 1 && UseIncDec) { decq(dst) ; return; }
631 /* else */ { subq(dst, value) ; return; }
632 }
633
634 void MacroAssembler::incrementq(AddressLiteral dst) {
635 if (reachable(dst)) {
636 incrementq(as_Address(dst));
637 } else {
638 lea(rscratch1, dst);
639 incrementq(Address(rscratch1, 0));
640 }
641 }
642
643 void MacroAssembler::incrementq(Register reg, int value) {
644 if (value == min_jint) { addq(reg, value); return; }
645 if (value < 0) { decrementq(reg, -value); return; }
646 if (value == 0) { ; return; }
647 if (value == 1 && UseIncDec) { incq(reg) ; return; }
648 /* else */ { addq(reg, value) ; return; }
649 }
650
651 void MacroAssembler::incrementq(Address dst, int value) {
652 if (value == min_jint) { addq(dst, value); return; }
653 if (value < 0) { decrementq(dst, -value); return; }
654 if (value == 0) { ; return; }
655 if (value == 1 && UseIncDec) { incq(dst) ; return; }
656 /* else */ { addq(dst, value) ; return; }
657 }
658
659 // 32bit can do a case table jump in one instruction but we no longer allow the base
660 // to be installed in the Address class
661 void MacroAssembler::jump(ArrayAddress entry) {
662 lea(rscratch1, entry.base());
663 Address dispatch = entry.index();
664 assert(dispatch._base == noreg, "must be");
665 dispatch._base = rscratch1;
666 jmp(dispatch);
667 }
668
669 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
670 ShouldNotReachHere(); // 64bit doesn't use two regs
671 cmpq(x_lo, y_lo);
672 }
673
674 void MacroAssembler::lea(Register dst, AddressLiteral src) {
675 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
676 }
677
678 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
679 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec());
680 movptr(dst, rscratch1);
681 }
682
683 void MacroAssembler::leave() {
684 // %%% is this really better? Why not on 32bit too?
685 emit_int8((unsigned char)0xC9); // LEAVE
686 }
687
688 void MacroAssembler::lneg(Register hi, Register lo) {
689 ShouldNotReachHere(); // 64bit doesn't use two regs
690 negq(lo);
691 }
692
693 void MacroAssembler::movoop(Register dst, jobject obj) {
694 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
695 }
696
697 void MacroAssembler::movoop(Address dst, jobject obj) {
698 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate());
699 movq(dst, rscratch1);
700 }
701
702 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
703 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
704 }
705
706 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
707 mov_literal64(rscratch1, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
708 movq(dst, rscratch1);
709 }
710
711 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
712 if (src.is_lval()) {
713 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
714 } else {
715 if (reachable(src)) {
716 movq(dst, as_Address(src));
717 } else {
718 lea(scratch, src);
719 movq(dst, Address(scratch, 0));
720 }
721 }
722 }
723
724 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
725 movq(as_Address(dst), src);
726 }
727
728 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
729 movq(dst, as_Address(src));
730 }
731
732 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
733 void MacroAssembler::movptr(Address dst, intptr_t src) {
734 mov64(rscratch1, src);
735 movq(dst, rscratch1);
736 }
737
738 // These are mostly for initializing NULL
739 void MacroAssembler::movptr(Address dst, int32_t src) {
740 movslq(dst, src);
741 }
742
743 void MacroAssembler::movptr(Register dst, int32_t src) {
744 mov64(dst, (intptr_t)src);
745 }
746
747 void MacroAssembler::pushoop(jobject obj) {
748 movoop(rscratch1, obj);
749 push(rscratch1);
750 }
751
752 void MacroAssembler::pushklass(Metadata* obj) {
753 mov_metadata(rscratch1, obj);
754 push(rscratch1);
755 }
756
757 void MacroAssembler::pushptr(AddressLiteral src) {
758 lea(rscratch1, src);
759 if (src.is_lval()) {
760 push(rscratch1);
761 } else {
762 pushq(Address(rscratch1, 0));
763 }
764 }
765
766 void MacroAssembler::reset_last_Java_frame(bool clear_fp) {
767 // we must set sp to zero to clear frame
768 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
769 // must clear fp, so that compiled frames are not confused; it is
770 // possible that we need it only for debugging
771 if (clear_fp) {
772 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
773 }
774
775 // Always clear the pc because it could have been set by make_walkable()
776 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
777 vzeroupper();
778 }
779
780 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
781 Register last_java_fp,
782 address last_java_pc) {
783 vzeroupper();
784 // determine last_java_sp register
785 if (!last_java_sp->is_valid()) {
786 last_java_sp = rsp;
787 }
788
789 // last_java_fp is optional
790 if (last_java_fp->is_valid()) {
791 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()),
792 last_java_fp);
793 }
794
795 // last_java_pc is optional
796 if (last_java_pc != NULL) {
797 Address java_pc(r15_thread,
798 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
799 lea(rscratch1, InternalAddress(last_java_pc));
800 movptr(java_pc, rscratch1);
801 }
802
803 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
804 }
805
806 static void pass_arg0(MacroAssembler* masm, Register arg) {
807 if (c_rarg0 != arg ) {
808 masm->mov(c_rarg0, arg);
809 }
810 }
811
812 static void pass_arg1(MacroAssembler* masm, Register arg) {
813 if (c_rarg1 != arg ) {
814 masm->mov(c_rarg1, arg);
815 }
816 }
817
818 static void pass_arg2(MacroAssembler* masm, Register arg) {
819 if (c_rarg2 != arg ) {
820 masm->mov(c_rarg2, arg);
821 }
822 }
823
824 static void pass_arg3(MacroAssembler* masm, Register arg) {
825 if (c_rarg3 != arg ) {
826 masm->mov(c_rarg3, arg);
827 }
828 }
829
830 void MacroAssembler::stop(const char* msg) {
831 address rip = pc();
832 pusha(); // get regs on stack
833 lea(c_rarg0, ExternalAddress((address) msg));
834 lea(c_rarg1, InternalAddress(rip));
835 movq(c_rarg2, rsp); // pass pointer to regs array
836 andq(rsp, -16); // align stack as required by ABI
837 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
838 hlt();
839 }
840
841 void MacroAssembler::warn(const char* msg) {
842 push(rbp);
843 movq(rbp, rsp);
844 andq(rsp, -16); // align stack as required by push_CPU_state and call
845 push_CPU_state(); // keeps alignment at 16 bytes
846 lea(c_rarg0, ExternalAddress((address) msg));
847 lea(rax, ExternalAddress(CAST_FROM_FN_PTR(address, warning)));
848 call(rax);
849 pop_CPU_state();
850 mov(rsp, rbp);
851 pop(rbp);
852 }
853
854 void MacroAssembler::print_state() {
855 address rip = pc();
856 pusha(); // get regs on stack
857 push(rbp);
858 movq(rbp, rsp);
859 andq(rsp, -16); // align stack as required by push_CPU_state and call
860 push_CPU_state(); // keeps alignment at 16 bytes
861
862 lea(c_rarg0, InternalAddress(rip));
863 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
864 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
865
866 pop_CPU_state();
867 mov(rsp, rbp);
868 pop(rbp);
869 popa();
870 }
871
872 #ifndef PRODUCT
873 extern "C" void findpc(intptr_t x);
874 #endif
875
876 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
877 // In order to get locks to work, we need to fake a in_VM state
878 if (ShowMessageBoxOnError) {
879 JavaThread* thread = JavaThread::current();
880 JavaThreadState saved_state = thread->thread_state();
881 thread->set_thread_state(_thread_in_vm);
882 #ifndef PRODUCT
883 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
884 ttyLocker ttyl;
885 BytecodeCounter::print();
886 }
887 #endif
888 // To see where a verify_oop failed, get $ebx+40/X for this frame.
889 // XXX correct this offset for amd64
890 // This is the value of eip which points to where verify_oop will return.
891 if (os::message_box(msg, "Execution stopped, print registers?")) {
892 print_state64(pc, regs);
893 BREAKPOINT;
894 assert(false, "start up GDB");
895 }
896 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
897 } else {
898 ttyLocker ttyl;
899 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n",
900 msg);
901 assert(false, "DEBUG MESSAGE: %s", msg);
902 }
903 }
904
905 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
906 ttyLocker ttyl;
907 FlagSetting fs(Debugging, true);
908 tty->print_cr("rip = 0x%016lx", (intptr_t)pc);
909 #ifndef PRODUCT
910 tty->cr();
911 findpc(pc);
912 tty->cr();
913 #endif
914 #define PRINT_REG(rax, value) \
915 { tty->print("%s = ", #rax); os::print_location(tty, value); }
916 PRINT_REG(rax, regs[15]);
917 PRINT_REG(rbx, regs[12]);
918 PRINT_REG(rcx, regs[14]);
919 PRINT_REG(rdx, regs[13]);
920 PRINT_REG(rdi, regs[8]);
921 PRINT_REG(rsi, regs[9]);
922 PRINT_REG(rbp, regs[10]);
923 PRINT_REG(rsp, regs[11]);
924 PRINT_REG(r8 , regs[7]);
925 PRINT_REG(r9 , regs[6]);
926 PRINT_REG(r10, regs[5]);
927 PRINT_REG(r11, regs[4]);
928 PRINT_REG(r12, regs[3]);
929 PRINT_REG(r13, regs[2]);
930 PRINT_REG(r14, regs[1]);
931 PRINT_REG(r15, regs[0]);
932 #undef PRINT_REG
933 // Print some words near top of staack.
934 int64_t* rsp = (int64_t*) regs[11];
935 int64_t* dump_sp = rsp;
936 for (int col1 = 0; col1 < 8; col1++) {
937 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
938 os::print_location(tty, *dump_sp++);
939 }
940 for (int row = 0; row < 25; row++) {
941 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
942 for (int col = 0; col < 4; col++) {
943 tty->print(" 0x%016lx", (intptr_t)*dump_sp++);
944 }
945 tty->cr();
946 }
947 // Print some instructions around pc:
948 Disassembler::decode((address)pc-64, (address)pc);
949 tty->print_cr("--------");
950 Disassembler::decode((address)pc, (address)pc+32);
951 }
952
953 #endif // _LP64
954
955 // Now versions that are common to 32/64 bit
956
957 void MacroAssembler::addptr(Register dst, int32_t imm32) {
958 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
959 }
960
961 void MacroAssembler::addptr(Register dst, Register src) {
962 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
963 }
964
965 void MacroAssembler::addptr(Address dst, Register src) {
966 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
967 }
968
969 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) {
970 if (reachable(src)) {
971 Assembler::addsd(dst, as_Address(src));
972 } else {
973 lea(rscratch1, src);
974 Assembler::addsd(dst, Address(rscratch1, 0));
975 }
976 }
977
978 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) {
979 if (reachable(src)) {
980 addss(dst, as_Address(src));
981 } else {
982 lea(rscratch1, src);
983 addss(dst, Address(rscratch1, 0));
984 }
985 }
986
987 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src) {
988 if (reachable(src)) {
989 Assembler::addpd(dst, as_Address(src));
990 } else {
991 lea(rscratch1, src);
992 Assembler::addpd(dst, Address(rscratch1, 0));
993 }
994 }
995
996 void MacroAssembler::align(int modulus) {
997 align(modulus, offset());
998 }
999
1000 void MacroAssembler::align(int modulus, int target) {
1001 if (target % modulus != 0) {
1002 nop(modulus - (target % modulus));
1003 }
1004 }
1005
1006 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) {
1007 // Used in sign-masking with aligned address.
1008 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1009 if (reachable(src)) {
1010 Assembler::andpd(dst, as_Address(src));
1011 } else {
1012 lea(rscratch1, src);
1013 Assembler::andpd(dst, Address(rscratch1, 0));
1014 }
1015 }
1016
1017 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src) {
1018 // Used in sign-masking with aligned address.
1019 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1020 if (reachable(src)) {
1021 Assembler::andps(dst, as_Address(src));
1022 } else {
1023 lea(rscratch1, src);
1024 Assembler::andps(dst, Address(rscratch1, 0));
1025 }
1026 }
1027
1028 void MacroAssembler::andptr(Register dst, int32_t imm32) {
1029 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
1030 }
1031
1032 void MacroAssembler::atomic_incl(Address counter_addr) {
1033 if (os::is_MP())
1034 lock();
1035 incrementl(counter_addr);
1036 }
1037
1038 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register scr) {
1039 if (reachable(counter_addr)) {
1040 atomic_incl(as_Address(counter_addr));
1041 } else {
1042 lea(scr, counter_addr);
1043 atomic_incl(Address(scr, 0));
1044 }
1045 }
1046
1047 #ifdef _LP64
1048 void MacroAssembler::atomic_incq(Address counter_addr) {
1049 if (os::is_MP())
1050 lock();
1051 incrementq(counter_addr);
1052 }
1053
1054 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register scr) {
1055 if (reachable(counter_addr)) {
1056 atomic_incq(as_Address(counter_addr));
1057 } else {
1058 lea(scr, counter_addr);
1059 atomic_incq(Address(scr, 0));
1060 }
1061 }
1062 #endif
1063
1064 // Writes to stack successive pages until offset reached to check for
1065 // stack overflow + shadow pages. This clobbers tmp.
1066 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
1067 movptr(tmp, rsp);
1068 // Bang stack for total size given plus shadow page size.
1069 // Bang one page at a time because large size can bang beyond yellow and
1070 // red zones.
1071 Label loop;
1072 bind(loop);
1073 movl(Address(tmp, (-os::vm_page_size())), size );
1074 subptr(tmp, os::vm_page_size());
1075 subl(size, os::vm_page_size());
1076 jcc(Assembler::greater, loop);
1077
1078 // Bang down shadow pages too.
1079 // At this point, (tmp-0) is the last address touched, so don't
1080 // touch it again. (It was touched as (tmp-pagesize) but then tmp
1081 // was post-decremented.) Skip this address by starting at i=1, and
1082 // touch a few more pages below. N.B. It is important to touch all
1083 // the way down including all pages in the shadow zone.
1084 for (int i = 1; i < ((int)JavaThread::stack_shadow_zone_size() / os::vm_page_size()); i++) {
1085 // this could be any sized move but this is can be a debugging crumb
1086 // so the bigger the better.
1087 movptr(Address(tmp, (-i*os::vm_page_size())), size );
1088 }
1089 }
1090
1091 void MacroAssembler::reserved_stack_check() {
1092 // testing if reserved zone needs to be enabled
1093 Label no_reserved_zone_enabling;
1094 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
1095 NOT_LP64(get_thread(rsi);)
1096
1097 cmpptr(rsp, Address(thread, JavaThread::reserved_stack_activation_offset()));
1098 jcc(Assembler::below, no_reserved_zone_enabling);
1099
1100 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), thread);
1101 jump(RuntimeAddress(StubRoutines::throw_delayed_StackOverflowError_entry()));
1102 should_not_reach_here();
1103
1104 bind(no_reserved_zone_enabling);
1105 }
1106
1107 int MacroAssembler::biased_locking_enter(Register lock_reg,
1108 Register obj_reg,
1109 Register swap_reg,
1110 Register tmp_reg,
1111 bool swap_reg_contains_mark,
1112 Label& done,
1113 Label* slow_case,
1114 BiasedLockingCounters* counters) {
1115 assert(UseBiasedLocking, "why call this otherwise?");
1116 assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq");
1117 assert(tmp_reg != noreg, "tmp_reg must be supplied");
1118 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg);
1119 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
1120 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes());
1121 NOT_LP64( Address saved_mark_addr(lock_reg, 0); )
1122
1123 if (PrintBiasedLockingStatistics && counters == NULL) {
1124 counters = BiasedLocking::counters();
1125 }
1126 // Biased locking
1127 // See whether the lock is currently biased toward our thread and
1128 // whether the epoch is still valid
1129 // Note that the runtime guarantees sufficient alignment of JavaThread
1130 // pointers to allow age to be placed into low bits
1131 // First check to see whether biasing is even enabled for this object
1132 Label cas_label;
1133 int null_check_offset = -1;
1134 if (!swap_reg_contains_mark) {
1135 null_check_offset = offset();
1136 movptr(swap_reg, mark_addr);
1137 }
1138 movptr(tmp_reg, swap_reg);
1139 andptr(tmp_reg, markOopDesc::biased_lock_mask_in_place);
1140 cmpptr(tmp_reg, markOopDesc::biased_lock_pattern);
1141 jcc(Assembler::notEqual, cas_label);
1142 // The bias pattern is present in the object's header. Need to check
1143 // whether the bias owner and the epoch are both still current.
1144 #ifndef _LP64
1145 // Note that because there is no current thread register on x86_32 we
1146 // need to store off the mark word we read out of the object to
1147 // avoid reloading it and needing to recheck invariants below. This
1148 // store is unfortunate but it makes the overall code shorter and
1149 // simpler.
1150 movptr(saved_mark_addr, swap_reg);
1151 #endif
1152 if (swap_reg_contains_mark) {
1153 null_check_offset = offset();
1154 }
1155 load_prototype_header(tmp_reg, obj_reg);
1156 #ifdef _LP64
1157 orptr(tmp_reg, r15_thread);
1158 xorptr(tmp_reg, swap_reg);
1159 Register header_reg = tmp_reg;
1160 #else
1161 xorptr(tmp_reg, swap_reg);
1162 get_thread(swap_reg);
1163 xorptr(swap_reg, tmp_reg);
1164 Register header_reg = swap_reg;
1165 #endif
1166 andptr(header_reg, ~((int) markOopDesc::age_mask_in_place));
1167 if (counters != NULL) {
1168 cond_inc32(Assembler::zero,
1169 ExternalAddress((address) counters->biased_lock_entry_count_addr()));
1170 }
1171 jcc(Assembler::equal, done);
1172
1173 Label try_revoke_bias;
1174 Label try_rebias;
1175
1176 // At this point we know that the header has the bias pattern and
1177 // that we are not the bias owner in the current epoch. We need to
1178 // figure out more details about the state of the header in order to
1179 // know what operations can be legally performed on the object's
1180 // header.
1181
1182 // If the low three bits in the xor result aren't clear, that means
1183 // the prototype header is no longer biased and we have to revoke
1184 // the bias on this object.
1185 testptr(header_reg, markOopDesc::biased_lock_mask_in_place);
1186 jccb(Assembler::notZero, try_revoke_bias);
1187
1188 // Biasing is still enabled for this data type. See whether the
1189 // epoch of the current bias is still valid, meaning that the epoch
1190 // bits of the mark word are equal to the epoch bits of the
1191 // prototype header. (Note that the prototype header's epoch bits
1192 // only change at a safepoint.) If not, attempt to rebias the object
1193 // toward the current thread. Note that we must be absolutely sure
1194 // that the current epoch is invalid in order to do this because
1195 // otherwise the manipulations it performs on the mark word are
1196 // illegal.
1197 testptr(header_reg, markOopDesc::epoch_mask_in_place);
1198 jccb(Assembler::notZero, try_rebias);
1199
1200 // The epoch of the current bias is still valid but we know nothing
1201 // about the owner; it might be set or it might be clear. Try to
1202 // acquire the bias of the object using an atomic operation. If this
1203 // fails we will go in to the runtime to revoke the object's bias.
1204 // Note that we first construct the presumed unbiased header so we
1205 // don't accidentally blow away another thread's valid bias.
1206 NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1207 andptr(swap_reg,
1208 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
1209 #ifdef _LP64
1210 movptr(tmp_reg, swap_reg);
1211 orptr(tmp_reg, r15_thread);
1212 #else
1213 get_thread(tmp_reg);
1214 orptr(tmp_reg, swap_reg);
1215 #endif
1216 if (os::is_MP()) {
1217 lock();
1218 }
1219 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1220 // If the biasing toward our thread failed, this means that
1221 // another thread succeeded in biasing it toward itself and we
1222 // need to revoke that bias. The revocation will occur in the
1223 // interpreter runtime in the slow case.
1224 if (counters != NULL) {
1225 cond_inc32(Assembler::zero,
1226 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr()));
1227 }
1228 if (slow_case != NULL) {
1229 jcc(Assembler::notZero, *slow_case);
1230 }
1231 jmp(done);
1232
1233 bind(try_rebias);
1234 // At this point we know the epoch has expired, meaning that the
1235 // current "bias owner", if any, is actually invalid. Under these
1236 // circumstances _only_, we are allowed to use the current header's
1237 // value as the comparison value when doing the cas to acquire the
1238 // bias in the current epoch. In other words, we allow transfer of
1239 // the bias from one thread to another directly in this situation.
1240 //
1241 // FIXME: due to a lack of registers we currently blow away the age
1242 // bits in this situation. Should attempt to preserve them.
1243 load_prototype_header(tmp_reg, obj_reg);
1244 #ifdef _LP64
1245 orptr(tmp_reg, r15_thread);
1246 #else
1247 get_thread(swap_reg);
1248 orptr(tmp_reg, swap_reg);
1249 movptr(swap_reg, saved_mark_addr);
1250 #endif
1251 if (os::is_MP()) {
1252 lock();
1253 }
1254 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1255 // If the biasing toward our thread failed, then another thread
1256 // succeeded in biasing it toward itself and we need to revoke that
1257 // bias. The revocation will occur in the runtime in the slow case.
1258 if (counters != NULL) {
1259 cond_inc32(Assembler::zero,
1260 ExternalAddress((address) counters->rebiased_lock_entry_count_addr()));
1261 }
1262 if (slow_case != NULL) {
1263 jcc(Assembler::notZero, *slow_case);
1264 }
1265 jmp(done);
1266
1267 bind(try_revoke_bias);
1268 // The prototype mark in the klass doesn't have the bias bit set any
1269 // more, indicating that objects of this data type are not supposed
1270 // to be biased any more. We are going to try to reset the mark of
1271 // this object to the prototype value and fall through to the
1272 // CAS-based locking scheme. Note that if our CAS fails, it means
1273 // that another thread raced us for the privilege of revoking the
1274 // bias of this particular object, so it's okay to continue in the
1275 // normal locking code.
1276 //
1277 // FIXME: due to a lack of registers we currently blow away the age
1278 // bits in this situation. Should attempt to preserve them.
1279 NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1280 load_prototype_header(tmp_reg, obj_reg);
1281 if (os::is_MP()) {
1282 lock();
1283 }
1284 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1285 // Fall through to the normal CAS-based lock, because no matter what
1286 // the result of the above CAS, some thread must have succeeded in
1287 // removing the bias bit from the object's header.
1288 if (counters != NULL) {
1289 cond_inc32(Assembler::zero,
1290 ExternalAddress((address) counters->revoked_lock_entry_count_addr()));
1291 }
1292
1293 bind(cas_label);
1294
1295 return null_check_offset;
1296 }
1297
1298 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) {
1299 assert(UseBiasedLocking, "why call this otherwise?");
1300
1301 // Check for biased locking unlock case, which is a no-op
1302 // Note: we do not have to check the thread ID for two reasons.
1303 // First, the interpreter checks for IllegalMonitorStateException at
1304 // a higher level. Second, if the bias was revoked while we held the
1305 // lock, the object could not be rebiased toward another thread, so
1306 // the bias bit would be clear.
1307 movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
1308 andptr(temp_reg, markOopDesc::biased_lock_mask_in_place);
1309 cmpptr(temp_reg, markOopDesc::biased_lock_pattern);
1310 jcc(Assembler::equal, done);
1311 }
1312
1313 #ifdef COMPILER2
1314
1315 #if INCLUDE_RTM_OPT
1316
1317 // Update rtm_counters based on abort status
1318 // input: abort_status
1319 // rtm_counters (RTMLockingCounters*)
1320 // flags are killed
1321 void MacroAssembler::rtm_counters_update(Register abort_status, Register rtm_counters) {
1322
1323 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abort_count_offset()));
1324 if (PrintPreciseRTMLockingStatistics) {
1325 for (int i = 0; i < RTMLockingCounters::ABORT_STATUS_LIMIT; i++) {
1326 Label check_abort;
1327 testl(abort_status, (1<<i));
1328 jccb(Assembler::equal, check_abort);
1329 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abortX_count_offset() + (i * sizeof(uintx))));
1330 bind(check_abort);
1331 }
1332 }
1333 }
1334
1335 // Branch if (random & (count-1) != 0), count is 2^n
1336 // tmp, scr and flags are killed
1337 void MacroAssembler::branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel) {
1338 assert(tmp == rax, "");
1339 assert(scr == rdx, "");
1340 rdtsc(); // modifies EDX:EAX
1341 andptr(tmp, count-1);
1342 jccb(Assembler::notZero, brLabel);
1343 }
1344
1345 // Perform abort ratio calculation, set no_rtm bit if high ratio
1346 // input: rtm_counters_Reg (RTMLockingCounters* address)
1347 // tmpReg, rtm_counters_Reg and flags are killed
1348 void MacroAssembler::rtm_abort_ratio_calculation(Register tmpReg,
1349 Register rtm_counters_Reg,
1350 RTMLockingCounters* rtm_counters,
1351 Metadata* method_data) {
1352 Label L_done, L_check_always_rtm1, L_check_always_rtm2;
1353
1354 if (RTMLockingCalculationDelay > 0) {
1355 // Delay calculation
1356 movptr(tmpReg, ExternalAddress((address) RTMLockingCounters::rtm_calculation_flag_addr()), tmpReg);
1357 testptr(tmpReg, tmpReg);
1358 jccb(Assembler::equal, L_done);
1359 }
1360 // Abort ratio calculation only if abort_count > RTMAbortThreshold
1361 // Aborted transactions = abort_count * 100
1362 // All transactions = total_count * RTMTotalCountIncrRate
1363 // Set no_rtm bit if (Aborted transactions >= All transactions * RTMAbortRatio)
1364
1365 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::abort_count_offset()));
1366 cmpptr(tmpReg, RTMAbortThreshold);
1367 jccb(Assembler::below, L_check_always_rtm2);
1368 imulptr(tmpReg, tmpReg, 100);
1369
1370 Register scrReg = rtm_counters_Reg;
1371 movptr(scrReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1372 imulptr(scrReg, scrReg, RTMTotalCountIncrRate);
1373 imulptr(scrReg, scrReg, RTMAbortRatio);
1374 cmpptr(tmpReg, scrReg);
1375 jccb(Assembler::below, L_check_always_rtm1);
1376 if (method_data != NULL) {
1377 // set rtm_state to "no rtm" in MDO
1378 mov_metadata(tmpReg, method_data);
1379 if (os::is_MP()) {
1380 lock();
1381 }
1382 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), NoRTM);
1383 }
1384 jmpb(L_done);
1385 bind(L_check_always_rtm1);
1386 // Reload RTMLockingCounters* address
1387 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1388 bind(L_check_always_rtm2);
1389 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1390 cmpptr(tmpReg, RTMLockingThreshold / RTMTotalCountIncrRate);
1391 jccb(Assembler::below, L_done);
1392 if (method_data != NULL) {
1393 // set rtm_state to "always rtm" in MDO
1394 mov_metadata(tmpReg, method_data);
1395 if (os::is_MP()) {
1396 lock();
1397 }
1398 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), UseRTM);
1399 }
1400 bind(L_done);
1401 }
1402
1403 // Update counters and perform abort ratio calculation
1404 // input: abort_status_Reg
1405 // rtm_counters_Reg, flags are killed
1406 void MacroAssembler::rtm_profiling(Register abort_status_Reg,
1407 Register rtm_counters_Reg,
1408 RTMLockingCounters* rtm_counters,
1409 Metadata* method_data,
1410 bool profile_rtm) {
1411
1412 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1413 // update rtm counters based on rax value at abort
1414 // reads abort_status_Reg, updates flags
1415 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1416 rtm_counters_update(abort_status_Reg, rtm_counters_Reg);
1417 if (profile_rtm) {
1418 // Save abort status because abort_status_Reg is used by following code.
1419 if (RTMRetryCount > 0) {
1420 push(abort_status_Reg);
1421 }
1422 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1423 rtm_abort_ratio_calculation(abort_status_Reg, rtm_counters_Reg, rtm_counters, method_data);
1424 // restore abort status
1425 if (RTMRetryCount > 0) {
1426 pop(abort_status_Reg);
1427 }
1428 }
1429 }
1430
1431 // Retry on abort if abort's status is 0x6: can retry (0x2) | memory conflict (0x4)
1432 // inputs: retry_count_Reg
1433 // : abort_status_Reg
1434 // output: retry_count_Reg decremented by 1
1435 // flags are killed
1436 void MacroAssembler::rtm_retry_lock_on_abort(Register retry_count_Reg, Register abort_status_Reg, Label& retryLabel) {
1437 Label doneRetry;
1438 assert(abort_status_Reg == rax, "");
1439 // The abort reason bits are in eax (see all states in rtmLocking.hpp)
1440 // 0x6 = conflict on which we can retry (0x2) | memory conflict (0x4)
1441 // if reason is in 0x6 and retry count != 0 then retry
1442 andptr(abort_status_Reg, 0x6);
1443 jccb(Assembler::zero, doneRetry);
1444 testl(retry_count_Reg, retry_count_Reg);
1445 jccb(Assembler::zero, doneRetry);
1446 pause();
1447 decrementl(retry_count_Reg);
1448 jmp(retryLabel);
1449 bind(doneRetry);
1450 }
1451
1452 // Spin and retry if lock is busy,
1453 // inputs: box_Reg (monitor address)
1454 // : retry_count_Reg
1455 // output: retry_count_Reg decremented by 1
1456 // : clear z flag if retry count exceeded
1457 // tmp_Reg, scr_Reg, flags are killed
1458 void MacroAssembler::rtm_retry_lock_on_busy(Register retry_count_Reg, Register box_Reg,
1459 Register tmp_Reg, Register scr_Reg, Label& retryLabel) {
1460 Label SpinLoop, SpinExit, doneRetry;
1461 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1462
1463 testl(retry_count_Reg, retry_count_Reg);
1464 jccb(Assembler::zero, doneRetry);
1465 decrementl(retry_count_Reg);
1466 movptr(scr_Reg, RTMSpinLoopCount);
1467
1468 bind(SpinLoop);
1469 pause();
1470 decrementl(scr_Reg);
1471 jccb(Assembler::lessEqual, SpinExit);
1472 movptr(tmp_Reg, Address(box_Reg, owner_offset));
1473 testptr(tmp_Reg, tmp_Reg);
1474 jccb(Assembler::notZero, SpinLoop);
1475
1476 bind(SpinExit);
1477 jmp(retryLabel);
1478 bind(doneRetry);
1479 incrementl(retry_count_Reg); // clear z flag
1480 }
1481
1482 // Use RTM for normal stack locks
1483 // Input: objReg (object to lock)
1484 void MacroAssembler::rtm_stack_locking(Register objReg, Register tmpReg, Register scrReg,
1485 Register retry_on_abort_count_Reg,
1486 RTMLockingCounters* stack_rtm_counters,
1487 Metadata* method_data, bool profile_rtm,
1488 Label& DONE_LABEL, Label& IsInflated) {
1489 assert(UseRTMForStackLocks, "why call this otherwise?");
1490 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
1491 assert(tmpReg == rax, "");
1492 assert(scrReg == rdx, "");
1493 Label L_rtm_retry, L_decrement_retry, L_on_abort;
1494
1495 if (RTMRetryCount > 0) {
1496 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1497 bind(L_rtm_retry);
1498 }
1499 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes()));
1500 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased
1501 jcc(Assembler::notZero, IsInflated);
1502
1503 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1504 Label L_noincrement;
1505 if (RTMTotalCountIncrRate > 1) {
1506 // tmpReg, scrReg and flags are killed
1507 branch_on_random_using_rdtsc(tmpReg, scrReg, RTMTotalCountIncrRate, L_noincrement);
1508 }
1509 assert(stack_rtm_counters != NULL, "should not be NULL when profiling RTM");
1510 atomic_incptr(ExternalAddress((address)stack_rtm_counters->total_count_addr()), scrReg);
1511 bind(L_noincrement);
1512 }
1513 xbegin(L_on_abort);
1514 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // fetch markword
1515 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
1516 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked
1517 jcc(Assembler::equal, DONE_LABEL); // all done if unlocked
1518
1519 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1520 if (UseRTMXendForLockBusy) {
1521 xend();
1522 movptr(abort_status_Reg, 0x2); // Set the abort status to 2 (so we can retry)
1523 jmp(L_decrement_retry);
1524 }
1525 else {
1526 xabort(0);
1527 }
1528 bind(L_on_abort);
1529 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1530 rtm_profiling(abort_status_Reg, scrReg, stack_rtm_counters, method_data, profile_rtm);
1531 }
1532 bind(L_decrement_retry);
1533 if (RTMRetryCount > 0) {
1534 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1535 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1536 }
1537 }
1538
1539 // Use RTM for inflating locks
1540 // inputs: objReg (object to lock)
1541 // boxReg (on-stack box address (displaced header location) - KILLED)
1542 // tmpReg (ObjectMonitor address + markOopDesc::monitor_value)
1543 void MacroAssembler::rtm_inflated_locking(Register objReg, Register boxReg, Register tmpReg,
1544 Register scrReg, Register retry_on_busy_count_Reg,
1545 Register retry_on_abort_count_Reg,
1546 RTMLockingCounters* rtm_counters,
1547 Metadata* method_data, bool profile_rtm,
1548 Label& DONE_LABEL) {
1549 assert(UseRTMLocking, "why call this otherwise?");
1550 assert(tmpReg == rax, "");
1551 assert(scrReg == rdx, "");
1552 Label L_rtm_retry, L_decrement_retry, L_on_abort;
1553 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1554
1555 // Without cast to int32_t a movptr will destroy r10 which is typically obj
1556 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1557 movptr(boxReg, tmpReg); // Save ObjectMonitor address
1558
1559 if (RTMRetryCount > 0) {
1560 movl(retry_on_busy_count_Reg, RTMRetryCount); // Retry on lock busy
1561 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1562 bind(L_rtm_retry);
1563 }
1564 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1565 Label L_noincrement;
1566 if (RTMTotalCountIncrRate > 1) {
1567 // tmpReg, scrReg and flags are killed
1568 branch_on_random_using_rdtsc(tmpReg, scrReg, RTMTotalCountIncrRate, L_noincrement);
1569 }
1570 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1571 atomic_incptr(ExternalAddress((address)rtm_counters->total_count_addr()), scrReg);
1572 bind(L_noincrement);
1573 }
1574 xbegin(L_on_abort);
1575 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes()));
1576 movptr(tmpReg, Address(tmpReg, owner_offset));
1577 testptr(tmpReg, tmpReg);
1578 jcc(Assembler::zero, DONE_LABEL);
1579 if (UseRTMXendForLockBusy) {
1580 xend();
1581 jmp(L_decrement_retry);
1582 }
1583 else {
1584 xabort(0);
1585 }
1586 bind(L_on_abort);
1587 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1588 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1589 rtm_profiling(abort_status_Reg, scrReg, rtm_counters, method_data, profile_rtm);
1590 }
1591 if (RTMRetryCount > 0) {
1592 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1593 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1594 }
1595
1596 movptr(tmpReg, Address(boxReg, owner_offset)) ;
1597 testptr(tmpReg, tmpReg) ;
1598 jccb(Assembler::notZero, L_decrement_retry) ;
1599
1600 // Appears unlocked - try to swing _owner from null to non-null.
1601 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1602 #ifdef _LP64
1603 Register threadReg = r15_thread;
1604 #else
1605 get_thread(scrReg);
1606 Register threadReg = scrReg;
1607 #endif
1608 if (os::is_MP()) {
1609 lock();
1610 }
1611 cmpxchgptr(threadReg, Address(boxReg, owner_offset)); // Updates tmpReg
1612
1613 if (RTMRetryCount > 0) {
1614 // success done else retry
1615 jccb(Assembler::equal, DONE_LABEL) ;
1616 bind(L_decrement_retry);
1617 // Spin and retry if lock is busy.
1618 rtm_retry_lock_on_busy(retry_on_busy_count_Reg, boxReg, tmpReg, scrReg, L_rtm_retry);
1619 }
1620 else {
1621 bind(L_decrement_retry);
1622 }
1623 }
1624
1625 #endif // INCLUDE_RTM_OPT
1626
1627 // Fast_Lock and Fast_Unlock used by C2
1628
1629 // Because the transitions from emitted code to the runtime
1630 // monitorenter/exit helper stubs are so slow it's critical that
1631 // we inline both the stack-locking fast-path and the inflated fast path.
1632 //
1633 // See also: cmpFastLock and cmpFastUnlock.
1634 //
1635 // What follows is a specialized inline transliteration of the code
1636 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
1637 // another option would be to emit TrySlowEnter and TrySlowExit methods
1638 // at startup-time. These methods would accept arguments as
1639 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
1640 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
1641 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
1642 // In practice, however, the # of lock sites is bounded and is usually small.
1643 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
1644 // if the processor uses simple bimodal branch predictors keyed by EIP
1645 // Since the helper routines would be called from multiple synchronization
1646 // sites.
1647 //
1648 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
1649 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
1650 // to those specialized methods. That'd give us a mostly platform-independent
1651 // implementation that the JITs could optimize and inline at their pleasure.
1652 // Done correctly, the only time we'd need to cross to native could would be
1653 // to park() or unpark() threads. We'd also need a few more unsafe operators
1654 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
1655 // (b) explicit barriers or fence operations.
1656 //
1657 // TODO:
1658 //
1659 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
1660 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
1661 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
1662 // the lock operators would typically be faster than reifying Self.
1663 //
1664 // * Ideally I'd define the primitives as:
1665 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
1666 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
1667 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
1668 // Instead, we're stuck with a rather awkward and brittle register assignments below.
1669 // Furthermore the register assignments are overconstrained, possibly resulting in
1670 // sub-optimal code near the synchronization site.
1671 //
1672 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
1673 // Alternately, use a better sp-proximity test.
1674 //
1675 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
1676 // Either one is sufficient to uniquely identify a thread.
1677 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
1678 //
1679 // * Intrinsify notify() and notifyAll() for the common cases where the
1680 // object is locked by the calling thread but the waitlist is empty.
1681 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
1682 //
1683 // * use jccb and jmpb instead of jcc and jmp to improve code density.
1684 // But beware of excessive branch density on AMD Opterons.
1685 //
1686 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
1687 // or failure of the fast-path. If the fast-path fails then we pass
1688 // control to the slow-path, typically in C. In Fast_Lock and
1689 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
1690 // will emit a conditional branch immediately after the node.
1691 // So we have branches to branches and lots of ICC.ZF games.
1692 // Instead, it might be better to have C2 pass a "FailureLabel"
1693 // into Fast_Lock and Fast_Unlock. In the case of success, control
1694 // will drop through the node. ICC.ZF is undefined at exit.
1695 // In the case of failure, the node will branch directly to the
1696 // FailureLabel
1697
1698
1699 // obj: object to lock
1700 // box: on-stack box address (displaced header location) - KILLED
1701 // rax,: tmp -- KILLED
1702 // scr: tmp -- KILLED
1703 void MacroAssembler::fast_lock(Register objReg, Register boxReg, Register tmpReg,
1704 Register scrReg, Register cx1Reg, Register cx2Reg,
1705 BiasedLockingCounters* counters,
1706 RTMLockingCounters* rtm_counters,
1707 RTMLockingCounters* stack_rtm_counters,
1708 Metadata* method_data,
1709 bool use_rtm, bool profile_rtm) {
1710 // Ensure the register assignments are disjoint
1711 assert(tmpReg == rax, "");
1712
1713 if (use_rtm) {
1714 assert_different_registers(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg);
1715 } else {
1716 assert(cx1Reg == noreg, "");
1717 assert(cx2Reg == noreg, "");
1718 assert_different_registers(objReg, boxReg, tmpReg, scrReg);
1719 }
1720
1721 if (counters != NULL) {
1722 atomic_incl(ExternalAddress((address)counters->total_entry_count_addr()), scrReg);
1723 }
1724 if (EmitSync & 1) {
1725 // set box->dhw = markOopDesc::unused_mark()
1726 // Force all sync thru slow-path: slow_enter() and slow_exit()
1727 movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1728 cmpptr (rsp, (int32_t)NULL_WORD);
1729 } else {
1730 // Possible cases that we'll encounter in fast_lock
1731 // ------------------------------------------------
1732 // * Inflated
1733 // -- unlocked
1734 // -- Locked
1735 // = by self
1736 // = by other
1737 // * biased
1738 // -- by Self
1739 // -- by other
1740 // * neutral
1741 // * stack-locked
1742 // -- by self
1743 // = sp-proximity test hits
1744 // = sp-proximity test generates false-negative
1745 // -- by other
1746 //
1747
1748 Label IsInflated, DONE_LABEL;
1749
1750 // it's stack-locked, biased or neutral
1751 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
1752 // order to reduce the number of conditional branches in the most common cases.
1753 // Beware -- there's a subtle invariant that fetch of the markword
1754 // at [FETCH], below, will never observe a biased encoding (*101b).
1755 // If this invariant is not held we risk exclusion (safety) failure.
1756 if (UseBiasedLocking && !UseOptoBiasInlining) {
1757 biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, counters);
1758 }
1759
1760 #if INCLUDE_RTM_OPT
1761 if (UseRTMForStackLocks && use_rtm) {
1762 rtm_stack_locking(objReg, tmpReg, scrReg, cx2Reg,
1763 stack_rtm_counters, method_data, profile_rtm,
1764 DONE_LABEL, IsInflated);
1765 }
1766 #endif // INCLUDE_RTM_OPT
1767
1768 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // [FETCH]
1769 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased
1770 jccb(Assembler::notZero, IsInflated);
1771
1772 // Attempt stack-locking ...
1773 orptr (tmpReg, markOopDesc::unlocked_value);
1774 movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
1775 if (os::is_MP()) {
1776 lock();
1777 }
1778 cmpxchgptr(boxReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Updates tmpReg
1779 if (counters != NULL) {
1780 cond_inc32(Assembler::equal,
1781 ExternalAddress((address)counters->fast_path_entry_count_addr()));
1782 }
1783 jcc(Assembler::equal, DONE_LABEL); // Success
1784
1785 // Recursive locking.
1786 // The object is stack-locked: markword contains stack pointer to BasicLock.
1787 // Locked by current thread if difference with current SP is less than one page.
1788 subptr(tmpReg, rsp);
1789 // Next instruction set ZFlag == 1 (Success) if difference is less then one page.
1790 andptr(tmpReg, (int32_t) (NOT_LP64(0xFFFFF003) LP64_ONLY(7 - os::vm_page_size())) );
1791 movptr(Address(boxReg, 0), tmpReg);
1792 if (counters != NULL) {
1793 cond_inc32(Assembler::equal,
1794 ExternalAddress((address)counters->fast_path_entry_count_addr()));
1795 }
1796 jmp(DONE_LABEL);
1797
1798 bind(IsInflated);
1799 // The object is inflated. tmpReg contains pointer to ObjectMonitor* + markOopDesc::monitor_value
1800
1801 #if INCLUDE_RTM_OPT
1802 // Use the same RTM locking code in 32- and 64-bit VM.
1803 if (use_rtm) {
1804 rtm_inflated_locking(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg,
1805 rtm_counters, method_data, profile_rtm, DONE_LABEL);
1806 } else {
1807 #endif // INCLUDE_RTM_OPT
1808
1809 #ifndef _LP64
1810 // The object is inflated.
1811
1812 // boxReg refers to the on-stack BasicLock in the current frame.
1813 // We'd like to write:
1814 // set box->_displaced_header = markOopDesc::unused_mark(). Any non-0 value suffices.
1815 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
1816 // additional latency as we have another ST in the store buffer that must drain.
1817
1818 if (EmitSync & 8192) {
1819 movptr(Address(boxReg, 0), 3); // results in ST-before-CAS penalty
1820 get_thread (scrReg);
1821 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
1822 movptr(tmpReg, NULL_WORD); // consider: xor vs mov
1823 if (os::is_MP()) {
1824 lock();
1825 }
1826 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1827 } else
1828 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
1829 // register juggle because we need tmpReg for cmpxchgptr below
1830 movptr(scrReg, boxReg);
1831 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
1832
1833 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
1834 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
1835 // prefetchw [eax + Offset(_owner)-2]
1836 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1837 }
1838
1839 if ((EmitSync & 64) == 0) {
1840 // Optimistic form: consider XORL tmpReg,tmpReg
1841 movptr(tmpReg, NULL_WORD);
1842 } else {
1843 // Can suffer RTS->RTO upgrades on shared or cold $ lines
1844 // Test-And-CAS instead of CAS
1845 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner
1846 testptr(tmpReg, tmpReg); // Locked ?
1847 jccb (Assembler::notZero, DONE_LABEL);
1848 }
1849
1850 // Appears unlocked - try to swing _owner from null to non-null.
1851 // Ideally, I'd manifest "Self" with get_thread and then attempt
1852 // to CAS the register containing Self into m->Owner.
1853 // But we don't have enough registers, so instead we can either try to CAS
1854 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
1855 // we later store "Self" into m->Owner. Transiently storing a stack address
1856 // (rsp or the address of the box) into m->owner is harmless.
1857 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1858 if (os::is_MP()) {
1859 lock();
1860 }
1861 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1862 movptr(Address(scrReg, 0), 3); // box->_displaced_header = 3
1863 // If we weren't able to swing _owner from NULL to the BasicLock
1864 // then take the slow path.
1865 jccb (Assembler::notZero, DONE_LABEL);
1866 // update _owner from BasicLock to thread
1867 get_thread (scrReg); // beware: clobbers ICCs
1868 movptr(Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), scrReg);
1869 xorptr(boxReg, boxReg); // set icc.ZFlag = 1 to indicate success
1870
1871 // If the CAS fails we can either retry or pass control to the slow-path.
1872 // We use the latter tactic.
1873 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1874 // If the CAS was successful ...
1875 // Self has acquired the lock
1876 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1877 // Intentional fall-through into DONE_LABEL ...
1878 } else {
1879 movptr(Address(boxReg, 0), intptr_t(markOopDesc::unused_mark())); // results in ST-before-CAS penalty
1880 movptr(boxReg, tmpReg);
1881
1882 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
1883 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
1884 // prefetchw [eax + Offset(_owner)-2]
1885 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1886 }
1887
1888 if ((EmitSync & 64) == 0) {
1889 // Optimistic form
1890 xorptr (tmpReg, tmpReg);
1891 } else {
1892 // Can suffer RTS->RTO upgrades on shared or cold $ lines
1893 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner
1894 testptr(tmpReg, tmpReg); // Locked ?
1895 jccb (Assembler::notZero, DONE_LABEL);
1896 }
1897
1898 // Appears unlocked - try to swing _owner from null to non-null.
1899 // Use either "Self" (in scr) or rsp as thread identity in _owner.
1900 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1901 get_thread (scrReg);
1902 if (os::is_MP()) {
1903 lock();
1904 }
1905 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1906
1907 // If the CAS fails we can either retry or pass control to the slow-path.
1908 // We use the latter tactic.
1909 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1910 // If the CAS was successful ...
1911 // Self has acquired the lock
1912 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1913 // Intentional fall-through into DONE_LABEL ...
1914 }
1915 #else // _LP64
1916 // It's inflated
1917 movq(scrReg, tmpReg);
1918 xorq(tmpReg, tmpReg);
1919
1920 if (os::is_MP()) {
1921 lock();
1922 }
1923 cmpxchgptr(r15_thread, Address(scrReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1924 // Unconditionally set box->_displaced_header = markOopDesc::unused_mark().
1925 // Without cast to int32_t movptr will destroy r10 which is typically obj.
1926 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1927 // Intentional fall-through into DONE_LABEL ...
1928 // Propagate ICC.ZF from CAS above into DONE_LABEL.
1929 #endif // _LP64
1930 #if INCLUDE_RTM_OPT
1931 } // use_rtm()
1932 #endif
1933 // DONE_LABEL is a hot target - we'd really like to place it at the
1934 // start of cache line by padding with NOPs.
1935 // See the AMD and Intel software optimization manuals for the
1936 // most efficient "long" NOP encodings.
1937 // Unfortunately none of our alignment mechanisms suffice.
1938 bind(DONE_LABEL);
1939
1940 // At DONE_LABEL the icc ZFlag is set as follows ...
1941 // Fast_Unlock uses the same protocol.
1942 // ZFlag == 1 -> Success
1943 // ZFlag == 0 -> Failure - force control through the slow-path
1944 }
1945 }
1946
1947 // obj: object to unlock
1948 // box: box address (displaced header location), killed. Must be EAX.
1949 // tmp: killed, cannot be obj nor box.
1950 //
1951 // Some commentary on balanced locking:
1952 //
1953 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
1954 // Methods that don't have provably balanced locking are forced to run in the
1955 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
1956 // The interpreter provides two properties:
1957 // I1: At return-time the interpreter automatically and quietly unlocks any
1958 // objects acquired the current activation (frame). Recall that the
1959 // interpreter maintains an on-stack list of locks currently held by
1960 // a frame.
1961 // I2: If a method attempts to unlock an object that is not held by the
1962 // the frame the interpreter throws IMSX.
1963 //
1964 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
1965 // B() doesn't have provably balanced locking so it runs in the interpreter.
1966 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
1967 // is still locked by A().
1968 //
1969 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
1970 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
1971 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
1972 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
1973 // Arguably given that the spec legislates the JNI case as undefined our implementation
1974 // could reasonably *avoid* checking owner in Fast_Unlock().
1975 // In the interest of performance we elide m->Owner==Self check in unlock.
1976 // A perfectly viable alternative is to elide the owner check except when
1977 // Xcheck:jni is enabled.
1978
1979 void MacroAssembler::fast_unlock(Register objReg, Register boxReg, Register tmpReg, bool use_rtm) {
1980 assert(boxReg == rax, "");
1981 assert_different_registers(objReg, boxReg, tmpReg);
1982
1983 if (EmitSync & 4) {
1984 // Disable - inhibit all inlining. Force control through the slow-path
1985 cmpptr (rsp, 0);
1986 } else {
1987 Label DONE_LABEL, Stacked, CheckSucc;
1988
1989 // Critically, the biased locking test must have precedence over
1990 // and appear before the (box->dhw == 0) recursive stack-lock test.
1991 if (UseBiasedLocking && !UseOptoBiasInlining) {
1992 biased_locking_exit(objReg, tmpReg, DONE_LABEL);
1993 }
1994
1995 #if INCLUDE_RTM_OPT
1996 if (UseRTMForStackLocks && use_rtm) {
1997 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
1998 Label L_regular_unlock;
1999 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // fetch markword
2000 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
2001 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked
2002 jccb(Assembler::notEqual, L_regular_unlock); // if !HLE RegularLock
2003 xend(); // otherwise end...
2004 jmp(DONE_LABEL); // ... and we're done
2005 bind(L_regular_unlock);
2006 }
2007 #endif
2008
2009 cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD); // Examine the displaced header
2010 jcc (Assembler::zero, DONE_LABEL); // 0 indicates recursive stack-lock
2011 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Examine the object's markword
2012 testptr(tmpReg, markOopDesc::monitor_value); // Inflated?
2013 jccb (Assembler::zero, Stacked);
2014
2015 // It's inflated.
2016 #if INCLUDE_RTM_OPT
2017 if (use_rtm) {
2018 Label L_regular_inflated_unlock;
2019 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
2020 movptr(boxReg, Address(tmpReg, owner_offset));
2021 testptr(boxReg, boxReg);
2022 jccb(Assembler::notZero, L_regular_inflated_unlock);
2023 xend();
2024 jmpb(DONE_LABEL);
2025 bind(L_regular_inflated_unlock);
2026 }
2027 #endif
2028
2029 // Despite our balanced locking property we still check that m->_owner == Self
2030 // as java routines or native JNI code called by this thread might
2031 // have released the lock.
2032 // Refer to the comments in synchronizer.cpp for how we might encode extra
2033 // state in _succ so we can avoid fetching EntryList|cxq.
2034 //
2035 // I'd like to add more cases in fast_lock() and fast_unlock() --
2036 // such as recursive enter and exit -- but we have to be wary of
2037 // I$ bloat, T$ effects and BP$ effects.
2038 //
2039 // If there's no contention try a 1-0 exit. That is, exit without
2040 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
2041 // we detect and recover from the race that the 1-0 exit admits.
2042 //
2043 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
2044 // before it STs null into _owner, releasing the lock. Updates
2045 // to data protected by the critical section must be visible before
2046 // we drop the lock (and thus before any other thread could acquire
2047 // the lock and observe the fields protected by the lock).
2048 // IA32's memory-model is SPO, so STs are ordered with respect to
2049 // each other and there's no need for an explicit barrier (fence).
2050 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
2051 #ifndef _LP64
2052 get_thread (boxReg);
2053 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
2054 // prefetchw [ebx + Offset(_owner)-2]
2055 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2056 }
2057
2058 // Note that we could employ various encoding schemes to reduce
2059 // the number of loads below (currently 4) to just 2 or 3.
2060 // Refer to the comments in synchronizer.cpp.
2061 // In practice the chain of fetches doesn't seem to impact performance, however.
2062 xorptr(boxReg, boxReg);
2063 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
2064 // Attempt to reduce branch density - AMD's branch predictor.
2065 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2066 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2067 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2068 jccb (Assembler::notZero, DONE_LABEL);
2069 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2070 jmpb (DONE_LABEL);
2071 } else {
2072 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2073 jccb (Assembler::notZero, DONE_LABEL);
2074 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2075 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2076 jccb (Assembler::notZero, CheckSucc);
2077 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2078 jmpb (DONE_LABEL);
2079 }
2080
2081 // The Following code fragment (EmitSync & 65536) improves the performance of
2082 // contended applications and contended synchronization microbenchmarks.
2083 // Unfortunately the emission of the code - even though not executed - causes regressions
2084 // in scimark and jetstream, evidently because of $ effects. Replacing the code
2085 // with an equal number of never-executed NOPs results in the same regression.
2086 // We leave it off by default.
2087
2088 if ((EmitSync & 65536) != 0) {
2089 Label LSuccess, LGoSlowPath ;
2090
2091 bind (CheckSucc);
2092
2093 // Optional pre-test ... it's safe to elide this
2094 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2095 jccb(Assembler::zero, LGoSlowPath);
2096
2097 // We have a classic Dekker-style idiom:
2098 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
2099 // There are a number of ways to implement the barrier:
2100 // (1) lock:andl &m->_owner, 0
2101 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
2102 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
2103 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
2104 // (2) If supported, an explicit MFENCE is appealing.
2105 // In older IA32 processors MFENCE is slower than lock:add or xchg
2106 // particularly if the write-buffer is full as might be the case if
2107 // if stores closely precede the fence or fence-equivalent instruction.
2108 // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences
2109 // as the situation has changed with Nehalem and Shanghai.
2110 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
2111 // The $lines underlying the top-of-stack should be in M-state.
2112 // The locked add instruction is serializing, of course.
2113 // (4) Use xchg, which is serializing
2114 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
2115 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
2116 // The integer condition codes will tell us if succ was 0.
2117 // Since _succ and _owner should reside in the same $line and
2118 // we just stored into _owner, it's likely that the $line
2119 // remains in M-state for the lock:orl.
2120 //
2121 // We currently use (3), although it's likely that switching to (2)
2122 // is correct for the future.
2123
2124 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2125 if (os::is_MP()) {
2126 lock(); addptr(Address(rsp, 0), 0);
2127 }
2128 // Ratify _succ remains non-null
2129 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), 0);
2130 jccb (Assembler::notZero, LSuccess);
2131
2132 xorptr(boxReg, boxReg); // box is really EAX
2133 if (os::is_MP()) { lock(); }
2134 cmpxchgptr(rsp, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2135 // There's no successor so we tried to regrab the lock with the
2136 // placeholder value. If that didn't work, then another thread
2137 // grabbed the lock so we're done (and exit was a success).
2138 jccb (Assembler::notEqual, LSuccess);
2139 // Since we're low on registers we installed rsp as a placeholding in _owner.
2140 // Now install Self over rsp. This is safe as we're transitioning from
2141 // non-null to non=null
2142 get_thread (boxReg);
2143 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), boxReg);
2144 // Intentional fall-through into LGoSlowPath ...
2145
2146 bind (LGoSlowPath);
2147 orptr(boxReg, 1); // set ICC.ZF=0 to indicate failure
2148 jmpb (DONE_LABEL);
2149
2150 bind (LSuccess);
2151 xorptr(boxReg, boxReg); // set ICC.ZF=1 to indicate success
2152 jmpb (DONE_LABEL);
2153 }
2154
2155 bind (Stacked);
2156 // It's not inflated and it's not recursively stack-locked and it's not biased.
2157 // It must be stack-locked.
2158 // Try to reset the header to displaced header.
2159 // The "box" value on the stack is stable, so we can reload
2160 // and be assured we observe the same value as above.
2161 movptr(tmpReg, Address(boxReg, 0));
2162 if (os::is_MP()) {
2163 lock();
2164 }
2165 cmpxchgptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Uses RAX which is box
2166 // Intention fall-thru into DONE_LABEL
2167
2168 // DONE_LABEL is a hot target - we'd really like to place it at the
2169 // start of cache line by padding with NOPs.
2170 // See the AMD and Intel software optimization manuals for the
2171 // most efficient "long" NOP encodings.
2172 // Unfortunately none of our alignment mechanisms suffice.
2173 if ((EmitSync & 65536) == 0) {
2174 bind (CheckSucc);
2175 }
2176 #else // _LP64
2177 // It's inflated
2178 if (EmitSync & 1024) {
2179 // Emit code to check that _owner == Self
2180 // We could fold the _owner test into subsequent code more efficiently
2181 // than using a stand-alone check, but since _owner checking is off by
2182 // default we don't bother. We also might consider predicating the
2183 // _owner==Self check on Xcheck:jni or running on a debug build.
2184 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2185 xorptr(boxReg, r15_thread);
2186 } else {
2187 xorptr(boxReg, boxReg);
2188 }
2189 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2190 jccb (Assembler::notZero, DONE_LABEL);
2191 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2192 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2193 jccb (Assembler::notZero, CheckSucc);
2194 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD);
2195 jmpb (DONE_LABEL);
2196
2197 if ((EmitSync & 65536) == 0) {
2198 // Try to avoid passing control into the slow_path ...
2199 Label LSuccess, LGoSlowPath ;
2200 bind (CheckSucc);
2201
2202 // The following optional optimization can be elided if necessary
2203 // Effectively: if (succ == null) goto SlowPath
2204 // The code reduces the window for a race, however,
2205 // and thus benefits performance.
2206 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2207 jccb (Assembler::zero, LGoSlowPath);
2208
2209 xorptr(boxReg, boxReg);
2210 if ((EmitSync & 16) && os::is_MP()) {
2211 xchgptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2212 } else {
2213 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD);
2214 if (os::is_MP()) {
2215 // Memory barrier/fence
2216 // Dekker pivot point -- fulcrum : ST Owner; MEMBAR; LD Succ
2217 // Instead of MFENCE we use a dummy locked add of 0 to the top-of-stack.
2218 // This is faster on Nehalem and AMD Shanghai/Barcelona.
2219 // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences
2220 // We might also restructure (ST Owner=0;barrier;LD _Succ) to
2221 // (mov box,0; xchgq box, &m->Owner; LD _succ) .
2222 lock(); addl(Address(rsp, 0), 0);
2223 }
2224 }
2225 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2226 jccb (Assembler::notZero, LSuccess);
2227
2228 // Rare inopportune interleaving - race.
2229 // The successor vanished in the small window above.
2230 // The lock is contended -- (cxq|EntryList) != null -- and there's no apparent successor.
2231 // We need to ensure progress and succession.
2232 // Try to reacquire the lock.
2233 // If that fails then the new owner is responsible for succession and this
2234 // thread needs to take no further action and can exit via the fast path (success).
2235 // If the re-acquire succeeds then pass control into the slow path.
2236 // As implemented, this latter mode is horrible because we generated more
2237 // coherence traffic on the lock *and* artifically extended the critical section
2238 // length while by virtue of passing control into the slow path.
2239
2240 // box is really RAX -- the following CMPXCHG depends on that binding
2241 // cmpxchg R,[M] is equivalent to rax = CAS(M,rax,R)
2242 if (os::is_MP()) { lock(); }
2243 cmpxchgptr(r15_thread, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2244 // There's no successor so we tried to regrab the lock.
2245 // If that didn't work, then another thread grabbed the
2246 // lock so we're done (and exit was a success).
2247 jccb (Assembler::notEqual, LSuccess);
2248 // Intentional fall-through into slow-path
2249
2250 bind (LGoSlowPath);
2251 orl (boxReg, 1); // set ICC.ZF=0 to indicate failure
2252 jmpb (DONE_LABEL);
2253
2254 bind (LSuccess);
2255 testl (boxReg, 0); // set ICC.ZF=1 to indicate success
2256 jmpb (DONE_LABEL);
2257 }
2258
2259 bind (Stacked);
2260 movptr(tmpReg, Address (boxReg, 0)); // re-fetch
2261 if (os::is_MP()) { lock(); }
2262 cmpxchgptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Uses RAX which is box
2263
2264 if (EmitSync & 65536) {
2265 bind (CheckSucc);
2266 }
2267 #endif
2268 bind(DONE_LABEL);
2269 }
2270 }
2271 #endif // COMPILER2
2272
2273 void MacroAssembler::c2bool(Register x) {
2274 // implements x == 0 ? 0 : 1
2275 // note: must only look at least-significant byte of x
2276 // since C-style booleans are stored in one byte
2277 // only! (was bug)
2278 andl(x, 0xFF);
2279 setb(Assembler::notZero, x);
2280 }
2281
2282 // Wouldn't need if AddressLiteral version had new name
2283 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
2284 Assembler::call(L, rtype);
2285 }
2286
2287 void MacroAssembler::call(Register entry) {
2288 Assembler::call(entry);
2289 }
2290
2291 void MacroAssembler::call(AddressLiteral entry) {
2292 if (reachable(entry)) {
2293 Assembler::call_literal(entry.target(), entry.rspec());
2294 } else {
2295 lea(rscratch1, entry);
2296 Assembler::call(rscratch1);
2297 }
2298 }
2299
2300 void MacroAssembler::ic_call(address entry, jint method_index) {
2301 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
2302 movptr(rax, (intptr_t)Universe::non_oop_word());
2303 call(AddressLiteral(entry, rh));
2304 }
2305
2306 // Implementation of call_VM versions
2307
2308 void MacroAssembler::call_VM(Register oop_result,
2309 address entry_point,
2310 bool check_exceptions) {
2311 Label C, E;
2312 call(C, relocInfo::none);
2313 jmp(E);
2314
2315 bind(C);
2316 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
2317 ret(0);
2318
2319 bind(E);
2320 }
2321
2322 void MacroAssembler::call_VM(Register oop_result,
2323 address entry_point,
2324 Register arg_1,
2325 bool check_exceptions) {
2326 Label C, E;
2327 call(C, relocInfo::none);
2328 jmp(E);
2329
2330 bind(C);
2331 pass_arg1(this, arg_1);
2332 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
2333 ret(0);
2334
2335 bind(E);
2336 }
2337
2338 void MacroAssembler::call_VM(Register oop_result,
2339 address entry_point,
2340 Register arg_1,
2341 Register arg_2,
2342 bool check_exceptions) {
2343 Label C, E;
2344 call(C, relocInfo::none);
2345 jmp(E);
2346
2347 bind(C);
2348
2349 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2350
2351 pass_arg2(this, arg_2);
2352 pass_arg1(this, arg_1);
2353 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
2354 ret(0);
2355
2356 bind(E);
2357 }
2358
2359 void MacroAssembler::call_VM(Register oop_result,
2360 address entry_point,
2361 Register arg_1,
2362 Register arg_2,
2363 Register arg_3,
2364 bool check_exceptions) {
2365 Label C, E;
2366 call(C, relocInfo::none);
2367 jmp(E);
2368
2369 bind(C);
2370
2371 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2372 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2373 pass_arg3(this, arg_3);
2374
2375 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2376 pass_arg2(this, arg_2);
2377
2378 pass_arg1(this, arg_1);
2379 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
2380 ret(0);
2381
2382 bind(E);
2383 }
2384
2385 void MacroAssembler::call_VM(Register oop_result,
2386 Register last_java_sp,
2387 address entry_point,
2388 int number_of_arguments,
2389 bool check_exceptions) {
2390 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2391 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2392 }
2393
2394 void MacroAssembler::call_VM(Register oop_result,
2395 Register last_java_sp,
2396 address entry_point,
2397 Register arg_1,
2398 bool check_exceptions) {
2399 pass_arg1(this, arg_1);
2400 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2401 }
2402
2403 void MacroAssembler::call_VM(Register oop_result,
2404 Register last_java_sp,
2405 address entry_point,
2406 Register arg_1,
2407 Register arg_2,
2408 bool check_exceptions) {
2409
2410 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2411 pass_arg2(this, arg_2);
2412 pass_arg1(this, arg_1);
2413 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2414 }
2415
2416 void MacroAssembler::call_VM(Register oop_result,
2417 Register last_java_sp,
2418 address entry_point,
2419 Register arg_1,
2420 Register arg_2,
2421 Register arg_3,
2422 bool check_exceptions) {
2423 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2424 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2425 pass_arg3(this, arg_3);
2426 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2427 pass_arg2(this, arg_2);
2428 pass_arg1(this, arg_1);
2429 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2430 }
2431
2432 void MacroAssembler::super_call_VM(Register oop_result,
2433 Register last_java_sp,
2434 address entry_point,
2435 int number_of_arguments,
2436 bool check_exceptions) {
2437 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2438 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2439 }
2440
2441 void MacroAssembler::super_call_VM(Register oop_result,
2442 Register last_java_sp,
2443 address entry_point,
2444 Register arg_1,
2445 bool check_exceptions) {
2446 pass_arg1(this, arg_1);
2447 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2448 }
2449
2450 void MacroAssembler::super_call_VM(Register oop_result,
2451 Register last_java_sp,
2452 address entry_point,
2453 Register arg_1,
2454 Register arg_2,
2455 bool check_exceptions) {
2456
2457 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2458 pass_arg2(this, arg_2);
2459 pass_arg1(this, arg_1);
2460 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2461 }
2462
2463 void MacroAssembler::super_call_VM(Register oop_result,
2464 Register last_java_sp,
2465 address entry_point,
2466 Register arg_1,
2467 Register arg_2,
2468 Register arg_3,
2469 bool check_exceptions) {
2470 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2471 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2472 pass_arg3(this, arg_3);
2473 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2474 pass_arg2(this, arg_2);
2475 pass_arg1(this, arg_1);
2476 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2477 }
2478
2479 void MacroAssembler::call_VM_base(Register oop_result,
2480 Register java_thread,
2481 Register last_java_sp,
2482 address entry_point,
2483 int number_of_arguments,
2484 bool check_exceptions) {
2485 // determine java_thread register
2486 if (!java_thread->is_valid()) {
2487 #ifdef _LP64
2488 java_thread = r15_thread;
2489 #else
2490 java_thread = rdi;
2491 get_thread(java_thread);
2492 #endif // LP64
2493 }
2494 // determine last_java_sp register
2495 if (!last_java_sp->is_valid()) {
2496 last_java_sp = rsp;
2497 }
2498 // debugging support
2499 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
2500 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
2501 #ifdef ASSERT
2502 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
2503 // r12 is the heapbase.
2504 LP64_ONLY(if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");)
2505 #endif // ASSERT
2506
2507 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
2508 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
2509
2510 // push java thread (becomes first argument of C function)
2511
2512 NOT_LP64(push(java_thread); number_of_arguments++);
2513 LP64_ONLY(mov(c_rarg0, r15_thread));
2514
2515 // set last Java frame before call
2516 assert(last_java_sp != rbp, "can't use ebp/rbp");
2517
2518 // Only interpreter should have to set fp
2519 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL);
2520
2521 // do the call, remove parameters
2522 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
2523
2524 // restore the thread (cannot use the pushed argument since arguments
2525 // may be overwritten by C code generated by an optimizing compiler);
2526 // however can use the register value directly if it is callee saved.
2527 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
2528 // rdi & rsi (also r15) are callee saved -> nothing to do
2529 #ifdef ASSERT
2530 guarantee(java_thread != rax, "change this code");
2531 push(rax);
2532 { Label L;
2533 get_thread(rax);
2534 cmpptr(java_thread, rax);
2535 jcc(Assembler::equal, L);
2536 STOP("MacroAssembler::call_VM_base: rdi not callee saved?");
2537 bind(L);
2538 }
2539 pop(rax);
2540 #endif
2541 } else {
2542 get_thread(java_thread);
2543 }
2544 // reset last Java frame
2545 // Only interpreter should have to clear fp
2546 reset_last_Java_frame(java_thread, true);
2547
2548 // C++ interp handles this in the interpreter
2549 check_and_handle_popframe(java_thread);
2550 check_and_handle_earlyret(java_thread);
2551
2552 if (check_exceptions) {
2553 // check for pending exceptions (java_thread is set upon return)
2554 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD);
2555 #ifndef _LP64
2556 jump_cc(Assembler::notEqual,
2557 RuntimeAddress(StubRoutines::forward_exception_entry()));
2558 #else
2559 // This used to conditionally jump to forward_exception however it is
2560 // possible if we relocate that the branch will not reach. So we must jump
2561 // around so we can always reach
2562
2563 Label ok;
2564 jcc(Assembler::equal, ok);
2565 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
2566 bind(ok);
2567 #endif // LP64
2568 }
2569
2570 // get oop result if there is one and reset the value in the thread
2571 if (oop_result->is_valid()) {
2572 get_vm_result(oop_result, java_thread);
2573 }
2574 }
2575
2576 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
2577
2578 // Calculate the value for last_Java_sp
2579 // somewhat subtle. call_VM does an intermediate call
2580 // which places a return address on the stack just under the
2581 // stack pointer as the user finsihed with it. This allows
2582 // use to retrieve last_Java_pc from last_Java_sp[-1].
2583 // On 32bit we then have to push additional args on the stack to accomplish
2584 // the actual requested call. On 64bit call_VM only can use register args
2585 // so the only extra space is the return address that call_VM created.
2586 // This hopefully explains the calculations here.
2587
2588 #ifdef _LP64
2589 // We've pushed one address, correct last_Java_sp
2590 lea(rax, Address(rsp, wordSize));
2591 #else
2592 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
2593 #endif // LP64
2594
2595 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
2596
2597 }
2598
2599 // Use this method when MacroAssembler version of call_VM_leaf_base() should be called from Interpreter.
2600 void MacroAssembler::call_VM_leaf0(address entry_point) {
2601 MacroAssembler::call_VM_leaf_base(entry_point, 0);
2602 }
2603
2604 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
2605 call_VM_leaf_base(entry_point, number_of_arguments);
2606 }
2607
2608 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
2609 pass_arg0(this, arg_0);
2610 call_VM_leaf(entry_point, 1);
2611 }
2612
2613 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2614
2615 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2616 pass_arg1(this, arg_1);
2617 pass_arg0(this, arg_0);
2618 call_VM_leaf(entry_point, 2);
2619 }
2620
2621 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2622 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2623 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2624 pass_arg2(this, arg_2);
2625 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2626 pass_arg1(this, arg_1);
2627 pass_arg0(this, arg_0);
2628 call_VM_leaf(entry_point, 3);
2629 }
2630
2631 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
2632 pass_arg0(this, arg_0);
2633 MacroAssembler::call_VM_leaf_base(entry_point, 1);
2634 }
2635
2636 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2637
2638 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2639 pass_arg1(this, arg_1);
2640 pass_arg0(this, arg_0);
2641 MacroAssembler::call_VM_leaf_base(entry_point, 2);
2642 }
2643
2644 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2645 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2646 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2647 pass_arg2(this, arg_2);
2648 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2649 pass_arg1(this, arg_1);
2650 pass_arg0(this, arg_0);
2651 MacroAssembler::call_VM_leaf_base(entry_point, 3);
2652 }
2653
2654 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
2655 LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg"));
2656 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2657 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2658 pass_arg3(this, arg_3);
2659 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2660 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2661 pass_arg2(this, arg_2);
2662 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2663 pass_arg1(this, arg_1);
2664 pass_arg0(this, arg_0);
2665 MacroAssembler::call_VM_leaf_base(entry_point, 4);
2666 }
2667
2668 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
2669 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
2670 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
2671 verify_oop(oop_result, "broken oop in call_VM_base");
2672 }
2673
2674 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
2675 movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
2676 movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD);
2677 }
2678
2679 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
2680 }
2681
2682 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
2683 }
2684
2685 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) {
2686 if (reachable(src1)) {
2687 cmpl(as_Address(src1), imm);
2688 } else {
2689 lea(rscratch1, src1);
2690 cmpl(Address(rscratch1, 0), imm);
2691 }
2692 }
2693
2694 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) {
2695 assert(!src2.is_lval(), "use cmpptr");
2696 if (reachable(src2)) {
2697 cmpl(src1, as_Address(src2));
2698 } else {
2699 lea(rscratch1, src2);
2700 cmpl(src1, Address(rscratch1, 0));
2701 }
2702 }
2703
2704 void MacroAssembler::cmp32(Register src1, int32_t imm) {
2705 Assembler::cmpl(src1, imm);
2706 }
2707
2708 void MacroAssembler::cmp32(Register src1, Address src2) {
2709 Assembler::cmpl(src1, src2);
2710 }
2711
2712 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2713 ucomisd(opr1, opr2);
2714
2715 Label L;
2716 if (unordered_is_less) {
2717 movl(dst, -1);
2718 jcc(Assembler::parity, L);
2719 jcc(Assembler::below , L);
2720 movl(dst, 0);
2721 jcc(Assembler::equal , L);
2722 increment(dst);
2723 } else { // unordered is greater
2724 movl(dst, 1);
2725 jcc(Assembler::parity, L);
2726 jcc(Assembler::above , L);
2727 movl(dst, 0);
2728 jcc(Assembler::equal , L);
2729 decrementl(dst);
2730 }
2731 bind(L);
2732 }
2733
2734 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2735 ucomiss(opr1, opr2);
2736
2737 Label L;
2738 if (unordered_is_less) {
2739 movl(dst, -1);
2740 jcc(Assembler::parity, L);
2741 jcc(Assembler::below , L);
2742 movl(dst, 0);
2743 jcc(Assembler::equal , L);
2744 increment(dst);
2745 } else { // unordered is greater
2746 movl(dst, 1);
2747 jcc(Assembler::parity, L);
2748 jcc(Assembler::above , L);
2749 movl(dst, 0);
2750 jcc(Assembler::equal , L);
2751 decrementl(dst);
2752 }
2753 bind(L);
2754 }
2755
2756
2757 void MacroAssembler::cmp8(AddressLiteral src1, int imm) {
2758 if (reachable(src1)) {
2759 cmpb(as_Address(src1), imm);
2760 } else {
2761 lea(rscratch1, src1);
2762 cmpb(Address(rscratch1, 0), imm);
2763 }
2764 }
2765
2766 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) {
2767 #ifdef _LP64
2768 if (src2.is_lval()) {
2769 movptr(rscratch1, src2);
2770 Assembler::cmpq(src1, rscratch1);
2771 } else if (reachable(src2)) {
2772 cmpq(src1, as_Address(src2));
2773 } else {
2774 lea(rscratch1, src2);
2775 Assembler::cmpq(src1, Address(rscratch1, 0));
2776 }
2777 #else
2778 if (src2.is_lval()) {
2779 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2780 } else {
2781 cmpl(src1, as_Address(src2));
2782 }
2783 #endif // _LP64
2784 }
2785
2786 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) {
2787 assert(src2.is_lval(), "not a mem-mem compare");
2788 #ifdef _LP64
2789 // moves src2's literal address
2790 movptr(rscratch1, src2);
2791 Assembler::cmpq(src1, rscratch1);
2792 #else
2793 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2794 #endif // _LP64
2795 }
2796
2797 void MacroAssembler::cmpoop(Register src1, Register src2) {
2798 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
2799 bs->obj_equals(this, src1, src2);
2800 }
2801
2802 void MacroAssembler::cmpoop(Register src1, Address src2) {
2803 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
2804 bs->obj_equals(this, src1, src2);
2805 }
2806
2807 #ifdef _LP64
2808 void MacroAssembler::cmpoop(Register src1, jobject src2) {
2809 movoop(rscratch1, src2);
2810 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
2811 bs->obj_equals(this, src1, rscratch1);
2812 }
2813 #endif
2814
2815 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) {
2816 if (reachable(adr)) {
2817 if (os::is_MP())
2818 lock();
2819 cmpxchgptr(reg, as_Address(adr));
2820 } else {
2821 lea(rscratch1, adr);
2822 if (os::is_MP())
2823 lock();
2824 cmpxchgptr(reg, Address(rscratch1, 0));
2825 }
2826 }
2827
2828 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
2829 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
2830 }
2831
2832 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) {
2833 if (reachable(src)) {
2834 Assembler::comisd(dst, as_Address(src));
2835 } else {
2836 lea(rscratch1, src);
2837 Assembler::comisd(dst, Address(rscratch1, 0));
2838 }
2839 }
2840
2841 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) {
2842 if (reachable(src)) {
2843 Assembler::comiss(dst, as_Address(src));
2844 } else {
2845 lea(rscratch1, src);
2846 Assembler::comiss(dst, Address(rscratch1, 0));
2847 }
2848 }
2849
2850
2851 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) {
2852 Condition negated_cond = negate_condition(cond);
2853 Label L;
2854 jcc(negated_cond, L);
2855 pushf(); // Preserve flags
2856 atomic_incl(counter_addr);
2857 popf();
2858 bind(L);
2859 }
2860
2861 int MacroAssembler::corrected_idivl(Register reg) {
2862 // Full implementation of Java idiv and irem; checks for
2863 // special case as described in JVM spec., p.243 & p.271.
2864 // The function returns the (pc) offset of the idivl
2865 // instruction - may be needed for implicit exceptions.
2866 //
2867 // normal case special case
2868 //
2869 // input : rax,: dividend min_int
2870 // reg: divisor (may not be rax,/rdx) -1
2871 //
2872 // output: rax,: quotient (= rax, idiv reg) min_int
2873 // rdx: remainder (= rax, irem reg) 0
2874 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
2875 const int min_int = 0x80000000;
2876 Label normal_case, special_case;
2877
2878 // check for special case
2879 cmpl(rax, min_int);
2880 jcc(Assembler::notEqual, normal_case);
2881 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
2882 cmpl(reg, -1);
2883 jcc(Assembler::equal, special_case);
2884
2885 // handle normal case
2886 bind(normal_case);
2887 cdql();
2888 int idivl_offset = offset();
2889 idivl(reg);
2890
2891 // normal and special case exit
2892 bind(special_case);
2893
2894 return idivl_offset;
2895 }
2896
2897
2898
2899 void MacroAssembler::decrementl(Register reg, int value) {
2900 if (value == min_jint) {subl(reg, value) ; return; }
2901 if (value < 0) { incrementl(reg, -value); return; }
2902 if (value == 0) { ; return; }
2903 if (value == 1 && UseIncDec) { decl(reg) ; return; }
2904 /* else */ { subl(reg, value) ; return; }
2905 }
2906
2907 void MacroAssembler::decrementl(Address dst, int value) {
2908 if (value == min_jint) {subl(dst, value) ; return; }
2909 if (value < 0) { incrementl(dst, -value); return; }
2910 if (value == 0) { ; return; }
2911 if (value == 1 && UseIncDec) { decl(dst) ; return; }
2912 /* else */ { subl(dst, value) ; return; }
2913 }
2914
2915 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
2916 assert (shift_value > 0, "illegal shift value");
2917 Label _is_positive;
2918 testl (reg, reg);
2919 jcc (Assembler::positive, _is_positive);
2920 int offset = (1 << shift_value) - 1 ;
2921
2922 if (offset == 1) {
2923 incrementl(reg);
2924 } else {
2925 addl(reg, offset);
2926 }
2927
2928 bind (_is_positive);
2929 sarl(reg, shift_value);
2930 }
2931
2932 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) {
2933 if (reachable(src)) {
2934 Assembler::divsd(dst, as_Address(src));
2935 } else {
2936 lea(rscratch1, src);
2937 Assembler::divsd(dst, Address(rscratch1, 0));
2938 }
2939 }
2940
2941 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) {
2942 if (reachable(src)) {
2943 Assembler::divss(dst, as_Address(src));
2944 } else {
2945 lea(rscratch1, src);
2946 Assembler::divss(dst, Address(rscratch1, 0));
2947 }
2948 }
2949
2950 // !defined(COMPILER2) is because of stupid core builds
2951 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2) || INCLUDE_JVMCI
2952 void MacroAssembler::empty_FPU_stack() {
2953 if (VM_Version::supports_mmx()) {
2954 emms();
2955 } else {
2956 for (int i = 8; i-- > 0; ) ffree(i);
2957 }
2958 }
2959 #endif // !LP64 || C1 || !C2 || INCLUDE_JVMCI
2960
2961
2962 void MacroAssembler::enter() {
2963 push(rbp);
2964 mov(rbp, rsp);
2965 }
2966
2967 // A 5 byte nop that is safe for patching (see patch_verified_entry)
2968 void MacroAssembler::fat_nop() {
2969 if (UseAddressNop) {
2970 addr_nop_5();
2971 } else {
2972 emit_int8(0x26); // es:
2973 emit_int8(0x2e); // cs:
2974 emit_int8(0x64); // fs:
2975 emit_int8(0x65); // gs:
2976 emit_int8((unsigned char)0x90);
2977 }
2978 }
2979
2980 void MacroAssembler::fcmp(Register tmp) {
2981 fcmp(tmp, 1, true, true);
2982 }
2983
2984 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
2985 assert(!pop_right || pop_left, "usage error");
2986 if (VM_Version::supports_cmov()) {
2987 assert(tmp == noreg, "unneeded temp");
2988 if (pop_left) {
2989 fucomip(index);
2990 } else {
2991 fucomi(index);
2992 }
2993 if (pop_right) {
2994 fpop();
2995 }
2996 } else {
2997 assert(tmp != noreg, "need temp");
2998 if (pop_left) {
2999 if (pop_right) {
3000 fcompp();
3001 } else {
3002 fcomp(index);
3003 }
3004 } else {
3005 fcom(index);
3006 }
3007 // convert FPU condition into eflags condition via rax,
3008 save_rax(tmp);
3009 fwait(); fnstsw_ax();
3010 sahf();
3011 restore_rax(tmp);
3012 }
3013 // condition codes set as follows:
3014 //
3015 // CF (corresponds to C0) if x < y
3016 // PF (corresponds to C2) if unordered
3017 // ZF (corresponds to C3) if x = y
3018 }
3019
3020 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
3021 fcmp2int(dst, unordered_is_less, 1, true, true);
3022 }
3023
3024 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
3025 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
3026 Label L;
3027 if (unordered_is_less) {
3028 movl(dst, -1);
3029 jcc(Assembler::parity, L);
3030 jcc(Assembler::below , L);
3031 movl(dst, 0);
3032 jcc(Assembler::equal , L);
3033 increment(dst);
3034 } else { // unordered is greater
3035 movl(dst, 1);
3036 jcc(Assembler::parity, L);
3037 jcc(Assembler::above , L);
3038 movl(dst, 0);
3039 jcc(Assembler::equal , L);
3040 decrementl(dst);
3041 }
3042 bind(L);
3043 }
3044
3045 void MacroAssembler::fld_d(AddressLiteral src) {
3046 fld_d(as_Address(src));
3047 }
3048
3049 void MacroAssembler::fld_s(AddressLiteral src) {
3050 fld_s(as_Address(src));
3051 }
3052
3053 void MacroAssembler::fld_x(AddressLiteral src) {
3054 Assembler::fld_x(as_Address(src));
3055 }
3056
3057 void MacroAssembler::fldcw(AddressLiteral src) {
3058 Assembler::fldcw(as_Address(src));
3059 }
3060
3061 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src) {
3062 if (reachable(src)) {
3063 Assembler::mulpd(dst, as_Address(src));
3064 } else {
3065 lea(rscratch1, src);
3066 Assembler::mulpd(dst, Address(rscratch1, 0));
3067 }
3068 }
3069
3070 void MacroAssembler::increase_precision() {
3071 subptr(rsp, BytesPerWord);
3072 fnstcw(Address(rsp, 0));
3073 movl(rax, Address(rsp, 0));
3074 orl(rax, 0x300);
3075 push(rax);
3076 fldcw(Address(rsp, 0));
3077 pop(rax);
3078 }
3079
3080 void MacroAssembler::restore_precision() {
3081 fldcw(Address(rsp, 0));
3082 addptr(rsp, BytesPerWord);
3083 }
3084
3085 void MacroAssembler::fpop() {
3086 ffree();
3087 fincstp();
3088 }
3089
3090 void MacroAssembler::load_float(Address src) {
3091 if (UseSSE >= 1) {
3092 movflt(xmm0, src);
3093 } else {
3094 LP64_ONLY(ShouldNotReachHere());
3095 NOT_LP64(fld_s(src));
3096 }
3097 }
3098
3099 void MacroAssembler::store_float(Address dst) {
3100 if (UseSSE >= 1) {
3101 movflt(dst, xmm0);
3102 } else {
3103 LP64_ONLY(ShouldNotReachHere());
3104 NOT_LP64(fstp_s(dst));
3105 }
3106 }
3107
3108 void MacroAssembler::load_double(Address src) {
3109 if (UseSSE >= 2) {
3110 movdbl(xmm0, src);
3111 } else {
3112 LP64_ONLY(ShouldNotReachHere());
3113 NOT_LP64(fld_d(src));
3114 }
3115 }
3116
3117 void MacroAssembler::store_double(Address dst) {
3118 if (UseSSE >= 2) {
3119 movdbl(dst, xmm0);
3120 } else {
3121 LP64_ONLY(ShouldNotReachHere());
3122 NOT_LP64(fstp_d(dst));
3123 }
3124 }
3125
3126 void MacroAssembler::push_zmm(XMMRegister reg) {
3127 lea(rsp, Address(rsp, -64)); // Use lea to not affect flags
3128 evmovdqul(Address(rsp, 0), reg, Assembler::AVX_512bit);
3129 }
3130
3131 void MacroAssembler::pop_zmm(XMMRegister reg) {
3132 evmovdqul(reg, Address(rsp, 0), Assembler::AVX_512bit);
3133 lea(rsp, Address(rsp, 64)); // Use lea to not affect flags
3134 }
3135
3136 void MacroAssembler::fremr(Register tmp) {
3137 save_rax(tmp);
3138 { Label L;
3139 bind(L);
3140 fprem();
3141 fwait(); fnstsw_ax();
3142 #ifdef _LP64
3143 testl(rax, 0x400);
3144 jcc(Assembler::notEqual, L);
3145 #else
3146 sahf();
3147 jcc(Assembler::parity, L);
3148 #endif // _LP64
3149 }
3150 restore_rax(tmp);
3151 // Result is in ST0.
3152 // Note: fxch & fpop to get rid of ST1
3153 // (otherwise FPU stack could overflow eventually)
3154 fxch(1);
3155 fpop();
3156 }
3157
3158 // dst = c = a * b + c
3159 void MacroAssembler::fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
3160 Assembler::vfmadd231sd(c, a, b);
3161 if (dst != c) {
3162 movdbl(dst, c);
3163 }
3164 }
3165
3166 // dst = c = a * b + c
3167 void MacroAssembler::fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
3168 Assembler::vfmadd231ss(c, a, b);
3169 if (dst != c) {
3170 movflt(dst, c);
3171 }
3172 }
3173
3174 // dst = c = a * b + c
3175 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
3176 Assembler::vfmadd231pd(c, a, b, vector_len);
3177 if (dst != c) {
3178 vmovdqu(dst, c);
3179 }
3180 }
3181
3182 // dst = c = a * b + c
3183 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
3184 Assembler::vfmadd231ps(c, a, b, vector_len);
3185 if (dst != c) {
3186 vmovdqu(dst, c);
3187 }
3188 }
3189
3190 // dst = c = a * b + c
3191 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
3192 Assembler::vfmadd231pd(c, a, b, vector_len);
3193 if (dst != c) {
3194 vmovdqu(dst, c);
3195 }
3196 }
3197
3198 // dst = c = a * b + c
3199 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
3200 Assembler::vfmadd231ps(c, a, b, vector_len);
3201 if (dst != c) {
3202 vmovdqu(dst, c);
3203 }
3204 }
3205
3206 void MacroAssembler::incrementl(AddressLiteral dst) {
3207 if (reachable(dst)) {
3208 incrementl(as_Address(dst));
3209 } else {
3210 lea(rscratch1, dst);
3211 incrementl(Address(rscratch1, 0));
3212 }
3213 }
3214
3215 void MacroAssembler::incrementl(ArrayAddress dst) {
3216 incrementl(as_Address(dst));
3217 }
3218
3219 void MacroAssembler::incrementl(Register reg, int value) {
3220 if (value == min_jint) {addl(reg, value) ; return; }
3221 if (value < 0) { decrementl(reg, -value); return; }
3222 if (value == 0) { ; return; }
3223 if (value == 1 && UseIncDec) { incl(reg) ; return; }
3224 /* else */ { addl(reg, value) ; return; }
3225 }
3226
3227 void MacroAssembler::incrementl(Address dst, int value) {
3228 if (value == min_jint) {addl(dst, value) ; return; }
3229 if (value < 0) { decrementl(dst, -value); return; }
3230 if (value == 0) { ; return; }
3231 if (value == 1 && UseIncDec) { incl(dst) ; return; }
3232 /* else */ { addl(dst, value) ; return; }
3233 }
3234
3235 void MacroAssembler::jump(AddressLiteral dst) {
3236 if (reachable(dst)) {
3237 jmp_literal(dst.target(), dst.rspec());
3238 } else {
3239 lea(rscratch1, dst);
3240 jmp(rscratch1);
3241 }
3242 }
3243
3244 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) {
3245 if (reachable(dst)) {
3246 InstructionMark im(this);
3247 relocate(dst.reloc());
3248 const int short_size = 2;
3249 const int long_size = 6;
3250 int offs = (intptr_t)dst.target() - ((intptr_t)pc());
3251 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
3252 // 0111 tttn #8-bit disp
3253 emit_int8(0x70 | cc);
3254 emit_int8((offs - short_size) & 0xFF);
3255 } else {
3256 // 0000 1111 1000 tttn #32-bit disp
3257 emit_int8(0x0F);
3258 emit_int8((unsigned char)(0x80 | cc));
3259 emit_int32(offs - long_size);
3260 }
3261 } else {
3262 #ifdef ASSERT
3263 warning("reversing conditional branch");
3264 #endif /* ASSERT */
3265 Label skip;
3266 jccb(reverse[cc], skip);
3267 lea(rscratch1, dst);
3268 Assembler::jmp(rscratch1);
3269 bind(skip);
3270 }
3271 }
3272
3273 void MacroAssembler::ldmxcsr(AddressLiteral src) {
3274 if (reachable(src)) {
3275 Assembler::ldmxcsr(as_Address(src));
3276 } else {
3277 lea(rscratch1, src);
3278 Assembler::ldmxcsr(Address(rscratch1, 0));
3279 }
3280 }
3281
3282 int MacroAssembler::load_signed_byte(Register dst, Address src) {
3283 int off;
3284 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3285 off = offset();
3286 movsbl(dst, src); // movsxb
3287 } else {
3288 off = load_unsigned_byte(dst, src);
3289 shll(dst, 24);
3290 sarl(dst, 24);
3291 }
3292 return off;
3293 }
3294
3295 // Note: load_signed_short used to be called load_signed_word.
3296 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
3297 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
3298 // The term "word" in HotSpot means a 32- or 64-bit machine word.
3299 int MacroAssembler::load_signed_short(Register dst, Address src) {
3300 int off;
3301 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3302 // This is dubious to me since it seems safe to do a signed 16 => 64 bit
3303 // version but this is what 64bit has always done. This seems to imply
3304 // that users are only using 32bits worth.
3305 off = offset();
3306 movswl(dst, src); // movsxw
3307 } else {
3308 off = load_unsigned_short(dst, src);
3309 shll(dst, 16);
3310 sarl(dst, 16);
3311 }
3312 return off;
3313 }
3314
3315 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
3316 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3317 // and "3.9 Partial Register Penalties", p. 22).
3318 int off;
3319 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
3320 off = offset();
3321 movzbl(dst, src); // movzxb
3322 } else {
3323 xorl(dst, dst);
3324 off = offset();
3325 movb(dst, src);
3326 }
3327 return off;
3328 }
3329
3330 // Note: load_unsigned_short used to be called load_unsigned_word.
3331 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
3332 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3333 // and "3.9 Partial Register Penalties", p. 22).
3334 int off;
3335 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
3336 off = offset();
3337 movzwl(dst, src); // movzxw
3338 } else {
3339 xorl(dst, dst);
3340 off = offset();
3341 movw(dst, src);
3342 }
3343 return off;
3344 }
3345
3346 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
3347 switch (size_in_bytes) {
3348 #ifndef _LP64
3349 case 8:
3350 assert(dst2 != noreg, "second dest register required");
3351 movl(dst, src);
3352 movl(dst2, src.plus_disp(BytesPerInt));
3353 break;
3354 #else
3355 case 8: movq(dst, src); break;
3356 #endif
3357 case 4: movl(dst, src); break;
3358 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
3359 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
3360 default: ShouldNotReachHere();
3361 }
3362 }
3363
3364 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
3365 switch (size_in_bytes) {
3366 #ifndef _LP64
3367 case 8:
3368 assert(src2 != noreg, "second source register required");
3369 movl(dst, src);
3370 movl(dst.plus_disp(BytesPerInt), src2);
3371 break;
3372 #else
3373 case 8: movq(dst, src); break;
3374 #endif
3375 case 4: movl(dst, src); break;
3376 case 2: movw(dst, src); break;
3377 case 1: movb(dst, src); break;
3378 default: ShouldNotReachHere();
3379 }
3380 }
3381
3382 void MacroAssembler::mov32(AddressLiteral dst, Register src) {
3383 if (reachable(dst)) {
3384 movl(as_Address(dst), src);
3385 } else {
3386 lea(rscratch1, dst);
3387 movl(Address(rscratch1, 0), src);
3388 }
3389 }
3390
3391 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
3392 if (reachable(src)) {
3393 movl(dst, as_Address(src));
3394 } else {
3395 lea(rscratch1, src);
3396 movl(dst, Address(rscratch1, 0));
3397 }
3398 }
3399
3400 // C++ bool manipulation
3401
3402 void MacroAssembler::movbool(Register dst, Address src) {
3403 if(sizeof(bool) == 1)
3404 movb(dst, src);
3405 else if(sizeof(bool) == 2)
3406 movw(dst, src);
3407 else if(sizeof(bool) == 4)
3408 movl(dst, src);
3409 else
3410 // unsupported
3411 ShouldNotReachHere();
3412 }
3413
3414 void MacroAssembler::movbool(Address dst, bool boolconst) {
3415 if(sizeof(bool) == 1)
3416 movb(dst, (int) boolconst);
3417 else if(sizeof(bool) == 2)
3418 movw(dst, (int) boolconst);
3419 else if(sizeof(bool) == 4)
3420 movl(dst, (int) boolconst);
3421 else
3422 // unsupported
3423 ShouldNotReachHere();
3424 }
3425
3426 void MacroAssembler::movbool(Address dst, Register src) {
3427 if(sizeof(bool) == 1)
3428 movb(dst, src);
3429 else if(sizeof(bool) == 2)
3430 movw(dst, src);
3431 else if(sizeof(bool) == 4)
3432 movl(dst, src);
3433 else
3434 // unsupported
3435 ShouldNotReachHere();
3436 }
3437
3438 void MacroAssembler::movbyte(ArrayAddress dst, int src) {
3439 movb(as_Address(dst), src);
3440 }
3441
3442 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src) {
3443 if (reachable(src)) {
3444 movdl(dst, as_Address(src));
3445 } else {
3446 lea(rscratch1, src);
3447 movdl(dst, Address(rscratch1, 0));
3448 }
3449 }
3450
3451 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src) {
3452 if (reachable(src)) {
3453 movq(dst, as_Address(src));
3454 } else {
3455 lea(rscratch1, src);
3456 movq(dst, Address(rscratch1, 0));
3457 }
3458 }
3459
3460 void MacroAssembler::setvectmask(Register dst, Register src) {
3461 Assembler::movl(dst, 1);
3462 Assembler::shlxl(dst, dst, src);
3463 Assembler::decl(dst);
3464 Assembler::kmovdl(k1, dst);
3465 Assembler::movl(dst, src);
3466 }
3467
3468 void MacroAssembler::restorevectmask() {
3469 Assembler::knotwl(k1, k0);
3470 }
3471
3472 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) {
3473 if (reachable(src)) {
3474 if (UseXmmLoadAndClearUpper) {
3475 movsd (dst, as_Address(src));
3476 } else {
3477 movlpd(dst, as_Address(src));
3478 }
3479 } else {
3480 lea(rscratch1, src);
3481 if (UseXmmLoadAndClearUpper) {
3482 movsd (dst, Address(rscratch1, 0));
3483 } else {
3484 movlpd(dst, Address(rscratch1, 0));
3485 }
3486 }
3487 }
3488
3489 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) {
3490 if (reachable(src)) {
3491 movss(dst, as_Address(src));
3492 } else {
3493 lea(rscratch1, src);
3494 movss(dst, Address(rscratch1, 0));
3495 }
3496 }
3497
3498 void MacroAssembler::movptr(Register dst, Register src) {
3499 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3500 }
3501
3502 void MacroAssembler::movptr(Register dst, Address src) {
3503 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3504 }
3505
3506 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
3507 void MacroAssembler::movptr(Register dst, intptr_t src) {
3508 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src));
3509 }
3510
3511 void MacroAssembler::movptr(Address dst, Register src) {
3512 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3513 }
3514
3515 void MacroAssembler::movdqu(Address dst, XMMRegister src) {
3516 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (src->encoding() > 15)) {
3517 Assembler::vextractf32x4(dst, src, 0);
3518 } else {
3519 Assembler::movdqu(dst, src);
3520 }
3521 }
3522
3523 void MacroAssembler::movdqu(XMMRegister dst, Address src) {
3524 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (dst->encoding() > 15)) {
3525 Assembler::vinsertf32x4(dst, dst, src, 0);
3526 } else {
3527 Assembler::movdqu(dst, src);
3528 }
3529 }
3530
3531 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) {
3532 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3533 Assembler::evmovdqul(dst, src, Assembler::AVX_512bit);
3534 } else {
3535 Assembler::movdqu(dst, src);
3536 }
3537 }
3538
3539 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src, Register scratchReg) {
3540 if (reachable(src)) {
3541 movdqu(dst, as_Address(src));
3542 } else {
3543 lea(scratchReg, src);
3544 movdqu(dst, Address(scratchReg, 0));
3545 }
3546 }
3547
3548 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) {
3549 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (src->encoding() > 15)) {
3550 vextractf64x4_low(dst, src);
3551 } else {
3552 Assembler::vmovdqu(dst, src);
3553 }
3554 }
3555
3556 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) {
3557 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (dst->encoding() > 15)) {
3558 vinsertf64x4_low(dst, src);
3559 } else {
3560 Assembler::vmovdqu(dst, src);
3561 }
3562 }
3563
3564 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) {
3565 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3566 Assembler::evmovdqul(dst, src, Assembler::AVX_512bit);
3567 }
3568 else {
3569 Assembler::vmovdqu(dst, src);
3570 }
3571 }
3572
3573 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src) {
3574 if (reachable(src)) {
3575 vmovdqu(dst, as_Address(src));
3576 }
3577 else {
3578 lea(rscratch1, src);
3579 vmovdqu(dst, Address(rscratch1, 0));
3580 }
3581 }
3582
3583 void MacroAssembler::evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3584 if (reachable(src)) {
3585 Assembler::evmovdquq(dst, as_Address(src), vector_len);
3586 } else {
3587 lea(rscratch, src);
3588 Assembler::evmovdquq(dst, Address(rscratch, 0), vector_len);
3589 }
3590 }
3591
3592 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src) {
3593 if (reachable(src)) {
3594 Assembler::movdqa(dst, as_Address(src));
3595 } else {
3596 lea(rscratch1, src);
3597 Assembler::movdqa(dst, Address(rscratch1, 0));
3598 }
3599 }
3600
3601 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) {
3602 if (reachable(src)) {
3603 Assembler::movsd(dst, as_Address(src));
3604 } else {
3605 lea(rscratch1, src);
3606 Assembler::movsd(dst, Address(rscratch1, 0));
3607 }
3608 }
3609
3610 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) {
3611 if (reachable(src)) {
3612 Assembler::movss(dst, as_Address(src));
3613 } else {
3614 lea(rscratch1, src);
3615 Assembler::movss(dst, Address(rscratch1, 0));
3616 }
3617 }
3618
3619 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) {
3620 if (reachable(src)) {
3621 Assembler::mulsd(dst, as_Address(src));
3622 } else {
3623 lea(rscratch1, src);
3624 Assembler::mulsd(dst, Address(rscratch1, 0));
3625 }
3626 }
3627
3628 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) {
3629 if (reachable(src)) {
3630 Assembler::mulss(dst, as_Address(src));
3631 } else {
3632 lea(rscratch1, src);
3633 Assembler::mulss(dst, Address(rscratch1, 0));
3634 }
3635 }
3636
3637 void MacroAssembler::null_check(Register reg, int offset) {
3638 if (needs_explicit_null_check(offset)) {
3639 // provoke OS NULL exception if reg = NULL by
3640 // accessing M[reg] w/o changing any (non-CC) registers
3641 // NOTE: cmpl is plenty here to provoke a segv
3642 cmpptr(rax, Address(reg, 0));
3643 // Note: should probably use testl(rax, Address(reg, 0));
3644 // may be shorter code (however, this version of
3645 // testl needs to be implemented first)
3646 } else {
3647 // nothing to do, (later) access of M[reg + offset]
3648 // will provoke OS NULL exception if reg = NULL
3649 }
3650 }
3651
3652 void MacroAssembler::os_breakpoint() {
3653 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
3654 // (e.g., MSVC can't call ps() otherwise)
3655 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
3656 }
3657
3658 void MacroAssembler::unimplemented(const char* what) {
3659 const char* buf = NULL;
3660 {
3661 ResourceMark rm;
3662 stringStream ss;
3663 ss.print("unimplemented: %s", what);
3664 buf = code_string(ss.as_string());
3665 }
3666 stop(buf);
3667 }
3668
3669 #ifdef _LP64
3670 #define XSTATE_BV 0x200
3671 #endif
3672
3673 void MacroAssembler::pop_CPU_state() {
3674 pop_FPU_state();
3675 pop_IU_state();
3676 }
3677
3678 void MacroAssembler::pop_FPU_state() {
3679 #ifndef _LP64
3680 frstor(Address(rsp, 0));
3681 #else
3682 fxrstor(Address(rsp, 0));
3683 #endif
3684 addptr(rsp, FPUStateSizeInWords * wordSize);
3685 }
3686
3687 void MacroAssembler::pop_IU_state() {
3688 popa();
3689 LP64_ONLY(addq(rsp, 8));
3690 popf();
3691 }
3692
3693 // Save Integer and Float state
3694 // Warning: Stack must be 16 byte aligned (64bit)
3695 void MacroAssembler::push_CPU_state() {
3696 push_IU_state();
3697 push_FPU_state();
3698 }
3699
3700 void MacroAssembler::push_FPU_state() {
3701 subptr(rsp, FPUStateSizeInWords * wordSize);
3702 #ifndef _LP64
3703 fnsave(Address(rsp, 0));
3704 fwait();
3705 #else
3706 fxsave(Address(rsp, 0));
3707 #endif // LP64
3708 }
3709
3710 void MacroAssembler::push_IU_state() {
3711 // Push flags first because pusha kills them
3712 pushf();
3713 // Make sure rsp stays 16-byte aligned
3714 LP64_ONLY(subq(rsp, 8));
3715 pusha();
3716 }
3717
3718 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp) { // determine java_thread register
3719 if (!java_thread->is_valid()) {
3720 java_thread = rdi;
3721 get_thread(java_thread);
3722 }
3723 // we must set sp to zero to clear frame
3724 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
3725 if (clear_fp) {
3726 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
3727 }
3728
3729 // Always clear the pc because it could have been set by make_walkable()
3730 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
3731
3732 vzeroupper();
3733 }
3734
3735 void MacroAssembler::restore_rax(Register tmp) {
3736 if (tmp == noreg) pop(rax);
3737 else if (tmp != rax) mov(rax, tmp);
3738 }
3739
3740 void MacroAssembler::round_to(Register reg, int modulus) {
3741 addptr(reg, modulus - 1);
3742 andptr(reg, -modulus);
3743 }
3744
3745 void MacroAssembler::save_rax(Register tmp) {
3746 if (tmp == noreg) push(rax);
3747 else if (tmp != rax) mov(tmp, rax);
3748 }
3749
3750 // Write serialization page so VM thread can do a pseudo remote membar.
3751 // We use the current thread pointer to calculate a thread specific
3752 // offset to write to within the page. This minimizes bus traffic
3753 // due to cache line collision.
3754 void MacroAssembler::serialize_memory(Register thread, Register tmp) {
3755 movl(tmp, thread);
3756 shrl(tmp, os::get_serialize_page_shift_count());
3757 andl(tmp, (os::vm_page_size() - sizeof(int)));
3758
3759 Address index(noreg, tmp, Address::times_1);
3760 ExternalAddress page(os::get_memory_serialize_page());
3761
3762 // Size of store must match masking code above
3763 movl(as_Address(ArrayAddress(page, index)), tmp);
3764 }
3765
3766 void MacroAssembler::safepoint_poll(Label& slow_path, Register thread_reg, Register temp_reg) {
3767 if (SafepointMechanism::uses_thread_local_poll()) {
3768 #ifdef _LP64
3769 assert(thread_reg == r15_thread, "should be");
3770 #else
3771 if (thread_reg == noreg) {
3772 thread_reg = temp_reg;
3773 get_thread(thread_reg);
3774 }
3775 #endif
3776 testb(Address(thread_reg, Thread::polling_page_offset()), SafepointMechanism::poll_bit());
3777 jcc(Assembler::notZero, slow_path); // handshake bit set implies poll
3778 } else {
3779 cmp32(ExternalAddress(SafepointSynchronize::address_of_state()),
3780 SafepointSynchronize::_not_synchronized);
3781 jcc(Assembler::notEqual, slow_path);
3782 }
3783 }
3784
3785 // Calls to C land
3786 //
3787 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
3788 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
3789 // has to be reset to 0. This is required to allow proper stack traversal.
3790 void MacroAssembler::set_last_Java_frame(Register java_thread,
3791 Register last_java_sp,
3792 Register last_java_fp,
3793 address last_java_pc) {
3794 vzeroupper();
3795 // determine java_thread register
3796 if (!java_thread->is_valid()) {
3797 java_thread = rdi;
3798 get_thread(java_thread);
3799 }
3800 // determine last_java_sp register
3801 if (!last_java_sp->is_valid()) {
3802 last_java_sp = rsp;
3803 }
3804
3805 // last_java_fp is optional
3806
3807 if (last_java_fp->is_valid()) {
3808 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
3809 }
3810
3811 // last_java_pc is optional
3812
3813 if (last_java_pc != NULL) {
3814 lea(Address(java_thread,
3815 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()),
3816 InternalAddress(last_java_pc));
3817
3818 }
3819 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
3820 }
3821
3822 void MacroAssembler::shlptr(Register dst, int imm8) {
3823 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
3824 }
3825
3826 void MacroAssembler::shrptr(Register dst, int imm8) {
3827 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
3828 }
3829
3830 void MacroAssembler::sign_extend_byte(Register reg) {
3831 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
3832 movsbl(reg, reg); // movsxb
3833 } else {
3834 shll(reg, 24);
3835 sarl(reg, 24);
3836 }
3837 }
3838
3839 void MacroAssembler::sign_extend_short(Register reg) {
3840 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3841 movswl(reg, reg); // movsxw
3842 } else {
3843 shll(reg, 16);
3844 sarl(reg, 16);
3845 }
3846 }
3847
3848 void MacroAssembler::testl(Register dst, AddressLiteral src) {
3849 assert(reachable(src), "Address should be reachable");
3850 testl(dst, as_Address(src));
3851 }
3852
3853 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
3854 int dst_enc = dst->encoding();
3855 int src_enc = src->encoding();
3856 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
3857 Assembler::pcmpeqb(dst, src);
3858 } else if ((dst_enc < 16) && (src_enc < 16)) {
3859 Assembler::pcmpeqb(dst, src);
3860 } else if (src_enc < 16) {
3861 push_zmm(xmm0);
3862 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3863 Assembler::pcmpeqb(xmm0, src);
3864 movdqu(dst, xmm0);
3865 pop_zmm(xmm0);
3866 } else if (dst_enc < 16) {
3867 push_zmm(xmm0);
3868 evmovdqul(xmm0, src, Assembler::AVX_512bit);
3869 Assembler::pcmpeqb(dst, xmm0);
3870 pop_zmm(xmm0);
3871 } else {
3872 push_zmm(xmm0);
3873 push_zmm(xmm1);
3874 movdqu(xmm0, src);
3875 movdqu(xmm1, dst);
3876 Assembler::pcmpeqb(xmm1, xmm0);
3877 movdqu(dst, xmm1);
3878 pop_zmm(xmm1);
3879 pop_zmm(xmm0);
3880 }
3881 }
3882
3883 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3884 int dst_enc = dst->encoding();
3885 int src_enc = src->encoding();
3886 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
3887 Assembler::pcmpeqw(dst, src);
3888 } else if ((dst_enc < 16) && (src_enc < 16)) {
3889 Assembler::pcmpeqw(dst, src);
3890 } else if (src_enc < 16) {
3891 push_zmm(xmm0);
3892 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3893 Assembler::pcmpeqw(xmm0, src);
3894 movdqu(dst, xmm0);
3895 pop_zmm(xmm0);
3896 } else if (dst_enc < 16) {
3897 push_zmm(xmm0);
3898 evmovdqul(xmm0, src, Assembler::AVX_512bit);
3899 Assembler::pcmpeqw(dst, xmm0);
3900 pop_zmm(xmm0);
3901 } else {
3902 push_zmm(xmm0);
3903 push_zmm(xmm1);
3904 movdqu(xmm0, src);
3905 movdqu(xmm1, dst);
3906 Assembler::pcmpeqw(xmm1, xmm0);
3907 movdqu(dst, xmm1);
3908 pop_zmm(xmm1);
3909 pop_zmm(xmm0);
3910 }
3911 }
3912
3913 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3914 int dst_enc = dst->encoding();
3915 if (dst_enc < 16) {
3916 Assembler::pcmpestri(dst, src, imm8);
3917 } else {
3918 push_zmm(xmm0);
3919 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3920 Assembler::pcmpestri(xmm0, src, imm8);
3921 movdqu(dst, xmm0);
3922 pop_zmm(xmm0);
3923 }
3924 }
3925
3926 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3927 int dst_enc = dst->encoding();
3928 int src_enc = src->encoding();
3929 if ((dst_enc < 16) && (src_enc < 16)) {
3930 Assembler::pcmpestri(dst, src, imm8);
3931 } else if (src_enc < 16) {
3932 push_zmm(xmm0);
3933 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3934 Assembler::pcmpestri(xmm0, src, imm8);
3935 movdqu(dst, xmm0);
3936 pop_zmm(xmm0);
3937 } else if (dst_enc < 16) {
3938 push_zmm(xmm0);
3939 evmovdqul(xmm0, src, Assembler::AVX_512bit);
3940 Assembler::pcmpestri(dst, xmm0, imm8);
3941 pop_zmm(xmm0);
3942 } else {
3943 push_zmm(xmm0);
3944 push_zmm(xmm1);
3945 movdqu(xmm0, src);
3946 movdqu(xmm1, dst);
3947 Assembler::pcmpestri(xmm1, xmm0, imm8);
3948 movdqu(dst, xmm1);
3949 pop_zmm(xmm1);
3950 pop_zmm(xmm0);
3951 }
3952 }
3953
3954 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3955 int dst_enc = dst->encoding();
3956 int src_enc = src->encoding();
3957 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
3958 Assembler::pmovzxbw(dst, src);
3959 } else if ((dst_enc < 16) && (src_enc < 16)) {
3960 Assembler::pmovzxbw(dst, src);
3961 } else if (src_enc < 16) {
3962 push_zmm(xmm0);
3963 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3964 Assembler::pmovzxbw(xmm0, src);
3965 movdqu(dst, xmm0);
3966 pop_zmm(xmm0);
3967 } else if (dst_enc < 16) {
3968 push_zmm(xmm0);
3969 evmovdqul(xmm0, src, Assembler::AVX_512bit);
3970 Assembler::pmovzxbw(dst, xmm0);
3971 pop_zmm(xmm0);
3972 } else {
3973 push_zmm(xmm0);
3974 push_zmm(xmm1);
3975 movdqu(xmm0, src);
3976 movdqu(xmm1, dst);
3977 Assembler::pmovzxbw(xmm1, xmm0);
3978 movdqu(dst, xmm1);
3979 pop_zmm(xmm1);
3980 pop_zmm(xmm0);
3981 }
3982 }
3983
3984 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) {
3985 int dst_enc = dst->encoding();
3986 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
3987 Assembler::pmovzxbw(dst, src);
3988 } else if (dst_enc < 16) {
3989 Assembler::pmovzxbw(dst, src);
3990 } else {
3991 push_zmm(xmm0);
3992 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3993 Assembler::pmovzxbw(xmm0, src);
3994 movdqu(dst, xmm0);
3995 pop_zmm(xmm0);
3996 }
3997 }
3998
3999 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) {
4000 int src_enc = src->encoding();
4001 if (src_enc < 16) {
4002 Assembler::pmovmskb(dst, src);
4003 } else {
4004 push_zmm(xmm0);
4005 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4006 Assembler::pmovmskb(dst, xmm0);
4007 pop_zmm(xmm0);
4008 }
4009 }
4010
4011 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) {
4012 int dst_enc = dst->encoding();
4013 int src_enc = src->encoding();
4014 if ((dst_enc < 16) && (src_enc < 16)) {
4015 Assembler::ptest(dst, src);
4016 } else if (src_enc < 16) {
4017 push_zmm(xmm0);
4018 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4019 Assembler::ptest(xmm0, src);
4020 pop_zmm(xmm0);
4021 } else if (dst_enc < 16) {
4022 push_zmm(xmm0);
4023 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4024 Assembler::ptest(dst, xmm0);
4025 pop_zmm(xmm0);
4026 } else {
4027 push_zmm(xmm0);
4028 push_zmm(xmm1);
4029 movdqu(xmm0, src);
4030 movdqu(xmm1, dst);
4031 Assembler::ptest(xmm1, xmm0);
4032 pop_zmm(xmm1);
4033 pop_zmm(xmm0);
4034 }
4035 }
4036
4037 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) {
4038 if (reachable(src)) {
4039 Assembler::sqrtsd(dst, as_Address(src));
4040 } else {
4041 lea(rscratch1, src);
4042 Assembler::sqrtsd(dst, Address(rscratch1, 0));
4043 }
4044 }
4045
4046 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) {
4047 if (reachable(src)) {
4048 Assembler::sqrtss(dst, as_Address(src));
4049 } else {
4050 lea(rscratch1, src);
4051 Assembler::sqrtss(dst, Address(rscratch1, 0));
4052 }
4053 }
4054
4055 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) {
4056 if (reachable(src)) {
4057 Assembler::subsd(dst, as_Address(src));
4058 } else {
4059 lea(rscratch1, src);
4060 Assembler::subsd(dst, Address(rscratch1, 0));
4061 }
4062 }
4063
4064 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) {
4065 if (reachable(src)) {
4066 Assembler::subss(dst, as_Address(src));
4067 } else {
4068 lea(rscratch1, src);
4069 Assembler::subss(dst, Address(rscratch1, 0));
4070 }
4071 }
4072
4073 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) {
4074 if (reachable(src)) {
4075 Assembler::ucomisd(dst, as_Address(src));
4076 } else {
4077 lea(rscratch1, src);
4078 Assembler::ucomisd(dst, Address(rscratch1, 0));
4079 }
4080 }
4081
4082 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) {
4083 if (reachable(src)) {
4084 Assembler::ucomiss(dst, as_Address(src));
4085 } else {
4086 lea(rscratch1, src);
4087 Assembler::ucomiss(dst, Address(rscratch1, 0));
4088 }
4089 }
4090
4091 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) {
4092 // Used in sign-bit flipping with aligned address.
4093 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
4094 if (reachable(src)) {
4095 Assembler::xorpd(dst, as_Address(src));
4096 } else {
4097 lea(rscratch1, src);
4098 Assembler::xorpd(dst, Address(rscratch1, 0));
4099 }
4100 }
4101
4102 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) {
4103 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
4104 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
4105 }
4106 else {
4107 Assembler::xorpd(dst, src);
4108 }
4109 }
4110
4111 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) {
4112 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
4113 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
4114 } else {
4115 Assembler::xorps(dst, src);
4116 }
4117 }
4118
4119 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) {
4120 // Used in sign-bit flipping with aligned address.
4121 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
4122 if (reachable(src)) {
4123 Assembler::xorps(dst, as_Address(src));
4124 } else {
4125 lea(rscratch1, src);
4126 Assembler::xorps(dst, Address(rscratch1, 0));
4127 }
4128 }
4129
4130 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src) {
4131 // Used in sign-bit flipping with aligned address.
4132 bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
4133 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
4134 if (reachable(src)) {
4135 Assembler::pshufb(dst, as_Address(src));
4136 } else {
4137 lea(rscratch1, src);
4138 Assembler::pshufb(dst, Address(rscratch1, 0));
4139 }
4140 }
4141
4142 // AVX 3-operands instructions
4143
4144 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4145 if (reachable(src)) {
4146 vaddsd(dst, nds, as_Address(src));
4147 } else {
4148 lea(rscratch1, src);
4149 vaddsd(dst, nds, Address(rscratch1, 0));
4150 }
4151 }
4152
4153 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4154 if (reachable(src)) {
4155 vaddss(dst, nds, as_Address(src));
4156 } else {
4157 lea(rscratch1, src);
4158 vaddss(dst, nds, Address(rscratch1, 0));
4159 }
4160 }
4161
4162 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) {
4163 int dst_enc = dst->encoding();
4164 int nds_enc = nds->encoding();
4165 int src_enc = src->encoding();
4166 if ((dst_enc < 16) && (nds_enc < 16)) {
4167 vandps(dst, nds, negate_field, vector_len);
4168 } else if ((src_enc < 16) && (dst_enc < 16)) {
4169 // Use src scratch register
4170 evmovdqul(src, nds, Assembler::AVX_512bit);
4171 vandps(dst, src, negate_field, vector_len);
4172 } else if (dst_enc < 16) {
4173 evmovdqul(dst, nds, Assembler::AVX_512bit);
4174 vandps(dst, dst, negate_field, vector_len);
4175 } else if (nds_enc < 16) {
4176 vandps(nds, nds, negate_field, vector_len);
4177 evmovdqul(dst, nds, Assembler::AVX_512bit);
4178 } else if (src_enc < 16) {
4179 evmovdqul(src, nds, Assembler::AVX_512bit);
4180 vandps(src, src, negate_field, vector_len);
4181 evmovdqul(dst, src, Assembler::AVX_512bit);
4182 } else {
4183 if (src_enc != dst_enc) {
4184 // Use src scratch register
4185 evmovdqul(src, xmm0, Assembler::AVX_512bit);
4186 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4187 vandps(xmm0, xmm0, negate_field, vector_len);
4188 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4189 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4190 } else {
4191 push_zmm(xmm0);
4192 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4193 vandps(xmm0, xmm0, negate_field, vector_len);
4194 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4195 pop_zmm(xmm0);
4196 }
4197 }
4198 }
4199
4200 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) {
4201 int dst_enc = dst->encoding();
4202 int nds_enc = nds->encoding();
4203 int src_enc = src->encoding();
4204 if ((dst_enc < 16) && (nds_enc < 16)) {
4205 vandpd(dst, nds, negate_field, vector_len);
4206 } else if ((src_enc < 16) && (dst_enc < 16)) {
4207 // Use src scratch register
4208 evmovdqul(src, nds, Assembler::AVX_512bit);
4209 vandpd(dst, src, negate_field, vector_len);
4210 } else if (dst_enc < 16) {
4211 evmovdqul(dst, nds, Assembler::AVX_512bit);
4212 vandpd(dst, dst, negate_field, vector_len);
4213 } else if (nds_enc < 16) {
4214 vandpd(nds, nds, negate_field, vector_len);
4215 evmovdqul(dst, nds, Assembler::AVX_512bit);
4216 } else if (src_enc < 16) {
4217 evmovdqul(src, nds, Assembler::AVX_512bit);
4218 vandpd(src, src, negate_field, vector_len);
4219 evmovdqul(dst, src, Assembler::AVX_512bit);
4220 } else {
4221 if (src_enc != dst_enc) {
4222 evmovdqul(src, xmm0, Assembler::AVX_512bit);
4223 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4224 vandpd(xmm0, xmm0, negate_field, vector_len);
4225 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4226 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4227 } else {
4228 push_zmm(xmm0);
4229 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4230 vandpd(xmm0, xmm0, negate_field, vector_len);
4231 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4232 pop_zmm(xmm0);
4233 }
4234 }
4235 }
4236
4237 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4238 int dst_enc = dst->encoding();
4239 int nds_enc = nds->encoding();
4240 int src_enc = src->encoding();
4241 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4242 Assembler::vpaddb(dst, nds, src, vector_len);
4243 } else if ((dst_enc < 16) && (src_enc < 16)) {
4244 Assembler::vpaddb(dst, dst, src, vector_len);
4245 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4246 // use nds as scratch for src
4247 evmovdqul(nds, src, Assembler::AVX_512bit);
4248 Assembler::vpaddb(dst, dst, nds, vector_len);
4249 } else if ((src_enc < 16) && (nds_enc < 16)) {
4250 // use nds as scratch for dst
4251 evmovdqul(nds, dst, Assembler::AVX_512bit);
4252 Assembler::vpaddb(nds, nds, src, vector_len);
4253 evmovdqul(dst, nds, Assembler::AVX_512bit);
4254 } else if (dst_enc < 16) {
4255 // use nds as scatch for xmm0 to hold src
4256 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4257 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4258 Assembler::vpaddb(dst, dst, xmm0, vector_len);
4259 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4260 } else {
4261 // worse case scenario, all regs are in the upper bank
4262 push_zmm(xmm1);
4263 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4264 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4265 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4266 Assembler::vpaddb(xmm0, xmm0, xmm1, vector_len);
4267 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4268 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4269 pop_zmm(xmm1);
4270 }
4271 }
4272
4273 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4274 int dst_enc = dst->encoding();
4275 int nds_enc = nds->encoding();
4276 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4277 Assembler::vpaddb(dst, nds, src, vector_len);
4278 } else if (dst_enc < 16) {
4279 Assembler::vpaddb(dst, dst, src, vector_len);
4280 } else if (nds_enc < 16) {
4281 // implies dst_enc in upper bank with src as scratch
4282 evmovdqul(nds, dst, Assembler::AVX_512bit);
4283 Assembler::vpaddb(nds, nds, src, vector_len);
4284 evmovdqul(dst, nds, Assembler::AVX_512bit);
4285 } else {
4286 // worse case scenario, all regs in upper bank
4287 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4288 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4289 Assembler::vpaddb(xmm0, xmm0, src, vector_len);
4290 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4291 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4292 }
4293 }
4294
4295 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4296 int dst_enc = dst->encoding();
4297 int nds_enc = nds->encoding();
4298 int src_enc = src->encoding();
4299 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4300 Assembler::vpaddw(dst, nds, src, vector_len);
4301 } else if ((dst_enc < 16) && (src_enc < 16)) {
4302 Assembler::vpaddw(dst, dst, src, vector_len);
4303 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4304 // use nds as scratch for src
4305 evmovdqul(nds, src, Assembler::AVX_512bit);
4306 Assembler::vpaddw(dst, dst, nds, vector_len);
4307 } else if ((src_enc < 16) && (nds_enc < 16)) {
4308 // use nds as scratch for dst
4309 evmovdqul(nds, dst, Assembler::AVX_512bit);
4310 Assembler::vpaddw(nds, nds, src, vector_len);
4311 evmovdqul(dst, nds, Assembler::AVX_512bit);
4312 } else if (dst_enc < 16) {
4313 // use nds as scatch for xmm0 to hold src
4314 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4315 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4316 Assembler::vpaddw(dst, dst, xmm0, vector_len);
4317 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4318 } else {
4319 // worse case scenario, all regs are in the upper bank
4320 push_zmm(xmm1);
4321 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4322 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4323 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4324 Assembler::vpaddw(xmm0, xmm0, xmm1, vector_len);
4325 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4326 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4327 pop_zmm(xmm1);
4328 }
4329 }
4330
4331 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4332 int dst_enc = dst->encoding();
4333 int nds_enc = nds->encoding();
4334 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4335 Assembler::vpaddw(dst, nds, src, vector_len);
4336 } else if (dst_enc < 16) {
4337 Assembler::vpaddw(dst, dst, src, vector_len);
4338 } else if (nds_enc < 16) {
4339 // implies dst_enc in upper bank with nds as scratch
4340 evmovdqul(nds, dst, Assembler::AVX_512bit);
4341 Assembler::vpaddw(nds, nds, src, vector_len);
4342 evmovdqul(dst, nds, Assembler::AVX_512bit);
4343 } else {
4344 // worse case scenario, all regs in upper bank
4345 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4346 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4347 Assembler::vpaddw(xmm0, xmm0, src, vector_len);
4348 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4349 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4350 }
4351 }
4352
4353 void MacroAssembler::vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
4354 if (reachable(src)) {
4355 Assembler::vpand(dst, nds, as_Address(src), vector_len);
4356 } else {
4357 lea(rscratch1, src);
4358 Assembler::vpand(dst, nds, Address(rscratch1, 0), vector_len);
4359 }
4360 }
4361
4362 void MacroAssembler::vpbroadcastw(XMMRegister dst, XMMRegister src) {
4363 int dst_enc = dst->encoding();
4364 int src_enc = src->encoding();
4365 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4366 Assembler::vpbroadcastw(dst, src);
4367 } else if ((dst_enc < 16) && (src_enc < 16)) {
4368 Assembler::vpbroadcastw(dst, src);
4369 } else if (src_enc < 16) {
4370 push_zmm(xmm0);
4371 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4372 Assembler::vpbroadcastw(xmm0, src);
4373 movdqu(dst, xmm0);
4374 pop_zmm(xmm0);
4375 } else if (dst_enc < 16) {
4376 push_zmm(xmm0);
4377 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4378 Assembler::vpbroadcastw(dst, xmm0);
4379 pop_zmm(xmm0);
4380 } else {
4381 push_zmm(xmm0);
4382 push_zmm(xmm1);
4383 movdqu(xmm0, src);
4384 movdqu(xmm1, dst);
4385 Assembler::vpbroadcastw(xmm1, xmm0);
4386 movdqu(dst, xmm1);
4387 pop_zmm(xmm1);
4388 pop_zmm(xmm0);
4389 }
4390 }
4391
4392 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4393 int dst_enc = dst->encoding();
4394 int nds_enc = nds->encoding();
4395 int src_enc = src->encoding();
4396 assert(dst_enc == nds_enc, "");
4397 if ((dst_enc < 16) && (src_enc < 16)) {
4398 Assembler::vpcmpeqb(dst, nds, src, vector_len);
4399 } else if (src_enc < 16) {
4400 push_zmm(xmm0);
4401 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4402 Assembler::vpcmpeqb(xmm0, xmm0, src, vector_len);
4403 movdqu(dst, xmm0);
4404 pop_zmm(xmm0);
4405 } else if (dst_enc < 16) {
4406 push_zmm(xmm0);
4407 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4408 Assembler::vpcmpeqb(dst, dst, xmm0, vector_len);
4409 pop_zmm(xmm0);
4410 } else {
4411 push_zmm(xmm0);
4412 push_zmm(xmm1);
4413 movdqu(xmm0, src);
4414 movdqu(xmm1, dst);
4415 Assembler::vpcmpeqb(xmm1, xmm1, xmm0, vector_len);
4416 movdqu(dst, xmm1);
4417 pop_zmm(xmm1);
4418 pop_zmm(xmm0);
4419 }
4420 }
4421
4422 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4423 int dst_enc = dst->encoding();
4424 int nds_enc = nds->encoding();
4425 int src_enc = src->encoding();
4426 assert(dst_enc == nds_enc, "");
4427 if ((dst_enc < 16) && (src_enc < 16)) {
4428 Assembler::vpcmpeqw(dst, nds, src, vector_len);
4429 } else if (src_enc < 16) {
4430 push_zmm(xmm0);
4431 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4432 Assembler::vpcmpeqw(xmm0, xmm0, src, vector_len);
4433 movdqu(dst, xmm0);
4434 pop_zmm(xmm0);
4435 } else if (dst_enc < 16) {
4436 push_zmm(xmm0);
4437 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4438 Assembler::vpcmpeqw(dst, dst, xmm0, vector_len);
4439 pop_zmm(xmm0);
4440 } else {
4441 push_zmm(xmm0);
4442 push_zmm(xmm1);
4443 movdqu(xmm0, src);
4444 movdqu(xmm1, dst);
4445 Assembler::vpcmpeqw(xmm1, xmm1, xmm0, vector_len);
4446 movdqu(dst, xmm1);
4447 pop_zmm(xmm1);
4448 pop_zmm(xmm0);
4449 }
4450 }
4451
4452 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
4453 int dst_enc = dst->encoding();
4454 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4455 Assembler::vpmovzxbw(dst, src, vector_len);
4456 } else if (dst_enc < 16) {
4457 Assembler::vpmovzxbw(dst, src, vector_len);
4458 } else {
4459 push_zmm(xmm0);
4460 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4461 Assembler::vpmovzxbw(xmm0, src, vector_len);
4462 movdqu(dst, xmm0);
4463 pop_zmm(xmm0);
4464 }
4465 }
4466
4467 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src) {
4468 int src_enc = src->encoding();
4469 if (src_enc < 16) {
4470 Assembler::vpmovmskb(dst, src);
4471 } else {
4472 push_zmm(xmm0);
4473 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4474 Assembler::vpmovmskb(dst, xmm0);
4475 pop_zmm(xmm0);
4476 }
4477 }
4478
4479 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4480 int dst_enc = dst->encoding();
4481 int nds_enc = nds->encoding();
4482 int src_enc = src->encoding();
4483 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4484 Assembler::vpmullw(dst, nds, src, vector_len);
4485 } else if ((dst_enc < 16) && (src_enc < 16)) {
4486 Assembler::vpmullw(dst, dst, src, vector_len);
4487 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4488 // use nds as scratch for src
4489 evmovdqul(nds, src, Assembler::AVX_512bit);
4490 Assembler::vpmullw(dst, dst, nds, vector_len);
4491 } else if ((src_enc < 16) && (nds_enc < 16)) {
4492 // use nds as scratch for dst
4493 evmovdqul(nds, dst, Assembler::AVX_512bit);
4494 Assembler::vpmullw(nds, nds, src, vector_len);
4495 evmovdqul(dst, nds, Assembler::AVX_512bit);
4496 } else if (dst_enc < 16) {
4497 // use nds as scatch for xmm0 to hold src
4498 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4499 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4500 Assembler::vpmullw(dst, dst, xmm0, vector_len);
4501 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4502 } else {
4503 // worse case scenario, all regs are in the upper bank
4504 push_zmm(xmm1);
4505 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4506 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4507 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4508 Assembler::vpmullw(xmm0, xmm0, xmm1, vector_len);
4509 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4510 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4511 pop_zmm(xmm1);
4512 }
4513 }
4514
4515 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4516 int dst_enc = dst->encoding();
4517 int nds_enc = nds->encoding();
4518 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4519 Assembler::vpmullw(dst, nds, src, vector_len);
4520 } else if (dst_enc < 16) {
4521 Assembler::vpmullw(dst, dst, src, vector_len);
4522 } else if (nds_enc < 16) {
4523 // implies dst_enc in upper bank with src as scratch
4524 evmovdqul(nds, dst, Assembler::AVX_512bit);
4525 Assembler::vpmullw(nds, nds, src, vector_len);
4526 evmovdqul(dst, nds, Assembler::AVX_512bit);
4527 } else {
4528 // worse case scenario, all regs in upper bank
4529 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4530 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4531 Assembler::vpmullw(xmm0, xmm0, src, vector_len);
4532 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4533 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4534 }
4535 }
4536
4537 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4538 int dst_enc = dst->encoding();
4539 int nds_enc = nds->encoding();
4540 int src_enc = src->encoding();
4541 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4542 Assembler::vpsubb(dst, nds, src, vector_len);
4543 } else if ((dst_enc < 16) && (src_enc < 16)) {
4544 Assembler::vpsubb(dst, dst, src, vector_len);
4545 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4546 // use nds as scratch for src
4547 evmovdqul(nds, src, Assembler::AVX_512bit);
4548 Assembler::vpsubb(dst, dst, nds, vector_len);
4549 } else if ((src_enc < 16) && (nds_enc < 16)) {
4550 // use nds as scratch for dst
4551 evmovdqul(nds, dst, Assembler::AVX_512bit);
4552 Assembler::vpsubb(nds, nds, src, vector_len);
4553 evmovdqul(dst, nds, Assembler::AVX_512bit);
4554 } else if (dst_enc < 16) {
4555 // use nds as scatch for xmm0 to hold src
4556 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4557 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4558 Assembler::vpsubb(dst, dst, xmm0, vector_len);
4559 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4560 } else {
4561 // worse case scenario, all regs are in the upper bank
4562 push_zmm(xmm1);
4563 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4564 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4565 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4566 Assembler::vpsubb(xmm0, xmm0, xmm1, vector_len);
4567 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4568 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4569 pop_zmm(xmm1);
4570 }
4571 }
4572
4573 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4574 int dst_enc = dst->encoding();
4575 int nds_enc = nds->encoding();
4576 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4577 Assembler::vpsubb(dst, nds, src, vector_len);
4578 } else if (dst_enc < 16) {
4579 Assembler::vpsubb(dst, dst, src, vector_len);
4580 } else if (nds_enc < 16) {
4581 // implies dst_enc in upper bank with src as scratch
4582 evmovdqul(nds, dst, Assembler::AVX_512bit);
4583 Assembler::vpsubb(nds, nds, src, vector_len);
4584 evmovdqul(dst, nds, Assembler::AVX_512bit);
4585 } else {
4586 // worse case scenario, all regs in upper bank
4587 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4588 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4589 Assembler::vpsubb(xmm0, xmm0, src, vector_len);
4590 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4591 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4592 }
4593 }
4594
4595 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4596 int dst_enc = dst->encoding();
4597 int nds_enc = nds->encoding();
4598 int src_enc = src->encoding();
4599 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4600 Assembler::vpsubw(dst, nds, src, vector_len);
4601 } else if ((dst_enc < 16) && (src_enc < 16)) {
4602 Assembler::vpsubw(dst, dst, src, vector_len);
4603 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4604 // use nds as scratch for src
4605 evmovdqul(nds, src, Assembler::AVX_512bit);
4606 Assembler::vpsubw(dst, dst, nds, vector_len);
4607 } else if ((src_enc < 16) && (nds_enc < 16)) {
4608 // use nds as scratch for dst
4609 evmovdqul(nds, dst, Assembler::AVX_512bit);
4610 Assembler::vpsubw(nds, nds, src, vector_len);
4611 evmovdqul(dst, nds, Assembler::AVX_512bit);
4612 } else if (dst_enc < 16) {
4613 // use nds as scatch for xmm0 to hold src
4614 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4615 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4616 Assembler::vpsubw(dst, dst, xmm0, vector_len);
4617 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4618 } else {
4619 // worse case scenario, all regs are in the upper bank
4620 push_zmm(xmm1);
4621 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4622 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4623 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4624 Assembler::vpsubw(xmm0, xmm0, xmm1, vector_len);
4625 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4626 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4627 pop_zmm(xmm1);
4628 }
4629 }
4630
4631 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4632 int dst_enc = dst->encoding();
4633 int nds_enc = nds->encoding();
4634 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4635 Assembler::vpsubw(dst, nds, src, vector_len);
4636 } else if (dst_enc < 16) {
4637 Assembler::vpsubw(dst, dst, src, vector_len);
4638 } else if (nds_enc < 16) {
4639 // implies dst_enc in upper bank with src as scratch
4640 evmovdqul(nds, dst, Assembler::AVX_512bit);
4641 Assembler::vpsubw(nds, nds, src, vector_len);
4642 evmovdqul(dst, nds, Assembler::AVX_512bit);
4643 } else {
4644 // worse case scenario, all regs in upper bank
4645 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4646 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4647 Assembler::vpsubw(xmm0, xmm0, src, vector_len);
4648 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4649 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4650 }
4651 }
4652
4653 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
4654 int dst_enc = dst->encoding();
4655 int nds_enc = nds->encoding();
4656 int shift_enc = shift->encoding();
4657 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4658 Assembler::vpsraw(dst, nds, shift, vector_len);
4659 } else if ((dst_enc < 16) && (shift_enc < 16)) {
4660 Assembler::vpsraw(dst, dst, shift, vector_len);
4661 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4662 // use nds as scratch with shift
4663 evmovdqul(nds, shift, Assembler::AVX_512bit);
4664 Assembler::vpsraw(dst, dst, nds, vector_len);
4665 } else if ((shift_enc < 16) && (nds_enc < 16)) {
4666 // use nds as scratch with dst
4667 evmovdqul(nds, dst, Assembler::AVX_512bit);
4668 Assembler::vpsraw(nds, nds, shift, vector_len);
4669 evmovdqul(dst, nds, Assembler::AVX_512bit);
4670 } else if (dst_enc < 16) {
4671 // use nds to save a copy of xmm0 and hold shift
4672 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4673 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4674 Assembler::vpsraw(dst, dst, xmm0, vector_len);
4675 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4676 } else if (nds_enc < 16) {
4677 // use nds and dst as temps
4678 evmovdqul(nds, dst, Assembler::AVX_512bit);
4679 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4680 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4681 Assembler::vpsraw(nds, nds, xmm0, vector_len);
4682 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4683 evmovdqul(dst, nds, Assembler::AVX_512bit);
4684 } else {
4685 // worse case scenario, all regs are in the upper bank
4686 push_zmm(xmm1);
4687 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4688 evmovdqul(xmm1, shift, Assembler::AVX_512bit);
4689 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4690 Assembler::vpsraw(xmm0, xmm0, xmm1, vector_len);
4691 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4692 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4693 pop_zmm(xmm1);
4694 }
4695 }
4696
4697 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
4698 int dst_enc = dst->encoding();
4699 int nds_enc = nds->encoding();
4700 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4701 Assembler::vpsraw(dst, nds, shift, vector_len);
4702 } else if (dst_enc < 16) {
4703 Assembler::vpsraw(dst, dst, shift, vector_len);
4704 } else if (nds_enc < 16) {
4705 // use nds as scratch
4706 evmovdqul(nds, dst, Assembler::AVX_512bit);
4707 Assembler::vpsraw(nds, nds, shift, vector_len);
4708 evmovdqul(dst, nds, Assembler::AVX_512bit);
4709 } else {
4710 // use nds as scratch for xmm0
4711 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4712 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4713 Assembler::vpsraw(xmm0, xmm0, shift, vector_len);
4714 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4715 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4716 }
4717 }
4718
4719 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
4720 int dst_enc = dst->encoding();
4721 int nds_enc = nds->encoding();
4722 int shift_enc = shift->encoding();
4723 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4724 Assembler::vpsrlw(dst, nds, shift, vector_len);
4725 } else if ((dst_enc < 16) && (shift_enc < 16)) {
4726 Assembler::vpsrlw(dst, dst, shift, vector_len);
4727 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4728 // use nds as scratch with shift
4729 evmovdqul(nds, shift, Assembler::AVX_512bit);
4730 Assembler::vpsrlw(dst, dst, nds, vector_len);
4731 } else if ((shift_enc < 16) && (nds_enc < 16)) {
4732 // use nds as scratch with dst
4733 evmovdqul(nds, dst, Assembler::AVX_512bit);
4734 Assembler::vpsrlw(nds, nds, shift, vector_len);
4735 evmovdqul(dst, nds, Assembler::AVX_512bit);
4736 } else if (dst_enc < 16) {
4737 // use nds to save a copy of xmm0 and hold shift
4738 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4739 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4740 Assembler::vpsrlw(dst, dst, xmm0, vector_len);
4741 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4742 } else if (nds_enc < 16) {
4743 // use nds and dst as temps
4744 evmovdqul(nds, dst, Assembler::AVX_512bit);
4745 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4746 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4747 Assembler::vpsrlw(nds, nds, xmm0, vector_len);
4748 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4749 evmovdqul(dst, nds, Assembler::AVX_512bit);
4750 } else {
4751 // worse case scenario, all regs are in the upper bank
4752 push_zmm(xmm1);
4753 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4754 evmovdqul(xmm1, shift, Assembler::AVX_512bit);
4755 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4756 Assembler::vpsrlw(xmm0, xmm0, xmm1, vector_len);
4757 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4758 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4759 pop_zmm(xmm1);
4760 }
4761 }
4762
4763 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
4764 int dst_enc = dst->encoding();
4765 int nds_enc = nds->encoding();
4766 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4767 Assembler::vpsrlw(dst, nds, shift, vector_len);
4768 } else if (dst_enc < 16) {
4769 Assembler::vpsrlw(dst, dst, shift, vector_len);
4770 } else if (nds_enc < 16) {
4771 // use nds as scratch
4772 evmovdqul(nds, dst, Assembler::AVX_512bit);
4773 Assembler::vpsrlw(nds, nds, shift, vector_len);
4774 evmovdqul(dst, nds, Assembler::AVX_512bit);
4775 } else {
4776 // use nds as scratch for xmm0
4777 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4778 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4779 Assembler::vpsrlw(xmm0, xmm0, shift, vector_len);
4780 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4781 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4782 }
4783 }
4784
4785 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
4786 int dst_enc = dst->encoding();
4787 int nds_enc = nds->encoding();
4788 int shift_enc = shift->encoding();
4789 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4790 Assembler::vpsllw(dst, nds, shift, vector_len);
4791 } else if ((dst_enc < 16) && (shift_enc < 16)) {
4792 Assembler::vpsllw(dst, dst, shift, vector_len);
4793 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4794 // use nds as scratch with shift
4795 evmovdqul(nds, shift, Assembler::AVX_512bit);
4796 Assembler::vpsllw(dst, dst, nds, vector_len);
4797 } else if ((shift_enc < 16) && (nds_enc < 16)) {
4798 // use nds as scratch with dst
4799 evmovdqul(nds, dst, Assembler::AVX_512bit);
4800 Assembler::vpsllw(nds, nds, shift, vector_len);
4801 evmovdqul(dst, nds, Assembler::AVX_512bit);
4802 } else if (dst_enc < 16) {
4803 // use nds to save a copy of xmm0 and hold shift
4804 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4805 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4806 Assembler::vpsllw(dst, dst, xmm0, vector_len);
4807 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4808 } else if (nds_enc < 16) {
4809 // use nds and dst as temps
4810 evmovdqul(nds, dst, Assembler::AVX_512bit);
4811 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4812 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4813 Assembler::vpsllw(nds, nds, xmm0, vector_len);
4814 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4815 evmovdqul(dst, nds, Assembler::AVX_512bit);
4816 } else {
4817 // worse case scenario, all regs are in the upper bank
4818 push_zmm(xmm1);
4819 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4820 evmovdqul(xmm1, shift, Assembler::AVX_512bit);
4821 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4822 Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len);
4823 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4824 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4825 pop_zmm(xmm1);
4826 }
4827 }
4828
4829 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
4830 int dst_enc = dst->encoding();
4831 int nds_enc = nds->encoding();
4832 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4833 Assembler::vpsllw(dst, nds, shift, vector_len);
4834 } else if (dst_enc < 16) {
4835 Assembler::vpsllw(dst, dst, shift, vector_len);
4836 } else if (nds_enc < 16) {
4837 // use nds as scratch
4838 evmovdqul(nds, dst, Assembler::AVX_512bit);
4839 Assembler::vpsllw(nds, nds, shift, vector_len);
4840 evmovdqul(dst, nds, Assembler::AVX_512bit);
4841 } else {
4842 // use nds as scratch for xmm0
4843 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4844 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4845 Assembler::vpsllw(xmm0, xmm0, shift, vector_len);
4846 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4847 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4848 }
4849 }
4850
4851 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) {
4852 int dst_enc = dst->encoding();
4853 int src_enc = src->encoding();
4854 if ((dst_enc < 16) && (src_enc < 16)) {
4855 Assembler::vptest(dst, src);
4856 } else if (src_enc < 16) {
4857 push_zmm(xmm0);
4858 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4859 Assembler::vptest(xmm0, src);
4860 pop_zmm(xmm0);
4861 } else if (dst_enc < 16) {
4862 push_zmm(xmm0);
4863 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4864 Assembler::vptest(dst, xmm0);
4865 pop_zmm(xmm0);
4866 } else {
4867 push_zmm(xmm0);
4868 push_zmm(xmm1);
4869 movdqu(xmm0, src);
4870 movdqu(xmm1, dst);
4871 Assembler::vptest(xmm1, xmm0);
4872 pop_zmm(xmm1);
4873 pop_zmm(xmm0);
4874 }
4875 }
4876
4877 // This instruction exists within macros, ergo we cannot control its input
4878 // when emitted through those patterns.
4879 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) {
4880 if (VM_Version::supports_avx512nobw()) {
4881 int dst_enc = dst->encoding();
4882 int src_enc = src->encoding();
4883 if (dst_enc == src_enc) {
4884 if (dst_enc < 16) {
4885 Assembler::punpcklbw(dst, src);
4886 } else {
4887 push_zmm(xmm0);
4888 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4889 Assembler::punpcklbw(xmm0, xmm0);
4890 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4891 pop_zmm(xmm0);
4892 }
4893 } else {
4894 if ((src_enc < 16) && (dst_enc < 16)) {
4895 Assembler::punpcklbw(dst, src);
4896 } else if (src_enc < 16) {
4897 push_zmm(xmm0);
4898 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4899 Assembler::punpcklbw(xmm0, src);
4900 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4901 pop_zmm(xmm0);
4902 } else if (dst_enc < 16) {
4903 push_zmm(xmm0);
4904 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4905 Assembler::punpcklbw(dst, xmm0);
4906 pop_zmm(xmm0);
4907 } else {
4908 push_zmm(xmm0);
4909 push_zmm(xmm1);
4910 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4911 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4912 Assembler::punpcklbw(xmm0, xmm1);
4913 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4914 pop_zmm(xmm1);
4915 pop_zmm(xmm0);
4916 }
4917 }
4918 } else {
4919 Assembler::punpcklbw(dst, src);
4920 }
4921 }
4922
4923 void MacroAssembler::pshufd(XMMRegister dst, Address src, int mode) {
4924 if (VM_Version::supports_avx512vl()) {
4925 Assembler::pshufd(dst, src, mode);
4926 } else {
4927 int dst_enc = dst->encoding();
4928 if (dst_enc < 16) {
4929 Assembler::pshufd(dst, src, mode);
4930 } else {
4931 push_zmm(xmm0);
4932 Assembler::pshufd(xmm0, src, mode);
4933 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4934 pop_zmm(xmm0);
4935 }
4936 }
4937 }
4938
4939 // This instruction exists within macros, ergo we cannot control its input
4940 // when emitted through those patterns.
4941 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
4942 if (VM_Version::supports_avx512nobw()) {
4943 int dst_enc = dst->encoding();
4944 int src_enc = src->encoding();
4945 if (dst_enc == src_enc) {
4946 if (dst_enc < 16) {
4947 Assembler::pshuflw(dst, src, mode);
4948 } else {
4949 push_zmm(xmm0);
4950 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4951 Assembler::pshuflw(xmm0, xmm0, mode);
4952 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4953 pop_zmm(xmm0);
4954 }
4955 } else {
4956 if ((src_enc < 16) && (dst_enc < 16)) {
4957 Assembler::pshuflw(dst, src, mode);
4958 } else if (src_enc < 16) {
4959 push_zmm(xmm0);
4960 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4961 Assembler::pshuflw(xmm0, src, mode);
4962 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4963 pop_zmm(xmm0);
4964 } else if (dst_enc < 16) {
4965 push_zmm(xmm0);
4966 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4967 Assembler::pshuflw(dst, xmm0, mode);
4968 pop_zmm(xmm0);
4969 } else {
4970 push_zmm(xmm0);
4971 push_zmm(xmm1);
4972 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4973 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4974 Assembler::pshuflw(xmm0, xmm1, mode);
4975 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4976 pop_zmm(xmm1);
4977 pop_zmm(xmm0);
4978 }
4979 }
4980 } else {
4981 Assembler::pshuflw(dst, src, mode);
4982 }
4983 }
4984
4985 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
4986 if (reachable(src)) {
4987 vandpd(dst, nds, as_Address(src), vector_len);
4988 } else {
4989 lea(rscratch1, src);
4990 vandpd(dst, nds, Address(rscratch1, 0), vector_len);
4991 }
4992 }
4993
4994 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
4995 if (reachable(src)) {
4996 vandps(dst, nds, as_Address(src), vector_len);
4997 } else {
4998 lea(rscratch1, src);
4999 vandps(dst, nds, Address(rscratch1, 0), vector_len);
5000 }
5001 }
5002
5003 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5004 if (reachable(src)) {
5005 vdivsd(dst, nds, as_Address(src));
5006 } else {
5007 lea(rscratch1, src);
5008 vdivsd(dst, nds, Address(rscratch1, 0));
5009 }
5010 }
5011
5012 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5013 if (reachable(src)) {
5014 vdivss(dst, nds, as_Address(src));
5015 } else {
5016 lea(rscratch1, src);
5017 vdivss(dst, nds, Address(rscratch1, 0));
5018 }
5019 }
5020
5021 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5022 if (reachable(src)) {
5023 vmulsd(dst, nds, as_Address(src));
5024 } else {
5025 lea(rscratch1, src);
5026 vmulsd(dst, nds, Address(rscratch1, 0));
5027 }
5028 }
5029
5030 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5031 if (reachable(src)) {
5032 vmulss(dst, nds, as_Address(src));
5033 } else {
5034 lea(rscratch1, src);
5035 vmulss(dst, nds, Address(rscratch1, 0));
5036 }
5037 }
5038
5039 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5040 if (reachable(src)) {
5041 vsubsd(dst, nds, as_Address(src));
5042 } else {
5043 lea(rscratch1, src);
5044 vsubsd(dst, nds, Address(rscratch1, 0));
5045 }
5046 }
5047
5048 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5049 if (reachable(src)) {
5050 vsubss(dst, nds, as_Address(src));
5051 } else {
5052 lea(rscratch1, src);
5053 vsubss(dst, nds, Address(rscratch1, 0));
5054 }
5055 }
5056
5057 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5058 int nds_enc = nds->encoding();
5059 int dst_enc = dst->encoding();
5060 bool dst_upper_bank = (dst_enc > 15);
5061 bool nds_upper_bank = (nds_enc > 15);
5062 if (VM_Version::supports_avx512novl() &&
5063 (nds_upper_bank || dst_upper_bank)) {
5064 if (dst_upper_bank) {
5065 push_zmm(xmm0);
5066 movflt(xmm0, nds);
5067 vxorps(xmm0, xmm0, src, Assembler::AVX_128bit);
5068 movflt(dst, xmm0);
5069 pop_zmm(xmm0);
5070 } else {
5071 movflt(dst, nds);
5072 vxorps(dst, dst, src, Assembler::AVX_128bit);
5073 }
5074 } else {
5075 vxorps(dst, nds, src, Assembler::AVX_128bit);
5076 }
5077 }
5078
5079 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5080 int nds_enc = nds->encoding();
5081 int dst_enc = dst->encoding();
5082 bool dst_upper_bank = (dst_enc > 15);
5083 bool nds_upper_bank = (nds_enc > 15);
5084 if (VM_Version::supports_avx512novl() &&
5085 (nds_upper_bank || dst_upper_bank)) {
5086 if (dst_upper_bank) {
5087 push_zmm(xmm0);
5088 movdbl(xmm0, nds);
5089 vxorpd(xmm0, xmm0, src, Assembler::AVX_128bit);
5090 movdbl(dst, xmm0);
5091 pop_zmm(xmm0);
5092 } else {
5093 movdbl(dst, nds);
5094 vxorpd(dst, dst, src, Assembler::AVX_128bit);
5095 }
5096 } else {
5097 vxorpd(dst, nds, src, Assembler::AVX_128bit);
5098 }
5099 }
5100
5101 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
5102 if (reachable(src)) {
5103 vxorpd(dst, nds, as_Address(src), vector_len);
5104 } else {
5105 lea(rscratch1, src);
5106 vxorpd(dst, nds, Address(rscratch1, 0), vector_len);
5107 }
5108 }
5109
5110 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
5111 if (reachable(src)) {
5112 vxorps(dst, nds, as_Address(src), vector_len);
5113 } else {
5114 lea(rscratch1, src);
5115 vxorps(dst, nds, Address(rscratch1, 0), vector_len);
5116 }
5117 }
5118
5119 void MacroAssembler::clear_jweak_tag(Register possibly_jweak) {
5120 const int32_t inverted_jweak_mask = ~static_cast<int32_t>(JNIHandles::weak_tag_mask);
5121 STATIC_ASSERT(inverted_jweak_mask == -2); // otherwise check this code
5122 // The inverted mask is sign-extended
5123 andptr(possibly_jweak, inverted_jweak_mask);
5124 }
5125
5126 void MacroAssembler::resolve_jobject(Register value,
5127 Register thread,
5128 Register tmp) {
5129 assert_different_registers(value, thread, tmp);
5130 Label done, not_weak;
5131 testptr(value, value);
5132 jcc(Assembler::zero, done); // Use NULL as-is.
5133 testptr(value, JNIHandles::weak_tag_mask); // Test for jweak tag.
5134 jcc(Assembler::zero, not_weak);
5135 // Resolve jweak.
5136 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
5137 value, Address(value, -JNIHandles::weak_tag_value), tmp, thread);
5138 verify_oop(value);
5139 jmp(done);
5140 bind(not_weak);
5141 // Resolve (untagged) jobject.
5142 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, 0), tmp, thread);
5143 verify_oop(value);
5144 bind(done);
5145 }
5146
5147 void MacroAssembler::subptr(Register dst, int32_t imm32) {
5148 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
5149 }
5150
5151 // Force generation of a 4 byte immediate value even if it fits into 8bit
5152 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
5153 LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32));
5154 }
5155
5156 void MacroAssembler::subptr(Register dst, Register src) {
5157 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
5158 }
5159
5160 // C++ bool manipulation
5161 void MacroAssembler::testbool(Register dst) {
5162 if(sizeof(bool) == 1)
5163 testb(dst, 0xff);
5164 else if(sizeof(bool) == 2) {
5165 // testw implementation needed for two byte bools
5166 ShouldNotReachHere();
5167 } else if(sizeof(bool) == 4)
5168 testl(dst, dst);
5169 else
5170 // unsupported
5171 ShouldNotReachHere();
5172 }
5173
5174 void MacroAssembler::testptr(Register dst, Register src) {
5175 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
5176 }
5177
5178 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
5179 void MacroAssembler::tlab_allocate(Register thread, Register obj,
5180 Register var_size_in_bytes,
5181 int con_size_in_bytes,
5182 Register t1,
5183 Register t2,
5184 Label& slow_case) {
5185 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5186 bs->tlab_allocate(this, thread, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
5187 }
5188
5189 // Defines obj, preserves var_size_in_bytes
5190 void MacroAssembler::eden_allocate(Register thread, Register obj,
5191 Register var_size_in_bytes,
5192 int con_size_in_bytes,
5193 Register t1,
5194 Label& slow_case) {
5195 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5196 bs->eden_allocate(this, thread, obj, var_size_in_bytes, con_size_in_bytes, t1, slow_case);
5197 }
5198
5199 // Preserves the contents of address, destroys the contents length_in_bytes and temp.
5200 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) {
5201 assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different");
5202 assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord");
5203 Label done;
5204
5205 testptr(length_in_bytes, length_in_bytes);
5206 jcc(Assembler::zero, done);
5207
5208 // initialize topmost word, divide index by 2, check if odd and test if zero
5209 // note: for the remaining code to work, index must be a multiple of BytesPerWord
5210 #ifdef ASSERT
5211 {
5212 Label L;
5213 testptr(length_in_bytes, BytesPerWord - 1);
5214 jcc(Assembler::zero, L);
5215 stop("length must be a multiple of BytesPerWord");
5216 bind(L);
5217 }
5218 #endif
5219 Register index = length_in_bytes;
5220 xorptr(temp, temp); // use _zero reg to clear memory (shorter code)
5221 if (UseIncDec) {
5222 shrptr(index, 3); // divide by 8/16 and set carry flag if bit 2 was set
5223 } else {
5224 shrptr(index, 2); // use 2 instructions to avoid partial flag stall
5225 shrptr(index, 1);
5226 }
5227 #ifndef _LP64
5228 // index could have not been a multiple of 8 (i.e., bit 2 was set)
5229 {
5230 Label even;
5231 // note: if index was a multiple of 8, then it cannot
5232 // be 0 now otherwise it must have been 0 before
5233 // => if it is even, we don't need to check for 0 again
5234 jcc(Assembler::carryClear, even);
5235 // clear topmost word (no jump would be needed if conditional assignment worked here)
5236 movptr(Address(address, index, Address::times_8, offset_in_bytes - 0*BytesPerWord), temp);
5237 // index could be 0 now, must check again
5238 jcc(Assembler::zero, done);
5239 bind(even);
5240 }
5241 #endif // !_LP64
5242 // initialize remaining object fields: index is a multiple of 2 now
5243 {
5244 Label loop;
5245 bind(loop);
5246 movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp);
5247 NOT_LP64(movptr(Address(address, index, Address::times_8, offset_in_bytes - 2*BytesPerWord), temp);)
5248 decrement(index);
5249 jcc(Assembler::notZero, loop);
5250 }
5251
5252 bind(done);
5253 }
5254
5255 // Look up the method for a megamorphic invokeinterface call.
5256 // The target method is determined by <intf_klass, itable_index>.
5257 // The receiver klass is in recv_klass.
5258 // On success, the result will be in method_result, and execution falls through.
5259 // On failure, execution transfers to the given label.
5260 void MacroAssembler::lookup_interface_method(Register recv_klass,
5261 Register intf_klass,
5262 RegisterOrConstant itable_index,
5263 Register method_result,
5264 Register scan_temp,
5265 Label& L_no_such_interface,
5266 bool return_method) {
5267 assert_different_registers(recv_klass, intf_klass, scan_temp);
5268 assert_different_registers(method_result, intf_klass, scan_temp);
5269 assert(recv_klass != method_result || !return_method,
5270 "recv_klass can be destroyed when method isn't needed");
5271
5272 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
5273 "caller must use same register for non-constant itable index as for method");
5274
5275 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
5276 int vtable_base = in_bytes(Klass::vtable_start_offset());
5277 int itentry_off = itableMethodEntry::method_offset_in_bytes();
5278 int scan_step = itableOffsetEntry::size() * wordSize;
5279 int vte_size = vtableEntry::size_in_bytes();
5280 Address::ScaleFactor times_vte_scale = Address::times_ptr;
5281 assert(vte_size == wordSize, "else adjust times_vte_scale");
5282
5283 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
5284
5285 // %%% Could store the aligned, prescaled offset in the klassoop.
5286 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
5287
5288 if (return_method) {
5289 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
5290 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
5291 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
5292 }
5293
5294 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
5295 // if (scan->interface() == intf) {
5296 // result = (klass + scan->offset() + itable_index);
5297 // }
5298 // }
5299 Label search, found_method;
5300
5301 for (int peel = 1; peel >= 0; peel--) {
5302 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
5303 cmpptr(intf_klass, method_result);
5304
5305 if (peel) {
5306 jccb(Assembler::equal, found_method);
5307 } else {
5308 jccb(Assembler::notEqual, search);
5309 // (invert the test to fall through to found_method...)
5310 }
5311
5312 if (!peel) break;
5313
5314 bind(search);
5315
5316 // Check that the previous entry is non-null. A null entry means that
5317 // the receiver class doesn't implement the interface, and wasn't the
5318 // same as when the caller was compiled.
5319 testptr(method_result, method_result);
5320 jcc(Assembler::zero, L_no_such_interface);
5321 addptr(scan_temp, scan_step);
5322 }
5323
5324 bind(found_method);
5325
5326 if (return_method) {
5327 // Got a hit.
5328 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes()));
5329 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
5330 }
5331 }
5332
5333
5334 // virtual method calling
5335 void MacroAssembler::lookup_virtual_method(Register recv_klass,
5336 RegisterOrConstant vtable_index,
5337 Register method_result) {
5338 const int base = in_bytes(Klass::vtable_start_offset());
5339 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
5340 Address vtable_entry_addr(recv_klass,
5341 vtable_index, Address::times_ptr,
5342 base + vtableEntry::method_offset_in_bytes());
5343 movptr(method_result, vtable_entry_addr);
5344 }
5345
5346
5347 void MacroAssembler::check_klass_subtype(Register sub_klass,
5348 Register super_klass,
5349 Register temp_reg,
5350 Label& L_success) {
5351 Label L_failure;
5352 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL);
5353 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL);
5354 bind(L_failure);
5355 }
5356
5357
5358 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
5359 Register super_klass,
5360 Register temp_reg,
5361 Label* L_success,
5362 Label* L_failure,
5363 Label* L_slow_path,
5364 RegisterOrConstant super_check_offset) {
5365 assert_different_registers(sub_klass, super_klass, temp_reg);
5366 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
5367 if (super_check_offset.is_register()) {
5368 assert_different_registers(sub_klass, super_klass,
5369 super_check_offset.as_register());
5370 } else if (must_load_sco) {
5371 assert(temp_reg != noreg, "supply either a temp or a register offset");
5372 }
5373
5374 Label L_fallthrough;
5375 int label_nulls = 0;
5376 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
5377 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
5378 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
5379 assert(label_nulls <= 1, "at most one NULL in the batch");
5380
5381 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
5382 int sco_offset = in_bytes(Klass::super_check_offset_offset());
5383 Address super_check_offset_addr(super_klass, sco_offset);
5384
5385 // Hacked jcc, which "knows" that L_fallthrough, at least, is in
5386 // range of a jccb. If this routine grows larger, reconsider at
5387 // least some of these.
5388 #define local_jcc(assembler_cond, label) \
5389 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \
5390 else jcc( assembler_cond, label) /*omit semi*/
5391
5392 // Hacked jmp, which may only be used just before L_fallthrough.
5393 #define final_jmp(label) \
5394 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
5395 else jmp(label) /*omit semi*/
5396
5397 // If the pointers are equal, we are done (e.g., String[] elements).
5398 // This self-check enables sharing of secondary supertype arrays among
5399 // non-primary types such as array-of-interface. Otherwise, each such
5400 // type would need its own customized SSA.
5401 // We move this check to the front of the fast path because many
5402 // type checks are in fact trivially successful in this manner,
5403 // so we get a nicely predicted branch right at the start of the check.
5404 cmpptr(sub_klass, super_klass);
5405 local_jcc(Assembler::equal, *L_success);
5406
5407 // Check the supertype display:
5408 if (must_load_sco) {
5409 // Positive movl does right thing on LP64.
5410 movl(temp_reg, super_check_offset_addr);
5411 super_check_offset = RegisterOrConstant(temp_reg);
5412 }
5413 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
5414 cmpptr(super_klass, super_check_addr); // load displayed supertype
5415
5416 // This check has worked decisively for primary supers.
5417 // Secondary supers are sought in the super_cache ('super_cache_addr').
5418 // (Secondary supers are interfaces and very deeply nested subtypes.)
5419 // This works in the same check above because of a tricky aliasing
5420 // between the super_cache and the primary super display elements.
5421 // (The 'super_check_addr' can address either, as the case requires.)
5422 // Note that the cache is updated below if it does not help us find
5423 // what we need immediately.
5424 // So if it was a primary super, we can just fail immediately.
5425 // Otherwise, it's the slow path for us (no success at this point).
5426
5427 if (super_check_offset.is_register()) {
5428 local_jcc(Assembler::equal, *L_success);
5429 cmpl(super_check_offset.as_register(), sc_offset);
5430 if (L_failure == &L_fallthrough) {
5431 local_jcc(Assembler::equal, *L_slow_path);
5432 } else {
5433 local_jcc(Assembler::notEqual, *L_failure);
5434 final_jmp(*L_slow_path);
5435 }
5436 } else if (super_check_offset.as_constant() == sc_offset) {
5437 // Need a slow path; fast failure is impossible.
5438 if (L_slow_path == &L_fallthrough) {
5439 local_jcc(Assembler::equal, *L_success);
5440 } else {
5441 local_jcc(Assembler::notEqual, *L_slow_path);
5442 final_jmp(*L_success);
5443 }
5444 } else {
5445 // No slow path; it's a fast decision.
5446 if (L_failure == &L_fallthrough) {
5447 local_jcc(Assembler::equal, *L_success);
5448 } else {
5449 local_jcc(Assembler::notEqual, *L_failure);
5450 final_jmp(*L_success);
5451 }
5452 }
5453
5454 bind(L_fallthrough);
5455
5456 #undef local_jcc
5457 #undef final_jmp
5458 }
5459
5460
5461 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
5462 Register super_klass,
5463 Register temp_reg,
5464 Register temp2_reg,
5465 Label* L_success,
5466 Label* L_failure,
5467 bool set_cond_codes) {
5468 assert_different_registers(sub_klass, super_klass, temp_reg);
5469 if (temp2_reg != noreg)
5470 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
5471 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
5472
5473 Label L_fallthrough;
5474 int label_nulls = 0;
5475 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
5476 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
5477 assert(label_nulls <= 1, "at most one NULL in the batch");
5478
5479 // a couple of useful fields in sub_klass:
5480 int ss_offset = in_bytes(Klass::secondary_supers_offset());
5481 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
5482 Address secondary_supers_addr(sub_klass, ss_offset);
5483 Address super_cache_addr( sub_klass, sc_offset);
5484
5485 // Do a linear scan of the secondary super-klass chain.
5486 // This code is rarely used, so simplicity is a virtue here.
5487 // The repne_scan instruction uses fixed registers, which we must spill.
5488 // Don't worry too much about pre-existing connections with the input regs.
5489
5490 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
5491 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
5492
5493 // Get super_klass value into rax (even if it was in rdi or rcx).
5494 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
5495 if (super_klass != rax || UseCompressedOops) {
5496 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
5497 mov(rax, super_klass);
5498 }
5499 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
5500 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
5501
5502 #ifndef PRODUCT
5503 int* pst_counter = &SharedRuntime::_partial_subtype_ctr;
5504 ExternalAddress pst_counter_addr((address) pst_counter);
5505 NOT_LP64( incrementl(pst_counter_addr) );
5506 LP64_ONLY( lea(rcx, pst_counter_addr) );
5507 LP64_ONLY( incrementl(Address(rcx, 0)) );
5508 #endif //PRODUCT
5509
5510 // We will consult the secondary-super array.
5511 movptr(rdi, secondary_supers_addr);
5512 // Load the array length. (Positive movl does right thing on LP64.)
5513 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
5514 // Skip to start of data.
5515 addptr(rdi, Array<Klass*>::base_offset_in_bytes());
5516
5517 // Scan RCX words at [RDI] for an occurrence of RAX.
5518 // Set NZ/Z based on last compare.
5519 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
5520 // not change flags (only scas instruction which is repeated sets flags).
5521 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
5522
5523 testptr(rax,rax); // Set Z = 0
5524 repne_scan();
5525
5526 // Unspill the temp. registers:
5527 if (pushed_rdi) pop(rdi);
5528 if (pushed_rcx) pop(rcx);
5529 if (pushed_rax) pop(rax);
5530
5531 if (set_cond_codes) {
5532 // Special hack for the AD files: rdi is guaranteed non-zero.
5533 assert(!pushed_rdi, "rdi must be left non-NULL");
5534 // Also, the condition codes are properly set Z/NZ on succeed/failure.
5535 }
5536
5537 if (L_failure == &L_fallthrough)
5538 jccb(Assembler::notEqual, *L_failure);
5539 else jcc(Assembler::notEqual, *L_failure);
5540
5541 // Success. Cache the super we found and proceed in triumph.
5542 movptr(super_cache_addr, super_klass);
5543
5544 if (L_success != &L_fallthrough) {
5545 jmp(*L_success);
5546 }
5547
5548 #undef IS_A_TEMP
5549
5550 bind(L_fallthrough);
5551 }
5552
5553
5554 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
5555 if (VM_Version::supports_cmov()) {
5556 cmovl(cc, dst, src);
5557 } else {
5558 Label L;
5559 jccb(negate_condition(cc), L);
5560 movl(dst, src);
5561 bind(L);
5562 }
5563 }
5564
5565 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
5566 if (VM_Version::supports_cmov()) {
5567 cmovl(cc, dst, src);
5568 } else {
5569 Label L;
5570 jccb(negate_condition(cc), L);
5571 movl(dst, src);
5572 bind(L);
5573 }
5574 }
5575
5576 void MacroAssembler::verify_oop(Register reg, const char* s) {
5577 if (!VerifyOops) return;
5578
5579 // Pass register number to verify_oop_subroutine
5580 const char* b = NULL;
5581 {
5582 ResourceMark rm;
5583 stringStream ss;
5584 ss.print("verify_oop: %s: %s", reg->name(), s);
5585 b = code_string(ss.as_string());
5586 }
5587 BLOCK_COMMENT("verify_oop {");
5588 #ifdef _LP64
5589 push(rscratch1); // save r10, trashed by movptr()
5590 #endif
5591 push(rax); // save rax,
5592 push(reg); // pass register argument
5593 ExternalAddress buffer((address) b);
5594 // avoid using pushptr, as it modifies scratch registers
5595 // and our contract is not to modify anything
5596 movptr(rax, buffer.addr());
5597 push(rax);
5598 // call indirectly to solve generation ordering problem
5599 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5600 call(rax);
5601 // Caller pops the arguments (oop, message) and restores rax, r10
5602 BLOCK_COMMENT("} verify_oop");
5603 }
5604
5605
5606 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
5607 Register tmp,
5608 int offset) {
5609 intptr_t value = *delayed_value_addr;
5610 if (value != 0)
5611 return RegisterOrConstant(value + offset);
5612
5613 // load indirectly to solve generation ordering problem
5614 movptr(tmp, ExternalAddress((address) delayed_value_addr));
5615
5616 #ifdef ASSERT
5617 { Label L;
5618 testptr(tmp, tmp);
5619 if (WizardMode) {
5620 const char* buf = NULL;
5621 {
5622 ResourceMark rm;
5623 stringStream ss;
5624 ss.print("DelayedValue=" INTPTR_FORMAT, delayed_value_addr[1]);
5625 buf = code_string(ss.as_string());
5626 }
5627 jcc(Assembler::notZero, L);
5628 STOP(buf);
5629 } else {
5630 jccb(Assembler::notZero, L);
5631 hlt();
5632 }
5633 bind(L);
5634 }
5635 #endif
5636
5637 if (offset != 0)
5638 addptr(tmp, offset);
5639
5640 return RegisterOrConstant(tmp);
5641 }
5642
5643
5644 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
5645 int extra_slot_offset) {
5646 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
5647 int stackElementSize = Interpreter::stackElementSize;
5648 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
5649 #ifdef ASSERT
5650 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
5651 assert(offset1 - offset == stackElementSize, "correct arithmetic");
5652 #endif
5653 Register scale_reg = noreg;
5654 Address::ScaleFactor scale_factor = Address::no_scale;
5655 if (arg_slot.is_constant()) {
5656 offset += arg_slot.as_constant() * stackElementSize;
5657 } else {
5658 scale_reg = arg_slot.as_register();
5659 scale_factor = Address::times(stackElementSize);
5660 }
5661 offset += wordSize; // return PC is on stack
5662 return Address(rsp, scale_reg, scale_factor, offset);
5663 }
5664
5665
5666 void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
5667 if (!VerifyOops) return;
5668
5669 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord);
5670 // Pass register number to verify_oop_subroutine
5671 const char* b = NULL;
5672 {
5673 ResourceMark rm;
5674 stringStream ss;
5675 ss.print("verify_oop_addr: %s", s);
5676 b = code_string(ss.as_string());
5677 }
5678 #ifdef _LP64
5679 push(rscratch1); // save r10, trashed by movptr()
5680 #endif
5681 push(rax); // save rax,
5682 // addr may contain rsp so we will have to adjust it based on the push
5683 // we just did (and on 64 bit we do two pushes)
5684 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
5685 // stores rax into addr which is backwards of what was intended.
5686 if (addr.uses(rsp)) {
5687 lea(rax, addr);
5688 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord));
5689 } else {
5690 pushptr(addr);
5691 }
5692
5693 ExternalAddress buffer((address) b);
5694 // pass msg argument
5695 // avoid using pushptr, as it modifies scratch registers
5696 // and our contract is not to modify anything
5697 movptr(rax, buffer.addr());
5698 push(rax);
5699
5700 // call indirectly to solve generation ordering problem
5701 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5702 call(rax);
5703 // Caller pops the arguments (addr, message) and restores rax, r10.
5704 }
5705
5706 void MacroAssembler::verify_tlab() {
5707 #ifdef ASSERT
5708 if (UseTLAB && VerifyOops) {
5709 Label next, ok;
5710 Register t1 = rsi;
5711 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
5712
5713 push(t1);
5714 NOT_LP64(push(thread_reg));
5715 NOT_LP64(get_thread(thread_reg));
5716
5717 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5718 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
5719 jcc(Assembler::aboveEqual, next);
5720 STOP("assert(top >= start)");
5721 should_not_reach_here();
5722
5723 bind(next);
5724 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
5725 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5726 jcc(Assembler::aboveEqual, ok);
5727 STOP("assert(top <= end)");
5728 should_not_reach_here();
5729
5730 bind(ok);
5731 NOT_LP64(pop(thread_reg));
5732 pop(t1);
5733 }
5734 #endif
5735 }
5736
5737 class ControlWord {
5738 public:
5739 int32_t _value;
5740
5741 int rounding_control() const { return (_value >> 10) & 3 ; }
5742 int precision_control() const { return (_value >> 8) & 3 ; }
5743 bool precision() const { return ((_value >> 5) & 1) != 0; }
5744 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5745 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5746 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5747 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5748 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5749
5750 void print() const {
5751 // rounding control
5752 const char* rc;
5753 switch (rounding_control()) {
5754 case 0: rc = "round near"; break;
5755 case 1: rc = "round down"; break;
5756 case 2: rc = "round up "; break;
5757 case 3: rc = "chop "; break;
5758 };
5759 // precision control
5760 const char* pc;
5761 switch (precision_control()) {
5762 case 0: pc = "24 bits "; break;
5763 case 1: pc = "reserved"; break;
5764 case 2: pc = "53 bits "; break;
5765 case 3: pc = "64 bits "; break;
5766 };
5767 // flags
5768 char f[9];
5769 f[0] = ' ';
5770 f[1] = ' ';
5771 f[2] = (precision ()) ? 'P' : 'p';
5772 f[3] = (underflow ()) ? 'U' : 'u';
5773 f[4] = (overflow ()) ? 'O' : 'o';
5774 f[5] = (zero_divide ()) ? 'Z' : 'z';
5775 f[6] = (denormalized()) ? 'D' : 'd';
5776 f[7] = (invalid ()) ? 'I' : 'i';
5777 f[8] = '\x0';
5778 // output
5779 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
5780 }
5781
5782 };
5783
5784 class StatusWord {
5785 public:
5786 int32_t _value;
5787
5788 bool busy() const { return ((_value >> 15) & 1) != 0; }
5789 bool C3() const { return ((_value >> 14) & 1) != 0; }
5790 bool C2() const { return ((_value >> 10) & 1) != 0; }
5791 bool C1() const { return ((_value >> 9) & 1) != 0; }
5792 bool C0() const { return ((_value >> 8) & 1) != 0; }
5793 int top() const { return (_value >> 11) & 7 ; }
5794 bool error_status() const { return ((_value >> 7) & 1) != 0; }
5795 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
5796 bool precision() const { return ((_value >> 5) & 1) != 0; }
5797 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5798 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5799 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5800 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5801 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5802
5803 void print() const {
5804 // condition codes
5805 char c[5];
5806 c[0] = (C3()) ? '3' : '-';
5807 c[1] = (C2()) ? '2' : '-';
5808 c[2] = (C1()) ? '1' : '-';
5809 c[3] = (C0()) ? '0' : '-';
5810 c[4] = '\x0';
5811 // flags
5812 char f[9];
5813 f[0] = (error_status()) ? 'E' : '-';
5814 f[1] = (stack_fault ()) ? 'S' : '-';
5815 f[2] = (precision ()) ? 'P' : '-';
5816 f[3] = (underflow ()) ? 'U' : '-';
5817 f[4] = (overflow ()) ? 'O' : '-';
5818 f[5] = (zero_divide ()) ? 'Z' : '-';
5819 f[6] = (denormalized()) ? 'D' : '-';
5820 f[7] = (invalid ()) ? 'I' : '-';
5821 f[8] = '\x0';
5822 // output
5823 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
5824 }
5825
5826 };
5827
5828 class TagWord {
5829 public:
5830 int32_t _value;
5831
5832 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
5833
5834 void print() const {
5835 printf("%04x", _value & 0xFFFF);
5836 }
5837
5838 };
5839
5840 class FPU_Register {
5841 public:
5842 int32_t _m0;
5843 int32_t _m1;
5844 int16_t _ex;
5845
5846 bool is_indefinite() const {
5847 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
5848 }
5849
5850 void print() const {
5851 char sign = (_ex < 0) ? '-' : '+';
5852 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
5853 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
5854 };
5855
5856 };
5857
5858 class FPU_State {
5859 public:
5860 enum {
5861 register_size = 10,
5862 number_of_registers = 8,
5863 register_mask = 7
5864 };
5865
5866 ControlWord _control_word;
5867 StatusWord _status_word;
5868 TagWord _tag_word;
5869 int32_t _error_offset;
5870 int32_t _error_selector;
5871 int32_t _data_offset;
5872 int32_t _data_selector;
5873 int8_t _register[register_size * number_of_registers];
5874
5875 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
5876 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
5877
5878 const char* tag_as_string(int tag) const {
5879 switch (tag) {
5880 case 0: return "valid";
5881 case 1: return "zero";
5882 case 2: return "special";
5883 case 3: return "empty";
5884 }
5885 ShouldNotReachHere();
5886 return NULL;
5887 }
5888
5889 void print() const {
5890 // print computation registers
5891 { int t = _status_word.top();
5892 for (int i = 0; i < number_of_registers; i++) {
5893 int j = (i - t) & register_mask;
5894 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
5895 st(j)->print();
5896 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
5897 }
5898 }
5899 printf("\n");
5900 // print control registers
5901 printf("ctrl = "); _control_word.print(); printf("\n");
5902 printf("stat = "); _status_word .print(); printf("\n");
5903 printf("tags = "); _tag_word .print(); printf("\n");
5904 }
5905
5906 };
5907
5908 class Flag_Register {
5909 public:
5910 int32_t _value;
5911
5912 bool overflow() const { return ((_value >> 11) & 1) != 0; }
5913 bool direction() const { return ((_value >> 10) & 1) != 0; }
5914 bool sign() const { return ((_value >> 7) & 1) != 0; }
5915 bool zero() const { return ((_value >> 6) & 1) != 0; }
5916 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
5917 bool parity() const { return ((_value >> 2) & 1) != 0; }
5918 bool carry() const { return ((_value >> 0) & 1) != 0; }
5919
5920 void print() const {
5921 // flags
5922 char f[8];
5923 f[0] = (overflow ()) ? 'O' : '-';
5924 f[1] = (direction ()) ? 'D' : '-';
5925 f[2] = (sign ()) ? 'S' : '-';
5926 f[3] = (zero ()) ? 'Z' : '-';
5927 f[4] = (auxiliary_carry()) ? 'A' : '-';
5928 f[5] = (parity ()) ? 'P' : '-';
5929 f[6] = (carry ()) ? 'C' : '-';
5930 f[7] = '\x0';
5931 // output
5932 printf("%08x flags = %s", _value, f);
5933 }
5934
5935 };
5936
5937 class IU_Register {
5938 public:
5939 int32_t _value;
5940
5941 void print() const {
5942 printf("%08x %11d", _value, _value);
5943 }
5944
5945 };
5946
5947 class IU_State {
5948 public:
5949 Flag_Register _eflags;
5950 IU_Register _rdi;
5951 IU_Register _rsi;
5952 IU_Register _rbp;
5953 IU_Register _rsp;
5954 IU_Register _rbx;
5955 IU_Register _rdx;
5956 IU_Register _rcx;
5957 IU_Register _rax;
5958
5959 void print() const {
5960 // computation registers
5961 printf("rax, = "); _rax.print(); printf("\n");
5962 printf("rbx, = "); _rbx.print(); printf("\n");
5963 printf("rcx = "); _rcx.print(); printf("\n");
5964 printf("rdx = "); _rdx.print(); printf("\n");
5965 printf("rdi = "); _rdi.print(); printf("\n");
5966 printf("rsi = "); _rsi.print(); printf("\n");
5967 printf("rbp, = "); _rbp.print(); printf("\n");
5968 printf("rsp = "); _rsp.print(); printf("\n");
5969 printf("\n");
5970 // control registers
5971 printf("flgs = "); _eflags.print(); printf("\n");
5972 }
5973 };
5974
5975
5976 class CPU_State {
5977 public:
5978 FPU_State _fpu_state;
5979 IU_State _iu_state;
5980
5981 void print() const {
5982 printf("--------------------------------------------------\n");
5983 _iu_state .print();
5984 printf("\n");
5985 _fpu_state.print();
5986 printf("--------------------------------------------------\n");
5987 }
5988
5989 };
5990
5991
5992 static void _print_CPU_state(CPU_State* state) {
5993 state->print();
5994 };
5995
5996
5997 void MacroAssembler::print_CPU_state() {
5998 push_CPU_state();
5999 push(rsp); // pass CPU state
6000 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
6001 addptr(rsp, wordSize); // discard argument
6002 pop_CPU_state();
6003 }
6004
6005
6006 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
6007 static int counter = 0;
6008 FPU_State* fs = &state->_fpu_state;
6009 counter++;
6010 // For leaf calls, only verify that the top few elements remain empty.
6011 // We only need 1 empty at the top for C2 code.
6012 if( stack_depth < 0 ) {
6013 if( fs->tag_for_st(7) != 3 ) {
6014 printf("FPR7 not empty\n");
6015 state->print();
6016 assert(false, "error");
6017 return false;
6018 }
6019 return true; // All other stack states do not matter
6020 }
6021
6022 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std,
6023 "bad FPU control word");
6024
6025 // compute stack depth
6026 int i = 0;
6027 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++;
6028 int d = i;
6029 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
6030 // verify findings
6031 if (i != FPU_State::number_of_registers) {
6032 // stack not contiguous
6033 printf("%s: stack not contiguous at ST%d\n", s, i);
6034 state->print();
6035 assert(false, "error");
6036 return false;
6037 }
6038 // check if computed stack depth corresponds to expected stack depth
6039 if (stack_depth < 0) {
6040 // expected stack depth is -stack_depth or less
6041 if (d > -stack_depth) {
6042 // too many elements on the stack
6043 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
6044 state->print();
6045 assert(false, "error");
6046 return false;
6047 }
6048 } else {
6049 // expected stack depth is stack_depth
6050 if (d != stack_depth) {
6051 // wrong stack depth
6052 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
6053 state->print();
6054 assert(false, "error");
6055 return false;
6056 }
6057 }
6058 // everything is cool
6059 return true;
6060 }
6061
6062
6063 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
6064 if (!VerifyFPU) return;
6065 push_CPU_state();
6066 push(rsp); // pass CPU state
6067 ExternalAddress msg((address) s);
6068 // pass message string s
6069 pushptr(msg.addr());
6070 push(stack_depth); // pass stack depth
6071 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
6072 addptr(rsp, 3 * wordSize); // discard arguments
6073 // check for error
6074 { Label L;
6075 testl(rax, rax);
6076 jcc(Assembler::notZero, L);
6077 int3(); // break if error condition
6078 bind(L);
6079 }
6080 pop_CPU_state();
6081 }
6082
6083 void MacroAssembler::restore_cpu_control_state_after_jni() {
6084 // Either restore the MXCSR register after returning from the JNI Call
6085 // or verify that it wasn't changed (with -Xcheck:jni flag).
6086 if (VM_Version::supports_sse()) {
6087 if (RestoreMXCSROnJNICalls) {
6088 ldmxcsr(ExternalAddress(StubRoutines::addr_mxcsr_std()));
6089 } else if (CheckJNICalls) {
6090 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
6091 }
6092 }
6093 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
6094 vzeroupper();
6095 // Reset k1 to 0xffff.
6096 if (VM_Version::supports_evex()) {
6097 push(rcx);
6098 movl(rcx, 0xffff);
6099 kmovwl(k1, rcx);
6100 pop(rcx);
6101 }
6102
6103 #ifndef _LP64
6104 // Either restore the x87 floating pointer control word after returning
6105 // from the JNI call or verify that it wasn't changed.
6106 if (CheckJNICalls) {
6107 call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry()));
6108 }
6109 #endif // _LP64
6110 }
6111
6112 // ((OopHandle)result).resolve();
6113 void MacroAssembler::resolve_oop_handle(Register result, Register tmp) {
6114 assert_different_registers(result, tmp);
6115
6116 // Only 64 bit platforms support GCs that require a tmp register
6117 // Only IN_HEAP loads require a thread_tmp register
6118 // OopHandle::resolve is an indirection like jobject.
6119 access_load_at(T_OBJECT, IN_NATIVE,
6120 result, Address(result, 0), tmp, /*tmp_thread*/noreg);
6121 }
6122
6123 void MacroAssembler::load_mirror(Register mirror, Register method, Register tmp) {
6124 // get mirror
6125 const int mirror_offset = in_bytes(Klass::java_mirror_offset());
6126 movptr(mirror, Address(method, Method::const_offset()));
6127 movptr(mirror, Address(mirror, ConstMethod::constants_offset()));
6128 movptr(mirror, Address(mirror, ConstantPool::pool_holder_offset_in_bytes()));
6129 movptr(mirror, Address(mirror, mirror_offset));
6130 resolve_oop_handle(mirror, tmp);
6131 }
6132
6133 void MacroAssembler::load_klass(Register dst, Register src) {
6134 #ifdef _LP64
6135 if (UseCompressedClassPointers) {
6136 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
6137 decode_klass_not_null(dst);
6138 } else
6139 #endif
6140 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
6141 }
6142
6143 void MacroAssembler::load_prototype_header(Register dst, Register src) {
6144 load_klass(dst, src);
6145 movptr(dst, Address(dst, Klass::prototype_header_offset()));
6146 }
6147
6148 void MacroAssembler::store_klass(Register dst, Register src) {
6149 #ifdef _LP64
6150 if (UseCompressedClassPointers) {
6151 encode_klass_not_null(src);
6152 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
6153 } else
6154 #endif
6155 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
6156 }
6157
6158 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
6159 Register tmp1, Register thread_tmp) {
6160 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
6161 decorators = AccessInternal::decorator_fixup(decorators);
6162 bool as_raw = (decorators & AS_RAW) != 0;
6163 if (as_raw) {
6164 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
6165 } else {
6166 bs->load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
6167 }
6168 }
6169
6170 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
6171 Register tmp1, Register tmp2) {
6172 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
6173 decorators = AccessInternal::decorator_fixup(decorators);
6174 bool as_raw = (decorators & AS_RAW) != 0;
6175 if (as_raw) {
6176 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, src, tmp1, tmp2);
6177 } else {
6178 bs->store_at(this, decorators, type, dst, src, tmp1, tmp2);
6179 }
6180 }
6181
6182 void MacroAssembler::resolve(DecoratorSet decorators, Register obj) {
6183 // Use stronger ACCESS_WRITE|ACCESS_READ by default.
6184 if ((decorators & (ACCESS_READ | ACCESS_WRITE)) == 0) {
6185 decorators |= ACCESS_READ | ACCESS_WRITE;
6186 }
6187 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
6188 return bs->resolve(this, decorators, obj);
6189 }
6190
6191 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1,
6192 Register thread_tmp, DecoratorSet decorators) {
6193 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, thread_tmp);
6194 }
6195
6196 // Doesn't do verfication, generates fixed size code
6197 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1,
6198 Register thread_tmp, DecoratorSet decorators) {
6199 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, thread_tmp);
6200 }
6201
6202 void MacroAssembler::store_heap_oop(Address dst, Register src, Register tmp1,
6203 Register tmp2, DecoratorSet decorators) {
6204 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, tmp2);
6205 }
6206
6207 // Used for storing NULLs.
6208 void MacroAssembler::store_heap_oop_null(Address dst) {
6209 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg);
6210 }
6211
6212 #ifdef _LP64
6213 void MacroAssembler::store_klass_gap(Register dst, Register src) {
6214 if (UseCompressedClassPointers) {
6215 // Store to klass gap in destination
6216 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
6217 }
6218 }
6219
6220 #ifdef ASSERT
6221 void MacroAssembler::verify_heapbase(const char* msg) {
6222 assert (UseCompressedOops, "should be compressed");
6223 assert (Universe::heap() != NULL, "java heap should be initialized");
6224 if (CheckCompressedOops) {
6225 Label ok;
6226 push(rscratch1); // cmpptr trashes rscratch1
6227 cmpptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
6228 jcc(Assembler::equal, ok);
6229 STOP(msg);
6230 bind(ok);
6231 pop(rscratch1);
6232 }
6233 }
6234 #endif
6235
6236 // Algorithm must match oop.inline.hpp encode_heap_oop.
6237 void MacroAssembler::encode_heap_oop(Register r) {
6238 #ifdef ASSERT
6239 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
6240 #endif
6241 verify_oop(r, "broken oop in encode_heap_oop");
6242 if (Universe::narrow_oop_base() == NULL) {
6243 if (Universe::narrow_oop_shift() != 0) {
6244 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6245 shrq(r, LogMinObjAlignmentInBytes);
6246 }
6247 return;
6248 }
6249 testq(r, r);
6250 cmovq(Assembler::equal, r, r12_heapbase);
6251 subq(r, r12_heapbase);
6252 shrq(r, LogMinObjAlignmentInBytes);
6253 }
6254
6255 void MacroAssembler::encode_heap_oop_not_null(Register r) {
6256 #ifdef ASSERT
6257 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
6258 if (CheckCompressedOops) {
6259 Label ok;
6260 testq(r, r);
6261 jcc(Assembler::notEqual, ok);
6262 STOP("null oop passed to encode_heap_oop_not_null");
6263 bind(ok);
6264 }
6265 #endif
6266 verify_oop(r, "broken oop in encode_heap_oop_not_null");
6267 if (Universe::narrow_oop_base() != NULL) {
6268 subq(r, r12_heapbase);
6269 }
6270 if (Universe::narrow_oop_shift() != 0) {
6271 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6272 shrq(r, LogMinObjAlignmentInBytes);
6273 }
6274 }
6275
6276 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
6277 #ifdef ASSERT
6278 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
6279 if (CheckCompressedOops) {
6280 Label ok;
6281 testq(src, src);
6282 jcc(Assembler::notEqual, ok);
6283 STOP("null oop passed to encode_heap_oop_not_null2");
6284 bind(ok);
6285 }
6286 #endif
6287 verify_oop(src, "broken oop in encode_heap_oop_not_null2");
6288 if (dst != src) {
6289 movq(dst, src);
6290 }
6291 if (Universe::narrow_oop_base() != NULL) {
6292 subq(dst, r12_heapbase);
6293 }
6294 if (Universe::narrow_oop_shift() != 0) {
6295 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6296 shrq(dst, LogMinObjAlignmentInBytes);
6297 }
6298 }
6299
6300 void MacroAssembler::decode_heap_oop(Register r) {
6301 #ifdef ASSERT
6302 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
6303 #endif
6304 if (Universe::narrow_oop_base() == NULL) {
6305 if (Universe::narrow_oop_shift() != 0) {
6306 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6307 shlq(r, LogMinObjAlignmentInBytes);
6308 }
6309 } else {
6310 Label done;
6311 shlq(r, LogMinObjAlignmentInBytes);
6312 jccb(Assembler::equal, done);
6313 addq(r, r12_heapbase);
6314 bind(done);
6315 }
6316 verify_oop(r, "broken oop in decode_heap_oop");
6317 }
6318
6319 void MacroAssembler::decode_heap_oop_not_null(Register r) {
6320 // Note: it will change flags
6321 assert (UseCompressedOops, "should only be used for compressed headers");
6322 assert (Universe::heap() != NULL, "java heap should be initialized");
6323 // Cannot assert, unverified entry point counts instructions (see .ad file)
6324 // vtableStubs also counts instructions in pd_code_size_limit.
6325 // Also do not verify_oop as this is called by verify_oop.
6326 if (Universe::narrow_oop_shift() != 0) {
6327 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6328 shlq(r, LogMinObjAlignmentInBytes);
6329 if (Universe::narrow_oop_base() != NULL) {
6330 addq(r, r12_heapbase);
6331 }
6332 } else {
6333 assert (Universe::narrow_oop_base() == NULL, "sanity");
6334 }
6335 }
6336
6337 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
6338 // Note: it will change flags
6339 assert (UseCompressedOops, "should only be used for compressed headers");
6340 assert (Universe::heap() != NULL, "java heap should be initialized");
6341 // Cannot assert, unverified entry point counts instructions (see .ad file)
6342 // vtableStubs also counts instructions in pd_code_size_limit.
6343 // Also do not verify_oop as this is called by verify_oop.
6344 if (Universe::narrow_oop_shift() != 0) {
6345 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6346 if (LogMinObjAlignmentInBytes == Address::times_8) {
6347 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
6348 } else {
6349 if (dst != src) {
6350 movq(dst, src);
6351 }
6352 shlq(dst, LogMinObjAlignmentInBytes);
6353 if (Universe::narrow_oop_base() != NULL) {
6354 addq(dst, r12_heapbase);
6355 }
6356 }
6357 } else {
6358 assert (Universe::narrow_oop_base() == NULL, "sanity");
6359 if (dst != src) {
6360 movq(dst, src);
6361 }
6362 }
6363 }
6364
6365 void MacroAssembler::encode_klass_not_null(Register r) {
6366 if (Universe::narrow_klass_base() != NULL) {
6367 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
6368 assert(r != r12_heapbase, "Encoding a klass in r12");
6369 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
6370 subq(r, r12_heapbase);
6371 }
6372 if (Universe::narrow_klass_shift() != 0) {
6373 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6374 shrq(r, LogKlassAlignmentInBytes);
6375 }
6376 if (Universe::narrow_klass_base() != NULL) {
6377 reinit_heapbase();
6378 }
6379 }
6380
6381 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
6382 if (dst == src) {
6383 encode_klass_not_null(src);
6384 } else {
6385 if (Universe::narrow_klass_base() != NULL) {
6386 mov64(dst, (int64_t)Universe::narrow_klass_base());
6387 negq(dst);
6388 addq(dst, src);
6389 } else {
6390 movptr(dst, src);
6391 }
6392 if (Universe::narrow_klass_shift() != 0) {
6393 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6394 shrq(dst, LogKlassAlignmentInBytes);
6395 }
6396 }
6397 }
6398
6399 // Function instr_size_for_decode_klass_not_null() counts the instructions
6400 // generated by decode_klass_not_null(register r) and reinit_heapbase(),
6401 // when (Universe::heap() != NULL). Hence, if the instructions they
6402 // generate change, then this method needs to be updated.
6403 int MacroAssembler::instr_size_for_decode_klass_not_null() {
6404 assert (UseCompressedClassPointers, "only for compressed klass ptrs");
6405 if (Universe::narrow_klass_base() != NULL) {
6406 // mov64 + addq + shlq? + mov64 (for reinit_heapbase()).
6407 return (Universe::narrow_klass_shift() == 0 ? 20 : 24);
6408 } else {
6409 // longest load decode klass function, mov64, leaq
6410 return 16;
6411 }
6412 }
6413
6414 // !!! If the instructions that get generated here change then function
6415 // instr_size_for_decode_klass_not_null() needs to get updated.
6416 void MacroAssembler::decode_klass_not_null(Register r) {
6417 // Note: it will change flags
6418 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6419 assert(r != r12_heapbase, "Decoding a klass in r12");
6420 // Cannot assert, unverified entry point counts instructions (see .ad file)
6421 // vtableStubs also counts instructions in pd_code_size_limit.
6422 // Also do not verify_oop as this is called by verify_oop.
6423 if (Universe::narrow_klass_shift() != 0) {
6424 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6425 shlq(r, LogKlassAlignmentInBytes);
6426 }
6427 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
6428 if (Universe::narrow_klass_base() != NULL) {
6429 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
6430 addq(r, r12_heapbase);
6431 reinit_heapbase();
6432 }
6433 }
6434
6435 void MacroAssembler::decode_klass_not_null(Register dst, Register src) {
6436 // Note: it will change flags
6437 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6438 if (dst == src) {
6439 decode_klass_not_null(dst);
6440 } else {
6441 // Cannot assert, unverified entry point counts instructions (see .ad file)
6442 // vtableStubs also counts instructions in pd_code_size_limit.
6443 // Also do not verify_oop as this is called by verify_oop.
6444 mov64(dst, (int64_t)Universe::narrow_klass_base());
6445 if (Universe::narrow_klass_shift() != 0) {
6446 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6447 assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?");
6448 leaq(dst, Address(dst, src, Address::times_8, 0));
6449 } else {
6450 addq(dst, src);
6451 }
6452 }
6453 }
6454
6455 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
6456 assert (UseCompressedOops, "should only be used for compressed headers");
6457 assert (Universe::heap() != NULL, "java heap should be initialized");
6458 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6459 int oop_index = oop_recorder()->find_index(obj);
6460 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6461 mov_narrow_oop(dst, oop_index, rspec);
6462 }
6463
6464 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
6465 assert (UseCompressedOops, "should only be used for compressed headers");
6466 assert (Universe::heap() != NULL, "java heap should be initialized");
6467 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6468 int oop_index = oop_recorder()->find_index(obj);
6469 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6470 mov_narrow_oop(dst, oop_index, rspec);
6471 }
6472
6473 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
6474 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6475 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6476 int klass_index = oop_recorder()->find_index(k);
6477 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6478 mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
6479 }
6480
6481 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
6482 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6483 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6484 int klass_index = oop_recorder()->find_index(k);
6485 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6486 mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
6487 }
6488
6489 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
6490 assert (UseCompressedOops, "should only be used for compressed headers");
6491 assert (Universe::heap() != NULL, "java heap should be initialized");
6492 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6493 int oop_index = oop_recorder()->find_index(obj);
6494 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6495 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6496 }
6497
6498 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
6499 assert (UseCompressedOops, "should only be used for compressed headers");
6500 assert (Universe::heap() != NULL, "java heap should be initialized");
6501 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6502 int oop_index = oop_recorder()->find_index(obj);
6503 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6504 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6505 }
6506
6507 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
6508 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6509 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6510 int klass_index = oop_recorder()->find_index(k);
6511 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6512 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
6513 }
6514
6515 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
6516 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6517 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6518 int klass_index = oop_recorder()->find_index(k);
6519 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6520 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
6521 }
6522
6523 void MacroAssembler::reinit_heapbase() {
6524 if (UseCompressedOops || UseCompressedClassPointers) {
6525 if (Universe::heap() != NULL) {
6526 if (Universe::narrow_oop_base() == NULL) {
6527 MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
6528 } else {
6529 mov64(r12_heapbase, (int64_t)Universe::narrow_ptrs_base());
6530 }
6531 } else {
6532 movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
6533 }
6534 }
6535 }
6536
6537 #endif // _LP64
6538
6539 // C2 compiled method's prolog code.
6540 void MacroAssembler::verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b) {
6541
6542 // WARNING: Initial instruction MUST be 5 bytes or longer so that
6543 // NativeJump::patch_verified_entry will be able to patch out the entry
6544 // code safely. The push to verify stack depth is ok at 5 bytes,
6545 // the frame allocation can be either 3 or 6 bytes. So if we don't do
6546 // stack bang then we must use the 6 byte frame allocation even if
6547 // we have no frame. :-(
6548 assert(stack_bang_size >= framesize || stack_bang_size <= 0, "stack bang size incorrect");
6549
6550 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
6551 // Remove word for return addr
6552 framesize -= wordSize;
6553 stack_bang_size -= wordSize;
6554
6555 // Calls to C2R adapters often do not accept exceptional returns.
6556 // We require that their callers must bang for them. But be careful, because
6557 // some VM calls (such as call site linkage) can use several kilobytes of
6558 // stack. But the stack safety zone should account for that.
6559 // See bugs 4446381, 4468289, 4497237.
6560 if (stack_bang_size > 0) {
6561 generate_stack_overflow_check(stack_bang_size);
6562
6563 // We always push rbp, so that on return to interpreter rbp, will be
6564 // restored correctly and we can correct the stack.
6565 push(rbp);
6566 // Save caller's stack pointer into RBP if the frame pointer is preserved.
6567 if (PreserveFramePointer) {
6568 mov(rbp, rsp);
6569 }
6570 // Remove word for ebp
6571 framesize -= wordSize;
6572
6573 // Create frame
6574 if (framesize) {
6575 subptr(rsp, framesize);
6576 }
6577 } else {
6578 // Create frame (force generation of a 4 byte immediate value)
6579 subptr_imm32(rsp, framesize);
6580
6581 // Save RBP register now.
6582 framesize -= wordSize;
6583 movptr(Address(rsp, framesize), rbp);
6584 // Save caller's stack pointer into RBP if the frame pointer is preserved.
6585 if (PreserveFramePointer) {
6586 movptr(rbp, rsp);
6587 if (framesize > 0) {
6588 addptr(rbp, framesize);
6589 }
6590 }
6591 }
6592
6593 if (VerifyStackAtCalls) { // Majik cookie to verify stack depth
6594 framesize -= wordSize;
6595 movptr(Address(rsp, framesize), (int32_t)0xbadb100d);
6596 }
6597
6598 #ifndef _LP64
6599 // If method sets FPU control word do it now
6600 if (fp_mode_24b) {
6601 fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
6602 }
6603 if (UseSSE >= 2 && VerifyFPU) {
6604 verify_FPU(0, "FPU stack must be clean on entry");
6605 }
6606 #endif
6607
6608 #ifdef ASSERT
6609 if (VerifyStackAtCalls) {
6610 Label L;
6611 push(rax);
6612 mov(rax, rsp);
6613 andptr(rax, StackAlignmentInBytes-1);
6614 cmpptr(rax, StackAlignmentInBytes-wordSize);
6615 pop(rax);
6616 jcc(Assembler::equal, L);
6617 STOP("Stack is not properly aligned!");
6618 bind(L);
6619 }
6620 #endif
6621
6622 }
6623
6624 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM registers
6625 void MacroAssembler::xmm_clear_mem(Register base, Register cnt, XMMRegister xtmp) {
6626 // cnt - number of qwords (8-byte words).
6627 // base - start address, qword aligned.
6628 Label L_zero_64_bytes, L_loop, L_sloop, L_tail, L_end;
6629 if (UseAVX >= 2) {
6630 vpxor(xtmp, xtmp, xtmp, AVX_256bit);
6631 } else {
6632 pxor(xtmp, xtmp);
6633 }
6634 jmp(L_zero_64_bytes);
6635
6636 BIND(L_loop);
6637 if (UseAVX >= 2) {
6638 vmovdqu(Address(base, 0), xtmp);
6639 vmovdqu(Address(base, 32), xtmp);
6640 } else {
6641 movdqu(Address(base, 0), xtmp);
6642 movdqu(Address(base, 16), xtmp);
6643 movdqu(Address(base, 32), xtmp);
6644 movdqu(Address(base, 48), xtmp);
6645 }
6646 addptr(base, 64);
6647
6648 BIND(L_zero_64_bytes);
6649 subptr(cnt, 8);
6650 jccb(Assembler::greaterEqual, L_loop);
6651 addptr(cnt, 4);
6652 jccb(Assembler::less, L_tail);
6653 // Copy trailing 32 bytes
6654 if (UseAVX >= 2) {
6655 vmovdqu(Address(base, 0), xtmp);
6656 } else {
6657 movdqu(Address(base, 0), xtmp);
6658 movdqu(Address(base, 16), xtmp);
6659 }
6660 addptr(base, 32);
6661 subptr(cnt, 4);
6662
6663 BIND(L_tail);
6664 addptr(cnt, 4);
6665 jccb(Assembler::lessEqual, L_end);
6666 decrement(cnt);
6667
6668 BIND(L_sloop);
6669 movq(Address(base, 0), xtmp);
6670 addptr(base, 8);
6671 decrement(cnt);
6672 jccb(Assembler::greaterEqual, L_sloop);
6673 BIND(L_end);
6674 }
6675
6676 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp, XMMRegister xtmp, bool is_large) {
6677 // cnt - number of qwords (8-byte words).
6678 // base - start address, qword aligned.
6679 // is_large - if optimizers know cnt is larger than InitArrayShortSize
6680 assert(base==rdi, "base register must be edi for rep stos");
6681 assert(tmp==rax, "tmp register must be eax for rep stos");
6682 assert(cnt==rcx, "cnt register must be ecx for rep stos");
6683 assert(InitArrayShortSize % BytesPerLong == 0,
6684 "InitArrayShortSize should be the multiple of BytesPerLong");
6685
6686 Label DONE;
6687
6688 if (!is_large || !UseXMMForObjInit) {
6689 xorptr(tmp, tmp);
6690 }
6691
6692 if (!is_large) {
6693 Label LOOP, LONG;
6694 cmpptr(cnt, InitArrayShortSize/BytesPerLong);
6695 jccb(Assembler::greater, LONG);
6696
6697 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
6698
6699 decrement(cnt);
6700 jccb(Assembler::negative, DONE); // Zero length
6701
6702 // Use individual pointer-sized stores for small counts:
6703 BIND(LOOP);
6704 movptr(Address(base, cnt, Address::times_ptr), tmp);
6705 decrement(cnt);
6706 jccb(Assembler::greaterEqual, LOOP);
6707 jmpb(DONE);
6708
6709 BIND(LONG);
6710 }
6711
6712 // Use longer rep-prefixed ops for non-small counts:
6713 if (UseFastStosb) {
6714 shlptr(cnt, 3); // convert to number of bytes
6715 rep_stosb();
6716 } else if (UseXMMForObjInit) {
6717 movptr(tmp, base);
6718 xmm_clear_mem(tmp, cnt, xtmp);
6719 } else {
6720 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
6721 rep_stos();
6722 }
6723
6724 BIND(DONE);
6725 }
6726
6727 #ifdef COMPILER2
6728
6729 // IndexOf for constant substrings with size >= 8 chars
6730 // which don't need to be loaded through stack.
6731 void MacroAssembler::string_indexofC8(Register str1, Register str2,
6732 Register cnt1, Register cnt2,
6733 int int_cnt2, Register result,
6734 XMMRegister vec, Register tmp,
6735 int ae) {
6736 ShortBranchVerifier sbv(this);
6737 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
6738 assert(ae != StrIntrinsicNode::LU, "Invalid encoding");
6739
6740 // This method uses the pcmpestri instruction with bound registers
6741 // inputs:
6742 // xmm - substring
6743 // rax - substring length (elements count)
6744 // mem - scanned string
6745 // rdx - string length (elements count)
6746 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
6747 // 0xc - mode: 1100 (substring search) + 00 (unsigned bytes)
6748 // outputs:
6749 // rcx - matched index in string
6750 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
6751 int mode = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts
6752 int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8
6753 Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2;
6754 Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1;
6755
6756 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR,
6757 RET_FOUND, RET_NOT_FOUND, EXIT, FOUND_SUBSTR,
6758 MATCH_SUBSTR_HEAD, RELOAD_STR, FOUND_CANDIDATE;
6759
6760 // Note, inline_string_indexOf() generates checks:
6761 // if (substr.count > string.count) return -1;
6762 // if (substr.count == 0) return 0;
6763 assert(int_cnt2 >= stride, "this code is used only for cnt2 >= 8 chars");
6764
6765 // Load substring.
6766 if (ae == StrIntrinsicNode::UL) {
6767 pmovzxbw(vec, Address(str2, 0));
6768 } else {
6769 movdqu(vec, Address(str2, 0));
6770 }
6771 movl(cnt2, int_cnt2);
6772 movptr(result, str1); // string addr
6773
6774 if (int_cnt2 > stride) {
6775 jmpb(SCAN_TO_SUBSTR);
6776
6777 // Reload substr for rescan, this code
6778 // is executed only for large substrings (> 8 chars)
6779 bind(RELOAD_SUBSTR);
6780 if (ae == StrIntrinsicNode::UL) {
6781 pmovzxbw(vec, Address(str2, 0));
6782 } else {
6783 movdqu(vec, Address(str2, 0));
6784 }
6785 negptr(cnt2); // Jumped here with negative cnt2, convert to positive
6786
6787 bind(RELOAD_STR);
6788 // We came here after the beginning of the substring was
6789 // matched but the rest of it was not so we need to search
6790 // again. Start from the next element after the previous match.
6791
6792 // cnt2 is number of substring reminding elements and
6793 // cnt1 is number of string reminding elements when cmp failed.
6794 // Restored cnt1 = cnt1 - cnt2 + int_cnt2
6795 subl(cnt1, cnt2);
6796 addl(cnt1, int_cnt2);
6797 movl(cnt2, int_cnt2); // Now restore cnt2
6798
6799 decrementl(cnt1); // Shift to next element
6800 cmpl(cnt1, cnt2);
6801 jcc(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6802
6803 addptr(result, (1<<scale1));
6804
6805 } // (int_cnt2 > 8)
6806
6807 // Scan string for start of substr in 16-byte vectors
6808 bind(SCAN_TO_SUBSTR);
6809 pcmpestri(vec, Address(result, 0), mode);
6810 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
6811 subl(cnt1, stride);
6812 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
6813 cmpl(cnt1, cnt2);
6814 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6815 addptr(result, 16);
6816 jmpb(SCAN_TO_SUBSTR);
6817
6818 // Found a potential substr
6819 bind(FOUND_CANDIDATE);
6820 // Matched whole vector if first element matched (tmp(rcx) == 0).
6821 if (int_cnt2 == stride) {
6822 jccb(Assembler::overflow, RET_FOUND); // OF == 1
6823 } else { // int_cnt2 > 8
6824 jccb(Assembler::overflow, FOUND_SUBSTR);
6825 }
6826 // After pcmpestri tmp(rcx) contains matched element index
6827 // Compute start addr of substr
6828 lea(result, Address(result, tmp, scale1));
6829
6830 // Make sure string is still long enough
6831 subl(cnt1, tmp);
6832 cmpl(cnt1, cnt2);
6833 if (int_cnt2 == stride) {
6834 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
6835 } else { // int_cnt2 > 8
6836 jccb(Assembler::greaterEqual, MATCH_SUBSTR_HEAD);
6837 }
6838 // Left less then substring.
6839
6840 bind(RET_NOT_FOUND);
6841 movl(result, -1);
6842 jmp(EXIT);
6843
6844 if (int_cnt2 > stride) {
6845 // This code is optimized for the case when whole substring
6846 // is matched if its head is matched.
6847 bind(MATCH_SUBSTR_HEAD);
6848 pcmpestri(vec, Address(result, 0), mode);
6849 // Reload only string if does not match
6850 jcc(Assembler::noOverflow, RELOAD_STR); // OF == 0
6851
6852 Label CONT_SCAN_SUBSTR;
6853 // Compare the rest of substring (> 8 chars).
6854 bind(FOUND_SUBSTR);
6855 // First 8 chars are already matched.
6856 negptr(cnt2);
6857 addptr(cnt2, stride);
6858
6859 bind(SCAN_SUBSTR);
6860 subl(cnt1, stride);
6861 cmpl(cnt2, -stride); // Do not read beyond substring
6862 jccb(Assembler::lessEqual, CONT_SCAN_SUBSTR);
6863 // Back-up strings to avoid reading beyond substring:
6864 // cnt1 = cnt1 - cnt2 + 8
6865 addl(cnt1, cnt2); // cnt2 is negative
6866 addl(cnt1, stride);
6867 movl(cnt2, stride); negptr(cnt2);
6868 bind(CONT_SCAN_SUBSTR);
6869 if (int_cnt2 < (int)G) {
6870 int tail_off1 = int_cnt2<<scale1;
6871 int tail_off2 = int_cnt2<<scale2;
6872 if (ae == StrIntrinsicNode::UL) {
6873 pmovzxbw(vec, Address(str2, cnt2, scale2, tail_off2));
6874 } else {
6875 movdqu(vec, Address(str2, cnt2, scale2, tail_off2));
6876 }
6877 pcmpestri(vec, Address(result, cnt2, scale1, tail_off1), mode);
6878 } else {
6879 // calculate index in register to avoid integer overflow (int_cnt2*2)
6880 movl(tmp, int_cnt2);
6881 addptr(tmp, cnt2);
6882 if (ae == StrIntrinsicNode::UL) {
6883 pmovzxbw(vec, Address(str2, tmp, scale2, 0));
6884 } else {
6885 movdqu(vec, Address(str2, tmp, scale2, 0));
6886 }
6887 pcmpestri(vec, Address(result, tmp, scale1, 0), mode);
6888 }
6889 // Need to reload strings pointers if not matched whole vector
6890 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
6891 addptr(cnt2, stride);
6892 jcc(Assembler::negative, SCAN_SUBSTR);
6893 // Fall through if found full substring
6894
6895 } // (int_cnt2 > 8)
6896
6897 bind(RET_FOUND);
6898 // Found result if we matched full small substring.
6899 // Compute substr offset
6900 subptr(result, str1);
6901 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
6902 shrl(result, 1); // index
6903 }
6904 bind(EXIT);
6905
6906 } // string_indexofC8
6907
6908 // Small strings are loaded through stack if they cross page boundary.
6909 void MacroAssembler::string_indexof(Register str1, Register str2,
6910 Register cnt1, Register cnt2,
6911 int int_cnt2, Register result,
6912 XMMRegister vec, Register tmp,
6913 int ae) {
6914 ShortBranchVerifier sbv(this);
6915 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
6916 assert(ae != StrIntrinsicNode::LU, "Invalid encoding");
6917
6918 //
6919 // int_cnt2 is length of small (< 8 chars) constant substring
6920 // or (-1) for non constant substring in which case its length
6921 // is in cnt2 register.
6922 //
6923 // Note, inline_string_indexOf() generates checks:
6924 // if (substr.count > string.count) return -1;
6925 // if (substr.count == 0) return 0;
6926 //
6927 int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8
6928 assert(int_cnt2 == -1 || (0 < int_cnt2 && int_cnt2 < stride), "should be != 0");
6929 // This method uses the pcmpestri instruction with bound registers
6930 // inputs:
6931 // xmm - substring
6932 // rax - substring length (elements count)
6933 // mem - scanned string
6934 // rdx - string length (elements count)
6935 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
6936 // 0xc - mode: 1100 (substring search) + 00 (unsigned bytes)
6937 // outputs:
6938 // rcx - matched index in string
6939 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
6940 int mode = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts
6941 Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2;
6942 Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1;
6943
6944 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, ADJUST_STR,
6945 RET_FOUND, RET_NOT_FOUND, CLEANUP, FOUND_SUBSTR,
6946 FOUND_CANDIDATE;
6947
6948 { //========================================================
6949 // We don't know where these strings are located
6950 // and we can't read beyond them. Load them through stack.
6951 Label BIG_STRINGS, CHECK_STR, COPY_SUBSTR, COPY_STR;
6952
6953 movptr(tmp, rsp); // save old SP
6954
6955 if (int_cnt2 > 0) { // small (< 8 chars) constant substring
6956 if (int_cnt2 == (1>>scale2)) { // One byte
6957 assert((ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL), "Only possible for latin1 encoding");
6958 load_unsigned_byte(result, Address(str2, 0));
6959 movdl(vec, result); // move 32 bits
6960 } else if (ae == StrIntrinsicNode::LL && int_cnt2 == 3) { // Three bytes
6961 // Not enough header space in 32-bit VM: 12+3 = 15.
6962 movl(result, Address(str2, -1));
6963 shrl(result, 8);
6964 movdl(vec, result); // move 32 bits
6965 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (2>>scale2)) { // One char
6966 load_unsigned_short(result, Address(str2, 0));
6967 movdl(vec, result); // move 32 bits
6968 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (4>>scale2)) { // Two chars
6969 movdl(vec, Address(str2, 0)); // move 32 bits
6970 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (8>>scale2)) { // Four chars
6971 movq(vec, Address(str2, 0)); // move 64 bits
6972 } else { // cnt2 = { 3, 5, 6, 7 } || (ae == StrIntrinsicNode::UL && cnt2 ={2, ..., 7})
6973 // Array header size is 12 bytes in 32-bit VM
6974 // + 6 bytes for 3 chars == 18 bytes,
6975 // enough space to load vec and shift.
6976 assert(HeapWordSize*TypeArrayKlass::header_size() >= 12,"sanity");
6977 if (ae == StrIntrinsicNode::UL) {
6978 int tail_off = int_cnt2-8;
6979 pmovzxbw(vec, Address(str2, tail_off));
6980 psrldq(vec, -2*tail_off);
6981 }
6982 else {
6983 int tail_off = int_cnt2*(1<<scale2);
6984 movdqu(vec, Address(str2, tail_off-16));
6985 psrldq(vec, 16-tail_off);
6986 }
6987 }
6988 } else { // not constant substring
6989 cmpl(cnt2, stride);
6990 jccb(Assembler::aboveEqual, BIG_STRINGS); // Both strings are big enough
6991
6992 // We can read beyond string if srt+16 does not cross page boundary
6993 // since heaps are aligned and mapped by pages.
6994 assert(os::vm_page_size() < (int)G, "default page should be small");
6995 movl(result, str2); // We need only low 32 bits
6996 andl(result, (os::vm_page_size()-1));
6997 cmpl(result, (os::vm_page_size()-16));
6998 jccb(Assembler::belowEqual, CHECK_STR);
6999
7000 // Move small strings to stack to allow load 16 bytes into vec.
7001 subptr(rsp, 16);
7002 int stk_offset = wordSize-(1<<scale2);
7003 push(cnt2);
7004
7005 bind(COPY_SUBSTR);
7006 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL) {
7007 load_unsigned_byte(result, Address(str2, cnt2, scale2, -1));
7008 movb(Address(rsp, cnt2, scale2, stk_offset), result);
7009 } else if (ae == StrIntrinsicNode::UU) {
7010 load_unsigned_short(result, Address(str2, cnt2, scale2, -2));
7011 movw(Address(rsp, cnt2, scale2, stk_offset), result);
7012 }
7013 decrement(cnt2);
7014 jccb(Assembler::notZero, COPY_SUBSTR);
7015
7016 pop(cnt2);
7017 movptr(str2, rsp); // New substring address
7018 } // non constant
7019
7020 bind(CHECK_STR);
7021 cmpl(cnt1, stride);
7022 jccb(Assembler::aboveEqual, BIG_STRINGS);
7023
7024 // Check cross page boundary.
7025 movl(result, str1); // We need only low 32 bits
7026 andl(result, (os::vm_page_size()-1));
7027 cmpl(result, (os::vm_page_size()-16));
7028 jccb(Assembler::belowEqual, BIG_STRINGS);
7029
7030 subptr(rsp, 16);
7031 int stk_offset = -(1<<scale1);
7032 if (int_cnt2 < 0) { // not constant
7033 push(cnt2);
7034 stk_offset += wordSize;
7035 }
7036 movl(cnt2, cnt1);
7037
7038 bind(COPY_STR);
7039 if (ae == StrIntrinsicNode::LL) {
7040 load_unsigned_byte(result, Address(str1, cnt2, scale1, -1));
7041 movb(Address(rsp, cnt2, scale1, stk_offset), result);
7042 } else {
7043 load_unsigned_short(result, Address(str1, cnt2, scale1, -2));
7044 movw(Address(rsp, cnt2, scale1, stk_offset), result);
7045 }
7046 decrement(cnt2);
7047 jccb(Assembler::notZero, COPY_STR);
7048
7049 if (int_cnt2 < 0) { // not constant
7050 pop(cnt2);
7051 }
7052 movptr(str1, rsp); // New string address
7053
7054 bind(BIG_STRINGS);
7055 // Load substring.
7056 if (int_cnt2 < 0) { // -1
7057 if (ae == StrIntrinsicNode::UL) {
7058 pmovzxbw(vec, Address(str2, 0));
7059 } else {
7060 movdqu(vec, Address(str2, 0));
7061 }
7062 push(cnt2); // substr count
7063 push(str2); // substr addr
7064 push(str1); // string addr
7065 } else {
7066 // Small (< 8 chars) constant substrings are loaded already.
7067 movl(cnt2, int_cnt2);
7068 }
7069 push(tmp); // original SP
7070
7071 } // Finished loading
7072
7073 //========================================================
7074 // Start search
7075 //
7076
7077 movptr(result, str1); // string addr
7078
7079 if (int_cnt2 < 0) { // Only for non constant substring
7080 jmpb(SCAN_TO_SUBSTR);
7081
7082 // SP saved at sp+0
7083 // String saved at sp+1*wordSize
7084 // Substr saved at sp+2*wordSize
7085 // Substr count saved at sp+3*wordSize
7086
7087 // Reload substr for rescan, this code
7088 // is executed only for large substrings (> 8 chars)
7089 bind(RELOAD_SUBSTR);
7090 movptr(str2, Address(rsp, 2*wordSize));
7091 movl(cnt2, Address(rsp, 3*wordSize));
7092 if (ae == StrIntrinsicNode::UL) {
7093 pmovzxbw(vec, Address(str2, 0));
7094 } else {
7095 movdqu(vec, Address(str2, 0));
7096 }
7097 // We came here after the beginning of the substring was
7098 // matched but the rest of it was not so we need to search
7099 // again. Start from the next element after the previous match.
7100 subptr(str1, result); // Restore counter
7101 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
7102 shrl(str1, 1);
7103 }
7104 addl(cnt1, str1);
7105 decrementl(cnt1); // Shift to next element
7106 cmpl(cnt1, cnt2);
7107 jcc(Assembler::negative, RET_NOT_FOUND); // Left less then substring
7108
7109 addptr(result, (1<<scale1));
7110 } // non constant
7111
7112 // Scan string for start of substr in 16-byte vectors
7113 bind(SCAN_TO_SUBSTR);
7114 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
7115 pcmpestri(vec, Address(result, 0), mode);
7116 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
7117 subl(cnt1, stride);
7118 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
7119 cmpl(cnt1, cnt2);
7120 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
7121 addptr(result, 16);
7122
7123 bind(ADJUST_STR);
7124 cmpl(cnt1, stride); // Do not read beyond string
7125 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
7126 // Back-up string to avoid reading beyond string.
7127 lea(result, Address(result, cnt1, scale1, -16));
7128 movl(cnt1, stride);
7129 jmpb(SCAN_TO_SUBSTR);
7130
7131 // Found a potential substr
7132 bind(FOUND_CANDIDATE);
7133 // After pcmpestri tmp(rcx) contains matched element index
7134
7135 // Make sure string is still long enough
7136 subl(cnt1, tmp);
7137 cmpl(cnt1, cnt2);
7138 jccb(Assembler::greaterEqual, FOUND_SUBSTR);
7139 // Left less then substring.
7140
7141 bind(RET_NOT_FOUND);
7142 movl(result, -1);
7143 jmp(CLEANUP);
7144
7145 bind(FOUND_SUBSTR);
7146 // Compute start addr of substr
7147 lea(result, Address(result, tmp, scale1));
7148 if (int_cnt2 > 0) { // Constant substring
7149 // Repeat search for small substring (< 8 chars)
7150 // from new point without reloading substring.
7151 // Have to check that we don't read beyond string.
7152 cmpl(tmp, stride-int_cnt2);
7153 jccb(Assembler::greater, ADJUST_STR);
7154 // Fall through if matched whole substring.
7155 } else { // non constant
7156 assert(int_cnt2 == -1, "should be != 0");
7157
7158 addl(tmp, cnt2);
7159 // Found result if we matched whole substring.
7160 cmpl(tmp, stride);
7161 jcc(Assembler::lessEqual, RET_FOUND);
7162
7163 // Repeat search for small substring (<= 8 chars)
7164 // from new point 'str1' without reloading substring.
7165 cmpl(cnt2, stride);
7166 // Have to check that we don't read beyond string.
7167 jccb(Assembler::lessEqual, ADJUST_STR);
7168
7169 Label CHECK_NEXT, CONT_SCAN_SUBSTR, RET_FOUND_LONG;
7170 // Compare the rest of substring (> 8 chars).
7171 movptr(str1, result);
7172
7173 cmpl(tmp, cnt2);
7174 // First 8 chars are already matched.
7175 jccb(Assembler::equal, CHECK_NEXT);
7176
7177 bind(SCAN_SUBSTR);
7178 pcmpestri(vec, Address(str1, 0), mode);
7179 // Need to reload strings pointers if not matched whole vector
7180 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
7181
7182 bind(CHECK_NEXT);
7183 subl(cnt2, stride);
7184 jccb(Assembler::lessEqual, RET_FOUND_LONG); // Found full substring
7185 addptr(str1, 16);
7186 if (ae == StrIntrinsicNode::UL) {
7187 addptr(str2, 8);
7188 } else {
7189 addptr(str2, 16);
7190 }
7191 subl(cnt1, stride);
7192 cmpl(cnt2, stride); // Do not read beyond substring
7193 jccb(Assembler::greaterEqual, CONT_SCAN_SUBSTR);
7194 // Back-up strings to avoid reading beyond substring.
7195
7196 if (ae == StrIntrinsicNode::UL) {
7197 lea(str2, Address(str2, cnt2, scale2, -8));
7198 lea(str1, Address(str1, cnt2, scale1, -16));
7199 } else {
7200 lea(str2, Address(str2, cnt2, scale2, -16));
7201 lea(str1, Address(str1, cnt2, scale1, -16));
7202 }
7203 subl(cnt1, cnt2);
7204 movl(cnt2, stride);
7205 addl(cnt1, stride);
7206 bind(CONT_SCAN_SUBSTR);
7207 if (ae == StrIntrinsicNode::UL) {
7208 pmovzxbw(vec, Address(str2, 0));
7209 } else {
7210 movdqu(vec, Address(str2, 0));
7211 }
7212 jmp(SCAN_SUBSTR);
7213
7214 bind(RET_FOUND_LONG);
7215 movptr(str1, Address(rsp, wordSize));
7216 } // non constant
7217
7218 bind(RET_FOUND);
7219 // Compute substr offset
7220 subptr(result, str1);
7221 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
7222 shrl(result, 1); // index
7223 }
7224 bind(CLEANUP);
7225 pop(rsp); // restore SP
7226
7227 } // string_indexof
7228
7229 void MacroAssembler::string_indexof_char(Register str1, Register cnt1, Register ch, Register result,
7230 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp) {
7231 ShortBranchVerifier sbv(this);
7232 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
7233
7234 int stride = 8;
7235
7236 Label FOUND_CHAR, SCAN_TO_CHAR, SCAN_TO_CHAR_LOOP,
7237 SCAN_TO_8_CHAR, SCAN_TO_8_CHAR_LOOP, SCAN_TO_16_CHAR_LOOP,
7238 RET_NOT_FOUND, SCAN_TO_8_CHAR_INIT,
7239 FOUND_SEQ_CHAR, DONE_LABEL;
7240
7241 movptr(result, str1);
7242 if (UseAVX >= 2) {
7243 cmpl(cnt1, stride);
7244 jcc(Assembler::less, SCAN_TO_CHAR_LOOP);
7245 cmpl(cnt1, 2*stride);
7246 jcc(Assembler::less, SCAN_TO_8_CHAR_INIT);
7247 movdl(vec1, ch);
7248 vpbroadcastw(vec1, vec1);
7249 vpxor(vec2, vec2);
7250 movl(tmp, cnt1);
7251 andl(tmp, 0xFFFFFFF0); //vector count (in chars)
7252 andl(cnt1,0x0000000F); //tail count (in chars)
7253
7254 bind(SCAN_TO_16_CHAR_LOOP);
7255 vmovdqu(vec3, Address(result, 0));
7256 vpcmpeqw(vec3, vec3, vec1, 1);
7257 vptest(vec2, vec3);
7258 jcc(Assembler::carryClear, FOUND_CHAR);
7259 addptr(result, 32);
7260 subl(tmp, 2*stride);
7261 jcc(Assembler::notZero, SCAN_TO_16_CHAR_LOOP);
7262 jmp(SCAN_TO_8_CHAR);
7263 bind(SCAN_TO_8_CHAR_INIT);
7264 movdl(vec1, ch);
7265 pshuflw(vec1, vec1, 0x00);
7266 pshufd(vec1, vec1, 0);
7267 pxor(vec2, vec2);
7268 }
7269 bind(SCAN_TO_8_CHAR);
7270 cmpl(cnt1, stride);
7271 if (UseAVX >= 2) {
7272 jcc(Assembler::less, SCAN_TO_CHAR);
7273 } else {
7274 jcc(Assembler::less, SCAN_TO_CHAR_LOOP);
7275 movdl(vec1, ch);
7276 pshuflw(vec1, vec1, 0x00);
7277 pshufd(vec1, vec1, 0);
7278 pxor(vec2, vec2);
7279 }
7280 movl(tmp, cnt1);
7281 andl(tmp, 0xFFFFFFF8); //vector count (in chars)
7282 andl(cnt1,0x00000007); //tail count (in chars)
7283
7284 bind(SCAN_TO_8_CHAR_LOOP);
7285 movdqu(vec3, Address(result, 0));
7286 pcmpeqw(vec3, vec1);
7287 ptest(vec2, vec3);
7288 jcc(Assembler::carryClear, FOUND_CHAR);
7289 addptr(result, 16);
7290 subl(tmp, stride);
7291 jcc(Assembler::notZero, SCAN_TO_8_CHAR_LOOP);
7292 bind(SCAN_TO_CHAR);
7293 testl(cnt1, cnt1);
7294 jcc(Assembler::zero, RET_NOT_FOUND);
7295 bind(SCAN_TO_CHAR_LOOP);
7296 load_unsigned_short(tmp, Address(result, 0));
7297 cmpl(ch, tmp);
7298 jccb(Assembler::equal, FOUND_SEQ_CHAR);
7299 addptr(result, 2);
7300 subl(cnt1, 1);
7301 jccb(Assembler::zero, RET_NOT_FOUND);
7302 jmp(SCAN_TO_CHAR_LOOP);
7303
7304 bind(RET_NOT_FOUND);
7305 movl(result, -1);
7306 jmpb(DONE_LABEL);
7307
7308 bind(FOUND_CHAR);
7309 if (UseAVX >= 2) {
7310 vpmovmskb(tmp, vec3);
7311 } else {
7312 pmovmskb(tmp, vec3);
7313 }
7314 bsfl(ch, tmp);
7315 addl(result, ch);
7316
7317 bind(FOUND_SEQ_CHAR);
7318 subptr(result, str1);
7319 shrl(result, 1);
7320
7321 bind(DONE_LABEL);
7322 } // string_indexof_char
7323
7324 // helper function for string_compare
7325 void MacroAssembler::load_next_elements(Register elem1, Register elem2, Register str1, Register str2,
7326 Address::ScaleFactor scale, Address::ScaleFactor scale1,
7327 Address::ScaleFactor scale2, Register index, int ae) {
7328 if (ae == StrIntrinsicNode::LL) {
7329 load_unsigned_byte(elem1, Address(str1, index, scale, 0));
7330 load_unsigned_byte(elem2, Address(str2, index, scale, 0));
7331 } else if (ae == StrIntrinsicNode::UU) {
7332 load_unsigned_short(elem1, Address(str1, index, scale, 0));
7333 load_unsigned_short(elem2, Address(str2, index, scale, 0));
7334 } else {
7335 load_unsigned_byte(elem1, Address(str1, index, scale1, 0));
7336 load_unsigned_short(elem2, Address(str2, index, scale2, 0));
7337 }
7338 }
7339
7340 // Compare strings, used for char[] and byte[].
7341 void MacroAssembler::string_compare(Register str1, Register str2,
7342 Register cnt1, Register cnt2, Register result,
7343 XMMRegister vec1, int ae) {
7344 ShortBranchVerifier sbv(this);
7345 Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL;
7346 Label COMPARE_WIDE_VECTORS_LOOP_FAILED; // used only _LP64 && AVX3
7347 int stride, stride2, adr_stride, adr_stride1, adr_stride2;
7348 int stride2x2 = 0x40;
7349 Address::ScaleFactor scale = Address::no_scale;
7350 Address::ScaleFactor scale1 = Address::no_scale;
7351 Address::ScaleFactor scale2 = Address::no_scale;
7352
7353 if (ae != StrIntrinsicNode::LL) {
7354 stride2x2 = 0x20;
7355 }
7356
7357 if (ae == StrIntrinsicNode::LU || ae == StrIntrinsicNode::UL) {
7358 shrl(cnt2, 1);
7359 }
7360 // Compute the minimum of the string lengths and the
7361 // difference of the string lengths (stack).
7362 // Do the conditional move stuff
7363 movl(result, cnt1);
7364 subl(cnt1, cnt2);
7365 push(cnt1);
7366 cmov32(Assembler::lessEqual, cnt2, result); // cnt2 = min(cnt1, cnt2)
7367
7368 // Is the minimum length zero?
7369 testl(cnt2, cnt2);
7370 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
7371 if (ae == StrIntrinsicNode::LL) {
7372 // Load first bytes
7373 load_unsigned_byte(result, Address(str1, 0)); // result = str1[0]
7374 load_unsigned_byte(cnt1, Address(str2, 0)); // cnt1 = str2[0]
7375 } else if (ae == StrIntrinsicNode::UU) {
7376 // Load first characters
7377 load_unsigned_short(result, Address(str1, 0));
7378 load_unsigned_short(cnt1, Address(str2, 0));
7379 } else {
7380 load_unsigned_byte(result, Address(str1, 0));
7381 load_unsigned_short(cnt1, Address(str2, 0));
7382 }
7383 subl(result, cnt1);
7384 jcc(Assembler::notZero, POP_LABEL);
7385
7386 if (ae == StrIntrinsicNode::UU) {
7387 // Divide length by 2 to get number of chars
7388 shrl(cnt2, 1);
7389 }
7390 cmpl(cnt2, 1);
7391 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
7392
7393 // Check if the strings start at the same location and setup scale and stride
7394 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7395 cmpptr(str1, str2);
7396 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
7397 if (ae == StrIntrinsicNode::LL) {
7398 scale = Address::times_1;
7399 stride = 16;
7400 } else {
7401 scale = Address::times_2;
7402 stride = 8;
7403 }
7404 } else {
7405 scale1 = Address::times_1;
7406 scale2 = Address::times_2;
7407 // scale not used
7408 stride = 8;
7409 }
7410
7411 if (UseAVX >= 2 && UseSSE42Intrinsics) {
7412 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_WIDE_TAIL, COMPARE_SMALL_STR;
7413 Label COMPARE_WIDE_VECTORS_LOOP, COMPARE_16_CHARS, COMPARE_INDEX_CHAR;
7414 Label COMPARE_WIDE_VECTORS_LOOP_AVX2;
7415 Label COMPARE_TAIL_LONG;
7416 Label COMPARE_WIDE_VECTORS_LOOP_AVX3; // used only _LP64 && AVX3
7417
7418 int pcmpmask = 0x19;
7419 if (ae == StrIntrinsicNode::LL) {
7420 pcmpmask &= ~0x01;
7421 }
7422
7423 // Setup to compare 16-chars (32-bytes) vectors,
7424 // start from first character again because it has aligned address.
7425 if (ae == StrIntrinsicNode::LL) {
7426 stride2 = 32;
7427 } else {
7428 stride2 = 16;
7429 }
7430 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7431 adr_stride = stride << scale;
7432 } else {
7433 adr_stride1 = 8; //stride << scale1;
7434 adr_stride2 = 16; //stride << scale2;
7435 }
7436
7437 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
7438 // rax and rdx are used by pcmpestri as elements counters
7439 movl(result, cnt2);
7440 andl(cnt2, ~(stride2-1)); // cnt2 holds the vector count
7441 jcc(Assembler::zero, COMPARE_TAIL_LONG);
7442
7443 // fast path : compare first 2 8-char vectors.
7444 bind(COMPARE_16_CHARS);
7445 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7446 movdqu(vec1, Address(str1, 0));
7447 } else {
7448 pmovzxbw(vec1, Address(str1, 0));
7449 }
7450 pcmpestri(vec1, Address(str2, 0), pcmpmask);
7451 jccb(Assembler::below, COMPARE_INDEX_CHAR);
7452
7453 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7454 movdqu(vec1, Address(str1, adr_stride));
7455 pcmpestri(vec1, Address(str2, adr_stride), pcmpmask);
7456 } else {
7457 pmovzxbw(vec1, Address(str1, adr_stride1));
7458 pcmpestri(vec1, Address(str2, adr_stride2), pcmpmask);
7459 }
7460 jccb(Assembler::aboveEqual, COMPARE_WIDE_VECTORS);
7461 addl(cnt1, stride);
7462
7463 // Compare the characters at index in cnt1
7464 bind(COMPARE_INDEX_CHAR); // cnt1 has the offset of the mismatching character
7465 load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae);
7466 subl(result, cnt2);
7467 jmp(POP_LABEL);
7468
7469 // Setup the registers to start vector comparison loop
7470 bind(COMPARE_WIDE_VECTORS);
7471 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7472 lea(str1, Address(str1, result, scale));
7473 lea(str2, Address(str2, result, scale));
7474 } else {
7475 lea(str1, Address(str1, result, scale1));
7476 lea(str2, Address(str2, result, scale2));
7477 }
7478 subl(result, stride2);
7479 subl(cnt2, stride2);
7480 jcc(Assembler::zero, COMPARE_WIDE_TAIL);
7481 negptr(result);
7482
7483 // In a loop, compare 16-chars (32-bytes) at once using (vpxor+vptest)
7484 bind(COMPARE_WIDE_VECTORS_LOOP);
7485
7486 #ifdef _LP64
7487 if (VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop
7488 cmpl(cnt2, stride2x2);
7489 jccb(Assembler::below, COMPARE_WIDE_VECTORS_LOOP_AVX2);
7490 testl(cnt2, stride2x2-1); // cnt2 holds the vector count
7491 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX2); // means we cannot subtract by 0x40
7492
7493 bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop
7494 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7495 evmovdquq(vec1, Address(str1, result, scale), Assembler::AVX_512bit);
7496 evpcmpeqb(k7, vec1, Address(str2, result, scale), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0
7497 } else {
7498 vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_512bit);
7499 evpcmpeqb(k7, vec1, Address(str2, result, scale2), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0
7500 }
7501 kortestql(k7, k7);
7502 jcc(Assembler::aboveEqual, COMPARE_WIDE_VECTORS_LOOP_FAILED); // miscompare
7503 addptr(result, stride2x2); // update since we already compared at this addr
7504 subl(cnt2, stride2x2); // and sub the size too
7505 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX3);
7506
7507 vpxor(vec1, vec1);
7508 jmpb(COMPARE_WIDE_TAIL);
7509 }//if (VM_Version::supports_avx512vlbw())
7510 #endif // _LP64
7511
7512
7513 bind(COMPARE_WIDE_VECTORS_LOOP_AVX2);
7514 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7515 vmovdqu(vec1, Address(str1, result, scale));
7516 vpxor(vec1, Address(str2, result, scale));
7517 } else {
7518 vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_256bit);
7519 vpxor(vec1, Address(str2, result, scale2));
7520 }
7521 vptest(vec1, vec1);
7522 jcc(Assembler::notZero, VECTOR_NOT_EQUAL);
7523 addptr(result, stride2);
7524 subl(cnt2, stride2);
7525 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP);
7526 // clean upper bits of YMM registers
7527 vpxor(vec1, vec1);
7528
7529 // compare wide vectors tail
7530 bind(COMPARE_WIDE_TAIL);
7531 testptr(result, result);
7532 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
7533
7534 movl(result, stride2);
7535 movl(cnt2, result);
7536 negptr(result);
7537 jmp(COMPARE_WIDE_VECTORS_LOOP_AVX2);
7538
7539 // Identifies the mismatching (higher or lower)16-bytes in the 32-byte vectors.
7540 bind(VECTOR_NOT_EQUAL);
7541 // clean upper bits of YMM registers
7542 vpxor(vec1, vec1);
7543 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7544 lea(str1, Address(str1, result, scale));
7545 lea(str2, Address(str2, result, scale));
7546 } else {
7547 lea(str1, Address(str1, result, scale1));
7548 lea(str2, Address(str2, result, scale2));
7549 }
7550 jmp(COMPARE_16_CHARS);
7551
7552 // Compare tail chars, length between 1 to 15 chars
7553 bind(COMPARE_TAIL_LONG);
7554 movl(cnt2, result);
7555 cmpl(cnt2, stride);
7556 jcc(Assembler::less, COMPARE_SMALL_STR);
7557
7558 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7559 movdqu(vec1, Address(str1, 0));
7560 } else {
7561 pmovzxbw(vec1, Address(str1, 0));
7562 }
7563 pcmpestri(vec1, Address(str2, 0), pcmpmask);
7564 jcc(Assembler::below, COMPARE_INDEX_CHAR);
7565 subptr(cnt2, stride);
7566 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
7567 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7568 lea(str1, Address(str1, result, scale));
7569 lea(str2, Address(str2, result, scale));
7570 } else {
7571 lea(str1, Address(str1, result, scale1));
7572 lea(str2, Address(str2, result, scale2));
7573 }
7574 negptr(cnt2);
7575 jmpb(WHILE_HEAD_LABEL);
7576
7577 bind(COMPARE_SMALL_STR);
7578 } else if (UseSSE42Intrinsics) {
7579 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL;
7580 int pcmpmask = 0x19;
7581 // Setup to compare 8-char (16-byte) vectors,
7582 // start from first character again because it has aligned address.
7583 movl(result, cnt2);
7584 andl(cnt2, ~(stride - 1)); // cnt2 holds the vector count
7585 if (ae == StrIntrinsicNode::LL) {
7586 pcmpmask &= ~0x01;
7587 }
7588 jcc(Assembler::zero, COMPARE_TAIL);
7589 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7590 lea(str1, Address(str1, result, scale));
7591 lea(str2, Address(str2, result, scale));
7592 } else {
7593 lea(str1, Address(str1, result, scale1));
7594 lea(str2, Address(str2, result, scale2));
7595 }
7596 negptr(result);
7597
7598 // pcmpestri
7599 // inputs:
7600 // vec1- substring
7601 // rax - negative string length (elements count)
7602 // mem - scanned string
7603 // rdx - string length (elements count)
7604 // pcmpmask - cmp mode: 11000 (string compare with negated result)
7605 // + 00 (unsigned bytes) or + 01 (unsigned shorts)
7606 // outputs:
7607 // rcx - first mismatched element index
7608 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
7609
7610 bind(COMPARE_WIDE_VECTORS);
7611 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7612 movdqu(vec1, Address(str1, result, scale));
7613 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
7614 } else {
7615 pmovzxbw(vec1, Address(str1, result, scale1));
7616 pcmpestri(vec1, Address(str2, result, scale2), pcmpmask);
7617 }
7618 // After pcmpestri cnt1(rcx) contains mismatched element index
7619
7620 jccb(Assembler::below, VECTOR_NOT_EQUAL); // CF==1
7621 addptr(result, stride);
7622 subptr(cnt2, stride);
7623 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS);
7624
7625 // compare wide vectors tail
7626 testptr(result, result);
7627 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
7628
7629 movl(cnt2, stride);
7630 movl(result, stride);
7631 negptr(result);
7632 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7633 movdqu(vec1, Address(str1, result, scale));
7634 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
7635 } else {
7636 pmovzxbw(vec1, Address(str1, result, scale1));
7637 pcmpestri(vec1, Address(str2, result, scale2), pcmpmask);
7638 }
7639 jccb(Assembler::aboveEqual, LENGTH_DIFF_LABEL);
7640
7641 // Mismatched characters in the vectors
7642 bind(VECTOR_NOT_EQUAL);
7643 addptr(cnt1, result);
7644 load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae);
7645 subl(result, cnt2);
7646 jmpb(POP_LABEL);
7647
7648 bind(COMPARE_TAIL); // limit is zero
7649 movl(cnt2, result);
7650 // Fallthru to tail compare
7651 }
7652 // Shift str2 and str1 to the end of the arrays, negate min
7653 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7654 lea(str1, Address(str1, cnt2, scale));
7655 lea(str2, Address(str2, cnt2, scale));
7656 } else {
7657 lea(str1, Address(str1, cnt2, scale1));
7658 lea(str2, Address(str2, cnt2, scale2));
7659 }
7660 decrementl(cnt2); // first character was compared already
7661 negptr(cnt2);
7662
7663 // Compare the rest of the elements
7664 bind(WHILE_HEAD_LABEL);
7665 load_next_elements(result, cnt1, str1, str2, scale, scale1, scale2, cnt2, ae);
7666 subl(result, cnt1);
7667 jccb(Assembler::notZero, POP_LABEL);
7668 increment(cnt2);
7669 jccb(Assembler::notZero, WHILE_HEAD_LABEL);
7670
7671 // Strings are equal up to min length. Return the length difference.
7672 bind(LENGTH_DIFF_LABEL);
7673 pop(result);
7674 if (ae == StrIntrinsicNode::UU) {
7675 // Divide diff by 2 to get number of chars
7676 sarl(result, 1);
7677 }
7678 jmpb(DONE_LABEL);
7679
7680 #ifdef _LP64
7681 if (VM_Version::supports_avx512vlbw()) {
7682
7683 bind(COMPARE_WIDE_VECTORS_LOOP_FAILED);
7684
7685 kmovql(cnt1, k7);
7686 notq(cnt1);
7687 bsfq(cnt2, cnt1);
7688 if (ae != StrIntrinsicNode::LL) {
7689 // Divide diff by 2 to get number of chars
7690 sarl(cnt2, 1);
7691 }
7692 addq(result, cnt2);
7693 if (ae == StrIntrinsicNode::LL) {
7694 load_unsigned_byte(cnt1, Address(str2, result));
7695 load_unsigned_byte(result, Address(str1, result));
7696 } else if (ae == StrIntrinsicNode::UU) {
7697 load_unsigned_short(cnt1, Address(str2, result, scale));
7698 load_unsigned_short(result, Address(str1, result, scale));
7699 } else {
7700 load_unsigned_short(cnt1, Address(str2, result, scale2));
7701 load_unsigned_byte(result, Address(str1, result, scale1));
7702 }
7703 subl(result, cnt1);
7704 jmpb(POP_LABEL);
7705 }//if (VM_Version::supports_avx512vlbw())
7706 #endif // _LP64
7707
7708 // Discard the stored length difference
7709 bind(POP_LABEL);
7710 pop(cnt1);
7711
7712 // That's it
7713 bind(DONE_LABEL);
7714 if(ae == StrIntrinsicNode::UL) {
7715 negl(result);
7716 }
7717
7718 }
7719
7720 // Search for Non-ASCII character (Negative byte value) in a byte array,
7721 // return true if it has any and false otherwise.
7722 // ..\jdk\src\java.base\share\classes\java\lang\StringCoding.java
7723 // @HotSpotIntrinsicCandidate
7724 // private static boolean hasNegatives(byte[] ba, int off, int len) {
7725 // for (int i = off; i < off + len; i++) {
7726 // if (ba[i] < 0) {
7727 // return true;
7728 // }
7729 // }
7730 // return false;
7731 // }
7732 void MacroAssembler::has_negatives(Register ary1, Register len,
7733 Register result, Register tmp1,
7734 XMMRegister vec1, XMMRegister vec2) {
7735 // rsi: byte array
7736 // rcx: len
7737 // rax: result
7738 ShortBranchVerifier sbv(this);
7739 assert_different_registers(ary1, len, result, tmp1);
7740 assert_different_registers(vec1, vec2);
7741 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_CHAR, COMPARE_VECTORS, COMPARE_BYTE;
7742
7743 // len == 0
7744 testl(len, len);
7745 jcc(Assembler::zero, FALSE_LABEL);
7746
7747 if ((UseAVX > 2) && // AVX512
7748 VM_Version::supports_avx512vlbw() &&
7749 VM_Version::supports_bmi2()) {
7750
7751 set_vector_masking(); // opening of the stub context for programming mask registers
7752
7753 Label test_64_loop, test_tail;
7754 Register tmp3_aliased = len;
7755
7756 movl(tmp1, len);
7757 vpxor(vec2, vec2, vec2, Assembler::AVX_512bit);
7758
7759 andl(tmp1, 64 - 1); // tail count (in chars) 0x3F
7760 andl(len, ~(64 - 1)); // vector count (in chars)
7761 jccb(Assembler::zero, test_tail);
7762
7763 lea(ary1, Address(ary1, len, Address::times_1));
7764 negptr(len);
7765
7766 bind(test_64_loop);
7767 // Check whether our 64 elements of size byte contain negatives
7768 evpcmpgtb(k2, vec2, Address(ary1, len, Address::times_1), Assembler::AVX_512bit);
7769 kortestql(k2, k2);
7770 jcc(Assembler::notZero, TRUE_LABEL);
7771
7772 addptr(len, 64);
7773 jccb(Assembler::notZero, test_64_loop);
7774
7775
7776 bind(test_tail);
7777 // bail out when there is nothing to be done
7778 testl(tmp1, -1);
7779 jcc(Assembler::zero, FALSE_LABEL);
7780
7781 // Save k1
7782 kmovql(k3, k1);
7783
7784 // ~(~0 << len) applied up to two times (for 32-bit scenario)
7785 #ifdef _LP64
7786 mov64(tmp3_aliased, 0xFFFFFFFFFFFFFFFF);
7787 shlxq(tmp3_aliased, tmp3_aliased, tmp1);
7788 notq(tmp3_aliased);
7789 kmovql(k1, tmp3_aliased);
7790 #else
7791 Label k_init;
7792 jmp(k_init);
7793
7794 // We could not read 64-bits from a general purpose register thus we move
7795 // data required to compose 64 1's to the instruction stream
7796 // We emit 64 byte wide series of elements from 0..63 which later on would
7797 // be used as a compare targets with tail count contained in tmp1 register.
7798 // Result would be a k1 register having tmp1 consecutive number or 1
7799 // counting from least significant bit.
7800 address tmp = pc();
7801 emit_int64(0x0706050403020100);
7802 emit_int64(0x0F0E0D0C0B0A0908);
7803 emit_int64(0x1716151413121110);
7804 emit_int64(0x1F1E1D1C1B1A1918);
7805 emit_int64(0x2726252423222120);
7806 emit_int64(0x2F2E2D2C2B2A2928);
7807 emit_int64(0x3736353433323130);
7808 emit_int64(0x3F3E3D3C3B3A3938);
7809
7810 bind(k_init);
7811 lea(len, InternalAddress(tmp));
7812 // create mask to test for negative byte inside a vector
7813 evpbroadcastb(vec1, tmp1, Assembler::AVX_512bit);
7814 evpcmpgtb(k1, vec1, Address(len, 0), Assembler::AVX_512bit);
7815
7816 #endif
7817 evpcmpgtb(k2, k1, vec2, Address(ary1, 0), Assembler::AVX_512bit);
7818 ktestq(k2, k1);
7819 // Restore k1
7820 kmovql(k1, k3);
7821 jcc(Assembler::notZero, TRUE_LABEL);
7822
7823 jmp(FALSE_LABEL);
7824
7825 clear_vector_masking(); // closing of the stub context for programming mask registers
7826 } else {
7827 movl(result, len); // copy
7828
7829 if (UseAVX == 2 && UseSSE >= 2) {
7830 // With AVX2, use 32-byte vector compare
7831 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
7832
7833 // Compare 32-byte vectors
7834 andl(result, 0x0000001f); // tail count (in bytes)
7835 andl(len, 0xffffffe0); // vector count (in bytes)
7836 jccb(Assembler::zero, COMPARE_TAIL);
7837
7838 lea(ary1, Address(ary1, len, Address::times_1));
7839 negptr(len);
7840
7841 movl(tmp1, 0x80808080); // create mask to test for Unicode chars in vector
7842 movdl(vec2, tmp1);
7843 vpbroadcastd(vec2, vec2);
7844
7845 bind(COMPARE_WIDE_VECTORS);
7846 vmovdqu(vec1, Address(ary1, len, Address::times_1));
7847 vptest(vec1, vec2);
7848 jccb(Assembler::notZero, TRUE_LABEL);
7849 addptr(len, 32);
7850 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
7851
7852 testl(result, result);
7853 jccb(Assembler::zero, FALSE_LABEL);
7854
7855 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32));
7856 vptest(vec1, vec2);
7857 jccb(Assembler::notZero, TRUE_LABEL);
7858 jmpb(FALSE_LABEL);
7859
7860 bind(COMPARE_TAIL); // len is zero
7861 movl(len, result);
7862 // Fallthru to tail compare
7863 } else if (UseSSE42Intrinsics) {
7864 // With SSE4.2, use double quad vector compare
7865 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
7866
7867 // Compare 16-byte vectors
7868 andl(result, 0x0000000f); // tail count (in bytes)
7869 andl(len, 0xfffffff0); // vector count (in bytes)
7870 jcc(Assembler::zero, COMPARE_TAIL);
7871
7872 lea(ary1, Address(ary1, len, Address::times_1));
7873 negptr(len);
7874
7875 movl(tmp1, 0x80808080);
7876 movdl(vec2, tmp1);
7877 pshufd(vec2, vec2, 0);
7878
7879 bind(COMPARE_WIDE_VECTORS);
7880 movdqu(vec1, Address(ary1, len, Address::times_1));
7881 ptest(vec1, vec2);
7882 jcc(Assembler::notZero, TRUE_LABEL);
7883 addptr(len, 16);
7884 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
7885
7886 testl(result, result);
7887 jcc(Assembler::zero, FALSE_LABEL);
7888
7889 movdqu(vec1, Address(ary1, result, Address::times_1, -16));
7890 ptest(vec1, vec2);
7891 jccb(Assembler::notZero, TRUE_LABEL);
7892 jmpb(FALSE_LABEL);
7893
7894 bind(COMPARE_TAIL); // len is zero
7895 movl(len, result);
7896 // Fallthru to tail compare
7897 }
7898 }
7899 // Compare 4-byte vectors
7900 andl(len, 0xfffffffc); // vector count (in bytes)
7901 jccb(Assembler::zero, COMPARE_CHAR);
7902
7903 lea(ary1, Address(ary1, len, Address::times_1));
7904 negptr(len);
7905
7906 bind(COMPARE_VECTORS);
7907 movl(tmp1, Address(ary1, len, Address::times_1));
7908 andl(tmp1, 0x80808080);
7909 jccb(Assembler::notZero, TRUE_LABEL);
7910 addptr(len, 4);
7911 jcc(Assembler::notZero, COMPARE_VECTORS);
7912
7913 // Compare trailing char (final 2 bytes), if any
7914 bind(COMPARE_CHAR);
7915 testl(result, 0x2); // tail char
7916 jccb(Assembler::zero, COMPARE_BYTE);
7917 load_unsigned_short(tmp1, Address(ary1, 0));
7918 andl(tmp1, 0x00008080);
7919 jccb(Assembler::notZero, TRUE_LABEL);
7920 subptr(result, 2);
7921 lea(ary1, Address(ary1, 2));
7922
7923 bind(COMPARE_BYTE);
7924 testl(result, 0x1); // tail byte
7925 jccb(Assembler::zero, FALSE_LABEL);
7926 load_unsigned_byte(tmp1, Address(ary1, 0));
7927 andl(tmp1, 0x00000080);
7928 jccb(Assembler::notEqual, TRUE_LABEL);
7929 jmpb(FALSE_LABEL);
7930
7931 bind(TRUE_LABEL);
7932 movl(result, 1); // return true
7933 jmpb(DONE);
7934
7935 bind(FALSE_LABEL);
7936 xorl(result, result); // return false
7937
7938 // That's it
7939 bind(DONE);
7940 if (UseAVX >= 2 && UseSSE >= 2) {
7941 // clean upper bits of YMM registers
7942 vpxor(vec1, vec1);
7943 vpxor(vec2, vec2);
7944 }
7945 }
7946 // Compare char[] or byte[] arrays aligned to 4 bytes or substrings.
7947 void MacroAssembler::arrays_equals(bool is_array_equ, Register ary1, Register ary2,
7948 Register limit, Register result, Register chr,
7949 XMMRegister vec1, XMMRegister vec2, bool is_char) {
7950 ShortBranchVerifier sbv(this);
7951 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR, COMPARE_BYTE;
7952
7953 int length_offset = arrayOopDesc::length_offset_in_bytes();
7954 int base_offset = arrayOopDesc::base_offset_in_bytes(is_char ? T_CHAR : T_BYTE);
7955
7956 if (is_array_equ) {
7957 // Check the input args
7958 cmpoop(ary1, ary2);
7959 jcc(Assembler::equal, TRUE_LABEL);
7960
7961 // Need additional checks for arrays_equals.
7962 testptr(ary1, ary1);
7963 jcc(Assembler::zero, FALSE_LABEL);
7964 testptr(ary2, ary2);
7965 jcc(Assembler::zero, FALSE_LABEL);
7966
7967 // Check the lengths
7968 movl(limit, Address(ary1, length_offset));
7969 cmpl(limit, Address(ary2, length_offset));
7970 jcc(Assembler::notEqual, FALSE_LABEL);
7971 }
7972
7973 // count == 0
7974 testl(limit, limit);
7975 jcc(Assembler::zero, TRUE_LABEL);
7976
7977 if (is_array_equ) {
7978 // Load array address
7979 lea(ary1, Address(ary1, base_offset));
7980 lea(ary2, Address(ary2, base_offset));
7981 }
7982
7983 if (is_array_equ && is_char) {
7984 // arrays_equals when used for char[].
7985 shll(limit, 1); // byte count != 0
7986 }
7987 movl(result, limit); // copy
7988
7989 if (UseAVX >= 2) {
7990 // With AVX2, use 32-byte vector compare
7991 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
7992
7993 // Compare 32-byte vectors
7994 andl(result, 0x0000001f); // tail count (in bytes)
7995 andl(limit, 0xffffffe0); // vector count (in bytes)
7996 jcc(Assembler::zero, COMPARE_TAIL);
7997
7998 lea(ary1, Address(ary1, limit, Address::times_1));
7999 lea(ary2, Address(ary2, limit, Address::times_1));
8000 negptr(limit);
8001
8002 bind(COMPARE_WIDE_VECTORS);
8003
8004 #ifdef _LP64
8005 if (VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop
8006 Label COMPARE_WIDE_VECTORS_LOOP_AVX2, COMPARE_WIDE_VECTORS_LOOP_AVX3;
8007
8008 cmpl(limit, -64);
8009 jccb(Assembler::greater, COMPARE_WIDE_VECTORS_LOOP_AVX2);
8010
8011 bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop
8012
8013 evmovdquq(vec1, Address(ary1, limit, Address::times_1), Assembler::AVX_512bit);
8014 evpcmpeqb(k7, vec1, Address(ary2, limit, Address::times_1), Assembler::AVX_512bit);
8015 kortestql(k7, k7);
8016 jcc(Assembler::aboveEqual, FALSE_LABEL); // miscompare
8017 addptr(limit, 64); // update since we already compared at this addr
8018 cmpl(limit, -64);
8019 jccb(Assembler::lessEqual, COMPARE_WIDE_VECTORS_LOOP_AVX3);
8020
8021 // At this point we may still need to compare -limit+result bytes.
8022 // We could execute the next two instruction and just continue via non-wide path:
8023 // cmpl(limit, 0);
8024 // jcc(Assembler::equal, COMPARE_TAIL); // true
8025 // But since we stopped at the points ary{1,2}+limit which are
8026 // not farther than 64 bytes from the ends of arrays ary{1,2}+result
8027 // (|limit| <= 32 and result < 32),
8028 // we may just compare the last 64 bytes.
8029 //
8030 addptr(result, -64); // it is safe, bc we just came from this area
8031 evmovdquq(vec1, Address(ary1, result, Address::times_1), Assembler::AVX_512bit);
8032 evpcmpeqb(k7, vec1, Address(ary2, result, Address::times_1), Assembler::AVX_512bit);
8033 kortestql(k7, k7);
8034 jcc(Assembler::aboveEqual, FALSE_LABEL); // miscompare
8035
8036 jmp(TRUE_LABEL);
8037
8038 bind(COMPARE_WIDE_VECTORS_LOOP_AVX2);
8039
8040 }//if (VM_Version::supports_avx512vlbw())
8041 #endif //_LP64
8042
8043 vmovdqu(vec1, Address(ary1, limit, Address::times_1));
8044 vmovdqu(vec2, Address(ary2, limit, Address::times_1));
8045 vpxor(vec1, vec2);
8046
8047 vptest(vec1, vec1);
8048 jcc(Assembler::notZero, FALSE_LABEL);
8049 addptr(limit, 32);
8050 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
8051
8052 testl(result, result);
8053 jcc(Assembler::zero, TRUE_LABEL);
8054
8055 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32));
8056 vmovdqu(vec2, Address(ary2, result, Address::times_1, -32));
8057 vpxor(vec1, vec2);
8058
8059 vptest(vec1, vec1);
8060 jccb(Assembler::notZero, FALSE_LABEL);
8061 jmpb(TRUE_LABEL);
8062
8063 bind(COMPARE_TAIL); // limit is zero
8064 movl(limit, result);
8065 // Fallthru to tail compare
8066 } else if (UseSSE42Intrinsics) {
8067 // With SSE4.2, use double quad vector compare
8068 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
8069
8070 // Compare 16-byte vectors
8071 andl(result, 0x0000000f); // tail count (in bytes)
8072 andl(limit, 0xfffffff0); // vector count (in bytes)
8073 jcc(Assembler::zero, COMPARE_TAIL);
8074
8075 lea(ary1, Address(ary1, limit, Address::times_1));
8076 lea(ary2, Address(ary2, limit, Address::times_1));
8077 negptr(limit);
8078
8079 bind(COMPARE_WIDE_VECTORS);
8080 movdqu(vec1, Address(ary1, limit, Address::times_1));
8081 movdqu(vec2, Address(ary2, limit, Address::times_1));
8082 pxor(vec1, vec2);
8083
8084 ptest(vec1, vec1);
8085 jcc(Assembler::notZero, FALSE_LABEL);
8086 addptr(limit, 16);
8087 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
8088
8089 testl(result, result);
8090 jcc(Assembler::zero, TRUE_LABEL);
8091
8092 movdqu(vec1, Address(ary1, result, Address::times_1, -16));
8093 movdqu(vec2, Address(ary2, result, Address::times_1, -16));
8094 pxor(vec1, vec2);
8095
8096 ptest(vec1, vec1);
8097 jccb(Assembler::notZero, FALSE_LABEL);
8098 jmpb(TRUE_LABEL);
8099
8100 bind(COMPARE_TAIL); // limit is zero
8101 movl(limit, result);
8102 // Fallthru to tail compare
8103 }
8104
8105 // Compare 4-byte vectors
8106 andl(limit, 0xfffffffc); // vector count (in bytes)
8107 jccb(Assembler::zero, COMPARE_CHAR);
8108
8109 lea(ary1, Address(ary1, limit, Address::times_1));
8110 lea(ary2, Address(ary2, limit, Address::times_1));
8111 negptr(limit);
8112
8113 bind(COMPARE_VECTORS);
8114 movl(chr, Address(ary1, limit, Address::times_1));
8115 cmpl(chr, Address(ary2, limit, Address::times_1));
8116 jccb(Assembler::notEqual, FALSE_LABEL);
8117 addptr(limit, 4);
8118 jcc(Assembler::notZero, COMPARE_VECTORS);
8119
8120 // Compare trailing char (final 2 bytes), if any
8121 bind(COMPARE_CHAR);
8122 testl(result, 0x2); // tail char
8123 jccb(Assembler::zero, COMPARE_BYTE);
8124 load_unsigned_short(chr, Address(ary1, 0));
8125 load_unsigned_short(limit, Address(ary2, 0));
8126 cmpl(chr, limit);
8127 jccb(Assembler::notEqual, FALSE_LABEL);
8128
8129 if (is_array_equ && is_char) {
8130 bind(COMPARE_BYTE);
8131 } else {
8132 lea(ary1, Address(ary1, 2));
8133 lea(ary2, Address(ary2, 2));
8134
8135 bind(COMPARE_BYTE);
8136 testl(result, 0x1); // tail byte
8137 jccb(Assembler::zero, TRUE_LABEL);
8138 load_unsigned_byte(chr, Address(ary1, 0));
8139 load_unsigned_byte(limit, Address(ary2, 0));
8140 cmpl(chr, limit);
8141 jccb(Assembler::notEqual, FALSE_LABEL);
8142 }
8143 bind(TRUE_LABEL);
8144 movl(result, 1); // return true
8145 jmpb(DONE);
8146
8147 bind(FALSE_LABEL);
8148 xorl(result, result); // return false
8149
8150 // That's it
8151 bind(DONE);
8152 if (UseAVX >= 2) {
8153 // clean upper bits of YMM registers
8154 vpxor(vec1, vec1);
8155 vpxor(vec2, vec2);
8156 }
8157 }
8158
8159 #endif
8160
8161 void MacroAssembler::generate_fill(BasicType t, bool aligned,
8162 Register to, Register value, Register count,
8163 Register rtmp, XMMRegister xtmp) {
8164 ShortBranchVerifier sbv(this);
8165 assert_different_registers(to, value, count, rtmp);
8166 Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte;
8167 Label L_fill_2_bytes, L_fill_4_bytes;
8168
8169 int shift = -1;
8170 switch (t) {
8171 case T_BYTE:
8172 shift = 2;
8173 break;
8174 case T_SHORT:
8175 shift = 1;
8176 break;
8177 case T_INT:
8178 shift = 0;
8179 break;
8180 default: ShouldNotReachHere();
8181 }
8182
8183 if (t == T_BYTE) {
8184 andl(value, 0xff);
8185 movl(rtmp, value);
8186 shll(rtmp, 8);
8187 orl(value, rtmp);
8188 }
8189 if (t == T_SHORT) {
8190 andl(value, 0xffff);
8191 }
8192 if (t == T_BYTE || t == T_SHORT) {
8193 movl(rtmp, value);
8194 shll(rtmp, 16);
8195 orl(value, rtmp);
8196 }
8197
8198 cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element
8199 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
8200 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
8201 // align source address at 4 bytes address boundary
8202 if (t == T_BYTE) {
8203 // One byte misalignment happens only for byte arrays
8204 testptr(to, 1);
8205 jccb(Assembler::zero, L_skip_align1);
8206 movb(Address(to, 0), value);
8207 increment(to);
8208 decrement(count);
8209 BIND(L_skip_align1);
8210 }
8211 // Two bytes misalignment happens only for byte and short (char) arrays
8212 testptr(to, 2);
8213 jccb(Assembler::zero, L_skip_align2);
8214 movw(Address(to, 0), value);
8215 addptr(to, 2);
8216 subl(count, 1<<(shift-1));
8217 BIND(L_skip_align2);
8218 }
8219 if (UseSSE < 2) {
8220 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
8221 // Fill 32-byte chunks
8222 subl(count, 8 << shift);
8223 jcc(Assembler::less, L_check_fill_8_bytes);
8224 align(16);
8225
8226 BIND(L_fill_32_bytes_loop);
8227
8228 for (int i = 0; i < 32; i += 4) {
8229 movl(Address(to, i), value);
8230 }
8231
8232 addptr(to, 32);
8233 subl(count, 8 << shift);
8234 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
8235 BIND(L_check_fill_8_bytes);
8236 addl(count, 8 << shift);
8237 jccb(Assembler::zero, L_exit);
8238 jmpb(L_fill_8_bytes);
8239
8240 //
8241 // length is too short, just fill qwords
8242 //
8243 BIND(L_fill_8_bytes_loop);
8244 movl(Address(to, 0), value);
8245 movl(Address(to, 4), value);
8246 addptr(to, 8);
8247 BIND(L_fill_8_bytes);
8248 subl(count, 1 << (shift + 1));
8249 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
8250 // fall through to fill 4 bytes
8251 } else {
8252 Label L_fill_32_bytes;
8253 if (!UseUnalignedLoadStores) {
8254 // align to 8 bytes, we know we are 4 byte aligned to start
8255 testptr(to, 4);
8256 jccb(Assembler::zero, L_fill_32_bytes);
8257 movl(Address(to, 0), value);
8258 addptr(to, 4);
8259 subl(count, 1<<shift);
8260 }
8261 BIND(L_fill_32_bytes);
8262 {
8263 assert( UseSSE >= 2, "supported cpu only" );
8264 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
8265 if (UseAVX > 2) {
8266 movl(rtmp, 0xffff);
8267 kmovwl(k1, rtmp);
8268 }
8269 movdl(xtmp, value);
8270 if (UseAVX > 2 && UseUnalignedLoadStores) {
8271 // Fill 64-byte chunks
8272 Label L_fill_64_bytes_loop, L_check_fill_32_bytes;
8273 evpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit);
8274
8275 subl(count, 16 << shift);
8276 jcc(Assembler::less, L_check_fill_32_bytes);
8277 align(16);
8278
8279 BIND(L_fill_64_bytes_loop);
8280 evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit);
8281 addptr(to, 64);
8282 subl(count, 16 << shift);
8283 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
8284
8285 BIND(L_check_fill_32_bytes);
8286 addl(count, 8 << shift);
8287 jccb(Assembler::less, L_check_fill_8_bytes);
8288 vmovdqu(Address(to, 0), xtmp);
8289 addptr(to, 32);
8290 subl(count, 8 << shift);
8291
8292 BIND(L_check_fill_8_bytes);
8293 } else if (UseAVX == 2 && UseUnalignedLoadStores) {
8294 // Fill 64-byte chunks
8295 Label L_fill_64_bytes_loop, L_check_fill_32_bytes;
8296 vpbroadcastd(xtmp, xtmp);
8297
8298 subl(count, 16 << shift);
8299 jcc(Assembler::less, L_check_fill_32_bytes);
8300 align(16);
8301
8302 BIND(L_fill_64_bytes_loop);
8303 vmovdqu(Address(to, 0), xtmp);
8304 vmovdqu(Address(to, 32), xtmp);
8305 addptr(to, 64);
8306 subl(count, 16 << shift);
8307 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
8308
8309 BIND(L_check_fill_32_bytes);
8310 addl(count, 8 << shift);
8311 jccb(Assembler::less, L_check_fill_8_bytes);
8312 vmovdqu(Address(to, 0), xtmp);
8313 addptr(to, 32);
8314 subl(count, 8 << shift);
8315
8316 BIND(L_check_fill_8_bytes);
8317 // clean upper bits of YMM registers
8318 movdl(xtmp, value);
8319 pshufd(xtmp, xtmp, 0);
8320 } else {
8321 // Fill 32-byte chunks
8322 pshufd(xtmp, xtmp, 0);
8323
8324 subl(count, 8 << shift);
8325 jcc(Assembler::less, L_check_fill_8_bytes);
8326 align(16);
8327
8328 BIND(L_fill_32_bytes_loop);
8329
8330 if (UseUnalignedLoadStores) {
8331 movdqu(Address(to, 0), xtmp);
8332 movdqu(Address(to, 16), xtmp);
8333 } else {
8334 movq(Address(to, 0), xtmp);
8335 movq(Address(to, 8), xtmp);
8336 movq(Address(to, 16), xtmp);
8337 movq(Address(to, 24), xtmp);
8338 }
8339
8340 addptr(to, 32);
8341 subl(count, 8 << shift);
8342 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
8343
8344 BIND(L_check_fill_8_bytes);
8345 }
8346 addl(count, 8 << shift);
8347 jccb(Assembler::zero, L_exit);
8348 jmpb(L_fill_8_bytes);
8349
8350 //
8351 // length is too short, just fill qwords
8352 //
8353 BIND(L_fill_8_bytes_loop);
8354 movq(Address(to, 0), xtmp);
8355 addptr(to, 8);
8356 BIND(L_fill_8_bytes);
8357 subl(count, 1 << (shift + 1));
8358 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
8359 }
8360 }
8361 // fill trailing 4 bytes
8362 BIND(L_fill_4_bytes);
8363 testl(count, 1<<shift);
8364 jccb(Assembler::zero, L_fill_2_bytes);
8365 movl(Address(to, 0), value);
8366 if (t == T_BYTE || t == T_SHORT) {
8367 addptr(to, 4);
8368 BIND(L_fill_2_bytes);
8369 // fill trailing 2 bytes
8370 testl(count, 1<<(shift-1));
8371 jccb(Assembler::zero, L_fill_byte);
8372 movw(Address(to, 0), value);
8373 if (t == T_BYTE) {
8374 addptr(to, 2);
8375 BIND(L_fill_byte);
8376 // fill trailing byte
8377 testl(count, 1);
8378 jccb(Assembler::zero, L_exit);
8379 movb(Address(to, 0), value);
8380 } else {
8381 BIND(L_fill_byte);
8382 }
8383 } else {
8384 BIND(L_fill_2_bytes);
8385 }
8386 BIND(L_exit);
8387 }
8388
8389 // encode char[] to byte[] in ISO_8859_1
8390 //@HotSpotIntrinsicCandidate
8391 //private static int implEncodeISOArray(byte[] sa, int sp,
8392 //byte[] da, int dp, int len) {
8393 // int i = 0;
8394 // for (; i < len; i++) {
8395 // char c = StringUTF16.getChar(sa, sp++);
8396 // if (c > '\u00FF')
8397 // break;
8398 // da[dp++] = (byte)c;
8399 // }
8400 // return i;
8401 //}
8402 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
8403 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
8404 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
8405 Register tmp5, Register result) {
8406
8407 // rsi: src
8408 // rdi: dst
8409 // rdx: len
8410 // rcx: tmp5
8411 // rax: result
8412 ShortBranchVerifier sbv(this);
8413 assert_different_registers(src, dst, len, tmp5, result);
8414 Label L_done, L_copy_1_char, L_copy_1_char_exit;
8415
8416 // set result
8417 xorl(result, result);
8418 // check for zero length
8419 testl(len, len);
8420 jcc(Assembler::zero, L_done);
8421
8422 movl(result, len);
8423
8424 // Setup pointers
8425 lea(src, Address(src, len, Address::times_2)); // char[]
8426 lea(dst, Address(dst, len, Address::times_1)); // byte[]
8427 negptr(len);
8428
8429 if (UseSSE42Intrinsics || UseAVX >= 2) {
8430 Label L_chars_8_check, L_copy_8_chars, L_copy_8_chars_exit;
8431 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
8432
8433 if (UseAVX >= 2) {
8434 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
8435 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector
8436 movdl(tmp1Reg, tmp5);
8437 vpbroadcastd(tmp1Reg, tmp1Reg);
8438 jmp(L_chars_32_check);
8439
8440 bind(L_copy_32_chars);
8441 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
8442 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
8443 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
8444 vptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
8445 jccb(Assembler::notZero, L_copy_32_chars_exit);
8446 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
8447 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1);
8448 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
8449
8450 bind(L_chars_32_check);
8451 addptr(len, 32);
8452 jcc(Assembler::lessEqual, L_copy_32_chars);
8453
8454 bind(L_copy_32_chars_exit);
8455 subptr(len, 16);
8456 jccb(Assembler::greater, L_copy_16_chars_exit);
8457
8458 } else if (UseSSE42Intrinsics) {
8459 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector
8460 movdl(tmp1Reg, tmp5);
8461 pshufd(tmp1Reg, tmp1Reg, 0);
8462 jmpb(L_chars_16_check);
8463 }
8464
8465 bind(L_copy_16_chars);
8466 if (UseAVX >= 2) {
8467 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
8468 vptest(tmp2Reg, tmp1Reg);
8469 jcc(Assembler::notZero, L_copy_16_chars_exit);
8470 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1);
8471 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1);
8472 } else {
8473 if (UseAVX > 0) {
8474 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
8475 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
8476 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0);
8477 } else {
8478 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
8479 por(tmp2Reg, tmp3Reg);
8480 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
8481 por(tmp2Reg, tmp4Reg);
8482 }
8483 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
8484 jccb(Assembler::notZero, L_copy_16_chars_exit);
8485 packuswb(tmp3Reg, tmp4Reg);
8486 }
8487 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
8488
8489 bind(L_chars_16_check);
8490 addptr(len, 16);
8491 jcc(Assembler::lessEqual, L_copy_16_chars);
8492
8493 bind(L_copy_16_chars_exit);
8494 if (UseAVX >= 2) {
8495 // clean upper bits of YMM registers
8496 vpxor(tmp2Reg, tmp2Reg);
8497 vpxor(tmp3Reg, tmp3Reg);
8498 vpxor(tmp4Reg, tmp4Reg);
8499 movdl(tmp1Reg, tmp5);
8500 pshufd(tmp1Reg, tmp1Reg, 0);
8501 }
8502 subptr(len, 8);
8503 jccb(Assembler::greater, L_copy_8_chars_exit);
8504
8505 bind(L_copy_8_chars);
8506 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
8507 ptest(tmp3Reg, tmp1Reg);
8508 jccb(Assembler::notZero, L_copy_8_chars_exit);
8509 packuswb(tmp3Reg, tmp1Reg);
8510 movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
8511 addptr(len, 8);
8512 jccb(Assembler::lessEqual, L_copy_8_chars);
8513
8514 bind(L_copy_8_chars_exit);
8515 subptr(len, 8);
8516 jccb(Assembler::zero, L_done);
8517 }
8518
8519 bind(L_copy_1_char);
8520 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
8521 testl(tmp5, 0xff00); // check if Unicode char
8522 jccb(Assembler::notZero, L_copy_1_char_exit);
8523 movb(Address(dst, len, Address::times_1, 0), tmp5);
8524 addptr(len, 1);
8525 jccb(Assembler::less, L_copy_1_char);
8526
8527 bind(L_copy_1_char_exit);
8528 addptr(result, len); // len is negative count of not processed elements
8529
8530 bind(L_done);
8531 }
8532
8533 #ifdef _LP64
8534 /**
8535 * Helper for multiply_to_len().
8536 */
8537 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
8538 addq(dest_lo, src1);
8539 adcq(dest_hi, 0);
8540 addq(dest_lo, src2);
8541 adcq(dest_hi, 0);
8542 }
8543
8544 /**
8545 * Multiply 64 bit by 64 bit first loop.
8546 */
8547 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
8548 Register y, Register y_idx, Register z,
8549 Register carry, Register product,
8550 Register idx, Register kdx) {
8551 //
8552 // jlong carry, x[], y[], z[];
8553 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
8554 // huge_128 product = y[idx] * x[xstart] + carry;
8555 // z[kdx] = (jlong)product;
8556 // carry = (jlong)(product >>> 64);
8557 // }
8558 // z[xstart] = carry;
8559 //
8560
8561 Label L_first_loop, L_first_loop_exit;
8562 Label L_one_x, L_one_y, L_multiply;
8563
8564 decrementl(xstart);
8565 jcc(Assembler::negative, L_one_x);
8566
8567 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
8568 rorq(x_xstart, 32); // convert big-endian to little-endian
8569
8570 bind(L_first_loop);
8571 decrementl(idx);
8572 jcc(Assembler::negative, L_first_loop_exit);
8573 decrementl(idx);
8574 jcc(Assembler::negative, L_one_y);
8575 movq(y_idx, Address(y, idx, Address::times_4, 0));
8576 rorq(y_idx, 32); // convert big-endian to little-endian
8577 bind(L_multiply);
8578 movq(product, x_xstart);
8579 mulq(y_idx); // product(rax) * y_idx -> rdx:rax
8580 addq(product, carry);
8581 adcq(rdx, 0);
8582 subl(kdx, 2);
8583 movl(Address(z, kdx, Address::times_4, 4), product);
8584 shrq(product, 32);
8585 movl(Address(z, kdx, Address::times_4, 0), product);
8586 movq(carry, rdx);
8587 jmp(L_first_loop);
8588
8589 bind(L_one_y);
8590 movl(y_idx, Address(y, 0));
8591 jmp(L_multiply);
8592
8593 bind(L_one_x);
8594 movl(x_xstart, Address(x, 0));
8595 jmp(L_first_loop);
8596
8597 bind(L_first_loop_exit);
8598 }
8599
8600 /**
8601 * Multiply 64 bit by 64 bit and add 128 bit.
8602 */
8603 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
8604 Register yz_idx, Register idx,
8605 Register carry, Register product, int offset) {
8606 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
8607 // z[kdx] = (jlong)product;
8608
8609 movq(yz_idx, Address(y, idx, Address::times_4, offset));
8610 rorq(yz_idx, 32); // convert big-endian to little-endian
8611 movq(product, x_xstart);
8612 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
8613 movq(yz_idx, Address(z, idx, Address::times_4, offset));
8614 rorq(yz_idx, 32); // convert big-endian to little-endian
8615
8616 add2_with_carry(rdx, product, carry, yz_idx);
8617
8618 movl(Address(z, idx, Address::times_4, offset+4), product);
8619 shrq(product, 32);
8620 movl(Address(z, idx, Address::times_4, offset), product);
8621
8622 }
8623
8624 /**
8625 * Multiply 128 bit by 128 bit. Unrolled inner loop.
8626 */
8627 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
8628 Register yz_idx, Register idx, Register jdx,
8629 Register carry, Register product,
8630 Register carry2) {
8631 // jlong carry, x[], y[], z[];
8632 // int kdx = ystart+1;
8633 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
8634 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
8635 // z[kdx+idx+1] = (jlong)product;
8636 // jlong carry2 = (jlong)(product >>> 64);
8637 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
8638 // z[kdx+idx] = (jlong)product;
8639 // carry = (jlong)(product >>> 64);
8640 // }
8641 // idx += 2;
8642 // if (idx > 0) {
8643 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
8644 // z[kdx+idx] = (jlong)product;
8645 // carry = (jlong)(product >>> 64);
8646 // }
8647 //
8648
8649 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
8650
8651 movl(jdx, idx);
8652 andl(jdx, 0xFFFFFFFC);
8653 shrl(jdx, 2);
8654
8655 bind(L_third_loop);
8656 subl(jdx, 1);
8657 jcc(Assembler::negative, L_third_loop_exit);
8658 subl(idx, 4);
8659
8660 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
8661 movq(carry2, rdx);
8662
8663 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
8664 movq(carry, rdx);
8665 jmp(L_third_loop);
8666
8667 bind (L_third_loop_exit);
8668
8669 andl (idx, 0x3);
8670 jcc(Assembler::zero, L_post_third_loop_done);
8671
8672 Label L_check_1;
8673 subl(idx, 2);
8674 jcc(Assembler::negative, L_check_1);
8675
8676 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
8677 movq(carry, rdx);
8678
8679 bind (L_check_1);
8680 addl (idx, 0x2);
8681 andl (idx, 0x1);
8682 subl(idx, 1);
8683 jcc(Assembler::negative, L_post_third_loop_done);
8684
8685 movl(yz_idx, Address(y, idx, Address::times_4, 0));
8686 movq(product, x_xstart);
8687 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
8688 movl(yz_idx, Address(z, idx, Address::times_4, 0));
8689
8690 add2_with_carry(rdx, product, yz_idx, carry);
8691
8692 movl(Address(z, idx, Address::times_4, 0), product);
8693 shrq(product, 32);
8694
8695 shlq(rdx, 32);
8696 orq(product, rdx);
8697 movq(carry, product);
8698
8699 bind(L_post_third_loop_done);
8700 }
8701
8702 /**
8703 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
8704 *
8705 */
8706 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
8707 Register carry, Register carry2,
8708 Register idx, Register jdx,
8709 Register yz_idx1, Register yz_idx2,
8710 Register tmp, Register tmp3, Register tmp4) {
8711 assert(UseBMI2Instructions, "should be used only when BMI2 is available");
8712
8713 // jlong carry, x[], y[], z[];
8714 // int kdx = ystart+1;
8715 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
8716 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
8717 // jlong carry2 = (jlong)(tmp3 >>> 64);
8718 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2;
8719 // carry = (jlong)(tmp4 >>> 64);
8720 // z[kdx+idx+1] = (jlong)tmp3;
8721 // z[kdx+idx] = (jlong)tmp4;
8722 // }
8723 // idx += 2;
8724 // if (idx > 0) {
8725 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
8726 // z[kdx+idx] = (jlong)yz_idx1;
8727 // carry = (jlong)(yz_idx1 >>> 64);
8728 // }
8729 //
8730
8731 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
8732
8733 movl(jdx, idx);
8734 andl(jdx, 0xFFFFFFFC);
8735 shrl(jdx, 2);
8736
8737 bind(L_third_loop);
8738 subl(jdx, 1);
8739 jcc(Assembler::negative, L_third_loop_exit);
8740 subl(idx, 4);
8741
8742 movq(yz_idx1, Address(y, idx, Address::times_4, 8));
8743 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
8744 movq(yz_idx2, Address(y, idx, Address::times_4, 0));
8745 rorxq(yz_idx2, yz_idx2, 32);
8746
8747 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
8748 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp
8749
8750 movq(yz_idx1, Address(z, idx, Address::times_4, 8));
8751 rorxq(yz_idx1, yz_idx1, 32);
8752 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
8753 rorxq(yz_idx2, yz_idx2, 32);
8754
8755 if (VM_Version::supports_adx()) {
8756 adcxq(tmp3, carry);
8757 adoxq(tmp3, yz_idx1);
8758
8759 adcxq(tmp4, tmp);
8760 adoxq(tmp4, yz_idx2);
8761
8762 movl(carry, 0); // does not affect flags
8763 adcxq(carry2, carry);
8764 adoxq(carry2, carry);
8765 } else {
8766 add2_with_carry(tmp4, tmp3, carry, yz_idx1);
8767 add2_with_carry(carry2, tmp4, tmp, yz_idx2);
8768 }
8769 movq(carry, carry2);
8770
8771 movl(Address(z, idx, Address::times_4, 12), tmp3);
8772 shrq(tmp3, 32);
8773 movl(Address(z, idx, Address::times_4, 8), tmp3);
8774
8775 movl(Address(z, idx, Address::times_4, 4), tmp4);
8776 shrq(tmp4, 32);
8777 movl(Address(z, idx, Address::times_4, 0), tmp4);
8778
8779 jmp(L_third_loop);
8780
8781 bind (L_third_loop_exit);
8782
8783 andl (idx, 0x3);
8784 jcc(Assembler::zero, L_post_third_loop_done);
8785
8786 Label L_check_1;
8787 subl(idx, 2);
8788 jcc(Assembler::negative, L_check_1);
8789
8790 movq(yz_idx1, Address(y, idx, Address::times_4, 0));
8791 rorxq(yz_idx1, yz_idx1, 32);
8792 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
8793 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
8794 rorxq(yz_idx2, yz_idx2, 32);
8795
8796 add2_with_carry(tmp4, tmp3, carry, yz_idx2);
8797
8798 movl(Address(z, idx, Address::times_4, 4), tmp3);
8799 shrq(tmp3, 32);
8800 movl(Address(z, idx, Address::times_4, 0), tmp3);
8801 movq(carry, tmp4);
8802
8803 bind (L_check_1);
8804 addl (idx, 0x2);
8805 andl (idx, 0x1);
8806 subl(idx, 1);
8807 jcc(Assembler::negative, L_post_third_loop_done);
8808 movl(tmp4, Address(y, idx, Address::times_4, 0));
8809 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3
8810 movl(tmp4, Address(z, idx, Address::times_4, 0));
8811
8812 add2_with_carry(carry2, tmp3, tmp4, carry);
8813
8814 movl(Address(z, idx, Address::times_4, 0), tmp3);
8815 shrq(tmp3, 32);
8816
8817 shlq(carry2, 32);
8818 orq(tmp3, carry2);
8819 movq(carry, tmp3);
8820
8821 bind(L_post_third_loop_done);
8822 }
8823
8824 /**
8825 * Code for BigInteger::multiplyToLen() instrinsic.
8826 *
8827 * rdi: x
8828 * rax: xlen
8829 * rsi: y
8830 * rcx: ylen
8831 * r8: z
8832 * r11: zlen
8833 * r12: tmp1
8834 * r13: tmp2
8835 * r14: tmp3
8836 * r15: tmp4
8837 * rbx: tmp5
8838 *
8839 */
8840 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
8841 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
8842 ShortBranchVerifier sbv(this);
8843 assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
8844
8845 push(tmp1);
8846 push(tmp2);
8847 push(tmp3);
8848 push(tmp4);
8849 push(tmp5);
8850
8851 push(xlen);
8852 push(zlen);
8853
8854 const Register idx = tmp1;
8855 const Register kdx = tmp2;
8856 const Register xstart = tmp3;
8857
8858 const Register y_idx = tmp4;
8859 const Register carry = tmp5;
8860 const Register product = xlen;
8861 const Register x_xstart = zlen; // reuse register
8862
8863 // First Loop.
8864 //
8865 // final static long LONG_MASK = 0xffffffffL;
8866 // int xstart = xlen - 1;
8867 // int ystart = ylen - 1;
8868 // long carry = 0;
8869 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
8870 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
8871 // z[kdx] = (int)product;
8872 // carry = product >>> 32;
8873 // }
8874 // z[xstart] = (int)carry;
8875 //
8876
8877 movl(idx, ylen); // idx = ylen;
8878 movl(kdx, zlen); // kdx = xlen+ylen;
8879 xorq(carry, carry); // carry = 0;
8880
8881 Label L_done;
8882
8883 movl(xstart, xlen);
8884 decrementl(xstart);
8885 jcc(Assembler::negative, L_done);
8886
8887 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
8888
8889 Label L_second_loop;
8890 testl(kdx, kdx);
8891 jcc(Assembler::zero, L_second_loop);
8892
8893 Label L_carry;
8894 subl(kdx, 1);
8895 jcc(Assembler::zero, L_carry);
8896
8897 movl(Address(z, kdx, Address::times_4, 0), carry);
8898 shrq(carry, 32);
8899 subl(kdx, 1);
8900
8901 bind(L_carry);
8902 movl(Address(z, kdx, Address::times_4, 0), carry);
8903
8904 // Second and third (nested) loops.
8905 //
8906 // for (int i = xstart-1; i >= 0; i--) { // Second loop
8907 // carry = 0;
8908 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
8909 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
8910 // (z[k] & LONG_MASK) + carry;
8911 // z[k] = (int)product;
8912 // carry = product >>> 32;
8913 // }
8914 // z[i] = (int)carry;
8915 // }
8916 //
8917 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
8918
8919 const Register jdx = tmp1;
8920
8921 bind(L_second_loop);
8922 xorl(carry, carry); // carry = 0;
8923 movl(jdx, ylen); // j = ystart+1
8924
8925 subl(xstart, 1); // i = xstart-1;
8926 jcc(Assembler::negative, L_done);
8927
8928 push (z);
8929
8930 Label L_last_x;
8931 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
8932 subl(xstart, 1); // i = xstart-1;
8933 jcc(Assembler::negative, L_last_x);
8934
8935 if (UseBMI2Instructions) {
8936 movq(rdx, Address(x, xstart, Address::times_4, 0));
8937 rorxq(rdx, rdx, 32); // convert big-endian to little-endian
8938 } else {
8939 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
8940 rorq(x_xstart, 32); // convert big-endian to little-endian
8941 }
8942
8943 Label L_third_loop_prologue;
8944 bind(L_third_loop_prologue);
8945
8946 push (x);
8947 push (xstart);
8948 push (ylen);
8949
8950
8951 if (UseBMI2Instructions) {
8952 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
8953 } else { // !UseBMI2Instructions
8954 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
8955 }
8956
8957 pop(ylen);
8958 pop(xlen);
8959 pop(x);
8960 pop(z);
8961
8962 movl(tmp3, xlen);
8963 addl(tmp3, 1);
8964 movl(Address(z, tmp3, Address::times_4, 0), carry);
8965 subl(tmp3, 1);
8966 jccb(Assembler::negative, L_done);
8967
8968 shrq(carry, 32);
8969 movl(Address(z, tmp3, Address::times_4, 0), carry);
8970 jmp(L_second_loop);
8971
8972 // Next infrequent code is moved outside loops.
8973 bind(L_last_x);
8974 if (UseBMI2Instructions) {
8975 movl(rdx, Address(x, 0));
8976 } else {
8977 movl(x_xstart, Address(x, 0));
8978 }
8979 jmp(L_third_loop_prologue);
8980
8981 bind(L_done);
8982
8983 pop(zlen);
8984 pop(xlen);
8985
8986 pop(tmp5);
8987 pop(tmp4);
8988 pop(tmp3);
8989 pop(tmp2);
8990 pop(tmp1);
8991 }
8992
8993 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
8994 Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){
8995 assert(UseSSE42Intrinsics, "SSE4.2 must be enabled.");
8996 Label VECTOR64_LOOP, VECTOR64_TAIL, VECTOR64_NOT_EQUAL, VECTOR32_TAIL;
8997 Label VECTOR32_LOOP, VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP;
8998 Label VECTOR16_TAIL, VECTOR8_TAIL, VECTOR4_TAIL;
8999 Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL;
9000 Label SAME_TILL_END, DONE;
9001 Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL;
9002
9003 //scale is in rcx in both Win64 and Unix
9004 ShortBranchVerifier sbv(this);
9005
9006 shlq(length);
9007 xorq(result, result);
9008
9009 if ((UseAVX > 2) &&
9010 VM_Version::supports_avx512vlbw()) {
9011 set_vector_masking(); // opening of the stub context for programming mask registers
9012 cmpq(length, 64);
9013 jcc(Assembler::less, VECTOR32_TAIL);
9014 movq(tmp1, length);
9015 andq(tmp1, 0x3F); // tail count
9016 andq(length, ~(0x3F)); //vector count
9017
9018 bind(VECTOR64_LOOP);
9019 // AVX512 code to compare 64 byte vectors.
9020 evmovdqub(rymm0, Address(obja, result), Assembler::AVX_512bit);
9021 evpcmpeqb(k7, rymm0, Address(objb, result), Assembler::AVX_512bit);
9022 kortestql(k7, k7);
9023 jcc(Assembler::aboveEqual, VECTOR64_NOT_EQUAL); // mismatch
9024 addq(result, 64);
9025 subq(length, 64);
9026 jccb(Assembler::notZero, VECTOR64_LOOP);
9027
9028 //bind(VECTOR64_TAIL);
9029 testq(tmp1, tmp1);
9030 jcc(Assembler::zero, SAME_TILL_END);
9031
9032 bind(VECTOR64_TAIL);
9033 // AVX512 code to compare upto 63 byte vectors.
9034 // Save k1
9035 kmovql(k3, k1);
9036 mov64(tmp2, 0xFFFFFFFFFFFFFFFF);
9037 shlxq(tmp2, tmp2, tmp1);
9038 notq(tmp2);
9039 kmovql(k1, tmp2);
9040
9041 evmovdqub(rymm0, k1, Address(obja, result), Assembler::AVX_512bit);
9042 evpcmpeqb(k7, k1, rymm0, Address(objb, result), Assembler::AVX_512bit);
9043
9044 ktestql(k7, k1);
9045 // Restore k1
9046 kmovql(k1, k3);
9047 jcc(Assembler::below, SAME_TILL_END); // not mismatch
9048
9049 bind(VECTOR64_NOT_EQUAL);
9050 kmovql(tmp1, k7);
9051 notq(tmp1);
9052 tzcntq(tmp1, tmp1);
9053 addq(result, tmp1);
9054 shrq(result);
9055 jmp(DONE);
9056 bind(VECTOR32_TAIL);
9057 clear_vector_masking(); // closing of the stub context for programming mask registers
9058 }
9059
9060 cmpq(length, 8);
9061 jcc(Assembler::equal, VECTOR8_LOOP);
9062 jcc(Assembler::less, VECTOR4_TAIL);
9063
9064 if (UseAVX >= 2) {
9065
9066 cmpq(length, 16);
9067 jcc(Assembler::equal, VECTOR16_LOOP);
9068 jcc(Assembler::less, VECTOR8_LOOP);
9069
9070 cmpq(length, 32);
9071 jccb(Assembler::less, VECTOR16_TAIL);
9072
9073 subq(length, 32);
9074 bind(VECTOR32_LOOP);
9075 vmovdqu(rymm0, Address(obja, result));
9076 vmovdqu(rymm1, Address(objb, result));
9077 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit);
9078 vptest(rymm2, rymm2);
9079 jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found
9080 addq(result, 32);
9081 subq(length, 32);
9082 jcc(Assembler::greaterEqual, VECTOR32_LOOP);
9083 addq(length, 32);
9084 jcc(Assembler::equal, SAME_TILL_END);
9085 //falling through if less than 32 bytes left //close the branch here.
9086
9087 bind(VECTOR16_TAIL);
9088 cmpq(length, 16);
9089 jccb(Assembler::less, VECTOR8_TAIL);
9090 bind(VECTOR16_LOOP);
9091 movdqu(rymm0, Address(obja, result));
9092 movdqu(rymm1, Address(objb, result));
9093 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit);
9094 ptest(rymm2, rymm2);
9095 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
9096 addq(result, 16);
9097 subq(length, 16);
9098 jcc(Assembler::equal, SAME_TILL_END);
9099 //falling through if less than 16 bytes left
9100 } else {//regular intrinsics
9101
9102 cmpq(length, 16);
9103 jccb(Assembler::less, VECTOR8_TAIL);
9104
9105 subq(length, 16);
9106 bind(VECTOR16_LOOP);
9107 movdqu(rymm0, Address(obja, result));
9108 movdqu(rymm1, Address(objb, result));
9109 pxor(rymm0, rymm1);
9110 ptest(rymm0, rymm0);
9111 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
9112 addq(result, 16);
9113 subq(length, 16);
9114 jccb(Assembler::greaterEqual, VECTOR16_LOOP);
9115 addq(length, 16);
9116 jcc(Assembler::equal, SAME_TILL_END);
9117 //falling through if less than 16 bytes left
9118 }
9119
9120 bind(VECTOR8_TAIL);
9121 cmpq(length, 8);
9122 jccb(Assembler::less, VECTOR4_TAIL);
9123 bind(VECTOR8_LOOP);
9124 movq(tmp1, Address(obja, result));
9125 movq(tmp2, Address(objb, result));
9126 xorq(tmp1, tmp2);
9127 testq(tmp1, tmp1);
9128 jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found
9129 addq(result, 8);
9130 subq(length, 8);
9131 jcc(Assembler::equal, SAME_TILL_END);
9132 //falling through if less than 8 bytes left
9133
9134 bind(VECTOR4_TAIL);
9135 cmpq(length, 4);
9136 jccb(Assembler::less, BYTES_TAIL);
9137 bind(VECTOR4_LOOP);
9138 movl(tmp1, Address(obja, result));
9139 xorl(tmp1, Address(objb, result));
9140 testl(tmp1, tmp1);
9141 jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found
9142 addq(result, 4);
9143 subq(length, 4);
9144 jcc(Assembler::equal, SAME_TILL_END);
9145 //falling through if less than 4 bytes left
9146
9147 bind(BYTES_TAIL);
9148 bind(BYTES_LOOP);
9149 load_unsigned_byte(tmp1, Address(obja, result));
9150 load_unsigned_byte(tmp2, Address(objb, result));
9151 xorl(tmp1, tmp2);
9152 testl(tmp1, tmp1);
9153 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
9154 decq(length);
9155 jcc(Assembler::zero, SAME_TILL_END);
9156 incq(result);
9157 load_unsigned_byte(tmp1, Address(obja, result));
9158 load_unsigned_byte(tmp2, Address(objb, result));
9159 xorl(tmp1, tmp2);
9160 testl(tmp1, tmp1);
9161 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
9162 decq(length);
9163 jcc(Assembler::zero, SAME_TILL_END);
9164 incq(result);
9165 load_unsigned_byte(tmp1, Address(obja, result));
9166 load_unsigned_byte(tmp2, Address(objb, result));
9167 xorl(tmp1, tmp2);
9168 testl(tmp1, tmp1);
9169 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
9170 jmp(SAME_TILL_END);
9171
9172 if (UseAVX >= 2) {
9173 bind(VECTOR32_NOT_EQUAL);
9174 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit);
9175 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit);
9176 vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit);
9177 vpmovmskb(tmp1, rymm0);
9178 bsfq(tmp1, tmp1);
9179 addq(result, tmp1);
9180 shrq(result);
9181 jmp(DONE);
9182 }
9183
9184 bind(VECTOR16_NOT_EQUAL);
9185 if (UseAVX >= 2) {
9186 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit);
9187 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit);
9188 pxor(rymm0, rymm2);
9189 } else {
9190 pcmpeqb(rymm2, rymm2);
9191 pxor(rymm0, rymm1);
9192 pcmpeqb(rymm0, rymm1);
9193 pxor(rymm0, rymm2);
9194 }
9195 pmovmskb(tmp1, rymm0);
9196 bsfq(tmp1, tmp1);
9197 addq(result, tmp1);
9198 shrq(result);
9199 jmpb(DONE);
9200
9201 bind(VECTOR8_NOT_EQUAL);
9202 bind(VECTOR4_NOT_EQUAL);
9203 bsfq(tmp1, tmp1);
9204 shrq(tmp1, 3);
9205 addq(result, tmp1);
9206 bind(BYTES_NOT_EQUAL);
9207 shrq(result);
9208 jmpb(DONE);
9209
9210 bind(SAME_TILL_END);
9211 mov64(result, -1);
9212
9213 bind(DONE);
9214 }
9215
9216 //Helper functions for square_to_len()
9217
9218 /**
9219 * Store the squares of x[], right shifted one bit (divided by 2) into z[]
9220 * Preserves x and z and modifies rest of the registers.
9221 */
9222 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
9223 // Perform square and right shift by 1
9224 // Handle odd xlen case first, then for even xlen do the following
9225 // jlong carry = 0;
9226 // for (int j=0, i=0; j < xlen; j+=2, i+=4) {
9227 // huge_128 product = x[j:j+1] * x[j:j+1];
9228 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65);
9229 // z[i+2:i+3] = (jlong)(product >>> 1);
9230 // carry = (jlong)product;
9231 // }
9232
9233 xorq(tmp5, tmp5); // carry
9234 xorq(rdxReg, rdxReg);
9235 xorl(tmp1, tmp1); // index for x
9236 xorl(tmp4, tmp4); // index for z
9237
9238 Label L_first_loop, L_first_loop_exit;
9239
9240 testl(xlen, 1);
9241 jccb(Assembler::zero, L_first_loop); //jump if xlen is even
9242
9243 // Square and right shift by 1 the odd element using 32 bit multiply
9244 movl(raxReg, Address(x, tmp1, Address::times_4, 0));
9245 imulq(raxReg, raxReg);
9246 shrq(raxReg, 1);
9247 adcq(tmp5, 0);
9248 movq(Address(z, tmp4, Address::times_4, 0), raxReg);
9249 incrementl(tmp1);
9250 addl(tmp4, 2);
9251
9252 // Square and right shift by 1 the rest using 64 bit multiply
9253 bind(L_first_loop);
9254 cmpptr(tmp1, xlen);
9255 jccb(Assembler::equal, L_first_loop_exit);
9256
9257 // Square
9258 movq(raxReg, Address(x, tmp1, Address::times_4, 0));
9259 rorq(raxReg, 32); // convert big-endian to little-endian
9260 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax
9261
9262 // Right shift by 1 and save carry
9263 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1
9264 rcrq(rdxReg, 1);
9265 rcrq(raxReg, 1);
9266 adcq(tmp5, 0);
9267
9268 // Store result in z
9269 movq(Address(z, tmp4, Address::times_4, 0), rdxReg);
9270 movq(Address(z, tmp4, Address::times_4, 8), raxReg);
9271
9272 // Update indices for x and z
9273 addl(tmp1, 2);
9274 addl(tmp4, 4);
9275 jmp(L_first_loop);
9276
9277 bind(L_first_loop_exit);
9278 }
9279
9280
9281 /**
9282 * Perform the following multiply add operation using BMI2 instructions
9283 * carry:sum = sum + op1*op2 + carry
9284 * op2 should be in rdx
9285 * op2 is preserved, all other registers are modified
9286 */
9287 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) {
9288 // assert op2 is rdx
9289 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1
9290 addq(sum, carry);
9291 adcq(tmp2, 0);
9292 addq(sum, op1);
9293 adcq(tmp2, 0);
9294 movq(carry, tmp2);
9295 }
9296
9297 /**
9298 * Perform the following multiply add operation:
9299 * carry:sum = sum + op1*op2 + carry
9300 * Preserves op1, op2 and modifies rest of registers
9301 */
9302 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) {
9303 // rdx:rax = op1 * op2
9304 movq(raxReg, op2);
9305 mulq(op1);
9306
9307 // rdx:rax = sum + carry + rdx:rax
9308 addq(sum, carry);
9309 adcq(rdxReg, 0);
9310 addq(sum, raxReg);
9311 adcq(rdxReg, 0);
9312
9313 // carry:sum = rdx:sum
9314 movq(carry, rdxReg);
9315 }
9316
9317 /**
9318 * Add 64 bit long carry into z[] with carry propogation.
9319 * Preserves z and carry register values and modifies rest of registers.
9320 *
9321 */
9322 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) {
9323 Label L_fourth_loop, L_fourth_loop_exit;
9324
9325 movl(tmp1, 1);
9326 subl(zlen, 2);
9327 addq(Address(z, zlen, Address::times_4, 0), carry);
9328
9329 bind(L_fourth_loop);
9330 jccb(Assembler::carryClear, L_fourth_loop_exit);
9331 subl(zlen, 2);
9332 jccb(Assembler::negative, L_fourth_loop_exit);
9333 addq(Address(z, zlen, Address::times_4, 0), tmp1);
9334 jmp(L_fourth_loop);
9335 bind(L_fourth_loop_exit);
9336 }
9337
9338 /**
9339 * Shift z[] left by 1 bit.
9340 * Preserves x, len, z and zlen registers and modifies rest of the registers.
9341 *
9342 */
9343 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
9344
9345 Label L_fifth_loop, L_fifth_loop_exit;
9346
9347 // Fifth loop
9348 // Perform primitiveLeftShift(z, zlen, 1)
9349
9350 const Register prev_carry = tmp1;
9351 const Register new_carry = tmp4;
9352 const Register value = tmp2;
9353 const Register zidx = tmp3;
9354
9355 // int zidx, carry;
9356 // long value;
9357 // carry = 0;
9358 // for (zidx = zlen-2; zidx >=0; zidx -= 2) {
9359 // (carry:value) = (z[i] << 1) | carry ;
9360 // z[i] = value;
9361 // }
9362
9363 movl(zidx, zlen);
9364 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register
9365
9366 bind(L_fifth_loop);
9367 decl(zidx); // Use decl to preserve carry flag
9368 decl(zidx);
9369 jccb(Assembler::negative, L_fifth_loop_exit);
9370
9371 if (UseBMI2Instructions) {
9372 movq(value, Address(z, zidx, Address::times_4, 0));
9373 rclq(value, 1);
9374 rorxq(value, value, 32);
9375 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
9376 }
9377 else {
9378 // clear new_carry
9379 xorl(new_carry, new_carry);
9380
9381 // Shift z[i] by 1, or in previous carry and save new carry
9382 movq(value, Address(z, zidx, Address::times_4, 0));
9383 shlq(value, 1);
9384 adcl(new_carry, 0);
9385
9386 orq(value, prev_carry);
9387 rorq(value, 0x20);
9388 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
9389
9390 // Set previous carry = new carry
9391 movl(prev_carry, new_carry);
9392 }
9393 jmp(L_fifth_loop);
9394
9395 bind(L_fifth_loop_exit);
9396 }
9397
9398
9399 /**
9400 * Code for BigInteger::squareToLen() intrinsic
9401 *
9402 * rdi: x
9403 * rsi: len
9404 * r8: z
9405 * rcx: zlen
9406 * r12: tmp1
9407 * r13: tmp2
9408 * r14: tmp3
9409 * r15: tmp4
9410 * rbx: tmp5
9411 *
9412 */
9413 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
9414
9415 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, fifth_loop, fifth_loop_exit, L_last_x, L_multiply;
9416 push(tmp1);
9417 push(tmp2);
9418 push(tmp3);
9419 push(tmp4);
9420 push(tmp5);
9421
9422 // First loop
9423 // Store the squares, right shifted one bit (i.e., divided by 2).
9424 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg);
9425
9426 // Add in off-diagonal sums.
9427 //
9428 // Second, third (nested) and fourth loops.
9429 // zlen +=2;
9430 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) {
9431 // carry = 0;
9432 // long op2 = x[xidx:xidx+1];
9433 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) {
9434 // k -= 2;
9435 // long op1 = x[j:j+1];
9436 // long sum = z[k:k+1];
9437 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs);
9438 // z[k:k+1] = sum;
9439 // }
9440 // add_one_64(z, k, carry, tmp_regs);
9441 // }
9442
9443 const Register carry = tmp5;
9444 const Register sum = tmp3;
9445 const Register op1 = tmp4;
9446 Register op2 = tmp2;
9447
9448 push(zlen);
9449 push(len);
9450 addl(zlen,2);
9451 bind(L_second_loop);
9452 xorq(carry, carry);
9453 subl(zlen, 4);
9454 subl(len, 2);
9455 push(zlen);
9456 push(len);
9457 cmpl(len, 0);
9458 jccb(Assembler::lessEqual, L_second_loop_exit);
9459
9460 // Multiply an array by one 64 bit long.
9461 if (UseBMI2Instructions) {
9462 op2 = rdxReg;
9463 movq(op2, Address(x, len, Address::times_4, 0));
9464 rorxq(op2, op2, 32);
9465 }
9466 else {
9467 movq(op2, Address(x, len, Address::times_4, 0));
9468 rorq(op2, 32);
9469 }
9470
9471 bind(L_third_loop);
9472 decrementl(len);
9473 jccb(Assembler::negative, L_third_loop_exit);
9474 decrementl(len);
9475 jccb(Assembler::negative, L_last_x);
9476
9477 movq(op1, Address(x, len, Address::times_4, 0));
9478 rorq(op1, 32);
9479
9480 bind(L_multiply);
9481 subl(zlen, 2);
9482 movq(sum, Address(z, zlen, Address::times_4, 0));
9483
9484 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry.
9485 if (UseBMI2Instructions) {
9486 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2);
9487 }
9488 else {
9489 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
9490 }
9491
9492 movq(Address(z, zlen, Address::times_4, 0), sum);
9493
9494 jmp(L_third_loop);
9495 bind(L_third_loop_exit);
9496
9497 // Fourth loop
9498 // Add 64 bit long carry into z with carry propogation.
9499 // Uses offsetted zlen.
9500 add_one_64(z, zlen, carry, tmp1);
9501
9502 pop(len);
9503 pop(zlen);
9504 jmp(L_second_loop);
9505
9506 // Next infrequent code is moved outside loops.
9507 bind(L_last_x);
9508 movl(op1, Address(x, 0));
9509 jmp(L_multiply);
9510
9511 bind(L_second_loop_exit);
9512 pop(len);
9513 pop(zlen);
9514 pop(len);
9515 pop(zlen);
9516
9517 // Fifth loop
9518 // Shift z left 1 bit.
9519 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4);
9520
9521 // z[zlen-1] |= x[len-1] & 1;
9522 movl(tmp3, Address(x, len, Address::times_4, -4));
9523 andl(tmp3, 1);
9524 orl(Address(z, zlen, Address::times_4, -4), tmp3);
9525
9526 pop(tmp5);
9527 pop(tmp4);
9528 pop(tmp3);
9529 pop(tmp2);
9530 pop(tmp1);
9531 }
9532
9533 /**
9534 * Helper function for mul_add()
9535 * Multiply the in[] by int k and add to out[] starting at offset offs using
9536 * 128 bit by 32 bit multiply and return the carry in tmp5.
9537 * Only quad int aligned length of in[] is operated on in this function.
9538 * k is in rdxReg for BMI2Instructions, for others it is in tmp2.
9539 * This function preserves out, in and k registers.
9540 * len and offset point to the appropriate index in "in" & "out" correspondingly
9541 * tmp5 has the carry.
9542 * other registers are temporary and are modified.
9543 *
9544 */
9545 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in,
9546 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3,
9547 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
9548
9549 Label L_first_loop, L_first_loop_exit;
9550
9551 movl(tmp1, len);
9552 shrl(tmp1, 2);
9553
9554 bind(L_first_loop);
9555 subl(tmp1, 1);
9556 jccb(Assembler::negative, L_first_loop_exit);
9557
9558 subl(len, 4);
9559 subl(offset, 4);
9560
9561 Register op2 = tmp2;
9562 const Register sum = tmp3;
9563 const Register op1 = tmp4;
9564 const Register carry = tmp5;
9565
9566 if (UseBMI2Instructions) {
9567 op2 = rdxReg;
9568 }
9569
9570 movq(op1, Address(in, len, Address::times_4, 8));
9571 rorq(op1, 32);
9572 movq(sum, Address(out, offset, Address::times_4, 8));
9573 rorq(sum, 32);
9574 if (UseBMI2Instructions) {
9575 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
9576 }
9577 else {
9578 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
9579 }
9580 // Store back in big endian from little endian
9581 rorq(sum, 0x20);
9582 movq(Address(out, offset, Address::times_4, 8), sum);
9583
9584 movq(op1, Address(in, len, Address::times_4, 0));
9585 rorq(op1, 32);
9586 movq(sum, Address(out, offset, Address::times_4, 0));
9587 rorq(sum, 32);
9588 if (UseBMI2Instructions) {
9589 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
9590 }
9591 else {
9592 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
9593 }
9594 // Store back in big endian from little endian
9595 rorq(sum, 0x20);
9596 movq(Address(out, offset, Address::times_4, 0), sum);
9597
9598 jmp(L_first_loop);
9599 bind(L_first_loop_exit);
9600 }
9601
9602 /**
9603 * Code for BigInteger::mulAdd() intrinsic
9604 *
9605 * rdi: out
9606 * rsi: in
9607 * r11: offs (out.length - offset)
9608 * rcx: len
9609 * r8: k
9610 * r12: tmp1
9611 * r13: tmp2
9612 * r14: tmp3
9613 * r15: tmp4
9614 * rbx: tmp5
9615 * Multiply the in[] by word k and add to out[], return the carry in rax
9616 */
9617 void MacroAssembler::mul_add(Register out, Register in, Register offs,
9618 Register len, Register k, Register tmp1, Register tmp2, Register tmp3,
9619 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
9620
9621 Label L_carry, L_last_in, L_done;
9622
9623 // carry = 0;
9624 // for (int j=len-1; j >= 0; j--) {
9625 // long product = (in[j] & LONG_MASK) * kLong +
9626 // (out[offs] & LONG_MASK) + carry;
9627 // out[offs--] = (int)product;
9628 // carry = product >>> 32;
9629 // }
9630 //
9631 push(tmp1);
9632 push(tmp2);
9633 push(tmp3);
9634 push(tmp4);
9635 push(tmp5);
9636
9637 Register op2 = tmp2;
9638 const Register sum = tmp3;
9639 const Register op1 = tmp4;
9640 const Register carry = tmp5;
9641
9642 if (UseBMI2Instructions) {
9643 op2 = rdxReg;
9644 movl(op2, k);
9645 }
9646 else {
9647 movl(op2, k);
9648 }
9649
9650 xorq(carry, carry);
9651
9652 //First loop
9653
9654 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply
9655 //The carry is in tmp5
9656 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg);
9657
9658 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any
9659 decrementl(len);
9660 jccb(Assembler::negative, L_carry);
9661 decrementl(len);
9662 jccb(Assembler::negative, L_last_in);
9663
9664 movq(op1, Address(in, len, Address::times_4, 0));
9665 rorq(op1, 32);
9666
9667 subl(offs, 2);
9668 movq(sum, Address(out, offs, Address::times_4, 0));
9669 rorq(sum, 32);
9670
9671 if (UseBMI2Instructions) {
9672 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
9673 }
9674 else {
9675 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
9676 }
9677
9678 // Store back in big endian from little endian
9679 rorq(sum, 0x20);
9680 movq(Address(out, offs, Address::times_4, 0), sum);
9681
9682 testl(len, len);
9683 jccb(Assembler::zero, L_carry);
9684
9685 //Multiply the last in[] entry, if any
9686 bind(L_last_in);
9687 movl(op1, Address(in, 0));
9688 movl(sum, Address(out, offs, Address::times_4, -4));
9689
9690 movl(raxReg, k);
9691 mull(op1); //tmp4 * eax -> edx:eax
9692 addl(sum, carry);
9693 adcl(rdxReg, 0);
9694 addl(sum, raxReg);
9695 adcl(rdxReg, 0);
9696 movl(carry, rdxReg);
9697
9698 movl(Address(out, offs, Address::times_4, -4), sum);
9699
9700 bind(L_carry);
9701 //return tmp5/carry as carry in rax
9702 movl(rax, carry);
9703
9704 bind(L_done);
9705 pop(tmp5);
9706 pop(tmp4);
9707 pop(tmp3);
9708 pop(tmp2);
9709 pop(tmp1);
9710 }
9711 #endif
9712
9713 /**
9714 * Emits code to update CRC-32 with a byte value according to constants in table
9715 *
9716 * @param [in,out]crc Register containing the crc.
9717 * @param [in]val Register containing the byte to fold into the CRC.
9718 * @param [in]table Register containing the table of crc constants.
9719 *
9720 * uint32_t crc;
9721 * val = crc_table[(val ^ crc) & 0xFF];
9722 * crc = val ^ (crc >> 8);
9723 *
9724 */
9725 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
9726 xorl(val, crc);
9727 andl(val, 0xFF);
9728 shrl(crc, 8); // unsigned shift
9729 xorl(crc, Address(table, val, Address::times_4, 0));
9730 }
9731
9732 /**
9733 * Fold four 128-bit data chunks
9734 */
9735 void MacroAssembler::fold_128bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
9736 evpclmulhdq(xtmp, xK, xcrc, Assembler::AVX_512bit); // [123:64]
9737 evpclmulldq(xcrc, xK, xcrc, Assembler::AVX_512bit); // [63:0]
9738 evpxorq(xcrc, xcrc, Address(buf, offset), Assembler::AVX_512bit /* vector_len */);
9739 evpxorq(xcrc, xcrc, xtmp, Assembler::AVX_512bit /* vector_len */);
9740 }
9741
9742 /**
9743 * Fold 128-bit data chunk
9744 */
9745 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
9746 if (UseAVX > 0) {
9747 vpclmulhdq(xtmp, xK, xcrc); // [123:64]
9748 vpclmulldq(xcrc, xK, xcrc); // [63:0]
9749 vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */);
9750 pxor(xcrc, xtmp);
9751 } else {
9752 movdqa(xtmp, xcrc);
9753 pclmulhdq(xtmp, xK); // [123:64]
9754 pclmulldq(xcrc, xK); // [63:0]
9755 pxor(xcrc, xtmp);
9756 movdqu(xtmp, Address(buf, offset));
9757 pxor(xcrc, xtmp);
9758 }
9759 }
9760
9761 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
9762 if (UseAVX > 0) {
9763 vpclmulhdq(xtmp, xK, xcrc);
9764 vpclmulldq(xcrc, xK, xcrc);
9765 pxor(xcrc, xbuf);
9766 pxor(xcrc, xtmp);
9767 } else {
9768 movdqa(xtmp, xcrc);
9769 pclmulhdq(xtmp, xK);
9770 pclmulldq(xcrc, xK);
9771 pxor(xcrc, xbuf);
9772 pxor(xcrc, xtmp);
9773 }
9774 }
9775
9776 /**
9777 * 8-bit folds to compute 32-bit CRC
9778 *
9779 * uint64_t xcrc;
9780 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
9781 */
9782 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
9783 movdl(tmp, xcrc);
9784 andl(tmp, 0xFF);
9785 movdl(xtmp, Address(table, tmp, Address::times_4, 0));
9786 psrldq(xcrc, 1); // unsigned shift one byte
9787 pxor(xcrc, xtmp);
9788 }
9789
9790 /**
9791 * uint32_t crc;
9792 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
9793 */
9794 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
9795 movl(tmp, crc);
9796 andl(tmp, 0xFF);
9797 shrl(crc, 8);
9798 xorl(crc, Address(table, tmp, Address::times_4, 0));
9799 }
9800
9801 /**
9802 * @param crc register containing existing CRC (32-bit)
9803 * @param buf register pointing to input byte buffer (byte*)
9804 * @param len register containing number of bytes
9805 * @param table register that will contain address of CRC table
9806 * @param tmp scratch register
9807 */
9808 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
9809 assert_different_registers(crc, buf, len, table, tmp, rax);
9810
9811 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
9812 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
9813
9814 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
9815 // context for the registers used, where all instructions below are using 128-bit mode
9816 // On EVEX without VL and BW, these instructions will all be AVX.
9817 if (VM_Version::supports_avx512vlbw()) {
9818 movl(tmp, 0xffff);
9819 kmovwl(k1, tmp);
9820 }
9821
9822 lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
9823 notl(crc); // ~crc
9824 cmpl(len, 16);
9825 jcc(Assembler::less, L_tail);
9826
9827 // Align buffer to 16 bytes
9828 movl(tmp, buf);
9829 andl(tmp, 0xF);
9830 jccb(Assembler::zero, L_aligned);
9831 subl(tmp, 16);
9832 addl(len, tmp);
9833
9834 align(4);
9835 BIND(L_align_loop);
9836 movsbl(rax, Address(buf, 0)); // load byte with sign extension
9837 update_byte_crc32(crc, rax, table);
9838 increment(buf);
9839 incrementl(tmp);
9840 jccb(Assembler::less, L_align_loop);
9841
9842 BIND(L_aligned);
9843 movl(tmp, len); // save
9844 shrl(len, 4);
9845 jcc(Assembler::zero, L_tail_restore);
9846
9847 // Fold total 512 bits of polynomial on each iteration
9848 if (VM_Version::supports_vpclmulqdq()) {
9849 Label Parallel_loop, L_No_Parallel;
9850
9851 cmpl(len, 8);
9852 jccb(Assembler::less, L_No_Parallel);
9853
9854 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32));
9855 evmovdquq(xmm1, Address(buf, 0), Assembler::AVX_512bit);
9856 movdl(xmm5, crc);
9857 evpxorq(xmm1, xmm1, xmm5, Assembler::AVX_512bit);
9858 addptr(buf, 64);
9859 subl(len, 7);
9860 evshufi64x2(xmm0, xmm0, xmm0, 0x00, Assembler::AVX_512bit); //propagate the mask from 128 bits to 512 bits
9861
9862 BIND(Parallel_loop);
9863 fold_128bit_crc32_avx512(xmm1, xmm0, xmm5, buf, 0);
9864 addptr(buf, 64);
9865 subl(len, 4);
9866 jcc(Assembler::greater, Parallel_loop);
9867
9868 vextracti64x2(xmm2, xmm1, 0x01);
9869 vextracti64x2(xmm3, xmm1, 0x02);
9870 vextracti64x2(xmm4, xmm1, 0x03);
9871 jmp(L_fold_512b);
9872
9873 BIND(L_No_Parallel);
9874 }
9875 // Fold crc into first bytes of vector
9876 movdqa(xmm1, Address(buf, 0));
9877 movdl(rax, xmm1);
9878 xorl(crc, rax);
9879 if (VM_Version::supports_sse4_1()) {
9880 pinsrd(xmm1, crc, 0);
9881 } else {
9882 pinsrw(xmm1, crc, 0);
9883 shrl(crc, 16);
9884 pinsrw(xmm1, crc, 1);
9885 }
9886 addptr(buf, 16);
9887 subl(len, 4); // len > 0
9888 jcc(Assembler::less, L_fold_tail);
9889
9890 movdqa(xmm2, Address(buf, 0));
9891 movdqa(xmm3, Address(buf, 16));
9892 movdqa(xmm4, Address(buf, 32));
9893 addptr(buf, 48);
9894 subl(len, 3);
9895 jcc(Assembler::lessEqual, L_fold_512b);
9896
9897 // Fold total 512 bits of polynomial on each iteration,
9898 // 128 bits per each of 4 parallel streams.
9899 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32));
9900
9901 align(32);
9902 BIND(L_fold_512b_loop);
9903 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
9904 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
9905 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
9906 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
9907 addptr(buf, 64);
9908 subl(len, 4);
9909 jcc(Assembler::greater, L_fold_512b_loop);
9910
9911 // Fold 512 bits to 128 bits.
9912 BIND(L_fold_512b);
9913 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
9914 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
9915 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
9916 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
9917
9918 // Fold the rest of 128 bits data chunks
9919 BIND(L_fold_tail);
9920 addl(len, 3);
9921 jccb(Assembler::lessEqual, L_fold_128b);
9922 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
9923
9924 BIND(L_fold_tail_loop);
9925 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
9926 addptr(buf, 16);
9927 decrementl(len);
9928 jccb(Assembler::greater, L_fold_tail_loop);
9929
9930 // Fold 128 bits in xmm1 down into 32 bits in crc register.
9931 BIND(L_fold_128b);
9932 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()));
9933 if (UseAVX > 0) {
9934 vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
9935 vpand(xmm3, xmm0, xmm2, 0 /* vector_len */);
9936 vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
9937 } else {
9938 movdqa(xmm2, xmm0);
9939 pclmulqdq(xmm2, xmm1, 0x1);
9940 movdqa(xmm3, xmm0);
9941 pand(xmm3, xmm2);
9942 pclmulqdq(xmm0, xmm3, 0x1);
9943 }
9944 psrldq(xmm1, 8);
9945 psrldq(xmm2, 4);
9946 pxor(xmm0, xmm1);
9947 pxor(xmm0, xmm2);
9948
9949 // 8 8-bit folds to compute 32-bit CRC.
9950 for (int j = 0; j < 4; j++) {
9951 fold_8bit_crc32(xmm0, table, xmm1, rax);
9952 }
9953 movdl(crc, xmm0); // mov 32 bits to general register
9954 for (int j = 0; j < 4; j++) {
9955 fold_8bit_crc32(crc, table, rax);
9956 }
9957
9958 BIND(L_tail_restore);
9959 movl(len, tmp); // restore
9960 BIND(L_tail);
9961 andl(len, 0xf);
9962 jccb(Assembler::zero, L_exit);
9963
9964 // Fold the rest of bytes
9965 align(4);
9966 BIND(L_tail_loop);
9967 movsbl(rax, Address(buf, 0)); // load byte with sign extension
9968 update_byte_crc32(crc, rax, table);
9969 increment(buf);
9970 decrementl(len);
9971 jccb(Assembler::greater, L_tail_loop);
9972
9973 BIND(L_exit);
9974 notl(crc); // ~c
9975 }
9976
9977 #ifdef _LP64
9978 // S. Gueron / Information Processing Letters 112 (2012) 184
9979 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table.
9980 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0].
9981 // Output: the 64-bit carry-less product of B * CONST
9982 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n,
9983 Register tmp1, Register tmp2, Register tmp3) {
9984 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
9985 if (n > 0) {
9986 addq(tmp3, n * 256 * 8);
9987 }
9988 // Q1 = TABLEExt[n][B & 0xFF];
9989 movl(tmp1, in);
9990 andl(tmp1, 0x000000FF);
9991 shll(tmp1, 3);
9992 addq(tmp1, tmp3);
9993 movq(tmp1, Address(tmp1, 0));
9994
9995 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
9996 movl(tmp2, in);
9997 shrl(tmp2, 8);
9998 andl(tmp2, 0x000000FF);
9999 shll(tmp2, 3);
10000 addq(tmp2, tmp3);
10001 movq(tmp2, Address(tmp2, 0));
10002
10003 shlq(tmp2, 8);
10004 xorq(tmp1, tmp2);
10005
10006 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
10007 movl(tmp2, in);
10008 shrl(tmp2, 16);
10009 andl(tmp2, 0x000000FF);
10010 shll(tmp2, 3);
10011 addq(tmp2, tmp3);
10012 movq(tmp2, Address(tmp2, 0));
10013
10014 shlq(tmp2, 16);
10015 xorq(tmp1, tmp2);
10016
10017 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
10018 shrl(in, 24);
10019 andl(in, 0x000000FF);
10020 shll(in, 3);
10021 addq(in, tmp3);
10022 movq(in, Address(in, 0));
10023
10024 shlq(in, 24);
10025 xorq(in, tmp1);
10026 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
10027 }
10028
10029 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
10030 Register in_out,
10031 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
10032 XMMRegister w_xtmp2,
10033 Register tmp1,
10034 Register n_tmp2, Register n_tmp3) {
10035 if (is_pclmulqdq_supported) {
10036 movdl(w_xtmp1, in_out); // modified blindly
10037
10038 movl(tmp1, const_or_pre_comp_const_index);
10039 movdl(w_xtmp2, tmp1);
10040 pclmulqdq(w_xtmp1, w_xtmp2, 0);
10041
10042 movdq(in_out, w_xtmp1);
10043 } else {
10044 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3);
10045 }
10046 }
10047
10048 // Recombination Alternative 2: No bit-reflections
10049 // T1 = (CRC_A * U1) << 1
10050 // T2 = (CRC_B * U2) << 1
10051 // C1 = T1 >> 32
10052 // C2 = T2 >> 32
10053 // T1 = T1 & 0xFFFFFFFF
10054 // T2 = T2 & 0xFFFFFFFF
10055 // T1 = CRC32(0, T1)
10056 // T2 = CRC32(0, T2)
10057 // C1 = C1 ^ T1
10058 // C2 = C2 ^ T2
10059 // CRC = C1 ^ C2 ^ CRC_C
10060 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
10061 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10062 Register tmp1, Register tmp2,
10063 Register n_tmp3) {
10064 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
10065 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
10066 shlq(in_out, 1);
10067 movl(tmp1, in_out);
10068 shrq(in_out, 32);
10069 xorl(tmp2, tmp2);
10070 crc32(tmp2, tmp1, 4);
10071 xorl(in_out, tmp2); // we don't care about upper 32 bit contents here
10072 shlq(in1, 1);
10073 movl(tmp1, in1);
10074 shrq(in1, 32);
10075 xorl(tmp2, tmp2);
10076 crc32(tmp2, tmp1, 4);
10077 xorl(in1, tmp2);
10078 xorl(in_out, in1);
10079 xorl(in_out, in2);
10080 }
10081
10082 // Set N to predefined value
10083 // Subtract from a lenght of a buffer
10084 // execute in a loop:
10085 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0
10086 // for i = 1 to N do
10087 // CRC_A = CRC32(CRC_A, A[i])
10088 // CRC_B = CRC32(CRC_B, B[i])
10089 // CRC_C = CRC32(CRC_C, C[i])
10090 // end for
10091 // Recombine
10092 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
10093 Register in_out1, Register in_out2, Register in_out3,
10094 Register tmp1, Register tmp2, Register tmp3,
10095 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10096 Register tmp4, Register tmp5,
10097 Register n_tmp6) {
10098 Label L_processPartitions;
10099 Label L_processPartition;
10100 Label L_exit;
10101
10102 bind(L_processPartitions);
10103 cmpl(in_out1, 3 * size);
10104 jcc(Assembler::less, L_exit);
10105 xorl(tmp1, tmp1);
10106 xorl(tmp2, tmp2);
10107 movq(tmp3, in_out2);
10108 addq(tmp3, size);
10109
10110 bind(L_processPartition);
10111 crc32(in_out3, Address(in_out2, 0), 8);
10112 crc32(tmp1, Address(in_out2, size), 8);
10113 crc32(tmp2, Address(in_out2, size * 2), 8);
10114 addq(in_out2, 8);
10115 cmpq(in_out2, tmp3);
10116 jcc(Assembler::less, L_processPartition);
10117 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
10118 w_xtmp1, w_xtmp2, w_xtmp3,
10119 tmp4, tmp5,
10120 n_tmp6);
10121 addq(in_out2, 2 * size);
10122 subl(in_out1, 3 * size);
10123 jmp(L_processPartitions);
10124
10125 bind(L_exit);
10126 }
10127 #else
10128 void MacroAssembler::crc32c_ipl_alg4(Register in_out, uint32_t n,
10129 Register tmp1, Register tmp2, Register tmp3,
10130 XMMRegister xtmp1, XMMRegister xtmp2) {
10131 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
10132 if (n > 0) {
10133 addl(tmp3, n * 256 * 8);
10134 }
10135 // Q1 = TABLEExt[n][B & 0xFF];
10136 movl(tmp1, in_out);
10137 andl(tmp1, 0x000000FF);
10138 shll(tmp1, 3);
10139 addl(tmp1, tmp3);
10140 movq(xtmp1, Address(tmp1, 0));
10141
10142 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
10143 movl(tmp2, in_out);
10144 shrl(tmp2, 8);
10145 andl(tmp2, 0x000000FF);
10146 shll(tmp2, 3);
10147 addl(tmp2, tmp3);
10148 movq(xtmp2, Address(tmp2, 0));
10149
10150 psllq(xtmp2, 8);
10151 pxor(xtmp1, xtmp2);
10152
10153 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
10154 movl(tmp2, in_out);
10155 shrl(tmp2, 16);
10156 andl(tmp2, 0x000000FF);
10157 shll(tmp2, 3);
10158 addl(tmp2, tmp3);
10159 movq(xtmp2, Address(tmp2, 0));
10160
10161 psllq(xtmp2, 16);
10162 pxor(xtmp1, xtmp2);
10163
10164 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
10165 shrl(in_out, 24);
10166 andl(in_out, 0x000000FF);
10167 shll(in_out, 3);
10168 addl(in_out, tmp3);
10169 movq(xtmp2, Address(in_out, 0));
10170
10171 psllq(xtmp2, 24);
10172 pxor(xtmp1, xtmp2); // Result in CXMM
10173 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
10174 }
10175
10176 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
10177 Register in_out,
10178 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
10179 XMMRegister w_xtmp2,
10180 Register tmp1,
10181 Register n_tmp2, Register n_tmp3) {
10182 if (is_pclmulqdq_supported) {
10183 movdl(w_xtmp1, in_out);
10184
10185 movl(tmp1, const_or_pre_comp_const_index);
10186 movdl(w_xtmp2, tmp1);
10187 pclmulqdq(w_xtmp1, w_xtmp2, 0);
10188 // Keep result in XMM since GPR is 32 bit in length
10189 } else {
10190 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3, w_xtmp1, w_xtmp2);
10191 }
10192 }
10193
10194 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
10195 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10196 Register tmp1, Register tmp2,
10197 Register n_tmp3) {
10198 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
10199 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
10200
10201 psllq(w_xtmp1, 1);
10202 movdl(tmp1, w_xtmp1);
10203 psrlq(w_xtmp1, 32);
10204 movdl(in_out, w_xtmp1);
10205
10206 xorl(tmp2, tmp2);
10207 crc32(tmp2, tmp1, 4);
10208 xorl(in_out, tmp2);
10209
10210 psllq(w_xtmp2, 1);
10211 movdl(tmp1, w_xtmp2);
10212 psrlq(w_xtmp2, 32);
10213 movdl(in1, w_xtmp2);
10214
10215 xorl(tmp2, tmp2);
10216 crc32(tmp2, tmp1, 4);
10217 xorl(in1, tmp2);
10218 xorl(in_out, in1);
10219 xorl(in_out, in2);
10220 }
10221
10222 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
10223 Register in_out1, Register in_out2, Register in_out3,
10224 Register tmp1, Register tmp2, Register tmp3,
10225 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10226 Register tmp4, Register tmp5,
10227 Register n_tmp6) {
10228 Label L_processPartitions;
10229 Label L_processPartition;
10230 Label L_exit;
10231
10232 bind(L_processPartitions);
10233 cmpl(in_out1, 3 * size);
10234 jcc(Assembler::less, L_exit);
10235 xorl(tmp1, tmp1);
10236 xorl(tmp2, tmp2);
10237 movl(tmp3, in_out2);
10238 addl(tmp3, size);
10239
10240 bind(L_processPartition);
10241 crc32(in_out3, Address(in_out2, 0), 4);
10242 crc32(tmp1, Address(in_out2, size), 4);
10243 crc32(tmp2, Address(in_out2, size*2), 4);
10244 crc32(in_out3, Address(in_out2, 0+4), 4);
10245 crc32(tmp1, Address(in_out2, size+4), 4);
10246 crc32(tmp2, Address(in_out2, size*2+4), 4);
10247 addl(in_out2, 8);
10248 cmpl(in_out2, tmp3);
10249 jcc(Assembler::less, L_processPartition);
10250
10251 push(tmp3);
10252 push(in_out1);
10253 push(in_out2);
10254 tmp4 = tmp3;
10255 tmp5 = in_out1;
10256 n_tmp6 = in_out2;
10257
10258 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
10259 w_xtmp1, w_xtmp2, w_xtmp3,
10260 tmp4, tmp5,
10261 n_tmp6);
10262
10263 pop(in_out2);
10264 pop(in_out1);
10265 pop(tmp3);
10266
10267 addl(in_out2, 2 * size);
10268 subl(in_out1, 3 * size);
10269 jmp(L_processPartitions);
10270
10271 bind(L_exit);
10272 }
10273 #endif //LP64
10274
10275 #ifdef _LP64
10276 // Algorithm 2: Pipelined usage of the CRC32 instruction.
10277 // Input: A buffer I of L bytes.
10278 // Output: the CRC32C value of the buffer.
10279 // Notations:
10280 // Write L = 24N + r, with N = floor (L/24).
10281 // r = L mod 24 (0 <= r < 24).
10282 // Consider I as the concatenation of A|B|C|R, where A, B, C, each,
10283 // N quadwords, and R consists of r bytes.
10284 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1
10285 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1
10286 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1
10287 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1
10288 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
10289 Register tmp1, Register tmp2, Register tmp3,
10290 Register tmp4, Register tmp5, Register tmp6,
10291 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10292 bool is_pclmulqdq_supported) {
10293 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
10294 Label L_wordByWord;
10295 Label L_byteByByteProlog;
10296 Label L_byteByByte;
10297 Label L_exit;
10298
10299 if (is_pclmulqdq_supported ) {
10300 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
10301 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr+1);
10302
10303 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
10304 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
10305
10306 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
10307 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
10308 assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\"");
10309 } else {
10310 const_or_pre_comp_const_index[0] = 1;
10311 const_or_pre_comp_const_index[1] = 0;
10312
10313 const_or_pre_comp_const_index[2] = 3;
10314 const_or_pre_comp_const_index[3] = 2;
10315
10316 const_or_pre_comp_const_index[4] = 5;
10317 const_or_pre_comp_const_index[5] = 4;
10318 }
10319 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
10320 in2, in1, in_out,
10321 tmp1, tmp2, tmp3,
10322 w_xtmp1, w_xtmp2, w_xtmp3,
10323 tmp4, tmp5,
10324 tmp6);
10325 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
10326 in2, in1, in_out,
10327 tmp1, tmp2, tmp3,
10328 w_xtmp1, w_xtmp2, w_xtmp3,
10329 tmp4, tmp5,
10330 tmp6);
10331 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
10332 in2, in1, in_out,
10333 tmp1, tmp2, tmp3,
10334 w_xtmp1, w_xtmp2, w_xtmp3,
10335 tmp4, tmp5,
10336 tmp6);
10337 movl(tmp1, in2);
10338 andl(tmp1, 0x00000007);
10339 negl(tmp1);
10340 addl(tmp1, in2);
10341 addq(tmp1, in1);
10342
10343 BIND(L_wordByWord);
10344 cmpq(in1, tmp1);
10345 jcc(Assembler::greaterEqual, L_byteByByteProlog);
10346 crc32(in_out, Address(in1, 0), 4);
10347 addq(in1, 4);
10348 jmp(L_wordByWord);
10349
10350 BIND(L_byteByByteProlog);
10351 andl(in2, 0x00000007);
10352 movl(tmp2, 1);
10353
10354 BIND(L_byteByByte);
10355 cmpl(tmp2, in2);
10356 jccb(Assembler::greater, L_exit);
10357 crc32(in_out, Address(in1, 0), 1);
10358 incq(in1);
10359 incl(tmp2);
10360 jmp(L_byteByByte);
10361
10362 BIND(L_exit);
10363 }
10364 #else
10365 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
10366 Register tmp1, Register tmp2, Register tmp3,
10367 Register tmp4, Register tmp5, Register tmp6,
10368 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10369 bool is_pclmulqdq_supported) {
10370 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
10371 Label L_wordByWord;
10372 Label L_byteByByteProlog;
10373 Label L_byteByByte;
10374 Label L_exit;
10375
10376 if (is_pclmulqdq_supported) {
10377 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
10378 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 1);
10379
10380 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
10381 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
10382
10383 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
10384 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
10385 } else {
10386 const_or_pre_comp_const_index[0] = 1;
10387 const_or_pre_comp_const_index[1] = 0;
10388
10389 const_or_pre_comp_const_index[2] = 3;
10390 const_or_pre_comp_const_index[3] = 2;
10391
10392 const_or_pre_comp_const_index[4] = 5;
10393 const_or_pre_comp_const_index[5] = 4;
10394 }
10395 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
10396 in2, in1, in_out,
10397 tmp1, tmp2, tmp3,
10398 w_xtmp1, w_xtmp2, w_xtmp3,
10399 tmp4, tmp5,
10400 tmp6);
10401 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
10402 in2, in1, in_out,
10403 tmp1, tmp2, tmp3,
10404 w_xtmp1, w_xtmp2, w_xtmp3,
10405 tmp4, tmp5,
10406 tmp6);
10407 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
10408 in2, in1, in_out,
10409 tmp1, tmp2, tmp3,
10410 w_xtmp1, w_xtmp2, w_xtmp3,
10411 tmp4, tmp5,
10412 tmp6);
10413 movl(tmp1, in2);
10414 andl(tmp1, 0x00000007);
10415 negl(tmp1);
10416 addl(tmp1, in2);
10417 addl(tmp1, in1);
10418
10419 BIND(L_wordByWord);
10420 cmpl(in1, tmp1);
10421 jcc(Assembler::greaterEqual, L_byteByByteProlog);
10422 crc32(in_out, Address(in1,0), 4);
10423 addl(in1, 4);
10424 jmp(L_wordByWord);
10425
10426 BIND(L_byteByByteProlog);
10427 andl(in2, 0x00000007);
10428 movl(tmp2, 1);
10429
10430 BIND(L_byteByByte);
10431 cmpl(tmp2, in2);
10432 jccb(Assembler::greater, L_exit);
10433 movb(tmp1, Address(in1, 0));
10434 crc32(in_out, tmp1, 1);
10435 incl(in1);
10436 incl(tmp2);
10437 jmp(L_byteByByte);
10438
10439 BIND(L_exit);
10440 }
10441 #endif // LP64
10442 #undef BIND
10443 #undef BLOCK_COMMENT
10444
10445 // Compress char[] array to byte[].
10446 // ..\jdk\src\java.base\share\classes\java\lang\StringUTF16.java
10447 // @HotSpotIntrinsicCandidate
10448 // private static int compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) {
10449 // for (int i = 0; i < len; i++) {
10450 // int c = src[srcOff++];
10451 // if (c >>> 8 != 0) {
10452 // return 0;
10453 // }
10454 // dst[dstOff++] = (byte)c;
10455 // }
10456 // return len;
10457 // }
10458 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
10459 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
10460 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
10461 Register tmp5, Register result) {
10462 Label copy_chars_loop, return_length, return_zero, done;
10463
10464 // rsi: src
10465 // rdi: dst
10466 // rdx: len
10467 // rcx: tmp5
10468 // rax: result
10469
10470 // rsi holds start addr of source char[] to be compressed
10471 // rdi holds start addr of destination byte[]
10472 // rdx holds length
10473
10474 assert(len != result, "");
10475
10476 // save length for return
10477 push(len);
10478
10479 if ((UseAVX > 2) && // AVX512
10480 VM_Version::supports_avx512vlbw() &&
10481 VM_Version::supports_bmi2()) {
10482
10483 set_vector_masking(); // opening of the stub context for programming mask registers
10484
10485 Label copy_32_loop, copy_loop_tail, restore_k1_return_zero, below_threshold;
10486
10487 // alignment
10488 Label post_alignment;
10489
10490 // if length of the string is less than 16, handle it in an old fashioned way
10491 testl(len, -32);
10492 jcc(Assembler::zero, below_threshold);
10493
10494 // First check whether a character is compressable ( <= 0xFF).
10495 // Create mask to test for Unicode chars inside zmm vector
10496 movl(result, 0x00FF);
10497 evpbroadcastw(tmp2Reg, result, Assembler::AVX_512bit);
10498
10499 // Save k1
10500 kmovql(k3, k1);
10501
10502 testl(len, -64);
10503 jcc(Assembler::zero, post_alignment);
10504
10505 movl(tmp5, dst);
10506 andl(tmp5, (32 - 1));
10507 negl(tmp5);
10508 andl(tmp5, (32 - 1));
10509
10510 // bail out when there is nothing to be done
10511 testl(tmp5, 0xFFFFFFFF);
10512 jcc(Assembler::zero, post_alignment);
10513
10514 // ~(~0 << len), where len is the # of remaining elements to process
10515 movl(result, 0xFFFFFFFF);
10516 shlxl(result, result, tmp5);
10517 notl(result);
10518 kmovdl(k1, result);
10519
10520 evmovdquw(tmp1Reg, k1, Address(src, 0), Assembler::AVX_512bit);
10521 evpcmpuw(k2, k1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
10522 ktestd(k2, k1);
10523 jcc(Assembler::carryClear, restore_k1_return_zero);
10524
10525 evpmovwb(Address(dst, 0), k1, tmp1Reg, Assembler::AVX_512bit);
10526
10527 addptr(src, tmp5);
10528 addptr(src, tmp5);
10529 addptr(dst, tmp5);
10530 subl(len, tmp5);
10531
10532 bind(post_alignment);
10533 // end of alignment
10534
10535 movl(tmp5, len);
10536 andl(tmp5, (32 - 1)); // tail count (in chars)
10537 andl(len, ~(32 - 1)); // vector count (in chars)
10538 jcc(Assembler::zero, copy_loop_tail);
10539
10540 lea(src, Address(src, len, Address::times_2));
10541 lea(dst, Address(dst, len, Address::times_1));
10542 negptr(len);
10543
10544 bind(copy_32_loop);
10545 evmovdquw(tmp1Reg, Address(src, len, Address::times_2), Assembler::AVX_512bit);
10546 evpcmpuw(k2, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
10547 kortestdl(k2, k2);
10548 jcc(Assembler::carryClear, restore_k1_return_zero);
10549
10550 // All elements in current processed chunk are valid candidates for
10551 // compression. Write a truncated byte elements to the memory.
10552 evpmovwb(Address(dst, len, Address::times_1), tmp1Reg, Assembler::AVX_512bit);
10553 addptr(len, 32);
10554 jcc(Assembler::notZero, copy_32_loop);
10555
10556 bind(copy_loop_tail);
10557 // bail out when there is nothing to be done
10558 testl(tmp5, 0xFFFFFFFF);
10559 // Restore k1
10560 kmovql(k1, k3);
10561 jcc(Assembler::zero, return_length);
10562
10563 movl(len, tmp5);
10564
10565 // ~(~0 << len), where len is the # of remaining elements to process
10566 movl(result, 0xFFFFFFFF);
10567 shlxl(result, result, len);
10568 notl(result);
10569
10570 kmovdl(k1, result);
10571
10572 evmovdquw(tmp1Reg, k1, Address(src, 0), Assembler::AVX_512bit);
10573 evpcmpuw(k2, k1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
10574 ktestd(k2, k1);
10575 jcc(Assembler::carryClear, restore_k1_return_zero);
10576
10577 evpmovwb(Address(dst, 0), k1, tmp1Reg, Assembler::AVX_512bit);
10578 // Restore k1
10579 kmovql(k1, k3);
10580 jmp(return_length);
10581
10582 bind(restore_k1_return_zero);
10583 // Restore k1
10584 kmovql(k1, k3);
10585 jmp(return_zero);
10586
10587 clear_vector_masking(); // closing of the stub context for programming mask registers
10588
10589 bind(below_threshold);
10590 }
10591
10592 if (UseSSE42Intrinsics) {
10593 Label copy_32_loop, copy_16, copy_tail;
10594
10595 movl(result, len);
10596
10597 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vectors
10598
10599 // vectored compression
10600 andl(len, 0xfffffff0); // vector count (in chars)
10601 andl(result, 0x0000000f); // tail count (in chars)
10602 testl(len, len);
10603 jcc(Assembler::zero, copy_16);
10604
10605 // compress 16 chars per iter
10606 movdl(tmp1Reg, tmp5);
10607 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
10608 pxor(tmp4Reg, tmp4Reg);
10609
10610 lea(src, Address(src, len, Address::times_2));
10611 lea(dst, Address(dst, len, Address::times_1));
10612 negptr(len);
10613
10614 bind(copy_32_loop);
10615 movdqu(tmp2Reg, Address(src, len, Address::times_2)); // load 1st 8 characters
10616 por(tmp4Reg, tmp2Reg);
10617 movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters
10618 por(tmp4Reg, tmp3Reg);
10619 ptest(tmp4Reg, tmp1Reg); // check for Unicode chars in next vector
10620 jcc(Assembler::notZero, return_zero);
10621 packuswb(tmp2Reg, tmp3Reg); // only ASCII chars; compress each to 1 byte
10622 movdqu(Address(dst, len, Address::times_1), tmp2Reg);
10623 addptr(len, 16);
10624 jcc(Assembler::notZero, copy_32_loop);
10625
10626 // compress next vector of 8 chars (if any)
10627 bind(copy_16);
10628 movl(len, result);
10629 andl(len, 0xfffffff8); // vector count (in chars)
10630 andl(result, 0x00000007); // tail count (in chars)
10631 testl(len, len);
10632 jccb(Assembler::zero, copy_tail);
10633
10634 movdl(tmp1Reg, tmp5);
10635 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
10636 pxor(tmp3Reg, tmp3Reg);
10637
10638 movdqu(tmp2Reg, Address(src, 0));
10639 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
10640 jccb(Assembler::notZero, return_zero);
10641 packuswb(tmp2Reg, tmp3Reg); // only LATIN1 chars; compress each to 1 byte
10642 movq(Address(dst, 0), tmp2Reg);
10643 addptr(src, 16);
10644 addptr(dst, 8);
10645
10646 bind(copy_tail);
10647 movl(len, result);
10648 }
10649 // compress 1 char per iter
10650 testl(len, len);
10651 jccb(Assembler::zero, return_length);
10652 lea(src, Address(src, len, Address::times_2));
10653 lea(dst, Address(dst, len, Address::times_1));
10654 negptr(len);
10655
10656 bind(copy_chars_loop);
10657 load_unsigned_short(result, Address(src, len, Address::times_2));
10658 testl(result, 0xff00); // check if Unicode char
10659 jccb(Assembler::notZero, return_zero);
10660 movb(Address(dst, len, Address::times_1), result); // ASCII char; compress to 1 byte
10661 increment(len);
10662 jcc(Assembler::notZero, copy_chars_loop);
10663
10664 // if compression succeeded, return length
10665 bind(return_length);
10666 pop(result);
10667 jmpb(done);
10668
10669 // if compression failed, return 0
10670 bind(return_zero);
10671 xorl(result, result);
10672 addptr(rsp, wordSize);
10673
10674 bind(done);
10675 }
10676
10677 // Inflate byte[] array to char[].
10678 // ..\jdk\src\java.base\share\classes\java\lang\StringLatin1.java
10679 // @HotSpotIntrinsicCandidate
10680 // private static void inflate(byte[] src, int srcOff, char[] dst, int dstOff, int len) {
10681 // for (int i = 0; i < len; i++) {
10682 // dst[dstOff++] = (char)(src[srcOff++] & 0xff);
10683 // }
10684 // }
10685 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
10686 XMMRegister tmp1, Register tmp2) {
10687 Label copy_chars_loop, done, below_threshold;
10688 // rsi: src
10689 // rdi: dst
10690 // rdx: len
10691 // rcx: tmp2
10692
10693 // rsi holds start addr of source byte[] to be inflated
10694 // rdi holds start addr of destination char[]
10695 // rdx holds length
10696 assert_different_registers(src, dst, len, tmp2);
10697
10698 if ((UseAVX > 2) && // AVX512
10699 VM_Version::supports_avx512vlbw() &&
10700 VM_Version::supports_bmi2()) {
10701
10702 set_vector_masking(); // opening of the stub context for programming mask registers
10703
10704 Label copy_32_loop, copy_tail;
10705 Register tmp3_aliased = len;
10706
10707 // if length of the string is less than 16, handle it in an old fashioned way
10708 testl(len, -16);
10709 jcc(Assembler::zero, below_threshold);
10710
10711 // In order to use only one arithmetic operation for the main loop we use
10712 // this pre-calculation
10713 movl(tmp2, len);
10714 andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop
10715 andl(len, -32); // vector count
10716 jccb(Assembler::zero, copy_tail);
10717
10718 lea(src, Address(src, len, Address::times_1));
10719 lea(dst, Address(dst, len, Address::times_2));
10720 negptr(len);
10721
10722
10723 // inflate 32 chars per iter
10724 bind(copy_32_loop);
10725 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_512bit);
10726 evmovdquw(Address(dst, len, Address::times_2), tmp1, Assembler::AVX_512bit);
10727 addptr(len, 32);
10728 jcc(Assembler::notZero, copy_32_loop);
10729
10730 bind(copy_tail);
10731 // bail out when there is nothing to be done
10732 testl(tmp2, -1); // we don't destroy the contents of tmp2 here
10733 jcc(Assembler::zero, done);
10734
10735 // Save k1
10736 kmovql(k2, k1);
10737
10738 // ~(~0 << length), where length is the # of remaining elements to process
10739 movl(tmp3_aliased, -1);
10740 shlxl(tmp3_aliased, tmp3_aliased, tmp2);
10741 notl(tmp3_aliased);
10742 kmovdl(k1, tmp3_aliased);
10743 evpmovzxbw(tmp1, k1, Address(src, 0), Assembler::AVX_512bit);
10744 evmovdquw(Address(dst, 0), k1, tmp1, Assembler::AVX_512bit);
10745
10746 // Restore k1
10747 kmovql(k1, k2);
10748 jmp(done);
10749
10750 clear_vector_masking(); // closing of the stub context for programming mask registers
10751 }
10752 if (UseSSE42Intrinsics) {
10753 Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail;
10754
10755 movl(tmp2, len);
10756
10757 if (UseAVX > 1) {
10758 andl(tmp2, (16 - 1));
10759 andl(len, -16);
10760 jccb(Assembler::zero, copy_new_tail);
10761 } else {
10762 andl(tmp2, 0x00000007); // tail count (in chars)
10763 andl(len, 0xfffffff8); // vector count (in chars)
10764 jccb(Assembler::zero, copy_tail);
10765 }
10766
10767 // vectored inflation
10768 lea(src, Address(src, len, Address::times_1));
10769 lea(dst, Address(dst, len, Address::times_2));
10770 negptr(len);
10771
10772 if (UseAVX > 1) {
10773 bind(copy_16_loop);
10774 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_256bit);
10775 vmovdqu(Address(dst, len, Address::times_2), tmp1);
10776 addptr(len, 16);
10777 jcc(Assembler::notZero, copy_16_loop);
10778
10779 bind(below_threshold);
10780 bind(copy_new_tail);
10781 if ((UseAVX > 2) &&
10782 VM_Version::supports_avx512vlbw() &&
10783 VM_Version::supports_bmi2()) {
10784 movl(tmp2, len);
10785 } else {
10786 movl(len, tmp2);
10787 }
10788 andl(tmp2, 0x00000007);
10789 andl(len, 0xFFFFFFF8);
10790 jccb(Assembler::zero, copy_tail);
10791
10792 pmovzxbw(tmp1, Address(src, 0));
10793 movdqu(Address(dst, 0), tmp1);
10794 addptr(src, 8);
10795 addptr(dst, 2 * 8);
10796
10797 jmp(copy_tail, true);
10798 }
10799
10800 // inflate 8 chars per iter
10801 bind(copy_8_loop);
10802 pmovzxbw(tmp1, Address(src, len, Address::times_1)); // unpack to 8 words
10803 movdqu(Address(dst, len, Address::times_2), tmp1);
10804 addptr(len, 8);
10805 jcc(Assembler::notZero, copy_8_loop);
10806
10807 bind(copy_tail);
10808 movl(len, tmp2);
10809
10810 cmpl(len, 4);
10811 jccb(Assembler::less, copy_bytes);
10812
10813 movdl(tmp1, Address(src, 0)); // load 4 byte chars
10814 pmovzxbw(tmp1, tmp1);
10815 movq(Address(dst, 0), tmp1);
10816 subptr(len, 4);
10817 addptr(src, 4);
10818 addptr(dst, 8);
10819
10820 bind(copy_bytes);
10821 } else {
10822 bind(below_threshold);
10823 }
10824
10825 testl(len, len);
10826 jccb(Assembler::zero, done);
10827 lea(src, Address(src, len, Address::times_1));
10828 lea(dst, Address(dst, len, Address::times_2));
10829 negptr(len);
10830
10831 // inflate 1 char per iter
10832 bind(copy_chars_loop);
10833 load_unsigned_byte(tmp2, Address(src, len, Address::times_1)); // load byte char
10834 movw(Address(dst, len, Address::times_2), tmp2); // inflate byte char to word
10835 increment(len);
10836 jcc(Assembler::notZero, copy_chars_loop);
10837
10838 bind(done);
10839 }
10840
10841 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
10842 switch (cond) {
10843 // Note some conditions are synonyms for others
10844 case Assembler::zero: return Assembler::notZero;
10845 case Assembler::notZero: return Assembler::zero;
10846 case Assembler::less: return Assembler::greaterEqual;
10847 case Assembler::lessEqual: return Assembler::greater;
10848 case Assembler::greater: return Assembler::lessEqual;
10849 case Assembler::greaterEqual: return Assembler::less;
10850 case Assembler::below: return Assembler::aboveEqual;
10851 case Assembler::belowEqual: return Assembler::above;
10852 case Assembler::above: return Assembler::belowEqual;
10853 case Assembler::aboveEqual: return Assembler::below;
10854 case Assembler::overflow: return Assembler::noOverflow;
10855 case Assembler::noOverflow: return Assembler::overflow;
10856 case Assembler::negative: return Assembler::positive;
10857 case Assembler::positive: return Assembler::negative;
10858 case Assembler::parity: return Assembler::noParity;
10859 case Assembler::noParity: return Assembler::parity;
10860 }
10861 ShouldNotReachHere(); return Assembler::overflow;
10862 }
10863
10864 SkipIfEqual::SkipIfEqual(
10865 MacroAssembler* masm, const bool* flag_addr, bool value) {
10866 _masm = masm;
10867 _masm->cmp8(ExternalAddress((address)flag_addr), value);
10868 _masm->jcc(Assembler::equal, _label);
10869 }
10870
10871 SkipIfEqual::~SkipIfEqual() {
10872 _masm->bind(_label);
10873 }
10874
10875 // 32-bit Windows has its own fast-path implementation
10876 // of get_thread
10877 #if !defined(WIN32) || defined(_LP64)
10878
10879 // This is simply a call to Thread::current()
10880 void MacroAssembler::get_thread(Register thread) {
10881 if (thread != rax) {
10882 push(rax);
10883 }
10884 LP64_ONLY(push(rdi);)
10885 LP64_ONLY(push(rsi);)
10886 push(rdx);
10887 push(rcx);
10888 #ifdef _LP64
10889 push(r8);
10890 push(r9);
10891 push(r10);
10892 push(r11);
10893 #endif
10894
10895 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0);
10896
10897 #ifdef _LP64
10898 pop(r11);
10899 pop(r10);
10900 pop(r9);
10901 pop(r8);
10902 #endif
10903 pop(rcx);
10904 pop(rdx);
10905 LP64_ONLY(pop(rsi);)
10906 LP64_ONLY(pop(rdi);)
10907 if (thread != rax) {
10908 mov(thread, rax);
10909 pop(rax);
10910 }
10911 }
10912
10913 #endif