1 /*
2 * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "jvm.h"
27 #include "asm/assembler.hpp"
28 #include "asm/assembler.inline.hpp"
29 #include "compiler/disassembler.hpp"
30 #include "gc/shared/barrierSet.hpp"
31 #include "gc/shared/barrierSetAssembler.hpp"
32 #include "gc/shared/collectedHeap.inline.hpp"
33 #include "interpreter/interpreter.hpp"
34 #include "memory/resourceArea.hpp"
35 #include "memory/universe.hpp"
36 #include "oops/accessDecorators.hpp"
37 #include "oops/klass.inline.hpp"
38 #include "prims/methodHandles.hpp"
39 #include "runtime/biasedLocking.hpp"
40 #include "runtime/flags/flagSetting.hpp"
41 #include "runtime/interfaceSupport.inline.hpp"
42 #include "runtime/objectMonitor.hpp"
43 #include "runtime/os.hpp"
44 #include "runtime/safepoint.hpp"
45 #include "runtime/safepointMechanism.hpp"
46 #include "runtime/sharedRuntime.hpp"
47 #include "runtime/stubRoutines.hpp"
48 #include "runtime/thread.hpp"
49 #include "utilities/macros.hpp"
50 #include "crc32c.h"
51 #ifdef COMPILER2
52 #include "opto/intrinsicnode.hpp"
53 #endif
54
55 #ifdef PRODUCT
56 #define BLOCK_COMMENT(str) /* nothing */
57 #define STOP(error) stop(error)
58 #else
59 #define BLOCK_COMMENT(str) block_comment(str)
60 #define STOP(error) block_comment(error); stop(error)
61 #endif
62
63 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
64
65 #ifdef ASSERT
66 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
67 #endif
68
69 static Assembler::Condition reverse[] = {
70 Assembler::noOverflow /* overflow = 0x0 */ ,
71 Assembler::overflow /* noOverflow = 0x1 */ ,
72 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
73 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
74 Assembler::notZero /* zero = 0x4, equal = 0x4 */ ,
75 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ ,
76 Assembler::above /* belowEqual = 0x6 */ ,
77 Assembler::belowEqual /* above = 0x7 */ ,
78 Assembler::positive /* negative = 0x8 */ ,
79 Assembler::negative /* positive = 0x9 */ ,
80 Assembler::noParity /* parity = 0xa */ ,
81 Assembler::parity /* noParity = 0xb */ ,
82 Assembler::greaterEqual /* less = 0xc */ ,
83 Assembler::less /* greaterEqual = 0xd */ ,
84 Assembler::greater /* lessEqual = 0xe */ ,
85 Assembler::lessEqual /* greater = 0xf, */
86
87 };
88
89
90 // Implementation of MacroAssembler
91
92 // First all the versions that have distinct versions depending on 32/64 bit
93 // Unless the difference is trivial (1 line or so).
94
95 #ifndef _LP64
96
97 // 32bit versions
98
99 Address MacroAssembler::as_Address(AddressLiteral adr) {
100 return Address(adr.target(), adr.rspec());
101 }
102
103 Address MacroAssembler::as_Address(ArrayAddress adr) {
104 return Address::make_array(adr);
105 }
106
107 void MacroAssembler::call_VM_leaf_base(address entry_point,
108 int number_of_arguments) {
109 call(RuntimeAddress(entry_point));
110 increment(rsp, number_of_arguments * wordSize);
111 }
112
113 void MacroAssembler::cmpklass(Address src1, Metadata* obj) {
114 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
115 }
116
117 void MacroAssembler::cmpklass(Register src1, Metadata* obj) {
118 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
119 }
120
121 void MacroAssembler::cmpoop_raw(Address src1, jobject obj) {
122 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
123 }
124
125 void MacroAssembler::cmpoop_raw(Register src1, jobject obj) {
126 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
127 }
128
129 void MacroAssembler::cmpoop(Address src1, jobject obj) {
130 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
131 bs->obj_equals(this, src1, obj);
132 }
133
134 void MacroAssembler::cmpoop(Register src1, jobject obj) {
135 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
136 bs->obj_equals(this, src1, obj);
137 }
138
139 void MacroAssembler::extend_sign(Register hi, Register lo) {
140 // According to Intel Doc. AP-526, "Integer Divide", p.18.
141 if (VM_Version::is_P6() && hi == rdx && lo == rax) {
142 cdql();
143 } else {
144 movl(hi, lo);
145 sarl(hi, 31);
146 }
147 }
148
149 void MacroAssembler::jC2(Register tmp, Label& L) {
150 // set parity bit if FPU flag C2 is set (via rax)
151 save_rax(tmp);
152 fwait(); fnstsw_ax();
153 sahf();
154 restore_rax(tmp);
155 // branch
156 jcc(Assembler::parity, L);
157 }
158
159 void MacroAssembler::jnC2(Register tmp, Label& L) {
160 // set parity bit if FPU flag C2 is set (via rax)
161 save_rax(tmp);
162 fwait(); fnstsw_ax();
163 sahf();
164 restore_rax(tmp);
165 // branch
166 jcc(Assembler::noParity, L);
167 }
168
169 // 32bit can do a case table jump in one instruction but we no longer allow the base
170 // to be installed in the Address class
171 void MacroAssembler::jump(ArrayAddress entry) {
172 jmp(as_Address(entry));
173 }
174
175 // Note: y_lo will be destroyed
176 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
177 // Long compare for Java (semantics as described in JVM spec.)
178 Label high, low, done;
179
180 cmpl(x_hi, y_hi);
181 jcc(Assembler::less, low);
182 jcc(Assembler::greater, high);
183 // x_hi is the return register
184 xorl(x_hi, x_hi);
185 cmpl(x_lo, y_lo);
186 jcc(Assembler::below, low);
187 jcc(Assembler::equal, done);
188
189 bind(high);
190 xorl(x_hi, x_hi);
191 increment(x_hi);
192 jmp(done);
193
194 bind(low);
195 xorl(x_hi, x_hi);
196 decrementl(x_hi);
197
198 bind(done);
199 }
200
201 void MacroAssembler::lea(Register dst, AddressLiteral src) {
202 mov_literal32(dst, (int32_t)src.target(), src.rspec());
203 }
204
205 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
206 // leal(dst, as_Address(adr));
207 // see note in movl as to why we must use a move
208 mov_literal32(dst, (int32_t) adr.target(), adr.rspec());
209 }
210
211 void MacroAssembler::leave() {
212 mov(rsp, rbp);
213 pop(rbp);
214 }
215
216 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
217 // Multiplication of two Java long values stored on the stack
218 // as illustrated below. Result is in rdx:rax.
219 //
220 // rsp ---> [ ?? ] \ \
221 // .... | y_rsp_offset |
222 // [ y_lo ] / (in bytes) | x_rsp_offset
223 // [ y_hi ] | (in bytes)
224 // .... |
225 // [ x_lo ] /
226 // [ x_hi ]
227 // ....
228 //
229 // Basic idea: lo(result) = lo(x_lo * y_lo)
230 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
231 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
232 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
233 Label quick;
234 // load x_hi, y_hi and check if quick
235 // multiplication is possible
236 movl(rbx, x_hi);
237 movl(rcx, y_hi);
238 movl(rax, rbx);
239 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0
240 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply
241 // do full multiplication
242 // 1st step
243 mull(y_lo); // x_hi * y_lo
244 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx,
245 // 2nd step
246 movl(rax, x_lo);
247 mull(rcx); // x_lo * y_hi
248 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx,
249 // 3rd step
250 bind(quick); // note: rbx, = 0 if quick multiply!
251 movl(rax, x_lo);
252 mull(y_lo); // x_lo * y_lo
253 addl(rdx, rbx); // correct hi(x_lo * y_lo)
254 }
255
256 void MacroAssembler::lneg(Register hi, Register lo) {
257 negl(lo);
258 adcl(hi, 0);
259 negl(hi);
260 }
261
262 void MacroAssembler::lshl(Register hi, Register lo) {
263 // Java shift left long support (semantics as described in JVM spec., p.305)
264 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
265 // shift value is in rcx !
266 assert(hi != rcx, "must not use rcx");
267 assert(lo != rcx, "must not use rcx");
268 const Register s = rcx; // shift count
269 const int n = BitsPerWord;
270 Label L;
271 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
272 cmpl(s, n); // if (s < n)
273 jcc(Assembler::less, L); // else (s >= n)
274 movl(hi, lo); // x := x << n
275 xorl(lo, lo);
276 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
277 bind(L); // s (mod n) < n
278 shldl(hi, lo); // x := x << s
279 shll(lo);
280 }
281
282
283 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
284 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
285 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
286 assert(hi != rcx, "must not use rcx");
287 assert(lo != rcx, "must not use rcx");
288 const Register s = rcx; // shift count
289 const int n = BitsPerWord;
290 Label L;
291 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
292 cmpl(s, n); // if (s < n)
293 jcc(Assembler::less, L); // else (s >= n)
294 movl(lo, hi); // x := x >> n
295 if (sign_extension) sarl(hi, 31);
296 else xorl(hi, hi);
297 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
298 bind(L); // s (mod n) < n
299 shrdl(lo, hi); // x := x >> s
300 if (sign_extension) sarl(hi);
301 else shrl(hi);
302 }
303
304 void MacroAssembler::movoop(Register dst, jobject obj) {
305 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
306 }
307
308 void MacroAssembler::movoop(Address dst, jobject obj) {
309 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
310 }
311
312 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
313 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
314 }
315
316 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
317 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
318 }
319
320 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
321 // scratch register is not used,
322 // it is defined to match parameters of 64-bit version of this method.
323 if (src.is_lval()) {
324 mov_literal32(dst, (intptr_t)src.target(), src.rspec());
325 } else {
326 movl(dst, as_Address(src));
327 }
328 }
329
330 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
331 movl(as_Address(dst), src);
332 }
333
334 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
335 movl(dst, as_Address(src));
336 }
337
338 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
339 void MacroAssembler::movptr(Address dst, intptr_t src) {
340 movl(dst, src);
341 }
342
343
344 void MacroAssembler::pop_callee_saved_registers() {
345 pop(rcx);
346 pop(rdx);
347 pop(rdi);
348 pop(rsi);
349 }
350
351 void MacroAssembler::pop_fTOS() {
352 fld_d(Address(rsp, 0));
353 addl(rsp, 2 * wordSize);
354 }
355
356 void MacroAssembler::push_callee_saved_registers() {
357 push(rsi);
358 push(rdi);
359 push(rdx);
360 push(rcx);
361 }
362
363 void MacroAssembler::push_fTOS() {
364 subl(rsp, 2 * wordSize);
365 fstp_d(Address(rsp, 0));
366 }
367
368
369 void MacroAssembler::pushoop(jobject obj) {
370 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
371 }
372
373 void MacroAssembler::pushklass(Metadata* obj) {
374 push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate());
375 }
376
377 void MacroAssembler::pushptr(AddressLiteral src) {
378 if (src.is_lval()) {
379 push_literal32((int32_t)src.target(), src.rspec());
380 } else {
381 pushl(as_Address(src));
382 }
383 }
384
385 void MacroAssembler::set_word_if_not_zero(Register dst) {
386 xorl(dst, dst);
387 set_byte_if_not_zero(dst);
388 }
389
390 static void pass_arg0(MacroAssembler* masm, Register arg) {
391 masm->push(arg);
392 }
393
394 static void pass_arg1(MacroAssembler* masm, Register arg) {
395 masm->push(arg);
396 }
397
398 static void pass_arg2(MacroAssembler* masm, Register arg) {
399 masm->push(arg);
400 }
401
402 static void pass_arg3(MacroAssembler* masm, Register arg) {
403 masm->push(arg);
404 }
405
406 #ifndef PRODUCT
407 extern "C" void findpc(intptr_t x);
408 #endif
409
410 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
411 // In order to get locks to work, we need to fake a in_VM state
412 JavaThread* thread = JavaThread::current();
413 JavaThreadState saved_state = thread->thread_state();
414 thread->set_thread_state(_thread_in_vm);
415 if (ShowMessageBoxOnError) {
416 JavaThread* thread = JavaThread::current();
417 JavaThreadState saved_state = thread->thread_state();
418 thread->set_thread_state(_thread_in_vm);
419 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
420 ttyLocker ttyl;
421 BytecodeCounter::print();
422 }
423 // To see where a verify_oop failed, get $ebx+40/X for this frame.
424 // This is the value of eip which points to where verify_oop will return.
425 if (os::message_box(msg, "Execution stopped, print registers?")) {
426 print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip);
427 BREAKPOINT;
428 }
429 } else {
430 ttyLocker ttyl;
431 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg);
432 }
433 // Don't assert holding the ttyLock
434 assert(false, "DEBUG MESSAGE: %s", msg);
435 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
436 }
437
438 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) {
439 ttyLocker ttyl;
440 FlagSetting fs(Debugging, true);
441 tty->print_cr("eip = 0x%08x", eip);
442 #ifndef PRODUCT
443 if ((WizardMode || Verbose) && PrintMiscellaneous) {
444 tty->cr();
445 findpc(eip);
446 tty->cr();
447 }
448 #endif
449 #define PRINT_REG(rax) \
450 { tty->print("%s = ", #rax); os::print_location(tty, rax); }
451 PRINT_REG(rax);
452 PRINT_REG(rbx);
453 PRINT_REG(rcx);
454 PRINT_REG(rdx);
455 PRINT_REG(rdi);
456 PRINT_REG(rsi);
457 PRINT_REG(rbp);
458 PRINT_REG(rsp);
459 #undef PRINT_REG
460 // Print some words near top of staack.
461 int* dump_sp = (int*) rsp;
462 for (int col1 = 0; col1 < 8; col1++) {
463 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
464 os::print_location(tty, *dump_sp++);
465 }
466 for (int row = 0; row < 16; row++) {
467 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
468 for (int col = 0; col < 8; col++) {
469 tty->print(" 0x%08x", *dump_sp++);
470 }
471 tty->cr();
472 }
473 // Print some instructions around pc:
474 Disassembler::decode((address)eip-64, (address)eip);
475 tty->print_cr("--------");
476 Disassembler::decode((address)eip, (address)eip+32);
477 }
478
479 void MacroAssembler::stop(const char* msg) {
480 ExternalAddress message((address)msg);
481 // push address of message
482 pushptr(message.addr());
483 { Label L; call(L, relocInfo::none); bind(L); } // push eip
484 pusha(); // push registers
485 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
486 hlt();
487 }
488
489 void MacroAssembler::warn(const char* msg) {
490 push_CPU_state();
491
492 ExternalAddress message((address) msg);
493 // push address of message
494 pushptr(message.addr());
495
496 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
497 addl(rsp, wordSize); // discard argument
498 pop_CPU_state();
499 }
500
501 void MacroAssembler::print_state() {
502 { Label L; call(L, relocInfo::none); bind(L); } // push eip
503 pusha(); // push registers
504
505 push_CPU_state();
506 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32)));
507 pop_CPU_state();
508
509 popa();
510 addl(rsp, wordSize);
511 }
512
513 #else // _LP64
514
515 // 64 bit versions
516
517 Address MacroAssembler::as_Address(AddressLiteral adr) {
518 // amd64 always does this as a pc-rel
519 // we can be absolute or disp based on the instruction type
520 // jmp/call are displacements others are absolute
521 assert(!adr.is_lval(), "must be rval");
522 assert(reachable(adr), "must be");
523 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc());
524
525 }
526
527 Address MacroAssembler::as_Address(ArrayAddress adr) {
528 AddressLiteral base = adr.base();
529 lea(rscratch1, base);
530 Address index = adr.index();
531 assert(index._disp == 0, "must not have disp"); // maybe it can?
532 Address array(rscratch1, index._index, index._scale, index._disp);
533 return array;
534 }
535
536 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
537 Label L, E;
538
539 #ifdef _WIN64
540 // Windows always allocates space for it's register args
541 assert(num_args <= 4, "only register arguments supported");
542 subq(rsp, frame::arg_reg_save_area_bytes);
543 #endif
544
545 // Align stack if necessary
546 testl(rsp, 15);
547 jcc(Assembler::zero, L);
548
549 subq(rsp, 8);
550 {
551 call(RuntimeAddress(entry_point));
552 }
553 addq(rsp, 8);
554 jmp(E);
555
556 bind(L);
557 {
558 call(RuntimeAddress(entry_point));
559 }
560
561 bind(E);
562
563 #ifdef _WIN64
564 // restore stack pointer
565 addq(rsp, frame::arg_reg_save_area_bytes);
566 #endif
567
568 }
569
570 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) {
571 assert(!src2.is_lval(), "should use cmpptr");
572
573 if (reachable(src2)) {
574 cmpq(src1, as_Address(src2));
575 } else {
576 lea(rscratch1, src2);
577 Assembler::cmpq(src1, Address(rscratch1, 0));
578 }
579 }
580
581 int MacroAssembler::corrected_idivq(Register reg) {
582 // Full implementation of Java ldiv and lrem; checks for special
583 // case as described in JVM spec., p.243 & p.271. The function
584 // returns the (pc) offset of the idivl instruction - may be needed
585 // for implicit exceptions.
586 //
587 // normal case special case
588 //
589 // input : rax: dividend min_long
590 // reg: divisor (may not be eax/edx) -1
591 //
592 // output: rax: quotient (= rax idiv reg) min_long
593 // rdx: remainder (= rax irem reg) 0
594 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
595 static const int64_t min_long = 0x8000000000000000;
596 Label normal_case, special_case;
597
598 // check for special case
599 cmp64(rax, ExternalAddress((address) &min_long));
600 jcc(Assembler::notEqual, normal_case);
601 xorl(rdx, rdx); // prepare rdx for possible special case (where
602 // remainder = 0)
603 cmpq(reg, -1);
604 jcc(Assembler::equal, special_case);
605
606 // handle normal case
607 bind(normal_case);
608 cdqq();
609 int idivq_offset = offset();
610 idivq(reg);
611
612 // normal and special case exit
613 bind(special_case);
614
615 return idivq_offset;
616 }
617
618 void MacroAssembler::decrementq(Register reg, int value) {
619 if (value == min_jint) { subq(reg, value); return; }
620 if (value < 0) { incrementq(reg, -value); return; }
621 if (value == 0) { ; return; }
622 if (value == 1 && UseIncDec) { decq(reg) ; return; }
623 /* else */ { subq(reg, value) ; return; }
624 }
625
626 void MacroAssembler::decrementq(Address dst, int value) {
627 if (value == min_jint) { subq(dst, value); return; }
628 if (value < 0) { incrementq(dst, -value); return; }
629 if (value == 0) { ; return; }
630 if (value == 1 && UseIncDec) { decq(dst) ; return; }
631 /* else */ { subq(dst, value) ; return; }
632 }
633
634 void MacroAssembler::incrementq(AddressLiteral dst) {
635 if (reachable(dst)) {
636 incrementq(as_Address(dst));
637 } else {
638 lea(rscratch1, dst);
639 incrementq(Address(rscratch1, 0));
640 }
641 }
642
643 void MacroAssembler::incrementq(Register reg, int value) {
644 if (value == min_jint) { addq(reg, value); return; }
645 if (value < 0) { decrementq(reg, -value); return; }
646 if (value == 0) { ; return; }
647 if (value == 1 && UseIncDec) { incq(reg) ; return; }
648 /* else */ { addq(reg, value) ; return; }
649 }
650
651 void MacroAssembler::incrementq(Address dst, int value) {
652 if (value == min_jint) { addq(dst, value); return; }
653 if (value < 0) { decrementq(dst, -value); return; }
654 if (value == 0) { ; return; }
655 if (value == 1 && UseIncDec) { incq(dst) ; return; }
656 /* else */ { addq(dst, value) ; return; }
657 }
658
659 // 32bit can do a case table jump in one instruction but we no longer allow the base
660 // to be installed in the Address class
661 void MacroAssembler::jump(ArrayAddress entry) {
662 lea(rscratch1, entry.base());
663 Address dispatch = entry.index();
664 assert(dispatch._base == noreg, "must be");
665 dispatch._base = rscratch1;
666 jmp(dispatch);
667 }
668
669 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
670 ShouldNotReachHere(); // 64bit doesn't use two regs
671 cmpq(x_lo, y_lo);
672 }
673
674 void MacroAssembler::lea(Register dst, AddressLiteral src) {
675 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
676 }
677
678 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
679 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec());
680 movptr(dst, rscratch1);
681 }
682
683 void MacroAssembler::leave() {
684 // %%% is this really better? Why not on 32bit too?
685 emit_int8((unsigned char)0xC9); // LEAVE
686 }
687
688 void MacroAssembler::lneg(Register hi, Register lo) {
689 ShouldNotReachHere(); // 64bit doesn't use two regs
690 negq(lo);
691 }
692
693 void MacroAssembler::movoop(Register dst, jobject obj) {
694 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
695 }
696
697 void MacroAssembler::movoop(Address dst, jobject obj) {
698 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate());
699 movq(dst, rscratch1);
700 }
701
702 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
703 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
704 }
705
706 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
707 mov_literal64(rscratch1, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
708 movq(dst, rscratch1);
709 }
710
711 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
712 if (src.is_lval()) {
713 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
714 } else {
715 if (reachable(src)) {
716 movq(dst, as_Address(src));
717 } else {
718 lea(scratch, src);
719 movq(dst, Address(scratch, 0));
720 }
721 }
722 }
723
724 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
725 movq(as_Address(dst), src);
726 }
727
728 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
729 movq(dst, as_Address(src));
730 }
731
732 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
733 void MacroAssembler::movptr(Address dst, intptr_t src) {
734 mov64(rscratch1, src);
735 movq(dst, rscratch1);
736 }
737
738 // These are mostly for initializing NULL
739 void MacroAssembler::movptr(Address dst, int32_t src) {
740 movslq(dst, src);
741 }
742
743 void MacroAssembler::movptr(Register dst, int32_t src) {
744 mov64(dst, (intptr_t)src);
745 }
746
747 void MacroAssembler::pushoop(jobject obj) {
748 movoop(rscratch1, obj);
749 push(rscratch1);
750 }
751
752 void MacroAssembler::pushklass(Metadata* obj) {
753 mov_metadata(rscratch1, obj);
754 push(rscratch1);
755 }
756
757 void MacroAssembler::pushptr(AddressLiteral src) {
758 lea(rscratch1, src);
759 if (src.is_lval()) {
760 push(rscratch1);
761 } else {
762 pushq(Address(rscratch1, 0));
763 }
764 }
765
766 void MacroAssembler::reset_last_Java_frame(bool clear_fp) {
767 // we must set sp to zero to clear frame
768 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
769 // must clear fp, so that compiled frames are not confused; it is
770 // possible that we need it only for debugging
771 if (clear_fp) {
772 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
773 }
774
775 // Always clear the pc because it could have been set by make_walkable()
776 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
777 vzeroupper();
778 }
779
780 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
781 Register last_java_fp,
782 address last_java_pc) {
783 vzeroupper();
784 // determine last_java_sp register
785 if (!last_java_sp->is_valid()) {
786 last_java_sp = rsp;
787 }
788
789 // last_java_fp is optional
790 if (last_java_fp->is_valid()) {
791 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()),
792 last_java_fp);
793 }
794
795 // last_java_pc is optional
796 if (last_java_pc != NULL) {
797 Address java_pc(r15_thread,
798 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
799 lea(rscratch1, InternalAddress(last_java_pc));
800 movptr(java_pc, rscratch1);
801 }
802
803 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
804 }
805
806 static void pass_arg0(MacroAssembler* masm, Register arg) {
807 if (c_rarg0 != arg ) {
808 masm->mov(c_rarg0, arg);
809 }
810 }
811
812 static void pass_arg1(MacroAssembler* masm, Register arg) {
813 if (c_rarg1 != arg ) {
814 masm->mov(c_rarg1, arg);
815 }
816 }
817
818 static void pass_arg2(MacroAssembler* masm, Register arg) {
819 if (c_rarg2 != arg ) {
820 masm->mov(c_rarg2, arg);
821 }
822 }
823
824 static void pass_arg3(MacroAssembler* masm, Register arg) {
825 if (c_rarg3 != arg ) {
826 masm->mov(c_rarg3, arg);
827 }
828 }
829
830 void MacroAssembler::stop(const char* msg) {
831 address rip = pc();
832 pusha(); // get regs on stack
833 lea(c_rarg0, ExternalAddress((address) msg));
834 lea(c_rarg1, InternalAddress(rip));
835 movq(c_rarg2, rsp); // pass pointer to regs array
836 andq(rsp, -16); // align stack as required by ABI
837 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
838 hlt();
839 }
840
841 void MacroAssembler::warn(const char* msg) {
842 push(rbp);
843 movq(rbp, rsp);
844 andq(rsp, -16); // align stack as required by push_CPU_state and call
845 push_CPU_state(); // keeps alignment at 16 bytes
846 lea(c_rarg0, ExternalAddress((address) msg));
847 lea(rax, ExternalAddress(CAST_FROM_FN_PTR(address, warning)));
848 call(rax);
849 pop_CPU_state();
850 mov(rsp, rbp);
851 pop(rbp);
852 }
853
854 void MacroAssembler::print_state() {
855 address rip = pc();
856 pusha(); // get regs on stack
857 push(rbp);
858 movq(rbp, rsp);
859 andq(rsp, -16); // align stack as required by push_CPU_state and call
860 push_CPU_state(); // keeps alignment at 16 bytes
861
862 lea(c_rarg0, InternalAddress(rip));
863 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
864 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
865
866 pop_CPU_state();
867 mov(rsp, rbp);
868 pop(rbp);
869 popa();
870 }
871
872 #ifndef PRODUCT
873 extern "C" void findpc(intptr_t x);
874 #endif
875
876 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
877 // In order to get locks to work, we need to fake a in_VM state
878 if (ShowMessageBoxOnError) {
879 JavaThread* thread = JavaThread::current();
880 JavaThreadState saved_state = thread->thread_state();
881 thread->set_thread_state(_thread_in_vm);
882 #ifndef PRODUCT
883 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
884 ttyLocker ttyl;
885 BytecodeCounter::print();
886 }
887 #endif
888 // To see where a verify_oop failed, get $ebx+40/X for this frame.
889 // XXX correct this offset for amd64
890 // This is the value of eip which points to where verify_oop will return.
891 if (os::message_box(msg, "Execution stopped, print registers?")) {
892 print_state64(pc, regs);
893 BREAKPOINT;
894 assert(false, "start up GDB");
895 }
896 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
897 } else {
898 ttyLocker ttyl;
899 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n",
900 msg);
901 assert(false, "DEBUG MESSAGE: %s", msg);
902 }
903 }
904
905 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
906 ttyLocker ttyl;
907 FlagSetting fs(Debugging, true);
908 tty->print_cr("rip = 0x%016lx", (intptr_t)pc);
909 #ifndef PRODUCT
910 tty->cr();
911 findpc(pc);
912 tty->cr();
913 #endif
914 #define PRINT_REG(rax, value) \
915 { tty->print("%s = ", #rax); os::print_location(tty, value); }
916 PRINT_REG(rax, regs[15]);
917 PRINT_REG(rbx, regs[12]);
918 PRINT_REG(rcx, regs[14]);
919 PRINT_REG(rdx, regs[13]);
920 PRINT_REG(rdi, regs[8]);
921 PRINT_REG(rsi, regs[9]);
922 PRINT_REG(rbp, regs[10]);
923 PRINT_REG(rsp, regs[11]);
924 PRINT_REG(r8 , regs[7]);
925 PRINT_REG(r9 , regs[6]);
926 PRINT_REG(r10, regs[5]);
927 PRINT_REG(r11, regs[4]);
928 PRINT_REG(r12, regs[3]);
929 PRINT_REG(r13, regs[2]);
930 PRINT_REG(r14, regs[1]);
931 PRINT_REG(r15, regs[0]);
932 #undef PRINT_REG
933 // Print some words near top of staack.
934 int64_t* rsp = (int64_t*) regs[11];
935 int64_t* dump_sp = rsp;
936 for (int col1 = 0; col1 < 8; col1++) {
937 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
938 os::print_location(tty, *dump_sp++);
939 }
940 for (int row = 0; row < 25; row++) {
941 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
942 for (int col = 0; col < 4; col++) {
943 tty->print(" 0x%016lx", (intptr_t)*dump_sp++);
944 }
945 tty->cr();
946 }
947 // Print some instructions around pc:
948 Disassembler::decode((address)pc-64, (address)pc);
949 tty->print_cr("--------");
950 Disassembler::decode((address)pc, (address)pc+32);
951 }
952
953 #endif // _LP64
954
955 // Now versions that are common to 32/64 bit
956
957 void MacroAssembler::addptr(Register dst, int32_t imm32) {
958 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
959 }
960
961 void MacroAssembler::addptr(Register dst, Register src) {
962 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
963 }
964
965 void MacroAssembler::addptr(Address dst, Register src) {
966 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
967 }
968
969 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) {
970 if (reachable(src)) {
971 Assembler::addsd(dst, as_Address(src));
972 } else {
973 lea(rscratch1, src);
974 Assembler::addsd(dst, Address(rscratch1, 0));
975 }
976 }
977
978 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) {
979 if (reachable(src)) {
980 addss(dst, as_Address(src));
981 } else {
982 lea(rscratch1, src);
983 addss(dst, Address(rscratch1, 0));
984 }
985 }
986
987 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src) {
988 if (reachable(src)) {
989 Assembler::addpd(dst, as_Address(src));
990 } else {
991 lea(rscratch1, src);
992 Assembler::addpd(dst, Address(rscratch1, 0));
993 }
994 }
995
996 void MacroAssembler::align(int modulus) {
997 align(modulus, offset());
998 }
999
1000 void MacroAssembler::align(int modulus, int target) {
1001 if (target % modulus != 0) {
1002 nop(modulus - (target % modulus));
1003 }
1004 }
1005
1006 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) {
1007 // Used in sign-masking with aligned address.
1008 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1009 if (reachable(src)) {
1010 Assembler::andpd(dst, as_Address(src));
1011 } else {
1012 lea(rscratch1, src);
1013 Assembler::andpd(dst, Address(rscratch1, 0));
1014 }
1015 }
1016
1017 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src) {
1018 // Used in sign-masking with aligned address.
1019 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1020 if (reachable(src)) {
1021 Assembler::andps(dst, as_Address(src));
1022 } else {
1023 lea(rscratch1, src);
1024 Assembler::andps(dst, Address(rscratch1, 0));
1025 }
1026 }
1027
1028 void MacroAssembler::andptr(Register dst, int32_t imm32) {
1029 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
1030 }
1031
1032 void MacroAssembler::atomic_incl(Address counter_addr) {
1033 if (os::is_MP())
1034 lock();
1035 incrementl(counter_addr);
1036 }
1037
1038 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register scr) {
1039 if (reachable(counter_addr)) {
1040 atomic_incl(as_Address(counter_addr));
1041 } else {
1042 lea(scr, counter_addr);
1043 atomic_incl(Address(scr, 0));
1044 }
1045 }
1046
1047 #ifdef _LP64
1048 void MacroAssembler::atomic_incq(Address counter_addr) {
1049 if (os::is_MP())
1050 lock();
1051 incrementq(counter_addr);
1052 }
1053
1054 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register scr) {
1055 if (reachable(counter_addr)) {
1056 atomic_incq(as_Address(counter_addr));
1057 } else {
1058 lea(scr, counter_addr);
1059 atomic_incq(Address(scr, 0));
1060 }
1061 }
1062 #endif
1063
1064 // Writes to stack successive pages until offset reached to check for
1065 // stack overflow + shadow pages. This clobbers tmp.
1066 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
1067 movptr(tmp, rsp);
1068 // Bang stack for total size given plus shadow page size.
1069 // Bang one page at a time because large size can bang beyond yellow and
1070 // red zones.
1071 Label loop;
1072 bind(loop);
1073 movl(Address(tmp, (-os::vm_page_size())), size );
1074 subptr(tmp, os::vm_page_size());
1075 subl(size, os::vm_page_size());
1076 jcc(Assembler::greater, loop);
1077
1078 // Bang down shadow pages too.
1079 // At this point, (tmp-0) is the last address touched, so don't
1080 // touch it again. (It was touched as (tmp-pagesize) but then tmp
1081 // was post-decremented.) Skip this address by starting at i=1, and
1082 // touch a few more pages below. N.B. It is important to touch all
1083 // the way down including all pages in the shadow zone.
1084 for (int i = 1; i < ((int)JavaThread::stack_shadow_zone_size() / os::vm_page_size()); i++) {
1085 // this could be any sized move but this is can be a debugging crumb
1086 // so the bigger the better.
1087 movptr(Address(tmp, (-i*os::vm_page_size())), size );
1088 }
1089 }
1090
1091 void MacroAssembler::reserved_stack_check() {
1092 // testing if reserved zone needs to be enabled
1093 Label no_reserved_zone_enabling;
1094 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
1095 NOT_LP64(get_thread(rsi);)
1096
1097 cmpptr(rsp, Address(thread, JavaThread::reserved_stack_activation_offset()));
1098 jcc(Assembler::below, no_reserved_zone_enabling);
1099
1100 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), thread);
1101 jump(RuntimeAddress(StubRoutines::throw_delayed_StackOverflowError_entry()));
1102 should_not_reach_here();
1103
1104 bind(no_reserved_zone_enabling);
1105 }
1106
1107 int MacroAssembler::biased_locking_enter(Register lock_reg,
1108 Register obj_reg,
1109 Register swap_reg,
1110 Register tmp_reg,
1111 bool swap_reg_contains_mark,
1112 Label& done,
1113 Label* slow_case,
1114 BiasedLockingCounters* counters) {
1115 assert(UseBiasedLocking, "why call this otherwise?");
1116 assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq");
1117 assert(tmp_reg != noreg, "tmp_reg must be supplied");
1118 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg);
1119 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
1120 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes());
1121 NOT_LP64( Address saved_mark_addr(lock_reg, 0); )
1122
1123 if (PrintBiasedLockingStatistics && counters == NULL) {
1124 counters = BiasedLocking::counters();
1125 }
1126 // Biased locking
1127 // See whether the lock is currently biased toward our thread and
1128 // whether the epoch is still valid
1129 // Note that the runtime guarantees sufficient alignment of JavaThread
1130 // pointers to allow age to be placed into low bits
1131 // First check to see whether biasing is even enabled for this object
1132 Label cas_label;
1133 int null_check_offset = -1;
1134 if (!swap_reg_contains_mark) {
1135 null_check_offset = offset();
1136 movptr(swap_reg, mark_addr);
1137 }
1138 movptr(tmp_reg, swap_reg);
1139 andptr(tmp_reg, markOopDesc::biased_lock_mask_in_place);
1140 cmpptr(tmp_reg, markOopDesc::biased_lock_pattern);
1141 jcc(Assembler::notEqual, cas_label);
1142 // The bias pattern is present in the object's header. Need to check
1143 // whether the bias owner and the epoch are both still current.
1144 #ifndef _LP64
1145 // Note that because there is no current thread register on x86_32 we
1146 // need to store off the mark word we read out of the object to
1147 // avoid reloading it and needing to recheck invariants below. This
1148 // store is unfortunate but it makes the overall code shorter and
1149 // simpler.
1150 movptr(saved_mark_addr, swap_reg);
1151 #endif
1152 if (swap_reg_contains_mark) {
1153 null_check_offset = offset();
1154 }
1155 load_prototype_header(tmp_reg, obj_reg);
1156 #ifdef _LP64
1157 orptr(tmp_reg, r15_thread);
1158 xorptr(tmp_reg, swap_reg);
1159 Register header_reg = tmp_reg;
1160 #else
1161 xorptr(tmp_reg, swap_reg);
1162 get_thread(swap_reg);
1163 xorptr(swap_reg, tmp_reg);
1164 Register header_reg = swap_reg;
1165 #endif
1166 andptr(header_reg, ~((int) markOopDesc::age_mask_in_place));
1167 if (counters != NULL) {
1168 cond_inc32(Assembler::zero,
1169 ExternalAddress((address) counters->biased_lock_entry_count_addr()));
1170 }
1171 jcc(Assembler::equal, done);
1172
1173 Label try_revoke_bias;
1174 Label try_rebias;
1175
1176 // At this point we know that the header has the bias pattern and
1177 // that we are not the bias owner in the current epoch. We need to
1178 // figure out more details about the state of the header in order to
1179 // know what operations can be legally performed on the object's
1180 // header.
1181
1182 // If the low three bits in the xor result aren't clear, that means
1183 // the prototype header is no longer biased and we have to revoke
1184 // the bias on this object.
1185 testptr(header_reg, markOopDesc::biased_lock_mask_in_place);
1186 jccb(Assembler::notZero, try_revoke_bias);
1187
1188 // Biasing is still enabled for this data type. See whether the
1189 // epoch of the current bias is still valid, meaning that the epoch
1190 // bits of the mark word are equal to the epoch bits of the
1191 // prototype header. (Note that the prototype header's epoch bits
1192 // only change at a safepoint.) If not, attempt to rebias the object
1193 // toward the current thread. Note that we must be absolutely sure
1194 // that the current epoch is invalid in order to do this because
1195 // otherwise the manipulations it performs on the mark word are
1196 // illegal.
1197 testptr(header_reg, markOopDesc::epoch_mask_in_place);
1198 jccb(Assembler::notZero, try_rebias);
1199
1200 // The epoch of the current bias is still valid but we know nothing
1201 // about the owner; it might be set or it might be clear. Try to
1202 // acquire the bias of the object using an atomic operation. If this
1203 // fails we will go in to the runtime to revoke the object's bias.
1204 // Note that we first construct the presumed unbiased header so we
1205 // don't accidentally blow away another thread's valid bias.
1206 NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1207 andptr(swap_reg,
1208 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
1209 #ifdef _LP64
1210 movptr(tmp_reg, swap_reg);
1211 orptr(tmp_reg, r15_thread);
1212 #else
1213 get_thread(tmp_reg);
1214 orptr(tmp_reg, swap_reg);
1215 #endif
1216 if (os::is_MP()) {
1217 lock();
1218 }
1219 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1220 // If the biasing toward our thread failed, this means that
1221 // another thread succeeded in biasing it toward itself and we
1222 // need to revoke that bias. The revocation will occur in the
1223 // interpreter runtime in the slow case.
1224 if (counters != NULL) {
1225 cond_inc32(Assembler::zero,
1226 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr()));
1227 }
1228 if (slow_case != NULL) {
1229 jcc(Assembler::notZero, *slow_case);
1230 }
1231 jmp(done);
1232
1233 bind(try_rebias);
1234 // At this point we know the epoch has expired, meaning that the
1235 // current "bias owner", if any, is actually invalid. Under these
1236 // circumstances _only_, we are allowed to use the current header's
1237 // value as the comparison value when doing the cas to acquire the
1238 // bias in the current epoch. In other words, we allow transfer of
1239 // the bias from one thread to another directly in this situation.
1240 //
1241 // FIXME: due to a lack of registers we currently blow away the age
1242 // bits in this situation. Should attempt to preserve them.
1243 load_prototype_header(tmp_reg, obj_reg);
1244 #ifdef _LP64
1245 orptr(tmp_reg, r15_thread);
1246 #else
1247 get_thread(swap_reg);
1248 orptr(tmp_reg, swap_reg);
1249 movptr(swap_reg, saved_mark_addr);
1250 #endif
1251 if (os::is_MP()) {
1252 lock();
1253 }
1254 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1255 // If the biasing toward our thread failed, then another thread
1256 // succeeded in biasing it toward itself and we need to revoke that
1257 // bias. The revocation will occur in the runtime in the slow case.
1258 if (counters != NULL) {
1259 cond_inc32(Assembler::zero,
1260 ExternalAddress((address) counters->rebiased_lock_entry_count_addr()));
1261 }
1262 if (slow_case != NULL) {
1263 jcc(Assembler::notZero, *slow_case);
1264 }
1265 jmp(done);
1266
1267 bind(try_revoke_bias);
1268 // The prototype mark in the klass doesn't have the bias bit set any
1269 // more, indicating that objects of this data type are not supposed
1270 // to be biased any more. We are going to try to reset the mark of
1271 // this object to the prototype value and fall through to the
1272 // CAS-based locking scheme. Note that if our CAS fails, it means
1273 // that another thread raced us for the privilege of revoking the
1274 // bias of this particular object, so it's okay to continue in the
1275 // normal locking code.
1276 //
1277 // FIXME: due to a lack of registers we currently blow away the age
1278 // bits in this situation. Should attempt to preserve them.
1279 NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1280 load_prototype_header(tmp_reg, obj_reg);
1281 if (os::is_MP()) {
1282 lock();
1283 }
1284 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1285 // Fall through to the normal CAS-based lock, because no matter what
1286 // the result of the above CAS, some thread must have succeeded in
1287 // removing the bias bit from the object's header.
1288 if (counters != NULL) {
1289 cond_inc32(Assembler::zero,
1290 ExternalAddress((address) counters->revoked_lock_entry_count_addr()));
1291 }
1292
1293 bind(cas_label);
1294
1295 return null_check_offset;
1296 }
1297
1298 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) {
1299 assert(UseBiasedLocking, "why call this otherwise?");
1300
1301 // Check for biased locking unlock case, which is a no-op
1302 // Note: we do not have to check the thread ID for two reasons.
1303 // First, the interpreter checks for IllegalMonitorStateException at
1304 // a higher level. Second, if the bias was revoked while we held the
1305 // lock, the object could not be rebiased toward another thread, so
1306 // the bias bit would be clear.
1307 movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
1308 andptr(temp_reg, markOopDesc::biased_lock_mask_in_place);
1309 cmpptr(temp_reg, markOopDesc::biased_lock_pattern);
1310 jcc(Assembler::equal, done);
1311 }
1312
1313 #ifdef COMPILER2
1314
1315 #if INCLUDE_RTM_OPT
1316
1317 // Update rtm_counters based on abort status
1318 // input: abort_status
1319 // rtm_counters (RTMLockingCounters*)
1320 // flags are killed
1321 void MacroAssembler::rtm_counters_update(Register abort_status, Register rtm_counters) {
1322
1323 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abort_count_offset()));
1324 if (PrintPreciseRTMLockingStatistics) {
1325 for (int i = 0; i < RTMLockingCounters::ABORT_STATUS_LIMIT; i++) {
1326 Label check_abort;
1327 testl(abort_status, (1<<i));
1328 jccb(Assembler::equal, check_abort);
1329 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abortX_count_offset() + (i * sizeof(uintx))));
1330 bind(check_abort);
1331 }
1332 }
1333 }
1334
1335 // Branch if (random & (count-1) != 0), count is 2^n
1336 // tmp, scr and flags are killed
1337 void MacroAssembler::branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel) {
1338 assert(tmp == rax, "");
1339 assert(scr == rdx, "");
1340 rdtsc(); // modifies EDX:EAX
1341 andptr(tmp, count-1);
1342 jccb(Assembler::notZero, brLabel);
1343 }
1344
1345 // Perform abort ratio calculation, set no_rtm bit if high ratio
1346 // input: rtm_counters_Reg (RTMLockingCounters* address)
1347 // tmpReg, rtm_counters_Reg and flags are killed
1348 void MacroAssembler::rtm_abort_ratio_calculation(Register tmpReg,
1349 Register rtm_counters_Reg,
1350 RTMLockingCounters* rtm_counters,
1351 Metadata* method_data) {
1352 Label L_done, L_check_always_rtm1, L_check_always_rtm2;
1353
1354 if (RTMLockingCalculationDelay > 0) {
1355 // Delay calculation
1356 movptr(tmpReg, ExternalAddress((address) RTMLockingCounters::rtm_calculation_flag_addr()), tmpReg);
1357 testptr(tmpReg, tmpReg);
1358 jccb(Assembler::equal, L_done);
1359 }
1360 // Abort ratio calculation only if abort_count > RTMAbortThreshold
1361 // Aborted transactions = abort_count * 100
1362 // All transactions = total_count * RTMTotalCountIncrRate
1363 // Set no_rtm bit if (Aborted transactions >= All transactions * RTMAbortRatio)
1364
1365 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::abort_count_offset()));
1366 cmpptr(tmpReg, RTMAbortThreshold);
1367 jccb(Assembler::below, L_check_always_rtm2);
1368 imulptr(tmpReg, tmpReg, 100);
1369
1370 Register scrReg = rtm_counters_Reg;
1371 movptr(scrReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1372 imulptr(scrReg, scrReg, RTMTotalCountIncrRate);
1373 imulptr(scrReg, scrReg, RTMAbortRatio);
1374 cmpptr(tmpReg, scrReg);
1375 jccb(Assembler::below, L_check_always_rtm1);
1376 if (method_data != NULL) {
1377 // set rtm_state to "no rtm" in MDO
1378 mov_metadata(tmpReg, method_data);
1379 if (os::is_MP()) {
1380 lock();
1381 }
1382 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), NoRTM);
1383 }
1384 jmpb(L_done);
1385 bind(L_check_always_rtm1);
1386 // Reload RTMLockingCounters* address
1387 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1388 bind(L_check_always_rtm2);
1389 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1390 cmpptr(tmpReg, RTMLockingThreshold / RTMTotalCountIncrRate);
1391 jccb(Assembler::below, L_done);
1392 if (method_data != NULL) {
1393 // set rtm_state to "always rtm" in MDO
1394 mov_metadata(tmpReg, method_data);
1395 if (os::is_MP()) {
1396 lock();
1397 }
1398 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), UseRTM);
1399 }
1400 bind(L_done);
1401 }
1402
1403 // Update counters and perform abort ratio calculation
1404 // input: abort_status_Reg
1405 // rtm_counters_Reg, flags are killed
1406 void MacroAssembler::rtm_profiling(Register abort_status_Reg,
1407 Register rtm_counters_Reg,
1408 RTMLockingCounters* rtm_counters,
1409 Metadata* method_data,
1410 bool profile_rtm) {
1411
1412 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1413 // update rtm counters based on rax value at abort
1414 // reads abort_status_Reg, updates flags
1415 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1416 rtm_counters_update(abort_status_Reg, rtm_counters_Reg);
1417 if (profile_rtm) {
1418 // Save abort status because abort_status_Reg is used by following code.
1419 if (RTMRetryCount > 0) {
1420 push(abort_status_Reg);
1421 }
1422 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1423 rtm_abort_ratio_calculation(abort_status_Reg, rtm_counters_Reg, rtm_counters, method_data);
1424 // restore abort status
1425 if (RTMRetryCount > 0) {
1426 pop(abort_status_Reg);
1427 }
1428 }
1429 }
1430
1431 // Retry on abort if abort's status is 0x6: can retry (0x2) | memory conflict (0x4)
1432 // inputs: retry_count_Reg
1433 // : abort_status_Reg
1434 // output: retry_count_Reg decremented by 1
1435 // flags are killed
1436 void MacroAssembler::rtm_retry_lock_on_abort(Register retry_count_Reg, Register abort_status_Reg, Label& retryLabel) {
1437 Label doneRetry;
1438 assert(abort_status_Reg == rax, "");
1439 // The abort reason bits are in eax (see all states in rtmLocking.hpp)
1440 // 0x6 = conflict on which we can retry (0x2) | memory conflict (0x4)
1441 // if reason is in 0x6 and retry count != 0 then retry
1442 andptr(abort_status_Reg, 0x6);
1443 jccb(Assembler::zero, doneRetry);
1444 testl(retry_count_Reg, retry_count_Reg);
1445 jccb(Assembler::zero, doneRetry);
1446 pause();
1447 decrementl(retry_count_Reg);
1448 jmp(retryLabel);
1449 bind(doneRetry);
1450 }
1451
1452 // Spin and retry if lock is busy,
1453 // inputs: box_Reg (monitor address)
1454 // : retry_count_Reg
1455 // output: retry_count_Reg decremented by 1
1456 // : clear z flag if retry count exceeded
1457 // tmp_Reg, scr_Reg, flags are killed
1458 void MacroAssembler::rtm_retry_lock_on_busy(Register retry_count_Reg, Register box_Reg,
1459 Register tmp_Reg, Register scr_Reg, Label& retryLabel) {
1460 Label SpinLoop, SpinExit, doneRetry;
1461 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1462
1463 testl(retry_count_Reg, retry_count_Reg);
1464 jccb(Assembler::zero, doneRetry);
1465 decrementl(retry_count_Reg);
1466 movptr(scr_Reg, RTMSpinLoopCount);
1467
1468 bind(SpinLoop);
1469 pause();
1470 decrementl(scr_Reg);
1471 jccb(Assembler::lessEqual, SpinExit);
1472 movptr(tmp_Reg, Address(box_Reg, owner_offset));
1473 testptr(tmp_Reg, tmp_Reg);
1474 jccb(Assembler::notZero, SpinLoop);
1475
1476 bind(SpinExit);
1477 jmp(retryLabel);
1478 bind(doneRetry);
1479 incrementl(retry_count_Reg); // clear z flag
1480 }
1481
1482 // Use RTM for normal stack locks
1483 // Input: objReg (object to lock)
1484 void MacroAssembler::rtm_stack_locking(Register objReg, Register tmpReg, Register scrReg,
1485 Register retry_on_abort_count_Reg,
1486 RTMLockingCounters* stack_rtm_counters,
1487 Metadata* method_data, bool profile_rtm,
1488 Label& DONE_LABEL, Label& IsInflated) {
1489 assert(UseRTMForStackLocks, "why call this otherwise?");
1490 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
1491 assert(tmpReg == rax, "");
1492 assert(scrReg == rdx, "");
1493 Label L_rtm_retry, L_decrement_retry, L_on_abort;
1494
1495 if (RTMRetryCount > 0) {
1496 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1497 bind(L_rtm_retry);
1498 }
1499 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes()));
1500 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased
1501 jcc(Assembler::notZero, IsInflated);
1502
1503 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1504 Label L_noincrement;
1505 if (RTMTotalCountIncrRate > 1) {
1506 // tmpReg, scrReg and flags are killed
1507 branch_on_random_using_rdtsc(tmpReg, scrReg, RTMTotalCountIncrRate, L_noincrement);
1508 }
1509 assert(stack_rtm_counters != NULL, "should not be NULL when profiling RTM");
1510 atomic_incptr(ExternalAddress((address)stack_rtm_counters->total_count_addr()), scrReg);
1511 bind(L_noincrement);
1512 }
1513 xbegin(L_on_abort);
1514 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // fetch markword
1515 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
1516 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked
1517 jcc(Assembler::equal, DONE_LABEL); // all done if unlocked
1518
1519 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1520 if (UseRTMXendForLockBusy) {
1521 xend();
1522 movptr(abort_status_Reg, 0x2); // Set the abort status to 2 (so we can retry)
1523 jmp(L_decrement_retry);
1524 }
1525 else {
1526 xabort(0);
1527 }
1528 bind(L_on_abort);
1529 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1530 rtm_profiling(abort_status_Reg, scrReg, stack_rtm_counters, method_data, profile_rtm);
1531 }
1532 bind(L_decrement_retry);
1533 if (RTMRetryCount > 0) {
1534 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1535 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1536 }
1537 }
1538
1539 // Use RTM for inflating locks
1540 // inputs: objReg (object to lock)
1541 // boxReg (on-stack box address (displaced header location) - KILLED)
1542 // tmpReg (ObjectMonitor address + markOopDesc::monitor_value)
1543 void MacroAssembler::rtm_inflated_locking(Register objReg, Register boxReg, Register tmpReg,
1544 Register scrReg, Register retry_on_busy_count_Reg,
1545 Register retry_on_abort_count_Reg,
1546 RTMLockingCounters* rtm_counters,
1547 Metadata* method_data, bool profile_rtm,
1548 Label& DONE_LABEL) {
1549 assert(UseRTMLocking, "why call this otherwise?");
1550 assert(tmpReg == rax, "");
1551 assert(scrReg == rdx, "");
1552 Label L_rtm_retry, L_decrement_retry, L_on_abort;
1553 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1554
1555 // Without cast to int32_t a movptr will destroy r10 which is typically obj
1556 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1557 movptr(boxReg, tmpReg); // Save ObjectMonitor address
1558
1559 if (RTMRetryCount > 0) {
1560 movl(retry_on_busy_count_Reg, RTMRetryCount); // Retry on lock busy
1561 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1562 bind(L_rtm_retry);
1563 }
1564 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1565 Label L_noincrement;
1566 if (RTMTotalCountIncrRate > 1) {
1567 // tmpReg, scrReg and flags are killed
1568 branch_on_random_using_rdtsc(tmpReg, scrReg, RTMTotalCountIncrRate, L_noincrement);
1569 }
1570 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1571 atomic_incptr(ExternalAddress((address)rtm_counters->total_count_addr()), scrReg);
1572 bind(L_noincrement);
1573 }
1574 xbegin(L_on_abort);
1575 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes()));
1576 movptr(tmpReg, Address(tmpReg, owner_offset));
1577 testptr(tmpReg, tmpReg);
1578 jcc(Assembler::zero, DONE_LABEL);
1579 if (UseRTMXendForLockBusy) {
1580 xend();
1581 jmp(L_decrement_retry);
1582 }
1583 else {
1584 xabort(0);
1585 }
1586 bind(L_on_abort);
1587 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1588 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1589 rtm_profiling(abort_status_Reg, scrReg, rtm_counters, method_data, profile_rtm);
1590 }
1591 if (RTMRetryCount > 0) {
1592 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1593 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1594 }
1595
1596 movptr(tmpReg, Address(boxReg, owner_offset)) ;
1597 testptr(tmpReg, tmpReg) ;
1598 jccb(Assembler::notZero, L_decrement_retry) ;
1599
1600 // Appears unlocked - try to swing _owner from null to non-null.
1601 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1602 #ifdef _LP64
1603 Register threadReg = r15_thread;
1604 #else
1605 get_thread(scrReg);
1606 Register threadReg = scrReg;
1607 #endif
1608 if (os::is_MP()) {
1609 lock();
1610 }
1611 cmpxchgptr(threadReg, Address(boxReg, owner_offset)); // Updates tmpReg
1612
1613 if (RTMRetryCount > 0) {
1614 // success done else retry
1615 jccb(Assembler::equal, DONE_LABEL) ;
1616 bind(L_decrement_retry);
1617 // Spin and retry if lock is busy.
1618 rtm_retry_lock_on_busy(retry_on_busy_count_Reg, boxReg, tmpReg, scrReg, L_rtm_retry);
1619 }
1620 else {
1621 bind(L_decrement_retry);
1622 }
1623 }
1624
1625 #endif // INCLUDE_RTM_OPT
1626
1627 // Fast_Lock and Fast_Unlock used by C2
1628
1629 // Because the transitions from emitted code to the runtime
1630 // monitorenter/exit helper stubs are so slow it's critical that
1631 // we inline both the stack-locking fast-path and the inflated fast path.
1632 //
1633 // See also: cmpFastLock and cmpFastUnlock.
1634 //
1635 // What follows is a specialized inline transliteration of the code
1636 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
1637 // another option would be to emit TrySlowEnter and TrySlowExit methods
1638 // at startup-time. These methods would accept arguments as
1639 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
1640 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
1641 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
1642 // In practice, however, the # of lock sites is bounded and is usually small.
1643 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
1644 // if the processor uses simple bimodal branch predictors keyed by EIP
1645 // Since the helper routines would be called from multiple synchronization
1646 // sites.
1647 //
1648 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
1649 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
1650 // to those specialized methods. That'd give us a mostly platform-independent
1651 // implementation that the JITs could optimize and inline at their pleasure.
1652 // Done correctly, the only time we'd need to cross to native could would be
1653 // to park() or unpark() threads. We'd also need a few more unsafe operators
1654 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
1655 // (b) explicit barriers or fence operations.
1656 //
1657 // TODO:
1658 //
1659 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
1660 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
1661 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
1662 // the lock operators would typically be faster than reifying Self.
1663 //
1664 // * Ideally I'd define the primitives as:
1665 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
1666 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
1667 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
1668 // Instead, we're stuck with a rather awkward and brittle register assignments below.
1669 // Furthermore the register assignments are overconstrained, possibly resulting in
1670 // sub-optimal code near the synchronization site.
1671 //
1672 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
1673 // Alternately, use a better sp-proximity test.
1674 //
1675 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
1676 // Either one is sufficient to uniquely identify a thread.
1677 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
1678 //
1679 // * Intrinsify notify() and notifyAll() for the common cases where the
1680 // object is locked by the calling thread but the waitlist is empty.
1681 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
1682 //
1683 // * use jccb and jmpb instead of jcc and jmp to improve code density.
1684 // But beware of excessive branch density on AMD Opterons.
1685 //
1686 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
1687 // or failure of the fast-path. If the fast-path fails then we pass
1688 // control to the slow-path, typically in C. In Fast_Lock and
1689 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
1690 // will emit a conditional branch immediately after the node.
1691 // So we have branches to branches and lots of ICC.ZF games.
1692 // Instead, it might be better to have C2 pass a "FailureLabel"
1693 // into Fast_Lock and Fast_Unlock. In the case of success, control
1694 // will drop through the node. ICC.ZF is undefined at exit.
1695 // In the case of failure, the node will branch directly to the
1696 // FailureLabel
1697
1698
1699 // obj: object to lock
1700 // box: on-stack box address (displaced header location) - KILLED
1701 // rax,: tmp -- KILLED
1702 // scr: tmp -- KILLED
1703 void MacroAssembler::fast_lock(Register objReg, Register boxReg, Register tmpReg,
1704 Register scrReg, Register cx1Reg, Register cx2Reg,
1705 BiasedLockingCounters* counters,
1706 RTMLockingCounters* rtm_counters,
1707 RTMLockingCounters* stack_rtm_counters,
1708 Metadata* method_data,
1709 bool use_rtm, bool profile_rtm) {
1710 // Ensure the register assignments are disjoint
1711 assert(tmpReg == rax, "");
1712
1713 if (use_rtm) {
1714 assert_different_registers(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg);
1715 } else {
1716 assert(cx1Reg == noreg, "");
1717 assert(cx2Reg == noreg, "");
1718 assert_different_registers(objReg, boxReg, tmpReg, scrReg);
1719 }
1720
1721 if (counters != NULL) {
1722 atomic_incl(ExternalAddress((address)counters->total_entry_count_addr()), scrReg);
1723 }
1724 if (EmitSync & 1) {
1725 // set box->dhw = markOopDesc::unused_mark()
1726 // Force all sync thru slow-path: slow_enter() and slow_exit()
1727 movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1728 cmpptr (rsp, (int32_t)NULL_WORD);
1729 } else {
1730 // Possible cases that we'll encounter in fast_lock
1731 // ------------------------------------------------
1732 // * Inflated
1733 // -- unlocked
1734 // -- Locked
1735 // = by self
1736 // = by other
1737 // * biased
1738 // -- by Self
1739 // -- by other
1740 // * neutral
1741 // * stack-locked
1742 // -- by self
1743 // = sp-proximity test hits
1744 // = sp-proximity test generates false-negative
1745 // -- by other
1746 //
1747
1748 Label IsInflated, DONE_LABEL;
1749
1750 // it's stack-locked, biased or neutral
1751 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
1752 // order to reduce the number of conditional branches in the most common cases.
1753 // Beware -- there's a subtle invariant that fetch of the markword
1754 // at [FETCH], below, will never observe a biased encoding (*101b).
1755 // If this invariant is not held we risk exclusion (safety) failure.
1756 if (UseBiasedLocking && !UseOptoBiasInlining) {
1757 biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, counters);
1758 }
1759
1760 #if INCLUDE_RTM_OPT
1761 if (UseRTMForStackLocks && use_rtm) {
1762 rtm_stack_locking(objReg, tmpReg, scrReg, cx2Reg,
1763 stack_rtm_counters, method_data, profile_rtm,
1764 DONE_LABEL, IsInflated);
1765 }
1766 #endif // INCLUDE_RTM_OPT
1767
1768 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // [FETCH]
1769 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased
1770 jccb(Assembler::notZero, IsInflated);
1771
1772 // Attempt stack-locking ...
1773 orptr (tmpReg, markOopDesc::unlocked_value);
1774 movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
1775 if (os::is_MP()) {
1776 lock();
1777 }
1778 cmpxchgptr(boxReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Updates tmpReg
1779 if (counters != NULL) {
1780 cond_inc32(Assembler::equal,
1781 ExternalAddress((address)counters->fast_path_entry_count_addr()));
1782 }
1783 jcc(Assembler::equal, DONE_LABEL); // Success
1784
1785 // Recursive locking.
1786 // The object is stack-locked: markword contains stack pointer to BasicLock.
1787 // Locked by current thread if difference with current SP is less than one page.
1788 subptr(tmpReg, rsp);
1789 // Next instruction set ZFlag == 1 (Success) if difference is less then one page.
1790 andptr(tmpReg, (int32_t) (NOT_LP64(0xFFFFF003) LP64_ONLY(7 - os::vm_page_size())) );
1791 movptr(Address(boxReg, 0), tmpReg);
1792 if (counters != NULL) {
1793 cond_inc32(Assembler::equal,
1794 ExternalAddress((address)counters->fast_path_entry_count_addr()));
1795 }
1796 jmp(DONE_LABEL);
1797
1798 bind(IsInflated);
1799 // The object is inflated. tmpReg contains pointer to ObjectMonitor* + markOopDesc::monitor_value
1800
1801 #if INCLUDE_RTM_OPT
1802 // Use the same RTM locking code in 32- and 64-bit VM.
1803 if (use_rtm) {
1804 rtm_inflated_locking(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg,
1805 rtm_counters, method_data, profile_rtm, DONE_LABEL);
1806 } else {
1807 #endif // INCLUDE_RTM_OPT
1808
1809 #ifndef _LP64
1810 // The object is inflated.
1811
1812 // boxReg refers to the on-stack BasicLock in the current frame.
1813 // We'd like to write:
1814 // set box->_displaced_header = markOopDesc::unused_mark(). Any non-0 value suffices.
1815 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
1816 // additional latency as we have another ST in the store buffer that must drain.
1817
1818 if (EmitSync & 8192) {
1819 movptr(Address(boxReg, 0), 3); // results in ST-before-CAS penalty
1820 get_thread (scrReg);
1821 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
1822 movptr(tmpReg, NULL_WORD); // consider: xor vs mov
1823 if (os::is_MP()) {
1824 lock();
1825 }
1826 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1827 } else
1828 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
1829 // register juggle because we need tmpReg for cmpxchgptr below
1830 movptr(scrReg, boxReg);
1831 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
1832
1833 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
1834 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
1835 // prefetchw [eax + Offset(_owner)-2]
1836 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1837 }
1838
1839 if ((EmitSync & 64) == 0) {
1840 // Optimistic form: consider XORL tmpReg,tmpReg
1841 movptr(tmpReg, NULL_WORD);
1842 } else {
1843 // Can suffer RTS->RTO upgrades on shared or cold $ lines
1844 // Test-And-CAS instead of CAS
1845 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner
1846 testptr(tmpReg, tmpReg); // Locked ?
1847 jccb (Assembler::notZero, DONE_LABEL);
1848 }
1849
1850 // Appears unlocked - try to swing _owner from null to non-null.
1851 // Ideally, I'd manifest "Self" with get_thread and then attempt
1852 // to CAS the register containing Self into m->Owner.
1853 // But we don't have enough registers, so instead we can either try to CAS
1854 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
1855 // we later store "Self" into m->Owner. Transiently storing a stack address
1856 // (rsp or the address of the box) into m->owner is harmless.
1857 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1858 if (os::is_MP()) {
1859 lock();
1860 }
1861 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1862 movptr(Address(scrReg, 0), 3); // box->_displaced_header = 3
1863 // If we weren't able to swing _owner from NULL to the BasicLock
1864 // then take the slow path.
1865 jccb (Assembler::notZero, DONE_LABEL);
1866 // update _owner from BasicLock to thread
1867 get_thread (scrReg); // beware: clobbers ICCs
1868 movptr(Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), scrReg);
1869 xorptr(boxReg, boxReg); // set icc.ZFlag = 1 to indicate success
1870
1871 // If the CAS fails we can either retry or pass control to the slow-path.
1872 // We use the latter tactic.
1873 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1874 // If the CAS was successful ...
1875 // Self has acquired the lock
1876 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1877 // Intentional fall-through into DONE_LABEL ...
1878 } else {
1879 movptr(Address(boxReg, 0), intptr_t(markOopDesc::unused_mark())); // results in ST-before-CAS penalty
1880 movptr(boxReg, tmpReg);
1881
1882 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
1883 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
1884 // prefetchw [eax + Offset(_owner)-2]
1885 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1886 }
1887
1888 if ((EmitSync & 64) == 0) {
1889 // Optimistic form
1890 xorptr (tmpReg, tmpReg);
1891 } else {
1892 // Can suffer RTS->RTO upgrades on shared or cold $ lines
1893 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner
1894 testptr(tmpReg, tmpReg); // Locked ?
1895 jccb (Assembler::notZero, DONE_LABEL);
1896 }
1897
1898 // Appears unlocked - try to swing _owner from null to non-null.
1899 // Use either "Self" (in scr) or rsp as thread identity in _owner.
1900 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1901 get_thread (scrReg);
1902 if (os::is_MP()) {
1903 lock();
1904 }
1905 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1906
1907 // If the CAS fails we can either retry or pass control to the slow-path.
1908 // We use the latter tactic.
1909 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1910 // If the CAS was successful ...
1911 // Self has acquired the lock
1912 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1913 // Intentional fall-through into DONE_LABEL ...
1914 }
1915 #else // _LP64
1916 // It's inflated
1917 movq(scrReg, tmpReg);
1918 xorq(tmpReg, tmpReg);
1919
1920 if (os::is_MP()) {
1921 lock();
1922 }
1923 cmpxchgptr(r15_thread, Address(scrReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1924 // Unconditionally set box->_displaced_header = markOopDesc::unused_mark().
1925 // Without cast to int32_t movptr will destroy r10 which is typically obj.
1926 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1927 // Intentional fall-through into DONE_LABEL ...
1928 // Propagate ICC.ZF from CAS above into DONE_LABEL.
1929 #endif // _LP64
1930 #if INCLUDE_RTM_OPT
1931 } // use_rtm()
1932 #endif
1933 // DONE_LABEL is a hot target - we'd really like to place it at the
1934 // start of cache line by padding with NOPs.
1935 // See the AMD and Intel software optimization manuals for the
1936 // most efficient "long" NOP encodings.
1937 // Unfortunately none of our alignment mechanisms suffice.
1938 bind(DONE_LABEL);
1939
1940 // At DONE_LABEL the icc ZFlag is set as follows ...
1941 // Fast_Unlock uses the same protocol.
1942 // ZFlag == 1 -> Success
1943 // ZFlag == 0 -> Failure - force control through the slow-path
1944 }
1945 }
1946
1947 // obj: object to unlock
1948 // box: box address (displaced header location), killed. Must be EAX.
1949 // tmp: killed, cannot be obj nor box.
1950 //
1951 // Some commentary on balanced locking:
1952 //
1953 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
1954 // Methods that don't have provably balanced locking are forced to run in the
1955 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
1956 // The interpreter provides two properties:
1957 // I1: At return-time the interpreter automatically and quietly unlocks any
1958 // objects acquired the current activation (frame). Recall that the
1959 // interpreter maintains an on-stack list of locks currently held by
1960 // a frame.
1961 // I2: If a method attempts to unlock an object that is not held by the
1962 // the frame the interpreter throws IMSX.
1963 //
1964 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
1965 // B() doesn't have provably balanced locking so it runs in the interpreter.
1966 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
1967 // is still locked by A().
1968 //
1969 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
1970 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
1971 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
1972 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
1973 // Arguably given that the spec legislates the JNI case as undefined our implementation
1974 // could reasonably *avoid* checking owner in Fast_Unlock().
1975 // In the interest of performance we elide m->Owner==Self check in unlock.
1976 // A perfectly viable alternative is to elide the owner check except when
1977 // Xcheck:jni is enabled.
1978
1979 void MacroAssembler::fast_unlock(Register objReg, Register boxReg, Register tmpReg, bool use_rtm) {
1980 assert(boxReg == rax, "");
1981 assert_different_registers(objReg, boxReg, tmpReg);
1982
1983 if (EmitSync & 4) {
1984 // Disable - inhibit all inlining. Force control through the slow-path
1985 cmpptr (rsp, 0);
1986 } else {
1987 Label DONE_LABEL, Stacked, CheckSucc;
1988
1989 // Critically, the biased locking test must have precedence over
1990 // and appear before the (box->dhw == 0) recursive stack-lock test.
1991 if (UseBiasedLocking && !UseOptoBiasInlining) {
1992 biased_locking_exit(objReg, tmpReg, DONE_LABEL);
1993 }
1994
1995 #if INCLUDE_RTM_OPT
1996 if (UseRTMForStackLocks && use_rtm) {
1997 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
1998 Label L_regular_unlock;
1999 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // fetch markword
2000 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
2001 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked
2002 jccb(Assembler::notEqual, L_regular_unlock); // if !HLE RegularLock
2003 xend(); // otherwise end...
2004 jmp(DONE_LABEL); // ... and we're done
2005 bind(L_regular_unlock);
2006 }
2007 #endif
2008
2009 cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD); // Examine the displaced header
2010 jcc (Assembler::zero, DONE_LABEL); // 0 indicates recursive stack-lock
2011 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Examine the object's markword
2012 testptr(tmpReg, markOopDesc::monitor_value); // Inflated?
2013 jccb (Assembler::zero, Stacked);
2014
2015 // It's inflated.
2016 #if INCLUDE_RTM_OPT
2017 if (use_rtm) {
2018 Label L_regular_inflated_unlock;
2019 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
2020 movptr(boxReg, Address(tmpReg, owner_offset));
2021 testptr(boxReg, boxReg);
2022 jccb(Assembler::notZero, L_regular_inflated_unlock);
2023 xend();
2024 jmpb(DONE_LABEL);
2025 bind(L_regular_inflated_unlock);
2026 }
2027 #endif
2028
2029 // Despite our balanced locking property we still check that m->_owner == Self
2030 // as java routines or native JNI code called by this thread might
2031 // have released the lock.
2032 // Refer to the comments in synchronizer.cpp for how we might encode extra
2033 // state in _succ so we can avoid fetching EntryList|cxq.
2034 //
2035 // I'd like to add more cases in fast_lock() and fast_unlock() --
2036 // such as recursive enter and exit -- but we have to be wary of
2037 // I$ bloat, T$ effects and BP$ effects.
2038 //
2039 // If there's no contention try a 1-0 exit. That is, exit without
2040 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
2041 // we detect and recover from the race that the 1-0 exit admits.
2042 //
2043 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
2044 // before it STs null into _owner, releasing the lock. Updates
2045 // to data protected by the critical section must be visible before
2046 // we drop the lock (and thus before any other thread could acquire
2047 // the lock and observe the fields protected by the lock).
2048 // IA32's memory-model is SPO, so STs are ordered with respect to
2049 // each other and there's no need for an explicit barrier (fence).
2050 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
2051 #ifndef _LP64
2052 get_thread (boxReg);
2053 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
2054 // prefetchw [ebx + Offset(_owner)-2]
2055 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2056 }
2057
2058 // Note that we could employ various encoding schemes to reduce
2059 // the number of loads below (currently 4) to just 2 or 3.
2060 // Refer to the comments in synchronizer.cpp.
2061 // In practice the chain of fetches doesn't seem to impact performance, however.
2062 xorptr(boxReg, boxReg);
2063 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
2064 // Attempt to reduce branch density - AMD's branch predictor.
2065 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2066 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2067 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2068 jccb (Assembler::notZero, DONE_LABEL);
2069 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2070 jmpb (DONE_LABEL);
2071 } else {
2072 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2073 jccb (Assembler::notZero, DONE_LABEL);
2074 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2075 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2076 jccb (Assembler::notZero, CheckSucc);
2077 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2078 jmpb (DONE_LABEL);
2079 }
2080
2081 // The Following code fragment (EmitSync & 65536) improves the performance of
2082 // contended applications and contended synchronization microbenchmarks.
2083 // Unfortunately the emission of the code - even though not executed - causes regressions
2084 // in scimark and jetstream, evidently because of $ effects. Replacing the code
2085 // with an equal number of never-executed NOPs results in the same regression.
2086 // We leave it off by default.
2087
2088 if ((EmitSync & 65536) != 0) {
2089 Label LSuccess, LGoSlowPath ;
2090
2091 bind (CheckSucc);
2092
2093 // Optional pre-test ... it's safe to elide this
2094 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2095 jccb(Assembler::zero, LGoSlowPath);
2096
2097 // We have a classic Dekker-style idiom:
2098 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
2099 // There are a number of ways to implement the barrier:
2100 // (1) lock:andl &m->_owner, 0
2101 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
2102 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
2103 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
2104 // (2) If supported, an explicit MFENCE is appealing.
2105 // In older IA32 processors MFENCE is slower than lock:add or xchg
2106 // particularly if the write-buffer is full as might be the case if
2107 // if stores closely precede the fence or fence-equivalent instruction.
2108 // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences
2109 // as the situation has changed with Nehalem and Shanghai.
2110 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
2111 // The $lines underlying the top-of-stack should be in M-state.
2112 // The locked add instruction is serializing, of course.
2113 // (4) Use xchg, which is serializing
2114 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
2115 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
2116 // The integer condition codes will tell us if succ was 0.
2117 // Since _succ and _owner should reside in the same $line and
2118 // we just stored into _owner, it's likely that the $line
2119 // remains in M-state for the lock:orl.
2120 //
2121 // We currently use (3), although it's likely that switching to (2)
2122 // is correct for the future.
2123
2124 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2125 if (os::is_MP()) {
2126 lock(); addptr(Address(rsp, 0), 0);
2127 }
2128 // Ratify _succ remains non-null
2129 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), 0);
2130 jccb (Assembler::notZero, LSuccess);
2131
2132 xorptr(boxReg, boxReg); // box is really EAX
2133 if (os::is_MP()) { lock(); }
2134 cmpxchgptr(rsp, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2135 // There's no successor so we tried to regrab the lock with the
2136 // placeholder value. If that didn't work, then another thread
2137 // grabbed the lock so we're done (and exit was a success).
2138 jccb (Assembler::notEqual, LSuccess);
2139 // Since we're low on registers we installed rsp as a placeholding in _owner.
2140 // Now install Self over rsp. This is safe as we're transitioning from
2141 // non-null to non=null
2142 get_thread (boxReg);
2143 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), boxReg);
2144 // Intentional fall-through into LGoSlowPath ...
2145
2146 bind (LGoSlowPath);
2147 orptr(boxReg, 1); // set ICC.ZF=0 to indicate failure
2148 jmpb (DONE_LABEL);
2149
2150 bind (LSuccess);
2151 xorptr(boxReg, boxReg); // set ICC.ZF=1 to indicate success
2152 jmpb (DONE_LABEL);
2153 }
2154
2155 bind (Stacked);
2156 // It's not inflated and it's not recursively stack-locked and it's not biased.
2157 // It must be stack-locked.
2158 // Try to reset the header to displaced header.
2159 // The "box" value on the stack is stable, so we can reload
2160 // and be assured we observe the same value as above.
2161 movptr(tmpReg, Address(boxReg, 0));
2162 if (os::is_MP()) {
2163 lock();
2164 }
2165 cmpxchgptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Uses RAX which is box
2166 // Intention fall-thru into DONE_LABEL
2167
2168 // DONE_LABEL is a hot target - we'd really like to place it at the
2169 // start of cache line by padding with NOPs.
2170 // See the AMD and Intel software optimization manuals for the
2171 // most efficient "long" NOP encodings.
2172 // Unfortunately none of our alignment mechanisms suffice.
2173 if ((EmitSync & 65536) == 0) {
2174 bind (CheckSucc);
2175 }
2176 #else // _LP64
2177 // It's inflated
2178 if (EmitSync & 1024) {
2179 // Emit code to check that _owner == Self
2180 // We could fold the _owner test into subsequent code more efficiently
2181 // than using a stand-alone check, but since _owner checking is off by
2182 // default we don't bother. We also might consider predicating the
2183 // _owner==Self check on Xcheck:jni or running on a debug build.
2184 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2185 xorptr(boxReg, r15_thread);
2186 } else {
2187 xorptr(boxReg, boxReg);
2188 }
2189 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2190 jccb (Assembler::notZero, DONE_LABEL);
2191 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2192 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2193 jccb (Assembler::notZero, CheckSucc);
2194 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD);
2195 jmpb (DONE_LABEL);
2196
2197 if ((EmitSync & 65536) == 0) {
2198 // Try to avoid passing control into the slow_path ...
2199 Label LSuccess, LGoSlowPath ;
2200 bind (CheckSucc);
2201
2202 // The following optional optimization can be elided if necessary
2203 // Effectively: if (succ == null) goto SlowPath
2204 // The code reduces the window for a race, however,
2205 // and thus benefits performance.
2206 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2207 jccb (Assembler::zero, LGoSlowPath);
2208
2209 xorptr(boxReg, boxReg);
2210 if ((EmitSync & 16) && os::is_MP()) {
2211 xchgptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2212 } else {
2213 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD);
2214 if (os::is_MP()) {
2215 // Memory barrier/fence
2216 // Dekker pivot point -- fulcrum : ST Owner; MEMBAR; LD Succ
2217 // Instead of MFENCE we use a dummy locked add of 0 to the top-of-stack.
2218 // This is faster on Nehalem and AMD Shanghai/Barcelona.
2219 // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences
2220 // We might also restructure (ST Owner=0;barrier;LD _Succ) to
2221 // (mov box,0; xchgq box, &m->Owner; LD _succ) .
2222 lock(); addl(Address(rsp, 0), 0);
2223 }
2224 }
2225 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2226 jccb (Assembler::notZero, LSuccess);
2227
2228 // Rare inopportune interleaving - race.
2229 // The successor vanished in the small window above.
2230 // The lock is contended -- (cxq|EntryList) != null -- and there's no apparent successor.
2231 // We need to ensure progress and succession.
2232 // Try to reacquire the lock.
2233 // If that fails then the new owner is responsible for succession and this
2234 // thread needs to take no further action and can exit via the fast path (success).
2235 // If the re-acquire succeeds then pass control into the slow path.
2236 // As implemented, this latter mode is horrible because we generated more
2237 // coherence traffic on the lock *and* artifically extended the critical section
2238 // length while by virtue of passing control into the slow path.
2239
2240 // box is really RAX -- the following CMPXCHG depends on that binding
2241 // cmpxchg R,[M] is equivalent to rax = CAS(M,rax,R)
2242 if (os::is_MP()) { lock(); }
2243 cmpxchgptr(r15_thread, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2244 // There's no successor so we tried to regrab the lock.
2245 // If that didn't work, then another thread grabbed the
2246 // lock so we're done (and exit was a success).
2247 jccb (Assembler::notEqual, LSuccess);
2248 // Intentional fall-through into slow-path
2249
2250 bind (LGoSlowPath);
2251 orl (boxReg, 1); // set ICC.ZF=0 to indicate failure
2252 jmpb (DONE_LABEL);
2253
2254 bind (LSuccess);
2255 testl (boxReg, 0); // set ICC.ZF=1 to indicate success
2256 jmpb (DONE_LABEL);
2257 }
2258
2259 bind (Stacked);
2260 movptr(tmpReg, Address (boxReg, 0)); // re-fetch
2261 if (os::is_MP()) { lock(); }
2262 cmpxchgptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Uses RAX which is box
2263
2264 if (EmitSync & 65536) {
2265 bind (CheckSucc);
2266 }
2267 #endif
2268 bind(DONE_LABEL);
2269 }
2270 }
2271 #endif // COMPILER2
2272
2273 void MacroAssembler::c2bool(Register x) {
2274 // implements x == 0 ? 0 : 1
2275 // note: must only look at least-significant byte of x
2276 // since C-style booleans are stored in one byte
2277 // only! (was bug)
2278 andl(x, 0xFF);
2279 setb(Assembler::notZero, x);
2280 }
2281
2282 // Wouldn't need if AddressLiteral version had new name
2283 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
2284 Assembler::call(L, rtype);
2285 }
2286
2287 void MacroAssembler::call(Register entry) {
2288 Assembler::call(entry);
2289 }
2290
2291 void MacroAssembler::call(AddressLiteral entry) {
2292 if (reachable(entry)) {
2293 Assembler::call_literal(entry.target(), entry.rspec());
2294 } else {
2295 lea(rscratch1, entry);
2296 Assembler::call(rscratch1);
2297 }
2298 }
2299
2300 void MacroAssembler::ic_call(address entry, jint method_index) {
2301 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
2302 movptr(rax, (intptr_t)Universe::non_oop_word());
2303 call(AddressLiteral(entry, rh));
2304 }
2305
2306 // Implementation of call_VM versions
2307
2308 void MacroAssembler::call_VM(Register oop_result,
2309 address entry_point,
2310 bool check_exceptions) {
2311 Label C, E;
2312 call(C, relocInfo::none);
2313 jmp(E);
2314
2315 bind(C);
2316 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
2317 ret(0);
2318
2319 bind(E);
2320 }
2321
2322 void MacroAssembler::call_VM(Register oop_result,
2323 address entry_point,
2324 Register arg_1,
2325 bool check_exceptions) {
2326 Label C, E;
2327 call(C, relocInfo::none);
2328 jmp(E);
2329
2330 bind(C);
2331 pass_arg1(this, arg_1);
2332 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
2333 ret(0);
2334
2335 bind(E);
2336 }
2337
2338 void MacroAssembler::call_VM(Register oop_result,
2339 address entry_point,
2340 Register arg_1,
2341 Register arg_2,
2342 bool check_exceptions) {
2343 Label C, E;
2344 call(C, relocInfo::none);
2345 jmp(E);
2346
2347 bind(C);
2348
2349 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2350
2351 pass_arg2(this, arg_2);
2352 pass_arg1(this, arg_1);
2353 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
2354 ret(0);
2355
2356 bind(E);
2357 }
2358
2359 void MacroAssembler::call_VM(Register oop_result,
2360 address entry_point,
2361 Register arg_1,
2362 Register arg_2,
2363 Register arg_3,
2364 bool check_exceptions) {
2365 Label C, E;
2366 call(C, relocInfo::none);
2367 jmp(E);
2368
2369 bind(C);
2370
2371 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2372 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2373 pass_arg3(this, arg_3);
2374
2375 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2376 pass_arg2(this, arg_2);
2377
2378 pass_arg1(this, arg_1);
2379 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
2380 ret(0);
2381
2382 bind(E);
2383 }
2384
2385 void MacroAssembler::call_VM(Register oop_result,
2386 Register last_java_sp,
2387 address entry_point,
2388 int number_of_arguments,
2389 bool check_exceptions) {
2390 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2391 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2392 }
2393
2394 void MacroAssembler::call_VM(Register oop_result,
2395 Register last_java_sp,
2396 address entry_point,
2397 Register arg_1,
2398 bool check_exceptions) {
2399 pass_arg1(this, arg_1);
2400 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2401 }
2402
2403 void MacroAssembler::call_VM(Register oop_result,
2404 Register last_java_sp,
2405 address entry_point,
2406 Register arg_1,
2407 Register arg_2,
2408 bool check_exceptions) {
2409
2410 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2411 pass_arg2(this, arg_2);
2412 pass_arg1(this, arg_1);
2413 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2414 }
2415
2416 void MacroAssembler::call_VM(Register oop_result,
2417 Register last_java_sp,
2418 address entry_point,
2419 Register arg_1,
2420 Register arg_2,
2421 Register arg_3,
2422 bool check_exceptions) {
2423 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2424 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2425 pass_arg3(this, arg_3);
2426 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2427 pass_arg2(this, arg_2);
2428 pass_arg1(this, arg_1);
2429 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2430 }
2431
2432 void MacroAssembler::super_call_VM(Register oop_result,
2433 Register last_java_sp,
2434 address entry_point,
2435 int number_of_arguments,
2436 bool check_exceptions) {
2437 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2438 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2439 }
2440
2441 void MacroAssembler::super_call_VM(Register oop_result,
2442 Register last_java_sp,
2443 address entry_point,
2444 Register arg_1,
2445 bool check_exceptions) {
2446 pass_arg1(this, arg_1);
2447 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2448 }
2449
2450 void MacroAssembler::super_call_VM(Register oop_result,
2451 Register last_java_sp,
2452 address entry_point,
2453 Register arg_1,
2454 Register arg_2,
2455 bool check_exceptions) {
2456
2457 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2458 pass_arg2(this, arg_2);
2459 pass_arg1(this, arg_1);
2460 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2461 }
2462
2463 void MacroAssembler::super_call_VM(Register oop_result,
2464 Register last_java_sp,
2465 address entry_point,
2466 Register arg_1,
2467 Register arg_2,
2468 Register arg_3,
2469 bool check_exceptions) {
2470 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2471 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2472 pass_arg3(this, arg_3);
2473 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2474 pass_arg2(this, arg_2);
2475 pass_arg1(this, arg_1);
2476 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2477 }
2478
2479 void MacroAssembler::call_VM_base(Register oop_result,
2480 Register java_thread,
2481 Register last_java_sp,
2482 address entry_point,
2483 int number_of_arguments,
2484 bool check_exceptions) {
2485 // determine java_thread register
2486 if (!java_thread->is_valid()) {
2487 #ifdef _LP64
2488 java_thread = r15_thread;
2489 #else
2490 java_thread = rdi;
2491 get_thread(java_thread);
2492 #endif // LP64
2493 }
2494 // determine last_java_sp register
2495 if (!last_java_sp->is_valid()) {
2496 last_java_sp = rsp;
2497 }
2498 // debugging support
2499 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
2500 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
2501 #ifdef ASSERT
2502 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
2503 // r12 is the heapbase.
2504 LP64_ONLY(if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");)
2505 #endif // ASSERT
2506
2507 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
2508 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
2509
2510 // push java thread (becomes first argument of C function)
2511
2512 NOT_LP64(push(java_thread); number_of_arguments++);
2513 LP64_ONLY(mov(c_rarg0, r15_thread));
2514
2515 // set last Java frame before call
2516 assert(last_java_sp != rbp, "can't use ebp/rbp");
2517
2518 // Only interpreter should have to set fp
2519 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL);
2520
2521 // do the call, remove parameters
2522 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
2523
2524 // restore the thread (cannot use the pushed argument since arguments
2525 // may be overwritten by C code generated by an optimizing compiler);
2526 // however can use the register value directly if it is callee saved.
2527 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
2528 // rdi & rsi (also r15) are callee saved -> nothing to do
2529 #ifdef ASSERT
2530 guarantee(java_thread != rax, "change this code");
2531 push(rax);
2532 { Label L;
2533 get_thread(rax);
2534 cmpptr(java_thread, rax);
2535 jcc(Assembler::equal, L);
2536 STOP("MacroAssembler::call_VM_base: rdi not callee saved?");
2537 bind(L);
2538 }
2539 pop(rax);
2540 #endif
2541 } else {
2542 get_thread(java_thread);
2543 }
2544 // reset last Java frame
2545 // Only interpreter should have to clear fp
2546 reset_last_Java_frame(java_thread, true);
2547
2548 // C++ interp handles this in the interpreter
2549 check_and_handle_popframe(java_thread);
2550 check_and_handle_earlyret(java_thread);
2551
2552 if (check_exceptions) {
2553 // check for pending exceptions (java_thread is set upon return)
2554 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD);
2555 #ifndef _LP64
2556 jump_cc(Assembler::notEqual,
2557 RuntimeAddress(StubRoutines::forward_exception_entry()));
2558 #else
2559 // This used to conditionally jump to forward_exception however it is
2560 // possible if we relocate that the branch will not reach. So we must jump
2561 // around so we can always reach
2562
2563 Label ok;
2564 jcc(Assembler::equal, ok);
2565 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
2566 bind(ok);
2567 #endif // LP64
2568 }
2569
2570 // get oop result if there is one and reset the value in the thread
2571 if (oop_result->is_valid()) {
2572 get_vm_result(oop_result, java_thread);
2573 }
2574 }
2575
2576 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
2577
2578 // Calculate the value for last_Java_sp
2579 // somewhat subtle. call_VM does an intermediate call
2580 // which places a return address on the stack just under the
2581 // stack pointer as the user finsihed with it. This allows
2582 // use to retrieve last_Java_pc from last_Java_sp[-1].
2583 // On 32bit we then have to push additional args on the stack to accomplish
2584 // the actual requested call. On 64bit call_VM only can use register args
2585 // so the only extra space is the return address that call_VM created.
2586 // This hopefully explains the calculations here.
2587
2588 #ifdef _LP64
2589 // We've pushed one address, correct last_Java_sp
2590 lea(rax, Address(rsp, wordSize));
2591 #else
2592 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
2593 #endif // LP64
2594
2595 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
2596
2597 }
2598
2599 // Use this method when MacroAssembler version of call_VM_leaf_base() should be called from Interpreter.
2600 void MacroAssembler::call_VM_leaf0(address entry_point) {
2601 MacroAssembler::call_VM_leaf_base(entry_point, 0);
2602 }
2603
2604 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
2605 call_VM_leaf_base(entry_point, number_of_arguments);
2606 }
2607
2608 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
2609 pass_arg0(this, arg_0);
2610 call_VM_leaf(entry_point, 1);
2611 }
2612
2613 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2614
2615 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2616 pass_arg1(this, arg_1);
2617 pass_arg0(this, arg_0);
2618 call_VM_leaf(entry_point, 2);
2619 }
2620
2621 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2622 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2623 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2624 pass_arg2(this, arg_2);
2625 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2626 pass_arg1(this, arg_1);
2627 pass_arg0(this, arg_0);
2628 call_VM_leaf(entry_point, 3);
2629 }
2630
2631 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
2632 pass_arg0(this, arg_0);
2633 MacroAssembler::call_VM_leaf_base(entry_point, 1);
2634 }
2635
2636 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2637
2638 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2639 pass_arg1(this, arg_1);
2640 pass_arg0(this, arg_0);
2641 MacroAssembler::call_VM_leaf_base(entry_point, 2);
2642 }
2643
2644 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2645 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2646 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2647 pass_arg2(this, arg_2);
2648 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2649 pass_arg1(this, arg_1);
2650 pass_arg0(this, arg_0);
2651 MacroAssembler::call_VM_leaf_base(entry_point, 3);
2652 }
2653
2654 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
2655 LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg"));
2656 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2657 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2658 pass_arg3(this, arg_3);
2659 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2660 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2661 pass_arg2(this, arg_2);
2662 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2663 pass_arg1(this, arg_1);
2664 pass_arg0(this, arg_0);
2665 MacroAssembler::call_VM_leaf_base(entry_point, 4);
2666 }
2667
2668 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
2669 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
2670 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
2671 verify_oop(oop_result, "broken oop in call_VM_base");
2672 }
2673
2674 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
2675 movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
2676 movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD);
2677 }
2678
2679 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
2680 }
2681
2682 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
2683 }
2684
2685 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) {
2686 if (reachable(src1)) {
2687 cmpl(as_Address(src1), imm);
2688 } else {
2689 lea(rscratch1, src1);
2690 cmpl(Address(rscratch1, 0), imm);
2691 }
2692 }
2693
2694 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) {
2695 assert(!src2.is_lval(), "use cmpptr");
2696 if (reachable(src2)) {
2697 cmpl(src1, as_Address(src2));
2698 } else {
2699 lea(rscratch1, src2);
2700 cmpl(src1, Address(rscratch1, 0));
2701 }
2702 }
2703
2704 void MacroAssembler::cmp32(Register src1, int32_t imm) {
2705 Assembler::cmpl(src1, imm);
2706 }
2707
2708 void MacroAssembler::cmp32(Register src1, Address src2) {
2709 Assembler::cmpl(src1, src2);
2710 }
2711
2712 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2713 ucomisd(opr1, opr2);
2714
2715 Label L;
2716 if (unordered_is_less) {
2717 movl(dst, -1);
2718 jcc(Assembler::parity, L);
2719 jcc(Assembler::below , L);
2720 movl(dst, 0);
2721 jcc(Assembler::equal , L);
2722 increment(dst);
2723 } else { // unordered is greater
2724 movl(dst, 1);
2725 jcc(Assembler::parity, L);
2726 jcc(Assembler::above , L);
2727 movl(dst, 0);
2728 jcc(Assembler::equal , L);
2729 decrementl(dst);
2730 }
2731 bind(L);
2732 }
2733
2734 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2735 ucomiss(opr1, opr2);
2736
2737 Label L;
2738 if (unordered_is_less) {
2739 movl(dst, -1);
2740 jcc(Assembler::parity, L);
2741 jcc(Assembler::below , L);
2742 movl(dst, 0);
2743 jcc(Assembler::equal , L);
2744 increment(dst);
2745 } else { // unordered is greater
2746 movl(dst, 1);
2747 jcc(Assembler::parity, L);
2748 jcc(Assembler::above , L);
2749 movl(dst, 0);
2750 jcc(Assembler::equal , L);
2751 decrementl(dst);
2752 }
2753 bind(L);
2754 }
2755
2756
2757 void MacroAssembler::cmp8(AddressLiteral src1, int imm) {
2758 if (reachable(src1)) {
2759 cmpb(as_Address(src1), imm);
2760 } else {
2761 lea(rscratch1, src1);
2762 cmpb(Address(rscratch1, 0), imm);
2763 }
2764 }
2765
2766 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) {
2767 #ifdef _LP64
2768 if (src2.is_lval()) {
2769 movptr(rscratch1, src2);
2770 Assembler::cmpq(src1, rscratch1);
2771 } else if (reachable(src2)) {
2772 cmpq(src1, as_Address(src2));
2773 } else {
2774 lea(rscratch1, src2);
2775 Assembler::cmpq(src1, Address(rscratch1, 0));
2776 }
2777 #else
2778 if (src2.is_lval()) {
2779 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2780 } else {
2781 cmpl(src1, as_Address(src2));
2782 }
2783 #endif // _LP64
2784 }
2785
2786 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) {
2787 assert(src2.is_lval(), "not a mem-mem compare");
2788 #ifdef _LP64
2789 // moves src2's literal address
2790 movptr(rscratch1, src2);
2791 Assembler::cmpq(src1, rscratch1);
2792 #else
2793 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2794 #endif // _LP64
2795 }
2796
2797 void MacroAssembler::cmpoop(Register src1, Register src2) {
2798 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
2799 bs->obj_equals(this, src1, src2);
2800 }
2801
2802 void MacroAssembler::cmpoop(Register src1, Address src2) {
2803 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
2804 bs->obj_equals(this, src1, src2);
2805 }
2806
2807 #ifdef _LP64
2808 void MacroAssembler::cmpoop(Register src1, jobject src2) {
2809 movoop(rscratch1, src2);
2810 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
2811 bs->obj_equals(this, src1, rscratch1);
2812 }
2813 #endif
2814
2815 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) {
2816 if (reachable(adr)) {
2817 if (os::is_MP())
2818 lock();
2819 cmpxchgptr(reg, as_Address(adr));
2820 } else {
2821 lea(rscratch1, adr);
2822 if (os::is_MP())
2823 lock();
2824 cmpxchgptr(reg, Address(rscratch1, 0));
2825 }
2826 }
2827
2828 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
2829 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
2830 }
2831
2832 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) {
2833 if (reachable(src)) {
2834 Assembler::comisd(dst, as_Address(src));
2835 } else {
2836 lea(rscratch1, src);
2837 Assembler::comisd(dst, Address(rscratch1, 0));
2838 }
2839 }
2840
2841 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) {
2842 if (reachable(src)) {
2843 Assembler::comiss(dst, as_Address(src));
2844 } else {
2845 lea(rscratch1, src);
2846 Assembler::comiss(dst, Address(rscratch1, 0));
2847 }
2848 }
2849
2850
2851 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) {
2852 Condition negated_cond = negate_condition(cond);
2853 Label L;
2854 jcc(negated_cond, L);
2855 pushf(); // Preserve flags
2856 atomic_incl(counter_addr);
2857 popf();
2858 bind(L);
2859 }
2860
2861 int MacroAssembler::corrected_idivl(Register reg) {
2862 // Full implementation of Java idiv and irem; checks for
2863 // special case as described in JVM spec., p.243 & p.271.
2864 // The function returns the (pc) offset of the idivl
2865 // instruction - may be needed for implicit exceptions.
2866 //
2867 // normal case special case
2868 //
2869 // input : rax,: dividend min_int
2870 // reg: divisor (may not be rax,/rdx) -1
2871 //
2872 // output: rax,: quotient (= rax, idiv reg) min_int
2873 // rdx: remainder (= rax, irem reg) 0
2874 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
2875 const int min_int = 0x80000000;
2876 Label normal_case, special_case;
2877
2878 // check for special case
2879 cmpl(rax, min_int);
2880 jcc(Assembler::notEqual, normal_case);
2881 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
2882 cmpl(reg, -1);
2883 jcc(Assembler::equal, special_case);
2884
2885 // handle normal case
2886 bind(normal_case);
2887 cdql();
2888 int idivl_offset = offset();
2889 idivl(reg);
2890
2891 // normal and special case exit
2892 bind(special_case);
2893
2894 return idivl_offset;
2895 }
2896
2897
2898
2899 void MacroAssembler::decrementl(Register reg, int value) {
2900 if (value == min_jint) {subl(reg, value) ; return; }
2901 if (value < 0) { incrementl(reg, -value); return; }
2902 if (value == 0) { ; return; }
2903 if (value == 1 && UseIncDec) { decl(reg) ; return; }
2904 /* else */ { subl(reg, value) ; return; }
2905 }
2906
2907 void MacroAssembler::decrementl(Address dst, int value) {
2908 if (value == min_jint) {subl(dst, value) ; return; }
2909 if (value < 0) { incrementl(dst, -value); return; }
2910 if (value == 0) { ; return; }
2911 if (value == 1 && UseIncDec) { decl(dst) ; return; }
2912 /* else */ { subl(dst, value) ; return; }
2913 }
2914
2915 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
2916 assert (shift_value > 0, "illegal shift value");
2917 Label _is_positive;
2918 testl (reg, reg);
2919 jcc (Assembler::positive, _is_positive);
2920 int offset = (1 << shift_value) - 1 ;
2921
2922 if (offset == 1) {
2923 incrementl(reg);
2924 } else {
2925 addl(reg, offset);
2926 }
2927
2928 bind (_is_positive);
2929 sarl(reg, shift_value);
2930 }
2931
2932 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) {
2933 if (reachable(src)) {
2934 Assembler::divsd(dst, as_Address(src));
2935 } else {
2936 lea(rscratch1, src);
2937 Assembler::divsd(dst, Address(rscratch1, 0));
2938 }
2939 }
2940
2941 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) {
2942 if (reachable(src)) {
2943 Assembler::divss(dst, as_Address(src));
2944 } else {
2945 lea(rscratch1, src);
2946 Assembler::divss(dst, Address(rscratch1, 0));
2947 }
2948 }
2949
2950 // !defined(COMPILER2) is because of stupid core builds
2951 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2) || INCLUDE_JVMCI
2952 void MacroAssembler::empty_FPU_stack() {
2953 if (VM_Version::supports_mmx()) {
2954 emms();
2955 } else {
2956 for (int i = 8; i-- > 0; ) ffree(i);
2957 }
2958 }
2959 #endif // !LP64 || C1 || !C2 || INCLUDE_JVMCI
2960
2961
2962 void MacroAssembler::enter() {
2963 push(rbp);
2964 mov(rbp, rsp);
2965 }
2966
2967 // A 5 byte nop that is safe for patching (see patch_verified_entry)
2968 void MacroAssembler::fat_nop() {
2969 if (UseAddressNop) {
2970 addr_nop_5();
2971 } else {
2972 emit_int8(0x26); // es:
2973 emit_int8(0x2e); // cs:
2974 emit_int8(0x64); // fs:
2975 emit_int8(0x65); // gs:
2976 emit_int8((unsigned char)0x90);
2977 }
2978 }
2979
2980 void MacroAssembler::fcmp(Register tmp) {
2981 fcmp(tmp, 1, true, true);
2982 }
2983
2984 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
2985 assert(!pop_right || pop_left, "usage error");
2986 if (VM_Version::supports_cmov()) {
2987 assert(tmp == noreg, "unneeded temp");
2988 if (pop_left) {
2989 fucomip(index);
2990 } else {
2991 fucomi(index);
2992 }
2993 if (pop_right) {
2994 fpop();
2995 }
2996 } else {
2997 assert(tmp != noreg, "need temp");
2998 if (pop_left) {
2999 if (pop_right) {
3000 fcompp();
3001 } else {
3002 fcomp(index);
3003 }
3004 } else {
3005 fcom(index);
3006 }
3007 // convert FPU condition into eflags condition via rax,
3008 save_rax(tmp);
3009 fwait(); fnstsw_ax();
3010 sahf();
3011 restore_rax(tmp);
3012 }
3013 // condition codes set as follows:
3014 //
3015 // CF (corresponds to C0) if x < y
3016 // PF (corresponds to C2) if unordered
3017 // ZF (corresponds to C3) if x = y
3018 }
3019
3020 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
3021 fcmp2int(dst, unordered_is_less, 1, true, true);
3022 }
3023
3024 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
3025 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
3026 Label L;
3027 if (unordered_is_less) {
3028 movl(dst, -1);
3029 jcc(Assembler::parity, L);
3030 jcc(Assembler::below , L);
3031 movl(dst, 0);
3032 jcc(Assembler::equal , L);
3033 increment(dst);
3034 } else { // unordered is greater
3035 movl(dst, 1);
3036 jcc(Assembler::parity, L);
3037 jcc(Assembler::above , L);
3038 movl(dst, 0);
3039 jcc(Assembler::equal , L);
3040 decrementl(dst);
3041 }
3042 bind(L);
3043 }
3044
3045 void MacroAssembler::fld_d(AddressLiteral src) {
3046 fld_d(as_Address(src));
3047 }
3048
3049 void MacroAssembler::fld_s(AddressLiteral src) {
3050 fld_s(as_Address(src));
3051 }
3052
3053 void MacroAssembler::fld_x(AddressLiteral src) {
3054 Assembler::fld_x(as_Address(src));
3055 }
3056
3057 void MacroAssembler::fldcw(AddressLiteral src) {
3058 Assembler::fldcw(as_Address(src));
3059 }
3060
3061 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src) {
3062 if (reachable(src)) {
3063 Assembler::mulpd(dst, as_Address(src));
3064 } else {
3065 lea(rscratch1, src);
3066 Assembler::mulpd(dst, Address(rscratch1, 0));
3067 }
3068 }
3069
3070 void MacroAssembler::increase_precision() {
3071 subptr(rsp, BytesPerWord);
3072 fnstcw(Address(rsp, 0));
3073 movl(rax, Address(rsp, 0));
3074 orl(rax, 0x300);
3075 push(rax);
3076 fldcw(Address(rsp, 0));
3077 pop(rax);
3078 }
3079
3080 void MacroAssembler::restore_precision() {
3081 fldcw(Address(rsp, 0));
3082 addptr(rsp, BytesPerWord);
3083 }
3084
3085 void MacroAssembler::fpop() {
3086 ffree();
3087 fincstp();
3088 }
3089
3090 void MacroAssembler::load_float(Address src) {
3091 if (UseSSE >= 1) {
3092 movflt(xmm0, src);
3093 } else {
3094 LP64_ONLY(ShouldNotReachHere());
3095 NOT_LP64(fld_s(src));
3096 }
3097 }
3098
3099 void MacroAssembler::store_float(Address dst) {
3100 if (UseSSE >= 1) {
3101 movflt(dst, xmm0);
3102 } else {
3103 LP64_ONLY(ShouldNotReachHere());
3104 NOT_LP64(fstp_s(dst));
3105 }
3106 }
3107
3108 void MacroAssembler::load_double(Address src) {
3109 if (UseSSE >= 2) {
3110 movdbl(xmm0, src);
3111 } else {
3112 LP64_ONLY(ShouldNotReachHere());
3113 NOT_LP64(fld_d(src));
3114 }
3115 }
3116
3117 void MacroAssembler::store_double(Address dst) {
3118 if (UseSSE >= 2) {
3119 movdbl(dst, xmm0);
3120 } else {
3121 LP64_ONLY(ShouldNotReachHere());
3122 NOT_LP64(fstp_d(dst));
3123 }
3124 }
3125
3126 void MacroAssembler::fremr(Register tmp) {
3127 save_rax(tmp);
3128 { Label L;
3129 bind(L);
3130 fprem();
3131 fwait(); fnstsw_ax();
3132 #ifdef _LP64
3133 testl(rax, 0x400);
3134 jcc(Assembler::notEqual, L);
3135 #else
3136 sahf();
3137 jcc(Assembler::parity, L);
3138 #endif // _LP64
3139 }
3140 restore_rax(tmp);
3141 // Result is in ST0.
3142 // Note: fxch & fpop to get rid of ST1
3143 // (otherwise FPU stack could overflow eventually)
3144 fxch(1);
3145 fpop();
3146 }
3147
3148 // dst = c = a * b + c
3149 void MacroAssembler::fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
3150 Assembler::vfmadd231sd(c, a, b);
3151 if (dst != c) {
3152 movdbl(dst, c);
3153 }
3154 }
3155
3156 // dst = c = a * b + c
3157 void MacroAssembler::fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
3158 Assembler::vfmadd231ss(c, a, b);
3159 if (dst != c) {
3160 movflt(dst, c);
3161 }
3162 }
3163
3164 // dst = c = a * b + c
3165 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
3166 Assembler::vfmadd231pd(c, a, b, vector_len);
3167 if (dst != c) {
3168 vmovdqu(dst, c);
3169 }
3170 }
3171
3172 // dst = c = a * b + c
3173 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
3174 Assembler::vfmadd231ps(c, a, b, vector_len);
3175 if (dst != c) {
3176 vmovdqu(dst, c);
3177 }
3178 }
3179
3180 // dst = c = a * b + c
3181 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
3182 Assembler::vfmadd231pd(c, a, b, vector_len);
3183 if (dst != c) {
3184 vmovdqu(dst, c);
3185 }
3186 }
3187
3188 // dst = c = a * b + c
3189 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
3190 Assembler::vfmadd231ps(c, a, b, vector_len);
3191 if (dst != c) {
3192 vmovdqu(dst, c);
3193 }
3194 }
3195
3196 void MacroAssembler::incrementl(AddressLiteral dst) {
3197 if (reachable(dst)) {
3198 incrementl(as_Address(dst));
3199 } else {
3200 lea(rscratch1, dst);
3201 incrementl(Address(rscratch1, 0));
3202 }
3203 }
3204
3205 void MacroAssembler::incrementl(ArrayAddress dst) {
3206 incrementl(as_Address(dst));
3207 }
3208
3209 void MacroAssembler::incrementl(Register reg, int value) {
3210 if (value == min_jint) {addl(reg, value) ; return; }
3211 if (value < 0) { decrementl(reg, -value); return; }
3212 if (value == 0) { ; return; }
3213 if (value == 1 && UseIncDec) { incl(reg) ; return; }
3214 /* else */ { addl(reg, value) ; return; }
3215 }
3216
3217 void MacroAssembler::incrementl(Address dst, int value) {
3218 if (value == min_jint) {addl(dst, value) ; return; }
3219 if (value < 0) { decrementl(dst, -value); return; }
3220 if (value == 0) { ; return; }
3221 if (value == 1 && UseIncDec) { incl(dst) ; return; }
3222 /* else */ { addl(dst, value) ; return; }
3223 }
3224
3225 void MacroAssembler::jump(AddressLiteral dst) {
3226 if (reachable(dst)) {
3227 jmp_literal(dst.target(), dst.rspec());
3228 } else {
3229 lea(rscratch1, dst);
3230 jmp(rscratch1);
3231 }
3232 }
3233
3234 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) {
3235 if (reachable(dst)) {
3236 InstructionMark im(this);
3237 relocate(dst.reloc());
3238 const int short_size = 2;
3239 const int long_size = 6;
3240 int offs = (intptr_t)dst.target() - ((intptr_t)pc());
3241 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
3242 // 0111 tttn #8-bit disp
3243 emit_int8(0x70 | cc);
3244 emit_int8((offs - short_size) & 0xFF);
3245 } else {
3246 // 0000 1111 1000 tttn #32-bit disp
3247 emit_int8(0x0F);
3248 emit_int8((unsigned char)(0x80 | cc));
3249 emit_int32(offs - long_size);
3250 }
3251 } else {
3252 #ifdef ASSERT
3253 warning("reversing conditional branch");
3254 #endif /* ASSERT */
3255 Label skip;
3256 jccb(reverse[cc], skip);
3257 lea(rscratch1, dst);
3258 Assembler::jmp(rscratch1);
3259 bind(skip);
3260 }
3261 }
3262
3263 void MacroAssembler::ldmxcsr(AddressLiteral src) {
3264 if (reachable(src)) {
3265 Assembler::ldmxcsr(as_Address(src));
3266 } else {
3267 lea(rscratch1, src);
3268 Assembler::ldmxcsr(Address(rscratch1, 0));
3269 }
3270 }
3271
3272 int MacroAssembler::load_signed_byte(Register dst, Address src) {
3273 int off;
3274 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3275 off = offset();
3276 movsbl(dst, src); // movsxb
3277 } else {
3278 off = load_unsigned_byte(dst, src);
3279 shll(dst, 24);
3280 sarl(dst, 24);
3281 }
3282 return off;
3283 }
3284
3285 // Note: load_signed_short used to be called load_signed_word.
3286 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
3287 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
3288 // The term "word" in HotSpot means a 32- or 64-bit machine word.
3289 int MacroAssembler::load_signed_short(Register dst, Address src) {
3290 int off;
3291 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3292 // This is dubious to me since it seems safe to do a signed 16 => 64 bit
3293 // version but this is what 64bit has always done. This seems to imply
3294 // that users are only using 32bits worth.
3295 off = offset();
3296 movswl(dst, src); // movsxw
3297 } else {
3298 off = load_unsigned_short(dst, src);
3299 shll(dst, 16);
3300 sarl(dst, 16);
3301 }
3302 return off;
3303 }
3304
3305 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
3306 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3307 // and "3.9 Partial Register Penalties", p. 22).
3308 int off;
3309 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
3310 off = offset();
3311 movzbl(dst, src); // movzxb
3312 } else {
3313 xorl(dst, dst);
3314 off = offset();
3315 movb(dst, src);
3316 }
3317 return off;
3318 }
3319
3320 // Note: load_unsigned_short used to be called load_unsigned_word.
3321 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
3322 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3323 // and "3.9 Partial Register Penalties", p. 22).
3324 int off;
3325 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
3326 off = offset();
3327 movzwl(dst, src); // movzxw
3328 } else {
3329 xorl(dst, dst);
3330 off = offset();
3331 movw(dst, src);
3332 }
3333 return off;
3334 }
3335
3336 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
3337 switch (size_in_bytes) {
3338 #ifndef _LP64
3339 case 8:
3340 assert(dst2 != noreg, "second dest register required");
3341 movl(dst, src);
3342 movl(dst2, src.plus_disp(BytesPerInt));
3343 break;
3344 #else
3345 case 8: movq(dst, src); break;
3346 #endif
3347 case 4: movl(dst, src); break;
3348 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
3349 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
3350 default: ShouldNotReachHere();
3351 }
3352 }
3353
3354 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
3355 switch (size_in_bytes) {
3356 #ifndef _LP64
3357 case 8:
3358 assert(src2 != noreg, "second source register required");
3359 movl(dst, src);
3360 movl(dst.plus_disp(BytesPerInt), src2);
3361 break;
3362 #else
3363 case 8: movq(dst, src); break;
3364 #endif
3365 case 4: movl(dst, src); break;
3366 case 2: movw(dst, src); break;
3367 case 1: movb(dst, src); break;
3368 default: ShouldNotReachHere();
3369 }
3370 }
3371
3372 void MacroAssembler::mov32(AddressLiteral dst, Register src) {
3373 if (reachable(dst)) {
3374 movl(as_Address(dst), src);
3375 } else {
3376 lea(rscratch1, dst);
3377 movl(Address(rscratch1, 0), src);
3378 }
3379 }
3380
3381 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
3382 if (reachable(src)) {
3383 movl(dst, as_Address(src));
3384 } else {
3385 lea(rscratch1, src);
3386 movl(dst, Address(rscratch1, 0));
3387 }
3388 }
3389
3390 // C++ bool manipulation
3391
3392 void MacroAssembler::movbool(Register dst, Address src) {
3393 if(sizeof(bool) == 1)
3394 movb(dst, src);
3395 else if(sizeof(bool) == 2)
3396 movw(dst, src);
3397 else if(sizeof(bool) == 4)
3398 movl(dst, src);
3399 else
3400 // unsupported
3401 ShouldNotReachHere();
3402 }
3403
3404 void MacroAssembler::movbool(Address dst, bool boolconst) {
3405 if(sizeof(bool) == 1)
3406 movb(dst, (int) boolconst);
3407 else if(sizeof(bool) == 2)
3408 movw(dst, (int) boolconst);
3409 else if(sizeof(bool) == 4)
3410 movl(dst, (int) boolconst);
3411 else
3412 // unsupported
3413 ShouldNotReachHere();
3414 }
3415
3416 void MacroAssembler::movbool(Address dst, Register src) {
3417 if(sizeof(bool) == 1)
3418 movb(dst, src);
3419 else if(sizeof(bool) == 2)
3420 movw(dst, src);
3421 else if(sizeof(bool) == 4)
3422 movl(dst, src);
3423 else
3424 // unsupported
3425 ShouldNotReachHere();
3426 }
3427
3428 void MacroAssembler::movbyte(ArrayAddress dst, int src) {
3429 movb(as_Address(dst), src);
3430 }
3431
3432 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src) {
3433 if (reachable(src)) {
3434 movdl(dst, as_Address(src));
3435 } else {
3436 lea(rscratch1, src);
3437 movdl(dst, Address(rscratch1, 0));
3438 }
3439 }
3440
3441 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src) {
3442 if (reachable(src)) {
3443 movq(dst, as_Address(src));
3444 } else {
3445 lea(rscratch1, src);
3446 movq(dst, Address(rscratch1, 0));
3447 }
3448 }
3449
3450 void MacroAssembler::setvectmask(Register dst, Register src) {
3451 Assembler::movl(dst, 1);
3452 Assembler::shlxl(dst, dst, src);
3453 Assembler::decl(dst);
3454 Assembler::kmovdl(k1, dst);
3455 Assembler::movl(dst, src);
3456 }
3457
3458 void MacroAssembler::restorevectmask() {
3459 Assembler::knotwl(k1, k0);
3460 }
3461
3462 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) {
3463 if (reachable(src)) {
3464 if (UseXmmLoadAndClearUpper) {
3465 movsd (dst, as_Address(src));
3466 } else {
3467 movlpd(dst, as_Address(src));
3468 }
3469 } else {
3470 lea(rscratch1, src);
3471 if (UseXmmLoadAndClearUpper) {
3472 movsd (dst, Address(rscratch1, 0));
3473 } else {
3474 movlpd(dst, Address(rscratch1, 0));
3475 }
3476 }
3477 }
3478
3479 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) {
3480 if (reachable(src)) {
3481 movss(dst, as_Address(src));
3482 } else {
3483 lea(rscratch1, src);
3484 movss(dst, Address(rscratch1, 0));
3485 }
3486 }
3487
3488 void MacroAssembler::movptr(Register dst, Register src) {
3489 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3490 }
3491
3492 void MacroAssembler::movptr(Register dst, Address src) {
3493 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3494 }
3495
3496 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
3497 void MacroAssembler::movptr(Register dst, intptr_t src) {
3498 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src));
3499 }
3500
3501 void MacroAssembler::movptr(Address dst, Register src) {
3502 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3503 }
3504
3505 void MacroAssembler::movdqu(Address dst, XMMRegister src) {
3506 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3507 Assembler::movdqu(dst, src);
3508 }
3509
3510 void MacroAssembler::movdqu(XMMRegister dst, Address src) {
3511 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3512 Assembler::movdqu(dst, src);
3513 }
3514
3515 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) {
3516 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3517 Assembler::movdqu(dst, src);
3518 }
3519
3520 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src, Register scratchReg) {
3521 if (reachable(src)) {
3522 movdqu(dst, as_Address(src));
3523 } else {
3524 lea(scratchReg, src);
3525 movdqu(dst, Address(scratchReg, 0));
3526 }
3527 }
3528
3529 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) {
3530 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3531 Assembler::vmovdqu(dst, src);
3532 }
3533
3534 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) {
3535 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3536 Assembler::vmovdqu(dst, src);
3537 }
3538
3539 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) {
3540 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3541 Assembler::vmovdqu(dst, src);
3542 }
3543
3544 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src) {
3545 if (reachable(src)) {
3546 vmovdqu(dst, as_Address(src));
3547 }
3548 else {
3549 lea(rscratch1, src);
3550 vmovdqu(dst, Address(rscratch1, 0));
3551 }
3552 }
3553
3554 void MacroAssembler::evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3555 if (reachable(src)) {
3556 Assembler::evmovdquq(dst, as_Address(src), vector_len);
3557 } else {
3558 lea(rscratch, src);
3559 Assembler::evmovdquq(dst, Address(rscratch, 0), vector_len);
3560 }
3561 }
3562
3563 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src) {
3564 if (reachable(src)) {
3565 Assembler::movdqa(dst, as_Address(src));
3566 } else {
3567 lea(rscratch1, src);
3568 Assembler::movdqa(dst, Address(rscratch1, 0));
3569 }
3570 }
3571
3572 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) {
3573 if (reachable(src)) {
3574 Assembler::movsd(dst, as_Address(src));
3575 } else {
3576 lea(rscratch1, src);
3577 Assembler::movsd(dst, Address(rscratch1, 0));
3578 }
3579 }
3580
3581 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) {
3582 if (reachable(src)) {
3583 Assembler::movss(dst, as_Address(src));
3584 } else {
3585 lea(rscratch1, src);
3586 Assembler::movss(dst, Address(rscratch1, 0));
3587 }
3588 }
3589
3590 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) {
3591 if (reachable(src)) {
3592 Assembler::mulsd(dst, as_Address(src));
3593 } else {
3594 lea(rscratch1, src);
3595 Assembler::mulsd(dst, Address(rscratch1, 0));
3596 }
3597 }
3598
3599 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) {
3600 if (reachable(src)) {
3601 Assembler::mulss(dst, as_Address(src));
3602 } else {
3603 lea(rscratch1, src);
3604 Assembler::mulss(dst, Address(rscratch1, 0));
3605 }
3606 }
3607
3608 void MacroAssembler::null_check(Register reg, int offset) {
3609 if (needs_explicit_null_check(offset)) {
3610 // provoke OS NULL exception if reg = NULL by
3611 // accessing M[reg] w/o changing any (non-CC) registers
3612 // NOTE: cmpl is plenty here to provoke a segv
3613 cmpptr(rax, Address(reg, 0));
3614 // Note: should probably use testl(rax, Address(reg, 0));
3615 // may be shorter code (however, this version of
3616 // testl needs to be implemented first)
3617 } else {
3618 // nothing to do, (later) access of M[reg + offset]
3619 // will provoke OS NULL exception if reg = NULL
3620 }
3621 }
3622
3623 void MacroAssembler::os_breakpoint() {
3624 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
3625 // (e.g., MSVC can't call ps() otherwise)
3626 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
3627 }
3628
3629 void MacroAssembler::unimplemented(const char* what) {
3630 const char* buf = NULL;
3631 {
3632 ResourceMark rm;
3633 stringStream ss;
3634 ss.print("unimplemented: %s", what);
3635 buf = code_string(ss.as_string());
3636 }
3637 stop(buf);
3638 }
3639
3640 #ifdef _LP64
3641 #define XSTATE_BV 0x200
3642 #endif
3643
3644 void MacroAssembler::pop_CPU_state() {
3645 pop_FPU_state();
3646 pop_IU_state();
3647 }
3648
3649 void MacroAssembler::pop_FPU_state() {
3650 #ifndef _LP64
3651 frstor(Address(rsp, 0));
3652 #else
3653 fxrstor(Address(rsp, 0));
3654 #endif
3655 addptr(rsp, FPUStateSizeInWords * wordSize);
3656 }
3657
3658 void MacroAssembler::pop_IU_state() {
3659 popa();
3660 LP64_ONLY(addq(rsp, 8));
3661 popf();
3662 }
3663
3664 // Save Integer and Float state
3665 // Warning: Stack must be 16 byte aligned (64bit)
3666 void MacroAssembler::push_CPU_state() {
3667 push_IU_state();
3668 push_FPU_state();
3669 }
3670
3671 void MacroAssembler::push_FPU_state() {
3672 subptr(rsp, FPUStateSizeInWords * wordSize);
3673 #ifndef _LP64
3674 fnsave(Address(rsp, 0));
3675 fwait();
3676 #else
3677 fxsave(Address(rsp, 0));
3678 #endif // LP64
3679 }
3680
3681 void MacroAssembler::push_IU_state() {
3682 // Push flags first because pusha kills them
3683 pushf();
3684 // Make sure rsp stays 16-byte aligned
3685 LP64_ONLY(subq(rsp, 8));
3686 pusha();
3687 }
3688
3689 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp) { // determine java_thread register
3690 if (!java_thread->is_valid()) {
3691 java_thread = rdi;
3692 get_thread(java_thread);
3693 }
3694 // we must set sp to zero to clear frame
3695 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
3696 if (clear_fp) {
3697 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
3698 }
3699
3700 // Always clear the pc because it could have been set by make_walkable()
3701 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
3702
3703 vzeroupper();
3704 }
3705
3706 void MacroAssembler::restore_rax(Register tmp) {
3707 if (tmp == noreg) pop(rax);
3708 else if (tmp != rax) mov(rax, tmp);
3709 }
3710
3711 void MacroAssembler::round_to(Register reg, int modulus) {
3712 addptr(reg, modulus - 1);
3713 andptr(reg, -modulus);
3714 }
3715
3716 void MacroAssembler::save_rax(Register tmp) {
3717 if (tmp == noreg) push(rax);
3718 else if (tmp != rax) mov(tmp, rax);
3719 }
3720
3721 // Write serialization page so VM thread can do a pseudo remote membar.
3722 // We use the current thread pointer to calculate a thread specific
3723 // offset to write to within the page. This minimizes bus traffic
3724 // due to cache line collision.
3725 void MacroAssembler::serialize_memory(Register thread, Register tmp) {
3726 movl(tmp, thread);
3727 shrl(tmp, os::get_serialize_page_shift_count());
3728 andl(tmp, (os::vm_page_size() - sizeof(int)));
3729
3730 Address index(noreg, tmp, Address::times_1);
3731 ExternalAddress page(os::get_memory_serialize_page());
3732
3733 // Size of store must match masking code above
3734 movl(as_Address(ArrayAddress(page, index)), tmp);
3735 }
3736
3737 void MacroAssembler::safepoint_poll(Label& slow_path, Register thread_reg, Register temp_reg) {
3738 if (SafepointMechanism::uses_thread_local_poll()) {
3739 #ifdef _LP64
3740 assert(thread_reg == r15_thread, "should be");
3741 #else
3742 if (thread_reg == noreg) {
3743 thread_reg = temp_reg;
3744 get_thread(thread_reg);
3745 }
3746 #endif
3747 testb(Address(thread_reg, Thread::polling_page_offset()), SafepointMechanism::poll_bit());
3748 jcc(Assembler::notZero, slow_path); // handshake bit set implies poll
3749 } else {
3750 cmp32(ExternalAddress(SafepointSynchronize::address_of_state()),
3751 SafepointSynchronize::_not_synchronized);
3752 jcc(Assembler::notEqual, slow_path);
3753 }
3754 }
3755
3756 // Calls to C land
3757 //
3758 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
3759 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
3760 // has to be reset to 0. This is required to allow proper stack traversal.
3761 void MacroAssembler::set_last_Java_frame(Register java_thread,
3762 Register last_java_sp,
3763 Register last_java_fp,
3764 address last_java_pc) {
3765 vzeroupper();
3766 // determine java_thread register
3767 if (!java_thread->is_valid()) {
3768 java_thread = rdi;
3769 get_thread(java_thread);
3770 }
3771 // determine last_java_sp register
3772 if (!last_java_sp->is_valid()) {
3773 last_java_sp = rsp;
3774 }
3775
3776 // last_java_fp is optional
3777
3778 if (last_java_fp->is_valid()) {
3779 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
3780 }
3781
3782 // last_java_pc is optional
3783
3784 if (last_java_pc != NULL) {
3785 lea(Address(java_thread,
3786 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()),
3787 InternalAddress(last_java_pc));
3788
3789 }
3790 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
3791 }
3792
3793 void MacroAssembler::shlptr(Register dst, int imm8) {
3794 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
3795 }
3796
3797 void MacroAssembler::shrptr(Register dst, int imm8) {
3798 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
3799 }
3800
3801 void MacroAssembler::sign_extend_byte(Register reg) {
3802 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
3803 movsbl(reg, reg); // movsxb
3804 } else {
3805 shll(reg, 24);
3806 sarl(reg, 24);
3807 }
3808 }
3809
3810 void MacroAssembler::sign_extend_short(Register reg) {
3811 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3812 movswl(reg, reg); // movsxw
3813 } else {
3814 shll(reg, 16);
3815 sarl(reg, 16);
3816 }
3817 }
3818
3819 void MacroAssembler::testl(Register dst, AddressLiteral src) {
3820 assert(reachable(src), "Address should be reachable");
3821 testl(dst, as_Address(src));
3822 }
3823
3824 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
3825 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3826 Assembler::pcmpeqb(dst, src);
3827 }
3828
3829 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3830 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3831 Assembler::pcmpeqw(dst, src);
3832 }
3833
3834 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3835 assert((dst->encoding() < 16),"XMM register should be 0-15");
3836 Assembler::pcmpestri(dst, src, imm8);
3837 }
3838
3839 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3840 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3841 Assembler::pcmpestri(dst, src, imm8);
3842 }
3843
3844 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3845 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3846 Assembler::pmovzxbw(dst, src);
3847 }
3848
3849 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) {
3850 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3851 Assembler::pmovzxbw(dst, src);
3852 }
3853
3854 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) {
3855 assert((src->encoding() < 16),"XMM register should be 0-15");
3856 Assembler::pmovmskb(dst, src);
3857 }
3858
3859 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) {
3860 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3861 Assembler::ptest(dst, src);
3862 }
3863
3864 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) {
3865 if (reachable(src)) {
3866 Assembler::sqrtsd(dst, as_Address(src));
3867 } else {
3868 lea(rscratch1, src);
3869 Assembler::sqrtsd(dst, Address(rscratch1, 0));
3870 }
3871 }
3872
3873 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) {
3874 if (reachable(src)) {
3875 Assembler::sqrtss(dst, as_Address(src));
3876 } else {
3877 lea(rscratch1, src);
3878 Assembler::sqrtss(dst, Address(rscratch1, 0));
3879 }
3880 }
3881
3882 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) {
3883 if (reachable(src)) {
3884 Assembler::subsd(dst, as_Address(src));
3885 } else {
3886 lea(rscratch1, src);
3887 Assembler::subsd(dst, Address(rscratch1, 0));
3888 }
3889 }
3890
3891 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) {
3892 if (reachable(src)) {
3893 Assembler::subss(dst, as_Address(src));
3894 } else {
3895 lea(rscratch1, src);
3896 Assembler::subss(dst, Address(rscratch1, 0));
3897 }
3898 }
3899
3900 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) {
3901 if (reachable(src)) {
3902 Assembler::ucomisd(dst, as_Address(src));
3903 } else {
3904 lea(rscratch1, src);
3905 Assembler::ucomisd(dst, Address(rscratch1, 0));
3906 }
3907 }
3908
3909 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) {
3910 if (reachable(src)) {
3911 Assembler::ucomiss(dst, as_Address(src));
3912 } else {
3913 lea(rscratch1, src);
3914 Assembler::ucomiss(dst, Address(rscratch1, 0));
3915 }
3916 }
3917
3918 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) {
3919 // Used in sign-bit flipping with aligned address.
3920 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3921 if (reachable(src)) {
3922 Assembler::xorpd(dst, as_Address(src));
3923 } else {
3924 lea(rscratch1, src);
3925 Assembler::xorpd(dst, Address(rscratch1, 0));
3926 }
3927 }
3928
3929 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) {
3930 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
3931 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
3932 }
3933 else {
3934 Assembler::xorpd(dst, src);
3935 }
3936 }
3937
3938 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) {
3939 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
3940 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
3941 } else {
3942 Assembler::xorps(dst, src);
3943 }
3944 }
3945
3946 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) {
3947 // Used in sign-bit flipping with aligned address.
3948 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3949 if (reachable(src)) {
3950 Assembler::xorps(dst, as_Address(src));
3951 } else {
3952 lea(rscratch1, src);
3953 Assembler::xorps(dst, Address(rscratch1, 0));
3954 }
3955 }
3956
3957 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src) {
3958 // Used in sign-bit flipping with aligned address.
3959 bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
3960 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
3961 if (reachable(src)) {
3962 Assembler::pshufb(dst, as_Address(src));
3963 } else {
3964 lea(rscratch1, src);
3965 Assembler::pshufb(dst, Address(rscratch1, 0));
3966 }
3967 }
3968
3969 // AVX 3-operands instructions
3970
3971 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3972 if (reachable(src)) {
3973 vaddsd(dst, nds, as_Address(src));
3974 } else {
3975 lea(rscratch1, src);
3976 vaddsd(dst, nds, Address(rscratch1, 0));
3977 }
3978 }
3979
3980 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3981 if (reachable(src)) {
3982 vaddss(dst, nds, as_Address(src));
3983 } else {
3984 lea(rscratch1, src);
3985 vaddss(dst, nds, Address(rscratch1, 0));
3986 }
3987 }
3988
3989 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) {
3990 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3991 vandps(dst, nds, negate_field, vector_len);
3992 }
3993
3994 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) {
3995 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3996 vandpd(dst, nds, negate_field, vector_len);
3997 }
3998
3999 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4000 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
4001 Assembler::vpaddb(dst, nds, src, vector_len);
4002 }
4003
4004 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4005 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
4006 Assembler::vpaddb(dst, nds, src, vector_len);
4007 }
4008
4009 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4010 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
4011 Assembler::vpaddw(dst, nds, src, vector_len);
4012 }
4013
4014 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4015 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
4016 Assembler::vpaddw(dst, nds, src, vector_len);
4017 }
4018
4019 void MacroAssembler::vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
4020 if (reachable(src)) {
4021 Assembler::vpand(dst, nds, as_Address(src), vector_len);
4022 } else {
4023 lea(rscratch1, src);
4024 Assembler::vpand(dst, nds, Address(rscratch1, 0), vector_len);
4025 }
4026 }
4027
4028 void MacroAssembler::vpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len) {
4029 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
4030 Assembler::vpbroadcastw(dst, src, vector_len);
4031 }
4032
4033 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4034 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
4035 Assembler::vpcmpeqb(dst, nds, src, vector_len);
4036 }
4037
4038 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4039 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
4040 Assembler::vpcmpeqw(dst, nds, src, vector_len);
4041 }
4042
4043 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
4044 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
4045 Assembler::vpmovzxbw(dst, src, vector_len);
4046 }
4047
4048 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src) {
4049 assert((src->encoding() < 16),"XMM register should be 0-15");
4050 Assembler::vpmovmskb(dst, src);
4051 }
4052
4053 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4054 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
4055 Assembler::vpmullw(dst, nds, src, vector_len);
4056 }
4057
4058 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4059 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
4060 Assembler::vpmullw(dst, nds, src, vector_len);
4061 }
4062
4063 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4064 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
4065 Assembler::vpsubb(dst, nds, src, vector_len);
4066 }
4067
4068 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4069 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
4070 Assembler::vpsubb(dst, nds, src, vector_len);
4071 }
4072
4073 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4074 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
4075 Assembler::vpsubw(dst, nds, src, vector_len);
4076 }
4077
4078 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4079 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
4080 Assembler::vpsubw(dst, nds, src, vector_len);
4081 }
4082
4083 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
4084 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
4085 Assembler::vpsraw(dst, nds, shift, vector_len);
4086 }
4087
4088 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
4089 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
4090 Assembler::vpsraw(dst, nds, shift, vector_len);
4091 }
4092
4093 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
4094 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
4095 Assembler::vpsrlw(dst, nds, shift, vector_len);
4096 }
4097
4098 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
4099 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
4100 Assembler::vpsrlw(dst, nds, shift, vector_len);
4101 }
4102
4103 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
4104 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
4105 Assembler::vpsllw(dst, nds, shift, vector_len);
4106 }
4107
4108 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
4109 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
4110 Assembler::vpsllw(dst, nds, shift, vector_len);
4111 }
4112
4113 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) {
4114 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
4115 Assembler::vptest(dst, src);
4116 }
4117
4118 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) {
4119 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
4120 Assembler::punpcklbw(dst, src);
4121 }
4122
4123 void MacroAssembler::pshufd(XMMRegister dst, Address src, int mode) {
4124 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
4125 Assembler::pshufd(dst, src, mode);
4126 }
4127
4128 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
4129 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
4130 Assembler::pshuflw(dst, src, mode);
4131 }
4132
4133 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
4134 if (reachable(src)) {
4135 vandpd(dst, nds, as_Address(src), vector_len);
4136 } else {
4137 lea(rscratch1, src);
4138 vandpd(dst, nds, Address(rscratch1, 0), vector_len);
4139 }
4140 }
4141
4142 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
4143 if (reachable(src)) {
4144 vandps(dst, nds, as_Address(src), vector_len);
4145 } else {
4146 lea(rscratch1, src);
4147 vandps(dst, nds, Address(rscratch1, 0), vector_len);
4148 }
4149 }
4150
4151 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4152 if (reachable(src)) {
4153 vdivsd(dst, nds, as_Address(src));
4154 } else {
4155 lea(rscratch1, src);
4156 vdivsd(dst, nds, Address(rscratch1, 0));
4157 }
4158 }
4159
4160 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4161 if (reachable(src)) {
4162 vdivss(dst, nds, as_Address(src));
4163 } else {
4164 lea(rscratch1, src);
4165 vdivss(dst, nds, Address(rscratch1, 0));
4166 }
4167 }
4168
4169 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4170 if (reachable(src)) {
4171 vmulsd(dst, nds, as_Address(src));
4172 } else {
4173 lea(rscratch1, src);
4174 vmulsd(dst, nds, Address(rscratch1, 0));
4175 }
4176 }
4177
4178 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4179 if (reachable(src)) {
4180 vmulss(dst, nds, as_Address(src));
4181 } else {
4182 lea(rscratch1, src);
4183 vmulss(dst, nds, Address(rscratch1, 0));
4184 }
4185 }
4186
4187 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4188 if (reachable(src)) {
4189 vsubsd(dst, nds, as_Address(src));
4190 } else {
4191 lea(rscratch1, src);
4192 vsubsd(dst, nds, Address(rscratch1, 0));
4193 }
4194 }
4195
4196 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4197 if (reachable(src)) {
4198 vsubss(dst, nds, as_Address(src));
4199 } else {
4200 lea(rscratch1, src);
4201 vsubss(dst, nds, Address(rscratch1, 0));
4202 }
4203 }
4204
4205 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4206 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
4207 vxorps(dst, nds, src, Assembler::AVX_128bit);
4208 }
4209
4210 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4211 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
4212 vxorpd(dst, nds, src, Assembler::AVX_128bit);
4213 }
4214
4215 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
4216 if (reachable(src)) {
4217 vxorpd(dst, nds, as_Address(src), vector_len);
4218 } else {
4219 lea(rscratch1, src);
4220 vxorpd(dst, nds, Address(rscratch1, 0), vector_len);
4221 }
4222 }
4223
4224 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
4225 if (reachable(src)) {
4226 vxorps(dst, nds, as_Address(src), vector_len);
4227 } else {
4228 lea(rscratch1, src);
4229 vxorps(dst, nds, Address(rscratch1, 0), vector_len);
4230 }
4231 }
4232
4233 void MacroAssembler::clear_jweak_tag(Register possibly_jweak) {
4234 const int32_t inverted_jweak_mask = ~static_cast<int32_t>(JNIHandles::weak_tag_mask);
4235 STATIC_ASSERT(inverted_jweak_mask == -2); // otherwise check this code
4236 // The inverted mask is sign-extended
4237 andptr(possibly_jweak, inverted_jweak_mask);
4238 }
4239
4240 void MacroAssembler::resolve_jobject(Register value,
4241 Register thread,
4242 Register tmp) {
4243 assert_different_registers(value, thread, tmp);
4244 Label done, not_weak;
4245 testptr(value, value);
4246 jcc(Assembler::zero, done); // Use NULL as-is.
4247 testptr(value, JNIHandles::weak_tag_mask); // Test for jweak tag.
4248 jcc(Assembler::zero, not_weak);
4249 // Resolve jweak.
4250 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
4251 value, Address(value, -JNIHandles::weak_tag_value), tmp, thread);
4252 verify_oop(value);
4253 jmp(done);
4254 bind(not_weak);
4255 // Resolve (untagged) jobject.
4256 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, 0), tmp, thread);
4257 verify_oop(value);
4258 bind(done);
4259 }
4260
4261 void MacroAssembler::subptr(Register dst, int32_t imm32) {
4262 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
4263 }
4264
4265 // Force generation of a 4 byte immediate value even if it fits into 8bit
4266 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
4267 LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32));
4268 }
4269
4270 void MacroAssembler::subptr(Register dst, Register src) {
4271 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
4272 }
4273
4274 // C++ bool manipulation
4275 void MacroAssembler::testbool(Register dst) {
4276 if(sizeof(bool) == 1)
4277 testb(dst, 0xff);
4278 else if(sizeof(bool) == 2) {
4279 // testw implementation needed for two byte bools
4280 ShouldNotReachHere();
4281 } else if(sizeof(bool) == 4)
4282 testl(dst, dst);
4283 else
4284 // unsupported
4285 ShouldNotReachHere();
4286 }
4287
4288 void MacroAssembler::testptr(Register dst, Register src) {
4289 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
4290 }
4291
4292 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
4293 void MacroAssembler::tlab_allocate(Register thread, Register obj,
4294 Register var_size_in_bytes,
4295 int con_size_in_bytes,
4296 Register t1,
4297 Register t2,
4298 Label& slow_case) {
4299 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
4300 bs->tlab_allocate(this, thread, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
4301 }
4302
4303 // Defines obj, preserves var_size_in_bytes
4304 void MacroAssembler::eden_allocate(Register thread, Register obj,
4305 Register var_size_in_bytes,
4306 int con_size_in_bytes,
4307 Register t1,
4308 Label& slow_case) {
4309 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
4310 bs->eden_allocate(this, thread, obj, var_size_in_bytes, con_size_in_bytes, t1, slow_case);
4311 }
4312
4313 // Preserves the contents of address, destroys the contents length_in_bytes and temp.
4314 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) {
4315 assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different");
4316 assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord");
4317 Label done;
4318
4319 testptr(length_in_bytes, length_in_bytes);
4320 jcc(Assembler::zero, done);
4321
4322 // initialize topmost word, divide index by 2, check if odd and test if zero
4323 // note: for the remaining code to work, index must be a multiple of BytesPerWord
4324 #ifdef ASSERT
4325 {
4326 Label L;
4327 testptr(length_in_bytes, BytesPerWord - 1);
4328 jcc(Assembler::zero, L);
4329 stop("length must be a multiple of BytesPerWord");
4330 bind(L);
4331 }
4332 #endif
4333 Register index = length_in_bytes;
4334 xorptr(temp, temp); // use _zero reg to clear memory (shorter code)
4335 if (UseIncDec) {
4336 shrptr(index, 3); // divide by 8/16 and set carry flag if bit 2 was set
4337 } else {
4338 shrptr(index, 2); // use 2 instructions to avoid partial flag stall
4339 shrptr(index, 1);
4340 }
4341 #ifndef _LP64
4342 // index could have not been a multiple of 8 (i.e., bit 2 was set)
4343 {
4344 Label even;
4345 // note: if index was a multiple of 8, then it cannot
4346 // be 0 now otherwise it must have been 0 before
4347 // => if it is even, we don't need to check for 0 again
4348 jcc(Assembler::carryClear, even);
4349 // clear topmost word (no jump would be needed if conditional assignment worked here)
4350 movptr(Address(address, index, Address::times_8, offset_in_bytes - 0*BytesPerWord), temp);
4351 // index could be 0 now, must check again
4352 jcc(Assembler::zero, done);
4353 bind(even);
4354 }
4355 #endif // !_LP64
4356 // initialize remaining object fields: index is a multiple of 2 now
4357 {
4358 Label loop;
4359 bind(loop);
4360 movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp);
4361 NOT_LP64(movptr(Address(address, index, Address::times_8, offset_in_bytes - 2*BytesPerWord), temp);)
4362 decrement(index);
4363 jcc(Assembler::notZero, loop);
4364 }
4365
4366 bind(done);
4367 }
4368
4369 // Look up the method for a megamorphic invokeinterface call.
4370 // The target method is determined by <intf_klass, itable_index>.
4371 // The receiver klass is in recv_klass.
4372 // On success, the result will be in method_result, and execution falls through.
4373 // On failure, execution transfers to the given label.
4374 void MacroAssembler::lookup_interface_method(Register recv_klass,
4375 Register intf_klass,
4376 RegisterOrConstant itable_index,
4377 Register method_result,
4378 Register scan_temp,
4379 Label& L_no_such_interface,
4380 bool return_method) {
4381 assert_different_registers(recv_klass, intf_klass, scan_temp);
4382 assert_different_registers(method_result, intf_klass, scan_temp);
4383 assert(recv_klass != method_result || !return_method,
4384 "recv_klass can be destroyed when method isn't needed");
4385
4386 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
4387 "caller must use same register for non-constant itable index as for method");
4388
4389 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
4390 int vtable_base = in_bytes(Klass::vtable_start_offset());
4391 int itentry_off = itableMethodEntry::method_offset_in_bytes();
4392 int scan_step = itableOffsetEntry::size() * wordSize;
4393 int vte_size = vtableEntry::size_in_bytes();
4394 Address::ScaleFactor times_vte_scale = Address::times_ptr;
4395 assert(vte_size == wordSize, "else adjust times_vte_scale");
4396
4397 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
4398
4399 // %%% Could store the aligned, prescaled offset in the klassoop.
4400 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
4401
4402 if (return_method) {
4403 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
4404 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
4405 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
4406 }
4407
4408 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
4409 // if (scan->interface() == intf) {
4410 // result = (klass + scan->offset() + itable_index);
4411 // }
4412 // }
4413 Label search, found_method;
4414
4415 for (int peel = 1; peel >= 0; peel--) {
4416 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
4417 cmpptr(intf_klass, method_result);
4418
4419 if (peel) {
4420 jccb(Assembler::equal, found_method);
4421 } else {
4422 jccb(Assembler::notEqual, search);
4423 // (invert the test to fall through to found_method...)
4424 }
4425
4426 if (!peel) break;
4427
4428 bind(search);
4429
4430 // Check that the previous entry is non-null. A null entry means that
4431 // the receiver class doesn't implement the interface, and wasn't the
4432 // same as when the caller was compiled.
4433 testptr(method_result, method_result);
4434 jcc(Assembler::zero, L_no_such_interface);
4435 addptr(scan_temp, scan_step);
4436 }
4437
4438 bind(found_method);
4439
4440 if (return_method) {
4441 // Got a hit.
4442 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes()));
4443 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
4444 }
4445 }
4446
4447
4448 // virtual method calling
4449 void MacroAssembler::lookup_virtual_method(Register recv_klass,
4450 RegisterOrConstant vtable_index,
4451 Register method_result) {
4452 const int base = in_bytes(Klass::vtable_start_offset());
4453 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
4454 Address vtable_entry_addr(recv_klass,
4455 vtable_index, Address::times_ptr,
4456 base + vtableEntry::method_offset_in_bytes());
4457 movptr(method_result, vtable_entry_addr);
4458 }
4459
4460
4461 void MacroAssembler::check_klass_subtype(Register sub_klass,
4462 Register super_klass,
4463 Register temp_reg,
4464 Label& L_success) {
4465 Label L_failure;
4466 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL);
4467 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL);
4468 bind(L_failure);
4469 }
4470
4471
4472 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
4473 Register super_klass,
4474 Register temp_reg,
4475 Label* L_success,
4476 Label* L_failure,
4477 Label* L_slow_path,
4478 RegisterOrConstant super_check_offset) {
4479 assert_different_registers(sub_klass, super_klass, temp_reg);
4480 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
4481 if (super_check_offset.is_register()) {
4482 assert_different_registers(sub_klass, super_klass,
4483 super_check_offset.as_register());
4484 } else if (must_load_sco) {
4485 assert(temp_reg != noreg, "supply either a temp or a register offset");
4486 }
4487
4488 Label L_fallthrough;
4489 int label_nulls = 0;
4490 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
4491 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
4492 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
4493 assert(label_nulls <= 1, "at most one NULL in the batch");
4494
4495 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4496 int sco_offset = in_bytes(Klass::super_check_offset_offset());
4497 Address super_check_offset_addr(super_klass, sco_offset);
4498
4499 // Hacked jcc, which "knows" that L_fallthrough, at least, is in
4500 // range of a jccb. If this routine grows larger, reconsider at
4501 // least some of these.
4502 #define local_jcc(assembler_cond, label) \
4503 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \
4504 else jcc( assembler_cond, label) /*omit semi*/
4505
4506 // Hacked jmp, which may only be used just before L_fallthrough.
4507 #define final_jmp(label) \
4508 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
4509 else jmp(label) /*omit semi*/
4510
4511 // If the pointers are equal, we are done (e.g., String[] elements).
4512 // This self-check enables sharing of secondary supertype arrays among
4513 // non-primary types such as array-of-interface. Otherwise, each such
4514 // type would need its own customized SSA.
4515 // We move this check to the front of the fast path because many
4516 // type checks are in fact trivially successful in this manner,
4517 // so we get a nicely predicted branch right at the start of the check.
4518 cmpptr(sub_klass, super_klass);
4519 local_jcc(Assembler::equal, *L_success);
4520
4521 // Check the supertype display:
4522 if (must_load_sco) {
4523 // Positive movl does right thing on LP64.
4524 movl(temp_reg, super_check_offset_addr);
4525 super_check_offset = RegisterOrConstant(temp_reg);
4526 }
4527 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
4528 cmpptr(super_klass, super_check_addr); // load displayed supertype
4529
4530 // This check has worked decisively for primary supers.
4531 // Secondary supers are sought in the super_cache ('super_cache_addr').
4532 // (Secondary supers are interfaces and very deeply nested subtypes.)
4533 // This works in the same check above because of a tricky aliasing
4534 // between the super_cache and the primary super display elements.
4535 // (The 'super_check_addr' can address either, as the case requires.)
4536 // Note that the cache is updated below if it does not help us find
4537 // what we need immediately.
4538 // So if it was a primary super, we can just fail immediately.
4539 // Otherwise, it's the slow path for us (no success at this point).
4540
4541 if (super_check_offset.is_register()) {
4542 local_jcc(Assembler::equal, *L_success);
4543 cmpl(super_check_offset.as_register(), sc_offset);
4544 if (L_failure == &L_fallthrough) {
4545 local_jcc(Assembler::equal, *L_slow_path);
4546 } else {
4547 local_jcc(Assembler::notEqual, *L_failure);
4548 final_jmp(*L_slow_path);
4549 }
4550 } else if (super_check_offset.as_constant() == sc_offset) {
4551 // Need a slow path; fast failure is impossible.
4552 if (L_slow_path == &L_fallthrough) {
4553 local_jcc(Assembler::equal, *L_success);
4554 } else {
4555 local_jcc(Assembler::notEqual, *L_slow_path);
4556 final_jmp(*L_success);
4557 }
4558 } else {
4559 // No slow path; it's a fast decision.
4560 if (L_failure == &L_fallthrough) {
4561 local_jcc(Assembler::equal, *L_success);
4562 } else {
4563 local_jcc(Assembler::notEqual, *L_failure);
4564 final_jmp(*L_success);
4565 }
4566 }
4567
4568 bind(L_fallthrough);
4569
4570 #undef local_jcc
4571 #undef final_jmp
4572 }
4573
4574
4575 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4576 Register super_klass,
4577 Register temp_reg,
4578 Register temp2_reg,
4579 Label* L_success,
4580 Label* L_failure,
4581 bool set_cond_codes) {
4582 assert_different_registers(sub_klass, super_klass, temp_reg);
4583 if (temp2_reg != noreg)
4584 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
4585 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
4586
4587 Label L_fallthrough;
4588 int label_nulls = 0;
4589 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
4590 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
4591 assert(label_nulls <= 1, "at most one NULL in the batch");
4592
4593 // a couple of useful fields in sub_klass:
4594 int ss_offset = in_bytes(Klass::secondary_supers_offset());
4595 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4596 Address secondary_supers_addr(sub_klass, ss_offset);
4597 Address super_cache_addr( sub_klass, sc_offset);
4598
4599 // Do a linear scan of the secondary super-klass chain.
4600 // This code is rarely used, so simplicity is a virtue here.
4601 // The repne_scan instruction uses fixed registers, which we must spill.
4602 // Don't worry too much about pre-existing connections with the input regs.
4603
4604 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
4605 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
4606
4607 // Get super_klass value into rax (even if it was in rdi or rcx).
4608 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
4609 if (super_klass != rax || UseCompressedOops) {
4610 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
4611 mov(rax, super_klass);
4612 }
4613 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
4614 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
4615
4616 #ifndef PRODUCT
4617 int* pst_counter = &SharedRuntime::_partial_subtype_ctr;
4618 ExternalAddress pst_counter_addr((address) pst_counter);
4619 NOT_LP64( incrementl(pst_counter_addr) );
4620 LP64_ONLY( lea(rcx, pst_counter_addr) );
4621 LP64_ONLY( incrementl(Address(rcx, 0)) );
4622 #endif //PRODUCT
4623
4624 // We will consult the secondary-super array.
4625 movptr(rdi, secondary_supers_addr);
4626 // Load the array length. (Positive movl does right thing on LP64.)
4627 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
4628 // Skip to start of data.
4629 addptr(rdi, Array<Klass*>::base_offset_in_bytes());
4630
4631 // Scan RCX words at [RDI] for an occurrence of RAX.
4632 // Set NZ/Z based on last compare.
4633 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
4634 // not change flags (only scas instruction which is repeated sets flags).
4635 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
4636
4637 testptr(rax,rax); // Set Z = 0
4638 repne_scan();
4639
4640 // Unspill the temp. registers:
4641 if (pushed_rdi) pop(rdi);
4642 if (pushed_rcx) pop(rcx);
4643 if (pushed_rax) pop(rax);
4644
4645 if (set_cond_codes) {
4646 // Special hack for the AD files: rdi is guaranteed non-zero.
4647 assert(!pushed_rdi, "rdi must be left non-NULL");
4648 // Also, the condition codes are properly set Z/NZ on succeed/failure.
4649 }
4650
4651 if (L_failure == &L_fallthrough)
4652 jccb(Assembler::notEqual, *L_failure);
4653 else jcc(Assembler::notEqual, *L_failure);
4654
4655 // Success. Cache the super we found and proceed in triumph.
4656 movptr(super_cache_addr, super_klass);
4657
4658 if (L_success != &L_fallthrough) {
4659 jmp(*L_success);
4660 }
4661
4662 #undef IS_A_TEMP
4663
4664 bind(L_fallthrough);
4665 }
4666
4667
4668 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
4669 if (VM_Version::supports_cmov()) {
4670 cmovl(cc, dst, src);
4671 } else {
4672 Label L;
4673 jccb(negate_condition(cc), L);
4674 movl(dst, src);
4675 bind(L);
4676 }
4677 }
4678
4679 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
4680 if (VM_Version::supports_cmov()) {
4681 cmovl(cc, dst, src);
4682 } else {
4683 Label L;
4684 jccb(negate_condition(cc), L);
4685 movl(dst, src);
4686 bind(L);
4687 }
4688 }
4689
4690 void MacroAssembler::verify_oop(Register reg, const char* s) {
4691 if (!VerifyOops) return;
4692
4693 // Pass register number to verify_oop_subroutine
4694 const char* b = NULL;
4695 {
4696 ResourceMark rm;
4697 stringStream ss;
4698 ss.print("verify_oop: %s: %s", reg->name(), s);
4699 b = code_string(ss.as_string());
4700 }
4701 BLOCK_COMMENT("verify_oop {");
4702 #ifdef _LP64
4703 push(rscratch1); // save r10, trashed by movptr()
4704 #endif
4705 push(rax); // save rax,
4706 push(reg); // pass register argument
4707 ExternalAddress buffer((address) b);
4708 // avoid using pushptr, as it modifies scratch registers
4709 // and our contract is not to modify anything
4710 movptr(rax, buffer.addr());
4711 push(rax);
4712 // call indirectly to solve generation ordering problem
4713 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
4714 call(rax);
4715 // Caller pops the arguments (oop, message) and restores rax, r10
4716 BLOCK_COMMENT("} verify_oop");
4717 }
4718
4719
4720 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
4721 Register tmp,
4722 int offset) {
4723 intptr_t value = *delayed_value_addr;
4724 if (value != 0)
4725 return RegisterOrConstant(value + offset);
4726
4727 // load indirectly to solve generation ordering problem
4728 movptr(tmp, ExternalAddress((address) delayed_value_addr));
4729
4730 #ifdef ASSERT
4731 { Label L;
4732 testptr(tmp, tmp);
4733 if (WizardMode) {
4734 const char* buf = NULL;
4735 {
4736 ResourceMark rm;
4737 stringStream ss;
4738 ss.print("DelayedValue=" INTPTR_FORMAT, delayed_value_addr[1]);
4739 buf = code_string(ss.as_string());
4740 }
4741 jcc(Assembler::notZero, L);
4742 STOP(buf);
4743 } else {
4744 jccb(Assembler::notZero, L);
4745 hlt();
4746 }
4747 bind(L);
4748 }
4749 #endif
4750
4751 if (offset != 0)
4752 addptr(tmp, offset);
4753
4754 return RegisterOrConstant(tmp);
4755 }
4756
4757
4758 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
4759 int extra_slot_offset) {
4760 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
4761 int stackElementSize = Interpreter::stackElementSize;
4762 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
4763 #ifdef ASSERT
4764 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
4765 assert(offset1 - offset == stackElementSize, "correct arithmetic");
4766 #endif
4767 Register scale_reg = noreg;
4768 Address::ScaleFactor scale_factor = Address::no_scale;
4769 if (arg_slot.is_constant()) {
4770 offset += arg_slot.as_constant() * stackElementSize;
4771 } else {
4772 scale_reg = arg_slot.as_register();
4773 scale_factor = Address::times(stackElementSize);
4774 }
4775 offset += wordSize; // return PC is on stack
4776 return Address(rsp, scale_reg, scale_factor, offset);
4777 }
4778
4779
4780 void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
4781 if (!VerifyOops) return;
4782
4783 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord);
4784 // Pass register number to verify_oop_subroutine
4785 const char* b = NULL;
4786 {
4787 ResourceMark rm;
4788 stringStream ss;
4789 ss.print("verify_oop_addr: %s", s);
4790 b = code_string(ss.as_string());
4791 }
4792 #ifdef _LP64
4793 push(rscratch1); // save r10, trashed by movptr()
4794 #endif
4795 push(rax); // save rax,
4796 // addr may contain rsp so we will have to adjust it based on the push
4797 // we just did (and on 64 bit we do two pushes)
4798 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
4799 // stores rax into addr which is backwards of what was intended.
4800 if (addr.uses(rsp)) {
4801 lea(rax, addr);
4802 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord));
4803 } else {
4804 pushptr(addr);
4805 }
4806
4807 ExternalAddress buffer((address) b);
4808 // pass msg argument
4809 // avoid using pushptr, as it modifies scratch registers
4810 // and our contract is not to modify anything
4811 movptr(rax, buffer.addr());
4812 push(rax);
4813
4814 // call indirectly to solve generation ordering problem
4815 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
4816 call(rax);
4817 // Caller pops the arguments (addr, message) and restores rax, r10.
4818 }
4819
4820 void MacroAssembler::verify_tlab() {
4821 #ifdef ASSERT
4822 if (UseTLAB && VerifyOops) {
4823 Label next, ok;
4824 Register t1 = rsi;
4825 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
4826
4827 push(t1);
4828 NOT_LP64(push(thread_reg));
4829 NOT_LP64(get_thread(thread_reg));
4830
4831 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
4832 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
4833 jcc(Assembler::aboveEqual, next);
4834 STOP("assert(top >= start)");
4835 should_not_reach_here();
4836
4837 bind(next);
4838 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
4839 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
4840 jcc(Assembler::aboveEqual, ok);
4841 STOP("assert(top <= end)");
4842 should_not_reach_here();
4843
4844 bind(ok);
4845 NOT_LP64(pop(thread_reg));
4846 pop(t1);
4847 }
4848 #endif
4849 }
4850
4851 class ControlWord {
4852 public:
4853 int32_t _value;
4854
4855 int rounding_control() const { return (_value >> 10) & 3 ; }
4856 int precision_control() const { return (_value >> 8) & 3 ; }
4857 bool precision() const { return ((_value >> 5) & 1) != 0; }
4858 bool underflow() const { return ((_value >> 4) & 1) != 0; }
4859 bool overflow() const { return ((_value >> 3) & 1) != 0; }
4860 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
4861 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
4862 bool invalid() const { return ((_value >> 0) & 1) != 0; }
4863
4864 void print() const {
4865 // rounding control
4866 const char* rc;
4867 switch (rounding_control()) {
4868 case 0: rc = "round near"; break;
4869 case 1: rc = "round down"; break;
4870 case 2: rc = "round up "; break;
4871 case 3: rc = "chop "; break;
4872 };
4873 // precision control
4874 const char* pc;
4875 switch (precision_control()) {
4876 case 0: pc = "24 bits "; break;
4877 case 1: pc = "reserved"; break;
4878 case 2: pc = "53 bits "; break;
4879 case 3: pc = "64 bits "; break;
4880 };
4881 // flags
4882 char f[9];
4883 f[0] = ' ';
4884 f[1] = ' ';
4885 f[2] = (precision ()) ? 'P' : 'p';
4886 f[3] = (underflow ()) ? 'U' : 'u';
4887 f[4] = (overflow ()) ? 'O' : 'o';
4888 f[5] = (zero_divide ()) ? 'Z' : 'z';
4889 f[6] = (denormalized()) ? 'D' : 'd';
4890 f[7] = (invalid ()) ? 'I' : 'i';
4891 f[8] = '\x0';
4892 // output
4893 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
4894 }
4895
4896 };
4897
4898 class StatusWord {
4899 public:
4900 int32_t _value;
4901
4902 bool busy() const { return ((_value >> 15) & 1) != 0; }
4903 bool C3() const { return ((_value >> 14) & 1) != 0; }
4904 bool C2() const { return ((_value >> 10) & 1) != 0; }
4905 bool C1() const { return ((_value >> 9) & 1) != 0; }
4906 bool C0() const { return ((_value >> 8) & 1) != 0; }
4907 int top() const { return (_value >> 11) & 7 ; }
4908 bool error_status() const { return ((_value >> 7) & 1) != 0; }
4909 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
4910 bool precision() const { return ((_value >> 5) & 1) != 0; }
4911 bool underflow() const { return ((_value >> 4) & 1) != 0; }
4912 bool overflow() const { return ((_value >> 3) & 1) != 0; }
4913 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
4914 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
4915 bool invalid() const { return ((_value >> 0) & 1) != 0; }
4916
4917 void print() const {
4918 // condition codes
4919 char c[5];
4920 c[0] = (C3()) ? '3' : '-';
4921 c[1] = (C2()) ? '2' : '-';
4922 c[2] = (C1()) ? '1' : '-';
4923 c[3] = (C0()) ? '0' : '-';
4924 c[4] = '\x0';
4925 // flags
4926 char f[9];
4927 f[0] = (error_status()) ? 'E' : '-';
4928 f[1] = (stack_fault ()) ? 'S' : '-';
4929 f[2] = (precision ()) ? 'P' : '-';
4930 f[3] = (underflow ()) ? 'U' : '-';
4931 f[4] = (overflow ()) ? 'O' : '-';
4932 f[5] = (zero_divide ()) ? 'Z' : '-';
4933 f[6] = (denormalized()) ? 'D' : '-';
4934 f[7] = (invalid ()) ? 'I' : '-';
4935 f[8] = '\x0';
4936 // output
4937 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
4938 }
4939
4940 };
4941
4942 class TagWord {
4943 public:
4944 int32_t _value;
4945
4946 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
4947
4948 void print() const {
4949 printf("%04x", _value & 0xFFFF);
4950 }
4951
4952 };
4953
4954 class FPU_Register {
4955 public:
4956 int32_t _m0;
4957 int32_t _m1;
4958 int16_t _ex;
4959
4960 bool is_indefinite() const {
4961 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
4962 }
4963
4964 void print() const {
4965 char sign = (_ex < 0) ? '-' : '+';
4966 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
4967 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
4968 };
4969
4970 };
4971
4972 class FPU_State {
4973 public:
4974 enum {
4975 register_size = 10,
4976 number_of_registers = 8,
4977 register_mask = 7
4978 };
4979
4980 ControlWord _control_word;
4981 StatusWord _status_word;
4982 TagWord _tag_word;
4983 int32_t _error_offset;
4984 int32_t _error_selector;
4985 int32_t _data_offset;
4986 int32_t _data_selector;
4987 int8_t _register[register_size * number_of_registers];
4988
4989 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
4990 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
4991
4992 const char* tag_as_string(int tag) const {
4993 switch (tag) {
4994 case 0: return "valid";
4995 case 1: return "zero";
4996 case 2: return "special";
4997 case 3: return "empty";
4998 }
4999 ShouldNotReachHere();
5000 return NULL;
5001 }
5002
5003 void print() const {
5004 // print computation registers
5005 { int t = _status_word.top();
5006 for (int i = 0; i < number_of_registers; i++) {
5007 int j = (i - t) & register_mask;
5008 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
5009 st(j)->print();
5010 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
5011 }
5012 }
5013 printf("\n");
5014 // print control registers
5015 printf("ctrl = "); _control_word.print(); printf("\n");
5016 printf("stat = "); _status_word .print(); printf("\n");
5017 printf("tags = "); _tag_word .print(); printf("\n");
5018 }
5019
5020 };
5021
5022 class Flag_Register {
5023 public:
5024 int32_t _value;
5025
5026 bool overflow() const { return ((_value >> 11) & 1) != 0; }
5027 bool direction() const { return ((_value >> 10) & 1) != 0; }
5028 bool sign() const { return ((_value >> 7) & 1) != 0; }
5029 bool zero() const { return ((_value >> 6) & 1) != 0; }
5030 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
5031 bool parity() const { return ((_value >> 2) & 1) != 0; }
5032 bool carry() const { return ((_value >> 0) & 1) != 0; }
5033
5034 void print() const {
5035 // flags
5036 char f[8];
5037 f[0] = (overflow ()) ? 'O' : '-';
5038 f[1] = (direction ()) ? 'D' : '-';
5039 f[2] = (sign ()) ? 'S' : '-';
5040 f[3] = (zero ()) ? 'Z' : '-';
5041 f[4] = (auxiliary_carry()) ? 'A' : '-';
5042 f[5] = (parity ()) ? 'P' : '-';
5043 f[6] = (carry ()) ? 'C' : '-';
5044 f[7] = '\x0';
5045 // output
5046 printf("%08x flags = %s", _value, f);
5047 }
5048
5049 };
5050
5051 class IU_Register {
5052 public:
5053 int32_t _value;
5054
5055 void print() const {
5056 printf("%08x %11d", _value, _value);
5057 }
5058
5059 };
5060
5061 class IU_State {
5062 public:
5063 Flag_Register _eflags;
5064 IU_Register _rdi;
5065 IU_Register _rsi;
5066 IU_Register _rbp;
5067 IU_Register _rsp;
5068 IU_Register _rbx;
5069 IU_Register _rdx;
5070 IU_Register _rcx;
5071 IU_Register _rax;
5072
5073 void print() const {
5074 // computation registers
5075 printf("rax, = "); _rax.print(); printf("\n");
5076 printf("rbx, = "); _rbx.print(); printf("\n");
5077 printf("rcx = "); _rcx.print(); printf("\n");
5078 printf("rdx = "); _rdx.print(); printf("\n");
5079 printf("rdi = "); _rdi.print(); printf("\n");
5080 printf("rsi = "); _rsi.print(); printf("\n");
5081 printf("rbp, = "); _rbp.print(); printf("\n");
5082 printf("rsp = "); _rsp.print(); printf("\n");
5083 printf("\n");
5084 // control registers
5085 printf("flgs = "); _eflags.print(); printf("\n");
5086 }
5087 };
5088
5089
5090 class CPU_State {
5091 public:
5092 FPU_State _fpu_state;
5093 IU_State _iu_state;
5094
5095 void print() const {
5096 printf("--------------------------------------------------\n");
5097 _iu_state .print();
5098 printf("\n");
5099 _fpu_state.print();
5100 printf("--------------------------------------------------\n");
5101 }
5102
5103 };
5104
5105
5106 static void _print_CPU_state(CPU_State* state) {
5107 state->print();
5108 };
5109
5110
5111 void MacroAssembler::print_CPU_state() {
5112 push_CPU_state();
5113 push(rsp); // pass CPU state
5114 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
5115 addptr(rsp, wordSize); // discard argument
5116 pop_CPU_state();
5117 }
5118
5119
5120 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
5121 static int counter = 0;
5122 FPU_State* fs = &state->_fpu_state;
5123 counter++;
5124 // For leaf calls, only verify that the top few elements remain empty.
5125 // We only need 1 empty at the top for C2 code.
5126 if( stack_depth < 0 ) {
5127 if( fs->tag_for_st(7) != 3 ) {
5128 printf("FPR7 not empty\n");
5129 state->print();
5130 assert(false, "error");
5131 return false;
5132 }
5133 return true; // All other stack states do not matter
5134 }
5135
5136 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std,
5137 "bad FPU control word");
5138
5139 // compute stack depth
5140 int i = 0;
5141 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++;
5142 int d = i;
5143 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
5144 // verify findings
5145 if (i != FPU_State::number_of_registers) {
5146 // stack not contiguous
5147 printf("%s: stack not contiguous at ST%d\n", s, i);
5148 state->print();
5149 assert(false, "error");
5150 return false;
5151 }
5152 // check if computed stack depth corresponds to expected stack depth
5153 if (stack_depth < 0) {
5154 // expected stack depth is -stack_depth or less
5155 if (d > -stack_depth) {
5156 // too many elements on the stack
5157 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
5158 state->print();
5159 assert(false, "error");
5160 return false;
5161 }
5162 } else {
5163 // expected stack depth is stack_depth
5164 if (d != stack_depth) {
5165 // wrong stack depth
5166 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
5167 state->print();
5168 assert(false, "error");
5169 return false;
5170 }
5171 }
5172 // everything is cool
5173 return true;
5174 }
5175
5176
5177 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
5178 if (!VerifyFPU) return;
5179 push_CPU_state();
5180 push(rsp); // pass CPU state
5181 ExternalAddress msg((address) s);
5182 // pass message string s
5183 pushptr(msg.addr());
5184 push(stack_depth); // pass stack depth
5185 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
5186 addptr(rsp, 3 * wordSize); // discard arguments
5187 // check for error
5188 { Label L;
5189 testl(rax, rax);
5190 jcc(Assembler::notZero, L);
5191 int3(); // break if error condition
5192 bind(L);
5193 }
5194 pop_CPU_state();
5195 }
5196
5197 void MacroAssembler::restore_cpu_control_state_after_jni() {
5198 // Either restore the MXCSR register after returning from the JNI Call
5199 // or verify that it wasn't changed (with -Xcheck:jni flag).
5200 if (VM_Version::supports_sse()) {
5201 if (RestoreMXCSROnJNICalls) {
5202 ldmxcsr(ExternalAddress(StubRoutines::addr_mxcsr_std()));
5203 } else if (CheckJNICalls) {
5204 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
5205 }
5206 }
5207 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
5208 vzeroupper();
5209 // Reset k1 to 0xffff.
5210 if (VM_Version::supports_evex()) {
5211 push(rcx);
5212 movl(rcx, 0xffff);
5213 kmovwl(k1, rcx);
5214 pop(rcx);
5215 }
5216
5217 #ifndef _LP64
5218 // Either restore the x87 floating pointer control word after returning
5219 // from the JNI call or verify that it wasn't changed.
5220 if (CheckJNICalls) {
5221 call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry()));
5222 }
5223 #endif // _LP64
5224 }
5225
5226 // ((OopHandle)result).resolve();
5227 void MacroAssembler::resolve_oop_handle(Register result, Register tmp) {
5228 assert_different_registers(result, tmp);
5229
5230 // Only 64 bit platforms support GCs that require a tmp register
5231 // Only IN_HEAP loads require a thread_tmp register
5232 // OopHandle::resolve is an indirection like jobject.
5233 access_load_at(T_OBJECT, IN_NATIVE,
5234 result, Address(result, 0), tmp, /*tmp_thread*/noreg);
5235 }
5236
5237 void MacroAssembler::load_mirror(Register mirror, Register method, Register tmp) {
5238 // get mirror
5239 const int mirror_offset = in_bytes(Klass::java_mirror_offset());
5240 movptr(mirror, Address(method, Method::const_offset()));
5241 movptr(mirror, Address(mirror, ConstMethod::constants_offset()));
5242 movptr(mirror, Address(mirror, ConstantPool::pool_holder_offset_in_bytes()));
5243 movptr(mirror, Address(mirror, mirror_offset));
5244 resolve_oop_handle(mirror, tmp);
5245 }
5246
5247 void MacroAssembler::load_klass(Register dst, Register src) {
5248 #ifdef _LP64
5249 if (UseCompressedClassPointers) {
5250 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5251 decode_klass_not_null(dst);
5252 } else
5253 #endif
5254 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5255 }
5256
5257 void MacroAssembler::load_prototype_header(Register dst, Register src) {
5258 load_klass(dst, src);
5259 movptr(dst, Address(dst, Klass::prototype_header_offset()));
5260 }
5261
5262 void MacroAssembler::store_klass(Register dst, Register src) {
5263 #ifdef _LP64
5264 if (UseCompressedClassPointers) {
5265 encode_klass_not_null(src);
5266 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5267 } else
5268 #endif
5269 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5270 }
5271
5272 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
5273 Register tmp1, Register thread_tmp) {
5274 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5275 decorators = AccessInternal::decorator_fixup(decorators);
5276 bool as_raw = (decorators & AS_RAW) != 0;
5277 if (as_raw) {
5278 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
5279 } else {
5280 bs->load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
5281 }
5282 }
5283
5284 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
5285 Register tmp1, Register tmp2) {
5286 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5287 decorators = AccessInternal::decorator_fixup(decorators);
5288 bool as_raw = (decorators & AS_RAW) != 0;
5289 if (as_raw) {
5290 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, src, tmp1, tmp2);
5291 } else {
5292 bs->store_at(this, decorators, type, dst, src, tmp1, tmp2);
5293 }
5294 }
5295
5296 void MacroAssembler::resolve(DecoratorSet decorators, Register obj) {
5297 // Use stronger ACCESS_WRITE|ACCESS_READ by default.
5298 if ((decorators & (ACCESS_READ | ACCESS_WRITE)) == 0) {
5299 decorators |= ACCESS_READ | ACCESS_WRITE;
5300 }
5301 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5302 return bs->resolve(this, decorators, obj);
5303 }
5304
5305 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1,
5306 Register thread_tmp, DecoratorSet decorators) {
5307 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, thread_tmp);
5308 }
5309
5310 // Doesn't do verfication, generates fixed size code
5311 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1,
5312 Register thread_tmp, DecoratorSet decorators) {
5313 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, thread_tmp);
5314 }
5315
5316 void MacroAssembler::store_heap_oop(Address dst, Register src, Register tmp1,
5317 Register tmp2, DecoratorSet decorators) {
5318 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, tmp2);
5319 }
5320
5321 // Used for storing NULLs.
5322 void MacroAssembler::store_heap_oop_null(Address dst) {
5323 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg);
5324 }
5325
5326 #ifdef _LP64
5327 void MacroAssembler::store_klass_gap(Register dst, Register src) {
5328 if (UseCompressedClassPointers) {
5329 // Store to klass gap in destination
5330 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
5331 }
5332 }
5333
5334 #ifdef ASSERT
5335 void MacroAssembler::verify_heapbase(const char* msg) {
5336 assert (UseCompressedOops, "should be compressed");
5337 assert (Universe::heap() != NULL, "java heap should be initialized");
5338 if (CheckCompressedOops) {
5339 Label ok;
5340 push(rscratch1); // cmpptr trashes rscratch1
5341 cmpptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
5342 jcc(Assembler::equal, ok);
5343 STOP(msg);
5344 bind(ok);
5345 pop(rscratch1);
5346 }
5347 }
5348 #endif
5349
5350 // Algorithm must match oop.inline.hpp encode_heap_oop.
5351 void MacroAssembler::encode_heap_oop(Register r) {
5352 #ifdef ASSERT
5353 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
5354 #endif
5355 verify_oop(r, "broken oop in encode_heap_oop");
5356 if (Universe::narrow_oop_base() == NULL) {
5357 if (Universe::narrow_oop_shift() != 0) {
5358 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5359 shrq(r, LogMinObjAlignmentInBytes);
5360 }
5361 return;
5362 }
5363 testq(r, r);
5364 cmovq(Assembler::equal, r, r12_heapbase);
5365 subq(r, r12_heapbase);
5366 shrq(r, LogMinObjAlignmentInBytes);
5367 }
5368
5369 void MacroAssembler::encode_heap_oop_not_null(Register r) {
5370 #ifdef ASSERT
5371 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
5372 if (CheckCompressedOops) {
5373 Label ok;
5374 testq(r, r);
5375 jcc(Assembler::notEqual, ok);
5376 STOP("null oop passed to encode_heap_oop_not_null");
5377 bind(ok);
5378 }
5379 #endif
5380 verify_oop(r, "broken oop in encode_heap_oop_not_null");
5381 if (Universe::narrow_oop_base() != NULL) {
5382 subq(r, r12_heapbase);
5383 }
5384 if (Universe::narrow_oop_shift() != 0) {
5385 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5386 shrq(r, LogMinObjAlignmentInBytes);
5387 }
5388 }
5389
5390 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
5391 #ifdef ASSERT
5392 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
5393 if (CheckCompressedOops) {
5394 Label ok;
5395 testq(src, src);
5396 jcc(Assembler::notEqual, ok);
5397 STOP("null oop passed to encode_heap_oop_not_null2");
5398 bind(ok);
5399 }
5400 #endif
5401 verify_oop(src, "broken oop in encode_heap_oop_not_null2");
5402 if (dst != src) {
5403 movq(dst, src);
5404 }
5405 if (Universe::narrow_oop_base() != NULL) {
5406 subq(dst, r12_heapbase);
5407 }
5408 if (Universe::narrow_oop_shift() != 0) {
5409 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5410 shrq(dst, LogMinObjAlignmentInBytes);
5411 }
5412 }
5413
5414 void MacroAssembler::decode_heap_oop(Register r) {
5415 #ifdef ASSERT
5416 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
5417 #endif
5418 if (Universe::narrow_oop_base() == NULL) {
5419 if (Universe::narrow_oop_shift() != 0) {
5420 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5421 shlq(r, LogMinObjAlignmentInBytes);
5422 }
5423 } else {
5424 Label done;
5425 shlq(r, LogMinObjAlignmentInBytes);
5426 jccb(Assembler::equal, done);
5427 addq(r, r12_heapbase);
5428 bind(done);
5429 }
5430 verify_oop(r, "broken oop in decode_heap_oop");
5431 }
5432
5433 void MacroAssembler::decode_heap_oop_not_null(Register r) {
5434 // Note: it will change flags
5435 assert (UseCompressedOops, "should only be used for compressed headers");
5436 assert (Universe::heap() != NULL, "java heap should be initialized");
5437 // Cannot assert, unverified entry point counts instructions (see .ad file)
5438 // vtableStubs also counts instructions in pd_code_size_limit.
5439 // Also do not verify_oop as this is called by verify_oop.
5440 if (Universe::narrow_oop_shift() != 0) {
5441 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5442 shlq(r, LogMinObjAlignmentInBytes);
5443 if (Universe::narrow_oop_base() != NULL) {
5444 addq(r, r12_heapbase);
5445 }
5446 } else {
5447 assert (Universe::narrow_oop_base() == NULL, "sanity");
5448 }
5449 }
5450
5451 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
5452 // Note: it will change flags
5453 assert (UseCompressedOops, "should only be used for compressed headers");
5454 assert (Universe::heap() != NULL, "java heap should be initialized");
5455 // Cannot assert, unverified entry point counts instructions (see .ad file)
5456 // vtableStubs also counts instructions in pd_code_size_limit.
5457 // Also do not verify_oop as this is called by verify_oop.
5458 if (Universe::narrow_oop_shift() != 0) {
5459 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5460 if (LogMinObjAlignmentInBytes == Address::times_8) {
5461 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
5462 } else {
5463 if (dst != src) {
5464 movq(dst, src);
5465 }
5466 shlq(dst, LogMinObjAlignmentInBytes);
5467 if (Universe::narrow_oop_base() != NULL) {
5468 addq(dst, r12_heapbase);
5469 }
5470 }
5471 } else {
5472 assert (Universe::narrow_oop_base() == NULL, "sanity");
5473 if (dst != src) {
5474 movq(dst, src);
5475 }
5476 }
5477 }
5478
5479 void MacroAssembler::encode_klass_not_null(Register r) {
5480 if (Universe::narrow_klass_base() != NULL) {
5481 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
5482 assert(r != r12_heapbase, "Encoding a klass in r12");
5483 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
5484 subq(r, r12_heapbase);
5485 }
5486 if (Universe::narrow_klass_shift() != 0) {
5487 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
5488 shrq(r, LogKlassAlignmentInBytes);
5489 }
5490 if (Universe::narrow_klass_base() != NULL) {
5491 reinit_heapbase();
5492 }
5493 }
5494
5495 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
5496 if (dst == src) {
5497 encode_klass_not_null(src);
5498 } else {
5499 if (Universe::narrow_klass_base() != NULL) {
5500 mov64(dst, (int64_t)Universe::narrow_klass_base());
5501 negq(dst);
5502 addq(dst, src);
5503 } else {
5504 movptr(dst, src);
5505 }
5506 if (Universe::narrow_klass_shift() != 0) {
5507 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
5508 shrq(dst, LogKlassAlignmentInBytes);
5509 }
5510 }
5511 }
5512
5513 // Function instr_size_for_decode_klass_not_null() counts the instructions
5514 // generated by decode_klass_not_null(register r) and reinit_heapbase(),
5515 // when (Universe::heap() != NULL). Hence, if the instructions they
5516 // generate change, then this method needs to be updated.
5517 int MacroAssembler::instr_size_for_decode_klass_not_null() {
5518 assert (UseCompressedClassPointers, "only for compressed klass ptrs");
5519 if (Universe::narrow_klass_base() != NULL) {
5520 // mov64 + addq + shlq? + mov64 (for reinit_heapbase()).
5521 return (Universe::narrow_klass_shift() == 0 ? 20 : 24);
5522 } else {
5523 // longest load decode klass function, mov64, leaq
5524 return 16;
5525 }
5526 }
5527
5528 // !!! If the instructions that get generated here change then function
5529 // instr_size_for_decode_klass_not_null() needs to get updated.
5530 void MacroAssembler::decode_klass_not_null(Register r) {
5531 // Note: it will change flags
5532 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5533 assert(r != r12_heapbase, "Decoding a klass in r12");
5534 // Cannot assert, unverified entry point counts instructions (see .ad file)
5535 // vtableStubs also counts instructions in pd_code_size_limit.
5536 // Also do not verify_oop as this is called by verify_oop.
5537 if (Universe::narrow_klass_shift() != 0) {
5538 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
5539 shlq(r, LogKlassAlignmentInBytes);
5540 }
5541 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
5542 if (Universe::narrow_klass_base() != NULL) {
5543 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
5544 addq(r, r12_heapbase);
5545 reinit_heapbase();
5546 }
5547 }
5548
5549 void MacroAssembler::decode_klass_not_null(Register dst, Register src) {
5550 // Note: it will change flags
5551 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5552 if (dst == src) {
5553 decode_klass_not_null(dst);
5554 } else {
5555 // Cannot assert, unverified entry point counts instructions (see .ad file)
5556 // vtableStubs also counts instructions in pd_code_size_limit.
5557 // Also do not verify_oop as this is called by verify_oop.
5558 mov64(dst, (int64_t)Universe::narrow_klass_base());
5559 if (Universe::narrow_klass_shift() != 0) {
5560 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
5561 assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?");
5562 leaq(dst, Address(dst, src, Address::times_8, 0));
5563 } else {
5564 addq(dst, src);
5565 }
5566 }
5567 }
5568
5569 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
5570 assert (UseCompressedOops, "should only be used for compressed headers");
5571 assert (Universe::heap() != NULL, "java heap should be initialized");
5572 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5573 int oop_index = oop_recorder()->find_index(obj);
5574 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5575 mov_narrow_oop(dst, oop_index, rspec);
5576 }
5577
5578 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
5579 assert (UseCompressedOops, "should only be used for compressed headers");
5580 assert (Universe::heap() != NULL, "java heap should be initialized");
5581 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5582 int oop_index = oop_recorder()->find_index(obj);
5583 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5584 mov_narrow_oop(dst, oop_index, rspec);
5585 }
5586
5587 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
5588 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5589 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5590 int klass_index = oop_recorder()->find_index(k);
5591 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5592 mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
5593 }
5594
5595 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
5596 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5597 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5598 int klass_index = oop_recorder()->find_index(k);
5599 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5600 mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
5601 }
5602
5603 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
5604 assert (UseCompressedOops, "should only be used for compressed headers");
5605 assert (Universe::heap() != NULL, "java heap should be initialized");
5606 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5607 int oop_index = oop_recorder()->find_index(obj);
5608 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5609 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
5610 }
5611
5612 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
5613 assert (UseCompressedOops, "should only be used for compressed headers");
5614 assert (Universe::heap() != NULL, "java heap should be initialized");
5615 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5616 int oop_index = oop_recorder()->find_index(obj);
5617 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5618 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
5619 }
5620
5621 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
5622 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5623 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5624 int klass_index = oop_recorder()->find_index(k);
5625 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5626 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
5627 }
5628
5629 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
5630 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5631 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5632 int klass_index = oop_recorder()->find_index(k);
5633 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5634 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
5635 }
5636
5637 void MacroAssembler::reinit_heapbase() {
5638 if (UseCompressedOops || UseCompressedClassPointers) {
5639 if (Universe::heap() != NULL) {
5640 if (Universe::narrow_oop_base() == NULL) {
5641 MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
5642 } else {
5643 mov64(r12_heapbase, (int64_t)Universe::narrow_ptrs_base());
5644 }
5645 } else {
5646 movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
5647 }
5648 }
5649 }
5650
5651 #endif // _LP64
5652
5653 // C2 compiled method's prolog code.
5654 void MacroAssembler::verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b) {
5655
5656 // WARNING: Initial instruction MUST be 5 bytes or longer so that
5657 // NativeJump::patch_verified_entry will be able to patch out the entry
5658 // code safely. The push to verify stack depth is ok at 5 bytes,
5659 // the frame allocation can be either 3 or 6 bytes. So if we don't do
5660 // stack bang then we must use the 6 byte frame allocation even if
5661 // we have no frame. :-(
5662 assert(stack_bang_size >= framesize || stack_bang_size <= 0, "stack bang size incorrect");
5663
5664 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
5665 // Remove word for return addr
5666 framesize -= wordSize;
5667 stack_bang_size -= wordSize;
5668
5669 // Calls to C2R adapters often do not accept exceptional returns.
5670 // We require that their callers must bang for them. But be careful, because
5671 // some VM calls (such as call site linkage) can use several kilobytes of
5672 // stack. But the stack safety zone should account for that.
5673 // See bugs 4446381, 4468289, 4497237.
5674 if (stack_bang_size > 0) {
5675 generate_stack_overflow_check(stack_bang_size);
5676
5677 // We always push rbp, so that on return to interpreter rbp, will be
5678 // restored correctly and we can correct the stack.
5679 push(rbp);
5680 // Save caller's stack pointer into RBP if the frame pointer is preserved.
5681 if (PreserveFramePointer) {
5682 mov(rbp, rsp);
5683 }
5684 // Remove word for ebp
5685 framesize -= wordSize;
5686
5687 // Create frame
5688 if (framesize) {
5689 subptr(rsp, framesize);
5690 }
5691 } else {
5692 // Create frame (force generation of a 4 byte immediate value)
5693 subptr_imm32(rsp, framesize);
5694
5695 // Save RBP register now.
5696 framesize -= wordSize;
5697 movptr(Address(rsp, framesize), rbp);
5698 // Save caller's stack pointer into RBP if the frame pointer is preserved.
5699 if (PreserveFramePointer) {
5700 movptr(rbp, rsp);
5701 if (framesize > 0) {
5702 addptr(rbp, framesize);
5703 }
5704 }
5705 }
5706
5707 if (VerifyStackAtCalls) { // Majik cookie to verify stack depth
5708 framesize -= wordSize;
5709 movptr(Address(rsp, framesize), (int32_t)0xbadb100d);
5710 }
5711
5712 #ifndef _LP64
5713 // If method sets FPU control word do it now
5714 if (fp_mode_24b) {
5715 fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
5716 }
5717 if (UseSSE >= 2 && VerifyFPU) {
5718 verify_FPU(0, "FPU stack must be clean on entry");
5719 }
5720 #endif
5721
5722 #ifdef ASSERT
5723 if (VerifyStackAtCalls) {
5724 Label L;
5725 push(rax);
5726 mov(rax, rsp);
5727 andptr(rax, StackAlignmentInBytes-1);
5728 cmpptr(rax, StackAlignmentInBytes-wordSize);
5729 pop(rax);
5730 jcc(Assembler::equal, L);
5731 STOP("Stack is not properly aligned!");
5732 bind(L);
5733 }
5734 #endif
5735
5736 }
5737
5738 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM registers
5739 void MacroAssembler::xmm_clear_mem(Register base, Register cnt, XMMRegister xtmp) {
5740 // cnt - number of qwords (8-byte words).
5741 // base - start address, qword aligned.
5742 Label L_zero_64_bytes, L_loop, L_sloop, L_tail, L_end;
5743 if (UseAVX >= 2) {
5744 vpxor(xtmp, xtmp, xtmp, AVX_256bit);
5745 } else {
5746 pxor(xtmp, xtmp);
5747 }
5748 jmp(L_zero_64_bytes);
5749
5750 BIND(L_loop);
5751 if (UseAVX >= 2) {
5752 vmovdqu(Address(base, 0), xtmp);
5753 vmovdqu(Address(base, 32), xtmp);
5754 } else {
5755 movdqu(Address(base, 0), xtmp);
5756 movdqu(Address(base, 16), xtmp);
5757 movdqu(Address(base, 32), xtmp);
5758 movdqu(Address(base, 48), xtmp);
5759 }
5760 addptr(base, 64);
5761
5762 BIND(L_zero_64_bytes);
5763 subptr(cnt, 8);
5764 jccb(Assembler::greaterEqual, L_loop);
5765 addptr(cnt, 4);
5766 jccb(Assembler::less, L_tail);
5767 // Copy trailing 32 bytes
5768 if (UseAVX >= 2) {
5769 vmovdqu(Address(base, 0), xtmp);
5770 } else {
5771 movdqu(Address(base, 0), xtmp);
5772 movdqu(Address(base, 16), xtmp);
5773 }
5774 addptr(base, 32);
5775 subptr(cnt, 4);
5776
5777 BIND(L_tail);
5778 addptr(cnt, 4);
5779 jccb(Assembler::lessEqual, L_end);
5780 decrement(cnt);
5781
5782 BIND(L_sloop);
5783 movq(Address(base, 0), xtmp);
5784 addptr(base, 8);
5785 decrement(cnt);
5786 jccb(Assembler::greaterEqual, L_sloop);
5787 BIND(L_end);
5788 }
5789
5790 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp, XMMRegister xtmp, bool is_large) {
5791 // cnt - number of qwords (8-byte words).
5792 // base - start address, qword aligned.
5793 // is_large - if optimizers know cnt is larger than InitArrayShortSize
5794 assert(base==rdi, "base register must be edi for rep stos");
5795 assert(tmp==rax, "tmp register must be eax for rep stos");
5796 assert(cnt==rcx, "cnt register must be ecx for rep stos");
5797 assert(InitArrayShortSize % BytesPerLong == 0,
5798 "InitArrayShortSize should be the multiple of BytesPerLong");
5799
5800 Label DONE;
5801
5802 if (!is_large || !UseXMMForObjInit) {
5803 xorptr(tmp, tmp);
5804 }
5805
5806 if (!is_large) {
5807 Label LOOP, LONG;
5808 cmpptr(cnt, InitArrayShortSize/BytesPerLong);
5809 jccb(Assembler::greater, LONG);
5810
5811 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
5812
5813 decrement(cnt);
5814 jccb(Assembler::negative, DONE); // Zero length
5815
5816 // Use individual pointer-sized stores for small counts:
5817 BIND(LOOP);
5818 movptr(Address(base, cnt, Address::times_ptr), tmp);
5819 decrement(cnt);
5820 jccb(Assembler::greaterEqual, LOOP);
5821 jmpb(DONE);
5822
5823 BIND(LONG);
5824 }
5825
5826 // Use longer rep-prefixed ops for non-small counts:
5827 if (UseFastStosb) {
5828 shlptr(cnt, 3); // convert to number of bytes
5829 rep_stosb();
5830 } else if (UseXMMForObjInit) {
5831 movptr(tmp, base);
5832 xmm_clear_mem(tmp, cnt, xtmp);
5833 } else {
5834 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
5835 rep_stos();
5836 }
5837
5838 BIND(DONE);
5839 }
5840
5841 #ifdef COMPILER2
5842
5843 // IndexOf for constant substrings with size >= 8 chars
5844 // which don't need to be loaded through stack.
5845 void MacroAssembler::string_indexofC8(Register str1, Register str2,
5846 Register cnt1, Register cnt2,
5847 int int_cnt2, Register result,
5848 XMMRegister vec, Register tmp,
5849 int ae) {
5850 ShortBranchVerifier sbv(this);
5851 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
5852 assert(ae != StrIntrinsicNode::LU, "Invalid encoding");
5853
5854 // This method uses the pcmpestri instruction with bound registers
5855 // inputs:
5856 // xmm - substring
5857 // rax - substring length (elements count)
5858 // mem - scanned string
5859 // rdx - string length (elements count)
5860 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
5861 // 0xc - mode: 1100 (substring search) + 00 (unsigned bytes)
5862 // outputs:
5863 // rcx - matched index in string
5864 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
5865 int mode = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts
5866 int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8
5867 Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2;
5868 Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1;
5869
5870 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR,
5871 RET_FOUND, RET_NOT_FOUND, EXIT, FOUND_SUBSTR,
5872 MATCH_SUBSTR_HEAD, RELOAD_STR, FOUND_CANDIDATE;
5873
5874 // Note, inline_string_indexOf() generates checks:
5875 // if (substr.count > string.count) return -1;
5876 // if (substr.count == 0) return 0;
5877 assert(int_cnt2 >= stride, "this code is used only for cnt2 >= 8 chars");
5878
5879 // Load substring.
5880 if (ae == StrIntrinsicNode::UL) {
5881 pmovzxbw(vec, Address(str2, 0));
5882 } else {
5883 movdqu(vec, Address(str2, 0));
5884 }
5885 movl(cnt2, int_cnt2);
5886 movptr(result, str1); // string addr
5887
5888 if (int_cnt2 > stride) {
5889 jmpb(SCAN_TO_SUBSTR);
5890
5891 // Reload substr for rescan, this code
5892 // is executed only for large substrings (> 8 chars)
5893 bind(RELOAD_SUBSTR);
5894 if (ae == StrIntrinsicNode::UL) {
5895 pmovzxbw(vec, Address(str2, 0));
5896 } else {
5897 movdqu(vec, Address(str2, 0));
5898 }
5899 negptr(cnt2); // Jumped here with negative cnt2, convert to positive
5900
5901 bind(RELOAD_STR);
5902 // We came here after the beginning of the substring was
5903 // matched but the rest of it was not so we need to search
5904 // again. Start from the next element after the previous match.
5905
5906 // cnt2 is number of substring reminding elements and
5907 // cnt1 is number of string reminding elements when cmp failed.
5908 // Restored cnt1 = cnt1 - cnt2 + int_cnt2
5909 subl(cnt1, cnt2);
5910 addl(cnt1, int_cnt2);
5911 movl(cnt2, int_cnt2); // Now restore cnt2
5912
5913 decrementl(cnt1); // Shift to next element
5914 cmpl(cnt1, cnt2);
5915 jcc(Assembler::negative, RET_NOT_FOUND); // Left less then substring
5916
5917 addptr(result, (1<<scale1));
5918
5919 } // (int_cnt2 > 8)
5920
5921 // Scan string for start of substr in 16-byte vectors
5922 bind(SCAN_TO_SUBSTR);
5923 pcmpestri(vec, Address(result, 0), mode);
5924 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
5925 subl(cnt1, stride);
5926 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
5927 cmpl(cnt1, cnt2);
5928 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
5929 addptr(result, 16);
5930 jmpb(SCAN_TO_SUBSTR);
5931
5932 // Found a potential substr
5933 bind(FOUND_CANDIDATE);
5934 // Matched whole vector if first element matched (tmp(rcx) == 0).
5935 if (int_cnt2 == stride) {
5936 jccb(Assembler::overflow, RET_FOUND); // OF == 1
5937 } else { // int_cnt2 > 8
5938 jccb(Assembler::overflow, FOUND_SUBSTR);
5939 }
5940 // After pcmpestri tmp(rcx) contains matched element index
5941 // Compute start addr of substr
5942 lea(result, Address(result, tmp, scale1));
5943
5944 // Make sure string is still long enough
5945 subl(cnt1, tmp);
5946 cmpl(cnt1, cnt2);
5947 if (int_cnt2 == stride) {
5948 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
5949 } else { // int_cnt2 > 8
5950 jccb(Assembler::greaterEqual, MATCH_SUBSTR_HEAD);
5951 }
5952 // Left less then substring.
5953
5954 bind(RET_NOT_FOUND);
5955 movl(result, -1);
5956 jmp(EXIT);
5957
5958 if (int_cnt2 > stride) {
5959 // This code is optimized for the case when whole substring
5960 // is matched if its head is matched.
5961 bind(MATCH_SUBSTR_HEAD);
5962 pcmpestri(vec, Address(result, 0), mode);
5963 // Reload only string if does not match
5964 jcc(Assembler::noOverflow, RELOAD_STR); // OF == 0
5965
5966 Label CONT_SCAN_SUBSTR;
5967 // Compare the rest of substring (> 8 chars).
5968 bind(FOUND_SUBSTR);
5969 // First 8 chars are already matched.
5970 negptr(cnt2);
5971 addptr(cnt2, stride);
5972
5973 bind(SCAN_SUBSTR);
5974 subl(cnt1, stride);
5975 cmpl(cnt2, -stride); // Do not read beyond substring
5976 jccb(Assembler::lessEqual, CONT_SCAN_SUBSTR);
5977 // Back-up strings to avoid reading beyond substring:
5978 // cnt1 = cnt1 - cnt2 + 8
5979 addl(cnt1, cnt2); // cnt2 is negative
5980 addl(cnt1, stride);
5981 movl(cnt2, stride); negptr(cnt2);
5982 bind(CONT_SCAN_SUBSTR);
5983 if (int_cnt2 < (int)G) {
5984 int tail_off1 = int_cnt2<<scale1;
5985 int tail_off2 = int_cnt2<<scale2;
5986 if (ae == StrIntrinsicNode::UL) {
5987 pmovzxbw(vec, Address(str2, cnt2, scale2, tail_off2));
5988 } else {
5989 movdqu(vec, Address(str2, cnt2, scale2, tail_off2));
5990 }
5991 pcmpestri(vec, Address(result, cnt2, scale1, tail_off1), mode);
5992 } else {
5993 // calculate index in register to avoid integer overflow (int_cnt2*2)
5994 movl(tmp, int_cnt2);
5995 addptr(tmp, cnt2);
5996 if (ae == StrIntrinsicNode::UL) {
5997 pmovzxbw(vec, Address(str2, tmp, scale2, 0));
5998 } else {
5999 movdqu(vec, Address(str2, tmp, scale2, 0));
6000 }
6001 pcmpestri(vec, Address(result, tmp, scale1, 0), mode);
6002 }
6003 // Need to reload strings pointers if not matched whole vector
6004 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
6005 addptr(cnt2, stride);
6006 jcc(Assembler::negative, SCAN_SUBSTR);
6007 // Fall through if found full substring
6008
6009 } // (int_cnt2 > 8)
6010
6011 bind(RET_FOUND);
6012 // Found result if we matched full small substring.
6013 // Compute substr offset
6014 subptr(result, str1);
6015 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
6016 shrl(result, 1); // index
6017 }
6018 bind(EXIT);
6019
6020 } // string_indexofC8
6021
6022 // Small strings are loaded through stack if they cross page boundary.
6023 void MacroAssembler::string_indexof(Register str1, Register str2,
6024 Register cnt1, Register cnt2,
6025 int int_cnt2, Register result,
6026 XMMRegister vec, Register tmp,
6027 int ae) {
6028 ShortBranchVerifier sbv(this);
6029 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
6030 assert(ae != StrIntrinsicNode::LU, "Invalid encoding");
6031
6032 //
6033 // int_cnt2 is length of small (< 8 chars) constant substring
6034 // or (-1) for non constant substring in which case its length
6035 // is in cnt2 register.
6036 //
6037 // Note, inline_string_indexOf() generates checks:
6038 // if (substr.count > string.count) return -1;
6039 // if (substr.count == 0) return 0;
6040 //
6041 int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8
6042 assert(int_cnt2 == -1 || (0 < int_cnt2 && int_cnt2 < stride), "should be != 0");
6043 // This method uses the pcmpestri instruction with bound registers
6044 // inputs:
6045 // xmm - substring
6046 // rax - substring length (elements count)
6047 // mem - scanned string
6048 // rdx - string length (elements count)
6049 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
6050 // 0xc - mode: 1100 (substring search) + 00 (unsigned bytes)
6051 // outputs:
6052 // rcx - matched index in string
6053 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
6054 int mode = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts
6055 Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2;
6056 Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1;
6057
6058 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, ADJUST_STR,
6059 RET_FOUND, RET_NOT_FOUND, CLEANUP, FOUND_SUBSTR,
6060 FOUND_CANDIDATE;
6061
6062 { //========================================================
6063 // We don't know where these strings are located
6064 // and we can't read beyond them. Load them through stack.
6065 Label BIG_STRINGS, CHECK_STR, COPY_SUBSTR, COPY_STR;
6066
6067 movptr(tmp, rsp); // save old SP
6068
6069 if (int_cnt2 > 0) { // small (< 8 chars) constant substring
6070 if (int_cnt2 == (1>>scale2)) { // One byte
6071 assert((ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL), "Only possible for latin1 encoding");
6072 load_unsigned_byte(result, Address(str2, 0));
6073 movdl(vec, result); // move 32 bits
6074 } else if (ae == StrIntrinsicNode::LL && int_cnt2 == 3) { // Three bytes
6075 // Not enough header space in 32-bit VM: 12+3 = 15.
6076 movl(result, Address(str2, -1));
6077 shrl(result, 8);
6078 movdl(vec, result); // move 32 bits
6079 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (2>>scale2)) { // One char
6080 load_unsigned_short(result, Address(str2, 0));
6081 movdl(vec, result); // move 32 bits
6082 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (4>>scale2)) { // Two chars
6083 movdl(vec, Address(str2, 0)); // move 32 bits
6084 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (8>>scale2)) { // Four chars
6085 movq(vec, Address(str2, 0)); // move 64 bits
6086 } else { // cnt2 = { 3, 5, 6, 7 } || (ae == StrIntrinsicNode::UL && cnt2 ={2, ..., 7})
6087 // Array header size is 12 bytes in 32-bit VM
6088 // + 6 bytes for 3 chars == 18 bytes,
6089 // enough space to load vec and shift.
6090 assert(HeapWordSize*TypeArrayKlass::header_size() >= 12,"sanity");
6091 if (ae == StrIntrinsicNode::UL) {
6092 int tail_off = int_cnt2-8;
6093 pmovzxbw(vec, Address(str2, tail_off));
6094 psrldq(vec, -2*tail_off);
6095 }
6096 else {
6097 int tail_off = int_cnt2*(1<<scale2);
6098 movdqu(vec, Address(str2, tail_off-16));
6099 psrldq(vec, 16-tail_off);
6100 }
6101 }
6102 } else { // not constant substring
6103 cmpl(cnt2, stride);
6104 jccb(Assembler::aboveEqual, BIG_STRINGS); // Both strings are big enough
6105
6106 // We can read beyond string if srt+16 does not cross page boundary
6107 // since heaps are aligned and mapped by pages.
6108 assert(os::vm_page_size() < (int)G, "default page should be small");
6109 movl(result, str2); // We need only low 32 bits
6110 andl(result, (os::vm_page_size()-1));
6111 cmpl(result, (os::vm_page_size()-16));
6112 jccb(Assembler::belowEqual, CHECK_STR);
6113
6114 // Move small strings to stack to allow load 16 bytes into vec.
6115 subptr(rsp, 16);
6116 int stk_offset = wordSize-(1<<scale2);
6117 push(cnt2);
6118
6119 bind(COPY_SUBSTR);
6120 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL) {
6121 load_unsigned_byte(result, Address(str2, cnt2, scale2, -1));
6122 movb(Address(rsp, cnt2, scale2, stk_offset), result);
6123 } else if (ae == StrIntrinsicNode::UU) {
6124 load_unsigned_short(result, Address(str2, cnt2, scale2, -2));
6125 movw(Address(rsp, cnt2, scale2, stk_offset), result);
6126 }
6127 decrement(cnt2);
6128 jccb(Assembler::notZero, COPY_SUBSTR);
6129
6130 pop(cnt2);
6131 movptr(str2, rsp); // New substring address
6132 } // non constant
6133
6134 bind(CHECK_STR);
6135 cmpl(cnt1, stride);
6136 jccb(Assembler::aboveEqual, BIG_STRINGS);
6137
6138 // Check cross page boundary.
6139 movl(result, str1); // We need only low 32 bits
6140 andl(result, (os::vm_page_size()-1));
6141 cmpl(result, (os::vm_page_size()-16));
6142 jccb(Assembler::belowEqual, BIG_STRINGS);
6143
6144 subptr(rsp, 16);
6145 int stk_offset = -(1<<scale1);
6146 if (int_cnt2 < 0) { // not constant
6147 push(cnt2);
6148 stk_offset += wordSize;
6149 }
6150 movl(cnt2, cnt1);
6151
6152 bind(COPY_STR);
6153 if (ae == StrIntrinsicNode::LL) {
6154 load_unsigned_byte(result, Address(str1, cnt2, scale1, -1));
6155 movb(Address(rsp, cnt2, scale1, stk_offset), result);
6156 } else {
6157 load_unsigned_short(result, Address(str1, cnt2, scale1, -2));
6158 movw(Address(rsp, cnt2, scale1, stk_offset), result);
6159 }
6160 decrement(cnt2);
6161 jccb(Assembler::notZero, COPY_STR);
6162
6163 if (int_cnt2 < 0) { // not constant
6164 pop(cnt2);
6165 }
6166 movptr(str1, rsp); // New string address
6167
6168 bind(BIG_STRINGS);
6169 // Load substring.
6170 if (int_cnt2 < 0) { // -1
6171 if (ae == StrIntrinsicNode::UL) {
6172 pmovzxbw(vec, Address(str2, 0));
6173 } else {
6174 movdqu(vec, Address(str2, 0));
6175 }
6176 push(cnt2); // substr count
6177 push(str2); // substr addr
6178 push(str1); // string addr
6179 } else {
6180 // Small (< 8 chars) constant substrings are loaded already.
6181 movl(cnt2, int_cnt2);
6182 }
6183 push(tmp); // original SP
6184
6185 } // Finished loading
6186
6187 //========================================================
6188 // Start search
6189 //
6190
6191 movptr(result, str1); // string addr
6192
6193 if (int_cnt2 < 0) { // Only for non constant substring
6194 jmpb(SCAN_TO_SUBSTR);
6195
6196 // SP saved at sp+0
6197 // String saved at sp+1*wordSize
6198 // Substr saved at sp+2*wordSize
6199 // Substr count saved at sp+3*wordSize
6200
6201 // Reload substr for rescan, this code
6202 // is executed only for large substrings (> 8 chars)
6203 bind(RELOAD_SUBSTR);
6204 movptr(str2, Address(rsp, 2*wordSize));
6205 movl(cnt2, Address(rsp, 3*wordSize));
6206 if (ae == StrIntrinsicNode::UL) {
6207 pmovzxbw(vec, Address(str2, 0));
6208 } else {
6209 movdqu(vec, Address(str2, 0));
6210 }
6211 // We came here after the beginning of the substring was
6212 // matched but the rest of it was not so we need to search
6213 // again. Start from the next element after the previous match.
6214 subptr(str1, result); // Restore counter
6215 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
6216 shrl(str1, 1);
6217 }
6218 addl(cnt1, str1);
6219 decrementl(cnt1); // Shift to next element
6220 cmpl(cnt1, cnt2);
6221 jcc(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6222
6223 addptr(result, (1<<scale1));
6224 } // non constant
6225
6226 // Scan string for start of substr in 16-byte vectors
6227 bind(SCAN_TO_SUBSTR);
6228 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
6229 pcmpestri(vec, Address(result, 0), mode);
6230 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
6231 subl(cnt1, stride);
6232 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
6233 cmpl(cnt1, cnt2);
6234 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6235 addptr(result, 16);
6236
6237 bind(ADJUST_STR);
6238 cmpl(cnt1, stride); // Do not read beyond string
6239 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
6240 // Back-up string to avoid reading beyond string.
6241 lea(result, Address(result, cnt1, scale1, -16));
6242 movl(cnt1, stride);
6243 jmpb(SCAN_TO_SUBSTR);
6244
6245 // Found a potential substr
6246 bind(FOUND_CANDIDATE);
6247 // After pcmpestri tmp(rcx) contains matched element index
6248
6249 // Make sure string is still long enough
6250 subl(cnt1, tmp);
6251 cmpl(cnt1, cnt2);
6252 jccb(Assembler::greaterEqual, FOUND_SUBSTR);
6253 // Left less then substring.
6254
6255 bind(RET_NOT_FOUND);
6256 movl(result, -1);
6257 jmp(CLEANUP);
6258
6259 bind(FOUND_SUBSTR);
6260 // Compute start addr of substr
6261 lea(result, Address(result, tmp, scale1));
6262 if (int_cnt2 > 0) { // Constant substring
6263 // Repeat search for small substring (< 8 chars)
6264 // from new point without reloading substring.
6265 // Have to check that we don't read beyond string.
6266 cmpl(tmp, stride-int_cnt2);
6267 jccb(Assembler::greater, ADJUST_STR);
6268 // Fall through if matched whole substring.
6269 } else { // non constant
6270 assert(int_cnt2 == -1, "should be != 0");
6271
6272 addl(tmp, cnt2);
6273 // Found result if we matched whole substring.
6274 cmpl(tmp, stride);
6275 jcc(Assembler::lessEqual, RET_FOUND);
6276
6277 // Repeat search for small substring (<= 8 chars)
6278 // from new point 'str1' without reloading substring.
6279 cmpl(cnt2, stride);
6280 // Have to check that we don't read beyond string.
6281 jccb(Assembler::lessEqual, ADJUST_STR);
6282
6283 Label CHECK_NEXT, CONT_SCAN_SUBSTR, RET_FOUND_LONG;
6284 // Compare the rest of substring (> 8 chars).
6285 movptr(str1, result);
6286
6287 cmpl(tmp, cnt2);
6288 // First 8 chars are already matched.
6289 jccb(Assembler::equal, CHECK_NEXT);
6290
6291 bind(SCAN_SUBSTR);
6292 pcmpestri(vec, Address(str1, 0), mode);
6293 // Need to reload strings pointers if not matched whole vector
6294 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
6295
6296 bind(CHECK_NEXT);
6297 subl(cnt2, stride);
6298 jccb(Assembler::lessEqual, RET_FOUND_LONG); // Found full substring
6299 addptr(str1, 16);
6300 if (ae == StrIntrinsicNode::UL) {
6301 addptr(str2, 8);
6302 } else {
6303 addptr(str2, 16);
6304 }
6305 subl(cnt1, stride);
6306 cmpl(cnt2, stride); // Do not read beyond substring
6307 jccb(Assembler::greaterEqual, CONT_SCAN_SUBSTR);
6308 // Back-up strings to avoid reading beyond substring.
6309
6310 if (ae == StrIntrinsicNode::UL) {
6311 lea(str2, Address(str2, cnt2, scale2, -8));
6312 lea(str1, Address(str1, cnt2, scale1, -16));
6313 } else {
6314 lea(str2, Address(str2, cnt2, scale2, -16));
6315 lea(str1, Address(str1, cnt2, scale1, -16));
6316 }
6317 subl(cnt1, cnt2);
6318 movl(cnt2, stride);
6319 addl(cnt1, stride);
6320 bind(CONT_SCAN_SUBSTR);
6321 if (ae == StrIntrinsicNode::UL) {
6322 pmovzxbw(vec, Address(str2, 0));
6323 } else {
6324 movdqu(vec, Address(str2, 0));
6325 }
6326 jmp(SCAN_SUBSTR);
6327
6328 bind(RET_FOUND_LONG);
6329 movptr(str1, Address(rsp, wordSize));
6330 } // non constant
6331
6332 bind(RET_FOUND);
6333 // Compute substr offset
6334 subptr(result, str1);
6335 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
6336 shrl(result, 1); // index
6337 }
6338 bind(CLEANUP);
6339 pop(rsp); // restore SP
6340
6341 } // string_indexof
6342
6343 void MacroAssembler::string_indexof_char(Register str1, Register cnt1, Register ch, Register result,
6344 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp) {
6345 ShortBranchVerifier sbv(this);
6346 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
6347
6348 int stride = 8;
6349
6350 Label FOUND_CHAR, SCAN_TO_CHAR, SCAN_TO_CHAR_LOOP,
6351 SCAN_TO_8_CHAR, SCAN_TO_8_CHAR_LOOP, SCAN_TO_16_CHAR_LOOP,
6352 RET_NOT_FOUND, SCAN_TO_8_CHAR_INIT,
6353 FOUND_SEQ_CHAR, DONE_LABEL;
6354
6355 movptr(result, str1);
6356 if (UseAVX >= 2) {
6357 cmpl(cnt1, stride);
6358 jcc(Assembler::less, SCAN_TO_CHAR_LOOP);
6359 cmpl(cnt1, 2*stride);
6360 jcc(Assembler::less, SCAN_TO_8_CHAR_INIT);
6361 movdl(vec1, ch);
6362 vpbroadcastw(vec1, vec1, Assembler::AVX_256bit);
6363 vpxor(vec2, vec2);
6364 movl(tmp, cnt1);
6365 andl(tmp, 0xFFFFFFF0); //vector count (in chars)
6366 andl(cnt1,0x0000000F); //tail count (in chars)
6367
6368 bind(SCAN_TO_16_CHAR_LOOP);
6369 vmovdqu(vec3, Address(result, 0));
6370 vpcmpeqw(vec3, vec3, vec1, 1);
6371 vptest(vec2, vec3);
6372 jcc(Assembler::carryClear, FOUND_CHAR);
6373 addptr(result, 32);
6374 subl(tmp, 2*stride);
6375 jcc(Assembler::notZero, SCAN_TO_16_CHAR_LOOP);
6376 jmp(SCAN_TO_8_CHAR);
6377 bind(SCAN_TO_8_CHAR_INIT);
6378 movdl(vec1, ch);
6379 pshuflw(vec1, vec1, 0x00);
6380 pshufd(vec1, vec1, 0);
6381 pxor(vec2, vec2);
6382 }
6383 bind(SCAN_TO_8_CHAR);
6384 cmpl(cnt1, stride);
6385 if (UseAVX >= 2) {
6386 jcc(Assembler::less, SCAN_TO_CHAR);
6387 } else {
6388 jcc(Assembler::less, SCAN_TO_CHAR_LOOP);
6389 movdl(vec1, ch);
6390 pshuflw(vec1, vec1, 0x00);
6391 pshufd(vec1, vec1, 0);
6392 pxor(vec2, vec2);
6393 }
6394 movl(tmp, cnt1);
6395 andl(tmp, 0xFFFFFFF8); //vector count (in chars)
6396 andl(cnt1,0x00000007); //tail count (in chars)
6397
6398 bind(SCAN_TO_8_CHAR_LOOP);
6399 movdqu(vec3, Address(result, 0));
6400 pcmpeqw(vec3, vec1);
6401 ptest(vec2, vec3);
6402 jcc(Assembler::carryClear, FOUND_CHAR);
6403 addptr(result, 16);
6404 subl(tmp, stride);
6405 jcc(Assembler::notZero, SCAN_TO_8_CHAR_LOOP);
6406 bind(SCAN_TO_CHAR);
6407 testl(cnt1, cnt1);
6408 jcc(Assembler::zero, RET_NOT_FOUND);
6409 bind(SCAN_TO_CHAR_LOOP);
6410 load_unsigned_short(tmp, Address(result, 0));
6411 cmpl(ch, tmp);
6412 jccb(Assembler::equal, FOUND_SEQ_CHAR);
6413 addptr(result, 2);
6414 subl(cnt1, 1);
6415 jccb(Assembler::zero, RET_NOT_FOUND);
6416 jmp(SCAN_TO_CHAR_LOOP);
6417
6418 bind(RET_NOT_FOUND);
6419 movl(result, -1);
6420 jmpb(DONE_LABEL);
6421
6422 bind(FOUND_CHAR);
6423 if (UseAVX >= 2) {
6424 vpmovmskb(tmp, vec3);
6425 } else {
6426 pmovmskb(tmp, vec3);
6427 }
6428 bsfl(ch, tmp);
6429 addl(result, ch);
6430
6431 bind(FOUND_SEQ_CHAR);
6432 subptr(result, str1);
6433 shrl(result, 1);
6434
6435 bind(DONE_LABEL);
6436 } // string_indexof_char
6437
6438 // helper function for string_compare
6439 void MacroAssembler::load_next_elements(Register elem1, Register elem2, Register str1, Register str2,
6440 Address::ScaleFactor scale, Address::ScaleFactor scale1,
6441 Address::ScaleFactor scale2, Register index, int ae) {
6442 if (ae == StrIntrinsicNode::LL) {
6443 load_unsigned_byte(elem1, Address(str1, index, scale, 0));
6444 load_unsigned_byte(elem2, Address(str2, index, scale, 0));
6445 } else if (ae == StrIntrinsicNode::UU) {
6446 load_unsigned_short(elem1, Address(str1, index, scale, 0));
6447 load_unsigned_short(elem2, Address(str2, index, scale, 0));
6448 } else {
6449 load_unsigned_byte(elem1, Address(str1, index, scale1, 0));
6450 load_unsigned_short(elem2, Address(str2, index, scale2, 0));
6451 }
6452 }
6453
6454 // Compare strings, used for char[] and byte[].
6455 void MacroAssembler::string_compare(Register str1, Register str2,
6456 Register cnt1, Register cnt2, Register result,
6457 XMMRegister vec1, int ae) {
6458 ShortBranchVerifier sbv(this);
6459 Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL;
6460 Label COMPARE_WIDE_VECTORS_LOOP_FAILED; // used only _LP64 && AVX3
6461 int stride, stride2, adr_stride, adr_stride1, adr_stride2;
6462 int stride2x2 = 0x40;
6463 Address::ScaleFactor scale = Address::no_scale;
6464 Address::ScaleFactor scale1 = Address::no_scale;
6465 Address::ScaleFactor scale2 = Address::no_scale;
6466
6467 if (ae != StrIntrinsicNode::LL) {
6468 stride2x2 = 0x20;
6469 }
6470
6471 if (ae == StrIntrinsicNode::LU || ae == StrIntrinsicNode::UL) {
6472 shrl(cnt2, 1);
6473 }
6474 // Compute the minimum of the string lengths and the
6475 // difference of the string lengths (stack).
6476 // Do the conditional move stuff
6477 movl(result, cnt1);
6478 subl(cnt1, cnt2);
6479 push(cnt1);
6480 cmov32(Assembler::lessEqual, cnt2, result); // cnt2 = min(cnt1, cnt2)
6481
6482 // Is the minimum length zero?
6483 testl(cnt2, cnt2);
6484 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
6485 if (ae == StrIntrinsicNode::LL) {
6486 // Load first bytes
6487 load_unsigned_byte(result, Address(str1, 0)); // result = str1[0]
6488 load_unsigned_byte(cnt1, Address(str2, 0)); // cnt1 = str2[0]
6489 } else if (ae == StrIntrinsicNode::UU) {
6490 // Load first characters
6491 load_unsigned_short(result, Address(str1, 0));
6492 load_unsigned_short(cnt1, Address(str2, 0));
6493 } else {
6494 load_unsigned_byte(result, Address(str1, 0));
6495 load_unsigned_short(cnt1, Address(str2, 0));
6496 }
6497 subl(result, cnt1);
6498 jcc(Assembler::notZero, POP_LABEL);
6499
6500 if (ae == StrIntrinsicNode::UU) {
6501 // Divide length by 2 to get number of chars
6502 shrl(cnt2, 1);
6503 }
6504 cmpl(cnt2, 1);
6505 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
6506
6507 // Check if the strings start at the same location and setup scale and stride
6508 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6509 cmpptr(str1, str2);
6510 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
6511 if (ae == StrIntrinsicNode::LL) {
6512 scale = Address::times_1;
6513 stride = 16;
6514 } else {
6515 scale = Address::times_2;
6516 stride = 8;
6517 }
6518 } else {
6519 scale1 = Address::times_1;
6520 scale2 = Address::times_2;
6521 // scale not used
6522 stride = 8;
6523 }
6524
6525 if (UseAVX >= 2 && UseSSE42Intrinsics) {
6526 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_WIDE_TAIL, COMPARE_SMALL_STR;
6527 Label COMPARE_WIDE_VECTORS_LOOP, COMPARE_16_CHARS, COMPARE_INDEX_CHAR;
6528 Label COMPARE_WIDE_VECTORS_LOOP_AVX2;
6529 Label COMPARE_TAIL_LONG;
6530 Label COMPARE_WIDE_VECTORS_LOOP_AVX3; // used only _LP64 && AVX3
6531
6532 int pcmpmask = 0x19;
6533 if (ae == StrIntrinsicNode::LL) {
6534 pcmpmask &= ~0x01;
6535 }
6536
6537 // Setup to compare 16-chars (32-bytes) vectors,
6538 // start from first character again because it has aligned address.
6539 if (ae == StrIntrinsicNode::LL) {
6540 stride2 = 32;
6541 } else {
6542 stride2 = 16;
6543 }
6544 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6545 adr_stride = stride << scale;
6546 } else {
6547 adr_stride1 = 8; //stride << scale1;
6548 adr_stride2 = 16; //stride << scale2;
6549 }
6550
6551 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
6552 // rax and rdx are used by pcmpestri as elements counters
6553 movl(result, cnt2);
6554 andl(cnt2, ~(stride2-1)); // cnt2 holds the vector count
6555 jcc(Assembler::zero, COMPARE_TAIL_LONG);
6556
6557 // fast path : compare first 2 8-char vectors.
6558 bind(COMPARE_16_CHARS);
6559 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6560 movdqu(vec1, Address(str1, 0));
6561 } else {
6562 pmovzxbw(vec1, Address(str1, 0));
6563 }
6564 pcmpestri(vec1, Address(str2, 0), pcmpmask);
6565 jccb(Assembler::below, COMPARE_INDEX_CHAR);
6566
6567 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6568 movdqu(vec1, Address(str1, adr_stride));
6569 pcmpestri(vec1, Address(str2, adr_stride), pcmpmask);
6570 } else {
6571 pmovzxbw(vec1, Address(str1, adr_stride1));
6572 pcmpestri(vec1, Address(str2, adr_stride2), pcmpmask);
6573 }
6574 jccb(Assembler::aboveEqual, COMPARE_WIDE_VECTORS);
6575 addl(cnt1, stride);
6576
6577 // Compare the characters at index in cnt1
6578 bind(COMPARE_INDEX_CHAR); // cnt1 has the offset of the mismatching character
6579 load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae);
6580 subl(result, cnt2);
6581 jmp(POP_LABEL);
6582
6583 // Setup the registers to start vector comparison loop
6584 bind(COMPARE_WIDE_VECTORS);
6585 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6586 lea(str1, Address(str1, result, scale));
6587 lea(str2, Address(str2, result, scale));
6588 } else {
6589 lea(str1, Address(str1, result, scale1));
6590 lea(str2, Address(str2, result, scale2));
6591 }
6592 subl(result, stride2);
6593 subl(cnt2, stride2);
6594 jcc(Assembler::zero, COMPARE_WIDE_TAIL);
6595 negptr(result);
6596
6597 // In a loop, compare 16-chars (32-bytes) at once using (vpxor+vptest)
6598 bind(COMPARE_WIDE_VECTORS_LOOP);
6599
6600 #ifdef _LP64
6601 if (VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop
6602 cmpl(cnt2, stride2x2);
6603 jccb(Assembler::below, COMPARE_WIDE_VECTORS_LOOP_AVX2);
6604 testl(cnt2, stride2x2-1); // cnt2 holds the vector count
6605 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX2); // means we cannot subtract by 0x40
6606
6607 bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop
6608 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6609 evmovdquq(vec1, Address(str1, result, scale), Assembler::AVX_512bit);
6610 evpcmpeqb(k7, vec1, Address(str2, result, scale), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0
6611 } else {
6612 vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_512bit);
6613 evpcmpeqb(k7, vec1, Address(str2, result, scale2), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0
6614 }
6615 kortestql(k7, k7);
6616 jcc(Assembler::aboveEqual, COMPARE_WIDE_VECTORS_LOOP_FAILED); // miscompare
6617 addptr(result, stride2x2); // update since we already compared at this addr
6618 subl(cnt2, stride2x2); // and sub the size too
6619 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX3);
6620
6621 vpxor(vec1, vec1);
6622 jmpb(COMPARE_WIDE_TAIL);
6623 }//if (VM_Version::supports_avx512vlbw())
6624 #endif // _LP64
6625
6626
6627 bind(COMPARE_WIDE_VECTORS_LOOP_AVX2);
6628 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6629 vmovdqu(vec1, Address(str1, result, scale));
6630 vpxor(vec1, Address(str2, result, scale));
6631 } else {
6632 vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_256bit);
6633 vpxor(vec1, Address(str2, result, scale2));
6634 }
6635 vptest(vec1, vec1);
6636 jcc(Assembler::notZero, VECTOR_NOT_EQUAL);
6637 addptr(result, stride2);
6638 subl(cnt2, stride2);
6639 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP);
6640 // clean upper bits of YMM registers
6641 vpxor(vec1, vec1);
6642
6643 // compare wide vectors tail
6644 bind(COMPARE_WIDE_TAIL);
6645 testptr(result, result);
6646 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
6647
6648 movl(result, stride2);
6649 movl(cnt2, result);
6650 negptr(result);
6651 jmp(COMPARE_WIDE_VECTORS_LOOP_AVX2);
6652
6653 // Identifies the mismatching (higher or lower)16-bytes in the 32-byte vectors.
6654 bind(VECTOR_NOT_EQUAL);
6655 // clean upper bits of YMM registers
6656 vpxor(vec1, vec1);
6657 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6658 lea(str1, Address(str1, result, scale));
6659 lea(str2, Address(str2, result, scale));
6660 } else {
6661 lea(str1, Address(str1, result, scale1));
6662 lea(str2, Address(str2, result, scale2));
6663 }
6664 jmp(COMPARE_16_CHARS);
6665
6666 // Compare tail chars, length between 1 to 15 chars
6667 bind(COMPARE_TAIL_LONG);
6668 movl(cnt2, result);
6669 cmpl(cnt2, stride);
6670 jcc(Assembler::less, COMPARE_SMALL_STR);
6671
6672 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6673 movdqu(vec1, Address(str1, 0));
6674 } else {
6675 pmovzxbw(vec1, Address(str1, 0));
6676 }
6677 pcmpestri(vec1, Address(str2, 0), pcmpmask);
6678 jcc(Assembler::below, COMPARE_INDEX_CHAR);
6679 subptr(cnt2, stride);
6680 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
6681 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6682 lea(str1, Address(str1, result, scale));
6683 lea(str2, Address(str2, result, scale));
6684 } else {
6685 lea(str1, Address(str1, result, scale1));
6686 lea(str2, Address(str2, result, scale2));
6687 }
6688 negptr(cnt2);
6689 jmpb(WHILE_HEAD_LABEL);
6690
6691 bind(COMPARE_SMALL_STR);
6692 } else if (UseSSE42Intrinsics) {
6693 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL;
6694 int pcmpmask = 0x19;
6695 // Setup to compare 8-char (16-byte) vectors,
6696 // start from first character again because it has aligned address.
6697 movl(result, cnt2);
6698 andl(cnt2, ~(stride - 1)); // cnt2 holds the vector count
6699 if (ae == StrIntrinsicNode::LL) {
6700 pcmpmask &= ~0x01;
6701 }
6702 jcc(Assembler::zero, COMPARE_TAIL);
6703 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6704 lea(str1, Address(str1, result, scale));
6705 lea(str2, Address(str2, result, scale));
6706 } else {
6707 lea(str1, Address(str1, result, scale1));
6708 lea(str2, Address(str2, result, scale2));
6709 }
6710 negptr(result);
6711
6712 // pcmpestri
6713 // inputs:
6714 // vec1- substring
6715 // rax - negative string length (elements count)
6716 // mem - scanned string
6717 // rdx - string length (elements count)
6718 // pcmpmask - cmp mode: 11000 (string compare with negated result)
6719 // + 00 (unsigned bytes) or + 01 (unsigned shorts)
6720 // outputs:
6721 // rcx - first mismatched element index
6722 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
6723
6724 bind(COMPARE_WIDE_VECTORS);
6725 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6726 movdqu(vec1, Address(str1, result, scale));
6727 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
6728 } else {
6729 pmovzxbw(vec1, Address(str1, result, scale1));
6730 pcmpestri(vec1, Address(str2, result, scale2), pcmpmask);
6731 }
6732 // After pcmpestri cnt1(rcx) contains mismatched element index
6733
6734 jccb(Assembler::below, VECTOR_NOT_EQUAL); // CF==1
6735 addptr(result, stride);
6736 subptr(cnt2, stride);
6737 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS);
6738
6739 // compare wide vectors tail
6740 testptr(result, result);
6741 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
6742
6743 movl(cnt2, stride);
6744 movl(result, stride);
6745 negptr(result);
6746 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6747 movdqu(vec1, Address(str1, result, scale));
6748 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
6749 } else {
6750 pmovzxbw(vec1, Address(str1, result, scale1));
6751 pcmpestri(vec1, Address(str2, result, scale2), pcmpmask);
6752 }
6753 jccb(Assembler::aboveEqual, LENGTH_DIFF_LABEL);
6754
6755 // Mismatched characters in the vectors
6756 bind(VECTOR_NOT_EQUAL);
6757 addptr(cnt1, result);
6758 load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae);
6759 subl(result, cnt2);
6760 jmpb(POP_LABEL);
6761
6762 bind(COMPARE_TAIL); // limit is zero
6763 movl(cnt2, result);
6764 // Fallthru to tail compare
6765 }
6766 // Shift str2 and str1 to the end of the arrays, negate min
6767 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6768 lea(str1, Address(str1, cnt2, scale));
6769 lea(str2, Address(str2, cnt2, scale));
6770 } else {
6771 lea(str1, Address(str1, cnt2, scale1));
6772 lea(str2, Address(str2, cnt2, scale2));
6773 }
6774 decrementl(cnt2); // first character was compared already
6775 negptr(cnt2);
6776
6777 // Compare the rest of the elements
6778 bind(WHILE_HEAD_LABEL);
6779 load_next_elements(result, cnt1, str1, str2, scale, scale1, scale2, cnt2, ae);
6780 subl(result, cnt1);
6781 jccb(Assembler::notZero, POP_LABEL);
6782 increment(cnt2);
6783 jccb(Assembler::notZero, WHILE_HEAD_LABEL);
6784
6785 // Strings are equal up to min length. Return the length difference.
6786 bind(LENGTH_DIFF_LABEL);
6787 pop(result);
6788 if (ae == StrIntrinsicNode::UU) {
6789 // Divide diff by 2 to get number of chars
6790 sarl(result, 1);
6791 }
6792 jmpb(DONE_LABEL);
6793
6794 #ifdef _LP64
6795 if (VM_Version::supports_avx512vlbw()) {
6796
6797 bind(COMPARE_WIDE_VECTORS_LOOP_FAILED);
6798
6799 kmovql(cnt1, k7);
6800 notq(cnt1);
6801 bsfq(cnt2, cnt1);
6802 if (ae != StrIntrinsicNode::LL) {
6803 // Divide diff by 2 to get number of chars
6804 sarl(cnt2, 1);
6805 }
6806 addq(result, cnt2);
6807 if (ae == StrIntrinsicNode::LL) {
6808 load_unsigned_byte(cnt1, Address(str2, result));
6809 load_unsigned_byte(result, Address(str1, result));
6810 } else if (ae == StrIntrinsicNode::UU) {
6811 load_unsigned_short(cnt1, Address(str2, result, scale));
6812 load_unsigned_short(result, Address(str1, result, scale));
6813 } else {
6814 load_unsigned_short(cnt1, Address(str2, result, scale2));
6815 load_unsigned_byte(result, Address(str1, result, scale1));
6816 }
6817 subl(result, cnt1);
6818 jmpb(POP_LABEL);
6819 }//if (VM_Version::supports_avx512vlbw())
6820 #endif // _LP64
6821
6822 // Discard the stored length difference
6823 bind(POP_LABEL);
6824 pop(cnt1);
6825
6826 // That's it
6827 bind(DONE_LABEL);
6828 if(ae == StrIntrinsicNode::UL) {
6829 negl(result);
6830 }
6831
6832 }
6833
6834 // Search for Non-ASCII character (Negative byte value) in a byte array,
6835 // return true if it has any and false otherwise.
6836 // ..\jdk\src\java.base\share\classes\java\lang\StringCoding.java
6837 // @HotSpotIntrinsicCandidate
6838 // private static boolean hasNegatives(byte[] ba, int off, int len) {
6839 // for (int i = off; i < off + len; i++) {
6840 // if (ba[i] < 0) {
6841 // return true;
6842 // }
6843 // }
6844 // return false;
6845 // }
6846 void MacroAssembler::has_negatives(Register ary1, Register len,
6847 Register result, Register tmp1,
6848 XMMRegister vec1, XMMRegister vec2) {
6849 // rsi: byte array
6850 // rcx: len
6851 // rax: result
6852 ShortBranchVerifier sbv(this);
6853 assert_different_registers(ary1, len, result, tmp1);
6854 assert_different_registers(vec1, vec2);
6855 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_CHAR, COMPARE_VECTORS, COMPARE_BYTE;
6856
6857 // len == 0
6858 testl(len, len);
6859 jcc(Assembler::zero, FALSE_LABEL);
6860
6861 if ((UseAVX > 2) && // AVX512
6862 VM_Version::supports_avx512vlbw() &&
6863 VM_Version::supports_bmi2()) {
6864
6865 set_vector_masking(); // opening of the stub context for programming mask registers
6866
6867 Label test_64_loop, test_tail;
6868 Register tmp3_aliased = len;
6869
6870 movl(tmp1, len);
6871 vpxor(vec2, vec2, vec2, Assembler::AVX_512bit);
6872
6873 andl(tmp1, 64 - 1); // tail count (in chars) 0x3F
6874 andl(len, ~(64 - 1)); // vector count (in chars)
6875 jccb(Assembler::zero, test_tail);
6876
6877 lea(ary1, Address(ary1, len, Address::times_1));
6878 negptr(len);
6879
6880 bind(test_64_loop);
6881 // Check whether our 64 elements of size byte contain negatives
6882 evpcmpgtb(k2, vec2, Address(ary1, len, Address::times_1), Assembler::AVX_512bit);
6883 kortestql(k2, k2);
6884 jcc(Assembler::notZero, TRUE_LABEL);
6885
6886 addptr(len, 64);
6887 jccb(Assembler::notZero, test_64_loop);
6888
6889
6890 bind(test_tail);
6891 // bail out when there is nothing to be done
6892 testl(tmp1, -1);
6893 jcc(Assembler::zero, FALSE_LABEL);
6894
6895 // Save k1
6896 kmovql(k3, k1);
6897
6898 // ~(~0 << len) applied up to two times (for 32-bit scenario)
6899 #ifdef _LP64
6900 mov64(tmp3_aliased, 0xFFFFFFFFFFFFFFFF);
6901 shlxq(tmp3_aliased, tmp3_aliased, tmp1);
6902 notq(tmp3_aliased);
6903 kmovql(k1, tmp3_aliased);
6904 #else
6905 Label k_init;
6906 jmp(k_init);
6907
6908 // We could not read 64-bits from a general purpose register thus we move
6909 // data required to compose 64 1's to the instruction stream
6910 // We emit 64 byte wide series of elements from 0..63 which later on would
6911 // be used as a compare targets with tail count contained in tmp1 register.
6912 // Result would be a k1 register having tmp1 consecutive number or 1
6913 // counting from least significant bit.
6914 address tmp = pc();
6915 emit_int64(0x0706050403020100);
6916 emit_int64(0x0F0E0D0C0B0A0908);
6917 emit_int64(0x1716151413121110);
6918 emit_int64(0x1F1E1D1C1B1A1918);
6919 emit_int64(0x2726252423222120);
6920 emit_int64(0x2F2E2D2C2B2A2928);
6921 emit_int64(0x3736353433323130);
6922 emit_int64(0x3F3E3D3C3B3A3938);
6923
6924 bind(k_init);
6925 lea(len, InternalAddress(tmp));
6926 // create mask to test for negative byte inside a vector
6927 evpbroadcastb(vec1, tmp1, Assembler::AVX_512bit);
6928 evpcmpgtb(k1, vec1, Address(len, 0), Assembler::AVX_512bit);
6929
6930 #endif
6931 evpcmpgtb(k2, k1, vec2, Address(ary1, 0), Assembler::AVX_512bit);
6932 ktestq(k2, k1);
6933 // Restore k1
6934 kmovql(k1, k3);
6935 jcc(Assembler::notZero, TRUE_LABEL);
6936
6937 jmp(FALSE_LABEL);
6938
6939 clear_vector_masking(); // closing of the stub context for programming mask registers
6940 } else {
6941 movl(result, len); // copy
6942
6943 if (UseAVX == 2 && UseSSE >= 2) {
6944 // With AVX2, use 32-byte vector compare
6945 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
6946
6947 // Compare 32-byte vectors
6948 andl(result, 0x0000001f); // tail count (in bytes)
6949 andl(len, 0xffffffe0); // vector count (in bytes)
6950 jccb(Assembler::zero, COMPARE_TAIL);
6951
6952 lea(ary1, Address(ary1, len, Address::times_1));
6953 negptr(len);
6954
6955 movl(tmp1, 0x80808080); // create mask to test for Unicode chars in vector
6956 movdl(vec2, tmp1);
6957 vpbroadcastd(vec2, vec2, Assembler::AVX_256bit);
6958
6959 bind(COMPARE_WIDE_VECTORS);
6960 vmovdqu(vec1, Address(ary1, len, Address::times_1));
6961 vptest(vec1, vec2);
6962 jccb(Assembler::notZero, TRUE_LABEL);
6963 addptr(len, 32);
6964 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
6965
6966 testl(result, result);
6967 jccb(Assembler::zero, FALSE_LABEL);
6968
6969 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32));
6970 vptest(vec1, vec2);
6971 jccb(Assembler::notZero, TRUE_LABEL);
6972 jmpb(FALSE_LABEL);
6973
6974 bind(COMPARE_TAIL); // len is zero
6975 movl(len, result);
6976 // Fallthru to tail compare
6977 } else if (UseSSE42Intrinsics) {
6978 // With SSE4.2, use double quad vector compare
6979 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
6980
6981 // Compare 16-byte vectors
6982 andl(result, 0x0000000f); // tail count (in bytes)
6983 andl(len, 0xfffffff0); // vector count (in bytes)
6984 jcc(Assembler::zero, COMPARE_TAIL);
6985
6986 lea(ary1, Address(ary1, len, Address::times_1));
6987 negptr(len);
6988
6989 movl(tmp1, 0x80808080);
6990 movdl(vec2, tmp1);
6991 pshufd(vec2, vec2, 0);
6992
6993 bind(COMPARE_WIDE_VECTORS);
6994 movdqu(vec1, Address(ary1, len, Address::times_1));
6995 ptest(vec1, vec2);
6996 jcc(Assembler::notZero, TRUE_LABEL);
6997 addptr(len, 16);
6998 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
6999
7000 testl(result, result);
7001 jcc(Assembler::zero, FALSE_LABEL);
7002
7003 movdqu(vec1, Address(ary1, result, Address::times_1, -16));
7004 ptest(vec1, vec2);
7005 jccb(Assembler::notZero, TRUE_LABEL);
7006 jmpb(FALSE_LABEL);
7007
7008 bind(COMPARE_TAIL); // len is zero
7009 movl(len, result);
7010 // Fallthru to tail compare
7011 }
7012 }
7013 // Compare 4-byte vectors
7014 andl(len, 0xfffffffc); // vector count (in bytes)
7015 jccb(Assembler::zero, COMPARE_CHAR);
7016
7017 lea(ary1, Address(ary1, len, Address::times_1));
7018 negptr(len);
7019
7020 bind(COMPARE_VECTORS);
7021 movl(tmp1, Address(ary1, len, Address::times_1));
7022 andl(tmp1, 0x80808080);
7023 jccb(Assembler::notZero, TRUE_LABEL);
7024 addptr(len, 4);
7025 jcc(Assembler::notZero, COMPARE_VECTORS);
7026
7027 // Compare trailing char (final 2 bytes), if any
7028 bind(COMPARE_CHAR);
7029 testl(result, 0x2); // tail char
7030 jccb(Assembler::zero, COMPARE_BYTE);
7031 load_unsigned_short(tmp1, Address(ary1, 0));
7032 andl(tmp1, 0x00008080);
7033 jccb(Assembler::notZero, TRUE_LABEL);
7034 subptr(result, 2);
7035 lea(ary1, Address(ary1, 2));
7036
7037 bind(COMPARE_BYTE);
7038 testl(result, 0x1); // tail byte
7039 jccb(Assembler::zero, FALSE_LABEL);
7040 load_unsigned_byte(tmp1, Address(ary1, 0));
7041 andl(tmp1, 0x00000080);
7042 jccb(Assembler::notEqual, TRUE_LABEL);
7043 jmpb(FALSE_LABEL);
7044
7045 bind(TRUE_LABEL);
7046 movl(result, 1); // return true
7047 jmpb(DONE);
7048
7049 bind(FALSE_LABEL);
7050 xorl(result, result); // return false
7051
7052 // That's it
7053 bind(DONE);
7054 if (UseAVX >= 2 && UseSSE >= 2) {
7055 // clean upper bits of YMM registers
7056 vpxor(vec1, vec1);
7057 vpxor(vec2, vec2);
7058 }
7059 }
7060 // Compare char[] or byte[] arrays aligned to 4 bytes or substrings.
7061 void MacroAssembler::arrays_equals(bool is_array_equ, Register ary1, Register ary2,
7062 Register limit, Register result, Register chr,
7063 XMMRegister vec1, XMMRegister vec2, bool is_char) {
7064 ShortBranchVerifier sbv(this);
7065 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR, COMPARE_BYTE;
7066
7067 int length_offset = arrayOopDesc::length_offset_in_bytes();
7068 int base_offset = arrayOopDesc::base_offset_in_bytes(is_char ? T_CHAR : T_BYTE);
7069
7070 if (is_array_equ) {
7071 // Check the input args
7072 cmpoop(ary1, ary2);
7073 jcc(Assembler::equal, TRUE_LABEL);
7074
7075 // Need additional checks for arrays_equals.
7076 testptr(ary1, ary1);
7077 jcc(Assembler::zero, FALSE_LABEL);
7078 testptr(ary2, ary2);
7079 jcc(Assembler::zero, FALSE_LABEL);
7080
7081 // Check the lengths
7082 movl(limit, Address(ary1, length_offset));
7083 cmpl(limit, Address(ary2, length_offset));
7084 jcc(Assembler::notEqual, FALSE_LABEL);
7085 }
7086
7087 // count == 0
7088 testl(limit, limit);
7089 jcc(Assembler::zero, TRUE_LABEL);
7090
7091 if (is_array_equ) {
7092 // Load array address
7093 lea(ary1, Address(ary1, base_offset));
7094 lea(ary2, Address(ary2, base_offset));
7095 }
7096
7097 if (is_array_equ && is_char) {
7098 // arrays_equals when used for char[].
7099 shll(limit, 1); // byte count != 0
7100 }
7101 movl(result, limit); // copy
7102
7103 if (UseAVX >= 2) {
7104 // With AVX2, use 32-byte vector compare
7105 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
7106
7107 // Compare 32-byte vectors
7108 andl(result, 0x0000001f); // tail count (in bytes)
7109 andl(limit, 0xffffffe0); // vector count (in bytes)
7110 jcc(Assembler::zero, COMPARE_TAIL);
7111
7112 lea(ary1, Address(ary1, limit, Address::times_1));
7113 lea(ary2, Address(ary2, limit, Address::times_1));
7114 negptr(limit);
7115
7116 bind(COMPARE_WIDE_VECTORS);
7117
7118 #ifdef _LP64
7119 if (VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop
7120 Label COMPARE_WIDE_VECTORS_LOOP_AVX2, COMPARE_WIDE_VECTORS_LOOP_AVX3;
7121
7122 cmpl(limit, -64);
7123 jccb(Assembler::greater, COMPARE_WIDE_VECTORS_LOOP_AVX2);
7124
7125 bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop
7126
7127 evmovdquq(vec1, Address(ary1, limit, Address::times_1), Assembler::AVX_512bit);
7128 evpcmpeqb(k7, vec1, Address(ary2, limit, Address::times_1), Assembler::AVX_512bit);
7129 kortestql(k7, k7);
7130 jcc(Assembler::aboveEqual, FALSE_LABEL); // miscompare
7131 addptr(limit, 64); // update since we already compared at this addr
7132 cmpl(limit, -64);
7133 jccb(Assembler::lessEqual, COMPARE_WIDE_VECTORS_LOOP_AVX3);
7134
7135 // At this point we may still need to compare -limit+result bytes.
7136 // We could execute the next two instruction and just continue via non-wide path:
7137 // cmpl(limit, 0);
7138 // jcc(Assembler::equal, COMPARE_TAIL); // true
7139 // But since we stopped at the points ary{1,2}+limit which are
7140 // not farther than 64 bytes from the ends of arrays ary{1,2}+result
7141 // (|limit| <= 32 and result < 32),
7142 // we may just compare the last 64 bytes.
7143 //
7144 addptr(result, -64); // it is safe, bc we just came from this area
7145 evmovdquq(vec1, Address(ary1, result, Address::times_1), Assembler::AVX_512bit);
7146 evpcmpeqb(k7, vec1, Address(ary2, result, Address::times_1), Assembler::AVX_512bit);
7147 kortestql(k7, k7);
7148 jcc(Assembler::aboveEqual, FALSE_LABEL); // miscompare
7149
7150 jmp(TRUE_LABEL);
7151
7152 bind(COMPARE_WIDE_VECTORS_LOOP_AVX2);
7153
7154 }//if (VM_Version::supports_avx512vlbw())
7155 #endif //_LP64
7156
7157 vmovdqu(vec1, Address(ary1, limit, Address::times_1));
7158 vmovdqu(vec2, Address(ary2, limit, Address::times_1));
7159 vpxor(vec1, vec2);
7160
7161 vptest(vec1, vec1);
7162 jcc(Assembler::notZero, FALSE_LABEL);
7163 addptr(limit, 32);
7164 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
7165
7166 testl(result, result);
7167 jcc(Assembler::zero, TRUE_LABEL);
7168
7169 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32));
7170 vmovdqu(vec2, Address(ary2, result, Address::times_1, -32));
7171 vpxor(vec1, vec2);
7172
7173 vptest(vec1, vec1);
7174 jccb(Assembler::notZero, FALSE_LABEL);
7175 jmpb(TRUE_LABEL);
7176
7177 bind(COMPARE_TAIL); // limit is zero
7178 movl(limit, result);
7179 // Fallthru to tail compare
7180 } else if (UseSSE42Intrinsics) {
7181 // With SSE4.2, use double quad vector compare
7182 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
7183
7184 // Compare 16-byte vectors
7185 andl(result, 0x0000000f); // tail count (in bytes)
7186 andl(limit, 0xfffffff0); // vector count (in bytes)
7187 jcc(Assembler::zero, COMPARE_TAIL);
7188
7189 lea(ary1, Address(ary1, limit, Address::times_1));
7190 lea(ary2, Address(ary2, limit, Address::times_1));
7191 negptr(limit);
7192
7193 bind(COMPARE_WIDE_VECTORS);
7194 movdqu(vec1, Address(ary1, limit, Address::times_1));
7195 movdqu(vec2, Address(ary2, limit, Address::times_1));
7196 pxor(vec1, vec2);
7197
7198 ptest(vec1, vec1);
7199 jcc(Assembler::notZero, FALSE_LABEL);
7200 addptr(limit, 16);
7201 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
7202
7203 testl(result, result);
7204 jcc(Assembler::zero, TRUE_LABEL);
7205
7206 movdqu(vec1, Address(ary1, result, Address::times_1, -16));
7207 movdqu(vec2, Address(ary2, result, Address::times_1, -16));
7208 pxor(vec1, vec2);
7209
7210 ptest(vec1, vec1);
7211 jccb(Assembler::notZero, FALSE_LABEL);
7212 jmpb(TRUE_LABEL);
7213
7214 bind(COMPARE_TAIL); // limit is zero
7215 movl(limit, result);
7216 // Fallthru to tail compare
7217 }
7218
7219 // Compare 4-byte vectors
7220 andl(limit, 0xfffffffc); // vector count (in bytes)
7221 jccb(Assembler::zero, COMPARE_CHAR);
7222
7223 lea(ary1, Address(ary1, limit, Address::times_1));
7224 lea(ary2, Address(ary2, limit, Address::times_1));
7225 negptr(limit);
7226
7227 bind(COMPARE_VECTORS);
7228 movl(chr, Address(ary1, limit, Address::times_1));
7229 cmpl(chr, Address(ary2, limit, Address::times_1));
7230 jccb(Assembler::notEqual, FALSE_LABEL);
7231 addptr(limit, 4);
7232 jcc(Assembler::notZero, COMPARE_VECTORS);
7233
7234 // Compare trailing char (final 2 bytes), if any
7235 bind(COMPARE_CHAR);
7236 testl(result, 0x2); // tail char
7237 jccb(Assembler::zero, COMPARE_BYTE);
7238 load_unsigned_short(chr, Address(ary1, 0));
7239 load_unsigned_short(limit, Address(ary2, 0));
7240 cmpl(chr, limit);
7241 jccb(Assembler::notEqual, FALSE_LABEL);
7242
7243 if (is_array_equ && is_char) {
7244 bind(COMPARE_BYTE);
7245 } else {
7246 lea(ary1, Address(ary1, 2));
7247 lea(ary2, Address(ary2, 2));
7248
7249 bind(COMPARE_BYTE);
7250 testl(result, 0x1); // tail byte
7251 jccb(Assembler::zero, TRUE_LABEL);
7252 load_unsigned_byte(chr, Address(ary1, 0));
7253 load_unsigned_byte(limit, Address(ary2, 0));
7254 cmpl(chr, limit);
7255 jccb(Assembler::notEqual, FALSE_LABEL);
7256 }
7257 bind(TRUE_LABEL);
7258 movl(result, 1); // return true
7259 jmpb(DONE);
7260
7261 bind(FALSE_LABEL);
7262 xorl(result, result); // return false
7263
7264 // That's it
7265 bind(DONE);
7266 if (UseAVX >= 2) {
7267 // clean upper bits of YMM registers
7268 vpxor(vec1, vec1);
7269 vpxor(vec2, vec2);
7270 }
7271 }
7272
7273 #endif
7274
7275 void MacroAssembler::generate_fill(BasicType t, bool aligned,
7276 Register to, Register value, Register count,
7277 Register rtmp, XMMRegister xtmp) {
7278 ShortBranchVerifier sbv(this);
7279 assert_different_registers(to, value, count, rtmp);
7280 Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte;
7281 Label L_fill_2_bytes, L_fill_4_bytes;
7282
7283 int shift = -1;
7284 switch (t) {
7285 case T_BYTE:
7286 shift = 2;
7287 break;
7288 case T_SHORT:
7289 shift = 1;
7290 break;
7291 case T_INT:
7292 shift = 0;
7293 break;
7294 default: ShouldNotReachHere();
7295 }
7296
7297 if (t == T_BYTE) {
7298 andl(value, 0xff);
7299 movl(rtmp, value);
7300 shll(rtmp, 8);
7301 orl(value, rtmp);
7302 }
7303 if (t == T_SHORT) {
7304 andl(value, 0xffff);
7305 }
7306 if (t == T_BYTE || t == T_SHORT) {
7307 movl(rtmp, value);
7308 shll(rtmp, 16);
7309 orl(value, rtmp);
7310 }
7311
7312 cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element
7313 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
7314 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
7315 // align source address at 4 bytes address boundary
7316 if (t == T_BYTE) {
7317 // One byte misalignment happens only for byte arrays
7318 testptr(to, 1);
7319 jccb(Assembler::zero, L_skip_align1);
7320 movb(Address(to, 0), value);
7321 increment(to);
7322 decrement(count);
7323 BIND(L_skip_align1);
7324 }
7325 // Two bytes misalignment happens only for byte and short (char) arrays
7326 testptr(to, 2);
7327 jccb(Assembler::zero, L_skip_align2);
7328 movw(Address(to, 0), value);
7329 addptr(to, 2);
7330 subl(count, 1<<(shift-1));
7331 BIND(L_skip_align2);
7332 }
7333 if (UseSSE < 2) {
7334 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
7335 // Fill 32-byte chunks
7336 subl(count, 8 << shift);
7337 jcc(Assembler::less, L_check_fill_8_bytes);
7338 align(16);
7339
7340 BIND(L_fill_32_bytes_loop);
7341
7342 for (int i = 0; i < 32; i += 4) {
7343 movl(Address(to, i), value);
7344 }
7345
7346 addptr(to, 32);
7347 subl(count, 8 << shift);
7348 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
7349 BIND(L_check_fill_8_bytes);
7350 addl(count, 8 << shift);
7351 jccb(Assembler::zero, L_exit);
7352 jmpb(L_fill_8_bytes);
7353
7354 //
7355 // length is too short, just fill qwords
7356 //
7357 BIND(L_fill_8_bytes_loop);
7358 movl(Address(to, 0), value);
7359 movl(Address(to, 4), value);
7360 addptr(to, 8);
7361 BIND(L_fill_8_bytes);
7362 subl(count, 1 << (shift + 1));
7363 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
7364 // fall through to fill 4 bytes
7365 } else {
7366 Label L_fill_32_bytes;
7367 if (!UseUnalignedLoadStores) {
7368 // align to 8 bytes, we know we are 4 byte aligned to start
7369 testptr(to, 4);
7370 jccb(Assembler::zero, L_fill_32_bytes);
7371 movl(Address(to, 0), value);
7372 addptr(to, 4);
7373 subl(count, 1<<shift);
7374 }
7375 BIND(L_fill_32_bytes);
7376 {
7377 assert( UseSSE >= 2, "supported cpu only" );
7378 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
7379 if (UseAVX > 2) {
7380 movl(rtmp, 0xffff);
7381 kmovwl(k1, rtmp);
7382 }
7383 movdl(xtmp, value);
7384 if (UseAVX > 2 && UseUnalignedLoadStores) {
7385 // Fill 64-byte chunks
7386 Label L_fill_64_bytes_loop, L_check_fill_32_bytes;
7387 vpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit);
7388
7389 subl(count, 16 << shift);
7390 jcc(Assembler::less, L_check_fill_32_bytes);
7391 align(16);
7392
7393 BIND(L_fill_64_bytes_loop);
7394 evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit);
7395 addptr(to, 64);
7396 subl(count, 16 << shift);
7397 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
7398
7399 BIND(L_check_fill_32_bytes);
7400 addl(count, 8 << shift);
7401 jccb(Assembler::less, L_check_fill_8_bytes);
7402 vmovdqu(Address(to, 0), xtmp);
7403 addptr(to, 32);
7404 subl(count, 8 << shift);
7405
7406 BIND(L_check_fill_8_bytes);
7407 } else if (UseAVX == 2 && UseUnalignedLoadStores) {
7408 // Fill 64-byte chunks
7409 Label L_fill_64_bytes_loop, L_check_fill_32_bytes;
7410 vpbroadcastd(xtmp, xtmp, Assembler::AVX_256bit);
7411
7412 subl(count, 16 << shift);
7413 jcc(Assembler::less, L_check_fill_32_bytes);
7414 align(16);
7415
7416 BIND(L_fill_64_bytes_loop);
7417 vmovdqu(Address(to, 0), xtmp);
7418 vmovdqu(Address(to, 32), xtmp);
7419 addptr(to, 64);
7420 subl(count, 16 << shift);
7421 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
7422
7423 BIND(L_check_fill_32_bytes);
7424 addl(count, 8 << shift);
7425 jccb(Assembler::less, L_check_fill_8_bytes);
7426 vmovdqu(Address(to, 0), xtmp);
7427 addptr(to, 32);
7428 subl(count, 8 << shift);
7429
7430 BIND(L_check_fill_8_bytes);
7431 // clean upper bits of YMM registers
7432 movdl(xtmp, value);
7433 pshufd(xtmp, xtmp, 0);
7434 } else {
7435 // Fill 32-byte chunks
7436 pshufd(xtmp, xtmp, 0);
7437
7438 subl(count, 8 << shift);
7439 jcc(Assembler::less, L_check_fill_8_bytes);
7440 align(16);
7441
7442 BIND(L_fill_32_bytes_loop);
7443
7444 if (UseUnalignedLoadStores) {
7445 movdqu(Address(to, 0), xtmp);
7446 movdqu(Address(to, 16), xtmp);
7447 } else {
7448 movq(Address(to, 0), xtmp);
7449 movq(Address(to, 8), xtmp);
7450 movq(Address(to, 16), xtmp);
7451 movq(Address(to, 24), xtmp);
7452 }
7453
7454 addptr(to, 32);
7455 subl(count, 8 << shift);
7456 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
7457
7458 BIND(L_check_fill_8_bytes);
7459 }
7460 addl(count, 8 << shift);
7461 jccb(Assembler::zero, L_exit);
7462 jmpb(L_fill_8_bytes);
7463
7464 //
7465 // length is too short, just fill qwords
7466 //
7467 BIND(L_fill_8_bytes_loop);
7468 movq(Address(to, 0), xtmp);
7469 addptr(to, 8);
7470 BIND(L_fill_8_bytes);
7471 subl(count, 1 << (shift + 1));
7472 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
7473 }
7474 }
7475 // fill trailing 4 bytes
7476 BIND(L_fill_4_bytes);
7477 testl(count, 1<<shift);
7478 jccb(Assembler::zero, L_fill_2_bytes);
7479 movl(Address(to, 0), value);
7480 if (t == T_BYTE || t == T_SHORT) {
7481 addptr(to, 4);
7482 BIND(L_fill_2_bytes);
7483 // fill trailing 2 bytes
7484 testl(count, 1<<(shift-1));
7485 jccb(Assembler::zero, L_fill_byte);
7486 movw(Address(to, 0), value);
7487 if (t == T_BYTE) {
7488 addptr(to, 2);
7489 BIND(L_fill_byte);
7490 // fill trailing byte
7491 testl(count, 1);
7492 jccb(Assembler::zero, L_exit);
7493 movb(Address(to, 0), value);
7494 } else {
7495 BIND(L_fill_byte);
7496 }
7497 } else {
7498 BIND(L_fill_2_bytes);
7499 }
7500 BIND(L_exit);
7501 }
7502
7503 // encode char[] to byte[] in ISO_8859_1
7504 //@HotSpotIntrinsicCandidate
7505 //private static int implEncodeISOArray(byte[] sa, int sp,
7506 //byte[] da, int dp, int len) {
7507 // int i = 0;
7508 // for (; i < len; i++) {
7509 // char c = StringUTF16.getChar(sa, sp++);
7510 // if (c > '\u00FF')
7511 // break;
7512 // da[dp++] = (byte)c;
7513 // }
7514 // return i;
7515 //}
7516 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
7517 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
7518 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
7519 Register tmp5, Register result) {
7520
7521 // rsi: src
7522 // rdi: dst
7523 // rdx: len
7524 // rcx: tmp5
7525 // rax: result
7526 ShortBranchVerifier sbv(this);
7527 assert_different_registers(src, dst, len, tmp5, result);
7528 Label L_done, L_copy_1_char, L_copy_1_char_exit;
7529
7530 // set result
7531 xorl(result, result);
7532 // check for zero length
7533 testl(len, len);
7534 jcc(Assembler::zero, L_done);
7535
7536 movl(result, len);
7537
7538 // Setup pointers
7539 lea(src, Address(src, len, Address::times_2)); // char[]
7540 lea(dst, Address(dst, len, Address::times_1)); // byte[]
7541 negptr(len);
7542
7543 if (UseSSE42Intrinsics || UseAVX >= 2) {
7544 Label L_chars_8_check, L_copy_8_chars, L_copy_8_chars_exit;
7545 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
7546
7547 if (UseAVX >= 2) {
7548 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
7549 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector
7550 movdl(tmp1Reg, tmp5);
7551 vpbroadcastd(tmp1Reg, tmp1Reg, Assembler::AVX_256bit);
7552 jmp(L_chars_32_check);
7553
7554 bind(L_copy_32_chars);
7555 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
7556 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
7557 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
7558 vptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
7559 jccb(Assembler::notZero, L_copy_32_chars_exit);
7560 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
7561 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1);
7562 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
7563
7564 bind(L_chars_32_check);
7565 addptr(len, 32);
7566 jcc(Assembler::lessEqual, L_copy_32_chars);
7567
7568 bind(L_copy_32_chars_exit);
7569 subptr(len, 16);
7570 jccb(Assembler::greater, L_copy_16_chars_exit);
7571
7572 } else if (UseSSE42Intrinsics) {
7573 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector
7574 movdl(tmp1Reg, tmp5);
7575 pshufd(tmp1Reg, tmp1Reg, 0);
7576 jmpb(L_chars_16_check);
7577 }
7578
7579 bind(L_copy_16_chars);
7580 if (UseAVX >= 2) {
7581 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
7582 vptest(tmp2Reg, tmp1Reg);
7583 jcc(Assembler::notZero, L_copy_16_chars_exit);
7584 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1);
7585 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1);
7586 } else {
7587 if (UseAVX > 0) {
7588 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
7589 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
7590 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0);
7591 } else {
7592 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
7593 por(tmp2Reg, tmp3Reg);
7594 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
7595 por(tmp2Reg, tmp4Reg);
7596 }
7597 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
7598 jccb(Assembler::notZero, L_copy_16_chars_exit);
7599 packuswb(tmp3Reg, tmp4Reg);
7600 }
7601 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
7602
7603 bind(L_chars_16_check);
7604 addptr(len, 16);
7605 jcc(Assembler::lessEqual, L_copy_16_chars);
7606
7607 bind(L_copy_16_chars_exit);
7608 if (UseAVX >= 2) {
7609 // clean upper bits of YMM registers
7610 vpxor(tmp2Reg, tmp2Reg);
7611 vpxor(tmp3Reg, tmp3Reg);
7612 vpxor(tmp4Reg, tmp4Reg);
7613 movdl(tmp1Reg, tmp5);
7614 pshufd(tmp1Reg, tmp1Reg, 0);
7615 }
7616 subptr(len, 8);
7617 jccb(Assembler::greater, L_copy_8_chars_exit);
7618
7619 bind(L_copy_8_chars);
7620 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
7621 ptest(tmp3Reg, tmp1Reg);
7622 jccb(Assembler::notZero, L_copy_8_chars_exit);
7623 packuswb(tmp3Reg, tmp1Reg);
7624 movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
7625 addptr(len, 8);
7626 jccb(Assembler::lessEqual, L_copy_8_chars);
7627
7628 bind(L_copy_8_chars_exit);
7629 subptr(len, 8);
7630 jccb(Assembler::zero, L_done);
7631 }
7632
7633 bind(L_copy_1_char);
7634 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
7635 testl(tmp5, 0xff00); // check if Unicode char
7636 jccb(Assembler::notZero, L_copy_1_char_exit);
7637 movb(Address(dst, len, Address::times_1, 0), tmp5);
7638 addptr(len, 1);
7639 jccb(Assembler::less, L_copy_1_char);
7640
7641 bind(L_copy_1_char_exit);
7642 addptr(result, len); // len is negative count of not processed elements
7643
7644 bind(L_done);
7645 }
7646
7647 #ifdef _LP64
7648 /**
7649 * Helper for multiply_to_len().
7650 */
7651 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
7652 addq(dest_lo, src1);
7653 adcq(dest_hi, 0);
7654 addq(dest_lo, src2);
7655 adcq(dest_hi, 0);
7656 }
7657
7658 /**
7659 * Multiply 64 bit by 64 bit first loop.
7660 */
7661 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
7662 Register y, Register y_idx, Register z,
7663 Register carry, Register product,
7664 Register idx, Register kdx) {
7665 //
7666 // jlong carry, x[], y[], z[];
7667 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7668 // huge_128 product = y[idx] * x[xstart] + carry;
7669 // z[kdx] = (jlong)product;
7670 // carry = (jlong)(product >>> 64);
7671 // }
7672 // z[xstart] = carry;
7673 //
7674
7675 Label L_first_loop, L_first_loop_exit;
7676 Label L_one_x, L_one_y, L_multiply;
7677
7678 decrementl(xstart);
7679 jcc(Assembler::negative, L_one_x);
7680
7681 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
7682 rorq(x_xstart, 32); // convert big-endian to little-endian
7683
7684 bind(L_first_loop);
7685 decrementl(idx);
7686 jcc(Assembler::negative, L_first_loop_exit);
7687 decrementl(idx);
7688 jcc(Assembler::negative, L_one_y);
7689 movq(y_idx, Address(y, idx, Address::times_4, 0));
7690 rorq(y_idx, 32); // convert big-endian to little-endian
7691 bind(L_multiply);
7692 movq(product, x_xstart);
7693 mulq(y_idx); // product(rax) * y_idx -> rdx:rax
7694 addq(product, carry);
7695 adcq(rdx, 0);
7696 subl(kdx, 2);
7697 movl(Address(z, kdx, Address::times_4, 4), product);
7698 shrq(product, 32);
7699 movl(Address(z, kdx, Address::times_4, 0), product);
7700 movq(carry, rdx);
7701 jmp(L_first_loop);
7702
7703 bind(L_one_y);
7704 movl(y_idx, Address(y, 0));
7705 jmp(L_multiply);
7706
7707 bind(L_one_x);
7708 movl(x_xstart, Address(x, 0));
7709 jmp(L_first_loop);
7710
7711 bind(L_first_loop_exit);
7712 }
7713
7714 /**
7715 * Multiply 64 bit by 64 bit and add 128 bit.
7716 */
7717 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
7718 Register yz_idx, Register idx,
7719 Register carry, Register product, int offset) {
7720 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
7721 // z[kdx] = (jlong)product;
7722
7723 movq(yz_idx, Address(y, idx, Address::times_4, offset));
7724 rorq(yz_idx, 32); // convert big-endian to little-endian
7725 movq(product, x_xstart);
7726 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7727 movq(yz_idx, Address(z, idx, Address::times_4, offset));
7728 rorq(yz_idx, 32); // convert big-endian to little-endian
7729
7730 add2_with_carry(rdx, product, carry, yz_idx);
7731
7732 movl(Address(z, idx, Address::times_4, offset+4), product);
7733 shrq(product, 32);
7734 movl(Address(z, idx, Address::times_4, offset), product);
7735
7736 }
7737
7738 /**
7739 * Multiply 128 bit by 128 bit. Unrolled inner loop.
7740 */
7741 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
7742 Register yz_idx, Register idx, Register jdx,
7743 Register carry, Register product,
7744 Register carry2) {
7745 // jlong carry, x[], y[], z[];
7746 // int kdx = ystart+1;
7747 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7748 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
7749 // z[kdx+idx+1] = (jlong)product;
7750 // jlong carry2 = (jlong)(product >>> 64);
7751 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
7752 // z[kdx+idx] = (jlong)product;
7753 // carry = (jlong)(product >>> 64);
7754 // }
7755 // idx += 2;
7756 // if (idx > 0) {
7757 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
7758 // z[kdx+idx] = (jlong)product;
7759 // carry = (jlong)(product >>> 64);
7760 // }
7761 //
7762
7763 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7764
7765 movl(jdx, idx);
7766 andl(jdx, 0xFFFFFFFC);
7767 shrl(jdx, 2);
7768
7769 bind(L_third_loop);
7770 subl(jdx, 1);
7771 jcc(Assembler::negative, L_third_loop_exit);
7772 subl(idx, 4);
7773
7774 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
7775 movq(carry2, rdx);
7776
7777 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
7778 movq(carry, rdx);
7779 jmp(L_third_loop);
7780
7781 bind (L_third_loop_exit);
7782
7783 andl (idx, 0x3);
7784 jcc(Assembler::zero, L_post_third_loop_done);
7785
7786 Label L_check_1;
7787 subl(idx, 2);
7788 jcc(Assembler::negative, L_check_1);
7789
7790 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
7791 movq(carry, rdx);
7792
7793 bind (L_check_1);
7794 addl (idx, 0x2);
7795 andl (idx, 0x1);
7796 subl(idx, 1);
7797 jcc(Assembler::negative, L_post_third_loop_done);
7798
7799 movl(yz_idx, Address(y, idx, Address::times_4, 0));
7800 movq(product, x_xstart);
7801 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7802 movl(yz_idx, Address(z, idx, Address::times_4, 0));
7803
7804 add2_with_carry(rdx, product, yz_idx, carry);
7805
7806 movl(Address(z, idx, Address::times_4, 0), product);
7807 shrq(product, 32);
7808
7809 shlq(rdx, 32);
7810 orq(product, rdx);
7811 movq(carry, product);
7812
7813 bind(L_post_third_loop_done);
7814 }
7815
7816 /**
7817 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
7818 *
7819 */
7820 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
7821 Register carry, Register carry2,
7822 Register idx, Register jdx,
7823 Register yz_idx1, Register yz_idx2,
7824 Register tmp, Register tmp3, Register tmp4) {
7825 assert(UseBMI2Instructions, "should be used only when BMI2 is available");
7826
7827 // jlong carry, x[], y[], z[];
7828 // int kdx = ystart+1;
7829 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7830 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
7831 // jlong carry2 = (jlong)(tmp3 >>> 64);
7832 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2;
7833 // carry = (jlong)(tmp4 >>> 64);
7834 // z[kdx+idx+1] = (jlong)tmp3;
7835 // z[kdx+idx] = (jlong)tmp4;
7836 // }
7837 // idx += 2;
7838 // if (idx > 0) {
7839 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
7840 // z[kdx+idx] = (jlong)yz_idx1;
7841 // carry = (jlong)(yz_idx1 >>> 64);
7842 // }
7843 //
7844
7845 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7846
7847 movl(jdx, idx);
7848 andl(jdx, 0xFFFFFFFC);
7849 shrl(jdx, 2);
7850
7851 bind(L_third_loop);
7852 subl(jdx, 1);
7853 jcc(Assembler::negative, L_third_loop_exit);
7854 subl(idx, 4);
7855
7856 movq(yz_idx1, Address(y, idx, Address::times_4, 8));
7857 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
7858 movq(yz_idx2, Address(y, idx, Address::times_4, 0));
7859 rorxq(yz_idx2, yz_idx2, 32);
7860
7861 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7862 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp
7863
7864 movq(yz_idx1, Address(z, idx, Address::times_4, 8));
7865 rorxq(yz_idx1, yz_idx1, 32);
7866 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7867 rorxq(yz_idx2, yz_idx2, 32);
7868
7869 if (VM_Version::supports_adx()) {
7870 adcxq(tmp3, carry);
7871 adoxq(tmp3, yz_idx1);
7872
7873 adcxq(tmp4, tmp);
7874 adoxq(tmp4, yz_idx2);
7875
7876 movl(carry, 0); // does not affect flags
7877 adcxq(carry2, carry);
7878 adoxq(carry2, carry);
7879 } else {
7880 add2_with_carry(tmp4, tmp3, carry, yz_idx1);
7881 add2_with_carry(carry2, tmp4, tmp, yz_idx2);
7882 }
7883 movq(carry, carry2);
7884
7885 movl(Address(z, idx, Address::times_4, 12), tmp3);
7886 shrq(tmp3, 32);
7887 movl(Address(z, idx, Address::times_4, 8), tmp3);
7888
7889 movl(Address(z, idx, Address::times_4, 4), tmp4);
7890 shrq(tmp4, 32);
7891 movl(Address(z, idx, Address::times_4, 0), tmp4);
7892
7893 jmp(L_third_loop);
7894
7895 bind (L_third_loop_exit);
7896
7897 andl (idx, 0x3);
7898 jcc(Assembler::zero, L_post_third_loop_done);
7899
7900 Label L_check_1;
7901 subl(idx, 2);
7902 jcc(Assembler::negative, L_check_1);
7903
7904 movq(yz_idx1, Address(y, idx, Address::times_4, 0));
7905 rorxq(yz_idx1, yz_idx1, 32);
7906 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7907 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7908 rorxq(yz_idx2, yz_idx2, 32);
7909
7910 add2_with_carry(tmp4, tmp3, carry, yz_idx2);
7911
7912 movl(Address(z, idx, Address::times_4, 4), tmp3);
7913 shrq(tmp3, 32);
7914 movl(Address(z, idx, Address::times_4, 0), tmp3);
7915 movq(carry, tmp4);
7916
7917 bind (L_check_1);
7918 addl (idx, 0x2);
7919 andl (idx, 0x1);
7920 subl(idx, 1);
7921 jcc(Assembler::negative, L_post_third_loop_done);
7922 movl(tmp4, Address(y, idx, Address::times_4, 0));
7923 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3
7924 movl(tmp4, Address(z, idx, Address::times_4, 0));
7925
7926 add2_with_carry(carry2, tmp3, tmp4, carry);
7927
7928 movl(Address(z, idx, Address::times_4, 0), tmp3);
7929 shrq(tmp3, 32);
7930
7931 shlq(carry2, 32);
7932 orq(tmp3, carry2);
7933 movq(carry, tmp3);
7934
7935 bind(L_post_third_loop_done);
7936 }
7937
7938 /**
7939 * Code for BigInteger::multiplyToLen() instrinsic.
7940 *
7941 * rdi: x
7942 * rax: xlen
7943 * rsi: y
7944 * rcx: ylen
7945 * r8: z
7946 * r11: zlen
7947 * r12: tmp1
7948 * r13: tmp2
7949 * r14: tmp3
7950 * r15: tmp4
7951 * rbx: tmp5
7952 *
7953 */
7954 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
7955 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
7956 ShortBranchVerifier sbv(this);
7957 assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
7958
7959 push(tmp1);
7960 push(tmp2);
7961 push(tmp3);
7962 push(tmp4);
7963 push(tmp5);
7964
7965 push(xlen);
7966 push(zlen);
7967
7968 const Register idx = tmp1;
7969 const Register kdx = tmp2;
7970 const Register xstart = tmp3;
7971
7972 const Register y_idx = tmp4;
7973 const Register carry = tmp5;
7974 const Register product = xlen;
7975 const Register x_xstart = zlen; // reuse register
7976
7977 // First Loop.
7978 //
7979 // final static long LONG_MASK = 0xffffffffL;
7980 // int xstart = xlen - 1;
7981 // int ystart = ylen - 1;
7982 // long carry = 0;
7983 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7984 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
7985 // z[kdx] = (int)product;
7986 // carry = product >>> 32;
7987 // }
7988 // z[xstart] = (int)carry;
7989 //
7990
7991 movl(idx, ylen); // idx = ylen;
7992 movl(kdx, zlen); // kdx = xlen+ylen;
7993 xorq(carry, carry); // carry = 0;
7994
7995 Label L_done;
7996
7997 movl(xstart, xlen);
7998 decrementl(xstart);
7999 jcc(Assembler::negative, L_done);
8000
8001 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
8002
8003 Label L_second_loop;
8004 testl(kdx, kdx);
8005 jcc(Assembler::zero, L_second_loop);
8006
8007 Label L_carry;
8008 subl(kdx, 1);
8009 jcc(Assembler::zero, L_carry);
8010
8011 movl(Address(z, kdx, Address::times_4, 0), carry);
8012 shrq(carry, 32);
8013 subl(kdx, 1);
8014
8015 bind(L_carry);
8016 movl(Address(z, kdx, Address::times_4, 0), carry);
8017
8018 // Second and third (nested) loops.
8019 //
8020 // for (int i = xstart-1; i >= 0; i--) { // Second loop
8021 // carry = 0;
8022 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
8023 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
8024 // (z[k] & LONG_MASK) + carry;
8025 // z[k] = (int)product;
8026 // carry = product >>> 32;
8027 // }
8028 // z[i] = (int)carry;
8029 // }
8030 //
8031 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
8032
8033 const Register jdx = tmp1;
8034
8035 bind(L_second_loop);
8036 xorl(carry, carry); // carry = 0;
8037 movl(jdx, ylen); // j = ystart+1
8038
8039 subl(xstart, 1); // i = xstart-1;
8040 jcc(Assembler::negative, L_done);
8041
8042 push (z);
8043
8044 Label L_last_x;
8045 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
8046 subl(xstart, 1); // i = xstart-1;
8047 jcc(Assembler::negative, L_last_x);
8048
8049 if (UseBMI2Instructions) {
8050 movq(rdx, Address(x, xstart, Address::times_4, 0));
8051 rorxq(rdx, rdx, 32); // convert big-endian to little-endian
8052 } else {
8053 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
8054 rorq(x_xstart, 32); // convert big-endian to little-endian
8055 }
8056
8057 Label L_third_loop_prologue;
8058 bind(L_third_loop_prologue);
8059
8060 push (x);
8061 push (xstart);
8062 push (ylen);
8063
8064
8065 if (UseBMI2Instructions) {
8066 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
8067 } else { // !UseBMI2Instructions
8068 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
8069 }
8070
8071 pop(ylen);
8072 pop(xlen);
8073 pop(x);
8074 pop(z);
8075
8076 movl(tmp3, xlen);
8077 addl(tmp3, 1);
8078 movl(Address(z, tmp3, Address::times_4, 0), carry);
8079 subl(tmp3, 1);
8080 jccb(Assembler::negative, L_done);
8081
8082 shrq(carry, 32);
8083 movl(Address(z, tmp3, Address::times_4, 0), carry);
8084 jmp(L_second_loop);
8085
8086 // Next infrequent code is moved outside loops.
8087 bind(L_last_x);
8088 if (UseBMI2Instructions) {
8089 movl(rdx, Address(x, 0));
8090 } else {
8091 movl(x_xstart, Address(x, 0));
8092 }
8093 jmp(L_third_loop_prologue);
8094
8095 bind(L_done);
8096
8097 pop(zlen);
8098 pop(xlen);
8099
8100 pop(tmp5);
8101 pop(tmp4);
8102 pop(tmp3);
8103 pop(tmp2);
8104 pop(tmp1);
8105 }
8106
8107 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
8108 Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){
8109 assert(UseSSE42Intrinsics, "SSE4.2 must be enabled.");
8110 Label VECTOR64_LOOP, VECTOR64_TAIL, VECTOR64_NOT_EQUAL, VECTOR32_TAIL;
8111 Label VECTOR32_LOOP, VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP;
8112 Label VECTOR16_TAIL, VECTOR8_TAIL, VECTOR4_TAIL;
8113 Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL;
8114 Label SAME_TILL_END, DONE;
8115 Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL;
8116
8117 //scale is in rcx in both Win64 and Unix
8118 ShortBranchVerifier sbv(this);
8119
8120 shlq(length);
8121 xorq(result, result);
8122
8123 if ((UseAVX > 2) &&
8124 VM_Version::supports_avx512vlbw()) {
8125 set_vector_masking(); // opening of the stub context for programming mask registers
8126 cmpq(length, 64);
8127 jcc(Assembler::less, VECTOR32_TAIL);
8128 movq(tmp1, length);
8129 andq(tmp1, 0x3F); // tail count
8130 andq(length, ~(0x3F)); //vector count
8131
8132 bind(VECTOR64_LOOP);
8133 // AVX512 code to compare 64 byte vectors.
8134 evmovdqub(rymm0, Address(obja, result), Assembler::AVX_512bit);
8135 evpcmpeqb(k7, rymm0, Address(objb, result), Assembler::AVX_512bit);
8136 kortestql(k7, k7);
8137 jcc(Assembler::aboveEqual, VECTOR64_NOT_EQUAL); // mismatch
8138 addq(result, 64);
8139 subq(length, 64);
8140 jccb(Assembler::notZero, VECTOR64_LOOP);
8141
8142 //bind(VECTOR64_TAIL);
8143 testq(tmp1, tmp1);
8144 jcc(Assembler::zero, SAME_TILL_END);
8145
8146 bind(VECTOR64_TAIL);
8147 // AVX512 code to compare upto 63 byte vectors.
8148 // Save k1
8149 kmovql(k3, k1);
8150 mov64(tmp2, 0xFFFFFFFFFFFFFFFF);
8151 shlxq(tmp2, tmp2, tmp1);
8152 notq(tmp2);
8153 kmovql(k1, tmp2);
8154
8155 evmovdqub(rymm0, k1, Address(obja, result), Assembler::AVX_512bit);
8156 evpcmpeqb(k7, k1, rymm0, Address(objb, result), Assembler::AVX_512bit);
8157
8158 ktestql(k7, k1);
8159 // Restore k1
8160 kmovql(k1, k3);
8161 jcc(Assembler::below, SAME_TILL_END); // not mismatch
8162
8163 bind(VECTOR64_NOT_EQUAL);
8164 kmovql(tmp1, k7);
8165 notq(tmp1);
8166 tzcntq(tmp1, tmp1);
8167 addq(result, tmp1);
8168 shrq(result);
8169 jmp(DONE);
8170 bind(VECTOR32_TAIL);
8171 clear_vector_masking(); // closing of the stub context for programming mask registers
8172 }
8173
8174 cmpq(length, 8);
8175 jcc(Assembler::equal, VECTOR8_LOOP);
8176 jcc(Assembler::less, VECTOR4_TAIL);
8177
8178 if (UseAVX >= 2) {
8179
8180 cmpq(length, 16);
8181 jcc(Assembler::equal, VECTOR16_LOOP);
8182 jcc(Assembler::less, VECTOR8_LOOP);
8183
8184 cmpq(length, 32);
8185 jccb(Assembler::less, VECTOR16_TAIL);
8186
8187 subq(length, 32);
8188 bind(VECTOR32_LOOP);
8189 vmovdqu(rymm0, Address(obja, result));
8190 vmovdqu(rymm1, Address(objb, result));
8191 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit);
8192 vptest(rymm2, rymm2);
8193 jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found
8194 addq(result, 32);
8195 subq(length, 32);
8196 jcc(Assembler::greaterEqual, VECTOR32_LOOP);
8197 addq(length, 32);
8198 jcc(Assembler::equal, SAME_TILL_END);
8199 //falling through if less than 32 bytes left //close the branch here.
8200
8201 bind(VECTOR16_TAIL);
8202 cmpq(length, 16);
8203 jccb(Assembler::less, VECTOR8_TAIL);
8204 bind(VECTOR16_LOOP);
8205 movdqu(rymm0, Address(obja, result));
8206 movdqu(rymm1, Address(objb, result));
8207 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit);
8208 ptest(rymm2, rymm2);
8209 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
8210 addq(result, 16);
8211 subq(length, 16);
8212 jcc(Assembler::equal, SAME_TILL_END);
8213 //falling through if less than 16 bytes left
8214 } else {//regular intrinsics
8215
8216 cmpq(length, 16);
8217 jccb(Assembler::less, VECTOR8_TAIL);
8218
8219 subq(length, 16);
8220 bind(VECTOR16_LOOP);
8221 movdqu(rymm0, Address(obja, result));
8222 movdqu(rymm1, Address(objb, result));
8223 pxor(rymm0, rymm1);
8224 ptest(rymm0, rymm0);
8225 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
8226 addq(result, 16);
8227 subq(length, 16);
8228 jccb(Assembler::greaterEqual, VECTOR16_LOOP);
8229 addq(length, 16);
8230 jcc(Assembler::equal, SAME_TILL_END);
8231 //falling through if less than 16 bytes left
8232 }
8233
8234 bind(VECTOR8_TAIL);
8235 cmpq(length, 8);
8236 jccb(Assembler::less, VECTOR4_TAIL);
8237 bind(VECTOR8_LOOP);
8238 movq(tmp1, Address(obja, result));
8239 movq(tmp2, Address(objb, result));
8240 xorq(tmp1, tmp2);
8241 testq(tmp1, tmp1);
8242 jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found
8243 addq(result, 8);
8244 subq(length, 8);
8245 jcc(Assembler::equal, SAME_TILL_END);
8246 //falling through if less than 8 bytes left
8247
8248 bind(VECTOR4_TAIL);
8249 cmpq(length, 4);
8250 jccb(Assembler::less, BYTES_TAIL);
8251 bind(VECTOR4_LOOP);
8252 movl(tmp1, Address(obja, result));
8253 xorl(tmp1, Address(objb, result));
8254 testl(tmp1, tmp1);
8255 jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found
8256 addq(result, 4);
8257 subq(length, 4);
8258 jcc(Assembler::equal, SAME_TILL_END);
8259 //falling through if less than 4 bytes left
8260
8261 bind(BYTES_TAIL);
8262 bind(BYTES_LOOP);
8263 load_unsigned_byte(tmp1, Address(obja, result));
8264 load_unsigned_byte(tmp2, Address(objb, result));
8265 xorl(tmp1, tmp2);
8266 testl(tmp1, tmp1);
8267 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
8268 decq(length);
8269 jcc(Assembler::zero, SAME_TILL_END);
8270 incq(result);
8271 load_unsigned_byte(tmp1, Address(obja, result));
8272 load_unsigned_byte(tmp2, Address(objb, result));
8273 xorl(tmp1, tmp2);
8274 testl(tmp1, tmp1);
8275 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
8276 decq(length);
8277 jcc(Assembler::zero, SAME_TILL_END);
8278 incq(result);
8279 load_unsigned_byte(tmp1, Address(obja, result));
8280 load_unsigned_byte(tmp2, Address(objb, result));
8281 xorl(tmp1, tmp2);
8282 testl(tmp1, tmp1);
8283 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
8284 jmp(SAME_TILL_END);
8285
8286 if (UseAVX >= 2) {
8287 bind(VECTOR32_NOT_EQUAL);
8288 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit);
8289 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit);
8290 vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit);
8291 vpmovmskb(tmp1, rymm0);
8292 bsfq(tmp1, tmp1);
8293 addq(result, tmp1);
8294 shrq(result);
8295 jmp(DONE);
8296 }
8297
8298 bind(VECTOR16_NOT_EQUAL);
8299 if (UseAVX >= 2) {
8300 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit);
8301 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit);
8302 pxor(rymm0, rymm2);
8303 } else {
8304 pcmpeqb(rymm2, rymm2);
8305 pxor(rymm0, rymm1);
8306 pcmpeqb(rymm0, rymm1);
8307 pxor(rymm0, rymm2);
8308 }
8309 pmovmskb(tmp1, rymm0);
8310 bsfq(tmp1, tmp1);
8311 addq(result, tmp1);
8312 shrq(result);
8313 jmpb(DONE);
8314
8315 bind(VECTOR8_NOT_EQUAL);
8316 bind(VECTOR4_NOT_EQUAL);
8317 bsfq(tmp1, tmp1);
8318 shrq(tmp1, 3);
8319 addq(result, tmp1);
8320 bind(BYTES_NOT_EQUAL);
8321 shrq(result);
8322 jmpb(DONE);
8323
8324 bind(SAME_TILL_END);
8325 mov64(result, -1);
8326
8327 bind(DONE);
8328 }
8329
8330 //Helper functions for square_to_len()
8331
8332 /**
8333 * Store the squares of x[], right shifted one bit (divided by 2) into z[]
8334 * Preserves x and z and modifies rest of the registers.
8335 */
8336 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8337 // Perform square and right shift by 1
8338 // Handle odd xlen case first, then for even xlen do the following
8339 // jlong carry = 0;
8340 // for (int j=0, i=0; j < xlen; j+=2, i+=4) {
8341 // huge_128 product = x[j:j+1] * x[j:j+1];
8342 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65);
8343 // z[i+2:i+3] = (jlong)(product >>> 1);
8344 // carry = (jlong)product;
8345 // }
8346
8347 xorq(tmp5, tmp5); // carry
8348 xorq(rdxReg, rdxReg);
8349 xorl(tmp1, tmp1); // index for x
8350 xorl(tmp4, tmp4); // index for z
8351
8352 Label L_first_loop, L_first_loop_exit;
8353
8354 testl(xlen, 1);
8355 jccb(Assembler::zero, L_first_loop); //jump if xlen is even
8356
8357 // Square and right shift by 1 the odd element using 32 bit multiply
8358 movl(raxReg, Address(x, tmp1, Address::times_4, 0));
8359 imulq(raxReg, raxReg);
8360 shrq(raxReg, 1);
8361 adcq(tmp5, 0);
8362 movq(Address(z, tmp4, Address::times_4, 0), raxReg);
8363 incrementl(tmp1);
8364 addl(tmp4, 2);
8365
8366 // Square and right shift by 1 the rest using 64 bit multiply
8367 bind(L_first_loop);
8368 cmpptr(tmp1, xlen);
8369 jccb(Assembler::equal, L_first_loop_exit);
8370
8371 // Square
8372 movq(raxReg, Address(x, tmp1, Address::times_4, 0));
8373 rorq(raxReg, 32); // convert big-endian to little-endian
8374 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax
8375
8376 // Right shift by 1 and save carry
8377 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1
8378 rcrq(rdxReg, 1);
8379 rcrq(raxReg, 1);
8380 adcq(tmp5, 0);
8381
8382 // Store result in z
8383 movq(Address(z, tmp4, Address::times_4, 0), rdxReg);
8384 movq(Address(z, tmp4, Address::times_4, 8), raxReg);
8385
8386 // Update indices for x and z
8387 addl(tmp1, 2);
8388 addl(tmp4, 4);
8389 jmp(L_first_loop);
8390
8391 bind(L_first_loop_exit);
8392 }
8393
8394
8395 /**
8396 * Perform the following multiply add operation using BMI2 instructions
8397 * carry:sum = sum + op1*op2 + carry
8398 * op2 should be in rdx
8399 * op2 is preserved, all other registers are modified
8400 */
8401 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) {
8402 // assert op2 is rdx
8403 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1
8404 addq(sum, carry);
8405 adcq(tmp2, 0);
8406 addq(sum, op1);
8407 adcq(tmp2, 0);
8408 movq(carry, tmp2);
8409 }
8410
8411 /**
8412 * Perform the following multiply add operation:
8413 * carry:sum = sum + op1*op2 + carry
8414 * Preserves op1, op2 and modifies rest of registers
8415 */
8416 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) {
8417 // rdx:rax = op1 * op2
8418 movq(raxReg, op2);
8419 mulq(op1);
8420
8421 // rdx:rax = sum + carry + rdx:rax
8422 addq(sum, carry);
8423 adcq(rdxReg, 0);
8424 addq(sum, raxReg);
8425 adcq(rdxReg, 0);
8426
8427 // carry:sum = rdx:sum
8428 movq(carry, rdxReg);
8429 }
8430
8431 /**
8432 * Add 64 bit long carry into z[] with carry propogation.
8433 * Preserves z and carry register values and modifies rest of registers.
8434 *
8435 */
8436 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) {
8437 Label L_fourth_loop, L_fourth_loop_exit;
8438
8439 movl(tmp1, 1);
8440 subl(zlen, 2);
8441 addq(Address(z, zlen, Address::times_4, 0), carry);
8442
8443 bind(L_fourth_loop);
8444 jccb(Assembler::carryClear, L_fourth_loop_exit);
8445 subl(zlen, 2);
8446 jccb(Assembler::negative, L_fourth_loop_exit);
8447 addq(Address(z, zlen, Address::times_4, 0), tmp1);
8448 jmp(L_fourth_loop);
8449 bind(L_fourth_loop_exit);
8450 }
8451
8452 /**
8453 * Shift z[] left by 1 bit.
8454 * Preserves x, len, z and zlen registers and modifies rest of the registers.
8455 *
8456 */
8457 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
8458
8459 Label L_fifth_loop, L_fifth_loop_exit;
8460
8461 // Fifth loop
8462 // Perform primitiveLeftShift(z, zlen, 1)
8463
8464 const Register prev_carry = tmp1;
8465 const Register new_carry = tmp4;
8466 const Register value = tmp2;
8467 const Register zidx = tmp3;
8468
8469 // int zidx, carry;
8470 // long value;
8471 // carry = 0;
8472 // for (zidx = zlen-2; zidx >=0; zidx -= 2) {
8473 // (carry:value) = (z[i] << 1) | carry ;
8474 // z[i] = value;
8475 // }
8476
8477 movl(zidx, zlen);
8478 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register
8479
8480 bind(L_fifth_loop);
8481 decl(zidx); // Use decl to preserve carry flag
8482 decl(zidx);
8483 jccb(Assembler::negative, L_fifth_loop_exit);
8484
8485 if (UseBMI2Instructions) {
8486 movq(value, Address(z, zidx, Address::times_4, 0));
8487 rclq(value, 1);
8488 rorxq(value, value, 32);
8489 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
8490 }
8491 else {
8492 // clear new_carry
8493 xorl(new_carry, new_carry);
8494
8495 // Shift z[i] by 1, or in previous carry and save new carry
8496 movq(value, Address(z, zidx, Address::times_4, 0));
8497 shlq(value, 1);
8498 adcl(new_carry, 0);
8499
8500 orq(value, prev_carry);
8501 rorq(value, 0x20);
8502 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
8503
8504 // Set previous carry = new carry
8505 movl(prev_carry, new_carry);
8506 }
8507 jmp(L_fifth_loop);
8508
8509 bind(L_fifth_loop_exit);
8510 }
8511
8512
8513 /**
8514 * Code for BigInteger::squareToLen() intrinsic
8515 *
8516 * rdi: x
8517 * rsi: len
8518 * r8: z
8519 * rcx: zlen
8520 * r12: tmp1
8521 * r13: tmp2
8522 * r14: tmp3
8523 * r15: tmp4
8524 * rbx: tmp5
8525 *
8526 */
8527 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8528
8529 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, fifth_loop, fifth_loop_exit, L_last_x, L_multiply;
8530 push(tmp1);
8531 push(tmp2);
8532 push(tmp3);
8533 push(tmp4);
8534 push(tmp5);
8535
8536 // First loop
8537 // Store the squares, right shifted one bit (i.e., divided by 2).
8538 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg);
8539
8540 // Add in off-diagonal sums.
8541 //
8542 // Second, third (nested) and fourth loops.
8543 // zlen +=2;
8544 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) {
8545 // carry = 0;
8546 // long op2 = x[xidx:xidx+1];
8547 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) {
8548 // k -= 2;
8549 // long op1 = x[j:j+1];
8550 // long sum = z[k:k+1];
8551 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs);
8552 // z[k:k+1] = sum;
8553 // }
8554 // add_one_64(z, k, carry, tmp_regs);
8555 // }
8556
8557 const Register carry = tmp5;
8558 const Register sum = tmp3;
8559 const Register op1 = tmp4;
8560 Register op2 = tmp2;
8561
8562 push(zlen);
8563 push(len);
8564 addl(zlen,2);
8565 bind(L_second_loop);
8566 xorq(carry, carry);
8567 subl(zlen, 4);
8568 subl(len, 2);
8569 push(zlen);
8570 push(len);
8571 cmpl(len, 0);
8572 jccb(Assembler::lessEqual, L_second_loop_exit);
8573
8574 // Multiply an array by one 64 bit long.
8575 if (UseBMI2Instructions) {
8576 op2 = rdxReg;
8577 movq(op2, Address(x, len, Address::times_4, 0));
8578 rorxq(op2, op2, 32);
8579 }
8580 else {
8581 movq(op2, Address(x, len, Address::times_4, 0));
8582 rorq(op2, 32);
8583 }
8584
8585 bind(L_third_loop);
8586 decrementl(len);
8587 jccb(Assembler::negative, L_third_loop_exit);
8588 decrementl(len);
8589 jccb(Assembler::negative, L_last_x);
8590
8591 movq(op1, Address(x, len, Address::times_4, 0));
8592 rorq(op1, 32);
8593
8594 bind(L_multiply);
8595 subl(zlen, 2);
8596 movq(sum, Address(z, zlen, Address::times_4, 0));
8597
8598 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry.
8599 if (UseBMI2Instructions) {
8600 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2);
8601 }
8602 else {
8603 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8604 }
8605
8606 movq(Address(z, zlen, Address::times_4, 0), sum);
8607
8608 jmp(L_third_loop);
8609 bind(L_third_loop_exit);
8610
8611 // Fourth loop
8612 // Add 64 bit long carry into z with carry propogation.
8613 // Uses offsetted zlen.
8614 add_one_64(z, zlen, carry, tmp1);
8615
8616 pop(len);
8617 pop(zlen);
8618 jmp(L_second_loop);
8619
8620 // Next infrequent code is moved outside loops.
8621 bind(L_last_x);
8622 movl(op1, Address(x, 0));
8623 jmp(L_multiply);
8624
8625 bind(L_second_loop_exit);
8626 pop(len);
8627 pop(zlen);
8628 pop(len);
8629 pop(zlen);
8630
8631 // Fifth loop
8632 // Shift z left 1 bit.
8633 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4);
8634
8635 // z[zlen-1] |= x[len-1] & 1;
8636 movl(tmp3, Address(x, len, Address::times_4, -4));
8637 andl(tmp3, 1);
8638 orl(Address(z, zlen, Address::times_4, -4), tmp3);
8639
8640 pop(tmp5);
8641 pop(tmp4);
8642 pop(tmp3);
8643 pop(tmp2);
8644 pop(tmp1);
8645 }
8646
8647 /**
8648 * Helper function for mul_add()
8649 * Multiply the in[] by int k and add to out[] starting at offset offs using
8650 * 128 bit by 32 bit multiply and return the carry in tmp5.
8651 * Only quad int aligned length of in[] is operated on in this function.
8652 * k is in rdxReg for BMI2Instructions, for others it is in tmp2.
8653 * This function preserves out, in and k registers.
8654 * len and offset point to the appropriate index in "in" & "out" correspondingly
8655 * tmp5 has the carry.
8656 * other registers are temporary and are modified.
8657 *
8658 */
8659 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in,
8660 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3,
8661 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8662
8663 Label L_first_loop, L_first_loop_exit;
8664
8665 movl(tmp1, len);
8666 shrl(tmp1, 2);
8667
8668 bind(L_first_loop);
8669 subl(tmp1, 1);
8670 jccb(Assembler::negative, L_first_loop_exit);
8671
8672 subl(len, 4);
8673 subl(offset, 4);
8674
8675 Register op2 = tmp2;
8676 const Register sum = tmp3;
8677 const Register op1 = tmp4;
8678 const Register carry = tmp5;
8679
8680 if (UseBMI2Instructions) {
8681 op2 = rdxReg;
8682 }
8683
8684 movq(op1, Address(in, len, Address::times_4, 8));
8685 rorq(op1, 32);
8686 movq(sum, Address(out, offset, Address::times_4, 8));
8687 rorq(sum, 32);
8688 if (UseBMI2Instructions) {
8689 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8690 }
8691 else {
8692 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8693 }
8694 // Store back in big endian from little endian
8695 rorq(sum, 0x20);
8696 movq(Address(out, offset, Address::times_4, 8), sum);
8697
8698 movq(op1, Address(in, len, Address::times_4, 0));
8699 rorq(op1, 32);
8700 movq(sum, Address(out, offset, Address::times_4, 0));
8701 rorq(sum, 32);
8702 if (UseBMI2Instructions) {
8703 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8704 }
8705 else {
8706 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8707 }
8708 // Store back in big endian from little endian
8709 rorq(sum, 0x20);
8710 movq(Address(out, offset, Address::times_4, 0), sum);
8711
8712 jmp(L_first_loop);
8713 bind(L_first_loop_exit);
8714 }
8715
8716 /**
8717 * Code for BigInteger::mulAdd() intrinsic
8718 *
8719 * rdi: out
8720 * rsi: in
8721 * r11: offs (out.length - offset)
8722 * rcx: len
8723 * r8: k
8724 * r12: tmp1
8725 * r13: tmp2
8726 * r14: tmp3
8727 * r15: tmp4
8728 * rbx: tmp5
8729 * Multiply the in[] by word k and add to out[], return the carry in rax
8730 */
8731 void MacroAssembler::mul_add(Register out, Register in, Register offs,
8732 Register len, Register k, Register tmp1, Register tmp2, Register tmp3,
8733 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8734
8735 Label L_carry, L_last_in, L_done;
8736
8737 // carry = 0;
8738 // for (int j=len-1; j >= 0; j--) {
8739 // long product = (in[j] & LONG_MASK) * kLong +
8740 // (out[offs] & LONG_MASK) + carry;
8741 // out[offs--] = (int)product;
8742 // carry = product >>> 32;
8743 // }
8744 //
8745 push(tmp1);
8746 push(tmp2);
8747 push(tmp3);
8748 push(tmp4);
8749 push(tmp5);
8750
8751 Register op2 = tmp2;
8752 const Register sum = tmp3;
8753 const Register op1 = tmp4;
8754 const Register carry = tmp5;
8755
8756 if (UseBMI2Instructions) {
8757 op2 = rdxReg;
8758 movl(op2, k);
8759 }
8760 else {
8761 movl(op2, k);
8762 }
8763
8764 xorq(carry, carry);
8765
8766 //First loop
8767
8768 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply
8769 //The carry is in tmp5
8770 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg);
8771
8772 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any
8773 decrementl(len);
8774 jccb(Assembler::negative, L_carry);
8775 decrementl(len);
8776 jccb(Assembler::negative, L_last_in);
8777
8778 movq(op1, Address(in, len, Address::times_4, 0));
8779 rorq(op1, 32);
8780
8781 subl(offs, 2);
8782 movq(sum, Address(out, offs, Address::times_4, 0));
8783 rorq(sum, 32);
8784
8785 if (UseBMI2Instructions) {
8786 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8787 }
8788 else {
8789 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8790 }
8791
8792 // Store back in big endian from little endian
8793 rorq(sum, 0x20);
8794 movq(Address(out, offs, Address::times_4, 0), sum);
8795
8796 testl(len, len);
8797 jccb(Assembler::zero, L_carry);
8798
8799 //Multiply the last in[] entry, if any
8800 bind(L_last_in);
8801 movl(op1, Address(in, 0));
8802 movl(sum, Address(out, offs, Address::times_4, -4));
8803
8804 movl(raxReg, k);
8805 mull(op1); //tmp4 * eax -> edx:eax
8806 addl(sum, carry);
8807 adcl(rdxReg, 0);
8808 addl(sum, raxReg);
8809 adcl(rdxReg, 0);
8810 movl(carry, rdxReg);
8811
8812 movl(Address(out, offs, Address::times_4, -4), sum);
8813
8814 bind(L_carry);
8815 //return tmp5/carry as carry in rax
8816 movl(rax, carry);
8817
8818 bind(L_done);
8819 pop(tmp5);
8820 pop(tmp4);
8821 pop(tmp3);
8822 pop(tmp2);
8823 pop(tmp1);
8824 }
8825 #endif
8826
8827 /**
8828 * Emits code to update CRC-32 with a byte value according to constants in table
8829 *
8830 * @param [in,out]crc Register containing the crc.
8831 * @param [in]val Register containing the byte to fold into the CRC.
8832 * @param [in]table Register containing the table of crc constants.
8833 *
8834 * uint32_t crc;
8835 * val = crc_table[(val ^ crc) & 0xFF];
8836 * crc = val ^ (crc >> 8);
8837 *
8838 */
8839 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
8840 xorl(val, crc);
8841 andl(val, 0xFF);
8842 shrl(crc, 8); // unsigned shift
8843 xorl(crc, Address(table, val, Address::times_4, 0));
8844 }
8845
8846 /**
8847 * Fold four 128-bit data chunks
8848 */
8849 void MacroAssembler::fold_128bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
8850 evpclmulhdq(xtmp, xK, xcrc, Assembler::AVX_512bit); // [123:64]
8851 evpclmulldq(xcrc, xK, xcrc, Assembler::AVX_512bit); // [63:0]
8852 evpxorq(xcrc, xcrc, Address(buf, offset), Assembler::AVX_512bit /* vector_len */);
8853 evpxorq(xcrc, xcrc, xtmp, Assembler::AVX_512bit /* vector_len */);
8854 }
8855
8856 /**
8857 * Fold 128-bit data chunk
8858 */
8859 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
8860 if (UseAVX > 0) {
8861 vpclmulhdq(xtmp, xK, xcrc); // [123:64]
8862 vpclmulldq(xcrc, xK, xcrc); // [63:0]
8863 vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */);
8864 pxor(xcrc, xtmp);
8865 } else {
8866 movdqa(xtmp, xcrc);
8867 pclmulhdq(xtmp, xK); // [123:64]
8868 pclmulldq(xcrc, xK); // [63:0]
8869 pxor(xcrc, xtmp);
8870 movdqu(xtmp, Address(buf, offset));
8871 pxor(xcrc, xtmp);
8872 }
8873 }
8874
8875 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
8876 if (UseAVX > 0) {
8877 vpclmulhdq(xtmp, xK, xcrc);
8878 vpclmulldq(xcrc, xK, xcrc);
8879 pxor(xcrc, xbuf);
8880 pxor(xcrc, xtmp);
8881 } else {
8882 movdqa(xtmp, xcrc);
8883 pclmulhdq(xtmp, xK);
8884 pclmulldq(xcrc, xK);
8885 pxor(xcrc, xbuf);
8886 pxor(xcrc, xtmp);
8887 }
8888 }
8889
8890 /**
8891 * 8-bit folds to compute 32-bit CRC
8892 *
8893 * uint64_t xcrc;
8894 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
8895 */
8896 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
8897 movdl(tmp, xcrc);
8898 andl(tmp, 0xFF);
8899 movdl(xtmp, Address(table, tmp, Address::times_4, 0));
8900 psrldq(xcrc, 1); // unsigned shift one byte
8901 pxor(xcrc, xtmp);
8902 }
8903
8904 /**
8905 * uint32_t crc;
8906 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
8907 */
8908 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
8909 movl(tmp, crc);
8910 andl(tmp, 0xFF);
8911 shrl(crc, 8);
8912 xorl(crc, Address(table, tmp, Address::times_4, 0));
8913 }
8914
8915 /**
8916 * @param crc register containing existing CRC (32-bit)
8917 * @param buf register pointing to input byte buffer (byte*)
8918 * @param len register containing number of bytes
8919 * @param table register that will contain address of CRC table
8920 * @param tmp scratch register
8921 */
8922 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
8923 assert_different_registers(crc, buf, len, table, tmp, rax);
8924
8925 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
8926 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
8927
8928 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
8929 // context for the registers used, where all instructions below are using 128-bit mode
8930 // On EVEX without VL and BW, these instructions will all be AVX.
8931 if (VM_Version::supports_avx512vlbw()) {
8932 movl(tmp, 0xffff);
8933 kmovwl(k1, tmp);
8934 }
8935
8936 lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
8937 notl(crc); // ~crc
8938 cmpl(len, 16);
8939 jcc(Assembler::less, L_tail);
8940
8941 // Align buffer to 16 bytes
8942 movl(tmp, buf);
8943 andl(tmp, 0xF);
8944 jccb(Assembler::zero, L_aligned);
8945 subl(tmp, 16);
8946 addl(len, tmp);
8947
8948 align(4);
8949 BIND(L_align_loop);
8950 movsbl(rax, Address(buf, 0)); // load byte with sign extension
8951 update_byte_crc32(crc, rax, table);
8952 increment(buf);
8953 incrementl(tmp);
8954 jccb(Assembler::less, L_align_loop);
8955
8956 BIND(L_aligned);
8957 movl(tmp, len); // save
8958 shrl(len, 4);
8959 jcc(Assembler::zero, L_tail_restore);
8960
8961 // Fold total 512 bits of polynomial on each iteration
8962 if (VM_Version::supports_vpclmulqdq()) {
8963 Label Parallel_loop, L_No_Parallel;
8964
8965 cmpl(len, 8);
8966 jccb(Assembler::less, L_No_Parallel);
8967
8968 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32));
8969 evmovdquq(xmm1, Address(buf, 0), Assembler::AVX_512bit);
8970 movdl(xmm5, crc);
8971 evpxorq(xmm1, xmm1, xmm5, Assembler::AVX_512bit);
8972 addptr(buf, 64);
8973 subl(len, 7);
8974 evshufi64x2(xmm0, xmm0, xmm0, 0x00, Assembler::AVX_512bit); //propagate the mask from 128 bits to 512 bits
8975
8976 BIND(Parallel_loop);
8977 fold_128bit_crc32_avx512(xmm1, xmm0, xmm5, buf, 0);
8978 addptr(buf, 64);
8979 subl(len, 4);
8980 jcc(Assembler::greater, Parallel_loop);
8981
8982 vextracti64x2(xmm2, xmm1, 0x01);
8983 vextracti64x2(xmm3, xmm1, 0x02);
8984 vextracti64x2(xmm4, xmm1, 0x03);
8985 jmp(L_fold_512b);
8986
8987 BIND(L_No_Parallel);
8988 }
8989 // Fold crc into first bytes of vector
8990 movdqa(xmm1, Address(buf, 0));
8991 movdl(rax, xmm1);
8992 xorl(crc, rax);
8993 if (VM_Version::supports_sse4_1()) {
8994 pinsrd(xmm1, crc, 0);
8995 } else {
8996 pinsrw(xmm1, crc, 0);
8997 shrl(crc, 16);
8998 pinsrw(xmm1, crc, 1);
8999 }
9000 addptr(buf, 16);
9001 subl(len, 4); // len > 0
9002 jcc(Assembler::less, L_fold_tail);
9003
9004 movdqa(xmm2, Address(buf, 0));
9005 movdqa(xmm3, Address(buf, 16));
9006 movdqa(xmm4, Address(buf, 32));
9007 addptr(buf, 48);
9008 subl(len, 3);
9009 jcc(Assembler::lessEqual, L_fold_512b);
9010
9011 // Fold total 512 bits of polynomial on each iteration,
9012 // 128 bits per each of 4 parallel streams.
9013 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32));
9014
9015 align(32);
9016 BIND(L_fold_512b_loop);
9017 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
9018 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
9019 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
9020 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
9021 addptr(buf, 64);
9022 subl(len, 4);
9023 jcc(Assembler::greater, L_fold_512b_loop);
9024
9025 // Fold 512 bits to 128 bits.
9026 BIND(L_fold_512b);
9027 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
9028 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
9029 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
9030 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
9031
9032 // Fold the rest of 128 bits data chunks
9033 BIND(L_fold_tail);
9034 addl(len, 3);
9035 jccb(Assembler::lessEqual, L_fold_128b);
9036 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
9037
9038 BIND(L_fold_tail_loop);
9039 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
9040 addptr(buf, 16);
9041 decrementl(len);
9042 jccb(Assembler::greater, L_fold_tail_loop);
9043
9044 // Fold 128 bits in xmm1 down into 32 bits in crc register.
9045 BIND(L_fold_128b);
9046 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()));
9047 if (UseAVX > 0) {
9048 vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
9049 vpand(xmm3, xmm0, xmm2, 0 /* vector_len */);
9050 vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
9051 } else {
9052 movdqa(xmm2, xmm0);
9053 pclmulqdq(xmm2, xmm1, 0x1);
9054 movdqa(xmm3, xmm0);
9055 pand(xmm3, xmm2);
9056 pclmulqdq(xmm0, xmm3, 0x1);
9057 }
9058 psrldq(xmm1, 8);
9059 psrldq(xmm2, 4);
9060 pxor(xmm0, xmm1);
9061 pxor(xmm0, xmm2);
9062
9063 // 8 8-bit folds to compute 32-bit CRC.
9064 for (int j = 0; j < 4; j++) {
9065 fold_8bit_crc32(xmm0, table, xmm1, rax);
9066 }
9067 movdl(crc, xmm0); // mov 32 bits to general register
9068 for (int j = 0; j < 4; j++) {
9069 fold_8bit_crc32(crc, table, rax);
9070 }
9071
9072 BIND(L_tail_restore);
9073 movl(len, tmp); // restore
9074 BIND(L_tail);
9075 andl(len, 0xf);
9076 jccb(Assembler::zero, L_exit);
9077
9078 // Fold the rest of bytes
9079 align(4);
9080 BIND(L_tail_loop);
9081 movsbl(rax, Address(buf, 0)); // load byte with sign extension
9082 update_byte_crc32(crc, rax, table);
9083 increment(buf);
9084 decrementl(len);
9085 jccb(Assembler::greater, L_tail_loop);
9086
9087 BIND(L_exit);
9088 notl(crc); // ~c
9089 }
9090
9091 #ifdef _LP64
9092 // S. Gueron / Information Processing Letters 112 (2012) 184
9093 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table.
9094 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0].
9095 // Output: the 64-bit carry-less product of B * CONST
9096 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n,
9097 Register tmp1, Register tmp2, Register tmp3) {
9098 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
9099 if (n > 0) {
9100 addq(tmp3, n * 256 * 8);
9101 }
9102 // Q1 = TABLEExt[n][B & 0xFF];
9103 movl(tmp1, in);
9104 andl(tmp1, 0x000000FF);
9105 shll(tmp1, 3);
9106 addq(tmp1, tmp3);
9107 movq(tmp1, Address(tmp1, 0));
9108
9109 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
9110 movl(tmp2, in);
9111 shrl(tmp2, 8);
9112 andl(tmp2, 0x000000FF);
9113 shll(tmp2, 3);
9114 addq(tmp2, tmp3);
9115 movq(tmp2, Address(tmp2, 0));
9116
9117 shlq(tmp2, 8);
9118 xorq(tmp1, tmp2);
9119
9120 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
9121 movl(tmp2, in);
9122 shrl(tmp2, 16);
9123 andl(tmp2, 0x000000FF);
9124 shll(tmp2, 3);
9125 addq(tmp2, tmp3);
9126 movq(tmp2, Address(tmp2, 0));
9127
9128 shlq(tmp2, 16);
9129 xorq(tmp1, tmp2);
9130
9131 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
9132 shrl(in, 24);
9133 andl(in, 0x000000FF);
9134 shll(in, 3);
9135 addq(in, tmp3);
9136 movq(in, Address(in, 0));
9137
9138 shlq(in, 24);
9139 xorq(in, tmp1);
9140 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
9141 }
9142
9143 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
9144 Register in_out,
9145 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
9146 XMMRegister w_xtmp2,
9147 Register tmp1,
9148 Register n_tmp2, Register n_tmp3) {
9149 if (is_pclmulqdq_supported) {
9150 movdl(w_xtmp1, in_out); // modified blindly
9151
9152 movl(tmp1, const_or_pre_comp_const_index);
9153 movdl(w_xtmp2, tmp1);
9154 pclmulqdq(w_xtmp1, w_xtmp2, 0);
9155
9156 movdq(in_out, w_xtmp1);
9157 } else {
9158 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3);
9159 }
9160 }
9161
9162 // Recombination Alternative 2: No bit-reflections
9163 // T1 = (CRC_A * U1) << 1
9164 // T2 = (CRC_B * U2) << 1
9165 // C1 = T1 >> 32
9166 // C2 = T2 >> 32
9167 // T1 = T1 & 0xFFFFFFFF
9168 // T2 = T2 & 0xFFFFFFFF
9169 // T1 = CRC32(0, T1)
9170 // T2 = CRC32(0, T2)
9171 // C1 = C1 ^ T1
9172 // C2 = C2 ^ T2
9173 // CRC = C1 ^ C2 ^ CRC_C
9174 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
9175 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9176 Register tmp1, Register tmp2,
9177 Register n_tmp3) {
9178 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
9179 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
9180 shlq(in_out, 1);
9181 movl(tmp1, in_out);
9182 shrq(in_out, 32);
9183 xorl(tmp2, tmp2);
9184 crc32(tmp2, tmp1, 4);
9185 xorl(in_out, tmp2); // we don't care about upper 32 bit contents here
9186 shlq(in1, 1);
9187 movl(tmp1, in1);
9188 shrq(in1, 32);
9189 xorl(tmp2, tmp2);
9190 crc32(tmp2, tmp1, 4);
9191 xorl(in1, tmp2);
9192 xorl(in_out, in1);
9193 xorl(in_out, in2);
9194 }
9195
9196 // Set N to predefined value
9197 // Subtract from a lenght of a buffer
9198 // execute in a loop:
9199 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0
9200 // for i = 1 to N do
9201 // CRC_A = CRC32(CRC_A, A[i])
9202 // CRC_B = CRC32(CRC_B, B[i])
9203 // CRC_C = CRC32(CRC_C, C[i])
9204 // end for
9205 // Recombine
9206 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
9207 Register in_out1, Register in_out2, Register in_out3,
9208 Register tmp1, Register tmp2, Register tmp3,
9209 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9210 Register tmp4, Register tmp5,
9211 Register n_tmp6) {
9212 Label L_processPartitions;
9213 Label L_processPartition;
9214 Label L_exit;
9215
9216 bind(L_processPartitions);
9217 cmpl(in_out1, 3 * size);
9218 jcc(Assembler::less, L_exit);
9219 xorl(tmp1, tmp1);
9220 xorl(tmp2, tmp2);
9221 movq(tmp3, in_out2);
9222 addq(tmp3, size);
9223
9224 bind(L_processPartition);
9225 crc32(in_out3, Address(in_out2, 0), 8);
9226 crc32(tmp1, Address(in_out2, size), 8);
9227 crc32(tmp2, Address(in_out2, size * 2), 8);
9228 addq(in_out2, 8);
9229 cmpq(in_out2, tmp3);
9230 jcc(Assembler::less, L_processPartition);
9231 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
9232 w_xtmp1, w_xtmp2, w_xtmp3,
9233 tmp4, tmp5,
9234 n_tmp6);
9235 addq(in_out2, 2 * size);
9236 subl(in_out1, 3 * size);
9237 jmp(L_processPartitions);
9238
9239 bind(L_exit);
9240 }
9241 #else
9242 void MacroAssembler::crc32c_ipl_alg4(Register in_out, uint32_t n,
9243 Register tmp1, Register tmp2, Register tmp3,
9244 XMMRegister xtmp1, XMMRegister xtmp2) {
9245 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
9246 if (n > 0) {
9247 addl(tmp3, n * 256 * 8);
9248 }
9249 // Q1 = TABLEExt[n][B & 0xFF];
9250 movl(tmp1, in_out);
9251 andl(tmp1, 0x000000FF);
9252 shll(tmp1, 3);
9253 addl(tmp1, tmp3);
9254 movq(xtmp1, Address(tmp1, 0));
9255
9256 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
9257 movl(tmp2, in_out);
9258 shrl(tmp2, 8);
9259 andl(tmp2, 0x000000FF);
9260 shll(tmp2, 3);
9261 addl(tmp2, tmp3);
9262 movq(xtmp2, Address(tmp2, 0));
9263
9264 psllq(xtmp2, 8);
9265 pxor(xtmp1, xtmp2);
9266
9267 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
9268 movl(tmp2, in_out);
9269 shrl(tmp2, 16);
9270 andl(tmp2, 0x000000FF);
9271 shll(tmp2, 3);
9272 addl(tmp2, tmp3);
9273 movq(xtmp2, Address(tmp2, 0));
9274
9275 psllq(xtmp2, 16);
9276 pxor(xtmp1, xtmp2);
9277
9278 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
9279 shrl(in_out, 24);
9280 andl(in_out, 0x000000FF);
9281 shll(in_out, 3);
9282 addl(in_out, tmp3);
9283 movq(xtmp2, Address(in_out, 0));
9284
9285 psllq(xtmp2, 24);
9286 pxor(xtmp1, xtmp2); // Result in CXMM
9287 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
9288 }
9289
9290 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
9291 Register in_out,
9292 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
9293 XMMRegister w_xtmp2,
9294 Register tmp1,
9295 Register n_tmp2, Register n_tmp3) {
9296 if (is_pclmulqdq_supported) {
9297 movdl(w_xtmp1, in_out);
9298
9299 movl(tmp1, const_or_pre_comp_const_index);
9300 movdl(w_xtmp2, tmp1);
9301 pclmulqdq(w_xtmp1, w_xtmp2, 0);
9302 // Keep result in XMM since GPR is 32 bit in length
9303 } else {
9304 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3, w_xtmp1, w_xtmp2);
9305 }
9306 }
9307
9308 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
9309 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9310 Register tmp1, Register tmp2,
9311 Register n_tmp3) {
9312 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
9313 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
9314
9315 psllq(w_xtmp1, 1);
9316 movdl(tmp1, w_xtmp1);
9317 psrlq(w_xtmp1, 32);
9318 movdl(in_out, w_xtmp1);
9319
9320 xorl(tmp2, tmp2);
9321 crc32(tmp2, tmp1, 4);
9322 xorl(in_out, tmp2);
9323
9324 psllq(w_xtmp2, 1);
9325 movdl(tmp1, w_xtmp2);
9326 psrlq(w_xtmp2, 32);
9327 movdl(in1, w_xtmp2);
9328
9329 xorl(tmp2, tmp2);
9330 crc32(tmp2, tmp1, 4);
9331 xorl(in1, tmp2);
9332 xorl(in_out, in1);
9333 xorl(in_out, in2);
9334 }
9335
9336 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
9337 Register in_out1, Register in_out2, Register in_out3,
9338 Register tmp1, Register tmp2, Register tmp3,
9339 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9340 Register tmp4, Register tmp5,
9341 Register n_tmp6) {
9342 Label L_processPartitions;
9343 Label L_processPartition;
9344 Label L_exit;
9345
9346 bind(L_processPartitions);
9347 cmpl(in_out1, 3 * size);
9348 jcc(Assembler::less, L_exit);
9349 xorl(tmp1, tmp1);
9350 xorl(tmp2, tmp2);
9351 movl(tmp3, in_out2);
9352 addl(tmp3, size);
9353
9354 bind(L_processPartition);
9355 crc32(in_out3, Address(in_out2, 0), 4);
9356 crc32(tmp1, Address(in_out2, size), 4);
9357 crc32(tmp2, Address(in_out2, size*2), 4);
9358 crc32(in_out3, Address(in_out2, 0+4), 4);
9359 crc32(tmp1, Address(in_out2, size+4), 4);
9360 crc32(tmp2, Address(in_out2, size*2+4), 4);
9361 addl(in_out2, 8);
9362 cmpl(in_out2, tmp3);
9363 jcc(Assembler::less, L_processPartition);
9364
9365 push(tmp3);
9366 push(in_out1);
9367 push(in_out2);
9368 tmp4 = tmp3;
9369 tmp5 = in_out1;
9370 n_tmp6 = in_out2;
9371
9372 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
9373 w_xtmp1, w_xtmp2, w_xtmp3,
9374 tmp4, tmp5,
9375 n_tmp6);
9376
9377 pop(in_out2);
9378 pop(in_out1);
9379 pop(tmp3);
9380
9381 addl(in_out2, 2 * size);
9382 subl(in_out1, 3 * size);
9383 jmp(L_processPartitions);
9384
9385 bind(L_exit);
9386 }
9387 #endif //LP64
9388
9389 #ifdef _LP64
9390 // Algorithm 2: Pipelined usage of the CRC32 instruction.
9391 // Input: A buffer I of L bytes.
9392 // Output: the CRC32C value of the buffer.
9393 // Notations:
9394 // Write L = 24N + r, with N = floor (L/24).
9395 // r = L mod 24 (0 <= r < 24).
9396 // Consider I as the concatenation of A|B|C|R, where A, B, C, each,
9397 // N quadwords, and R consists of r bytes.
9398 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1
9399 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1
9400 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1
9401 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1
9402 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
9403 Register tmp1, Register tmp2, Register tmp3,
9404 Register tmp4, Register tmp5, Register tmp6,
9405 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9406 bool is_pclmulqdq_supported) {
9407 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
9408 Label L_wordByWord;
9409 Label L_byteByByteProlog;
9410 Label L_byteByByte;
9411 Label L_exit;
9412
9413 if (is_pclmulqdq_supported ) {
9414 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
9415 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr+1);
9416
9417 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
9418 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
9419
9420 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
9421 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
9422 assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\"");
9423 } else {
9424 const_or_pre_comp_const_index[0] = 1;
9425 const_or_pre_comp_const_index[1] = 0;
9426
9427 const_or_pre_comp_const_index[2] = 3;
9428 const_or_pre_comp_const_index[3] = 2;
9429
9430 const_or_pre_comp_const_index[4] = 5;
9431 const_or_pre_comp_const_index[5] = 4;
9432 }
9433 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
9434 in2, in1, in_out,
9435 tmp1, tmp2, tmp3,
9436 w_xtmp1, w_xtmp2, w_xtmp3,
9437 tmp4, tmp5,
9438 tmp6);
9439 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
9440 in2, in1, in_out,
9441 tmp1, tmp2, tmp3,
9442 w_xtmp1, w_xtmp2, w_xtmp3,
9443 tmp4, tmp5,
9444 tmp6);
9445 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
9446 in2, in1, in_out,
9447 tmp1, tmp2, tmp3,
9448 w_xtmp1, w_xtmp2, w_xtmp3,
9449 tmp4, tmp5,
9450 tmp6);
9451 movl(tmp1, in2);
9452 andl(tmp1, 0x00000007);
9453 negl(tmp1);
9454 addl(tmp1, in2);
9455 addq(tmp1, in1);
9456
9457 BIND(L_wordByWord);
9458 cmpq(in1, tmp1);
9459 jcc(Assembler::greaterEqual, L_byteByByteProlog);
9460 crc32(in_out, Address(in1, 0), 4);
9461 addq(in1, 4);
9462 jmp(L_wordByWord);
9463
9464 BIND(L_byteByByteProlog);
9465 andl(in2, 0x00000007);
9466 movl(tmp2, 1);
9467
9468 BIND(L_byteByByte);
9469 cmpl(tmp2, in2);
9470 jccb(Assembler::greater, L_exit);
9471 crc32(in_out, Address(in1, 0), 1);
9472 incq(in1);
9473 incl(tmp2);
9474 jmp(L_byteByByte);
9475
9476 BIND(L_exit);
9477 }
9478 #else
9479 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
9480 Register tmp1, Register tmp2, Register tmp3,
9481 Register tmp4, Register tmp5, Register tmp6,
9482 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9483 bool is_pclmulqdq_supported) {
9484 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
9485 Label L_wordByWord;
9486 Label L_byteByByteProlog;
9487 Label L_byteByByte;
9488 Label L_exit;
9489
9490 if (is_pclmulqdq_supported) {
9491 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
9492 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 1);
9493
9494 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
9495 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
9496
9497 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
9498 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
9499 } else {
9500 const_or_pre_comp_const_index[0] = 1;
9501 const_or_pre_comp_const_index[1] = 0;
9502
9503 const_or_pre_comp_const_index[2] = 3;
9504 const_or_pre_comp_const_index[3] = 2;
9505
9506 const_or_pre_comp_const_index[4] = 5;
9507 const_or_pre_comp_const_index[5] = 4;
9508 }
9509 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
9510 in2, in1, in_out,
9511 tmp1, tmp2, tmp3,
9512 w_xtmp1, w_xtmp2, w_xtmp3,
9513 tmp4, tmp5,
9514 tmp6);
9515 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
9516 in2, in1, in_out,
9517 tmp1, tmp2, tmp3,
9518 w_xtmp1, w_xtmp2, w_xtmp3,
9519 tmp4, tmp5,
9520 tmp6);
9521 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
9522 in2, in1, in_out,
9523 tmp1, tmp2, tmp3,
9524 w_xtmp1, w_xtmp2, w_xtmp3,
9525 tmp4, tmp5,
9526 tmp6);
9527 movl(tmp1, in2);
9528 andl(tmp1, 0x00000007);
9529 negl(tmp1);
9530 addl(tmp1, in2);
9531 addl(tmp1, in1);
9532
9533 BIND(L_wordByWord);
9534 cmpl(in1, tmp1);
9535 jcc(Assembler::greaterEqual, L_byteByByteProlog);
9536 crc32(in_out, Address(in1,0), 4);
9537 addl(in1, 4);
9538 jmp(L_wordByWord);
9539
9540 BIND(L_byteByByteProlog);
9541 andl(in2, 0x00000007);
9542 movl(tmp2, 1);
9543
9544 BIND(L_byteByByte);
9545 cmpl(tmp2, in2);
9546 jccb(Assembler::greater, L_exit);
9547 movb(tmp1, Address(in1, 0));
9548 crc32(in_out, tmp1, 1);
9549 incl(in1);
9550 incl(tmp2);
9551 jmp(L_byteByByte);
9552
9553 BIND(L_exit);
9554 }
9555 #endif // LP64
9556 #undef BIND
9557 #undef BLOCK_COMMENT
9558
9559 // Compress char[] array to byte[].
9560 // ..\jdk\src\java.base\share\classes\java\lang\StringUTF16.java
9561 // @HotSpotIntrinsicCandidate
9562 // private static int compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) {
9563 // for (int i = 0; i < len; i++) {
9564 // int c = src[srcOff++];
9565 // if (c >>> 8 != 0) {
9566 // return 0;
9567 // }
9568 // dst[dstOff++] = (byte)c;
9569 // }
9570 // return len;
9571 // }
9572 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
9573 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
9574 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
9575 Register tmp5, Register result) {
9576 Label copy_chars_loop, return_length, return_zero, done;
9577
9578 // rsi: src
9579 // rdi: dst
9580 // rdx: len
9581 // rcx: tmp5
9582 // rax: result
9583
9584 // rsi holds start addr of source char[] to be compressed
9585 // rdi holds start addr of destination byte[]
9586 // rdx holds length
9587
9588 assert(len != result, "");
9589
9590 // save length for return
9591 push(len);
9592
9593 if ((UseAVX > 2) && // AVX512
9594 VM_Version::supports_avx512vlbw() &&
9595 VM_Version::supports_bmi2()) {
9596
9597 set_vector_masking(); // opening of the stub context for programming mask registers
9598
9599 Label copy_32_loop, copy_loop_tail, restore_k1_return_zero, below_threshold;
9600
9601 // alignment
9602 Label post_alignment;
9603
9604 // if length of the string is less than 16, handle it in an old fashioned way
9605 testl(len, -32);
9606 jcc(Assembler::zero, below_threshold);
9607
9608 // First check whether a character is compressable ( <= 0xFF).
9609 // Create mask to test for Unicode chars inside zmm vector
9610 movl(result, 0x00FF);
9611 evpbroadcastw(tmp2Reg, result, Assembler::AVX_512bit);
9612
9613 // Save k1
9614 kmovql(k3, k1);
9615
9616 testl(len, -64);
9617 jcc(Assembler::zero, post_alignment);
9618
9619 movl(tmp5, dst);
9620 andl(tmp5, (32 - 1));
9621 negl(tmp5);
9622 andl(tmp5, (32 - 1));
9623
9624 // bail out when there is nothing to be done
9625 testl(tmp5, 0xFFFFFFFF);
9626 jcc(Assembler::zero, post_alignment);
9627
9628 // ~(~0 << len), where len is the # of remaining elements to process
9629 movl(result, 0xFFFFFFFF);
9630 shlxl(result, result, tmp5);
9631 notl(result);
9632 kmovdl(k1, result);
9633
9634 evmovdquw(tmp1Reg, k1, Address(src, 0), Assembler::AVX_512bit);
9635 evpcmpuw(k2, k1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
9636 ktestd(k2, k1);
9637 jcc(Assembler::carryClear, restore_k1_return_zero);
9638
9639 evpmovwb(Address(dst, 0), k1, tmp1Reg, Assembler::AVX_512bit);
9640
9641 addptr(src, tmp5);
9642 addptr(src, tmp5);
9643 addptr(dst, tmp5);
9644 subl(len, tmp5);
9645
9646 bind(post_alignment);
9647 // end of alignment
9648
9649 movl(tmp5, len);
9650 andl(tmp5, (32 - 1)); // tail count (in chars)
9651 andl(len, ~(32 - 1)); // vector count (in chars)
9652 jcc(Assembler::zero, copy_loop_tail);
9653
9654 lea(src, Address(src, len, Address::times_2));
9655 lea(dst, Address(dst, len, Address::times_1));
9656 negptr(len);
9657
9658 bind(copy_32_loop);
9659 evmovdquw(tmp1Reg, Address(src, len, Address::times_2), Assembler::AVX_512bit);
9660 evpcmpuw(k2, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
9661 kortestdl(k2, k2);
9662 jcc(Assembler::carryClear, restore_k1_return_zero);
9663
9664 // All elements in current processed chunk are valid candidates for
9665 // compression. Write a truncated byte elements to the memory.
9666 evpmovwb(Address(dst, len, Address::times_1), tmp1Reg, Assembler::AVX_512bit);
9667 addptr(len, 32);
9668 jcc(Assembler::notZero, copy_32_loop);
9669
9670 bind(copy_loop_tail);
9671 // bail out when there is nothing to be done
9672 testl(tmp5, 0xFFFFFFFF);
9673 // Restore k1
9674 kmovql(k1, k3);
9675 jcc(Assembler::zero, return_length);
9676
9677 movl(len, tmp5);
9678
9679 // ~(~0 << len), where len is the # of remaining elements to process
9680 movl(result, 0xFFFFFFFF);
9681 shlxl(result, result, len);
9682 notl(result);
9683
9684 kmovdl(k1, result);
9685
9686 evmovdquw(tmp1Reg, k1, Address(src, 0), Assembler::AVX_512bit);
9687 evpcmpuw(k2, k1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
9688 ktestd(k2, k1);
9689 jcc(Assembler::carryClear, restore_k1_return_zero);
9690
9691 evpmovwb(Address(dst, 0), k1, tmp1Reg, Assembler::AVX_512bit);
9692 // Restore k1
9693 kmovql(k1, k3);
9694 jmp(return_length);
9695
9696 bind(restore_k1_return_zero);
9697 // Restore k1
9698 kmovql(k1, k3);
9699 jmp(return_zero);
9700
9701 clear_vector_masking(); // closing of the stub context for programming mask registers
9702
9703 bind(below_threshold);
9704 }
9705
9706 if (UseSSE42Intrinsics) {
9707 Label copy_32_loop, copy_16, copy_tail;
9708
9709 movl(result, len);
9710
9711 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vectors
9712
9713 // vectored compression
9714 andl(len, 0xfffffff0); // vector count (in chars)
9715 andl(result, 0x0000000f); // tail count (in chars)
9716 testl(len, len);
9717 jcc(Assembler::zero, copy_16);
9718
9719 // compress 16 chars per iter
9720 movdl(tmp1Reg, tmp5);
9721 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
9722 pxor(tmp4Reg, tmp4Reg);
9723
9724 lea(src, Address(src, len, Address::times_2));
9725 lea(dst, Address(dst, len, Address::times_1));
9726 negptr(len);
9727
9728 bind(copy_32_loop);
9729 movdqu(tmp2Reg, Address(src, len, Address::times_2)); // load 1st 8 characters
9730 por(tmp4Reg, tmp2Reg);
9731 movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters
9732 por(tmp4Reg, tmp3Reg);
9733 ptest(tmp4Reg, tmp1Reg); // check for Unicode chars in next vector
9734 jcc(Assembler::notZero, return_zero);
9735 packuswb(tmp2Reg, tmp3Reg); // only ASCII chars; compress each to 1 byte
9736 movdqu(Address(dst, len, Address::times_1), tmp2Reg);
9737 addptr(len, 16);
9738 jcc(Assembler::notZero, copy_32_loop);
9739
9740 // compress next vector of 8 chars (if any)
9741 bind(copy_16);
9742 movl(len, result);
9743 andl(len, 0xfffffff8); // vector count (in chars)
9744 andl(result, 0x00000007); // tail count (in chars)
9745 testl(len, len);
9746 jccb(Assembler::zero, copy_tail);
9747
9748 movdl(tmp1Reg, tmp5);
9749 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
9750 pxor(tmp3Reg, tmp3Reg);
9751
9752 movdqu(tmp2Reg, Address(src, 0));
9753 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
9754 jccb(Assembler::notZero, return_zero);
9755 packuswb(tmp2Reg, tmp3Reg); // only LATIN1 chars; compress each to 1 byte
9756 movq(Address(dst, 0), tmp2Reg);
9757 addptr(src, 16);
9758 addptr(dst, 8);
9759
9760 bind(copy_tail);
9761 movl(len, result);
9762 }
9763 // compress 1 char per iter
9764 testl(len, len);
9765 jccb(Assembler::zero, return_length);
9766 lea(src, Address(src, len, Address::times_2));
9767 lea(dst, Address(dst, len, Address::times_1));
9768 negptr(len);
9769
9770 bind(copy_chars_loop);
9771 load_unsigned_short(result, Address(src, len, Address::times_2));
9772 testl(result, 0xff00); // check if Unicode char
9773 jccb(Assembler::notZero, return_zero);
9774 movb(Address(dst, len, Address::times_1), result); // ASCII char; compress to 1 byte
9775 increment(len);
9776 jcc(Assembler::notZero, copy_chars_loop);
9777
9778 // if compression succeeded, return length
9779 bind(return_length);
9780 pop(result);
9781 jmpb(done);
9782
9783 // if compression failed, return 0
9784 bind(return_zero);
9785 xorl(result, result);
9786 addptr(rsp, wordSize);
9787
9788 bind(done);
9789 }
9790
9791 // Inflate byte[] array to char[].
9792 // ..\jdk\src\java.base\share\classes\java\lang\StringLatin1.java
9793 // @HotSpotIntrinsicCandidate
9794 // private static void inflate(byte[] src, int srcOff, char[] dst, int dstOff, int len) {
9795 // for (int i = 0; i < len; i++) {
9796 // dst[dstOff++] = (char)(src[srcOff++] & 0xff);
9797 // }
9798 // }
9799 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
9800 XMMRegister tmp1, Register tmp2) {
9801 Label copy_chars_loop, done, below_threshold;
9802 // rsi: src
9803 // rdi: dst
9804 // rdx: len
9805 // rcx: tmp2
9806
9807 // rsi holds start addr of source byte[] to be inflated
9808 // rdi holds start addr of destination char[]
9809 // rdx holds length
9810 assert_different_registers(src, dst, len, tmp2);
9811
9812 if ((UseAVX > 2) && // AVX512
9813 VM_Version::supports_avx512vlbw() &&
9814 VM_Version::supports_bmi2()) {
9815
9816 set_vector_masking(); // opening of the stub context for programming mask registers
9817
9818 Label copy_32_loop, copy_tail;
9819 Register tmp3_aliased = len;
9820
9821 // if length of the string is less than 16, handle it in an old fashioned way
9822 testl(len, -16);
9823 jcc(Assembler::zero, below_threshold);
9824
9825 // In order to use only one arithmetic operation for the main loop we use
9826 // this pre-calculation
9827 movl(tmp2, len);
9828 andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop
9829 andl(len, -32); // vector count
9830 jccb(Assembler::zero, copy_tail);
9831
9832 lea(src, Address(src, len, Address::times_1));
9833 lea(dst, Address(dst, len, Address::times_2));
9834 negptr(len);
9835
9836
9837 // inflate 32 chars per iter
9838 bind(copy_32_loop);
9839 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_512bit);
9840 evmovdquw(Address(dst, len, Address::times_2), tmp1, Assembler::AVX_512bit);
9841 addptr(len, 32);
9842 jcc(Assembler::notZero, copy_32_loop);
9843
9844 bind(copy_tail);
9845 // bail out when there is nothing to be done
9846 testl(tmp2, -1); // we don't destroy the contents of tmp2 here
9847 jcc(Assembler::zero, done);
9848
9849 // Save k1
9850 kmovql(k2, k1);
9851
9852 // ~(~0 << length), where length is the # of remaining elements to process
9853 movl(tmp3_aliased, -1);
9854 shlxl(tmp3_aliased, tmp3_aliased, tmp2);
9855 notl(tmp3_aliased);
9856 kmovdl(k1, tmp3_aliased);
9857 evpmovzxbw(tmp1, k1, Address(src, 0), Assembler::AVX_512bit);
9858 evmovdquw(Address(dst, 0), k1, tmp1, Assembler::AVX_512bit);
9859
9860 // Restore k1
9861 kmovql(k1, k2);
9862 jmp(done);
9863
9864 clear_vector_masking(); // closing of the stub context for programming mask registers
9865 }
9866 if (UseSSE42Intrinsics) {
9867 Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail;
9868
9869 movl(tmp2, len);
9870
9871 if (UseAVX > 1) {
9872 andl(tmp2, (16 - 1));
9873 andl(len, -16);
9874 jccb(Assembler::zero, copy_new_tail);
9875 } else {
9876 andl(tmp2, 0x00000007); // tail count (in chars)
9877 andl(len, 0xfffffff8); // vector count (in chars)
9878 jccb(Assembler::zero, copy_tail);
9879 }
9880
9881 // vectored inflation
9882 lea(src, Address(src, len, Address::times_1));
9883 lea(dst, Address(dst, len, Address::times_2));
9884 negptr(len);
9885
9886 if (UseAVX > 1) {
9887 bind(copy_16_loop);
9888 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_256bit);
9889 vmovdqu(Address(dst, len, Address::times_2), tmp1);
9890 addptr(len, 16);
9891 jcc(Assembler::notZero, copy_16_loop);
9892
9893 bind(below_threshold);
9894 bind(copy_new_tail);
9895 if ((UseAVX > 2) &&
9896 VM_Version::supports_avx512vlbw() &&
9897 VM_Version::supports_bmi2()) {
9898 movl(tmp2, len);
9899 } else {
9900 movl(len, tmp2);
9901 }
9902 andl(tmp2, 0x00000007);
9903 andl(len, 0xFFFFFFF8);
9904 jccb(Assembler::zero, copy_tail);
9905
9906 pmovzxbw(tmp1, Address(src, 0));
9907 movdqu(Address(dst, 0), tmp1);
9908 addptr(src, 8);
9909 addptr(dst, 2 * 8);
9910
9911 jmp(copy_tail, true);
9912 }
9913
9914 // inflate 8 chars per iter
9915 bind(copy_8_loop);
9916 pmovzxbw(tmp1, Address(src, len, Address::times_1)); // unpack to 8 words
9917 movdqu(Address(dst, len, Address::times_2), tmp1);
9918 addptr(len, 8);
9919 jcc(Assembler::notZero, copy_8_loop);
9920
9921 bind(copy_tail);
9922 movl(len, tmp2);
9923
9924 cmpl(len, 4);
9925 jccb(Assembler::less, copy_bytes);
9926
9927 movdl(tmp1, Address(src, 0)); // load 4 byte chars
9928 pmovzxbw(tmp1, tmp1);
9929 movq(Address(dst, 0), tmp1);
9930 subptr(len, 4);
9931 addptr(src, 4);
9932 addptr(dst, 8);
9933
9934 bind(copy_bytes);
9935 } else {
9936 bind(below_threshold);
9937 }
9938
9939 testl(len, len);
9940 jccb(Assembler::zero, done);
9941 lea(src, Address(src, len, Address::times_1));
9942 lea(dst, Address(dst, len, Address::times_2));
9943 negptr(len);
9944
9945 // inflate 1 char per iter
9946 bind(copy_chars_loop);
9947 load_unsigned_byte(tmp2, Address(src, len, Address::times_1)); // load byte char
9948 movw(Address(dst, len, Address::times_2), tmp2); // inflate byte char to word
9949 increment(len);
9950 jcc(Assembler::notZero, copy_chars_loop);
9951
9952 bind(done);
9953 }
9954
9955 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
9956 switch (cond) {
9957 // Note some conditions are synonyms for others
9958 case Assembler::zero: return Assembler::notZero;
9959 case Assembler::notZero: return Assembler::zero;
9960 case Assembler::less: return Assembler::greaterEqual;
9961 case Assembler::lessEqual: return Assembler::greater;
9962 case Assembler::greater: return Assembler::lessEqual;
9963 case Assembler::greaterEqual: return Assembler::less;
9964 case Assembler::below: return Assembler::aboveEqual;
9965 case Assembler::belowEqual: return Assembler::above;
9966 case Assembler::above: return Assembler::belowEqual;
9967 case Assembler::aboveEqual: return Assembler::below;
9968 case Assembler::overflow: return Assembler::noOverflow;
9969 case Assembler::noOverflow: return Assembler::overflow;
9970 case Assembler::negative: return Assembler::positive;
9971 case Assembler::positive: return Assembler::negative;
9972 case Assembler::parity: return Assembler::noParity;
9973 case Assembler::noParity: return Assembler::parity;
9974 }
9975 ShouldNotReachHere(); return Assembler::overflow;
9976 }
9977
9978 SkipIfEqual::SkipIfEqual(
9979 MacroAssembler* masm, const bool* flag_addr, bool value) {
9980 _masm = masm;
9981 _masm->cmp8(ExternalAddress((address)flag_addr), value);
9982 _masm->jcc(Assembler::equal, _label);
9983 }
9984
9985 SkipIfEqual::~SkipIfEqual() {
9986 _masm->bind(_label);
9987 }
9988
9989 // 32-bit Windows has its own fast-path implementation
9990 // of get_thread
9991 #if !defined(WIN32) || defined(_LP64)
9992
9993 // This is simply a call to Thread::current()
9994 void MacroAssembler::get_thread(Register thread) {
9995 if (thread != rax) {
9996 push(rax);
9997 }
9998 LP64_ONLY(push(rdi);)
9999 LP64_ONLY(push(rsi);)
10000 push(rdx);
10001 push(rcx);
10002 #ifdef _LP64
10003 push(r8);
10004 push(r9);
10005 push(r10);
10006 push(r11);
10007 #endif
10008
10009 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0);
10010
10011 #ifdef _LP64
10012 pop(r11);
10013 pop(r10);
10014 pop(r9);
10015 pop(r8);
10016 #endif
10017 pop(rcx);
10018 pop(rdx);
10019 LP64_ONLY(pop(rsi);)
10020 LP64_ONLY(pop(rdi);)
10021 if (thread != rax) {
10022 mov(thread, rax);
10023 pop(rax);
10024 }
10025 }
10026
10027 #endif