src/hotspot/cpu/x86/x86_32.ad

*** 4099,4151 ****
--- 4099,4201 ----
    match(RegF);
    format %{ %}
    interface(REG_INTER);
  %}
  
+ // Float register operands
+ operand vlRegF() %{
+    constraint(ALLOC_IN_RC(float_reg_vl));
+    match(RegF);
+ 
+    format %{ %}
+    interface(REG_INTER);
+ %}
+ 
  // XMM Double register operands
  operand regD() %{
    predicate( UseSSE>=2 );
    constraint(ALLOC_IN_RC(double_reg_legacy));
    match(RegD);
    format %{ %}
    interface(REG_INTER);
  %}
  
+ // Double register operands
+ operand vlRegD() %{
+    constraint(ALLOC_IN_RC(double_reg_vl));
+    match(RegD);
+ 
+    format %{ %}
+    interface(REG_INTER);
+ %}
+ 
  // Vectors : note, we use legacy registers to avoid extra (unneeded in 32-bit VM)
  // runtime code generation via reg_class_dynamic.
  operand vecS() %{
    constraint(ALLOC_IN_RC(vectors_reg_legacy));
    match(VecS);
  
    format %{ %}
    interface(REG_INTER);
  %}
  
+ operand legVecS() %{
+   constraint(ALLOC_IN_RC(vectors_reg_legacy));
+   match(VecS);
+ 
+   format %{ %}
+   interface(REG_INTER);
+ %}
+ 
  operand vecD() %{
    constraint(ALLOC_IN_RC(vectord_reg_legacy));
    match(VecD);
  
    format %{ %}
    interface(REG_INTER);
  %}
  
+ operand legVecD() %{
+   constraint(ALLOC_IN_RC(vectord_reg_legacy));
+   match(VecD);
+ 
+   format %{ %}
+   interface(REG_INTER);
+ %}
+ 
  operand vecX() %{
    constraint(ALLOC_IN_RC(vectorx_reg_legacy));
    match(VecX);
  
    format %{ %}
    interface(REG_INTER);
  %}
  
+ operand legVecX() %{
+   constraint(ALLOC_IN_RC(vectorx_reg_legacy));
+   match(VecX);
+ 
+   format %{ %}
+   interface(REG_INTER);
+ %}
+ 
  operand vecY() %{
    constraint(ALLOC_IN_RC(vectory_reg_legacy));
    match(VecY);
  
    format %{ %}
    interface(REG_INTER);
  %}
  
+ operand legVecY() %{
+   constraint(ALLOC_IN_RC(vectory_reg_legacy));
+   match(VecY);
+ 
+   format %{ %}
+   interface(REG_INTER);
+ %}
+ 
  //----------Memory Operands----------------------------------------------------
  // Direct Memory Operand
  operand direct(immP addr) %{
    match(addr);
  
*** 6513,6522 ****
--- 6563,6592 ----
      __ movdbl($mem$$Address, $src$$XMMRegister);
    %}
    ins_pipe( pipe_slow );
  %}
  
+ // Load Double
+ instruct MoveD2VL(vlRegD dst, regD src) %{
+   match(Set dst src);
+   format %{ "movsd $dst,$src\t! load double (8 bytes)" %}
+   ins_encode %{
+     __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
+   %}
+   ins_pipe( fpu_reg_reg );
+ %}
+ 
+ // Load Double
+ instruct MoveVL2D(regD dst, vlRegD src) %{
+   match(Set dst src);
+   format %{ "movsd $dst,$src\t! load double (8 bytes)" %}
+   ins_encode %{
+     __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
+   %}
+   ins_pipe( fpu_reg_reg );
+ %}
+ 
  // Store XMM register to memory (single-precision floating point)
  // MOVSS instruction
  instruct storeF(memory mem, regF src) %{
    predicate(UseSSE>=1);
    match(Set mem (StoreF mem src));
*** 6526,6535 ****
--- 6596,6625 ----
      __ movflt($mem$$Address, $src$$XMMRegister);
    %}
    ins_pipe( pipe_slow );
  %}
  
+ // Load Float
+ instruct MoveF2VL(vlRegF dst, regF src) %{
+   match(Set dst src);
+   format %{ "movss $dst,$src\t! load float (4 bytes)" %}
+   ins_encode %{
+     __ movflt($dst$$XMMRegister, $src$$XMMRegister);
+   %}
+   ins_pipe( fpu_reg_reg );
+ %}
+ 
+ // Load Float
+ instruct MoveVL2F(regF dst, vlRegF src) %{
+   match(Set dst src);
+   format %{ "movss $dst,$src\t! load float (4 bytes)" %}
+   ins_encode %{
+     __ movflt($dst$$XMMRegister, $src$$XMMRegister);
+   %}
+   ins_pipe( fpu_reg_reg );
+ %}
+ 
  // Store Float
  instruct storeFPR( memory mem, regFPR1 src) %{
    predicate(UseSSE==0);
    match(Set mem (StoreF mem src));