1 //
2 // Copyright (c) 2011, 2014, Oracle and/or its affiliates. All rights reserved.
3 // Copyright 2012, 2014 SAP AG. All rights reserved.
4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 //
6 // This code is free software; you can redistribute it and/or modify it
7 // under the terms of the GNU General Public License version 2 only, as
8 // published by the Free Software Foundation.
9 //
10 // This code is distributed in the hope that it will be useful, but WITHOUT
11 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 // version 2 for more details (a copy is included in the LICENSE file that
14 // accompanied this code).
15 //
16 // You should have received a copy of the GNU General Public License version
17 // 2 along with this work; if not, write to the Free Software Foundation,
18 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 //
20 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 // or visit www.oracle.com if you need additional information or have any
22 // questions.
23 //
24 //
25
26 //
27 // PPC64 Architecture Description File
28 //
29
30 //----------REGISTER DEFINITION BLOCK------------------------------------------
31 // This information is used by the matcher and the register allocator to
32 // describe individual registers and classes of registers within the target
33 // architecture.
34 register %{
35 //----------Architecture Description Register Definitions----------------------
36 // General Registers
37 // "reg_def" name (register save type, C convention save type,
38 // ideal register type, encoding);
39 //
40 // Register Save Types:
41 //
42 // NS = No-Save: The register allocator assumes that these registers
43 // can be used without saving upon entry to the method, &
44 // that they do not need to be saved at call sites.
45 //
46 // SOC = Save-On-Call: The register allocator assumes that these registers
47 // can be used without saving upon entry to the method,
48 // but that they must be saved at call sites.
49 // These are called "volatiles" on ppc.
50 //
51 // SOE = Save-On-Entry: The register allocator assumes that these registers
52 // must be saved before using them upon entry to the
53 // method, but they do not need to be saved at call
54 // sites.
55 // These are called "nonvolatiles" on ppc.
56 //
57 // AS = Always-Save: The register allocator assumes that these registers
58 // must be saved before using them upon entry to the
59 // method, & that they must be saved at call sites.
60 //
61 // Ideal Register Type is used to determine how to save & restore a
62 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
63 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
64 //
65 // The encoding number is the actual bit-pattern placed into the opcodes.
66 //
67 // PPC64 register definitions, based on the 64-bit PowerPC ELF ABI
68 // Supplement Version 1.7 as of 2003-10-29.
69 //
70 // For each 64-bit register we must define two registers: the register
71 // itself, e.g. R3, and a corresponding virtual other (32-bit-)'half',
72 // e.g. R3_H, which is needed by the allocator, but is not used
73 // for stores, loads, etc.
74
75 // ----------------------------
76 // Integer/Long Registers
77 // ----------------------------
78
79 // PPC64 has 32 64-bit integer registers.
80
81 // types: v = volatile, nv = non-volatile, s = system
82 reg_def R0 ( SOC, SOC, Op_RegI, 0, R0->as_VMReg() ); // v used in prologs
83 reg_def R0_H ( SOC, SOC, Op_RegI, 99, R0->as_VMReg()->next() );
84 reg_def R1 ( NS, NS, Op_RegI, 1, R1->as_VMReg() ); // s SP
85 reg_def R1_H ( NS, NS, Op_RegI, 99, R1->as_VMReg()->next() );
86 reg_def R2 ( SOC, SOC, Op_RegI, 2, R2->as_VMReg() ); // v TOC
87 reg_def R2_H ( SOC, SOC, Op_RegI, 99, R2->as_VMReg()->next() );
88 reg_def R3 ( SOC, SOC, Op_RegI, 3, R3->as_VMReg() ); // v iarg1 & iret
89 reg_def R3_H ( SOC, SOC, Op_RegI, 99, R3->as_VMReg()->next() );
90 reg_def R4 ( SOC, SOC, Op_RegI, 4, R4->as_VMReg() ); // iarg2
91 reg_def R4_H ( SOC, SOC, Op_RegI, 99, R4->as_VMReg()->next() );
92 reg_def R5 ( SOC, SOC, Op_RegI, 5, R5->as_VMReg() ); // v iarg3
93 reg_def R5_H ( SOC, SOC, Op_RegI, 99, R5->as_VMReg()->next() );
94 reg_def R6 ( SOC, SOC, Op_RegI, 6, R6->as_VMReg() ); // v iarg4
95 reg_def R6_H ( SOC, SOC, Op_RegI, 99, R6->as_VMReg()->next() );
96 reg_def R7 ( SOC, SOC, Op_RegI, 7, R7->as_VMReg() ); // v iarg5
97 reg_def R7_H ( SOC, SOC, Op_RegI, 99, R7->as_VMReg()->next() );
98 reg_def R8 ( SOC, SOC, Op_RegI, 8, R8->as_VMReg() ); // v iarg6
99 reg_def R8_H ( SOC, SOC, Op_RegI, 99, R8->as_VMReg()->next() );
100 reg_def R9 ( SOC, SOC, Op_RegI, 9, R9->as_VMReg() ); // v iarg7
101 reg_def R9_H ( SOC, SOC, Op_RegI, 99, R9->as_VMReg()->next() );
102 reg_def R10 ( SOC, SOC, Op_RegI, 10, R10->as_VMReg() ); // v iarg8
103 reg_def R10_H( SOC, SOC, Op_RegI, 99, R10->as_VMReg()->next());
104 reg_def R11 ( SOC, SOC, Op_RegI, 11, R11->as_VMReg() ); // v ENV / scratch
105 reg_def R11_H( SOC, SOC, Op_RegI, 99, R11->as_VMReg()->next());
106 reg_def R12 ( SOC, SOC, Op_RegI, 12, R12->as_VMReg() ); // v scratch
107 reg_def R12_H( SOC, SOC, Op_RegI, 99, R12->as_VMReg()->next());
108 reg_def R13 ( NS, NS, Op_RegI, 13, R13->as_VMReg() ); // s system thread id
109 reg_def R13_H( NS, NS, Op_RegI, 99, R13->as_VMReg()->next());
110 reg_def R14 ( SOC, SOE, Op_RegI, 14, R14->as_VMReg() ); // nv
111 reg_def R14_H( SOC, SOE, Op_RegI, 99, R14->as_VMReg()->next());
112 reg_def R15 ( SOC, SOE, Op_RegI, 15, R15->as_VMReg() ); // nv
113 reg_def R15_H( SOC, SOE, Op_RegI, 99, R15->as_VMReg()->next());
114 reg_def R16 ( SOC, SOE, Op_RegI, 16, R16->as_VMReg() ); // nv
115 reg_def R16_H( SOC, SOE, Op_RegI, 99, R16->as_VMReg()->next());
116 reg_def R17 ( SOC, SOE, Op_RegI, 17, R17->as_VMReg() ); // nv
117 reg_def R17_H( SOC, SOE, Op_RegI, 99, R17->as_VMReg()->next());
118 reg_def R18 ( SOC, SOE, Op_RegI, 18, R18->as_VMReg() ); // nv
119 reg_def R18_H( SOC, SOE, Op_RegI, 99, R18->as_VMReg()->next());
120 reg_def R19 ( SOC, SOE, Op_RegI, 19, R19->as_VMReg() ); // nv
121 reg_def R19_H( SOC, SOE, Op_RegI, 99, R19->as_VMReg()->next());
122 reg_def R20 ( SOC, SOE, Op_RegI, 20, R20->as_VMReg() ); // nv
123 reg_def R20_H( SOC, SOE, Op_RegI, 99, R20->as_VMReg()->next());
124 reg_def R21 ( SOC, SOE, Op_RegI, 21, R21->as_VMReg() ); // nv
125 reg_def R21_H( SOC, SOE, Op_RegI, 99, R21->as_VMReg()->next());
126 reg_def R22 ( SOC, SOE, Op_RegI, 22, R22->as_VMReg() ); // nv
127 reg_def R22_H( SOC, SOE, Op_RegI, 99, R22->as_VMReg()->next());
128 reg_def R23 ( SOC, SOE, Op_RegI, 23, R23->as_VMReg() ); // nv
129 reg_def R23_H( SOC, SOE, Op_RegI, 99, R23->as_VMReg()->next());
130 reg_def R24 ( SOC, SOE, Op_RegI, 24, R24->as_VMReg() ); // nv
131 reg_def R24_H( SOC, SOE, Op_RegI, 99, R24->as_VMReg()->next());
132 reg_def R25 ( SOC, SOE, Op_RegI, 25, R25->as_VMReg() ); // nv
133 reg_def R25_H( SOC, SOE, Op_RegI, 99, R25->as_VMReg()->next());
134 reg_def R26 ( SOC, SOE, Op_RegI, 26, R26->as_VMReg() ); // nv
135 reg_def R26_H( SOC, SOE, Op_RegI, 99, R26->as_VMReg()->next());
136 reg_def R27 ( SOC, SOE, Op_RegI, 27, R27->as_VMReg() ); // nv
137 reg_def R27_H( SOC, SOE, Op_RegI, 99, R27->as_VMReg()->next());
138 reg_def R28 ( SOC, SOE, Op_RegI, 28, R28->as_VMReg() ); // nv
139 reg_def R28_H( SOC, SOE, Op_RegI, 99, R28->as_VMReg()->next());
140 reg_def R29 ( SOC, SOE, Op_RegI, 29, R29->as_VMReg() ); // nv
141 reg_def R29_H( SOC, SOE, Op_RegI, 99, R29->as_VMReg()->next());
142 reg_def R30 ( SOC, SOE, Op_RegI, 30, R30->as_VMReg() ); // nv
143 reg_def R30_H( SOC, SOE, Op_RegI, 99, R30->as_VMReg()->next());
144 reg_def R31 ( SOC, SOE, Op_RegI, 31, R31->as_VMReg() ); // nv
145 reg_def R31_H( SOC, SOE, Op_RegI, 99, R31->as_VMReg()->next());
146
147
148 // ----------------------------
149 // Float/Double Registers
150 // ----------------------------
151
152 // Double Registers
153 // The rules of ADL require that double registers be defined in pairs.
154 // Each pair must be two 32-bit values, but not necessarily a pair of
155 // single float registers. In each pair, ADLC-assigned register numbers
156 // must be adjacent, with the lower number even. Finally, when the
157 // CPU stores such a register pair to memory, the word associated with
158 // the lower ADLC-assigned number must be stored to the lower address.
159
160 // PPC64 has 32 64-bit floating-point registers. Each can store a single
161 // or double precision floating-point value.
162
163 // types: v = volatile, nv = non-volatile, s = system
164 reg_def F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg() ); // v scratch
165 reg_def F0_H ( SOC, SOC, Op_RegF, 99, F0->as_VMReg()->next() );
166 reg_def F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg() ); // v farg1 & fret
167 reg_def F1_H ( SOC, SOC, Op_RegF, 99, F1->as_VMReg()->next() );
168 reg_def F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg() ); // v farg2
169 reg_def F2_H ( SOC, SOC, Op_RegF, 99, F2->as_VMReg()->next() );
170 reg_def F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg() ); // v farg3
171 reg_def F3_H ( SOC, SOC, Op_RegF, 99, F3->as_VMReg()->next() );
172 reg_def F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg() ); // v farg4
173 reg_def F4_H ( SOC, SOC, Op_RegF, 99, F4->as_VMReg()->next() );
174 reg_def F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg() ); // v farg5
175 reg_def F5_H ( SOC, SOC, Op_RegF, 99, F5->as_VMReg()->next() );
176 reg_def F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg() ); // v farg6
177 reg_def F6_H ( SOC, SOC, Op_RegF, 99, F6->as_VMReg()->next() );
178 reg_def F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg() ); // v farg7
179 reg_def F7_H ( SOC, SOC, Op_RegF, 99, F7->as_VMReg()->next() );
180 reg_def F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg() ); // v farg8
181 reg_def F8_H ( SOC, SOC, Op_RegF, 99, F8->as_VMReg()->next() );
182 reg_def F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg() ); // v farg9
183 reg_def F9_H ( SOC, SOC, Op_RegF, 99, F9->as_VMReg()->next() );
184 reg_def F10 ( SOC, SOC, Op_RegF, 10, F10->as_VMReg() ); // v farg10
185 reg_def F10_H( SOC, SOC, Op_RegF, 99, F10->as_VMReg()->next());
186 reg_def F11 ( SOC, SOC, Op_RegF, 11, F11->as_VMReg() ); // v farg11
187 reg_def F11_H( SOC, SOC, Op_RegF, 99, F11->as_VMReg()->next());
188 reg_def F12 ( SOC, SOC, Op_RegF, 12, F12->as_VMReg() ); // v farg12
189 reg_def F12_H( SOC, SOC, Op_RegF, 99, F12->as_VMReg()->next());
190 reg_def F13 ( SOC, SOC, Op_RegF, 13, F13->as_VMReg() ); // v farg13
191 reg_def F13_H( SOC, SOC, Op_RegF, 99, F13->as_VMReg()->next());
192 reg_def F14 ( SOC, SOE, Op_RegF, 14, F14->as_VMReg() ); // nv
193 reg_def F14_H( SOC, SOE, Op_RegF, 99, F14->as_VMReg()->next());
194 reg_def F15 ( SOC, SOE, Op_RegF, 15, F15->as_VMReg() ); // nv
195 reg_def F15_H( SOC, SOE, Op_RegF, 99, F15->as_VMReg()->next());
196 reg_def F16 ( SOC, SOE, Op_RegF, 16, F16->as_VMReg() ); // nv
197 reg_def F16_H( SOC, SOE, Op_RegF, 99, F16->as_VMReg()->next());
198 reg_def F17 ( SOC, SOE, Op_RegF, 17, F17->as_VMReg() ); // nv
199 reg_def F17_H( SOC, SOE, Op_RegF, 99, F17->as_VMReg()->next());
200 reg_def F18 ( SOC, SOE, Op_RegF, 18, F18->as_VMReg() ); // nv
201 reg_def F18_H( SOC, SOE, Op_RegF, 99, F18->as_VMReg()->next());
202 reg_def F19 ( SOC, SOE, Op_RegF, 19, F19->as_VMReg() ); // nv
203 reg_def F19_H( SOC, SOE, Op_RegF, 99, F19->as_VMReg()->next());
204 reg_def F20 ( SOC, SOE, Op_RegF, 20, F20->as_VMReg() ); // nv
205 reg_def F20_H( SOC, SOE, Op_RegF, 99, F20->as_VMReg()->next());
206 reg_def F21 ( SOC, SOE, Op_RegF, 21, F21->as_VMReg() ); // nv
207 reg_def F21_H( SOC, SOE, Op_RegF, 99, F21->as_VMReg()->next());
208 reg_def F22 ( SOC, SOE, Op_RegF, 22, F22->as_VMReg() ); // nv
209 reg_def F22_H( SOC, SOE, Op_RegF, 99, F22->as_VMReg()->next());
210 reg_def F23 ( SOC, SOE, Op_RegF, 23, F23->as_VMReg() ); // nv
211 reg_def F23_H( SOC, SOE, Op_RegF, 99, F23->as_VMReg()->next());
212 reg_def F24 ( SOC, SOE, Op_RegF, 24, F24->as_VMReg() ); // nv
213 reg_def F24_H( SOC, SOE, Op_RegF, 99, F24->as_VMReg()->next());
214 reg_def F25 ( SOC, SOE, Op_RegF, 25, F25->as_VMReg() ); // nv
215 reg_def F25_H( SOC, SOE, Op_RegF, 99, F25->as_VMReg()->next());
216 reg_def F26 ( SOC, SOE, Op_RegF, 26, F26->as_VMReg() ); // nv
217 reg_def F26_H( SOC, SOE, Op_RegF, 99, F26->as_VMReg()->next());
218 reg_def F27 ( SOC, SOE, Op_RegF, 27, F27->as_VMReg() ); // nv
219 reg_def F27_H( SOC, SOE, Op_RegF, 99, F27->as_VMReg()->next());
220 reg_def F28 ( SOC, SOE, Op_RegF, 28, F28->as_VMReg() ); // nv
221 reg_def F28_H( SOC, SOE, Op_RegF, 99, F28->as_VMReg()->next());
222 reg_def F29 ( SOC, SOE, Op_RegF, 29, F29->as_VMReg() ); // nv
223 reg_def F29_H( SOC, SOE, Op_RegF, 99, F29->as_VMReg()->next());
224 reg_def F30 ( SOC, SOE, Op_RegF, 30, F30->as_VMReg() ); // nv
225 reg_def F30_H( SOC, SOE, Op_RegF, 99, F30->as_VMReg()->next());
226 reg_def F31 ( SOC, SOE, Op_RegF, 31, F31->as_VMReg() ); // nv
227 reg_def F31_H( SOC, SOE, Op_RegF, 99, F31->as_VMReg()->next());
228
229 // ----------------------------
230 // Special Registers
231 // ----------------------------
232
233 // Condition Codes Flag Registers
234
235 // PPC64 has 8 condition code "registers" which are all contained
236 // in the CR register.
237
238 // types: v = volatile, nv = non-volatile, s = system
239 reg_def CCR0(SOC, SOC, Op_RegFlags, 0, CCR0->as_VMReg()); // v
240 reg_def CCR1(SOC, SOC, Op_RegFlags, 1, CCR1->as_VMReg()); // v
241 reg_def CCR2(SOC, SOC, Op_RegFlags, 2, CCR2->as_VMReg()); // nv
242 reg_def CCR3(SOC, SOC, Op_RegFlags, 3, CCR3->as_VMReg()); // nv
243 reg_def CCR4(SOC, SOC, Op_RegFlags, 4, CCR4->as_VMReg()); // nv
244 reg_def CCR5(SOC, SOC, Op_RegFlags, 5, CCR5->as_VMReg()); // v
245 reg_def CCR6(SOC, SOC, Op_RegFlags, 6, CCR6->as_VMReg()); // v
246 reg_def CCR7(SOC, SOC, Op_RegFlags, 7, CCR7->as_VMReg()); // v
247
248 // Special registers of PPC64
249
250 reg_def SR_XER( SOC, SOC, Op_RegP, 0, SR_XER->as_VMReg()); // v
251 reg_def SR_LR( SOC, SOC, Op_RegP, 1, SR_LR->as_VMReg()); // v
252 reg_def SR_CTR( SOC, SOC, Op_RegP, 2, SR_CTR->as_VMReg()); // v
253 reg_def SR_VRSAVE( SOC, SOC, Op_RegP, 3, SR_VRSAVE->as_VMReg()); // v
254 reg_def SR_SPEFSCR(SOC, SOC, Op_RegP, 4, SR_SPEFSCR->as_VMReg()); // v
255 reg_def SR_PPR( SOC, SOC, Op_RegP, 5, SR_PPR->as_VMReg()); // v
256
257
258 // ----------------------------
259 // Specify priority of register selection within phases of register
260 // allocation. Highest priority is first. A useful heuristic is to
261 // give registers a low priority when they are required by machine
262 // instructions, like EAX and EDX on I486, and choose no-save registers
263 // before save-on-call, & save-on-call before save-on-entry. Registers
264 // which participate in fixed calling sequences should come last.
265 // Registers which are used as pairs must fall on an even boundary.
266
267 // It's worth about 1% on SPEC geomean to get this right.
268
269 // Chunk0, chunk1, and chunk2 form the MachRegisterNumbers enumeration
270 // in adGlobals_ppc64.hpp which defines the <register>_num values, e.g.
271 // R3_num. Therefore, R3_num may not be (and in reality is not)
272 // the same as R3->encoding()! Furthermore, we cannot make any
273 // assumptions on ordering, e.g. R3_num may be less than R2_num.
274 // Additionally, the function
275 // static enum RC rc_class(OptoReg::Name reg )
276 // maps a given <register>_num value to its chunk type (except for flags)
277 // and its current implementation relies on chunk0 and chunk1 having a
278 // size of 64 each.
279
280 // If you change this allocation class, please have a look at the
281 // default values for the parameters RoundRobinIntegerRegIntervalStart
282 // and RoundRobinFloatRegIntervalStart
283
284 alloc_class chunk0 (
285 // Chunk0 contains *all* 64 integer registers halves.
286
287 // "non-volatile" registers
288 R14, R14_H,
289 R15, R15_H,
290 R17, R17_H,
291 R18, R18_H,
292 R19, R19_H,
293 R20, R20_H,
294 R21, R21_H,
295 R22, R22_H,
296 R23, R23_H,
297 R24, R24_H,
298 R25, R25_H,
299 R26, R26_H,
300 R27, R27_H,
301 R28, R28_H,
302 R29, R29_H,
303 R30, R30_H,
304 R31, R31_H,
305
306 // scratch/special registers
307 R11, R11_H,
308 R12, R12_H,
309
310 // argument registers
311 R10, R10_H,
312 R9, R9_H,
313 R8, R8_H,
314 R7, R7_H,
315 R6, R6_H,
316 R5, R5_H,
317 R4, R4_H,
318 R3, R3_H,
319
320 // special registers, not available for allocation
321 R16, R16_H, // R16_thread
322 R13, R13_H, // system thread id
323 R2, R2_H, // may be used for TOC
324 R1, R1_H, // SP
325 R0, R0_H // R0 (scratch)
326 );
327
328 // If you change this allocation class, please have a look at the
329 // default values for the parameters RoundRobinIntegerRegIntervalStart
330 // and RoundRobinFloatRegIntervalStart
331
332 alloc_class chunk1 (
333 // Chunk1 contains *all* 64 floating-point registers halves.
334
335 // scratch register
336 F0, F0_H,
337
338 // argument registers
339 F13, F13_H,
340 F12, F12_H,
341 F11, F11_H,
342 F10, F10_H,
343 F9, F9_H,
344 F8, F8_H,
345 F7, F7_H,
346 F6, F6_H,
347 F5, F5_H,
348 F4, F4_H,
349 F3, F3_H,
350 F2, F2_H,
351 F1, F1_H,
352
353 // non-volatile registers
354 F14, F14_H,
355 F15, F15_H,
356 F16, F16_H,
357 F17, F17_H,
358 F18, F18_H,
359 F19, F19_H,
360 F20, F20_H,
361 F21, F21_H,
362 F22, F22_H,
363 F23, F23_H,
364 F24, F24_H,
365 F25, F25_H,
366 F26, F26_H,
367 F27, F27_H,
368 F28, F28_H,
369 F29, F29_H,
370 F30, F30_H,
371 F31, F31_H
372 );
373
374 alloc_class chunk2 (
375 // Chunk2 contains *all* 8 condition code registers.
376
377 CCR0,
378 CCR1,
379 CCR2,
380 CCR3,
381 CCR4,
382 CCR5,
383 CCR6,
384 CCR7
385 );
386
387 alloc_class chunk3 (
388 // special registers
389 // These registers are not allocated, but used for nodes generated by postalloc expand.
390 SR_XER,
391 SR_LR,
392 SR_CTR,
393 SR_VRSAVE,
394 SR_SPEFSCR,
395 SR_PPR
396 );
397
398 //-------Architecture Description Register Classes-----------------------
399
400 // Several register classes are automatically defined based upon
401 // information in this architecture description.
402
403 // 1) reg_class inline_cache_reg ( as defined in frame section )
404 // 2) reg_class compiler_method_oop_reg ( as defined in frame section )
405 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
406 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
407 //
408
409 // ----------------------------
410 // 32 Bit Register Classes
411 // ----------------------------
412
413 // We specify registers twice, once as read/write, and once read-only.
414 // We use the read-only registers for source operands. With this, we
415 // can include preset read only registers in this class, as a hard-coded
416 // '0'-register. (We used to simulate this on ppc.)
417
418 // 32 bit registers that can be read and written i.e. these registers
419 // can be dest (or src) of normal instructions.
420 reg_class bits32_reg_rw(
421 /*R0*/ // R0
422 /*R1*/ // SP
423 R2, // TOC
424 R3,
425 R4,
426 R5,
427 R6,
428 R7,
429 R8,
430 R9,
431 R10,
432 R11,
433 R12,
434 /*R13*/ // system thread id
435 R14,
436 R15,
437 /*R16*/ // R16_thread
438 R17,
439 R18,
440 R19,
441 R20,
442 R21,
443 R22,
444 R23,
445 R24,
446 R25,
447 R26,
448 R27,
449 R28,
450 /*R29*/ // global TOC
451 /*R30*/ // Narrow Oop Base
452 R31
453 );
454
455 // 32 bit registers that can only be read i.e. these registers can
456 // only be src of all instructions.
457 reg_class bits32_reg_ro(
458 /*R0*/ // R0
459 /*R1*/ // SP
460 R2 // TOC
461 R3,
462 R4,
463 R5,
464 R6,
465 R7,
466 R8,
467 R9,
468 R10,
469 R11,
470 R12,
471 /*R13*/ // system thread id
472 R14,
473 R15,
474 /*R16*/ // R16_thread
475 R17,
476 R18,
477 R19,
478 R20,
479 R21,
480 R22,
481 R23,
482 R24,
483 R25,
484 R26,
485 R27,
486 R28,
487 /*R29*/
488 /*R30*/ // Narrow Oop Base
489 R31
490 );
491
492 // Complement-required-in-pipeline operands for narrow oops.
493 reg_class bits32_reg_ro_not_complement (
494 /*R0*/ // R0
495 R1, // SP
496 R2, // TOC
497 R3,
498 R4,
499 R5,
500 R6,
501 R7,
502 R8,
503 R9,
504 R10,
505 R11,
506 R12,
507 /*R13,*/ // system thread id
508 R14,
509 R15,
510 R16, // R16_thread
511 R17,
512 R18,
513 R19,
514 R20,
515 R21,
516 R22,
517 /*R23,
518 R24,
519 R25,
520 R26,
521 R27,
522 R28,*/
523 /*R29,*/ // TODO: let allocator handle TOC!!
524 /*R30,*/
525 R31
526 );
527
528 // Complement-required-in-pipeline operands for narrow oops.
529 // See 64-bit declaration.
530 reg_class bits32_reg_ro_complement (
531 R23,
532 R24,
533 R25,
534 R26,
535 R27,
536 R28
537 );
538
539 reg_class rscratch1_bits32_reg(R11);
540 reg_class rscratch2_bits32_reg(R12);
541 reg_class rarg1_bits32_reg(R3);
542 reg_class rarg2_bits32_reg(R4);
543 reg_class rarg3_bits32_reg(R5);
544 reg_class rarg4_bits32_reg(R6);
545
546 // ----------------------------
547 // 64 Bit Register Classes
548 // ----------------------------
549 // 64-bit build means 64-bit pointers means hi/lo pairs
550
551 reg_class rscratch1_bits64_reg(R11_H, R11);
552 reg_class rscratch2_bits64_reg(R12_H, R12);
553 reg_class rarg1_bits64_reg(R3_H, R3);
554 reg_class rarg2_bits64_reg(R4_H, R4);
555 reg_class rarg3_bits64_reg(R5_H, R5);
556 reg_class rarg4_bits64_reg(R6_H, R6);
557 // Thread register, 'written' by tlsLoadP, see there.
558 reg_class thread_bits64_reg(R16_H, R16);
559
560 reg_class r19_bits64_reg(R19_H, R19);
561
562 // 64 bit registers that can be read and written i.e. these registers
563 // can be dest (or src) of normal instructions.
564 reg_class bits64_reg_rw(
565 /*R0_H, R0*/ // R0
566 /*R1_H, R1*/ // SP
567 R2_H, R2, // TOC
568 R3_H, R3,
569 R4_H, R4,
570 R5_H, R5,
571 R6_H, R6,
572 R7_H, R7,
573 R8_H, R8,
574 R9_H, R9,
575 R10_H, R10,
576 R11_H, R11,
577 R12_H, R12,
578 /*R13_H, R13*/ // system thread id
579 R14_H, R14,
580 R15_H, R15,
581 /*R16_H, R16*/ // R16_thread
582 R17_H, R17,
583 R18_H, R18,
584 R19_H, R19,
585 R20_H, R20,
586 R21_H, R21,
587 R22_H, R22,
588 R23_H, R23,
589 R24_H, R24,
590 R25_H, R25,
591 R26_H, R26,
592 R27_H, R27,
593 R28_H, R28,
594 /*R29_H, R29*/
595 /*R30_H, R30*/
596 R31_H, R31
597 );
598
599 // 64 bit registers used excluding r2, r11 and r12
600 // Used to hold the TOC to avoid collisions with expanded LeafCall which uses
601 // r2, r11 and r12 internally.
602 reg_class bits64_reg_leaf_call(
603 /*R0_H, R0*/ // R0
604 /*R1_H, R1*/ // SP
605 /*R2_H, R2*/ // TOC
606 R3_H, R3,
607 R4_H, R4,
608 R5_H, R5,
609 R6_H, R6,
610 R7_H, R7,
611 R8_H, R8,
612 R9_H, R9,
613 R10_H, R10,
614 /*R11_H, R11*/
615 /*R12_H, R12*/
616 /*R13_H, R13*/ // system thread id
617 R14_H, R14,
618 R15_H, R15,
619 /*R16_H, R16*/ // R16_thread
620 R17_H, R17,
621 R18_H, R18,
622 R19_H, R19,
623 R20_H, R20,
624 R21_H, R21,
625 R22_H, R22,
626 R23_H, R23,
627 R24_H, R24,
628 R25_H, R25,
629 R26_H, R26,
630 R27_H, R27,
631 R28_H, R28,
632 /*R29_H, R29*/
633 /*R30_H, R30*/
634 R31_H, R31
635 );
636
637 // Used to hold the TOC to avoid collisions with expanded DynamicCall
638 // which uses r19 as inline cache internally and expanded LeafCall which uses
639 // r2, r11 and r12 internally.
640 reg_class bits64_constant_table_base(
641 /*R0_H, R0*/ // R0
642 /*R1_H, R1*/ // SP
643 /*R2_H, R2*/ // TOC
644 R3_H, R3,
645 R4_H, R4,
646 R5_H, R5,
647 R6_H, R6,
648 R7_H, R7,
649 R8_H, R8,
650 R9_H, R9,
651 R10_H, R10,
652 /*R11_H, R11*/
653 /*R12_H, R12*/
654 /*R13_H, R13*/ // system thread id
655 R14_H, R14,
656 R15_H, R15,
657 /*R16_H, R16*/ // R16_thread
658 R17_H, R17,
659 R18_H, R18,
660 /*R19_H, R19*/
661 R20_H, R20,
662 R21_H, R21,
663 R22_H, R22,
664 R23_H, R23,
665 R24_H, R24,
666 R25_H, R25,
667 R26_H, R26,
668 R27_H, R27,
669 R28_H, R28,
670 /*R29_H, R29*/
671 /*R30_H, R30*/
672 R31_H, R31
673 );
674
675 // 64 bit registers that can only be read i.e. these registers can
676 // only be src of all instructions.
677 reg_class bits64_reg_ro(
678 /*R0_H, R0*/ // R0
679 R1_H, R1,
680 R2_H, R2, // TOC
681 R3_H, R3,
682 R4_H, R4,
683 R5_H, R5,
684 R6_H, R6,
685 R7_H, R7,
686 R8_H, R8,
687 R9_H, R9,
688 R10_H, R10,
689 R11_H, R11,
690 R12_H, R12,
691 /*R13_H, R13*/ // system thread id
692 R14_H, R14,
693 R15_H, R15,
694 R16_H, R16, // R16_thread
695 R17_H, R17,
696 R18_H, R18,
697 R19_H, R19,
698 R20_H, R20,
699 R21_H, R21,
700 R22_H, R22,
701 R23_H, R23,
702 R24_H, R24,
703 R25_H, R25,
704 R26_H, R26,
705 R27_H, R27,
706 R28_H, R28,
707 /*R29_H, R29*/ // TODO: let allocator handle TOC!!
708 /*R30_H, R30,*/
709 R31_H, R31
710 );
711
712 // Complement-required-in-pipeline operands.
713 reg_class bits64_reg_ro_not_complement (
714 /*R0_H, R0*/ // R0
715 R1_H, R1, // SP
716 R2_H, R2, // TOC
717 R3_H, R3,
718 R4_H, R4,
719 R5_H, R5,
720 R6_H, R6,
721 R7_H, R7,
722 R8_H, R8,
723 R9_H, R9,
724 R10_H, R10,
725 R11_H, R11,
726 R12_H, R12,
727 /*R13_H, R13*/ // system thread id
728 R14_H, R14,
729 R15_H, R15,
730 R16_H, R16, // R16_thread
731 R17_H, R17,
732 R18_H, R18,
733 R19_H, R19,
734 R20_H, R20,
735 R21_H, R21,
736 R22_H, R22,
737 /*R23_H, R23,
738 R24_H, R24,
739 R25_H, R25,
740 R26_H, R26,
741 R27_H, R27,
742 R28_H, R28,*/
743 /*R29_H, R29*/ // TODO: let allocator handle TOC!!
744 /*R30_H, R30,*/
745 R31_H, R31
746 );
747
748 // Complement-required-in-pipeline operands.
749 // This register mask is used for the trap instructions that implement
750 // the null checks on AIX. The trap instruction first computes the
751 // complement of the value it shall trap on. Because of this, the
752 // instruction can not be scheduled in the same cycle as an other
753 // instruction reading the normal value of the same register. So we
754 // force the value to check into 'bits64_reg_ro_not_complement'
755 // and then copy it to 'bits64_reg_ro_complement' for the trap.
756 reg_class bits64_reg_ro_complement (
757 R23_H, R23,
758 R24_H, R24,
759 R25_H, R25,
760 R26_H, R26,
761 R27_H, R27,
762 R28_H, R28
763 );
764
765
766 // ----------------------------
767 // Special Class for Condition Code Flags Register
768
769 reg_class int_flags(
770 /*CCR0*/ // scratch
771 /*CCR1*/ // scratch
772 /*CCR2*/ // nv!
773 /*CCR3*/ // nv!
774 /*CCR4*/ // nv!
775 CCR5,
776 CCR6,
777 CCR7
778 );
779
780 reg_class int_flags_CR0(CCR0);
781 reg_class int_flags_CR1(CCR1);
782 reg_class int_flags_CR6(CCR6);
783 reg_class ctr_reg(SR_CTR);
784
785 // ----------------------------
786 // Float Register Classes
787 // ----------------------------
788
789 reg_class flt_reg(
790 /*F0*/ // scratch
791 F1,
792 F2,
793 F3,
794 F4,
795 F5,
796 F6,
797 F7,
798 F8,
799 F9,
800 F10,
801 F11,
802 F12,
803 F13,
804 F14, // nv!
805 F15, // nv!
806 F16, // nv!
807 F17, // nv!
808 F18, // nv!
809 F19, // nv!
810 F20, // nv!
811 F21, // nv!
812 F22, // nv!
813 F23, // nv!
814 F24, // nv!
815 F25, // nv!
816 F26, // nv!
817 F27, // nv!
818 F28, // nv!
819 F29, // nv!
820 F30, // nv!
821 F31 // nv!
822 );
823
824 // Double precision float registers have virtual `high halves' that
825 // are needed by the allocator.
826 reg_class dbl_reg(
827 /*F0, F0_H*/ // scratch
828 F1, F1_H,
829 F2, F2_H,
830 F3, F3_H,
831 F4, F4_H,
832 F5, F5_H,
833 F6, F6_H,
834 F7, F7_H,
835 F8, F8_H,
836 F9, F9_H,
837 F10, F10_H,
838 F11, F11_H,
839 F12, F12_H,
840 F13, F13_H,
841 F14, F14_H, // nv!
842 F15, F15_H, // nv!
843 F16, F16_H, // nv!
844 F17, F17_H, // nv!
845 F18, F18_H, // nv!
846 F19, F19_H, // nv!
847 F20, F20_H, // nv!
848 F21, F21_H, // nv!
849 F22, F22_H, // nv!
850 F23, F23_H, // nv!
851 F24, F24_H, // nv!
852 F25, F25_H, // nv!
853 F26, F26_H, // nv!
854 F27, F27_H, // nv!
855 F28, F28_H, // nv!
856 F29, F29_H, // nv!
857 F30, F30_H, // nv!
858 F31, F31_H // nv!
859 );
860
861 %}
862
863 //----------DEFINITION BLOCK---------------------------------------------------
864 // Define name --> value mappings to inform the ADLC of an integer valued name
865 // Current support includes integer values in the range [0, 0x7FFFFFFF]
866 // Format:
867 // int_def <name> ( <int_value>, <expression>);
868 // Generated Code in ad_<arch>.hpp
869 // #define <name> (<expression>)
870 // // value == <int_value>
871 // Generated code in ad_<arch>.cpp adlc_verification()
872 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
873 //
874 definitions %{
875 // The default cost (of an ALU instruction).
876 int_def DEFAULT_COST_LOW ( 30, 30);
877 int_def DEFAULT_COST ( 100, 100);
878 int_def HUGE_COST (1000000, 1000000);
879
880 // Memory refs
881 int_def MEMORY_REF_COST_LOW ( 200, DEFAULT_COST * 2);
882 int_def MEMORY_REF_COST ( 300, DEFAULT_COST * 3);
883
884 // Branches are even more expensive.
885 int_def BRANCH_COST ( 900, DEFAULT_COST * 9);
886 int_def CALL_COST ( 1300, DEFAULT_COST * 13);
887 %}
888
889
890 //----------SOURCE BLOCK-------------------------------------------------------
891 // This is a block of C++ code which provides values, functions, and
892 // definitions necessary in the rest of the architecture description.
893 source_hpp %{
894 // Header information of the source block.
895 // Method declarations/definitions which are used outside
896 // the ad-scope can conveniently be defined here.
897 //
898 // To keep related declarations/definitions/uses close together,
899 // we switch between source %{ }% and source_hpp %{ }% freely as needed.
900
901 // Returns true if Node n is followed by a MemBar node that
902 // will do an acquire. If so, this node must not do the acquire
903 // operation.
904 bool followed_by_acquire(const Node *n);
905 %}
906
907 source %{
908
909 // Optimize load-acquire.
910 //
911 // Check if acquire is unnecessary due to following operation that does
912 // acquire anyways.
913 // Walk the pattern:
914 //
915 // n: Load.acq
916 // |
917 // MemBarAcquire
918 // | |
919 // Proj(ctrl) Proj(mem)
920 // | |
921 // MemBarRelease/Volatile
922 //
923 bool followed_by_acquire(const Node *load) {
924 assert(load->is_Load(), "So far implemented only for loads.");
925
926 // Find MemBarAcquire.
927 const Node *mba = NULL;
928 for (DUIterator_Fast imax, i = load->fast_outs(imax); i < imax; i++) {
929 const Node *out = load->fast_out(i);
930 if (out->Opcode() == Op_MemBarAcquire) {
931 if (out->in(0) == load) continue; // Skip control edge, membar should be found via precedence edge.
932 mba = out;
933 break;
934 }
935 }
936 if (!mba) return false;
937
938 // Find following MemBar node.
939 //
940 // The following node must be reachable by control AND memory
941 // edge to assure no other operations are in between the two nodes.
942 //
943 // So first get the Proj node, mem_proj, to use it to iterate forward.
944 Node *mem_proj = NULL;
945 for (DUIterator_Fast imax, i = mba->fast_outs(imax); i < imax; i++) {
946 mem_proj = mba->fast_out(i); // Throw out-of-bounds if proj not found
947 assert(mem_proj->is_Proj(), "only projections here");
948 ProjNode *proj = mem_proj->as_Proj();
949 if (proj->_con == TypeFunc::Memory &&
950 !Compile::current()->node_arena()->contains(mem_proj)) // Unmatched old-space only
951 break;
952 }
953 assert(mem_proj->as_Proj()->_con == TypeFunc::Memory, "Graph broken");
954
955 // Search MemBar behind Proj. If there are other memory operations
956 // behind the Proj we lost.
957 for (DUIterator_Fast jmax, j = mem_proj->fast_outs(jmax); j < jmax; j++) {
958 Node *x = mem_proj->fast_out(j);
959 // Proj might have an edge to a store or load node which precedes the membar.
960 if (x->is_Mem()) return false;
961
962 // On PPC64 release and volatile are implemented by an instruction
963 // that also has acquire semantics. I.e. there is no need for an
964 // acquire before these.
965 int xop = x->Opcode();
966 if (xop == Op_MemBarRelease || xop == Op_MemBarVolatile) {
967 // Make sure we're not missing Call/Phi/MergeMem by checking
968 // control edges. The control edge must directly lead back
969 // to the MemBarAcquire
970 Node *ctrl_proj = x->in(0);
971 if (ctrl_proj->is_Proj() && ctrl_proj->in(0) == mba) {
972 return true;
973 }
974 }
975 }
976
977 return false;
978 }
979
980 #define __ _masm.
981
982 // Tertiary op of a LoadP or StoreP encoding.
983 #define REGP_OP true
984
985 // ****************************************************************************
986
987 // REQUIRED FUNCTIONALITY
988
989 // !!!!! Special hack to get all type of calls to specify the byte offset
990 // from the start of the call to the point where the return address
991 // will point.
992
993 // PPC port: Removed use of lazy constant construct.
994
995 int MachCallStaticJavaNode::ret_addr_offset() {
996 // It's only a single branch-and-link instruction.
997 return 4;
998 }
999
1000 int MachCallDynamicJavaNode::ret_addr_offset() {
1001 // Offset is 4 with postalloc expanded calls (bl is one instruction). We use
1002 // postalloc expanded calls if we use inline caches and do not update method data.
1003 if (UseInlineCaches)
1004 return 4;
1005
1006 int vtable_index = this->_vtable_index;
1007 if (vtable_index < 0) {
1008 // Must be invalid_vtable_index, not nonvirtual_vtable_index.
1009 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
1010 return 12;
1011 } else {
1012 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
1013 return 24;
1014 }
1015 }
1016
1017 int MachCallRuntimeNode::ret_addr_offset() {
1018 #if defined(ABI_ELFv2)
1019 return 28;
1020 #else
1021 return 40;
1022 #endif
1023 }
1024
1025 //=============================================================================
1026
1027 // condition code conversions
1028
1029 static int cc_to_boint(int cc) {
1030 return Assembler::bcondCRbiIs0 | (cc & 8);
1031 }
1032
1033 static int cc_to_inverse_boint(int cc) {
1034 return Assembler::bcondCRbiIs0 | (8-(cc & 8));
1035 }
1036
1037 static int cc_to_biint(int cc, int flags_reg) {
1038 return (flags_reg << 2) | (cc & 3);
1039 }
1040
1041 //=============================================================================
1042
1043 // Compute padding required for nodes which need alignment. The padding
1044 // is the number of bytes (not instructions) which will be inserted before
1045 // the instruction. The padding must match the size of a NOP instruction.
1046
1047 int string_indexOf_imm1_charNode::compute_padding(int current_offset) const {
1048 return (3*4-current_offset)&31;
1049 }
1050
1051 int string_indexOf_imm1Node::compute_padding(int current_offset) const {
1052 return (2*4-current_offset)&31;
1053 }
1054
1055 int string_indexOf_immNode::compute_padding(int current_offset) const {
1056 return (3*4-current_offset)&31;
1057 }
1058
1059 int string_indexOfNode::compute_padding(int current_offset) const {
1060 return (1*4-current_offset)&31;
1061 }
1062
1063 int string_compareNode::compute_padding(int current_offset) const {
1064 return (4*4-current_offset)&31;
1065 }
1066
1067 int string_equals_immNode::compute_padding(int current_offset) const {
1068 if (opnd_array(3)->constant() < 16) return 0; // Don't insert nops for short version (loop completely unrolled).
1069 return (2*4-current_offset)&31;
1070 }
1071
1072 int string_equalsNode::compute_padding(int current_offset) const {
1073 return (7*4-current_offset)&31;
1074 }
1075
1076 int inlineCallClearArrayNode::compute_padding(int current_offset) const {
1077 return (2*4-current_offset)&31;
1078 }
1079
1080 //=============================================================================
1081
1082 // Indicate if the safepoint node needs the polling page as an input.
1083 bool SafePointNode::needs_polling_address_input() {
1084 // The address is loaded from thread by a seperate node.
1085 return true;
1086 }
1087
1088 //=============================================================================
1089
1090 // Emit an interrupt that is caught by the debugger (for debugging compiler).
1091 void emit_break(CodeBuffer &cbuf) {
1092 MacroAssembler _masm(&cbuf);
1093 __ illtrap();
1094 }
1095
1096 #ifndef PRODUCT
1097 void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1098 st->print("BREAKPOINT");
1099 }
1100 #endif
1101
1102 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1103 emit_break(cbuf);
1104 }
1105
1106 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
1107 return MachNode::size(ra_);
1108 }
1109
1110 //=============================================================================
1111
1112 void emit_nop(CodeBuffer &cbuf) {
1113 MacroAssembler _masm(&cbuf);
1114 __ nop();
1115 }
1116
1117 static inline void emit_long(CodeBuffer &cbuf, int value) {
1118 *((int*)(cbuf.insts_end())) = value;
1119 cbuf.set_insts_end(cbuf.insts_end() + BytesPerInstWord);
1120 }
1121
1122 //=============================================================================
1123
1124 %} // interrupt source
1125
1126 source_hpp %{ // Header information of the source block.
1127
1128 //--------------------------------------------------------------
1129 //---< Used for optimization in Compile::Shorten_branches >---
1130 //--------------------------------------------------------------
1131
1132 const uint trampoline_stub_size = 6 * BytesPerInstWord;
1133
1134 class CallStubImpl {
1135
1136 public:
1137
1138 // Emit call stub, compiled java to interpreter.
1139 static void emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset);
1140
1141 // Size of call trampoline stub.
1142 // This doesn't need to be accurate to the byte, but it
1143 // must be larger than or equal to the real size of the stub.
1144 static uint size_call_trampoline() {
1145 return trampoline_stub_size;
1146 }
1147
1148 // number of relocations needed by a call trampoline stub
1149 static uint reloc_call_trampoline() {
1150 return 5;
1151 }
1152
1153 };
1154
1155 %} // end source_hpp
1156
1157 source %{
1158
1159 // Emit a trampoline stub for a call to a target which is too far away.
1160 //
1161 // code sequences:
1162 //
1163 // call-site:
1164 // branch-and-link to <destination> or <trampoline stub>
1165 //
1166 // Related trampoline stub for this call-site in the stub section:
1167 // load the call target from the constant pool
1168 // branch via CTR (LR/link still points to the call-site above)
1169
1170 void CallStubImpl::emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset) {
1171 // Start the stub.
1172 address stub = __ start_a_stub(Compile::MAX_stubs_size/2);
1173 if (stub == NULL) {
1174 ciEnv::current()->record_failure("CodeCache is full");
1175 return;
1176 }
1177
1178 // For java_to_interp stubs we use R11_scratch1 as scratch register
1179 // and in call trampoline stubs we use R12_scratch2. This way we
1180 // can distinguish them (see is_NativeCallTrampolineStub_at()).
1181 Register reg_scratch = R12_scratch2;
1182
1183 // Create a trampoline stub relocation which relates this trampoline stub
1184 // with the call instruction at insts_call_instruction_offset in the
1185 // instructions code-section.
1186 __ relocate(trampoline_stub_Relocation::spec(__ code()->insts()->start() + insts_call_instruction_offset));
1187 const int stub_start_offset = __ offset();
1188
1189 // Now, create the trampoline stub's code:
1190 // - load the TOC
1191 // - load the call target from the constant pool
1192 // - call
1193 __ calculate_address_from_global_toc(reg_scratch, __ method_toc());
1194 __ ld_largeoffset_unchecked(reg_scratch, destination_toc_offset, reg_scratch, false);
1195 __ mtctr(reg_scratch);
1196 __ bctr();
1197
1198 const address stub_start_addr = __ addr_at(stub_start_offset);
1199
1200 // FIXME: Assert that the trampoline stub can be identified and patched.
1201
1202 // Assert that the encoded destination_toc_offset can be identified and that it is correct.
1203 assert(destination_toc_offset == NativeCallTrampolineStub_at(stub_start_addr)->destination_toc_offset(),
1204 "encoded offset into the constant pool must match");
1205 // Trampoline_stub_size should be good.
1206 assert((uint)(__ offset() - stub_start_offset) <= trampoline_stub_size, "should be good size");
1207 assert(is_NativeCallTrampolineStub_at(stub_start_addr), "doesn't look like a trampoline");
1208
1209 // End the stub.
1210 __ end_a_stub();
1211 }
1212
1213 //=============================================================================
1214
1215 // Emit an inline branch-and-link call and a related trampoline stub.
1216 //
1217 // code sequences:
1218 //
1219 // call-site:
1220 // branch-and-link to <destination> or <trampoline stub>
1221 //
1222 // Related trampoline stub for this call-site in the stub section:
1223 // load the call target from the constant pool
1224 // branch via CTR (LR/link still points to the call-site above)
1225 //
1226
1227 typedef struct {
1228 int insts_call_instruction_offset;
1229 int ret_addr_offset;
1230 } EmitCallOffsets;
1231
1232 // Emit a branch-and-link instruction that branches to a trampoline.
1233 // - Remember the offset of the branch-and-link instruction.
1234 // - Add a relocation at the branch-and-link instruction.
1235 // - Emit a branch-and-link.
1236 // - Remember the return pc offset.
1237 EmitCallOffsets emit_call_with_trampoline_stub(MacroAssembler &_masm, address entry_point, relocInfo::relocType rtype) {
1238 EmitCallOffsets offsets = { -1, -1 };
1239 const int start_offset = __ offset();
1240 offsets.insts_call_instruction_offset = __ offset();
1241
1242 // No entry point given, use the current pc.
1243 if (entry_point == NULL) entry_point = __ pc();
1244
1245 if (!Compile::current()->in_scratch_emit_size()) {
1246 // Put the entry point as a constant into the constant pool.
1247 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none);
1248 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
1249
1250 // Emit the trampoline stub which will be related to the branch-and-link below.
1251 CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, offsets.insts_call_instruction_offset);
1252 if (ciEnv::current()->failing()) { return offsets; } // Code cache may be full.
1253 __ relocate(rtype);
1254 }
1255
1256 // Note: At this point we do not have the address of the trampoline
1257 // stub, and the entry point might be too far away for bl, so __ pc()
1258 // serves as dummy and the bl will be patched later.
1259 __ bl((address) __ pc());
1260
1261 offsets.ret_addr_offset = __ offset() - start_offset;
1262
1263 return offsets;
1264 }
1265
1266 //=============================================================================
1267
1268 // Factory for creating loadConL* nodes for large/small constant pool.
1269
1270 static inline jlong replicate_immF(float con) {
1271 // Replicate float con 2 times and pack into vector.
1272 int val = *((int*)&con);
1273 jlong lval = val;
1274 lval = (lval << 32) | (lval & 0xFFFFFFFFl);
1275 return lval;
1276 }
1277
1278 //=============================================================================
1279
1280 const RegMask& MachConstantBaseNode::_out_RegMask = BITS64_CONSTANT_TABLE_BASE_mask();
1281 int Compile::ConstantTable::calculate_table_base_offset() const {
1282 return 0; // absolute addressing, no offset
1283 }
1284
1285 bool MachConstantBaseNode::requires_postalloc_expand() const { return true; }
1286 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1287 Compile *C = ra_->C;
1288
1289 iRegPdstOper *op_dst = new (C) iRegPdstOper();
1290 MachNode *m1 = new (C) loadToc_hiNode();
1291 MachNode *m2 = new (C) loadToc_loNode();
1292
1293 m1->add_req(NULL);
1294 m2->add_req(NULL, m1);
1295 m1->_opnds[0] = op_dst;
1296 m2->_opnds[0] = op_dst;
1297 m2->_opnds[1] = op_dst;
1298 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
1299 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
1300 nodes->push(m1);
1301 nodes->push(m2);
1302 }
1303
1304 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1305 // Is postalloc expanded.
1306 ShouldNotReachHere();
1307 }
1308
1309 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
1310 return 0;
1311 }
1312
1313 #ifndef PRODUCT
1314 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1315 st->print("-- \t// MachConstantBaseNode (empty encoding)");
1316 }
1317 #endif
1318
1319 //=============================================================================
1320
1321 #ifndef PRODUCT
1322 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1323 Compile* C = ra_->C;
1324 const long framesize = C->frame_slots() << LogBytesPerInt;
1325
1326 st->print("PROLOG\n\t");
1327 if (C->need_stack_bang(framesize)) {
1328 st->print("stack_overflow_check\n\t");
1329 }
1330
1331 if (!false /* TODO: PPC port C->is_frameless_method()*/) {
1332 st->print("save return pc\n\t");
1333 st->print("push frame %ld\n\t", -framesize);
1334 }
1335 }
1336 #endif
1337
1338 // Macro used instead of the common __ to emulate the pipes of PPC.
1339 // Instead of e.g. __ ld(...) one hase to write ___(ld) ld(...) This enables the
1340 // micro scheduler to cope with "hand written" assembler like in the prolog. Though
1341 // still no scheduling of this code is possible, the micro scheduler is aware of the
1342 // code and can update its internal data. The following mechanism is used to achieve this:
1343 // The micro scheduler calls size() of each compound node during scheduling. size() does a
1344 // dummy emit and only during this dummy emit C->hb_scheduling() is not NULL.
1345 #if 0 // TODO: PPC port
1346 #define ___(op) if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \
1347 C->hb_scheduling()->_pdScheduling->PdEmulatePipe(ppc64Opcode_##op); \
1348 _masm.
1349 #define ___stop if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \
1350 C->hb_scheduling()->_pdScheduling->PdEmulatePipe(archOpcode_none)
1351 #define ___advance if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \
1352 C->hb_scheduling()->_pdScheduling->advance_offset
1353 #else
1354 #define ___(op) if (UsePower6SchedulerPPC64) \
1355 Unimplemented(); \
1356 _masm.
1357 #define ___stop if (UsePower6SchedulerPPC64) \
1358 Unimplemented()
1359 #define ___advance if (UsePower6SchedulerPPC64) \
1360 Unimplemented()
1361 #endif
1362
1363 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1364 Compile* C = ra_->C;
1365 MacroAssembler _masm(&cbuf);
1366
1367 const long framesize = C->frame_size_in_bytes();
1368 assert(framesize % (2 * wordSize) == 0, "must preserve 2*wordSize alignment");
1369
1370 const bool method_is_frameless = false /* TODO: PPC port C->is_frameless_method()*/;
1371
1372 const Register return_pc = R20; // Must match return_addr() in frame section.
1373 const Register callers_sp = R21;
1374 const Register push_frame_temp = R22;
1375 const Register toc_temp = R23;
1376 assert_different_registers(R11, return_pc, callers_sp, push_frame_temp, toc_temp);
1377
1378 if (method_is_frameless) {
1379 // Add nop at beginning of all frameless methods to prevent any
1380 // oop instructions from getting overwritten by make_not_entrant
1381 // (patching attempt would fail).
1382 ___(nop) nop();
1383 } else {
1384 // Get return pc.
1385 ___(mflr) mflr(return_pc);
1386 }
1387
1388 // Calls to C2R adapters often do not accept exceptional returns.
1389 // We require that their callers must bang for them. But be
1390 // careful, because some VM calls (such as call site linkage) can
1391 // use several kilobytes of stack. But the stack safety zone should
1392 // account for that. See bugs 4446381, 4468289, 4497237.
1393
1394 int bangsize = C->bang_size_in_bytes();
1395 assert(bangsize >= framesize || bangsize <= 0, "stack bang size incorrect");
1396 if (C->need_stack_bang(bangsize) && UseStackBanging) {
1397 // Unfortunately we cannot use the function provided in
1398 // assembler.cpp as we have to emulate the pipes. So I had to
1399 // insert the code of generate_stack_overflow_check(), see
1400 // assembler.cpp for some illuminative comments.
1401 const int page_size = os::vm_page_size();
1402 int bang_end = StackShadowPages * page_size;
1403
1404 // This is how far the previous frame's stack banging extended.
1405 const int bang_end_safe = bang_end;
1406
1407 if (bangsize > page_size) {
1408 bang_end += bangsize;
1409 }
1410
1411 int bang_offset = bang_end_safe;
1412
1413 while (bang_offset <= bang_end) {
1414 // Need at least one stack bang at end of shadow zone.
1415
1416 // Again I had to copy code, this time from assembler_ppc.cpp,
1417 // bang_stack_with_offset - see there for comments.
1418
1419 // Stack grows down, caller passes positive offset.
1420 assert(bang_offset > 0, "must bang with positive offset");
1421
1422 long stdoffset = -bang_offset;
1423
1424 if (Assembler::is_simm(stdoffset, 16)) {
1425 // Signed 16 bit offset, a simple std is ok.
1426 if (UseLoadInstructionsForStackBangingPPC64) {
1427 ___(ld) ld(R0, (int)(signed short)stdoffset, R1_SP);
1428 } else {
1429 ___(std) std(R0, (int)(signed short)stdoffset, R1_SP);
1430 }
1431 } else if (Assembler::is_simm(stdoffset, 31)) {
1432 // Use largeoffset calculations for addis & ld/std.
1433 const int hi = MacroAssembler::largeoffset_si16_si16_hi(stdoffset);
1434 const int lo = MacroAssembler::largeoffset_si16_si16_lo(stdoffset);
1435
1436 Register tmp = R11;
1437 ___(addis) addis(tmp, R1_SP, hi);
1438 if (UseLoadInstructionsForStackBangingPPC64) {
1439 ___(ld) ld(R0, lo, tmp);
1440 } else {
1441 ___(std) std(R0, lo, tmp);
1442 }
1443 } else {
1444 ShouldNotReachHere();
1445 }
1446
1447 bang_offset += page_size;
1448 }
1449 // R11 trashed
1450 } // C->need_stack_bang(framesize) && UseStackBanging
1451
1452 unsigned int bytes = (unsigned int)framesize;
1453 long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes);
1454 ciMethod *currMethod = C->method();
1455
1456 // Optimized version for most common case.
1457 if (UsePower6SchedulerPPC64 &&
1458 !method_is_frameless && Assembler::is_simm((int)(-offset), 16) &&
1459 !(false /* ConstantsALot TODO: PPC port*/)) {
1460 ___(or) mr(callers_sp, R1_SP);
1461 ___(std) std(return_pc, _abi(lr), R1_SP);
1462 ___(stdu) stdu(R1_SP, -offset, R1_SP);
1463 return;
1464 }
1465
1466 if (!method_is_frameless) {
1467 // Get callers sp.
1468 ___(or) mr(callers_sp, R1_SP);
1469
1470 // Push method's frame, modifies SP.
1471 assert(Assembler::is_uimm(framesize, 32U), "wrong type");
1472 // The ABI is already accounted for in 'framesize' via the
1473 // 'out_preserve' area.
1474 Register tmp = push_frame_temp;
1475 // Had to insert code of push_frame((unsigned int)framesize, push_frame_temp).
1476 if (Assembler::is_simm(-offset, 16)) {
1477 ___(stdu) stdu(R1_SP, -offset, R1_SP);
1478 } else {
1479 long x = -offset;
1480 // Had to insert load_const(tmp, -offset).
1481 ___(addis) lis( tmp, (int)((signed short)(((x >> 32) & 0xffff0000) >> 16)));
1482 ___(ori) ori( tmp, tmp, ((x >> 32) & 0x0000ffff));
1483 ___(rldicr) sldi(tmp, tmp, 32);
1484 ___(oris) oris(tmp, tmp, (x & 0xffff0000) >> 16);
1485 ___(ori) ori( tmp, tmp, (x & 0x0000ffff));
1486
1487 ___(stdux) stdux(R1_SP, R1_SP, tmp);
1488 }
1489 }
1490 #if 0 // TODO: PPC port
1491 // For testing large constant pools, emit a lot of constants to constant pool.
1492 // "Randomize" const_size.
1493 if (ConstantsALot) {
1494 const int num_consts = const_size();
1495 for (int i = 0; i < num_consts; i++) {
1496 __ long_constant(0xB0B5B00BBABE);
1497 }
1498 }
1499 #endif
1500 if (!method_is_frameless) {
1501 // Save return pc.
1502 ___(std) std(return_pc, _abi(lr), callers_sp);
1503 }
1504 }
1505 #undef ___
1506 #undef ___stop
1507 #undef ___advance
1508
1509 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1510 // Variable size. determine dynamically.
1511 return MachNode::size(ra_);
1512 }
1513
1514 int MachPrologNode::reloc() const {
1515 // Return number of relocatable values contained in this instruction.
1516 return 1; // 1 reloc entry for load_const(toc).
1517 }
1518
1519 //=============================================================================
1520
1521 #ifndef PRODUCT
1522 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1523 Compile* C = ra_->C;
1524
1525 st->print("EPILOG\n\t");
1526 st->print("restore return pc\n\t");
1527 st->print("pop frame\n\t");
1528
1529 if (do_polling() && C->is_method_compilation()) {
1530 st->print("touch polling page\n\t");
1531 }
1532 }
1533 #endif
1534
1535 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1536 Compile* C = ra_->C;
1537 MacroAssembler _masm(&cbuf);
1538
1539 const long framesize = ((long)C->frame_slots()) << LogBytesPerInt;
1540 assert(framesize >= 0, "negative frame-size?");
1541
1542 const bool method_needs_polling = do_polling() && C->is_method_compilation();
1543 const bool method_is_frameless = false /* TODO: PPC port C->is_frameless_method()*/;
1544 const Register return_pc = R11;
1545 const Register polling_page = R12;
1546
1547 if (!method_is_frameless) {
1548 // Restore return pc relative to callers' sp.
1549 __ ld(return_pc, ((int)framesize) + _abi(lr), R1_SP);
1550 }
1551
1552 if (method_needs_polling) {
1553 if (LoadPollAddressFromThread) {
1554 // TODO: PPC port __ ld(polling_page, in_bytes(JavaThread::poll_address_offset()), R16_thread);
1555 Unimplemented();
1556 } else {
1557 __ load_const_optimized(polling_page, (long)(address) os::get_polling_page()); // TODO: PPC port: get_standard_polling_page()
1558 }
1559 }
1560
1561 if (!method_is_frameless) {
1562 // Move return pc to LR.
1563 __ mtlr(return_pc);
1564 // Pop frame (fixed frame-size).
1565 __ addi(R1_SP, R1_SP, (int)framesize);
1566 }
1567
1568 if (method_needs_polling) {
1569 // We need to mark the code position where the load from the safepoint
1570 // polling page was emitted as relocInfo::poll_return_type here.
1571 __ relocate(relocInfo::poll_return_type);
1572 __ load_from_polling_page(polling_page);
1573 }
1574 }
1575
1576 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1577 // Variable size. Determine dynamically.
1578 return MachNode::size(ra_);
1579 }
1580
1581 int MachEpilogNode::reloc() const {
1582 // Return number of relocatable values contained in this instruction.
1583 return 1; // 1 for load_from_polling_page.
1584 }
1585
1586 const Pipeline * MachEpilogNode::pipeline() const {
1587 return MachNode::pipeline_class();
1588 }
1589
1590 // This method seems to be obsolete. It is declared in machnode.hpp
1591 // and defined in all *.ad files, but it is never called. Should we
1592 // get rid of it?
1593 int MachEpilogNode::safepoint_offset() const {
1594 assert(do_polling(), "no return for this epilog node");
1595 return 0;
1596 }
1597
1598 #if 0 // TODO: PPC port
1599 void MachLoadPollAddrLateNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1600 MacroAssembler _masm(&cbuf);
1601 if (LoadPollAddressFromThread) {
1602 _masm.ld(R11, in_bytes(JavaThread::poll_address_offset()), R16_thread);
1603 } else {
1604 _masm.nop();
1605 }
1606 }
1607
1608 uint MachLoadPollAddrLateNode::size(PhaseRegAlloc* ra_) const {
1609 if (LoadPollAddressFromThread) {
1610 return 4;
1611 } else {
1612 return 4;
1613 }
1614 }
1615
1616 #ifndef PRODUCT
1617 void MachLoadPollAddrLateNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1618 st->print_cr(" LD R11, PollAddressOffset, R16_thread \t// LoadPollAddressFromThread");
1619 }
1620 #endif
1621
1622 const RegMask &MachLoadPollAddrLateNode::out_RegMask() const {
1623 return RSCRATCH1_BITS64_REG_mask();
1624 }
1625 #endif // PPC port
1626
1627 // =============================================================================
1628
1629 // Figure out which register class each belongs in: rc_int, rc_float or
1630 // rc_stack.
1631 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1632
1633 static enum RC rc_class(OptoReg::Name reg) {
1634 // Return the register class for the given register. The given register
1635 // reg is a <register>_num value, which is an index into the MachRegisterNumbers
1636 // enumeration in adGlobals_ppc64.hpp.
1637
1638 if (reg == OptoReg::Bad) return rc_bad;
1639
1640 // We have 64 integer register halves, starting at index 0.
1641 if (reg < 64) return rc_int;
1642
1643 // We have 64 floating-point register halves, starting at index 64.
1644 if (reg < 64+64) return rc_float;
1645
1646 // Between float regs & stack are the flags regs.
1647 assert(OptoReg::is_stack(reg), "blow up if spilling flags");
1648
1649 return rc_stack;
1650 }
1651
1652 static int ld_st_helper(CodeBuffer *cbuf, const char *op_str, uint opcode, int reg, int offset,
1653 bool do_print, Compile* C, outputStream *st) {
1654
1655 assert(opcode == Assembler::LD_OPCODE ||
1656 opcode == Assembler::STD_OPCODE ||
1657 opcode == Assembler::LWZ_OPCODE ||
1658 opcode == Assembler::STW_OPCODE ||
1659 opcode == Assembler::LFD_OPCODE ||
1660 opcode == Assembler::STFD_OPCODE ||
1661 opcode == Assembler::LFS_OPCODE ||
1662 opcode == Assembler::STFS_OPCODE,
1663 "opcode not supported");
1664
1665 if (cbuf) {
1666 int d =
1667 (Assembler::LD_OPCODE == opcode || Assembler::STD_OPCODE == opcode) ?
1668 Assembler::ds(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/)
1669 : Assembler::d1(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/); // Makes no difference in opt build.
1670 emit_long(*cbuf, opcode | Assembler::rt(Matcher::_regEncode[reg]) | d | Assembler::ra(R1_SP));
1671 }
1672 #ifndef PRODUCT
1673 else if (do_print) {
1674 st->print("%-7s %s, [R1_SP + #%d+%d] \t// spill copy",
1675 op_str,
1676 Matcher::regName[reg],
1677 offset, 0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/);
1678 }
1679 #endif
1680 return 4; // size
1681 }
1682
1683 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream *st) const {
1684 Compile* C = ra_->C;
1685
1686 // Get registers to move.
1687 OptoReg::Name src_hi = ra_->get_reg_second(in(1));
1688 OptoReg::Name src_lo = ra_->get_reg_first(in(1));
1689 OptoReg::Name dst_hi = ra_->get_reg_second(this);
1690 OptoReg::Name dst_lo = ra_->get_reg_first(this);
1691
1692 enum RC src_hi_rc = rc_class(src_hi);
1693 enum RC src_lo_rc = rc_class(src_lo);
1694 enum RC dst_hi_rc = rc_class(dst_hi);
1695 enum RC dst_lo_rc = rc_class(dst_lo);
1696
1697 assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
1698 if (src_hi != OptoReg::Bad)
1699 assert((src_lo&1)==0 && src_lo+1==src_hi &&
1700 (dst_lo&1)==0 && dst_lo+1==dst_hi,
1701 "expected aligned-adjacent pairs");
1702 // Generate spill code!
1703 int size = 0;
1704
1705 if (src_lo == dst_lo && src_hi == dst_hi)
1706 return size; // Self copy, no move.
1707
1708 // --------------------------------------
1709 // Memory->Memory Spill. Use R0 to hold the value.
1710 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1711 int src_offset = ra_->reg2offset(src_lo);
1712 int dst_offset = ra_->reg2offset(dst_lo);
1713 if (src_hi != OptoReg::Bad) {
1714 assert(src_hi_rc==rc_stack && dst_hi_rc==rc_stack,
1715 "expected same type of move for high parts");
1716 size += ld_st_helper(cbuf, "LD ", Assembler::LD_OPCODE, R0_num, src_offset, !do_size, C, st);
1717 if (!cbuf && !do_size) st->print("\n\t");
1718 size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, R0_num, dst_offset, !do_size, C, st);
1719 } else {
1720 size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, R0_num, src_offset, !do_size, C, st);
1721 if (!cbuf && !do_size) st->print("\n\t");
1722 size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, R0_num, dst_offset, !do_size, C, st);
1723 }
1724 return size;
1725 }
1726
1727 // --------------------------------------
1728 // Check for float->int copy; requires a trip through memory.
1729 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
1730 Unimplemented();
1731 }
1732
1733 // --------------------------------------
1734 // Check for integer reg-reg copy.
1735 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
1736 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
1737 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
1738 size = (Rsrc != Rdst) ? 4 : 0;
1739
1740 if (cbuf) {
1741 MacroAssembler _masm(cbuf);
1742 if (size) {
1743 __ mr(Rdst, Rsrc);
1744 }
1745 }
1746 #ifndef PRODUCT
1747 else if (!do_size) {
1748 if (size) {
1749 st->print("%-7s %s, %s \t// spill copy", "MR", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1750 } else {
1751 st->print("%-7s %s, %s \t// spill copy", "MR-NOP", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1752 }
1753 }
1754 #endif
1755 return size;
1756 }
1757
1758 // Check for integer store.
1759 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
1760 int dst_offset = ra_->reg2offset(dst_lo);
1761 if (src_hi != OptoReg::Bad) {
1762 assert(src_hi_rc==rc_int && dst_hi_rc==rc_stack,
1763 "expected same type of move for high parts");
1764 size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, src_lo, dst_offset, !do_size, C, st);
1765 } else {
1766 size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, src_lo, dst_offset, !do_size, C, st);
1767 }
1768 return size;
1769 }
1770
1771 // Check for integer load.
1772 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
1773 int src_offset = ra_->reg2offset(src_lo);
1774 if (src_hi != OptoReg::Bad) {
1775 assert(dst_hi_rc==rc_int && src_hi_rc==rc_stack,
1776 "expected same type of move for high parts");
1777 size += ld_st_helper(cbuf, "LD ", Assembler::LD_OPCODE, dst_lo, src_offset, !do_size, C, st);
1778 } else {
1779 size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, dst_lo, src_offset, !do_size, C, st);
1780 }
1781 return size;
1782 }
1783
1784 // Check for float reg-reg copy.
1785 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
1786 if (cbuf) {
1787 MacroAssembler _masm(cbuf);
1788 FloatRegister Rsrc = as_FloatRegister(Matcher::_regEncode[src_lo]);
1789 FloatRegister Rdst = as_FloatRegister(Matcher::_regEncode[dst_lo]);
1790 __ fmr(Rdst, Rsrc);
1791 }
1792 #ifndef PRODUCT
1793 else if (!do_size) {
1794 st->print("%-7s %s, %s \t// spill copy", "FMR", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1795 }
1796 #endif
1797 return 4;
1798 }
1799
1800 // Check for float store.
1801 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
1802 int dst_offset = ra_->reg2offset(dst_lo);
1803 if (src_hi != OptoReg::Bad) {
1804 assert(src_hi_rc==rc_float && dst_hi_rc==rc_stack,
1805 "expected same type of move for high parts");
1806 size += ld_st_helper(cbuf, "STFD", Assembler::STFD_OPCODE, src_lo, dst_offset, !do_size, C, st);
1807 } else {
1808 size += ld_st_helper(cbuf, "STFS", Assembler::STFS_OPCODE, src_lo, dst_offset, !do_size, C, st);
1809 }
1810 return size;
1811 }
1812
1813 // Check for float load.
1814 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
1815 int src_offset = ra_->reg2offset(src_lo);
1816 if (src_hi != OptoReg::Bad) {
1817 assert(dst_hi_rc==rc_float && src_hi_rc==rc_stack,
1818 "expected same type of move for high parts");
1819 size += ld_st_helper(cbuf, "LFD ", Assembler::LFD_OPCODE, dst_lo, src_offset, !do_size, C, st);
1820 } else {
1821 size += ld_st_helper(cbuf, "LFS ", Assembler::LFS_OPCODE, dst_lo, src_offset, !do_size, C, st);
1822 }
1823 return size;
1824 }
1825
1826 // --------------------------------------------------------------------
1827 // Check for hi bits still needing moving. Only happens for misaligned
1828 // arguments to native calls.
1829 if (src_hi == dst_hi)
1830 return size; // Self copy; no move.
1831
1832 assert(src_hi_rc != rc_bad && dst_hi_rc != rc_bad, "src_hi & dst_hi cannot be Bad");
1833 ShouldNotReachHere(); // Unimplemented
1834 return 0;
1835 }
1836
1837 #ifndef PRODUCT
1838 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1839 if (!ra_)
1840 st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx);
1841 else
1842 implementation(NULL, ra_, false, st);
1843 }
1844 #endif
1845
1846 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1847 implementation(&cbuf, ra_, false, NULL);
1848 }
1849
1850 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1851 return implementation(NULL, ra_, true, NULL);
1852 }
1853
1854 #if 0 // TODO: PPC port
1855 ArchOpcode MachSpillCopyNode_archOpcode(MachSpillCopyNode *n, PhaseRegAlloc *ra_) {
1856 #ifndef PRODUCT
1857 if (ra_->node_regs_max_index() == 0) return archOpcode_undefined;
1858 #endif
1859 assert(ra_->node_regs_max_index() != 0, "");
1860
1861 // Get registers to move.
1862 OptoReg::Name src_hi = ra_->get_reg_second(n->in(1));
1863 OptoReg::Name src_lo = ra_->get_reg_first(n->in(1));
1864 OptoReg::Name dst_hi = ra_->get_reg_second(n);
1865 OptoReg::Name dst_lo = ra_->get_reg_first(n);
1866
1867 enum RC src_lo_rc = rc_class(src_lo);
1868 enum RC dst_lo_rc = rc_class(dst_lo);
1869
1870 if (src_lo == dst_lo && src_hi == dst_hi)
1871 return ppc64Opcode_none; // Self copy, no move.
1872
1873 // --------------------------------------
1874 // Memory->Memory Spill. Use R0 to hold the value.
1875 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1876 return ppc64Opcode_compound;
1877 }
1878
1879 // --------------------------------------
1880 // Check for float->int copy; requires a trip through memory.
1881 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
1882 Unimplemented();
1883 }
1884
1885 // --------------------------------------
1886 // Check for integer reg-reg copy.
1887 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
1888 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
1889 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
1890 if (Rsrc == Rdst) {
1891 return ppc64Opcode_none;
1892 } else {
1893 return ppc64Opcode_or;
1894 }
1895 }
1896
1897 // Check for integer store.
1898 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
1899 if (src_hi != OptoReg::Bad) {
1900 return ppc64Opcode_std;
1901 } else {
1902 return ppc64Opcode_stw;
1903 }
1904 }
1905
1906 // Check for integer load.
1907 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
1908 if (src_hi != OptoReg::Bad) {
1909 return ppc64Opcode_ld;
1910 } else {
1911 return ppc64Opcode_lwz;
1912 }
1913 }
1914
1915 // Check for float reg-reg copy.
1916 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
1917 return ppc64Opcode_fmr;
1918 }
1919
1920 // Check for float store.
1921 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
1922 if (src_hi != OptoReg::Bad) {
1923 return ppc64Opcode_stfd;
1924 } else {
1925 return ppc64Opcode_stfs;
1926 }
1927 }
1928
1929 // Check for float load.
1930 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
1931 if (src_hi != OptoReg::Bad) {
1932 return ppc64Opcode_lfd;
1933 } else {
1934 return ppc64Opcode_lfs;
1935 }
1936 }
1937
1938 // --------------------------------------------------------------------
1939 // Check for hi bits still needing moving. Only happens for misaligned
1940 // arguments to native calls.
1941 if (src_hi == dst_hi) {
1942 return ppc64Opcode_none; // Self copy; no move.
1943 }
1944
1945 ShouldNotReachHere();
1946 return ppc64Opcode_undefined;
1947 }
1948 #endif // PPC port
1949
1950 #ifndef PRODUCT
1951 void MachNopNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1952 st->print("NOP \t// %d nops to pad for loops.", _count);
1953 }
1954 #endif
1955
1956 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *) const {
1957 MacroAssembler _masm(&cbuf);
1958 // _count contains the number of nops needed for padding.
1959 for (int i = 0; i < _count; i++) {
1960 __ nop();
1961 }
1962 }
1963
1964 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1965 return _count * 4;
1966 }
1967
1968 #ifndef PRODUCT
1969 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1970 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1971 char reg_str[128];
1972 ra_->dump_register(this, reg_str);
1973 st->print("ADDI %s, SP, %d \t// box node", reg_str, offset);
1974 }
1975 #endif
1976
1977 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1978 MacroAssembler _masm(&cbuf);
1979
1980 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1981 int reg = ra_->get_encode(this);
1982
1983 if (Assembler::is_simm(offset, 16)) {
1984 __ addi(as_Register(reg), R1, offset);
1985 } else {
1986 ShouldNotReachHere();
1987 }
1988 }
1989
1990 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1991 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_).
1992 return 4;
1993 }
1994
1995 #ifndef PRODUCT
1996 void MachUEPNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1997 st->print_cr("---- MachUEPNode ----");
1998 st->print_cr("...");
1999 }
2000 #endif
2001
2002 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
2003 // This is the unverified entry point.
2004 MacroAssembler _masm(&cbuf);
2005
2006 // Inline_cache contains a klass.
2007 Register ic_klass = as_Register(Matcher::inline_cache_reg_encode());
2008 Register receiver_klass = R12_scratch2; // tmp
2009
2010 assert_different_registers(ic_klass, receiver_klass, R11_scratch1, R3_ARG1);
2011 assert(R11_scratch1 == R11, "need prologue scratch register");
2012
2013 // Check for NULL argument if we don't have implicit null checks.
2014 if (!ImplicitNullChecks || !os::zero_page_read_protected()) {
2015 if (TrapBasedNullChecks) {
2016 __ trap_null_check(R3_ARG1);
2017 } else {
2018 Label valid;
2019 __ cmpdi(CCR0, R3_ARG1, 0);
2020 __ bne_predict_taken(CCR0, valid);
2021 // We have a null argument, branch to ic_miss_stub.
2022 __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(),
2023 relocInfo::runtime_call_type);
2024 __ bind(valid);
2025 }
2026 }
2027 // Assume argument is not NULL, load klass from receiver.
2028 __ load_klass(receiver_klass, R3_ARG1);
2029
2030 if (TrapBasedICMissChecks) {
2031 __ trap_ic_miss_check(receiver_klass, ic_klass);
2032 } else {
2033 Label valid;
2034 __ cmpd(CCR0, receiver_klass, ic_klass);
2035 __ beq_predict_taken(CCR0, valid);
2036 // We have an unexpected klass, branch to ic_miss_stub.
2037 __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(),
2038 relocInfo::runtime_call_type);
2039 __ bind(valid);
2040 }
2041
2042 // Argument is valid and klass is as expected, continue.
2043 }
2044
2045 #if 0 // TODO: PPC port
2046 // Optimize UEP code on z (save a load_const() call in main path).
2047 int MachUEPNode::ep_offset() {
2048 return 0;
2049 }
2050 #endif
2051
2052 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
2053 // Variable size. Determine dynamically.
2054 return MachNode::size(ra_);
2055 }
2056
2057 //=============================================================================
2058
2059 %} // interrupt source
2060
2061 source_hpp %{ // Header information of the source block.
2062
2063 class HandlerImpl {
2064
2065 public:
2066
2067 static int emit_exception_handler(CodeBuffer &cbuf);
2068 static int emit_deopt_handler(CodeBuffer& cbuf);
2069
2070 static uint size_exception_handler() {
2071 // The exception_handler is a b64_patchable.
2072 return MacroAssembler::b64_patchable_size;
2073 }
2074
2075 static uint size_deopt_handler() {
2076 // The deopt_handler is a bl64_patchable.
2077 return MacroAssembler::bl64_patchable_size;
2078 }
2079
2080 };
2081
2082 %} // end source_hpp
2083
2084 source %{
2085
2086 int HandlerImpl::emit_exception_handler(CodeBuffer &cbuf) {
2087 MacroAssembler _masm(&cbuf);
2088
2089 address base = __ start_a_stub(size_exception_handler());
2090 if (base == NULL) return 0; // CodeBuffer::expand failed
2091
2092 int offset = __ offset();
2093 __ b64_patchable((address)OptoRuntime::exception_blob()->content_begin(),
2094 relocInfo::runtime_call_type);
2095 assert(__ offset() - offset == (int)size_exception_handler(), "must be fixed size");
2096 __ end_a_stub();
2097
2098 return offset;
2099 }
2100
2101 // The deopt_handler is like the exception handler, but it calls to
2102 // the deoptimization blob instead of jumping to the exception blob.
2103 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) {
2104 MacroAssembler _masm(&cbuf);
2105
2106 address base = __ start_a_stub(size_deopt_handler());
2107 if (base == NULL) return 0; // CodeBuffer::expand failed
2108
2109 int offset = __ offset();
2110 __ bl64_patchable((address)SharedRuntime::deopt_blob()->unpack(),
2111 relocInfo::runtime_call_type);
2112 assert(__ offset() - offset == (int) size_deopt_handler(), "must be fixed size");
2113 __ end_a_stub();
2114
2115 return offset;
2116 }
2117
2118 //=============================================================================
2119
2120 // Use a frame slots bias for frameless methods if accessing the stack.
2121 static int frame_slots_bias(int reg_enc, PhaseRegAlloc* ra_) {
2122 if (as_Register(reg_enc) == R1_SP) {
2123 return 0; // TODO: PPC port ra_->C->frame_slots_sp_bias_in_bytes();
2124 }
2125 return 0;
2126 }
2127
2128 const bool Matcher::match_rule_supported(int opcode) {
2129 if (!has_match_rule(opcode))
2130 return false;
2131
2132 switch (opcode) {
2133 case Op_SqrtD:
2134 return VM_Version::has_fsqrt();
2135 case Op_CountLeadingZerosI:
2136 case Op_CountLeadingZerosL:
2137 case Op_CountTrailingZerosI:
2138 case Op_CountTrailingZerosL:
2139 if (!UseCountLeadingZerosInstructionsPPC64)
2140 return false;
2141 break;
2142
2143 case Op_PopCountI:
2144 case Op_PopCountL:
2145 return (UsePopCountInstruction && VM_Version::has_popcntw());
2146
2147 case Op_StrComp:
2148 return SpecialStringCompareTo;
2149 case Op_StrEquals:
2150 return SpecialStringEquals;
2151 case Op_StrIndexOf:
2152 return SpecialStringIndexOf;
2153 }
2154
2155 return true; // Per default match rules are supported.
2156 }
2157
2158 int Matcher::regnum_to_fpu_offset(int regnum) {
2159 // No user for this method?
2160 Unimplemented();
2161 return 999;
2162 }
2163
2164 const bool Matcher::convL2FSupported(void) {
2165 // fcfids can do the conversion (>= Power7).
2166 // fcfid + frsp showed rounding problem when result should be 0x3f800001.
2167 return VM_Version::has_fcfids(); // False means that conversion is done by runtime call.
2168 }
2169
2170 // Vector width in bytes.
2171 const int Matcher::vector_width_in_bytes(BasicType bt) {
2172 assert(MaxVectorSize == 8, "");
2173 return 8;
2174 }
2175
2176 // Vector ideal reg.
2177 const int Matcher::vector_ideal_reg(int size) {
2178 assert(MaxVectorSize == 8 && size == 8, "");
2179 return Op_RegL;
2180 }
2181
2182 const int Matcher::vector_shift_count_ideal_reg(int size) {
2183 fatal("vector shift is not supported");
2184 return Node::NotAMachineReg;
2185 }
2186
2187 // Limits on vector size (number of elements) loaded into vector.
2188 const int Matcher::max_vector_size(const BasicType bt) {
2189 assert(is_java_primitive(bt), "only primitive type vectors");
2190 return vector_width_in_bytes(bt)/type2aelembytes(bt);
2191 }
2192
2193 const int Matcher::min_vector_size(const BasicType bt) {
2194 return max_vector_size(bt); // Same as max.
2195 }
2196
2197 // PPC doesn't support misaligned vectors store/load.
2198 const bool Matcher::misaligned_vectors_ok() {
2199 return false;
2200 }
2201
2202 // PPC AES support not yet implemented
2203 const bool Matcher::pass_original_key_for_aes() {
2204 return false;
2205 }
2206
2207 // RETURNS: whether this branch offset is short enough that a short
2208 // branch can be used.
2209 //
2210 // If the platform does not provide any short branch variants, then
2211 // this method should return `false' for offset 0.
2212 //
2213 // `Compile::Fill_buffer' will decide on basis of this information
2214 // whether to do the pass `Compile::Shorten_branches' at all.
2215 //
2216 // And `Compile::Shorten_branches' will decide on basis of this
2217 // information whether to replace particular branch sites by short
2218 // ones.
2219 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
2220 // Is the offset within the range of a ppc64 pc relative branch?
2221 bool b;
2222
2223 const int safety_zone = 3 * BytesPerInstWord;
2224 b = Assembler::is_simm((offset<0 ? offset-safety_zone : offset+safety_zone),
2225 29 - 16 + 1 + 2);
2226 return b;
2227 }
2228
2229 const bool Matcher::isSimpleConstant64(jlong value) {
2230 // Probably always true, even if a temp register is required.
2231 return true;
2232 }
2233 /* TODO: PPC port
2234 // Make a new machine dependent decode node (with its operands).
2235 MachTypeNode *Matcher::make_decode_node(Compile *C) {
2236 assert(Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0,
2237 "This method is only implemented for unscaled cOops mode so far");
2238 MachTypeNode *decode = new (C) decodeN_unscaledNode();
2239 decode->set_opnd_array(0, new (C) iRegPdstOper());
2240 decode->set_opnd_array(1, new (C) iRegNsrcOper());
2241 return decode;
2242 }
2243 */
2244 // Threshold size for cleararray.
2245 const int Matcher::init_array_short_size = 8 * BytesPerLong;
2246
2247 // false => size gets scaled to BytesPerLong, ok.
2248 const bool Matcher::init_array_count_is_in_bytes = false;
2249
2250 // Use conditional move (CMOVL) on Power7.
2251 const int Matcher::long_cmove_cost() { return 0; } // this only makes long cmoves more expensive than int cmoves
2252
2253 // Suppress CMOVF. Conditional move available (sort of) on PPC64 only from P7 onwards. Not exploited yet.
2254 // fsel doesn't accept a condition register as input, so this would be slightly different.
2255 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
2256
2257 // Power6 requires postalloc expand (see block.cpp for description of postalloc expand).
2258 const bool Matcher::require_postalloc_expand = true;
2259
2260 // Should the Matcher clone shifts on addressing modes, expecting them to
2261 // be subsumed into complex addressing expressions or compute them into
2262 // registers? True for Intel but false for most RISCs.
2263 const bool Matcher::clone_shift_expressions = false;
2264
2265 // Do we need to mask the count passed to shift instructions or does
2266 // the cpu only look at the lower 5/6 bits anyway?
2267 // PowerPC requires masked shift counts.
2268 const bool Matcher::need_masked_shift_count = true;
2269
2270 // This affects two different things:
2271 // - how Decode nodes are matched
2272 // - how ImplicitNullCheck opportunities are recognized
2273 // If true, the matcher will try to remove all Decodes and match them
2274 // (as operands) into nodes. NullChecks are not prepared to deal with
2275 // Decodes by final_graph_reshaping().
2276 // If false, final_graph_reshaping() forces the decode behind the Cmp
2277 // for a NullCheck. The matcher matches the Decode node into a register.
2278 // Implicit_null_check optimization moves the Decode along with the
2279 // memory operation back up before the NullCheck.
2280 bool Matcher::narrow_oop_use_complex_address() {
2281 // TODO: PPC port if (MatchDecodeNodes) return true;
2282 return false;
2283 }
2284
2285 bool Matcher::narrow_klass_use_complex_address() {
2286 NOT_LP64(ShouldNotCallThis());
2287 assert(UseCompressedClassPointers, "only for compressed klass code");
2288 // TODO: PPC port if (MatchDecodeNodes) return true;
2289 return false;
2290 }
2291
2292 // Is it better to copy float constants, or load them directly from memory?
2293 // Intel can load a float constant from a direct address, requiring no
2294 // extra registers. Most RISCs will have to materialize an address into a
2295 // register first, so they would do better to copy the constant from stack.
2296 const bool Matcher::rematerialize_float_constants = false;
2297
2298 // If CPU can load and store mis-aligned doubles directly then no fixup is
2299 // needed. Else we split the double into 2 integer pieces and move it
2300 // piece-by-piece. Only happens when passing doubles into C code as the
2301 // Java calling convention forces doubles to be aligned.
2302 const bool Matcher::misaligned_doubles_ok = true;
2303
2304 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
2305 Unimplemented();
2306 }
2307
2308 // Advertise here if the CPU requires explicit rounding operations
2309 // to implement the UseStrictFP mode.
2310 const bool Matcher::strict_fp_requires_explicit_rounding = false;
2311
2312 // Do floats take an entire double register or just half?
2313 //
2314 // A float occupies a ppc64 double register. For the allocator, a
2315 // ppc64 double register appears as a pair of float registers.
2316 bool Matcher::float_in_double() { return true; }
2317
2318 // Do ints take an entire long register or just half?
2319 // The relevant question is how the int is callee-saved:
2320 // the whole long is written but de-opt'ing will have to extract
2321 // the relevant 32 bits.
2322 const bool Matcher::int_in_long = true;
2323
2324 // Constants for c2c and c calling conventions.
2325
2326 const MachRegisterNumbers iarg_reg[8] = {
2327 R3_num, R4_num, R5_num, R6_num,
2328 R7_num, R8_num, R9_num, R10_num
2329 };
2330
2331 const MachRegisterNumbers farg_reg[13] = {
2332 F1_num, F2_num, F3_num, F4_num,
2333 F5_num, F6_num, F7_num, F8_num,
2334 F9_num, F10_num, F11_num, F12_num,
2335 F13_num
2336 };
2337
2338 const int num_iarg_registers = sizeof(iarg_reg) / sizeof(iarg_reg[0]);
2339
2340 const int num_farg_registers = sizeof(farg_reg) / sizeof(farg_reg[0]);
2341
2342 // Return whether or not this register is ever used as an argument. This
2343 // function is used on startup to build the trampoline stubs in generateOptoStub.
2344 // Registers not mentioned will be killed by the VM call in the trampoline, and
2345 // arguments in those registers not be available to the callee.
2346 bool Matcher::can_be_java_arg(int reg) {
2347 // We return true for all registers contained in iarg_reg[] and
2348 // farg_reg[] and their virtual halves.
2349 // We must include the virtual halves in order to get STDs and LDs
2350 // instead of STWs and LWs in the trampoline stubs.
2351
2352 if ( reg == R3_num || reg == R3_H_num
2353 || reg == R4_num || reg == R4_H_num
2354 || reg == R5_num || reg == R5_H_num
2355 || reg == R6_num || reg == R6_H_num
2356 || reg == R7_num || reg == R7_H_num
2357 || reg == R8_num || reg == R8_H_num
2358 || reg == R9_num || reg == R9_H_num
2359 || reg == R10_num || reg == R10_H_num)
2360 return true;
2361
2362 if ( reg == F1_num || reg == F1_H_num
2363 || reg == F2_num || reg == F2_H_num
2364 || reg == F3_num || reg == F3_H_num
2365 || reg == F4_num || reg == F4_H_num
2366 || reg == F5_num || reg == F5_H_num
2367 || reg == F6_num || reg == F6_H_num
2368 || reg == F7_num || reg == F7_H_num
2369 || reg == F8_num || reg == F8_H_num
2370 || reg == F9_num || reg == F9_H_num
2371 || reg == F10_num || reg == F10_H_num
2372 || reg == F11_num || reg == F11_H_num
2373 || reg == F12_num || reg == F12_H_num
2374 || reg == F13_num || reg == F13_H_num)
2375 return true;
2376
2377 return false;
2378 }
2379
2380 bool Matcher::is_spillable_arg(int reg) {
2381 return can_be_java_arg(reg);
2382 }
2383
2384 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) {
2385 return false;
2386 }
2387
2388 // Register for DIVI projection of divmodI.
2389 RegMask Matcher::divI_proj_mask() {
2390 ShouldNotReachHere();
2391 return RegMask();
2392 }
2393
2394 // Register for MODI projection of divmodI.
2395 RegMask Matcher::modI_proj_mask() {
2396 ShouldNotReachHere();
2397 return RegMask();
2398 }
2399
2400 // Register for DIVL projection of divmodL.
2401 RegMask Matcher::divL_proj_mask() {
2402 ShouldNotReachHere();
2403 return RegMask();
2404 }
2405
2406 // Register for MODL projection of divmodL.
2407 RegMask Matcher::modL_proj_mask() {
2408 ShouldNotReachHere();
2409 return RegMask();
2410 }
2411
2412 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2413 return RegMask();
2414 }
2415
2416 %}
2417
2418 //----------ENCODING BLOCK-----------------------------------------------------
2419 // This block specifies the encoding classes used by the compiler to output
2420 // byte streams. Encoding classes are parameterized macros used by
2421 // Machine Instruction Nodes in order to generate the bit encoding of the
2422 // instruction. Operands specify their base encoding interface with the
2423 // interface keyword. There are currently supported four interfaces,
2424 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
2425 // operand to generate a function which returns its register number when
2426 // queried. CONST_INTER causes an operand to generate a function which
2427 // returns the value of the constant when queried. MEMORY_INTER causes an
2428 // operand to generate four functions which return the Base Register, the
2429 // Index Register, the Scale Value, and the Offset Value of the operand when
2430 // queried. COND_INTER causes an operand to generate six functions which
2431 // return the encoding code (ie - encoding bits for the instruction)
2432 // associated with each basic boolean condition for a conditional instruction.
2433 //
2434 // Instructions specify two basic values for encoding. Again, a function
2435 // is available to check if the constant displacement is an oop. They use the
2436 // ins_encode keyword to specify their encoding classes (which must be
2437 // a sequence of enc_class names, and their parameters, specified in
2438 // the encoding block), and they use the
2439 // opcode keyword to specify, in order, their primary, secondary, and
2440 // tertiary opcode. Only the opcode sections which a particular instruction
2441 // needs for encoding need to be specified.
2442 encode %{
2443 enc_class enc_unimplemented %{
2444 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2445 MacroAssembler _masm(&cbuf);
2446 __ unimplemented("Unimplemented mach node encoding in AD file.", 13);
2447 %}
2448
2449 enc_class enc_untested %{
2450 #ifdef ASSERT
2451 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2452 MacroAssembler _masm(&cbuf);
2453 __ untested("Untested mach node encoding in AD file.");
2454 #else
2455 // TODO: PPC port $archOpcode(ppc64Opcode_none);
2456 #endif
2457 %}
2458
2459 enc_class enc_lbz(iRegIdst dst, memory mem) %{
2460 // TODO: PPC port $archOpcode(ppc64Opcode_lbz);
2461 MacroAssembler _masm(&cbuf);
2462 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2463 __ lbz($dst$$Register, Idisp, $mem$$base$$Register);
2464 %}
2465
2466 // Load acquire.
2467 enc_class enc_lbz_ac(iRegIdst dst, memory mem) %{
2468 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2469 MacroAssembler _masm(&cbuf);
2470 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2471 __ lbz($dst$$Register, Idisp, $mem$$base$$Register);
2472 __ twi_0($dst$$Register);
2473 __ isync();
2474 %}
2475
2476 enc_class enc_lhz(iRegIdst dst, memory mem) %{
2477 // TODO: PPC port $archOpcode(ppc64Opcode_lhz);
2478
2479 MacroAssembler _masm(&cbuf);
2480 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2481 __ lhz($dst$$Register, Idisp, $mem$$base$$Register);
2482 %}
2483
2484 // Load acquire.
2485 enc_class enc_lhz_ac(iRegIdst dst, memory mem) %{
2486 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2487
2488 MacroAssembler _masm(&cbuf);
2489 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2490 __ lhz($dst$$Register, Idisp, $mem$$base$$Register);
2491 __ twi_0($dst$$Register);
2492 __ isync();
2493 %}
2494
2495 enc_class enc_lwz(iRegIdst dst, memory mem) %{
2496 // TODO: PPC port $archOpcode(ppc64Opcode_lwz);
2497
2498 MacroAssembler _masm(&cbuf);
2499 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2500 __ lwz($dst$$Register, Idisp, $mem$$base$$Register);
2501 %}
2502
2503 // Load acquire.
2504 enc_class enc_lwz_ac(iRegIdst dst, memory mem) %{
2505 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2506
2507 MacroAssembler _masm(&cbuf);
2508 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2509 __ lwz($dst$$Register, Idisp, $mem$$base$$Register);
2510 __ twi_0($dst$$Register);
2511 __ isync();
2512 %}
2513
2514 enc_class enc_ld(iRegLdst dst, memoryAlg4 mem) %{
2515 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2516 MacroAssembler _masm(&cbuf);
2517 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2518 // Operand 'ds' requires 4-alignment.
2519 assert((Idisp & 0x3) == 0, "unaligned offset");
2520 __ ld($dst$$Register, Idisp, $mem$$base$$Register);
2521 %}
2522
2523 // Load acquire.
2524 enc_class enc_ld_ac(iRegLdst dst, memoryAlg4 mem) %{
2525 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2526 MacroAssembler _masm(&cbuf);
2527 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2528 // Operand 'ds' requires 4-alignment.
2529 assert((Idisp & 0x3) == 0, "unaligned offset");
2530 __ ld($dst$$Register, Idisp, $mem$$base$$Register);
2531 __ twi_0($dst$$Register);
2532 __ isync();
2533 %}
2534
2535 enc_class enc_lfd(RegF dst, memory mem) %{
2536 // TODO: PPC port $archOpcode(ppc64Opcode_lfd);
2537 MacroAssembler _masm(&cbuf);
2538 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2539 __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register);
2540 %}
2541
2542 enc_class enc_load_long_constL(iRegLdst dst, immL src, iRegLdst toc) %{
2543 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2544
2545 MacroAssembler _masm(&cbuf);
2546 int toc_offset = 0;
2547
2548 if (!ra_->C->in_scratch_emit_size()) {
2549 address const_toc_addr;
2550 // Create a non-oop constant, no relocation needed.
2551 // If it is an IC, it has a virtual_call_Relocation.
2552 const_toc_addr = __ long_constant((jlong)$src$$constant);
2553
2554 // Get the constant's TOC offset.
2555 toc_offset = __ offset_to_method_toc(const_toc_addr);
2556
2557 // Keep the current instruction offset in mind.
2558 ((loadConLNode*)this)->_cbuf_insts_offset = __ offset();
2559 }
2560
2561 __ ld($dst$$Register, toc_offset, $toc$$Register);
2562 %}
2563
2564 enc_class enc_load_long_constL_hi(iRegLdst dst, iRegLdst toc, immL src) %{
2565 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
2566
2567 MacroAssembler _masm(&cbuf);
2568
2569 if (!ra_->C->in_scratch_emit_size()) {
2570 address const_toc_addr;
2571 // Create a non-oop constant, no relocation needed.
2572 // If it is an IC, it has a virtual_call_Relocation.
2573 const_toc_addr = __ long_constant((jlong)$src$$constant);
2574
2575 // Get the constant's TOC offset.
2576 const int toc_offset = __ offset_to_method_toc(const_toc_addr);
2577 // Store the toc offset of the constant.
2578 ((loadConL_hiNode*)this)->_const_toc_offset = toc_offset;
2579
2580 // Also keep the current instruction offset in mind.
2581 ((loadConL_hiNode*)this)->_cbuf_insts_offset = __ offset();
2582 }
2583
2584 __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset));
2585 %}
2586
2587 %} // encode
2588
2589 source %{
2590
2591 typedef struct {
2592 loadConL_hiNode *_large_hi;
2593 loadConL_loNode *_large_lo;
2594 loadConLNode *_small;
2595 MachNode *_last;
2596 } loadConLNodesTuple;
2597
2598 loadConLNodesTuple loadConLNodesTuple_create(Compile *C, PhaseRegAlloc *ra_, Node *toc, immLOper *immSrc,
2599 OptoReg::Name reg_second, OptoReg::Name reg_first) {
2600 loadConLNodesTuple nodes;
2601
2602 const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2603 if (large_constant_pool) {
2604 // Create new nodes.
2605 loadConL_hiNode *m1 = new (C) loadConL_hiNode();
2606 loadConL_loNode *m2 = new (C) loadConL_loNode();
2607
2608 // inputs for new nodes
2609 m1->add_req(NULL, toc);
2610 m2->add_req(NULL, m1);
2611
2612 // operands for new nodes
2613 m1->_opnds[0] = new (C) iRegLdstOper(); // dst
2614 m1->_opnds[1] = immSrc; // src
2615 m1->_opnds[2] = new (C) iRegPdstOper(); // toc
2616 m2->_opnds[0] = new (C) iRegLdstOper(); // dst
2617 m2->_opnds[1] = immSrc; // src
2618 m2->_opnds[2] = new (C) iRegLdstOper(); // base
2619
2620 // Initialize ins_attrib TOC fields.
2621 m1->_const_toc_offset = -1;
2622 m2->_const_toc_offset_hi_node = m1;
2623
2624 // Initialize ins_attrib instruction offset.
2625 m1->_cbuf_insts_offset = -1;
2626
2627 // register allocation for new nodes
2628 ra_->set_pair(m1->_idx, reg_second, reg_first);
2629 ra_->set_pair(m2->_idx, reg_second, reg_first);
2630
2631 // Create result.
2632 nodes._large_hi = m1;
2633 nodes._large_lo = m2;
2634 nodes._small = NULL;
2635 nodes._last = nodes._large_lo;
2636 assert(m2->bottom_type()->isa_long(), "must be long");
2637 } else {
2638 loadConLNode *m2 = new (C) loadConLNode();
2639
2640 // inputs for new nodes
2641 m2->add_req(NULL, toc);
2642
2643 // operands for new nodes
2644 m2->_opnds[0] = new (C) iRegLdstOper(); // dst
2645 m2->_opnds[1] = immSrc; // src
2646 m2->_opnds[2] = new (C) iRegPdstOper(); // toc
2647
2648 // Initialize ins_attrib instruction offset.
2649 m2->_cbuf_insts_offset = -1;
2650
2651 // register allocation for new nodes
2652 ra_->set_pair(m2->_idx, reg_second, reg_first);
2653
2654 // Create result.
2655 nodes._large_hi = NULL;
2656 nodes._large_lo = NULL;
2657 nodes._small = m2;
2658 nodes._last = nodes._small;
2659 assert(m2->bottom_type()->isa_long(), "must be long");
2660 }
2661
2662 return nodes;
2663 }
2664
2665 %} // source
2666
2667 encode %{
2668 // Postalloc expand emitter for loading a long constant from the method's TOC.
2669 // Enc_class needed as consttanttablebase is not supported by postalloc
2670 // expand.
2671 enc_class postalloc_expand_load_long_constant(iRegLdst dst, immL src, iRegLdst toc) %{
2672 // Create new nodes.
2673 loadConLNodesTuple loadConLNodes =
2674 loadConLNodesTuple_create(C, ra_, n_toc, op_src,
2675 ra_->get_reg_second(this), ra_->get_reg_first(this));
2676
2677 // Push new nodes.
2678 if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi);
2679 if (loadConLNodes._last) nodes->push(loadConLNodes._last);
2680
2681 // some asserts
2682 assert(nodes->length() >= 1, "must have created at least 1 node");
2683 assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long");
2684 %}
2685
2686 enc_class enc_load_long_constP(iRegLdst dst, immP src, iRegLdst toc) %{
2687 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2688
2689 MacroAssembler _masm(&cbuf);
2690 int toc_offset = 0;
2691
2692 if (!ra_->C->in_scratch_emit_size()) {
2693 intptr_t val = $src$$constant;
2694 relocInfo::relocType constant_reloc = $src->constant_reloc(); // src
2695 address const_toc_addr;
2696 if (constant_reloc == relocInfo::oop_type) {
2697 // Create an oop constant and a corresponding relocation.
2698 AddressLiteral a = __ allocate_oop_address((jobject)val);
2699 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2700 __ relocate(a.rspec());
2701 } else if (constant_reloc == relocInfo::metadata_type) {
2702 AddressLiteral a = __ allocate_metadata_address((Metadata *)val);
2703 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2704 __ relocate(a.rspec());
2705 } else {
2706 // Create a non-oop constant, no relocation needed.
2707 const_toc_addr = __ long_constant((jlong)$src$$constant);
2708 }
2709
2710 // Get the constant's TOC offset.
2711 toc_offset = __ offset_to_method_toc(const_toc_addr);
2712 }
2713
2714 __ ld($dst$$Register, toc_offset, $toc$$Register);
2715 %}
2716
2717 enc_class enc_load_long_constP_hi(iRegLdst dst, immP src, iRegLdst toc) %{
2718 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
2719
2720 MacroAssembler _masm(&cbuf);
2721 if (!ra_->C->in_scratch_emit_size()) {
2722 intptr_t val = $src$$constant;
2723 relocInfo::relocType constant_reloc = $src->constant_reloc(); // src
2724 address const_toc_addr;
2725 if (constant_reloc == relocInfo::oop_type) {
2726 // Create an oop constant and a corresponding relocation.
2727 AddressLiteral a = __ allocate_oop_address((jobject)val);
2728 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2729 __ relocate(a.rspec());
2730 } else if (constant_reloc == relocInfo::metadata_type) {
2731 AddressLiteral a = __ allocate_metadata_address((Metadata *)val);
2732 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2733 __ relocate(a.rspec());
2734 } else { // non-oop pointers, e.g. card mark base, heap top
2735 // Create a non-oop constant, no relocation needed.
2736 const_toc_addr = __ long_constant((jlong)$src$$constant);
2737 }
2738
2739 // Get the constant's TOC offset.
2740 const int toc_offset = __ offset_to_method_toc(const_toc_addr);
2741 // Store the toc offset of the constant.
2742 ((loadConP_hiNode*)this)->_const_toc_offset = toc_offset;
2743 }
2744
2745 __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset));
2746 %}
2747
2748 // Postalloc expand emitter for loading a ptr constant from the method's TOC.
2749 // Enc_class needed as consttanttablebase is not supported by postalloc
2750 // expand.
2751 enc_class postalloc_expand_load_ptr_constant(iRegPdst dst, immP src, iRegLdst toc) %{
2752 const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2753 if (large_constant_pool) {
2754 // Create new nodes.
2755 loadConP_hiNode *m1 = new (C) loadConP_hiNode();
2756 loadConP_loNode *m2 = new (C) loadConP_loNode();
2757
2758 // inputs for new nodes
2759 m1->add_req(NULL, n_toc);
2760 m2->add_req(NULL, m1);
2761
2762 // operands for new nodes
2763 m1->_opnds[0] = new (C) iRegPdstOper(); // dst
2764 m1->_opnds[1] = op_src; // src
2765 m1->_opnds[2] = new (C) iRegPdstOper(); // toc
2766 m2->_opnds[0] = new (C) iRegPdstOper(); // dst
2767 m2->_opnds[1] = op_src; // src
2768 m2->_opnds[2] = new (C) iRegLdstOper(); // base
2769
2770 // Initialize ins_attrib TOC fields.
2771 m1->_const_toc_offset = -1;
2772 m2->_const_toc_offset_hi_node = m1;
2773
2774 // Register allocation for new nodes.
2775 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2776 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2777
2778 nodes->push(m1);
2779 nodes->push(m2);
2780 assert(m2->bottom_type()->isa_ptr(), "must be ptr");
2781 } else {
2782 loadConPNode *m2 = new (C) loadConPNode();
2783
2784 // inputs for new nodes
2785 m2->add_req(NULL, n_toc);
2786
2787 // operands for new nodes
2788 m2->_opnds[0] = new (C) iRegPdstOper(); // dst
2789 m2->_opnds[1] = op_src; // src
2790 m2->_opnds[2] = new (C) iRegPdstOper(); // toc
2791
2792 // Register allocation for new nodes.
2793 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2794
2795 nodes->push(m2);
2796 assert(m2->bottom_type()->isa_ptr(), "must be ptr");
2797 }
2798 %}
2799
2800 // Enc_class needed as consttanttablebase is not supported by postalloc
2801 // expand.
2802 enc_class postalloc_expand_load_float_constant(regF dst, immF src, iRegLdst toc) %{
2803 bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2804
2805 MachNode *m2;
2806 if (large_constant_pool) {
2807 m2 = new (C) loadConFCompNode();
2808 } else {
2809 m2 = new (C) loadConFNode();
2810 }
2811 // inputs for new nodes
2812 m2->add_req(NULL, n_toc);
2813
2814 // operands for new nodes
2815 m2->_opnds[0] = op_dst;
2816 m2->_opnds[1] = op_src;
2817 m2->_opnds[2] = new (C) iRegPdstOper(); // constanttablebase
2818
2819 // register allocation for new nodes
2820 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2821 nodes->push(m2);
2822 %}
2823
2824 // Enc_class needed as consttanttablebase is not supported by postalloc
2825 // expand.
2826 enc_class postalloc_expand_load_double_constant(regD dst, immD src, iRegLdst toc) %{
2827 bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2828
2829 MachNode *m2;
2830 if (large_constant_pool) {
2831 m2 = new (C) loadConDCompNode();
2832 } else {
2833 m2 = new (C) loadConDNode();
2834 }
2835 // inputs for new nodes
2836 m2->add_req(NULL, n_toc);
2837
2838 // operands for new nodes
2839 m2->_opnds[0] = op_dst;
2840 m2->_opnds[1] = op_src;
2841 m2->_opnds[2] = new (C) iRegPdstOper(); // constanttablebase
2842
2843 // register allocation for new nodes
2844 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2845 nodes->push(m2);
2846 %}
2847
2848 enc_class enc_stw(iRegIsrc src, memory mem) %{
2849 // TODO: PPC port $archOpcode(ppc64Opcode_stw);
2850 MacroAssembler _masm(&cbuf);
2851 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2852 __ stw($src$$Register, Idisp, $mem$$base$$Register);
2853 %}
2854
2855 enc_class enc_std(iRegIsrc src, memoryAlg4 mem) %{
2856 // TODO: PPC port $archOpcode(ppc64Opcode_std);
2857 MacroAssembler _masm(&cbuf);
2858 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2859 // Operand 'ds' requires 4-alignment.
2860 assert((Idisp & 0x3) == 0, "unaligned offset");
2861 __ std($src$$Register, Idisp, $mem$$base$$Register);
2862 %}
2863
2864 enc_class enc_stfs(RegF src, memory mem) %{
2865 // TODO: PPC port $archOpcode(ppc64Opcode_stfs);
2866 MacroAssembler _masm(&cbuf);
2867 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2868 __ stfs($src$$FloatRegister, Idisp, $mem$$base$$Register);
2869 %}
2870
2871 enc_class enc_stfd(RegF src, memory mem) %{
2872 // TODO: PPC port $archOpcode(ppc64Opcode_stfd);
2873 MacroAssembler _masm(&cbuf);
2874 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2875 __ stfd($src$$FloatRegister, Idisp, $mem$$base$$Register);
2876 %}
2877
2878 // Use release_store for card-marking to ensure that previous
2879 // oop-stores are visible before the card-mark change.
2880 enc_class enc_cms_card_mark(memory mem, iRegLdst releaseFieldAddr) %{
2881 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2882 // FIXME: Implement this as a cmove and use a fixed condition code
2883 // register which is written on every transition to compiled code,
2884 // e.g. in call-stub and when returning from runtime stubs.
2885 //
2886 // Proposed code sequence for the cmove implementation:
2887 //
2888 // Label skip_release;
2889 // __ beq(CCRfixed, skip_release);
2890 // __ release();
2891 // __ bind(skip_release);
2892 // __ stb(card mark);
2893
2894 MacroAssembler _masm(&cbuf);
2895 Label skip_storestore;
2896
2897 #if 0 // TODO: PPC port
2898 // Check CMSCollectorCardTableModRefBSExt::_requires_release and do the
2899 // StoreStore barrier conditionally.
2900 __ lwz(R0, 0, $releaseFieldAddr$$Register);
2901 __ cmpwi(CCR0, R0, 0);
2902 __ beq_predict_taken(CCR0, skip_storestore);
2903 #endif
2904 __ li(R0, 0);
2905 __ membar(Assembler::StoreStore);
2906 #if 0 // TODO: PPC port
2907 __ bind(skip_storestore);
2908 #endif
2909
2910 // Do the store.
2911 if ($mem$$index == 0) {
2912 __ stb(R0, $mem$$disp, $mem$$base$$Register);
2913 } else {
2914 assert(0 == $mem$$disp, "no displacement possible with indexed load/stores on ppc");
2915 __ stbx(R0, $mem$$base$$Register, $mem$$index$$Register);
2916 }
2917 %}
2918
2919 enc_class postalloc_expand_encode_oop(iRegNdst dst, iRegPdst src, flagsReg crx) %{
2920
2921 if (VM_Version::has_isel()) {
2922 // use isel instruction with Power 7
2923 cmpP_reg_imm16Node *n_compare = new (C) cmpP_reg_imm16Node();
2924 encodeP_subNode *n_sub_base = new (C) encodeP_subNode();
2925 encodeP_shiftNode *n_shift = new (C) encodeP_shiftNode();
2926 cond_set_0_oopNode *n_cond_set = new (C) cond_set_0_oopNode();
2927
2928 n_compare->add_req(n_region, n_src);
2929 n_compare->_opnds[0] = op_crx;
2930 n_compare->_opnds[1] = op_src;
2931 n_compare->_opnds[2] = new (C) immL16Oper(0);
2932
2933 n_sub_base->add_req(n_region, n_src);
2934 n_sub_base->_opnds[0] = op_dst;
2935 n_sub_base->_opnds[1] = op_src;
2936 n_sub_base->_bottom_type = _bottom_type;
2937
2938 n_shift->add_req(n_region, n_sub_base);
2939 n_shift->_opnds[0] = op_dst;
2940 n_shift->_opnds[1] = op_dst;
2941 n_shift->_bottom_type = _bottom_type;
2942
2943 n_cond_set->add_req(n_region, n_compare, n_shift);
2944 n_cond_set->_opnds[0] = op_dst;
2945 n_cond_set->_opnds[1] = op_crx;
2946 n_cond_set->_opnds[2] = op_dst;
2947 n_cond_set->_bottom_type = _bottom_type;
2948
2949 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2950 ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2951 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2952 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2953
2954 nodes->push(n_compare);
2955 nodes->push(n_sub_base);
2956 nodes->push(n_shift);
2957 nodes->push(n_cond_set);
2958
2959 } else {
2960 // before Power 7
2961 moveRegNode *n_move = new (C) moveRegNode();
2962 cmpP_reg_imm16Node *n_compare = new (C) cmpP_reg_imm16Node();
2963 encodeP_shiftNode *n_shift = new (C) encodeP_shiftNode();
2964 cond_sub_baseNode *n_sub_base = new (C) cond_sub_baseNode();
2965
2966 n_move->add_req(n_region, n_src);
2967 n_move->_opnds[0] = op_dst;
2968 n_move->_opnds[1] = op_src;
2969 ra_->set_oop(n_move, true); // Until here, 'n_move' still produces an oop.
2970
2971 n_compare->add_req(n_region, n_src);
2972 n_compare->add_prec(n_move);
2973
2974 n_compare->_opnds[0] = op_crx;
2975 n_compare->_opnds[1] = op_src;
2976 n_compare->_opnds[2] = new (C) immL16Oper(0);
2977
2978 n_sub_base->add_req(n_region, n_compare, n_src);
2979 n_sub_base->_opnds[0] = op_dst;
2980 n_sub_base->_opnds[1] = op_crx;
2981 n_sub_base->_opnds[2] = op_src;
2982 n_sub_base->_bottom_type = _bottom_type;
2983
2984 n_shift->add_req(n_region, n_sub_base);
2985 n_shift->_opnds[0] = op_dst;
2986 n_shift->_opnds[1] = op_dst;
2987 n_shift->_bottom_type = _bottom_type;
2988
2989 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2990 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2991 ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2992 ra_->set_pair(n_move->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2993
2994 nodes->push(n_move);
2995 nodes->push(n_compare);
2996 nodes->push(n_sub_base);
2997 nodes->push(n_shift);
2998 }
2999
3000 assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed.
3001 %}
3002
3003 enc_class postalloc_expand_encode_oop_not_null(iRegNdst dst, iRegPdst src) %{
3004
3005 encodeP_subNode *n1 = new (C) encodeP_subNode();
3006 n1->add_req(n_region, n_src);
3007 n1->_opnds[0] = op_dst;
3008 n1->_opnds[1] = op_src;
3009 n1->_bottom_type = _bottom_type;
3010
3011 encodeP_shiftNode *n2 = new (C) encodeP_shiftNode();
3012 n2->add_req(n_region, n1);
3013 n2->_opnds[0] = op_dst;
3014 n2->_opnds[1] = op_dst;
3015 n2->_bottom_type = _bottom_type;
3016 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3017 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3018
3019 nodes->push(n1);
3020 nodes->push(n2);
3021 assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed.
3022 %}
3023
3024 enc_class postalloc_expand_decode_oop(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
3025 decodeN_shiftNode *n_shift = new (C) decodeN_shiftNode();
3026 cmpN_reg_imm0Node *n_compare = new (C) cmpN_reg_imm0Node();
3027
3028 n_compare->add_req(n_region, n_src);
3029 n_compare->_opnds[0] = op_crx;
3030 n_compare->_opnds[1] = op_src;
3031 n_compare->_opnds[2] = new (C) immN_0Oper(TypeNarrowOop::NULL_PTR);
3032
3033 n_shift->add_req(n_region, n_src);
3034 n_shift->_opnds[0] = op_dst;
3035 n_shift->_opnds[1] = op_src;
3036 n_shift->_bottom_type = _bottom_type;
3037
3038 if (VM_Version::has_isel()) {
3039 // use isel instruction with Power 7
3040
3041 decodeN_addNode *n_add_base = new (C) decodeN_addNode();
3042 n_add_base->add_req(n_region, n_shift);
3043 n_add_base->_opnds[0] = op_dst;
3044 n_add_base->_opnds[1] = op_dst;
3045 n_add_base->_bottom_type = _bottom_type;
3046
3047 cond_set_0_ptrNode *n_cond_set = new (C) cond_set_0_ptrNode();
3048 n_cond_set->add_req(n_region, n_compare, n_add_base);
3049 n_cond_set->_opnds[0] = op_dst;
3050 n_cond_set->_opnds[1] = op_crx;
3051 n_cond_set->_opnds[2] = op_dst;
3052 n_cond_set->_bottom_type = _bottom_type;
3053
3054 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
3055 ra_->set_oop(n_cond_set, true);
3056
3057 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3058 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
3059 ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3060 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3061
3062 nodes->push(n_compare);
3063 nodes->push(n_shift);
3064 nodes->push(n_add_base);
3065 nodes->push(n_cond_set);
3066
3067 } else {
3068 // before Power 7
3069 cond_add_baseNode *n_add_base = new (C) cond_add_baseNode();
3070
3071 n_add_base->add_req(n_region, n_compare, n_shift);
3072 n_add_base->_opnds[0] = op_dst;
3073 n_add_base->_opnds[1] = op_crx;
3074 n_add_base->_opnds[2] = op_dst;
3075 n_add_base->_bottom_type = _bottom_type;
3076
3077 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
3078 ra_->set_oop(n_add_base, true);
3079
3080 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3081 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
3082 ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3083
3084 nodes->push(n_compare);
3085 nodes->push(n_shift);
3086 nodes->push(n_add_base);
3087 }
3088 %}
3089
3090 enc_class postalloc_expand_decode_oop_not_null(iRegPdst dst, iRegNsrc src) %{
3091 decodeN_shiftNode *n1 = new (C) decodeN_shiftNode();
3092 n1->add_req(n_region, n_src);
3093 n1->_opnds[0] = op_dst;
3094 n1->_opnds[1] = op_src;
3095 n1->_bottom_type = _bottom_type;
3096
3097 decodeN_addNode *n2 = new (C) decodeN_addNode();
3098 n2->add_req(n_region, n1);
3099 n2->_opnds[0] = op_dst;
3100 n2->_opnds[1] = op_dst;
3101 n2->_bottom_type = _bottom_type;
3102 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3103 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3104
3105 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
3106 ra_->set_oop(n2, true);
3107
3108 nodes->push(n1);
3109 nodes->push(n2);
3110 %}
3111
3112 enc_class enc_cmove_reg(iRegIdst dst, flagsReg crx, iRegIsrc src, cmpOp cmp) %{
3113 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3114
3115 MacroAssembler _masm(&cbuf);
3116 int cc = $cmp$$cmpcode;
3117 int flags_reg = $crx$$reg;
3118 Label done;
3119 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3120 // Branch if not (cmp crx).
3121 __ bc(cc_to_inverse_boint(cc), cc_to_biint(cc, flags_reg), done);
3122 __ mr($dst$$Register, $src$$Register);
3123 // TODO PPC port __ endgroup_if_needed(_size == 12);
3124 __ bind(done);
3125 %}
3126
3127 enc_class enc_cmove_imm(iRegIdst dst, flagsReg crx, immI16 src, cmpOp cmp) %{
3128 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3129
3130 MacroAssembler _masm(&cbuf);
3131 Label done;
3132 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3133 // Branch if not (cmp crx).
3134 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
3135 __ li($dst$$Register, $src$$constant);
3136 // TODO PPC port __ endgroup_if_needed(_size == 12);
3137 __ bind(done);
3138 %}
3139
3140 // New atomics.
3141 enc_class enc_GetAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
3142 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3143
3144 MacroAssembler _masm(&cbuf);
3145 Register Rtmp = R0;
3146 Register Rres = $res$$Register;
3147 Register Rsrc = $src$$Register;
3148 Register Rptr = $mem_ptr$$Register;
3149 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3150 Register Rold = RegCollision ? Rtmp : Rres;
3151
3152 Label Lretry;
3153 __ bind(Lretry);
3154 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3155 __ add(Rtmp, Rsrc, Rold);
3156 __ stwcx_(Rtmp, Rptr);
3157 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3158 __ bne_predict_not_taken(CCR0, Lretry);
3159 } else {
3160 __ bne( CCR0, Lretry);
3161 }
3162 if (RegCollision) __ subf(Rres, Rsrc, Rtmp);
3163 __ fence();
3164 %}
3165
3166 enc_class enc_GetAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
3167 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3168
3169 MacroAssembler _masm(&cbuf);
3170 Register Rtmp = R0;
3171 Register Rres = $res$$Register;
3172 Register Rsrc = $src$$Register;
3173 Register Rptr = $mem_ptr$$Register;
3174 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3175 Register Rold = RegCollision ? Rtmp : Rres;
3176
3177 Label Lretry;
3178 __ bind(Lretry);
3179 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3180 __ add(Rtmp, Rsrc, Rold);
3181 __ stdcx_(Rtmp, Rptr);
3182 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3183 __ bne_predict_not_taken(CCR0, Lretry);
3184 } else {
3185 __ bne( CCR0, Lretry);
3186 }
3187 if (RegCollision) __ subf(Rres, Rsrc, Rtmp);
3188 __ fence();
3189 %}
3190
3191 enc_class enc_GetAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
3192 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3193
3194 MacroAssembler _masm(&cbuf);
3195 Register Rtmp = R0;
3196 Register Rres = $res$$Register;
3197 Register Rsrc = $src$$Register;
3198 Register Rptr = $mem_ptr$$Register;
3199 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3200 Register Rold = RegCollision ? Rtmp : Rres;
3201
3202 Label Lretry;
3203 __ bind(Lretry);
3204 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3205 __ stwcx_(Rsrc, Rptr);
3206 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3207 __ bne_predict_not_taken(CCR0, Lretry);
3208 } else {
3209 __ bne( CCR0, Lretry);
3210 }
3211 if (RegCollision) __ mr(Rres, Rtmp);
3212 __ fence();
3213 %}
3214
3215 enc_class enc_GetAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
3216 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3217
3218 MacroAssembler _masm(&cbuf);
3219 Register Rtmp = R0;
3220 Register Rres = $res$$Register;
3221 Register Rsrc = $src$$Register;
3222 Register Rptr = $mem_ptr$$Register;
3223 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3224 Register Rold = RegCollision ? Rtmp : Rres;
3225
3226 Label Lretry;
3227 __ bind(Lretry);
3228 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3229 __ stdcx_(Rsrc, Rptr);
3230 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3231 __ bne_predict_not_taken(CCR0, Lretry);
3232 } else {
3233 __ bne( CCR0, Lretry);
3234 }
3235 if (RegCollision) __ mr(Rres, Rtmp);
3236 __ fence();
3237 %}
3238
3239 // This enc_class is needed so that scheduler gets proper
3240 // input mapping for latency computation.
3241 enc_class enc_andc(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
3242 // TODO: PPC port $archOpcode(ppc64Opcode_andc);
3243 MacroAssembler _masm(&cbuf);
3244 __ andc($dst$$Register, $src1$$Register, $src2$$Register);
3245 %}
3246
3247 enc_class enc_convI2B_regI__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{
3248 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3249
3250 MacroAssembler _masm(&cbuf);
3251
3252 Label done;
3253 __ cmpwi($crx$$CondRegister, $src$$Register, 0);
3254 __ li($dst$$Register, $zero$$constant);
3255 __ beq($crx$$CondRegister, done);
3256 __ li($dst$$Register, $notzero$$constant);
3257 __ bind(done);
3258 %}
3259
3260 enc_class enc_convP2B_regP__cmove(iRegIdst dst, iRegPsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{
3261 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3262
3263 MacroAssembler _masm(&cbuf);
3264
3265 Label done;
3266 __ cmpdi($crx$$CondRegister, $src$$Register, 0);
3267 __ li($dst$$Register, $zero$$constant);
3268 __ beq($crx$$CondRegister, done);
3269 __ li($dst$$Register, $notzero$$constant);
3270 __ bind(done);
3271 %}
3272
3273 enc_class enc_cmove_bso_stackSlotL(iRegLdst dst, flagsReg crx, stackSlotL mem ) %{
3274 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3275
3276 MacroAssembler _masm(&cbuf);
3277 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
3278 Label done;
3279 __ bso($crx$$CondRegister, done);
3280 __ ld($dst$$Register, Idisp, $mem$$base$$Register);
3281 // TODO PPC port __ endgroup_if_needed(_size == 12);
3282 __ bind(done);
3283 %}
3284
3285 enc_class enc_bc(flagsReg crx, cmpOp cmp, Label lbl) %{
3286 // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3287
3288 MacroAssembler _masm(&cbuf);
3289 Label d; // dummy
3290 __ bind(d);
3291 Label* p = ($lbl$$label);
3292 // `p' is `NULL' when this encoding class is used only to
3293 // determine the size of the encoded instruction.
3294 Label& l = (NULL == p)? d : *(p);
3295 int cc = $cmp$$cmpcode;
3296 int flags_reg = $crx$$reg;
3297 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3298 int bhint = Assembler::bhintNoHint;
3299
3300 if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3301 if (_prob <= PROB_NEVER) {
3302 bhint = Assembler::bhintIsNotTaken;
3303 } else if (_prob >= PROB_ALWAYS) {
3304 bhint = Assembler::bhintIsTaken;
3305 }
3306 }
3307
3308 __ bc(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3309 cc_to_biint(cc, flags_reg),
3310 l);
3311 %}
3312
3313 enc_class enc_bc_far(flagsReg crx, cmpOp cmp, Label lbl) %{
3314 // The scheduler doesn't know about branch shortening, so we set the opcode
3315 // to ppc64Opcode_bc in order to hide this detail from the scheduler.
3316 // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3317
3318 MacroAssembler _masm(&cbuf);
3319 Label d; // dummy
3320 __ bind(d);
3321 Label* p = ($lbl$$label);
3322 // `p' is `NULL' when this encoding class is used only to
3323 // determine the size of the encoded instruction.
3324 Label& l = (NULL == p)? d : *(p);
3325 int cc = $cmp$$cmpcode;
3326 int flags_reg = $crx$$reg;
3327 int bhint = Assembler::bhintNoHint;
3328
3329 if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3330 if (_prob <= PROB_NEVER) {
3331 bhint = Assembler::bhintIsNotTaken;
3332 } else if (_prob >= PROB_ALWAYS) {
3333 bhint = Assembler::bhintIsTaken;
3334 }
3335 }
3336
3337 // Tell the conditional far branch to optimize itself when being relocated.
3338 __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3339 cc_to_biint(cc, flags_reg),
3340 l,
3341 MacroAssembler::bc_far_optimize_on_relocate);
3342 %}
3343
3344 // Branch used with Power6 scheduling (can be shortened without changing the node).
3345 enc_class enc_bc_short_far(flagsReg crx, cmpOp cmp, Label lbl) %{
3346 // The scheduler doesn't know about branch shortening, so we set the opcode
3347 // to ppc64Opcode_bc in order to hide this detail from the scheduler.
3348 // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3349
3350 MacroAssembler _masm(&cbuf);
3351 Label d; // dummy
3352 __ bind(d);
3353 Label* p = ($lbl$$label);
3354 // `p' is `NULL' when this encoding class is used only to
3355 // determine the size of the encoded instruction.
3356 Label& l = (NULL == p)? d : *(p);
3357 int cc = $cmp$$cmpcode;
3358 int flags_reg = $crx$$reg;
3359 int bhint = Assembler::bhintNoHint;
3360
3361 if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3362 if (_prob <= PROB_NEVER) {
3363 bhint = Assembler::bhintIsNotTaken;
3364 } else if (_prob >= PROB_ALWAYS) {
3365 bhint = Assembler::bhintIsTaken;
3366 }
3367 }
3368
3369 #if 0 // TODO: PPC port
3370 if (_size == 8) {
3371 // Tell the conditional far branch to optimize itself when being relocated.
3372 __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3373 cc_to_biint(cc, flags_reg),
3374 l,
3375 MacroAssembler::bc_far_optimize_on_relocate);
3376 } else {
3377 __ bc (Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3378 cc_to_biint(cc, flags_reg),
3379 l);
3380 }
3381 #endif
3382 Unimplemented();
3383 %}
3384
3385 // Postalloc expand emitter for loading a replicatef float constant from
3386 // the method's TOC.
3387 // Enc_class needed as consttanttablebase is not supported by postalloc
3388 // expand.
3389 enc_class postalloc_expand_load_replF_constant(iRegLdst dst, immF src, iRegLdst toc) %{
3390 // Create new nodes.
3391
3392 // Make an operand with the bit pattern to load as float.
3393 immLOper *op_repl = new (C) immLOper((jlong)replicate_immF(op_src->constantF()));
3394
3395 loadConLNodesTuple loadConLNodes =
3396 loadConLNodesTuple_create(C, ra_, n_toc, op_repl,
3397 ra_->get_reg_second(this), ra_->get_reg_first(this));
3398
3399 // Push new nodes.
3400 if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi);
3401 if (loadConLNodes._last) nodes->push(loadConLNodes._last);
3402
3403 assert(nodes->length() >= 1, "must have created at least 1 node");
3404 assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long");
3405 %}
3406
3407 // This enc_class is needed so that scheduler gets proper
3408 // input mapping for latency computation.
3409 enc_class enc_poll(immI dst, iRegLdst poll) %{
3410 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
3411 // Fake operand dst needed for PPC scheduler.
3412 assert($dst$$constant == 0x0, "dst must be 0x0");
3413
3414 MacroAssembler _masm(&cbuf);
3415 // Mark the code position where the load from the safepoint
3416 // polling page was emitted as relocInfo::poll_type.
3417 __ relocate(relocInfo::poll_type);
3418 __ load_from_polling_page($poll$$Register);
3419 %}
3420
3421 // A Java static call or a runtime call.
3422 //
3423 // Branch-and-link relative to a trampoline.
3424 // The trampoline loads the target address and does a long branch to there.
3425 // In case we call java, the trampoline branches to a interpreter_stub
3426 // which loads the inline cache and the real call target from the constant pool.
3427 //
3428 // This basically looks like this:
3429 //
3430 // >>>> consts -+ -+
3431 // | |- offset1
3432 // [call target1] | <-+
3433 // [IC cache] |- offset2
3434 // [call target2] <--+
3435 //
3436 // <<<< consts
3437 // >>>> insts
3438 //
3439 // bl offset16 -+ -+ ??? // How many bits available?
3440 // | |
3441 // <<<< insts | |
3442 // >>>> stubs | |
3443 // | |- trampoline_stub_Reloc
3444 // trampoline stub: | <-+
3445 // r2 = toc |
3446 // r2 = [r2 + offset1] | // Load call target1 from const section
3447 // mtctr r2 |
3448 // bctr |- static_stub_Reloc
3449 // comp_to_interp_stub: <---+
3450 // r1 = toc
3451 // ICreg = [r1 + IC_offset] // Load IC from const section
3452 // r1 = [r1 + offset2] // Load call target2 from const section
3453 // mtctr r1
3454 // bctr
3455 //
3456 // <<<< stubs
3457 //
3458 // The call instruction in the code either
3459 // - Branches directly to a compiled method if the offset is encodable in instruction.
3460 // - Branches to the trampoline stub if the offset to the compiled method is not encodable.
3461 // - Branches to the compiled_to_interp stub if the target is interpreted.
3462 //
3463 // Further there are three relocations from the loads to the constants in
3464 // the constant section.
3465 //
3466 // Usage of r1 and r2 in the stubs allows to distinguish them.
3467 enc_class enc_java_static_call(method meth) %{
3468 // TODO: PPC port $archOpcode(ppc64Opcode_bl);
3469
3470 MacroAssembler _masm(&cbuf);
3471 address entry_point = (address)$meth$$method;
3472
3473 if (!_method) {
3474 // A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap.
3475 emit_call_with_trampoline_stub(_masm, entry_point, relocInfo::runtime_call_type);
3476 } else {
3477 // Remember the offset not the address.
3478 const int start_offset = __ offset();
3479 // The trampoline stub.
3480 if (!Compile::current()->in_scratch_emit_size()) {
3481 // No entry point given, use the current pc.
3482 // Make sure branch fits into
3483 if (entry_point == 0) entry_point = __ pc();
3484
3485 // Put the entry point as a constant into the constant pool.
3486 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none);
3487 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
3488
3489 // Emit the trampoline stub which will be related to the branch-and-link below.
3490 CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset);
3491 if (ciEnv::current()->failing()) { return; } // Code cache may be full.
3492 __ relocate(_optimized_virtual ?
3493 relocInfo::opt_virtual_call_type : relocInfo::static_call_type);
3494 }
3495
3496 // The real call.
3497 // Note: At this point we do not have the address of the trampoline
3498 // stub, and the entry point might be too far away for bl, so __ pc()
3499 // serves as dummy and the bl will be patched later.
3500 cbuf.set_insts_mark();
3501 __ bl(__ pc()); // Emits a relocation.
3502
3503 // The stub for call to interpreter.
3504 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf);
3505 if (stub == NULL) {
3506 ciEnv::current()->record_failure("CodeCache is full");
3507 return;
3508 }
3509 }
3510 %}
3511
3512 // Emit a method handle call.
3513 //
3514 // Method handle calls from compiled to compiled are going thru a
3515 // c2i -> i2c adapter, extending the frame for their arguments. The
3516 // caller however, returns directly to the compiled callee, that has
3517 // to cope with the extended frame. We restore the original frame by
3518 // loading the callers sp and adding the calculated framesize.
3519 enc_class enc_java_handle_call(method meth) %{
3520 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3521
3522 MacroAssembler _masm(&cbuf);
3523 address entry_point = (address)$meth$$method;
3524
3525 // Remember the offset not the address.
3526 const int start_offset = __ offset();
3527 // The trampoline stub.
3528 if (!ra_->C->in_scratch_emit_size()) {
3529 // No entry point given, use the current pc.
3530 // Make sure branch fits into
3531 if (entry_point == 0) entry_point = __ pc();
3532
3533 // Put the entry point as a constant into the constant pool.
3534 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none);
3535 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
3536
3537 // Emit the trampoline stub which will be related to the branch-and-link below.
3538 CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset);
3539 if (ra_->C->env()->failing()) { return; } // Code cache may be full.
3540 assert(_optimized_virtual, "methodHandle call should be a virtual call");
3541 __ relocate(relocInfo::opt_virtual_call_type);
3542 }
3543
3544 // The real call.
3545 // Note: At this point we do not have the address of the trampoline
3546 // stub, and the entry point might be too far away for bl, so __ pc()
3547 // serves as dummy and the bl will be patched later.
3548 cbuf.set_insts_mark();
3549 __ bl(__ pc()); // Emits a relocation.
3550
3551 assert(_method, "execute next statement conditionally");
3552 // The stub for call to interpreter.
3553 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf);
3554 if (stub == NULL) {
3555 ciEnv::current()->record_failure("CodeCache is full");
3556 return;
3557 }
3558
3559 // Restore original sp.
3560 __ ld(R11_scratch1, 0, R1_SP); // Load caller sp.
3561 const long framesize = ra_->C->frame_slots() << LogBytesPerInt;
3562 unsigned int bytes = (unsigned int)framesize;
3563 long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes);
3564 if (Assembler::is_simm(-offset, 16)) {
3565 __ addi(R1_SP, R11_scratch1, -offset);
3566 } else {
3567 __ load_const_optimized(R12_scratch2, -offset);
3568 __ add(R1_SP, R11_scratch1, R12_scratch2);
3569 }
3570 #ifdef ASSERT
3571 __ ld(R12_scratch2, 0, R1_SP); // Load from unextended_sp.
3572 __ cmpd(CCR0, R11_scratch1, R12_scratch2);
3573 __ asm_assert_eq("backlink changed", 0x8000);
3574 #endif
3575 // If fails should store backlink before unextending.
3576
3577 if (ra_->C->env()->failing()) {
3578 return;
3579 }
3580 %}
3581
3582 // Second node of expanded dynamic call - the call.
3583 enc_class enc_java_dynamic_call_sched(method meth) %{
3584 // TODO: PPC port $archOpcode(ppc64Opcode_bl);
3585
3586 MacroAssembler _masm(&cbuf);
3587
3588 if (!ra_->C->in_scratch_emit_size()) {
3589 // Create a call trampoline stub for the given method.
3590 const address entry_point = !($meth$$method) ? 0 : (address)$meth$$method;
3591 const address entry_point_const = __ address_constant(entry_point, RelocationHolder::none);
3592 const int entry_point_const_toc_offset = __ offset_to_method_toc(entry_point_const);
3593 CallStubImpl::emit_trampoline_stub(_masm, entry_point_const_toc_offset, __ offset());
3594 if (ra_->C->env()->failing()) { return; } // Code cache may be full.
3595
3596 // Build relocation at call site with ic position as data.
3597 assert((_load_ic_hi_node != NULL && _load_ic_node == NULL) ||
3598 (_load_ic_hi_node == NULL && _load_ic_node != NULL),
3599 "must have one, but can't have both");
3600 assert((_load_ic_hi_node != NULL && _load_ic_hi_node->_cbuf_insts_offset != -1) ||
3601 (_load_ic_node != NULL && _load_ic_node->_cbuf_insts_offset != -1),
3602 "must contain instruction offset");
3603 const int virtual_call_oop_addr_offset = _load_ic_hi_node != NULL
3604 ? _load_ic_hi_node->_cbuf_insts_offset
3605 : _load_ic_node->_cbuf_insts_offset;
3606 const address virtual_call_oop_addr = __ addr_at(virtual_call_oop_addr_offset);
3607 assert(MacroAssembler::is_load_const_from_method_toc_at(virtual_call_oop_addr),
3608 "should be load from TOC");
3609
3610 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr));
3611 }
3612
3613 // At this point I do not have the address of the trampoline stub,
3614 // and the entry point might be too far away for bl. Pc() serves
3615 // as dummy and bl will be patched later.
3616 __ bl((address) __ pc());
3617 %}
3618
3619 // postalloc expand emitter for virtual calls.
3620 enc_class postalloc_expand_java_dynamic_call_sched(method meth, iRegLdst toc) %{
3621
3622 // Create the nodes for loading the IC from the TOC.
3623 loadConLNodesTuple loadConLNodes_IC =
3624 loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper((jlong)Universe::non_oop_word()),
3625 OptoReg::Name(R19_H_num), OptoReg::Name(R19_num));
3626
3627 // Create the call node.
3628 CallDynamicJavaDirectSchedNode *call = new (C) CallDynamicJavaDirectSchedNode();
3629 call->_method_handle_invoke = _method_handle_invoke;
3630 call->_vtable_index = _vtable_index;
3631 call->_method = _method;
3632 call->_bci = _bci;
3633 call->_optimized_virtual = _optimized_virtual;
3634 call->_tf = _tf;
3635 call->_entry_point = _entry_point;
3636 call->_cnt = _cnt;
3637 call->_argsize = _argsize;
3638 call->_oop_map = _oop_map;
3639 call->_jvms = _jvms;
3640 call->_jvmadj = _jvmadj;
3641 call->_in_rms = _in_rms;
3642 call->_nesting = _nesting;
3643
3644 // New call needs all inputs of old call.
3645 // Req...
3646 for (uint i = 0; i < req(); ++i) {
3647 // The expanded node does not need toc any more.
3648 // Add the inline cache constant here instead. This expresses the
3649 // register of the inline cache must be live at the call.
3650 // Else we would have to adapt JVMState by -1.
3651 if (i == mach_constant_base_node_input()) {
3652 call->add_req(loadConLNodes_IC._last);
3653 } else {
3654 call->add_req(in(i));
3655 }
3656 }
3657 // ...as well as prec
3658 for (uint i = req(); i < len(); ++i) {
3659 call->add_prec(in(i));
3660 }
3661
3662 // Remember nodes loading the inline cache into r19.
3663 call->_load_ic_hi_node = loadConLNodes_IC._large_hi;
3664 call->_load_ic_node = loadConLNodes_IC._small;
3665
3666 // Operands for new nodes.
3667 call->_opnds[0] = _opnds[0];
3668 call->_opnds[1] = _opnds[1];
3669
3670 // Only the inline cache is associated with a register.
3671 assert(Matcher::inline_cache_reg() == OptoReg::Name(R19_num), "ic reg should be R19");
3672
3673 // Push new nodes.
3674 if (loadConLNodes_IC._large_hi) nodes->push(loadConLNodes_IC._large_hi);
3675 if (loadConLNodes_IC._last) nodes->push(loadConLNodes_IC._last);
3676 nodes->push(call);
3677 %}
3678
3679 // Compound version of call dynamic
3680 // Toc is only passed so that it can be used in ins_encode statement.
3681 // In the code we have to use $constanttablebase.
3682 enc_class enc_java_dynamic_call(method meth, iRegLdst toc) %{
3683 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3684 MacroAssembler _masm(&cbuf);
3685 int start_offset = __ offset();
3686
3687 Register Rtoc = (ra_) ? $constanttablebase : R2_TOC;
3688 #if 0
3689 int vtable_index = this->_vtable_index;
3690 if (_vtable_index < 0) {
3691 // Must be invalid_vtable_index, not nonvirtual_vtable_index.
3692 assert(_vtable_index == Method::invalid_vtable_index, "correct sentinel value");
3693 Register ic_reg = as_Register(Matcher::inline_cache_reg_encode());
3694
3695 // Virtual call relocation will point to ic load.
3696 address virtual_call_meta_addr = __ pc();
3697 // Load a clear inline cache.
3698 AddressLiteral empty_ic((address) Universe::non_oop_word());
3699 __ load_const_from_method_toc(ic_reg, empty_ic, Rtoc);
3700 // CALL to fixup routine. Fixup routine uses ScopeDesc info
3701 // to determine who we intended to call.
3702 __ relocate(virtual_call_Relocation::spec(virtual_call_meta_addr));
3703 emit_call_with_trampoline_stub(_masm, (address)$meth$$method, relocInfo::none);
3704 assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset,
3705 "Fix constant in ret_addr_offset()");
3706 } else {
3707 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
3708 // Go thru the vtable. Get receiver klass. Receiver already
3709 // checked for non-null. If we'll go thru a C2I adapter, the
3710 // interpreter expects method in R19_method.
3711
3712 __ load_klass(R11_scratch1, R3);
3713
3714 int entry_offset = InstanceKlass::vtable_start_offset() + _vtable_index * vtableEntry::size();
3715 int v_off = entry_offset * wordSize + vtableEntry::method_offset_in_bytes();
3716 __ li(R19_method, v_off);
3717 __ ldx(R19_method/*method oop*/, R19_method/*method offset*/, R11_scratch1/*class*/);
3718 // NOTE: for vtable dispatches, the vtable entry will never be
3719 // null. However it may very well end up in handle_wrong_method
3720 // if the method is abstract for the particular class.
3721 __ ld(R11_scratch1, in_bytes(Method::from_compiled_offset()), R19_method);
3722 // Call target. Either compiled code or C2I adapter.
3723 __ mtctr(R11_scratch1);
3724 __ bctrl();
3725 if (((MachCallDynamicJavaNode*)this)->ret_addr_offset() != __ offset() - start_offset) {
3726 tty->print(" %d, %d\n", ((MachCallDynamicJavaNode*)this)->ret_addr_offset(),__ offset() - start_offset);
3727 }
3728 assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset,
3729 "Fix constant in ret_addr_offset()");
3730 }
3731 #endif
3732 Unimplemented(); // ret_addr_offset not yet fixed. Depends on compressed oops (load klass!).
3733 %}
3734
3735 // a runtime call
3736 enc_class enc_java_to_runtime_call (method meth) %{
3737 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3738
3739 MacroAssembler _masm(&cbuf);
3740 const address start_pc = __ pc();
3741
3742 #if defined(ABI_ELFv2)
3743 address entry= !($meth$$method) ? NULL : (address)$meth$$method;
3744 __ call_c(entry, relocInfo::runtime_call_type);
3745 #else
3746 // The function we're going to call.
3747 FunctionDescriptor fdtemp;
3748 const FunctionDescriptor* fd = !($meth$$method) ? &fdtemp : (FunctionDescriptor*)$meth$$method;
3749
3750 Register Rtoc = R12_scratch2;
3751 // Calculate the method's TOC.
3752 __ calculate_address_from_global_toc(Rtoc, __ method_toc());
3753 // Put entry, env, toc into the constant pool, this needs up to 3 constant
3754 // pool entries; call_c_using_toc will optimize the call.
3755 __ call_c_using_toc(fd, relocInfo::runtime_call_type, Rtoc);
3756 #endif
3757
3758 // Check the ret_addr_offset.
3759 assert(((MachCallRuntimeNode*)this)->ret_addr_offset() == __ last_calls_return_pc() - start_pc,
3760 "Fix constant in ret_addr_offset()");
3761 %}
3762
3763 // Move to ctr for leaf call.
3764 // This enc_class is needed so that scheduler gets proper
3765 // input mapping for latency computation.
3766 enc_class enc_leaf_call_mtctr(iRegLsrc src) %{
3767 // TODO: PPC port $archOpcode(ppc64Opcode_mtctr);
3768 MacroAssembler _masm(&cbuf);
3769 __ mtctr($src$$Register);
3770 %}
3771
3772 // Postalloc expand emitter for runtime leaf calls.
3773 enc_class postalloc_expand_java_to_runtime_call(method meth, iRegLdst toc) %{
3774 loadConLNodesTuple loadConLNodes_Entry;
3775 #if defined(ABI_ELFv2)
3776 jlong entry_address = (jlong) this->entry_point();
3777 assert(entry_address, "need address here");
3778 loadConLNodes_Entry = loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper(entry_address),
3779 OptoReg::Name(R12_H_num), OptoReg::Name(R12_num));
3780 #else
3781 // Get the struct that describes the function we are about to call.
3782 FunctionDescriptor* fd = (FunctionDescriptor*) this->entry_point();
3783 assert(fd, "need fd here");
3784 jlong entry_address = (jlong) fd->entry();
3785 // new nodes
3786 loadConLNodesTuple loadConLNodes_Env;
3787 loadConLNodesTuple loadConLNodes_Toc;
3788
3789 // Create nodes and operands for loading the entry point.
3790 loadConLNodes_Entry = loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper(entry_address),
3791 OptoReg::Name(R12_H_num), OptoReg::Name(R12_num));
3792
3793
3794 // Create nodes and operands for loading the env pointer.
3795 if (fd->env() != NULL) {
3796 loadConLNodes_Env = loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper((jlong) fd->env()),
3797 OptoReg::Name(R11_H_num), OptoReg::Name(R11_num));
3798 } else {
3799 loadConLNodes_Env._large_hi = NULL;
3800 loadConLNodes_Env._large_lo = NULL;
3801 loadConLNodes_Env._small = NULL;
3802 loadConLNodes_Env._last = new (C) loadConL16Node();
3803 loadConLNodes_Env._last->_opnds[0] = new (C) iRegLdstOper();
3804 loadConLNodes_Env._last->_opnds[1] = new (C) immL16Oper(0);
3805 ra_->set_pair(loadConLNodes_Env._last->_idx, OptoReg::Name(R11_H_num), OptoReg::Name(R11_num));
3806 }
3807
3808 // Create nodes and operands for loading the Toc point.
3809 loadConLNodes_Toc = loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper((jlong) fd->toc()),
3810 OptoReg::Name(R2_H_num), OptoReg::Name(R2_num));
3811 #endif // ABI_ELFv2
3812 // mtctr node
3813 MachNode *mtctr = new (C) CallLeafDirect_mtctrNode();
3814
3815 assert(loadConLNodes_Entry._last != NULL, "entry must exist");
3816 mtctr->add_req(0, loadConLNodes_Entry._last);
3817
3818 mtctr->_opnds[0] = new (C) iRegLdstOper();
3819 mtctr->_opnds[1] = new (C) iRegLdstOper();
3820
3821 // call node
3822 MachCallLeafNode *call = new (C) CallLeafDirectNode();
3823
3824 call->_opnds[0] = _opnds[0];
3825 call->_opnds[1] = new (C) methodOper((intptr_t) entry_address); // May get set later.
3826
3827 // Make the new call node look like the old one.
3828 call->_name = _name;
3829 call->_tf = _tf;
3830 call->_entry_point = _entry_point;
3831 call->_cnt = _cnt;
3832 call->_argsize = _argsize;
3833 call->_oop_map = _oop_map;
3834 guarantee(!_jvms, "You must clone the jvms and adapt the offsets by fix_jvms().");
3835 call->_jvms = NULL;
3836 call->_jvmadj = _jvmadj;
3837 call->_in_rms = _in_rms;
3838 call->_nesting = _nesting;
3839
3840
3841 // New call needs all inputs of old call.
3842 // Req...
3843 for (uint i = 0; i < req(); ++i) {
3844 if (i != mach_constant_base_node_input()) {
3845 call->add_req(in(i));
3846 }
3847 }
3848
3849 // These must be reqired edges, as the registers are live up to
3850 // the call. Else the constants are handled as kills.
3851 call->add_req(mtctr);
3852 #if !defined(ABI_ELFv2)
3853 call->add_req(loadConLNodes_Env._last);
3854 call->add_req(loadConLNodes_Toc._last);
3855 #endif
3856
3857 // ...as well as prec
3858 for (uint i = req(); i < len(); ++i) {
3859 call->add_prec(in(i));
3860 }
3861
3862 // registers
3863 ra_->set1(mtctr->_idx, OptoReg::Name(SR_CTR_num));
3864
3865 // Insert the new nodes.
3866 if (loadConLNodes_Entry._large_hi) nodes->push(loadConLNodes_Entry._large_hi);
3867 if (loadConLNodes_Entry._last) nodes->push(loadConLNodes_Entry._last);
3868 #if !defined(ABI_ELFv2)
3869 if (loadConLNodes_Env._large_hi) nodes->push(loadConLNodes_Env._large_hi);
3870 if (loadConLNodes_Env._last) nodes->push(loadConLNodes_Env._last);
3871 if (loadConLNodes_Toc._large_hi) nodes->push(loadConLNodes_Toc._large_hi);
3872 if (loadConLNodes_Toc._last) nodes->push(loadConLNodes_Toc._last);
3873 #endif
3874 nodes->push(mtctr);
3875 nodes->push(call);
3876 %}
3877 %}
3878
3879 //----------FRAME--------------------------------------------------------------
3880 // Definition of frame structure and management information.
3881
3882 frame %{
3883 // What direction does stack grow in (assumed to be same for native & Java).
3884 stack_direction(TOWARDS_LOW);
3885
3886 // These two registers define part of the calling convention between
3887 // compiled code and the interpreter.
3888
3889 // Inline Cache Register or method for I2C.
3890 inline_cache_reg(R19); // R19_method
3891
3892 // Method Oop Register when calling interpreter.
3893 interpreter_method_oop_reg(R19); // R19_method
3894
3895 // Optional: name the operand used by cisc-spilling to access
3896 // [stack_pointer + offset].
3897 cisc_spilling_operand_name(indOffset);
3898
3899 // Number of stack slots consumed by a Monitor enter.
3900 sync_stack_slots((frame::jit_monitor_size / VMRegImpl::stack_slot_size));
3901
3902 // Compiled code's Frame Pointer.
3903 frame_pointer(R1); // R1_SP
3904
3905 // Interpreter stores its frame pointer in a register which is
3906 // stored to the stack by I2CAdaptors. I2CAdaptors convert from
3907 // interpreted java to compiled java.
3908 //
3909 // R14_state holds pointer to caller's cInterpreter.
3910 interpreter_frame_pointer(R14); // R14_state
3911
3912 stack_alignment(frame::alignment_in_bytes);
3913
3914 in_preserve_stack_slots((frame::jit_in_preserve_size / VMRegImpl::stack_slot_size));
3915
3916 // Number of outgoing stack slots killed above the
3917 // out_preserve_stack_slots for calls to C. Supports the var-args
3918 // backing area for register parms.
3919 //
3920 varargs_C_out_slots_killed(((frame::abi_reg_args_size - frame::jit_out_preserve_size) / VMRegImpl::stack_slot_size));
3921
3922 // The after-PROLOG location of the return address. Location of
3923 // return address specifies a type (REG or STACK) and a number
3924 // representing the register number (i.e. - use a register name) or
3925 // stack slot.
3926 //
3927 // A: Link register is stored in stack slot ...
3928 // M: ... but it's in the caller's frame according to PPC-64 ABI.
3929 // J: Therefore, we make sure that the link register is also in R11_scratch1
3930 // at the end of the prolog.
3931 // B: We use R20, now.
3932 //return_addr(REG R20);
3933
3934 // G: After reading the comments made by all the luminaries on their
3935 // failure to tell the compiler where the return address really is,
3936 // I hardly dare to try myself. However, I'm convinced it's in slot
3937 // 4 what apparently works and saves us some spills.
3938 return_addr(STACK 4);
3939
3940 // This is the body of the function
3941 //
3942 // void Matcher::calling_convention(OptoRegPair* sig, // array of ideal regs
3943 // uint length, // length of array
3944 // bool is_outgoing)
3945 //
3946 // The `sig' array is to be updated. sig[j] represents the location
3947 // of the j-th argument, either a register or a stack slot.
3948
3949 // Comment taken from i486.ad:
3950 // Body of function which returns an integer array locating
3951 // arguments either in registers or in stack slots. Passed an array
3952 // of ideal registers called "sig" and a "length" count. Stack-slot
3953 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3954 // arguments for a CALLEE. Incoming stack arguments are
3955 // automatically biased by the preserve_stack_slots field above.
3956 calling_convention %{
3957 // No difference between ingoing/outgoing. Just pass false.
3958 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3959 %}
3960
3961 // Comment taken from i486.ad:
3962 // Body of function which returns an integer array locating
3963 // arguments either in registers or in stack slots. Passed an array
3964 // of ideal registers called "sig" and a "length" count. Stack-slot
3965 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3966 // arguments for a CALLEE. Incoming stack arguments are
3967 // automatically biased by the preserve_stack_slots field above.
3968 c_calling_convention %{
3969 // This is obviously always outgoing.
3970 // C argument in register AND stack slot.
3971 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
3972 %}
3973
3974 // Location of native (C/C++) and interpreter return values. This
3975 // is specified to be the same as Java. In the 32-bit VM, long
3976 // values are actually returned from native calls in O0:O1 and
3977 // returned to the interpreter in I0:I1. The copying to and from
3978 // the register pairs is done by the appropriate call and epilog
3979 // opcodes. This simplifies the register allocator.
3980 c_return_value %{
3981 assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) ||
3982 (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0),
3983 "only return normal values");
3984 // enum names from opcodes.hpp: Op_Node Op_Set Op_RegN Op_RegI Op_RegP Op_RegF Op_RegD Op_RegL
3985 static int typeToRegLo[Op_RegL+1] = { 0, 0, R3_num, R3_num, R3_num, F1_num, F1_num, R3_num };
3986 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num };
3987 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
3988 %}
3989
3990 // Location of compiled Java return values. Same as C
3991 return_value %{
3992 assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) ||
3993 (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0),
3994 "only return normal values");
3995 // enum names from opcodes.hpp: Op_Node Op_Set Op_RegN Op_RegI Op_RegP Op_RegF Op_RegD Op_RegL
3996 static int typeToRegLo[Op_RegL+1] = { 0, 0, R3_num, R3_num, R3_num, F1_num, F1_num, R3_num };
3997 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num };
3998 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
3999 %}
4000 %}
4001
4002
4003 //----------ATTRIBUTES---------------------------------------------------------
4004
4005 //----------Operand Attributes-------------------------------------------------
4006 op_attrib op_cost(1); // Required cost attribute.
4007
4008 //----------Instruction Attributes---------------------------------------------
4009
4010 // Cost attribute. required.
4011 ins_attrib ins_cost(DEFAULT_COST);
4012
4013 // Is this instruction a non-matching short branch variant of some
4014 // long branch? Not required.
4015 ins_attrib ins_short_branch(0);
4016
4017 ins_attrib ins_is_TrapBasedCheckNode(true);
4018
4019 // Number of constants.
4020 // This instruction uses the given number of constants
4021 // (optional attribute).
4022 // This is needed to determine in time whether the constant pool will
4023 // exceed 4000 entries. Before postalloc_expand the overall number of constants
4024 // is determined. It's also used to compute the constant pool size
4025 // in Output().
4026 ins_attrib ins_num_consts(0);
4027
4028 // Required alignment attribute (must be a power of 2) specifies the
4029 // alignment that some part of the instruction (not necessarily the
4030 // start) requires. If > 1, a compute_padding() function must be
4031 // provided for the instruction.
4032 ins_attrib ins_alignment(1);
4033
4034 // Enforce/prohibit rematerializations.
4035 // - If an instruction is attributed with 'ins_cannot_rematerialize(true)'
4036 // then rematerialization of that instruction is prohibited and the
4037 // instruction's value will be spilled if necessary.
4038 // Causes that MachNode::rematerialize() returns false.
4039 // - If an instruction is attributed with 'ins_should_rematerialize(true)'
4040 // then rematerialization should be enforced and a copy of the instruction
4041 // should be inserted if possible; rematerialization is not guaranteed.
4042 // Note: this may result in rematerializations in front of every use.
4043 // Causes that MachNode::rematerialize() can return true.
4044 // (optional attribute)
4045 ins_attrib ins_cannot_rematerialize(false);
4046 ins_attrib ins_should_rematerialize(false);
4047
4048 // Instruction has variable size depending on alignment.
4049 ins_attrib ins_variable_size_depending_on_alignment(false);
4050
4051 // Instruction is a nop.
4052 ins_attrib ins_is_nop(false);
4053
4054 // Instruction is mapped to a MachIfFastLock node (instead of MachFastLock).
4055 ins_attrib ins_use_mach_if_fast_lock_node(false);
4056
4057 // Field for the toc offset of a constant.
4058 //
4059 // This is needed if the toc offset is not encodable as an immediate in
4060 // the PPC load instruction. If so, the upper (hi) bits of the offset are
4061 // added to the toc, and from this a load with immediate is performed.
4062 // With postalloc expand, we get two nodes that require the same offset
4063 // but which don't know about each other. The offset is only known
4064 // when the constant is added to the constant pool during emitting.
4065 // It is generated in the 'hi'-node adding the upper bits, and saved
4066 // in this node. The 'lo'-node has a link to the 'hi'-node and reads
4067 // the offset from there when it gets encoded.
4068 ins_attrib ins_field_const_toc_offset(0);
4069 ins_attrib ins_field_const_toc_offset_hi_node(0);
4070
4071 // A field that can hold the instructions offset in the code buffer.
4072 // Set in the nodes emitter.
4073 ins_attrib ins_field_cbuf_insts_offset(-1);
4074
4075 // Fields for referencing a call's load-IC-node.
4076 // If the toc offset can not be encoded as an immediate in a load, we
4077 // use two nodes.
4078 ins_attrib ins_field_load_ic_hi_node(0);
4079 ins_attrib ins_field_load_ic_node(0);
4080
4081 //----------OPERANDS-----------------------------------------------------------
4082 // Operand definitions must precede instruction definitions for correct
4083 // parsing in the ADLC because operands constitute user defined types
4084 // which are used in instruction definitions.
4085 //
4086 // Formats are generated automatically for constants and base registers.
4087
4088 //----------Simple Operands----------------------------------------------------
4089 // Immediate Operands
4090
4091 // Integer Immediate: 32-bit
4092 operand immI() %{
4093 match(ConI);
4094 op_cost(40);
4095 format %{ %}
4096 interface(CONST_INTER);
4097 %}
4098
4099 operand immI8() %{
4100 predicate(Assembler::is_simm(n->get_int(), 8));
4101 op_cost(0);
4102 match(ConI);
4103 format %{ %}
4104 interface(CONST_INTER);
4105 %}
4106
4107 // Integer Immediate: 16-bit
4108 operand immI16() %{
4109 predicate(Assembler::is_simm(n->get_int(), 16));
4110 op_cost(0);
4111 match(ConI);
4112 format %{ %}
4113 interface(CONST_INTER);
4114 %}
4115
4116 // Integer Immediate: 32-bit, where lowest 16 bits are 0x0000.
4117 operand immIhi16() %{
4118 predicate(((n->get_int() & 0xffff0000) != 0) && ((n->get_int() & 0xffff) == 0));
4119 match(ConI);
4120 op_cost(0);
4121 format %{ %}
4122 interface(CONST_INTER);
4123 %}
4124
4125 operand immInegpow2() %{
4126 predicate(is_power_of_2_long((jlong) (julong) (juint) (-(n->get_int()))));
4127 match(ConI);
4128 op_cost(0);
4129 format %{ %}
4130 interface(CONST_INTER);
4131 %}
4132
4133 operand immIpow2minus1() %{
4134 predicate(is_power_of_2_long((((jlong) (n->get_int()))+1)));
4135 match(ConI);
4136 op_cost(0);
4137 format %{ %}
4138 interface(CONST_INTER);
4139 %}
4140
4141 operand immIpowerOf2() %{
4142 predicate(is_power_of_2_long((((jlong) (julong) (juint) (n->get_int())))));
4143 match(ConI);
4144 op_cost(0);
4145 format %{ %}
4146 interface(CONST_INTER);
4147 %}
4148
4149 // Unsigned Integer Immediate: the values 0-31
4150 operand uimmI5() %{
4151 predicate(Assembler::is_uimm(n->get_int(), 5));
4152 match(ConI);
4153 op_cost(0);
4154 format %{ %}
4155 interface(CONST_INTER);
4156 %}
4157
4158 // Unsigned Integer Immediate: 6-bit
4159 operand uimmI6() %{
4160 predicate(Assembler::is_uimm(n->get_int(), 6));
4161 match(ConI);
4162 op_cost(0);
4163 format %{ %}
4164 interface(CONST_INTER);
4165 %}
4166
4167 // Unsigned Integer Immediate: 6-bit int, greater than 32
4168 operand uimmI6_ge32() %{
4169 predicate(Assembler::is_uimm(n->get_int(), 6) && n->get_int() >= 32);
4170 match(ConI);
4171 op_cost(0);
4172 format %{ %}
4173 interface(CONST_INTER);
4174 %}
4175
4176 // Unsigned Integer Immediate: 15-bit
4177 operand uimmI15() %{
4178 predicate(Assembler::is_uimm(n->get_int(), 15));
4179 match(ConI);
4180 op_cost(0);
4181 format %{ %}
4182 interface(CONST_INTER);
4183 %}
4184
4185 // Unsigned Integer Immediate: 16-bit
4186 operand uimmI16() %{
4187 predicate(Assembler::is_uimm(n->get_int(), 16));
4188 match(ConI);
4189 op_cost(0);
4190 format %{ %}
4191 interface(CONST_INTER);
4192 %}
4193
4194 // constant 'int 0'.
4195 operand immI_0() %{
4196 predicate(n->get_int() == 0);
4197 match(ConI);
4198 op_cost(0);
4199 format %{ %}
4200 interface(CONST_INTER);
4201 %}
4202
4203 // constant 'int 1'.
4204 operand immI_1() %{
4205 predicate(n->get_int() == 1);
4206 match(ConI);
4207 op_cost(0);
4208 format %{ %}
4209 interface(CONST_INTER);
4210 %}
4211
4212 // constant 'int -1'.
4213 operand immI_minus1() %{
4214 predicate(n->get_int() == -1);
4215 match(ConI);
4216 op_cost(0);
4217 format %{ %}
4218 interface(CONST_INTER);
4219 %}
4220
4221 // int value 16.
4222 operand immI_16() %{
4223 predicate(n->get_int() == 16);
4224 match(ConI);
4225 op_cost(0);
4226 format %{ %}
4227 interface(CONST_INTER);
4228 %}
4229
4230 // int value 24.
4231 operand immI_24() %{
4232 predicate(n->get_int() == 24);
4233 match(ConI);
4234 op_cost(0);
4235 format %{ %}
4236 interface(CONST_INTER);
4237 %}
4238
4239 // Compressed oops constants
4240 // Pointer Immediate
4241 operand immN() %{
4242 match(ConN);
4243
4244 op_cost(10);
4245 format %{ %}
4246 interface(CONST_INTER);
4247 %}
4248
4249 // NULL Pointer Immediate
4250 operand immN_0() %{
4251 predicate(n->get_narrowcon() == 0);
4252 match(ConN);
4253
4254 op_cost(0);
4255 format %{ %}
4256 interface(CONST_INTER);
4257 %}
4258
4259 // Compressed klass constants
4260 operand immNKlass() %{
4261 match(ConNKlass);
4262
4263 op_cost(0);
4264 format %{ %}
4265 interface(CONST_INTER);
4266 %}
4267
4268 // This operand can be used to avoid matching of an instruct
4269 // with chain rule.
4270 operand immNKlass_NM() %{
4271 match(ConNKlass);
4272 predicate(false);
4273 op_cost(0);
4274 format %{ %}
4275 interface(CONST_INTER);
4276 %}
4277
4278 // Pointer Immediate: 64-bit
4279 operand immP() %{
4280 match(ConP);
4281 op_cost(0);
4282 format %{ %}
4283 interface(CONST_INTER);
4284 %}
4285
4286 // Operand to avoid match of loadConP.
4287 // This operand can be used to avoid matching of an instruct
4288 // with chain rule.
4289 operand immP_NM() %{
4290 match(ConP);
4291 predicate(false);
4292 op_cost(0);
4293 format %{ %}
4294 interface(CONST_INTER);
4295 %}
4296
4297 // costant 'pointer 0'.
4298 operand immP_0() %{
4299 predicate(n->get_ptr() == 0);
4300 match(ConP);
4301 op_cost(0);
4302 format %{ %}
4303 interface(CONST_INTER);
4304 %}
4305
4306 // pointer 0x0 or 0x1
4307 operand immP_0or1() %{
4308 predicate((n->get_ptr() == 0) || (n->get_ptr() == 1));
4309 match(ConP);
4310 op_cost(0);
4311 format %{ %}
4312 interface(CONST_INTER);
4313 %}
4314
4315 operand immL() %{
4316 match(ConL);
4317 op_cost(40);
4318 format %{ %}
4319 interface(CONST_INTER);
4320 %}
4321
4322 // Long Immediate: 16-bit
4323 operand immL16() %{
4324 predicate(Assembler::is_simm(n->get_long(), 16));
4325 match(ConL);
4326 op_cost(0);
4327 format %{ %}
4328 interface(CONST_INTER);
4329 %}
4330
4331 // Long Immediate: 16-bit, 4-aligned
4332 operand immL16Alg4() %{
4333 predicate(Assembler::is_simm(n->get_long(), 16) && ((n->get_long() & 0x3) == 0));
4334 match(ConL);
4335 op_cost(0);
4336 format %{ %}
4337 interface(CONST_INTER);
4338 %}
4339
4340 // Long Immediate: 32-bit, where lowest 16 bits are 0x0000.
4341 operand immL32hi16() %{
4342 predicate(Assembler::is_simm(n->get_long(), 32) && ((n->get_long() & 0xffffL) == 0L));
4343 match(ConL);
4344 op_cost(0);
4345 format %{ %}
4346 interface(CONST_INTER);
4347 %}
4348
4349 // Long Immediate: 32-bit
4350 operand immL32() %{
4351 predicate(Assembler::is_simm(n->get_long(), 32));
4352 match(ConL);
4353 op_cost(0);
4354 format %{ %}
4355 interface(CONST_INTER);
4356 %}
4357
4358 // Long Immediate: 64-bit, where highest 16 bits are not 0x0000.
4359 operand immLhighest16() %{
4360 predicate((n->get_long() & 0xffff000000000000L) != 0L && (n->get_long() & 0x0000ffffffffffffL) == 0L);
4361 match(ConL);
4362 op_cost(0);
4363 format %{ %}
4364 interface(CONST_INTER);
4365 %}
4366
4367 operand immLnegpow2() %{
4368 predicate(is_power_of_2_long((jlong)-(n->get_long())));
4369 match(ConL);
4370 op_cost(0);
4371 format %{ %}
4372 interface(CONST_INTER);
4373 %}
4374
4375 operand immLpow2minus1() %{
4376 predicate(is_power_of_2_long((((jlong) (n->get_long()))+1)) &&
4377 (n->get_long() != (jlong)0xffffffffffffffffL));
4378 match(ConL);
4379 op_cost(0);
4380 format %{ %}
4381 interface(CONST_INTER);
4382 %}
4383
4384 // constant 'long 0'.
4385 operand immL_0() %{
4386 predicate(n->get_long() == 0L);
4387 match(ConL);
4388 op_cost(0);
4389 format %{ %}
4390 interface(CONST_INTER);
4391 %}
4392
4393 // constat ' long -1'.
4394 operand immL_minus1() %{
4395 predicate(n->get_long() == -1L);
4396 match(ConL);
4397 op_cost(0);
4398 format %{ %}
4399 interface(CONST_INTER);
4400 %}
4401
4402 // Long Immediate: low 32-bit mask
4403 operand immL_32bits() %{
4404 predicate(n->get_long() == 0xFFFFFFFFL);
4405 match(ConL);
4406 op_cost(0);
4407 format %{ %}
4408 interface(CONST_INTER);
4409 %}
4410
4411 // Unsigned Long Immediate: 16-bit
4412 operand uimmL16() %{
4413 predicate(Assembler::is_uimm(n->get_long(), 16));
4414 match(ConL);
4415 op_cost(0);
4416 format %{ %}
4417 interface(CONST_INTER);
4418 %}
4419
4420 // Float Immediate
4421 operand immF() %{
4422 match(ConF);
4423 op_cost(40);
4424 format %{ %}
4425 interface(CONST_INTER);
4426 %}
4427
4428 // Float Immediate: +0.0f.
4429 operand immF_0() %{
4430 predicate(jint_cast(n->getf()) == 0);
4431 match(ConF);
4432
4433 op_cost(0);
4434 format %{ %}
4435 interface(CONST_INTER);
4436 %}
4437
4438 // Double Immediate
4439 operand immD() %{
4440 match(ConD);
4441 op_cost(40);
4442 format %{ %}
4443 interface(CONST_INTER);
4444 %}
4445
4446 // Integer Register Operands
4447 // Integer Destination Register
4448 // See definition of reg_class bits32_reg_rw.
4449 operand iRegIdst() %{
4450 constraint(ALLOC_IN_RC(bits32_reg_rw));
4451 match(RegI);
4452 match(rscratch1RegI);
4453 match(rscratch2RegI);
4454 match(rarg1RegI);
4455 match(rarg2RegI);
4456 match(rarg3RegI);
4457 match(rarg4RegI);
4458 format %{ %}
4459 interface(REG_INTER);
4460 %}
4461
4462 // Integer Source Register
4463 // See definition of reg_class bits32_reg_ro.
4464 operand iRegIsrc() %{
4465 constraint(ALLOC_IN_RC(bits32_reg_ro));
4466 match(RegI);
4467 match(rscratch1RegI);
4468 match(rscratch2RegI);
4469 match(rarg1RegI);
4470 match(rarg2RegI);
4471 match(rarg3RegI);
4472 match(rarg4RegI);
4473 format %{ %}
4474 interface(REG_INTER);
4475 %}
4476
4477 operand rscratch1RegI() %{
4478 constraint(ALLOC_IN_RC(rscratch1_bits32_reg));
4479 match(iRegIdst);
4480 format %{ %}
4481 interface(REG_INTER);
4482 %}
4483
4484 operand rscratch2RegI() %{
4485 constraint(ALLOC_IN_RC(rscratch2_bits32_reg));
4486 match(iRegIdst);
4487 format %{ %}
4488 interface(REG_INTER);
4489 %}
4490
4491 operand rarg1RegI() %{
4492 constraint(ALLOC_IN_RC(rarg1_bits32_reg));
4493 match(iRegIdst);
4494 format %{ %}
4495 interface(REG_INTER);
4496 %}
4497
4498 operand rarg2RegI() %{
4499 constraint(ALLOC_IN_RC(rarg2_bits32_reg));
4500 match(iRegIdst);
4501 format %{ %}
4502 interface(REG_INTER);
4503 %}
4504
4505 operand rarg3RegI() %{
4506 constraint(ALLOC_IN_RC(rarg3_bits32_reg));
4507 match(iRegIdst);
4508 format %{ %}
4509 interface(REG_INTER);
4510 %}
4511
4512 operand rarg4RegI() %{
4513 constraint(ALLOC_IN_RC(rarg4_bits32_reg));
4514 match(iRegIdst);
4515 format %{ %}
4516 interface(REG_INTER);
4517 %}
4518
4519 operand rarg1RegL() %{
4520 constraint(ALLOC_IN_RC(rarg1_bits64_reg));
4521 match(iRegLdst);
4522 format %{ %}
4523 interface(REG_INTER);
4524 %}
4525
4526 operand rarg2RegL() %{
4527 constraint(ALLOC_IN_RC(rarg2_bits64_reg));
4528 match(iRegLdst);
4529 format %{ %}
4530 interface(REG_INTER);
4531 %}
4532
4533 operand rarg3RegL() %{
4534 constraint(ALLOC_IN_RC(rarg3_bits64_reg));
4535 match(iRegLdst);
4536 format %{ %}
4537 interface(REG_INTER);
4538 %}
4539
4540 operand rarg4RegL() %{
4541 constraint(ALLOC_IN_RC(rarg4_bits64_reg));
4542 match(iRegLdst);
4543 format %{ %}
4544 interface(REG_INTER);
4545 %}
4546
4547 // Pointer Destination Register
4548 // See definition of reg_class bits64_reg_rw.
4549 operand iRegPdst() %{
4550 constraint(ALLOC_IN_RC(bits64_reg_rw));
4551 match(RegP);
4552 match(rscratch1RegP);
4553 match(rscratch2RegP);
4554 match(rarg1RegP);
4555 match(rarg2RegP);
4556 match(rarg3RegP);
4557 match(rarg4RegP);
4558 format %{ %}
4559 interface(REG_INTER);
4560 %}
4561
4562 // Pointer Destination Register
4563 // Operand not using r11 and r12 (killed in epilog).
4564 operand iRegPdstNoScratch() %{
4565 constraint(ALLOC_IN_RC(bits64_reg_leaf_call));
4566 match(RegP);
4567 match(rarg1RegP);
4568 match(rarg2RegP);
4569 match(rarg3RegP);
4570 match(rarg4RegP);
4571 format %{ %}
4572 interface(REG_INTER);
4573 %}
4574
4575 // Pointer Source Register
4576 // See definition of reg_class bits64_reg_ro.
4577 operand iRegPsrc() %{
4578 constraint(ALLOC_IN_RC(bits64_reg_ro));
4579 match(RegP);
4580 match(iRegPdst);
4581 match(rscratch1RegP);
4582 match(rscratch2RegP);
4583 match(rarg1RegP);
4584 match(rarg2RegP);
4585 match(rarg3RegP);
4586 match(rarg4RegP);
4587 match(threadRegP);
4588 format %{ %}
4589 interface(REG_INTER);
4590 %}
4591
4592 // Thread operand.
4593 operand threadRegP() %{
4594 constraint(ALLOC_IN_RC(thread_bits64_reg));
4595 match(iRegPdst);
4596 format %{ "R16" %}
4597 interface(REG_INTER);
4598 %}
4599
4600 operand rscratch1RegP() %{
4601 constraint(ALLOC_IN_RC(rscratch1_bits64_reg));
4602 match(iRegPdst);
4603 format %{ "R11" %}
4604 interface(REG_INTER);
4605 %}
4606
4607 operand rscratch2RegP() %{
4608 constraint(ALLOC_IN_RC(rscratch2_bits64_reg));
4609 match(iRegPdst);
4610 format %{ %}
4611 interface(REG_INTER);
4612 %}
4613
4614 operand rarg1RegP() %{
4615 constraint(ALLOC_IN_RC(rarg1_bits64_reg));
4616 match(iRegPdst);
4617 format %{ %}
4618 interface(REG_INTER);
4619 %}
4620
4621 operand rarg2RegP() %{
4622 constraint(ALLOC_IN_RC(rarg2_bits64_reg));
4623 match(iRegPdst);
4624 format %{ %}
4625 interface(REG_INTER);
4626 %}
4627
4628 operand rarg3RegP() %{
4629 constraint(ALLOC_IN_RC(rarg3_bits64_reg));
4630 match(iRegPdst);
4631 format %{ %}
4632 interface(REG_INTER);
4633 %}
4634
4635 operand rarg4RegP() %{
4636 constraint(ALLOC_IN_RC(rarg4_bits64_reg));
4637 match(iRegPdst);
4638 format %{ %}
4639 interface(REG_INTER);
4640 %}
4641
4642 operand iRegNsrc() %{
4643 constraint(ALLOC_IN_RC(bits32_reg_ro));
4644 match(RegN);
4645 match(iRegNdst);
4646
4647 format %{ %}
4648 interface(REG_INTER);
4649 %}
4650
4651 operand iRegNdst() %{
4652 constraint(ALLOC_IN_RC(bits32_reg_rw));
4653 match(RegN);
4654
4655 format %{ %}
4656 interface(REG_INTER);
4657 %}
4658
4659 // Long Destination Register
4660 // See definition of reg_class bits64_reg_rw.
4661 operand iRegLdst() %{
4662 constraint(ALLOC_IN_RC(bits64_reg_rw));
4663 match(RegL);
4664 match(rscratch1RegL);
4665 match(rscratch2RegL);
4666 format %{ %}
4667 interface(REG_INTER);
4668 %}
4669
4670 // Long Source Register
4671 // See definition of reg_class bits64_reg_ro.
4672 operand iRegLsrc() %{
4673 constraint(ALLOC_IN_RC(bits64_reg_ro));
4674 match(RegL);
4675 match(iRegLdst);
4676 match(rscratch1RegL);
4677 match(rscratch2RegL);
4678 format %{ %}
4679 interface(REG_INTER);
4680 %}
4681
4682 // Special operand for ConvL2I.
4683 operand iRegL2Isrc(iRegLsrc reg) %{
4684 constraint(ALLOC_IN_RC(bits64_reg_ro));
4685 match(ConvL2I reg);
4686 format %{ "ConvL2I($reg)" %}
4687 interface(REG_INTER)
4688 %}
4689
4690 operand rscratch1RegL() %{
4691 constraint(ALLOC_IN_RC(rscratch1_bits64_reg));
4692 match(RegL);
4693 format %{ %}
4694 interface(REG_INTER);
4695 %}
4696
4697 operand rscratch2RegL() %{
4698 constraint(ALLOC_IN_RC(rscratch2_bits64_reg));
4699 match(RegL);
4700 format %{ %}
4701 interface(REG_INTER);
4702 %}
4703
4704 // Condition Code Flag Registers
4705 operand flagsReg() %{
4706 constraint(ALLOC_IN_RC(int_flags));
4707 match(RegFlags);
4708 format %{ %}
4709 interface(REG_INTER);
4710 %}
4711
4712 // Condition Code Flag Register CR0
4713 operand flagsRegCR0() %{
4714 constraint(ALLOC_IN_RC(int_flags_CR0));
4715 match(RegFlags);
4716 format %{ "CR0" %}
4717 interface(REG_INTER);
4718 %}
4719
4720 operand flagsRegCR1() %{
4721 constraint(ALLOC_IN_RC(int_flags_CR1));
4722 match(RegFlags);
4723 format %{ "CR1" %}
4724 interface(REG_INTER);
4725 %}
4726
4727 operand flagsRegCR6() %{
4728 constraint(ALLOC_IN_RC(int_flags_CR6));
4729 match(RegFlags);
4730 format %{ "CR6" %}
4731 interface(REG_INTER);
4732 %}
4733
4734 operand regCTR() %{
4735 constraint(ALLOC_IN_RC(ctr_reg));
4736 // RegFlags should work. Introducing a RegSpecial type would cause a
4737 // lot of changes.
4738 match(RegFlags);
4739 format %{"SR_CTR" %}
4740 interface(REG_INTER);
4741 %}
4742
4743 operand regD() %{
4744 constraint(ALLOC_IN_RC(dbl_reg));
4745 match(RegD);
4746 format %{ %}
4747 interface(REG_INTER);
4748 %}
4749
4750 operand regF() %{
4751 constraint(ALLOC_IN_RC(flt_reg));
4752 match(RegF);
4753 format %{ %}
4754 interface(REG_INTER);
4755 %}
4756
4757 // Special Registers
4758
4759 // Method Register
4760 operand inline_cache_regP(iRegPdst reg) %{
4761 constraint(ALLOC_IN_RC(r19_bits64_reg)); // inline_cache_reg
4762 match(reg);
4763 format %{ %}
4764 interface(REG_INTER);
4765 %}
4766
4767 operand compiler_method_oop_regP(iRegPdst reg) %{
4768 constraint(ALLOC_IN_RC(rscratch1_bits64_reg)); // compiler_method_oop_reg
4769 match(reg);
4770 format %{ %}
4771 interface(REG_INTER);
4772 %}
4773
4774 operand interpreter_method_oop_regP(iRegPdst reg) %{
4775 constraint(ALLOC_IN_RC(r19_bits64_reg)); // interpreter_method_oop_reg
4776 match(reg);
4777 format %{ %}
4778 interface(REG_INTER);
4779 %}
4780
4781 // Operands to remove register moves in unscaled mode.
4782 // Match read/write registers with an EncodeP node if neither shift nor add are required.
4783 operand iRegP2N(iRegPsrc reg) %{
4784 predicate(false /* TODO: PPC port MatchDecodeNodes*/&& Universe::narrow_oop_shift() == 0);
4785 constraint(ALLOC_IN_RC(bits64_reg_ro));
4786 match(EncodeP reg);
4787 format %{ "$reg" %}
4788 interface(REG_INTER)
4789 %}
4790
4791 operand iRegN2P(iRegNsrc reg) %{
4792 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4793 constraint(ALLOC_IN_RC(bits32_reg_ro));
4794 match(DecodeN reg);
4795 match(DecodeNKlass reg);
4796 format %{ "$reg" %}
4797 interface(REG_INTER)
4798 %}
4799
4800 //----------Complex Operands---------------------------------------------------
4801 // Indirect Memory Reference
4802 operand indirect(iRegPsrc reg) %{
4803 constraint(ALLOC_IN_RC(bits64_reg_ro));
4804 match(reg);
4805 op_cost(100);
4806 format %{ "[$reg]" %}
4807 interface(MEMORY_INTER) %{
4808 base($reg);
4809 index(0x0);
4810 scale(0x0);
4811 disp(0x0);
4812 %}
4813 %}
4814
4815 // Indirect with Offset
4816 operand indOffset16(iRegPsrc reg, immL16 offset) %{
4817 constraint(ALLOC_IN_RC(bits64_reg_ro));
4818 match(AddP reg offset);
4819 op_cost(100);
4820 format %{ "[$reg + $offset]" %}
4821 interface(MEMORY_INTER) %{
4822 base($reg);
4823 index(0x0);
4824 scale(0x0);
4825 disp($offset);
4826 %}
4827 %}
4828
4829 // Indirect with 4-aligned Offset
4830 operand indOffset16Alg4(iRegPsrc reg, immL16Alg4 offset) %{
4831 constraint(ALLOC_IN_RC(bits64_reg_ro));
4832 match(AddP reg offset);
4833 op_cost(100);
4834 format %{ "[$reg + $offset]" %}
4835 interface(MEMORY_INTER) %{
4836 base($reg);
4837 index(0x0);
4838 scale(0x0);
4839 disp($offset);
4840 %}
4841 %}
4842
4843 //----------Complex Operands for Compressed OOPs-------------------------------
4844 // Compressed OOPs with narrow_oop_shift == 0.
4845
4846 // Indirect Memory Reference, compressed OOP
4847 operand indirectNarrow(iRegNsrc reg) %{
4848 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4849 constraint(ALLOC_IN_RC(bits64_reg_ro));
4850 match(DecodeN reg);
4851 match(DecodeNKlass reg);
4852 op_cost(100);
4853 format %{ "[$reg]" %}
4854 interface(MEMORY_INTER) %{
4855 base($reg);
4856 index(0x0);
4857 scale(0x0);
4858 disp(0x0);
4859 %}
4860 %}
4861
4862 // Indirect with Offset, compressed OOP
4863 operand indOffset16Narrow(iRegNsrc reg, immL16 offset) %{
4864 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4865 constraint(ALLOC_IN_RC(bits64_reg_ro));
4866 match(AddP (DecodeN reg) offset);
4867 match(AddP (DecodeNKlass reg) offset);
4868 op_cost(100);
4869 format %{ "[$reg + $offset]" %}
4870 interface(MEMORY_INTER) %{
4871 base($reg);
4872 index(0x0);
4873 scale(0x0);
4874 disp($offset);
4875 %}
4876 %}
4877
4878 // Indirect with 4-aligned Offset, compressed OOP
4879 operand indOffset16NarrowAlg4(iRegNsrc reg, immL16Alg4 offset) %{
4880 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4881 constraint(ALLOC_IN_RC(bits64_reg_ro));
4882 match(AddP (DecodeN reg) offset);
4883 match(AddP (DecodeNKlass reg) offset);
4884 op_cost(100);
4885 format %{ "[$reg + $offset]" %}
4886 interface(MEMORY_INTER) %{
4887 base($reg);
4888 index(0x0);
4889 scale(0x0);
4890 disp($offset);
4891 %}
4892 %}
4893
4894 //----------Special Memory Operands--------------------------------------------
4895 // Stack Slot Operand
4896 //
4897 // This operand is used for loading and storing temporary values on
4898 // the stack where a match requires a value to flow through memory.
4899 operand stackSlotI(sRegI reg) %{
4900 constraint(ALLOC_IN_RC(stack_slots));
4901 op_cost(100);
4902 //match(RegI);
4903 format %{ "[sp+$reg]" %}
4904 interface(MEMORY_INTER) %{
4905 base(0x1); // R1_SP
4906 index(0x0);
4907 scale(0x0);
4908 disp($reg); // Stack Offset
4909 %}
4910 %}
4911
4912 operand stackSlotL(sRegL reg) %{
4913 constraint(ALLOC_IN_RC(stack_slots));
4914 op_cost(100);
4915 //match(RegL);
4916 format %{ "[sp+$reg]" %}
4917 interface(MEMORY_INTER) %{
4918 base(0x1); // R1_SP
4919 index(0x0);
4920 scale(0x0);
4921 disp($reg); // Stack Offset
4922 %}
4923 %}
4924
4925 operand stackSlotP(sRegP reg) %{
4926 constraint(ALLOC_IN_RC(stack_slots));
4927 op_cost(100);
4928 //match(RegP);
4929 format %{ "[sp+$reg]" %}
4930 interface(MEMORY_INTER) %{
4931 base(0x1); // R1_SP
4932 index(0x0);
4933 scale(0x0);
4934 disp($reg); // Stack Offset
4935 %}
4936 %}
4937
4938 operand stackSlotF(sRegF reg) %{
4939 constraint(ALLOC_IN_RC(stack_slots));
4940 op_cost(100);
4941 //match(RegF);
4942 format %{ "[sp+$reg]" %}
4943 interface(MEMORY_INTER) %{
4944 base(0x1); // R1_SP
4945 index(0x0);
4946 scale(0x0);
4947 disp($reg); // Stack Offset
4948 %}
4949 %}
4950
4951 operand stackSlotD(sRegD reg) %{
4952 constraint(ALLOC_IN_RC(stack_slots));
4953 op_cost(100);
4954 //match(RegD);
4955 format %{ "[sp+$reg]" %}
4956 interface(MEMORY_INTER) %{
4957 base(0x1); // R1_SP
4958 index(0x0);
4959 scale(0x0);
4960 disp($reg); // Stack Offset
4961 %}
4962 %}
4963
4964 // Operands for expressing Control Flow
4965 // NOTE: Label is a predefined operand which should not be redefined in
4966 // the AD file. It is generically handled within the ADLC.
4967
4968 //----------Conditional Branch Operands----------------------------------------
4969 // Comparison Op
4970 //
4971 // This is the operation of the comparison, and is limited to the
4972 // following set of codes: L (<), LE (<=), G (>), GE (>=), E (==), NE
4973 // (!=).
4974 //
4975 // Other attributes of the comparison, such as unsignedness, are specified
4976 // by the comparison instruction that sets a condition code flags register.
4977 // That result is represented by a flags operand whose subtype is appropriate
4978 // to the unsignedness (etc.) of the comparison.
4979 //
4980 // Later, the instruction which matches both the Comparison Op (a Bool) and
4981 // the flags (produced by the Cmp) specifies the coding of the comparison op
4982 // by matching a specific subtype of Bool operand below.
4983
4984 // When used for floating point comparisons: unordered same as less.
4985 operand cmpOp() %{
4986 match(Bool);
4987 format %{ "" %}
4988 interface(COND_INTER) %{
4989 // BO only encodes bit 4 of bcondCRbiIsX, as bits 1-3 are always '100'.
4990 // BO & BI
4991 equal(0xA); // 10 10: bcondCRbiIs1 & Condition::equal
4992 not_equal(0x2); // 00 10: bcondCRbiIs0 & Condition::equal
4993 less(0x8); // 10 00: bcondCRbiIs1 & Condition::less
4994 greater_equal(0x0); // 00 00: bcondCRbiIs0 & Condition::less
4995 less_equal(0x1); // 00 01: bcondCRbiIs0 & Condition::greater
4996 greater(0x9); // 10 01: bcondCRbiIs1 & Condition::greater
4997 overflow(0xB); // 10 11: bcondCRbiIs1 & Condition::summary_overflow
4998 no_overflow(0x3); // 00 11: bcondCRbiIs0 & Condition::summary_overflow
4999 %}
5000 %}
5001
5002 //----------OPERAND CLASSES----------------------------------------------------
5003 // Operand Classes are groups of operands that are used to simplify
5004 // instruction definitions by not requiring the AD writer to specify
5005 // seperate instructions for every form of operand when the
5006 // instruction accepts multiple operand types with the same basic
5007 // encoding and format. The classic case of this is memory operands.
5008 // Indirect is not included since its use is limited to Compare & Swap.
5009
5010 opclass memory(indirect, indOffset16 /*, indIndex, tlsReference*/, indirectNarrow, indOffset16Narrow);
5011 // Memory operand where offsets are 4-aligned. Required for ld, std.
5012 opclass memoryAlg4(indirect, indOffset16Alg4, indirectNarrow, indOffset16NarrowAlg4);
5013 opclass indirectMemory(indirect, indirectNarrow);
5014
5015 // Special opclass for I and ConvL2I.
5016 opclass iRegIsrc_iRegL2Isrc(iRegIsrc, iRegL2Isrc);
5017
5018 // Operand classes to match encode and decode. iRegN_P2N is only used
5019 // for storeN. I have never seen an encode node elsewhere.
5020 opclass iRegN_P2N(iRegNsrc, iRegP2N);
5021 opclass iRegP_N2P(iRegPsrc, iRegN2P);
5022
5023 //----------PIPELINE-----------------------------------------------------------
5024
5025 pipeline %{
5026
5027 // See J.M.Tendler et al. "Power4 system microarchitecture", IBM
5028 // J. Res. & Dev., No. 1, Jan. 2002.
5029
5030 //----------ATTRIBUTES---------------------------------------------------------
5031 attributes %{
5032
5033 // Power4 instructions are of fixed length.
5034 fixed_size_instructions;
5035
5036 // TODO: if `bundle' means number of instructions fetched
5037 // per cycle, this is 8. If `bundle' means Power4 `group', that is
5038 // max instructions issued per cycle, this is 5.
5039 max_instructions_per_bundle = 8;
5040
5041 // A Power4 instruction is 4 bytes long.
5042 instruction_unit_size = 4;
5043
5044 // The Power4 processor fetches 64 bytes...
5045 instruction_fetch_unit_size = 64;
5046
5047 // ...in one line
5048 instruction_fetch_units = 1
5049
5050 // Unused, list one so that array generated by adlc is not empty.
5051 // Aix compiler chokes if _nop_count = 0.
5052 nops(fxNop);
5053 %}
5054
5055 //----------RESOURCES----------------------------------------------------------
5056 // Resources are the functional units available to the machine
5057 resources(
5058 PPC_BR, // branch unit
5059 PPC_CR, // condition unit
5060 PPC_FX1, // integer arithmetic unit 1
5061 PPC_FX2, // integer arithmetic unit 2
5062 PPC_LDST1, // load/store unit 1
5063 PPC_LDST2, // load/store unit 2
5064 PPC_FP1, // float arithmetic unit 1
5065 PPC_FP2, // float arithmetic unit 2
5066 PPC_LDST = PPC_LDST1 | PPC_LDST2,
5067 PPC_FX = PPC_FX1 | PPC_FX2,
5068 PPC_FP = PPC_FP1 | PPC_FP2
5069 );
5070
5071 //----------PIPELINE DESCRIPTION-----------------------------------------------
5072 // Pipeline Description specifies the stages in the machine's pipeline
5073 pipe_desc(
5074 // Power4 longest pipeline path
5075 PPC_IF, // instruction fetch
5076 PPC_IC,
5077 //PPC_BP, // branch prediction
5078 PPC_D0, // decode
5079 PPC_D1, // decode
5080 PPC_D2, // decode
5081 PPC_D3, // decode
5082 PPC_Xfer1,
5083 PPC_GD, // group definition
5084 PPC_MP, // map
5085 PPC_ISS, // issue
5086 PPC_RF, // resource fetch
5087 PPC_EX1, // execute (all units)
5088 PPC_EX2, // execute (FP, LDST)
5089 PPC_EX3, // execute (FP, LDST)
5090 PPC_EX4, // execute (FP)
5091 PPC_EX5, // execute (FP)
5092 PPC_EX6, // execute (FP)
5093 PPC_WB, // write back
5094 PPC_Xfer2,
5095 PPC_CP
5096 );
5097
5098 //----------PIPELINE CLASSES---------------------------------------------------
5099 // Pipeline Classes describe the stages in which input and output are
5100 // referenced by the hardware pipeline.
5101
5102 // Simple pipeline classes.
5103
5104 // Default pipeline class.
5105 pipe_class pipe_class_default() %{
5106 single_instruction;
5107 fixed_latency(2);
5108 %}
5109
5110 // Pipeline class for empty instructions.
5111 pipe_class pipe_class_empty() %{
5112 single_instruction;
5113 fixed_latency(0);
5114 %}
5115
5116 // Pipeline class for compares.
5117 pipe_class pipe_class_compare() %{
5118 single_instruction;
5119 fixed_latency(16);
5120 %}
5121
5122 // Pipeline class for traps.
5123 pipe_class pipe_class_trap() %{
5124 single_instruction;
5125 fixed_latency(100);
5126 %}
5127
5128 // Pipeline class for memory operations.
5129 pipe_class pipe_class_memory() %{
5130 single_instruction;
5131 fixed_latency(16);
5132 %}
5133
5134 // Pipeline class for call.
5135 pipe_class pipe_class_call() %{
5136 single_instruction;
5137 fixed_latency(100);
5138 %}
5139
5140 // Define the class for the Nop node.
5141 define %{
5142 MachNop = pipe_class_default;
5143 %}
5144
5145 %}
5146
5147 //----------INSTRUCTIONS-------------------------------------------------------
5148
5149 // Naming of instructions:
5150 // opA_operB / opA_operB_operC:
5151 // Operation 'op' with one or two source operands 'oper'. Result
5152 // type is A, source operand types are B and C.
5153 // Iff A == B == C, B and C are left out.
5154 //
5155 // The instructions are ordered according to the following scheme:
5156 // - loads
5157 // - load constants
5158 // - prefetch
5159 // - store
5160 // - encode/decode
5161 // - membar
5162 // - conditional moves
5163 // - compare & swap
5164 // - arithmetic and logic operations
5165 // * int: Add, Sub, Mul, Div, Mod
5166 // * int: lShift, arShift, urShift, rot
5167 // * float: Add, Sub, Mul, Div
5168 // * and, or, xor ...
5169 // - register moves: float <-> int, reg <-> stack, repl
5170 // - cast (high level type cast, XtoP, castPP, castII, not_null etc.
5171 // - conv (low level type cast requiring bit changes (sign extend etc)
5172 // - compares, range & zero checks.
5173 // - branches
5174 // - complex operations, intrinsics, min, max, replicate
5175 // - lock
5176 // - Calls
5177 //
5178 // If there are similar instructions with different types they are sorted:
5179 // int before float
5180 // small before big
5181 // signed before unsigned
5182 // e.g., loadS before loadUS before loadI before loadF.
5183
5184
5185 //----------Load/Store Instructions--------------------------------------------
5186
5187 //----------Load Instructions--------------------------------------------------
5188
5189 // Converts byte to int.
5190 // As convB2I_reg, but without match rule. The match rule of convB2I_reg
5191 // reuses the 'amount' operand, but adlc expects that operand specification
5192 // and operands in match rule are equivalent.
5193 instruct convB2I_reg_2(iRegIdst dst, iRegIsrc src) %{
5194 effect(DEF dst, USE src);
5195 format %{ "EXTSB $dst, $src \t// byte->int" %}
5196 size(4);
5197 ins_encode %{
5198 // TODO: PPC port $archOpcode(ppc64Opcode_extsb);
5199 __ extsb($dst$$Register, $src$$Register);
5200 %}
5201 ins_pipe(pipe_class_default);
5202 %}
5203
5204 instruct loadUB_indirect(iRegIdst dst, indirectMemory mem) %{
5205 // match-rule, false predicate
5206 match(Set dst (LoadB mem));
5207 predicate(false);
5208
5209 format %{ "LBZ $dst, $mem" %}
5210 size(4);
5211 ins_encode( enc_lbz(dst, mem) );
5212 ins_pipe(pipe_class_memory);
5213 %}
5214
5215 instruct loadUB_indirect_ac(iRegIdst dst, indirectMemory mem) %{
5216 // match-rule, false predicate
5217 match(Set dst (LoadB mem));
5218 predicate(false);
5219
5220 format %{ "LBZ $dst, $mem\n\t"
5221 "TWI $dst\n\t"
5222 "ISYNC" %}
5223 size(12);
5224 ins_encode( enc_lbz_ac(dst, mem) );
5225 ins_pipe(pipe_class_memory);
5226 %}
5227
5228 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B.
5229 instruct loadB_indirect_Ex(iRegIdst dst, indirectMemory mem) %{
5230 match(Set dst (LoadB mem));
5231 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5232 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5233 expand %{
5234 iRegIdst tmp;
5235 loadUB_indirect(tmp, mem);
5236 convB2I_reg_2(dst, tmp);
5237 %}
5238 %}
5239
5240 instruct loadB_indirect_ac_Ex(iRegIdst dst, indirectMemory mem) %{
5241 match(Set dst (LoadB mem));
5242 ins_cost(3*MEMORY_REF_COST + DEFAULT_COST);
5243 expand %{
5244 iRegIdst tmp;
5245 loadUB_indirect_ac(tmp, mem);
5246 convB2I_reg_2(dst, tmp);
5247 %}
5248 %}
5249
5250 instruct loadUB_indOffset16(iRegIdst dst, indOffset16 mem) %{
5251 // match-rule, false predicate
5252 match(Set dst (LoadB mem));
5253 predicate(false);
5254
5255 format %{ "LBZ $dst, $mem" %}
5256 size(4);
5257 ins_encode( enc_lbz(dst, mem) );
5258 ins_pipe(pipe_class_memory);
5259 %}
5260
5261 instruct loadUB_indOffset16_ac(iRegIdst dst, indOffset16 mem) %{
5262 // match-rule, false predicate
5263 match(Set dst (LoadB mem));
5264 predicate(false);
5265
5266 format %{ "LBZ $dst, $mem\n\t"
5267 "TWI $dst\n\t"
5268 "ISYNC" %}
5269 size(12);
5270 ins_encode( enc_lbz_ac(dst, mem) );
5271 ins_pipe(pipe_class_memory);
5272 %}
5273
5274 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B.
5275 instruct loadB_indOffset16_Ex(iRegIdst dst, indOffset16 mem) %{
5276 match(Set dst (LoadB mem));
5277 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5278 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5279
5280 expand %{
5281 iRegIdst tmp;
5282 loadUB_indOffset16(tmp, mem);
5283 convB2I_reg_2(dst, tmp);
5284 %}
5285 %}
5286
5287 instruct loadB_indOffset16_ac_Ex(iRegIdst dst, indOffset16 mem) %{
5288 match(Set dst (LoadB mem));
5289 ins_cost(3*MEMORY_REF_COST + DEFAULT_COST);
5290
5291 expand %{
5292 iRegIdst tmp;
5293 loadUB_indOffset16_ac(tmp, mem);
5294 convB2I_reg_2(dst, tmp);
5295 %}
5296 %}
5297
5298 // Load Unsigned Byte (8bit UNsigned) into an int reg.
5299 instruct loadUB(iRegIdst dst, memory mem) %{
5300 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5301 match(Set dst (LoadUB mem));
5302 ins_cost(MEMORY_REF_COST);
5303
5304 format %{ "LBZ $dst, $mem \t// byte, zero-extend to int" %}
5305 size(4);
5306 ins_encode( enc_lbz(dst, mem) );
5307 ins_pipe(pipe_class_memory);
5308 %}
5309
5310 // Load Unsigned Byte (8bit UNsigned) acquire.
5311 instruct loadUB_ac(iRegIdst dst, memory mem) %{
5312 match(Set dst (LoadUB mem));
5313 ins_cost(3*MEMORY_REF_COST);
5314
5315 format %{ "LBZ $dst, $mem \t// byte, zero-extend to int, acquire\n\t"
5316 "TWI $dst\n\t"
5317 "ISYNC" %}
5318 size(12);
5319 ins_encode( enc_lbz_ac(dst, mem) );
5320 ins_pipe(pipe_class_memory);
5321 %}
5322
5323 // Load Unsigned Byte (8bit UNsigned) into a Long Register.
5324 instruct loadUB2L(iRegLdst dst, memory mem) %{
5325 match(Set dst (ConvI2L (LoadUB mem)));
5326 predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf));
5327 ins_cost(MEMORY_REF_COST);
5328
5329 format %{ "LBZ $dst, $mem \t// byte, zero-extend to long" %}
5330 size(4);
5331 ins_encode( enc_lbz(dst, mem) );
5332 ins_pipe(pipe_class_memory);
5333 %}
5334
5335 instruct loadUB2L_ac(iRegLdst dst, memory mem) %{
5336 match(Set dst (ConvI2L (LoadUB mem)));
5337 ins_cost(3*MEMORY_REF_COST);
5338
5339 format %{ "LBZ $dst, $mem \t// byte, zero-extend to long, acquire\n\t"
5340 "TWI $dst\n\t"
5341 "ISYNC" %}
5342 size(12);
5343 ins_encode( enc_lbz_ac(dst, mem) );
5344 ins_pipe(pipe_class_memory);
5345 %}
5346
5347 // Load Short (16bit signed)
5348 instruct loadS(iRegIdst dst, memory mem) %{
5349 match(Set dst (LoadS mem));
5350 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5351 ins_cost(MEMORY_REF_COST);
5352
5353 format %{ "LHA $dst, $mem" %}
5354 size(4);
5355 ins_encode %{
5356 // TODO: PPC port $archOpcode(ppc64Opcode_lha);
5357 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5358 __ lha($dst$$Register, Idisp, $mem$$base$$Register);
5359 %}
5360 ins_pipe(pipe_class_memory);
5361 %}
5362
5363 // Load Short (16bit signed) acquire.
5364 instruct loadS_ac(iRegIdst dst, memory mem) %{
5365 match(Set dst (LoadS mem));
5366 ins_cost(3*MEMORY_REF_COST);
5367
5368 format %{ "LHA $dst, $mem\t acquire\n\t"
5369 "TWI $dst\n\t"
5370 "ISYNC" %}
5371 size(12);
5372 ins_encode %{
5373 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5374 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5375 __ lha($dst$$Register, Idisp, $mem$$base$$Register);
5376 __ twi_0($dst$$Register);
5377 __ isync();
5378 %}
5379 ins_pipe(pipe_class_memory);
5380 %}
5381
5382 // Load Char (16bit unsigned)
5383 instruct loadUS(iRegIdst dst, memory mem) %{
5384 match(Set dst (LoadUS mem));
5385 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5386 ins_cost(MEMORY_REF_COST);
5387
5388 format %{ "LHZ $dst, $mem" %}
5389 size(4);
5390 ins_encode( enc_lhz(dst, mem) );
5391 ins_pipe(pipe_class_memory);
5392 %}
5393
5394 // Load Char (16bit unsigned) acquire.
5395 instruct loadUS_ac(iRegIdst dst, memory mem) %{
5396 match(Set dst (LoadUS mem));
5397 ins_cost(3*MEMORY_REF_COST);
5398
5399 format %{ "LHZ $dst, $mem \t// acquire\n\t"
5400 "TWI $dst\n\t"
5401 "ISYNC" %}
5402 size(12);
5403 ins_encode( enc_lhz_ac(dst, mem) );
5404 ins_pipe(pipe_class_memory);
5405 %}
5406
5407 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register.
5408 instruct loadUS2L(iRegLdst dst, memory mem) %{
5409 match(Set dst (ConvI2L (LoadUS mem)));
5410 predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf));
5411 ins_cost(MEMORY_REF_COST);
5412
5413 format %{ "LHZ $dst, $mem \t// short, zero-extend to long" %}
5414 size(4);
5415 ins_encode( enc_lhz(dst, mem) );
5416 ins_pipe(pipe_class_memory);
5417 %}
5418
5419 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register acquire.
5420 instruct loadUS2L_ac(iRegLdst dst, memory mem) %{
5421 match(Set dst (ConvI2L (LoadUS mem)));
5422 ins_cost(3*MEMORY_REF_COST);
5423
5424 format %{ "LHZ $dst, $mem \t// short, zero-extend to long, acquire\n\t"
5425 "TWI $dst\n\t"
5426 "ISYNC" %}
5427 size(12);
5428 ins_encode( enc_lhz_ac(dst, mem) );
5429 ins_pipe(pipe_class_memory);
5430 %}
5431
5432 // Load Integer.
5433 instruct loadI(iRegIdst dst, memory mem) %{
5434 match(Set dst (LoadI mem));
5435 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5436 ins_cost(MEMORY_REF_COST);
5437
5438 format %{ "LWZ $dst, $mem" %}
5439 size(4);
5440 ins_encode( enc_lwz(dst, mem) );
5441 ins_pipe(pipe_class_memory);
5442 %}
5443
5444 // Load Integer acquire.
5445 instruct loadI_ac(iRegIdst dst, memory mem) %{
5446 match(Set dst (LoadI mem));
5447 ins_cost(3*MEMORY_REF_COST);
5448
5449 format %{ "LWZ $dst, $mem \t// load acquire\n\t"
5450 "TWI $dst\n\t"
5451 "ISYNC" %}
5452 size(12);
5453 ins_encode( enc_lwz_ac(dst, mem) );
5454 ins_pipe(pipe_class_memory);
5455 %}
5456
5457 // Match loading integer and casting it to unsigned int in
5458 // long register.
5459 // LoadI + ConvI2L + AndL 0xffffffff.
5460 instruct loadUI2L(iRegLdst dst, memory mem, immL_32bits mask) %{
5461 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5462 predicate(_kids[0]->_kids[0]->_leaf->as_Load()->is_unordered());
5463 ins_cost(MEMORY_REF_COST);
5464
5465 format %{ "LWZ $dst, $mem \t// zero-extend to long" %}
5466 size(4);
5467 ins_encode( enc_lwz(dst, mem) );
5468 ins_pipe(pipe_class_memory);
5469 %}
5470
5471 // Match loading integer and casting it to long.
5472 instruct loadI2L(iRegLdst dst, memory mem) %{
5473 match(Set dst (ConvI2L (LoadI mem)));
5474 predicate(_kids[0]->_leaf->as_Load()->is_unordered());
5475 ins_cost(MEMORY_REF_COST);
5476
5477 format %{ "LWA $dst, $mem \t// loadI2L" %}
5478 size(4);
5479 ins_encode %{
5480 // TODO: PPC port $archOpcode(ppc64Opcode_lwa);
5481 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5482 __ lwa($dst$$Register, Idisp, $mem$$base$$Register);
5483 %}
5484 ins_pipe(pipe_class_memory);
5485 %}
5486
5487 // Match loading integer and casting it to long - acquire.
5488 instruct loadI2L_ac(iRegLdst dst, memory mem) %{
5489 match(Set dst (ConvI2L (LoadI mem)));
5490 ins_cost(3*MEMORY_REF_COST);
5491
5492 format %{ "LWA $dst, $mem \t// loadI2L acquire"
5493 "TWI $dst\n\t"
5494 "ISYNC" %}
5495 size(12);
5496 ins_encode %{
5497 // TODO: PPC port $archOpcode(ppc64Opcode_lwa);
5498 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5499 __ lwa($dst$$Register, Idisp, $mem$$base$$Register);
5500 __ twi_0($dst$$Register);
5501 __ isync();
5502 %}
5503 ins_pipe(pipe_class_memory);
5504 %}
5505
5506 // Load Long - aligned
5507 instruct loadL(iRegLdst dst, memoryAlg4 mem) %{
5508 match(Set dst (LoadL mem));
5509 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5510 ins_cost(MEMORY_REF_COST);
5511
5512 format %{ "LD $dst, $mem \t// long" %}
5513 size(4);
5514 ins_encode( enc_ld(dst, mem) );
5515 ins_pipe(pipe_class_memory);
5516 %}
5517
5518 // Load Long - aligned acquire.
5519 instruct loadL_ac(iRegLdst dst, memoryAlg4 mem) %{
5520 match(Set dst (LoadL mem));
5521 ins_cost(3*MEMORY_REF_COST);
5522
5523 format %{ "LD $dst, $mem \t// long acquire\n\t"
5524 "TWI $dst\n\t"
5525 "ISYNC" %}
5526 size(12);
5527 ins_encode( enc_ld_ac(dst, mem) );
5528 ins_pipe(pipe_class_memory);
5529 %}
5530
5531 // Load Long - UNaligned
5532 instruct loadL_unaligned(iRegLdst dst, memoryAlg4 mem) %{
5533 match(Set dst (LoadL_unaligned mem));
5534 // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense).
5535 ins_cost(MEMORY_REF_COST);
5536
5537 format %{ "LD $dst, $mem \t// unaligned long" %}
5538 size(4);
5539 ins_encode( enc_ld(dst, mem) );
5540 ins_pipe(pipe_class_memory);
5541 %}
5542
5543 // Load nodes for superwords
5544
5545 // Load Aligned Packed Byte
5546 instruct loadV8(iRegLdst dst, memoryAlg4 mem) %{
5547 predicate(n->as_LoadVector()->memory_size() == 8);
5548 match(Set dst (LoadVector mem));
5549 ins_cost(MEMORY_REF_COST);
5550
5551 format %{ "LD $dst, $mem \t// load 8-byte Vector" %}
5552 size(4);
5553 ins_encode( enc_ld(dst, mem) );
5554 ins_pipe(pipe_class_memory);
5555 %}
5556
5557 // Load Range, range = array length (=jint)
5558 instruct loadRange(iRegIdst dst, memory mem) %{
5559 match(Set dst (LoadRange mem));
5560 ins_cost(MEMORY_REF_COST);
5561
5562 format %{ "LWZ $dst, $mem \t// range" %}
5563 size(4);
5564 ins_encode( enc_lwz(dst, mem) );
5565 ins_pipe(pipe_class_memory);
5566 %}
5567
5568 // Load Compressed Pointer
5569 instruct loadN(iRegNdst dst, memory mem) %{
5570 match(Set dst (LoadN mem));
5571 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5572 ins_cost(MEMORY_REF_COST);
5573
5574 format %{ "LWZ $dst, $mem \t// load compressed ptr" %}
5575 size(4);
5576 ins_encode( enc_lwz(dst, mem) );
5577 ins_pipe(pipe_class_memory);
5578 %}
5579
5580 // Load Compressed Pointer acquire.
5581 instruct loadN_ac(iRegNdst dst, memory mem) %{
5582 match(Set dst (LoadN mem));
5583 ins_cost(3*MEMORY_REF_COST);
5584
5585 format %{ "LWZ $dst, $mem \t// load acquire compressed ptr\n\t"
5586 "TWI $dst\n\t"
5587 "ISYNC" %}
5588 size(12);
5589 ins_encode( enc_lwz_ac(dst, mem) );
5590 ins_pipe(pipe_class_memory);
5591 %}
5592
5593 // Load Compressed Pointer and decode it if narrow_oop_shift == 0.
5594 instruct loadN2P_unscaled(iRegPdst dst, memory mem) %{
5595 match(Set dst (DecodeN (LoadN mem)));
5596 predicate(_kids[0]->_leaf->as_Load()->is_unordered() && Universe::narrow_oop_shift() == 0);
5597 ins_cost(MEMORY_REF_COST);
5598
5599 format %{ "LWZ $dst, $mem \t// DecodeN (unscaled)" %}
5600 size(4);
5601 ins_encode( enc_lwz(dst, mem) );
5602 ins_pipe(pipe_class_memory);
5603 %}
5604
5605 // Load Pointer
5606 instruct loadP(iRegPdst dst, memoryAlg4 mem) %{
5607 match(Set dst (LoadP mem));
5608 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5609 ins_cost(MEMORY_REF_COST);
5610
5611 format %{ "LD $dst, $mem \t// ptr" %}
5612 size(4);
5613 ins_encode( enc_ld(dst, mem) );
5614 ins_pipe(pipe_class_memory);
5615 %}
5616
5617 // Load Pointer acquire.
5618 instruct loadP_ac(iRegPdst dst, memoryAlg4 mem) %{
5619 match(Set dst (LoadP mem));
5620 ins_cost(3*MEMORY_REF_COST);
5621
5622 format %{ "LD $dst, $mem \t// ptr acquire\n\t"
5623 "TWI $dst\n\t"
5624 "ISYNC" %}
5625 size(12);
5626 ins_encode( enc_ld_ac(dst, mem) );
5627 ins_pipe(pipe_class_memory);
5628 %}
5629
5630 // LoadP + CastP2L
5631 instruct loadP2X(iRegLdst dst, memoryAlg4 mem) %{
5632 match(Set dst (CastP2X (LoadP mem)));
5633 predicate(_kids[0]->_leaf->as_Load()->is_unordered());
5634 ins_cost(MEMORY_REF_COST);
5635
5636 format %{ "LD $dst, $mem \t// ptr + p2x" %}
5637 size(4);
5638 ins_encode( enc_ld(dst, mem) );
5639 ins_pipe(pipe_class_memory);
5640 %}
5641
5642 // Load compressed klass pointer.
5643 instruct loadNKlass(iRegNdst dst, memory mem) %{
5644 match(Set dst (LoadNKlass mem));
5645 ins_cost(MEMORY_REF_COST);
5646
5647 format %{ "LWZ $dst, $mem \t// compressed klass ptr" %}
5648 size(4);
5649 ins_encode( enc_lwz(dst, mem) );
5650 ins_pipe(pipe_class_memory);
5651 %}
5652
5653 // Load Klass Pointer
5654 instruct loadKlass(iRegPdst dst, memoryAlg4 mem) %{
5655 match(Set dst (LoadKlass mem));
5656 ins_cost(MEMORY_REF_COST);
5657
5658 format %{ "LD $dst, $mem \t// klass ptr" %}
5659 size(4);
5660 ins_encode( enc_ld(dst, mem) );
5661 ins_pipe(pipe_class_memory);
5662 %}
5663
5664 // Load Float
5665 instruct loadF(regF dst, memory mem) %{
5666 match(Set dst (LoadF mem));
5667 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5668 ins_cost(MEMORY_REF_COST);
5669
5670 format %{ "LFS $dst, $mem" %}
5671 size(4);
5672 ins_encode %{
5673 // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
5674 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5675 __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5676 %}
5677 ins_pipe(pipe_class_memory);
5678 %}
5679
5680 // Load Float acquire.
5681 instruct loadF_ac(regF dst, memory mem) %{
5682 match(Set dst (LoadF mem));
5683 ins_cost(3*MEMORY_REF_COST);
5684
5685 format %{ "LFS $dst, $mem \t// acquire\n\t"
5686 "FCMPU cr0, $dst, $dst\n\t"
5687 "BNE cr0, next\n"
5688 "next:\n\t"
5689 "ISYNC" %}
5690 size(16);
5691 ins_encode %{
5692 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5693 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5694 Label next;
5695 __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5696 __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister);
5697 __ bne(CCR0, next);
5698 __ bind(next);
5699 __ isync();
5700 %}
5701 ins_pipe(pipe_class_memory);
5702 %}
5703
5704 // Load Double - aligned
5705 instruct loadD(regD dst, memory mem) %{
5706 match(Set dst (LoadD mem));
5707 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5708 ins_cost(MEMORY_REF_COST);
5709
5710 format %{ "LFD $dst, $mem" %}
5711 size(4);
5712 ins_encode( enc_lfd(dst, mem) );
5713 ins_pipe(pipe_class_memory);
5714 %}
5715
5716 // Load Double - aligned acquire.
5717 instruct loadD_ac(regD dst, memory mem) %{
5718 match(Set dst (LoadD mem));
5719 ins_cost(3*MEMORY_REF_COST);
5720
5721 format %{ "LFD $dst, $mem \t// acquire\n\t"
5722 "FCMPU cr0, $dst, $dst\n\t"
5723 "BNE cr0, next\n"
5724 "next:\n\t"
5725 "ISYNC" %}
5726 size(16);
5727 ins_encode %{
5728 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5729 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5730 Label next;
5731 __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5732 __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister);
5733 __ bne(CCR0, next);
5734 __ bind(next);
5735 __ isync();
5736 %}
5737 ins_pipe(pipe_class_memory);
5738 %}
5739
5740 // Load Double - UNaligned
5741 instruct loadD_unaligned(regD dst, memory mem) %{
5742 match(Set dst (LoadD_unaligned mem));
5743 // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense).
5744 ins_cost(MEMORY_REF_COST);
5745
5746 format %{ "LFD $dst, $mem" %}
5747 size(4);
5748 ins_encode( enc_lfd(dst, mem) );
5749 ins_pipe(pipe_class_memory);
5750 %}
5751
5752 //----------Constants--------------------------------------------------------
5753
5754 // Load MachConstantTableBase: add hi offset to global toc.
5755 // TODO: Handle hidden register r29 in bundler!
5756 instruct loadToc_hi(iRegLdst dst) %{
5757 effect(DEF dst);
5758 ins_cost(DEFAULT_COST);
5759
5760 format %{ "ADDIS $dst, R29, DISP.hi \t// load TOC hi" %}
5761 size(4);
5762 ins_encode %{
5763 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5764 __ calculate_address_from_global_toc_hi16only($dst$$Register, __ method_toc());
5765 %}
5766 ins_pipe(pipe_class_default);
5767 %}
5768
5769 // Load MachConstantTableBase: add lo offset to global toc.
5770 instruct loadToc_lo(iRegLdst dst, iRegLdst src) %{
5771 effect(DEF dst, USE src);
5772 ins_cost(DEFAULT_COST);
5773
5774 format %{ "ADDI $dst, $src, DISP.lo \t// load TOC lo" %}
5775 size(4);
5776 ins_encode %{
5777 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5778 __ calculate_address_from_global_toc_lo16only($dst$$Register, __ method_toc());
5779 %}
5780 ins_pipe(pipe_class_default);
5781 %}
5782
5783 // Load 16-bit integer constant 0xssss????
5784 instruct loadConI16(iRegIdst dst, immI16 src) %{
5785 match(Set dst src);
5786
5787 format %{ "LI $dst, $src" %}
5788 size(4);
5789 ins_encode %{
5790 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5791 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
5792 %}
5793 ins_pipe(pipe_class_default);
5794 %}
5795
5796 // Load integer constant 0x????0000
5797 instruct loadConIhi16(iRegIdst dst, immIhi16 src) %{
5798 match(Set dst src);
5799 ins_cost(DEFAULT_COST);
5800
5801 format %{ "LIS $dst, $src.hi" %}
5802 size(4);
5803 ins_encode %{
5804 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5805 // Lis sign extends 16-bit src then shifts it 16 bit to the left.
5806 __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16)));
5807 %}
5808 ins_pipe(pipe_class_default);
5809 %}
5810
5811 // Part 2 of loading 32 bit constant: hi16 is is src1 (properly shifted
5812 // and sign extended), this adds the low 16 bits.
5813 instruct loadConI32_lo16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
5814 // no match-rule, false predicate
5815 effect(DEF dst, USE src1, USE src2);
5816 predicate(false);
5817
5818 format %{ "ORI $dst, $src1.hi, $src2.lo" %}
5819 size(4);
5820 ins_encode %{
5821 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5822 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
5823 %}
5824 ins_pipe(pipe_class_default);
5825 %}
5826
5827 instruct loadConI_Ex(iRegIdst dst, immI src) %{
5828 match(Set dst src);
5829 ins_cost(DEFAULT_COST*2);
5830
5831 expand %{
5832 // Would like to use $src$$constant.
5833 immI16 srcLo %{ _opnds[1]->constant() %}
5834 // srcHi can be 0000 if srcLo sign-extends to a negative number.
5835 immIhi16 srcHi %{ _opnds[1]->constant() %}
5836 iRegIdst tmpI;
5837 loadConIhi16(tmpI, srcHi);
5838 loadConI32_lo16(dst, tmpI, srcLo);
5839 %}
5840 %}
5841
5842 // No constant pool entries required.
5843 instruct loadConL16(iRegLdst dst, immL16 src) %{
5844 match(Set dst src);
5845
5846 format %{ "LI $dst, $src \t// long" %}
5847 size(4);
5848 ins_encode %{
5849 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5850 __ li($dst$$Register, (int)((short) ($src$$constant & 0xFFFF)));
5851 %}
5852 ins_pipe(pipe_class_default);
5853 %}
5854
5855 // Load long constant 0xssssssss????0000
5856 instruct loadConL32hi16(iRegLdst dst, immL32hi16 src) %{
5857 match(Set dst src);
5858 ins_cost(DEFAULT_COST);
5859
5860 format %{ "LIS $dst, $src.hi \t// long" %}
5861 size(4);
5862 ins_encode %{
5863 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5864 __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16)));
5865 %}
5866 ins_pipe(pipe_class_default);
5867 %}
5868
5869 // To load a 32 bit constant: merge lower 16 bits into already loaded
5870 // high 16 bits.
5871 instruct loadConL32_lo16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
5872 // no match-rule, false predicate
5873 effect(DEF dst, USE src1, USE src2);
5874 predicate(false);
5875
5876 format %{ "ORI $dst, $src1, $src2.lo" %}
5877 size(4);
5878 ins_encode %{
5879 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5880 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
5881 %}
5882 ins_pipe(pipe_class_default);
5883 %}
5884
5885 // Load 32-bit long constant
5886 instruct loadConL32_Ex(iRegLdst dst, immL32 src) %{
5887 match(Set dst src);
5888 ins_cost(DEFAULT_COST*2);
5889
5890 expand %{
5891 // Would like to use $src$$constant.
5892 immL16 srcLo %{ _opnds[1]->constant() /*& 0x0000FFFFL */%}
5893 // srcHi can be 0000 if srcLo sign-extends to a negative number.
5894 immL32hi16 srcHi %{ _opnds[1]->constant() /*& 0xFFFF0000L */%}
5895 iRegLdst tmpL;
5896 loadConL32hi16(tmpL, srcHi);
5897 loadConL32_lo16(dst, tmpL, srcLo);
5898 %}
5899 %}
5900
5901 // Load long constant 0x????000000000000.
5902 instruct loadConLhighest16_Ex(iRegLdst dst, immLhighest16 src) %{
5903 match(Set dst src);
5904 ins_cost(DEFAULT_COST);
5905
5906 expand %{
5907 immL32hi16 srcHi %{ _opnds[1]->constant() >> 32 /*& 0xFFFF0000L */%}
5908 immI shift32 %{ 32 %}
5909 iRegLdst tmpL;
5910 loadConL32hi16(tmpL, srcHi);
5911 lshiftL_regL_immI(dst, tmpL, shift32);
5912 %}
5913 %}
5914
5915 // Expand node for constant pool load: small offset.
5916 instruct loadConL(iRegLdst dst, immL src, iRegLdst toc) %{
5917 effect(DEF dst, USE src, USE toc);
5918 ins_cost(MEMORY_REF_COST);
5919
5920 ins_num_consts(1);
5921 // Needed so that CallDynamicJavaDirect can compute the address of this
5922 // instruction for relocation.
5923 ins_field_cbuf_insts_offset(int);
5924
5925 format %{ "LD $dst, offset, $toc \t// load long $src from TOC" %}
5926 size(4);
5927 ins_encode( enc_load_long_constL(dst, src, toc) );
5928 ins_pipe(pipe_class_memory);
5929 %}
5930
5931 // Expand node for constant pool load: large offset.
5932 instruct loadConL_hi(iRegLdst dst, immL src, iRegLdst toc) %{
5933 effect(DEF dst, USE src, USE toc);
5934 predicate(false);
5935
5936 ins_num_consts(1);
5937 ins_field_const_toc_offset(int);
5938 // Needed so that CallDynamicJavaDirect can compute the address of this
5939 // instruction for relocation.
5940 ins_field_cbuf_insts_offset(int);
5941
5942 format %{ "ADDIS $dst, $toc, offset \t// load long $src from TOC (hi)" %}
5943 size(4);
5944 ins_encode( enc_load_long_constL_hi(dst, toc, src) );
5945 ins_pipe(pipe_class_default);
5946 %}
5947
5948 // Expand node for constant pool load: large offset.
5949 // No constant pool entries required.
5950 instruct loadConL_lo(iRegLdst dst, immL src, iRegLdst base) %{
5951 effect(DEF dst, USE src, USE base);
5952 predicate(false);
5953
5954 ins_field_const_toc_offset_hi_node(loadConL_hiNode*);
5955
5956 format %{ "LD $dst, offset, $base \t// load long $src from TOC (lo)" %}
5957 size(4);
5958 ins_encode %{
5959 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
5960 int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset;
5961 __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register);
5962 %}
5963 ins_pipe(pipe_class_memory);
5964 %}
5965
5966 // Load long constant from constant table. Expand in case of
5967 // offset > 16 bit is needed.
5968 // Adlc adds toc node MachConstantTableBase.
5969 instruct loadConL_Ex(iRegLdst dst, immL src) %{
5970 match(Set dst src);
5971 ins_cost(MEMORY_REF_COST);
5972
5973 format %{ "LD $dst, offset, $constanttablebase\t// load long $src from table, postalloc expanded" %}
5974 // We can not inline the enc_class for the expand as that does not support constanttablebase.
5975 postalloc_expand( postalloc_expand_load_long_constant(dst, src, constanttablebase) );
5976 %}
5977
5978 // Load NULL as compressed oop.
5979 instruct loadConN0(iRegNdst dst, immN_0 src) %{
5980 match(Set dst src);
5981 ins_cost(DEFAULT_COST);
5982
5983 format %{ "LI $dst, $src \t// compressed ptr" %}
5984 size(4);
5985 ins_encode %{
5986 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5987 __ li($dst$$Register, 0);
5988 %}
5989 ins_pipe(pipe_class_default);
5990 %}
5991
5992 // Load hi part of compressed oop constant.
5993 instruct loadConN_hi(iRegNdst dst, immN src) %{
5994 effect(DEF dst, USE src);
5995 ins_cost(DEFAULT_COST);
5996
5997 format %{ "LIS $dst, $src \t// narrow oop hi" %}
5998 size(4);
5999 ins_encode %{
6000 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
6001 __ lis($dst$$Register, (int)(short)(($src$$constant >> 16) & 0xffff));
6002 %}
6003 ins_pipe(pipe_class_default);
6004 %}
6005
6006 // Add lo part of compressed oop constant to already loaded hi part.
6007 instruct loadConN_lo(iRegNdst dst, iRegNsrc src1, immN src2) %{
6008 effect(DEF dst, USE src1, USE src2);
6009 ins_cost(DEFAULT_COST);
6010
6011 format %{ "ORI $dst, $src1, $src2 \t// narrow oop lo" %}
6012 size(4);
6013 ins_encode %{
6014 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
6015 assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder");
6016 int oop_index = __ oop_recorder()->find_index((jobject)$src2$$constant);
6017 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6018 __ relocate(rspec, 1);
6019 __ ori($dst$$Register, $src1$$Register, $src2$$constant & 0xffff);
6020 %}
6021 ins_pipe(pipe_class_default);
6022 %}
6023
6024 // Needed to postalloc expand loadConN: ConN is loaded as ConI
6025 // leaving the upper 32 bits with sign-extension bits.
6026 // This clears these bits: dst = src & 0xFFFFFFFF.
6027 // TODO: Eventually call this maskN_regN_FFFFFFFF.
6028 instruct clearMs32b(iRegNdst dst, iRegNsrc src) %{
6029 effect(DEF dst, USE src);
6030 predicate(false);
6031
6032 format %{ "MASK $dst, $src, 0xFFFFFFFF" %} // mask
6033 size(4);
6034 ins_encode %{
6035 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6036 __ clrldi($dst$$Register, $src$$Register, 0x20);
6037 %}
6038 ins_pipe(pipe_class_default);
6039 %}
6040
6041 // Loading ConN must be postalloc expanded so that edges between
6042 // the nodes are safe. They may not interfere with a safepoint.
6043 // GL TODO: This needs three instructions: better put this into the constant pool.
6044 instruct loadConN_Ex(iRegNdst dst, immN src) %{
6045 match(Set dst src);
6046 ins_cost(DEFAULT_COST*2);
6047
6048 format %{ "LoadN $dst, $src \t// postalloc expanded" %} // mask
6049 postalloc_expand %{
6050 MachNode *m1 = new (C) loadConN_hiNode();
6051 MachNode *m2 = new (C) loadConN_loNode();
6052 MachNode *m3 = new (C) clearMs32bNode();
6053 m1->add_req(NULL);
6054 m2->add_req(NULL, m1);
6055 m3->add_req(NULL, m2);
6056 m1->_opnds[0] = op_dst;
6057 m1->_opnds[1] = op_src;
6058 m2->_opnds[0] = op_dst;
6059 m2->_opnds[1] = op_dst;
6060 m2->_opnds[2] = op_src;
6061 m3->_opnds[0] = op_dst;
6062 m3->_opnds[1] = op_dst;
6063 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6064 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6065 ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6066 nodes->push(m1);
6067 nodes->push(m2);
6068 nodes->push(m3);
6069 %}
6070 %}
6071
6072 // We have seen a safepoint between the hi and lo parts, and this node was handled
6073 // as an oop. Therefore this needs a match rule so that build_oop_map knows this is
6074 // not a narrow oop.
6075 instruct loadConNKlass_hi(iRegNdst dst, immNKlass_NM src) %{
6076 match(Set dst src);
6077 effect(DEF dst, USE src);
6078 ins_cost(DEFAULT_COST);
6079
6080 format %{ "LIS $dst, $src \t// narrow klass hi" %}
6081 size(4);
6082 ins_encode %{
6083 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
6084 intptr_t Csrc = Klass::encode_klass((Klass *)$src$$constant);
6085 __ lis($dst$$Register, (int)(short)((Csrc >> 16) & 0xffff));
6086 %}
6087 ins_pipe(pipe_class_default);
6088 %}
6089
6090 // As loadConNKlass_hi this must be recognized as narrow klass, not oop!
6091 instruct loadConNKlass_mask(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{
6092 match(Set dst src1);
6093 effect(TEMP src2);
6094 ins_cost(DEFAULT_COST);
6095
6096 format %{ "MASK $dst, $src2, 0xFFFFFFFF" %} // mask
6097 size(4);
6098 ins_encode %{
6099 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6100 __ clrldi($dst$$Register, $src2$$Register, 0x20);
6101 %}
6102 ins_pipe(pipe_class_default);
6103 %}
6104
6105 // This needs a match rule so that build_oop_map knows this is
6106 // not a narrow oop.
6107 instruct loadConNKlass_lo(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{
6108 match(Set dst src1);
6109 effect(TEMP src2);
6110 ins_cost(DEFAULT_COST);
6111
6112 format %{ "ORI $dst, $src1, $src2 \t// narrow klass lo" %}
6113 size(4);
6114 ins_encode %{
6115 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
6116 intptr_t Csrc = Klass::encode_klass((Klass *)$src1$$constant);
6117 assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder");
6118 int klass_index = __ oop_recorder()->find_index((Klass *)$src1$$constant);
6119 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6120
6121 __ relocate(rspec, 1);
6122 __ ori($dst$$Register, $src2$$Register, Csrc & 0xffff);
6123 %}
6124 ins_pipe(pipe_class_default);
6125 %}
6126
6127 // Loading ConNKlass must be postalloc expanded so that edges between
6128 // the nodes are safe. They may not interfere with a safepoint.
6129 instruct loadConNKlass_Ex(iRegNdst dst, immNKlass src) %{
6130 match(Set dst src);
6131 ins_cost(DEFAULT_COST*2);
6132
6133 format %{ "LoadN $dst, $src \t// postalloc expanded" %} // mask
6134 postalloc_expand %{
6135 // Load high bits into register. Sign extended.
6136 MachNode *m1 = new (C) loadConNKlass_hiNode();
6137 m1->add_req(NULL);
6138 m1->_opnds[0] = op_dst;
6139 m1->_opnds[1] = op_src;
6140 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6141 nodes->push(m1);
6142
6143 MachNode *m2 = m1;
6144 if (!Assembler::is_uimm((jlong)Klass::encode_klass((Klass *)op_src->constant()), 31)) {
6145 // Value might be 1-extended. Mask out these bits.
6146 m2 = new (C) loadConNKlass_maskNode();
6147 m2->add_req(NULL, m1);
6148 m2->_opnds[0] = op_dst;
6149 m2->_opnds[1] = op_src;
6150 m2->_opnds[2] = op_dst;
6151 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6152 nodes->push(m2);
6153 }
6154
6155 MachNode *m3 = new (C) loadConNKlass_loNode();
6156 m3->add_req(NULL, m2);
6157 m3->_opnds[0] = op_dst;
6158 m3->_opnds[1] = op_src;
6159 m3->_opnds[2] = op_dst;
6160 ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6161 nodes->push(m3);
6162 %}
6163 %}
6164
6165 // 0x1 is used in object initialization (initial object header).
6166 // No constant pool entries required.
6167 instruct loadConP0or1(iRegPdst dst, immP_0or1 src) %{
6168 match(Set dst src);
6169
6170 format %{ "LI $dst, $src \t// ptr" %}
6171 size(4);
6172 ins_encode %{
6173 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
6174 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
6175 %}
6176 ins_pipe(pipe_class_default);
6177 %}
6178
6179 // Expand node for constant pool load: small offset.
6180 // The match rule is needed to generate the correct bottom_type(),
6181 // however this node should never match. The use of predicate is not
6182 // possible since ADLC forbids predicates for chain rules. The higher
6183 // costs do not prevent matching in this case. For that reason the
6184 // operand immP_NM with predicate(false) is used.
6185 instruct loadConP(iRegPdst dst, immP_NM src, iRegLdst toc) %{
6186 match(Set dst src);
6187 effect(TEMP toc);
6188
6189 ins_num_consts(1);
6190
6191 format %{ "LD $dst, offset, $toc \t// load ptr $src from TOC" %}
6192 size(4);
6193 ins_encode( enc_load_long_constP(dst, src, toc) );
6194 ins_pipe(pipe_class_memory);
6195 %}
6196
6197 // Expand node for constant pool load: large offset.
6198 instruct loadConP_hi(iRegPdst dst, immP_NM src, iRegLdst toc) %{
6199 effect(DEF dst, USE src, USE toc);
6200 predicate(false);
6201
6202 ins_num_consts(1);
6203 ins_field_const_toc_offset(int);
6204
6205 format %{ "ADDIS $dst, $toc, offset \t// load ptr $src from TOC (hi)" %}
6206 size(4);
6207 ins_encode( enc_load_long_constP_hi(dst, src, toc) );
6208 ins_pipe(pipe_class_default);
6209 %}
6210
6211 // Expand node for constant pool load: large offset.
6212 instruct loadConP_lo(iRegPdst dst, immP_NM src, iRegLdst base) %{
6213 match(Set dst src);
6214 effect(TEMP base);
6215
6216 ins_field_const_toc_offset_hi_node(loadConP_hiNode*);
6217
6218 format %{ "LD $dst, offset, $base \t// load ptr $src from TOC (lo)" %}
6219 size(4);
6220 ins_encode %{
6221 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
6222 int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset;
6223 __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register);
6224 %}
6225 ins_pipe(pipe_class_memory);
6226 %}
6227
6228 // Load pointer constant from constant table. Expand in case an
6229 // offset > 16 bit is needed.
6230 // Adlc adds toc node MachConstantTableBase.
6231 instruct loadConP_Ex(iRegPdst dst, immP src) %{
6232 match(Set dst src);
6233 ins_cost(MEMORY_REF_COST);
6234
6235 // This rule does not use "expand" because then
6236 // the result type is not known to be an Oop. An ADLC
6237 // enhancement will be needed to make that work - not worth it!
6238
6239 // If this instruction rematerializes, it prolongs the live range
6240 // of the toc node, causing illegal graphs.
6241 // assert(edge_from_to(_reg_node[reg_lo],def)) fails in verify_good_schedule().
6242 ins_cannot_rematerialize(true);
6243
6244 format %{ "LD $dst, offset, $constanttablebase \t// load ptr $src from table, postalloc expanded" %}
6245 postalloc_expand( postalloc_expand_load_ptr_constant(dst, src, constanttablebase) );
6246 %}
6247
6248 // Expand node for constant pool load: small offset.
6249 instruct loadConF(regF dst, immF src, iRegLdst toc) %{
6250 effect(DEF dst, USE src, USE toc);
6251 ins_cost(MEMORY_REF_COST);
6252
6253 ins_num_consts(1);
6254
6255 format %{ "LFS $dst, offset, $toc \t// load float $src from TOC" %}
6256 size(4);
6257 ins_encode %{
6258 // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
6259 address float_address = __ float_constant($src$$constant);
6260 __ lfs($dst$$FloatRegister, __ offset_to_method_toc(float_address), $toc$$Register);
6261 %}
6262 ins_pipe(pipe_class_memory);
6263 %}
6264
6265 // Expand node for constant pool load: large offset.
6266 instruct loadConFComp(regF dst, immF src, iRegLdst toc) %{
6267 effect(DEF dst, USE src, USE toc);
6268 ins_cost(MEMORY_REF_COST);
6269
6270 ins_num_consts(1);
6271
6272 format %{ "ADDIS $toc, $toc, offset_hi\n\t"
6273 "LFS $dst, offset_lo, $toc \t// load float $src from TOC (hi/lo)\n\t"
6274 "ADDIS $toc, $toc, -offset_hi"%}
6275 size(12);
6276 ins_encode %{
6277 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6278 FloatRegister Rdst = $dst$$FloatRegister;
6279 Register Rtoc = $toc$$Register;
6280 address float_address = __ float_constant($src$$constant);
6281 int offset = __ offset_to_method_toc(float_address);
6282 int hi = (offset + (1<<15))>>16;
6283 int lo = offset - hi * (1<<16);
6284
6285 __ addis(Rtoc, Rtoc, hi);
6286 __ lfs(Rdst, lo, Rtoc);
6287 __ addis(Rtoc, Rtoc, -hi);
6288 %}
6289 ins_pipe(pipe_class_memory);
6290 %}
6291
6292 // Adlc adds toc node MachConstantTableBase.
6293 instruct loadConF_Ex(regF dst, immF src) %{
6294 match(Set dst src);
6295 ins_cost(MEMORY_REF_COST);
6296
6297 // See loadConP.
6298 ins_cannot_rematerialize(true);
6299
6300 format %{ "LFS $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %}
6301 postalloc_expand( postalloc_expand_load_float_constant(dst, src, constanttablebase) );
6302 %}
6303
6304 // Expand node for constant pool load: small offset.
6305 instruct loadConD(regD dst, immD src, iRegLdst toc) %{
6306 effect(DEF dst, USE src, USE toc);
6307 ins_cost(MEMORY_REF_COST);
6308
6309 ins_num_consts(1);
6310
6311 format %{ "LFD $dst, offset, $toc \t// load double $src from TOC" %}
6312 size(4);
6313 ins_encode %{
6314 // TODO: PPC port $archOpcode(ppc64Opcode_lfd);
6315 int offset = __ offset_to_method_toc(__ double_constant($src$$constant));
6316 __ lfd($dst$$FloatRegister, offset, $toc$$Register);
6317 %}
6318 ins_pipe(pipe_class_memory);
6319 %}
6320
6321 // Expand node for constant pool load: large offset.
6322 instruct loadConDComp(regD dst, immD src, iRegLdst toc) %{
6323 effect(DEF dst, USE src, USE toc);
6324 ins_cost(MEMORY_REF_COST);
6325
6326 ins_num_consts(1);
6327
6328 format %{ "ADDIS $toc, $toc, offset_hi\n\t"
6329 "LFD $dst, offset_lo, $toc \t// load double $src from TOC (hi/lo)\n\t"
6330 "ADDIS $toc, $toc, -offset_hi" %}
6331 size(12);
6332 ins_encode %{
6333 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6334 FloatRegister Rdst = $dst$$FloatRegister;
6335 Register Rtoc = $toc$$Register;
6336 address float_address = __ double_constant($src$$constant);
6337 int offset = __ offset_to_method_toc(float_address);
6338 int hi = (offset + (1<<15))>>16;
6339 int lo = offset - hi * (1<<16);
6340
6341 __ addis(Rtoc, Rtoc, hi);
6342 __ lfd(Rdst, lo, Rtoc);
6343 __ addis(Rtoc, Rtoc, -hi);
6344 %}
6345 ins_pipe(pipe_class_memory);
6346 %}
6347
6348 // Adlc adds toc node MachConstantTableBase.
6349 instruct loadConD_Ex(regD dst, immD src) %{
6350 match(Set dst src);
6351 ins_cost(MEMORY_REF_COST);
6352
6353 // See loadConP.
6354 ins_cannot_rematerialize(true);
6355
6356 format %{ "ConD $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %}
6357 postalloc_expand( postalloc_expand_load_double_constant(dst, src, constanttablebase) );
6358 %}
6359
6360 // Prefetch instructions.
6361 // Must be safe to execute with invalid address (cannot fault).
6362
6363 instruct prefetchr(indirectMemory mem, iRegLsrc src) %{
6364 match(PrefetchRead (AddP mem src));
6365 ins_cost(MEMORY_REF_COST);
6366
6367 format %{ "PREFETCH $mem, 0, $src \t// Prefetch read-many" %}
6368 size(4);
6369 ins_encode %{
6370 // TODO: PPC port $archOpcode(ppc64Opcode_dcbt);
6371 __ dcbt($src$$Register, $mem$$base$$Register);
6372 %}
6373 ins_pipe(pipe_class_memory);
6374 %}
6375
6376 instruct prefetchr_no_offset(indirectMemory mem) %{
6377 match(PrefetchRead mem);
6378 ins_cost(MEMORY_REF_COST);
6379
6380 format %{ "PREFETCH $mem" %}
6381 size(4);
6382 ins_encode %{
6383 // TODO: PPC port $archOpcode(ppc64Opcode_dcbt);
6384 __ dcbt($mem$$base$$Register);
6385 %}
6386 ins_pipe(pipe_class_memory);
6387 %}
6388
6389 instruct prefetchw(indirectMemory mem, iRegLsrc src) %{
6390 match(PrefetchWrite (AddP mem src));
6391 ins_cost(MEMORY_REF_COST);
6392
6393 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many (and read)" %}
6394 size(4);
6395 ins_encode %{
6396 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6397 __ dcbtst($src$$Register, $mem$$base$$Register);
6398 %}
6399 ins_pipe(pipe_class_memory);
6400 %}
6401
6402 instruct prefetchw_no_offset(indirectMemory mem) %{
6403 match(PrefetchWrite mem);
6404 ins_cost(MEMORY_REF_COST);
6405
6406 format %{ "PREFETCH $mem" %}
6407 size(4);
6408 ins_encode %{
6409 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6410 __ dcbtst($mem$$base$$Register);
6411 %}
6412 ins_pipe(pipe_class_memory);
6413 %}
6414
6415 // Special prefetch versions which use the dcbz instruction.
6416 instruct prefetch_alloc_zero(indirectMemory mem, iRegLsrc src) %{
6417 match(PrefetchAllocation (AddP mem src));
6418 predicate(AllocatePrefetchStyle == 3);
6419 ins_cost(MEMORY_REF_COST);
6420
6421 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many with zero" %}
6422 size(4);
6423 ins_encode %{
6424 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6425 __ dcbz($src$$Register, $mem$$base$$Register);
6426 %}
6427 ins_pipe(pipe_class_memory);
6428 %}
6429
6430 instruct prefetch_alloc_zero_no_offset(indirectMemory mem) %{
6431 match(PrefetchAllocation mem);
6432 predicate(AllocatePrefetchStyle == 3);
6433 ins_cost(MEMORY_REF_COST);
6434
6435 format %{ "PREFETCH $mem, 2 \t// Prefetch write-many with zero" %}
6436 size(4);
6437 ins_encode %{
6438 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6439 __ dcbz($mem$$base$$Register);
6440 %}
6441 ins_pipe(pipe_class_memory);
6442 %}
6443
6444 instruct prefetch_alloc(indirectMemory mem, iRegLsrc src) %{
6445 match(PrefetchAllocation (AddP mem src));
6446 predicate(AllocatePrefetchStyle != 3);
6447 ins_cost(MEMORY_REF_COST);
6448
6449 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many" %}
6450 size(4);
6451 ins_encode %{
6452 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6453 __ dcbtst($src$$Register, $mem$$base$$Register);
6454 %}
6455 ins_pipe(pipe_class_memory);
6456 %}
6457
6458 instruct prefetch_alloc_no_offset(indirectMemory mem) %{
6459 match(PrefetchAllocation mem);
6460 predicate(AllocatePrefetchStyle != 3);
6461 ins_cost(MEMORY_REF_COST);
6462
6463 format %{ "PREFETCH $mem, 2 \t// Prefetch write-many" %}
6464 size(4);
6465 ins_encode %{
6466 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6467 __ dcbtst($mem$$base$$Register);
6468 %}
6469 ins_pipe(pipe_class_memory);
6470 %}
6471
6472 //----------Store Instructions-------------------------------------------------
6473
6474 // Store Byte
6475 instruct storeB(memory mem, iRegIsrc src) %{
6476 match(Set mem (StoreB mem src));
6477 ins_cost(MEMORY_REF_COST);
6478
6479 format %{ "STB $src, $mem \t// byte" %}
6480 size(4);
6481 ins_encode %{
6482 // TODO: PPC port $archOpcode(ppc64Opcode_stb);
6483 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
6484 __ stb($src$$Register, Idisp, $mem$$base$$Register);
6485 %}
6486 ins_pipe(pipe_class_memory);
6487 %}
6488
6489 // Store Char/Short
6490 instruct storeC(memory mem, iRegIsrc src) %{
6491 match(Set mem (StoreC mem src));
6492 ins_cost(MEMORY_REF_COST);
6493
6494 format %{ "STH $src, $mem \t// short" %}
6495 size(4);
6496 ins_encode %{
6497 // TODO: PPC port $archOpcode(ppc64Opcode_sth);
6498 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
6499 __ sth($src$$Register, Idisp, $mem$$base$$Register);
6500 %}
6501 ins_pipe(pipe_class_memory);
6502 %}
6503
6504 // Store Integer
6505 instruct storeI(memory mem, iRegIsrc src) %{
6506 match(Set mem (StoreI mem src));
6507 ins_cost(MEMORY_REF_COST);
6508
6509 format %{ "STW $src, $mem" %}
6510 size(4);
6511 ins_encode( enc_stw(src, mem) );
6512 ins_pipe(pipe_class_memory);
6513 %}
6514
6515 // ConvL2I + StoreI.
6516 instruct storeI_convL2I(memory mem, iRegLsrc src) %{
6517 match(Set mem (StoreI mem (ConvL2I src)));
6518 ins_cost(MEMORY_REF_COST);
6519
6520 format %{ "STW l2i($src), $mem" %}
6521 size(4);
6522 ins_encode( enc_stw(src, mem) );
6523 ins_pipe(pipe_class_memory);
6524 %}
6525
6526 // Store Long
6527 instruct storeL(memoryAlg4 mem, iRegLsrc src) %{
6528 match(Set mem (StoreL mem src));
6529 ins_cost(MEMORY_REF_COST);
6530
6531 format %{ "STD $src, $mem \t// long" %}
6532 size(4);
6533 ins_encode( enc_std(src, mem) );
6534 ins_pipe(pipe_class_memory);
6535 %}
6536
6537 // Store super word nodes.
6538
6539 // Store Aligned Packed Byte long register to memory
6540 instruct storeA8B(memoryAlg4 mem, iRegLsrc src) %{
6541 predicate(n->as_StoreVector()->memory_size() == 8);
6542 match(Set mem (StoreVector mem src));
6543 ins_cost(MEMORY_REF_COST);
6544
6545 format %{ "STD $mem, $src \t// packed8B" %}
6546 size(4);
6547 ins_encode( enc_std(src, mem) );
6548 ins_pipe(pipe_class_memory);
6549 %}
6550
6551 // Store Compressed Oop
6552 instruct storeN(memory dst, iRegN_P2N src) %{
6553 match(Set dst (StoreN dst src));
6554 ins_cost(MEMORY_REF_COST);
6555
6556 format %{ "STW $src, $dst \t// compressed oop" %}
6557 size(4);
6558 ins_encode( enc_stw(src, dst) );
6559 ins_pipe(pipe_class_memory);
6560 %}
6561
6562 // Store Compressed KLass
6563 instruct storeNKlass(memory dst, iRegN_P2N src) %{
6564 match(Set dst (StoreNKlass dst src));
6565 ins_cost(MEMORY_REF_COST);
6566
6567 format %{ "STW $src, $dst \t// compressed klass" %}
6568 size(4);
6569 ins_encode( enc_stw(src, dst) );
6570 ins_pipe(pipe_class_memory);
6571 %}
6572
6573 // Store Pointer
6574 instruct storeP(memoryAlg4 dst, iRegPsrc src) %{
6575 match(Set dst (StoreP dst src));
6576 ins_cost(MEMORY_REF_COST);
6577
6578 format %{ "STD $src, $dst \t// ptr" %}
6579 size(4);
6580 ins_encode( enc_std(src, dst) );
6581 ins_pipe(pipe_class_memory);
6582 %}
6583
6584 // Store Float
6585 instruct storeF(memory mem, regF src) %{
6586 match(Set mem (StoreF mem src));
6587 ins_cost(MEMORY_REF_COST);
6588
6589 format %{ "STFS $src, $mem" %}
6590 size(4);
6591 ins_encode( enc_stfs(src, mem) );
6592 ins_pipe(pipe_class_memory);
6593 %}
6594
6595 // Store Double
6596 instruct storeD(memory mem, regD src) %{
6597 match(Set mem (StoreD mem src));
6598 ins_cost(MEMORY_REF_COST);
6599
6600 format %{ "STFD $src, $mem" %}
6601 size(4);
6602 ins_encode( enc_stfd(src, mem) );
6603 ins_pipe(pipe_class_memory);
6604 %}
6605
6606 //----------Store Instructions With Zeros--------------------------------------
6607
6608 // Card-mark for CMS garbage collection.
6609 // This cardmark does an optimization so that it must not always
6610 // do a releasing store. For this, it gets the address of
6611 // CMSCollectorCardTableModRefBSExt::_requires_release as input.
6612 // (Using releaseFieldAddr in the match rule is a hack.)
6613 instruct storeCM_CMS(memory mem, iRegLdst releaseFieldAddr) %{
6614 match(Set mem (StoreCM mem releaseFieldAddr));
6615 predicate(false);
6616 ins_cost(MEMORY_REF_COST);
6617
6618 // See loadConP.
6619 ins_cannot_rematerialize(true);
6620
6621 format %{ "STB #0, $mem \t// CMS card-mark byte (must be 0!), checking requires_release in [$releaseFieldAddr]" %}
6622 ins_encode( enc_cms_card_mark(mem, releaseFieldAddr) );
6623 ins_pipe(pipe_class_memory);
6624 %}
6625
6626 // Card-mark for CMS garbage collection.
6627 // This cardmark does an optimization so that it must not always
6628 // do a releasing store. For this, it needs the constant address of
6629 // CMSCollectorCardTableModRefBSExt::_requires_release.
6630 // This constant address is split off here by expand so we can use
6631 // adlc / matcher functionality to load it from the constant section.
6632 instruct storeCM_CMS_ExEx(memory mem, immI_0 zero) %{
6633 match(Set mem (StoreCM mem zero));
6634 predicate(UseConcMarkSweepGC);
6635
6636 expand %{
6637 immL baseImm %{ 0 /* TODO: PPC port (jlong)CMSCollectorCardTableModRefBSExt::requires_release_address() */ %}
6638 iRegLdst releaseFieldAddress;
6639 loadConL_Ex(releaseFieldAddress, baseImm);
6640 storeCM_CMS(mem, releaseFieldAddress);
6641 %}
6642 %}
6643
6644 instruct storeCM_G1(memory mem, immI_0 zero) %{
6645 match(Set mem (StoreCM mem zero));
6646 predicate(UseG1GC);
6647 ins_cost(MEMORY_REF_COST);
6648
6649 ins_cannot_rematerialize(true);
6650
6651 format %{ "STB #0, $mem \t// CMS card-mark byte store (G1)" %}
6652 size(8);
6653 ins_encode %{
6654 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6655 __ li(R0, 0);
6656 //__ release(); // G1: oops are allowed to get visible after dirty marking
6657 guarantee($mem$$base$$Register != R1_SP, "use frame_slots_bias");
6658 __ stb(R0, $mem$$disp, $mem$$base$$Register);
6659 %}
6660 ins_pipe(pipe_class_memory);
6661 %}
6662
6663 // Convert oop pointer into compressed form.
6664
6665 // Nodes for postalloc expand.
6666
6667 // Shift node for expand.
6668 instruct encodeP_shift(iRegNdst dst, iRegNsrc src) %{
6669 // The match rule is needed to make it a 'MachTypeNode'!
6670 match(Set dst (EncodeP src));
6671 predicate(false);
6672
6673 format %{ "SRDI $dst, $src, 3 \t// encode" %}
6674 size(4);
6675 ins_encode %{
6676 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6677 __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f);
6678 %}
6679 ins_pipe(pipe_class_default);
6680 %}
6681
6682 // Add node for expand.
6683 instruct encodeP_sub(iRegPdst dst, iRegPdst src) %{
6684 // The match rule is needed to make it a 'MachTypeNode'!
6685 match(Set dst (EncodeP src));
6686 predicate(false);
6687
6688 format %{ "SUB $dst, $src, oop_base \t// encode" %}
6689 size(4);
6690 ins_encode %{
6691 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
6692 __ subf($dst$$Register, R30, $src$$Register);
6693 %}
6694 ins_pipe(pipe_class_default);
6695 %}
6696
6697 // Conditional sub base.
6698 instruct cond_sub_base(iRegNdst dst, flagsReg crx, iRegPsrc src1) %{
6699 // The match rule is needed to make it a 'MachTypeNode'!
6700 match(Set dst (EncodeP (Binary crx src1)));
6701 predicate(false);
6702
6703 ins_variable_size_depending_on_alignment(true);
6704
6705 format %{ "BEQ $crx, done\n\t"
6706 "SUB $dst, $src1, R30 \t// encode: subtract base if != NULL\n"
6707 "done:" %}
6708 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
6709 ins_encode %{
6710 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
6711 Label done;
6712 __ beq($crx$$CondRegister, done);
6713 __ subf($dst$$Register, R30, $src1$$Register);
6714 // TODO PPC port __ endgroup_if_needed(_size == 12);
6715 __ bind(done);
6716 %}
6717 ins_pipe(pipe_class_default);
6718 %}
6719
6720 // Power 7 can use isel instruction
6721 instruct cond_set_0_oop(iRegNdst dst, flagsReg crx, iRegPsrc src1) %{
6722 // The match rule is needed to make it a 'MachTypeNode'!
6723 match(Set dst (EncodeP (Binary crx src1)));
6724 predicate(false);
6725
6726 format %{ "CMOVE $dst, $crx eq, 0, $src1 \t// encode: preserve 0" %}
6727 size(4);
6728 ins_encode %{
6729 // This is a Power7 instruction for which no machine description exists.
6730 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6731 __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register);
6732 %}
6733 ins_pipe(pipe_class_default);
6734 %}
6735
6736 // base != 0
6737 // 32G aligned narrow oop base.
6738 instruct encodeP_32GAligned(iRegNdst dst, iRegPsrc src) %{
6739 match(Set dst (EncodeP src));
6740 predicate(false /* TODO: PPC port Universe::narrow_oop_base_disjoint()*/);
6741
6742 format %{ "EXTRDI $dst, $src, #32, #3 \t// encode with 32G aligned base" %}
6743 size(4);
6744 ins_encode %{
6745 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6746 __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_oop_shift(), 32);
6747 %}
6748 ins_pipe(pipe_class_default);
6749 %}
6750
6751 // shift != 0, base != 0
6752 instruct encodeP_Ex(iRegNdst dst, flagsReg crx, iRegPsrc src) %{
6753 match(Set dst (EncodeP src));
6754 effect(TEMP crx);
6755 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull &&
6756 Universe::narrow_oop_shift() != 0 &&
6757 true /* TODO: PPC port Universe::narrow_oop_base_overlaps()*/);
6758
6759 format %{ "EncodeP $dst, $crx, $src \t// postalloc expanded" %}
6760 postalloc_expand( postalloc_expand_encode_oop(dst, src, crx));
6761 %}
6762
6763 // shift != 0, base != 0
6764 instruct encodeP_not_null_Ex(iRegNdst dst, iRegPsrc src) %{
6765 match(Set dst (EncodeP src));
6766 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull &&
6767 Universe::narrow_oop_shift() != 0 &&
6768 true /* TODO: PPC port Universe::narrow_oop_base_overlaps()*/);
6769
6770 format %{ "EncodeP $dst, $src\t// $src != Null, postalloc expanded" %}
6771 postalloc_expand( postalloc_expand_encode_oop_not_null(dst, src) );
6772 %}
6773
6774 // shift != 0, base == 0
6775 // TODO: This is the same as encodeP_shift. Merge!
6776 instruct encodeP_not_null_base_null(iRegNdst dst, iRegPsrc src) %{
6777 match(Set dst (EncodeP src));
6778 predicate(Universe::narrow_oop_shift() != 0 &&
6779 Universe::narrow_oop_base() ==0);
6780
6781 format %{ "SRDI $dst, $src, #3 \t// encodeP, $src != NULL" %}
6782 size(4);
6783 ins_encode %{
6784 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6785 __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f);
6786 %}
6787 ins_pipe(pipe_class_default);
6788 %}
6789
6790 // Compressed OOPs with narrow_oop_shift == 0.
6791 // shift == 0, base == 0
6792 instruct encodeP_narrow_oop_shift_0(iRegNdst dst, iRegPsrc src) %{
6793 match(Set dst (EncodeP src));
6794 predicate(Universe::narrow_oop_shift() == 0);
6795
6796 format %{ "MR $dst, $src \t// Ptr->Narrow" %}
6797 // variable size, 0 or 4.
6798 ins_encode %{
6799 // TODO: PPC port $archOpcode(ppc64Opcode_or);
6800 __ mr_if_needed($dst$$Register, $src$$Register);
6801 %}
6802 ins_pipe(pipe_class_default);
6803 %}
6804
6805 // Decode nodes.
6806
6807 // Shift node for expand.
6808 instruct decodeN_shift(iRegPdst dst, iRegPsrc src) %{
6809 // The match rule is needed to make it a 'MachTypeNode'!
6810 match(Set dst (DecodeN src));
6811 predicate(false);
6812
6813 format %{ "SLDI $dst, $src, #3 \t// DecodeN" %}
6814 size(4);
6815 ins_encode %{
6816 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
6817 __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift());
6818 %}
6819 ins_pipe(pipe_class_default);
6820 %}
6821
6822 // Add node for expand.
6823 instruct decodeN_add(iRegPdst dst, iRegPdst src) %{
6824 // The match rule is needed to make it a 'MachTypeNode'!
6825 match(Set dst (DecodeN src));
6826 predicate(false);
6827
6828 format %{ "ADD $dst, $src, R30 \t// DecodeN, add oop base" %}
6829 size(4);
6830 ins_encode %{
6831 // TODO: PPC port $archOpcode(ppc64Opcode_add);
6832 __ add($dst$$Register, $src$$Register, R30);
6833 %}
6834 ins_pipe(pipe_class_default);
6835 %}
6836
6837 // conditianal add base for expand
6838 instruct cond_add_base(iRegPdst dst, flagsReg crx, iRegPsrc src1) %{
6839 // The match rule is needed to make it a 'MachTypeNode'!
6840 // NOTICE that the rule is nonsense - we just have to make sure that:
6841 // - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp)
6842 // - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC.
6843 match(Set dst (DecodeN (Binary crx src1)));
6844 predicate(false);
6845
6846 ins_variable_size_depending_on_alignment(true);
6847
6848 format %{ "BEQ $crx, done\n\t"
6849 "ADD $dst, $src1, R30 \t// DecodeN: add oop base if $src1 != NULL\n"
6850 "done:" %}
6851 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling()) */? 12 : 8);
6852 ins_encode %{
6853 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
6854 Label done;
6855 __ beq($crx$$CondRegister, done);
6856 __ add($dst$$Register, $src1$$Register, R30);
6857 // TODO PPC port __ endgroup_if_needed(_size == 12);
6858 __ bind(done);
6859 %}
6860 ins_pipe(pipe_class_default);
6861 %}
6862
6863 instruct cond_set_0_ptr(iRegPdst dst, flagsReg crx, iRegPsrc src1) %{
6864 // The match rule is needed to make it a 'MachTypeNode'!
6865 // NOTICE that the rule is nonsense - we just have to make sure that:
6866 // - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp)
6867 // - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC.
6868 match(Set dst (DecodeN (Binary crx src1)));
6869 predicate(false);
6870
6871 format %{ "CMOVE $dst, $crx eq, 0, $src1 \t// decode: preserve 0" %}
6872 size(4);
6873 ins_encode %{
6874 // This is a Power7 instruction for which no machine description exists.
6875 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6876 __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register);
6877 %}
6878 ins_pipe(pipe_class_default);
6879 %}
6880
6881 // shift != 0, base != 0
6882 instruct decodeN_Ex(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
6883 match(Set dst (DecodeN src));
6884 predicate((n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6885 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant) &&
6886 Universe::narrow_oop_shift() != 0 &&
6887 Universe::narrow_oop_base() != 0);
6888 effect(TEMP crx);
6889
6890 format %{ "DecodeN $dst, $src \t// Kills $crx, postalloc expanded" %}
6891 postalloc_expand( postalloc_expand_decode_oop(dst, src, crx) );
6892 %}
6893
6894 // shift != 0, base == 0
6895 instruct decodeN_nullBase(iRegPdst dst, iRegNsrc src) %{
6896 match(Set dst (DecodeN src));
6897 predicate(Universe::narrow_oop_shift() != 0 &&
6898 Universe::narrow_oop_base() == 0);
6899
6900 format %{ "SLDI $dst, $src, #3 \t// DecodeN (zerobased)" %}
6901 size(4);
6902 ins_encode %{
6903 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
6904 __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift());
6905 %}
6906 ins_pipe(pipe_class_default);
6907 %}
6908
6909 // src != 0, shift != 0, base != 0
6910 instruct decodeN_notNull_addBase_Ex(iRegPdst dst, iRegNsrc src) %{
6911 match(Set dst (DecodeN src));
6912 predicate((n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6913 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
6914 Universe::narrow_oop_shift() != 0 &&
6915 Universe::narrow_oop_base() != 0);
6916
6917 format %{ "DecodeN $dst, $src \t// $src != NULL, postalloc expanded" %}
6918 postalloc_expand( postalloc_expand_decode_oop_not_null(dst, src));
6919 %}
6920
6921 // Compressed OOPs with narrow_oop_shift == 0.
6922 instruct decodeN_unscaled(iRegPdst dst, iRegNsrc src) %{
6923 match(Set dst (DecodeN src));
6924 predicate(Universe::narrow_oop_shift() == 0);
6925 ins_cost(DEFAULT_COST);
6926
6927 format %{ "MR $dst, $src \t// DecodeN (unscaled)" %}
6928 // variable size, 0 or 4.
6929 ins_encode %{
6930 // TODO: PPC port $archOpcode(ppc64Opcode_or);
6931 __ mr_if_needed($dst$$Register, $src$$Register);
6932 %}
6933 ins_pipe(pipe_class_default);
6934 %}
6935
6936 // Convert compressed oop into int for vectors alignment masking.
6937 instruct decodeN2I_unscaled(iRegIdst dst, iRegNsrc src) %{
6938 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
6939 predicate(Universe::narrow_oop_shift() == 0);
6940 ins_cost(DEFAULT_COST);
6941
6942 format %{ "MR $dst, $src \t// (int)DecodeN (unscaled)" %}
6943 // variable size, 0 or 4.
6944 ins_encode %{
6945 // TODO: PPC port $archOpcode(ppc64Opcode_or);
6946 __ mr_if_needed($dst$$Register, $src$$Register);
6947 %}
6948 ins_pipe(pipe_class_default);
6949 %}
6950
6951 // Convert klass pointer into compressed form.
6952
6953 // Nodes for postalloc expand.
6954
6955 // Shift node for expand.
6956 instruct encodePKlass_shift(iRegNdst dst, iRegNsrc src) %{
6957 // The match rule is needed to make it a 'MachTypeNode'!
6958 match(Set dst (EncodePKlass src));
6959 predicate(false);
6960
6961 format %{ "SRDI $dst, $src, 3 \t// encode" %}
6962 size(4);
6963 ins_encode %{
6964 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6965 __ srdi($dst$$Register, $src$$Register, Universe::narrow_klass_shift());
6966 %}
6967 ins_pipe(pipe_class_default);
6968 %}
6969
6970 // Add node for expand.
6971 instruct encodePKlass_sub_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{
6972 // The match rule is needed to make it a 'MachTypeNode'!
6973 match(Set dst (EncodePKlass (Binary base src)));
6974 predicate(false);
6975
6976 format %{ "SUB $dst, $base, $src \t// encode" %}
6977 size(4);
6978 ins_encode %{
6979 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
6980 __ subf($dst$$Register, $base$$Register, $src$$Register);
6981 %}
6982 ins_pipe(pipe_class_default);
6983 %}
6984
6985 // base != 0
6986 // 32G aligned narrow oop base.
6987 instruct encodePKlass_32GAligned(iRegNdst dst, iRegPsrc src) %{
6988 match(Set dst (EncodePKlass src));
6989 predicate(false /* TODO: PPC port Universe::narrow_klass_base_disjoint()*/);
6990
6991 format %{ "EXTRDI $dst, $src, #32, #3 \t// encode with 32G aligned base" %}
6992 size(4);
6993 ins_encode %{
6994 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6995 __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_klass_shift(), 32);
6996 %}
6997 ins_pipe(pipe_class_default);
6998 %}
6999
7000 // shift != 0, base != 0
7001 instruct encodePKlass_not_null_Ex(iRegNdst dst, iRegLsrc base, iRegPsrc src) %{
7002 match(Set dst (EncodePKlass (Binary base src)));
7003 predicate(false);
7004
7005 format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %}
7006 postalloc_expand %{
7007 encodePKlass_sub_baseNode *n1 = new (C) encodePKlass_sub_baseNode();
7008 n1->add_req(n_region, n_base, n_src);
7009 n1->_opnds[0] = op_dst;
7010 n1->_opnds[1] = op_base;
7011 n1->_opnds[2] = op_src;
7012 n1->_bottom_type = _bottom_type;
7013
7014 encodePKlass_shiftNode *n2 = new (C) encodePKlass_shiftNode();
7015 n2->add_req(n_region, n1);
7016 n2->_opnds[0] = op_dst;
7017 n2->_opnds[1] = op_dst;
7018 n2->_bottom_type = _bottom_type;
7019 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7020 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7021
7022 nodes->push(n1);
7023 nodes->push(n2);
7024 %}
7025 %}
7026
7027 // shift != 0, base != 0
7028 instruct encodePKlass_not_null_ExEx(iRegNdst dst, iRegPsrc src) %{
7029 match(Set dst (EncodePKlass src));
7030 //predicate(Universe::narrow_klass_shift() != 0 &&
7031 // true /* TODO: PPC port Universe::narrow_klass_base_overlaps()*/);
7032
7033 //format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %}
7034 ins_cost(DEFAULT_COST*2); // Don't count constant.
7035 expand %{
7036 immL baseImm %{ (jlong)(intptr_t)Universe::narrow_klass_base() %}
7037 iRegLdst base;
7038 loadConL_Ex(base, baseImm);
7039 encodePKlass_not_null_Ex(dst, base, src);
7040 %}
7041 %}
7042
7043 // Decode nodes.
7044
7045 // Shift node for expand.
7046 instruct decodeNKlass_shift(iRegPdst dst, iRegPsrc src) %{
7047 // The match rule is needed to make it a 'MachTypeNode'!
7048 match(Set dst (DecodeNKlass src));
7049 predicate(false);
7050
7051 format %{ "SLDI $dst, $src, #3 \t// DecodeNKlass" %}
7052 size(4);
7053 ins_encode %{
7054 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
7055 __ sldi($dst$$Register, $src$$Register, Universe::narrow_klass_shift());
7056 %}
7057 ins_pipe(pipe_class_default);
7058 %}
7059
7060 // Add node for expand.
7061
7062 instruct decodeNKlass_add_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{
7063 // The match rule is needed to make it a 'MachTypeNode'!
7064 match(Set dst (DecodeNKlass (Binary base src)));
7065 predicate(false);
7066
7067 format %{ "ADD $dst, $base, $src \t// DecodeNKlass, add klass base" %}
7068 size(4);
7069 ins_encode %{
7070 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7071 __ add($dst$$Register, $base$$Register, $src$$Register);
7072 %}
7073 ins_pipe(pipe_class_default);
7074 %}
7075
7076 // src != 0, shift != 0, base != 0
7077 instruct decodeNKlass_notNull_addBase_Ex(iRegPdst dst, iRegLsrc base, iRegNsrc src) %{
7078 match(Set dst (DecodeNKlass (Binary base src)));
7079 //effect(kill src); // We need a register for the immediate result after shifting.
7080 predicate(false);
7081
7082 format %{ "DecodeNKlass $dst = $base + ($src << 3) \t// $src != NULL, postalloc expanded" %}
7083 postalloc_expand %{
7084 decodeNKlass_add_baseNode *n1 = new (C) decodeNKlass_add_baseNode();
7085 n1->add_req(n_region, n_base, n_src);
7086 n1->_opnds[0] = op_dst;
7087 n1->_opnds[1] = op_base;
7088 n1->_opnds[2] = op_src;
7089 n1->_bottom_type = _bottom_type;
7090
7091 decodeNKlass_shiftNode *n2 = new (C) decodeNKlass_shiftNode();
7092 n2->add_req(n_region, n1);
7093 n2->_opnds[0] = op_dst;
7094 n2->_opnds[1] = op_dst;
7095 n2->_bottom_type = _bottom_type;
7096
7097 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7098 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7099
7100 nodes->push(n1);
7101 nodes->push(n2);
7102 %}
7103 %}
7104
7105 // src != 0, shift != 0, base != 0
7106 instruct decodeNKlass_notNull_addBase_ExEx(iRegPdst dst, iRegNsrc src) %{
7107 match(Set dst (DecodeNKlass src));
7108 // predicate(Universe::narrow_klass_shift() != 0 &&
7109 // Universe::narrow_klass_base() != 0);
7110
7111 //format %{ "DecodeNKlass $dst, $src \t// $src != NULL, expanded" %}
7112
7113 ins_cost(DEFAULT_COST*2); // Don't count constant.
7114 expand %{
7115 // We add first, then we shift. Like this, we can get along with one register less.
7116 // But we have to load the base pre-shifted.
7117 immL baseImm %{ (jlong)((intptr_t)Universe::narrow_klass_base() >> Universe::narrow_klass_shift()) %}
7118 iRegLdst base;
7119 loadConL_Ex(base, baseImm);
7120 decodeNKlass_notNull_addBase_Ex(dst, base, src);
7121 %}
7122 %}
7123
7124 //----------MemBar Instructions-----------------------------------------------
7125 // Memory barrier flavors
7126
7127 instruct membar_acquire() %{
7128 match(LoadFence);
7129 ins_cost(4*MEMORY_REF_COST);
7130
7131 format %{ "MEMBAR-acquire" %}
7132 size(4);
7133 ins_encode %{
7134 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7135 __ acquire();
7136 %}
7137 ins_pipe(pipe_class_default);
7138 %}
7139
7140 instruct unnecessary_membar_acquire() %{
7141 match(MemBarAcquire);
7142 ins_cost(0);
7143
7144 format %{ " -- \t// redundant MEMBAR-acquire - empty" %}
7145 size(0);
7146 ins_encode( /*empty*/ );
7147 ins_pipe(pipe_class_default);
7148 %}
7149
7150 instruct membar_acquire_lock() %{
7151 match(MemBarAcquireLock);
7152 ins_cost(0);
7153
7154 format %{ " -- \t// redundant MEMBAR-acquire - empty (acquire as part of CAS in prior FastLock)" %}
7155 size(0);
7156 ins_encode( /*empty*/ );
7157 ins_pipe(pipe_class_default);
7158 %}
7159
7160 instruct membar_release() %{
7161 match(MemBarRelease);
7162 match(StoreFence);
7163 ins_cost(4*MEMORY_REF_COST);
7164
7165 format %{ "MEMBAR-release" %}
7166 size(4);
7167 ins_encode %{
7168 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7169 __ release();
7170 %}
7171 ins_pipe(pipe_class_default);
7172 %}
7173
7174 instruct membar_storestore() %{
7175 match(MemBarStoreStore);
7176 ins_cost(4*MEMORY_REF_COST);
7177
7178 format %{ "MEMBAR-store-store" %}
7179 size(4);
7180 ins_encode %{
7181 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7182 __ membar(Assembler::StoreStore);
7183 %}
7184 ins_pipe(pipe_class_default);
7185 %}
7186
7187 instruct membar_release_lock() %{
7188 match(MemBarReleaseLock);
7189 ins_cost(0);
7190
7191 format %{ " -- \t// redundant MEMBAR-release - empty (release in FastUnlock)" %}
7192 size(0);
7193 ins_encode( /*empty*/ );
7194 ins_pipe(pipe_class_default);
7195 %}
7196
7197 instruct membar_volatile() %{
7198 match(MemBarVolatile);
7199 ins_cost(4*MEMORY_REF_COST);
7200
7201 format %{ "MEMBAR-volatile" %}
7202 size(4);
7203 ins_encode %{
7204 // TODO: PPC port $archOpcode(ppc64Opcode_sync);
7205 __ fence();
7206 %}
7207 ins_pipe(pipe_class_default);
7208 %}
7209
7210 // This optimization is wrong on PPC. The following pattern is not supported:
7211 // MemBarVolatile
7212 // ^ ^
7213 // | |
7214 // CtrlProj MemProj
7215 // ^ ^
7216 // | |
7217 // | Load
7218 // |
7219 // MemBarVolatile
7220 //
7221 // The first MemBarVolatile could get optimized out! According to
7222 // Vladimir, this pattern can not occur on Oracle platforms.
7223 // However, it does occur on PPC64 (because of membars in
7224 // inline_unsafe_load_store).
7225 //
7226 // Add this node again if we found a good solution for inline_unsafe_load_store().
7227 // Don't forget to look at the implementation of post_store_load_barrier again,
7228 // we did other fixes in that method.
7229 //instruct unnecessary_membar_volatile() %{
7230 // match(MemBarVolatile);
7231 // predicate(Matcher::post_store_load_barrier(n));
7232 // ins_cost(0);
7233 //
7234 // format %{ " -- \t// redundant MEMBAR-volatile - empty" %}
7235 // size(0);
7236 // ins_encode( /*empty*/ );
7237 // ins_pipe(pipe_class_default);
7238 //%}
7239
7240 instruct membar_CPUOrder() %{
7241 match(MemBarCPUOrder);
7242 ins_cost(0);
7243
7244 format %{ " -- \t// MEMBAR-CPUOrder - empty: PPC64 processors are self-consistent." %}
7245 size(0);
7246 ins_encode( /*empty*/ );
7247 ins_pipe(pipe_class_default);
7248 %}
7249
7250 //----------Conditional Move---------------------------------------------------
7251
7252 // Cmove using isel.
7253 instruct cmovI_reg_isel(cmpOp cmp, flagsReg crx, iRegIdst dst, iRegIsrc src) %{
7254 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7255 predicate(VM_Version::has_isel());
7256 ins_cost(DEFAULT_COST);
7257
7258 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7259 size(4);
7260 ins_encode %{
7261 // This is a Power7 instruction for which no machine description
7262 // exists. Anyways, the scheduler should be off on Power7.
7263 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7264 int cc = $cmp$$cmpcode;
7265 __ isel($dst$$Register, $crx$$CondRegister,
7266 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7267 %}
7268 ins_pipe(pipe_class_default);
7269 %}
7270
7271 instruct cmovI_reg(cmpOp cmp, flagsReg crx, iRegIdst dst, iRegIsrc src) %{
7272 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7273 predicate(!VM_Version::has_isel());
7274 ins_cost(DEFAULT_COST+BRANCH_COST);
7275
7276 ins_variable_size_depending_on_alignment(true);
7277
7278 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7279 // Worst case is branch + move + stop, no stop without scheduler
7280 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7281 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7282 ins_pipe(pipe_class_default);
7283 %}
7284
7285 instruct cmovI_imm(cmpOp cmp, flagsReg crx, iRegIdst dst, immI16 src) %{
7286 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7287 ins_cost(DEFAULT_COST+BRANCH_COST);
7288
7289 ins_variable_size_depending_on_alignment(true);
7290
7291 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7292 // Worst case is branch + move + stop, no stop without scheduler
7293 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7294 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7295 ins_pipe(pipe_class_default);
7296 %}
7297
7298 // Cmove using isel.
7299 instruct cmovL_reg_isel(cmpOp cmp, flagsReg crx, iRegLdst dst, iRegLsrc src) %{
7300 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7301 predicate(VM_Version::has_isel());
7302 ins_cost(DEFAULT_COST);
7303
7304 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7305 size(4);
7306 ins_encode %{
7307 // This is a Power7 instruction for which no machine description
7308 // exists. Anyways, the scheduler should be off on Power7.
7309 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7310 int cc = $cmp$$cmpcode;
7311 __ isel($dst$$Register, $crx$$CondRegister,
7312 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7313 %}
7314 ins_pipe(pipe_class_default);
7315 %}
7316
7317 instruct cmovL_reg(cmpOp cmp, flagsReg crx, iRegLdst dst, iRegLsrc src) %{
7318 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7319 predicate(!VM_Version::has_isel());
7320 ins_cost(DEFAULT_COST+BRANCH_COST);
7321
7322 ins_variable_size_depending_on_alignment(true);
7323
7324 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7325 // Worst case is branch + move + stop, no stop without scheduler.
7326 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7327 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7328 ins_pipe(pipe_class_default);
7329 %}
7330
7331 instruct cmovL_imm(cmpOp cmp, flagsReg crx, iRegLdst dst, immL16 src) %{
7332 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7333 ins_cost(DEFAULT_COST+BRANCH_COST);
7334
7335 ins_variable_size_depending_on_alignment(true);
7336
7337 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7338 // Worst case is branch + move + stop, no stop without scheduler.
7339 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7340 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7341 ins_pipe(pipe_class_default);
7342 %}
7343
7344 // Cmove using isel.
7345 instruct cmovN_reg_isel(cmpOp cmp, flagsReg crx, iRegNdst dst, iRegNsrc src) %{
7346 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7347 predicate(VM_Version::has_isel());
7348 ins_cost(DEFAULT_COST);
7349
7350 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7351 size(4);
7352 ins_encode %{
7353 // This is a Power7 instruction for which no machine description
7354 // exists. Anyways, the scheduler should be off on Power7.
7355 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7356 int cc = $cmp$$cmpcode;
7357 __ isel($dst$$Register, $crx$$CondRegister,
7358 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7359 %}
7360 ins_pipe(pipe_class_default);
7361 %}
7362
7363 // Conditional move for RegN. Only cmov(reg, reg).
7364 instruct cmovN_reg(cmpOp cmp, flagsReg crx, iRegNdst dst, iRegNsrc src) %{
7365 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7366 predicate(!VM_Version::has_isel());
7367 ins_cost(DEFAULT_COST+BRANCH_COST);
7368
7369 ins_variable_size_depending_on_alignment(true);
7370
7371 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7372 // Worst case is branch + move + stop, no stop without scheduler.
7373 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7374 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7375 ins_pipe(pipe_class_default);
7376 %}
7377
7378 instruct cmovN_imm(cmpOp cmp, flagsReg crx, iRegNdst dst, immN_0 src) %{
7379 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7380 ins_cost(DEFAULT_COST+BRANCH_COST);
7381
7382 ins_variable_size_depending_on_alignment(true);
7383
7384 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7385 // Worst case is branch + move + stop, no stop without scheduler.
7386 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7387 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7388 ins_pipe(pipe_class_default);
7389 %}
7390
7391 // Cmove using isel.
7392 instruct cmovP_reg_isel(cmpOp cmp, flagsReg crx, iRegPdst dst, iRegPsrc src) %{
7393 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7394 predicate(VM_Version::has_isel());
7395 ins_cost(DEFAULT_COST);
7396
7397 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7398 size(4);
7399 ins_encode %{
7400 // This is a Power7 instruction for which no machine description
7401 // exists. Anyways, the scheduler should be off on Power7.
7402 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7403 int cc = $cmp$$cmpcode;
7404 __ isel($dst$$Register, $crx$$CondRegister,
7405 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7406 %}
7407 ins_pipe(pipe_class_default);
7408 %}
7409
7410 instruct cmovP_reg(cmpOp cmp, flagsReg crx, iRegPdst dst, iRegP_N2P src) %{
7411 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7412 predicate(!VM_Version::has_isel());
7413 ins_cost(DEFAULT_COST+BRANCH_COST);
7414
7415 ins_variable_size_depending_on_alignment(true);
7416
7417 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7418 // Worst case is branch + move + stop, no stop without scheduler.
7419 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7420 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7421 ins_pipe(pipe_class_default);
7422 %}
7423
7424 instruct cmovP_imm(cmpOp cmp, flagsReg crx, iRegPdst dst, immP_0 src) %{
7425 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7426 ins_cost(DEFAULT_COST+BRANCH_COST);
7427
7428 ins_variable_size_depending_on_alignment(true);
7429
7430 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7431 // Worst case is branch + move + stop, no stop without scheduler.
7432 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7433 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7434 ins_pipe(pipe_class_default);
7435 %}
7436
7437 instruct cmovF_reg(cmpOp cmp, flagsReg crx, regF dst, regF src) %{
7438 match(Set dst (CMoveF (Binary cmp crx) (Binary dst src)));
7439 ins_cost(DEFAULT_COST+BRANCH_COST);
7440
7441 ins_variable_size_depending_on_alignment(true);
7442
7443 format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %}
7444 // Worst case is branch + move + stop, no stop without scheduler.
7445 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
7446 ins_encode %{
7447 // TODO: PPC port $archOpcode(ppc64Opcode_cmovef);
7448 Label done;
7449 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
7450 // Branch if not (cmp crx).
7451 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
7452 __ fmr($dst$$FloatRegister, $src$$FloatRegister);
7453 // TODO PPC port __ endgroup_if_needed(_size == 12);
7454 __ bind(done);
7455 %}
7456 ins_pipe(pipe_class_default);
7457 %}
7458
7459 instruct cmovD_reg(cmpOp cmp, flagsReg crx, regD dst, regD src) %{
7460 match(Set dst (CMoveD (Binary cmp crx) (Binary dst src)));
7461 ins_cost(DEFAULT_COST+BRANCH_COST);
7462
7463 ins_variable_size_depending_on_alignment(true);
7464
7465 format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %}
7466 // Worst case is branch + move + stop, no stop without scheduler.
7467 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
7468 ins_encode %{
7469 // TODO: PPC port $archOpcode(ppc64Opcode_cmovef);
7470 Label done;
7471 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
7472 // Branch if not (cmp crx).
7473 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
7474 __ fmr($dst$$FloatRegister, $src$$FloatRegister);
7475 // TODO PPC port __ endgroup_if_needed(_size == 12);
7476 __ bind(done);
7477 %}
7478 ins_pipe(pipe_class_default);
7479 %}
7480
7481 //----------Conditional_store--------------------------------------------------
7482 // Conditional-store of the updated heap-top.
7483 // Used during allocation of the shared heap.
7484 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
7485
7486 // As compareAndSwapL, but return flag register instead of boolean value in
7487 // int register.
7488 // Used by sun/misc/AtomicLongCSImpl.java.
7489 // Mem_ptr must be a memory operand, else this node does not get
7490 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node
7491 // can be rematerialized which leads to errors.
7492 instruct storeLConditional_regP_regL_regL(flagsReg crx, indirect mem_ptr, iRegLsrc oldVal, iRegLsrc newVal) %{
7493 match(Set crx (StoreLConditional mem_ptr (Binary oldVal newVal)));
7494 format %{ "CMPXCHGD if ($crx = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %}
7495 ins_encode %{
7496 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7497 __ cmpxchgd($crx$$CondRegister, R0, $oldVal$$Register, $newVal$$Register, $mem_ptr$$Register,
7498 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7499 noreg, NULL, true);
7500 %}
7501 ins_pipe(pipe_class_default);
7502 %}
7503
7504 // As compareAndSwapP, but return flag register instead of boolean value in
7505 // int register.
7506 // This instruction is matched if UseTLAB is off.
7507 // Mem_ptr must be a memory operand, else this node does not get
7508 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node
7509 // can be rematerialized which leads to errors.
7510 instruct storePConditional_regP_regP_regP(flagsReg crx, indirect mem_ptr, iRegPsrc oldVal, iRegPsrc newVal) %{
7511 match(Set crx (StorePConditional mem_ptr (Binary oldVal newVal)));
7512 format %{ "CMPXCHGD if ($crx = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %}
7513 ins_encode %{
7514 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7515 __ cmpxchgd($crx$$CondRegister, R0, $oldVal$$Register, $newVal$$Register, $mem_ptr$$Register,
7516 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7517 noreg, NULL, true);
7518 %}
7519 ins_pipe(pipe_class_default);
7520 %}
7521
7522 // Implement LoadPLocked. Must be ordered against changes of the memory location
7523 // by storePConditional.
7524 // Don't know whether this is ever used.
7525 instruct loadPLocked(iRegPdst dst, memory mem) %{
7526 match(Set dst (LoadPLocked mem));
7527 ins_cost(MEMORY_REF_COST);
7528
7529 format %{ "LD $dst, $mem \t// loadPLocked\n\t"
7530 "TWI $dst\n\t"
7531 "ISYNC" %}
7532 size(12);
7533 ins_encode( enc_ld_ac(dst, mem) );
7534 ins_pipe(pipe_class_memory);
7535 %}
7536
7537 //----------Compare-And-Swap---------------------------------------------------
7538
7539 // CompareAndSwap{P,I,L} have more than one output, therefore "CmpI
7540 // (CompareAndSwap ...)" or "If (CmpI (CompareAndSwap ..))" cannot be
7541 // matched.
7542
7543 instruct compareAndSwapI_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2) %{
7544 match(Set res (CompareAndSwapI mem_ptr (Binary src1 src2)));
7545 format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
7546 // Variable size: instruction count smaller if regs are disjoint.
7547 ins_encode %{
7548 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7549 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7550 __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7551 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7552 $res$$Register, true);
7553 %}
7554 ins_pipe(pipe_class_default);
7555 %}
7556
7557 instruct compareAndSwapN_regP_regN_regN(iRegIdst res, iRegPdst mem_ptr, iRegNsrc src1, iRegNsrc src2) %{
7558 match(Set res (CompareAndSwapN mem_ptr (Binary src1 src2)));
7559 format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
7560 // Variable size: instruction count smaller if regs are disjoint.
7561 ins_encode %{
7562 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7563 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7564 __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7565 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7566 $res$$Register, true);
7567 %}
7568 ins_pipe(pipe_class_default);
7569 %}
7570
7571 instruct compareAndSwapL_regP_regL_regL(iRegIdst res, iRegPdst mem_ptr, iRegLsrc src1, iRegLsrc src2) %{
7572 match(Set res (CompareAndSwapL mem_ptr (Binary src1 src2)));
7573 format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool" %}
7574 // Variable size: instruction count smaller if regs are disjoint.
7575 ins_encode %{
7576 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7577 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7578 __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7579 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7580 $res$$Register, NULL, true);
7581 %}
7582 ins_pipe(pipe_class_default);
7583 %}
7584
7585 instruct compareAndSwapP_regP_regP_regP(iRegIdst res, iRegPdst mem_ptr, iRegPsrc src1, iRegPsrc src2) %{
7586 match(Set res (CompareAndSwapP mem_ptr (Binary src1 src2)));
7587 format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool; ptr" %}
7588 // Variable size: instruction count smaller if regs are disjoint.
7589 ins_encode %{
7590 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7591 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7592 __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7593 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7594 $res$$Register, NULL, true);
7595 %}
7596 ins_pipe(pipe_class_default);
7597 %}
7598
7599 instruct getAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
7600 match(Set res (GetAndAddI mem_ptr src));
7601 format %{ "GetAndAddI $res, $mem_ptr, $src" %}
7602 // Variable size: instruction count smaller if regs are disjoint.
7603 ins_encode( enc_GetAndAddI(res, mem_ptr, src) );
7604 ins_pipe(pipe_class_default);
7605 %}
7606
7607 instruct getAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
7608 match(Set res (GetAndAddL mem_ptr src));
7609 format %{ "GetAndAddL $res, $mem_ptr, $src" %}
7610 // Variable size: instruction count smaller if regs are disjoint.
7611 ins_encode( enc_GetAndAddL(res, mem_ptr, src) );
7612 ins_pipe(pipe_class_default);
7613 %}
7614
7615 instruct getAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
7616 match(Set res (GetAndSetI mem_ptr src));
7617 format %{ "GetAndSetI $res, $mem_ptr, $src" %}
7618 // Variable size: instruction count smaller if regs are disjoint.
7619 ins_encode( enc_GetAndSetI(res, mem_ptr, src) );
7620 ins_pipe(pipe_class_default);
7621 %}
7622
7623 instruct getAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
7624 match(Set res (GetAndSetL mem_ptr src));
7625 format %{ "GetAndSetL $res, $mem_ptr, $src" %}
7626 // Variable size: instruction count smaller if regs are disjoint.
7627 ins_encode( enc_GetAndSetL(res, mem_ptr, src) );
7628 ins_pipe(pipe_class_default);
7629 %}
7630
7631 instruct getAndSetP(iRegPdst res, iRegPdst mem_ptr, iRegPsrc src) %{
7632 match(Set res (GetAndSetP mem_ptr src));
7633 format %{ "GetAndSetP $res, $mem_ptr, $src" %}
7634 // Variable size: instruction count smaller if regs are disjoint.
7635 ins_encode( enc_GetAndSetL(res, mem_ptr, src) );
7636 ins_pipe(pipe_class_default);
7637 %}
7638
7639 instruct getAndSetN(iRegNdst res, iRegPdst mem_ptr, iRegNsrc src) %{
7640 match(Set res (GetAndSetN mem_ptr src));
7641 format %{ "GetAndSetN $res, $mem_ptr, $src" %}
7642 // Variable size: instruction count smaller if regs are disjoint.
7643 ins_encode( enc_GetAndSetI(res, mem_ptr, src) );
7644 ins_pipe(pipe_class_default);
7645 %}
7646
7647 //----------Arithmetic Instructions--------------------------------------------
7648 // Addition Instructions
7649
7650 // Register Addition
7651 instruct addI_reg_reg(iRegIdst dst, iRegIsrc_iRegL2Isrc src1, iRegIsrc_iRegL2Isrc src2) %{
7652 match(Set dst (AddI src1 src2));
7653 format %{ "ADD $dst, $src1, $src2" %}
7654 size(4);
7655 ins_encode %{
7656 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7657 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7658 %}
7659 ins_pipe(pipe_class_default);
7660 %}
7661
7662 // Expand does not work with above instruct. (??)
7663 instruct addI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
7664 // no match-rule
7665 effect(DEF dst, USE src1, USE src2);
7666 format %{ "ADD $dst, $src1, $src2" %}
7667 size(4);
7668 ins_encode %{
7669 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7670 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7671 %}
7672 ins_pipe(pipe_class_default);
7673 %}
7674
7675 instruct tree_addI_addI_addI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
7676 match(Set dst (AddI (AddI (AddI src1 src2) src3) src4));
7677 ins_cost(DEFAULT_COST*3);
7678
7679 expand %{
7680 // FIXME: we should do this in the ideal world.
7681 iRegIdst tmp1;
7682 iRegIdst tmp2;
7683 addI_reg_reg(tmp1, src1, src2);
7684 addI_reg_reg_2(tmp2, src3, src4); // Adlc complains about addI_reg_reg.
7685 addI_reg_reg(dst, tmp1, tmp2);
7686 %}
7687 %}
7688
7689 // Immediate Addition
7690 instruct addI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
7691 match(Set dst (AddI src1 src2));
7692 format %{ "ADDI $dst, $src1, $src2" %}
7693 size(4);
7694 ins_encode %{
7695 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7696 __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7697 %}
7698 ins_pipe(pipe_class_default);
7699 %}
7700
7701 // Immediate Addition with 16-bit shifted operand
7702 instruct addI_reg_immhi16(iRegIdst dst, iRegIsrc src1, immIhi16 src2) %{
7703 match(Set dst (AddI src1 src2));
7704 format %{ "ADDIS $dst, $src1, $src2" %}
7705 size(4);
7706 ins_encode %{
7707 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7708 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7709 %}
7710 ins_pipe(pipe_class_default);
7711 %}
7712
7713 // Long Addition
7714 instruct addL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7715 match(Set dst (AddL src1 src2));
7716 format %{ "ADD $dst, $src1, $src2 \t// long" %}
7717 size(4);
7718 ins_encode %{
7719 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7720 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7721 %}
7722 ins_pipe(pipe_class_default);
7723 %}
7724
7725 // Expand does not work with above instruct. (??)
7726 instruct addL_reg_reg_2(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7727 // no match-rule
7728 effect(DEF dst, USE src1, USE src2);
7729 format %{ "ADD $dst, $src1, $src2 \t// long" %}
7730 size(4);
7731 ins_encode %{
7732 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7733 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7734 %}
7735 ins_pipe(pipe_class_default);
7736 %}
7737
7738 instruct tree_addL_addL_addL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2, iRegLsrc src3, iRegLsrc src4) %{
7739 match(Set dst (AddL (AddL (AddL src1 src2) src3) src4));
7740 ins_cost(DEFAULT_COST*3);
7741
7742 expand %{
7743 // FIXME: we should do this in the ideal world.
7744 iRegLdst tmp1;
7745 iRegLdst tmp2;
7746 addL_reg_reg(tmp1, src1, src2);
7747 addL_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg.
7748 addL_reg_reg(dst, tmp1, tmp2);
7749 %}
7750 %}
7751
7752 // AddL + ConvL2I.
7753 instruct addI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
7754 match(Set dst (ConvL2I (AddL src1 src2)));
7755
7756 format %{ "ADD $dst, $src1, $src2 \t// long + l2i" %}
7757 size(4);
7758 ins_encode %{
7759 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7760 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7761 %}
7762 ins_pipe(pipe_class_default);
7763 %}
7764
7765 // No constant pool entries required.
7766 instruct addL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
7767 match(Set dst (AddL src1 src2));
7768
7769 format %{ "ADDI $dst, $src1, $src2" %}
7770 size(4);
7771 ins_encode %{
7772 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7773 __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7774 %}
7775 ins_pipe(pipe_class_default);
7776 %}
7777
7778 // Long Immediate Addition with 16-bit shifted operand.
7779 // No constant pool entries required.
7780 instruct addL_reg_immhi16(iRegLdst dst, iRegLsrc src1, immL32hi16 src2) %{
7781 match(Set dst (AddL src1 src2));
7782
7783 format %{ "ADDIS $dst, $src1, $src2" %}
7784 size(4);
7785 ins_encode %{
7786 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7787 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7788 %}
7789 ins_pipe(pipe_class_default);
7790 %}
7791
7792 // Pointer Register Addition
7793 instruct addP_reg_reg(iRegPdst dst, iRegP_N2P src1, iRegLsrc src2) %{
7794 match(Set dst (AddP src1 src2));
7795 format %{ "ADD $dst, $src1, $src2" %}
7796 size(4);
7797 ins_encode %{
7798 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7799 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7800 %}
7801 ins_pipe(pipe_class_default);
7802 %}
7803
7804 // Pointer Immediate Addition
7805 // No constant pool entries required.
7806 instruct addP_reg_imm16(iRegPdst dst, iRegP_N2P src1, immL16 src2) %{
7807 match(Set dst (AddP src1 src2));
7808
7809 format %{ "ADDI $dst, $src1, $src2" %}
7810 size(4);
7811 ins_encode %{
7812 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7813 __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7814 %}
7815 ins_pipe(pipe_class_default);
7816 %}
7817
7818 // Pointer Immediate Addition with 16-bit shifted operand.
7819 // No constant pool entries required.
7820 instruct addP_reg_immhi16(iRegPdst dst, iRegP_N2P src1, immL32hi16 src2) %{
7821 match(Set dst (AddP src1 src2));
7822
7823 format %{ "ADDIS $dst, $src1, $src2" %}
7824 size(4);
7825 ins_encode %{
7826 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7827 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7828 %}
7829 ins_pipe(pipe_class_default);
7830 %}
7831
7832 //---------------------
7833 // Subtraction Instructions
7834
7835 // Register Subtraction
7836 instruct subI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
7837 match(Set dst (SubI src1 src2));
7838 format %{ "SUBF $dst, $src2, $src1" %}
7839 size(4);
7840 ins_encode %{
7841 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7842 __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7843 %}
7844 ins_pipe(pipe_class_default);
7845 %}
7846
7847 // Immediate Subtraction
7848 // The compiler converts "x-c0" into "x+ -c0" (see SubINode::Ideal),
7849 // so this rule seems to be unused.
7850 instruct subI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
7851 match(Set dst (SubI src1 src2));
7852 format %{ "SUBI $dst, $src1, $src2" %}
7853 size(4);
7854 ins_encode %{
7855 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7856 __ addi($dst$$Register, $src1$$Register, ($src2$$constant) * (-1));
7857 %}
7858 ins_pipe(pipe_class_default);
7859 %}
7860
7861 // SubI from constant (using subfic).
7862 instruct subI_imm16_reg(iRegIdst dst, immI16 src1, iRegIsrc src2) %{
7863 match(Set dst (SubI src1 src2));
7864 format %{ "SUBI $dst, $src1, $src2" %}
7865
7866 size(4);
7867 ins_encode %{
7868 // TODO: PPC port $archOpcode(ppc64Opcode_subfic);
7869 __ subfic($dst$$Register, $src2$$Register, $src1$$constant);
7870 %}
7871 ins_pipe(pipe_class_default);
7872 %}
7873
7874 // Turn the sign-bit of an integer into a 32-bit mask, 0x0...0 for
7875 // positive integers and 0xF...F for negative ones.
7876 instruct signmask32I_regI(iRegIdst dst, iRegIsrc src) %{
7877 // no match-rule, false predicate
7878 effect(DEF dst, USE src);
7879 predicate(false);
7880
7881 format %{ "SRAWI $dst, $src, #31" %}
7882 size(4);
7883 ins_encode %{
7884 // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
7885 __ srawi($dst$$Register, $src$$Register, 0x1f);
7886 %}
7887 ins_pipe(pipe_class_default);
7888 %}
7889
7890 instruct absI_reg_Ex(iRegIdst dst, iRegIsrc src) %{
7891 match(Set dst (AbsI src));
7892 ins_cost(DEFAULT_COST*3);
7893
7894 expand %{
7895 iRegIdst tmp1;
7896 iRegIdst tmp2;
7897 signmask32I_regI(tmp1, src);
7898 xorI_reg_reg(tmp2, tmp1, src);
7899 subI_reg_reg(dst, tmp2, tmp1);
7900 %}
7901 %}
7902
7903 instruct negI_regI(iRegIdst dst, immI_0 zero, iRegIsrc src2) %{
7904 match(Set dst (SubI zero src2));
7905 format %{ "NEG $dst, $src2" %}
7906 size(4);
7907 ins_encode %{
7908 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
7909 __ neg($dst$$Register, $src2$$Register);
7910 %}
7911 ins_pipe(pipe_class_default);
7912 %}
7913
7914 // Long subtraction
7915 instruct subL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7916 match(Set dst (SubL src1 src2));
7917 format %{ "SUBF $dst, $src2, $src1 \t// long" %}
7918 size(4);
7919 ins_encode %{
7920 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7921 __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7922 %}
7923 ins_pipe(pipe_class_default);
7924 %}
7925
7926 // SubL + convL2I.
7927 instruct subI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
7928 match(Set dst (ConvL2I (SubL src1 src2)));
7929
7930 format %{ "SUBF $dst, $src2, $src1 \t// long + l2i" %}
7931 size(4);
7932 ins_encode %{
7933 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7934 __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7935 %}
7936 ins_pipe(pipe_class_default);
7937 %}
7938
7939 // Immediate Subtraction
7940 // The compiler converts "x-c0" into "x+ -c0" (see SubLNode::Ideal),
7941 // so this rule seems to be unused.
7942 // No constant pool entries required.
7943 instruct subL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
7944 match(Set dst (SubL src1 src2));
7945
7946 format %{ "SUBI $dst, $src1, $src2 \t// long" %}
7947 size(4);
7948 ins_encode %{
7949 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7950 __ addi($dst$$Register, $src1$$Register, ($src2$$constant) * (-1));
7951 %}
7952 ins_pipe(pipe_class_default);
7953 %}
7954
7955 // Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for
7956 // positive longs and 0xF...F for negative ones.
7957 instruct signmask64I_regL(iRegIdst dst, iRegLsrc src) %{
7958 // no match-rule, false predicate
7959 effect(DEF dst, USE src);
7960 predicate(false);
7961
7962 format %{ "SRADI $dst, $src, #63" %}
7963 size(4);
7964 ins_encode %{
7965 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
7966 __ sradi($dst$$Register, $src$$Register, 0x3f);
7967 %}
7968 ins_pipe(pipe_class_default);
7969 %}
7970
7971 // Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for
7972 // positive longs and 0xF...F for negative ones.
7973 instruct signmask64L_regL(iRegLdst dst, iRegLsrc src) %{
7974 // no match-rule, false predicate
7975 effect(DEF dst, USE src);
7976 predicate(false);
7977
7978 format %{ "SRADI $dst, $src, #63" %}
7979 size(4);
7980 ins_encode %{
7981 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
7982 __ sradi($dst$$Register, $src$$Register, 0x3f);
7983 %}
7984 ins_pipe(pipe_class_default);
7985 %}
7986
7987 // Long negation
7988 instruct negL_reg_reg(iRegLdst dst, immL_0 zero, iRegLsrc src2) %{
7989 match(Set dst (SubL zero src2));
7990 format %{ "NEG $dst, $src2 \t// long" %}
7991 size(4);
7992 ins_encode %{
7993 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
7994 __ neg($dst$$Register, $src2$$Register);
7995 %}
7996 ins_pipe(pipe_class_default);
7997 %}
7998
7999 // NegL + ConvL2I.
8000 instruct negI_con0_regL(iRegIdst dst, immL_0 zero, iRegLsrc src2) %{
8001 match(Set dst (ConvL2I (SubL zero src2)));
8002
8003 format %{ "NEG $dst, $src2 \t// long + l2i" %}
8004 size(4);
8005 ins_encode %{
8006 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8007 __ neg($dst$$Register, $src2$$Register);
8008 %}
8009 ins_pipe(pipe_class_default);
8010 %}
8011
8012 // Multiplication Instructions
8013 // Integer Multiplication
8014
8015 // Register Multiplication
8016 instruct mulI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8017 match(Set dst (MulI src1 src2));
8018 ins_cost(DEFAULT_COST);
8019
8020 format %{ "MULLW $dst, $src1, $src2" %}
8021 size(4);
8022 ins_encode %{
8023 // TODO: PPC port $archOpcode(ppc64Opcode_mullw);
8024 __ mullw($dst$$Register, $src1$$Register, $src2$$Register);
8025 %}
8026 ins_pipe(pipe_class_default);
8027 %}
8028
8029 // Immediate Multiplication
8030 instruct mulI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
8031 match(Set dst (MulI src1 src2));
8032 ins_cost(DEFAULT_COST);
8033
8034 format %{ "MULLI $dst, $src1, $src2" %}
8035 size(4);
8036 ins_encode %{
8037 // TODO: PPC port $archOpcode(ppc64Opcode_mulli);
8038 __ mulli($dst$$Register, $src1$$Register, $src2$$constant);
8039 %}
8040 ins_pipe(pipe_class_default);
8041 %}
8042
8043 instruct mulL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8044 match(Set dst (MulL src1 src2));
8045 ins_cost(DEFAULT_COST);
8046
8047 format %{ "MULLD $dst $src1, $src2 \t// long" %}
8048 size(4);
8049 ins_encode %{
8050 // TODO: PPC port $archOpcode(ppc64Opcode_mulld);
8051 __ mulld($dst$$Register, $src1$$Register, $src2$$Register);
8052 %}
8053 ins_pipe(pipe_class_default);
8054 %}
8055
8056 // Multiply high for optimized long division by constant.
8057 instruct mulHighL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8058 match(Set dst (MulHiL src1 src2));
8059 ins_cost(DEFAULT_COST);
8060
8061 format %{ "MULHD $dst $src1, $src2 \t// long" %}
8062 size(4);
8063 ins_encode %{
8064 // TODO: PPC port $archOpcode(ppc64Opcode_mulhd);
8065 __ mulhd($dst$$Register, $src1$$Register, $src2$$Register);
8066 %}
8067 ins_pipe(pipe_class_default);
8068 %}
8069
8070 // Immediate Multiplication
8071 instruct mulL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
8072 match(Set dst (MulL src1 src2));
8073 ins_cost(DEFAULT_COST);
8074
8075 format %{ "MULLI $dst, $src1, $src2" %}
8076 size(4);
8077 ins_encode %{
8078 // TODO: PPC port $archOpcode(ppc64Opcode_mulli);
8079 __ mulli($dst$$Register, $src1$$Register, $src2$$constant);
8080 %}
8081 ins_pipe(pipe_class_default);
8082 %}
8083
8084 // Integer Division with Immediate -1: Negate.
8085 instruct divI_reg_immIvalueMinus1(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{
8086 match(Set dst (DivI src1 src2));
8087 ins_cost(DEFAULT_COST);
8088
8089 format %{ "NEG $dst, $src1 \t// /-1" %}
8090 size(4);
8091 ins_encode %{
8092 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8093 __ neg($dst$$Register, $src1$$Register);
8094 %}
8095 ins_pipe(pipe_class_default);
8096 %}
8097
8098 // Integer Division with constant, but not -1.
8099 // We should be able to improve this by checking the type of src2.
8100 // It might well be that src2 is known to be positive.
8101 instruct divI_reg_regnotMinus1(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8102 match(Set dst (DivI src1 src2));
8103 predicate(n->in(2)->find_int_con(-1) != -1); // src2 is a constant, but not -1
8104 ins_cost(2*DEFAULT_COST);
8105
8106 format %{ "DIVW $dst, $src1, $src2 \t// /not-1" %}
8107 size(4);
8108 ins_encode %{
8109 // TODO: PPC port $archOpcode(ppc64Opcode_divw);
8110 __ divw($dst$$Register, $src1$$Register, $src2$$Register);
8111 %}
8112 ins_pipe(pipe_class_default);
8113 %}
8114
8115 instruct cmovI_bne_negI_reg(iRegIdst dst, flagsReg crx, iRegIsrc src1) %{
8116 effect(USE_DEF dst, USE src1, USE crx);
8117 predicate(false);
8118
8119 ins_variable_size_depending_on_alignment(true);
8120
8121 format %{ "CMOVE $dst, neg($src1), $crx" %}
8122 // Worst case is branch + move + stop, no stop without scheduler.
8123 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
8124 ins_encode %{
8125 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
8126 Label done;
8127 __ bne($crx$$CondRegister, done);
8128 __ neg($dst$$Register, $src1$$Register);
8129 // TODO PPC port __ endgroup_if_needed(_size == 12);
8130 __ bind(done);
8131 %}
8132 ins_pipe(pipe_class_default);
8133 %}
8134
8135 // Integer Division with Registers not containing constants.
8136 instruct divI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8137 match(Set dst (DivI src1 src2));
8138 ins_cost(10*DEFAULT_COST);
8139
8140 expand %{
8141 immI16 imm %{ (int)-1 %}
8142 flagsReg tmp1;
8143 cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1
8144 divI_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2
8145 cmovI_bne_negI_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1
8146 %}
8147 %}
8148
8149 // Long Division with Immediate -1: Negate.
8150 instruct divL_reg_immLvalueMinus1(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{
8151 match(Set dst (DivL src1 src2));
8152 ins_cost(DEFAULT_COST);
8153
8154 format %{ "NEG $dst, $src1 \t// /-1, long" %}
8155 size(4);
8156 ins_encode %{
8157 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8158 __ neg($dst$$Register, $src1$$Register);
8159 %}
8160 ins_pipe(pipe_class_default);
8161 %}
8162
8163 // Long Division with constant, but not -1.
8164 instruct divL_reg_regnotMinus1(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8165 match(Set dst (DivL src1 src2));
8166 predicate(n->in(2)->find_long_con(-1L) != -1L); // Src2 is a constant, but not -1.
8167 ins_cost(2*DEFAULT_COST);
8168
8169 format %{ "DIVD $dst, $src1, $src2 \t// /not-1, long" %}
8170 size(4);
8171 ins_encode %{
8172 // TODO: PPC port $archOpcode(ppc64Opcode_divd);
8173 __ divd($dst$$Register, $src1$$Register, $src2$$Register);
8174 %}
8175 ins_pipe(pipe_class_default);
8176 %}
8177
8178 instruct cmovL_bne_negL_reg(iRegLdst dst, flagsReg crx, iRegLsrc src1) %{
8179 effect(USE_DEF dst, USE src1, USE crx);
8180 predicate(false);
8181
8182 ins_variable_size_depending_on_alignment(true);
8183
8184 format %{ "CMOVE $dst, neg($src1), $crx" %}
8185 // Worst case is branch + move + stop, no stop without scheduler.
8186 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
8187 ins_encode %{
8188 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
8189 Label done;
8190 __ bne($crx$$CondRegister, done);
8191 __ neg($dst$$Register, $src1$$Register);
8192 // TODO PPC port __ endgroup_if_needed(_size == 12);
8193 __ bind(done);
8194 %}
8195 ins_pipe(pipe_class_default);
8196 %}
8197
8198 // Long Division with Registers not containing constants.
8199 instruct divL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8200 match(Set dst (DivL src1 src2));
8201 ins_cost(10*DEFAULT_COST);
8202
8203 expand %{
8204 immL16 imm %{ (int)-1 %}
8205 flagsReg tmp1;
8206 cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1
8207 divL_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2
8208 cmovL_bne_negL_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1
8209 %}
8210 %}
8211
8212 // Integer Remainder with registers.
8213 instruct modI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8214 match(Set dst (ModI src1 src2));
8215 ins_cost(10*DEFAULT_COST);
8216
8217 expand %{
8218 immI16 imm %{ (int)-1 %}
8219 flagsReg tmp1;
8220 iRegIdst tmp2;
8221 iRegIdst tmp3;
8222 cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1
8223 divI_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2
8224 cmovI_bne_negI_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1
8225 mulI_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2
8226 subI_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3
8227 %}
8228 %}
8229
8230 // Long Remainder with registers
8231 instruct modL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2, flagsRegCR0 cr0) %{
8232 match(Set dst (ModL src1 src2));
8233 ins_cost(10*DEFAULT_COST);
8234
8235 expand %{
8236 immL16 imm %{ (int)-1 %}
8237 flagsReg tmp1;
8238 iRegLdst tmp2;
8239 iRegLdst tmp3;
8240 cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1
8241 divL_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2
8242 cmovL_bne_negL_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1
8243 mulL_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2
8244 subL_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3
8245 %}
8246 %}
8247
8248 // Integer Shift Instructions
8249
8250 // Register Shift Left
8251
8252 // Clear all but the lowest #mask bits.
8253 // Used to normalize shift amounts in registers.
8254 instruct maskI_reg_imm(iRegIdst dst, iRegIsrc src, uimmI6 mask) %{
8255 // no match-rule, false predicate
8256 effect(DEF dst, USE src, USE mask);
8257 predicate(false);
8258
8259 format %{ "MASK $dst, $src, $mask \t// clear $mask upper bits" %}
8260 size(4);
8261 ins_encode %{
8262 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8263 __ clrldi($dst$$Register, $src$$Register, $mask$$constant);
8264 %}
8265 ins_pipe(pipe_class_default);
8266 %}
8267
8268 instruct lShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8269 // no match-rule, false predicate
8270 effect(DEF dst, USE src1, USE src2);
8271 predicate(false);
8272
8273 format %{ "SLW $dst, $src1, $src2" %}
8274 size(4);
8275 ins_encode %{
8276 // TODO: PPC port $archOpcode(ppc64Opcode_slw);
8277 __ slw($dst$$Register, $src1$$Register, $src2$$Register);
8278 %}
8279 ins_pipe(pipe_class_default);
8280 %}
8281
8282 instruct lShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8283 match(Set dst (LShiftI src1 src2));
8284 ins_cost(DEFAULT_COST*2);
8285 expand %{
8286 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8287 iRegIdst tmpI;
8288 maskI_reg_imm(tmpI, src2, mask);
8289 lShiftI_reg_reg(dst, src1, tmpI);
8290 %}
8291 %}
8292
8293 // Register Shift Left Immediate
8294 instruct lShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8295 match(Set dst (LShiftI src1 src2));
8296
8297 format %{ "SLWI $dst, $src1, ($src2 & 0x1f)" %}
8298 size(4);
8299 ins_encode %{
8300 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8301 __ slwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8302 %}
8303 ins_pipe(pipe_class_default);
8304 %}
8305
8306 // AndI with negpow2-constant + LShiftI
8307 instruct lShiftI_andI_immInegpow2_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{
8308 match(Set dst (LShiftI (AndI src1 src2) src3));
8309 predicate(UseRotateAndMaskInstructionsPPC64);
8310
8311 format %{ "RLWINM $dst, lShiftI(AndI($src1, $src2), $src3)" %}
8312 size(4);
8313 ins_encode %{
8314 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi
8315 long src2 = $src2$$constant;
8316 long src3 = $src3$$constant;
8317 long maskbits = src3 + log2_long((jlong) (julong) (juint) -src2);
8318 if (maskbits >= 32) {
8319 __ li($dst$$Register, 0); // addi
8320 } else {
8321 __ rlwinm($dst$$Register, $src1$$Register, src3 & 0x1f, 0, (31-maskbits) & 0x1f);
8322 }
8323 %}
8324 ins_pipe(pipe_class_default);
8325 %}
8326
8327 // RShiftI + AndI with negpow2-constant + LShiftI
8328 instruct lShiftI_andI_immInegpow2_rShiftI_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{
8329 match(Set dst (LShiftI (AndI (RShiftI src1 src3) src2) src3));
8330 predicate(UseRotateAndMaskInstructionsPPC64);
8331
8332 format %{ "RLWINM $dst, lShiftI(AndI(RShiftI($src1, $src3), $src2), $src3)" %}
8333 size(4);
8334 ins_encode %{
8335 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi
8336 long src2 = $src2$$constant;
8337 long src3 = $src3$$constant;
8338 long maskbits = src3 + log2_long((jlong) (julong) (juint) -src2);
8339 if (maskbits >= 32) {
8340 __ li($dst$$Register, 0); // addi
8341 } else {
8342 __ rlwinm($dst$$Register, $src1$$Register, 0, 0, (31-maskbits) & 0x1f);
8343 }
8344 %}
8345 ins_pipe(pipe_class_default);
8346 %}
8347
8348 instruct lShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8349 // no match-rule, false predicate
8350 effect(DEF dst, USE src1, USE src2);
8351 predicate(false);
8352
8353 format %{ "SLD $dst, $src1, $src2" %}
8354 size(4);
8355 ins_encode %{
8356 // TODO: PPC port $archOpcode(ppc64Opcode_sld);
8357 __ sld($dst$$Register, $src1$$Register, $src2$$Register);
8358 %}
8359 ins_pipe(pipe_class_default);
8360 %}
8361
8362 // Register Shift Left
8363 instruct lShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8364 match(Set dst (LShiftL src1 src2));
8365 ins_cost(DEFAULT_COST*2);
8366 expand %{
8367 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8368 iRegIdst tmpI;
8369 maskI_reg_imm(tmpI, src2, mask);
8370 lShiftL_regL_regI(dst, src1, tmpI);
8371 %}
8372 %}
8373
8374 // Register Shift Left Immediate
8375 instruct lshiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8376 match(Set dst (LShiftL src1 src2));
8377 format %{ "SLDI $dst, $src1, ($src2 & 0x3f)" %}
8378 size(4);
8379 ins_encode %{
8380 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8381 __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8382 %}
8383 ins_pipe(pipe_class_default);
8384 %}
8385
8386 // If we shift more than 32 bits, we need not convert I2L.
8387 instruct lShiftL_regI_immGE32(iRegLdst dst, iRegIsrc src1, uimmI6_ge32 src2) %{
8388 match(Set dst (LShiftL (ConvI2L src1) src2));
8389 ins_cost(DEFAULT_COST);
8390
8391 size(4);
8392 format %{ "SLDI $dst, i2l($src1), $src2" %}
8393 ins_encode %{
8394 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8395 __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8396 %}
8397 ins_pipe(pipe_class_default);
8398 %}
8399
8400 // Shift a postivie int to the left.
8401 // Clrlsldi clears the upper 32 bits and shifts.
8402 instruct scaledPositiveI2L_lShiftL_convI2L_reg_imm6(iRegLdst dst, iRegIsrc src1, uimmI6 src2) %{
8403 match(Set dst (LShiftL (ConvI2L src1) src2));
8404 predicate(((ConvI2LNode*)(_kids[0]->_leaf))->type()->is_long()->is_positive_int());
8405
8406 format %{ "SLDI $dst, i2l(positive_int($src1)), $src2" %}
8407 size(4);
8408 ins_encode %{
8409 // TODO: PPC port $archOpcode(ppc64Opcode_rldic);
8410 __ clrlsldi($dst$$Register, $src1$$Register, 0x20, $src2$$constant);
8411 %}
8412 ins_pipe(pipe_class_default);
8413 %}
8414
8415 instruct arShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8416 // no match-rule, false predicate
8417 effect(DEF dst, USE src1, USE src2);
8418 predicate(false);
8419
8420 format %{ "SRAW $dst, $src1, $src2" %}
8421 size(4);
8422 ins_encode %{
8423 // TODO: PPC port $archOpcode(ppc64Opcode_sraw);
8424 __ sraw($dst$$Register, $src1$$Register, $src2$$Register);
8425 %}
8426 ins_pipe(pipe_class_default);
8427 %}
8428
8429 // Register Arithmetic Shift Right
8430 instruct arShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8431 match(Set dst (RShiftI src1 src2));
8432 ins_cost(DEFAULT_COST*2);
8433 expand %{
8434 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8435 iRegIdst tmpI;
8436 maskI_reg_imm(tmpI, src2, mask);
8437 arShiftI_reg_reg(dst, src1, tmpI);
8438 %}
8439 %}
8440
8441 // Register Arithmetic Shift Right Immediate
8442 instruct arShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8443 match(Set dst (RShiftI src1 src2));
8444
8445 format %{ "SRAWI $dst, $src1, ($src2 & 0x1f)" %}
8446 size(4);
8447 ins_encode %{
8448 // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
8449 __ srawi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8450 %}
8451 ins_pipe(pipe_class_default);
8452 %}
8453
8454 instruct arShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8455 // no match-rule, false predicate
8456 effect(DEF dst, USE src1, USE src2);
8457 predicate(false);
8458
8459 format %{ "SRAD $dst, $src1, $src2" %}
8460 size(4);
8461 ins_encode %{
8462 // TODO: PPC port $archOpcode(ppc64Opcode_srad);
8463 __ srad($dst$$Register, $src1$$Register, $src2$$Register);
8464 %}
8465 ins_pipe(pipe_class_default);
8466 %}
8467
8468 // Register Shift Right Arithmetic Long
8469 instruct arShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8470 match(Set dst (RShiftL src1 src2));
8471 ins_cost(DEFAULT_COST*2);
8472
8473 expand %{
8474 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8475 iRegIdst tmpI;
8476 maskI_reg_imm(tmpI, src2, mask);
8477 arShiftL_regL_regI(dst, src1, tmpI);
8478 %}
8479 %}
8480
8481 // Register Shift Right Immediate
8482 instruct arShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8483 match(Set dst (RShiftL src1 src2));
8484
8485 format %{ "SRADI $dst, $src1, ($src2 & 0x3f)" %}
8486 size(4);
8487 ins_encode %{
8488 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
8489 __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8490 %}
8491 ins_pipe(pipe_class_default);
8492 %}
8493
8494 // RShiftL + ConvL2I
8495 instruct convL2I_arShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{
8496 match(Set dst (ConvL2I (RShiftL src1 src2)));
8497
8498 format %{ "SRADI $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %}
8499 size(4);
8500 ins_encode %{
8501 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
8502 __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8503 %}
8504 ins_pipe(pipe_class_default);
8505 %}
8506
8507 instruct urShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8508 // no match-rule, false predicate
8509 effect(DEF dst, USE src1, USE src2);
8510 predicate(false);
8511
8512 format %{ "SRW $dst, $src1, $src2" %}
8513 size(4);
8514 ins_encode %{
8515 // TODO: PPC port $archOpcode(ppc64Opcode_srw);
8516 __ srw($dst$$Register, $src1$$Register, $src2$$Register);
8517 %}
8518 ins_pipe(pipe_class_default);
8519 %}
8520
8521 // Register Shift Right
8522 instruct urShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8523 match(Set dst (URShiftI src1 src2));
8524 ins_cost(DEFAULT_COST*2);
8525
8526 expand %{
8527 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8528 iRegIdst tmpI;
8529 maskI_reg_imm(tmpI, src2, mask);
8530 urShiftI_reg_reg(dst, src1, tmpI);
8531 %}
8532 %}
8533
8534 // Register Shift Right Immediate
8535 instruct urShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8536 match(Set dst (URShiftI src1 src2));
8537
8538 format %{ "SRWI $dst, $src1, ($src2 & 0x1f)" %}
8539 size(4);
8540 ins_encode %{
8541 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8542 __ srwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8543 %}
8544 ins_pipe(pipe_class_default);
8545 %}
8546
8547 instruct urShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8548 // no match-rule, false predicate
8549 effect(DEF dst, USE src1, USE src2);
8550 predicate(false);
8551
8552 format %{ "SRD $dst, $src1, $src2" %}
8553 size(4);
8554 ins_encode %{
8555 // TODO: PPC port $archOpcode(ppc64Opcode_srd);
8556 __ srd($dst$$Register, $src1$$Register, $src2$$Register);
8557 %}
8558 ins_pipe(pipe_class_default);
8559 %}
8560
8561 // Register Shift Right
8562 instruct urShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8563 match(Set dst (URShiftL src1 src2));
8564 ins_cost(DEFAULT_COST*2);
8565
8566 expand %{
8567 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8568 iRegIdst tmpI;
8569 maskI_reg_imm(tmpI, src2, mask);
8570 urShiftL_regL_regI(dst, src1, tmpI);
8571 %}
8572 %}
8573
8574 // Register Shift Right Immediate
8575 instruct urShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8576 match(Set dst (URShiftL src1 src2));
8577
8578 format %{ "SRDI $dst, $src1, ($src2 & 0x3f)" %}
8579 size(4);
8580 ins_encode %{
8581 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8582 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8583 %}
8584 ins_pipe(pipe_class_default);
8585 %}
8586
8587 // URShiftL + ConvL2I.
8588 instruct convL2I_urShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{
8589 match(Set dst (ConvL2I (URShiftL src1 src2)));
8590
8591 format %{ "SRDI $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %}
8592 size(4);
8593 ins_encode %{
8594 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8595 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8596 %}
8597 ins_pipe(pipe_class_default);
8598 %}
8599
8600 // Register Shift Right Immediate with a CastP2X
8601 instruct shrP_convP2X_reg_imm6(iRegLdst dst, iRegP_N2P src1, uimmI6 src2) %{
8602 match(Set dst (URShiftL (CastP2X src1) src2));
8603
8604 format %{ "SRDI $dst, $src1, $src2 \t// Cast ptr $src1 to long and shift" %}
8605 size(4);
8606 ins_encode %{
8607 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8608 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8609 %}
8610 ins_pipe(pipe_class_default);
8611 %}
8612
8613 instruct sxtI_reg(iRegIdst dst, iRegIsrc src) %{
8614 match(Set dst (ConvL2I (ConvI2L src)));
8615
8616 format %{ "EXTSW $dst, $src \t// int->int" %}
8617 size(4);
8618 ins_encode %{
8619 // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
8620 __ extsw($dst$$Register, $src$$Register);
8621 %}
8622 ins_pipe(pipe_class_default);
8623 %}
8624
8625 //----------Rotate Instructions------------------------------------------------
8626
8627 // Rotate Left by 8-bit immediate
8628 instruct rotlI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 lshift, immI8 rshift) %{
8629 match(Set dst (OrI (LShiftI src lshift) (URShiftI src rshift)));
8630 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8631
8632 format %{ "ROTLWI $dst, $src, $lshift" %}
8633 size(4);
8634 ins_encode %{
8635 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8636 __ rotlwi($dst$$Register, $src$$Register, $lshift$$constant);
8637 %}
8638 ins_pipe(pipe_class_default);
8639 %}
8640
8641 // Rotate Right by 8-bit immediate
8642 instruct rotrI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 rshift, immI8 lshift) %{
8643 match(Set dst (OrI (URShiftI src rshift) (LShiftI src lshift)));
8644 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8645
8646 format %{ "ROTRWI $dst, $rshift" %}
8647 size(4);
8648 ins_encode %{
8649 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8650 __ rotrwi($dst$$Register, $src$$Register, $rshift$$constant);
8651 %}
8652 ins_pipe(pipe_class_default);
8653 %}
8654
8655 //----------Floating Point Arithmetic Instructions-----------------------------
8656
8657 // Add float single precision
8658 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
8659 match(Set dst (AddF src1 src2));
8660
8661 format %{ "FADDS $dst, $src1, $src2" %}
8662 size(4);
8663 ins_encode %{
8664 // TODO: PPC port $archOpcode(ppc64Opcode_fadds);
8665 __ fadds($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8666 %}
8667 ins_pipe(pipe_class_default);
8668 %}
8669
8670 // Add float double precision
8671 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
8672 match(Set dst (AddD src1 src2));
8673
8674 format %{ "FADD $dst, $src1, $src2" %}
8675 size(4);
8676 ins_encode %{
8677 // TODO: PPC port $archOpcode(ppc64Opcode_fadd);
8678 __ fadd($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8679 %}
8680 ins_pipe(pipe_class_default);
8681 %}
8682
8683 // Sub float single precision
8684 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
8685 match(Set dst (SubF src1 src2));
8686
8687 format %{ "FSUBS $dst, $src1, $src2" %}
8688 size(4);
8689 ins_encode %{
8690 // TODO: PPC port $archOpcode(ppc64Opcode_fsubs);
8691 __ fsubs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8692 %}
8693 ins_pipe(pipe_class_default);
8694 %}
8695
8696 // Sub float double precision
8697 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
8698 match(Set dst (SubD src1 src2));
8699 format %{ "FSUB $dst, $src1, $src2" %}
8700 size(4);
8701 ins_encode %{
8702 // TODO: PPC port $archOpcode(ppc64Opcode_fsub);
8703 __ fsub($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8704 %}
8705 ins_pipe(pipe_class_default);
8706 %}
8707
8708 // Mul float single precision
8709 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
8710 match(Set dst (MulF src1 src2));
8711 format %{ "FMULS $dst, $src1, $src2" %}
8712 size(4);
8713 ins_encode %{
8714 // TODO: PPC port $archOpcode(ppc64Opcode_fmuls);
8715 __ fmuls($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8716 %}
8717 ins_pipe(pipe_class_default);
8718 %}
8719
8720 // Mul float double precision
8721 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
8722 match(Set dst (MulD src1 src2));
8723 format %{ "FMUL $dst, $src1, $src2" %}
8724 size(4);
8725 ins_encode %{
8726 // TODO: PPC port $archOpcode(ppc64Opcode_fmul);
8727 __ fmul($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8728 %}
8729 ins_pipe(pipe_class_default);
8730 %}
8731
8732 // Div float single precision
8733 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
8734 match(Set dst (DivF src1 src2));
8735 format %{ "FDIVS $dst, $src1, $src2" %}
8736 size(4);
8737 ins_encode %{
8738 // TODO: PPC port $archOpcode(ppc64Opcode_fdivs);
8739 __ fdivs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8740 %}
8741 ins_pipe(pipe_class_default);
8742 %}
8743
8744 // Div float double precision
8745 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
8746 match(Set dst (DivD src1 src2));
8747 format %{ "FDIV $dst, $src1, $src2" %}
8748 size(4);
8749 ins_encode %{
8750 // TODO: PPC port $archOpcode(ppc64Opcode_fdiv);
8751 __ fdiv($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8752 %}
8753 ins_pipe(pipe_class_default);
8754 %}
8755
8756 // Absolute float single precision
8757 instruct absF_reg(regF dst, regF src) %{
8758 match(Set dst (AbsF src));
8759 format %{ "FABS $dst, $src \t// float" %}
8760 size(4);
8761 ins_encode %{
8762 // TODO: PPC port $archOpcode(ppc64Opcode_fabs);
8763 __ fabs($dst$$FloatRegister, $src$$FloatRegister);
8764 %}
8765 ins_pipe(pipe_class_default);
8766 %}
8767
8768 // Absolute float double precision
8769 instruct absD_reg(regD dst, regD src) %{
8770 match(Set dst (AbsD src));
8771 format %{ "FABS $dst, $src \t// double" %}
8772 size(4);
8773 ins_encode %{
8774 // TODO: PPC port $archOpcode(ppc64Opcode_fabs);
8775 __ fabs($dst$$FloatRegister, $src$$FloatRegister);
8776 %}
8777 ins_pipe(pipe_class_default);
8778 %}
8779
8780 instruct negF_reg(regF dst, regF src) %{
8781 match(Set dst (NegF src));
8782 format %{ "FNEG $dst, $src \t// float" %}
8783 size(4);
8784 ins_encode %{
8785 // TODO: PPC port $archOpcode(ppc64Opcode_fneg);
8786 __ fneg($dst$$FloatRegister, $src$$FloatRegister);
8787 %}
8788 ins_pipe(pipe_class_default);
8789 %}
8790
8791 instruct negD_reg(regD dst, regD src) %{
8792 match(Set dst (NegD src));
8793 format %{ "FNEG $dst, $src \t// double" %}
8794 size(4);
8795 ins_encode %{
8796 // TODO: PPC port $archOpcode(ppc64Opcode_fneg);
8797 __ fneg($dst$$FloatRegister, $src$$FloatRegister);
8798 %}
8799 ins_pipe(pipe_class_default);
8800 %}
8801
8802 // AbsF + NegF.
8803 instruct negF_absF_reg(regF dst, regF src) %{
8804 match(Set dst (NegF (AbsF src)));
8805 format %{ "FNABS $dst, $src \t// float" %}
8806 size(4);
8807 ins_encode %{
8808 // TODO: PPC port $archOpcode(ppc64Opcode_fnabs);
8809 __ fnabs($dst$$FloatRegister, $src$$FloatRegister);
8810 %}
8811 ins_pipe(pipe_class_default);
8812 %}
8813
8814 // AbsD + NegD.
8815 instruct negD_absD_reg(regD dst, regD src) %{
8816 match(Set dst (NegD (AbsD src)));
8817 format %{ "FNABS $dst, $src \t// double" %}
8818 size(4);
8819 ins_encode %{
8820 // TODO: PPC port $archOpcode(ppc64Opcode_fnabs);
8821 __ fnabs($dst$$FloatRegister, $src$$FloatRegister);
8822 %}
8823 ins_pipe(pipe_class_default);
8824 %}
8825
8826 // VM_Version::has_fsqrt() decides if this node will be used.
8827 // Sqrt float double precision
8828 instruct sqrtD_reg(regD dst, regD src) %{
8829 match(Set dst (SqrtD src));
8830 format %{ "FSQRT $dst, $src" %}
8831 size(4);
8832 ins_encode %{
8833 // TODO: PPC port $archOpcode(ppc64Opcode_fsqrt);
8834 __ fsqrt($dst$$FloatRegister, $src$$FloatRegister);
8835 %}
8836 ins_pipe(pipe_class_default);
8837 %}
8838
8839 // Single-precision sqrt.
8840 instruct sqrtF_reg(regF dst, regF src) %{
8841 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
8842 predicate(VM_Version::has_fsqrts());
8843 ins_cost(DEFAULT_COST);
8844
8845 format %{ "FSQRTS $dst, $src" %}
8846 size(4);
8847 ins_encode %{
8848 // TODO: PPC port $archOpcode(ppc64Opcode_fsqrts);
8849 __ fsqrts($dst$$FloatRegister, $src$$FloatRegister);
8850 %}
8851 ins_pipe(pipe_class_default);
8852 %}
8853
8854 instruct roundDouble_nop(regD dst) %{
8855 match(Set dst (RoundDouble dst));
8856 ins_cost(0);
8857
8858 format %{ " -- \t// RoundDouble not needed - empty" %}
8859 size(0);
8860 // PPC results are already "rounded" (i.e., normal-format IEEE).
8861 ins_encode( /*empty*/ );
8862 ins_pipe(pipe_class_default);
8863 %}
8864
8865 instruct roundFloat_nop(regF dst) %{
8866 match(Set dst (RoundFloat dst));
8867 ins_cost(0);
8868
8869 format %{ " -- \t// RoundFloat not needed - empty" %}
8870 size(0);
8871 // PPC results are already "rounded" (i.e., normal-format IEEE).
8872 ins_encode( /*empty*/ );
8873 ins_pipe(pipe_class_default);
8874 %}
8875
8876 //----------Logical Instructions-----------------------------------------------
8877
8878 // And Instructions
8879
8880 // Register And
8881 instruct andI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8882 match(Set dst (AndI src1 src2));
8883 format %{ "AND $dst, $src1, $src2" %}
8884 size(4);
8885 ins_encode %{
8886 // TODO: PPC port $archOpcode(ppc64Opcode_and);
8887 __ andr($dst$$Register, $src1$$Register, $src2$$Register);
8888 %}
8889 ins_pipe(pipe_class_default);
8890 %}
8891
8892 // Immediate And
8893 instruct andI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2, flagsRegCR0 cr0) %{
8894 match(Set dst (AndI src1 src2));
8895 effect(KILL cr0);
8896
8897 format %{ "ANDI $dst, $src1, $src2" %}
8898 size(4);
8899 ins_encode %{
8900 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
8901 // FIXME: avoid andi_ ?
8902 __ andi_($dst$$Register, $src1$$Register, $src2$$constant);
8903 %}
8904 ins_pipe(pipe_class_default);
8905 %}
8906
8907 // Immediate And where the immediate is a negative power of 2.
8908 instruct andI_reg_immInegpow2(iRegIdst dst, iRegIsrc src1, immInegpow2 src2) %{
8909 match(Set dst (AndI src1 src2));
8910 format %{ "ANDWI $dst, $src1, $src2" %}
8911 size(4);
8912 ins_encode %{
8913 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8914 __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)(julong)(juint)-($src2$$constant)));
8915 %}
8916 ins_pipe(pipe_class_default);
8917 %}
8918
8919 instruct andI_reg_immIpow2minus1(iRegIdst dst, iRegIsrc src1, immIpow2minus1 src2) %{
8920 match(Set dst (AndI src1 src2));
8921 format %{ "ANDWI $dst, $src1, $src2" %}
8922 size(4);
8923 ins_encode %{
8924 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8925 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
8926 %}
8927 ins_pipe(pipe_class_default);
8928 %}
8929
8930 instruct andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src1, immIpowerOf2 src2) %{
8931 match(Set dst (AndI src1 src2));
8932 predicate(UseRotateAndMaskInstructionsPPC64);
8933 format %{ "ANDWI $dst, $src1, $src2" %}
8934 size(4);
8935 ins_encode %{
8936 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8937 __ rlwinm($dst$$Register, $src1$$Register, 0,
8938 (31-log2_long((jlong) $src2$$constant)) & 0x1f, (31-log2_long((jlong) $src2$$constant)) & 0x1f);
8939 %}
8940 ins_pipe(pipe_class_default);
8941 %}
8942
8943 // Register And Long
8944 instruct andL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8945 match(Set dst (AndL src1 src2));
8946 ins_cost(DEFAULT_COST);
8947
8948 format %{ "AND $dst, $src1, $src2 \t// long" %}
8949 size(4);
8950 ins_encode %{
8951 // TODO: PPC port $archOpcode(ppc64Opcode_and);
8952 __ andr($dst$$Register, $src1$$Register, $src2$$Register);
8953 %}
8954 ins_pipe(pipe_class_default);
8955 %}
8956
8957 // Immediate And long
8958 instruct andL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2, flagsRegCR0 cr0) %{
8959 match(Set dst (AndL src1 src2));
8960 effect(KILL cr0);
8961 ins_cost(DEFAULT_COST);
8962
8963 format %{ "ANDI $dst, $src1, $src2 \t// long" %}
8964 size(4);
8965 ins_encode %{
8966 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
8967 // FIXME: avoid andi_ ?
8968 __ andi_($dst$$Register, $src1$$Register, $src2$$constant);
8969 %}
8970 ins_pipe(pipe_class_default);
8971 %}
8972
8973 // Immediate And Long where the immediate is a negative power of 2.
8974 instruct andL_reg_immLnegpow2(iRegLdst dst, iRegLsrc src1, immLnegpow2 src2) %{
8975 match(Set dst (AndL src1 src2));
8976 format %{ "ANDDI $dst, $src1, $src2" %}
8977 size(4);
8978 ins_encode %{
8979 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8980 __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)-$src2$$constant));
8981 %}
8982 ins_pipe(pipe_class_default);
8983 %}
8984
8985 instruct andL_reg_immLpow2minus1(iRegLdst dst, iRegLsrc src1, immLpow2minus1 src2) %{
8986 match(Set dst (AndL src1 src2));
8987 format %{ "ANDDI $dst, $src1, $src2" %}
8988 size(4);
8989 ins_encode %{
8990 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8991 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
8992 %}
8993 ins_pipe(pipe_class_default);
8994 %}
8995
8996 // AndL + ConvL2I.
8997 instruct convL2I_andL_reg_immLpow2minus1(iRegIdst dst, iRegLsrc src1, immLpow2minus1 src2) %{
8998 match(Set dst (ConvL2I (AndL src1 src2)));
8999 ins_cost(DEFAULT_COST);
9000
9001 format %{ "ANDDI $dst, $src1, $src2 \t// long + l2i" %}
9002 size(4);
9003 ins_encode %{
9004 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9005 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
9006 %}
9007 ins_pipe(pipe_class_default);
9008 %}
9009
9010 // Or Instructions
9011
9012 // Register Or
9013 instruct orI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9014 match(Set dst (OrI src1 src2));
9015 format %{ "OR $dst, $src1, $src2" %}
9016 size(4);
9017 ins_encode %{
9018 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9019 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9020 %}
9021 ins_pipe(pipe_class_default);
9022 %}
9023
9024 // Expand does not work with above instruct. (??)
9025 instruct orI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9026 // no match-rule
9027 effect(DEF dst, USE src1, USE src2);
9028 format %{ "OR $dst, $src1, $src2" %}
9029 size(4);
9030 ins_encode %{
9031 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9032 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9033 %}
9034 ins_pipe(pipe_class_default);
9035 %}
9036
9037 instruct tree_orI_orI_orI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
9038 match(Set dst (OrI (OrI (OrI src1 src2) src3) src4));
9039 ins_cost(DEFAULT_COST*3);
9040
9041 expand %{
9042 // FIXME: we should do this in the ideal world.
9043 iRegIdst tmp1;
9044 iRegIdst tmp2;
9045 orI_reg_reg(tmp1, src1, src2);
9046 orI_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg.
9047 orI_reg_reg(dst, tmp1, tmp2);
9048 %}
9049 %}
9050
9051 // Immediate Or
9052 instruct orI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{
9053 match(Set dst (OrI src1 src2));
9054 format %{ "ORI $dst, $src1, $src2" %}
9055 size(4);
9056 ins_encode %{
9057 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
9058 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
9059 %}
9060 ins_pipe(pipe_class_default);
9061 %}
9062
9063 // Register Or Long
9064 instruct orL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9065 match(Set dst (OrL src1 src2));
9066 ins_cost(DEFAULT_COST);
9067
9068 size(4);
9069 format %{ "OR $dst, $src1, $src2 \t// long" %}
9070 ins_encode %{
9071 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9072 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9073 %}
9074 ins_pipe(pipe_class_default);
9075 %}
9076
9077 // OrL + ConvL2I.
9078 instruct orI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
9079 match(Set dst (ConvL2I (OrL src1 src2)));
9080 ins_cost(DEFAULT_COST);
9081
9082 format %{ "OR $dst, $src1, $src2 \t// long + l2i" %}
9083 size(4);
9084 ins_encode %{
9085 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9086 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9087 %}
9088 ins_pipe(pipe_class_default);
9089 %}
9090
9091 // Immediate Or long
9092 instruct orL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 con) %{
9093 match(Set dst (OrL src1 con));
9094 ins_cost(DEFAULT_COST);
9095
9096 format %{ "ORI $dst, $src1, $con \t// long" %}
9097 size(4);
9098 ins_encode %{
9099 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
9100 __ ori($dst$$Register, $src1$$Register, ($con$$constant) & 0xFFFF);
9101 %}
9102 ins_pipe(pipe_class_default);
9103 %}
9104
9105 // Xor Instructions
9106
9107 // Register Xor
9108 instruct xorI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9109 match(Set dst (XorI src1 src2));
9110 format %{ "XOR $dst, $src1, $src2" %}
9111 size(4);
9112 ins_encode %{
9113 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9114 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9115 %}
9116 ins_pipe(pipe_class_default);
9117 %}
9118
9119 // Expand does not work with above instruct. (??)
9120 instruct xorI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9121 // no match-rule
9122 effect(DEF dst, USE src1, USE src2);
9123 format %{ "XOR $dst, $src1, $src2" %}
9124 size(4);
9125 ins_encode %{
9126 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9127 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9128 %}
9129 ins_pipe(pipe_class_default);
9130 %}
9131
9132 instruct tree_xorI_xorI_xorI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
9133 match(Set dst (XorI (XorI (XorI src1 src2) src3) src4));
9134 ins_cost(DEFAULT_COST*3);
9135
9136 expand %{
9137 // FIXME: we should do this in the ideal world.
9138 iRegIdst tmp1;
9139 iRegIdst tmp2;
9140 xorI_reg_reg(tmp1, src1, src2);
9141 xorI_reg_reg_2(tmp2, src3, src4); // Adlc complains about xorI_reg_reg.
9142 xorI_reg_reg(dst, tmp1, tmp2);
9143 %}
9144 %}
9145
9146 // Immediate Xor
9147 instruct xorI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{
9148 match(Set dst (XorI src1 src2));
9149 format %{ "XORI $dst, $src1, $src2" %}
9150 size(4);
9151 ins_encode %{
9152 // TODO: PPC port $archOpcode(ppc64Opcode_xori);
9153 __ xori($dst$$Register, $src1$$Register, $src2$$constant);
9154 %}
9155 ins_pipe(pipe_class_default);
9156 %}
9157
9158 // Register Xor Long
9159 instruct xorL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9160 match(Set dst (XorL src1 src2));
9161 ins_cost(DEFAULT_COST);
9162
9163 format %{ "XOR $dst, $src1, $src2 \t// long" %}
9164 size(4);
9165 ins_encode %{
9166 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9167 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9168 %}
9169 ins_pipe(pipe_class_default);
9170 %}
9171
9172 // XorL + ConvL2I.
9173 instruct xorI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
9174 match(Set dst (ConvL2I (XorL src1 src2)));
9175 ins_cost(DEFAULT_COST);
9176
9177 format %{ "XOR $dst, $src1, $src2 \t// long + l2i" %}
9178 size(4);
9179 ins_encode %{
9180 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9181 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9182 %}
9183 ins_pipe(pipe_class_default);
9184 %}
9185
9186 // Immediate Xor Long
9187 instruct xorL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2) %{
9188 match(Set dst (XorL src1 src2));
9189 ins_cost(DEFAULT_COST);
9190
9191 format %{ "XORI $dst, $src1, $src2 \t// long" %}
9192 size(4);
9193 ins_encode %{
9194 // TODO: PPC port $archOpcode(ppc64Opcode_xori);
9195 __ xori($dst$$Register, $src1$$Register, $src2$$constant);
9196 %}
9197 ins_pipe(pipe_class_default);
9198 %}
9199
9200 instruct notI_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{
9201 match(Set dst (XorI src1 src2));
9202 ins_cost(DEFAULT_COST);
9203
9204 format %{ "NOT $dst, $src1 ($src2)" %}
9205 size(4);
9206 ins_encode %{
9207 // TODO: PPC port $archOpcode(ppc64Opcode_nor);
9208 __ nor($dst$$Register, $src1$$Register, $src1$$Register);
9209 %}
9210 ins_pipe(pipe_class_default);
9211 %}
9212
9213 instruct notL_reg(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{
9214 match(Set dst (XorL src1 src2));
9215 ins_cost(DEFAULT_COST);
9216
9217 format %{ "NOT $dst, $src1 ($src2) \t// long" %}
9218 size(4);
9219 ins_encode %{
9220 // TODO: PPC port $archOpcode(ppc64Opcode_nor);
9221 __ nor($dst$$Register, $src1$$Register, $src1$$Register);
9222 %}
9223 ins_pipe(pipe_class_default);
9224 %}
9225
9226 // And-complement
9227 instruct andcI_reg_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2, iRegIsrc src3) %{
9228 match(Set dst (AndI (XorI src1 src2) src3));
9229 ins_cost(DEFAULT_COST);
9230
9231 format %{ "ANDW $dst, xori($src1, $src2), $src3" %}
9232 size(4);
9233 ins_encode( enc_andc(dst, src3, src1) );
9234 ins_pipe(pipe_class_default);
9235 %}
9236
9237 // And-complement
9238 instruct andcL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9239 // no match-rule, false predicate
9240 effect(DEF dst, USE src1, USE src2);
9241 predicate(false);
9242
9243 format %{ "ANDC $dst, $src1, $src2" %}
9244 size(4);
9245 ins_encode %{
9246 // TODO: PPC port $archOpcode(ppc64Opcode_andc);
9247 __ andc($dst$$Register, $src1$$Register, $src2$$Register);
9248 %}
9249 ins_pipe(pipe_class_default);
9250 %}
9251
9252 //----------Moves between int/long and float/double----------------------------
9253 //
9254 // The following rules move values from int/long registers/stack-locations
9255 // to float/double registers/stack-locations and vice versa, without doing any
9256 // conversions. These rules are used to implement the bit-conversion methods
9257 // of java.lang.Float etc., e.g.
9258 // int floatToIntBits(float value)
9259 // float intBitsToFloat(int bits)
9260 //
9261 // Notes on the implementation on ppc64:
9262 // We only provide rules which move between a register and a stack-location,
9263 // because we always have to go through memory when moving between a float
9264 // register and an integer register.
9265
9266 //---------- Chain stack slots between similar types --------
9267
9268 // These are needed so that the rules below can match.
9269
9270 // Load integer from stack slot
9271 instruct stkI_to_regI(iRegIdst dst, stackSlotI src) %{
9272 match(Set dst src);
9273 ins_cost(MEMORY_REF_COST);
9274
9275 format %{ "LWZ $dst, $src" %}
9276 size(4);
9277 ins_encode( enc_lwz(dst, src) );
9278 ins_pipe(pipe_class_memory);
9279 %}
9280
9281 // Store integer to stack slot
9282 instruct regI_to_stkI(stackSlotI dst, iRegIsrc src) %{
9283 match(Set dst src);
9284 ins_cost(MEMORY_REF_COST);
9285
9286 format %{ "STW $src, $dst \t// stk" %}
9287 size(4);
9288 ins_encode( enc_stw(src, dst) ); // rs=rt
9289 ins_pipe(pipe_class_memory);
9290 %}
9291
9292 // Load long from stack slot
9293 instruct stkL_to_regL(iRegLdst dst, stackSlotL src) %{
9294 match(Set dst src);
9295 ins_cost(MEMORY_REF_COST);
9296
9297 format %{ "LD $dst, $src \t// long" %}
9298 size(4);
9299 ins_encode( enc_ld(dst, src) );
9300 ins_pipe(pipe_class_memory);
9301 %}
9302
9303 // Store long to stack slot
9304 instruct regL_to_stkL(stackSlotL dst, iRegLsrc src) %{
9305 match(Set dst src);
9306 ins_cost(MEMORY_REF_COST);
9307
9308 format %{ "STD $src, $dst \t// long" %}
9309 size(4);
9310 ins_encode( enc_std(src, dst) ); // rs=rt
9311 ins_pipe(pipe_class_memory);
9312 %}
9313
9314 //----------Moves between int and float
9315
9316 // Move float value from float stack-location to integer register.
9317 instruct moveF2I_stack_reg(iRegIdst dst, stackSlotF src) %{
9318 match(Set dst (MoveF2I src));
9319 ins_cost(MEMORY_REF_COST);
9320
9321 format %{ "LWZ $dst, $src \t// MoveF2I" %}
9322 size(4);
9323 ins_encode( enc_lwz(dst, src) );
9324 ins_pipe(pipe_class_memory);
9325 %}
9326
9327 // Move float value from float register to integer stack-location.
9328 instruct moveF2I_reg_stack(stackSlotI dst, regF src) %{
9329 match(Set dst (MoveF2I src));
9330 ins_cost(MEMORY_REF_COST);
9331
9332 format %{ "STFS $src, $dst \t// MoveF2I" %}
9333 size(4);
9334 ins_encode( enc_stfs(src, dst) );
9335 ins_pipe(pipe_class_memory);
9336 %}
9337
9338 // Move integer value from integer stack-location to float register.
9339 instruct moveI2F_stack_reg(regF dst, stackSlotI src) %{
9340 match(Set dst (MoveI2F src));
9341 ins_cost(MEMORY_REF_COST);
9342
9343 format %{ "LFS $dst, $src \t// MoveI2F" %}
9344 size(4);
9345 ins_encode %{
9346 // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
9347 int Idisp = $src$$disp + frame_slots_bias($src$$base, ra_);
9348 __ lfs($dst$$FloatRegister, Idisp, $src$$base$$Register);
9349 %}
9350 ins_pipe(pipe_class_memory);
9351 %}
9352
9353 // Move integer value from integer register to float stack-location.
9354 instruct moveI2F_reg_stack(stackSlotF dst, iRegIsrc src) %{
9355 match(Set dst (MoveI2F src));
9356 ins_cost(MEMORY_REF_COST);
9357
9358 format %{ "STW $src, $dst \t// MoveI2F" %}
9359 size(4);
9360 ins_encode( enc_stw(src, dst) );
9361 ins_pipe(pipe_class_memory);
9362 %}
9363
9364 //----------Moves between long and float
9365
9366 instruct moveF2L_reg_stack(stackSlotL dst, regF src) %{
9367 // no match-rule, false predicate
9368 effect(DEF dst, USE src);
9369 predicate(false);
9370
9371 format %{ "storeD $src, $dst \t// STACK" %}
9372 size(4);
9373 ins_encode( enc_stfd(src, dst) );
9374 ins_pipe(pipe_class_default);
9375 %}
9376
9377 //----------Moves between long and double
9378
9379 // Move double value from double stack-location to long register.
9380 instruct moveD2L_stack_reg(iRegLdst dst, stackSlotD src) %{
9381 match(Set dst (MoveD2L src));
9382 ins_cost(MEMORY_REF_COST);
9383 size(4);
9384 format %{ "LD $dst, $src \t// MoveD2L" %}
9385 ins_encode( enc_ld(dst, src) );
9386 ins_pipe(pipe_class_memory);
9387 %}
9388
9389 // Move double value from double register to long stack-location.
9390 instruct moveD2L_reg_stack(stackSlotL dst, regD src) %{
9391 match(Set dst (MoveD2L src));
9392 effect(DEF dst, USE src);
9393 ins_cost(MEMORY_REF_COST);
9394
9395 format %{ "STFD $src, $dst \t// MoveD2L" %}
9396 size(4);
9397 ins_encode( enc_stfd(src, dst) );
9398 ins_pipe(pipe_class_memory);
9399 %}
9400
9401 // Move long value from long stack-location to double register.
9402 instruct moveL2D_stack_reg(regD dst, stackSlotL src) %{
9403 match(Set dst (MoveL2D src));
9404 ins_cost(MEMORY_REF_COST);
9405
9406 format %{ "LFD $dst, $src \t// MoveL2D" %}
9407 size(4);
9408 ins_encode( enc_lfd(dst, src) );
9409 ins_pipe(pipe_class_memory);
9410 %}
9411
9412 // Move long value from long register to double stack-location.
9413 instruct moveL2D_reg_stack(stackSlotD dst, iRegLsrc src) %{
9414 match(Set dst (MoveL2D src));
9415 ins_cost(MEMORY_REF_COST);
9416
9417 format %{ "STD $src, $dst \t// MoveL2D" %}
9418 size(4);
9419 ins_encode( enc_std(src, dst) );
9420 ins_pipe(pipe_class_memory);
9421 %}
9422
9423 //----------Register Move Instructions-----------------------------------------
9424
9425 // Replicate for Superword
9426
9427 instruct moveReg(iRegLdst dst, iRegIsrc src) %{
9428 predicate(false);
9429 effect(DEF dst, USE src);
9430
9431 format %{ "MR $dst, $src \t// replicate " %}
9432 // variable size, 0 or 4.
9433 ins_encode %{
9434 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9435 __ mr_if_needed($dst$$Register, $src$$Register);
9436 %}
9437 ins_pipe(pipe_class_default);
9438 %}
9439
9440 //----------Cast instructions (Java-level type cast)---------------------------
9441
9442 // Cast Long to Pointer for unsafe natives.
9443 instruct castX2P(iRegPdst dst, iRegLsrc src) %{
9444 match(Set dst (CastX2P src));
9445
9446 format %{ "MR $dst, $src \t// Long->Ptr" %}
9447 // variable size, 0 or 4.
9448 ins_encode %{
9449 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9450 __ mr_if_needed($dst$$Register, $src$$Register);
9451 %}
9452 ins_pipe(pipe_class_default);
9453 %}
9454
9455 // Cast Pointer to Long for unsafe natives.
9456 instruct castP2X(iRegLdst dst, iRegP_N2P src) %{
9457 match(Set dst (CastP2X src));
9458
9459 format %{ "MR $dst, $src \t// Ptr->Long" %}
9460 // variable size, 0 or 4.
9461 ins_encode %{
9462 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9463 __ mr_if_needed($dst$$Register, $src$$Register);
9464 %}
9465 ins_pipe(pipe_class_default);
9466 %}
9467
9468 instruct castPP(iRegPdst dst) %{
9469 match(Set dst (CastPP dst));
9470 format %{ " -- \t// castPP of $dst" %}
9471 size(0);
9472 ins_encode( /*empty*/ );
9473 ins_pipe(pipe_class_default);
9474 %}
9475
9476 instruct castII(iRegIdst dst) %{
9477 match(Set dst (CastII dst));
9478 format %{ " -- \t// castII of $dst" %}
9479 size(0);
9480 ins_encode( /*empty*/ );
9481 ins_pipe(pipe_class_default);
9482 %}
9483
9484 instruct checkCastPP(iRegPdst dst) %{
9485 match(Set dst (CheckCastPP dst));
9486 format %{ " -- \t// checkcastPP of $dst" %}
9487 size(0);
9488 ins_encode( /*empty*/ );
9489 ins_pipe(pipe_class_default);
9490 %}
9491
9492 //----------Convert instructions-----------------------------------------------
9493
9494 // Convert to boolean.
9495
9496 // int_to_bool(src) : { 1 if src != 0
9497 // { 0 else
9498 //
9499 // strategy:
9500 // 1) Count leading zeros of 32 bit-value src,
9501 // this returns 32 (0b10.0000) iff src == 0 and <32 otherwise.
9502 // 2) Shift 5 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise.
9503 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0.
9504
9505 // convI2Bool
9506 instruct convI2Bool_reg__cntlz_Ex(iRegIdst dst, iRegIsrc src) %{
9507 match(Set dst (Conv2B src));
9508 predicate(UseCountLeadingZerosInstructionsPPC64);
9509 ins_cost(DEFAULT_COST);
9510
9511 expand %{
9512 immI shiftAmount %{ 0x5 %}
9513 uimmI16 mask %{ 0x1 %}
9514 iRegIdst tmp1;
9515 iRegIdst tmp2;
9516 countLeadingZerosI(tmp1, src);
9517 urShiftI_reg_imm(tmp2, tmp1, shiftAmount);
9518 xorI_reg_uimm16(dst, tmp2, mask);
9519 %}
9520 %}
9521
9522 instruct convI2Bool_reg__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx) %{
9523 match(Set dst (Conv2B src));
9524 effect(TEMP crx);
9525 predicate(!UseCountLeadingZerosInstructionsPPC64);
9526 ins_cost(DEFAULT_COST);
9527
9528 format %{ "CMPWI $crx, $src, #0 \t// convI2B"
9529 "LI $dst, #0\n\t"
9530 "BEQ $crx, done\n\t"
9531 "LI $dst, #1\n"
9532 "done:" %}
9533 size(16);
9534 ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x0, 0x1) );
9535 ins_pipe(pipe_class_compare);
9536 %}
9537
9538 // ConvI2B + XorI
9539 instruct xorI_convI2Bool_reg_immIvalue1__cntlz_Ex(iRegIdst dst, iRegIsrc src, immI_1 mask) %{
9540 match(Set dst (XorI (Conv2B src) mask));
9541 predicate(UseCountLeadingZerosInstructionsPPC64);
9542 ins_cost(DEFAULT_COST);
9543
9544 expand %{
9545 immI shiftAmount %{ 0x5 %}
9546 iRegIdst tmp1;
9547 countLeadingZerosI(tmp1, src);
9548 urShiftI_reg_imm(dst, tmp1, shiftAmount);
9549 %}
9550 %}
9551
9552 instruct xorI_convI2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI_1 mask) %{
9553 match(Set dst (XorI (Conv2B src) mask));
9554 effect(TEMP crx);
9555 predicate(!UseCountLeadingZerosInstructionsPPC64);
9556 ins_cost(DEFAULT_COST);
9557
9558 format %{ "CMPWI $crx, $src, #0 \t// Xor(convI2B($src), $mask)"
9559 "LI $dst, #1\n\t"
9560 "BEQ $crx, done\n\t"
9561 "LI $dst, #0\n"
9562 "done:" %}
9563 size(16);
9564 ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x1, 0x0) );
9565 ins_pipe(pipe_class_compare);
9566 %}
9567
9568 // AndI 0b0..010..0 + ConvI2B
9569 instruct convI2Bool_andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src, immIpowerOf2 mask) %{
9570 match(Set dst (Conv2B (AndI src mask)));
9571 predicate(UseRotateAndMaskInstructionsPPC64);
9572 ins_cost(DEFAULT_COST);
9573
9574 format %{ "RLWINM $dst, $src, $mask \t// convI2B(AndI($src, $mask))" %}
9575 size(4);
9576 ins_encode %{
9577 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
9578 __ rlwinm($dst$$Register, $src$$Register, (32-log2_long((jlong)$mask$$constant)) & 0x1f, 31, 31);
9579 %}
9580 ins_pipe(pipe_class_default);
9581 %}
9582
9583 // Convert pointer to boolean.
9584 //
9585 // ptr_to_bool(src) : { 1 if src != 0
9586 // { 0 else
9587 //
9588 // strategy:
9589 // 1) Count leading zeros of 64 bit-value src,
9590 // this returns 64 (0b100.0000) iff src == 0 and <64 otherwise.
9591 // 2) Shift 6 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise.
9592 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0.
9593
9594 // ConvP2B
9595 instruct convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src) %{
9596 match(Set dst (Conv2B src));
9597 predicate(UseCountLeadingZerosInstructionsPPC64);
9598 ins_cost(DEFAULT_COST);
9599
9600 expand %{
9601 immI shiftAmount %{ 0x6 %}
9602 uimmI16 mask %{ 0x1 %}
9603 iRegIdst tmp1;
9604 iRegIdst tmp2;
9605 countLeadingZerosP(tmp1, src);
9606 urShiftI_reg_imm(tmp2, tmp1, shiftAmount);
9607 xorI_reg_uimm16(dst, tmp2, mask);
9608 %}
9609 %}
9610
9611 instruct convP2Bool_reg__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx) %{
9612 match(Set dst (Conv2B src));
9613 effect(TEMP crx);
9614 predicate(!UseCountLeadingZerosInstructionsPPC64);
9615 ins_cost(DEFAULT_COST);
9616
9617 format %{ "CMPDI $crx, $src, #0 \t// convP2B"
9618 "LI $dst, #0\n\t"
9619 "BEQ $crx, done\n\t"
9620 "LI $dst, #1\n"
9621 "done:" %}
9622 size(16);
9623 ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x0, 0x1) );
9624 ins_pipe(pipe_class_compare);
9625 %}
9626
9627 // ConvP2B + XorI
9628 instruct xorI_convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src, immI_1 mask) %{
9629 match(Set dst (XorI (Conv2B src) mask));
9630 predicate(UseCountLeadingZerosInstructionsPPC64);
9631 ins_cost(DEFAULT_COST);
9632
9633 expand %{
9634 immI shiftAmount %{ 0x6 %}
9635 iRegIdst tmp1;
9636 countLeadingZerosP(tmp1, src);
9637 urShiftI_reg_imm(dst, tmp1, shiftAmount);
9638 %}
9639 %}
9640
9641 instruct xorI_convP2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx, immI_1 mask) %{
9642 match(Set dst (XorI (Conv2B src) mask));
9643 effect(TEMP crx);
9644 predicate(!UseCountLeadingZerosInstructionsPPC64);
9645 ins_cost(DEFAULT_COST);
9646
9647 format %{ "CMPDI $crx, $src, #0 \t// XorI(convP2B($src), $mask)"
9648 "LI $dst, #1\n\t"
9649 "BEQ $crx, done\n\t"
9650 "LI $dst, #0\n"
9651 "done:" %}
9652 size(16);
9653 ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x1, 0x0) );
9654 ins_pipe(pipe_class_compare);
9655 %}
9656
9657 // if src1 < src2, return -1 else return 0
9658 instruct cmpLTMask_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9659 match(Set dst (CmpLTMask src1 src2));
9660 ins_cost(DEFAULT_COST*4);
9661
9662 expand %{
9663 iRegLdst src1s;
9664 iRegLdst src2s;
9665 iRegLdst diff;
9666 convI2L_reg(src1s, src1); // Ensure proper sign extension.
9667 convI2L_reg(src2s, src2); // Ensure proper sign extension.
9668 subL_reg_reg(diff, src1s, src2s);
9669 // Need to consider >=33 bit result, therefore we need signmaskL.
9670 signmask64I_regL(dst, diff);
9671 %}
9672 %}
9673
9674 instruct cmpLTMask_reg_immI0(iRegIdst dst, iRegIsrc src1, immI_0 src2) %{
9675 match(Set dst (CmpLTMask src1 src2)); // if src1 < src2, return -1 else return 0
9676 format %{ "SRAWI $dst, $src1, $src2 \t// CmpLTMask" %}
9677 size(4);
9678 ins_encode %{
9679 // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
9680 __ srawi($dst$$Register, $src1$$Register, 0x1f);
9681 %}
9682 ins_pipe(pipe_class_default);
9683 %}
9684
9685 //----------Arithmetic Conversion Instructions---------------------------------
9686
9687 // Convert to Byte -- nop
9688 // Convert to Short -- nop
9689
9690 // Convert to Int
9691
9692 instruct convB2I_reg(iRegIdst dst, iRegIsrc src, immI_24 amount) %{
9693 match(Set dst (RShiftI (LShiftI src amount) amount));
9694 format %{ "EXTSB $dst, $src \t// byte->int" %}
9695 size(4);
9696 ins_encode %{
9697 // TODO: PPC port $archOpcode(ppc64Opcode_extsb);
9698 __ extsb($dst$$Register, $src$$Register);
9699 %}
9700 ins_pipe(pipe_class_default);
9701 %}
9702
9703 // LShiftI 16 + RShiftI 16 converts short to int.
9704 instruct convS2I_reg(iRegIdst dst, iRegIsrc src, immI_16 amount) %{
9705 match(Set dst (RShiftI (LShiftI src amount) amount));
9706 format %{ "EXTSH $dst, $src \t// short->int" %}
9707 size(4);
9708 ins_encode %{
9709 // TODO: PPC port $archOpcode(ppc64Opcode_extsh);
9710 __ extsh($dst$$Register, $src$$Register);
9711 %}
9712 ins_pipe(pipe_class_default);
9713 %}
9714
9715 // ConvL2I + ConvI2L: Sign extend int in long register.
9716 instruct sxtI_L2L_reg(iRegLdst dst, iRegLsrc src) %{
9717 match(Set dst (ConvI2L (ConvL2I src)));
9718
9719 format %{ "EXTSW $dst, $src \t// long->long" %}
9720 size(4);
9721 ins_encode %{
9722 // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
9723 __ extsw($dst$$Register, $src$$Register);
9724 %}
9725 ins_pipe(pipe_class_default);
9726 %}
9727
9728 instruct convL2I_reg(iRegIdst dst, iRegLsrc src) %{
9729 match(Set dst (ConvL2I src));
9730 format %{ "MR $dst, $src \t// long->int" %}
9731 // variable size, 0 or 4
9732 ins_encode %{
9733 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9734 __ mr_if_needed($dst$$Register, $src$$Register);
9735 %}
9736 ins_pipe(pipe_class_default);
9737 %}
9738
9739 instruct convD2IRaw_regD(regD dst, regD src) %{
9740 // no match-rule, false predicate
9741 effect(DEF dst, USE src);
9742 predicate(false);
9743
9744 format %{ "FCTIWZ $dst, $src \t// convD2I, $src != NaN" %}
9745 size(4);
9746 ins_encode %{
9747 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);;
9748 __ fctiwz($dst$$FloatRegister, $src$$FloatRegister);
9749 %}
9750 ins_pipe(pipe_class_default);
9751 %}
9752
9753 instruct cmovI_bso_stackSlotL(iRegIdst dst, flagsReg crx, stackSlotL src) %{
9754 // no match-rule, false predicate
9755 effect(DEF dst, USE crx, USE src);
9756 predicate(false);
9757
9758 ins_variable_size_depending_on_alignment(true);
9759
9760 format %{ "cmovI $crx, $dst, $src" %}
9761 // Worst case is branch + move + stop, no stop without scheduler.
9762 size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
9763 ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
9764 ins_pipe(pipe_class_default);
9765 %}
9766
9767 instruct cmovI_bso_stackSlotL_conLvalue0_Ex(iRegIdst dst, flagsReg crx, stackSlotL mem) %{
9768 // no match-rule, false predicate
9769 effect(DEF dst, USE crx, USE mem);
9770 predicate(false);
9771
9772 format %{ "CmovI $dst, $crx, $mem \t// postalloc expanded" %}
9773 postalloc_expand %{
9774 //
9775 // replaces
9776 //
9777 // region dst crx mem
9778 // \ | | /
9779 // dst=cmovI_bso_stackSlotL_conLvalue0
9780 //
9781 // with
9782 //
9783 // region dst
9784 // \ /
9785 // dst=loadConI16(0)
9786 // |
9787 // ^ region dst crx mem
9788 // | \ | | /
9789 // dst=cmovI_bso_stackSlotL
9790 //
9791
9792 // Create new nodes.
9793 MachNode *m1 = new (C) loadConI16Node();
9794 MachNode *m2 = new (C) cmovI_bso_stackSlotLNode();
9795
9796 // inputs for new nodes
9797 m1->add_req(n_region);
9798 m2->add_req(n_region, n_crx, n_mem);
9799
9800 // precedences for new nodes
9801 m2->add_prec(m1);
9802
9803 // operands for new nodes
9804 m1->_opnds[0] = op_dst;
9805 m1->_opnds[1] = new (C) immI16Oper(0);
9806
9807 m2->_opnds[0] = op_dst;
9808 m2->_opnds[1] = op_crx;
9809 m2->_opnds[2] = op_mem;
9810
9811 // registers for new nodes
9812 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9813 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9814
9815 // Insert new nodes.
9816 nodes->push(m1);
9817 nodes->push(m2);
9818 %}
9819 %}
9820
9821 // Double to Int conversion, NaN is mapped to 0.
9822 instruct convD2I_reg_ExEx(iRegIdst dst, regD src) %{
9823 match(Set dst (ConvD2I src));
9824 ins_cost(DEFAULT_COST);
9825
9826 expand %{
9827 regD tmpD;
9828 stackSlotL tmpS;
9829 flagsReg crx;
9830 cmpDUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
9831 convD2IRaw_regD(tmpD, src); // Convert float to int (speculated).
9832 moveD2L_reg_stack(tmpS, tmpD); // Store float to stack (speculated).
9833 cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9834 %}
9835 %}
9836
9837 instruct convF2IRaw_regF(regF dst, regF src) %{
9838 // no match-rule, false predicate
9839 effect(DEF dst, USE src);
9840 predicate(false);
9841
9842 format %{ "FCTIWZ $dst, $src \t// convF2I, $src != NaN" %}
9843 size(4);
9844 ins_encode %{
9845 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
9846 __ fctiwz($dst$$FloatRegister, $src$$FloatRegister);
9847 %}
9848 ins_pipe(pipe_class_default);
9849 %}
9850
9851 // Float to Int conversion, NaN is mapped to 0.
9852 instruct convF2I_regF_ExEx(iRegIdst dst, regF src) %{
9853 match(Set dst (ConvF2I src));
9854 ins_cost(DEFAULT_COST);
9855
9856 expand %{
9857 regF tmpF;
9858 stackSlotL tmpS;
9859 flagsReg crx;
9860 cmpFUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
9861 convF2IRaw_regF(tmpF, src); // Convert float to int (speculated).
9862 moveF2L_reg_stack(tmpS, tmpF); // Store float to stack (speculated).
9863 cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9864 %}
9865 %}
9866
9867 // Convert to Long
9868
9869 instruct convI2L_reg(iRegLdst dst, iRegIsrc src) %{
9870 match(Set dst (ConvI2L src));
9871 format %{ "EXTSW $dst, $src \t// int->long" %}
9872 size(4);
9873 ins_encode %{
9874 // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
9875 __ extsw($dst$$Register, $src$$Register);
9876 %}
9877 ins_pipe(pipe_class_default);
9878 %}
9879
9880 // Zero-extend: convert unsigned int to long (convUI2L).
9881 instruct zeroExtendL_regI(iRegLdst dst, iRegIsrc src, immL_32bits mask) %{
9882 match(Set dst (AndL (ConvI2L src) mask));
9883 ins_cost(DEFAULT_COST);
9884
9885 format %{ "CLRLDI $dst, $src, #32 \t// zero-extend int to long" %}
9886 size(4);
9887 ins_encode %{
9888 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9889 __ clrldi($dst$$Register, $src$$Register, 32);
9890 %}
9891 ins_pipe(pipe_class_default);
9892 %}
9893
9894 // Zero-extend: convert unsigned int to long in long register.
9895 instruct zeroExtendL_regL(iRegLdst dst, iRegLsrc src, immL_32bits mask) %{
9896 match(Set dst (AndL src mask));
9897 ins_cost(DEFAULT_COST);
9898
9899 format %{ "CLRLDI $dst, $src, #32 \t// zero-extend int to long" %}
9900 size(4);
9901 ins_encode %{
9902 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9903 __ clrldi($dst$$Register, $src$$Register, 32);
9904 %}
9905 ins_pipe(pipe_class_default);
9906 %}
9907
9908 instruct convF2LRaw_regF(regF dst, regF src) %{
9909 // no match-rule, false predicate
9910 effect(DEF dst, USE src);
9911 predicate(false);
9912
9913 format %{ "FCTIDZ $dst, $src \t// convF2L, $src != NaN" %}
9914 size(4);
9915 ins_encode %{
9916 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
9917 __ fctidz($dst$$FloatRegister, $src$$FloatRegister);
9918 %}
9919 ins_pipe(pipe_class_default);
9920 %}
9921
9922 instruct cmovL_bso_stackSlotL(iRegLdst dst, flagsReg crx, stackSlotL src) %{
9923 // no match-rule, false predicate
9924 effect(DEF dst, USE crx, USE src);
9925 predicate(false);
9926
9927 ins_variable_size_depending_on_alignment(true);
9928
9929 format %{ "cmovL $crx, $dst, $src" %}
9930 // Worst case is branch + move + stop, no stop without scheduler.
9931 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
9932 ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
9933 ins_pipe(pipe_class_default);
9934 %}
9935
9936 instruct cmovL_bso_stackSlotL_conLvalue0_Ex(iRegLdst dst, flagsReg crx, stackSlotL mem) %{
9937 // no match-rule, false predicate
9938 effect(DEF dst, USE crx, USE mem);
9939 predicate(false);
9940
9941 format %{ "CmovL $dst, $crx, $mem \t// postalloc expanded" %}
9942 postalloc_expand %{
9943 //
9944 // replaces
9945 //
9946 // region dst crx mem
9947 // \ | | /
9948 // dst=cmovL_bso_stackSlotL_conLvalue0
9949 //
9950 // with
9951 //
9952 // region dst
9953 // \ /
9954 // dst=loadConL16(0)
9955 // |
9956 // ^ region dst crx mem
9957 // | \ | | /
9958 // dst=cmovL_bso_stackSlotL
9959 //
9960
9961 // Create new nodes.
9962 MachNode *m1 = new (C) loadConL16Node();
9963 MachNode *m2 = new (C) cmovL_bso_stackSlotLNode();
9964
9965 // inputs for new nodes
9966 m1->add_req(n_region);
9967 m2->add_req(n_region, n_crx, n_mem);
9968 m2->add_prec(m1);
9969
9970 // operands for new nodes
9971 m1->_opnds[0] = op_dst;
9972 m1->_opnds[1] = new (C) immL16Oper(0);
9973 m2->_opnds[0] = op_dst;
9974 m2->_opnds[1] = op_crx;
9975 m2->_opnds[2] = op_mem;
9976
9977 // registers for new nodes
9978 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9979 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9980
9981 // Insert new nodes.
9982 nodes->push(m1);
9983 nodes->push(m2);
9984 %}
9985 %}
9986
9987 // Float to Long conversion, NaN is mapped to 0.
9988 instruct convF2L_reg_ExEx(iRegLdst dst, regF src) %{
9989 match(Set dst (ConvF2L src));
9990 ins_cost(DEFAULT_COST);
9991
9992 expand %{
9993 regF tmpF;
9994 stackSlotL tmpS;
9995 flagsReg crx;
9996 cmpFUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
9997 convF2LRaw_regF(tmpF, src); // Convert float to long (speculated).
9998 moveF2L_reg_stack(tmpS, tmpF); // Store float to stack (speculated).
9999 cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
10000 %}
10001 %}
10002
10003 instruct convD2LRaw_regD(regD dst, regD src) %{
10004 // no match-rule, false predicate
10005 effect(DEF dst, USE src);
10006 predicate(false);
10007
10008 format %{ "FCTIDZ $dst, $src \t// convD2L $src != NaN" %}
10009 size(4);
10010 ins_encode %{
10011 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
10012 __ fctidz($dst$$FloatRegister, $src$$FloatRegister);
10013 %}
10014 ins_pipe(pipe_class_default);
10015 %}
10016
10017 // Double to Long conversion, NaN is mapped to 0.
10018 instruct convD2L_reg_ExEx(iRegLdst dst, regD src) %{
10019 match(Set dst (ConvD2L src));
10020 ins_cost(DEFAULT_COST);
10021
10022 expand %{
10023 regD tmpD;
10024 stackSlotL tmpS;
10025 flagsReg crx;
10026 cmpDUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
10027 convD2LRaw_regD(tmpD, src); // Convert float to long (speculated).
10028 moveD2L_reg_stack(tmpS, tmpD); // Store float to stack (speculated).
10029 cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
10030 %}
10031 %}
10032
10033 // Convert to Float
10034
10035 // Placed here as needed in expand.
10036 instruct convL2DRaw_regD(regD dst, regD src) %{
10037 // no match-rule, false predicate
10038 effect(DEF dst, USE src);
10039 predicate(false);
10040
10041 format %{ "FCFID $dst, $src \t// convL2D" %}
10042 size(4);
10043 ins_encode %{
10044 // TODO: PPC port $archOpcode(ppc64Opcode_fcfid);
10045 __ fcfid($dst$$FloatRegister, $src$$FloatRegister);
10046 %}
10047 ins_pipe(pipe_class_default);
10048 %}
10049
10050 // Placed here as needed in expand.
10051 instruct convD2F_reg(regF dst, regD src) %{
10052 match(Set dst (ConvD2F src));
10053 format %{ "FRSP $dst, $src \t// convD2F" %}
10054 size(4);
10055 ins_encode %{
10056 // TODO: PPC port $archOpcode(ppc64Opcode_frsp);
10057 __ frsp($dst$$FloatRegister, $src$$FloatRegister);
10058 %}
10059 ins_pipe(pipe_class_default);
10060 %}
10061
10062 // Integer to Float conversion.
10063 instruct convI2F_ireg_Ex(regF dst, iRegIsrc src) %{
10064 match(Set dst (ConvI2F src));
10065 predicate(!VM_Version::has_fcfids());
10066 ins_cost(DEFAULT_COST);
10067
10068 expand %{
10069 iRegLdst tmpL;
10070 stackSlotL tmpS;
10071 regD tmpD;
10072 regD tmpD2;
10073 convI2L_reg(tmpL, src); // Sign-extension int to long.
10074 regL_to_stkL(tmpS, tmpL); // Store long to stack.
10075 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10076 convL2DRaw_regD(tmpD2, tmpD); // Convert to double.
10077 convD2F_reg(dst, tmpD2); // Convert double to float.
10078 %}
10079 %}
10080
10081 instruct convL2FRaw_regF(regF dst, regD src) %{
10082 // no match-rule, false predicate
10083 effect(DEF dst, USE src);
10084 predicate(false);
10085
10086 format %{ "FCFIDS $dst, $src \t// convL2F" %}
10087 size(4);
10088 ins_encode %{
10089 // TODO: PPC port $archOpcode(ppc64Opcode_fcfid);
10090 __ fcfids($dst$$FloatRegister, $src$$FloatRegister);
10091 %}
10092 ins_pipe(pipe_class_default);
10093 %}
10094
10095 // Integer to Float conversion. Special version for Power7.
10096 instruct convI2F_ireg_fcfids_Ex(regF dst, iRegIsrc src) %{
10097 match(Set dst (ConvI2F src));
10098 predicate(VM_Version::has_fcfids());
10099 ins_cost(DEFAULT_COST);
10100
10101 expand %{
10102 iRegLdst tmpL;
10103 stackSlotL tmpS;
10104 regD tmpD;
10105 convI2L_reg(tmpL, src); // Sign-extension int to long.
10106 regL_to_stkL(tmpS, tmpL); // Store long to stack.
10107 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10108 convL2FRaw_regF(dst, tmpD); // Convert to float.
10109 %}
10110 %}
10111
10112 // L2F to avoid runtime call.
10113 instruct convL2F_ireg_fcfids_Ex(regF dst, iRegLsrc src) %{
10114 match(Set dst (ConvL2F src));
10115 predicate(VM_Version::has_fcfids());
10116 ins_cost(DEFAULT_COST);
10117
10118 expand %{
10119 stackSlotL tmpS;
10120 regD tmpD;
10121 regL_to_stkL(tmpS, src); // Store long to stack.
10122 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10123 convL2FRaw_regF(dst, tmpD); // Convert to float.
10124 %}
10125 %}
10126
10127 // Moved up as used in expand.
10128 //instruct convD2F_reg(regF dst, regD src) %{%}
10129
10130 // Convert to Double
10131
10132 // Integer to Double conversion.
10133 instruct convI2D_reg_Ex(regD dst, iRegIsrc src) %{
10134 match(Set dst (ConvI2D src));
10135 ins_cost(DEFAULT_COST);
10136
10137 expand %{
10138 iRegLdst tmpL;
10139 stackSlotL tmpS;
10140 regD tmpD;
10141 convI2L_reg(tmpL, src); // Sign-extension int to long.
10142 regL_to_stkL(tmpS, tmpL); // Store long to stack.
10143 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10144 convL2DRaw_regD(dst, tmpD); // Convert to double.
10145 %}
10146 %}
10147
10148 // Long to Double conversion
10149 instruct convL2D_reg_Ex(regD dst, stackSlotL src) %{
10150 match(Set dst (ConvL2D src));
10151 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
10152
10153 expand %{
10154 regD tmpD;
10155 moveL2D_stack_reg(tmpD, src);
10156 convL2DRaw_regD(dst, tmpD);
10157 %}
10158 %}
10159
10160 instruct convF2D_reg(regD dst, regF src) %{
10161 match(Set dst (ConvF2D src));
10162 format %{ "FMR $dst, $src \t// float->double" %}
10163 // variable size, 0 or 4
10164 ins_encode %{
10165 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
10166 __ fmr_if_needed($dst$$FloatRegister, $src$$FloatRegister);
10167 %}
10168 ins_pipe(pipe_class_default);
10169 %}
10170
10171 //----------Control Flow Instructions------------------------------------------
10172 // Compare Instructions
10173
10174 // Compare Integers
10175 instruct cmpI_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{
10176 match(Set crx (CmpI src1 src2));
10177 size(4);
10178 format %{ "CMPW $crx, $src1, $src2" %}
10179 ins_encode %{
10180 // TODO: PPC port $archOpcode(ppc64Opcode_cmp);
10181 __ cmpw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10182 %}
10183 ins_pipe(pipe_class_compare);
10184 %}
10185
10186 instruct cmpI_reg_imm16(flagsReg crx, iRegIsrc src1, immI16 src2) %{
10187 match(Set crx (CmpI src1 src2));
10188 format %{ "CMPWI $crx, $src1, $src2" %}
10189 size(4);
10190 ins_encode %{
10191 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10192 __ cmpwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10193 %}
10194 ins_pipe(pipe_class_compare);
10195 %}
10196
10197 // (src1 & src2) == 0?
10198 instruct testI_reg_imm(flagsRegCR0 cr0, iRegIsrc src1, uimmI16 src2, immI_0 zero) %{
10199 match(Set cr0 (CmpI (AndI src1 src2) zero));
10200 // r0 is killed
10201 format %{ "ANDI R0, $src1, $src2 \t// BTST int" %}
10202 size(4);
10203 ins_encode %{
10204 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
10205 // FIXME: avoid andi_ ?
10206 __ andi_(R0, $src1$$Register, $src2$$constant);
10207 %}
10208 ins_pipe(pipe_class_compare);
10209 %}
10210
10211 instruct cmpL_reg_reg(flagsReg crx, iRegLsrc src1, iRegLsrc src2) %{
10212 match(Set crx (CmpL src1 src2));
10213 format %{ "CMPD $crx, $src1, $src2" %}
10214 size(4);
10215 ins_encode %{
10216 // TODO: PPC port $archOpcode(ppc64Opcode_cmp);
10217 __ cmpd($crx$$CondRegister, $src1$$Register, $src2$$Register);
10218 %}
10219 ins_pipe(pipe_class_compare);
10220 %}
10221
10222 instruct cmpL_reg_imm16(flagsReg crx, iRegLsrc src1, immL16 src2) %{
10223 match(Set crx (CmpL src1 src2));
10224 format %{ "CMPDI $crx, $src1, $src2" %}
10225 size(4);
10226 ins_encode %{
10227 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10228 __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10229 %}
10230 ins_pipe(pipe_class_compare);
10231 %}
10232
10233 instruct testL_reg_reg(flagsRegCR0 cr0, iRegLsrc src1, iRegLsrc src2, immL_0 zero) %{
10234 match(Set cr0 (CmpL (AndL src1 src2) zero));
10235 // r0 is killed
10236 format %{ "AND R0, $src1, $src2 \t// BTST long" %}
10237 size(4);
10238 ins_encode %{
10239 // TODO: PPC port $archOpcode(ppc64Opcode_and_);
10240 __ and_(R0, $src1$$Register, $src2$$Register);
10241 %}
10242 ins_pipe(pipe_class_compare);
10243 %}
10244
10245 instruct testL_reg_imm(flagsRegCR0 cr0, iRegLsrc src1, uimmL16 src2, immL_0 zero) %{
10246 match(Set cr0 (CmpL (AndL src1 src2) zero));
10247 // r0 is killed
10248 format %{ "ANDI R0, $src1, $src2 \t// BTST long" %}
10249 size(4);
10250 ins_encode %{
10251 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
10252 // FIXME: avoid andi_ ?
10253 __ andi_(R0, $src1$$Register, $src2$$constant);
10254 %}
10255 ins_pipe(pipe_class_compare);
10256 %}
10257
10258 instruct cmovI_conIvalueMinus1_conIvalue1(iRegIdst dst, flagsReg crx) %{
10259 // no match-rule, false predicate
10260 effect(DEF dst, USE crx);
10261 predicate(false);
10262
10263 ins_variable_size_depending_on_alignment(true);
10264
10265 format %{ "cmovI $crx, $dst, -1, 0, +1" %}
10266 // Worst case is branch + move + branch + move + stop, no stop without scheduler.
10267 size(false /* TODO: PPC PORTInsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 20 : 16);
10268 ins_encode %{
10269 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
10270 Label done;
10271 // li(Rdst, 0); // equal -> 0
10272 __ beq($crx$$CondRegister, done);
10273 __ li($dst$$Register, 1); // greater -> +1
10274 __ bgt($crx$$CondRegister, done);
10275 __ li($dst$$Register, -1); // unordered or less -> -1
10276 // TODO: PPC port__ endgroup_if_needed(_size == 20);
10277 __ bind(done);
10278 %}
10279 ins_pipe(pipe_class_compare);
10280 %}
10281
10282 instruct cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(iRegIdst dst, flagsReg crx) %{
10283 // no match-rule, false predicate
10284 effect(DEF dst, USE crx);
10285 predicate(false);
10286
10287 format %{ "CmovI $crx, $dst, -1, 0, +1 \t// postalloc expanded" %}
10288 postalloc_expand %{
10289 //
10290 // replaces
10291 //
10292 // region crx
10293 // \ |
10294 // dst=cmovI_conIvalueMinus1_conIvalue0_conIvalue1
10295 //
10296 // with
10297 //
10298 // region
10299 // \
10300 // dst=loadConI16(0)
10301 // |
10302 // ^ region crx
10303 // | \ |
10304 // dst=cmovI_conIvalueMinus1_conIvalue1
10305 //
10306
10307 // Create new nodes.
10308 MachNode *m1 = new (C) loadConI16Node();
10309 MachNode *m2 = new (C) cmovI_conIvalueMinus1_conIvalue1Node();
10310
10311 // inputs for new nodes
10312 m1->add_req(n_region);
10313 m2->add_req(n_region, n_crx);
10314 m2->add_prec(m1);
10315
10316 // operands for new nodes
10317 m1->_opnds[0] = op_dst;
10318 m1->_opnds[1] = new (C) immI16Oper(0);
10319 m2->_opnds[0] = op_dst;
10320 m2->_opnds[1] = op_crx;
10321
10322 // registers for new nodes
10323 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10324 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10325
10326 // Insert new nodes.
10327 nodes->push(m1);
10328 nodes->push(m2);
10329 %}
10330 %}
10331
10332 // Manifest a CmpL3 result in an integer register. Very painful.
10333 // This is the test to avoid.
10334 // (src1 < src2) ? -1 : ((src1 > src2) ? 1 : 0)
10335 instruct cmpL3_reg_reg_ExEx(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
10336 match(Set dst (CmpL3 src1 src2));
10337 ins_cost(DEFAULT_COST*5+BRANCH_COST);
10338
10339 expand %{
10340 flagsReg tmp1;
10341 cmpL_reg_reg(tmp1, src1, src2);
10342 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10343 %}
10344 %}
10345
10346 // Implicit range checks.
10347 // A range check in the ideal world has one of the following shapes:
10348 // - (If le (CmpU length index)), (IfTrue throw exception)
10349 // - (If lt (CmpU index length)), (IfFalse throw exception)
10350 //
10351 // Match range check 'If le (CmpU length index)'.
10352 instruct rangeCheck_iReg_uimm15(cmpOp cmp, iRegIsrc src_length, uimmI15 index, label labl) %{
10353 match(If cmp (CmpU src_length index));
10354 effect(USE labl);
10355 predicate(TrapBasedRangeChecks &&
10356 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le &&
10357 PROB_UNLIKELY(_leaf->as_If()->_prob) >= PROB_ALWAYS &&
10358 (Matcher::branches_to_uncommon_trap(_leaf)));
10359
10360 ins_is_TrapBasedCheckNode(true);
10361
10362 format %{ "TWI $index $cmp $src_length \t// RangeCheck => trap $labl" %}
10363 size(4);
10364 ins_encode %{
10365 // TODO: PPC port $archOpcode(ppc64Opcode_twi);
10366 if ($cmp$$cmpcode == 0x1 /* less_equal */) {
10367 __ trap_range_check_le($src_length$$Register, $index$$constant);
10368 } else {
10369 // Both successors are uncommon traps, probability is 0.
10370 // Node got flipped during fixup flow.
10371 assert($cmp$$cmpcode == 0x9, "must be greater");
10372 __ trap_range_check_g($src_length$$Register, $index$$constant);
10373 }
10374 %}
10375 ins_pipe(pipe_class_trap);
10376 %}
10377
10378 // Match range check 'If lt (CmpU index length)'.
10379 instruct rangeCheck_iReg_iReg(cmpOp cmp, iRegIsrc src_index, iRegIsrc src_length, label labl) %{
10380 match(If cmp (CmpU src_index src_length));
10381 effect(USE labl);
10382 predicate(TrapBasedRangeChecks &&
10383 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
10384 _leaf->as_If()->_prob >= PROB_ALWAYS &&
10385 (Matcher::branches_to_uncommon_trap(_leaf)));
10386
10387 ins_is_TrapBasedCheckNode(true);
10388
10389 format %{ "TW $src_index $cmp $src_length \t// RangeCheck => trap $labl" %}
10390 size(4);
10391 ins_encode %{
10392 // TODO: PPC port $archOpcode(ppc64Opcode_tw);
10393 if ($cmp$$cmpcode == 0x0 /* greater_equal */) {
10394 __ trap_range_check_ge($src_index$$Register, $src_length$$Register);
10395 } else {
10396 // Both successors are uncommon traps, probability is 0.
10397 // Node got flipped during fixup flow.
10398 assert($cmp$$cmpcode == 0x8, "must be less");
10399 __ trap_range_check_l($src_index$$Register, $src_length$$Register);
10400 }
10401 %}
10402 ins_pipe(pipe_class_trap);
10403 %}
10404
10405 // Match range check 'If lt (CmpU index length)'.
10406 instruct rangeCheck_uimm15_iReg(cmpOp cmp, iRegIsrc src_index, uimmI15 length, label labl) %{
10407 match(If cmp (CmpU src_index length));
10408 effect(USE labl);
10409 predicate(TrapBasedRangeChecks &&
10410 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
10411 _leaf->as_If()->_prob >= PROB_ALWAYS &&
10412 (Matcher::branches_to_uncommon_trap(_leaf)));
10413
10414 ins_is_TrapBasedCheckNode(true);
10415
10416 format %{ "TWI $src_index $cmp $length \t// RangeCheck => trap $labl" %}
10417 size(4);
10418 ins_encode %{
10419 // TODO: PPC port $archOpcode(ppc64Opcode_twi);
10420 if ($cmp$$cmpcode == 0x0 /* greater_equal */) {
10421 __ trap_range_check_ge($src_index$$Register, $length$$constant);
10422 } else {
10423 // Both successors are uncommon traps, probability is 0.
10424 // Node got flipped during fixup flow.
10425 assert($cmp$$cmpcode == 0x8, "must be less");
10426 __ trap_range_check_l($src_index$$Register, $length$$constant);
10427 }
10428 %}
10429 ins_pipe(pipe_class_trap);
10430 %}
10431
10432 instruct compU_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{
10433 match(Set crx (CmpU src1 src2));
10434 format %{ "CMPLW $crx, $src1, $src2 \t// unsigned" %}
10435 size(4);
10436 ins_encode %{
10437 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10438 __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10439 %}
10440 ins_pipe(pipe_class_compare);
10441 %}
10442
10443 instruct compU_reg_uimm16(flagsReg crx, iRegIsrc src1, uimmI16 src2) %{
10444 match(Set crx (CmpU src1 src2));
10445 size(4);
10446 format %{ "CMPLWI $crx, $src1, $src2" %}
10447 ins_encode %{
10448 // TODO: PPC port $archOpcode(ppc64Opcode_cmpli);
10449 __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10450 %}
10451 ins_pipe(pipe_class_compare);
10452 %}
10453
10454 // Implicit zero checks (more implicit null checks).
10455 // No constant pool entries required.
10456 instruct zeroCheckN_iReg_imm0(cmpOp cmp, iRegNsrc value, immN_0 zero, label labl) %{
10457 match(If cmp (CmpN value zero));
10458 effect(USE labl);
10459 predicate(TrapBasedNullChecks &&
10460 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
10461 _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) &&
10462 Matcher::branches_to_uncommon_trap(_leaf));
10463 ins_cost(1);
10464
10465 ins_is_TrapBasedCheckNode(true);
10466
10467 format %{ "TDI $value $cmp $zero \t// ZeroCheckN => trap $labl" %}
10468 size(4);
10469 ins_encode %{
10470 // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
10471 if ($cmp$$cmpcode == 0xA) {
10472 __ trap_null_check($value$$Register);
10473 } else {
10474 // Both successors are uncommon traps, probability is 0.
10475 // Node got flipped during fixup flow.
10476 assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)");
10477 __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned);
10478 }
10479 %}
10480 ins_pipe(pipe_class_trap);
10481 %}
10482
10483 // Compare narrow oops.
10484 instruct cmpN_reg_reg(flagsReg crx, iRegNsrc src1, iRegNsrc src2) %{
10485 match(Set crx (CmpN src1 src2));
10486
10487 size(4);
10488 ins_cost(DEFAULT_COST);
10489 format %{ "CMPLW $crx, $src1, $src2 \t// compressed ptr" %}
10490 ins_encode %{
10491 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10492 __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10493 %}
10494 ins_pipe(pipe_class_compare);
10495 %}
10496
10497 instruct cmpN_reg_imm0(flagsReg crx, iRegNsrc src1, immN_0 src2) %{
10498 match(Set crx (CmpN src1 src2));
10499 // Make this more expensive than zeroCheckN_iReg_imm0.
10500 ins_cost(DEFAULT_COST);
10501
10502 format %{ "CMPLWI $crx, $src1, $src2 \t// compressed ptr" %}
10503 size(4);
10504 ins_encode %{
10505 // TODO: PPC port $archOpcode(ppc64Opcode_cmpli);
10506 __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10507 %}
10508 ins_pipe(pipe_class_compare);
10509 %}
10510
10511 // Implicit zero checks (more implicit null checks).
10512 // No constant pool entries required.
10513 instruct zeroCheckP_reg_imm0(cmpOp cmp, iRegP_N2P value, immP_0 zero, label labl) %{
10514 match(If cmp (CmpP value zero));
10515 effect(USE labl);
10516 predicate(TrapBasedNullChecks &&
10517 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
10518 _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) &&
10519 Matcher::branches_to_uncommon_trap(_leaf));
10520
10521 ins_is_TrapBasedCheckNode(true);
10522
10523 format %{ "TDI $value $cmp $zero \t// ZeroCheckP => trap $labl" %}
10524 size(4);
10525 ins_encode %{
10526 // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
10527 if ($cmp$$cmpcode == 0xA) {
10528 __ trap_null_check($value$$Register);
10529 } else {
10530 // Both successors are uncommon traps, probability is 0.
10531 // Node got flipped during fixup flow.
10532 assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)");
10533 __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned);
10534 }
10535 %}
10536 ins_pipe(pipe_class_trap);
10537 %}
10538
10539 // Compare Pointers
10540 instruct cmpP_reg_reg(flagsReg crx, iRegP_N2P src1, iRegP_N2P src2) %{
10541 match(Set crx (CmpP src1 src2));
10542 format %{ "CMPLD $crx, $src1, $src2 \t// ptr" %}
10543 size(4);
10544 ins_encode %{
10545 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10546 __ cmpld($crx$$CondRegister, $src1$$Register, $src2$$Register);
10547 %}
10548 ins_pipe(pipe_class_compare);
10549 %}
10550
10551 // Used in postalloc expand.
10552 instruct cmpP_reg_imm16(flagsReg crx, iRegPsrc src1, immL16 src2) %{
10553 // This match rule prevents reordering of node before a safepoint.
10554 // This only makes sense if this instructions is used exclusively
10555 // for the expansion of EncodeP!
10556 match(Set crx (CmpP src1 src2));
10557 predicate(false);
10558
10559 format %{ "CMPDI $crx, $src1, $src2" %}
10560 size(4);
10561 ins_encode %{
10562 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10563 __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10564 %}
10565 ins_pipe(pipe_class_compare);
10566 %}
10567
10568 //----------Float Compares----------------------------------------------------
10569
10570 instruct cmpFUnordered_reg_reg(flagsReg crx, regF src1, regF src2) %{
10571 // no match-rule, false predicate
10572 effect(DEF crx, USE src1, USE src2);
10573 predicate(false);
10574
10575 format %{ "cmpFUrd $crx, $src1, $src2" %}
10576 size(4);
10577 ins_encode %{
10578 // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu);
10579 __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister);
10580 %}
10581 ins_pipe(pipe_class_default);
10582 %}
10583
10584 instruct cmov_bns_less(flagsReg crx) %{
10585 // no match-rule, false predicate
10586 effect(DEF crx);
10587 predicate(false);
10588
10589 ins_variable_size_depending_on_alignment(true);
10590
10591 format %{ "cmov $crx" %}
10592 // Worst case is branch + move + stop, no stop without scheduler.
10593 size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 16 : 12);
10594 ins_encode %{
10595 // TODO: PPC port $archOpcode(ppc64Opcode_cmovecr);
10596 Label done;
10597 __ bns($crx$$CondRegister, done); // not unordered -> keep crx
10598 __ li(R0, 0);
10599 __ cmpwi($crx$$CondRegister, R0, 1); // unordered -> set crx to 'less'
10600 // TODO PPC port __ endgroup_if_needed(_size == 16);
10601 __ bind(done);
10602 %}
10603 ins_pipe(pipe_class_default);
10604 %}
10605
10606 // Compare floating, generate condition code.
10607 instruct cmpF_reg_reg_Ex(flagsReg crx, regF src1, regF src2) %{
10608 // FIXME: should we match 'If cmp (CmpF src1 src2))' ??
10609 //
10610 // The following code sequence occurs a lot in mpegaudio:
10611 //
10612 // block BXX:
10613 // 0: instruct cmpFUnordered_reg_reg (cmpF_reg_reg-0):
10614 // cmpFUrd CCR6, F11, F9
10615 // 4: instruct cmov_bns_less (cmpF_reg_reg-1):
10616 // cmov CCR6
10617 // 8: instruct branchConSched:
10618 // B_FARle CCR6, B56 P=0.500000 C=-1.000000
10619 match(Set crx (CmpF src1 src2));
10620 ins_cost(DEFAULT_COST+BRANCH_COST);
10621
10622 format %{ "CmpF $crx, $src1, $src2 \t// postalloc expanded" %}
10623 postalloc_expand %{
10624 //
10625 // replaces
10626 //
10627 // region src1 src2
10628 // \ | |
10629 // crx=cmpF_reg_reg
10630 //
10631 // with
10632 //
10633 // region src1 src2
10634 // \ | |
10635 // crx=cmpFUnordered_reg_reg
10636 // |
10637 // ^ region
10638 // | \
10639 // crx=cmov_bns_less
10640 //
10641
10642 // Create new nodes.
10643 MachNode *m1 = new (C) cmpFUnordered_reg_regNode();
10644 MachNode *m2 = new (C) cmov_bns_lessNode();
10645
10646 // inputs for new nodes
10647 m1->add_req(n_region, n_src1, n_src2);
10648 m2->add_req(n_region);
10649 m2->add_prec(m1);
10650
10651 // operands for new nodes
10652 m1->_opnds[0] = op_crx;
10653 m1->_opnds[1] = op_src1;
10654 m1->_opnds[2] = op_src2;
10655 m2->_opnds[0] = op_crx;
10656
10657 // registers for new nodes
10658 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10659 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10660
10661 // Insert new nodes.
10662 nodes->push(m1);
10663 nodes->push(m2);
10664 %}
10665 %}
10666
10667 // Compare float, generate -1,0,1
10668 instruct cmpF3_reg_reg_ExEx(iRegIdst dst, regF src1, regF src2) %{
10669 match(Set dst (CmpF3 src1 src2));
10670 ins_cost(DEFAULT_COST*5+BRANCH_COST);
10671
10672 expand %{
10673 flagsReg tmp1;
10674 cmpFUnordered_reg_reg(tmp1, src1, src2);
10675 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10676 %}
10677 %}
10678
10679 instruct cmpDUnordered_reg_reg(flagsReg crx, regD src1, regD src2) %{
10680 // no match-rule, false predicate
10681 effect(DEF crx, USE src1, USE src2);
10682 predicate(false);
10683
10684 format %{ "cmpFUrd $crx, $src1, $src2" %}
10685 size(4);
10686 ins_encode %{
10687 // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu);
10688 __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister);
10689 %}
10690 ins_pipe(pipe_class_default);
10691 %}
10692
10693 instruct cmpD_reg_reg_Ex(flagsReg crx, regD src1, regD src2) %{
10694 match(Set crx (CmpD src1 src2));
10695 ins_cost(DEFAULT_COST+BRANCH_COST);
10696
10697 format %{ "CmpD $crx, $src1, $src2 \t// postalloc expanded" %}
10698 postalloc_expand %{
10699 //
10700 // replaces
10701 //
10702 // region src1 src2
10703 // \ | |
10704 // crx=cmpD_reg_reg
10705 //
10706 // with
10707 //
10708 // region src1 src2
10709 // \ | |
10710 // crx=cmpDUnordered_reg_reg
10711 // |
10712 // ^ region
10713 // | \
10714 // crx=cmov_bns_less
10715 //
10716
10717 // create new nodes
10718 MachNode *m1 = new (C) cmpDUnordered_reg_regNode();
10719 MachNode *m2 = new (C) cmov_bns_lessNode();
10720
10721 // inputs for new nodes
10722 m1->add_req(n_region, n_src1, n_src2);
10723 m2->add_req(n_region);
10724 m2->add_prec(m1);
10725
10726 // operands for new nodes
10727 m1->_opnds[0] = op_crx;
10728 m1->_opnds[1] = op_src1;
10729 m1->_opnds[2] = op_src2;
10730 m2->_opnds[0] = op_crx;
10731
10732 // registers for new nodes
10733 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10734 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10735
10736 // Insert new nodes.
10737 nodes->push(m1);
10738 nodes->push(m2);
10739 %}
10740 %}
10741
10742 // Compare double, generate -1,0,1
10743 instruct cmpD3_reg_reg_ExEx(iRegIdst dst, regD src1, regD src2) %{
10744 match(Set dst (CmpD3 src1 src2));
10745 ins_cost(DEFAULT_COST*5+BRANCH_COST);
10746
10747 expand %{
10748 flagsReg tmp1;
10749 cmpDUnordered_reg_reg(tmp1, src1, src2);
10750 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10751 %}
10752 %}
10753
10754 //----------Branches---------------------------------------------------------
10755 // Jump
10756
10757 // Direct Branch.
10758 instruct branch(label labl) %{
10759 match(Goto);
10760 effect(USE labl);
10761 ins_cost(BRANCH_COST);
10762
10763 format %{ "B $labl" %}
10764 size(4);
10765 ins_encode %{
10766 // TODO: PPC port $archOpcode(ppc64Opcode_b);
10767 Label d; // dummy
10768 __ bind(d);
10769 Label* p = $labl$$label;
10770 // `p' is `NULL' when this encoding class is used only to
10771 // determine the size of the encoded instruction.
10772 Label& l = (NULL == p)? d : *(p);
10773 __ b(l);
10774 %}
10775 ins_pipe(pipe_class_default);
10776 %}
10777
10778 // Conditional Near Branch
10779 instruct branchCon(cmpOp cmp, flagsReg crx, label lbl) %{
10780 // Same match rule as `branchConFar'.
10781 match(If cmp crx);
10782 effect(USE lbl);
10783 ins_cost(BRANCH_COST);
10784
10785 // If set to 1 this indicates that the current instruction is a
10786 // short variant of a long branch. This avoids using this
10787 // instruction in first-pass matching. It will then only be used in
10788 // the `Shorten_branches' pass.
10789 ins_short_branch(1);
10790
10791 format %{ "B$cmp $crx, $lbl" %}
10792 size(4);
10793 ins_encode( enc_bc(crx, cmp, lbl) );
10794 ins_pipe(pipe_class_default);
10795 %}
10796
10797 // This is for cases when the ppc64 `bc' instruction does not
10798 // reach far enough. So we emit a far branch here, which is more
10799 // expensive.
10800 //
10801 // Conditional Far Branch
10802 instruct branchConFar(cmpOp cmp, flagsReg crx, label lbl) %{
10803 // Same match rule as `branchCon'.
10804 match(If cmp crx);
10805 effect(USE crx, USE lbl);
10806 predicate(!false /* TODO: PPC port HB_Schedule*/);
10807 // Higher cost than `branchCon'.
10808 ins_cost(5*BRANCH_COST);
10809
10810 // This is not a short variant of a branch, but the long variant.
10811 ins_short_branch(0);
10812
10813 format %{ "B_FAR$cmp $crx, $lbl" %}
10814 size(8);
10815 ins_encode( enc_bc_far(crx, cmp, lbl) );
10816 ins_pipe(pipe_class_default);
10817 %}
10818
10819 // Conditional Branch used with Power6 scheduler (can be far or short).
10820 instruct branchConSched(cmpOp cmp, flagsReg crx, label lbl) %{
10821 // Same match rule as `branchCon'.
10822 match(If cmp crx);
10823 effect(USE crx, USE lbl);
10824 predicate(false /* TODO: PPC port HB_Schedule*/);
10825 // Higher cost than `branchCon'.
10826 ins_cost(5*BRANCH_COST);
10827
10828 // Actually size doesn't depend on alignment but on shortening.
10829 ins_variable_size_depending_on_alignment(true);
10830 // long variant.
10831 ins_short_branch(0);
10832
10833 format %{ "B_FAR$cmp $crx, $lbl" %}
10834 size(8); // worst case
10835 ins_encode( enc_bc_short_far(crx, cmp, lbl) );
10836 ins_pipe(pipe_class_default);
10837 %}
10838
10839 instruct branchLoopEnd(cmpOp cmp, flagsReg crx, label labl) %{
10840 match(CountedLoopEnd cmp crx);
10841 effect(USE labl);
10842 ins_cost(BRANCH_COST);
10843
10844 // short variant.
10845 ins_short_branch(1);
10846
10847 format %{ "B$cmp $crx, $labl \t// counted loop end" %}
10848 size(4);
10849 ins_encode( enc_bc(crx, cmp, labl) );
10850 ins_pipe(pipe_class_default);
10851 %}
10852
10853 instruct branchLoopEndFar(cmpOp cmp, flagsReg crx, label labl) %{
10854 match(CountedLoopEnd cmp crx);
10855 effect(USE labl);
10856 predicate(!false /* TODO: PPC port HB_Schedule */);
10857 ins_cost(BRANCH_COST);
10858
10859 // Long variant.
10860 ins_short_branch(0);
10861
10862 format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %}
10863 size(8);
10864 ins_encode( enc_bc_far(crx, cmp, labl) );
10865 ins_pipe(pipe_class_default);
10866 %}
10867
10868 // Conditional Branch used with Power6 scheduler (can be far or short).
10869 instruct branchLoopEndSched(cmpOp cmp, flagsReg crx, label labl) %{
10870 match(CountedLoopEnd cmp crx);
10871 effect(USE labl);
10872 predicate(false /* TODO: PPC port HB_Schedule */);
10873 // Higher cost than `branchCon'.
10874 ins_cost(5*BRANCH_COST);
10875
10876 // Actually size doesn't depend on alignment but on shortening.
10877 ins_variable_size_depending_on_alignment(true);
10878 // Long variant.
10879 ins_short_branch(0);
10880
10881 format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %}
10882 size(8); // worst case
10883 ins_encode( enc_bc_short_far(crx, cmp, labl) );
10884 ins_pipe(pipe_class_default);
10885 %}
10886
10887 // ============================================================================
10888 // Java runtime operations, intrinsics and other complex operations.
10889
10890 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
10891 // array for an instance of the superklass. Set a hidden internal cache on a
10892 // hit (cache is checked with exposed code in gen_subtype_check()). Return
10893 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
10894 //
10895 // GL TODO: Improve this.
10896 // - result should not be a TEMP
10897 // - Add match rule as on sparc avoiding additional Cmp.
10898 instruct partialSubtypeCheck(iRegPdst result, iRegP_N2P subklass, iRegP_N2P superklass,
10899 iRegPdst tmp_klass, iRegPdst tmp_arrayptr) %{
10900 match(Set result (PartialSubtypeCheck subklass superklass));
10901 effect(TEMP result, TEMP tmp_klass, TEMP tmp_arrayptr);
10902 ins_cost(DEFAULT_COST*10);
10903
10904 format %{ "PartialSubtypeCheck $result = ($subklass instanceOf $superklass) tmp: $tmp_klass, $tmp_arrayptr" %}
10905 ins_encode %{
10906 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10907 __ check_klass_subtype_slow_path($subklass$$Register, $superklass$$Register, $tmp_arrayptr$$Register,
10908 $tmp_klass$$Register, NULL, $result$$Register);
10909 %}
10910 ins_pipe(pipe_class_default);
10911 %}
10912
10913 // inlined locking and unlocking
10914
10915 instruct cmpFastLock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
10916 match(Set crx (FastLock oop box));
10917 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
10918 // TODO PPC port predicate(!UseNewFastLockPPC64 || UseBiasedLocking);
10919
10920 format %{ "FASTLOCK $oop, $box, $tmp1, $tmp2, $tmp3" %}
10921 ins_encode %{
10922 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10923 __ compiler_fast_lock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
10924 $tmp3$$Register, $tmp1$$Register, $tmp2$$Register);
10925 // If locking was successfull, crx should indicate 'EQ'.
10926 // The compiler generates a branch to the runtime call to
10927 // _complete_monitor_locking_Java for the case where crx is 'NE'.
10928 %}
10929 ins_pipe(pipe_class_compare);
10930 %}
10931
10932 instruct cmpFastUnlock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
10933 match(Set crx (FastUnlock oop box));
10934 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
10935
10936 format %{ "FASTUNLOCK $oop, $box, $tmp1, $tmp2" %}
10937 ins_encode %{
10938 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10939 __ compiler_fast_unlock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
10940 $tmp3$$Register, $tmp1$$Register, $tmp2$$Register);
10941 // If unlocking was successfull, crx should indicate 'EQ'.
10942 // The compiler generates a branch to the runtime call to
10943 // _complete_monitor_unlocking_Java for the case where crx is 'NE'.
10944 %}
10945 ins_pipe(pipe_class_compare);
10946 %}
10947
10948 // Align address.
10949 instruct align_addr(iRegPdst dst, iRegPsrc src, immLnegpow2 mask) %{
10950 match(Set dst (CastX2P (AndL (CastP2X src) mask)));
10951
10952 format %{ "ANDDI $dst, $src, $mask \t// next aligned address" %}
10953 size(4);
10954 ins_encode %{
10955 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
10956 __ clrrdi($dst$$Register, $src$$Register, log2_long((jlong)-$mask$$constant));
10957 %}
10958 ins_pipe(pipe_class_default);
10959 %}
10960
10961 // Array size computation.
10962 instruct array_size(iRegLdst dst, iRegPsrc end, iRegPsrc start) %{
10963 match(Set dst (SubL (CastP2X end) (CastP2X start)));
10964
10965 format %{ "SUB $dst, $end, $start \t// array size in bytes" %}
10966 size(4);
10967 ins_encode %{
10968 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
10969 __ subf($dst$$Register, $start$$Register, $end$$Register);
10970 %}
10971 ins_pipe(pipe_class_default);
10972 %}
10973
10974 // Clear-array with dynamic array-size.
10975 instruct inlineCallClearArray(rarg1RegL cnt, rarg2RegP base, Universe dummy, regCTR ctr) %{
10976 match(Set dummy (ClearArray cnt base));
10977 effect(USE_KILL cnt, USE_KILL base, KILL ctr);
10978 ins_cost(MEMORY_REF_COST);
10979
10980 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
10981
10982 format %{ "ClearArray $cnt, $base" %}
10983 ins_encode %{
10984 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10985 __ clear_memory_doubleword($base$$Register, $cnt$$Register); // kills cnt, base, R0
10986 %}
10987 ins_pipe(pipe_class_default);
10988 %}
10989
10990 // String_IndexOf for needle of length 1.
10991 //
10992 // Match needle into immediate operands: no loadConP node needed. Saves one
10993 // register and two instructions over string_indexOf_imm1Node.
10994 //
10995 // Assumes register result differs from all input registers.
10996 //
10997 // Preserves registers haystack, haycnt
10998 // Kills registers tmp1, tmp2
10999 // Defines registers result
11000 //
11001 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11002 //
11003 // Unfortunately this does not match too often. In many situations the AddP is used
11004 // by several nodes, even several StrIndexOf nodes, breaking the match tree.
11005 instruct string_indexOf_imm1_char(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
11006 immP needleImm, immL offsetImm, immI_1 needlecntImm,
11007 iRegIdst tmp1, iRegIdst tmp2,
11008 flagsRegCR0 cr0, flagsRegCR1 cr1) %{
11009 predicate(SpecialStringIndexOf); // type check implicit by parameter type, See Matcher::match_rule_supported
11010 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary (AddP needleImm offsetImm) needlecntImm)));
11011
11012 effect(TEMP result, TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1);
11013
11014 ins_cost(150);
11015 format %{ "String IndexOf CSCL1 $haystack[0..$haycnt], $needleImm+$offsetImm[0..$needlecntImm]"
11016 "-> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %}
11017
11018 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted
11019 ins_encode %{
11020 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11021 immPOper *needleOper = (immPOper *)$needleImm;
11022 const TypeOopPtr *t = needleOper->type()->isa_oopptr();
11023 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char *
11024
11025 __ string_indexof_1($result$$Register,
11026 $haystack$$Register, $haycnt$$Register,
11027 R0, needle_values->char_at(0),
11028 $tmp1$$Register, $tmp2$$Register);
11029 %}
11030 ins_pipe(pipe_class_compare);
11031 %}
11032
11033 // String_IndexOf for needle of length 1.
11034 //
11035 // Special case requires less registers and emits less instructions.
11036 //
11037 // Assumes register result differs from all input registers.
11038 //
11039 // Preserves registers haystack, haycnt
11040 // Kills registers tmp1, tmp2, needle
11041 // Defines registers result
11042 //
11043 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11044 instruct string_indexOf_imm1(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
11045 rscratch2RegP needle, immI_1 needlecntImm,
11046 iRegIdst tmp1, iRegIdst tmp2,
11047 flagsRegCR0 cr0, flagsRegCR1 cr1) %{
11048 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
11049 effect(USE_KILL needle, /* TDEF needle, */ TEMP result,
11050 TEMP tmp1, TEMP tmp2);
11051 // Required for EA: check if it is still a type_array.
11052 predicate(SpecialStringIndexOf && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
11053 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
11054 ins_cost(180);
11055
11056 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11057
11058 format %{ "String IndexOf SCL1 $haystack[0..$haycnt], $needle[0..$needlecntImm]"
11059 " -> $result \t// KILL $haycnt, $needle, $tmp1, $tmp2, $cr0, $cr1" %}
11060 ins_encode %{
11061 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11062 Node *ndl = in(operand_index($needle)); // The node that defines needle.
11063 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
11064 guarantee(needle_values, "sanity");
11065 if (needle_values != NULL) {
11066 __ string_indexof_1($result$$Register,
11067 $haystack$$Register, $haycnt$$Register,
11068 R0, needle_values->char_at(0),
11069 $tmp1$$Register, $tmp2$$Register);
11070 } else {
11071 __ string_indexof_1($result$$Register,
11072 $haystack$$Register, $haycnt$$Register,
11073 $needle$$Register, 0,
11074 $tmp1$$Register, $tmp2$$Register);
11075 }
11076 %}
11077 ins_pipe(pipe_class_compare);
11078 %}
11079
11080 // String_IndexOf.
11081 //
11082 // Length of needle as immediate. This saves instruction loading constant needle
11083 // length.
11084 // @@@ TODO Specify rules for length < 8 or so, and roll out comparison of needle
11085 // completely or do it in vector instruction. This should save registers for
11086 // needlecnt and needle.
11087 //
11088 // Assumes register result differs from all input registers.
11089 // Overwrites haycnt, needlecnt.
11090 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11091 instruct string_indexOf_imm(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt,
11092 iRegPsrc needle, uimmI15 needlecntImm,
11093 iRegIdst tmp1, iRegIdst tmp2, iRegIdst tmp3, iRegIdst tmp4, iRegIdst tmp5,
11094 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6) %{
11095 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
11096 effect(USE_KILL haycnt, /* better: TDEF haycnt, */ TEMP result,
11097 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, KILL cr0, KILL cr1, KILL cr6);
11098 // Required for EA: check if it is still a type_array.
11099 predicate(SpecialStringIndexOf && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
11100 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
11101 ins_cost(250);
11102
11103 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11104
11105 format %{ "String IndexOf SCL $haystack[0..$haycnt], $needle[0..$needlecntImm]"
11106 " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5, $cr0, $cr1" %}
11107 ins_encode %{
11108 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11109 Node *ndl = in(operand_index($needle)); // The node that defines needle.
11110 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
11111
11112 __ string_indexof($result$$Register,
11113 $haystack$$Register, $haycnt$$Register,
11114 $needle$$Register, needle_values, $tmp5$$Register, $needlecntImm$$constant,
11115 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
11116 %}
11117 ins_pipe(pipe_class_compare);
11118 %}
11119
11120 // StrIndexOf node.
11121 //
11122 // Assumes register result differs from all input registers.
11123 // Overwrites haycnt, needlecnt.
11124 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11125 instruct string_indexOf(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, iRegPsrc needle, rscratch2RegI needlecnt,
11126 iRegLdst tmp1, iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4,
11127 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6) %{
11128 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
11129 effect(USE_KILL haycnt, USE_KILL needlecnt, /*better: TDEF haycnt, TDEF needlecnt,*/
11130 TEMP result,
11131 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr0, KILL cr1, KILL cr6);
11132 predicate(SpecialStringIndexOf); // See Matcher::match_rule_supported.
11133 ins_cost(300);
11134
11135 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11136
11137 format %{ "String IndexOf $haystack[0..$haycnt], $needle[0..$needlecnt]"
11138 " -> $result \t// KILL $haycnt, $needlecnt, $tmp1, $tmp2, $tmp3, $tmp4, $cr0, $cr1" %}
11139 ins_encode %{
11140 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11141 __ string_indexof($result$$Register,
11142 $haystack$$Register, $haycnt$$Register,
11143 $needle$$Register, NULL, $needlecnt$$Register, 0, // needlecnt not constant.
11144 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
11145 %}
11146 ins_pipe(pipe_class_compare);
11147 %}
11148
11149 // String equals with immediate.
11150 instruct string_equals_imm(iRegPsrc str1, iRegPsrc str2, uimmI15 cntImm, iRegIdst result,
11151 iRegPdst tmp1, iRegPdst tmp2,
11152 flagsRegCR0 cr0, flagsRegCR6 cr6, regCTR ctr) %{
11153 match(Set result (StrEquals (Binary str1 str2) cntImm));
11154 effect(TEMP result, TEMP tmp1, TEMP tmp2,
11155 KILL cr0, KILL cr6, KILL ctr);
11156 predicate(SpecialStringEquals); // See Matcher::match_rule_supported.
11157 ins_cost(250);
11158
11159 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11160
11161 format %{ "String Equals SCL [0..$cntImm]($str1),[0..$cntImm]($str2)"
11162 " -> $result \t// KILL $cr0, $cr6, $ctr, TEMP $result, $tmp1, $tmp2" %}
11163 ins_encode %{
11164 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11165 __ char_arrays_equalsImm($str1$$Register, $str2$$Register, $cntImm$$constant,
11166 $result$$Register, $tmp1$$Register, $tmp2$$Register);
11167 %}
11168 ins_pipe(pipe_class_compare);
11169 %}
11170
11171 // String equals.
11172 // Use dst register classes if register gets killed, as it is the case for TEMP operands!
11173 instruct string_equals(iRegPsrc str1, iRegPsrc str2, iRegIsrc cnt, iRegIdst result,
11174 iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3, iRegPdst tmp4, iRegPdst tmp5,
11175 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
11176 match(Set result (StrEquals (Binary str1 str2) cnt));
11177 effect(TEMP result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5,
11178 KILL cr0, KILL cr1, KILL cr6, KILL ctr);
11179 predicate(SpecialStringEquals); // See Matcher::match_rule_supported.
11180 ins_cost(300);
11181
11182 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11183
11184 format %{ "String Equals [0..$cnt]($str1),[0..$cnt]($str2) -> $result"
11185 " \t// KILL $cr0, $cr1, $cr6, $ctr, TEMP $result, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5" %}
11186 ins_encode %{
11187 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11188 __ char_arrays_equals($str1$$Register, $str2$$Register, $cnt$$Register, $result$$Register,
11189 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, $tmp5$$Register);
11190 %}
11191 ins_pipe(pipe_class_compare);
11192 %}
11193
11194 // String compare.
11195 // Char[] pointers are passed in.
11196 // Use dst register classes if register gets killed, as it is the case for TEMP operands!
11197 instruct string_compare(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt1, rarg4RegI cnt2, iRegIdst result,
11198 iRegPdst tmp, flagsRegCR0 cr0, regCTR ctr) %{
11199 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11200 effect(USE_KILL cnt1, USE_KILL cnt2, USE_KILL str1, USE_KILL str2, TEMP result, TEMP tmp, KILL cr0, KILL ctr);
11201 ins_cost(300);
11202
11203 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11204
11205 format %{ "String Compare $str1[0..$cnt1], $str2[0..$cnt2] -> $result"
11206 " \t// TEMP $tmp, $result KILLs $str1, $cnt1, $str2, $cnt2, $cr0, $ctr" %}
11207 ins_encode %{
11208 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11209 __ string_compare($str1$$Register, $str2$$Register, $cnt1$$Register, $cnt2$$Register,
11210 $result$$Register, $tmp$$Register);
11211 %}
11212 ins_pipe(pipe_class_compare);
11213 %}
11214
11215 //---------- Min/Max Instructions ---------------------------------------------
11216
11217 instruct minI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
11218 match(Set dst (MinI src1 src2));
11219 ins_cost(DEFAULT_COST*6);
11220
11221 expand %{
11222 iRegLdst src1s;
11223 iRegLdst src2s;
11224 iRegLdst diff;
11225 iRegLdst sm;
11226 iRegLdst doz; // difference or zero
11227 convI2L_reg(src1s, src1); // Ensure proper sign extension.
11228 convI2L_reg(src2s, src2); // Ensure proper sign extension.
11229 subL_reg_reg(diff, src2s, src1s);
11230 // Need to consider >=33 bit result, therefore we need signmaskL.
11231 signmask64L_regL(sm, diff);
11232 andL_reg_reg(doz, diff, sm); // <=0
11233 addI_regL_regL(dst, doz, src1s);
11234 %}
11235 %}
11236
11237 instruct maxI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
11238 match(Set dst (MaxI src1 src2));
11239 ins_cost(DEFAULT_COST*6);
11240
11241 expand %{
11242 iRegLdst src1s;
11243 iRegLdst src2s;
11244 iRegLdst diff;
11245 iRegLdst sm;
11246 iRegLdst doz; // difference or zero
11247 convI2L_reg(src1s, src1); // Ensure proper sign extension.
11248 convI2L_reg(src2s, src2); // Ensure proper sign extension.
11249 subL_reg_reg(diff, src2s, src1s);
11250 // Need to consider >=33 bit result, therefore we need signmaskL.
11251 signmask64L_regL(sm, diff);
11252 andcL_reg_reg(doz, diff, sm); // >=0
11253 addI_regL_regL(dst, doz, src1s);
11254 %}
11255 %}
11256
11257 //---------- Population Count Instructions ------------------------------------
11258
11259 // Popcnt for Power7.
11260 instruct popCountI(iRegIdst dst, iRegIsrc src) %{
11261 match(Set dst (PopCountI src));
11262 predicate(UsePopCountInstruction && VM_Version::has_popcntw());
11263 ins_cost(DEFAULT_COST);
11264
11265 format %{ "POPCNTW $dst, $src" %}
11266 size(4);
11267 ins_encode %{
11268 // TODO: PPC port $archOpcode(ppc64Opcode_popcntb);
11269 __ popcntw($dst$$Register, $src$$Register);
11270 %}
11271 ins_pipe(pipe_class_default);
11272 %}
11273
11274 // Popcnt for Power7.
11275 instruct popCountL(iRegIdst dst, iRegLsrc src) %{
11276 predicate(UsePopCountInstruction && VM_Version::has_popcntw());
11277 match(Set dst (PopCountL src));
11278 ins_cost(DEFAULT_COST);
11279
11280 format %{ "POPCNTD $dst, $src" %}
11281 size(4);
11282 ins_encode %{
11283 // TODO: PPC port $archOpcode(ppc64Opcode_popcntb);
11284 __ popcntd($dst$$Register, $src$$Register);
11285 %}
11286 ins_pipe(pipe_class_default);
11287 %}
11288
11289 instruct countLeadingZerosI(iRegIdst dst, iRegIsrc src) %{
11290 match(Set dst (CountLeadingZerosI src));
11291 predicate(UseCountLeadingZerosInstructionsPPC64); // See Matcher::match_rule_supported.
11292 ins_cost(DEFAULT_COST);
11293
11294 format %{ "CNTLZW $dst, $src" %}
11295 size(4);
11296 ins_encode %{
11297 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzw);
11298 __ cntlzw($dst$$Register, $src$$Register);
11299 %}
11300 ins_pipe(pipe_class_default);
11301 %}
11302
11303 instruct countLeadingZerosL(iRegIdst dst, iRegLsrc src) %{
11304 match(Set dst (CountLeadingZerosL src));
11305 predicate(UseCountLeadingZerosInstructionsPPC64); // See Matcher::match_rule_supported.
11306 ins_cost(DEFAULT_COST);
11307
11308 format %{ "CNTLZD $dst, $src" %}
11309 size(4);
11310 ins_encode %{
11311 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd);
11312 __ cntlzd($dst$$Register, $src$$Register);
11313 %}
11314 ins_pipe(pipe_class_default);
11315 %}
11316
11317 instruct countLeadingZerosP(iRegIdst dst, iRegPsrc src) %{
11318 // no match-rule, false predicate
11319 effect(DEF dst, USE src);
11320 predicate(false);
11321
11322 format %{ "CNTLZD $dst, $src" %}
11323 size(4);
11324 ins_encode %{
11325 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd);
11326 __ cntlzd($dst$$Register, $src$$Register);
11327 %}
11328 ins_pipe(pipe_class_default);
11329 %}
11330
11331 instruct countTrailingZerosI_Ex(iRegIdst dst, iRegIsrc src) %{
11332 match(Set dst (CountTrailingZerosI src));
11333 predicate(UseCountLeadingZerosInstructionsPPC64);
11334 ins_cost(DEFAULT_COST);
11335
11336 expand %{
11337 immI16 imm1 %{ (int)-1 %}
11338 immI16 imm2 %{ (int)32 %}
11339 immI_minus1 m1 %{ -1 %}
11340 iRegIdst tmpI1;
11341 iRegIdst tmpI2;
11342 iRegIdst tmpI3;
11343 addI_reg_imm16(tmpI1, src, imm1);
11344 andcI_reg_reg(tmpI2, src, m1, tmpI1);
11345 countLeadingZerosI(tmpI3, tmpI2);
11346 subI_imm16_reg(dst, imm2, tmpI3);
11347 %}
11348 %}
11349
11350 instruct countTrailingZerosL_Ex(iRegIdst dst, iRegLsrc src) %{
11351 match(Set dst (CountTrailingZerosL src));
11352 predicate(UseCountLeadingZerosInstructionsPPC64);
11353 ins_cost(DEFAULT_COST);
11354
11355 expand %{
11356 immL16 imm1 %{ (long)-1 %}
11357 immI16 imm2 %{ (int)64 %}
11358 iRegLdst tmpL1;
11359 iRegLdst tmpL2;
11360 iRegIdst tmpL3;
11361 addL_reg_imm16(tmpL1, src, imm1);
11362 andcL_reg_reg(tmpL2, tmpL1, src);
11363 countLeadingZerosL(tmpL3, tmpL2);
11364 subI_imm16_reg(dst, imm2, tmpL3);
11365 %}
11366 %}
11367
11368 // Expand nodes for byte_reverse_int.
11369 instruct insrwi_a(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{
11370 effect(DEF dst, USE src, USE pos, USE shift);
11371 predicate(false);
11372
11373 format %{ "INSRWI $dst, $src, $pos, $shift" %}
11374 size(4);
11375 ins_encode %{
11376 // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi);
11377 __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant);
11378 %}
11379 ins_pipe(pipe_class_default);
11380 %}
11381
11382 // As insrwi_a, but with USE_DEF.
11383 instruct insrwi(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{
11384 effect(USE_DEF dst, USE src, USE pos, USE shift);
11385 predicate(false);
11386
11387 format %{ "INSRWI $dst, $src, $pos, $shift" %}
11388 size(4);
11389 ins_encode %{
11390 // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi);
11391 __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant);
11392 %}
11393 ins_pipe(pipe_class_default);
11394 %}
11395
11396 // Just slightly faster than java implementation.
11397 instruct bytes_reverse_int_Ex(iRegIdst dst, iRegIsrc src) %{
11398 match(Set dst (ReverseBytesI src));
11399 predicate(UseCountLeadingZerosInstructionsPPC64);
11400 ins_cost(DEFAULT_COST);
11401
11402 expand %{
11403 immI16 imm24 %{ (int) 24 %}
11404 immI16 imm16 %{ (int) 16 %}
11405 immI16 imm8 %{ (int) 8 %}
11406 immI16 imm4 %{ (int) 4 %}
11407 immI16 imm0 %{ (int) 0 %}
11408 iRegLdst tmpI1;
11409 iRegLdst tmpI2;
11410 iRegLdst tmpI3;
11411
11412 urShiftI_reg_imm(tmpI1, src, imm24);
11413 insrwi_a(dst, tmpI1, imm24, imm8);
11414 urShiftI_reg_imm(tmpI2, src, imm16);
11415 insrwi(dst, tmpI2, imm8, imm16);
11416 urShiftI_reg_imm(tmpI3, src, imm8);
11417 insrwi(dst, tmpI3, imm8, imm8);
11418 insrwi(dst, src, imm0, imm8);
11419 %}
11420 %}
11421
11422 //---------- Replicate Vector Instructions ------------------------------------
11423
11424 // Insrdi does replicate if src == dst.
11425 instruct repl32(iRegLdst dst) %{
11426 predicate(false);
11427 effect(USE_DEF dst);
11428
11429 format %{ "INSRDI $dst, #0, $dst, #32 \t// replicate" %}
11430 size(4);
11431 ins_encode %{
11432 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
11433 __ insrdi($dst$$Register, $dst$$Register, 32, 0);
11434 %}
11435 ins_pipe(pipe_class_default);
11436 %}
11437
11438 // Insrdi does replicate if src == dst.
11439 instruct repl48(iRegLdst dst) %{
11440 predicate(false);
11441 effect(USE_DEF dst);
11442
11443 format %{ "INSRDI $dst, #0, $dst, #48 \t// replicate" %}
11444 size(4);
11445 ins_encode %{
11446 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
11447 __ insrdi($dst$$Register, $dst$$Register, 48, 0);
11448 %}
11449 ins_pipe(pipe_class_default);
11450 %}
11451
11452 // Insrdi does replicate if src == dst.
11453 instruct repl56(iRegLdst dst) %{
11454 predicate(false);
11455 effect(USE_DEF dst);
11456
11457 format %{ "INSRDI $dst, #0, $dst, #56 \t// replicate" %}
11458 size(4);
11459 ins_encode %{
11460 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
11461 __ insrdi($dst$$Register, $dst$$Register, 56, 0);
11462 %}
11463 ins_pipe(pipe_class_default);
11464 %}
11465
11466 instruct repl8B_reg_Ex(iRegLdst dst, iRegIsrc src) %{
11467 match(Set dst (ReplicateB src));
11468 predicate(n->as_Vector()->length() == 8);
11469 expand %{
11470 moveReg(dst, src);
11471 repl56(dst);
11472 repl48(dst);
11473 repl32(dst);
11474 %}
11475 %}
11476
11477 instruct repl8B_immI0(iRegLdst dst, immI_0 zero) %{
11478 match(Set dst (ReplicateB zero));
11479 predicate(n->as_Vector()->length() == 8);
11480 format %{ "LI $dst, #0 \t// replicate8B" %}
11481 size(4);
11482 ins_encode %{
11483 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11484 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
11485 %}
11486 ins_pipe(pipe_class_default);
11487 %}
11488
11489 instruct repl8B_immIminus1(iRegLdst dst, immI_minus1 src) %{
11490 match(Set dst (ReplicateB src));
11491 predicate(n->as_Vector()->length() == 8);
11492 format %{ "LI $dst, #-1 \t// replicate8B" %}
11493 size(4);
11494 ins_encode %{
11495 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11496 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
11497 %}
11498 ins_pipe(pipe_class_default);
11499 %}
11500
11501 instruct repl4S_reg_Ex(iRegLdst dst, iRegIsrc src) %{
11502 match(Set dst (ReplicateS src));
11503 predicate(n->as_Vector()->length() == 4);
11504 expand %{
11505 moveReg(dst, src);
11506 repl48(dst);
11507 repl32(dst);
11508 %}
11509 %}
11510
11511 instruct repl4S_immI0(iRegLdst dst, immI_0 zero) %{
11512 match(Set dst (ReplicateS zero));
11513 predicate(n->as_Vector()->length() == 4);
11514 format %{ "LI $dst, #0 \t// replicate4C" %}
11515 size(4);
11516 ins_encode %{
11517 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11518 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
11519 %}
11520 ins_pipe(pipe_class_default);
11521 %}
11522
11523 instruct repl4S_immIminus1(iRegLdst dst, immI_minus1 src) %{
11524 match(Set dst (ReplicateS src));
11525 predicate(n->as_Vector()->length() == 4);
11526 format %{ "LI $dst, -1 \t// replicate4C" %}
11527 size(4);
11528 ins_encode %{
11529 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11530 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
11531 %}
11532 ins_pipe(pipe_class_default);
11533 %}
11534
11535 instruct repl2I_reg_Ex(iRegLdst dst, iRegIsrc src) %{
11536 match(Set dst (ReplicateI src));
11537 predicate(n->as_Vector()->length() == 2);
11538 ins_cost(2 * DEFAULT_COST);
11539 expand %{
11540 moveReg(dst, src);
11541 repl32(dst);
11542 %}
11543 %}
11544
11545 instruct repl2I_immI0(iRegLdst dst, immI_0 zero) %{
11546 match(Set dst (ReplicateI zero));
11547 predicate(n->as_Vector()->length() == 2);
11548 format %{ "LI $dst, #0 \t// replicate4C" %}
11549 size(4);
11550 ins_encode %{
11551 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11552 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
11553 %}
11554 ins_pipe(pipe_class_default);
11555 %}
11556
11557 instruct repl2I_immIminus1(iRegLdst dst, immI_minus1 src) %{
11558 match(Set dst (ReplicateI src));
11559 predicate(n->as_Vector()->length() == 2);
11560 format %{ "LI $dst, -1 \t// replicate4C" %}
11561 size(4);
11562 ins_encode %{
11563 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11564 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
11565 %}
11566 ins_pipe(pipe_class_default);
11567 %}
11568
11569 // Move float to int register via stack, replicate.
11570 instruct repl2F_reg_Ex(iRegLdst dst, regF src) %{
11571 match(Set dst (ReplicateF src));
11572 predicate(n->as_Vector()->length() == 2);
11573 ins_cost(2 * MEMORY_REF_COST + DEFAULT_COST);
11574 expand %{
11575 stackSlotL tmpS;
11576 iRegIdst tmpI;
11577 moveF2I_reg_stack(tmpS, src); // Move float to stack.
11578 moveF2I_stack_reg(tmpI, tmpS); // Move stack to int reg.
11579 moveReg(dst, tmpI); // Move int to long reg.
11580 repl32(dst); // Replicate bitpattern.
11581 %}
11582 %}
11583
11584 // Replicate scalar constant to packed float values in Double register
11585 instruct repl2F_immF_Ex(iRegLdst dst, immF src) %{
11586 match(Set dst (ReplicateF src));
11587 predicate(n->as_Vector()->length() == 2);
11588 ins_cost(5 * DEFAULT_COST);
11589
11590 format %{ "LD $dst, offset, $constanttablebase\t// load replicated float $src $src from table, postalloc expanded" %}
11591 postalloc_expand( postalloc_expand_load_replF_constant(dst, src, constanttablebase) );
11592 %}
11593
11594 // Replicate scalar zero constant to packed float values in Double register
11595 instruct repl2F_immF0(iRegLdst dst, immF_0 zero) %{
11596 match(Set dst (ReplicateF zero));
11597 predicate(n->as_Vector()->length() == 2);
11598
11599 format %{ "LI $dst, #0 \t// replicate2F" %}
11600 ins_encode %{
11601 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11602 __ li($dst$$Register, 0x0);
11603 %}
11604 ins_pipe(pipe_class_default);
11605 %}
11606
11607 // ============================================================================
11608 // Safepoint Instruction
11609
11610 instruct safePoint_poll(iRegPdst poll) %{
11611 match(SafePoint poll);
11612 predicate(LoadPollAddressFromThread);
11613
11614 // It caused problems to add the effect that r0 is killed, but this
11615 // effect no longer needs to be mentioned, since r0 is not contained
11616 // in a reg_class.
11617
11618 format %{ "LD R0, #0, $poll \t// Safepoint poll for GC" %}
11619 size(4);
11620 ins_encode( enc_poll(0x0, poll) );
11621 ins_pipe(pipe_class_default);
11622 %}
11623
11624 // Safepoint without per-thread support. Load address of page to poll
11625 // as constant.
11626 // Rscratch2RegP is R12.
11627 // LoadConPollAddr node is added in pd_post_matching_hook(). It must be
11628 // a seperate node so that the oop map is at the right location.
11629 instruct safePoint_poll_conPollAddr(rscratch2RegP poll) %{
11630 match(SafePoint poll);
11631 predicate(!LoadPollAddressFromThread);
11632
11633 // It caused problems to add the effect that r0 is killed, but this
11634 // effect no longer needs to be mentioned, since r0 is not contained
11635 // in a reg_class.
11636
11637 format %{ "LD R0, #0, R12 \t// Safepoint poll for GC" %}
11638 ins_encode( enc_poll(0x0, poll) );
11639 ins_pipe(pipe_class_default);
11640 %}
11641
11642 // ============================================================================
11643 // Call Instructions
11644
11645 // Call Java Static Instruction
11646
11647 // Schedulable version of call static node.
11648 instruct CallStaticJavaDirect(method meth) %{
11649 match(CallStaticJava);
11650 effect(USE meth);
11651 predicate(!((CallStaticJavaNode*)n)->is_method_handle_invoke());
11652 ins_cost(CALL_COST);
11653
11654 ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */);
11655
11656 format %{ "CALL,static $meth \t// ==> " %}
11657 size(4);
11658 ins_encode( enc_java_static_call(meth) );
11659 ins_pipe(pipe_class_call);
11660 %}
11661
11662 // Schedulable version of call static node.
11663 instruct CallStaticJavaDirectHandle(method meth) %{
11664 match(CallStaticJava);
11665 effect(USE meth);
11666 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
11667 ins_cost(CALL_COST);
11668
11669 ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */);
11670
11671 format %{ "CALL,static $meth \t// ==> " %}
11672 ins_encode( enc_java_handle_call(meth) );
11673 ins_pipe(pipe_class_call);
11674 %}
11675
11676 // Call Java Dynamic Instruction
11677
11678 // Used by postalloc expand of CallDynamicJavaDirectSchedEx (actual call).
11679 // Loading of IC was postalloc expanded. The nodes loading the IC are reachable
11680 // via fields ins_field_load_ic_hi_node and ins_field_load_ic_node.
11681 // The call destination must still be placed in the constant pool.
11682 instruct CallDynamicJavaDirectSched(method meth) %{
11683 match(CallDynamicJava); // To get all the data fields we need ...
11684 effect(USE meth);
11685 predicate(false); // ... but never match.
11686
11687 ins_field_load_ic_hi_node(loadConL_hiNode*);
11688 ins_field_load_ic_node(loadConLNode*);
11689 ins_num_consts(1 /* 1 patchable constant: call destination */);
11690
11691 format %{ "BL \t// dynamic $meth ==> " %}
11692 size(4);
11693 ins_encode( enc_java_dynamic_call_sched(meth) );
11694 ins_pipe(pipe_class_call);
11695 %}
11696
11697 // Schedulable (i.e. postalloc expanded) version of call dynamic java.
11698 // We use postalloc expanded calls if we use inline caches
11699 // and do not update method data.
11700 //
11701 // This instruction has two constants: inline cache (IC) and call destination.
11702 // Loading the inline cache will be postalloc expanded, thus leaving a call with
11703 // one constant.
11704 instruct CallDynamicJavaDirectSched_Ex(method meth) %{
11705 match(CallDynamicJava);
11706 effect(USE meth);
11707 predicate(UseInlineCaches);
11708 ins_cost(CALL_COST);
11709
11710 ins_num_consts(2 /* 2 patchable constants: inline cache, call destination. */);
11711
11712 format %{ "CALL,dynamic $meth \t// postalloc expanded" %}
11713 postalloc_expand( postalloc_expand_java_dynamic_call_sched(meth, constanttablebase) );
11714 %}
11715
11716 // Compound version of call dynamic java
11717 // We use postalloc expanded calls if we use inline caches
11718 // and do not update method data.
11719 instruct CallDynamicJavaDirect(method meth) %{
11720 match(CallDynamicJava);
11721 effect(USE meth);
11722 predicate(!UseInlineCaches);
11723 ins_cost(CALL_COST);
11724
11725 // Enc_java_to_runtime_call needs up to 4 constants (method data oop).
11726 ins_num_consts(4);
11727
11728 format %{ "CALL,dynamic $meth \t// ==> " %}
11729 ins_encode( enc_java_dynamic_call(meth, constanttablebase) );
11730 ins_pipe(pipe_class_call);
11731 %}
11732
11733 // Call Runtime Instruction
11734
11735 instruct CallRuntimeDirect(method meth) %{
11736 match(CallRuntime);
11737 effect(USE meth);
11738 ins_cost(CALL_COST);
11739
11740 // Enc_java_to_runtime_call needs up to 3 constants: call target,
11741 // env for callee, C-toc.
11742 ins_num_consts(3);
11743
11744 format %{ "CALL,runtime" %}
11745 ins_encode( enc_java_to_runtime_call(meth) );
11746 ins_pipe(pipe_class_call);
11747 %}
11748
11749 // Call Leaf
11750
11751 // Used by postalloc expand of CallLeafDirect_Ex (mtctr).
11752 instruct CallLeafDirect_mtctr(iRegLdst dst, iRegLsrc src) %{
11753 effect(DEF dst, USE src);
11754
11755 ins_num_consts(1);
11756
11757 format %{ "MTCTR $src" %}
11758 size(4);
11759 ins_encode( enc_leaf_call_mtctr(src) );
11760 ins_pipe(pipe_class_default);
11761 %}
11762
11763 // Used by postalloc expand of CallLeafDirect_Ex (actual call).
11764 instruct CallLeafDirect(method meth) %{
11765 match(CallLeaf); // To get the data all the data fields we need ...
11766 effect(USE meth);
11767 predicate(false); // but never match.
11768
11769 format %{ "BCTRL \t// leaf call $meth ==> " %}
11770 size(4);
11771 ins_encode %{
11772 // TODO: PPC port $archOpcode(ppc64Opcode_bctrl);
11773 __ bctrl();
11774 %}
11775 ins_pipe(pipe_class_call);
11776 %}
11777
11778 // postalloc expand of CallLeafDirect.
11779 // Load adress to call from TOC, then bl to it.
11780 instruct CallLeafDirect_Ex(method meth) %{
11781 match(CallLeaf);
11782 effect(USE meth);
11783 ins_cost(CALL_COST);
11784
11785 // Postalloc_expand_java_to_runtime_call needs up to 3 constants: call target,
11786 // env for callee, C-toc.
11787 ins_num_consts(3);
11788
11789 format %{ "CALL,runtime leaf $meth \t// postalloc expanded" %}
11790 postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) );
11791 %}
11792
11793 // Call runtime without safepoint - same as CallLeaf.
11794 // postalloc expand of CallLeafNoFPDirect.
11795 // Load adress to call from TOC, then bl to it.
11796 instruct CallLeafNoFPDirect_Ex(method meth) %{
11797 match(CallLeafNoFP);
11798 effect(USE meth);
11799 ins_cost(CALL_COST);
11800
11801 // Enc_java_to_runtime_call needs up to 3 constants: call target,
11802 // env for callee, C-toc.
11803 ins_num_consts(3);
11804
11805 format %{ "CALL,runtime leaf nofp $meth \t// postalloc expanded" %}
11806 postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) );
11807 %}
11808
11809 // Tail Call; Jump from runtime stub to Java code.
11810 // Also known as an 'interprocedural jump'.
11811 // Target of jump will eventually return to caller.
11812 // TailJump below removes the return address.
11813 instruct TailCalljmpInd(iRegPdstNoScratch jump_target, inline_cache_regP method_oop) %{
11814 match(TailCall jump_target method_oop);
11815 ins_cost(CALL_COST);
11816
11817 format %{ "MTCTR $jump_target \t// $method_oop holds method oop\n\t"
11818 "BCTR \t// tail call" %}
11819 size(8);
11820 ins_encode %{
11821 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11822 __ mtctr($jump_target$$Register);
11823 __ bctr();
11824 %}
11825 ins_pipe(pipe_class_call);
11826 %}
11827
11828 // Return Instruction
11829 instruct Ret() %{
11830 match(Return);
11831 format %{ "BLR \t// branch to link register" %}
11832 size(4);
11833 ins_encode %{
11834 // TODO: PPC port $archOpcode(ppc64Opcode_blr);
11835 // LR is restored in MachEpilogNode. Just do the RET here.
11836 __ blr();
11837 %}
11838 ins_pipe(pipe_class_default);
11839 %}
11840
11841 // Tail Jump; remove the return address; jump to target.
11842 // TailCall above leaves the return address around.
11843 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
11844 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
11845 // "restore" before this instruction (in Epilogue), we need to materialize it
11846 // in %i0.
11847 instruct tailjmpInd(iRegPdstNoScratch jump_target, rarg1RegP ex_oop) %{
11848 match(TailJump jump_target ex_oop);
11849 ins_cost(CALL_COST);
11850
11851 format %{ "LD R4_ARG2 = LR\n\t"
11852 "MTCTR $jump_target\n\t"
11853 "BCTR \t// TailJump, exception oop: $ex_oop" %}
11854 size(12);
11855 ins_encode %{
11856 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11857 __ ld(R4_ARG2/* issuing pc */, _abi(lr), R1_SP);
11858 __ mtctr($jump_target$$Register);
11859 __ bctr();
11860 %}
11861 ins_pipe(pipe_class_call);
11862 %}
11863
11864 // Create exception oop: created by stack-crawling runtime code.
11865 // Created exception is now available to this handler, and is setup
11866 // just prior to jumping to this handler. No code emitted.
11867 instruct CreateException(rarg1RegP ex_oop) %{
11868 match(Set ex_oop (CreateEx));
11869 ins_cost(0);
11870
11871 format %{ " -- \t// exception oop; no code emitted" %}
11872 size(0);
11873 ins_encode( /*empty*/ );
11874 ins_pipe(pipe_class_default);
11875 %}
11876
11877 // Rethrow exception: The exception oop will come in the first
11878 // argument position. Then JUMP (not call) to the rethrow stub code.
11879 instruct RethrowException() %{
11880 match(Rethrow);
11881 ins_cost(CALL_COST);
11882
11883 format %{ "Jmp rethrow_stub" %}
11884 ins_encode %{
11885 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11886 cbuf.set_insts_mark();
11887 __ b64_patchable((address)OptoRuntime::rethrow_stub(), relocInfo::runtime_call_type);
11888 %}
11889 ins_pipe(pipe_class_call);
11890 %}
11891
11892 // Die now.
11893 instruct ShouldNotReachHere() %{
11894 match(Halt);
11895 ins_cost(CALL_COST);
11896
11897 format %{ "ShouldNotReachHere" %}
11898 size(4);
11899 ins_encode %{
11900 // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
11901 __ trap_should_not_reach_here();
11902 %}
11903 ins_pipe(pipe_class_default);
11904 %}
11905
11906 // This name is KNOWN by the ADLC and cannot be changed. The ADLC
11907 // forces a 'TypeRawPtr::BOTTOM' output type for this guy.
11908 // Get a DEF on threadRegP, no costs, no encoding, use
11909 // 'ins_should_rematerialize(true)' to avoid spilling.
11910 instruct tlsLoadP(threadRegP dst) %{
11911 match(Set dst (ThreadLocal));
11912 ins_cost(0);
11913
11914 ins_should_rematerialize(true);
11915
11916 format %{ " -- \t// $dst=Thread::current(), empty" %}
11917 size(0);
11918 ins_encode( /*empty*/ );
11919 ins_pipe(pipe_class_empty);
11920 %}
11921
11922 //---Some PPC specific nodes---------------------------------------------------
11923
11924 // Stop a group.
11925 instruct endGroup() %{
11926 ins_cost(0);
11927
11928 ins_is_nop(true);
11929
11930 format %{ "End Bundle (ori r1, r1, 0)" %}
11931 size(4);
11932 ins_encode %{
11933 // TODO: PPC port $archOpcode(ppc64Opcode_endgroup);
11934 __ endgroup();
11935 %}
11936 ins_pipe(pipe_class_default);
11937 %}
11938
11939 // Nop instructions
11940
11941 instruct fxNop() %{
11942 ins_cost(0);
11943
11944 ins_is_nop(true);
11945
11946 format %{ "fxNop" %}
11947 size(4);
11948 ins_encode %{
11949 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
11950 __ nop();
11951 %}
11952 ins_pipe(pipe_class_default);
11953 %}
11954
11955 instruct fpNop0() %{
11956 ins_cost(0);
11957
11958 ins_is_nop(true);
11959
11960 format %{ "fpNop0" %}
11961 size(4);
11962 ins_encode %{
11963 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
11964 __ fpnop0();
11965 %}
11966 ins_pipe(pipe_class_default);
11967 %}
11968
11969 instruct fpNop1() %{
11970 ins_cost(0);
11971
11972 ins_is_nop(true);
11973
11974 format %{ "fpNop1" %}
11975 size(4);
11976 ins_encode %{
11977 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
11978 __ fpnop1();
11979 %}
11980 ins_pipe(pipe_class_default);
11981 %}
11982
11983 instruct brNop0() %{
11984 ins_cost(0);
11985 size(4);
11986 format %{ "brNop0" %}
11987 ins_encode %{
11988 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
11989 __ brnop0();
11990 %}
11991 ins_is_nop(true);
11992 ins_pipe(pipe_class_default);
11993 %}
11994
11995 instruct brNop1() %{
11996 ins_cost(0);
11997
11998 ins_is_nop(true);
11999
12000 format %{ "brNop1" %}
12001 size(4);
12002 ins_encode %{
12003 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
12004 __ brnop1();
12005 %}
12006 ins_pipe(pipe_class_default);
12007 %}
12008
12009 instruct brNop2() %{
12010 ins_cost(0);
12011
12012 ins_is_nop(true);
12013
12014 format %{ "brNop2" %}
12015 size(4);
12016 ins_encode %{
12017 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
12018 __ brnop2();
12019 %}
12020 ins_pipe(pipe_class_default);
12021 %}
12022
12023 //----------PEEPHOLE RULES-----------------------------------------------------
12024 // These must follow all instruction definitions as they use the names
12025 // defined in the instructions definitions.
12026 //
12027 // peepmatch ( root_instr_name [preceeding_instruction]* );
12028 //
12029 // peepconstraint %{
12030 // (instruction_number.operand_name relational_op instruction_number.operand_name
12031 // [, ...] );
12032 // // instruction numbers are zero-based using left to right order in peepmatch
12033 //
12034 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
12035 // // provide an instruction_number.operand_name for each operand that appears
12036 // // in the replacement instruction's match rule
12037 //
12038 // ---------VM FLAGS---------------------------------------------------------
12039 //
12040 // All peephole optimizations can be turned off using -XX:-OptoPeephole
12041 //
12042 // Each peephole rule is given an identifying number starting with zero and
12043 // increasing by one in the order seen by the parser. An individual peephole
12044 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
12045 // on the command-line.
12046 //
12047 // ---------CURRENT LIMITATIONS----------------------------------------------
12048 //
12049 // Only match adjacent instructions in same basic block
12050 // Only equality constraints
12051 // Only constraints between operands, not (0.dest_reg == EAX_enc)
12052 // Only one replacement instruction
12053 //
12054 // ---------EXAMPLE----------------------------------------------------------
12055 //
12056 // // pertinent parts of existing instructions in architecture description
12057 // instruct movI(eRegI dst, eRegI src) %{
12058 // match(Set dst (CopyI src));
12059 // %}
12060 //
12061 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
12062 // match(Set dst (AddI dst src));
12063 // effect(KILL cr);
12064 // %}
12065 //
12066 // // Change (inc mov) to lea
12067 // peephole %{
12068 // // increment preceeded by register-register move
12069 // peepmatch ( incI_eReg movI );
12070 // // require that the destination register of the increment
12071 // // match the destination register of the move
12072 // peepconstraint ( 0.dst == 1.dst );
12073 // // construct a replacement instruction that sets
12074 // // the destination to ( move's source register + one )
12075 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12076 // %}
12077 //
12078 // Implementation no longer uses movX instructions since
12079 // machine-independent system no longer uses CopyX nodes.
12080 //
12081 // peephole %{
12082 // peepmatch ( incI_eReg movI );
12083 // peepconstraint ( 0.dst == 1.dst );
12084 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12085 // %}
12086 //
12087 // peephole %{
12088 // peepmatch ( decI_eReg movI );
12089 // peepconstraint ( 0.dst == 1.dst );
12090 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12091 // %}
12092 //
12093 // peephole %{
12094 // peepmatch ( addI_eReg_imm movI );
12095 // peepconstraint ( 0.dst == 1.dst );
12096 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12097 // %}
12098 //
12099 // peephole %{
12100 // peepmatch ( addP_eReg_imm movP );
12101 // peepconstraint ( 0.dst == 1.dst );
12102 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
12103 // %}
12104
12105 // // Change load of spilled value to only a spill
12106 // instruct storeI(memory mem, eRegI src) %{
12107 // match(Set mem (StoreI mem src));
12108 // %}
12109 //
12110 // instruct loadI(eRegI dst, memory mem) %{
12111 // match(Set dst (LoadI mem));
12112 // %}
12113 //
12114 peephole %{
12115 peepmatch ( loadI storeI );
12116 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
12117 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
12118 %}
12119
12120 peephole %{
12121 peepmatch ( loadL storeL );
12122 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
12123 peepreplace ( storeL( 1.mem 1.mem 1.src ) );
12124 %}
12125
12126 peephole %{
12127 peepmatch ( loadP storeP );
12128 peepconstraint ( 1.src == 0.dst, 1.dst == 0.mem );
12129 peepreplace ( storeP( 1.dst 1.dst 1.src ) );
12130 %}
12131
12132 //----------SMARTSPILL RULES---------------------------------------------------
12133 // These must follow all instruction definitions as they use the names
12134 // defined in the instructions definitions.