1 //
   2 // Copyright (c) 1998, 2013, Oracle and/or its affiliates. All rights reserved.
   3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4 //
   5 // This code is free software; you can redistribute it and/or modify it
   6 // under the terms of the GNU General Public License version 2 only, as
   7 // published by the Free Software Foundation.
   8 //
   9 // This code is distributed in the hope that it will be useful, but WITHOUT
  10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12 // version 2 for more details (a copy is included in the LICENSE file that
  13 // accompanied this code).
  14 //
  15 // You should have received a copy of the GNU General Public License version
  16 // 2 along with this work; if not, write to the Free Software Foundation,
  17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18 //
  19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20 // or visit www.oracle.com if you need additional information or have any
  21 // questions.
  22 //
  23 //
  24 
  25 // SPARC Architecture Description File
  26 
  27 //----------REGISTER DEFINITION BLOCK------------------------------------------
  28 // This information is used by the matcher and the register allocator to
  29 // describe individual registers and classes of registers within the target
  30 // archtecture.
  31 register %{
  32 //----------Architecture Description Register Definitions----------------------
  33 // General Registers
  34 // "reg_def"  name ( register save type, C convention save type,
  35 //                   ideal register type, encoding, vm name );
  36 // Register Save Types:
  37 //
  38 // NS  = No-Save:       The register allocator assumes that these registers
  39 //                      can be used without saving upon entry to the method, &
  40 //                      that they do not need to be saved at call sites.
  41 //
  42 // SOC = Save-On-Call:  The register allocator assumes that these registers
  43 //                      can be used without saving upon entry to the method,
  44 //                      but that they must be saved at call sites.
  45 //
  46 // SOE = Save-On-Entry: The register allocator assumes that these registers
  47 //                      must be saved before using them upon entry to the
  48 //                      method, but they do not need to be saved at call
  49 //                      sites.
  50 //
  51 // AS  = Always-Save:   The register allocator assumes that these registers
  52 //                      must be saved before using them upon entry to the
  53 //                      method, & that they must be saved at call sites.
  54 //
  55 // Ideal Register Type is used to determine how to save & restore a
  56 // register.  Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
  57 // spilled with LoadP/StoreP.  If the register supports both, use Op_RegI.
  58 //
  59 // The encoding number is the actual bit-pattern placed into the opcodes.
  60 
  61 
  62 // ----------------------------
  63 // Integer/Long Registers
  64 // ----------------------------
  65 
  66 // Need to expose the hi/lo aspect of 64-bit registers
  67 // This register set is used for both the 64-bit build and
  68 // the 32-bit build with 1-register longs.
  69 
  70 // Global Registers 0-7
  71 reg_def R_G0H( NS,  NS, Op_RegI,128, G0->as_VMReg()->next());
  72 reg_def R_G0 ( NS,  NS, Op_RegI,  0, G0->as_VMReg());
  73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next());
  74 reg_def R_G1 (SOC, SOC, Op_RegI,  1, G1->as_VMReg());
  75 reg_def R_G2H( NS,  NS, Op_RegI,130, G2->as_VMReg()->next());
  76 reg_def R_G2 ( NS,  NS, Op_RegI,  2, G2->as_VMReg());
  77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next());
  78 reg_def R_G3 (SOC, SOC, Op_RegI,  3, G3->as_VMReg());
  79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next());
  80 reg_def R_G4 (SOC, SOC, Op_RegI,  4, G4->as_VMReg());
  81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next());
  82 reg_def R_G5 (SOC, SOC, Op_RegI,  5, G5->as_VMReg());
  83 reg_def R_G6H( NS,  NS, Op_RegI,134, G6->as_VMReg()->next());
  84 reg_def R_G6 ( NS,  NS, Op_RegI,  6, G6->as_VMReg());
  85 reg_def R_G7H( NS,  NS, Op_RegI,135, G7->as_VMReg()->next());
  86 reg_def R_G7 ( NS,  NS, Op_RegI,  7, G7->as_VMReg());
  87 
  88 // Output Registers 0-7
  89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next());
  90 reg_def R_O0 (SOC, SOC, Op_RegI,  8, O0->as_VMReg());
  91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next());
  92 reg_def R_O1 (SOC, SOC, Op_RegI,  9, O1->as_VMReg());
  93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next());
  94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg());
  95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next());
  96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg());
  97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next());
  98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg());
  99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next());
 100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg());
 101 reg_def R_SPH( NS,  NS, Op_RegI,142, SP->as_VMReg()->next());
 102 reg_def R_SP ( NS,  NS, Op_RegI, 14, SP->as_VMReg());
 103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next());
 104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg());
 105 
 106 // Local Registers 0-7
 107 reg_def R_L0H( NS,  NS, Op_RegI,144, L0->as_VMReg()->next());
 108 reg_def R_L0 ( NS,  NS, Op_RegI, 16, L0->as_VMReg());
 109 reg_def R_L1H( NS,  NS, Op_RegI,145, L1->as_VMReg()->next());
 110 reg_def R_L1 ( NS,  NS, Op_RegI, 17, L1->as_VMReg());
 111 reg_def R_L2H( NS,  NS, Op_RegI,146, L2->as_VMReg()->next());
 112 reg_def R_L2 ( NS,  NS, Op_RegI, 18, L2->as_VMReg());
 113 reg_def R_L3H( NS,  NS, Op_RegI,147, L3->as_VMReg()->next());
 114 reg_def R_L3 ( NS,  NS, Op_RegI, 19, L3->as_VMReg());
 115 reg_def R_L4H( NS,  NS, Op_RegI,148, L4->as_VMReg()->next());
 116 reg_def R_L4 ( NS,  NS, Op_RegI, 20, L4->as_VMReg());
 117 reg_def R_L5H( NS,  NS, Op_RegI,149, L5->as_VMReg()->next());
 118 reg_def R_L5 ( NS,  NS, Op_RegI, 21, L5->as_VMReg());
 119 reg_def R_L6H( NS,  NS, Op_RegI,150, L6->as_VMReg()->next());
 120 reg_def R_L6 ( NS,  NS, Op_RegI, 22, L6->as_VMReg());
 121 reg_def R_L7H( NS,  NS, Op_RegI,151, L7->as_VMReg()->next());
 122 reg_def R_L7 ( NS,  NS, Op_RegI, 23, L7->as_VMReg());
 123 
 124 // Input Registers 0-7
 125 reg_def R_I0H( NS,  NS, Op_RegI,152, I0->as_VMReg()->next());
 126 reg_def R_I0 ( NS,  NS, Op_RegI, 24, I0->as_VMReg());
 127 reg_def R_I1H( NS,  NS, Op_RegI,153, I1->as_VMReg()->next());
 128 reg_def R_I1 ( NS,  NS, Op_RegI, 25, I1->as_VMReg());
 129 reg_def R_I2H( NS,  NS, Op_RegI,154, I2->as_VMReg()->next());
 130 reg_def R_I2 ( NS,  NS, Op_RegI, 26, I2->as_VMReg());
 131 reg_def R_I3H( NS,  NS, Op_RegI,155, I3->as_VMReg()->next());
 132 reg_def R_I3 ( NS,  NS, Op_RegI, 27, I3->as_VMReg());
 133 reg_def R_I4H( NS,  NS, Op_RegI,156, I4->as_VMReg()->next());
 134 reg_def R_I4 ( NS,  NS, Op_RegI, 28, I4->as_VMReg());
 135 reg_def R_I5H( NS,  NS, Op_RegI,157, I5->as_VMReg()->next());
 136 reg_def R_I5 ( NS,  NS, Op_RegI, 29, I5->as_VMReg());
 137 reg_def R_FPH( NS,  NS, Op_RegI,158, FP->as_VMReg()->next());
 138 reg_def R_FP ( NS,  NS, Op_RegI, 30, FP->as_VMReg());
 139 reg_def R_I7H( NS,  NS, Op_RegI,159, I7->as_VMReg()->next());
 140 reg_def R_I7 ( NS,  NS, Op_RegI, 31, I7->as_VMReg());
 141 
 142 // ----------------------------
 143 // Float/Double Registers
 144 // ----------------------------
 145 
 146 // Float Registers
 147 reg_def R_F0 ( SOC, SOC, Op_RegF,  0, F0->as_VMReg());
 148 reg_def R_F1 ( SOC, SOC, Op_RegF,  1, F1->as_VMReg());
 149 reg_def R_F2 ( SOC, SOC, Op_RegF,  2, F2->as_VMReg());
 150 reg_def R_F3 ( SOC, SOC, Op_RegF,  3, F3->as_VMReg());
 151 reg_def R_F4 ( SOC, SOC, Op_RegF,  4, F4->as_VMReg());
 152 reg_def R_F5 ( SOC, SOC, Op_RegF,  5, F5->as_VMReg());
 153 reg_def R_F6 ( SOC, SOC, Op_RegF,  6, F6->as_VMReg());
 154 reg_def R_F7 ( SOC, SOC, Op_RegF,  7, F7->as_VMReg());
 155 reg_def R_F8 ( SOC, SOC, Op_RegF,  8, F8->as_VMReg());
 156 reg_def R_F9 ( SOC, SOC, Op_RegF,  9, F9->as_VMReg());
 157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg());
 158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg());
 159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg());
 160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg());
 161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg());
 162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg());
 163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg());
 164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg());
 165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg());
 166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg());
 167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg());
 168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg());
 169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg());
 170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg());
 171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg());
 172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg());
 173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg());
 174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg());
 175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg());
 176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg());
 177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg());
 178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg());
 179 
 180 // Double Registers
 181 // The rules of ADL require that double registers be defined in pairs.
 182 // Each pair must be two 32-bit values, but not necessarily a pair of
 183 // single float registers.  In each pair, ADLC-assigned register numbers
 184 // must be adjacent, with the lower number even.  Finally, when the
 185 // CPU stores such a register pair to memory, the word associated with
 186 // the lower ADLC-assigned number must be stored to the lower address.
 187 
 188 // These definitions specify the actual bit encodings of the sparc
 189 // double fp register numbers.  FloatRegisterImpl in register_sparc.hpp
 190 // wants 0-63, so we have to convert every time we want to use fp regs
 191 // with the macroassembler, using reg_to_DoubleFloatRegister_object().
 192 // 255 is a flag meaning "don't go here".
 193 // I believe we can't handle callee-save doubles D32 and up until
 194 // the place in the sparc stack crawler that asserts on the 255 is
 195 // fixed up.
 196 reg_def R_D32 (SOC, SOC, Op_RegD,  1, F32->as_VMReg());
 197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next());
 198 reg_def R_D34 (SOC, SOC, Op_RegD,  3, F34->as_VMReg());
 199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next());
 200 reg_def R_D36 (SOC, SOC, Op_RegD,  5, F36->as_VMReg());
 201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next());
 202 reg_def R_D38 (SOC, SOC, Op_RegD,  7, F38->as_VMReg());
 203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next());
 204 reg_def R_D40 (SOC, SOC, Op_RegD,  9, F40->as_VMReg());
 205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next());
 206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg());
 207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next());
 208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg());
 209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next());
 210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg());
 211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next());
 212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg());
 213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next());
 214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg());
 215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next());
 216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg());
 217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next());
 218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg());
 219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next());
 220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg());
 221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next());
 222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg());
 223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next());
 224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg());
 225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next());
 226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg());
 227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next());
 228 
 229 
 230 // ----------------------------
 231 // Special Registers
 232 // Condition Codes Flag Registers
 233 // I tried to break out ICC and XCC but it's not very pretty.
 234 // Every Sparc instruction which defs/kills one also kills the other.
 235 // Hence every compare instruction which defs one kind of flags ends
 236 // up needing a kill of the other.
 237 reg_def CCR (SOC, SOC,  Op_RegFlags, 0, VMRegImpl::Bad());
 238 
 239 reg_def FCC0(SOC, SOC,  Op_RegFlags, 0, VMRegImpl::Bad());
 240 reg_def FCC1(SOC, SOC,  Op_RegFlags, 1, VMRegImpl::Bad());
 241 reg_def FCC2(SOC, SOC,  Op_RegFlags, 2, VMRegImpl::Bad());
 242 reg_def FCC3(SOC, SOC,  Op_RegFlags, 3, VMRegImpl::Bad());
 243 
 244 // ----------------------------
 245 // Specify the enum values for the registers.  These enums are only used by the
 246 // OptoReg "class". We can convert these enum values at will to VMReg when needed
 247 // for visibility to the rest of the vm. The order of this enum influences the
 248 // register allocator so having the freedom to set this order and not be stuck
 249 // with the order that is natural for the rest of the vm is worth it.
 250 alloc_class chunk0(
 251   R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H,
 252   R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H,
 253   R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H,
 254   R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H);
 255 
 256 // Note that a register is not allocatable unless it is also mentioned
 257 // in a widely-used reg_class below.  Thus, R_G7 and R_G0 are outside i_reg.
 258 
 259 alloc_class chunk1(
 260   // The first registers listed here are those most likely to be used
 261   // as temporaries.  We move F0..F7 away from the front of the list,
 262   // to reduce the likelihood of interferences with parameters and
 263   // return values.  Likewise, we avoid using F0/F1 for parameters,
 264   // since they are used for return values.
 265   // This FPU fine-tuning is worth about 1% on the SPEC geomean.
 266   R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
 267   R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,
 268   R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31,
 269   R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values
 270   R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,
 271   R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
 272   R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,
 273   R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x);
 274 
 275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3);
 276 
 277 //----------Architecture Description Register Classes--------------------------
 278 // Several register classes are automatically defined based upon information in
 279 // this architecture description.
 280 // 1) reg_class inline_cache_reg           ( as defined in frame section )
 281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
 282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
 283 //
 284 
 285 // G0 is not included in integer class since it has special meaning.
 286 reg_class g0_reg(R_G0);
 287 
 288 // ----------------------------
 289 // Integer Register Classes
 290 // ----------------------------
 291 // Exclusions from i_reg:
 292 // R_G0: hardwired zero
 293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java)
 294 // R_G6: reserved by Solaris ABI to tools
 295 // R_G7: reserved by Solaris ABI to libthread
 296 // R_O7: Used as a temp in many encodings
 297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
 298 
 299 // Class for all integer registers, except the G registers.  This is used for
 300 // encodings which use G registers as temps.  The regular inputs to such
 301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator
 302 // will not put an input into a temp register.
 303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
 304 
 305 reg_class g1_regI(R_G1);
 306 reg_class g3_regI(R_G3);
 307 reg_class g4_regI(R_G4);
 308 reg_class o0_regI(R_O0);
 309 reg_class o7_regI(R_O7);
 310 
 311 // ----------------------------
 312 // Pointer Register Classes
 313 // ----------------------------
 314 #ifdef _LP64
 315 // 64-bit build means 64-bit pointers means hi/lo pairs
 316 reg_class ptr_reg(            R_G1H,R_G1,             R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
 317                   R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
 318                   R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
 319                   R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
 320 // Lock encodings use G3 and G4 internally
 321 reg_class lock_ptr_reg(       R_G1H,R_G1,                                     R_G5H,R_G5,
 322                   R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
 323                   R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
 324                   R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
 325 // Special class for storeP instructions, which can store SP or RPC to TLS.
 326 // It is also used for memory addressing, allowing direct TLS addressing.
 327 reg_class sp_ptr_reg(         R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
 328                   R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP,
 329                   R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
 330                   R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP );
 331 // R_L7 is the lowest-priority callee-save (i.e., NS) register
 332 // We use it to save R_G2 across calls out of Java.
 333 reg_class l7_regP(R_L7H,R_L7);
 334 
 335 // Other special pointer regs
 336 reg_class g1_regP(R_G1H,R_G1);
 337 reg_class g2_regP(R_G2H,R_G2);
 338 reg_class g3_regP(R_G3H,R_G3);
 339 reg_class g4_regP(R_G4H,R_G4);
 340 reg_class g5_regP(R_G5H,R_G5);
 341 reg_class i0_regP(R_I0H,R_I0);
 342 reg_class o0_regP(R_O0H,R_O0);
 343 reg_class o1_regP(R_O1H,R_O1);
 344 reg_class o2_regP(R_O2H,R_O2);
 345 reg_class o7_regP(R_O7H,R_O7);
 346 
 347 #else // _LP64
 348 // 32-bit build means 32-bit pointers means 1 register.
 349 reg_class ptr_reg(     R_G1,     R_G3,R_G4,R_G5,
 350                   R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
 351                   R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
 352                   R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
 353 // Lock encodings use G3 and G4 internally
 354 reg_class lock_ptr_reg(R_G1,               R_G5,
 355                   R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
 356                   R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
 357                   R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
 358 // Special class for storeP instructions, which can store SP or RPC to TLS.
 359 // It is also used for memory addressing, allowing direct TLS addressing.
 360 reg_class sp_ptr_reg(  R_G1,R_G2,R_G3,R_G4,R_G5,
 361                   R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP,
 362                   R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
 363                   R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP);
 364 // R_L7 is the lowest-priority callee-save (i.e., NS) register
 365 // We use it to save R_G2 across calls out of Java.
 366 reg_class l7_regP(R_L7);
 367 
 368 // Other special pointer regs
 369 reg_class g1_regP(R_G1);
 370 reg_class g2_regP(R_G2);
 371 reg_class g3_regP(R_G3);
 372 reg_class g4_regP(R_G4);
 373 reg_class g5_regP(R_G5);
 374 reg_class i0_regP(R_I0);
 375 reg_class o0_regP(R_O0);
 376 reg_class o1_regP(R_O1);
 377 reg_class o2_regP(R_O2);
 378 reg_class o7_regP(R_O7);
 379 #endif // _LP64
 380 
 381 
 382 // ----------------------------
 383 // Long Register Classes
 384 // ----------------------------
 385 // Longs in 1 register.  Aligned adjacent hi/lo pairs.
 386 // Note:  O7 is never in this class; it is sometimes used as an encoding temp.
 387 reg_class long_reg(             R_G1H,R_G1,             R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5
 388                    ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5
 389 #ifdef _LP64
 390 // 64-bit, longs in 1 register: use all 64-bit integer registers
 391 // 32-bit, longs in 1 register: cannot use I's and L's.  Restrict to O's and G's.
 392                    ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7
 393                    ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5
 394 #endif // _LP64
 395                   );
 396 
 397 reg_class g1_regL(R_G1H,R_G1);
 398 reg_class g3_regL(R_G3H,R_G3);
 399 reg_class o2_regL(R_O2H,R_O2);
 400 reg_class o7_regL(R_O7H,R_O7);
 401 
 402 // ----------------------------
 403 // Special Class for Condition Code Flags Register
 404 reg_class int_flags(CCR);
 405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3);
 406 reg_class float_flag0(FCC0);
 407 
 408 
 409 // ----------------------------
 410 // Float Point Register Classes
 411 // ----------------------------
 412 // Skip F30/F31, they are reserved for mem-mem copies
 413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
 414 
 415 // Paired floating point registers--they show up in the same order as the floats,
 416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
 417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
 418                    R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,
 419                    /* Use extra V9 double registers; this AD file does not support V8 */
 420                    R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
 421                    R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x
 422                    );
 423 
 424 // Paired floating point registers--they show up in the same order as the floats,
 425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
 426 // This class is usable for mis-aligned loads as happen in I2C adapters.
 427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
 428                    R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
 429 %}
 430 
 431 //----------DEFINITION BLOCK---------------------------------------------------
 432 // Define name --> value mappings to inform the ADLC of an integer valued name
 433 // Current support includes integer values in the range [0, 0x7FFFFFFF]
 434 // Format:
 435 //        int_def  <name>         ( <int_value>, <expression>);
 436 // Generated Code in ad_<arch>.hpp
 437 //        #define  <name>   (<expression>)
 438 //        // value == <int_value>
 439 // Generated code in ad_<arch>.cpp adlc_verification()
 440 //        assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
 441 //
 442 definitions %{
 443 // The default cost (of an ALU instruction).
 444   int_def DEFAULT_COST      (    100,     100);
 445   int_def HUGE_COST         (1000000, 1000000);
 446 
 447 // Memory refs are twice as expensive as run-of-the-mill.
 448   int_def MEMORY_REF_COST   (    200, DEFAULT_COST * 2);
 449 
 450 // Branches are even more expensive.
 451   int_def BRANCH_COST       (    300, DEFAULT_COST * 3);
 452   int_def CALL_COST         (    300, DEFAULT_COST * 3);
 453 %}
 454 
 455 
 456 //----------SOURCE BLOCK-------------------------------------------------------
 457 // This is a block of C++ code which provides values, functions, and
 458 // definitions necessary in the rest of the architecture description
 459 source_hpp %{
 460 // Header information of the source block.
 461 // Method declarations/definitions which are used outside
 462 // the ad-scope can conveniently be defined here.
 463 //
 464 // To keep related declarations/definitions/uses close together,
 465 // we switch between source %{ }% and source_hpp %{ }% freely as needed.
 466 
 467 // Must be visible to the DFA in dfa_sparc.cpp
 468 extern bool can_branch_register( Node *bol, Node *cmp );
 469 
 470 extern bool use_block_zeroing(Node* count);
 471 
 472 // Macros to extract hi & lo halves from a long pair.
 473 // G0 is not part of any long pair, so assert on that.
 474 // Prevents accidentally using G1 instead of G0.
 475 #define LONG_HI_REG(x) (x)
 476 #define LONG_LO_REG(x) (x)
 477 
 478 class CallStubImpl {
 479 
 480   //--------------------------------------------------------------
 481   //---<  Used for optimization in Compile::Shorten_branches  >---
 482   //--------------------------------------------------------------
 483 
 484  public:
 485   // Size of call trampoline stub.
 486   static uint size_call_trampoline() {
 487     return 0; // no call trampolines on this platform
 488   }
 489 
 490   // number of relocations needed by a call trampoline stub
 491   static uint reloc_call_trampoline() {
 492     return 0; // no call trampolines on this platform
 493   }
 494 };
 495 
 496 class HandlerImpl {
 497 
 498  public:
 499 
 500   static int emit_exception_handler(CodeBuffer &cbuf);
 501   static int emit_deopt_handler(CodeBuffer& cbuf);
 502 
 503   static uint size_exception_handler() {
 504     if (TraceJumps) {
 505       return (400); // just a guess
 506     }
 507     return ( NativeJump::instruction_size ); // sethi;jmp;nop
 508   }
 509 
 510   static uint size_deopt_handler() {
 511     if (TraceJumps) {
 512       return (400); // just a guess
 513     }
 514     return ( 4+  NativeJump::instruction_size ); // save;sethi;jmp;restore
 515   }
 516 };
 517 
 518 %}
 519 
 520 source %{
 521 #define __ _masm.
 522 
 523 // tertiary op of a LoadP or StoreP encoding
 524 #define REGP_OP true
 525 
 526 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding);
 527 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding);
 528 static Register reg_to_register_object(int register_encoding);
 529 
 530 // Used by the DFA in dfa_sparc.cpp.
 531 // Check for being able to use a V9 branch-on-register.  Requires a
 532 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign-
 533 // extended.  Doesn't work following an integer ADD, for example, because of
 534 // overflow (-1 incremented yields 0 plus a carry in the high-order word).  On
 535 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and
 536 // replace them with zero, which could become sign-extension in a different OS
 537 // release.  There's no obvious reason why an interrupt will ever fill these
 538 // bits with non-zero junk (the registers are reloaded with standard LD
 539 // instructions which either zero-fill or sign-fill).
 540 bool can_branch_register( Node *bol, Node *cmp ) {
 541   if( !BranchOnRegister ) return false;
 542 #ifdef _LP64
 543   if( cmp->Opcode() == Op_CmpP )
 544     return true;  // No problems with pointer compares
 545 #endif
 546   if( cmp->Opcode() == Op_CmpL )
 547     return true;  // No problems with long compares
 548 
 549   if( !SparcV9RegsHiBitsZero ) return false;
 550   if( bol->as_Bool()->_test._test != BoolTest::ne &&
 551       bol->as_Bool()->_test._test != BoolTest::eq )
 552      return false;
 553 
 554   // Check for comparing against a 'safe' value.  Any operation which
 555   // clears out the high word is safe.  Thus, loads and certain shifts
 556   // are safe, as are non-negative constants.  Any operation which
 557   // preserves zero bits in the high word is safe as long as each of its
 558   // inputs are safe.  Thus, phis and bitwise booleans are safe if their
 559   // inputs are safe.  At present, the only important case to recognize
 560   // seems to be loads.  Constants should fold away, and shifts &
 561   // logicals can use the 'cc' forms.
 562   Node *x = cmp->in(1);
 563   if( x->is_Load() ) return true;
 564   if( x->is_Phi() ) {
 565     for( uint i = 1; i < x->req(); i++ )
 566       if( !x->in(i)->is_Load() )
 567         return false;
 568     return true;
 569   }
 570   return false;
 571 }
 572 
 573 bool use_block_zeroing(Node* count) {
 574   // Use BIS for zeroing if count is not constant
 575   // or it is >= BlockZeroingLowLimit.
 576   return UseBlockZeroing && (count->find_intptr_t_con(BlockZeroingLowLimit) >= BlockZeroingLowLimit);
 577 }
 578 
 579 // ****************************************************************************
 580 
 581 // REQUIRED FUNCTIONALITY
 582 
 583 // !!!!! Special hack to get all type of calls to specify the byte offset
 584 //       from the start of the call to the point where the return address
 585 //       will point.
 586 //       The "return address" is the address of the call instruction, plus 8.
 587 
 588 int MachCallStaticJavaNode::ret_addr_offset() {
 589   int offset = NativeCall::instruction_size;  // call; delay slot
 590   if (_method_handle_invoke)
 591     offset += 4;  // restore SP
 592   return offset;
 593 }
 594 
 595 int MachCallDynamicJavaNode::ret_addr_offset() {
 596   int vtable_index = this->_vtable_index;
 597   if (vtable_index < 0) {
 598     // must be invalid_vtable_index, not nonvirtual_vtable_index
 599     assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
 600     return (NativeMovConstReg::instruction_size +
 601            NativeCall::instruction_size);  // sethi; setlo; call; delay slot
 602   } else {
 603     assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
 604     int entry_offset = InstanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
 605     int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
 606     int klass_load_size;
 607     if (UseCompressedClassPointers) {
 608       assert(Universe::heap() != NULL, "java heap should be initialized");
 609       klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord;
 610     } else {
 611       klass_load_size = 1*BytesPerInstWord;
 612     }
 613     if (Assembler::is_simm13(v_off)) {
 614       return klass_load_size +
 615              (2*BytesPerInstWord +           // ld_ptr, ld_ptr
 616              NativeCall::instruction_size);  // call; delay slot
 617     } else {
 618       return klass_load_size +
 619              (4*BytesPerInstWord +           // set_hi, set, ld_ptr, ld_ptr
 620              NativeCall::instruction_size);  // call; delay slot
 621     }
 622   }
 623 }
 624 
 625 int MachCallRuntimeNode::ret_addr_offset() {
 626 #ifdef _LP64
 627   if (MacroAssembler::is_far_target(entry_point())) {
 628     return NativeFarCall::instruction_size;
 629   } else {
 630     return NativeCall::instruction_size;
 631   }
 632 #else
 633   return NativeCall::instruction_size;  // call; delay slot
 634 #endif
 635 }
 636 
 637 // Indicate if the safepoint node needs the polling page as an input.
 638 // Since Sparc does not have absolute addressing, it does.
 639 bool SafePointNode::needs_polling_address_input() {
 640   return true;
 641 }
 642 
 643 // emit an interrupt that is caught by the debugger (for debugging compiler)
 644 void emit_break(CodeBuffer &cbuf) {
 645   MacroAssembler _masm(&cbuf);
 646   __ breakpoint_trap();
 647 }
 648 
 649 #ifndef PRODUCT
 650 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const {
 651   st->print("TA");
 652 }
 653 #endif
 654 
 655 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
 656   emit_break(cbuf);
 657 }
 658 
 659 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
 660   return MachNode::size(ra_);
 661 }
 662 
 663 // Traceable jump
 664 void  emit_jmpl(CodeBuffer &cbuf, int jump_target) {
 665   MacroAssembler _masm(&cbuf);
 666   Register rdest = reg_to_register_object(jump_target);
 667   __ JMP(rdest, 0);
 668   __ delayed()->nop();
 669 }
 670 
 671 // Traceable jump and set exception pc
 672 void  emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) {
 673   MacroAssembler _masm(&cbuf);
 674   Register rdest = reg_to_register_object(jump_target);
 675   __ JMP(rdest, 0);
 676   __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc );
 677 }
 678 
 679 void emit_nop(CodeBuffer &cbuf) {
 680   MacroAssembler _masm(&cbuf);
 681   __ nop();
 682 }
 683 
 684 void emit_illtrap(CodeBuffer &cbuf) {
 685   MacroAssembler _masm(&cbuf);
 686   __ illtrap(0);
 687 }
 688 
 689 
 690 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) {
 691   assert(n->rule() != loadUB_rule, "");
 692 
 693   intptr_t offset = 0;
 694   const TypePtr *adr_type = TYPE_PTR_SENTINAL;  // Check for base==RegI, disp==immP
 695   const Node* addr = n->get_base_and_disp(offset, adr_type);
 696   assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP");
 697   assert(addr != NULL && addr != (Node*)-1, "invalid addr");
 698   assert(addr->bottom_type()->isa_oopptr() == atype, "");
 699   atype = atype->add_offset(offset);
 700   assert(disp32 == offset, "wrong disp32");
 701   return atype->_offset;
 702 }
 703 
 704 
 705 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) {
 706   assert(n->rule() != loadUB_rule, "");
 707 
 708   intptr_t offset = 0;
 709   Node* addr = n->in(2);
 710   assert(addr->bottom_type()->isa_oopptr() == atype, "");
 711   if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) {
 712     Node* a = addr->in(2/*AddPNode::Address*/);
 713     Node* o = addr->in(3/*AddPNode::Offset*/);
 714     offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot;
 715     atype = a->bottom_type()->is_ptr()->add_offset(offset);
 716     assert(atype->isa_oop_ptr(), "still an oop");
 717   }
 718   offset = atype->is_ptr()->_offset;
 719   if (offset != Type::OffsetBot)  offset += disp32;
 720   return offset;
 721 }
 722 
 723 static inline jdouble replicate_immI(int con, int count, int width) {
 724   // Load a constant replicated "count" times with width "width"
 725   assert(count*width == 8 && width <= 4, "sanity");
 726   int bit_width = width * 8;
 727   jlong val = con;
 728   val &= (((jlong) 1) << bit_width) - 1;  // mask off sign bits
 729   for (int i = 0; i < count - 1; i++) {
 730     val |= (val << bit_width);
 731   }
 732   jdouble dval = *((jdouble*) &val);  // coerce to double type
 733   return dval;
 734 }
 735 
 736 static inline jdouble replicate_immF(float con) {
 737   // Replicate float con 2 times and pack into vector.
 738   int val = *((int*)&con);
 739   jlong lval = val;
 740   lval = (lval << 32) | (lval & 0xFFFFFFFFl);
 741   jdouble dval = *((jdouble*) &lval);  // coerce to double type
 742   return dval;
 743 }
 744 
 745 // Standard Sparc opcode form2 field breakdown
 746 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) {
 747   f0 &= (1<<19)-1;     // Mask displacement to 19 bits
 748   int op = (f30 << 30) |
 749            (f29 << 29) |
 750            (f25 << 25) |
 751            (f22 << 22) |
 752            (f20 << 20) |
 753            (f19 << 19) |
 754            (f0  <<  0);
 755   cbuf.insts()->emit_int32(op);
 756 }
 757 
 758 // Standard Sparc opcode form2 field breakdown
 759 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) {
 760   f0 >>= 10;           // Drop 10 bits
 761   f0 &= (1<<22)-1;     // Mask displacement to 22 bits
 762   int op = (f30 << 30) |
 763            (f25 << 25) |
 764            (f22 << 22) |
 765            (f0  <<  0);
 766   cbuf.insts()->emit_int32(op);
 767 }
 768 
 769 // Standard Sparc opcode form3 field breakdown
 770 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) {
 771   int op = (f30 << 30) |
 772            (f25 << 25) |
 773            (f19 << 19) |
 774            (f14 << 14) |
 775            (f5  <<  5) |
 776            (f0  <<  0);
 777   cbuf.insts()->emit_int32(op);
 778 }
 779 
 780 // Standard Sparc opcode form3 field breakdown
 781 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) {
 782   simm13 &= (1<<13)-1; // Mask to 13 bits
 783   int op = (f30 << 30) |
 784            (f25 << 25) |
 785            (f19 << 19) |
 786            (f14 << 14) |
 787            (1   << 13) | // bit to indicate immediate-mode
 788            (simm13<<0);
 789   cbuf.insts()->emit_int32(op);
 790 }
 791 
 792 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) {
 793   simm10 &= (1<<10)-1; // Mask to 10 bits
 794   emit3_simm13(cbuf,f30,f25,f19,f14,simm10);
 795 }
 796 
 797 #ifdef ASSERT
 798 // Helper function for VerifyOops in emit_form3_mem_reg
 799 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) {
 800   warning("VerifyOops encountered unexpected instruction:");
 801   n->dump(2);
 802   warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]);
 803 }
 804 #endif
 805 
 806 
 807 void emit_form3_mem_reg(CodeBuffer &cbuf, PhaseRegAlloc* ra, const MachNode* n, int primary, int tertiary,
 808                         int src1_enc, int disp32, int src2_enc, int dst_enc) {
 809 
 810 #ifdef ASSERT
 811   // The following code implements the +VerifyOops feature.
 812   // It verifies oop values which are loaded into or stored out of
 813   // the current method activation.  +VerifyOops complements techniques
 814   // like ScavengeALot, because it eagerly inspects oops in transit,
 815   // as they enter or leave the stack, as opposed to ScavengeALot,
 816   // which inspects oops "at rest", in the stack or heap, at safepoints.
 817   // For this reason, +VerifyOops can sometimes detect bugs very close
 818   // to their point of creation.  It can also serve as a cross-check
 819   // on the validity of oop maps, when used toegether with ScavengeALot.
 820 
 821   // It would be good to verify oops at other points, especially
 822   // when an oop is used as a base pointer for a load or store.
 823   // This is presently difficult, because it is hard to know when
 824   // a base address is biased or not.  (If we had such information,
 825   // it would be easy and useful to make a two-argument version of
 826   // verify_oop which unbiases the base, and performs verification.)
 827 
 828   assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary");
 829   bool is_verified_oop_base  = false;
 830   bool is_verified_oop_load  = false;
 831   bool is_verified_oop_store = false;
 832   int tmp_enc = -1;
 833   if (VerifyOops && src1_enc != R_SP_enc) {
 834     // classify the op, mainly for an assert check
 835     int st_op = 0, ld_op = 0;
 836     switch (primary) {
 837     case Assembler::stb_op3:  st_op = Op_StoreB; break;
 838     case Assembler::sth_op3:  st_op = Op_StoreC; break;
 839     case Assembler::stx_op3:  // may become StoreP or stay StoreI or StoreD0
 840     case Assembler::stw_op3:  st_op = Op_StoreI; break;
 841     case Assembler::std_op3:  st_op = Op_StoreL; break;
 842     case Assembler::stf_op3:  st_op = Op_StoreF; break;
 843     case Assembler::stdf_op3: st_op = Op_StoreD; break;
 844 
 845     case Assembler::ldsb_op3: ld_op = Op_LoadB; break;
 846     case Assembler::ldub_op3: ld_op = Op_LoadUB; break;
 847     case Assembler::lduh_op3: ld_op = Op_LoadUS; break;
 848     case Assembler::ldsh_op3: ld_op = Op_LoadS; break;
 849     case Assembler::ldx_op3:  // may become LoadP or stay LoadI
 850     case Assembler::ldsw_op3: // may become LoadP or stay LoadI
 851     case Assembler::lduw_op3: ld_op = Op_LoadI; break;
 852     case Assembler::ldd_op3:  ld_op = Op_LoadL; break;
 853     case Assembler::ldf_op3:  ld_op = Op_LoadF; break;
 854     case Assembler::lddf_op3: ld_op = Op_LoadD; break;
 855     case Assembler::prefetch_op3: ld_op = Op_LoadI; break;
 856 
 857     default: ShouldNotReachHere();
 858     }
 859     if (tertiary == REGP_OP) {
 860       if      (st_op == Op_StoreI)  st_op = Op_StoreP;
 861       else if (ld_op == Op_LoadI)   ld_op = Op_LoadP;
 862       else                          ShouldNotReachHere();
 863       if (st_op) {
 864         // a store
 865         // inputs are (0:control, 1:memory, 2:address, 3:value)
 866         Node* n2 = n->in(3);
 867         if (n2 != NULL) {
 868           const Type* t = n2->bottom_type();
 869           is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
 870         }
 871       } else {
 872         // a load
 873         const Type* t = n->bottom_type();
 874         is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
 875       }
 876     }
 877 
 878     if (ld_op) {
 879       // a Load
 880       // inputs are (0:control, 1:memory, 2:address)
 881       if (!(n->ideal_Opcode()==ld_op)       && // Following are special cases
 882           !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) &&
 883           !(n->ideal_Opcode()==Op_LoadI     && ld_op==Op_LoadF) &&
 884           !(n->ideal_Opcode()==Op_LoadF     && ld_op==Op_LoadI) &&
 885           !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) &&
 886           !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) &&
 887           !(n->ideal_Opcode()==Op_LoadL     && ld_op==Op_LoadI) &&
 888           !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) &&
 889           !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) &&
 890           !(n->ideal_Opcode()==Op_ConvI2F   && ld_op==Op_LoadF) &&
 891           !(n->ideal_Opcode()==Op_ConvI2D   && ld_op==Op_LoadF) &&
 892           !(n->ideal_Opcode()==Op_PrefetchRead  && ld_op==Op_LoadI) &&
 893           !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) &&
 894           !(n->ideal_Opcode()==Op_PrefetchAllocation && ld_op==Op_LoadI) &&
 895           !(n->ideal_Opcode()==Op_LoadVector && ld_op==Op_LoadD) &&
 896           !(n->rule() == loadUB_rule)) {
 897         verify_oops_warning(n, n->ideal_Opcode(), ld_op);
 898       }
 899     } else if (st_op) {
 900       // a Store
 901       // inputs are (0:control, 1:memory, 2:address, 3:value)
 902       if (!(n->ideal_Opcode()==st_op)    && // Following are special cases
 903           !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) &&
 904           !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) &&
 905           !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) &&
 906           !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) &&
 907           !(n->ideal_Opcode()==Op_StoreVector && st_op==Op_StoreD) &&
 908           !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) {
 909         verify_oops_warning(n, n->ideal_Opcode(), st_op);
 910       }
 911     }
 912 
 913     if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) {
 914       Node* addr = n->in(2);
 915       if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) {
 916         const TypeOopPtr* atype = addr->bottom_type()->isa_instptr();  // %%% oopptr?
 917         if (atype != NULL) {
 918           intptr_t offset = get_offset_from_base(n, atype, disp32);
 919           intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32);
 920           if (offset != offset_2) {
 921             get_offset_from_base(n, atype, disp32);
 922             get_offset_from_base_2(n, atype, disp32);
 923           }
 924           assert(offset == offset_2, "different offsets");
 925           if (offset == disp32) {
 926             // we now know that src1 is a true oop pointer
 927             is_verified_oop_base = true;
 928             if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) {
 929               if( primary == Assembler::ldd_op3 ) {
 930                 is_verified_oop_base = false; // Cannot 'ldd' into O7
 931               } else {
 932                 tmp_enc = dst_enc;
 933                 dst_enc = R_O7_enc; // Load into O7; preserve source oop
 934                 assert(src1_enc != dst_enc, "");
 935               }
 936             }
 937           }
 938           if (st_op && (( offset == oopDesc::klass_offset_in_bytes())
 939                        || offset == oopDesc::mark_offset_in_bytes())) {
 940                       // loading the mark should not be allowed either, but
 941                       // we don't check this since it conflicts with InlineObjectHash
 942                       // usage of LoadINode to get the mark. We could keep the
 943                       // check if we create a new LoadMarkNode
 944             // but do not verify the object before its header is initialized
 945             ShouldNotReachHere();
 946           }
 947         }
 948       }
 949     }
 950   }
 951 #endif
 952 
 953   uint instr;
 954   instr = (Assembler::ldst_op << 30)
 955         | (dst_enc        << 25)
 956         | (primary        << 19)
 957         | (src1_enc       << 14);
 958 
 959   uint index = src2_enc;
 960   int disp = disp32;
 961 
 962   if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) {
 963     disp += STACK_BIAS;
 964     // Quick fix for JDK-8029668: check that stack offset fits, bailout if not
 965     if (!Assembler::is_simm13(disp)) {
 966       ra->C->record_method_not_compilable("unable to handle large constant offsets");
 967       return;
 968     }
 969   }
 970 
 971   // We should have a compiler bailout here rather than a guarantee.
 972   // Better yet would be some mechanism to handle variable-size matches correctly.
 973   guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" );
 974 
 975   if( disp == 0 ) {
 976     // use reg-reg form
 977     // bit 13 is already zero
 978     instr |= index;
 979   } else {
 980     // use reg-imm form
 981     instr |= 0x00002000;          // set bit 13 to one
 982     instr |= disp & 0x1FFF;
 983   }
 984 
 985   cbuf.insts()->emit_int32(instr);
 986 
 987 #ifdef ASSERT
 988   {
 989     MacroAssembler _masm(&cbuf);
 990     if (is_verified_oop_base) {
 991       __ verify_oop(reg_to_register_object(src1_enc));
 992     }
 993     if (is_verified_oop_store) {
 994       __ verify_oop(reg_to_register_object(dst_enc));
 995     }
 996     if (tmp_enc != -1) {
 997       __ mov(O7, reg_to_register_object(tmp_enc));
 998     }
 999     if (is_verified_oop_load) {
1000       __ verify_oop(reg_to_register_object(dst_enc));
1001     }
1002   }
1003 #endif
1004 }
1005 
1006 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false) {
1007   // The method which records debug information at every safepoint
1008   // expects the call to be the first instruction in the snippet as
1009   // it creates a PcDesc structure which tracks the offset of a call
1010   // from the start of the codeBlob. This offset is computed as
1011   // code_end() - code_begin() of the code which has been emitted
1012   // so far.
1013   // In this particular case we have skirted around the problem by
1014   // putting the "mov" instruction in the delay slot but the problem
1015   // may bite us again at some other point and a cleaner/generic
1016   // solution using relocations would be needed.
1017   MacroAssembler _masm(&cbuf);
1018   __ set_inst_mark();
1019 
1020   // We flush the current window just so that there is a valid stack copy
1021   // the fact that the current window becomes active again instantly is
1022   // not a problem there is nothing live in it.
1023 
1024 #ifdef ASSERT
1025   int startpos = __ offset();
1026 #endif /* ASSERT */
1027 
1028   __ call((address)entry_point, rtype);
1029 
1030   if (preserve_g2)   __ delayed()->mov(G2, L7);
1031   else __ delayed()->nop();
1032 
1033   if (preserve_g2)   __ mov(L7, G2);
1034 
1035 #ifdef ASSERT
1036   if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) {
1037 #ifdef _LP64
1038     // Trash argument dump slots.
1039     __ set(0xb0b8ac0db0b8ac0d, G1);
1040     __ mov(G1, G5);
1041     __ stx(G1, SP, STACK_BIAS + 0x80);
1042     __ stx(G1, SP, STACK_BIAS + 0x88);
1043     __ stx(G1, SP, STACK_BIAS + 0x90);
1044     __ stx(G1, SP, STACK_BIAS + 0x98);
1045     __ stx(G1, SP, STACK_BIAS + 0xA0);
1046     __ stx(G1, SP, STACK_BIAS + 0xA8);
1047 #else // _LP64
1048     // this is also a native call, so smash the first 7 stack locations,
1049     // and the various registers
1050 
1051     // Note:  [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset],
1052     // while [SP+0x44..0x58] are the argument dump slots.
1053     __ set((intptr_t)0xbaadf00d, G1);
1054     __ mov(G1, G5);
1055     __ sllx(G1, 32, G1);
1056     __ or3(G1, G5, G1);
1057     __ mov(G1, G5);
1058     __ stx(G1, SP, 0x40);
1059     __ stx(G1, SP, 0x48);
1060     __ stx(G1, SP, 0x50);
1061     __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot
1062 #endif // _LP64
1063   }
1064 #endif /*ASSERT*/
1065 }
1066 
1067 //=============================================================================
1068 // REQUIRED FUNCTIONALITY for encoding
1069 void emit_lo(CodeBuffer &cbuf, int val) {  }
1070 void emit_hi(CodeBuffer &cbuf, int val) {  }
1071 
1072 
1073 //=============================================================================
1074 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask();
1075 
1076 int Compile::ConstantTable::calculate_table_base_offset() const {
1077   if (UseRDPCForConstantTableBase) {
1078     // The table base offset might be less but then it fits into
1079     // simm13 anyway and we are good (cf. MachConstantBaseNode::emit).
1080     return Assembler::min_simm13();
1081   } else {
1082     int offset = -(size() / 2);
1083     if (!Assembler::is_simm13(offset)) {
1084       offset = Assembler::min_simm13();
1085     }
1086     return offset;
1087   }
1088 }
1089 
1090 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
1091 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1092   ShouldNotReachHere();
1093 }
1094 
1095 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1096   Compile* C = ra_->C;
1097   Compile::ConstantTable& constant_table = C->constant_table();
1098   MacroAssembler _masm(&cbuf);
1099 
1100   Register r = as_Register(ra_->get_encode(this));
1101   CodeSection* consts_section = __ code()->consts();
1102   int consts_size = consts_section->align_at_start(consts_section->size());
1103   assert(constant_table.size() == consts_size, err_msg("must be: %d == %d", constant_table.size(), consts_size));
1104 
1105   if (UseRDPCForConstantTableBase) {
1106     // For the following RDPC logic to work correctly the consts
1107     // section must be allocated right before the insts section.  This
1108     // assert checks for that.  The layout and the SECT_* constants
1109     // are defined in src/share/vm/asm/codeBuffer.hpp.
1110     assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be");
1111     int insts_offset = __ offset();
1112 
1113     // Layout:
1114     //
1115     // |----------- consts section ------------|----------- insts section -----------...
1116     // |------ constant table -----|- padding -|------------------x----
1117     //                                                            \ current PC (RDPC instruction)
1118     // |<------------- consts_size ----------->|<- insts_offset ->|
1119     //                                                            \ table base
1120     // The table base offset is later added to the load displacement
1121     // so it has to be negative.
1122     int table_base_offset = -(consts_size + insts_offset);
1123     int disp;
1124 
1125     // If the displacement from the current PC to the constant table
1126     // base fits into simm13 we set the constant table base to the
1127     // current PC.
1128     if (Assembler::is_simm13(table_base_offset)) {
1129       constant_table.set_table_base_offset(table_base_offset);
1130       disp = 0;
1131     } else {
1132       // Otherwise we set the constant table base offset to the
1133       // maximum negative displacement of load instructions to keep
1134       // the disp as small as possible:
1135       //
1136       // |<------------- consts_size ----------->|<- insts_offset ->|
1137       // |<--------- min_simm13 --------->|<-------- disp --------->|
1138       //                                  \ table base
1139       table_base_offset = Assembler::min_simm13();
1140       constant_table.set_table_base_offset(table_base_offset);
1141       disp = (consts_size + insts_offset) + table_base_offset;
1142     }
1143 
1144     __ rdpc(r);
1145 
1146     if (disp != 0) {
1147       assert(r != O7, "need temporary");
1148       __ sub(r, __ ensure_simm13_or_reg(disp, O7), r);
1149     }
1150   }
1151   else {
1152     // Materialize the constant table base.
1153     address baseaddr = consts_section->start() + -(constant_table.table_base_offset());
1154     RelocationHolder rspec = internal_word_Relocation::spec(baseaddr);
1155     AddressLiteral base(baseaddr, rspec);
1156     __ set(base, r);
1157   }
1158 }
1159 
1160 uint MachConstantBaseNode::size(PhaseRegAlloc*) const {
1161   if (UseRDPCForConstantTableBase) {
1162     // This is really the worst case but generally it's only 1 instruction.
1163     return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord;
1164   } else {
1165     return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord;
1166   }
1167 }
1168 
1169 #ifndef PRODUCT
1170 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1171   char reg[128];
1172   ra_->dump_register(this, reg);
1173   if (UseRDPCForConstantTableBase) {
1174     st->print("RDPC   %s\t! constant table base", reg);
1175   } else {
1176     st->print("SET    &constanttable,%s\t! constant table base", reg);
1177   }
1178 }
1179 #endif
1180 
1181 
1182 //=============================================================================
1183 
1184 #ifndef PRODUCT
1185 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1186   Compile* C = ra_->C;
1187 
1188   for (int i = 0; i < OptoPrologueNops; i++) {
1189     st->print_cr("NOP"); st->print("\t");
1190   }
1191 
1192   if( VerifyThread ) {
1193     st->print_cr("Verify_Thread"); st->print("\t");
1194   }
1195 
1196   size_t framesize = C->frame_size_in_bytes();
1197   int bangsize = C->bang_size_in_bytes();
1198 
1199   // Calls to C2R adapters often do not accept exceptional returns.
1200   // We require that their callers must bang for them.  But be careful, because
1201   // some VM calls (such as call site linkage) can use several kilobytes of
1202   // stack.  But the stack safety zone should account for that.
1203   // See bugs 4446381, 4468289, 4497237.
1204   if (C->need_stack_bang(bangsize)) {
1205     st->print_cr("! stack bang (%d bytes)", bangsize); st->print("\t");
1206   }
1207 
1208   if (Assembler::is_simm13(-framesize)) {
1209     st->print   ("SAVE   R_SP,-%d,R_SP",framesize);
1210   } else {
1211     st->print_cr("SETHI  R_SP,hi%%(-%d),R_G3",framesize); st->print("\t");
1212     st->print_cr("ADD    R_G3,lo%%(-%d),R_G3",framesize); st->print("\t");
1213     st->print   ("SAVE   R_SP,R_G3,R_SP");
1214   }
1215 
1216 }
1217 #endif
1218 
1219 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1220   Compile* C = ra_->C;
1221   MacroAssembler _masm(&cbuf);
1222 
1223   for (int i = 0; i < OptoPrologueNops; i++) {
1224     __ nop();
1225   }
1226 
1227   __ verify_thread();
1228 
1229   size_t framesize = C->frame_size_in_bytes();
1230   assert(framesize >= 16*wordSize, "must have room for reg. save area");
1231   assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
1232   int bangsize = C->bang_size_in_bytes();
1233 
1234   // Calls to C2R adapters often do not accept exceptional returns.
1235   // We require that their callers must bang for them.  But be careful, because
1236   // some VM calls (such as call site linkage) can use several kilobytes of
1237   // stack.  But the stack safety zone should account for that.
1238   // See bugs 4446381, 4468289, 4497237.
1239   if (C->need_stack_bang(bangsize)) {
1240     __ generate_stack_overflow_check(bangsize);
1241   }
1242 
1243   if (Assembler::is_simm13(-framesize)) {
1244     __ save(SP, -framesize, SP);
1245   } else {
1246     __ sethi(-framesize & ~0x3ff, G3);
1247     __ add(G3, -framesize & 0x3ff, G3);
1248     __ save(SP, G3, SP);
1249   }
1250   C->set_frame_complete( __ offset() );
1251 
1252   if (!UseRDPCForConstantTableBase && C->has_mach_constant_base_node()) {
1253     // NOTE: We set the table base offset here because users might be
1254     // emitted before MachConstantBaseNode.
1255     Compile::ConstantTable& constant_table = C->constant_table();
1256     constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
1257   }
1258 }
1259 
1260 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1261   return MachNode::size(ra_);
1262 }
1263 
1264 int MachPrologNode::reloc() const {
1265   return 10; // a large enough number
1266 }
1267 
1268 //=============================================================================
1269 #ifndef PRODUCT
1270 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1271   Compile* C = ra_->C;
1272 
1273   if(do_polling() && ra_->C->is_method_compilation()) {
1274     st->print("SETHI  #PollAddr,L0\t! Load Polling address\n\t");
1275 #ifdef _LP64
1276     st->print("LDX    [L0],G0\t!Poll for Safepointing\n\t");
1277 #else
1278     st->print("LDUW   [L0],G0\t!Poll for Safepointing\n\t");
1279 #endif
1280   }
1281 
1282   if(do_polling()) {
1283     if (UseCBCond && !ra_->C->is_method_compilation()) {
1284       st->print("NOP\n\t");
1285     }
1286     st->print("RET\n\t");
1287   }
1288 
1289   st->print("RESTORE");
1290 }
1291 #endif
1292 
1293 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1294   MacroAssembler _masm(&cbuf);
1295   Compile* C = ra_->C;
1296 
1297   __ verify_thread();
1298 
1299   // If this does safepoint polling, then do it here
1300   if(do_polling() && ra_->C->is_method_compilation()) {
1301     AddressLiteral polling_page(os::get_polling_page());
1302     __ sethi(polling_page, L0);
1303     __ relocate(relocInfo::poll_return_type);
1304     __ ld_ptr(L0, 0, G0);
1305   }
1306 
1307   // If this is a return, then stuff the restore in the delay slot
1308   if(do_polling()) {
1309     if (UseCBCond && !ra_->C->is_method_compilation()) {
1310       // Insert extra padding for the case when the epilogue is preceded by
1311       // a cbcond jump, which can't be followed by a CTI instruction
1312       __ nop();
1313     }
1314     __ ret();
1315     __ delayed()->restore();
1316   } else {
1317     __ restore();
1318   }
1319 }
1320 
1321 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1322   return MachNode::size(ra_);
1323 }
1324 
1325 int MachEpilogNode::reloc() const {
1326   return 16; // a large enough number
1327 }
1328 
1329 const Pipeline * MachEpilogNode::pipeline() const {
1330   return MachNode::pipeline_class();
1331 }
1332 
1333 int MachEpilogNode::safepoint_offset() const {
1334   assert( do_polling(), "no return for this epilog node");
1335   return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord;
1336 }
1337 
1338 //=============================================================================
1339 
1340 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack
1341 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1342 static enum RC rc_class( OptoReg::Name reg ) {
1343   if( !OptoReg::is_valid(reg)  ) return rc_bad;
1344   if (OptoReg::is_stack(reg)) return rc_stack;
1345   VMReg r = OptoReg::as_VMReg(reg);
1346   if (r->is_Register()) return rc_int;
1347   assert(r->is_FloatRegister(), "must be");
1348   return rc_float;
1349 }
1350 
1351 static int impl_helper(const MachNode* mach, CodeBuffer* cbuf, PhaseRegAlloc* ra, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) {
1352   if (cbuf) {
1353     emit_form3_mem_reg(*cbuf, ra, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
1354   }
1355 #ifndef PRODUCT
1356   else if (!do_size) {
1357     if (size != 0) st->print("\n\t");
1358     if (is_load) st->print("%s   [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg));
1359     else         st->print("%s   R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset);
1360   }
1361 #endif
1362   return size+4;
1363 }
1364 
1365 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) {
1366   if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] );
1367 #ifndef PRODUCT
1368   else if( !do_size ) {
1369     if( size != 0 ) st->print("\n\t");
1370     st->print("%s  R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst));
1371   }
1372 #endif
1373   return size+4;
1374 }
1375 
1376 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf,
1377                                         PhaseRegAlloc *ra_,
1378                                         bool do_size,
1379                                         outputStream* st ) const {
1380   // Get registers to move
1381   OptoReg::Name src_second = ra_->get_reg_second(in(1));
1382   OptoReg::Name src_first = ra_->get_reg_first(in(1));
1383   OptoReg::Name dst_second = ra_->get_reg_second(this );
1384   OptoReg::Name dst_first = ra_->get_reg_first(this );
1385 
1386   enum RC src_second_rc = rc_class(src_second);
1387   enum RC src_first_rc = rc_class(src_first);
1388   enum RC dst_second_rc = rc_class(dst_second);
1389   enum RC dst_first_rc = rc_class(dst_first);
1390 
1391   assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
1392 
1393   // Generate spill code!
1394   int size = 0;
1395 
1396   if( src_first == dst_first && src_second == dst_second )
1397     return size;            // Self copy, no move
1398 
1399   // --------------------------------------
1400   // Check for mem-mem move.  Load into unused float registers and fall into
1401   // the float-store case.
1402   if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1403     int offset = ra_->reg2offset(src_first);
1404     // Further check for aligned-adjacent pair, so we can use a double load
1405     if( (src_first&1)==0 && src_first+1 == src_second ) {
1406       src_second    = OptoReg::Name(R_F31_num);
1407       src_second_rc = rc_float;
1408       size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st);
1409     } else {
1410       size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st);
1411     }
1412     src_first    = OptoReg::Name(R_F30_num);
1413     src_first_rc = rc_float;
1414   }
1415 
1416   if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) {
1417     int offset = ra_->reg2offset(src_second);
1418     size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st);
1419     src_second    = OptoReg::Name(R_F31_num);
1420     src_second_rc = rc_float;
1421   }
1422 
1423   // --------------------------------------
1424   // Check for float->int copy; requires a trip through memory
1425   if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) {
1426     int offset = frame::register_save_words*wordSize;
1427     if (cbuf) {
1428       emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 );
1429       impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1430       impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1431       emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 );
1432     }
1433 #ifndef PRODUCT
1434     else if (!do_size) {
1435       if (size != 0) st->print("\n\t");
1436       st->print(  "SUB    R_SP,16,R_SP\n");
1437       impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1438       impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1439       st->print("\tADD    R_SP,16,R_SP\n");
1440     }
1441 #endif
1442     size += 16;
1443   }
1444 
1445   // Check for float->int copy on T4
1446   if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) {
1447     // Further check for aligned-adjacent pair, so we can use a double move
1448     if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)
1449       return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mdtox_opf,"MOVDTOX",size, st);
1450     size  =  impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mstouw_opf,"MOVSTOUW",size, st);
1451   }
1452   // Check for int->float copy on T4
1453   if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) {
1454     // Further check for aligned-adjacent pair, so we can use a double move
1455     if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)
1456       return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mxtod_opf,"MOVXTOD",size, st);
1457     size  =  impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mwtos_opf,"MOVWTOS",size, st);
1458   }
1459 
1460   // --------------------------------------
1461   // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations.
1462   // In such cases, I have to do the big-endian swap.  For aligned targets, the
1463   // hardware does the flop for me.  Doubles are always aligned, so no problem
1464   // there.  Misaligned sources only come from native-long-returns (handled
1465   // special below).
1466 #ifndef _LP64
1467   if( src_first_rc == rc_int &&     // source is already big-endian
1468       src_second_rc != rc_bad &&    // 64-bit move
1469       ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst
1470     assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" );
1471     // Do the big-endian flop.
1472     OptoReg::Name tmp    = dst_first   ; dst_first    = dst_second   ; dst_second    = tmp   ;
1473     enum RC       tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc;
1474   }
1475 #endif
1476 
1477   // --------------------------------------
1478   // Check for integer reg-reg copy
1479   if( src_first_rc == rc_int && dst_first_rc == rc_int ) {
1480 #ifndef _LP64
1481     if( src_first == R_O0_num && src_second == R_O1_num ) {  // Check for the evil O0/O1 native long-return case
1482       // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1483       //       as stored in memory.  On a big-endian machine like SPARC, this means that the _second
1484       //       operand contains the least significant word of the 64-bit value and vice versa.
1485       OptoReg::Name tmp = OptoReg::Name(R_O7_num);
1486       assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" );
1487       // Shift O0 left in-place, zero-extend O1, then OR them into the dst
1488       if( cbuf ) {
1489         emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 );
1490         emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 );
1491         emit3       ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] );
1492 #ifndef PRODUCT
1493       } else if( !do_size ) {
1494         if( size != 0 ) st->print("\n\t");
1495         st->print("SLLX   R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp));
1496         st->print("SRL    R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second));
1497         st->print("OR     R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first));
1498 #endif
1499       }
1500       return size+12;
1501     }
1502     else if( dst_first == R_I0_num && dst_second == R_I1_num ) {
1503       // returning a long value in I0/I1
1504       // a SpillCopy must be able to target a return instruction's reg_class
1505       // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1506       //       as stored in memory.  On a big-endian machine like SPARC, this means that the _second
1507       //       operand contains the least significant word of the 64-bit value and vice versa.
1508       OptoReg::Name tdest = dst_first;
1509 
1510       if (src_first == dst_first) {
1511         tdest = OptoReg::Name(R_O7_num);
1512         size += 4;
1513       }
1514 
1515       if( cbuf ) {
1516         assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg");
1517         // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1
1518         // ShrL_reg_imm6
1519         emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 );
1520         // ShrR_reg_imm6  src, 0, dst
1521         emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 );
1522         if (tdest != dst_first) {
1523           emit3     ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] );
1524         }
1525       }
1526 #ifndef PRODUCT
1527       else if( !do_size ) {
1528         if( size != 0 ) st->print("\n\t");  // %%%%% !!!!!
1529         st->print("SRLX   R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest));
1530         st->print("SRL    R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second));
1531         if (tdest != dst_first) {
1532           st->print("MOV    R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first));
1533         }
1534       }
1535 #endif // PRODUCT
1536       return size+8;
1537     }
1538 #endif // !_LP64
1539     // Else normal reg-reg copy
1540     assert( src_second != dst_first, "smashed second before evacuating it" );
1541     size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV  ",size, st);
1542     assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" );
1543     // This moves an aligned adjacent pair.
1544     // See if we are done.
1545     if( src_first+1 == src_second && dst_first+1 == dst_second )
1546       return size;
1547   }
1548 
1549   // Check for integer store
1550   if( src_first_rc == rc_int && dst_first_rc == rc_stack ) {
1551     int offset = ra_->reg2offset(dst_first);
1552     // Further check for aligned-adjacent pair, so we can use a double store
1553     if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1554       return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st);
1555     size  =  impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st);
1556   }
1557 
1558   // Check for integer load
1559   if( dst_first_rc == rc_int && src_first_rc == rc_stack ) {
1560     int offset = ra_->reg2offset(src_first);
1561     // Further check for aligned-adjacent pair, so we can use a double load
1562     if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1563       return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st);
1564     size  =  impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1565   }
1566 
1567   // Check for float reg-reg copy
1568   if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1569     // Further check for aligned-adjacent pair, so we can use a double move
1570     if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1571       return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st);
1572     size  =  impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st);
1573   }
1574 
1575   // Check for float store
1576   if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1577     int offset = ra_->reg2offset(dst_first);
1578     // Further check for aligned-adjacent pair, so we can use a double store
1579     if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1580       return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st);
1581     size  =  impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1582   }
1583 
1584   // Check for float load
1585   if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1586     int offset = ra_->reg2offset(src_first);
1587     // Further check for aligned-adjacent pair, so we can use a double load
1588     if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1589       return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st);
1590     size  =  impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st);
1591   }
1592 
1593   // --------------------------------------------------------------------
1594   // Check for hi bits still needing moving.  Only happens for misaligned
1595   // arguments to native calls.
1596   if( src_second == dst_second )
1597     return size;               // Self copy; no move
1598   assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1599 
1600 #ifndef _LP64
1601   // In the LP64 build, all registers can be moved as aligned/adjacent
1602   // pairs, so there's never any need to move the high bits separately.
1603   // The 32-bit builds have to deal with the 32-bit ABI which can force
1604   // all sorts of silly alignment problems.
1605 
1606   // Check for integer reg-reg copy.  Hi bits are stuck up in the top
1607   // 32-bits of a 64-bit register, but are needed in low bits of another
1608   // register (else it's a hi-bits-to-hi-bits copy which should have
1609   // happened already as part of a 64-bit move)
1610   if( src_second_rc == rc_int && dst_second_rc == rc_int ) {
1611     assert( (src_second&1)==1, "its the evil O0/O1 native return case" );
1612     assert( (dst_second&1)==0, "should have moved with 1 64-bit move" );
1613     // Shift src_second down to dst_second's low bits.
1614     if( cbuf ) {
1615       emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1616 #ifndef PRODUCT
1617     } else if( !do_size ) {
1618       if( size != 0 ) st->print("\n\t");
1619       st->print("SRLX   R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second));
1620 #endif
1621     }
1622     return size+4;
1623   }
1624 
1625   // Check for high word integer store.  Must down-shift the hi bits
1626   // into a temp register, then fall into the case of storing int bits.
1627   if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) {
1628     // Shift src_second down to dst_second's low bits.
1629     if( cbuf ) {
1630       emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1631 #ifndef PRODUCT
1632     } else if( !do_size ) {
1633       if( size != 0 ) st->print("\n\t");
1634       st->print("SRLX   R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num));
1635 #endif
1636     }
1637     size+=4;
1638     src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num!
1639   }
1640 
1641   // Check for high word integer load
1642   if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1643     return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st);
1644 
1645   // Check for high word integer store
1646   if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1647     return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st);
1648 
1649   // Check for high word float store
1650   if( src_second_rc == rc_float && dst_second_rc == rc_stack )
1651     return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st);
1652 
1653 #endif // !_LP64
1654 
1655   Unimplemented();
1656 }
1657 
1658 #ifndef PRODUCT
1659 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1660   implementation( NULL, ra_, false, st );
1661 }
1662 #endif
1663 
1664 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1665   implementation( &cbuf, ra_, false, NULL );
1666 }
1667 
1668 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1669   return implementation( NULL, ra_, true, NULL );
1670 }
1671 
1672 //=============================================================================
1673 #ifndef PRODUCT
1674 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const {
1675   st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
1676 }
1677 #endif
1678 
1679 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1680   MacroAssembler _masm(&cbuf);
1681   for(int i = 0; i < _count; i += 1) {
1682     __ nop();
1683   }
1684 }
1685 
1686 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1687   return 4 * _count;
1688 }
1689 
1690 
1691 //=============================================================================
1692 #ifndef PRODUCT
1693 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1694   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1695   int reg = ra_->get_reg_first(this);
1696   st->print("LEA    [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]);
1697 }
1698 #endif
1699 
1700 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1701   MacroAssembler _masm(&cbuf);
1702   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS;
1703   int reg = ra_->get_encode(this);
1704 
1705   if (Assembler::is_simm13(offset)) {
1706      __ add(SP, offset, reg_to_register_object(reg));
1707   } else {
1708      __ set(offset, O7);
1709      __ add(SP, O7, reg_to_register_object(reg));
1710   }
1711 }
1712 
1713 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1714   // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
1715   assert(ra_ == ra_->C->regalloc(), "sanity");
1716   return ra_->C->scratch_emit_size(this);
1717 }
1718 
1719 //=============================================================================
1720 #ifndef PRODUCT
1721 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1722   st->print_cr("\nUEP:");
1723 #ifdef    _LP64
1724   if (UseCompressedClassPointers) {
1725     assert(Universe::heap() != NULL, "java heap should be initialized");
1726     st->print_cr("\tLDUW   [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass");
1727     if (Universe::narrow_klass_base() != 0) {
1728       st->print_cr("\tSET    Universe::narrow_klass_base,R_G6_heap_base");
1729       if (Universe::narrow_klass_shift() != 0) {
1730         st->print_cr("\tSLL    R_G5,Universe::narrow_klass_shift,R_G5");
1731       }
1732       st->print_cr("\tADD    R_G5,R_G6_heap_base,R_G5");
1733       st->print_cr("\tSET    Universe::narrow_ptrs_base,R_G6_heap_base");
1734     } else {
1735       st->print_cr("\tSLL    R_G5,Universe::narrow_klass_shift,R_G5");
1736     }
1737   } else {
1738     st->print_cr("\tLDX    [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1739   }
1740   st->print_cr("\tCMP    R_G5,R_G3" );
1741   st->print   ("\tTne    xcc,R_G0+ST_RESERVED_FOR_USER_0+2");
1742 #else  // _LP64
1743   st->print_cr("\tLDUW   [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1744   st->print_cr("\tCMP    R_G5,R_G3" );
1745   st->print   ("\tTne    icc,R_G0+ST_RESERVED_FOR_USER_0+2");
1746 #endif // _LP64
1747 }
1748 #endif
1749 
1750 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1751   MacroAssembler _masm(&cbuf);
1752   Register G5_ic_reg  = reg_to_register_object(Matcher::inline_cache_reg_encode());
1753   Register temp_reg   = G3;
1754   assert( G5_ic_reg != temp_reg, "conflicting registers" );
1755 
1756   // Load klass from receiver
1757   __ load_klass(O0, temp_reg);
1758   // Compare against expected klass
1759   __ cmp(temp_reg, G5_ic_reg);
1760   // Branch to miss code, checks xcc or icc depending
1761   __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2);
1762 }
1763 
1764 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1765   return MachNode::size(ra_);
1766 }
1767 
1768 
1769 //=============================================================================
1770 
1771 
1772 // Emit exception handler code.
1773 int HandlerImpl::emit_exception_handler(CodeBuffer& cbuf) {
1774   Register temp_reg = G3;
1775   AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point());
1776   MacroAssembler _masm(&cbuf);
1777 
1778   address base = __ start_a_stub(size_exception_handler());
1779   if (base == NULL) {
1780     ciEnv::current()->record_failure("CodeCache is full");
1781     return 0;  // CodeBuffer::expand failed
1782   }
1783 
1784   int offset = __ offset();
1785 
1786   __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp
1787   __ delayed()->nop();
1788 
1789   assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1790 
1791   __ end_a_stub();
1792 
1793   return offset;
1794 }
1795 
1796 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) {
1797   // Can't use any of the current frame's registers as we may have deopted
1798   // at a poll and everything (including G3) can be live.
1799   Register temp_reg = L0;
1800   AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
1801   MacroAssembler _masm(&cbuf);
1802 
1803   address base = __ start_a_stub(size_deopt_handler());
1804   if (base == NULL) {
1805     ciEnv::current()->record_failure("CodeCache is full");
1806     return 0;  // CodeBuffer::expand failed
1807   }
1808 
1809   int offset = __ offset();
1810   __ save_frame(0);
1811   __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp
1812   __ delayed()->restore();
1813 
1814   assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1815 
1816   __ end_a_stub();
1817   return offset;
1818 
1819 }
1820 
1821 // Given a register encoding, produce a Integer Register object
1822 static Register reg_to_register_object(int register_encoding) {
1823   assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding");
1824   return as_Register(register_encoding);
1825 }
1826 
1827 // Given a register encoding, produce a single-precision Float Register object
1828 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) {
1829   assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding");
1830   return as_SingleFloatRegister(register_encoding);
1831 }
1832 
1833 // Given a register encoding, produce a double-precision Float Register object
1834 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) {
1835   assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding");
1836   assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding");
1837   return as_DoubleFloatRegister(register_encoding);
1838 }
1839 
1840 const bool Matcher::match_rule_supported(int opcode) {
1841   if (!has_match_rule(opcode))
1842     return false;
1843 
1844   switch (opcode) {
1845   case Op_CountLeadingZerosI:
1846   case Op_CountLeadingZerosL:
1847   case Op_CountTrailingZerosI:
1848   case Op_CountTrailingZerosL:
1849   case Op_PopCountI:
1850   case Op_PopCountL:
1851     if (!UsePopCountInstruction)
1852       return false;
1853   case Op_CompareAndSwapL:
1854 #ifdef _LP64
1855   case Op_CompareAndSwapP:
1856 #endif
1857     if (!VM_Version::supports_cx8())
1858       return false;
1859     break;
1860   }
1861 
1862   return true;  // Per default match rules are supported.
1863 }
1864 
1865 int Matcher::regnum_to_fpu_offset(int regnum) {
1866   return regnum - 32; // The FP registers are in the second chunk
1867 }
1868 
1869 #ifdef ASSERT
1870 address last_rethrow = NULL;  // debugging aid for Rethrow encoding
1871 #endif
1872 
1873 // Vector width in bytes
1874 const int Matcher::vector_width_in_bytes(BasicType bt) {
1875   assert(MaxVectorSize == 8, "");
1876   return 8;
1877 }
1878 
1879 // Vector ideal reg
1880 const int Matcher::vector_ideal_reg(int size) {
1881   assert(MaxVectorSize == 8, "");
1882   return Op_RegD;
1883 }
1884 
1885 const int Matcher::vector_shift_count_ideal_reg(int size) {
1886   fatal("vector shift is not supported");
1887   return Node::NotAMachineReg;
1888 }
1889 
1890 // Limits on vector size (number of elements) loaded into vector.
1891 const int Matcher::max_vector_size(const BasicType bt) {
1892   assert(is_java_primitive(bt), "only primitive type vectors");
1893   return vector_width_in_bytes(bt)/type2aelembytes(bt);
1894 }
1895 
1896 const int Matcher::min_vector_size(const BasicType bt) {
1897   return max_vector_size(bt); // Same as max.
1898 }
1899 
1900 // SPARC doesn't support misaligned vectors store/load.
1901 const bool Matcher::misaligned_vectors_ok() {
1902   return false;
1903 }
1904 
1905 // Current (2013) SPARC platforms need to read original key
1906 // to construct decryption expanded key 
1907 const bool Matcher::pass_original_key_for_aes() {
1908   return true;
1909 }
1910 
1911 // USII supports fxtof through the whole range of number, USIII doesn't
1912 const bool Matcher::convL2FSupported(void) {
1913   return VM_Version::has_fast_fxtof();
1914 }
1915 
1916 // Is this branch offset short enough that a short branch can be used?
1917 //
1918 // NOTE: If the platform does not provide any short branch variants, then
1919 //       this method should return false for offset 0.
1920 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1921   // The passed offset is relative to address of the branch.
1922   // Don't need to adjust the offset.
1923   return UseCBCond && Assembler::is_simm12(offset);
1924 }
1925 
1926 const bool Matcher::isSimpleConstant64(jlong value) {
1927   // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1928   // Depends on optimizations in MacroAssembler::setx.
1929   int hi = (int)(value >> 32);
1930   int lo = (int)(value & ~0);
1931   return (hi == 0) || (hi == -1) || (lo == 0);
1932 }
1933 
1934 // No scaling for the parameter the ClearArray node.
1935 const bool Matcher::init_array_count_is_in_bytes = true;
1936 
1937 // Threshold size for cleararray.
1938 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1939 
1940 // No additional cost for CMOVL.
1941 const int Matcher::long_cmove_cost() { return 0; }
1942 
1943 // CMOVF/CMOVD are expensive on T4 and on SPARC64.
1944 const int Matcher::float_cmove_cost() {
1945   return (VM_Version::is_T4() || VM_Version::is_sparc64()) ? ConditionalMoveLimit : 0;
1946 }
1947 
1948 // Does the CPU require late expand (see block.cpp for description of late expand)?
1949 const bool Matcher::require_postalloc_expand = false;
1950 
1951 // Should the Matcher clone shifts on addressing modes, expecting them to
1952 // be subsumed into complex addressing expressions or compute them into
1953 // registers?  True for Intel but false for most RISCs
1954 const bool Matcher::clone_shift_expressions = false;
1955 
1956 // Do we need to mask the count passed to shift instructions or does
1957 // the cpu only look at the lower 5/6 bits anyway?
1958 const bool Matcher::need_masked_shift_count = false;
1959 
1960 bool Matcher::narrow_oop_use_complex_address() {
1961   NOT_LP64(ShouldNotCallThis());
1962   assert(UseCompressedOops, "only for compressed oops code");
1963   return false;
1964 }
1965 
1966 bool Matcher::narrow_klass_use_complex_address() {
1967   NOT_LP64(ShouldNotCallThis());
1968   assert(UseCompressedClassPointers, "only for compressed klass code");
1969   return false;
1970 }
1971 
1972 // Is it better to copy float constants, or load them directly from memory?
1973 // Intel can load a float constant from a direct address, requiring no
1974 // extra registers.  Most RISCs will have to materialize an address into a
1975 // register first, so they would do better to copy the constant from stack.
1976 const bool Matcher::rematerialize_float_constants = false;
1977 
1978 // If CPU can load and store mis-aligned doubles directly then no fixup is
1979 // needed.  Else we split the double into 2 integer pieces and move it
1980 // piece-by-piece.  Only happens when passing doubles into C code as the
1981 // Java calling convention forces doubles to be aligned.
1982 #ifdef _LP64
1983 const bool Matcher::misaligned_doubles_ok = true;
1984 #else
1985 const bool Matcher::misaligned_doubles_ok = false;
1986 #endif
1987 
1988 // No-op on SPARC.
1989 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1990 }
1991 
1992 // Advertise here if the CPU requires explicit rounding operations
1993 // to implement the UseStrictFP mode.
1994 const bool Matcher::strict_fp_requires_explicit_rounding = false;
1995 
1996 // Are floats converted to double when stored to stack during deoptimization?
1997 // Sparc does not handle callee-save floats.
1998 bool Matcher::float_in_double() { return false; }
1999 
2000 // Do ints take an entire long register or just half?
2001 // Note that we if-def off of _LP64.
2002 // The relevant question is how the int is callee-saved.  In _LP64
2003 // the whole long is written but de-opt'ing will have to extract
2004 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written.
2005 #ifdef _LP64
2006 const bool Matcher::int_in_long = true;
2007 #else
2008 const bool Matcher::int_in_long = false;
2009 #endif
2010 
2011 // Return whether or not this register is ever used as an argument.  This
2012 // function is used on startup to build the trampoline stubs in generateOptoStub.
2013 // Registers not mentioned will be killed by the VM call in the trampoline, and
2014 // arguments in those registers not be available to the callee.
2015 bool Matcher::can_be_java_arg( int reg ) {
2016   // Standard sparc 6 args in registers
2017   if( reg == R_I0_num ||
2018       reg == R_I1_num ||
2019       reg == R_I2_num ||
2020       reg == R_I3_num ||
2021       reg == R_I4_num ||
2022       reg == R_I5_num ) return true;
2023 #ifdef _LP64
2024   // 64-bit builds can pass 64-bit pointers and longs in
2025   // the high I registers
2026   if( reg == R_I0H_num ||
2027       reg == R_I1H_num ||
2028       reg == R_I2H_num ||
2029       reg == R_I3H_num ||
2030       reg == R_I4H_num ||
2031       reg == R_I5H_num ) return true;
2032 
2033   if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) {
2034     return true;
2035   }
2036 
2037 #else
2038   // 32-bit builds with longs-in-one-entry pass longs in G1 & G4.
2039   // Longs cannot be passed in O regs, because O regs become I regs
2040   // after a 'save' and I regs get their high bits chopped off on
2041   // interrupt.
2042   if( reg == R_G1H_num || reg == R_G1_num ) return true;
2043   if( reg == R_G4H_num || reg == R_G4_num ) return true;
2044 #endif
2045   // A few float args in registers
2046   if( reg >= R_F0_num && reg <= R_F7_num ) return true;
2047 
2048   return false;
2049 }
2050 
2051 bool Matcher::is_spillable_arg( int reg ) {
2052   return can_be_java_arg(reg);
2053 }
2054 
2055 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
2056   // Use hardware SDIVX instruction when it is
2057   // faster than a code which use multiply.
2058   return VM_Version::has_fast_idiv();
2059 }
2060 
2061 // Register for DIVI projection of divmodI
2062 RegMask Matcher::divI_proj_mask() {
2063   ShouldNotReachHere();
2064   return RegMask();
2065 }
2066 
2067 // Register for MODI projection of divmodI
2068 RegMask Matcher::modI_proj_mask() {
2069   ShouldNotReachHere();
2070   return RegMask();
2071 }
2072 
2073 // Register for DIVL projection of divmodL
2074 RegMask Matcher::divL_proj_mask() {
2075   ShouldNotReachHere();
2076   return RegMask();
2077 }
2078 
2079 // Register for MODL projection of divmodL
2080 RegMask Matcher::modL_proj_mask() {
2081   ShouldNotReachHere();
2082   return RegMask();
2083 }
2084 
2085 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2086   return L7_REGP_mask();
2087 }
2088 
2089 %}
2090 
2091 
2092 // The intptr_t operand types, defined by textual substitution.
2093 // (Cf. opto/type.hpp.  This lets us avoid many, many other ifdefs.)
2094 #ifdef _LP64
2095 #define immX      immL
2096 #define immX13    immL13
2097 #define immX13m7  immL13m7
2098 #define iRegX     iRegL
2099 #define g1RegX    g1RegL
2100 #else
2101 #define immX      immI
2102 #define immX13    immI13
2103 #define immX13m7  immI13m7
2104 #define iRegX     iRegI
2105 #define g1RegX    g1RegI
2106 #endif
2107 
2108 //----------ENCODING BLOCK-----------------------------------------------------
2109 // This block specifies the encoding classes used by the compiler to output
2110 // byte streams.  Encoding classes are parameterized macros used by
2111 // Machine Instruction Nodes in order to generate the bit encoding of the
2112 // instruction.  Operands specify their base encoding interface with the
2113 // interface keyword.  There are currently supported four interfaces,
2114 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER.  REG_INTER causes an
2115 // operand to generate a function which returns its register number when
2116 // queried.   CONST_INTER causes an operand to generate a function which
2117 // returns the value of the constant when queried.  MEMORY_INTER causes an
2118 // operand to generate four functions which return the Base Register, the
2119 // Index Register, the Scale Value, and the Offset Value of the operand when
2120 // queried.  COND_INTER causes an operand to generate six functions which
2121 // return the encoding code (ie - encoding bits for the instruction)
2122 // associated with each basic boolean condition for a conditional instruction.
2123 //
2124 // Instructions specify two basic values for encoding.  Again, a function
2125 // is available to check if the constant displacement is an oop. They use the
2126 // ins_encode keyword to specify their encoding classes (which must be
2127 // a sequence of enc_class names, and their parameters, specified in
2128 // the encoding block), and they use the
2129 // opcode keyword to specify, in order, their primary, secondary, and
2130 // tertiary opcode.  Only the opcode sections which a particular instruction
2131 // needs for encoding need to be specified.
2132 encode %{
2133   enc_class enc_untested %{
2134 #ifdef ASSERT
2135     MacroAssembler _masm(&cbuf);
2136     __ untested("encoding");
2137 #endif
2138   %}
2139 
2140   enc_class form3_mem_reg( memory mem, iRegI dst ) %{
2141     emit_form3_mem_reg(cbuf, ra_, this, $primary, $tertiary,
2142                        $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2143   %}
2144 
2145   enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{
2146     emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2147                        $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2148   %}
2149 
2150   enc_class form3_mem_prefetch_read( memory mem ) %{
2151     emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2152                        $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/);
2153   %}
2154 
2155   enc_class form3_mem_prefetch_write( memory mem ) %{
2156     emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2157                        $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/);
2158   %}
2159 
2160   enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{
2161     assert(Assembler::is_simm13($mem$$disp  ), "need disp and disp+4");
2162     assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2163     guarantee($mem$$index == R_G0_enc, "double index?");
2164     emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc );
2165     emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp,   R_G0_enc, $reg$$reg );
2166     emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 );
2167     emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc );
2168   %}
2169 
2170   enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{
2171     assert(Assembler::is_simm13($mem$$disp  ), "need disp and disp+4");
2172     assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2173     guarantee($mem$$index == R_G0_enc, "double index?");
2174     // Load long with 2 instructions
2175     emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp,   R_G0_enc, $reg$$reg+0 );
2176     emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 );
2177   %}
2178 
2179   //%%% form3_mem_plus_4_reg is a hack--get rid of it
2180   enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{
2181     guarantee($mem$$disp, "cannot offset a reg-reg operand by 4");
2182     emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg);
2183   %}
2184 
2185   enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{
2186     // Encode a reg-reg copy.  If it is useless, then empty encoding.
2187     if( $rs2$$reg != $rd$$reg )
2188       emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg );
2189   %}
2190 
2191   // Target lo half of long
2192   enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{
2193     // Encode a reg-reg copy.  If it is useless, then empty encoding.
2194     if( $rs2$$reg != LONG_LO_REG($rd$$reg) )
2195       emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg );
2196   %}
2197 
2198   // Source lo half of long
2199   enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{
2200     // Encode a reg-reg copy.  If it is useless, then empty encoding.
2201     if( LONG_LO_REG($rs2$$reg) != $rd$$reg )
2202       emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) );
2203   %}
2204 
2205   // Target hi half of long
2206   enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{
2207     emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 );
2208   %}
2209 
2210   // Source lo half of long, and leave it sign extended.
2211   enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{
2212     // Sign extend low half
2213     emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 );
2214   %}
2215 
2216   // Source hi half of long, and leave it sign extended.
2217   enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{
2218     // Shift high half to low half
2219     emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 );
2220   %}
2221 
2222   // Source hi half of long
2223   enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{
2224     // Encode a reg-reg copy.  If it is useless, then empty encoding.
2225     if( LONG_HI_REG($rs2$$reg) != $rd$$reg )
2226       emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) );
2227   %}
2228 
2229   enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{
2230     emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg );
2231   %}
2232 
2233   enc_class enc_to_bool( iRegI src, iRegI dst ) %{
2234     emit3       ( cbuf, Assembler::arith_op,         0, Assembler::subcc_op3, 0, 0, $src$$reg );
2235     emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 );
2236   %}
2237 
2238   enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{
2239     emit3       ( cbuf, Assembler::arith_op,         0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg );
2240     // clear if nothing else is happening
2241     emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0,  0 );
2242     // blt,a,pn done
2243     emit2_19    ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 );
2244     // mov dst,-1 in delay slot
2245     emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2246   %}
2247 
2248   enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{
2249     emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F );
2250   %}
2251 
2252   enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{
2253     emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 );
2254   %}
2255 
2256   enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{
2257     emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg );
2258   %}
2259 
2260   enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{
2261     emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant );
2262   %}
2263 
2264   enc_class move_return_pc_to_o1() %{
2265     emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset );
2266   %}
2267 
2268 #ifdef _LP64
2269   /* %%% merge with enc_to_bool */
2270   enc_class enc_convP2B( iRegI dst, iRegP src ) %{
2271     MacroAssembler _masm(&cbuf);
2272 
2273     Register   src_reg = reg_to_register_object($src$$reg);
2274     Register   dst_reg = reg_to_register_object($dst$$reg);
2275     __ movr(Assembler::rc_nz, src_reg, 1, dst_reg);
2276   %}
2277 #endif
2278 
2279   enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{
2280     // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)))
2281     MacroAssembler _masm(&cbuf);
2282 
2283     Register   p_reg = reg_to_register_object($p$$reg);
2284     Register   q_reg = reg_to_register_object($q$$reg);
2285     Register   y_reg = reg_to_register_object($y$$reg);
2286     Register tmp_reg = reg_to_register_object($tmp$$reg);
2287 
2288     __ subcc( p_reg, q_reg,   p_reg );
2289     __ add  ( p_reg, y_reg, tmp_reg );
2290     __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg );
2291   %}
2292 
2293   enc_class form_d2i_helper(regD src, regF dst) %{
2294     // fcmp %fcc0,$src,$src
2295     emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2296     // branch %fcc0 not-nan, predict taken
2297     emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2298     // fdtoi $src,$dst
2299     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fdtoi_opf, $src$$reg );
2300     // fitos $dst,$dst (if nan)
2301     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fitos_opf, $dst$$reg );
2302     // clear $dst (if nan)
2303     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2304     // carry on here...
2305   %}
2306 
2307   enc_class form_d2l_helper(regD src, regD dst) %{
2308     // fcmp %fcc0,$src,$src  check for NAN
2309     emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2310     // branch %fcc0 not-nan, predict taken
2311     emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2312     // fdtox $src,$dst   convert in delay slot
2313     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fdtox_opf, $src$$reg );
2314     // fxtod $dst,$dst  (if nan)
2315     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fxtod_opf, $dst$$reg );
2316     // clear $dst (if nan)
2317     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2318     // carry on here...
2319   %}
2320 
2321   enc_class form_f2i_helper(regF src, regF dst) %{
2322     // fcmps %fcc0,$src,$src
2323     emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2324     // branch %fcc0 not-nan, predict taken
2325     emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2326     // fstoi $src,$dst
2327     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fstoi_opf, $src$$reg );
2328     // fitos $dst,$dst (if nan)
2329     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fitos_opf, $dst$$reg );
2330     // clear $dst (if nan)
2331     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2332     // carry on here...
2333   %}
2334 
2335   enc_class form_f2l_helper(regF src, regD dst) %{
2336     // fcmps %fcc0,$src,$src
2337     emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2338     // branch %fcc0 not-nan, predict taken
2339     emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2340     // fstox $src,$dst
2341     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fstox_opf, $src$$reg );
2342     // fxtod $dst,$dst (if nan)
2343     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fxtod_opf, $dst$$reg );
2344     // clear $dst (if nan)
2345     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2346     // carry on here...
2347   %}
2348 
2349   enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2350   enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2351   enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2352   enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2353 
2354   enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %}
2355 
2356   enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2357   enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %}
2358 
2359   enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{
2360     emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2361   %}
2362 
2363   enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{
2364     emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2365   %}
2366 
2367   enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{
2368     emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2369   %}
2370 
2371   enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{
2372     emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2373   %}
2374 
2375   enc_class form3_convI2F(regF rs2, regF rd) %{
2376     emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg);
2377   %}
2378 
2379   // Encloding class for traceable jumps
2380   enc_class form_jmpl(g3RegP dest) %{
2381     emit_jmpl(cbuf, $dest$$reg);
2382   %}
2383 
2384   enc_class form_jmpl_set_exception_pc(g1RegP dest) %{
2385     emit_jmpl_set_exception_pc(cbuf, $dest$$reg);
2386   %}
2387 
2388   enc_class form2_nop() %{
2389     emit_nop(cbuf);
2390   %}
2391 
2392   enc_class form2_illtrap() %{
2393     emit_illtrap(cbuf);
2394   %}
2395 
2396 
2397   // Compare longs and convert into -1, 0, 1.
2398   enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{
2399     // CMP $src1,$src2
2400     emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg );
2401     // blt,a,pn done
2402     emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less   , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 );
2403     // mov dst,-1 in delay slot
2404     emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2405     // bgt,a,pn done
2406     emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 );
2407     // mov dst,1 in delay slot
2408     emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0,  1 );
2409     // CLR    $dst
2410     emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 );
2411   %}
2412 
2413   enc_class enc_PartialSubtypeCheck() %{
2414     MacroAssembler _masm(&cbuf);
2415     __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type);
2416     __ delayed()->nop();
2417   %}
2418 
2419   enc_class enc_bp( label labl, cmpOp cmp, flagsReg cc ) %{
2420     MacroAssembler _masm(&cbuf);
2421     Label* L = $labl$$label;
2422     Assembler::Predict predict_taken =
2423       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2424 
2425     __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
2426     __ delayed()->nop();
2427   %}
2428 
2429   enc_class enc_bpr( label labl, cmpOp_reg cmp, iRegI op1 ) %{
2430     MacroAssembler _masm(&cbuf);
2431     Label* L = $labl$$label;
2432     Assembler::Predict predict_taken =
2433       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2434 
2435     __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), *L);
2436     __ delayed()->nop();
2437   %}
2438 
2439   enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{
2440     int op = (Assembler::arith_op << 30) |
2441              ($dst$$reg << 25) |
2442              (Assembler::movcc_op3 << 19) |
2443              (1 << 18) |                    // cc2 bit for 'icc'
2444              ($cmp$$cmpcode << 14) |
2445              (0 << 13) |                    // select register move
2446              ($pcc$$constant << 11) |       // cc1, cc0 bits for 'icc' or 'xcc'
2447              ($src$$reg << 0);
2448     cbuf.insts()->emit_int32(op);
2449   %}
2450 
2451   enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{
2452     int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2453     int op = (Assembler::arith_op << 30) |
2454              ($dst$$reg << 25) |
2455              (Assembler::movcc_op3 << 19) |
2456              (1 << 18) |                    // cc2 bit for 'icc'
2457              ($cmp$$cmpcode << 14) |
2458              (1 << 13) |                    // select immediate move
2459              ($pcc$$constant << 11) |       // cc1, cc0 bits for 'icc'
2460              (simm11 << 0);
2461     cbuf.insts()->emit_int32(op);
2462   %}
2463 
2464   enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{
2465     int op = (Assembler::arith_op << 30) |
2466              ($dst$$reg << 25) |
2467              (Assembler::movcc_op3 << 19) |
2468              (0 << 18) |                    // cc2 bit for 'fccX'
2469              ($cmp$$cmpcode << 14) |
2470              (0 << 13) |                    // select register move
2471              ($fcc$$reg << 11) |            // cc1, cc0 bits for fcc0-fcc3
2472              ($src$$reg << 0);
2473     cbuf.insts()->emit_int32(op);
2474   %}
2475 
2476   enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{
2477     int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2478     int op = (Assembler::arith_op << 30) |
2479              ($dst$$reg << 25) |
2480              (Assembler::movcc_op3 << 19) |
2481              (0 << 18) |                    // cc2 bit for 'fccX'
2482              ($cmp$$cmpcode << 14) |
2483              (1 << 13) |                    // select immediate move
2484              ($fcc$$reg << 11) |            // cc1, cc0 bits for fcc0-fcc3
2485              (simm11 << 0);
2486     cbuf.insts()->emit_int32(op);
2487   %}
2488 
2489   enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{
2490     int op = (Assembler::arith_op << 30) |
2491              ($dst$$reg << 25) |
2492              (Assembler::fpop2_op3 << 19) |
2493              (0 << 18) |
2494              ($cmp$$cmpcode << 14) |
2495              (1 << 13) |                    // select register move
2496              ($pcc$$constant << 11) |       // cc1-cc0 bits for 'icc' or 'xcc'
2497              ($primary << 5) |              // select single, double or quad
2498              ($src$$reg << 0);
2499     cbuf.insts()->emit_int32(op);
2500   %}
2501 
2502   enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{
2503     int op = (Assembler::arith_op << 30) |
2504              ($dst$$reg << 25) |
2505              (Assembler::fpop2_op3 << 19) |
2506              (0 << 18) |
2507              ($cmp$$cmpcode << 14) |
2508              ($fcc$$reg << 11) |            // cc2-cc0 bits for 'fccX'
2509              ($primary << 5) |              // select single, double or quad
2510              ($src$$reg << 0);
2511     cbuf.insts()->emit_int32(op);
2512   %}
2513 
2514   // Used by the MIN/MAX encodings.  Same as a CMOV, but
2515   // the condition comes from opcode-field instead of an argument.
2516   enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{
2517     int op = (Assembler::arith_op << 30) |
2518              ($dst$$reg << 25) |
2519              (Assembler::movcc_op3 << 19) |
2520              (1 << 18) |                    // cc2 bit for 'icc'
2521              ($primary << 14) |
2522              (0 << 13) |                    // select register move
2523              (0 << 11) |                    // cc1, cc0 bits for 'icc'
2524              ($src$$reg << 0);
2525     cbuf.insts()->emit_int32(op);
2526   %}
2527 
2528   enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{
2529     int op = (Assembler::arith_op << 30) |
2530              ($dst$$reg << 25) |
2531              (Assembler::movcc_op3 << 19) |
2532              (6 << 16) |                    // cc2 bit for 'xcc'
2533              ($primary << 14) |
2534              (0 << 13) |                    // select register move
2535              (0 << 11) |                    // cc1, cc0 bits for 'icc'
2536              ($src$$reg << 0);
2537     cbuf.insts()->emit_int32(op);
2538   %}
2539 
2540   enc_class Set13( immI13 src, iRegI rd ) %{
2541     emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant );
2542   %}
2543 
2544   enc_class SetHi22( immI src, iRegI rd ) %{
2545     emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant );
2546   %}
2547 
2548   enc_class Set32( immI src, iRegI rd ) %{
2549     MacroAssembler _masm(&cbuf);
2550     __ set($src$$constant, reg_to_register_object($rd$$reg));
2551   %}
2552 
2553   enc_class call_epilog %{
2554     if( VerifyStackAtCalls ) {
2555       MacroAssembler _masm(&cbuf);
2556       int framesize = ra_->C->frame_size_in_bytes();
2557       Register temp_reg = G3;
2558       __ add(SP, framesize, temp_reg);
2559       __ cmp(temp_reg, FP);
2560       __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc);
2561     }
2562   %}
2563 
2564   // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value
2565   // to G1 so the register allocator will not have to deal with the misaligned register
2566   // pair.
2567   enc_class adjust_long_from_native_call %{
2568 #ifndef _LP64
2569     if (returns_long()) {
2570       //    sllx  O0,32,O0
2571       emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 );
2572       //    srl   O1,0,O1
2573       emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 );
2574       //    or    O0,O1,G1
2575       emit3       ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc );
2576     }
2577 #endif
2578   %}
2579 
2580   enc_class Java_To_Runtime (method meth) %{    // CALL Java_To_Runtime
2581     // CALL directly to the runtime
2582     // The user of this is responsible for ensuring that R_L7 is empty (killed).
2583     emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type,
2584                     /*preserve_g2=*/true);
2585   %}
2586 
2587   enc_class preserve_SP %{
2588     MacroAssembler _masm(&cbuf);
2589     __ mov(SP, L7_mh_SP_save);
2590   %}
2591 
2592   enc_class restore_SP %{
2593     MacroAssembler _masm(&cbuf);
2594     __ mov(L7_mh_SP_save, SP);
2595   %}
2596 
2597   enc_class Java_Static_Call (method meth) %{    // JAVA STATIC CALL
2598     // CALL to fixup routine.  Fixup routine uses ScopeDesc info to determine
2599     // who we intended to call.
2600     if (!_method) {
2601       emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type);
2602     } else if (_optimized_virtual) {
2603       emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type);
2604     } else {
2605       emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type);
2606     }
2607     if (_method) {  // Emit stub for static call.
2608       address stub = CompiledStaticCall::emit_to_interp_stub(cbuf);
2609       // Stub does not fit into scratch buffer if TraceJumps is enabled
2610       if (stub == NULL && !(TraceJumps && Compile::current()->in_scratch_emit_size())) {
2611         ciEnv::current()->record_failure("CodeCache is full");
2612         return;
2613       } 
2614     }
2615   %}
2616 
2617   enc_class Java_Dynamic_Call (method meth) %{    // JAVA DYNAMIC CALL
2618     MacroAssembler _masm(&cbuf);
2619     __ set_inst_mark();
2620     int vtable_index = this->_vtable_index;
2621     // MachCallDynamicJavaNode::ret_addr_offset uses this same test
2622     if (vtable_index < 0) {
2623       // must be invalid_vtable_index, not nonvirtual_vtable_index
2624       assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
2625       Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2626       assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()");
2627       assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub");
2628       __ ic_call((address)$meth$$method);
2629     } else {
2630       assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
2631       // Just go thru the vtable
2632       // get receiver klass (receiver already checked for non-null)
2633       // If we end up going thru a c2i adapter interpreter expects method in G5
2634       int off = __ offset();
2635       __ load_klass(O0, G3_scratch);
2636       int klass_load_size;
2637       if (UseCompressedClassPointers) {
2638         assert(Universe::heap() != NULL, "java heap should be initialized");
2639         klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord;
2640       } else {
2641         klass_load_size = 1*BytesPerInstWord;
2642       }
2643       int entry_offset = InstanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
2644       int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
2645       if (Assembler::is_simm13(v_off)) {
2646         __ ld_ptr(G3, v_off, G5_method);
2647       } else {
2648         // Generate 2 instructions
2649         __ Assembler::sethi(v_off & ~0x3ff, G5_method);
2650         __ or3(G5_method, v_off & 0x3ff, G5_method);
2651         // ld_ptr, set_hi, set
2652         assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord,
2653                "Unexpected instruction size(s)");
2654         __ ld_ptr(G3, G5_method, G5_method);
2655       }
2656       // NOTE: for vtable dispatches, the vtable entry will never be null.
2657       // However it may very well end up in handle_wrong_method if the
2658       // method is abstract for the particular class.
2659       __ ld_ptr(G5_method, in_bytes(Method::from_compiled_offset()), G3_scratch);
2660       // jump to target (either compiled code or c2iadapter)
2661       __ jmpl(G3_scratch, G0, O7);
2662       __ delayed()->nop();
2663     }
2664   %}
2665 
2666   enc_class Java_Compiled_Call (method meth) %{    // JAVA COMPILED CALL
2667     MacroAssembler _masm(&cbuf);
2668 
2669     Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2670     Register temp_reg = G3;   // caller must kill G3!  We cannot reuse G5_ic_reg here because
2671                               // we might be calling a C2I adapter which needs it.
2672 
2673     assert(temp_reg != G5_ic_reg, "conflicting registers");
2674     // Load nmethod
2675     __ ld_ptr(G5_ic_reg, in_bytes(Method::from_compiled_offset()), temp_reg);
2676 
2677     // CALL to compiled java, indirect the contents of G3
2678     __ set_inst_mark();
2679     __ callr(temp_reg, G0);
2680     __ delayed()->nop();
2681   %}
2682 
2683 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{
2684     MacroAssembler _masm(&cbuf);
2685     Register Rdividend = reg_to_register_object($src1$$reg);
2686     Register Rdivisor = reg_to_register_object($src2$$reg);
2687     Register Rresult = reg_to_register_object($dst$$reg);
2688 
2689     __ sra(Rdivisor, 0, Rdivisor);
2690     __ sra(Rdividend, 0, Rdividend);
2691     __ sdivx(Rdividend, Rdivisor, Rresult);
2692 %}
2693 
2694 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{
2695     MacroAssembler _masm(&cbuf);
2696 
2697     Register Rdividend = reg_to_register_object($src1$$reg);
2698     int divisor = $imm$$constant;
2699     Register Rresult = reg_to_register_object($dst$$reg);
2700 
2701     __ sra(Rdividend, 0, Rdividend);
2702     __ sdivx(Rdividend, divisor, Rresult);
2703 %}
2704 
2705 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{
2706     MacroAssembler _masm(&cbuf);
2707     Register Rsrc1 = reg_to_register_object($src1$$reg);
2708     Register Rsrc2 = reg_to_register_object($src2$$reg);
2709     Register Rdst  = reg_to_register_object($dst$$reg);
2710 
2711     __ sra( Rsrc1, 0, Rsrc1 );
2712     __ sra( Rsrc2, 0, Rsrc2 );
2713     __ mulx( Rsrc1, Rsrc2, Rdst );
2714     __ srlx( Rdst, 32, Rdst );
2715 %}
2716 
2717 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{
2718     MacroAssembler _masm(&cbuf);
2719     Register Rdividend = reg_to_register_object($src1$$reg);
2720     Register Rdivisor = reg_to_register_object($src2$$reg);
2721     Register Rresult = reg_to_register_object($dst$$reg);
2722     Register Rscratch = reg_to_register_object($scratch$$reg);
2723 
2724     assert(Rdividend != Rscratch, "");
2725     assert(Rdivisor  != Rscratch, "");
2726 
2727     __ sra(Rdividend, 0, Rdividend);
2728     __ sra(Rdivisor, 0, Rdivisor);
2729     __ sdivx(Rdividend, Rdivisor, Rscratch);
2730     __ mulx(Rscratch, Rdivisor, Rscratch);
2731     __ sub(Rdividend, Rscratch, Rresult);
2732 %}
2733 
2734 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{
2735     MacroAssembler _masm(&cbuf);
2736 
2737     Register Rdividend = reg_to_register_object($src1$$reg);
2738     int divisor = $imm$$constant;
2739     Register Rresult = reg_to_register_object($dst$$reg);
2740     Register Rscratch = reg_to_register_object($scratch$$reg);
2741 
2742     assert(Rdividend != Rscratch, "");
2743 
2744     __ sra(Rdividend, 0, Rdividend);
2745     __ sdivx(Rdividend, divisor, Rscratch);
2746     __ mulx(Rscratch, divisor, Rscratch);
2747     __ sub(Rdividend, Rscratch, Rresult);
2748 %}
2749 
2750 enc_class fabss (sflt_reg dst, sflt_reg src) %{
2751     MacroAssembler _masm(&cbuf);
2752 
2753     FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2754     FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2755 
2756     __ fabs(FloatRegisterImpl::S, Fsrc, Fdst);
2757 %}
2758 
2759 enc_class fabsd (dflt_reg dst, dflt_reg src) %{
2760     MacroAssembler _masm(&cbuf);
2761 
2762     FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2763     FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2764 
2765     __ fabs(FloatRegisterImpl::D, Fsrc, Fdst);
2766 %}
2767 
2768 enc_class fnegd (dflt_reg dst, dflt_reg src) %{
2769     MacroAssembler _masm(&cbuf);
2770 
2771     FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2772     FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2773 
2774     __ fneg(FloatRegisterImpl::D, Fsrc, Fdst);
2775 %}
2776 
2777 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{
2778     MacroAssembler _masm(&cbuf);
2779 
2780     FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2781     FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2782 
2783     __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst);
2784 %}
2785 
2786 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{
2787     MacroAssembler _masm(&cbuf);
2788 
2789     FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2790     FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2791 
2792     __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst);
2793 %}
2794 
2795 enc_class fmovs (dflt_reg dst, dflt_reg src) %{
2796     MacroAssembler _masm(&cbuf);
2797 
2798     FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2799     FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2800 
2801     __ fmov(FloatRegisterImpl::S, Fsrc, Fdst);
2802 %}
2803 
2804 enc_class fmovd (dflt_reg dst, dflt_reg src) %{
2805     MacroAssembler _masm(&cbuf);
2806 
2807     FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2808     FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2809 
2810     __ fmov(FloatRegisterImpl::D, Fsrc, Fdst);
2811 %}
2812 
2813 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2814     MacroAssembler _masm(&cbuf);
2815 
2816     Register Roop  = reg_to_register_object($oop$$reg);
2817     Register Rbox  = reg_to_register_object($box$$reg);
2818     Register Rscratch = reg_to_register_object($scratch$$reg);
2819     Register Rmark =    reg_to_register_object($scratch2$$reg);
2820 
2821     assert(Roop  != Rscratch, "");
2822     assert(Roop  != Rmark, "");
2823     assert(Rbox  != Rscratch, "");
2824     assert(Rbox  != Rmark, "");
2825 
2826     __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining);
2827 %}
2828 
2829 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2830     MacroAssembler _masm(&cbuf);
2831 
2832     Register Roop  = reg_to_register_object($oop$$reg);
2833     Register Rbox  = reg_to_register_object($box$$reg);
2834     Register Rscratch = reg_to_register_object($scratch$$reg);
2835     Register Rmark =    reg_to_register_object($scratch2$$reg);
2836 
2837     assert(Roop  != Rscratch, "");
2838     assert(Roop  != Rmark, "");
2839     assert(Rbox  != Rscratch, "");
2840     assert(Rbox  != Rmark, "");
2841 
2842     __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining);
2843   %}
2844 
2845   enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{
2846     MacroAssembler _masm(&cbuf);
2847     Register Rmem = reg_to_register_object($mem$$reg);
2848     Register Rold = reg_to_register_object($old$$reg);
2849     Register Rnew = reg_to_register_object($new$$reg);
2850 
2851     __ cas_ptr(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold
2852     __ cmp( Rold, Rnew );
2853   %}
2854 
2855   enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{
2856     Register Rmem = reg_to_register_object($mem$$reg);
2857     Register Rold = reg_to_register_object($old$$reg);
2858     Register Rnew = reg_to_register_object($new$$reg);
2859 
2860     MacroAssembler _masm(&cbuf);
2861     __ mov(Rnew, O7);
2862     __ casx(Rmem, Rold, O7);
2863     __ cmp( Rold, O7 );
2864   %}
2865 
2866   // raw int cas, used for compareAndSwap
2867   enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{
2868     Register Rmem = reg_to_register_object($mem$$reg);
2869     Register Rold = reg_to_register_object($old$$reg);
2870     Register Rnew = reg_to_register_object($new$$reg);
2871 
2872     MacroAssembler _masm(&cbuf);
2873     __ mov(Rnew, O7);
2874     __ cas(Rmem, Rold, O7);
2875     __ cmp( Rold, O7 );
2876   %}
2877 
2878   enc_class enc_lflags_ne_to_boolean( iRegI res ) %{
2879     Register Rres = reg_to_register_object($res$$reg);
2880 
2881     MacroAssembler _masm(&cbuf);
2882     __ mov(1, Rres);
2883     __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres );
2884   %}
2885 
2886   enc_class enc_iflags_ne_to_boolean( iRegI res ) %{
2887     Register Rres = reg_to_register_object($res$$reg);
2888 
2889     MacroAssembler _masm(&cbuf);
2890     __ mov(1, Rres);
2891     __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres );
2892   %}
2893 
2894   enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{
2895     MacroAssembler _masm(&cbuf);
2896     Register Rdst = reg_to_register_object($dst$$reg);
2897     FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg)
2898                                      : reg_to_DoubleFloatRegister_object($src1$$reg);
2899     FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg)
2900                                      : reg_to_DoubleFloatRegister_object($src2$$reg);
2901 
2902     // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1)
2903     __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst);
2904   %}
2905 
2906 
2907   enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result) %{
2908     Label Ldone, Lloop;
2909     MacroAssembler _masm(&cbuf);
2910 
2911     Register   str1_reg = reg_to_register_object($str1$$reg);
2912     Register   str2_reg = reg_to_register_object($str2$$reg);
2913     Register   cnt1_reg = reg_to_register_object($cnt1$$reg);
2914     Register   cnt2_reg = reg_to_register_object($cnt2$$reg);
2915     Register result_reg = reg_to_register_object($result$$reg);
2916 
2917     assert(result_reg != str1_reg &&
2918            result_reg != str2_reg &&
2919            result_reg != cnt1_reg &&
2920            result_reg != cnt2_reg ,
2921            "need different registers");
2922 
2923     // Compute the minimum of the string lengths(str1_reg) and the
2924     // difference of the string lengths (stack)
2925 
2926     // See if the lengths are different, and calculate min in str1_reg.
2927     // Stash diff in O7 in case we need it for a tie-breaker.
2928     Label Lskip;
2929     __ subcc(cnt1_reg, cnt2_reg, O7);
2930     __ sll(cnt1_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit
2931     __ br(Assembler::greater, true, Assembler::pt, Lskip);
2932     // cnt2 is shorter, so use its count:
2933     __ delayed()->sll(cnt2_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit
2934     __ bind(Lskip);
2935 
2936     // reallocate cnt1_reg, cnt2_reg, result_reg
2937     // Note:  limit_reg holds the string length pre-scaled by 2
2938     Register limit_reg =   cnt1_reg;
2939     Register  chr2_reg =   cnt2_reg;
2940     Register  chr1_reg = result_reg;
2941     // str{12} are the base pointers
2942 
2943     // Is the minimum length zero?
2944     __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity
2945     __ br(Assembler::equal, true, Assembler::pn, Ldone);
2946     __ delayed()->mov(O7, result_reg);  // result is difference in lengths
2947 
2948     // Load first characters
2949     __ lduh(str1_reg, 0, chr1_reg);
2950     __ lduh(str2_reg, 0, chr2_reg);
2951 
2952     // Compare first characters
2953     __ subcc(chr1_reg, chr2_reg, chr1_reg);
2954     __ br(Assembler::notZero, false, Assembler::pt,  Ldone);
2955     assert(chr1_reg == result_reg, "result must be pre-placed");
2956     __ delayed()->nop();
2957 
2958     {
2959       // Check after comparing first character to see if strings are equivalent
2960       Label LSkip2;
2961       // Check if the strings start at same location
2962       __ cmp(str1_reg, str2_reg);
2963       __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2);
2964       __ delayed()->nop();
2965 
2966       // Check if the length difference is zero (in O7)
2967       __ cmp(G0, O7);
2968       __ br(Assembler::equal, true, Assembler::pn, Ldone);
2969       __ delayed()->mov(G0, result_reg);  // result is zero
2970 
2971       // Strings might not be equal
2972       __ bind(LSkip2);
2973     }
2974 
2975     // We have no guarantee that on 64 bit the higher half of limit_reg is 0
2976     __ signx(limit_reg);
2977 
2978     __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg);
2979     __ br(Assembler::equal, true, Assembler::pn, Ldone);
2980     __ delayed()->mov(O7, result_reg);  // result is difference in lengths
2981 
2982     // Shift str1_reg and str2_reg to the end of the arrays, negate limit
2983     __ add(str1_reg, limit_reg, str1_reg);
2984     __ add(str2_reg, limit_reg, str2_reg);
2985     __ neg(chr1_reg, limit_reg);  // limit = -(limit-2)
2986 
2987     // Compare the rest of the characters
2988     __ lduh(str1_reg, limit_reg, chr1_reg);
2989     __ bind(Lloop);
2990     // __ lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2991     __ lduh(str2_reg, limit_reg, chr2_reg);
2992     __ subcc(chr1_reg, chr2_reg, chr1_reg);
2993     __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2994     assert(chr1_reg == result_reg, "result must be pre-placed");
2995     __ delayed()->inccc(limit_reg, sizeof(jchar));
2996     // annul LDUH if branch is not taken to prevent access past end of string
2997     __ br(Assembler::notZero, true, Assembler::pt, Lloop);
2998     __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2999 
3000     // If strings are equal up to min length, return the length difference.
3001     __ mov(O7, result_reg);
3002 
3003     // Otherwise, return the difference between the first mismatched chars.
3004     __ bind(Ldone);
3005   %}
3006 
3007 enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result) %{
3008     Label Lword_loop, Lpost_word, Lchar, Lchar_loop, Ldone;
3009     MacroAssembler _masm(&cbuf);
3010 
3011     Register   str1_reg = reg_to_register_object($str1$$reg);
3012     Register   str2_reg = reg_to_register_object($str2$$reg);
3013     Register    cnt_reg = reg_to_register_object($cnt$$reg);
3014     Register   tmp1_reg = O7;
3015     Register result_reg = reg_to_register_object($result$$reg);
3016 
3017     assert(result_reg != str1_reg &&
3018            result_reg != str2_reg &&
3019            result_reg !=  cnt_reg &&
3020            result_reg != tmp1_reg ,
3021            "need different registers");
3022 
3023     __ cmp(str1_reg, str2_reg); //same char[] ?
3024     __ brx(Assembler::equal, true, Assembler::pn, Ldone);
3025     __ delayed()->add(G0, 1, result_reg);
3026 
3027     __ cmp_zero_and_br(Assembler::zero, cnt_reg, Ldone, true, Assembler::pn);
3028     __ delayed()->add(G0, 1, result_reg); // count == 0
3029 
3030     //rename registers
3031     Register limit_reg =    cnt_reg;
3032     Register  chr1_reg = result_reg;
3033     Register  chr2_reg =   tmp1_reg;
3034 
3035     // We have no guarantee that on 64 bit the higher half of limit_reg is 0
3036     __ signx(limit_reg);
3037 
3038     //check for alignment and position the pointers to the ends
3039     __ or3(str1_reg, str2_reg, chr1_reg);
3040     __ andcc(chr1_reg, 0x3, chr1_reg);
3041     // notZero means at least one not 4-byte aligned.
3042     // We could optimize the case when both arrays are not aligned
3043     // but it is not frequent case and it requires additional checks.
3044     __ br(Assembler::notZero, false, Assembler::pn, Lchar); // char by char compare
3045     __ delayed()->sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); // set byte count
3046 
3047     // Compare char[] arrays aligned to 4 bytes.
3048     __ char_arrays_equals(str1_reg, str2_reg, limit_reg, result_reg,
3049                           chr1_reg, chr2_reg, Ldone);
3050     __ ba(Ldone);
3051     __ delayed()->add(G0, 1, result_reg);
3052 
3053     // char by char compare
3054     __ bind(Lchar);
3055     __ add(str1_reg, limit_reg, str1_reg);
3056     __ add(str2_reg, limit_reg, str2_reg);
3057     __ neg(limit_reg); //negate count
3058 
3059     __ lduh(str1_reg, limit_reg, chr1_reg);
3060     // Lchar_loop
3061     __ bind(Lchar_loop);
3062     __ lduh(str2_reg, limit_reg, chr2_reg);
3063     __ cmp(chr1_reg, chr2_reg);
3064     __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
3065     __ delayed()->mov(G0, result_reg); //not equal
3066     __ inccc(limit_reg, sizeof(jchar));
3067     // annul LDUH if branch is not taken to prevent access past end of string
3068     __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop);
3069     __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted
3070 
3071     __ add(G0, 1, result_reg);  //equal
3072 
3073     __ bind(Ldone);
3074   %}
3075 
3076 enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, notemp_iRegI result) %{
3077     Label Lvector, Ldone, Lloop;
3078     MacroAssembler _masm(&cbuf);
3079 
3080     Register   ary1_reg = reg_to_register_object($ary1$$reg);
3081     Register   ary2_reg = reg_to_register_object($ary2$$reg);
3082     Register   tmp1_reg = reg_to_register_object($tmp1$$reg);
3083     Register   tmp2_reg = O7;
3084     Register result_reg = reg_to_register_object($result$$reg);
3085 
3086     int length_offset  = arrayOopDesc::length_offset_in_bytes();
3087     int base_offset    = arrayOopDesc::base_offset_in_bytes(T_CHAR);
3088 
3089     // return true if the same array
3090     __ cmp(ary1_reg, ary2_reg);
3091     __ brx(Assembler::equal, true, Assembler::pn, Ldone);
3092     __ delayed()->add(G0, 1, result_reg); // equal
3093 
3094     __ br_null(ary1_reg, true, Assembler::pn, Ldone);
3095     __ delayed()->mov(G0, result_reg);    // not equal
3096 
3097     __ br_null(ary2_reg, true, Assembler::pn, Ldone);
3098     __ delayed()->mov(G0, result_reg);    // not equal
3099 
3100     //load the lengths of arrays
3101     __ ld(Address(ary1_reg, length_offset), tmp1_reg);
3102     __ ld(Address(ary2_reg, length_offset), tmp2_reg);
3103 
3104     // return false if the two arrays are not equal length
3105     __ cmp(tmp1_reg, tmp2_reg);
3106     __ br(Assembler::notEqual, true, Assembler::pn, Ldone);
3107     __ delayed()->mov(G0, result_reg);     // not equal
3108 
3109     __ cmp_zero_and_br(Assembler::zero, tmp1_reg, Ldone, true, Assembler::pn);
3110     __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal
3111 
3112     // load array addresses
3113     __ add(ary1_reg, base_offset, ary1_reg);
3114     __ add(ary2_reg, base_offset, ary2_reg);
3115 
3116     // renaming registers
3117     Register chr1_reg  =  result_reg; // for characters in ary1
3118     Register chr2_reg  =  tmp2_reg;   // for characters in ary2
3119     Register limit_reg =  tmp1_reg;   // length
3120 
3121     // set byte count
3122     __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg);
3123 
3124     // Compare char[] arrays aligned to 4 bytes.
3125     __ char_arrays_equals(ary1_reg, ary2_reg, limit_reg, result_reg,
3126                           chr1_reg, chr2_reg, Ldone);
3127     __ add(G0, 1, result_reg); // equals
3128 
3129     __ bind(Ldone);
3130   %}
3131 
3132   enc_class enc_rethrow() %{
3133     cbuf.set_insts_mark();
3134     Register temp_reg = G3;
3135     AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub());
3136     assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg");
3137     MacroAssembler _masm(&cbuf);
3138 #ifdef ASSERT
3139     __ save_frame(0);
3140     AddressLiteral last_rethrow_addrlit(&last_rethrow);
3141     __ sethi(last_rethrow_addrlit, L1);
3142     Address addr(L1, last_rethrow_addrlit.low10());
3143     __ rdpc(L2);
3144     __ inc(L2, 3 * BytesPerInstWord);  // skip this & 2 more insns to point at jump_to
3145     __ st_ptr(L2, addr);
3146     __ restore();
3147 #endif
3148     __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp
3149     __ delayed()->nop();
3150   %}
3151 
3152   enc_class emit_mem_nop() %{
3153     // Generates the instruction LDUXA [o6,g0],#0x82,g0
3154     cbuf.insts()->emit_int32((unsigned int) 0xc0839040);
3155   %}
3156 
3157   enc_class emit_fadd_nop() %{
3158     // Generates the instruction FMOVS f31,f31
3159     cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f);
3160   %}
3161 
3162   enc_class emit_br_nop() %{
3163     // Generates the instruction BPN,PN .
3164     cbuf.insts()->emit_int32((unsigned int) 0x00400000);
3165   %}
3166 
3167   enc_class enc_membar_acquire %{
3168     MacroAssembler _masm(&cbuf);
3169     __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) );
3170   %}
3171 
3172   enc_class enc_membar_release %{
3173     MacroAssembler _masm(&cbuf);
3174     __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) );
3175   %}
3176 
3177   enc_class enc_membar_volatile %{
3178     MacroAssembler _masm(&cbuf);
3179     __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3180   %}
3181 
3182 %}
3183 
3184 //----------FRAME--------------------------------------------------------------
3185 // Definition of frame structure and management information.
3186 //
3187 //  S T A C K   L A Y O U T    Allocators stack-slot number
3188 //                             |   (to get allocators register number
3189 //  G  Owned by    |        |  v    add VMRegImpl::stack0)
3190 //  r   CALLER     |        |
3191 //  o     |        +--------+      pad to even-align allocators stack-slot
3192 //  w     V        |  pad0  |        numbers; owned by CALLER
3193 //  t   -----------+--------+----> Matcher::_in_arg_limit, unaligned
3194 //  h     ^        |   in   |  5
3195 //        |        |  args  |  4   Holes in incoming args owned by SELF
3196 //  |     |        |        |  3
3197 //  |     |        +--------+
3198 //  V     |        | old out|      Empty on Intel, window on Sparc
3199 //        |    old |preserve|      Must be even aligned.
3200 //        |     SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned
3201 //        |        |   in   |  3   area for Intel ret address
3202 //     Owned by    |preserve|      Empty on Sparc.
3203 //       SELF      +--------+
3204 //        |        |  pad2  |  2   pad to align old SP
3205 //        |        +--------+  1
3206 //        |        | locks  |  0
3207 //        |        +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned
3208 //        |        |  pad1  | 11   pad to align new SP
3209 //        |        +--------+
3210 //        |        |        | 10
3211 //        |        | spills |  9   spills
3212 //        V        |        |  8   (pad0 slot for callee)
3213 //      -----------+--------+----> Matcher::_out_arg_limit, unaligned
3214 //        ^        |  out   |  7
3215 //        |        |  args  |  6   Holes in outgoing args owned by CALLEE
3216 //     Owned by    +--------+
3217 //      CALLEE     | new out|  6   Empty on Intel, window on Sparc
3218 //        |    new |preserve|      Must be even-aligned.
3219 //        |     SP-+--------+----> Matcher::_new_SP, even aligned
3220 //        |        |        |
3221 //
3222 // Note 1: Only region 8-11 is determined by the allocator.  Region 0-5 is
3223 //         known from SELF's arguments and the Java calling convention.
3224 //         Region 6-7 is determined per call site.
3225 // Note 2: If the calling convention leaves holes in the incoming argument
3226 //         area, those holes are owned by SELF.  Holes in the outgoing area
3227 //         are owned by the CALLEE.  Holes should not be nessecary in the
3228 //         incoming area, as the Java calling convention is completely under
3229 //         the control of the AD file.  Doubles can be sorted and packed to
3230 //         avoid holes.  Holes in the outgoing arguments may be necessary for
3231 //         varargs C calling conventions.
3232 // Note 3: Region 0-3 is even aligned, with pad2 as needed.  Region 3-5 is
3233 //         even aligned with pad0 as needed.
3234 //         Region 6 is even aligned.  Region 6-7 is NOT even aligned;
3235 //         region 6-11 is even aligned; it may be padded out more so that
3236 //         the region from SP to FP meets the minimum stack alignment.
3237 
3238 frame %{
3239   // What direction does stack grow in (assumed to be same for native & Java)
3240   stack_direction(TOWARDS_LOW);
3241 
3242   // These two registers define part of the calling convention
3243   // between compiled code and the interpreter.
3244   inline_cache_reg(R_G5);                // Inline Cache Register or Method* for I2C
3245   interpreter_method_oop_reg(R_G5);      // Method Oop Register when calling interpreter
3246 
3247   // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3248   cisc_spilling_operand_name(indOffset);
3249 
3250   // Number of stack slots consumed by a Monitor enter
3251 #ifdef _LP64
3252   sync_stack_slots(2);
3253 #else
3254   sync_stack_slots(1);
3255 #endif
3256 
3257   // Compiled code's Frame Pointer
3258   frame_pointer(R_SP);
3259 
3260   // Stack alignment requirement
3261   stack_alignment(StackAlignmentInBytes);
3262   //  LP64: Alignment size in bytes (128-bit -> 16 bytes)
3263   // !LP64: Alignment size in bytes (64-bit  ->  8 bytes)
3264 
3265   // Number of stack slots between incoming argument block and the start of
3266   // a new frame.  The PROLOG must add this many slots to the stack.  The
3267   // EPILOG must remove this many slots.
3268   in_preserve_stack_slots(0);
3269 
3270   // Number of outgoing stack slots killed above the out_preserve_stack_slots
3271   // for calls to C.  Supports the var-args backing area for register parms.
3272   // ADLC doesn't support parsing expressions, so I folded the math by hand.
3273 #ifdef _LP64
3274   // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word
3275   varargs_C_out_slots_killed(12);
3276 #else
3277   // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word
3278   varargs_C_out_slots_killed( 7);
3279 #endif
3280 
3281   // The after-PROLOG location of the return address.  Location of
3282   // return address specifies a type (REG or STACK) and a number
3283   // representing the register number (i.e. - use a register name) or
3284   // stack slot.
3285   return_addr(REG R_I7);          // Ret Addr is in register I7
3286 
3287   // Body of function which returns an OptoRegs array locating
3288   // arguments either in registers or in stack slots for calling
3289   // java
3290   calling_convention %{
3291     (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing);
3292 
3293   %}
3294 
3295   // Body of function which returns an OptoRegs array locating
3296   // arguments either in registers or in stack slots for calling
3297   // C.
3298   c_calling_convention %{
3299     // This is obviously always outgoing
3300     (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
3301   %}
3302 
3303   // Location of native (C/C++) and interpreter return values.  This is specified to
3304   // be the  same as Java.  In the 32-bit VM, long values are actually returned from
3305   // native calls in O0:O1 and returned to the interpreter in I0:I1.  The copying
3306   // to and from the register pairs is done by the appropriate call and epilog
3307   // opcodes.  This simplifies the register allocator.
3308   c_return_value %{
3309     assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3310 #ifdef     _LP64
3311     static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num,     R_O0_num,     R_O0_num,     R_F0_num,     R_F0_num, R_O0_num };
3312     static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num,    OptoReg::Bad, R_F1_num, R_O0H_num};
3313     static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num,     R_I0_num,     R_I0_num,     R_F0_num,     R_F0_num, R_I0_num };
3314     static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num,    OptoReg::Bad, R_F1_num, R_I0H_num};
3315 #else  // !_LP64
3316     static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num,     R_O0_num,     R_O0_num,     R_F0_num,     R_F0_num, R_G1_num };
3317     static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3318     static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num,     R_I0_num,     R_I0_num,     R_F0_num,     R_F0_num, R_G1_num };
3319     static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3320 #endif
3321     return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3322                         (is_outgoing?lo_out:lo_in)[ideal_reg] );
3323   %}
3324 
3325   // Location of compiled Java return values.  Same as C
3326   return_value %{
3327     assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3328 #ifdef     _LP64
3329     static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num,     R_O0_num,     R_O0_num,     R_F0_num,     R_F0_num, R_O0_num };
3330     static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num,    OptoReg::Bad, R_F1_num, R_O0H_num};
3331     static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num,     R_I0_num,     R_I0_num,     R_F0_num,     R_F0_num, R_I0_num };
3332     static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num,    OptoReg::Bad, R_F1_num, R_I0H_num};
3333 #else  // !_LP64
3334     static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num,     R_O0_num,     R_O0_num,     R_F0_num,     R_F0_num, R_G1_num };
3335     static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3336     static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num,     R_I0_num,     R_I0_num,     R_F0_num,     R_F0_num, R_G1_num };
3337     static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3338 #endif
3339     return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3340                         (is_outgoing?lo_out:lo_in)[ideal_reg] );
3341   %}
3342 
3343 %}
3344 
3345 
3346 //----------ATTRIBUTES---------------------------------------------------------
3347 //----------Operand Attributes-------------------------------------------------
3348 op_attrib op_cost(1);          // Required cost attribute
3349 
3350 //----------Instruction Attributes---------------------------------------------
3351 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
3352 ins_attrib ins_size(32);           // Required size attribute (in bits)
3353 
3354 // avoid_back_to_back attribute is an expression that must return
3355 // one of the following values defined in MachNode:
3356 // AVOID_NONE   - instruction can be placed anywhere
3357 // AVOID_BEFORE - instruction cannot be placed after an
3358 //                instruction with MachNode::AVOID_AFTER
3359 // AVOID_AFTER  - the next instruction cannot be the one 
3360 //                with MachNode::AVOID_BEFORE
3361 // AVOID_BEFORE_AND_AFTER - BEFORE and AFTER attributes at 
3362 //                          the same time                                
3363 ins_attrib ins_avoid_back_to_back(MachNode::AVOID_NONE);
3364 
3365 ins_attrib ins_short_branch(0);    // Required flag: is this instruction a
3366                                    // non-matching short branch variant of some
3367                                                             // long branch?
3368 
3369 //----------OPERANDS-----------------------------------------------------------
3370 // Operand definitions must precede instruction definitions for correct parsing
3371 // in the ADLC because operands constitute user defined types which are used in
3372 // instruction definitions.
3373 
3374 //----------Simple Operands----------------------------------------------------
3375 // Immediate Operands
3376 // Integer Immediate: 32-bit
3377 operand immI() %{
3378   match(ConI);
3379 
3380   op_cost(0);
3381   // formats are generated automatically for constants and base registers
3382   format %{ %}
3383   interface(CONST_INTER);
3384 %}
3385 
3386 // Integer Immediate: 8-bit
3387 operand immI8() %{
3388   predicate(Assembler::is_simm8(n->get_int()));
3389   match(ConI);
3390   op_cost(0);
3391   format %{ %}
3392   interface(CONST_INTER);
3393 %}
3394 
3395 // Integer Immediate: 13-bit
3396 operand immI13() %{
3397   predicate(Assembler::is_simm13(n->get_int()));
3398   match(ConI);
3399   op_cost(0);
3400 
3401   format %{ %}
3402   interface(CONST_INTER);
3403 %}
3404 
3405 // Integer Immediate: 13-bit minus 7
3406 operand immI13m7() %{
3407   predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095));
3408   match(ConI);
3409   op_cost(0);
3410 
3411   format %{ %}
3412   interface(CONST_INTER);
3413 %}
3414 
3415 // Integer Immediate: 16-bit
3416 operand immI16() %{
3417   predicate(Assembler::is_simm16(n->get_int()));
3418   match(ConI);
3419   op_cost(0);
3420   format %{ %}
3421   interface(CONST_INTER);
3422 %}
3423 
3424 // Unsigned Integer Immediate: 12-bit (non-negative that fits in simm13)
3425 operand immU12() %{
3426   predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
3427   match(ConI);
3428   op_cost(0);
3429 
3430   format %{ %}
3431   interface(CONST_INTER);
3432 %}
3433 
3434 // Integer Immediate: 6-bit
3435 operand immU6() %{
3436   predicate(n->get_int() >= 0 && n->get_int() <= 63);
3437   match(ConI);
3438   op_cost(0);
3439   format %{ %}
3440   interface(CONST_INTER);
3441 %}
3442 
3443 // Integer Immediate: 11-bit
3444 operand immI11() %{
3445   predicate(Assembler::is_simm11(n->get_int()));
3446   match(ConI);
3447   op_cost(0);
3448   format %{ %}
3449   interface(CONST_INTER);
3450 %}
3451 
3452 // Integer Immediate: 5-bit
3453 operand immI5() %{
3454   predicate(Assembler::is_simm5(n->get_int()));
3455   match(ConI);
3456   op_cost(0);
3457   format %{ %}
3458   interface(CONST_INTER);
3459 %}
3460 
3461 // Int Immediate non-negative
3462 operand immU31()
3463 %{
3464   predicate(n->get_int() >= 0);
3465   match(ConI);
3466 
3467   op_cost(0);
3468   format %{ %}
3469   interface(CONST_INTER);
3470 %}
3471 
3472 // Integer Immediate: 0-bit
3473 operand immI0() %{
3474   predicate(n->get_int() == 0);
3475   match(ConI);
3476   op_cost(0);
3477 
3478   format %{ %}
3479   interface(CONST_INTER);
3480 %}
3481 
3482 // Integer Immediate: the value 10
3483 operand immI10() %{
3484   predicate(n->get_int() == 10);
3485   match(ConI);
3486   op_cost(0);
3487 
3488   format %{ %}
3489   interface(CONST_INTER);
3490 %}
3491 
3492 // Integer Immediate: the values 0-31
3493 operand immU5() %{
3494   predicate(n->get_int() >= 0 && n->get_int() <= 31);
3495   match(ConI);
3496   op_cost(0);
3497 
3498   format %{ %}
3499   interface(CONST_INTER);
3500 %}
3501 
3502 // Integer Immediate: the values 1-31
3503 operand immI_1_31() %{
3504   predicate(n->get_int() >= 1 && n->get_int() <= 31);
3505   match(ConI);
3506   op_cost(0);
3507 
3508   format %{ %}
3509   interface(CONST_INTER);
3510 %}
3511 
3512 // Integer Immediate: the values 32-63
3513 operand immI_32_63() %{
3514   predicate(n->get_int() >= 32 && n->get_int() <= 63);
3515   match(ConI);
3516   op_cost(0);
3517 
3518   format %{ %}
3519   interface(CONST_INTER);
3520 %}
3521 
3522 // Immediates for special shifts (sign extend)
3523 
3524 // Integer Immediate: the value 16
3525 operand immI_16() %{
3526   predicate(n->get_int() == 16);
3527   match(ConI);
3528   op_cost(0);
3529 
3530   format %{ %}
3531   interface(CONST_INTER);
3532 %}
3533 
3534 // Integer Immediate: the value 24
3535 operand immI_24() %{
3536   predicate(n->get_int() == 24);
3537   match(ConI);
3538   op_cost(0);
3539 
3540   format %{ %}
3541   interface(CONST_INTER);
3542 %}
3543 
3544 // Integer Immediate: the value 255
3545 operand immI_255() %{
3546   predicate( n->get_int() == 255 );
3547   match(ConI);
3548   op_cost(0);
3549 
3550   format %{ %}
3551   interface(CONST_INTER);
3552 %}
3553 
3554 // Integer Immediate: the value 65535
3555 operand immI_65535() %{
3556   predicate(n->get_int() == 65535);
3557   match(ConI);
3558   op_cost(0);
3559 
3560   format %{ %}
3561   interface(CONST_INTER);
3562 %}
3563 
3564 // Long Immediate: the value FF
3565 operand immL_FF() %{
3566   predicate( n->get_long() == 0xFFL );
3567   match(ConL);
3568   op_cost(0);
3569 
3570   format %{ %}
3571   interface(CONST_INTER);
3572 %}
3573 
3574 // Long Immediate: the value FFFF
3575 operand immL_FFFF() %{
3576   predicate( n->get_long() == 0xFFFFL );
3577   match(ConL);
3578   op_cost(0);
3579 
3580   format %{ %}
3581   interface(CONST_INTER);
3582 %}
3583 
3584 // Pointer Immediate: 32 or 64-bit
3585 operand immP() %{
3586   match(ConP);
3587 
3588   op_cost(5);
3589   // formats are generated automatically for constants and base registers
3590   format %{ %}
3591   interface(CONST_INTER);
3592 %}
3593 
3594 #ifdef _LP64
3595 // Pointer Immediate: 64-bit
3596 operand immP_set() %{
3597   predicate(!VM_Version::is_niagara_plus());
3598   match(ConP);
3599 
3600   op_cost(5);
3601   // formats are generated automatically for constants and base registers
3602   format %{ %}
3603   interface(CONST_INTER);
3604 %}
3605 
3606 // Pointer Immediate: 64-bit
3607 // From Niagara2 processors on a load should be better than materializing.
3608 operand immP_load() %{
3609   predicate(VM_Version::is_niagara_plus() && (n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set(n->get_ptr()) > 3)));
3610   match(ConP);
3611 
3612   op_cost(5);
3613   // formats are generated automatically for constants and base registers
3614   format %{ %}
3615   interface(CONST_INTER);
3616 %}
3617 
3618 // Pointer Immediate: 64-bit
3619 operand immP_no_oop_cheap() %{
3620   predicate(VM_Version::is_niagara_plus() && !n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set(n->get_ptr()) <= 3));
3621   match(ConP);
3622 
3623   op_cost(5);
3624   // formats are generated automatically for constants and base registers
3625   format %{ %}
3626   interface(CONST_INTER);
3627 %}
3628 #endif
3629 
3630 operand immP13() %{
3631   predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095));
3632   match(ConP);
3633   op_cost(0);
3634 
3635   format %{ %}
3636   interface(CONST_INTER);
3637 %}
3638 
3639 operand immP0() %{
3640   predicate(n->get_ptr() == 0);
3641   match(ConP);
3642   op_cost(0);
3643 
3644   format %{ %}
3645   interface(CONST_INTER);
3646 %}
3647 
3648 operand immP_poll() %{
3649   predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
3650   match(ConP);
3651 
3652   // formats are generated automatically for constants and base registers
3653   format %{ %}
3654   interface(CONST_INTER);
3655 %}
3656 
3657 // Pointer Immediate
3658 operand immN()
3659 %{
3660   match(ConN);
3661 
3662   op_cost(10);
3663   format %{ %}
3664   interface(CONST_INTER);
3665 %}
3666 
3667 operand immNKlass()
3668 %{
3669   match(ConNKlass);
3670 
3671   op_cost(10);
3672   format %{ %}
3673   interface(CONST_INTER);
3674 %}
3675 
3676 // NULL Pointer Immediate
3677 operand immN0()
3678 %{
3679   predicate(n->get_narrowcon() == 0);
3680   match(ConN);
3681 
3682   op_cost(0);
3683   format %{ %}
3684   interface(CONST_INTER);
3685 %}
3686 
3687 operand immL() %{
3688   match(ConL);
3689   op_cost(40);
3690   // formats are generated automatically for constants and base registers
3691   format %{ %}
3692   interface(CONST_INTER);
3693 %}
3694 
3695 operand immL0() %{
3696   predicate(n->get_long() == 0L);
3697   match(ConL);
3698   op_cost(0);
3699   // formats are generated automatically for constants and base registers
3700   format %{ %}
3701   interface(CONST_INTER);
3702 %}
3703 
3704 // Integer Immediate: 5-bit
3705 operand immL5() %{
3706   predicate(n->get_long() == (int)n->get_long() && Assembler::is_simm5((int)n->get_long()));
3707   match(ConL);
3708   op_cost(0);
3709   format %{ %}
3710   interface(CONST_INTER);
3711 %}
3712 
3713 // Long Immediate: 13-bit
3714 operand immL13() %{
3715   predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L));
3716   match(ConL);
3717   op_cost(0);
3718 
3719   format %{ %}
3720   interface(CONST_INTER);
3721 %}
3722 
3723 // Long Immediate: 13-bit minus 7
3724 operand immL13m7() %{
3725   predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L));
3726   match(ConL);
3727   op_cost(0);
3728 
3729   format %{ %}
3730   interface(CONST_INTER);
3731 %}
3732 
3733 // Long Immediate: low 32-bit mask
3734 operand immL_32bits() %{
3735   predicate(n->get_long() == 0xFFFFFFFFL);
3736   match(ConL);
3737   op_cost(0);
3738 
3739   format %{ %}
3740   interface(CONST_INTER);
3741 %}
3742 
3743 // Long Immediate: cheap (materialize in <= 3 instructions)
3744 operand immL_cheap() %{
3745   predicate(!VM_Version::is_niagara_plus() || MacroAssembler::insts_for_set64(n->get_long()) <= 3);
3746   match(ConL);
3747   op_cost(0);
3748 
3749   format %{ %}
3750   interface(CONST_INTER);
3751 %}
3752 
3753 // Long Immediate: expensive (materialize in > 3 instructions)
3754 operand immL_expensive() %{
3755   predicate(VM_Version::is_niagara_plus() && MacroAssembler::insts_for_set64(n->get_long()) > 3);
3756   match(ConL);
3757   op_cost(0);
3758 
3759   format %{ %}
3760   interface(CONST_INTER);
3761 %}
3762 
3763 // Double Immediate
3764 operand immD() %{
3765   match(ConD);
3766 
3767   op_cost(40);
3768   format %{ %}
3769   interface(CONST_INTER);
3770 %}
3771 
3772 // Double Immediate: +0.0d
3773 operand immD0() %{
3774   predicate(jlong_cast(n->getd()) == 0);
3775   match(ConD);
3776 
3777   op_cost(0);
3778   format %{ %}
3779   interface(CONST_INTER);
3780 %}
3781 
3782 // Float Immediate
3783 operand immF() %{
3784   match(ConF);
3785 
3786   op_cost(20);
3787   format %{ %}
3788   interface(CONST_INTER);
3789 %}
3790 
3791 // Float Immediate: +0.0f
3792 operand immF0() %{ 
3793   predicate(jint_cast(n->getf()) == 0);  
3794   match(ConF);
3795 
3796   op_cost(0);
3797   format %{ %}
3798   interface(CONST_INTER);
3799 %}
3800 
3801 // Integer Register Operands
3802 // Integer Register
3803 operand iRegI() %{
3804   constraint(ALLOC_IN_RC(int_reg));
3805   match(RegI);
3806 
3807   match(notemp_iRegI);
3808   match(g1RegI);
3809   match(o0RegI);
3810   match(iRegIsafe);
3811 
3812   format %{ %}
3813   interface(REG_INTER);
3814 %}
3815 
3816 operand notemp_iRegI() %{
3817   constraint(ALLOC_IN_RC(notemp_int_reg));
3818   match(RegI);
3819 
3820   match(o0RegI);
3821 
3822   format %{ %}
3823   interface(REG_INTER);
3824 %}
3825 
3826 operand o0RegI() %{
3827   constraint(ALLOC_IN_RC(o0_regI));
3828   match(iRegI);
3829 
3830   format %{ %}
3831   interface(REG_INTER);
3832 %}
3833 
3834 // Pointer Register
3835 operand iRegP() %{
3836   constraint(ALLOC_IN_RC(ptr_reg));
3837   match(RegP);
3838 
3839   match(lock_ptr_RegP);
3840   match(g1RegP);
3841   match(g2RegP);
3842   match(g3RegP);
3843   match(g4RegP);
3844   match(i0RegP);
3845   match(o0RegP);
3846   match(o1RegP);
3847   match(l7RegP);
3848 
3849   format %{ %}
3850   interface(REG_INTER);
3851 %}
3852 
3853 operand sp_ptr_RegP() %{
3854   constraint(ALLOC_IN_RC(sp_ptr_reg));
3855   match(RegP);
3856   match(iRegP);
3857 
3858   format %{ %}
3859   interface(REG_INTER);
3860 %}
3861 
3862 operand lock_ptr_RegP() %{
3863   constraint(ALLOC_IN_RC(lock_ptr_reg));
3864   match(RegP);
3865   match(i0RegP);
3866   match(o0RegP);
3867   match(o1RegP);
3868   match(l7RegP);
3869 
3870   format %{ %}
3871   interface(REG_INTER);
3872 %}
3873 
3874 operand g1RegP() %{
3875   constraint(ALLOC_IN_RC(g1_regP));
3876   match(iRegP);
3877 
3878   format %{ %}
3879   interface(REG_INTER);
3880 %}
3881 
3882 operand g2RegP() %{
3883   constraint(ALLOC_IN_RC(g2_regP));
3884   match(iRegP);
3885 
3886   format %{ %}
3887   interface(REG_INTER);
3888 %}
3889 
3890 operand g3RegP() %{
3891   constraint(ALLOC_IN_RC(g3_regP));
3892   match(iRegP);
3893 
3894   format %{ %}
3895   interface(REG_INTER);
3896 %}
3897 
3898 operand g1RegI() %{
3899   constraint(ALLOC_IN_RC(g1_regI));
3900   match(iRegI);
3901 
3902   format %{ %}
3903   interface(REG_INTER);
3904 %}
3905 
3906 operand g3RegI() %{
3907   constraint(ALLOC_IN_RC(g3_regI));
3908   match(iRegI);
3909 
3910   format %{ %}
3911   interface(REG_INTER);
3912 %}
3913 
3914 operand g4RegI() %{
3915   constraint(ALLOC_IN_RC(g4_regI));
3916   match(iRegI);
3917 
3918   format %{ %}
3919   interface(REG_INTER);
3920 %}
3921 
3922 operand g4RegP() %{
3923   constraint(ALLOC_IN_RC(g4_regP));
3924   match(iRegP);
3925 
3926   format %{ %}
3927   interface(REG_INTER);
3928 %}
3929 
3930 operand i0RegP() %{
3931   constraint(ALLOC_IN_RC(i0_regP));
3932   match(iRegP);
3933 
3934   format %{ %}
3935   interface(REG_INTER);
3936 %}
3937 
3938 operand o0RegP() %{
3939   constraint(ALLOC_IN_RC(o0_regP));
3940   match(iRegP);
3941 
3942   format %{ %}
3943   interface(REG_INTER);
3944 %}
3945 
3946 operand o1RegP() %{
3947   constraint(ALLOC_IN_RC(o1_regP));
3948   match(iRegP);
3949 
3950   format %{ %}
3951   interface(REG_INTER);
3952 %}
3953 
3954 operand o2RegP() %{
3955   constraint(ALLOC_IN_RC(o2_regP));
3956   match(iRegP);
3957 
3958   format %{ %}
3959   interface(REG_INTER);
3960 %}
3961 
3962 operand o7RegP() %{
3963   constraint(ALLOC_IN_RC(o7_regP));
3964   match(iRegP);
3965 
3966   format %{ %}
3967   interface(REG_INTER);
3968 %}
3969 
3970 operand l7RegP() %{
3971   constraint(ALLOC_IN_RC(l7_regP));
3972   match(iRegP);
3973 
3974   format %{ %}
3975   interface(REG_INTER);
3976 %}
3977 
3978 operand o7RegI() %{
3979   constraint(ALLOC_IN_RC(o7_regI));
3980   match(iRegI);
3981 
3982   format %{ %}
3983   interface(REG_INTER);
3984 %}
3985 
3986 operand iRegN() %{
3987   constraint(ALLOC_IN_RC(int_reg));
3988   match(RegN);
3989 
3990   format %{ %}
3991   interface(REG_INTER);
3992 %}
3993 
3994 // Long Register
3995 operand iRegL() %{
3996   constraint(ALLOC_IN_RC(long_reg));
3997   match(RegL);
3998 
3999   format %{ %}
4000   interface(REG_INTER);
4001 %}
4002 
4003 operand o2RegL() %{
4004   constraint(ALLOC_IN_RC(o2_regL));
4005   match(iRegL);
4006 
4007   format %{ %}
4008   interface(REG_INTER);
4009 %}
4010 
4011 operand o7RegL() %{
4012   constraint(ALLOC_IN_RC(o7_regL));
4013   match(iRegL);
4014 
4015   format %{ %}
4016   interface(REG_INTER);
4017 %}
4018 
4019 operand g1RegL() %{
4020   constraint(ALLOC_IN_RC(g1_regL));
4021   match(iRegL);
4022 
4023   format %{ %}
4024   interface(REG_INTER);
4025 %}
4026 
4027 operand g3RegL() %{
4028   constraint(ALLOC_IN_RC(g3_regL));
4029   match(iRegL);
4030 
4031   format %{ %}
4032   interface(REG_INTER);
4033 %}
4034 
4035 // Int Register safe
4036 // This is 64bit safe
4037 operand iRegIsafe() %{
4038   constraint(ALLOC_IN_RC(long_reg));
4039 
4040   match(iRegI);
4041 
4042   format %{ %}
4043   interface(REG_INTER);
4044 %}
4045 
4046 // Condition Code Flag Register
4047 operand flagsReg() %{
4048   constraint(ALLOC_IN_RC(int_flags));
4049   match(RegFlags);
4050 
4051   format %{ "ccr" %} // both ICC and XCC
4052   interface(REG_INTER);
4053 %}
4054 
4055 // Condition Code Register, unsigned comparisons.
4056 operand flagsRegU() %{
4057   constraint(ALLOC_IN_RC(int_flags));
4058   match(RegFlags);
4059 
4060   format %{ "icc_U" %}
4061   interface(REG_INTER);
4062 %}
4063 
4064 // Condition Code Register, pointer comparisons.
4065 operand flagsRegP() %{
4066   constraint(ALLOC_IN_RC(int_flags));
4067   match(RegFlags);
4068 
4069 #ifdef _LP64
4070   format %{ "xcc_P" %}
4071 #else
4072   format %{ "icc_P" %}
4073 #endif
4074   interface(REG_INTER);
4075 %}
4076 
4077 // Condition Code Register, long comparisons.
4078 operand flagsRegL() %{
4079   constraint(ALLOC_IN_RC(int_flags));
4080   match(RegFlags);
4081 
4082   format %{ "xcc_L" %}
4083   interface(REG_INTER);
4084 %}
4085 
4086 // Condition Code Register, floating comparisons, unordered same as "less".
4087 operand flagsRegF() %{
4088   constraint(ALLOC_IN_RC(float_flags));
4089   match(RegFlags);
4090   match(flagsRegF0);
4091 
4092   format %{ %}
4093   interface(REG_INTER);
4094 %}
4095 
4096 operand flagsRegF0() %{
4097   constraint(ALLOC_IN_RC(float_flag0));
4098   match(RegFlags);
4099 
4100   format %{ %}
4101   interface(REG_INTER);
4102 %}
4103 
4104 
4105 // Condition Code Flag Register used by long compare
4106 operand flagsReg_long_LTGE() %{
4107   constraint(ALLOC_IN_RC(int_flags));
4108   match(RegFlags);
4109   format %{ "icc_LTGE" %}
4110   interface(REG_INTER);
4111 %}
4112 operand flagsReg_long_EQNE() %{
4113   constraint(ALLOC_IN_RC(int_flags));
4114   match(RegFlags);
4115   format %{ "icc_EQNE" %}
4116   interface(REG_INTER);
4117 %}
4118 operand flagsReg_long_LEGT() %{
4119   constraint(ALLOC_IN_RC(int_flags));
4120   match(RegFlags);
4121   format %{ "icc_LEGT" %}
4122   interface(REG_INTER);
4123 %}
4124 
4125 
4126 operand regD() %{
4127   constraint(ALLOC_IN_RC(dflt_reg));
4128   match(RegD);
4129 
4130   match(regD_low);
4131 
4132   format %{ %}
4133   interface(REG_INTER);
4134 %}
4135 
4136 operand regF() %{
4137   constraint(ALLOC_IN_RC(sflt_reg));
4138   match(RegF);
4139 
4140   format %{ %}
4141   interface(REG_INTER);
4142 %}
4143 
4144 operand regD_low() %{
4145   constraint(ALLOC_IN_RC(dflt_low_reg));
4146   match(regD);
4147 
4148   format %{ %}
4149   interface(REG_INTER);
4150 %}
4151 
4152 // Special Registers
4153 
4154 // Method Register
4155 operand inline_cache_regP(iRegP reg) %{
4156   constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1
4157   match(reg);
4158   format %{ %}
4159   interface(REG_INTER);
4160 %}
4161 
4162 operand interpreter_method_oop_regP(iRegP reg) %{
4163   constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1
4164   match(reg);
4165   format %{ %}
4166   interface(REG_INTER);
4167 %}
4168 
4169 
4170 //----------Complex Operands---------------------------------------------------
4171 // Indirect Memory Reference
4172 operand indirect(sp_ptr_RegP reg) %{
4173   constraint(ALLOC_IN_RC(sp_ptr_reg));
4174   match(reg);
4175 
4176   op_cost(100);
4177   format %{ "[$reg]" %}
4178   interface(MEMORY_INTER) %{
4179     base($reg);
4180     index(0x0);
4181     scale(0x0);
4182     disp(0x0);
4183   %}
4184 %}
4185 
4186 // Indirect with simm13 Offset
4187 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{
4188   constraint(ALLOC_IN_RC(sp_ptr_reg));
4189   match(AddP reg offset);
4190 
4191   op_cost(100);
4192   format %{ "[$reg + $offset]" %}
4193   interface(MEMORY_INTER) %{
4194     base($reg);
4195     index(0x0);
4196     scale(0x0);
4197     disp($offset);
4198   %}
4199 %}
4200 
4201 // Indirect with simm13 Offset minus 7
4202 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{
4203   constraint(ALLOC_IN_RC(sp_ptr_reg));
4204   match(AddP reg offset);
4205 
4206   op_cost(100);
4207   format %{ "[$reg + $offset]" %}
4208   interface(MEMORY_INTER) %{
4209     base($reg);
4210     index(0x0);
4211     scale(0x0);
4212     disp($offset);
4213   %}
4214 %}
4215 
4216 // Note:  Intel has a swapped version also, like this:
4217 //operand indOffsetX(iRegI reg, immP offset) %{
4218 //  constraint(ALLOC_IN_RC(int_reg));
4219 //  match(AddP offset reg);
4220 //
4221 //  op_cost(100);
4222 //  format %{ "[$reg + $offset]" %}
4223 //  interface(MEMORY_INTER) %{
4224 //    base($reg);
4225 //    index(0x0);
4226 //    scale(0x0);
4227 //    disp($offset);
4228 //  %}
4229 //%}
4230 //// However, it doesn't make sense for SPARC, since
4231 // we have no particularly good way to embed oops in
4232 // single instructions.
4233 
4234 // Indirect with Register Index
4235 operand indIndex(iRegP addr, iRegX index) %{
4236   constraint(ALLOC_IN_RC(ptr_reg));
4237   match(AddP addr index);
4238 
4239   op_cost(100);
4240   format %{ "[$addr + $index]" %}
4241   interface(MEMORY_INTER) %{
4242     base($addr);
4243     index($index);
4244     scale(0x0);
4245     disp(0x0);
4246   %}
4247 %}
4248 
4249 //----------Special Memory Operands--------------------------------------------
4250 // Stack Slot Operand - This operand is used for loading and storing temporary
4251 //                      values on the stack where a match requires a value to
4252 //                      flow through memory.
4253 operand stackSlotI(sRegI reg) %{
4254   constraint(ALLOC_IN_RC(stack_slots));
4255   op_cost(100);
4256   //match(RegI);
4257   format %{ "[$reg]" %}
4258   interface(MEMORY_INTER) %{
4259     base(0xE);   // R_SP
4260     index(0x0);
4261     scale(0x0);
4262     disp($reg);  // Stack Offset
4263   %}
4264 %}
4265 
4266 operand stackSlotP(sRegP reg) %{
4267   constraint(ALLOC_IN_RC(stack_slots));
4268   op_cost(100);
4269   //match(RegP);
4270   format %{ "[$reg]" %}
4271   interface(MEMORY_INTER) %{
4272     base(0xE);   // R_SP
4273     index(0x0);
4274     scale(0x0);
4275     disp($reg);  // Stack Offset
4276   %}
4277 %}
4278 
4279 operand stackSlotF(sRegF reg) %{
4280   constraint(ALLOC_IN_RC(stack_slots));
4281   op_cost(100);
4282   //match(RegF);
4283   format %{ "[$reg]" %}
4284   interface(MEMORY_INTER) %{
4285     base(0xE);   // R_SP
4286     index(0x0);
4287     scale(0x0);
4288     disp($reg);  // Stack Offset
4289   %}
4290 %}
4291 operand stackSlotD(sRegD reg) %{
4292   constraint(ALLOC_IN_RC(stack_slots));
4293   op_cost(100);
4294   //match(RegD);
4295   format %{ "[$reg]" %}
4296   interface(MEMORY_INTER) %{
4297     base(0xE);   // R_SP
4298     index(0x0);
4299     scale(0x0);
4300     disp($reg);  // Stack Offset
4301   %}
4302 %}
4303 operand stackSlotL(sRegL reg) %{
4304   constraint(ALLOC_IN_RC(stack_slots));
4305   op_cost(100);
4306   //match(RegL);
4307   format %{ "[$reg]" %}
4308   interface(MEMORY_INTER) %{
4309     base(0xE);   // R_SP
4310     index(0x0);
4311     scale(0x0);
4312     disp($reg);  // Stack Offset
4313   %}
4314 %}
4315 
4316 // Operands for expressing Control Flow
4317 // NOTE:  Label is a predefined operand which should not be redefined in
4318 //        the AD file.  It is generically handled within the ADLC.
4319 
4320 //----------Conditional Branch Operands----------------------------------------
4321 // Comparison Op  - This is the operation of the comparison, and is limited to
4322 //                  the following set of codes:
4323 //                  L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4324 //
4325 // Other attributes of the comparison, such as unsignedness, are specified
4326 // by the comparison instruction that sets a condition code flags register.
4327 // That result is represented by a flags operand whose subtype is appropriate
4328 // to the unsignedness (etc.) of the comparison.
4329 //
4330 // Later, the instruction which matches both the Comparison Op (a Bool) and
4331 // the flags (produced by the Cmp) specifies the coding of the comparison op
4332 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4333 
4334 operand cmpOp() %{
4335   match(Bool);
4336 
4337   format %{ "" %}
4338   interface(COND_INTER) %{
4339     equal(0x1);
4340     not_equal(0x9);
4341     less(0x3);
4342     greater_equal(0xB);
4343     less_equal(0x2);
4344     greater(0xA);
4345     overflow(0x7);
4346     no_overflow(0xF);
4347   %}
4348 %}
4349 
4350 // Comparison Op, unsigned
4351 operand cmpOpU() %{
4352   match(Bool);
4353   predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4354             n->as_Bool()->_test._test != BoolTest::no_overflow);
4355 
4356   format %{ "u" %}
4357   interface(COND_INTER) %{
4358     equal(0x1);
4359     not_equal(0x9);
4360     less(0x5);
4361     greater_equal(0xD);
4362     less_equal(0x4);
4363     greater(0xC);
4364     overflow(0x7);
4365     no_overflow(0xF);
4366   %}
4367 %}
4368 
4369 // Comparison Op, pointer (same as unsigned)
4370 operand cmpOpP() %{
4371   match(Bool);
4372   predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4373             n->as_Bool()->_test._test != BoolTest::no_overflow);
4374 
4375   format %{ "p" %}
4376   interface(COND_INTER) %{
4377     equal(0x1);
4378     not_equal(0x9);
4379     less(0x5);
4380     greater_equal(0xD);
4381     less_equal(0x4);
4382     greater(0xC);
4383     overflow(0x7);
4384     no_overflow(0xF);
4385   %}
4386 %}
4387 
4388 // Comparison Op, branch-register encoding
4389 operand cmpOp_reg() %{
4390   match(Bool);
4391   predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4392             n->as_Bool()->_test._test != BoolTest::no_overflow);
4393 
4394   format %{ "" %}
4395   interface(COND_INTER) %{
4396     equal        (0x1);
4397     not_equal    (0x5);
4398     less         (0x3);
4399     greater_equal(0x7);
4400     less_equal   (0x2);
4401     greater      (0x6);
4402     overflow(0x7); // not supported
4403     no_overflow(0xF); // not supported
4404   %}
4405 %}
4406 
4407 // Comparison Code, floating, unordered same as less
4408 operand cmpOpF() %{
4409   match(Bool);
4410   predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4411             n->as_Bool()->_test._test != BoolTest::no_overflow);
4412 
4413   format %{ "fl" %}
4414   interface(COND_INTER) %{
4415     equal(0x9);
4416     not_equal(0x1);
4417     less(0x3);
4418     greater_equal(0xB);
4419     less_equal(0xE);
4420     greater(0x6);
4421 
4422     overflow(0x7); // not supported
4423     no_overflow(0xF); // not supported
4424   %}
4425 %}
4426 
4427 // Used by long compare
4428 operand cmpOp_commute() %{
4429   match(Bool);
4430   predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4431             n->as_Bool()->_test._test != BoolTest::no_overflow);
4432 
4433   format %{ "" %}
4434   interface(COND_INTER) %{
4435     equal(0x1);
4436     not_equal(0x9);
4437     less(0xA);
4438     greater_equal(0x2);
4439     less_equal(0xB);
4440     greater(0x3);
4441     overflow(0x7);
4442     no_overflow(0xF);
4443   %}
4444 %}
4445 
4446 //----------OPERAND CLASSES----------------------------------------------------
4447 // Operand Classes are groups of operands that are used to simplify
4448 // instruction definitions by not requiring the AD writer to specify separate
4449 // instructions for every form of operand when the instruction accepts
4450 // multiple operand types with the same basic encoding and format.  The classic
4451 // case of this is memory operands.
4452 opclass memory( indirect, indOffset13, indIndex );
4453 opclass indIndexMemory( indIndex );
4454 
4455 //----------PIPELINE-----------------------------------------------------------
4456 pipeline %{
4457 
4458 //----------ATTRIBUTES---------------------------------------------------------
4459 attributes %{
4460   fixed_size_instructions;           // Fixed size instructions
4461   branch_has_delay_slot;             // Branch has delay slot following
4462   max_instructions_per_bundle = 4;   // Up to 4 instructions per bundle
4463   instruction_unit_size = 4;         // An instruction is 4 bytes long
4464   instruction_fetch_unit_size = 16;  // The processor fetches one line
4465   instruction_fetch_units = 1;       // of 16 bytes
4466 
4467   // List of nop instructions
4468   nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR );
4469 %}
4470 
4471 //----------RESOURCES----------------------------------------------------------
4472 // Resources are the functional units available to the machine
4473 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1);
4474 
4475 //----------PIPELINE DESCRIPTION-----------------------------------------------
4476 // Pipeline Description specifies the stages in the machine's pipeline
4477 
4478 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D);
4479 
4480 //----------PIPELINE CLASSES---------------------------------------------------
4481 // Pipeline Classes describe the stages in which input and output are
4482 // referenced by the hardware pipeline.
4483 
4484 // Integer ALU reg-reg operation
4485 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4486     single_instruction;
4487     dst   : E(write);
4488     src1  : R(read);
4489     src2  : R(read);
4490     IALU  : R;
4491 %}
4492 
4493 // Integer ALU reg-reg long operation
4494 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
4495     instruction_count(2);
4496     dst   : E(write);
4497     src1  : R(read);
4498     src2  : R(read);
4499     IALU  : R;
4500     IALU  : R;
4501 %}
4502 
4503 // Integer ALU reg-reg long dependent operation
4504 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
4505     instruction_count(1); multiple_bundles;
4506     dst   : E(write);
4507     src1  : R(read);
4508     src2  : R(read);
4509     cr    : E(write);
4510     IALU  : R(2);
4511 %}
4512 
4513 // Integer ALU reg-imm operaion
4514 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4515     single_instruction;
4516     dst   : E(write);
4517     src1  : R(read);
4518     IALU  : R;
4519 %}
4520 
4521 // Integer ALU reg-reg operation with condition code
4522 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
4523     single_instruction;
4524     dst   : E(write);
4525     cr    : E(write);
4526     src1  : R(read);
4527     src2  : R(read);
4528     IALU  : R;
4529 %}
4530 
4531 // Integer ALU reg-imm operation with condition code
4532 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{
4533     single_instruction;
4534     dst   : E(write);
4535     cr    : E(write);
4536     src1  : R(read);
4537     IALU  : R;
4538 %}
4539 
4540 // Integer ALU zero-reg operation
4541 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
4542     single_instruction;
4543     dst   : E(write);
4544     src2  : R(read);
4545     IALU  : R;
4546 %}
4547 
4548 // Integer ALU zero-reg operation with condition code only
4549 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{
4550     single_instruction;
4551     cr    : E(write);
4552     src   : R(read);
4553     IALU  : R;
4554 %}
4555 
4556 // Integer ALU reg-reg operation with condition code only
4557 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4558     single_instruction;
4559     cr    : E(write);
4560     src1  : R(read);
4561     src2  : R(read);
4562     IALU  : R;
4563 %}
4564 
4565 // Integer ALU reg-imm operation with condition code only
4566 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4567     single_instruction;
4568     cr    : E(write);
4569     src1  : R(read);
4570     IALU  : R;
4571 %}
4572 
4573 // Integer ALU reg-reg-zero operation with condition code only
4574 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{
4575     single_instruction;
4576     cr    : E(write);
4577     src1  : R(read);
4578     src2  : R(read);
4579     IALU  : R;
4580 %}
4581 
4582 // Integer ALU reg-imm-zero operation with condition code only
4583 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{
4584     single_instruction;
4585     cr    : E(write);
4586     src1  : R(read);
4587     IALU  : R;
4588 %}
4589 
4590 // Integer ALU reg-reg operation with condition code, src1 modified
4591 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4592     single_instruction;
4593     cr    : E(write);
4594     src1  : E(write);
4595     src1  : R(read);
4596     src2  : R(read);
4597     IALU  : R;
4598 %}
4599 
4600 // Integer ALU reg-imm operation with condition code, src1 modified
4601 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4602     single_instruction;
4603     cr    : E(write);
4604     src1  : E(write);
4605     src1  : R(read);
4606     IALU  : R;
4607 %}
4608 
4609 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{
4610     multiple_bundles;
4611     dst   : E(write)+4;
4612     cr    : E(write);
4613     src1  : R(read);
4614     src2  : R(read);
4615     IALU  : R(3);
4616     BR    : R(2);
4617 %}
4618 
4619 // Integer ALU operation
4620 pipe_class ialu_none(iRegI dst) %{
4621     single_instruction;
4622     dst   : E(write);
4623     IALU  : R;
4624 %}
4625 
4626 // Integer ALU reg operation
4627 pipe_class ialu_reg(iRegI dst, iRegI src) %{
4628     single_instruction; may_have_no_code;
4629     dst   : E(write);
4630     src   : R(read);
4631     IALU  : R;
4632 %}
4633 
4634 // Integer ALU reg conditional operation
4635 // This instruction has a 1 cycle stall, and cannot execute
4636 // in the same cycle as the instruction setting the condition
4637 // code. We kludge this by pretending to read the condition code
4638 // 1 cycle earlier, and by marking the functional units as busy
4639 // for 2 cycles with the result available 1 cycle later than
4640 // is really the case.
4641 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{
4642     single_instruction;
4643     op2_out : C(write);
4644     op1     : R(read);
4645     cr      : R(read);       // This is really E, with a 1 cycle stall
4646     BR      : R(2);
4647     MS      : R(2);
4648 %}
4649 
4650 #ifdef _LP64
4651 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{
4652     instruction_count(1); multiple_bundles;
4653     dst     : C(write)+1;
4654     src     : R(read)+1;
4655     IALU    : R(1);
4656     BR      : E(2);
4657     MS      : E(2);
4658 %}
4659 #endif
4660 
4661 // Integer ALU reg operation
4662 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{
4663     single_instruction; may_have_no_code;
4664     dst   : E(write);
4665     src   : R(read);
4666     IALU  : R;
4667 %}
4668 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{
4669     single_instruction; may_have_no_code;
4670     dst   : E(write);
4671     src   : R(read);
4672     IALU  : R;
4673 %}
4674 
4675 // Two integer ALU reg operations
4676 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{
4677     instruction_count(2);
4678     dst   : E(write);
4679     src   : R(read);
4680     A0    : R;
4681     A1    : R;
4682 %}
4683 
4684 // Two integer ALU reg operations
4685 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{
4686     instruction_count(2); may_have_no_code;
4687     dst   : E(write);
4688     src   : R(read);
4689     A0    : R;
4690     A1    : R;
4691 %}
4692 
4693 // Integer ALU imm operation
4694 pipe_class ialu_imm(iRegI dst, immI13 src) %{
4695     single_instruction;
4696     dst   : E(write);
4697     IALU  : R;
4698 %}
4699 
4700 // Integer ALU reg-reg with carry operation
4701 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{
4702     single_instruction;
4703     dst   : E(write);
4704     src1  : R(read);
4705     src2  : R(read);
4706     IALU  : R;
4707 %}
4708 
4709 // Integer ALU cc operation
4710 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{
4711     single_instruction;
4712     dst   : E(write);
4713     cc    : R(read);
4714     IALU  : R;
4715 %}
4716 
4717 // Integer ALU cc / second IALU operation
4718 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{
4719     instruction_count(1); multiple_bundles;
4720     dst   : E(write)+1;
4721     src   : R(read);
4722     IALU  : R;
4723 %}
4724 
4725 // Integer ALU cc / second IALU operation
4726 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{
4727     instruction_count(1); multiple_bundles;
4728     dst   : E(write)+1;
4729     p     : R(read);
4730     q     : R(read);
4731     IALU  : R;
4732 %}
4733 
4734 // Integer ALU hi-lo-reg operation
4735 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{
4736     instruction_count(1); multiple_bundles;
4737     dst   : E(write)+1;
4738     IALU  : R(2);
4739 %}
4740 
4741 // Float ALU hi-lo-reg operation (with temp)
4742 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{
4743     instruction_count(1); multiple_bundles;
4744     dst   : E(write)+1;
4745     IALU  : R(2);
4746 %}
4747 
4748 // Long Constant
4749 pipe_class loadConL( iRegL dst, immL src ) %{
4750     instruction_count(2); multiple_bundles;
4751     dst   : E(write)+1;
4752     IALU  : R(2);
4753     IALU  : R(2);
4754 %}
4755 
4756 // Pointer Constant
4757 pipe_class loadConP( iRegP dst, immP src ) %{
4758     instruction_count(0); multiple_bundles;
4759     fixed_latency(6);
4760 %}
4761 
4762 // Polling Address
4763 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{
4764 #ifdef _LP64
4765     instruction_count(0); multiple_bundles;
4766     fixed_latency(6);
4767 #else
4768     dst   : E(write);
4769     IALU  : R;
4770 #endif
4771 %}
4772 
4773 // Long Constant small
4774 pipe_class loadConLlo( iRegL dst, immL src ) %{
4775     instruction_count(2);
4776     dst   : E(write);
4777     IALU  : R;
4778     IALU  : R;
4779 %}
4780 
4781 // [PHH] This is wrong for 64-bit.  See LdImmF/D.
4782 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{
4783     instruction_count(1); multiple_bundles;
4784     src   : R(read);
4785     dst   : M(write)+1;
4786     IALU  : R;
4787     MS    : E;
4788 %}
4789 
4790 // Integer ALU nop operation
4791 pipe_class ialu_nop() %{
4792     single_instruction;
4793     IALU  : R;
4794 %}
4795 
4796 // Integer ALU nop operation
4797 pipe_class ialu_nop_A0() %{
4798     single_instruction;
4799     A0    : R;
4800 %}
4801 
4802 // Integer ALU nop operation
4803 pipe_class ialu_nop_A1() %{
4804     single_instruction;
4805     A1    : R;
4806 %}
4807 
4808 // Integer Multiply reg-reg operation
4809 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4810     single_instruction;
4811     dst   : E(write);
4812     src1  : R(read);
4813     src2  : R(read);
4814     MS    : R(5);
4815 %}
4816 
4817 // Integer Multiply reg-imm operation
4818 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4819     single_instruction;
4820     dst   : E(write);
4821     src1  : R(read);
4822     MS    : R(5);
4823 %}
4824 
4825 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4826     single_instruction;
4827     dst   : E(write)+4;
4828     src1  : R(read);
4829     src2  : R(read);
4830     MS    : R(6);
4831 %}
4832 
4833 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4834     single_instruction;
4835     dst   : E(write)+4;
4836     src1  : R(read);
4837     MS    : R(6);
4838 %}
4839 
4840 // Integer Divide reg-reg
4841 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{
4842     instruction_count(1); multiple_bundles;
4843     dst   : E(write);
4844     temp  : E(write);
4845     src1  : R(read);
4846     src2  : R(read);
4847     temp  : R(read);
4848     MS    : R(38);
4849 %}
4850 
4851 // Integer Divide reg-imm
4852 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{
4853     instruction_count(1); multiple_bundles;
4854     dst   : E(write);
4855     temp  : E(write);
4856     src1  : R(read);
4857     temp  : R(read);
4858     MS    : R(38);
4859 %}
4860 
4861 // Long Divide
4862 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4863     dst  : E(write)+71;
4864     src1 : R(read);
4865     src2 : R(read)+1;
4866     MS   : R(70);
4867 %}
4868 
4869 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4870     dst  : E(write)+71;
4871     src1 : R(read);
4872     MS   : R(70);
4873 %}
4874 
4875 // Floating Point Add Float
4876 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{
4877     single_instruction;
4878     dst   : X(write);
4879     src1  : E(read);
4880     src2  : E(read);
4881     FA    : R;
4882 %}
4883 
4884 // Floating Point Add Double
4885 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{
4886     single_instruction;
4887     dst   : X(write);
4888     src1  : E(read);
4889     src2  : E(read);
4890     FA    : R;
4891 %}
4892 
4893 // Floating Point Conditional Move based on integer flags
4894 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{
4895     single_instruction;
4896     dst   : X(write);
4897     src   : E(read);
4898     cr    : R(read);
4899     FA    : R(2);
4900     BR    : R(2);
4901 %}
4902 
4903 // Floating Point Conditional Move based on integer flags
4904 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{
4905     single_instruction;
4906     dst   : X(write);
4907     src   : E(read);
4908     cr    : R(read);
4909     FA    : R(2);
4910     BR    : R(2);
4911 %}
4912 
4913 // Floating Point Multiply Float
4914 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{
4915     single_instruction;
4916     dst   : X(write);
4917     src1  : E(read);
4918     src2  : E(read);
4919     FM    : R;
4920 %}
4921 
4922 // Floating Point Multiply Double
4923 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{
4924     single_instruction;
4925     dst   : X(write);
4926     src1  : E(read);
4927     src2  : E(read);
4928     FM    : R;
4929 %}
4930 
4931 // Floating Point Divide Float
4932 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{
4933     single_instruction;
4934     dst   : X(write);
4935     src1  : E(read);
4936     src2  : E(read);
4937     FM    : R;
4938     FDIV  : C(14);
4939 %}
4940 
4941 // Floating Point Divide Double
4942 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{
4943     single_instruction;
4944     dst   : X(write);
4945     src1  : E(read);
4946     src2  : E(read);
4947     FM    : R;
4948     FDIV  : C(17);
4949 %}
4950 
4951 // Floating Point Move/Negate/Abs Float
4952 pipe_class faddF_reg(regF dst, regF src) %{
4953     single_instruction;
4954     dst   : W(write);
4955     src   : E(read);
4956     FA    : R(1);
4957 %}
4958 
4959 // Floating Point Move/Negate/Abs Double
4960 pipe_class faddD_reg(regD dst, regD src) %{
4961     single_instruction;
4962     dst   : W(write);
4963     src   : E(read);
4964     FA    : R;
4965 %}
4966 
4967 // Floating Point Convert F->D
4968 pipe_class fcvtF2D(regD dst, regF src) %{
4969     single_instruction;
4970     dst   : X(write);
4971     src   : E(read);
4972     FA    : R;
4973 %}
4974 
4975 // Floating Point Convert I->D
4976 pipe_class fcvtI2D(regD dst, regF src) %{
4977     single_instruction;
4978     dst   : X(write);
4979     src   : E(read);
4980     FA    : R;
4981 %}
4982 
4983 // Floating Point Convert LHi->D
4984 pipe_class fcvtLHi2D(regD dst, regD src) %{
4985     single_instruction;
4986     dst   : X(write);
4987     src   : E(read);
4988     FA    : R;
4989 %}
4990 
4991 // Floating Point Convert L->D
4992 pipe_class fcvtL2D(regD dst, regF src) %{
4993     single_instruction;
4994     dst   : X(write);
4995     src   : E(read);
4996     FA    : R;
4997 %}
4998 
4999 // Floating Point Convert L->F
5000 pipe_class fcvtL2F(regD dst, regF src) %{
5001     single_instruction;
5002     dst   : X(write);
5003     src   : E(read);
5004     FA    : R;
5005 %}
5006 
5007 // Floating Point Convert D->F
5008 pipe_class fcvtD2F(regD dst, regF src) %{
5009     single_instruction;
5010     dst   : X(write);
5011     src   : E(read);
5012     FA    : R;
5013 %}
5014 
5015 // Floating Point Convert I->L
5016 pipe_class fcvtI2L(regD dst, regF src) %{
5017     single_instruction;
5018     dst   : X(write);
5019     src   : E(read);
5020     FA    : R;
5021 %}
5022 
5023 // Floating Point Convert D->F
5024 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{
5025     instruction_count(1); multiple_bundles;
5026     dst   : X(write)+6;
5027     src   : E(read);
5028     FA    : R;
5029 %}
5030 
5031 // Floating Point Convert D->L
5032 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{
5033     instruction_count(1); multiple_bundles;
5034     dst   : X(write)+6;
5035     src   : E(read);
5036     FA    : R;
5037 %}
5038 
5039 // Floating Point Convert F->I
5040 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{
5041     instruction_count(1); multiple_bundles;
5042     dst   : X(write)+6;
5043     src   : E(read);
5044     FA    : R;
5045 %}
5046 
5047 // Floating Point Convert F->L
5048 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{
5049     instruction_count(1); multiple_bundles;
5050     dst   : X(write)+6;
5051     src   : E(read);
5052     FA    : R;
5053 %}
5054 
5055 // Floating Point Convert I->F
5056 pipe_class fcvtI2F(regF dst, regF src) %{
5057     single_instruction;
5058     dst   : X(write);
5059     src   : E(read);
5060     FA    : R;
5061 %}
5062 
5063 // Floating Point Compare
5064 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{
5065     single_instruction;
5066     cr    : X(write);
5067     src1  : E(read);
5068     src2  : E(read);
5069     FA    : R;
5070 %}
5071 
5072 // Floating Point Compare
5073 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{
5074     single_instruction;
5075     cr    : X(write);
5076     src1  : E(read);
5077     src2  : E(read);
5078     FA    : R;
5079 %}
5080 
5081 // Floating Add Nop
5082 pipe_class fadd_nop() %{
5083     single_instruction;
5084     FA  : R;
5085 %}
5086 
5087 // Integer Store to Memory
5088 pipe_class istore_mem_reg(memory mem, iRegI src) %{
5089     single_instruction;
5090     mem   : R(read);
5091     src   : C(read);
5092     MS    : R;
5093 %}
5094 
5095 // Integer Store to Memory
5096 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{
5097     single_instruction;
5098     mem   : R(read);
5099     src   : C(read);
5100     MS    : R;
5101 %}
5102 
5103 // Integer Store Zero to Memory
5104 pipe_class istore_mem_zero(memory mem, immI0 src) %{
5105     single_instruction;
5106     mem   : R(read);
5107     MS    : R;
5108 %}
5109 
5110 // Special Stack Slot Store
5111 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{
5112     single_instruction;
5113     stkSlot : R(read);
5114     src     : C(read);
5115     MS      : R;
5116 %}
5117 
5118 // Special Stack Slot Store
5119 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{
5120     instruction_count(2); multiple_bundles;
5121     stkSlot : R(read);
5122     src     : C(read);
5123     MS      : R(2);
5124 %}
5125 
5126 // Float Store
5127 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{
5128     single_instruction;
5129     mem : R(read);
5130     src : C(read);
5131     MS  : R;
5132 %}
5133 
5134 // Float Store
5135 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{
5136     single_instruction;
5137     mem : R(read);
5138     MS  : R;
5139 %}
5140 
5141 // Double Store
5142 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{
5143     instruction_count(1);
5144     mem : R(read);
5145     src : C(read);
5146     MS  : R;
5147 %}
5148 
5149 // Double Store
5150 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{
5151     single_instruction;
5152     mem : R(read);
5153     MS  : R;
5154 %}
5155 
5156 // Special Stack Slot Float Store
5157 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{
5158     single_instruction;
5159     stkSlot : R(read);
5160     src     : C(read);
5161     MS      : R;
5162 %}
5163 
5164 // Special Stack Slot Double Store
5165 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{
5166     single_instruction;
5167     stkSlot : R(read);
5168     src     : C(read);
5169     MS      : R;
5170 %}
5171 
5172 // Integer Load (when sign bit propagation not needed)
5173 pipe_class iload_mem(iRegI dst, memory mem) %{
5174     single_instruction;
5175     mem : R(read);
5176     dst : C(write);
5177     MS  : R;
5178 %}
5179 
5180 // Integer Load from stack operand
5181 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{
5182     single_instruction;
5183     mem : R(read);
5184     dst : C(write);
5185     MS  : R;
5186 %}
5187 
5188 // Integer Load (when sign bit propagation or masking is needed)
5189 pipe_class iload_mask_mem(iRegI dst, memory mem) %{
5190     single_instruction;
5191     mem : R(read);
5192     dst : M(write);
5193     MS  : R;
5194 %}
5195 
5196 // Float Load
5197 pipe_class floadF_mem(regF dst, memory mem) %{
5198     single_instruction;
5199     mem : R(read);
5200     dst : M(write);
5201     MS  : R;
5202 %}
5203 
5204 // Float Load
5205 pipe_class floadD_mem(regD dst, memory mem) %{
5206     instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case
5207     mem : R(read);
5208     dst : M(write);
5209     MS  : R;
5210 %}
5211 
5212 // Float Load
5213 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{
5214     single_instruction;
5215     stkSlot : R(read);
5216     dst : M(write);
5217     MS  : R;
5218 %}
5219 
5220 // Float Load
5221 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{
5222     single_instruction;
5223     stkSlot : R(read);
5224     dst : M(write);
5225     MS  : R;
5226 %}
5227 
5228 // Memory Nop
5229 pipe_class mem_nop() %{
5230     single_instruction;
5231     MS  : R;
5232 %}
5233 
5234 pipe_class sethi(iRegP dst, immI src) %{
5235     single_instruction;
5236     dst  : E(write);
5237     IALU : R;
5238 %}
5239 
5240 pipe_class loadPollP(iRegP poll) %{
5241     single_instruction;
5242     poll : R(read);
5243     MS   : R;
5244 %}
5245 
5246 pipe_class br(Universe br, label labl) %{
5247     single_instruction_with_delay_slot;
5248     BR  : R;
5249 %}
5250 
5251 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{
5252     single_instruction_with_delay_slot;
5253     cr    : E(read);
5254     BR    : R;
5255 %}
5256 
5257 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{
5258     single_instruction_with_delay_slot;
5259     op1 : E(read);
5260     BR  : R;
5261     MS  : R;
5262 %}
5263 
5264 // Compare and branch
5265 pipe_class cmp_br_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
5266     instruction_count(2); has_delay_slot;
5267     cr    : E(write);
5268     src1  : R(read);
5269     src2  : R(read);
5270     IALU  : R;
5271     BR    : R;
5272 %}
5273 
5274 // Compare and branch
5275 pipe_class cmp_br_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI13 src2, label labl, flagsReg cr) %{
5276     instruction_count(2); has_delay_slot;
5277     cr    : E(write);
5278     src1  : R(read);
5279     IALU  : R;
5280     BR    : R;
5281 %}
5282 
5283 // Compare and branch using cbcond
5284 pipe_class cbcond_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl) %{
5285     single_instruction;
5286     src1  : E(read);
5287     src2  : E(read);
5288     IALU  : R;
5289     BR    : R;
5290 %}
5291 
5292 // Compare and branch using cbcond
5293 pipe_class cbcond_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI5 src2, label labl) %{
5294     single_instruction;
5295     src1  : E(read);
5296     IALU  : R;
5297     BR    : R;
5298 %}
5299 
5300 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{
5301     single_instruction_with_delay_slot;
5302     cr    : E(read);
5303     BR    : R;
5304 %}
5305 
5306 pipe_class br_nop() %{
5307     single_instruction;
5308     BR  : R;
5309 %}
5310 
5311 pipe_class simple_call(method meth) %{
5312     instruction_count(2); multiple_bundles; force_serialization;
5313     fixed_latency(100);
5314     BR  : R(1);
5315     MS  : R(1);
5316     A0  : R(1);
5317 %}
5318 
5319 pipe_class compiled_call(method meth) %{
5320     instruction_count(1); multiple_bundles; force_serialization;
5321     fixed_latency(100);
5322     MS  : R(1);
5323 %}
5324 
5325 pipe_class call(method meth) %{
5326     instruction_count(0); multiple_bundles; force_serialization;
5327     fixed_latency(100);
5328 %}
5329 
5330 pipe_class tail_call(Universe ignore, label labl) %{
5331     single_instruction; has_delay_slot;
5332     fixed_latency(100);
5333     BR  : R(1);
5334     MS  : R(1);
5335 %}
5336 
5337 pipe_class ret(Universe ignore) %{
5338     single_instruction; has_delay_slot;
5339     BR  : R(1);
5340     MS  : R(1);
5341 %}
5342 
5343 pipe_class ret_poll(g3RegP poll) %{
5344     instruction_count(3); has_delay_slot;
5345     poll : E(read);
5346     MS   : R;
5347 %}
5348 
5349 // The real do-nothing guy
5350 pipe_class empty( ) %{
5351     instruction_count(0);
5352 %}
5353 
5354 pipe_class long_memory_op() %{
5355     instruction_count(0); multiple_bundles; force_serialization;
5356     fixed_latency(25);
5357     MS  : R(1);
5358 %}
5359 
5360 // Check-cast
5361 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{
5362     array : R(read);
5363     match  : R(read);
5364     IALU   : R(2);
5365     BR     : R(2);
5366     MS     : R;
5367 %}
5368 
5369 // Convert FPU flags into +1,0,-1
5370 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{
5371     src1  : E(read);
5372     src2  : E(read);
5373     dst   : E(write);
5374     FA    : R;
5375     MS    : R(2);
5376     BR    : R(2);
5377 %}
5378 
5379 // Compare for p < q, and conditionally add y
5380 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{
5381     p     : E(read);
5382     q     : E(read);
5383     y     : E(read);
5384     IALU  : R(3)
5385 %}
5386 
5387 // Perform a compare, then move conditionally in a branch delay slot.
5388 pipe_class min_max( iRegI src2, iRegI srcdst ) %{
5389     src2   : E(read);
5390     srcdst : E(read);
5391     IALU   : R;
5392     BR     : R;
5393 %}
5394 
5395 // Define the class for the Nop node
5396 define %{
5397    MachNop = ialu_nop;
5398 %}
5399 
5400 %}
5401 
5402 //----------INSTRUCTIONS-------------------------------------------------------
5403 
5404 //------------Special Stack Slot instructions - no match rules-----------------
5405 instruct stkI_to_regF(regF dst, stackSlotI src) %{
5406   // No match rule to avoid chain rule match.
5407   effect(DEF dst, USE src);
5408   ins_cost(MEMORY_REF_COST);
5409   size(4);
5410   format %{ "LDF    $src,$dst\t! stkI to regF" %}
5411   opcode(Assembler::ldf_op3);
5412   ins_encode(simple_form3_mem_reg(src, dst));
5413   ins_pipe(floadF_stk);
5414 %}
5415 
5416 instruct stkL_to_regD(regD dst, stackSlotL src) %{
5417   // No match rule to avoid chain rule match.
5418   effect(DEF dst, USE src);
5419   ins_cost(MEMORY_REF_COST);
5420   size(4);
5421   format %{ "LDDF   $src,$dst\t! stkL to regD" %}
5422   opcode(Assembler::lddf_op3);
5423   ins_encode(simple_form3_mem_reg(src, dst));
5424   ins_pipe(floadD_stk);
5425 %}
5426 
5427 instruct regF_to_stkI(stackSlotI dst, regF src) %{
5428   // No match rule to avoid chain rule match.
5429   effect(DEF dst, USE src);
5430   ins_cost(MEMORY_REF_COST);
5431   size(4);
5432   format %{ "STF    $src,$dst\t! regF to stkI" %}
5433   opcode(Assembler::stf_op3);
5434   ins_encode(simple_form3_mem_reg(dst, src));
5435   ins_pipe(fstoreF_stk_reg);
5436 %}
5437 
5438 instruct regD_to_stkL(stackSlotL dst, regD src) %{
5439   // No match rule to avoid chain rule match.
5440   effect(DEF dst, USE src);
5441   ins_cost(MEMORY_REF_COST);
5442   size(4);
5443   format %{ "STDF   $src,$dst\t! regD to stkL" %}
5444   opcode(Assembler::stdf_op3);
5445   ins_encode(simple_form3_mem_reg(dst, src));
5446   ins_pipe(fstoreD_stk_reg);
5447 %}
5448 
5449 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{
5450   effect(DEF dst, USE src);
5451   ins_cost(MEMORY_REF_COST*2);
5452   size(8);
5453   format %{ "STW    $src,$dst.hi\t! long\n\t"
5454             "STW    R_G0,$dst.lo" %}
5455   opcode(Assembler::stw_op3);
5456   ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0));
5457   ins_pipe(lstoreI_stk_reg);
5458 %}
5459 
5460 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{
5461   // No match rule to avoid chain rule match.
5462   effect(DEF dst, USE src);
5463   ins_cost(MEMORY_REF_COST);
5464   size(4);
5465   format %{ "STX    $src,$dst\t! regL to stkD" %}
5466   opcode(Assembler::stx_op3);
5467   ins_encode(simple_form3_mem_reg( dst, src ) );
5468   ins_pipe(istore_stk_reg);
5469 %}
5470 
5471 //---------- Chain stack slots between similar types --------
5472 
5473 // Load integer from stack slot
5474 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{
5475   match(Set dst src);
5476   ins_cost(MEMORY_REF_COST);
5477 
5478   size(4);
5479   format %{ "LDUW   $src,$dst\t!stk" %}
5480   opcode(Assembler::lduw_op3);
5481   ins_encode(simple_form3_mem_reg( src, dst ) );
5482   ins_pipe(iload_mem);
5483 %}
5484 
5485 // Store integer to stack slot
5486 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{
5487   match(Set dst src);
5488   ins_cost(MEMORY_REF_COST);
5489 
5490   size(4);
5491   format %{ "STW    $src,$dst\t!stk" %}
5492   opcode(Assembler::stw_op3);
5493   ins_encode(simple_form3_mem_reg( dst, src ) );
5494   ins_pipe(istore_mem_reg);
5495 %}
5496 
5497 // Load long from stack slot
5498 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{
5499   match(Set dst src);
5500 
5501   ins_cost(MEMORY_REF_COST);
5502   size(4);
5503   format %{ "LDX    $src,$dst\t! long" %}
5504   opcode(Assembler::ldx_op3);
5505   ins_encode(simple_form3_mem_reg( src, dst ) );
5506   ins_pipe(iload_mem);
5507 %}
5508 
5509 // Store long to stack slot
5510 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
5511   match(Set dst src);
5512 
5513   ins_cost(MEMORY_REF_COST);
5514   size(4);
5515   format %{ "STX    $src,$dst\t! long" %}
5516   opcode(Assembler::stx_op3);
5517   ins_encode(simple_form3_mem_reg( dst, src ) );
5518   ins_pipe(istore_mem_reg);
5519 %}
5520 
5521 #ifdef _LP64
5522 // Load pointer from stack slot, 64-bit encoding
5523 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5524   match(Set dst src);
5525   ins_cost(MEMORY_REF_COST);
5526   size(4);
5527   format %{ "LDX    $src,$dst\t!ptr" %}
5528   opcode(Assembler::ldx_op3);
5529   ins_encode(simple_form3_mem_reg( src, dst ) );
5530   ins_pipe(iload_mem);
5531 %}
5532 
5533 // Store pointer to stack slot
5534 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5535   match(Set dst src);
5536   ins_cost(MEMORY_REF_COST);
5537   size(4);
5538   format %{ "STX    $src,$dst\t!ptr" %}
5539   opcode(Assembler::stx_op3);
5540   ins_encode(simple_form3_mem_reg( dst, src ) );
5541   ins_pipe(istore_mem_reg);
5542 %}
5543 #else // _LP64
5544 // Load pointer from stack slot, 32-bit encoding
5545 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5546   match(Set dst src);
5547   ins_cost(MEMORY_REF_COST);
5548   format %{ "LDUW   $src,$dst\t!ptr" %}
5549   opcode(Assembler::lduw_op3, Assembler::ldst_op);
5550   ins_encode(simple_form3_mem_reg( src, dst ) );
5551   ins_pipe(iload_mem);
5552 %}
5553 
5554 // Store pointer to stack slot
5555 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5556   match(Set dst src);
5557   ins_cost(MEMORY_REF_COST);
5558   format %{ "STW    $src,$dst\t!ptr" %}
5559   opcode(Assembler::stw_op3, Assembler::ldst_op);
5560   ins_encode(simple_form3_mem_reg( dst, src ) );
5561   ins_pipe(istore_mem_reg);
5562 %}
5563 #endif // _LP64
5564 
5565 //------------Special Nop instructions for bundling - no match rules-----------
5566 // Nop using the A0 functional unit
5567 instruct Nop_A0() %{
5568   ins_cost(0);
5569 
5570   format %{ "NOP    ! Alu Pipeline" %}
5571   opcode(Assembler::or_op3, Assembler::arith_op);
5572   ins_encode( form2_nop() );
5573   ins_pipe(ialu_nop_A0);
5574 %}
5575 
5576 // Nop using the A1 functional unit
5577 instruct Nop_A1( ) %{
5578   ins_cost(0);
5579 
5580   format %{ "NOP    ! Alu Pipeline" %}
5581   opcode(Assembler::or_op3, Assembler::arith_op);
5582   ins_encode( form2_nop() );
5583   ins_pipe(ialu_nop_A1);
5584 %}
5585 
5586 // Nop using the memory functional unit
5587 instruct Nop_MS( ) %{
5588   ins_cost(0);
5589 
5590   format %{ "NOP    ! Memory Pipeline" %}
5591   ins_encode( emit_mem_nop );
5592   ins_pipe(mem_nop);
5593 %}
5594 
5595 // Nop using the floating add functional unit
5596 instruct Nop_FA( ) %{
5597   ins_cost(0);
5598 
5599   format %{ "NOP    ! Floating Add Pipeline" %}
5600   ins_encode( emit_fadd_nop );
5601   ins_pipe(fadd_nop);
5602 %}
5603 
5604 // Nop using the branch functional unit
5605 instruct Nop_BR( ) %{
5606   ins_cost(0);
5607 
5608   format %{ "NOP    ! Branch Pipeline" %}
5609   ins_encode( emit_br_nop );
5610   ins_pipe(br_nop);
5611 %}
5612 
5613 //----------Load/Store/Move Instructions---------------------------------------
5614 //----------Load Instructions--------------------------------------------------
5615 // Load Byte (8bit signed)
5616 instruct loadB(iRegI dst, memory mem) %{
5617   match(Set dst (LoadB mem));
5618   ins_cost(MEMORY_REF_COST);
5619 
5620   size(4);
5621   format %{ "LDSB   $mem,$dst\t! byte" %}
5622   ins_encode %{
5623     __ ldsb($mem$$Address, $dst$$Register);
5624   %}
5625   ins_pipe(iload_mask_mem);
5626 %}
5627 
5628 // Load Byte (8bit signed) into a Long Register
5629 instruct loadB2L(iRegL dst, memory mem) %{
5630   match(Set dst (ConvI2L (LoadB mem)));
5631   ins_cost(MEMORY_REF_COST);
5632 
5633   size(4);
5634   format %{ "LDSB   $mem,$dst\t! byte -> long" %}
5635   ins_encode %{
5636     __ ldsb($mem$$Address, $dst$$Register);
5637   %}
5638   ins_pipe(iload_mask_mem);
5639 %}
5640 
5641 // Load Unsigned Byte (8bit UNsigned) into an int reg
5642 instruct loadUB(iRegI dst, memory mem) %{
5643   match(Set dst (LoadUB mem));
5644   ins_cost(MEMORY_REF_COST);
5645 
5646   size(4);
5647   format %{ "LDUB   $mem,$dst\t! ubyte" %}
5648   ins_encode %{
5649     __ ldub($mem$$Address, $dst$$Register);
5650   %}
5651   ins_pipe(iload_mem);
5652 %}
5653 
5654 // Load Unsigned Byte (8bit UNsigned) into a Long Register
5655 instruct loadUB2L(iRegL dst, memory mem) %{
5656   match(Set dst (ConvI2L (LoadUB mem)));
5657   ins_cost(MEMORY_REF_COST);
5658 
5659   size(4);
5660   format %{ "LDUB   $mem,$dst\t! ubyte -> long" %}
5661   ins_encode %{
5662     __ ldub($mem$$Address, $dst$$Register);
5663   %}
5664   ins_pipe(iload_mem);
5665 %}
5666 
5667 // Load Unsigned Byte (8 bit UNsigned) with 8-bit mask into Long Register
5668 instruct loadUB2L_immI8(iRegL dst, memory mem, immI8 mask) %{
5669   match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5670   ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5671 
5672   size(2*4);
5673   format %{ "LDUB   $mem,$dst\t# ubyte & 8-bit mask -> long\n\t"
5674             "AND    $dst,$mask,$dst" %}
5675   ins_encode %{
5676     __ ldub($mem$$Address, $dst$$Register);
5677     __ and3($dst$$Register, $mask$$constant, $dst$$Register);
5678   %}
5679   ins_pipe(iload_mem);
5680 %}
5681 
5682 // Load Short (16bit signed)
5683 instruct loadS(iRegI dst, memory mem) %{
5684   match(Set dst (LoadS mem));
5685   ins_cost(MEMORY_REF_COST);
5686 
5687   size(4);
5688   format %{ "LDSH   $mem,$dst\t! short" %}
5689   ins_encode %{
5690     __ ldsh($mem$$Address, $dst$$Register);
5691   %}
5692   ins_pipe(iload_mask_mem);
5693 %}
5694 
5695 // Load Short (16 bit signed) to Byte (8 bit signed)
5696 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5697   match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5698   ins_cost(MEMORY_REF_COST);
5699 
5700   size(4);
5701 
5702   format %{ "LDSB   $mem+1,$dst\t! short -> byte" %}
5703   ins_encode %{
5704     __ ldsb($mem$$Address, $dst$$Register, 1);
5705   %}
5706   ins_pipe(iload_mask_mem);
5707 %}
5708 
5709 // Load Short (16bit signed) into a Long Register
5710 instruct loadS2L(iRegL dst, memory mem) %{
5711   match(Set dst (ConvI2L (LoadS mem)));
5712   ins_cost(MEMORY_REF_COST);
5713 
5714   size(4);
5715   format %{ "LDSH   $mem,$dst\t! short -> long" %}
5716   ins_encode %{
5717     __ ldsh($mem$$Address, $dst$$Register);
5718   %}
5719   ins_pipe(iload_mask_mem);
5720 %}
5721 
5722 // Load Unsigned Short/Char (16bit UNsigned)
5723 instruct loadUS(iRegI dst, memory mem) %{
5724   match(Set dst (LoadUS mem));
5725   ins_cost(MEMORY_REF_COST);
5726 
5727   size(4);
5728   format %{ "LDUH   $mem,$dst\t! ushort/char" %}
5729   ins_encode %{
5730     __ lduh($mem$$Address, $dst$$Register);
5731   %}
5732   ins_pipe(iload_mem);
5733 %}
5734 
5735 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5736 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5737   match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5738   ins_cost(MEMORY_REF_COST);
5739 
5740   size(4);
5741   format %{ "LDSB   $mem+1,$dst\t! ushort -> byte" %}
5742   ins_encode %{
5743     __ ldsb($mem$$Address, $dst$$Register, 1);
5744   %}
5745   ins_pipe(iload_mask_mem);
5746 %}
5747 
5748 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register
5749 instruct loadUS2L(iRegL dst, memory mem) %{
5750   match(Set dst (ConvI2L (LoadUS mem)));
5751   ins_cost(MEMORY_REF_COST);
5752 
5753   size(4);
5754   format %{ "LDUH   $mem,$dst\t! ushort/char -> long" %}
5755   ins_encode %{
5756     __ lduh($mem$$Address, $dst$$Register);
5757   %}
5758   ins_pipe(iload_mem);
5759 %}
5760 
5761 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register
5762 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5763   match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5764   ins_cost(MEMORY_REF_COST);
5765 
5766   size(4);
5767   format %{ "LDUB   $mem+1,$dst\t! ushort/char & 0xFF -> long" %}
5768   ins_encode %{
5769     __ ldub($mem$$Address, $dst$$Register, 1);  // LSB is index+1 on BE
5770   %}
5771   ins_pipe(iload_mem);
5772 %}
5773 
5774 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register
5775 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5776   match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5777   ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5778 
5779   size(2*4);
5780   format %{ "LDUH   $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t"
5781             "AND    $dst,$mask,$dst" %}
5782   ins_encode %{
5783     Register Rdst = $dst$$Register;
5784     __ lduh($mem$$Address, Rdst);
5785     __ and3(Rdst, $mask$$constant, Rdst);
5786   %}
5787   ins_pipe(iload_mem);
5788 %}
5789 
5790 // Load Unsigned Short/Char (16bit UNsigned) with a 16-bit mask into a Long Register
5791 instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{
5792   match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5793   effect(TEMP dst, TEMP tmp);
5794   ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5795 
5796   format %{ "LDUH   $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t"
5797             "SET    $mask,$tmp\n\t"
5798             "AND    $dst,$tmp,$dst" %}
5799   ins_encode %{
5800     Register Rdst = $dst$$Register;
5801     Register Rtmp = $tmp$$Register;
5802     __ lduh($mem$$Address, Rdst);
5803     __ set($mask$$constant, Rtmp);
5804     __ and3(Rdst, Rtmp, Rdst);
5805   %}
5806   ins_pipe(iload_mem);
5807 %}
5808 
5809 // Load Integer
5810 instruct loadI(iRegI dst, memory mem) %{
5811   match(Set dst (LoadI mem));
5812   ins_cost(MEMORY_REF_COST);
5813 
5814   size(4);
5815   format %{ "LDUW   $mem,$dst\t! int" %}
5816   ins_encode %{
5817     __ lduw($mem$$Address, $dst$$Register);
5818   %}
5819   ins_pipe(iload_mem);
5820 %}
5821 
5822 // Load Integer to Byte (8 bit signed)
5823 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5824   match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5825   ins_cost(MEMORY_REF_COST);
5826 
5827   size(4);
5828 
5829   format %{ "LDSB   $mem+3,$dst\t! int -> byte" %}
5830   ins_encode %{
5831     __ ldsb($mem$$Address, $dst$$Register, 3);
5832   %}
5833   ins_pipe(iload_mask_mem);
5834 %}
5835 
5836 // Load Integer to Unsigned Byte (8 bit UNsigned)
5837 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{
5838   match(Set dst (AndI (LoadI mem) mask));
5839   ins_cost(MEMORY_REF_COST);
5840 
5841   size(4);
5842 
5843   format %{ "LDUB   $mem+3,$dst\t! int -> ubyte" %}
5844   ins_encode %{
5845     __ ldub($mem$$Address, $dst$$Register, 3);
5846   %}
5847   ins_pipe(iload_mask_mem);
5848 %}
5849 
5850 // Load Integer to Short (16 bit signed)
5851 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{
5852   match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5853   ins_cost(MEMORY_REF_COST);
5854 
5855   size(4);
5856 
5857   format %{ "LDSH   $mem+2,$dst\t! int -> short" %}
5858   ins_encode %{
5859     __ ldsh($mem$$Address, $dst$$Register, 2);
5860   %}
5861   ins_pipe(iload_mask_mem);
5862 %}
5863 
5864 // Load Integer to Unsigned Short (16 bit UNsigned)
5865 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{
5866   match(Set dst (AndI (LoadI mem) mask));
5867   ins_cost(MEMORY_REF_COST);
5868 
5869   size(4);
5870 
5871   format %{ "LDUH   $mem+2,$dst\t! int -> ushort/char" %}
5872   ins_encode %{
5873     __ lduh($mem$$Address, $dst$$Register, 2);
5874   %}
5875   ins_pipe(iload_mask_mem);
5876 %}
5877 
5878 // Load Integer into a Long Register
5879 instruct loadI2L(iRegL dst, memory mem) %{
5880   match(Set dst (ConvI2L (LoadI mem)));
5881   ins_cost(MEMORY_REF_COST);
5882 
5883   size(4);
5884   format %{ "LDSW   $mem,$dst\t! int -> long" %}
5885   ins_encode %{
5886     __ ldsw($mem$$Address, $dst$$Register);
5887   %}
5888   ins_pipe(iload_mask_mem);
5889 %}
5890 
5891 // Load Integer with mask 0xFF into a Long Register
5892 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5893   match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5894   ins_cost(MEMORY_REF_COST);
5895 
5896   size(4);
5897   format %{ "LDUB   $mem+3,$dst\t! int & 0xFF -> long" %}
5898   ins_encode %{
5899     __ ldub($mem$$Address, $dst$$Register, 3);  // LSB is index+3 on BE
5900   %}
5901   ins_pipe(iload_mem);
5902 %}
5903 
5904 // Load Integer with mask 0xFFFF into a Long Register
5905 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{
5906   match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5907   ins_cost(MEMORY_REF_COST);
5908 
5909   size(4);
5910   format %{ "LDUH   $mem+2,$dst\t! int & 0xFFFF -> long" %}
5911   ins_encode %{
5912     __ lduh($mem$$Address, $dst$$Register, 2);  // LSW is index+2 on BE
5913   %}
5914   ins_pipe(iload_mem);
5915 %}
5916 
5917 // Load Integer with a 12-bit mask into a Long Register
5918 instruct loadI2L_immU12(iRegL dst, memory mem, immU12 mask) %{
5919   match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5920   ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5921 
5922   size(2*4);
5923   format %{ "LDUW   $mem,$dst\t! int & 12-bit mask -> long\n\t"
5924             "AND    $dst,$mask,$dst" %}
5925   ins_encode %{
5926     Register Rdst = $dst$$Register;
5927     __ lduw($mem$$Address, Rdst);
5928     __ and3(Rdst, $mask$$constant, Rdst);
5929   %}
5930   ins_pipe(iload_mem);
5931 %}
5932 
5933 // Load Integer with a 31-bit mask into a Long Register
5934 instruct loadI2L_immU31(iRegL dst, memory mem, immU31 mask, iRegL tmp) %{
5935   match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5936   effect(TEMP dst, TEMP tmp);
5937   ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5938 
5939   format %{ "LDUW   $mem,$dst\t! int & 31-bit mask -> long\n\t"
5940             "SET    $mask,$tmp\n\t"
5941             "AND    $dst,$tmp,$dst" %}
5942   ins_encode %{
5943     Register Rdst = $dst$$Register;
5944     Register Rtmp = $tmp$$Register;
5945     __ lduw($mem$$Address, Rdst);
5946     __ set($mask$$constant, Rtmp);
5947     __ and3(Rdst, Rtmp, Rdst);
5948   %}
5949   ins_pipe(iload_mem);
5950 %}
5951 
5952 // Load Unsigned Integer into a Long Register
5953 instruct loadUI2L(iRegL dst, memory mem, immL_32bits mask) %{
5954   match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5955   ins_cost(MEMORY_REF_COST);
5956 
5957   size(4);
5958   format %{ "LDUW   $mem,$dst\t! uint -> long" %}
5959   ins_encode %{
5960     __ lduw($mem$$Address, $dst$$Register);
5961   %}
5962   ins_pipe(iload_mem);
5963 %}
5964 
5965 // Load Long - aligned
5966 instruct loadL(iRegL dst, memory mem ) %{
5967   match(Set dst (LoadL mem));
5968   ins_cost(MEMORY_REF_COST);
5969 
5970   size(4);
5971   format %{ "LDX    $mem,$dst\t! long" %}
5972   ins_encode %{
5973     __ ldx($mem$$Address, $dst$$Register);
5974   %}
5975   ins_pipe(iload_mem);
5976 %}
5977 
5978 // Load Long - UNaligned
5979 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{
5980   match(Set dst (LoadL_unaligned mem));
5981   effect(KILL tmp);
5982   ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5983   size(16);
5984   format %{ "LDUW   $mem+4,R_O7\t! misaligned long\n"
5985           "\tLDUW   $mem  ,$dst\n"
5986           "\tSLLX   #32, $dst, $dst\n"
5987           "\tOR     $dst, R_O7, $dst" %}
5988   opcode(Assembler::lduw_op3);
5989   ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst ));
5990   ins_pipe(iload_mem);
5991 %}
5992 
5993 // Load Range
5994 instruct loadRange(iRegI dst, memory mem) %{
5995   match(Set dst (LoadRange mem));
5996   ins_cost(MEMORY_REF_COST);
5997 
5998   size(4);
5999   format %{ "LDUW   $mem,$dst\t! range" %}
6000   opcode(Assembler::lduw_op3);
6001   ins_encode(simple_form3_mem_reg( mem, dst ) );
6002   ins_pipe(iload_mem);
6003 %}
6004 
6005 // Load Integer into %f register (for fitos/fitod)
6006 instruct loadI_freg(regF dst, memory mem) %{
6007   match(Set dst (LoadI mem));
6008   ins_cost(MEMORY_REF_COST);
6009   size(4);
6010 
6011   format %{ "LDF    $mem,$dst\t! for fitos/fitod" %}
6012   opcode(Assembler::ldf_op3);
6013   ins_encode(simple_form3_mem_reg( mem, dst ) );
6014   ins_pipe(floadF_mem);
6015 %}
6016 
6017 // Load Pointer
6018 instruct loadP(iRegP dst, memory mem) %{
6019   match(Set dst (LoadP mem));
6020   ins_cost(MEMORY_REF_COST);
6021   size(4);
6022 
6023 #ifndef _LP64
6024   format %{ "LDUW   $mem,$dst\t! ptr" %}
6025   ins_encode %{
6026     __ lduw($mem$$Address, $dst$$Register);
6027   %}
6028 #else
6029   format %{ "LDX    $mem,$dst\t! ptr" %}
6030   ins_encode %{
6031     __ ldx($mem$$Address, $dst$$Register);
6032   %}
6033 #endif
6034   ins_pipe(iload_mem);
6035 %}
6036 
6037 // Load Compressed Pointer
6038 instruct loadN(iRegN dst, memory mem) %{
6039   match(Set dst (LoadN mem));
6040   ins_cost(MEMORY_REF_COST);
6041   size(4);
6042 
6043   format %{ "LDUW   $mem,$dst\t! compressed ptr" %}
6044   ins_encode %{
6045     __ lduw($mem$$Address, $dst$$Register);
6046   %}
6047   ins_pipe(iload_mem);
6048 %}
6049 
6050 // Load Klass Pointer
6051 instruct loadKlass(iRegP dst, memory mem) %{
6052   match(Set dst (LoadKlass mem));
6053   ins_cost(MEMORY_REF_COST);
6054   size(4);
6055 
6056 #ifndef _LP64
6057   format %{ "LDUW   $mem,$dst\t! klass ptr" %}
6058   ins_encode %{
6059     __ lduw($mem$$Address, $dst$$Register);
6060   %}
6061 #else
6062   format %{ "LDX    $mem,$dst\t! klass ptr" %}
6063   ins_encode %{
6064     __ ldx($mem$$Address, $dst$$Register);
6065   %}
6066 #endif
6067   ins_pipe(iload_mem);
6068 %}
6069 
6070 // Load narrow Klass Pointer
6071 instruct loadNKlass(iRegN dst, memory mem) %{
6072   match(Set dst (LoadNKlass mem));
6073   ins_cost(MEMORY_REF_COST);
6074   size(4);
6075 
6076   format %{ "LDUW   $mem,$dst\t! compressed klass ptr" %}
6077   ins_encode %{
6078     __ lduw($mem$$Address, $dst$$Register);
6079   %}
6080   ins_pipe(iload_mem);
6081 %}
6082 
6083 // Load Double
6084 instruct loadD(regD dst, memory mem) %{
6085   match(Set dst (LoadD mem));
6086   ins_cost(MEMORY_REF_COST);
6087 
6088   size(4);
6089   format %{ "LDDF   $mem,$dst" %}
6090   opcode(Assembler::lddf_op3);
6091   ins_encode(simple_form3_mem_reg( mem, dst ) );
6092   ins_pipe(floadD_mem);
6093 %}
6094 
6095 // Load Double - UNaligned
6096 instruct loadD_unaligned(regD_low dst, memory mem ) %{
6097   match(Set dst (LoadD_unaligned mem));
6098   ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
6099   size(8);
6100   format %{ "LDF    $mem  ,$dst.hi\t! misaligned double\n"
6101           "\tLDF    $mem+4,$dst.lo\t!" %}
6102   opcode(Assembler::ldf_op3);
6103   ins_encode( form3_mem_reg_double_unaligned( mem, dst ));
6104   ins_pipe(iload_mem);
6105 %}
6106 
6107 // Load Float
6108 instruct loadF(regF dst, memory mem) %{
6109   match(Set dst (LoadF mem));
6110   ins_cost(MEMORY_REF_COST);
6111 
6112   size(4);
6113   format %{ "LDF    $mem,$dst" %}
6114   opcode(Assembler::ldf_op3);
6115   ins_encode(simple_form3_mem_reg( mem, dst ) );
6116   ins_pipe(floadF_mem);
6117 %}
6118 
6119 // Load Constant
6120 instruct loadConI( iRegI dst, immI src ) %{
6121   match(Set dst src);
6122   ins_cost(DEFAULT_COST * 3/2);
6123   format %{ "SET    $src,$dst" %}
6124   ins_encode( Set32(src, dst) );
6125   ins_pipe(ialu_hi_lo_reg);
6126 %}
6127 
6128 instruct loadConI13( iRegI dst, immI13 src ) %{
6129   match(Set dst src);
6130 
6131   size(4);
6132   format %{ "MOV    $src,$dst" %}
6133   ins_encode( Set13( src, dst ) );
6134   ins_pipe(ialu_imm);
6135 %}
6136 
6137 #ifndef _LP64
6138 instruct loadConP(iRegP dst, immP con) %{
6139   match(Set dst con);
6140   ins_cost(DEFAULT_COST * 3/2);
6141   format %{ "SET    $con,$dst\t!ptr" %}
6142   ins_encode %{
6143     relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc();
6144       intptr_t val = $con$$constant;
6145     if (constant_reloc == relocInfo::oop_type) {
6146       __ set_oop_constant((jobject) val, $dst$$Register);
6147     } else if (constant_reloc == relocInfo::metadata_type) {
6148       __ set_metadata_constant((Metadata*)val, $dst$$Register);
6149     } else {          // non-oop pointers, e.g. card mark base, heap top
6150       assert(constant_reloc == relocInfo::none, "unexpected reloc type");
6151       __ set(val, $dst$$Register);
6152     }
6153   %}
6154   ins_pipe(loadConP);
6155 %}
6156 #else
6157 instruct loadConP_set(iRegP dst, immP_set con) %{
6158   match(Set dst con);
6159   ins_cost(DEFAULT_COST * 3/2);
6160   format %{ "SET    $con,$dst\t! ptr" %}
6161   ins_encode %{
6162     relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc();
6163       intptr_t val = $con$$constant;
6164     if (constant_reloc == relocInfo::oop_type) {
6165       __ set_oop_constant((jobject) val, $dst$$Register);
6166     } else if (constant_reloc == relocInfo::metadata_type) {
6167       __ set_metadata_constant((Metadata*)val, $dst$$Register);
6168     } else {          // non-oop pointers, e.g. card mark base, heap top
6169       assert(constant_reloc == relocInfo::none, "unexpected reloc type");
6170       __ set(val, $dst$$Register);
6171     }
6172   %}
6173   ins_pipe(loadConP);
6174 %}
6175 
6176 instruct loadConP_load(iRegP dst, immP_load con) %{
6177   match(Set dst con);
6178   ins_cost(MEMORY_REF_COST);
6179   format %{ "LD     [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %}
6180   ins_encode %{
6181     RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
6182     __ ld_ptr($constanttablebase, con_offset, $dst$$Register);
6183   %}
6184   ins_pipe(loadConP);
6185 %}
6186 
6187 instruct loadConP_no_oop_cheap(iRegP dst, immP_no_oop_cheap con) %{
6188   match(Set dst con);
6189   ins_cost(DEFAULT_COST * 3/2);
6190   format %{ "SET    $con,$dst\t! non-oop ptr" %}
6191   ins_encode %{
6192     if (_opnds[1]->constant_reloc() == relocInfo::metadata_type) {
6193       __ set_metadata_constant((Metadata*)$con$$constant, $dst$$Register);
6194     } else {
6195       __ set($con$$constant, $dst$$Register);
6196     }
6197   %}
6198   ins_pipe(loadConP);
6199 %}
6200 #endif // _LP64
6201 
6202 instruct loadConP0(iRegP dst, immP0 src) %{
6203   match(Set dst src);
6204 
6205   size(4);
6206   format %{ "CLR    $dst\t!ptr" %}
6207   ins_encode %{
6208     __ clr($dst$$Register);
6209   %}
6210   ins_pipe(ialu_imm);
6211 %}
6212 
6213 instruct loadConP_poll(iRegP dst, immP_poll src) %{
6214   match(Set dst src);
6215   ins_cost(DEFAULT_COST);
6216   format %{ "SET    $src,$dst\t!ptr" %}
6217   ins_encode %{
6218     AddressLiteral polling_page(os::get_polling_page());
6219     __ sethi(polling_page, reg_to_register_object($dst$$reg));
6220   %}
6221   ins_pipe(loadConP_poll);
6222 %}
6223 
6224 instruct loadConN0(iRegN dst, immN0 src) %{
6225   match(Set dst src);
6226 
6227   size(4);
6228   format %{ "CLR    $dst\t! compressed NULL ptr" %}
6229   ins_encode %{
6230     __ clr($dst$$Register);
6231   %}
6232   ins_pipe(ialu_imm);
6233 %}
6234 
6235 instruct loadConN(iRegN dst, immN src) %{
6236   match(Set dst src);
6237   ins_cost(DEFAULT_COST * 3/2);
6238   format %{ "SET    $src,$dst\t! compressed ptr" %}
6239   ins_encode %{
6240     Register dst = $dst$$Register;
6241     __ set_narrow_oop((jobject)$src$$constant, dst);
6242   %}
6243   ins_pipe(ialu_hi_lo_reg);
6244 %}
6245 
6246 instruct loadConNKlass(iRegN dst, immNKlass src) %{
6247   match(Set dst src);
6248   ins_cost(DEFAULT_COST * 3/2);
6249   format %{ "SET    $src,$dst\t! compressed klass ptr" %}
6250   ins_encode %{
6251     Register dst = $dst$$Register;
6252     __ set_narrow_klass((Klass*)$src$$constant, dst);
6253   %}
6254   ins_pipe(ialu_hi_lo_reg);
6255 %}
6256 
6257 // Materialize long value (predicated by immL_cheap).
6258 instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{
6259   match(Set dst con);
6260   effect(KILL tmp);
6261   ins_cost(DEFAULT_COST * 3);
6262   format %{ "SET64   $con,$dst KILL $tmp\t! cheap long" %}
6263   ins_encode %{
6264     __ set64($con$$constant, $dst$$Register, $tmp$$Register);
6265   %}
6266   ins_pipe(loadConL);
6267 %}
6268 
6269 // Load long value from constant table (predicated by immL_expensive).
6270 instruct loadConL_ldx(iRegL dst, immL_expensive con) %{
6271   match(Set dst con);
6272   ins_cost(MEMORY_REF_COST);
6273   format %{ "LDX     [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %}
6274   ins_encode %{
6275       RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
6276     __ ldx($constanttablebase, con_offset, $dst$$Register);
6277   %}
6278   ins_pipe(loadConL);
6279 %}
6280 
6281 instruct loadConL0( iRegL dst, immL0 src ) %{
6282   match(Set dst src);
6283   ins_cost(DEFAULT_COST);
6284   size(4);
6285   format %{ "CLR    $dst\t! long" %}
6286   ins_encode( Set13( src, dst ) );
6287   ins_pipe(ialu_imm);
6288 %}
6289 
6290 instruct loadConL13( iRegL dst, immL13 src ) %{
6291   match(Set dst src);
6292   ins_cost(DEFAULT_COST * 2);
6293 
6294   size(4);
6295   format %{ "MOV    $src,$dst\t! long" %}
6296   ins_encode( Set13( src, dst ) );
6297   ins_pipe(ialu_imm);
6298 %}
6299 
6300 instruct loadConF(regF dst, immF con, o7RegI tmp) %{
6301   match(Set dst con);
6302   effect(KILL tmp);
6303   format %{ "LDF    [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %}
6304   ins_encode %{
6305       RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6306     __ ldf(FloatRegisterImpl::S, $constanttablebase, con_offset, $dst$$FloatRegister);
6307   %}
6308   ins_pipe(loadConFD);
6309 %}
6310 
6311 instruct loadConD(regD dst, immD con, o7RegI tmp) %{
6312   match(Set dst con);
6313   effect(KILL tmp);
6314   format %{ "LDDF   [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %}
6315   ins_encode %{
6316     // XXX This is a quick fix for 6833573.
6317     //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister);
6318     RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6319     __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
6320   %}
6321   ins_pipe(loadConFD);
6322 %}
6323 
6324 // Prefetch instructions.
6325 // Must be safe to execute with invalid address (cannot fault).
6326 
6327 instruct prefetchr( memory mem ) %{
6328   match( PrefetchRead mem );
6329   ins_cost(MEMORY_REF_COST);
6330   size(4);
6331 
6332   format %{ "PREFETCH $mem,0\t! Prefetch read-many" %}
6333   opcode(Assembler::prefetch_op3);
6334   ins_encode( form3_mem_prefetch_read( mem ) );
6335   ins_pipe(iload_mem);
6336 %}
6337 
6338 instruct prefetchw( memory mem ) %{
6339   match( PrefetchWrite mem );
6340   ins_cost(MEMORY_REF_COST);
6341   size(4);
6342 
6343   format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %}
6344   opcode(Assembler::prefetch_op3);
6345   ins_encode( form3_mem_prefetch_write( mem ) );
6346   ins_pipe(iload_mem);
6347 %}
6348 
6349 // Prefetch instructions for allocation.
6350 
6351 instruct prefetchAlloc( memory mem ) %{
6352   predicate(AllocatePrefetchInstr == 0);
6353   match( PrefetchAllocation mem );
6354   ins_cost(MEMORY_REF_COST);
6355   size(4);
6356 
6357   format %{ "PREFETCH $mem,2\t! Prefetch allocation" %}
6358   opcode(Assembler::prefetch_op3);
6359   ins_encode( form3_mem_prefetch_write( mem ) );
6360   ins_pipe(iload_mem);
6361 %}
6362 
6363 // Use BIS instruction to prefetch for allocation.
6364 // Could fault, need space at the end of TLAB.
6365 instruct prefetchAlloc_bis( iRegP dst ) %{
6366   predicate(AllocatePrefetchInstr == 1);
6367   match( PrefetchAllocation dst );
6368   ins_cost(MEMORY_REF_COST);
6369   size(4);
6370 
6371   format %{ "STXA   [$dst]\t! // Prefetch allocation using BIS" %}
6372   ins_encode %{
6373     __ stxa(G0, $dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY);
6374   %}
6375   ins_pipe(istore_mem_reg);
6376 %}
6377 
6378 // Next code is used for finding next cache line address to prefetch.
6379 #ifndef _LP64
6380 instruct cacheLineAdr( iRegP dst, iRegP src, immI13 mask ) %{
6381   match(Set dst (CastX2P (AndI (CastP2X src) mask)));
6382   ins_cost(DEFAULT_COST);
6383   size(4);
6384 
6385   format %{ "AND    $src,$mask,$dst\t! next cache line address" %}
6386   ins_encode %{
6387     __ and3($src$$Register, $mask$$constant, $dst$$Register);
6388   %}
6389   ins_pipe(ialu_reg_imm);
6390 %}
6391 #else
6392 instruct cacheLineAdr( iRegP dst, iRegP src, immL13 mask ) %{
6393   match(Set dst (CastX2P (AndL (CastP2X src) mask)));
6394   ins_cost(DEFAULT_COST);
6395   size(4);
6396 
6397   format %{ "AND    $src,$mask,$dst\t! next cache line address" %}
6398   ins_encode %{
6399     __ and3($src$$Register, $mask$$constant, $dst$$Register);
6400   %}
6401   ins_pipe(ialu_reg_imm);
6402 %}
6403 #endif
6404 
6405 //----------Store Instructions-------------------------------------------------
6406 // Store Byte
6407 instruct storeB(memory mem, iRegI src) %{
6408   match(Set mem (StoreB mem src));
6409   ins_cost(MEMORY_REF_COST);
6410 
6411   size(4);
6412   format %{ "STB    $src,$mem\t! byte" %}
6413   opcode(Assembler::stb_op3);
6414   ins_encode(simple_form3_mem_reg( mem, src ) );
6415   ins_pipe(istore_mem_reg);
6416 %}
6417 
6418 instruct storeB0(memory mem, immI0 src) %{
6419   match(Set mem (StoreB mem src));
6420   ins_cost(MEMORY_REF_COST);
6421 
6422   size(4);
6423   format %{ "STB    $src,$mem\t! byte" %}
6424   opcode(Assembler::stb_op3);
6425   ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6426   ins_pipe(istore_mem_zero);
6427 %}
6428 
6429 instruct storeCM0(memory mem, immI0 src) %{
6430   match(Set mem (StoreCM mem src));
6431   ins_cost(MEMORY_REF_COST);
6432 
6433   size(4);
6434   format %{ "STB    $src,$mem\t! CMS card-mark byte 0" %}
6435   opcode(Assembler::stb_op3);
6436   ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6437   ins_pipe(istore_mem_zero);
6438 %}
6439 
6440 // Store Char/Short
6441 instruct storeC(memory mem, iRegI src) %{
6442   match(Set mem (StoreC mem src));
6443   ins_cost(MEMORY_REF_COST);
6444 
6445   size(4);
6446   format %{ "STH    $src,$mem\t! short" %}
6447   opcode(Assembler::sth_op3);
6448   ins_encode(simple_form3_mem_reg( mem, src ) );
6449   ins_pipe(istore_mem_reg);
6450 %}
6451 
6452 instruct storeC0(memory mem, immI0 src) %{
6453   match(Set mem (StoreC mem src));
6454   ins_cost(MEMORY_REF_COST);
6455 
6456   size(4);
6457   format %{ "STH    $src,$mem\t! short" %}
6458   opcode(Assembler::sth_op3);
6459   ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6460   ins_pipe(istore_mem_zero);
6461 %}
6462 
6463 // Store Integer
6464 instruct storeI(memory mem, iRegI src) %{
6465   match(Set mem (StoreI mem src));
6466   ins_cost(MEMORY_REF_COST);
6467 
6468   size(4);
6469   format %{ "STW    $src,$mem" %}
6470   opcode(Assembler::stw_op3);
6471   ins_encode(simple_form3_mem_reg( mem, src ) );
6472   ins_pipe(istore_mem_reg);
6473 %}
6474 
6475 // Store Long
6476 instruct storeL(memory mem, iRegL src) %{
6477   match(Set mem (StoreL mem src));
6478   ins_cost(MEMORY_REF_COST);
6479   size(4);
6480   format %{ "STX    $src,$mem\t! long" %}
6481   opcode(Assembler::stx_op3);
6482   ins_encode(simple_form3_mem_reg( mem, src ) );
6483   ins_pipe(istore_mem_reg);
6484 %}
6485 
6486 instruct storeI0(memory mem, immI0 src) %{
6487   match(Set mem (StoreI mem src));
6488   ins_cost(MEMORY_REF_COST);
6489 
6490   size(4);
6491   format %{ "STW    $src,$mem" %}
6492   opcode(Assembler::stw_op3);
6493   ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6494   ins_pipe(istore_mem_zero);
6495 %}
6496 
6497 instruct storeL0(memory mem, immL0 src) %{
6498   match(Set mem (StoreL mem src));
6499   ins_cost(MEMORY_REF_COST);
6500 
6501   size(4);
6502   format %{ "STX    $src,$mem" %}
6503   opcode(Assembler::stx_op3);
6504   ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6505   ins_pipe(istore_mem_zero);
6506 %}
6507 
6508 // Store Integer from float register (used after fstoi)
6509 instruct storeI_Freg(memory mem, regF src) %{
6510   match(Set mem (StoreI mem src));
6511   ins_cost(MEMORY_REF_COST);
6512 
6513   size(4);
6514   format %{ "STF    $src,$mem\t! after fstoi/fdtoi" %}
6515   opcode(Assembler::stf_op3);
6516   ins_encode(simple_form3_mem_reg( mem, src ) );
6517   ins_pipe(fstoreF_mem_reg);
6518 %}
6519 
6520 // Store Pointer
6521 instruct storeP(memory dst, sp_ptr_RegP src) %{
6522   match(Set dst (StoreP dst src));
6523   ins_cost(MEMORY_REF_COST);
6524   size(4);
6525 
6526 #ifndef _LP64
6527   format %{ "STW    $src,$dst\t! ptr" %}
6528   opcode(Assembler::stw_op3, 0, REGP_OP);
6529 #else
6530   format %{ "STX    $src,$dst\t! ptr" %}
6531   opcode(Assembler::stx_op3, 0, REGP_OP);
6532 #endif
6533   ins_encode( form3_mem_reg( dst, src ) );
6534   ins_pipe(istore_mem_spORreg);
6535 %}
6536 
6537 instruct storeP0(memory dst, immP0 src) %{
6538   match(Set dst (StoreP dst src));
6539   ins_cost(MEMORY_REF_COST);
6540   size(4);
6541 
6542 #ifndef _LP64
6543   format %{ "STW    $src,$dst\t! ptr" %}
6544   opcode(Assembler::stw_op3, 0, REGP_OP);
6545 #else
6546   format %{ "STX    $src,$dst\t! ptr" %}
6547   opcode(Assembler::stx_op3, 0, REGP_OP);
6548 #endif
6549   ins_encode( form3_mem_reg( dst, R_G0 ) );
6550   ins_pipe(istore_mem_zero);
6551 %}
6552 
6553 // Store Compressed Pointer
6554 instruct storeN(memory dst, iRegN src) %{
6555    match(Set dst (StoreN dst src));
6556    ins_cost(MEMORY_REF_COST);
6557    size(4);
6558 
6559    format %{ "STW    $src,$dst\t! compressed ptr" %}
6560    ins_encode %{
6561      Register base = as_Register($dst$$base);
6562      Register index = as_Register($dst$$index);
6563      Register src = $src$$Register;
6564      if (index != G0) {
6565        __ stw(src, base, index);
6566      } else {
6567        __ stw(src, base, $dst$$disp);
6568      }
6569    %}
6570    ins_pipe(istore_mem_spORreg);
6571 %}
6572 
6573 instruct storeNKlass(memory dst, iRegN src) %{
6574    match(Set dst (StoreNKlass dst src));
6575    ins_cost(MEMORY_REF_COST);
6576    size(4);
6577 
6578    format %{ "STW    $src,$dst\t! compressed klass ptr" %}
6579    ins_encode %{
6580      Register base = as_Register($dst$$base);
6581      Register index = as_Register($dst$$index);
6582      Register src = $src$$Register;
6583      if (index != G0) {
6584        __ stw(src, base, index);
6585      } else {
6586        __ stw(src, base, $dst$$disp);
6587      }
6588    %}
6589    ins_pipe(istore_mem_spORreg);
6590 %}
6591 
6592 instruct storeN0(memory dst, immN0 src) %{
6593    match(Set dst (StoreN dst src));
6594    ins_cost(MEMORY_REF_COST);
6595    size(4);
6596 
6597    format %{ "STW    $src,$dst\t! compressed ptr" %}
6598    ins_encode %{
6599      Register base = as_Register($dst$$base);
6600      Register index = as_Register($dst$$index);
6601      if (index != G0) {
6602        __ stw(0, base, index);
6603      } else {
6604        __ stw(0, base, $dst$$disp);
6605      }
6606    %}
6607    ins_pipe(istore_mem_zero);
6608 %}
6609 
6610 // Store Double
6611 instruct storeD( memory mem, regD src) %{
6612   match(Set mem (StoreD mem src));
6613   ins_cost(MEMORY_REF_COST);
6614 
6615   size(4);
6616   format %{ "STDF   $src,$mem" %}
6617   opcode(Assembler::stdf_op3);
6618   ins_encode(simple_form3_mem_reg( mem, src ) );
6619   ins_pipe(fstoreD_mem_reg);
6620 %}
6621 
6622 instruct storeD0( memory mem, immD0 src) %{
6623   match(Set mem (StoreD mem src));
6624   ins_cost(MEMORY_REF_COST);
6625 
6626   size(4);
6627   format %{ "STX    $src,$mem" %}
6628   opcode(Assembler::stx_op3);
6629   ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6630   ins_pipe(fstoreD_mem_zero);
6631 %}
6632 
6633 // Store Float
6634 instruct storeF( memory mem, regF src) %{
6635   match(Set mem (StoreF mem src));
6636   ins_cost(MEMORY_REF_COST);
6637 
6638   size(4);
6639   format %{ "STF    $src,$mem" %}
6640   opcode(Assembler::stf_op3);
6641   ins_encode(simple_form3_mem_reg( mem, src ) );
6642   ins_pipe(fstoreF_mem_reg);
6643 %}
6644 
6645 instruct storeF0( memory mem, immF0 src) %{
6646   match(Set mem (StoreF mem src));
6647   ins_cost(MEMORY_REF_COST);
6648 
6649   size(4);
6650   format %{ "STW    $src,$mem\t! storeF0" %}
6651   opcode(Assembler::stw_op3);
6652   ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6653   ins_pipe(fstoreF_mem_zero);
6654 %}
6655 
6656 // Convert oop pointer into compressed form
6657 instruct encodeHeapOop(iRegN dst, iRegP src) %{
6658   predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6659   match(Set dst (EncodeP src));
6660   format %{ "encode_heap_oop $src, $dst" %}
6661   ins_encode %{
6662     __ encode_heap_oop($src$$Register, $dst$$Register);
6663   %}
6664   ins_avoid_back_to_back(Universe::narrow_oop_base() == NULL ? AVOID_NONE : AVOID_BEFORE);
6665   ins_pipe(ialu_reg);
6666 %}
6667 
6668 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{
6669   predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6670   match(Set dst (EncodeP src));
6671   format %{ "encode_heap_oop_not_null $src, $dst" %}
6672   ins_encode %{
6673     __ encode_heap_oop_not_null($src$$Register, $dst$$Register);
6674   %}
6675   ins_pipe(ialu_reg);
6676 %}
6677 
6678 instruct decodeHeapOop(iRegP dst, iRegN src) %{
6679   predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6680             n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
6681   match(Set dst (DecodeN src));
6682   format %{ "decode_heap_oop $src, $dst" %}
6683   ins_encode %{
6684     __ decode_heap_oop($src$$Register, $dst$$Register);
6685   %}
6686   ins_pipe(ialu_reg);
6687 %}
6688 
6689 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{
6690   predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6691             n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
6692   match(Set dst (DecodeN src));
6693   format %{ "decode_heap_oop_not_null $src, $dst" %}
6694   ins_encode %{
6695     __ decode_heap_oop_not_null($src$$Register, $dst$$Register);
6696   %}
6697   ins_pipe(ialu_reg);
6698 %}
6699 
6700 instruct encodeKlass_not_null(iRegN dst, iRegP src) %{
6701   match(Set dst (EncodePKlass src));
6702   format %{ "encode_klass_not_null $src, $dst" %}
6703   ins_encode %{
6704     __ encode_klass_not_null($src$$Register, $dst$$Register);
6705   %}
6706   ins_pipe(ialu_reg);
6707 %}
6708 
6709 instruct decodeKlass_not_null(iRegP dst, iRegN src) %{
6710   match(Set dst (DecodeNKlass src));
6711   format %{ "decode_klass_not_null $src, $dst" %}
6712   ins_encode %{
6713     __ decode_klass_not_null($src$$Register, $dst$$Register);
6714   %}
6715   ins_pipe(ialu_reg);
6716 %}
6717 
6718 //----------MemBar Instructions-----------------------------------------------
6719 // Memory barrier flavors
6720 
6721 instruct membar_acquire() %{
6722   match(MemBarAcquire);
6723   match(LoadFence);
6724   ins_cost(4*MEMORY_REF_COST);
6725 
6726   size(0);
6727   format %{ "MEMBAR-acquire" %}
6728   ins_encode( enc_membar_acquire );
6729   ins_pipe(long_memory_op);
6730 %}
6731 
6732 instruct membar_acquire_lock() %{
6733   match(MemBarAcquireLock);
6734   ins_cost(0);
6735 
6736   size(0);
6737   format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
6738   ins_encode( );
6739   ins_pipe(empty);
6740 %}
6741 
6742 instruct membar_release() %{
6743   match(MemBarRelease);
6744   match(StoreFence);
6745   ins_cost(4*MEMORY_REF_COST);
6746 
6747   size(0);
6748   format %{ "MEMBAR-release" %}
6749   ins_encode( enc_membar_release );
6750   ins_pipe(long_memory_op);
6751 %}
6752 
6753 instruct membar_release_lock() %{
6754   match(MemBarReleaseLock);
6755   ins_cost(0);
6756 
6757   size(0);
6758   format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
6759   ins_encode( );
6760   ins_pipe(empty);
6761 %}
6762 
6763 instruct membar_volatile() %{
6764   match(MemBarVolatile);
6765   ins_cost(4*MEMORY_REF_COST);
6766 
6767   size(4);
6768   format %{ "MEMBAR-volatile" %}
6769   ins_encode( enc_membar_volatile );
6770   ins_pipe(long_memory_op);
6771 %}
6772 
6773 instruct unnecessary_membar_volatile() %{
6774   match(MemBarVolatile);
6775   predicate(Matcher::post_store_load_barrier(n));
6776   ins_cost(0);
6777 
6778   size(0);
6779   format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %}
6780   ins_encode( );
6781   ins_pipe(empty);
6782 %}
6783 
6784 instruct membar_storestore() %{
6785   match(MemBarStoreStore);
6786   ins_cost(0);
6787 
6788   size(0);
6789   format %{ "!MEMBAR-storestore (empty encoding)" %}
6790   ins_encode( );
6791   ins_pipe(empty);
6792 %}
6793 
6794 //----------Register Move Instructions-----------------------------------------
6795 instruct roundDouble_nop(regD dst) %{
6796   match(Set dst (RoundDouble dst));
6797   ins_cost(0);
6798   // SPARC results are already "rounded" (i.e., normal-format IEEE)
6799   ins_encode( );
6800   ins_pipe(empty);
6801 %}
6802 
6803 
6804 instruct roundFloat_nop(regF dst) %{
6805   match(Set dst (RoundFloat dst));
6806   ins_cost(0);
6807   // SPARC results are already "rounded" (i.e., normal-format IEEE)
6808   ins_encode( );
6809   ins_pipe(empty);
6810 %}
6811 
6812 
6813 // Cast Index to Pointer for unsafe natives
6814 instruct castX2P(iRegX src, iRegP dst) %{
6815   match(Set dst (CastX2P src));
6816 
6817   format %{ "MOV    $src,$dst\t! IntX->Ptr" %}
6818   ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6819   ins_pipe(ialu_reg);
6820 %}
6821 
6822 // Cast Pointer to Index for unsafe natives
6823 instruct castP2X(iRegP src, iRegX dst) %{
6824   match(Set dst (CastP2X src));
6825 
6826   format %{ "MOV    $src,$dst\t! Ptr->IntX" %}
6827   ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6828   ins_pipe(ialu_reg);
6829 %}
6830 
6831 instruct stfSSD(stackSlotD stkSlot, regD src) %{
6832   // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6833   match(Set stkSlot src);   // chain rule
6834   ins_cost(MEMORY_REF_COST);
6835   format %{ "STDF   $src,$stkSlot\t!stk" %}
6836   opcode(Assembler::stdf_op3);
6837   ins_encode(simple_form3_mem_reg(stkSlot, src));
6838   ins_pipe(fstoreD_stk_reg);
6839 %}
6840 
6841 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{
6842   // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6843   match(Set dst stkSlot);   // chain rule
6844   ins_cost(MEMORY_REF_COST);
6845   format %{ "LDDF   $stkSlot,$dst\t!stk" %}
6846   opcode(Assembler::lddf_op3);
6847   ins_encode(simple_form3_mem_reg(stkSlot, dst));
6848   ins_pipe(floadD_stk);
6849 %}
6850 
6851 instruct stfSSF(stackSlotF stkSlot, regF src) %{
6852   // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6853   match(Set stkSlot src);   // chain rule
6854   ins_cost(MEMORY_REF_COST);
6855   format %{ "STF   $src,$stkSlot\t!stk" %}
6856   opcode(Assembler::stf_op3);
6857   ins_encode(simple_form3_mem_reg(stkSlot, src));
6858   ins_pipe(fstoreF_stk_reg);
6859 %}
6860 
6861 //----------Conditional Move---------------------------------------------------
6862 // Conditional move
6863 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{
6864   match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6865   ins_cost(150);
6866   format %{ "MOV$cmp $pcc,$src,$dst" %}
6867   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6868   ins_pipe(ialu_reg);
6869 %}
6870 
6871 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{
6872   match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6873   ins_cost(140);
6874   format %{ "MOV$cmp $pcc,$src,$dst" %}
6875   ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6876   ins_pipe(ialu_imm);
6877 %}
6878 
6879 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{
6880   match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6881   ins_cost(150);
6882   size(4);
6883   format %{ "MOV$cmp  $icc,$src,$dst" %}
6884   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6885   ins_pipe(ialu_reg);
6886 %}
6887 
6888 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{
6889   match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6890   ins_cost(140);
6891   size(4);
6892   format %{ "MOV$cmp  $icc,$src,$dst" %}
6893   ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6894   ins_pipe(ialu_imm);
6895 %}
6896 
6897 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{
6898   match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6899   ins_cost(150);
6900   size(4);
6901   format %{ "MOV$cmp  $icc,$src,$dst" %}
6902   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6903   ins_pipe(ialu_reg);
6904 %}
6905 
6906 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{
6907   match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6908   ins_cost(140);
6909   size(4);
6910   format %{ "MOV$cmp  $icc,$src,$dst" %}
6911   ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6912   ins_pipe(ialu_imm);
6913 %}
6914 
6915 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{
6916   match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6917   ins_cost(150);
6918   size(4);
6919   format %{ "MOV$cmp $fcc,$src,$dst" %}
6920   ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6921   ins_pipe(ialu_reg);
6922 %}
6923 
6924 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{
6925   match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6926   ins_cost(140);
6927   size(4);
6928   format %{ "MOV$cmp $fcc,$src,$dst" %}
6929   ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6930   ins_pipe(ialu_imm);
6931 %}
6932 
6933 // Conditional move for RegN. Only cmov(reg,reg).
6934 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{
6935   match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src)));
6936   ins_cost(150);
6937   format %{ "MOV$cmp $pcc,$src,$dst" %}
6938   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6939   ins_pipe(ialu_reg);
6940 %}
6941 
6942 // This instruction also works with CmpN so we don't need cmovNN_reg.
6943 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{
6944   match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6945   ins_cost(150);
6946   size(4);
6947   format %{ "MOV$cmp  $icc,$src,$dst" %}
6948   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6949   ins_pipe(ialu_reg);
6950 %}
6951 
6952 // This instruction also works with CmpN so we don't need cmovNN_reg.
6953 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{
6954   match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6955   ins_cost(150);
6956   size(4);
6957   format %{ "MOV$cmp  $icc,$src,$dst" %}
6958   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6959   ins_pipe(ialu_reg);
6960 %}
6961 
6962 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{
6963   match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src)));
6964   ins_cost(150);
6965   size(4);
6966   format %{ "MOV$cmp $fcc,$src,$dst" %}
6967   ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6968   ins_pipe(ialu_reg);
6969 %}
6970 
6971 // Conditional move
6972 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{
6973   match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6974   ins_cost(150);
6975   format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6976   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6977   ins_pipe(ialu_reg);
6978 %}
6979 
6980 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{
6981   match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6982   ins_cost(140);
6983   format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6984   ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6985   ins_pipe(ialu_imm);
6986 %}
6987 
6988 // This instruction also works with CmpN so we don't need cmovPN_reg.
6989 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{
6990   match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6991   ins_cost(150);
6992 
6993   size(4);
6994   format %{ "MOV$cmp  $icc,$src,$dst\t! ptr" %}
6995   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6996   ins_pipe(ialu_reg);
6997 %}
6998 
6999 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{
7000   match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
7001   ins_cost(150);
7002 
7003   size(4);
7004   format %{ "MOV$cmp  $icc,$src,$dst\t! ptr" %}
7005   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
7006   ins_pipe(ialu_reg);
7007 %}
7008 
7009 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{
7010   match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
7011   ins_cost(140);
7012 
7013   size(4);
7014   format %{ "MOV$cmp  $icc,$src,$dst\t! ptr" %}
7015   ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
7016   ins_pipe(ialu_imm);
7017 %}
7018 
7019 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{
7020   match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
7021   ins_cost(140);
7022 
7023   size(4);
7024   format %{ "MOV$cmp  $icc,$src,$dst\t! ptr" %}
7025   ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
7026   ins_pipe(ialu_imm);
7027 %}
7028 
7029 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{
7030   match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
7031   ins_cost(150);
7032   size(4);
7033   format %{ "MOV$cmp $fcc,$src,$dst" %}
7034   ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
7035   ins_pipe(ialu_imm);
7036 %}
7037 
7038 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{
7039   match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
7040   ins_cost(140);
7041   size(4);
7042   format %{ "MOV$cmp $fcc,$src,$dst" %}
7043   ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
7044   ins_pipe(ialu_imm);
7045 %}
7046 
7047 // Conditional move
7048 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{
7049   match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src)));
7050   ins_cost(150);
7051   opcode(0x101);
7052   format %{ "FMOVD$cmp $pcc,$src,$dst" %}
7053   ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
7054   ins_pipe(int_conditional_float_move);
7055 %}
7056 
7057 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{
7058   match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
7059   ins_cost(150);
7060 
7061   size(4);
7062   format %{ "FMOVS$cmp $icc,$src,$dst" %}
7063   opcode(0x101);
7064   ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
7065   ins_pipe(int_conditional_float_move);
7066 %}
7067 
7068 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{
7069   match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
7070   ins_cost(150);
7071 
7072   size(4);
7073   format %{ "FMOVS$cmp $icc,$src,$dst" %}
7074   opcode(0x101);
7075   ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
7076   ins_pipe(int_conditional_float_move);
7077 %}
7078 
7079 // Conditional move,
7080 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{
7081   match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src)));
7082   ins_cost(150);
7083   size(4);
7084   format %{ "FMOVF$cmp $fcc,$src,$dst" %}
7085   opcode(0x1);
7086   ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
7087   ins_pipe(int_conditional_double_move);
7088 %}
7089 
7090 // Conditional move
7091 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{
7092   match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src)));
7093   ins_cost(150);
7094   size(4);
7095   opcode(0x102);
7096   format %{ "FMOVD$cmp $pcc,$src,$dst" %}
7097   ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
7098   ins_pipe(int_conditional_double_move);
7099 %}
7100 
7101 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{
7102   match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
7103   ins_cost(150);
7104 
7105   size(4);
7106   format %{ "FMOVD$cmp $icc,$src,$dst" %}
7107   opcode(0x102);
7108   ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
7109   ins_pipe(int_conditional_double_move);
7110 %}
7111 
7112 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{
7113   match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
7114   ins_cost(150);
7115 
7116   size(4);
7117   format %{ "FMOVD$cmp $icc,$src,$dst" %}
7118   opcode(0x102);
7119   ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
7120   ins_pipe(int_conditional_double_move);
7121 %}
7122 
7123 // Conditional move,
7124 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{
7125   match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src)));
7126   ins_cost(150);
7127   size(4);
7128   format %{ "FMOVD$cmp $fcc,$src,$dst" %}
7129   opcode(0x2);
7130   ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
7131   ins_pipe(int_conditional_double_move);
7132 %}
7133 
7134 // Conditional move
7135 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{
7136   match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
7137   ins_cost(150);
7138   format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
7139   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
7140   ins_pipe(ialu_reg);
7141 %}
7142 
7143 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{
7144   match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
7145   ins_cost(140);
7146   format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
7147   ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
7148   ins_pipe(ialu_imm);
7149 %}
7150 
7151 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{
7152   match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
7153   ins_cost(150);
7154 
7155   size(4);
7156   format %{ "MOV$cmp  $icc,$src,$dst\t! long" %}
7157   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
7158   ins_pipe(ialu_reg);
7159 %}
7160 
7161 
7162 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{
7163   match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
7164   ins_cost(150);
7165 
7166   size(4);
7167   format %{ "MOV$cmp  $icc,$src,$dst\t! long" %}
7168   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
7169   ins_pipe(ialu_reg);
7170 %}
7171 
7172 
7173 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{
7174   match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src)));
7175   ins_cost(150);
7176 
7177   size(4);
7178   format %{ "MOV$cmp  $fcc,$src,$dst\t! long" %}
7179   ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
7180   ins_pipe(ialu_reg);
7181 %}
7182 
7183 
7184 
7185 //----------OS and Locking Instructions----------------------------------------
7186 
7187 // This name is KNOWN by the ADLC and cannot be changed.
7188 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
7189 // for this guy.
7190 instruct tlsLoadP(g2RegP dst) %{
7191   match(Set dst (ThreadLocal));
7192 
7193   size(0);
7194   ins_cost(0);
7195   format %{ "# TLS is in G2" %}
7196   ins_encode( /*empty encoding*/ );
7197   ins_pipe(ialu_none);
7198 %}
7199 
7200 instruct checkCastPP( iRegP dst ) %{
7201   match(Set dst (CheckCastPP dst));
7202 
7203   size(0);
7204   format %{ "# checkcastPP of $dst" %}
7205   ins_encode( /*empty encoding*/ );
7206   ins_pipe(empty);
7207 %}
7208 
7209 
7210 instruct castPP( iRegP dst ) %{
7211   match(Set dst (CastPP dst));
7212   format %{ "# castPP of $dst" %}
7213   ins_encode( /*empty encoding*/ );
7214   ins_pipe(empty);
7215 %}
7216 
7217 instruct castII( iRegI dst ) %{
7218   match(Set dst (CastII dst));
7219   format %{ "# castII of $dst" %}
7220   ins_encode( /*empty encoding*/ );
7221   ins_cost(0);
7222   ins_pipe(empty);
7223 %}
7224 
7225 //----------Arithmetic Instructions--------------------------------------------
7226 // Addition Instructions
7227 // Register Addition
7228 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7229   match(Set dst (AddI src1 src2));
7230 
7231   size(4);
7232   format %{ "ADD    $src1,$src2,$dst" %}
7233   ins_encode %{
7234     __ add($src1$$Register, $src2$$Register, $dst$$Register);
7235   %}
7236   ins_pipe(ialu_reg_reg);
7237 %}
7238 
7239 // Immediate Addition
7240 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7241   match(Set dst (AddI src1 src2));
7242 
7243   size(4);
7244   format %{ "ADD    $src1,$src2,$dst" %}
7245   opcode(Assembler::add_op3, Assembler::arith_op);
7246   ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7247   ins_pipe(ialu_reg_imm);
7248 %}
7249 
7250 // Pointer Register Addition
7251 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{
7252   match(Set dst (AddP src1 src2));
7253 
7254   size(4);
7255   format %{ "ADD    $src1,$src2,$dst" %}
7256   opcode(Assembler::add_op3, Assembler::arith_op);
7257   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7258   ins_pipe(ialu_reg_reg);
7259 %}
7260 
7261 // Pointer Immediate Addition
7262 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{
7263   match(Set dst (AddP src1 src2));
7264 
7265   size(4);
7266   format %{ "ADD    $src1,$src2,$dst" %}
7267   opcode(Assembler::add_op3, Assembler::arith_op);
7268   ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7269   ins_pipe(ialu_reg_imm);
7270 %}
7271 
7272 // Long Addition
7273 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7274   match(Set dst (AddL src1 src2));
7275 
7276   size(4);
7277   format %{ "ADD    $src1,$src2,$dst\t! long" %}
7278   opcode(Assembler::add_op3, Assembler::arith_op);
7279   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7280   ins_pipe(ialu_reg_reg);
7281 %}
7282 
7283 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7284   match(Set dst (AddL src1 con));
7285 
7286   size(4);
7287   format %{ "ADD    $src1,$con,$dst" %}
7288   opcode(Assembler::add_op3, Assembler::arith_op);
7289   ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7290   ins_pipe(ialu_reg_imm);
7291 %}
7292 
7293 //----------Conditional_store--------------------------------------------------
7294 // Conditional-store of the updated heap-top.
7295 // Used during allocation of the shared heap.
7296 // Sets flags (EQ) on success.  Implemented with a CASA on Sparc.
7297 
7298 // LoadP-locked.  Same as a regular pointer load when used with a compare-swap
7299 instruct loadPLocked(iRegP dst, memory mem) %{
7300   match(Set dst (LoadPLocked mem));
7301   ins_cost(MEMORY_REF_COST);
7302 
7303 #ifndef _LP64
7304   size(4);
7305   format %{ "LDUW   $mem,$dst\t! ptr" %}
7306   opcode(Assembler::lduw_op3, 0, REGP_OP);
7307 #else
7308   format %{ "LDX    $mem,$dst\t! ptr" %}
7309   opcode(Assembler::ldx_op3, 0, REGP_OP);
7310 #endif
7311   ins_encode( form3_mem_reg( mem, dst ) );
7312   ins_pipe(iload_mem);
7313 %}
7314 
7315 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{
7316   match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval)));
7317   effect( KILL newval );
7318   format %{ "CASA   [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t"
7319             "CMP    R_G3,$oldval\t\t! See if we made progress"  %}
7320   ins_encode( enc_cas(heap_top_ptr,oldval,newval) );
7321   ins_pipe( long_memory_op );
7322 %}
7323 
7324 // Conditional-store of an int value.
7325 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{
7326   match(Set icc (StoreIConditional mem_ptr (Binary oldval newval)));
7327   effect( KILL newval );
7328   format %{ "CASA   [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7329             "CMP    $oldval,$newval\t\t! See if we made progress"  %}
7330   ins_encode( enc_cas(mem_ptr,oldval,newval) );
7331   ins_pipe( long_memory_op );
7332 %}
7333 
7334 // Conditional-store of a long value.
7335 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{
7336   match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval)));
7337   effect( KILL newval );
7338   format %{ "CASXA  [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7339             "CMP    $oldval,$newval\t\t! See if we made progress"  %}
7340   ins_encode( enc_cas(mem_ptr,oldval,newval) );
7341   ins_pipe( long_memory_op );
7342 %}
7343 
7344 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7345 
7346 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7347   predicate(VM_Version::supports_cx8());
7348   match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7349   effect( USE mem_ptr, KILL ccr, KILL tmp1);
7350   format %{
7351             "MOV    $newval,O7\n\t"
7352             "CASXA  [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7353             "CMP    $oldval,O7\t\t! See if we made progress\n\t"
7354             "MOV    1,$res\n\t"
7355             "MOVne  xcc,R_G0,$res"
7356   %}
7357   ins_encode( enc_casx(mem_ptr, oldval, newval),
7358               enc_lflags_ne_to_boolean(res) );
7359   ins_pipe( long_memory_op );
7360 %}
7361 
7362 
7363 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7364   match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7365   effect( USE mem_ptr, KILL ccr, KILL tmp1);
7366   format %{
7367             "MOV    $newval,O7\n\t"
7368             "CASA   [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7369             "CMP    $oldval,O7\t\t! See if we made progress\n\t"
7370             "MOV    1,$res\n\t"
7371             "MOVne  icc,R_G0,$res"
7372   %}
7373   ins_encode( enc_casi(mem_ptr, oldval, newval),
7374               enc_iflags_ne_to_boolean(res) );
7375   ins_pipe( long_memory_op );
7376 %}
7377 
7378 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7379 #ifdef _LP64
7380   predicate(VM_Version::supports_cx8());
7381 #endif
7382   match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7383   effect( USE mem_ptr, KILL ccr, KILL tmp1);
7384   format %{
7385             "MOV    $newval,O7\n\t"
7386             "CASA_PTR  [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7387             "CMP    $oldval,O7\t\t! See if we made progress\n\t"
7388             "MOV    1,$res\n\t"
7389             "MOVne  xcc,R_G0,$res"
7390   %}
7391 #ifdef _LP64
7392   ins_encode( enc_casx(mem_ptr, oldval, newval),
7393               enc_lflags_ne_to_boolean(res) );
7394 #else
7395   ins_encode( enc_casi(mem_ptr, oldval, newval),
7396               enc_iflags_ne_to_boolean(res) );
7397 #endif
7398   ins_pipe( long_memory_op );
7399 %}
7400 
7401 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7402   match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7403   effect( USE mem_ptr, KILL ccr, KILL tmp1);
7404   format %{
7405             "MOV    $newval,O7\n\t"
7406             "CASA   [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7407             "CMP    $oldval,O7\t\t! See if we made progress\n\t"
7408             "MOV    1,$res\n\t"
7409             "MOVne  icc,R_G0,$res"
7410   %}
7411   ins_encode( enc_casi(mem_ptr, oldval, newval),
7412               enc_iflags_ne_to_boolean(res) );
7413   ins_pipe( long_memory_op );
7414 %}
7415 
7416 instruct xchgI( memory mem, iRegI newval) %{
7417   match(Set newval (GetAndSetI mem newval));
7418   format %{ "SWAP  [$mem],$newval" %}
7419   size(4);
7420   ins_encode %{
7421     __ swap($mem$$Address, $newval$$Register);
7422   %}
7423   ins_pipe( long_memory_op );
7424 %}
7425 
7426 #ifndef _LP64
7427 instruct xchgP( memory mem, iRegP newval) %{
7428   match(Set newval (GetAndSetP mem newval));
7429   format %{ "SWAP  [$mem],$newval" %}
7430   size(4);
7431   ins_encode %{
7432     __ swap($mem$$Address, $newval$$Register);
7433   %}
7434   ins_pipe( long_memory_op );
7435 %}
7436 #endif
7437 
7438 instruct xchgN( memory mem, iRegN newval) %{
7439   match(Set newval (GetAndSetN mem newval));
7440   format %{ "SWAP  [$mem],$newval" %}
7441   size(4);
7442   ins_encode %{
7443     __ swap($mem$$Address, $newval$$Register);
7444   %}
7445   ins_pipe( long_memory_op );
7446 %}
7447 
7448 //---------------------
7449 // Subtraction Instructions
7450 // Register Subtraction
7451 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7452   match(Set dst (SubI src1 src2));
7453 
7454   size(4);
7455   format %{ "SUB    $src1,$src2,$dst" %}
7456   opcode(Assembler::sub_op3, Assembler::arith_op);
7457   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7458   ins_pipe(ialu_reg_reg);
7459 %}
7460 
7461 // Immediate Subtraction
7462 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7463   match(Set dst (SubI src1 src2));
7464 
7465   size(4);
7466   format %{ "SUB    $src1,$src2,$dst" %}
7467   opcode(Assembler::sub_op3, Assembler::arith_op);
7468   ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7469   ins_pipe(ialu_reg_imm);
7470 %}
7471 
7472 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
7473   match(Set dst (SubI zero src2));
7474 
7475   size(4);
7476   format %{ "NEG    $src2,$dst" %}
7477   opcode(Assembler::sub_op3, Assembler::arith_op);
7478   ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7479   ins_pipe(ialu_zero_reg);
7480 %}
7481 
7482 // Long subtraction
7483 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7484   match(Set dst (SubL src1 src2));
7485 
7486   size(4);
7487   format %{ "SUB    $src1,$src2,$dst\t! long" %}
7488   opcode(Assembler::sub_op3, Assembler::arith_op);
7489   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7490   ins_pipe(ialu_reg_reg);
7491 %}
7492 
7493 // Immediate Subtraction
7494 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7495   match(Set dst (SubL src1 con));
7496 
7497   size(4);
7498   format %{ "SUB    $src1,$con,$dst\t! long" %}
7499   opcode(Assembler::sub_op3, Assembler::arith_op);
7500   ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7501   ins_pipe(ialu_reg_imm);
7502 %}
7503 
7504 // Long negation
7505 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{
7506   match(Set dst (SubL zero src2));
7507 
7508   size(4);
7509   format %{ "NEG    $src2,$dst\t! long" %}
7510   opcode(Assembler::sub_op3, Assembler::arith_op);
7511   ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7512   ins_pipe(ialu_zero_reg);
7513 %}
7514 
7515 // Multiplication Instructions
7516 // Integer Multiplication
7517 // Register Multiplication
7518 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7519   match(Set dst (MulI src1 src2));
7520 
7521   size(4);
7522   format %{ "MULX   $src1,$src2,$dst" %}
7523   opcode(Assembler::mulx_op3, Assembler::arith_op);
7524   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7525   ins_pipe(imul_reg_reg);
7526 %}
7527 
7528 // Immediate Multiplication
7529 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7530   match(Set dst (MulI src1 src2));
7531 
7532   size(4);
7533   format %{ "MULX   $src1,$src2,$dst" %}
7534   opcode(Assembler::mulx_op3, Assembler::arith_op);
7535   ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7536   ins_pipe(imul_reg_imm);
7537 %}
7538 
7539 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7540   match(Set dst (MulL src1 src2));
7541   ins_cost(DEFAULT_COST * 5);
7542   size(4);
7543   format %{ "MULX   $src1,$src2,$dst\t! long" %}
7544   opcode(Assembler::mulx_op3, Assembler::arith_op);
7545   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7546   ins_pipe(mulL_reg_reg);
7547 %}
7548 
7549 // Immediate Multiplication
7550 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7551   match(Set dst (MulL src1 src2));
7552   ins_cost(DEFAULT_COST * 5);
7553   size(4);
7554   format %{ "MULX   $src1,$src2,$dst" %}
7555   opcode(Assembler::mulx_op3, Assembler::arith_op);
7556   ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7557   ins_pipe(mulL_reg_imm);
7558 %}
7559 
7560 // Integer Division
7561 // Register Division
7562 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{
7563   match(Set dst (DivI src1 src2));
7564   ins_cost((2+71)*DEFAULT_COST);
7565 
7566   format %{ "SRA     $src2,0,$src2\n\t"
7567             "SRA     $src1,0,$src1\n\t"
7568             "SDIVX   $src1,$src2,$dst" %}
7569   ins_encode( idiv_reg( src1, src2, dst ) );
7570   ins_pipe(sdiv_reg_reg);
7571 %}
7572 
7573 // Immediate Division
7574 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{
7575   match(Set dst (DivI src1 src2));
7576   ins_cost((2+71)*DEFAULT_COST);
7577 
7578   format %{ "SRA     $src1,0,$src1\n\t"
7579             "SDIVX   $src1,$src2,$dst" %}
7580   ins_encode( idiv_imm( src1, src2, dst ) );
7581   ins_pipe(sdiv_reg_imm);
7582 %}
7583 
7584 //----------Div-By-10-Expansion------------------------------------------------
7585 // Extract hi bits of a 32x32->64 bit multiply.
7586 // Expand rule only, not matched
7587 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{
7588   effect( DEF dst, USE src1, USE src2 );
7589   format %{ "MULX   $src1,$src2,$dst\t! Used in div-by-10\n\t"
7590             "SRLX   $dst,#32,$dst\t\t! Extract only hi word of result" %}
7591   ins_encode( enc_mul_hi(dst,src1,src2));
7592   ins_pipe(sdiv_reg_reg);
7593 %}
7594 
7595 // Magic constant, reciprocal of 10
7596 instruct loadConI_x66666667(iRegIsafe dst) %{
7597   effect( DEF dst );
7598 
7599   size(8);
7600   format %{ "SET    0x66666667,$dst\t! Used in div-by-10" %}
7601   ins_encode( Set32(0x66666667, dst) );
7602   ins_pipe(ialu_hi_lo_reg);
7603 %}
7604 
7605 // Register Shift Right Arithmetic Long by 32-63
7606 instruct sra_31( iRegI dst, iRegI src ) %{
7607   effect( DEF dst, USE src );
7608   format %{ "SRA    $src,31,$dst\t! Used in div-by-10" %}
7609   ins_encode( form3_rs1_rd_copysign_hi(src,dst) );
7610   ins_pipe(ialu_reg_reg);
7611 %}
7612 
7613 // Arithmetic Shift Right by 8-bit immediate
7614 instruct sra_reg_2( iRegI dst, iRegI src ) %{
7615   effect( DEF dst, USE src );
7616   format %{ "SRA    $src,2,$dst\t! Used in div-by-10" %}
7617   opcode(Assembler::sra_op3, Assembler::arith_op);
7618   ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) );
7619   ins_pipe(ialu_reg_imm);
7620 %}
7621 
7622 // Integer DIV with 10
7623 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{
7624   match(Set dst (DivI src div));
7625   ins_cost((6+6)*DEFAULT_COST);
7626   expand %{
7627     iRegIsafe tmp1;               // Killed temps;
7628     iRegIsafe tmp2;               // Killed temps;
7629     iRegI tmp3;                   // Killed temps;
7630     iRegI tmp4;                   // Killed temps;
7631     loadConI_x66666667( tmp1 );   // SET  0x66666667 -> tmp1
7632     mul_hi( tmp2, src, tmp1 );    // MUL  hibits(src * tmp1) -> tmp2
7633     sra_31( tmp3, src );          // SRA  src,31 -> tmp3
7634     sra_reg_2( tmp4, tmp2 );      // SRA  tmp2,2 -> tmp4
7635     subI_reg_reg( dst,tmp4,tmp3); // SUB  tmp4 - tmp3 -> dst
7636   %}
7637 %}
7638 
7639 // Register Long Division
7640 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7641   match(Set dst (DivL src1 src2));
7642   ins_cost(DEFAULT_COST*71);
7643   size(4);
7644   format %{ "SDIVX  $src1,$src2,$dst\t! long" %}
7645   opcode(Assembler::sdivx_op3, Assembler::arith_op);
7646   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7647   ins_pipe(divL_reg_reg);
7648 %}
7649 
7650 // Register Long Division
7651 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7652   match(Set dst (DivL src1 src2));
7653   ins_cost(DEFAULT_COST*71);
7654   size(4);
7655   format %{ "SDIVX  $src1,$src2,$dst\t! long" %}
7656   opcode(Assembler::sdivx_op3, Assembler::arith_op);
7657   ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7658   ins_pipe(divL_reg_imm);
7659 %}
7660 
7661 // Integer Remainder
7662 // Register Remainder
7663 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{
7664   match(Set dst (ModI src1 src2));
7665   effect( KILL ccr, KILL temp);
7666 
7667   format %{ "SREM   $src1,$src2,$dst" %}
7668   ins_encode( irem_reg(src1, src2, dst, temp) );
7669   ins_pipe(sdiv_reg_reg);
7670 %}
7671 
7672 // Immediate Remainder
7673 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{
7674   match(Set dst (ModI src1 src2));
7675   effect( KILL ccr, KILL temp);
7676 
7677   format %{ "SREM   $src1,$src2,$dst" %}
7678   ins_encode( irem_imm(src1, src2, dst, temp) );
7679   ins_pipe(sdiv_reg_imm);
7680 %}
7681 
7682 // Register Long Remainder
7683 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7684   effect(DEF dst, USE src1, USE src2);
7685   size(4);
7686   format %{ "SDIVX  $src1,$src2,$dst\t! long" %}
7687   opcode(Assembler::sdivx_op3, Assembler::arith_op);
7688   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7689   ins_pipe(divL_reg_reg);
7690 %}
7691 
7692 // Register Long Division
7693 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7694   effect(DEF dst, USE src1, USE src2);
7695   size(4);
7696   format %{ "SDIVX  $src1,$src2,$dst\t! long" %}
7697   opcode(Assembler::sdivx_op3, Assembler::arith_op);
7698   ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7699   ins_pipe(divL_reg_imm);
7700 %}
7701 
7702 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7703   effect(DEF dst, USE src1, USE src2);
7704   size(4);
7705   format %{ "MULX   $src1,$src2,$dst\t! long" %}
7706   opcode(Assembler::mulx_op3, Assembler::arith_op);
7707   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7708   ins_pipe(mulL_reg_reg);
7709 %}
7710 
7711 // Immediate Multiplication
7712 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7713   effect(DEF dst, USE src1, USE src2);
7714   size(4);
7715   format %{ "MULX   $src1,$src2,$dst" %}
7716   opcode(Assembler::mulx_op3, Assembler::arith_op);
7717   ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7718   ins_pipe(mulL_reg_imm);
7719 %}
7720 
7721 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7722   effect(DEF dst, USE src1, USE src2);
7723   size(4);
7724   format %{ "SUB    $src1,$src2,$dst\t! long" %}
7725   opcode(Assembler::sub_op3, Assembler::arith_op);
7726   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7727   ins_pipe(ialu_reg_reg);
7728 %}
7729 
7730 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
7731   effect(DEF dst, USE src1, USE src2);
7732   size(4);
7733   format %{ "SUB    $src1,$src2,$dst\t! long" %}
7734   opcode(Assembler::sub_op3, Assembler::arith_op);
7735   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7736   ins_pipe(ialu_reg_reg);
7737 %}
7738 
7739 // Register Long Remainder
7740 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7741   match(Set dst (ModL src1 src2));
7742   ins_cost(DEFAULT_COST*(71 + 6 + 1));
7743   expand %{
7744     iRegL tmp1;
7745     iRegL tmp2;
7746     divL_reg_reg_1(tmp1, src1, src2);
7747     mulL_reg_reg_1(tmp2, tmp1, src2);
7748     subL_reg_reg_1(dst,  src1, tmp2);
7749   %}
7750 %}
7751 
7752 // Register Long Remainder
7753 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7754   match(Set dst (ModL src1 src2));
7755   ins_cost(DEFAULT_COST*(71 + 6 + 1));
7756   expand %{
7757     iRegL tmp1;
7758     iRegL tmp2;
7759     divL_reg_imm13_1(tmp1, src1, src2);
7760     mulL_reg_imm13_1(tmp2, tmp1, src2);
7761     subL_reg_reg_2  (dst,  src1, tmp2);
7762   %}
7763 %}
7764 
7765 // Integer Shift Instructions
7766 // Register Shift Left
7767 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7768   match(Set dst (LShiftI src1 src2));
7769 
7770   size(4);
7771   format %{ "SLL    $src1,$src2,$dst" %}
7772   opcode(Assembler::sll_op3, Assembler::arith_op);
7773   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7774   ins_pipe(ialu_reg_reg);
7775 %}
7776 
7777 // Register Shift Left Immediate
7778 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7779   match(Set dst (LShiftI src1 src2));
7780 
7781   size(4);
7782   format %{ "SLL    $src1,$src2,$dst" %}
7783   opcode(Assembler::sll_op3, Assembler::arith_op);
7784   ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7785   ins_pipe(ialu_reg_imm);
7786 %}
7787 
7788 // Register Shift Left
7789 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7790   match(Set dst (LShiftL src1 src2));
7791 
7792   size(4);
7793   format %{ "SLLX   $src1,$src2,$dst" %}
7794   opcode(Assembler::sllx_op3, Assembler::arith_op);
7795   ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7796   ins_pipe(ialu_reg_reg);
7797 %}
7798 
7799 // Register Shift Left Immediate
7800 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7801   match(Set dst (LShiftL src1 src2));
7802 
7803   size(4);
7804   format %{ "SLLX   $src1,$src2,$dst" %}
7805   opcode(Assembler::sllx_op3, Assembler::arith_op);
7806   ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7807   ins_pipe(ialu_reg_imm);
7808 %}
7809 
7810 // Register Arithmetic Shift Right
7811 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7812   match(Set dst (RShiftI src1 src2));
7813   size(4);
7814   format %{ "SRA    $src1,$src2,$dst" %}
7815   opcode(Assembler::sra_op3, Assembler::arith_op);
7816   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7817   ins_pipe(ialu_reg_reg);
7818 %}
7819 
7820 // Register Arithmetic Shift Right Immediate
7821 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7822   match(Set dst (RShiftI src1 src2));
7823 
7824   size(4);
7825   format %{ "SRA    $src1,$src2,$dst" %}
7826   opcode(Assembler::sra_op3, Assembler::arith_op);
7827   ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7828   ins_pipe(ialu_reg_imm);
7829 %}
7830 
7831 // Register Shift Right Arithmatic Long
7832 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7833   match(Set dst (RShiftL src1 src2));
7834 
7835   size(4);
7836   format %{ "SRAX   $src1,$src2,$dst" %}
7837   opcode(Assembler::srax_op3, Assembler::arith_op);
7838   ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7839   ins_pipe(ialu_reg_reg);
7840 %}
7841 
7842 // Register Shift Left Immediate
7843 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7844   match(Set dst (RShiftL src1 src2));
7845 
7846   size(4);
7847   format %{ "SRAX   $src1,$src2,$dst" %}
7848   opcode(Assembler::srax_op3, Assembler::arith_op);
7849   ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7850   ins_pipe(ialu_reg_imm);
7851 %}
7852 
7853 // Register Shift Right
7854 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7855   match(Set dst (URShiftI src1 src2));
7856 
7857   size(4);
7858   format %{ "SRL    $src1,$src2,$dst" %}
7859   opcode(Assembler::srl_op3, Assembler::arith_op);
7860   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7861   ins_pipe(ialu_reg_reg);
7862 %}
7863 
7864 // Register Shift Right Immediate
7865 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7866   match(Set dst (URShiftI src1 src2));
7867 
7868   size(4);
7869   format %{ "SRL    $src1,$src2,$dst" %}
7870   opcode(Assembler::srl_op3, Assembler::arith_op);
7871   ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7872   ins_pipe(ialu_reg_imm);
7873 %}
7874 
7875 // Register Shift Right
7876 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7877   match(Set dst (URShiftL src1 src2));
7878 
7879   size(4);
7880   format %{ "SRLX   $src1,$src2,$dst" %}
7881   opcode(Assembler::srlx_op3, Assembler::arith_op);
7882   ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7883   ins_pipe(ialu_reg_reg);
7884 %}
7885 
7886 // Register Shift Right Immediate
7887 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7888   match(Set dst (URShiftL src1 src2));
7889 
7890   size(4);
7891   format %{ "SRLX   $src1,$src2,$dst" %}
7892   opcode(Assembler::srlx_op3, Assembler::arith_op);
7893   ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7894   ins_pipe(ialu_reg_imm);
7895 %}
7896 
7897 // Register Shift Right Immediate with a CastP2X
7898 #ifdef _LP64
7899 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{
7900   match(Set dst (URShiftL (CastP2X src1) src2));
7901   size(4);
7902   format %{ "SRLX   $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %}
7903   opcode(Assembler::srlx_op3, Assembler::arith_op);
7904   ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7905   ins_pipe(ialu_reg_imm);
7906 %}
7907 #else
7908 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{
7909   match(Set dst (URShiftI (CastP2X src1) src2));
7910   size(4);
7911   format %{ "SRL    $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %}
7912   opcode(Assembler::srl_op3, Assembler::arith_op);
7913   ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7914   ins_pipe(ialu_reg_imm);
7915 %}
7916 #endif
7917 
7918 
7919 //----------Floating Point Arithmetic Instructions-----------------------------
7920 
7921 //  Add float single precision
7922 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
7923   match(Set dst (AddF src1 src2));
7924 
7925   size(4);
7926   format %{ "FADDS  $src1,$src2,$dst" %}
7927   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf);
7928   ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7929   ins_pipe(faddF_reg_reg);
7930 %}
7931 
7932 //  Add float double precision
7933 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
7934   match(Set dst (AddD src1 src2));
7935 
7936   size(4);
7937   format %{ "FADDD  $src1,$src2,$dst" %}
7938   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
7939   ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7940   ins_pipe(faddD_reg_reg);
7941 %}
7942 
7943 //  Sub float single precision
7944 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
7945   match(Set dst (SubF src1 src2));
7946 
7947   size(4);
7948   format %{ "FSUBS  $src1,$src2,$dst" %}
7949   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf);
7950   ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7951   ins_pipe(faddF_reg_reg);
7952 %}
7953 
7954 //  Sub float double precision
7955 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
7956   match(Set dst (SubD src1 src2));
7957 
7958   size(4);
7959   format %{ "FSUBD  $src1,$src2,$dst" %}
7960   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
7961   ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7962   ins_pipe(faddD_reg_reg);
7963 %}
7964 
7965 //  Mul float single precision
7966 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
7967   match(Set dst (MulF src1 src2));
7968 
7969   size(4);
7970   format %{ "FMULS  $src1,$src2,$dst" %}
7971   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf);
7972   ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7973   ins_pipe(fmulF_reg_reg);
7974 %}
7975 
7976 //  Mul float double precision
7977 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
7978   match(Set dst (MulD src1 src2));
7979 
7980   size(4);
7981   format %{ "FMULD  $src1,$src2,$dst" %}
7982   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
7983   ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7984   ins_pipe(fmulD_reg_reg);
7985 %}
7986 
7987 //  Div float single precision
7988 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
7989   match(Set dst (DivF src1 src2));
7990 
7991   size(4);
7992   format %{ "FDIVS  $src1,$src2,$dst" %}
7993   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf);
7994   ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7995   ins_pipe(fdivF_reg_reg);
7996 %}
7997 
7998 //  Div float double precision
7999 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
8000   match(Set dst (DivD src1 src2));
8001 
8002   size(4);
8003   format %{ "FDIVD  $src1,$src2,$dst" %}
8004   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf);
8005   ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8006   ins_pipe(fdivD_reg_reg);
8007 %}
8008 
8009 //  Absolute float double precision
8010 instruct absD_reg(regD dst, regD src) %{
8011   match(Set dst (AbsD src));
8012 
8013   format %{ "FABSd  $src,$dst" %}
8014   ins_encode(fabsd(dst, src));
8015   ins_pipe(faddD_reg);
8016 %}
8017 
8018 //  Absolute float single precision
8019 instruct absF_reg(regF dst, regF src) %{
8020   match(Set dst (AbsF src));
8021 
8022   format %{ "FABSs  $src,$dst" %}
8023   ins_encode(fabss(dst, src));
8024   ins_pipe(faddF_reg);
8025 %}
8026 
8027 instruct negF_reg(regF dst, regF src) %{
8028   match(Set dst (NegF src));
8029 
8030   size(4);
8031   format %{ "FNEGs  $src,$dst" %}
8032   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf);
8033   ins_encode(form3_opf_rs2F_rdF(src, dst));
8034   ins_pipe(faddF_reg);
8035 %}
8036 
8037 instruct negD_reg(regD dst, regD src) %{
8038   match(Set dst (NegD src));
8039 
8040   format %{ "FNEGd  $src,$dst" %}
8041   ins_encode(fnegd(dst, src));
8042   ins_pipe(faddD_reg);
8043 %}
8044 
8045 //  Sqrt float double precision
8046 instruct sqrtF_reg_reg(regF dst, regF src) %{
8047   match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
8048 
8049   size(4);
8050   format %{ "FSQRTS $src,$dst" %}
8051   ins_encode(fsqrts(dst, src));
8052   ins_pipe(fdivF_reg_reg);
8053 %}
8054 
8055 //  Sqrt float double precision
8056 instruct sqrtD_reg_reg(regD dst, regD src) %{
8057   match(Set dst (SqrtD src));
8058 
8059   size(4);
8060   format %{ "FSQRTD $src,$dst" %}
8061   ins_encode(fsqrtd(dst, src));
8062   ins_pipe(fdivD_reg_reg);
8063 %}
8064 
8065 //----------Logical Instructions-----------------------------------------------
8066 // And Instructions
8067 // Register And
8068 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
8069   match(Set dst (AndI src1 src2));
8070 
8071   size(4);
8072   format %{ "AND    $src1,$src2,$dst" %}
8073   opcode(Assembler::and_op3, Assembler::arith_op);
8074   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8075   ins_pipe(ialu_reg_reg);
8076 %}
8077 
8078 // Immediate And
8079 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
8080   match(Set dst (AndI src1 src2));
8081 
8082   size(4);
8083   format %{ "AND    $src1,$src2,$dst" %}
8084   opcode(Assembler::and_op3, Assembler::arith_op);
8085   ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
8086   ins_pipe(ialu_reg_imm);
8087 %}
8088 
8089 // Register And Long
8090 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
8091   match(Set dst (AndL src1 src2));
8092 
8093   ins_cost(DEFAULT_COST);
8094   size(4);
8095   format %{ "AND    $src1,$src2,$dst\t! long" %}
8096   opcode(Assembler::and_op3, Assembler::arith_op);
8097   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8098   ins_pipe(ialu_reg_reg);
8099 %}
8100 
8101 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
8102   match(Set dst (AndL src1 con));
8103 
8104   ins_cost(DEFAULT_COST);
8105   size(4);
8106   format %{ "AND    $src1,$con,$dst\t! long" %}
8107   opcode(Assembler::and_op3, Assembler::arith_op);
8108   ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8109   ins_pipe(ialu_reg_imm);
8110 %}
8111 
8112 // Or Instructions
8113 // Register Or
8114 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
8115   match(Set dst (OrI src1 src2));
8116 
8117   size(4);
8118   format %{ "OR     $src1,$src2,$dst" %}
8119   opcode(Assembler::or_op3, Assembler::arith_op);
8120   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8121   ins_pipe(ialu_reg_reg);
8122 %}
8123 
8124 // Immediate Or
8125 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
8126   match(Set dst (OrI src1 src2));
8127 
8128   size(4);
8129   format %{ "OR     $src1,$src2,$dst" %}
8130   opcode(Assembler::or_op3, Assembler::arith_op);
8131   ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
8132   ins_pipe(ialu_reg_imm);
8133 %}
8134 
8135 // Register Or Long
8136 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
8137   match(Set dst (OrL src1 src2));
8138 
8139   ins_cost(DEFAULT_COST);
8140   size(4);
8141   format %{ "OR     $src1,$src2,$dst\t! long" %}
8142   opcode(Assembler::or_op3, Assembler::arith_op);
8143   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8144   ins_pipe(ialu_reg_reg);
8145 %}
8146 
8147 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
8148   match(Set dst (OrL src1 con));
8149   ins_cost(DEFAULT_COST*2);
8150 
8151   ins_cost(DEFAULT_COST);
8152   size(4);
8153   format %{ "OR     $src1,$con,$dst\t! long" %}
8154   opcode(Assembler::or_op3, Assembler::arith_op);
8155   ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8156   ins_pipe(ialu_reg_imm);
8157 %}
8158 
8159 #ifndef _LP64
8160 
8161 // Use sp_ptr_RegP to match G2 (TLS register) without spilling.
8162 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{
8163   match(Set dst (OrI src1 (CastP2X src2)));
8164 
8165   size(4);
8166   format %{ "OR     $src1,$src2,$dst" %}
8167   opcode(Assembler::or_op3, Assembler::arith_op);
8168   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8169   ins_pipe(ialu_reg_reg);
8170 %}
8171 
8172 #else
8173 
8174 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{
8175   match(Set dst (OrL src1 (CastP2X src2)));
8176 
8177   ins_cost(DEFAULT_COST);
8178   size(4);
8179   format %{ "OR     $src1,$src2,$dst\t! long" %}
8180   opcode(Assembler::or_op3, Assembler::arith_op);
8181   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8182   ins_pipe(ialu_reg_reg);
8183 %}
8184 
8185 #endif
8186 
8187 // Xor Instructions
8188 // Register Xor
8189 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
8190   match(Set dst (XorI src1 src2));
8191 
8192   size(4);
8193   format %{ "XOR    $src1,$src2,$dst" %}
8194   opcode(Assembler::xor_op3, Assembler::arith_op);
8195   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8196   ins_pipe(ialu_reg_reg);
8197 %}
8198 
8199 // Immediate Xor
8200 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
8201   match(Set dst (XorI src1 src2));
8202 
8203   size(4);
8204   format %{ "XOR    $src1,$src2,$dst" %}
8205   opcode(Assembler::xor_op3, Assembler::arith_op);
8206   ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
8207   ins_pipe(ialu_reg_imm);
8208 %}
8209 
8210 // Register Xor Long
8211 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
8212   match(Set dst (XorL src1 src2));
8213 
8214   ins_cost(DEFAULT_COST);
8215   size(4);
8216   format %{ "XOR    $src1,$src2,$dst\t! long" %}
8217   opcode(Assembler::xor_op3, Assembler::arith_op);
8218   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8219   ins_pipe(ialu_reg_reg);
8220 %}
8221 
8222 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
8223   match(Set dst (XorL src1 con));
8224 
8225   ins_cost(DEFAULT_COST);
8226   size(4);
8227   format %{ "XOR    $src1,$con,$dst\t! long" %}
8228   opcode(Assembler::xor_op3, Assembler::arith_op);
8229   ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8230   ins_pipe(ialu_reg_imm);
8231 %}
8232 
8233 //----------Convert to Boolean-------------------------------------------------
8234 // Nice hack for 32-bit tests but doesn't work for
8235 // 64-bit pointers.
8236 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{
8237   match(Set dst (Conv2B src));
8238   effect( KILL ccr );
8239   ins_cost(DEFAULT_COST*2);
8240   format %{ "CMP    R_G0,$src\n\t"
8241             "ADDX   R_G0,0,$dst" %}
8242   ins_encode( enc_to_bool( src, dst ) );
8243   ins_pipe(ialu_reg_ialu);
8244 %}
8245 
8246 #ifndef _LP64
8247 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{
8248   match(Set dst (Conv2B src));
8249   effect( KILL ccr );
8250   ins_cost(DEFAULT_COST*2);
8251   format %{ "CMP    R_G0,$src\n\t"
8252             "ADDX   R_G0,0,$dst" %}
8253   ins_encode( enc_to_bool( src, dst ) );
8254   ins_pipe(ialu_reg_ialu);
8255 %}
8256 #else
8257 instruct convP2B( iRegI dst, iRegP src ) %{
8258   match(Set dst (Conv2B src));
8259   ins_cost(DEFAULT_COST*2);
8260   format %{ "MOV    $src,$dst\n\t"
8261             "MOVRNZ $src,1,$dst" %}
8262   ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) );
8263   ins_pipe(ialu_clr_and_mover);
8264 %}
8265 #endif
8266 
8267 instruct cmpLTMask0( iRegI dst, iRegI src, immI0 zero, flagsReg ccr ) %{
8268   match(Set dst (CmpLTMask src zero));
8269   effect(KILL ccr);
8270   size(4);
8271   format %{ "SRA    $src,#31,$dst\t# cmpLTMask0" %}
8272   ins_encode %{
8273     __ sra($src$$Register, 31, $dst$$Register);
8274   %}
8275   ins_pipe(ialu_reg_imm);
8276 %}
8277 
8278 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{
8279   match(Set dst (CmpLTMask p q));
8280   effect( KILL ccr );
8281   ins_cost(DEFAULT_COST*4);
8282   format %{ "CMP    $p,$q\n\t"
8283             "MOV    #0,$dst\n\t"
8284             "BLT,a  .+8\n\t"
8285             "MOV    #-1,$dst" %}
8286   ins_encode( enc_ltmask(p,q,dst) );
8287   ins_pipe(ialu_reg_reg_ialu);
8288 %}
8289 
8290 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
8291   match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8292   effect(KILL ccr, TEMP tmp);
8293   ins_cost(DEFAULT_COST*3);
8294 
8295   format %{ "SUBcc  $p,$q,$p\t! p' = p-q\n\t"
8296             "ADD    $p,$y,$tmp\t! g3=p-q+y\n\t"
8297             "MOVlt  $tmp,$p\t! p' < 0 ? p'+y : p'" %}
8298   ins_encode(enc_cadd_cmpLTMask(p, q, y, tmp));
8299   ins_pipe(cadd_cmpltmask);
8300 %}
8301 
8302 instruct and_cmpLTMask(iRegI p, iRegI q, iRegI y, flagsReg ccr) %{
8303   match(Set p (AndI (CmpLTMask p q) y));
8304   effect(KILL ccr);
8305   ins_cost(DEFAULT_COST*3);
8306 
8307   format %{ "CMP  $p,$q\n\t"
8308             "MOV  $y,$p\n\t"
8309             "MOVge G0,$p" %}
8310   ins_encode %{
8311     __ cmp($p$$Register, $q$$Register);
8312     __ mov($y$$Register, $p$$Register);
8313     __ movcc(Assembler::greaterEqual, false, Assembler::icc, G0, $p$$Register);
8314   %}
8315   ins_pipe(ialu_reg_reg_ialu);
8316 %}
8317 
8318 //-----------------------------------------------------------------
8319 // Direct raw moves between float and general registers using VIS3.
8320 
8321 //  ins_pipe(faddF_reg);
8322 instruct MoveF2I_reg_reg(iRegI dst, regF src) %{
8323   predicate(UseVIS >= 3);
8324   match(Set dst (MoveF2I src));
8325 
8326   format %{ "MOVSTOUW $src,$dst\t! MoveF2I" %}
8327   ins_encode %{
8328     __ movstouw($src$$FloatRegister, $dst$$Register);
8329   %}
8330   ins_pipe(ialu_reg_reg);
8331 %}
8332 
8333 instruct MoveI2F_reg_reg(regF dst, iRegI src) %{
8334   predicate(UseVIS >= 3);
8335   match(Set dst (MoveI2F src));
8336 
8337   format %{ "MOVWTOS $src,$dst\t! MoveI2F" %}
8338   ins_encode %{
8339     __ movwtos($src$$Register, $dst$$FloatRegister);
8340   %}
8341   ins_pipe(ialu_reg_reg);
8342 %}
8343 
8344 instruct MoveD2L_reg_reg(iRegL dst, regD src) %{
8345   predicate(UseVIS >= 3);
8346   match(Set dst (MoveD2L src));
8347 
8348   format %{ "MOVDTOX $src,$dst\t! MoveD2L" %}
8349   ins_encode %{
8350     __ movdtox(as_DoubleFloatRegister($src$$reg), $dst$$Register);
8351   %}
8352   ins_pipe(ialu_reg_reg);
8353 %}
8354 
8355 instruct MoveL2D_reg_reg(regD dst, iRegL src) %{
8356   predicate(UseVIS >= 3);
8357   match(Set dst (MoveL2D src));
8358 
8359   format %{ "MOVXTOD $src,$dst\t! MoveL2D" %}
8360   ins_encode %{
8361     __ movxtod($src$$Register, as_DoubleFloatRegister($dst$$reg));
8362   %}
8363   ins_pipe(ialu_reg_reg);
8364 %}
8365 
8366 
8367 // Raw moves between float and general registers using stack.
8368 
8369 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
8370   match(Set dst (MoveF2I src));
8371   effect(DEF dst, USE src);
8372   ins_cost(MEMORY_REF_COST);
8373 
8374   size(4);
8375   format %{ "LDUW   $src,$dst\t! MoveF2I" %}
8376   opcode(Assembler::lduw_op3);
8377   ins_encode(simple_form3_mem_reg( src, dst ) );
8378   ins_pipe(iload_mem);
8379 %}
8380 
8381 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
8382   match(Set dst (MoveI2F src));
8383   effect(DEF dst, USE src);
8384   ins_cost(MEMORY_REF_COST);
8385 
8386   size(4);
8387   format %{ "LDF    $src,$dst\t! MoveI2F" %}
8388   opcode(Assembler::ldf_op3);
8389   ins_encode(simple_form3_mem_reg(src, dst));
8390   ins_pipe(floadF_stk);
8391 %}
8392 
8393 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
8394   match(Set dst (MoveD2L src));
8395   effect(DEF dst, USE src);
8396   ins_cost(MEMORY_REF_COST);
8397 
8398   size(4);
8399   format %{ "LDX    $src,$dst\t! MoveD2L" %}
8400   opcode(Assembler::ldx_op3);
8401   ins_encode(simple_form3_mem_reg( src, dst ) );
8402   ins_pipe(iload_mem);
8403 %}
8404 
8405 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
8406   match(Set dst (MoveL2D src));
8407   effect(DEF dst, USE src);
8408   ins_cost(MEMORY_REF_COST);
8409 
8410   size(4);
8411   format %{ "LDDF   $src,$dst\t! MoveL2D" %}
8412   opcode(Assembler::lddf_op3);
8413   ins_encode(simple_form3_mem_reg(src, dst));
8414   ins_pipe(floadD_stk);
8415 %}
8416 
8417 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
8418   match(Set dst (MoveF2I src));
8419   effect(DEF dst, USE src);
8420   ins_cost(MEMORY_REF_COST);
8421 
8422   size(4);
8423   format %{ "STF   $src,$dst\t! MoveF2I" %}
8424   opcode(Assembler::stf_op3);
8425   ins_encode(simple_form3_mem_reg(dst, src));
8426   ins_pipe(fstoreF_stk_reg);
8427 %}
8428 
8429 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8430   match(Set dst (MoveI2F src));
8431   effect(DEF dst, USE src);
8432   ins_cost(MEMORY_REF_COST);
8433 
8434   size(4);
8435   format %{ "STW    $src,$dst\t! MoveI2F" %}
8436   opcode(Assembler::stw_op3);
8437   ins_encode(simple_form3_mem_reg( dst, src ) );
8438   ins_pipe(istore_mem_reg);
8439 %}
8440 
8441 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
8442   match(Set dst (MoveD2L src));
8443   effect(DEF dst, USE src);
8444   ins_cost(MEMORY_REF_COST);
8445 
8446   size(4);
8447   format %{ "STDF   $src,$dst\t! MoveD2L" %}
8448   opcode(Assembler::stdf_op3);
8449   ins_encode(simple_form3_mem_reg(dst, src));
8450   ins_pipe(fstoreD_stk_reg);
8451 %}
8452 
8453 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8454   match(Set dst (MoveL2D src));
8455   effect(DEF dst, USE src);
8456   ins_cost(MEMORY_REF_COST);
8457 
8458   size(4);
8459   format %{ "STX    $src,$dst\t! MoveL2D" %}
8460   opcode(Assembler::stx_op3);
8461   ins_encode(simple_form3_mem_reg( dst, src ) );
8462   ins_pipe(istore_mem_reg);
8463 %}
8464 
8465 
8466 //----------Arithmetic Conversion Instructions---------------------------------
8467 // The conversions operations are all Alpha sorted.  Please keep it that way!
8468 
8469 instruct convD2F_reg(regF dst, regD src) %{
8470   match(Set dst (ConvD2F src));
8471   size(4);
8472   format %{ "FDTOS  $src,$dst" %}
8473   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf);
8474   ins_encode(form3_opf_rs2D_rdF(src, dst));
8475   ins_pipe(fcvtD2F);
8476 %}
8477 
8478 
8479 // Convert a double to an int in a float register.
8480 // If the double is a NAN, stuff a zero in instead.
8481 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{
8482   effect(DEF dst, USE src, KILL fcc0);
8483   format %{ "FCMPd  fcc0,$src,$src\t! check for NAN\n\t"
8484             "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8485             "FDTOI  $src,$dst\t! convert in delay slot\n\t"
8486             "FITOS  $dst,$dst\t! change NaN/max-int to valid float\n\t"
8487             "FSUBs  $dst,$dst,$dst\t! cleared only if nan\n"
8488       "skip:" %}
8489   ins_encode(form_d2i_helper(src,dst));
8490   ins_pipe(fcvtD2I);
8491 %}
8492 
8493 instruct convD2I_stk(stackSlotI dst, regD src) %{
8494   match(Set dst (ConvD2I src));
8495   ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8496   expand %{
8497     regF tmp;
8498     convD2I_helper(tmp, src);
8499     regF_to_stkI(dst, tmp);
8500   %}
8501 %}
8502 
8503 instruct convD2I_reg(iRegI dst, regD src) %{
8504   predicate(UseVIS >= 3);
8505   match(Set dst (ConvD2I src));
8506   ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8507   expand %{
8508     regF tmp;
8509     convD2I_helper(tmp, src);
8510     MoveF2I_reg_reg(dst, tmp);
8511   %}
8512 %}
8513 
8514 
8515 // Convert a double to a long in a double register.
8516 // If the double is a NAN, stuff a zero in instead.
8517 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{
8518   effect(DEF dst, USE src, KILL fcc0);
8519   format %{ "FCMPd  fcc0,$src,$src\t! check for NAN\n\t"
8520             "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8521             "FDTOX  $src,$dst\t! convert in delay slot\n\t"
8522             "FXTOD  $dst,$dst\t! change NaN/max-long to valid double\n\t"
8523             "FSUBd  $dst,$dst,$dst\t! cleared only if nan\n"
8524       "skip:" %}
8525   ins_encode(form_d2l_helper(src,dst));
8526   ins_pipe(fcvtD2L);
8527 %}
8528 
8529 instruct convD2L_stk(stackSlotL dst, regD src) %{
8530   match(Set dst (ConvD2L src));
8531   ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8532   expand %{
8533     regD tmp;
8534     convD2L_helper(tmp, src);
8535     regD_to_stkL(dst, tmp);
8536   %}
8537 %}
8538 
8539 instruct convD2L_reg(iRegL dst, regD src) %{
8540   predicate(UseVIS >= 3);
8541   match(Set dst (ConvD2L src));
8542   ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8543   expand %{
8544     regD tmp;
8545     convD2L_helper(tmp, src);
8546     MoveD2L_reg_reg(dst, tmp);
8547   %}
8548 %}
8549 
8550 
8551 instruct convF2D_reg(regD dst, regF src) %{
8552   match(Set dst (ConvF2D src));
8553   format %{ "FSTOD  $src,$dst" %}
8554   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf);
8555   ins_encode(form3_opf_rs2F_rdD(src, dst));
8556   ins_pipe(fcvtF2D);
8557 %}
8558 
8559 
8560 // Convert a float to an int in a float register.
8561 // If the float is a NAN, stuff a zero in instead.
8562 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{
8563   effect(DEF dst, USE src, KILL fcc0);
8564   format %{ "FCMPs  fcc0,$src,$src\t! check for NAN\n\t"
8565             "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8566             "FSTOI  $src,$dst\t! convert in delay slot\n\t"
8567             "FITOS  $dst,$dst\t! change NaN/max-int to valid float\n\t"
8568             "FSUBs  $dst,$dst,$dst\t! cleared only if nan\n"
8569       "skip:" %}
8570   ins_encode(form_f2i_helper(src,dst));
8571   ins_pipe(fcvtF2I);
8572 %}
8573 
8574 instruct convF2I_stk(stackSlotI dst, regF src) %{
8575   match(Set dst (ConvF2I src));
8576   ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8577   expand %{
8578     regF tmp;
8579     convF2I_helper(tmp, src);
8580     regF_to_stkI(dst, tmp);
8581   %}
8582 %}
8583 
8584 instruct convF2I_reg(iRegI dst, regF src) %{
8585   predicate(UseVIS >= 3);
8586   match(Set dst (ConvF2I src));
8587   ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8588   expand %{
8589     regF tmp;
8590     convF2I_helper(tmp, src);
8591     MoveF2I_reg_reg(dst, tmp);
8592   %}
8593 %}
8594 
8595 
8596 // Convert a float to a long in a float register.
8597 // If the float is a NAN, stuff a zero in instead.
8598 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{
8599   effect(DEF dst, USE src, KILL fcc0);
8600   format %{ "FCMPs  fcc0,$src,$src\t! check for NAN\n\t"
8601             "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8602             "FSTOX  $src,$dst\t! convert in delay slot\n\t"
8603             "FXTOD  $dst,$dst\t! change NaN/max-long to valid double\n\t"
8604             "FSUBd  $dst,$dst,$dst\t! cleared only if nan\n"
8605       "skip:" %}
8606   ins_encode(form_f2l_helper(src,dst));
8607   ins_pipe(fcvtF2L);
8608 %}
8609 
8610 instruct convF2L_stk(stackSlotL dst, regF src) %{
8611   match(Set dst (ConvF2L src));
8612   ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8613   expand %{
8614     regD tmp;
8615     convF2L_helper(tmp, src);
8616     regD_to_stkL(dst, tmp);
8617   %}
8618 %}
8619 
8620 instruct convF2L_reg(iRegL dst, regF src) %{
8621   predicate(UseVIS >= 3);
8622   match(Set dst (ConvF2L src));
8623   ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8624   expand %{
8625     regD tmp;
8626     convF2L_helper(tmp, src);
8627     MoveD2L_reg_reg(dst, tmp);
8628   %}
8629 %}
8630 
8631 
8632 instruct convI2D_helper(regD dst, regF tmp) %{
8633   effect(USE tmp, DEF dst);
8634   format %{ "FITOD  $tmp,$dst" %}
8635   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8636   ins_encode(form3_opf_rs2F_rdD(tmp, dst));
8637   ins_pipe(fcvtI2D);
8638 %}
8639 
8640 instruct convI2D_stk(stackSlotI src, regD dst) %{
8641   match(Set dst (ConvI2D src));
8642   ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8643   expand %{
8644     regF tmp;
8645     stkI_to_regF(tmp, src);
8646     convI2D_helper(dst, tmp);
8647   %}
8648 %}
8649 
8650 instruct convI2D_reg(regD_low dst, iRegI src) %{
8651   predicate(UseVIS >= 3);
8652   match(Set dst (ConvI2D src));
8653   expand %{
8654     regF tmp;
8655     MoveI2F_reg_reg(tmp, src);
8656     convI2D_helper(dst, tmp);
8657   %}
8658 %}
8659 
8660 instruct convI2D_mem(regD_low dst, memory mem) %{
8661   match(Set dst (ConvI2D (LoadI mem)));
8662   ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8663   size(8);
8664   format %{ "LDF    $mem,$dst\n\t"
8665             "FITOD  $dst,$dst" %}
8666   opcode(Assembler::ldf_op3, Assembler::fitod_opf);
8667   ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8668   ins_pipe(floadF_mem);
8669 %}
8670 
8671 
8672 instruct convI2F_helper(regF dst, regF tmp) %{
8673   effect(DEF dst, USE tmp);
8674   format %{ "FITOS  $tmp,$dst" %}
8675   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf);
8676   ins_encode(form3_opf_rs2F_rdF(tmp, dst));
8677   ins_pipe(fcvtI2F);
8678 %}
8679 
8680 instruct convI2F_stk(regF dst, stackSlotI src) %{
8681   match(Set dst (ConvI2F src));
8682   ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8683   expand %{
8684     regF tmp;
8685     stkI_to_regF(tmp,src);
8686     convI2F_helper(dst, tmp);
8687   %}
8688 %}
8689 
8690 instruct convI2F_reg(regF dst, iRegI src) %{
8691   predicate(UseVIS >= 3);
8692   match(Set dst (ConvI2F src));
8693   ins_cost(DEFAULT_COST);
8694   expand %{
8695     regF tmp;
8696     MoveI2F_reg_reg(tmp, src);
8697     convI2F_helper(dst, tmp);
8698   %}
8699 %}
8700 
8701 instruct convI2F_mem( regF dst, memory mem ) %{
8702   match(Set dst (ConvI2F (LoadI mem)));
8703   ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8704   size(8);
8705   format %{ "LDF    $mem,$dst\n\t"
8706             "FITOS  $dst,$dst" %}
8707   opcode(Assembler::ldf_op3, Assembler::fitos_opf);
8708   ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8709   ins_pipe(floadF_mem);
8710 %}
8711 
8712 
8713 instruct convI2L_reg(iRegL dst, iRegI src) %{
8714   match(Set dst (ConvI2L src));
8715   size(4);
8716   format %{ "SRA    $src,0,$dst\t! int->long" %}
8717   opcode(Assembler::sra_op3, Assembler::arith_op);
8718   ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8719   ins_pipe(ialu_reg_reg);
8720 %}
8721 
8722 // Zero-extend convert int to long
8723 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{
8724   match(Set dst (AndL (ConvI2L src) mask) );
8725   size(4);
8726   format %{ "SRL    $src,0,$dst\t! zero-extend int to long" %}
8727   opcode(Assembler::srl_op3, Assembler::arith_op);
8728   ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8729   ins_pipe(ialu_reg_reg);
8730 %}
8731 
8732 // Zero-extend long
8733 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{
8734   match(Set dst (AndL src mask) );
8735   size(4);
8736   format %{ "SRL    $src,0,$dst\t! zero-extend long" %}
8737   opcode(Assembler::srl_op3, Assembler::arith_op);
8738   ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8739   ins_pipe(ialu_reg_reg);
8740 %}
8741 
8742 
8743 //-----------
8744 // Long to Double conversion using V8 opcodes.
8745 // Still useful because cheetah traps and becomes
8746 // amazingly slow for some common numbers.
8747 
8748 // Magic constant, 0x43300000
8749 instruct loadConI_x43300000(iRegI dst) %{
8750   effect(DEF dst);
8751   size(4);
8752   format %{ "SETHI  HI(0x43300000),$dst\t! 2^52" %}
8753   ins_encode(SetHi22(0x43300000, dst));
8754   ins_pipe(ialu_none);
8755 %}
8756 
8757 // Magic constant, 0x41f00000
8758 instruct loadConI_x41f00000(iRegI dst) %{
8759   effect(DEF dst);
8760   size(4);
8761   format %{ "SETHI  HI(0x41f00000),$dst\t! 2^32" %}
8762   ins_encode(SetHi22(0x41f00000, dst));
8763   ins_pipe(ialu_none);
8764 %}
8765 
8766 // Construct a double from two float halves
8767 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{
8768   effect(DEF dst, USE src1, USE src2);
8769   size(8);
8770   format %{ "FMOVS  $src1.hi,$dst.hi\n\t"
8771             "FMOVS  $src2.lo,$dst.lo" %}
8772   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf);
8773   ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst));
8774   ins_pipe(faddD_reg_reg);
8775 %}
8776 
8777 // Convert integer in high half of a double register (in the lower half of
8778 // the double register file) to double
8779 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{
8780   effect(DEF dst, USE src);
8781   size(4);
8782   format %{ "FITOD  $src,$dst" %}
8783   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8784   ins_encode(form3_opf_rs2D_rdD(src, dst));
8785   ins_pipe(fcvtLHi2D);
8786 %}
8787 
8788 // Add float double precision
8789 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{
8790   effect(DEF dst, USE src1, USE src2);
8791   size(4);
8792   format %{ "FADDD  $src1,$src2,$dst" %}
8793   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
8794   ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8795   ins_pipe(faddD_reg_reg);
8796 %}
8797 
8798 // Sub float double precision
8799 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{
8800   effect(DEF dst, USE src1, USE src2);
8801   size(4);
8802   format %{ "FSUBD  $src1,$src2,$dst" %}
8803   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
8804   ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8805   ins_pipe(faddD_reg_reg);
8806 %}
8807 
8808 // Mul float double precision
8809 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{
8810   effect(DEF dst, USE src1, USE src2);
8811   size(4);
8812   format %{ "FMULD  $src1,$src2,$dst" %}
8813   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
8814   ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8815   ins_pipe(fmulD_reg_reg);
8816 %}
8817 
8818 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{
8819   match(Set dst (ConvL2D src));
8820   ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6);
8821 
8822   expand %{
8823     regD_low   tmpsrc;
8824     iRegI      ix43300000;
8825     iRegI      ix41f00000;
8826     stackSlotL lx43300000;
8827     stackSlotL lx41f00000;
8828     regD_low   dx43300000;
8829     regD       dx41f00000;
8830     regD       tmp1;
8831     regD_low   tmp2;
8832     regD       tmp3;
8833     regD       tmp4;
8834 
8835     stkL_to_regD(tmpsrc, src);
8836 
8837     loadConI_x43300000(ix43300000);
8838     loadConI_x41f00000(ix41f00000);
8839     regI_to_stkLHi(lx43300000, ix43300000);
8840     regI_to_stkLHi(lx41f00000, ix41f00000);
8841     stkL_to_regD(dx43300000, lx43300000);
8842     stkL_to_regD(dx41f00000, lx41f00000);
8843 
8844     convI2D_regDHi_regD(tmp1, tmpsrc);
8845     regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc);
8846     subD_regD_regD(tmp3, tmp2, dx43300000);
8847     mulD_regD_regD(tmp4, tmp1, dx41f00000);
8848     addD_regD_regD(dst, tmp3, tmp4);
8849   %}
8850 %}
8851 
8852 // Long to Double conversion using fast fxtof
8853 instruct convL2D_helper(regD dst, regD tmp) %{
8854   effect(DEF dst, USE tmp);
8855   size(4);
8856   format %{ "FXTOD  $tmp,$dst" %}
8857   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf);
8858   ins_encode(form3_opf_rs2D_rdD(tmp, dst));
8859   ins_pipe(fcvtL2D);
8860 %}
8861 
8862 instruct convL2D_stk_fast_fxtof(regD dst, stackSlotL src) %{
8863   predicate(VM_Version::has_fast_fxtof());
8864   match(Set dst (ConvL2D src));
8865   ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST);
8866   expand %{
8867     regD tmp;
8868     stkL_to_regD(tmp, src);
8869     convL2D_helper(dst, tmp);
8870   %}
8871 %}
8872 
8873 instruct convL2D_reg(regD dst, iRegL src) %{
8874   predicate(UseVIS >= 3);
8875   match(Set dst (ConvL2D src));
8876   expand %{
8877     regD tmp;
8878     MoveL2D_reg_reg(tmp, src);
8879     convL2D_helper(dst, tmp);
8880   %}
8881 %}
8882 
8883 // Long to Float conversion using fast fxtof
8884 instruct convL2F_helper(regF dst, regD tmp) %{
8885   effect(DEF dst, USE tmp);
8886   size(4);
8887   format %{ "FXTOS  $tmp,$dst" %}
8888   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf);
8889   ins_encode(form3_opf_rs2D_rdF(tmp, dst));
8890   ins_pipe(fcvtL2F);
8891 %}
8892 
8893 instruct convL2F_stk_fast_fxtof(regF dst, stackSlotL src) %{
8894   match(Set dst (ConvL2F src));
8895   ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8896   expand %{
8897     regD tmp;
8898     stkL_to_regD(tmp, src);
8899     convL2F_helper(dst, tmp);
8900   %}
8901 %}
8902 
8903 instruct convL2F_reg(regF dst, iRegL src) %{
8904   predicate(UseVIS >= 3);
8905   match(Set dst (ConvL2F src));
8906   ins_cost(DEFAULT_COST);
8907   expand %{
8908     regD tmp;
8909     MoveL2D_reg_reg(tmp, src);
8910     convL2F_helper(dst, tmp);
8911   %}
8912 %}
8913 
8914 //-----------
8915 
8916 instruct convL2I_reg(iRegI dst, iRegL src) %{
8917   match(Set dst (ConvL2I src));
8918 #ifndef _LP64
8919   format %{ "MOV    $src.lo,$dst\t! long->int" %}
8920   ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) );
8921   ins_pipe(ialu_move_reg_I_to_L);
8922 #else
8923   size(4);
8924   format %{ "SRA    $src,R_G0,$dst\t! long->int" %}
8925   ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) );
8926   ins_pipe(ialu_reg);
8927 #endif
8928 %}
8929 
8930 // Register Shift Right Immediate
8931 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{
8932   match(Set dst (ConvL2I (RShiftL src cnt)));
8933 
8934   size(4);
8935   format %{ "SRAX   $src,$cnt,$dst" %}
8936   opcode(Assembler::srax_op3, Assembler::arith_op);
8937   ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) );
8938   ins_pipe(ialu_reg_imm);
8939 %}
8940 
8941 //----------Control Flow Instructions------------------------------------------
8942 // Compare Instructions
8943 // Compare Integers
8944 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{
8945   match(Set icc (CmpI op1 op2));
8946   effect( DEF icc, USE op1, USE op2 );
8947 
8948   size(4);
8949   format %{ "CMP    $op1,$op2" %}
8950   opcode(Assembler::subcc_op3, Assembler::arith_op);
8951   ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8952   ins_pipe(ialu_cconly_reg_reg);
8953 %}
8954 
8955 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{
8956   match(Set icc (CmpU op1 op2));
8957 
8958   size(4);
8959   format %{ "CMP    $op1,$op2\t! unsigned" %}
8960   opcode(Assembler::subcc_op3, Assembler::arith_op);
8961   ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8962   ins_pipe(ialu_cconly_reg_reg);
8963 %}
8964 
8965 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{
8966   match(Set icc (CmpI op1 op2));
8967   effect( DEF icc, USE op1 );
8968 
8969   size(4);
8970   format %{ "CMP    $op1,$op2" %}
8971   opcode(Assembler::subcc_op3, Assembler::arith_op);
8972   ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8973   ins_pipe(ialu_cconly_reg_imm);
8974 %}
8975 
8976 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{
8977   match(Set icc (CmpI (AndI op1 op2) zero));
8978 
8979   size(4);
8980   format %{ "BTST   $op2,$op1" %}
8981   opcode(Assembler::andcc_op3, Assembler::arith_op);
8982   ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8983   ins_pipe(ialu_cconly_reg_reg_zero);
8984 %}
8985 
8986 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{
8987   match(Set icc (CmpI (AndI op1 op2) zero));
8988 
8989   size(4);
8990   format %{ "BTST   $op2,$op1" %}
8991   opcode(Assembler::andcc_op3, Assembler::arith_op);
8992   ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8993   ins_pipe(ialu_cconly_reg_imm_zero);
8994 %}
8995 
8996 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{
8997   match(Set xcc (CmpL op1 op2));
8998   effect( DEF xcc, USE op1, USE op2 );
8999 
9000   size(4);
9001   format %{ "CMP    $op1,$op2\t\t! long" %}
9002   opcode(Assembler::subcc_op3, Assembler::arith_op);
9003   ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
9004   ins_pipe(ialu_cconly_reg_reg);
9005 %}
9006 
9007 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{
9008   match(Set xcc (CmpL op1 con));
9009   effect( DEF xcc, USE op1, USE con );
9010 
9011   size(4);
9012   format %{ "CMP    $op1,$con\t\t! long" %}
9013   opcode(Assembler::subcc_op3, Assembler::arith_op);
9014   ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
9015   ins_pipe(ialu_cconly_reg_reg);
9016 %}
9017 
9018 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{
9019   match(Set xcc (CmpL (AndL op1 op2) zero));
9020   effect( DEF xcc, USE op1, USE op2 );
9021 
9022   size(4);
9023   format %{ "BTST   $op1,$op2\t\t! long" %}
9024   opcode(Assembler::andcc_op3, Assembler::arith_op);
9025   ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
9026   ins_pipe(ialu_cconly_reg_reg);
9027 %}
9028 
9029 // useful for checking the alignment of a pointer:
9030 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{
9031   match(Set xcc (CmpL (AndL op1 con) zero));
9032   effect( DEF xcc, USE op1, USE con );
9033 
9034   size(4);
9035   format %{ "BTST   $op1,$con\t\t! long" %}
9036   opcode(Assembler::andcc_op3, Assembler::arith_op);
9037   ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
9038   ins_pipe(ialu_cconly_reg_reg);
9039 %}
9040 
9041 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU12 op2 ) %{
9042   match(Set icc (CmpU op1 op2));
9043 
9044   size(4);
9045   format %{ "CMP    $op1,$op2\t! unsigned" %}
9046   opcode(Assembler::subcc_op3, Assembler::arith_op);
9047   ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
9048   ins_pipe(ialu_cconly_reg_imm);
9049 %}
9050 
9051 // Compare Pointers
9052 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{
9053   match(Set pcc (CmpP op1 op2));
9054 
9055   size(4);
9056   format %{ "CMP    $op1,$op2\t! ptr" %}
9057   opcode(Assembler::subcc_op3, Assembler::arith_op);
9058   ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
9059   ins_pipe(ialu_cconly_reg_reg);
9060 %}
9061 
9062 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{
9063   match(Set pcc (CmpP op1 op2));
9064 
9065   size(4);
9066   format %{ "CMP    $op1,$op2\t! ptr" %}
9067   opcode(Assembler::subcc_op3, Assembler::arith_op);
9068   ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
9069   ins_pipe(ialu_cconly_reg_imm);
9070 %}
9071 
9072 // Compare Narrow oops
9073 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{
9074   match(Set icc (CmpN op1 op2));
9075 
9076   size(4);
9077   format %{ "CMP    $op1,$op2\t! compressed ptr" %}
9078   opcode(Assembler::subcc_op3, Assembler::arith_op);
9079   ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
9080   ins_pipe(ialu_cconly_reg_reg);
9081 %}
9082 
9083 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{
9084   match(Set icc (CmpN op1 op2));
9085 
9086   size(4);
9087   format %{ "CMP    $op1,$op2\t! compressed ptr" %}
9088   opcode(Assembler::subcc_op3, Assembler::arith_op);
9089   ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
9090   ins_pipe(ialu_cconly_reg_imm);
9091 %}
9092 
9093 //----------Max and Min--------------------------------------------------------
9094 // Min Instructions
9095 // Conditional move for min
9096 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{
9097   effect( USE_DEF op2, USE op1, USE icc );
9098 
9099   size(4);
9100   format %{ "MOVlt  icc,$op1,$op2\t! min" %}
9101   opcode(Assembler::less);
9102   ins_encode( enc_cmov_reg_minmax(op2,op1) );
9103   ins_pipe(ialu_reg_flags);
9104 %}
9105 
9106 // Min Register with Register.
9107 instruct minI_eReg(iRegI op1, iRegI op2) %{
9108   match(Set op2 (MinI op1 op2));
9109   ins_cost(DEFAULT_COST*2);
9110   expand %{
9111     flagsReg icc;
9112     compI_iReg(icc,op1,op2);
9113     cmovI_reg_lt(op2,op1,icc);
9114   %}
9115 %}
9116 
9117 // Max Instructions
9118 // Conditional move for max
9119 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{
9120   effect( USE_DEF op2, USE op1, USE icc );
9121   format %{ "MOVgt  icc,$op1,$op2\t! max" %}
9122   opcode(Assembler::greater);
9123   ins_encode( enc_cmov_reg_minmax(op2,op1) );
9124   ins_pipe(ialu_reg_flags);
9125 %}
9126 
9127 // Max Register with Register
9128 instruct maxI_eReg(iRegI op1, iRegI op2) %{
9129   match(Set op2 (MaxI op1 op2));
9130   ins_cost(DEFAULT_COST*2);
9131   expand %{
9132     flagsReg icc;
9133     compI_iReg(icc,op1,op2);
9134     cmovI_reg_gt(op2,op1,icc);
9135   %}
9136 %}
9137 
9138 
9139 //----------Float Compares----------------------------------------------------
9140 // Compare floating, generate condition code
9141 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{
9142   match(Set fcc (CmpF src1 src2));
9143 
9144   size(4);
9145   format %{ "FCMPs  $fcc,$src1,$src2" %}
9146   opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf);
9147   ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) );
9148   ins_pipe(faddF_fcc_reg_reg_zero);
9149 %}
9150 
9151 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{
9152   match(Set fcc (CmpD src1 src2));
9153 
9154   size(4);
9155   format %{ "FCMPd  $fcc,$src1,$src2" %}
9156   opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf);
9157   ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) );
9158   ins_pipe(faddD_fcc_reg_reg_zero);
9159 %}
9160 
9161 
9162 // Compare floating, generate -1,0,1
9163 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{
9164   match(Set dst (CmpF3 src1 src2));
9165   effect(KILL fcc0);
9166   ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
9167   format %{ "fcmpl  $dst,$src1,$src2" %}
9168   // Primary = float
9169   opcode( true );
9170   ins_encode( floating_cmp( dst, src1, src2 ) );
9171   ins_pipe( floating_cmp );
9172 %}
9173 
9174 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{
9175   match(Set dst (CmpD3 src1 src2));
9176   effect(KILL fcc0);
9177   ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
9178   format %{ "dcmpl  $dst,$src1,$src2" %}
9179   // Primary = double (not float)
9180   opcode( false );
9181   ins_encode( floating_cmp( dst, src1, src2 ) );
9182   ins_pipe( floating_cmp );
9183 %}
9184 
9185 //----------Branches---------------------------------------------------------
9186 // Jump
9187 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above)
9188 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{
9189   match(Jump switch_val);
9190   effect(TEMP table);
9191 
9192   ins_cost(350);
9193 
9194   format %{  "ADD    $constanttablebase, $constantoffset, O7\n\t"
9195              "LD     [O7 + $switch_val], O7\n\t"
9196              "JUMP   O7" %}
9197   ins_encode %{
9198     // Calculate table address into a register.
9199     Register table_reg;
9200     Register label_reg = O7;
9201     // If we are calculating the size of this instruction don't trust
9202     // zero offsets because they might change when
9203     // MachConstantBaseNode decides to optimize the constant table
9204     // base.
9205     if ((constant_offset() == 0) && !Compile::current()->in_scratch_emit_size()) {
9206       table_reg = $constanttablebase;
9207     } else {
9208       table_reg = O7;
9209       RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7);
9210       __ add($constanttablebase, con_offset, table_reg);
9211     }
9212 
9213     // Jump to base address + switch value
9214     __ ld_ptr(table_reg, $switch_val$$Register, label_reg);
9215     __ jmp(label_reg, G0);
9216     __ delayed()->nop();
9217   %}
9218   ins_pipe(ialu_reg_reg);
9219 %}
9220 
9221 // Direct Branch.  Use V8 version with longer range.
9222 instruct branch(label labl) %{
9223   match(Goto);
9224   effect(USE labl);
9225 
9226   size(8);
9227   ins_cost(BRANCH_COST);
9228   format %{ "BA     $labl" %}
9229   ins_encode %{
9230     Label* L = $labl$$label;
9231     __ ba(*L);
9232     __ delayed()->nop();
9233   %}
9234   ins_avoid_back_to_back(AVOID_BEFORE);
9235   ins_pipe(br);
9236 %}
9237 
9238 // Direct Branch, short with no delay slot
9239 instruct branch_short(label labl) %{
9240   match(Goto);
9241   predicate(UseCBCond);
9242   effect(USE labl);
9243 
9244   size(4);
9245   ins_cost(BRANCH_COST);
9246   format %{ "BA     $labl\t! short branch" %}
9247   ins_encode %{
9248     Label* L = $labl$$label;
9249     assert(__ use_cbcond(*L), "back to back cbcond");
9250     __ ba_short(*L);
9251   %}
9252   ins_short_branch(1);
9253   ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9254   ins_pipe(cbcond_reg_imm);
9255 %}
9256 
9257 // Conditional Direct Branch
9258 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
9259   match(If cmp icc);
9260   effect(USE labl);
9261 
9262   size(8);
9263   ins_cost(BRANCH_COST);
9264   format %{ "BP$cmp   $icc,$labl" %}
9265   // Prim = bits 24-22, Secnd = bits 31-30
9266   ins_encode( enc_bp( labl, cmp, icc ) );
9267   ins_avoid_back_to_back(AVOID_BEFORE);
9268   ins_pipe(br_cc);
9269 %}
9270 
9271 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{
9272   match(If cmp icc);
9273   effect(USE labl);
9274 
9275   ins_cost(BRANCH_COST);
9276   format %{ "BP$cmp  $icc,$labl" %}
9277   // Prim = bits 24-22, Secnd = bits 31-30
9278   ins_encode( enc_bp( labl, cmp, icc ) );
9279   ins_avoid_back_to_back(AVOID_BEFORE);
9280   ins_pipe(br_cc);
9281 %}
9282 
9283 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{
9284   match(If cmp pcc);
9285   effect(USE labl);
9286 
9287   size(8);
9288   ins_cost(BRANCH_COST);
9289   format %{ "BP$cmp  $pcc,$labl" %}
9290   ins_encode %{
9291     Label* L = $labl$$label;
9292     Assembler::Predict predict_taken =
9293       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9294 
9295     __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9296     __ delayed()->nop();
9297   %}
9298   ins_avoid_back_to_back(AVOID_BEFORE);
9299   ins_pipe(br_cc);
9300 %}
9301 
9302 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{
9303   match(If cmp fcc);
9304   effect(USE labl);
9305 
9306   size(8);
9307   ins_cost(BRANCH_COST);
9308   format %{ "FBP$cmp $fcc,$labl" %}
9309   ins_encode %{
9310     Label* L = $labl$$label;
9311     Assembler::Predict predict_taken =
9312       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9313 
9314     __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L);
9315     __ delayed()->nop();
9316   %}
9317   ins_avoid_back_to_back(AVOID_BEFORE);
9318   ins_pipe(br_fcc);
9319 %}
9320 
9321 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
9322   match(CountedLoopEnd cmp icc);
9323   effect(USE labl);
9324 
9325   size(8);
9326   ins_cost(BRANCH_COST);
9327   format %{ "BP$cmp   $icc,$labl\t! Loop end" %}
9328   // Prim = bits 24-22, Secnd = bits 31-30
9329   ins_encode( enc_bp( labl, cmp, icc ) );
9330   ins_avoid_back_to_back(AVOID_BEFORE);
9331   ins_pipe(br_cc);
9332 %}
9333 
9334 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{
9335   match(CountedLoopEnd cmp icc);
9336   effect(USE labl);
9337 
9338   size(8);
9339   ins_cost(BRANCH_COST);
9340   format %{ "BP$cmp  $icc,$labl\t! Loop end" %}
9341   // Prim = bits 24-22, Secnd = bits 31-30
9342   ins_encode( enc_bp( labl, cmp, icc ) );
9343   ins_avoid_back_to_back(AVOID_BEFORE);
9344   ins_pipe(br_cc);
9345 %}
9346 
9347 // Compare and branch instructions
9348 instruct cmpI_reg_branch(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9349   match(If cmp (CmpI op1 op2));
9350   effect(USE labl, KILL icc);
9351 
9352   size(12);
9353   ins_cost(BRANCH_COST);
9354   format %{ "CMP    $op1,$op2\t! int\n\t"
9355             "BP$cmp   $labl" %}
9356   ins_encode %{
9357     Label* L = $labl$$label;
9358     Assembler::Predict predict_taken =
9359       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9360     __ cmp($op1$$Register, $op2$$Register);
9361     __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9362     __ delayed()->nop();
9363   %}
9364   ins_pipe(cmp_br_reg_reg);
9365 %}
9366 
9367 instruct cmpI_imm_branch(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9368   match(If cmp (CmpI op1 op2));
9369   effect(USE labl, KILL icc);
9370 
9371   size(12);
9372   ins_cost(BRANCH_COST);
9373   format %{ "CMP    $op1,$op2\t! int\n\t"
9374             "BP$cmp   $labl" %}
9375   ins_encode %{
9376     Label* L = $labl$$label;
9377     Assembler::Predict predict_taken =
9378       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9379     __ cmp($op1$$Register, $op2$$constant);
9380     __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9381     __ delayed()->nop();
9382   %}
9383   ins_pipe(cmp_br_reg_imm);
9384 %}
9385 
9386 instruct cmpU_reg_branch(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9387   match(If cmp (CmpU op1 op2));
9388   effect(USE labl, KILL icc);
9389 
9390   size(12);
9391   ins_cost(BRANCH_COST);
9392   format %{ "CMP    $op1,$op2\t! unsigned\n\t"
9393             "BP$cmp  $labl" %}
9394   ins_encode %{
9395     Label* L = $labl$$label;
9396     Assembler::Predict predict_taken =
9397       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9398     __ cmp($op1$$Register, $op2$$Register);
9399     __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9400     __ delayed()->nop();
9401   %}
9402   ins_pipe(cmp_br_reg_reg);
9403 %}
9404 
9405 instruct cmpU_imm_branch(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9406   match(If cmp (CmpU op1 op2));
9407   effect(USE labl, KILL icc);
9408 
9409   size(12);
9410   ins_cost(BRANCH_COST);
9411   format %{ "CMP    $op1,$op2\t! unsigned\n\t"
9412             "BP$cmp  $labl" %}
9413   ins_encode %{
9414     Label* L = $labl$$label;
9415     Assembler::Predict predict_taken =
9416       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9417     __ cmp($op1$$Register, $op2$$constant);
9418     __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9419     __ delayed()->nop();
9420   %}
9421   ins_pipe(cmp_br_reg_imm);
9422 %}
9423 
9424 instruct cmpL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9425   match(If cmp (CmpL op1 op2));
9426   effect(USE labl, KILL xcc);
9427 
9428   size(12);
9429   ins_cost(BRANCH_COST);
9430   format %{ "CMP    $op1,$op2\t! long\n\t"
9431             "BP$cmp   $labl" %}
9432   ins_encode %{
9433     Label* L = $labl$$label;
9434     Assembler::Predict predict_taken =
9435       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9436     __ cmp($op1$$Register, $op2$$Register);
9437     __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9438     __ delayed()->nop();
9439   %}
9440   ins_pipe(cmp_br_reg_reg);
9441 %}
9442 
9443 instruct cmpL_imm_branch(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9444   match(If cmp (CmpL op1 op2));
9445   effect(USE labl, KILL xcc);
9446 
9447   size(12);
9448   ins_cost(BRANCH_COST);
9449   format %{ "CMP    $op1,$op2\t! long\n\t"
9450             "BP$cmp   $labl" %}
9451   ins_encode %{
9452     Label* L = $labl$$label;
9453     Assembler::Predict predict_taken =
9454       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9455     __ cmp($op1$$Register, $op2$$constant);
9456     __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9457     __ delayed()->nop();
9458   %}
9459   ins_pipe(cmp_br_reg_imm);
9460 %}
9461 
9462 // Compare Pointers and branch
9463 instruct cmpP_reg_branch(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9464   match(If cmp (CmpP op1 op2));
9465   effect(USE labl, KILL pcc);
9466 
9467   size(12);
9468   ins_cost(BRANCH_COST);
9469   format %{ "CMP    $op1,$op2\t! ptr\n\t"
9470             "B$cmp   $labl" %}
9471   ins_encode %{
9472     Label* L = $labl$$label;
9473     Assembler::Predict predict_taken =
9474       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9475     __ cmp($op1$$Register, $op2$$Register);
9476     __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9477     __ delayed()->nop();
9478   %}
9479   ins_pipe(cmp_br_reg_reg);
9480 %}
9481 
9482 instruct cmpP_null_branch(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9483   match(If cmp (CmpP op1 null));
9484   effect(USE labl, KILL pcc);
9485 
9486   size(12);
9487   ins_cost(BRANCH_COST);
9488   format %{ "CMP    $op1,0\t! ptr\n\t"
9489             "B$cmp   $labl" %}
9490   ins_encode %{
9491     Label* L = $labl$$label;
9492     Assembler::Predict predict_taken =
9493       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9494     __ cmp($op1$$Register, G0);
9495     // bpr() is not used here since it has shorter distance.
9496     __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9497     __ delayed()->nop();
9498   %}
9499   ins_pipe(cmp_br_reg_reg);
9500 %}
9501 
9502 instruct cmpN_reg_branch(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9503   match(If cmp (CmpN op1 op2));
9504   effect(USE labl, KILL icc);
9505 
9506   size(12);
9507   ins_cost(BRANCH_COST);
9508   format %{ "CMP    $op1,$op2\t! compressed ptr\n\t"
9509             "BP$cmp   $labl" %}
9510   ins_encode %{
9511     Label* L = $labl$$label;
9512     Assembler::Predict predict_taken =
9513       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9514     __ cmp($op1$$Register, $op2$$Register);
9515     __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9516     __ delayed()->nop();
9517   %}
9518   ins_pipe(cmp_br_reg_reg);
9519 %}
9520 
9521 instruct cmpN_null_branch(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9522   match(If cmp (CmpN op1 null));
9523   effect(USE labl, KILL icc);
9524 
9525   size(12);
9526   ins_cost(BRANCH_COST);
9527   format %{ "CMP    $op1,0\t! compressed ptr\n\t"
9528             "BP$cmp   $labl" %}
9529   ins_encode %{
9530     Label* L = $labl$$label;
9531     Assembler::Predict predict_taken =
9532       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9533     __ cmp($op1$$Register, G0);
9534     __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9535     __ delayed()->nop();
9536   %}
9537   ins_pipe(cmp_br_reg_reg);
9538 %}
9539 
9540 // Loop back branch
9541 instruct cmpI_reg_branchLoopEnd(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9542   match(CountedLoopEnd cmp (CmpI op1 op2));
9543   effect(USE labl, KILL icc);
9544 
9545   size(12);
9546   ins_cost(BRANCH_COST);
9547   format %{ "CMP    $op1,$op2\t! int\n\t"
9548             "BP$cmp   $labl\t! Loop end" %}
9549   ins_encode %{
9550     Label* L = $labl$$label;
9551     Assembler::Predict predict_taken =
9552       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9553     __ cmp($op1$$Register, $op2$$Register);
9554     __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9555     __ delayed()->nop();
9556   %}
9557   ins_pipe(cmp_br_reg_reg);
9558 %}
9559 
9560 instruct cmpI_imm_branchLoopEnd(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9561   match(CountedLoopEnd cmp (CmpI op1 op2));
9562   effect(USE labl, KILL icc);
9563 
9564   size(12);
9565   ins_cost(BRANCH_COST);
9566   format %{ "CMP    $op1,$op2\t! int\n\t"
9567             "BP$cmp   $labl\t! Loop end" %}
9568   ins_encode %{
9569     Label* L = $labl$$label;
9570     Assembler::Predict predict_taken =
9571       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9572     __ cmp($op1$$Register, $op2$$constant);
9573     __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9574     __ delayed()->nop();
9575   %}
9576   ins_pipe(cmp_br_reg_imm);
9577 %}
9578 
9579 // Short compare and branch instructions
9580 instruct cmpI_reg_branch_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9581   match(If cmp (CmpI op1 op2));
9582   predicate(UseCBCond);
9583   effect(USE labl, KILL icc);
9584 
9585   size(4);
9586   ins_cost(BRANCH_COST);
9587   format %{ "CWB$cmp  $op1,$op2,$labl\t! int" %}
9588   ins_encode %{
9589     Label* L = $labl$$label;
9590     assert(__ use_cbcond(*L), "back to back cbcond");
9591     __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9592   %}
9593   ins_short_branch(1);
9594   ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9595   ins_pipe(cbcond_reg_reg);
9596 %}
9597 
9598 instruct cmpI_imm_branch_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9599   match(If cmp (CmpI op1 op2));
9600   predicate(UseCBCond);
9601   effect(USE labl, KILL icc);
9602 
9603   size(4);
9604   ins_cost(BRANCH_COST);
9605   format %{ "CWB$cmp  $op1,$op2,$labl\t! int" %}
9606   ins_encode %{
9607     Label* L = $labl$$label;
9608     assert(__ use_cbcond(*L), "back to back cbcond");
9609     __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9610   %}
9611   ins_short_branch(1);
9612   ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9613   ins_pipe(cbcond_reg_imm);
9614 %}
9615 
9616 instruct cmpU_reg_branch_short(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9617   match(If cmp (CmpU op1 op2));
9618   predicate(UseCBCond);
9619   effect(USE labl, KILL icc);
9620 
9621   size(4);
9622   ins_cost(BRANCH_COST);
9623   format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9624   ins_encode %{
9625     Label* L = $labl$$label;
9626     assert(__ use_cbcond(*L), "back to back cbcond");
9627     __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9628   %}
9629   ins_short_branch(1);
9630   ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9631   ins_pipe(cbcond_reg_reg);
9632 %}
9633 
9634 instruct cmpU_imm_branch_short(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9635   match(If cmp (CmpU op1 op2));
9636   predicate(UseCBCond);
9637   effect(USE labl, KILL icc);
9638 
9639   size(4);
9640   ins_cost(BRANCH_COST);
9641   format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9642   ins_encode %{
9643     Label* L = $labl$$label;
9644     assert(__ use_cbcond(*L), "back to back cbcond");
9645     __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9646   %}
9647   ins_short_branch(1);
9648   ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9649   ins_pipe(cbcond_reg_imm);
9650 %}
9651 
9652 instruct cmpL_reg_branch_short(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9653   match(If cmp (CmpL op1 op2));
9654   predicate(UseCBCond);
9655   effect(USE labl, KILL xcc);
9656 
9657   size(4);
9658   ins_cost(BRANCH_COST);
9659   format %{ "CXB$cmp  $op1,$op2,$labl\t! long" %}
9660   ins_encode %{
9661     Label* L = $labl$$label;
9662     assert(__ use_cbcond(*L), "back to back cbcond");
9663     __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L);
9664   %}
9665   ins_short_branch(1);
9666   ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9667   ins_pipe(cbcond_reg_reg);
9668 %}
9669 
9670 instruct cmpL_imm_branch_short(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9671   match(If cmp (CmpL op1 op2));
9672   predicate(UseCBCond);
9673   effect(USE labl, KILL xcc);
9674 
9675   size(4);
9676   ins_cost(BRANCH_COST);
9677   format %{ "CXB$cmp  $op1,$op2,$labl\t! long" %}
9678   ins_encode %{
9679     Label* L = $labl$$label;
9680     assert(__ use_cbcond(*L), "back to back cbcond");
9681     __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L);
9682   %}
9683   ins_short_branch(1);
9684   ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9685   ins_pipe(cbcond_reg_imm);
9686 %}
9687 
9688 // Compare Pointers and branch
9689 instruct cmpP_reg_branch_short(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9690   match(If cmp (CmpP op1 op2));
9691   predicate(UseCBCond);
9692   effect(USE labl, KILL pcc);
9693 
9694   size(4);
9695   ins_cost(BRANCH_COST);
9696 #ifdef _LP64
9697   format %{ "CXB$cmp $op1,$op2,$labl\t! ptr" %}
9698 #else
9699   format %{ "CWB$cmp $op1,$op2,$labl\t! ptr" %}
9700 #endif
9701   ins_encode %{
9702     Label* L = $labl$$label;
9703     assert(__ use_cbcond(*L), "back to back cbcond");
9704     __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, $op2$$Register, *L);
9705   %}
9706   ins_short_branch(1);
9707   ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9708   ins_pipe(cbcond_reg_reg);
9709 %}
9710 
9711 instruct cmpP_null_branch_short(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9712   match(If cmp (CmpP op1 null));
9713   predicate(UseCBCond);
9714   effect(USE labl, KILL pcc);
9715 
9716   size(4);
9717   ins_cost(BRANCH_COST);
9718 #ifdef _LP64
9719   format %{ "CXB$cmp $op1,0,$labl\t! ptr" %}
9720 #else
9721   format %{ "CWB$cmp $op1,0,$labl\t! ptr" %}
9722 #endif
9723   ins_encode %{
9724     Label* L = $labl$$label;
9725     assert(__ use_cbcond(*L), "back to back cbcond");
9726     __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, G0, *L);
9727   %}
9728   ins_short_branch(1);
9729   ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9730   ins_pipe(cbcond_reg_reg);
9731 %}
9732 
9733 instruct cmpN_reg_branch_short(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9734   match(If cmp (CmpN op1 op2));
9735   predicate(UseCBCond);
9736   effect(USE labl, KILL icc);
9737 
9738   size(4);
9739   ins_cost(BRANCH_COST);
9740   format %{ "CWB$cmp  $op1,op2,$labl\t! compressed ptr" %}
9741   ins_encode %{
9742     Label* L = $labl$$label;
9743     assert(__ use_cbcond(*L), "back to back cbcond");
9744     __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9745   %}
9746   ins_short_branch(1);
9747   ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9748   ins_pipe(cbcond_reg_reg);
9749 %}
9750 
9751 instruct cmpN_null_branch_short(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9752   match(If cmp (CmpN op1 null));
9753   predicate(UseCBCond);
9754   effect(USE labl, KILL icc);
9755 
9756   size(4);
9757   ins_cost(BRANCH_COST);
9758   format %{ "CWB$cmp  $op1,0,$labl\t! compressed ptr" %}
9759   ins_encode %{
9760     Label* L = $labl$$label;
9761     assert(__ use_cbcond(*L), "back to back cbcond");
9762     __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, G0, *L);
9763   %}
9764   ins_short_branch(1);
9765   ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9766   ins_pipe(cbcond_reg_reg);
9767 %}
9768 
9769 // Loop back branch
9770 instruct cmpI_reg_branchLoopEnd_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9771   match(CountedLoopEnd cmp (CmpI op1 op2));
9772   predicate(UseCBCond);
9773   effect(USE labl, KILL icc);
9774 
9775   size(4);
9776   ins_cost(BRANCH_COST);
9777   format %{ "CWB$cmp  $op1,$op2,$labl\t! Loop end" %}
9778   ins_encode %{
9779     Label* L = $labl$$label;
9780     assert(__ use_cbcond(*L), "back to back cbcond");
9781     __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9782   %}
9783   ins_short_branch(1);
9784   ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9785   ins_pipe(cbcond_reg_reg);
9786 %}
9787 
9788 instruct cmpI_imm_branchLoopEnd_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9789   match(CountedLoopEnd cmp (CmpI op1 op2));
9790   predicate(UseCBCond);
9791   effect(USE labl, KILL icc);
9792 
9793   size(4);
9794   ins_cost(BRANCH_COST);
9795   format %{ "CWB$cmp  $op1,$op2,$labl\t! Loop end" %}
9796   ins_encode %{
9797     Label* L = $labl$$label;
9798     assert(__ use_cbcond(*L), "back to back cbcond");
9799     __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9800   %}
9801   ins_short_branch(1);
9802   ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9803   ins_pipe(cbcond_reg_imm);
9804 %}
9805 
9806 // Branch-on-register tests all 64 bits.  We assume that values
9807 // in 64-bit registers always remains zero or sign extended
9808 // unless our code munges the high bits.  Interrupts can chop
9809 // the high order bits to zero or sign at any time.
9810 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{
9811   match(If cmp (CmpI op1 zero));
9812   predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9813   effect(USE labl);
9814 
9815   size(8);
9816   ins_cost(BRANCH_COST);
9817   format %{ "BR$cmp   $op1,$labl" %}
9818   ins_encode( enc_bpr( labl, cmp, op1 ) );
9819   ins_avoid_back_to_back(AVOID_BEFORE);
9820   ins_pipe(br_reg);
9821 %}
9822 
9823 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{
9824   match(If cmp (CmpP op1 null));
9825   predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9826   effect(USE labl);
9827 
9828   size(8);
9829   ins_cost(BRANCH_COST);
9830   format %{ "BR$cmp   $op1,$labl" %}
9831   ins_encode( enc_bpr( labl, cmp, op1 ) );
9832   ins_avoid_back_to_back(AVOID_BEFORE);
9833   ins_pipe(br_reg);
9834 %}
9835 
9836 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{
9837   match(If cmp (CmpL op1 zero));
9838   predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9839   effect(USE labl);
9840 
9841   size(8);
9842   ins_cost(BRANCH_COST);
9843   format %{ "BR$cmp   $op1,$labl" %}
9844   ins_encode( enc_bpr( labl, cmp, op1 ) );
9845   ins_avoid_back_to_back(AVOID_BEFORE);
9846   ins_pipe(br_reg);
9847 %}
9848 
9849 
9850 // ============================================================================
9851 // Long Compare
9852 //
9853 // Currently we hold longs in 2 registers.  Comparing such values efficiently
9854 // is tricky.  The flavor of compare used depends on whether we are testing
9855 // for LT, LE, or EQ.  For a simple LT test we can check just the sign bit.
9856 // The GE test is the negated LT test.  The LE test can be had by commuting
9857 // the operands (yielding a GE test) and then negating; negate again for the
9858 // GT test.  The EQ test is done by ORcc'ing the high and low halves, and the
9859 // NE test is negated from that.
9860 
9861 // Due to a shortcoming in the ADLC, it mixes up expressions like:
9862 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)).  Note the
9863 // difference between 'Y' and '0L'.  The tree-matches for the CmpI sections
9864 // are collapsed internally in the ADLC's dfa-gen code.  The match for
9865 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
9866 // foo match ends up with the wrong leaf.  One fix is to not match both
9867 // reg-reg and reg-zero forms of long-compare.  This is unfortunate because
9868 // both forms beat the trinary form of long-compare and both are very useful
9869 // on Intel which has so few registers.
9870 
9871 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{
9872   match(If cmp xcc);
9873   effect(USE labl);
9874 
9875   size(8);
9876   ins_cost(BRANCH_COST);
9877   format %{ "BP$cmp   $xcc,$labl" %}
9878   ins_encode %{
9879     Label* L = $labl$$label;
9880     Assembler::Predict predict_taken =
9881       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9882 
9883     __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9884     __ delayed()->nop();
9885   %}
9886   ins_avoid_back_to_back(AVOID_BEFORE);
9887   ins_pipe(br_cc);
9888 %}
9889 
9890 // Manifest a CmpL3 result in an integer register.  Very painful.
9891 // This is the test to avoid.
9892 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{
9893   match(Set dst (CmpL3 src1 src2) );
9894   effect( KILL ccr );
9895   ins_cost(6*DEFAULT_COST);
9896   size(24);
9897   format %{ "CMP    $src1,$src2\t\t! long\n"
9898           "\tBLT,a,pn done\n"
9899           "\tMOV    -1,$dst\t! delay slot\n"
9900           "\tBGT,a,pn done\n"
9901           "\tMOV    1,$dst\t! delay slot\n"
9902           "\tCLR    $dst\n"
9903     "done:"     %}
9904   ins_encode( cmpl_flag(src1,src2,dst) );
9905   ins_pipe(cmpL_reg);
9906 %}
9907 
9908 // Conditional move
9909 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{
9910   match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9911   ins_cost(150);
9912   format %{ "MOV$cmp  $xcc,$src,$dst\t! long" %}
9913   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9914   ins_pipe(ialu_reg);
9915 %}
9916 
9917 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{
9918   match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9919   ins_cost(140);
9920   format %{ "MOV$cmp  $xcc,$src,$dst\t! long" %}
9921   ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9922   ins_pipe(ialu_imm);
9923 %}
9924 
9925 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{
9926   match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9927   ins_cost(150);
9928   format %{ "MOV$cmp  $xcc,$src,$dst" %}
9929   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9930   ins_pipe(ialu_reg);
9931 %}
9932 
9933 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{
9934   match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9935   ins_cost(140);
9936   format %{ "MOV$cmp  $xcc,$src,$dst" %}
9937   ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9938   ins_pipe(ialu_imm);
9939 %}
9940 
9941 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{
9942   match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src)));
9943   ins_cost(150);
9944   format %{ "MOV$cmp  $xcc,$src,$dst" %}
9945   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9946   ins_pipe(ialu_reg);
9947 %}
9948 
9949 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{
9950   match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9951   ins_cost(150);
9952   format %{ "MOV$cmp  $xcc,$src,$dst" %}
9953   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9954   ins_pipe(ialu_reg);
9955 %}
9956 
9957 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{
9958   match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9959   ins_cost(140);
9960   format %{ "MOV$cmp  $xcc,$src,$dst" %}
9961   ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9962   ins_pipe(ialu_imm);
9963 %}
9964 
9965 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{
9966   match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src)));
9967   ins_cost(150);
9968   opcode(0x101);
9969   format %{ "FMOVS$cmp $xcc,$src,$dst" %}
9970   ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9971   ins_pipe(int_conditional_float_move);
9972 %}
9973 
9974 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{
9975   match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src)));
9976   ins_cost(150);
9977   opcode(0x102);
9978   format %{ "FMOVD$cmp $xcc,$src,$dst" %}
9979   ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9980   ins_pipe(int_conditional_float_move);
9981 %}
9982 
9983 // ============================================================================
9984 // Safepoint Instruction
9985 instruct safePoint_poll(iRegP poll) %{
9986   match(SafePoint poll);
9987   effect(USE poll);
9988 
9989   size(4);
9990 #ifdef _LP64
9991   format %{ "LDX    [$poll],R_G0\t! Safepoint: poll for GC" %}
9992 #else
9993   format %{ "LDUW   [$poll],R_G0\t! Safepoint: poll for GC" %}
9994 #endif
9995   ins_encode %{
9996     __ relocate(relocInfo::poll_type);
9997     __ ld_ptr($poll$$Register, 0, G0);
9998   %}
9999   ins_pipe(loadPollP);
10000 %}
10001 
10002 // ============================================================================
10003 // Call Instructions
10004 // Call Java Static Instruction
10005 instruct CallStaticJavaDirect( method meth ) %{
10006   match(CallStaticJava);
10007   predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
10008   effect(USE meth);
10009 
10010   size(8);
10011   ins_cost(CALL_COST);
10012   format %{ "CALL,static  ; NOP ==> " %}
10013   ins_encode( Java_Static_Call( meth ), call_epilog );
10014   ins_avoid_back_to_back(AVOID_BEFORE);
10015   ins_pipe(simple_call);
10016 %}
10017 
10018 // Call Java Static Instruction (method handle version)
10019 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{
10020   match(CallStaticJava);
10021   predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
10022   effect(USE meth, KILL l7_mh_SP_save);
10023 
10024   size(16);
10025   ins_cost(CALL_COST);
10026   format %{ "CALL,static/MethodHandle" %}
10027   ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog);
10028   ins_pipe(simple_call);
10029 %}
10030 
10031 // Call Java Dynamic Instruction
10032 instruct CallDynamicJavaDirect( method meth ) %{
10033   match(CallDynamicJava);
10034   effect(USE meth);
10035 
10036   ins_cost(CALL_COST);
10037   format %{ "SET    (empty),R_G5\n\t"
10038             "CALL,dynamic  ; NOP ==> " %}
10039   ins_encode( Java_Dynamic_Call( meth ), call_epilog );
10040   ins_pipe(call);
10041 %}
10042 
10043 // Call Runtime Instruction
10044 instruct CallRuntimeDirect(method meth, l7RegP l7) %{
10045   match(CallRuntime);
10046   effect(USE meth, KILL l7);
10047   ins_cost(CALL_COST);
10048   format %{ "CALL,runtime" %}
10049   ins_encode( Java_To_Runtime( meth ),
10050               call_epilog, adjust_long_from_native_call );
10051   ins_avoid_back_to_back(AVOID_BEFORE);
10052   ins_pipe(simple_call);
10053 %}
10054 
10055 // Call runtime without safepoint - same as CallRuntime
10056 instruct CallLeafDirect(method meth, l7RegP l7) %{
10057   match(CallLeaf);
10058   effect(USE meth, KILL l7);
10059   ins_cost(CALL_COST);
10060   format %{ "CALL,runtime leaf" %}
10061   ins_encode( Java_To_Runtime( meth ),
10062               call_epilog,
10063               adjust_long_from_native_call );
10064   ins_avoid_back_to_back(AVOID_BEFORE);
10065   ins_pipe(simple_call);
10066 %}
10067 
10068 // Call runtime without safepoint - same as CallLeaf
10069 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{
10070   match(CallLeafNoFP);
10071   effect(USE meth, KILL l7);
10072   ins_cost(CALL_COST);
10073   format %{ "CALL,runtime leaf nofp" %}
10074   ins_encode( Java_To_Runtime( meth ),
10075               call_epilog,
10076               adjust_long_from_native_call );
10077   ins_avoid_back_to_back(AVOID_BEFORE);
10078   ins_pipe(simple_call);
10079 %}
10080 
10081 // Tail Call; Jump from runtime stub to Java code.
10082 // Also known as an 'interprocedural jump'.
10083 // Target of jump will eventually return to caller.
10084 // TailJump below removes the return address.
10085 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{
10086   match(TailCall jump_target method_oop );
10087 
10088   ins_cost(CALL_COST);
10089   format %{ "Jmp     $jump_target  ; NOP \t! $method_oop holds method oop" %}
10090   ins_encode(form_jmpl(jump_target));
10091   ins_avoid_back_to_back(AVOID_BEFORE);
10092   ins_pipe(tail_call);
10093 %}
10094 
10095 
10096 // Return Instruction
10097 instruct Ret() %{
10098   match(Return);
10099 
10100   // The epilogue node did the ret already.
10101   size(0);
10102   format %{ "! return" %}
10103   ins_encode();
10104   ins_pipe(empty);
10105 %}
10106 
10107 
10108 // Tail Jump; remove the return address; jump to target.
10109 // TailCall above leaves the return address around.
10110 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
10111 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
10112 // "restore" before this instruction (in Epilogue), we need to materialize it
10113 // in %i0.
10114 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{
10115   match( TailJump jump_target ex_oop );
10116   ins_cost(CALL_COST);
10117   format %{ "! discard R_O7\n\t"
10118             "Jmp     $jump_target  ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %}
10119   ins_encode(form_jmpl_set_exception_pc(jump_target));
10120   // opcode(Assembler::jmpl_op3, Assembler::arith_op);
10121   // The hack duplicates the exception oop into G3, so that CreateEx can use it there.
10122   // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() );
10123   ins_avoid_back_to_back(AVOID_BEFORE);
10124   ins_pipe(tail_call);
10125 %}
10126 
10127 // Create exception oop: created by stack-crawling runtime code.
10128 // Created exception is now available to this handler, and is setup
10129 // just prior to jumping to this handler.  No code emitted.
10130 instruct CreateException( o0RegP ex_oop )
10131 %{
10132   match(Set ex_oop (CreateEx));
10133   ins_cost(0);
10134 
10135   size(0);
10136   // use the following format syntax
10137   format %{ "! exception oop is in R_O0; no code emitted" %}
10138   ins_encode();
10139   ins_pipe(empty);
10140 %}
10141 
10142 
10143 // Rethrow exception:
10144 // The exception oop will come in the first argument position.
10145 // Then JUMP (not call) to the rethrow stub code.
10146 instruct RethrowException()
10147 %{
10148   match(Rethrow);
10149   ins_cost(CALL_COST);
10150 
10151   // use the following format syntax
10152   format %{ "Jmp    rethrow_stub" %}
10153   ins_encode(enc_rethrow);
10154   ins_avoid_back_to_back(AVOID_BEFORE);
10155   ins_pipe(tail_call);
10156 %}
10157 
10158 
10159 // Die now
10160 instruct ShouldNotReachHere( )
10161 %{
10162   match(Halt);
10163   ins_cost(CALL_COST);
10164 
10165   size(4);
10166   // Use the following format syntax
10167   format %{ "ILLTRAP   ; ShouldNotReachHere" %}
10168   ins_encode( form2_illtrap() );
10169   ins_pipe(tail_call);
10170 %}
10171 
10172 // ============================================================================
10173 // The 2nd slow-half of a subtype check.  Scan the subklass's 2ndary superklass
10174 // array for an instance of the superklass.  Set a hidden internal cache on a
10175 // hit (cache is checked with exposed code in gen_subtype_check()).  Return
10176 // not zero for a miss or zero for a hit.  The encoding ALSO sets flags.
10177 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{
10178   match(Set index (PartialSubtypeCheck sub super));
10179   effect( KILL pcc, KILL o7 );
10180   ins_cost(DEFAULT_COST*10);
10181   format %{ "CALL   PartialSubtypeCheck\n\tNOP" %}
10182   ins_encode( enc_PartialSubtypeCheck() );
10183   ins_avoid_back_to_back(AVOID_BEFORE);
10184   ins_pipe(partial_subtype_check_pipe);
10185 %}
10186 
10187 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{
10188   match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero));
10189   effect( KILL idx, KILL o7 );
10190   ins_cost(DEFAULT_COST*10);
10191   format %{ "CALL   PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %}
10192   ins_encode( enc_PartialSubtypeCheck() );
10193   ins_avoid_back_to_back(AVOID_BEFORE);
10194   ins_pipe(partial_subtype_check_pipe);
10195 %}
10196 
10197 
10198 // ============================================================================
10199 // inlined locking and unlocking
10200 
10201 instruct cmpFastLock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
10202   match(Set pcc (FastLock object box));
10203 
10204   effect(TEMP scratch2, USE_KILL box, KILL scratch);
10205   ins_cost(100);
10206 
10207   format %{ "FASTLOCK  $object,$box\t! kills $box,$scratch,$scratch2" %}
10208   ins_encode( Fast_Lock(object, box, scratch, scratch2) );
10209   ins_pipe(long_memory_op);
10210 %}
10211 
10212 
10213 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
10214   match(Set pcc (FastUnlock object box));
10215   effect(TEMP scratch2, USE_KILL box, KILL scratch);
10216   ins_cost(100);
10217 
10218   format %{ "FASTUNLOCK  $object,$box\t! kills $box,$scratch,$scratch2" %}
10219   ins_encode( Fast_Unlock(object, box, scratch, scratch2) );
10220   ins_pipe(long_memory_op);
10221 %}
10222 
10223 // The encodings are generic.
10224 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{
10225   predicate(!use_block_zeroing(n->in(2)) );
10226   match(Set dummy (ClearArray cnt base));
10227   effect(TEMP temp, KILL ccr);
10228   ins_cost(300);
10229   format %{ "MOV    $cnt,$temp\n"
10230     "loop:   SUBcc  $temp,8,$temp\t! Count down a dword of bytes\n"
10231     "        BRge   loop\t\t! Clearing loop\n"
10232     "        STX    G0,[$base+$temp]\t! delay slot" %}
10233 
10234   ins_encode %{
10235     // Compiler ensures base is doubleword aligned and cnt is count of doublewords
10236     Register nof_bytes_arg    = $cnt$$Register;
10237     Register nof_bytes_tmp    = $temp$$Register;
10238     Register base_pointer_arg = $base$$Register;
10239 
10240     Label loop;
10241     __ mov(nof_bytes_arg, nof_bytes_tmp);
10242 
10243     // Loop and clear, walking backwards through the array.
10244     // nof_bytes_tmp (if >0) is always the number of bytes to zero
10245     __ bind(loop);
10246     __ deccc(nof_bytes_tmp, 8);
10247     __ br(Assembler::greaterEqual, true, Assembler::pt, loop);
10248     __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp);
10249     // %%%% this mini-loop must not cross a cache boundary!
10250   %}
10251   ins_pipe(long_memory_op);
10252 %}
10253 
10254 instruct clear_array_bis(g1RegX cnt, o0RegP base, Universe dummy, flagsReg ccr) %{
10255   predicate(use_block_zeroing(n->in(2)));
10256   match(Set dummy (ClearArray cnt base));
10257   effect(USE_KILL cnt, USE_KILL base, KILL ccr);
10258   ins_cost(300);
10259   format %{ "CLEAR  [$base, $cnt]\t! ClearArray" %}
10260 
10261   ins_encode %{
10262 
10263     assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
10264     Register to    = $base$$Register;
10265     Register count = $cnt$$Register;
10266 
10267     Label Ldone;
10268     __ nop(); // Separate short branches
10269     // Use BIS for zeroing (temp is not used).
10270     __ bis_zeroing(to, count, G0, Ldone);
10271     __ bind(Ldone);
10272 
10273   %}
10274   ins_pipe(long_memory_op);
10275 %}
10276 
10277 instruct clear_array_bis_2(g1RegX cnt, o0RegP base, iRegX tmp, Universe dummy, flagsReg ccr) %{
10278   predicate(use_block_zeroing(n->in(2)) && !Assembler::is_simm13((int)BlockZeroingLowLimit));
10279   match(Set dummy (ClearArray cnt base));
10280   effect(TEMP tmp, USE_KILL cnt, USE_KILL base, KILL ccr);
10281   ins_cost(300);
10282   format %{ "CLEAR  [$base, $cnt]\t! ClearArray" %}
10283 
10284   ins_encode %{
10285 
10286     assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
10287     Register to    = $base$$Register;
10288     Register count = $cnt$$Register;
10289     Register temp  = $tmp$$Register;
10290 
10291     Label Ldone;
10292     __ nop(); // Separate short branches
10293     // Use BIS for zeroing
10294     __ bis_zeroing(to, count, temp, Ldone);
10295     __ bind(Ldone);
10296 
10297   %}
10298   ins_pipe(long_memory_op);
10299 %}
10300 
10301 instruct string_compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10302                         o7RegI tmp, flagsReg ccr) %{
10303   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10304   effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp);
10305   ins_cost(300);
10306   format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result   // KILL $tmp" %}
10307   ins_encode( enc_String_Compare(str1, str2, cnt1, cnt2, result) );
10308   ins_pipe(long_memory_op);
10309 %}
10310 
10311 instruct string_equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result,
10312                        o7RegI tmp, flagsReg ccr) %{
10313   match(Set result (StrEquals (Binary str1 str2) cnt));
10314   effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr);
10315   ins_cost(300);
10316   format %{ "String Equals $str1,$str2,$cnt -> $result   // KILL $tmp" %}
10317   ins_encode( enc_String_Equals(str1, str2, cnt, result) );
10318   ins_pipe(long_memory_op);
10319 %}
10320 
10321 instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result,
10322                       o7RegI tmp2, flagsReg ccr) %{
10323   match(Set result (AryEq ary1 ary2));
10324   effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
10325   ins_cost(300);
10326   format %{ "Array Equals $ary1,$ary2 -> $result   // KILL $tmp1,$tmp2" %}
10327   ins_encode( enc_Array_Equals(ary1, ary2, tmp1, result));
10328   ins_pipe(long_memory_op);
10329 %}
10330 
10331 
10332 //---------- Zeros Count Instructions ------------------------------------------
10333 
10334 instruct countLeadingZerosI(iRegIsafe dst, iRegI src, iRegI tmp, flagsReg cr) %{
10335   predicate(UsePopCountInstruction);  // See Matcher::match_rule_supported
10336   match(Set dst (CountLeadingZerosI src));
10337   effect(TEMP dst, TEMP tmp, KILL cr);
10338 
10339   // x |= (x >> 1);
10340   // x |= (x >> 2);
10341   // x |= (x >> 4);
10342   // x |= (x >> 8);
10343   // x |= (x >> 16);
10344   // return (WORDBITS - popc(x));
10345   format %{ "SRL     $src,1,$tmp\t! count leading zeros (int)\n\t"
10346             "SRL     $src,0,$dst\t! 32-bit zero extend\n\t"
10347             "OR      $dst,$tmp,$dst\n\t"
10348             "SRL     $dst,2,$tmp\n\t"
10349             "OR      $dst,$tmp,$dst\n\t"
10350             "SRL     $dst,4,$tmp\n\t"
10351             "OR      $dst,$tmp,$dst\n\t"
10352             "SRL     $dst,8,$tmp\n\t"
10353             "OR      $dst,$tmp,$dst\n\t"
10354             "SRL     $dst,16,$tmp\n\t"
10355             "OR      $dst,$tmp,$dst\n\t"
10356             "POPC    $dst,$dst\n\t"
10357             "MOV     32,$tmp\n\t"
10358             "SUB     $tmp,$dst,$dst" %}
10359   ins_encode %{
10360     Register Rdst = $dst$$Register;
10361     Register Rsrc = $src$$Register;
10362     Register Rtmp = $tmp$$Register;
10363     __ srl(Rsrc, 1,    Rtmp);
10364     __ srl(Rsrc, 0,    Rdst);
10365     __ or3(Rdst, Rtmp, Rdst);
10366     __ srl(Rdst, 2,    Rtmp);
10367     __ or3(Rdst, Rtmp, Rdst);
10368     __ srl(Rdst, 4,    Rtmp);
10369     __ or3(Rdst, Rtmp, Rdst);
10370     __ srl(Rdst, 8,    Rtmp);
10371     __ or3(Rdst, Rtmp, Rdst);
10372     __ srl(Rdst, 16,   Rtmp);
10373     __ or3(Rdst, Rtmp, Rdst);
10374     __ popc(Rdst, Rdst);
10375     __ mov(BitsPerInt, Rtmp);
10376     __ sub(Rtmp, Rdst, Rdst);
10377   %}
10378   ins_pipe(ialu_reg);
10379 %}
10380 
10381 instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{
10382   predicate(UsePopCountInstruction);  // See Matcher::match_rule_supported
10383   match(Set dst (CountLeadingZerosL src));
10384   effect(TEMP dst, TEMP tmp, KILL cr);
10385 
10386   // x |= (x >> 1);
10387   // x |= (x >> 2);
10388   // x |= (x >> 4);
10389   // x |= (x >> 8);
10390   // x |= (x >> 16);
10391   // x |= (x >> 32);
10392   // return (WORDBITS - popc(x));
10393   format %{ "SRLX    $src,1,$tmp\t! count leading zeros (long)\n\t"
10394             "OR      $src,$tmp,$dst\n\t"
10395             "SRLX    $dst,2,$tmp\n\t"
10396             "OR      $dst,$tmp,$dst\n\t"
10397             "SRLX    $dst,4,$tmp\n\t"
10398             "OR      $dst,$tmp,$dst\n\t"
10399             "SRLX    $dst,8,$tmp\n\t"
10400             "OR      $dst,$tmp,$dst\n\t"
10401             "SRLX    $dst,16,$tmp\n\t"
10402             "OR      $dst,$tmp,$dst\n\t"
10403             "SRLX    $dst,32,$tmp\n\t"
10404             "OR      $dst,$tmp,$dst\n\t"
10405             "POPC    $dst,$dst\n\t"
10406             "MOV     64,$tmp\n\t"
10407             "SUB     $tmp,$dst,$dst" %}
10408   ins_encode %{
10409     Register Rdst = $dst$$Register;
10410     Register Rsrc = $src$$Register;
10411     Register Rtmp = $tmp$$Register;
10412     __ srlx(Rsrc, 1,    Rtmp);
10413     __ or3( Rsrc, Rtmp, Rdst);
10414     __ srlx(Rdst, 2,    Rtmp);
10415     __ or3( Rdst, Rtmp, Rdst);
10416     __ srlx(Rdst, 4,    Rtmp);
10417     __ or3( Rdst, Rtmp, Rdst);
10418     __ srlx(Rdst, 8,    Rtmp);
10419     __ or3( Rdst, Rtmp, Rdst);
10420     __ srlx(Rdst, 16,   Rtmp);
10421     __ or3( Rdst, Rtmp, Rdst);
10422     __ srlx(Rdst, 32,   Rtmp);
10423     __ or3( Rdst, Rtmp, Rdst);
10424     __ popc(Rdst, Rdst);
10425     __ mov(BitsPerLong, Rtmp);
10426     __ sub(Rtmp, Rdst, Rdst);
10427   %}
10428   ins_pipe(ialu_reg);
10429 %}
10430 
10431 instruct countTrailingZerosI(iRegIsafe dst, iRegI src, flagsReg cr) %{
10432   predicate(UsePopCountInstruction);  // See Matcher::match_rule_supported
10433   match(Set dst (CountTrailingZerosI src));
10434   effect(TEMP dst, KILL cr);
10435 
10436   // return popc(~x & (x - 1));
10437   format %{ "SUB     $src,1,$dst\t! count trailing zeros (int)\n\t"
10438             "ANDN    $dst,$src,$dst\n\t"
10439             "SRL     $dst,R_G0,$dst\n\t"
10440             "POPC    $dst,$dst" %}
10441   ins_encode %{
10442     Register Rdst = $dst$$Register;
10443     Register Rsrc = $src$$Register;
10444     __ sub(Rsrc, 1, Rdst);
10445     __ andn(Rdst, Rsrc, Rdst);
10446     __ srl(Rdst, G0, Rdst);
10447     __ popc(Rdst, Rdst);
10448   %}
10449   ins_pipe(ialu_reg);
10450 %}
10451 
10452 instruct countTrailingZerosL(iRegIsafe dst, iRegL src, flagsReg cr) %{
10453   predicate(UsePopCountInstruction);  // See Matcher::match_rule_supported
10454   match(Set dst (CountTrailingZerosL src));
10455   effect(TEMP dst, KILL cr);
10456 
10457   // return popc(~x & (x - 1));
10458   format %{ "SUB     $src,1,$dst\t! count trailing zeros (long)\n\t"
10459             "ANDN    $dst,$src,$dst\n\t"
10460             "POPC    $dst,$dst" %}
10461   ins_encode %{
10462     Register Rdst = $dst$$Register;
10463     Register Rsrc = $src$$Register;
10464     __ sub(Rsrc, 1, Rdst);
10465     __ andn(Rdst, Rsrc, Rdst);
10466     __ popc(Rdst, Rdst);
10467   %}
10468   ins_pipe(ialu_reg);
10469 %}
10470 
10471 
10472 //---------- Population Count Instructions -------------------------------------
10473 
10474 instruct popCountI(iRegIsafe dst, iRegI src) %{
10475   predicate(UsePopCountInstruction);
10476   match(Set dst (PopCountI src));
10477 
10478   format %{ "SRL    $src, G0, $dst\t! clear upper word for 64 bit POPC\n\t"
10479             "POPC   $dst, $dst" %}
10480   ins_encode %{
10481     __ srl($src$$Register, G0, $dst$$Register);
10482     __ popc($dst$$Register, $dst$$Register);
10483   %}
10484   ins_pipe(ialu_reg);
10485 %}
10486 
10487 // Note: Long.bitCount(long) returns an int.
10488 instruct popCountL(iRegIsafe dst, iRegL src) %{
10489   predicate(UsePopCountInstruction);
10490   match(Set dst (PopCountL src));
10491 
10492   format %{ "POPC   $src, $dst" %}
10493   ins_encode %{
10494     __ popc($src$$Register, $dst$$Register);
10495   %}
10496   ins_pipe(ialu_reg);
10497 %}
10498 
10499 
10500 // ============================================================================
10501 //------------Bytes reverse--------------------------------------------------
10502 
10503 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{
10504   match(Set dst (ReverseBytesI src));
10505 
10506   // Op cost is artificially doubled to make sure that load or store
10507   // instructions are preferred over this one which requires a spill
10508   // onto a stack slot.
10509   ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10510   format %{ "LDUWA  $src, $dst\t!asi=primary_little" %}
10511 
10512   ins_encode %{
10513     __ set($src$$disp + STACK_BIAS, O7);
10514     __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10515   %}
10516   ins_pipe( iload_mem );
10517 %}
10518 
10519 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{
10520   match(Set dst (ReverseBytesL src));
10521 
10522   // Op cost is artificially doubled to make sure that load or store
10523   // instructions are preferred over this one which requires a spill
10524   // onto a stack slot.
10525   ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10526   format %{ "LDXA   $src, $dst\t!asi=primary_little" %}
10527 
10528   ins_encode %{
10529     __ set($src$$disp + STACK_BIAS, O7);
10530     __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10531   %}
10532   ins_pipe( iload_mem );
10533 %}
10534 
10535 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{
10536   match(Set dst (ReverseBytesUS src));
10537 
10538   // Op cost is artificially doubled to make sure that load or store
10539   // instructions are preferred over this one which requires a spill
10540   // onto a stack slot.
10541   ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10542   format %{ "LDUHA  $src, $dst\t!asi=primary_little\n\t" %}
10543 
10544   ins_encode %{
10545     // the value was spilled as an int so bias the load
10546     __ set($src$$disp + STACK_BIAS + 2, O7);
10547     __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10548   %}
10549   ins_pipe( iload_mem );
10550 %}
10551 
10552 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{
10553   match(Set dst (ReverseBytesS src));
10554 
10555   // Op cost is artificially doubled to make sure that load or store
10556   // instructions are preferred over this one which requires a spill
10557   // onto a stack slot.
10558   ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10559   format %{ "LDSHA  $src, $dst\t!asi=primary_little\n\t" %}
10560 
10561   ins_encode %{
10562     // the value was spilled as an int so bias the load
10563     __ set($src$$disp + STACK_BIAS + 2, O7);
10564     __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10565   %}
10566   ins_pipe( iload_mem );
10567 %}
10568 
10569 // Load Integer reversed byte order
10570 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{
10571   match(Set dst (ReverseBytesI (LoadI src)));
10572 
10573   ins_cost(DEFAULT_COST + MEMORY_REF_COST);
10574   size(4);
10575   format %{ "LDUWA  $src, $dst\t!asi=primary_little" %}
10576 
10577   ins_encode %{
10578     __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10579   %}
10580   ins_pipe(iload_mem);
10581 %}
10582 
10583 // Load Long - aligned and reversed
10584 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{
10585   match(Set dst (ReverseBytesL (LoadL src)));
10586 
10587   ins_cost(MEMORY_REF_COST);
10588   size(4);
10589   format %{ "LDXA   $src, $dst\t!asi=primary_little" %}
10590 
10591   ins_encode %{
10592     __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10593   %}
10594   ins_pipe(iload_mem);
10595 %}
10596 
10597 // Load unsigned short / char reversed byte order
10598 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{
10599   match(Set dst (ReverseBytesUS (LoadUS src)));
10600 
10601   ins_cost(MEMORY_REF_COST);
10602   size(4);
10603   format %{ "LDUHA  $src, $dst\t!asi=primary_little" %}
10604 
10605   ins_encode %{
10606     __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10607   %}
10608   ins_pipe(iload_mem);
10609 %}
10610 
10611 // Load short reversed byte order
10612 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{
10613   match(Set dst (ReverseBytesS (LoadS src)));
10614 
10615   ins_cost(MEMORY_REF_COST);
10616   size(4);
10617   format %{ "LDSHA  $src, $dst\t!asi=primary_little" %}
10618 
10619   ins_encode %{
10620     __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10621   %}
10622   ins_pipe(iload_mem);
10623 %}
10624 
10625 // Store Integer reversed byte order
10626 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{
10627   match(Set dst (StoreI dst (ReverseBytesI src)));
10628 
10629   ins_cost(MEMORY_REF_COST);
10630   size(4);
10631   format %{ "STWA   $src, $dst\t!asi=primary_little" %}
10632 
10633   ins_encode %{
10634     __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10635   %}
10636   ins_pipe(istore_mem_reg);
10637 %}
10638 
10639 // Store Long reversed byte order
10640 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{
10641   match(Set dst (StoreL dst (ReverseBytesL src)));
10642 
10643   ins_cost(MEMORY_REF_COST);
10644   size(4);
10645   format %{ "STXA   $src, $dst\t!asi=primary_little" %}
10646 
10647   ins_encode %{
10648     __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10649   %}
10650   ins_pipe(istore_mem_reg);
10651 %}
10652 
10653 // Store unsighed short/char reversed byte order
10654 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{
10655   match(Set dst (StoreC dst (ReverseBytesUS src)));
10656 
10657   ins_cost(MEMORY_REF_COST);
10658   size(4);
10659   format %{ "STHA   $src, $dst\t!asi=primary_little" %}
10660 
10661   ins_encode %{
10662     __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10663   %}
10664   ins_pipe(istore_mem_reg);
10665 %}
10666 
10667 // Store short reversed byte order
10668 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{
10669   match(Set dst (StoreC dst (ReverseBytesS src)));
10670 
10671   ins_cost(MEMORY_REF_COST);
10672   size(4);
10673   format %{ "STHA   $src, $dst\t!asi=primary_little" %}
10674 
10675   ins_encode %{
10676     __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10677   %}
10678   ins_pipe(istore_mem_reg);
10679 %}
10680 
10681 // ====================VECTOR INSTRUCTIONS=====================================
10682 
10683 // Load Aligned Packed values into a Double Register
10684 instruct loadV8(regD dst, memory mem) %{
10685   predicate(n->as_LoadVector()->memory_size() == 8);
10686   match(Set dst (LoadVector mem));
10687   ins_cost(MEMORY_REF_COST);
10688   size(4);
10689   format %{ "LDDF   $mem,$dst\t! load vector (8 bytes)" %}
10690   ins_encode %{
10691     __ ldf(FloatRegisterImpl::D, $mem$$Address, as_DoubleFloatRegister($dst$$reg));
10692   %}
10693   ins_pipe(floadD_mem);
10694 %}
10695 
10696 // Store Vector in Double register to memory
10697 instruct storeV8(memory mem, regD src) %{
10698   predicate(n->as_StoreVector()->memory_size() == 8);
10699   match(Set mem (StoreVector mem src));
10700   ins_cost(MEMORY_REF_COST);
10701   size(4);
10702   format %{ "STDF   $src,$mem\t! store vector (8 bytes)" %}
10703   ins_encode %{
10704     __ stf(FloatRegisterImpl::D, as_DoubleFloatRegister($src$$reg), $mem$$Address);
10705   %}
10706   ins_pipe(fstoreD_mem_reg);
10707 %}
10708 
10709 // Store Zero into vector in memory
10710 instruct storeV8B_zero(memory mem, immI0 zero) %{
10711   predicate(n->as_StoreVector()->memory_size() == 8);
10712   match(Set mem (StoreVector mem (ReplicateB zero)));
10713   ins_cost(MEMORY_REF_COST);
10714   size(4);
10715   format %{ "STX    $zero,$mem\t! store zero vector (8 bytes)" %}
10716   ins_encode %{
10717     __ stx(G0, $mem$$Address);
10718   %}
10719   ins_pipe(fstoreD_mem_zero);
10720 %}
10721 
10722 instruct storeV4S_zero(memory mem, immI0 zero) %{
10723   predicate(n->as_StoreVector()->memory_size() == 8);
10724   match(Set mem (StoreVector mem (ReplicateS zero)));
10725   ins_cost(MEMORY_REF_COST);
10726   size(4);
10727   format %{ "STX    $zero,$mem\t! store zero vector (4 shorts)" %}
10728   ins_encode %{
10729     __ stx(G0, $mem$$Address);
10730   %}
10731   ins_pipe(fstoreD_mem_zero);
10732 %}
10733 
10734 instruct storeV2I_zero(memory mem, immI0 zero) %{
10735   predicate(n->as_StoreVector()->memory_size() == 8);
10736   match(Set mem (StoreVector mem (ReplicateI zero)));
10737   ins_cost(MEMORY_REF_COST);
10738   size(4);
10739   format %{ "STX    $zero,$mem\t! store zero vector (2 ints)" %}
10740   ins_encode %{
10741     __ stx(G0, $mem$$Address);
10742   %}
10743   ins_pipe(fstoreD_mem_zero);
10744 %}
10745 
10746 instruct storeV2F_zero(memory mem, immF0 zero) %{
10747   predicate(n->as_StoreVector()->memory_size() == 8);
10748   match(Set mem (StoreVector mem (ReplicateF zero)));
10749   ins_cost(MEMORY_REF_COST);
10750   size(4);
10751   format %{ "STX    $zero,$mem\t! store zero vector (2 floats)" %}
10752   ins_encode %{
10753     __ stx(G0, $mem$$Address);
10754   %}
10755   ins_pipe(fstoreD_mem_zero);
10756 %}
10757 
10758 // Replicate scalar to packed byte values into Double register
10759 instruct Repl8B_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10760   predicate(n->as_Vector()->length() == 8 && UseVIS >= 3);
10761   match(Set dst (ReplicateB src));
10762   effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10763   format %{ "SLLX  $src,56,$tmp\n\t"
10764             "SRLX  $tmp, 8,$tmp2\n\t"
10765             "OR    $tmp,$tmp2,$tmp\n\t"
10766             "SRLX  $tmp,16,$tmp2\n\t"
10767             "OR    $tmp,$tmp2,$tmp\n\t"
10768             "SRLX  $tmp,32,$tmp2\n\t"
10769             "OR    $tmp,$tmp2,$tmp\t! replicate8B\n\t"
10770             "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10771   ins_encode %{
10772     Register Rsrc = $src$$Register;
10773     Register Rtmp = $tmp$$Register;
10774     Register Rtmp2 = $tmp2$$Register;
10775     __ sllx(Rsrc,    56, Rtmp);
10776     __ srlx(Rtmp,     8, Rtmp2);
10777     __ or3 (Rtmp, Rtmp2, Rtmp);
10778     __ srlx(Rtmp,    16, Rtmp2);
10779     __ or3 (Rtmp, Rtmp2, Rtmp);
10780     __ srlx(Rtmp,    32, Rtmp2);
10781     __ or3 (Rtmp, Rtmp2, Rtmp);
10782     __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10783   %}
10784   ins_pipe(ialu_reg);
10785 %}
10786 
10787 // Replicate scalar to packed byte values into Double stack
10788 instruct Repl8B_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10789   predicate(n->as_Vector()->length() == 8 && UseVIS < 3);
10790   match(Set dst (ReplicateB src));
10791   effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10792   format %{ "SLLX  $src,56,$tmp\n\t"
10793             "SRLX  $tmp, 8,$tmp2\n\t"
10794             "OR    $tmp,$tmp2,$tmp\n\t"
10795             "SRLX  $tmp,16,$tmp2\n\t"
10796             "OR    $tmp,$tmp2,$tmp\n\t"
10797             "SRLX  $tmp,32,$tmp2\n\t"
10798             "OR    $tmp,$tmp2,$tmp\t! replicate8B\n\t"
10799             "STX   $tmp,$dst\t! regL to stkD" %}
10800   ins_encode %{
10801     Register Rsrc = $src$$Register;
10802     Register Rtmp = $tmp$$Register;
10803     Register Rtmp2 = $tmp2$$Register;
10804     __ sllx(Rsrc,    56, Rtmp);
10805     __ srlx(Rtmp,     8, Rtmp2);
10806     __ or3 (Rtmp, Rtmp2, Rtmp);
10807     __ srlx(Rtmp,    16, Rtmp2);
10808     __ or3 (Rtmp, Rtmp2, Rtmp);
10809     __ srlx(Rtmp,    32, Rtmp2);
10810     __ or3 (Rtmp, Rtmp2, Rtmp);
10811     __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10812     __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10813   %}
10814   ins_pipe(ialu_reg);
10815 %}
10816 
10817 // Replicate scalar constant to packed byte values in Double register
10818 instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{
10819   predicate(n->as_Vector()->length() == 8);
10820   match(Set dst (ReplicateB con));
10821   effect(KILL tmp);
10822   format %{ "LDDF   [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %}
10823   ins_encode %{
10824     // XXX This is a quick fix for 6833573.
10825     //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister);
10826     RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register);
10827     __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10828   %}
10829   ins_pipe(loadConFD);
10830 %}
10831 
10832 // Replicate scalar to packed char/short values into Double register
10833 instruct Repl4S_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10834   predicate(n->as_Vector()->length() == 4 && UseVIS >= 3);
10835   match(Set dst (ReplicateS src));
10836   effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10837   format %{ "SLLX  $src,48,$tmp\n\t"
10838             "SRLX  $tmp,16,$tmp2\n\t"
10839             "OR    $tmp,$tmp2,$tmp\n\t"
10840             "SRLX  $tmp,32,$tmp2\n\t"
10841             "OR    $tmp,$tmp2,$tmp\t! replicate4S\n\t"
10842             "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10843   ins_encode %{
10844     Register Rsrc = $src$$Register;
10845     Register Rtmp = $tmp$$Register;
10846     Register Rtmp2 = $tmp2$$Register;
10847     __ sllx(Rsrc,    48, Rtmp);
10848     __ srlx(Rtmp,    16, Rtmp2);
10849     __ or3 (Rtmp, Rtmp2, Rtmp);
10850     __ srlx(Rtmp,    32, Rtmp2);
10851     __ or3 (Rtmp, Rtmp2, Rtmp);
10852     __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10853   %}
10854   ins_pipe(ialu_reg);
10855 %}
10856 
10857 // Replicate scalar to packed char/short values into Double stack
10858 instruct Repl4S_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10859   predicate(n->as_Vector()->length() == 4 && UseVIS < 3);
10860   match(Set dst (ReplicateS src));
10861   effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10862   format %{ "SLLX  $src,48,$tmp\n\t"
10863             "SRLX  $tmp,16,$tmp2\n\t"
10864             "OR    $tmp,$tmp2,$tmp\n\t"
10865             "SRLX  $tmp,32,$tmp2\n\t"
10866             "OR    $tmp,$tmp2,$tmp\t! replicate4S\n\t"
10867             "STX   $tmp,$dst\t! regL to stkD" %}
10868   ins_encode %{
10869     Register Rsrc = $src$$Register;
10870     Register Rtmp = $tmp$$Register;
10871     Register Rtmp2 = $tmp2$$Register;
10872     __ sllx(Rsrc,    48, Rtmp);
10873     __ srlx(Rtmp,    16, Rtmp2);
10874     __ or3 (Rtmp, Rtmp2, Rtmp);
10875     __ srlx(Rtmp,    32, Rtmp2);
10876     __ or3 (Rtmp, Rtmp2, Rtmp);
10877     __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10878     __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10879   %}
10880   ins_pipe(ialu_reg);
10881 %}
10882 
10883 // Replicate scalar constant to packed char/short values in Double register
10884 instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{
10885   predicate(n->as_Vector()->length() == 4);
10886   match(Set dst (ReplicateS con));
10887   effect(KILL tmp);
10888   format %{ "LDDF   [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %}
10889   ins_encode %{
10890     // XXX This is a quick fix for 6833573.
10891     //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister);
10892     RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register);
10893     __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10894   %}
10895   ins_pipe(loadConFD);
10896 %}
10897 
10898 // Replicate scalar to packed int values into Double register
10899 instruct Repl2I_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10900   predicate(n->as_Vector()->length() == 2 && UseVIS >= 3);
10901   match(Set dst (ReplicateI src));
10902   effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10903   format %{ "SLLX  $src,32,$tmp\n\t"
10904             "SRLX  $tmp,32,$tmp2\n\t"
10905             "OR    $tmp,$tmp2,$tmp\t! replicate2I\n\t"
10906             "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10907   ins_encode %{
10908     Register Rsrc = $src$$Register;
10909     Register Rtmp = $tmp$$Register;
10910     Register Rtmp2 = $tmp2$$Register;
10911     __ sllx(Rsrc,    32, Rtmp);
10912     __ srlx(Rtmp,    32, Rtmp2);
10913     __ or3 (Rtmp, Rtmp2, Rtmp);
10914     __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10915   %}
10916   ins_pipe(ialu_reg);
10917 %}
10918 
10919 // Replicate scalar to packed int values into Double stack
10920 instruct Repl2I_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10921   predicate(n->as_Vector()->length() == 2 && UseVIS < 3);
10922   match(Set dst (ReplicateI src));
10923   effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10924   format %{ "SLLX  $src,32,$tmp\n\t"
10925             "SRLX  $tmp,32,$tmp2\n\t"
10926             "OR    $tmp,$tmp2,$tmp\t! replicate2I\n\t"
10927             "STX   $tmp,$dst\t! regL to stkD" %}
10928   ins_encode %{
10929     Register Rsrc = $src$$Register;
10930     Register Rtmp = $tmp$$Register;
10931     Register Rtmp2 = $tmp2$$Register;
10932     __ sllx(Rsrc,    32, Rtmp);
10933     __ srlx(Rtmp,    32, Rtmp2);
10934     __ or3 (Rtmp, Rtmp2, Rtmp);
10935     __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10936     __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10937   %}
10938   ins_pipe(ialu_reg);
10939 %}
10940 
10941 // Replicate scalar zero constant to packed int values in Double register
10942 instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{
10943   predicate(n->as_Vector()->length() == 2);
10944   match(Set dst (ReplicateI con));
10945   effect(KILL tmp);
10946   format %{ "LDDF   [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %}
10947   ins_encode %{
10948     // XXX This is a quick fix for 6833573.
10949     //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister);
10950     RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register);
10951     __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10952   %}
10953   ins_pipe(loadConFD);
10954 %}
10955 
10956 // Replicate scalar to packed float values into Double stack
10957 instruct Repl2F_stk(stackSlotD dst, regF src) %{
10958   predicate(n->as_Vector()->length() == 2);
10959   match(Set dst (ReplicateF src));
10960   ins_cost(MEMORY_REF_COST*2);
10961   format %{ "STF    $src,$dst.hi\t! packed2F\n\t"
10962             "STF    $src,$dst.lo" %}
10963   opcode(Assembler::stf_op3);
10964   ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, src));
10965   ins_pipe(fstoreF_stk_reg);
10966 %}
10967 
10968 // Replicate scalar zero constant to packed float values in Double register
10969 instruct Repl2F_immF(regD dst, immF con, o7RegI tmp) %{
10970   predicate(n->as_Vector()->length() == 2);
10971   match(Set dst (ReplicateF con));
10972   effect(KILL tmp);
10973   format %{ "LDDF   [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2F($con)" %}
10974   ins_encode %{
10975     // XXX This is a quick fix for 6833573.
10976     //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immF($con$$constant)), $dst$$FloatRegister);
10977     RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immF($con$$constant)), $tmp$$Register);
10978     __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10979   %}
10980   ins_pipe(loadConFD);
10981 %}
10982 
10983 //----------PEEPHOLE RULES-----------------------------------------------------
10984 // These must follow all instruction definitions as they use the names
10985 // defined in the instructions definitions.
10986 //
10987 // peepmatch ( root_instr_name [preceding_instruction]* );
10988 //
10989 // peepconstraint %{
10990 // (instruction_number.operand_name relational_op instruction_number.operand_name
10991 //  [, ...] );
10992 // // instruction numbers are zero-based using left to right order in peepmatch
10993 //
10994 // peepreplace ( instr_name  ( [instruction_number.operand_name]* ) );
10995 // // provide an instruction_number.operand_name for each operand that appears
10996 // // in the replacement instruction's match rule
10997 //
10998 // ---------VM FLAGS---------------------------------------------------------
10999 //
11000 // All peephole optimizations can be turned off using -XX:-OptoPeephole
11001 //
11002 // Each peephole rule is given an identifying number starting with zero and
11003 // increasing by one in the order seen by the parser.  An individual peephole
11004 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
11005 // on the command-line.
11006 //
11007 // ---------CURRENT LIMITATIONS----------------------------------------------
11008 //
11009 // Only match adjacent instructions in same basic block
11010 // Only equality constraints
11011 // Only constraints between operands, not (0.dest_reg == EAX_enc)
11012 // Only one replacement instruction
11013 //
11014 // ---------EXAMPLE----------------------------------------------------------
11015 //
11016 // // pertinent parts of existing instructions in architecture description
11017 // instruct movI(eRegI dst, eRegI src) %{
11018 //   match(Set dst (CopyI src));
11019 // %}
11020 //
11021 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
11022 //   match(Set dst (AddI dst src));
11023 //   effect(KILL cr);
11024 // %}
11025 //
11026 // // Change (inc mov) to lea
11027 // peephole %{
11028 //   // increment preceeded by register-register move
11029 //   peepmatch ( incI_eReg movI );
11030 //   // require that the destination register of the increment
11031 //   // match the destination register of the move
11032 //   peepconstraint ( 0.dst == 1.dst );
11033 //   // construct a replacement instruction that sets
11034 //   // the destination to ( move's source register + one )
11035 //   peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) );
11036 // %}
11037 //
11038 
11039 // // Change load of spilled value to only a spill
11040 // instruct storeI(memory mem, eRegI src) %{
11041 //   match(Set mem (StoreI mem src));
11042 // %}
11043 //
11044 // instruct loadI(eRegI dst, memory mem) %{
11045 //   match(Set dst (LoadI mem));
11046 // %}
11047 //
11048 // peephole %{
11049 //   peepmatch ( loadI storeI );
11050 //   peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
11051 //   peepreplace ( storeI( 1.mem 1.mem 1.src ) );
11052 // %}
11053 
11054 //----------SMARTSPILL RULES---------------------------------------------------
11055 // These must follow all instruction definitions as they use the names
11056 // defined in the instructions definitions.
11057 //
11058 // SPARC will probably not have any of these rules due to RISC instruction set.
11059 
11060 //----------PIPELINE-----------------------------------------------------------
11061 // Rules which define the behavior of the target architectures pipeline.
--- EOF ---