1 //
2 // Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // X86 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // Previously set EBX, ESI, and EDI as save-on-entry for java code
64 // Turn off SOE in java-code due to frequent use of uncommon-traps.
65 // Now that allocator is better, turn on ESI and EDI as SOE registers.
66
67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code
72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg());
73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg());
75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg());
76
77 // Float registers. We treat TOS/FPR0 special. It is invisible to the
78 // allocator, and only shows up in the encodings.
79 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
80 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
81 // Ok so here's the trick FPR1 is really st(0) except in the midst
82 // of emission of assembly for a machnode. During the emission the fpu stack
83 // is pushed making FPR1 == st(1) temporarily. However at any safepoint
84 // the stack will not have this element so FPR1 == st(0) from the
85 // oopMap viewpoint. This same weirdness with numbering causes
86 // instruction encoding to have to play games with the register
87 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation
88 // where it does flt->flt moves to see an example
89 //
90 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg());
91 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next());
92 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg());
93 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next());
94 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg());
95 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next());
96 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg());
97 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next());
98 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg());
99 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next());
100 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg());
101 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next());
102 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg());
103 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next());
104
105 // Specify priority of register selection within phases of register
106 // allocation. Highest priority is first. A useful heuristic is to
107 // give registers a low priority when they are required by machine
108 // instructions, like EAX and EDX. Registers which are used as
109 // pairs must fall on an even boundary (witness the FPR#L's in this list).
110 // For the Intel integer registers, the equivalent Long pairs are
111 // EDX:EAX, EBX:ECX, and EDI:EBP.
112 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP,
113 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H,
114 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H,
115 FPR6L, FPR6H, FPR7L, FPR7H );
116
117
118 //----------Architecture Description Register Classes--------------------------
119 // Several register classes are automatically defined based upon information in
120 // this architecture description.
121 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
122 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
123 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
124 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
125 //
126 // Class for no registers (empty set).
127 reg_class no_reg();
128
129 // Class for all registers
130 reg_class any_reg_with_ebp(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP);
131 // Class for all registers (excluding EBP)
132 reg_class any_reg_no_ebp(EAX, EDX, EDI, ESI, ECX, EBX, ESP);
133 // Dynamic register class that selects at runtime between register classes
134 // any_reg and any_no_ebp_reg (depending on the value of the flag PreserveFramePointer).
135 // Equivalent to: return PreserveFramePointer ? any_no_ebp_reg : any_reg;
136 reg_class_dynamic any_reg(any_reg_no_ebp, any_reg_with_ebp, %{ PreserveFramePointer %});
137
138 // Class for general registers
139 reg_class int_reg_with_ebp(EAX, EDX, EBP, EDI, ESI, ECX, EBX);
140 // Class for general registers (excluding EBP).
141 // This register class can be used for implicit null checks on win95.
142 // It is also safe for use by tailjumps (we don't want to allocate in ebp).
143 // Used also if the PreserveFramePointer flag is true.
144 reg_class int_reg_no_ebp(EAX, EDX, EDI, ESI, ECX, EBX);
145 // Dynamic register class that selects between int_reg and int_reg_no_ebp.
146 reg_class_dynamic int_reg(int_reg_no_ebp, int_reg_with_ebp, %{ PreserveFramePointer %});
147
148 // Class of "X" registers
149 reg_class int_x_reg(EBX, ECX, EDX, EAX);
150
151 // Class of registers that can appear in an address with no offset.
152 // EBP and ESP require an extra instruction byte for zero offset.
153 // Used in fast-unlock
154 reg_class p_reg(EDX, EDI, ESI, EBX);
155
156 // Class for general registers excluding ECX
157 reg_class ncx_reg_with_ebp(EAX, EDX, EBP, EDI, ESI, EBX);
158 // Class for general registers excluding ECX (and EBP)
159 reg_class ncx_reg_no_ebp(EAX, EDX, EDI, ESI, EBX);
160 // Dynamic register class that selects between ncx_reg and ncx_reg_no_ebp.
161 reg_class_dynamic ncx_reg(ncx_reg_no_ebp, ncx_reg_with_ebp, %{ PreserveFramePointer %});
162
163 // Class for general registers excluding EAX
164 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX);
165
166 // Class for general registers excluding EAX and EBX.
167 reg_class nabx_reg_with_ebp(EDX, EDI, ESI, ECX, EBP);
168 // Class for general registers excluding EAX and EBX (and EBP)
169 reg_class nabx_reg_no_ebp(EDX, EDI, ESI, ECX);
170 // Dynamic register class that selects between nabx_reg and nabx_reg_no_ebp.
171 reg_class_dynamic nabx_reg(nabx_reg_no_ebp, nabx_reg_with_ebp, %{ PreserveFramePointer %});
172
173 // Class of EAX (for multiply and divide operations)
174 reg_class eax_reg(EAX);
175
176 // Class of EBX (for atomic add)
177 reg_class ebx_reg(EBX);
178
179 // Class of ECX (for shift and JCXZ operations and cmpLTMask)
180 reg_class ecx_reg(ECX);
181
182 // Class of EDX (for multiply and divide operations)
183 reg_class edx_reg(EDX);
184
185 // Class of EDI (for synchronization)
186 reg_class edi_reg(EDI);
187
188 // Class of ESI (for synchronization)
189 reg_class esi_reg(ESI);
190
191 // Singleton class for stack pointer
192 reg_class sp_reg(ESP);
193
194 // Singleton class for instruction pointer
195 // reg_class ip_reg(EIP);
196
197 // Class of integer register pairs
198 reg_class long_reg_with_ebp( EAX,EDX, ECX,EBX, EBP,EDI );
199 // Class of integer register pairs (excluding EBP and EDI);
200 reg_class long_reg_no_ebp( EAX,EDX, ECX,EBX );
201 // Dynamic register class that selects between long_reg and long_reg_no_ebp.
202 reg_class_dynamic long_reg(long_reg_no_ebp, long_reg_with_ebp, %{ PreserveFramePointer %});
203
204 // Class of integer register pairs that aligns with calling convention
205 reg_class eadx_reg( EAX,EDX );
206 reg_class ebcx_reg( ECX,EBX );
207
208 // Not AX or DX, used in divides
209 reg_class nadx_reg_with_ebp(EBX, ECX, ESI, EDI, EBP);
210 // Not AX or DX (and neither EBP), used in divides
211 reg_class nadx_reg_no_ebp(EBX, ECX, ESI, EDI);
212 // Dynamic register class that selects between nadx_reg and nadx_reg_no_ebp.
213 reg_class_dynamic nadx_reg(nadx_reg_no_ebp, nadx_reg_with_ebp, %{ PreserveFramePointer %});
214
215 // Floating point registers. Notice FPR0 is not a choice.
216 // FPR0 is not ever allocated; we use clever encodings to fake
217 // a 2-address instructions out of Intels FP stack.
218 reg_class fp_flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L );
219
220 reg_class fp_dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H,
221 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H,
222 FPR7L,FPR7H );
223
224 reg_class fp_flt_reg0( FPR1L );
225 reg_class fp_dbl_reg0( FPR1L,FPR1H );
226 reg_class fp_dbl_reg1( FPR2L,FPR2H );
227 reg_class fp_dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H,
228 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H );
229
230 %}
231
232
233 //----------SOURCE BLOCK-------------------------------------------------------
234 // This is a block of C++ code which provides values, functions, and
235 // definitions necessary in the rest of the architecture description
236 source_hpp %{
237 // Must be visible to the DFA in dfa_x86_32.cpp
238 extern bool is_operand_hi32_zero(Node* n);
239 %}
240
241 source %{
242 #define RELOC_IMM32 Assembler::imm_operand
243 #define RELOC_DISP32 Assembler::disp32_operand
244
245 #define __ _masm.
246
247 // How to find the high register of a Long pair, given the low register
248 #define HIGH_FROM_LOW(x) ((x)+2)
249
250 // These masks are used to provide 128-bit aligned bitmasks to the XMM
251 // instructions, to allow sign-masking or sign-bit flipping. They allow
252 // fast versions of NegF/NegD and AbsF/AbsD.
253
254 // Note: 'double' and 'long long' have 32-bits alignment on x86.
255 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
256 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
257 // of 128-bits operands for SSE instructions.
258 jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF)));
259 // Store the value to a 128-bits operand.
260 operand[0] = lo;
261 operand[1] = hi;
262 return operand;
263 }
264
265 // Buffer for 128-bits masks used by SSE instructions.
266 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
267
268 // Static initialization during VM startup.
269 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
270 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
271 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
272 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
273
274 // Offset hacking within calls.
275 static int pre_call_resets_size() {
276 int size = 0;
277 Compile* C = Compile::current();
278 if (C->in_24_bit_fp_mode()) {
279 size += 6; // fldcw
280 }
281 if (C->max_vector_size() > 16) {
282 size += 3; // vzeroupper
283 }
284 return size;
285 }
286
287 // !!!!! Special hack to get all type of calls to specify the byte offset
288 // from the start of the call to the point where the return address
289 // will point.
290 int MachCallStaticJavaNode::ret_addr_offset() {
291 return 5 + pre_call_resets_size(); // 5 bytes from start of call to where return address points
292 }
293
294 int MachCallDynamicJavaNode::ret_addr_offset() {
295 return 10 + pre_call_resets_size(); // 10 bytes from start of call to where return address points
296 }
297
298 static int sizeof_FFree_Float_Stack_All = -1;
299
300 int MachCallRuntimeNode::ret_addr_offset() {
301 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already");
302 return sizeof_FFree_Float_Stack_All + 5 + pre_call_resets_size();
303 }
304
305 // Indicate if the safepoint node needs the polling page as an input.
306 // Since x86 does have absolute addressing, it doesn't.
307 bool SafePointNode::needs_polling_address_input() {
308 return false;
309 }
310
311 //
312 // Compute padding required for nodes which need alignment
313 //
314
315 // The address of the call instruction needs to be 4-byte aligned to
316 // ensure that it does not span a cache line so that it can be patched.
317 int CallStaticJavaDirectNode::compute_padding(int current_offset) const {
318 current_offset += pre_call_resets_size(); // skip fldcw, if any
319 current_offset += 1; // skip call opcode byte
320 return round_to(current_offset, alignment_required()) - current_offset;
321 }
322
323 // The address of the call instruction needs to be 4-byte aligned to
324 // ensure that it does not span a cache line so that it can be patched.
325 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const {
326 current_offset += pre_call_resets_size(); // skip fldcw, if any
327 current_offset += 5; // skip MOV instruction
328 current_offset += 1; // skip call opcode byte
329 return round_to(current_offset, alignment_required()) - current_offset;
330 }
331
332 // EMIT_RM()
333 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
334 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3);
335 cbuf.insts()->emit_int8(c);
336 }
337
338 // EMIT_CC()
339 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
340 unsigned char c = (unsigned char)( f1 | f2 );
341 cbuf.insts()->emit_int8(c);
342 }
343
344 // EMIT_OPCODE()
345 void emit_opcode(CodeBuffer &cbuf, int code) {
346 cbuf.insts()->emit_int8((unsigned char) code);
347 }
348
349 // EMIT_OPCODE() w/ relocation information
350 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) {
351 cbuf.relocate(cbuf.insts_mark() + offset, reloc);
352 emit_opcode(cbuf, code);
353 }
354
355 // EMIT_D8()
356 void emit_d8(CodeBuffer &cbuf, int d8) {
357 cbuf.insts()->emit_int8((unsigned char) d8);
358 }
359
360 // EMIT_D16()
361 void emit_d16(CodeBuffer &cbuf, int d16) {
362 cbuf.insts()->emit_int16(d16);
363 }
364
365 // EMIT_D32()
366 void emit_d32(CodeBuffer &cbuf, int d32) {
367 cbuf.insts()->emit_int32(d32);
368 }
369
370 // emit 32 bit value and construct relocation entry from relocInfo::relocType
371 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc,
372 int format) {
373 cbuf.relocate(cbuf.insts_mark(), reloc, format);
374 cbuf.insts()->emit_int32(d32);
375 }
376
377 // emit 32 bit value and construct relocation entry from RelocationHolder
378 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec,
379 int format) {
380 #ifdef ASSERT
381 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) {
382 assert(cast_to_oop(d32)->is_oop() && (ScavengeRootsInCode || !cast_to_oop(d32)->is_scavengable()), "cannot embed scavengable oops in code");
383 }
384 #endif
385 cbuf.relocate(cbuf.insts_mark(), rspec, format);
386 cbuf.insts()->emit_int32(d32);
387 }
388
389 // Access stack slot for load or store
390 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) {
391 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src])
392 if( -128 <= disp && disp <= 127 ) {
393 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte
394 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
395 emit_d8 (cbuf, disp); // Displacement // R/M byte
396 } else {
397 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte
398 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
399 emit_d32(cbuf, disp); // Displacement // R/M byte
400 }
401 }
402
403 // rRegI ereg, memory mem) %{ // emit_reg_mem
404 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, relocInfo::relocType disp_reloc ) {
405 // There is no index & no scale, use form without SIB byte
406 if ((index == 0x4) &&
407 (scale == 0) && (base != ESP_enc)) {
408 // If no displacement, mode is 0x0; unless base is [EBP]
409 if ( (displace == 0) && (base != EBP_enc) ) {
410 emit_rm(cbuf, 0x0, reg_encoding, base);
411 }
412 else { // If 8-bit displacement, mode 0x1
413 if ((displace >= -128) && (displace <= 127)
414 && (disp_reloc == relocInfo::none) ) {
415 emit_rm(cbuf, 0x1, reg_encoding, base);
416 emit_d8(cbuf, displace);
417 }
418 else { // If 32-bit displacement
419 if (base == -1) { // Special flag for absolute address
420 emit_rm(cbuf, 0x0, reg_encoding, 0x5);
421 // (manual lies; no SIB needed here)
422 if ( disp_reloc != relocInfo::none ) {
423 emit_d32_reloc(cbuf, displace, disp_reloc, 1);
424 } else {
425 emit_d32 (cbuf, displace);
426 }
427 }
428 else { // Normal base + offset
429 emit_rm(cbuf, 0x2, reg_encoding, base);
430 if ( disp_reloc != relocInfo::none ) {
431 emit_d32_reloc(cbuf, displace, disp_reloc, 1);
432 } else {
433 emit_d32 (cbuf, displace);
434 }
435 }
436 }
437 }
438 }
439 else { // Else, encode with the SIB byte
440 // If no displacement, mode is 0x0; unless base is [EBP]
441 if (displace == 0 && (base != EBP_enc)) { // If no displacement
442 emit_rm(cbuf, 0x0, reg_encoding, 0x4);
443 emit_rm(cbuf, scale, index, base);
444 }
445 else { // If 8-bit displacement, mode 0x1
446 if ((displace >= -128) && (displace <= 127)
447 && (disp_reloc == relocInfo::none) ) {
448 emit_rm(cbuf, 0x1, reg_encoding, 0x4);
449 emit_rm(cbuf, scale, index, base);
450 emit_d8(cbuf, displace);
451 }
452 else { // If 32-bit displacement
453 if (base == 0x04 ) {
454 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
455 emit_rm(cbuf, scale, index, 0x04);
456 } else {
457 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
458 emit_rm(cbuf, scale, index, base);
459 }
460 if ( disp_reloc != relocInfo::none ) {
461 emit_d32_reloc(cbuf, displace, disp_reloc, 1);
462 } else {
463 emit_d32 (cbuf, displace);
464 }
465 }
466 }
467 }
468 }
469
470
471 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
472 if( dst_encoding == src_encoding ) {
473 // reg-reg copy, use an empty encoding
474 } else {
475 emit_opcode( cbuf, 0x8B );
476 emit_rm(cbuf, 0x3, dst_encoding, src_encoding );
477 }
478 }
479
480 void emit_cmpfp_fixup(MacroAssembler& _masm) {
481 Label exit;
482 __ jccb(Assembler::noParity, exit);
483 __ pushf();
484 //
485 // comiss/ucomiss instructions set ZF,PF,CF flags and
486 // zero OF,AF,SF for NaN values.
487 // Fixup flags by zeroing ZF,PF so that compare of NaN
488 // values returns 'less than' result (CF is set).
489 // Leave the rest of flags unchanged.
490 //
491 // 7 6 5 4 3 2 1 0
492 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
493 // 0 0 1 0 1 0 1 1 (0x2B)
494 //
495 __ andl(Address(rsp, 0), 0xffffff2b);
496 __ popf();
497 __ bind(exit);
498 }
499
500 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
501 Label done;
502 __ movl(dst, -1);
503 __ jcc(Assembler::parity, done);
504 __ jcc(Assembler::below, done);
505 __ setb(Assembler::notEqual, dst);
506 __ movzbl(dst, dst);
507 __ bind(done);
508 }
509
510
511 //=============================================================================
512 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
513
514 int Compile::ConstantTable::calculate_table_base_offset() const {
515 return 0; // absolute addressing, no offset
516 }
517
518 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
519 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
520 ShouldNotReachHere();
521 }
522
523 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
524 // Empty encoding
525 }
526
527 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
528 return 0;
529 }
530
531 #ifndef PRODUCT
532 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
533 st->print("# MachConstantBaseNode (empty encoding)");
534 }
535 #endif
536
537
538 //=============================================================================
539 #ifndef PRODUCT
540 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
541 Compile* C = ra_->C;
542
543 int framesize = C->frame_size_in_bytes();
544 int bangsize = C->bang_size_in_bytes();
545 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
546 // Remove wordSize for return addr which is already pushed.
547 framesize -= wordSize;
548
549 if (C->need_stack_bang(bangsize)) {
550 framesize -= wordSize;
551 st->print("# stack bang (%d bytes)", bangsize);
552 st->print("\n\t");
553 st->print("PUSH EBP\t# Save EBP");
554 if (PreserveFramePointer) {
555 st->print("\n\t");
556 st->print("MOV EBP, ESP\t# Save the caller's SP into EBP");
557 }
558 if (framesize) {
559 st->print("\n\t");
560 st->print("SUB ESP, #%d\t# Create frame",framesize);
561 }
562 } else {
563 st->print("SUB ESP, #%d\t# Create frame",framesize);
564 st->print("\n\t");
565 framesize -= wordSize;
566 st->print("MOV [ESP + #%d], EBP\t# Save EBP",framesize);
567 if (PreserveFramePointer) {
568 st->print("\n\t");
569 st->print("MOV EBP, ESP\t# Save the caller's SP into EBP");
570 if (framesize > 0) {
571 st->print("\n\t");
572 st->print("ADD EBP, #%d", framesize);
573 }
574 }
575 }
576
577 if (VerifyStackAtCalls) {
578 st->print("\n\t");
579 framesize -= wordSize;
580 st->print("MOV [ESP + #%d], 0xBADB100D\t# Majik cookie for stack depth check",framesize);
581 }
582
583 if( C->in_24_bit_fp_mode() ) {
584 st->print("\n\t");
585 st->print("FLDCW \t# load 24 bit fpu control word");
586 }
587 if (UseSSE >= 2 && VerifyFPU) {
588 st->print("\n\t");
589 st->print("# verify FPU stack (must be clean on entry)");
590 }
591
592 #ifdef ASSERT
593 if (VerifyStackAtCalls) {
594 st->print("\n\t");
595 st->print("# stack alignment check");
596 }
597 #endif
598 st->cr();
599 }
600 #endif
601
602
603 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
604 Compile* C = ra_->C;
605 MacroAssembler _masm(&cbuf);
606
607 int framesize = C->frame_size_in_bytes();
608 int bangsize = C->bang_size_in_bytes();
609
610 __ verified_entry(framesize, C->need_stack_bang(bangsize)?bangsize:0, C->in_24_bit_fp_mode());
611
612 C->set_frame_complete(cbuf.insts_size());
613
614 if (C->has_mach_constant_base_node()) {
615 // NOTE: We set the table base offset here because users might be
616 // emitted before MachConstantBaseNode.
617 Compile::ConstantTable& constant_table = C->constant_table();
618 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
619 }
620 }
621
622 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
623 return MachNode::size(ra_); // too many variables; just compute it the hard way
624 }
625
626 int MachPrologNode::reloc() const {
627 return 0; // a large enough number
628 }
629
630 //=============================================================================
631 #ifndef PRODUCT
632 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
633 Compile *C = ra_->C;
634 int framesize = C->frame_size_in_bytes();
635 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
636 // Remove two words for return addr and rbp,
637 framesize -= 2*wordSize;
638
639 if (C->max_vector_size() > 16) {
640 st->print("VZEROUPPER");
641 st->cr(); st->print("\t");
642 }
643 if (C->in_24_bit_fp_mode()) {
644 st->print("FLDCW standard control word");
645 st->cr(); st->print("\t");
646 }
647 if (framesize) {
648 st->print("ADD ESP,%d\t# Destroy frame",framesize);
649 st->cr(); st->print("\t");
650 }
651 st->print_cr("POPL EBP"); st->print("\t");
652 if (do_polling() && C->is_method_compilation()) {
653 st->print("TEST PollPage,EAX\t! Poll Safepoint");
654 st->cr(); st->print("\t");
655 }
656 }
657 #endif
658
659 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
660 Compile *C = ra_->C;
661
662 if (C->max_vector_size() > 16) {
663 // Clear upper bits of YMM registers when current compiled code uses
664 // wide vectors to avoid AVX <-> SSE transition penalty during call.
665 MacroAssembler masm(&cbuf);
666 masm.vzeroupper();
667 }
668 // If method set FPU control word, restore to standard control word
669 if (C->in_24_bit_fp_mode()) {
670 MacroAssembler masm(&cbuf);
671 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
672 }
673
674 int framesize = C->frame_size_in_bytes();
675 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
676 // Remove two words for return addr and rbp,
677 framesize -= 2*wordSize;
678
679 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
680
681 if (framesize >= 128) {
682 emit_opcode(cbuf, 0x81); // add SP, #framesize
683 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
684 emit_d32(cbuf, framesize);
685 } else if (framesize) {
686 emit_opcode(cbuf, 0x83); // add SP, #framesize
687 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
688 emit_d8(cbuf, framesize);
689 }
690
691 emit_opcode(cbuf, 0x58 | EBP_enc);
692
693 if (do_polling() && C->is_method_compilation()) {
694 cbuf.relocate(cbuf.insts_end(), relocInfo::poll_return_type, 0);
695 emit_opcode(cbuf,0x85);
696 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX
697 emit_d32(cbuf, (intptr_t)os::get_polling_page());
698 }
699 }
700
701 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
702 Compile *C = ra_->C;
703 // If method set FPU control word, restore to standard control word
704 int size = C->in_24_bit_fp_mode() ? 6 : 0;
705 if (C->max_vector_size() > 16) size += 3; // vzeroupper
706 if (do_polling() && C->is_method_compilation()) size += 6;
707
708 int framesize = C->frame_size_in_bytes();
709 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
710 // Remove two words for return addr and rbp,
711 framesize -= 2*wordSize;
712
713 size++; // popl rbp,
714
715 if (framesize >= 128) {
716 size += 6;
717 } else {
718 size += framesize ? 3 : 0;
719 }
720 return size;
721 }
722
723 int MachEpilogNode::reloc() const {
724 return 0; // a large enough number
725 }
726
727 const Pipeline * MachEpilogNode::pipeline() const {
728 return MachNode::pipeline_class();
729 }
730
731 int MachEpilogNode::safepoint_offset() const { return 0; }
732
733 //=============================================================================
734
735 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack };
736 static enum RC rc_class( OptoReg::Name reg ) {
737
738 if( !OptoReg::is_valid(reg) ) return rc_bad;
739 if (OptoReg::is_stack(reg)) return rc_stack;
740
741 VMReg r = OptoReg::as_VMReg(reg);
742 if (r->is_Register()) return rc_int;
743 if (r->is_FloatRegister()) {
744 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode");
745 return rc_float;
746 }
747 assert(r->is_XMMRegister(), "must be");
748 return rc_xmm;
749 }
750
751 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg,
752 int opcode, const char *op_str, int size, outputStream* st ) {
753 if( cbuf ) {
754 emit_opcode (*cbuf, opcode );
755 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, relocInfo::none);
756 #ifndef PRODUCT
757 } else if( !do_size ) {
758 if( size != 0 ) st->print("\n\t");
759 if( opcode == 0x8B || opcode == 0x89 ) { // MOV
760 if( is_load ) st->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset);
761 else st->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]);
762 } else { // FLD, FST, PUSH, POP
763 st->print("%s [ESP + #%d]",op_str,offset);
764 }
765 #endif
766 }
767 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
768 return size+3+offset_size;
769 }
770
771 // Helper for XMM registers. Extra opcode bits, limited syntax.
772 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load,
773 int offset, int reg_lo, int reg_hi, int size, outputStream* st ) {
774 if (cbuf) {
775 MacroAssembler _masm(cbuf);
776 if (reg_lo+1 == reg_hi) { // double move?
777 if (is_load) {
778 __ movdbl(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
779 } else {
780 __ movdbl(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
781 }
782 } else {
783 if (is_load) {
784 __ movflt(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
785 } else {
786 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
787 }
788 }
789 #ifndef PRODUCT
790 } else if (!do_size) {
791 if (size != 0) st->print("\n\t");
792 if (reg_lo+1 == reg_hi) { // double move?
793 if (is_load) st->print("%s %s,[ESP + #%d]",
794 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD",
795 Matcher::regName[reg_lo], offset);
796 else st->print("MOVSD [ESP + #%d],%s",
797 offset, Matcher::regName[reg_lo]);
798 } else {
799 if (is_load) st->print("MOVSS %s,[ESP + #%d]",
800 Matcher::regName[reg_lo], offset);
801 else st->print("MOVSS [ESP + #%d],%s",
802 offset, Matcher::regName[reg_lo]);
803 }
804 #endif
805 }
806 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
807 // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes as SIMD prefix.
808 return size+5+offset_size;
809 }
810
811
812 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
813 int src_hi, int dst_hi, int size, outputStream* st ) {
814 if (cbuf) {
815 MacroAssembler _masm(cbuf);
816 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
817 __ movdbl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
818 as_XMMRegister(Matcher::_regEncode[src_lo]));
819 } else {
820 __ movflt(as_XMMRegister(Matcher::_regEncode[dst_lo]),
821 as_XMMRegister(Matcher::_regEncode[src_lo]));
822 }
823 #ifndef PRODUCT
824 } else if (!do_size) {
825 if (size != 0) st->print("\n\t");
826 if (UseXmmRegToRegMoveAll) {//Use movaps,movapd to move between xmm registers
827 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
828 st->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
829 } else {
830 st->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
831 }
832 } else {
833 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
834 st->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
835 } else {
836 st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
837 }
838 }
839 #endif
840 }
841 // VEX_2bytes prefix is used if UseAVX > 0, and it takes the same 2 bytes as SIMD prefix.
842 // Only MOVAPS SSE prefix uses 1 byte.
843 int sz = 4;
844 if (!(src_lo+1 == src_hi && dst_lo+1 == dst_hi) &&
845 UseXmmRegToRegMoveAll && (UseAVX == 0)) sz = 3;
846 return size + sz;
847 }
848
849 static int impl_movgpr2x_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
850 int src_hi, int dst_hi, int size, outputStream* st ) {
851 // 32-bit
852 if (cbuf) {
853 MacroAssembler _masm(cbuf);
854 __ movdl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
855 as_Register(Matcher::_regEncode[src_lo]));
856 #ifndef PRODUCT
857 } else if (!do_size) {
858 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
859 #endif
860 }
861 return 4;
862 }
863
864
865 static int impl_movx2gpr_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
866 int src_hi, int dst_hi, int size, outputStream* st ) {
867 // 32-bit
868 if (cbuf) {
869 MacroAssembler _masm(cbuf);
870 __ movdl(as_Register(Matcher::_regEncode[dst_lo]),
871 as_XMMRegister(Matcher::_regEncode[src_lo]));
872 #ifndef PRODUCT
873 } else if (!do_size) {
874 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
875 #endif
876 }
877 return 4;
878 }
879
880 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size, outputStream* st ) {
881 if( cbuf ) {
882 emit_opcode(*cbuf, 0x8B );
883 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] );
884 #ifndef PRODUCT
885 } else if( !do_size ) {
886 if( size != 0 ) st->print("\n\t");
887 st->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]);
888 #endif
889 }
890 return size+2;
891 }
892
893 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi,
894 int offset, int size, outputStream* st ) {
895 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there
896 if( cbuf ) {
897 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it)
898 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] );
899 #ifndef PRODUCT
900 } else if( !do_size ) {
901 if( size != 0 ) st->print("\n\t");
902 st->print("FLD %s",Matcher::regName[src_lo]);
903 #endif
904 }
905 size += 2;
906 }
907
908 int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/;
909 const char *op_str;
910 int op;
911 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store?
912 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D ";
913 op = 0xDD;
914 } else { // 32-bit store
915 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S ";
916 op = 0xD9;
917 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" );
918 }
919
920 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st);
921 }
922
923 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
924 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
925 int src_hi, int dst_hi, uint ireg, outputStream* st);
926
927 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
928 int stack_offset, int reg, uint ireg, outputStream* st);
929
930 static int vec_stack_to_stack_helper(CodeBuffer *cbuf, bool do_size, int src_offset,
931 int dst_offset, uint ireg, outputStream* st) {
932 int calc_size = 0;
933 int src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4);
934 int dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4);
935 switch (ireg) {
936 case Op_VecS:
937 calc_size = 3+src_offset_size + 3+dst_offset_size;
938 break;
939 case Op_VecD:
940 calc_size = 3+src_offset_size + 3+dst_offset_size;
941 src_offset += 4;
942 dst_offset += 4;
943 src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4);
944 dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4);
945 calc_size += 3+src_offset_size + 3+dst_offset_size;
946 break;
947 case Op_VecX:
948 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size;
949 break;
950 case Op_VecY:
951 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size;
952 break;
953 default:
954 ShouldNotReachHere();
955 }
956 if (cbuf) {
957 MacroAssembler _masm(cbuf);
958 int offset = __ offset();
959 switch (ireg) {
960 case Op_VecS:
961 __ pushl(Address(rsp, src_offset));
962 __ popl (Address(rsp, dst_offset));
963 break;
964 case Op_VecD:
965 __ pushl(Address(rsp, src_offset));
966 __ popl (Address(rsp, dst_offset));
967 __ pushl(Address(rsp, src_offset+4));
968 __ popl (Address(rsp, dst_offset+4));
969 break;
970 case Op_VecX:
971 __ movdqu(Address(rsp, -16), xmm0);
972 __ movdqu(xmm0, Address(rsp, src_offset));
973 __ movdqu(Address(rsp, dst_offset), xmm0);
974 __ movdqu(xmm0, Address(rsp, -16));
975 break;
976 case Op_VecY:
977 __ vmovdqu(Address(rsp, -32), xmm0);
978 __ vmovdqu(xmm0, Address(rsp, src_offset));
979 __ vmovdqu(Address(rsp, dst_offset), xmm0);
980 __ vmovdqu(xmm0, Address(rsp, -32));
981 break;
982 default:
983 ShouldNotReachHere();
984 }
985 int size = __ offset() - offset;
986 assert(size == calc_size, "incorrect size calculattion");
987 return size;
988 #ifndef PRODUCT
989 } else if (!do_size) {
990 switch (ireg) {
991 case Op_VecS:
992 st->print("pushl [rsp + #%d]\t# 32-bit mem-mem spill\n\t"
993 "popl [rsp + #%d]",
994 src_offset, dst_offset);
995 break;
996 case Op_VecD:
997 st->print("pushl [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
998 "popq [rsp + #%d]\n\t"
999 "pushl [rsp + #%d]\n\t"
1000 "popq [rsp + #%d]",
1001 src_offset, dst_offset, src_offset+4, dst_offset+4);
1002 break;
1003 case Op_VecX:
1004 st->print("movdqu [rsp - #16], xmm0\t# 128-bit mem-mem spill\n\t"
1005 "movdqu xmm0, [rsp + #%d]\n\t"
1006 "movdqu [rsp + #%d], xmm0\n\t"
1007 "movdqu xmm0, [rsp - #16]",
1008 src_offset, dst_offset);
1009 break;
1010 case Op_VecY:
1011 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
1012 "vmovdqu xmm0, [rsp + #%d]\n\t"
1013 "vmovdqu [rsp + #%d], xmm0\n\t"
1014 "vmovdqu xmm0, [rsp - #32]",
1015 src_offset, dst_offset);
1016 break;
1017 default:
1018 ShouldNotReachHere();
1019 }
1020 #endif
1021 }
1022 return calc_size;
1023 }
1024
1025 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const {
1026 // Get registers to move
1027 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1028 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1029 OptoReg::Name dst_second = ra_->get_reg_second(this );
1030 OptoReg::Name dst_first = ra_->get_reg_first(this );
1031
1032 enum RC src_second_rc = rc_class(src_second);
1033 enum RC src_first_rc = rc_class(src_first);
1034 enum RC dst_second_rc = rc_class(dst_second);
1035 enum RC dst_first_rc = rc_class(dst_first);
1036
1037 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
1038
1039 // Generate spill code!
1040 int size = 0;
1041
1042 if( src_first == dst_first && src_second == dst_second )
1043 return size; // Self copy, no move
1044
1045 if (bottom_type()->isa_vect() != NULL) {
1046 uint ireg = ideal_reg();
1047 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
1048 assert((src_first_rc != rc_float && dst_first_rc != rc_float), "sanity");
1049 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY), "sanity");
1050 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1051 // mem -> mem
1052 int src_offset = ra_->reg2offset(src_first);
1053 int dst_offset = ra_->reg2offset(dst_first);
1054 return vec_stack_to_stack_helper(cbuf, do_size, src_offset, dst_offset, ireg, st);
1055 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
1056 return vec_mov_helper(cbuf, do_size, src_first, dst_first, src_second, dst_second, ireg, st);
1057 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
1058 int stack_offset = ra_->reg2offset(dst_first);
1059 return vec_spill_helper(cbuf, do_size, false, stack_offset, src_first, ireg, st);
1060 } else if (src_first_rc == rc_stack && dst_first_rc == rc_xmm ) {
1061 int stack_offset = ra_->reg2offset(src_first);
1062 return vec_spill_helper(cbuf, do_size, true, stack_offset, dst_first, ireg, st);
1063 } else {
1064 ShouldNotReachHere();
1065 }
1066 }
1067
1068 // --------------------------------------
1069 // Check for mem-mem move. push/pop to move.
1070 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1071 if( src_second == dst_first ) { // overlapping stack copy ranges
1072 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" );
1073 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
1074 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
1075 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits
1076 }
1077 // move low bits
1078 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size, st);
1079 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size, st);
1080 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits
1081 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
1082 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
1083 }
1084 return size;
1085 }
1086
1087 // --------------------------------------
1088 // Check for integer reg-reg copy
1089 if( src_first_rc == rc_int && dst_first_rc == rc_int )
1090 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size, st);
1091
1092 // Check for integer store
1093 if( src_first_rc == rc_int && dst_first_rc == rc_stack )
1094 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size, st);
1095
1096 // Check for integer load
1097 if( dst_first_rc == rc_int && src_first_rc == rc_stack )
1098 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size, st);
1099
1100 // Check for integer reg-xmm reg copy
1101 if( src_first_rc == rc_int && dst_first_rc == rc_xmm ) {
1102 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
1103 "no 64 bit integer-float reg moves" );
1104 return impl_movgpr2x_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1105 }
1106 // --------------------------------------
1107 // Check for float reg-reg copy
1108 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1109 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1110 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" );
1111 if( cbuf ) {
1112
1113 // Note the mucking with the register encode to compensate for the 0/1
1114 // indexing issue mentioned in a comment in the reg_def sections
1115 // for FPR registers many lines above here.
1116
1117 if( src_first != FPR1L_num ) {
1118 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i)
1119 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 );
1120 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
1121 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1122 } else {
1123 emit_opcode (*cbuf, 0xDD ); // FST ST(i)
1124 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 );
1125 }
1126 #ifndef PRODUCT
1127 } else if( !do_size ) {
1128 if( size != 0 ) st->print("\n\t");
1129 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]);
1130 else st->print( "FST %s", Matcher::regName[dst_first]);
1131 #endif
1132 }
1133 return size + ((src_first != FPR1L_num) ? 2+2 : 2);
1134 }
1135
1136 // Check for float store
1137 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1138 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size, st);
1139 }
1140
1141 // Check for float load
1142 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1143 int offset = ra_->reg2offset(src_first);
1144 const char *op_str;
1145 int op;
1146 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load?
1147 op_str = "FLD_D";
1148 op = 0xDD;
1149 } else { // 32-bit load
1150 op_str = "FLD_S";
1151 op = 0xD9;
1152 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" );
1153 }
1154 if( cbuf ) {
1155 emit_opcode (*cbuf, op );
1156 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, relocInfo::none);
1157 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
1158 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1159 #ifndef PRODUCT
1160 } else if( !do_size ) {
1161 if( size != 0 ) st->print("\n\t");
1162 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]);
1163 #endif
1164 }
1165 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
1166 return size + 3+offset_size+2;
1167 }
1168
1169 // Check for xmm reg-reg copy
1170 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
1171 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1172 (src_first+1 == src_second && dst_first+1 == dst_second),
1173 "no non-adjacent float-moves" );
1174 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1175 }
1176
1177 // Check for xmm reg-integer reg copy
1178 if( src_first_rc == rc_xmm && dst_first_rc == rc_int ) {
1179 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
1180 "no 64 bit float-integer reg moves" );
1181 return impl_movx2gpr_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1182 }
1183
1184 // Check for xmm store
1185 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
1186 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size, st);
1187 }
1188
1189 // Check for float xmm load
1190 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) {
1191 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size, st);
1192 }
1193
1194 // Copy from float reg to xmm reg
1195 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) {
1196 // copy to the top of stack from floating point reg
1197 // and use LEA to preserve flags
1198 if( cbuf ) {
1199 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8]
1200 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1201 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1202 emit_d8(*cbuf,0xF8);
1203 #ifndef PRODUCT
1204 } else if( !do_size ) {
1205 if( size != 0 ) st->print("\n\t");
1206 st->print("LEA ESP,[ESP-8]");
1207 #endif
1208 }
1209 size += 4;
1210
1211 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size, st);
1212
1213 // Copy from the temp memory to the xmm reg.
1214 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size, st);
1215
1216 if( cbuf ) {
1217 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8]
1218 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1219 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1220 emit_d8(*cbuf,0x08);
1221 #ifndef PRODUCT
1222 } else if( !do_size ) {
1223 if( size != 0 ) st->print("\n\t");
1224 st->print("LEA ESP,[ESP+8]");
1225 #endif
1226 }
1227 size += 4;
1228 return size;
1229 }
1230
1231 assert( size > 0, "missed a case" );
1232
1233 // --------------------------------------------------------------------
1234 // Check for second bits still needing moving.
1235 if( src_second == dst_second )
1236 return size; // Self copy; no move
1237 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1238
1239 // Check for second word int-int move
1240 if( src_second_rc == rc_int && dst_second_rc == rc_int )
1241 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size, st);
1242
1243 // Check for second word integer store
1244 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1245 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size, st);
1246
1247 // Check for second word integer load
1248 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1249 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size, st);
1250
1251
1252 Unimplemented();
1253 }
1254
1255 #ifndef PRODUCT
1256 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1257 implementation( NULL, ra_, false, st );
1258 }
1259 #endif
1260
1261 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1262 implementation( &cbuf, ra_, false, NULL );
1263 }
1264
1265 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1266 return implementation( NULL, ra_, true, NULL );
1267 }
1268
1269
1270 //=============================================================================
1271 #ifndef PRODUCT
1272 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1273 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1274 int reg = ra_->get_reg_first(this);
1275 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset);
1276 }
1277 #endif
1278
1279 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1280 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1281 int reg = ra_->get_encode(this);
1282 if( offset >= 128 ) {
1283 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1284 emit_rm(cbuf, 0x2, reg, 0x04);
1285 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1286 emit_d32(cbuf, offset);
1287 }
1288 else {
1289 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1290 emit_rm(cbuf, 0x1, reg, 0x04);
1291 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1292 emit_d8(cbuf, offset);
1293 }
1294 }
1295
1296 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1297 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1298 if( offset >= 128 ) {
1299 return 7;
1300 }
1301 else {
1302 return 4;
1303 }
1304 }
1305
1306 //=============================================================================
1307 #ifndef PRODUCT
1308 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1309 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check");
1310 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub");
1311 st->print_cr("\tNOP");
1312 st->print_cr("\tNOP");
1313 if( !OptoBreakpoint )
1314 st->print_cr("\tNOP");
1315 }
1316 #endif
1317
1318 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1319 MacroAssembler masm(&cbuf);
1320 #ifdef ASSERT
1321 uint insts_size = cbuf.insts_size();
1322 #endif
1323 masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes()));
1324 masm.jump_cc(Assembler::notEqual,
1325 RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1326 /* WARNING these NOPs are critical so that verified entry point is properly
1327 aligned for patching by NativeJump::patch_verified_entry() */
1328 int nops_cnt = 2;
1329 if( !OptoBreakpoint ) // Leave space for int3
1330 nops_cnt += 1;
1331 masm.nop(nops_cnt);
1332
1333 assert(cbuf.insts_size() - insts_size == size(ra_), "checking code size of inline cache node");
1334 }
1335
1336 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1337 return OptoBreakpoint ? 11 : 12;
1338 }
1339
1340
1341 //=============================================================================
1342
1343 int Matcher::regnum_to_fpu_offset(int regnum) {
1344 return regnum - 32; // The FP registers are in the second chunk
1345 }
1346
1347 // This is UltraSparc specific, true just means we have fast l2f conversion
1348 const bool Matcher::convL2FSupported(void) {
1349 return true;
1350 }
1351
1352 // Is this branch offset short enough that a short branch can be used?
1353 //
1354 // NOTE: If the platform does not provide any short branch variants, then
1355 // this method should return false for offset 0.
1356 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1357 // The passed offset is relative to address of the branch.
1358 // On 86 a branch displacement is calculated relative to address
1359 // of a next instruction.
1360 offset -= br_size;
1361
1362 // the short version of jmpConUCF2 contains multiple branches,
1363 // making the reach slightly less
1364 if (rule == jmpConUCF2_rule)
1365 return (-126 <= offset && offset <= 125);
1366 return (-128 <= offset && offset <= 127);
1367 }
1368
1369 const bool Matcher::isSimpleConstant64(jlong value) {
1370 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1371 return false;
1372 }
1373
1374 // The ecx parameter to rep stos for the ClearArray node is in dwords.
1375 const bool Matcher::init_array_count_is_in_bytes = false;
1376
1377 // Threshold size for cleararray.
1378 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1379
1380 // Needs 2 CMOV's for longs.
1381 const int Matcher::long_cmove_cost() { return 1; }
1382
1383 // No CMOVF/CMOVD with SSE/SSE2
1384 const int Matcher::float_cmove_cost() { return (UseSSE>=1) ? ConditionalMoveLimit : 0; }
1385
1386 // Does the CPU require late expand (see block.cpp for description of late expand)?
1387 const bool Matcher::require_postalloc_expand = false;
1388
1389 // Should the Matcher clone shifts on addressing modes, expecting them to
1390 // be subsumed into complex addressing expressions or compute them into
1391 // registers? True for Intel but false for most RISCs
1392 const bool Matcher::clone_shift_expressions = true;
1393
1394 // Do we need to mask the count passed to shift instructions or does
1395 // the cpu only look at the lower 5/6 bits anyway?
1396 const bool Matcher::need_masked_shift_count = false;
1397
1398 bool Matcher::narrow_oop_use_complex_address() {
1399 ShouldNotCallThis();
1400 return true;
1401 }
1402
1403 bool Matcher::narrow_klass_use_complex_address() {
1404 ShouldNotCallThis();
1405 return true;
1406 }
1407
1408
1409 // Is it better to copy float constants, or load them directly from memory?
1410 // Intel can load a float constant from a direct address, requiring no
1411 // extra registers. Most RISCs will have to materialize an address into a
1412 // register first, so they would do better to copy the constant from stack.
1413 const bool Matcher::rematerialize_float_constants = true;
1414
1415 // If CPU can load and store mis-aligned doubles directly then no fixup is
1416 // needed. Else we split the double into 2 integer pieces and move it
1417 // piece-by-piece. Only happens when passing doubles into C code as the
1418 // Java calling convention forces doubles to be aligned.
1419 const bool Matcher::misaligned_doubles_ok = true;
1420
1421
1422 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1423 // Get the memory operand from the node
1424 uint numopnds = node->num_opnds(); // Virtual call for number of operands
1425 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far
1426 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" );
1427 uint opcnt = 1; // First operand
1428 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand
1429 while( idx >= skipped+num_edges ) {
1430 skipped += num_edges;
1431 opcnt++; // Bump operand count
1432 assert( opcnt < numopnds, "Accessing non-existent operand" );
1433 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand
1434 }
1435
1436 MachOper *memory = node->_opnds[opcnt];
1437 MachOper *new_memory = NULL;
1438 switch (memory->opcode()) {
1439 case DIRECT:
1440 case INDOFFSET32X:
1441 // No transformation necessary.
1442 return;
1443 case INDIRECT:
1444 new_memory = new (C) indirect_win95_safeOper( );
1445 break;
1446 case INDOFFSET8:
1447 new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0));
1448 break;
1449 case INDOFFSET32:
1450 new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0));
1451 break;
1452 case INDINDEXOFFSET:
1453 new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0));
1454 break;
1455 case INDINDEXSCALE:
1456 new_memory = new (C) indIndexScale_win95_safeOper(memory->scale());
1457 break;
1458 case INDINDEXSCALEOFFSET:
1459 new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0));
1460 break;
1461 case LOAD_LONG_INDIRECT:
1462 case LOAD_LONG_INDOFFSET32:
1463 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI}
1464 return;
1465 default:
1466 assert(false, "unexpected memory operand in pd_implicit_null_fixup()");
1467 return;
1468 }
1469 node->_opnds[opcnt] = new_memory;
1470 }
1471
1472 // Advertise here if the CPU requires explicit rounding operations
1473 // to implement the UseStrictFP mode.
1474 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1475
1476 // Are floats conerted to double when stored to stack during deoptimization?
1477 // On x32 it is stored with convertion only when FPU is used for floats.
1478 bool Matcher::float_in_double() { return (UseSSE == 0); }
1479
1480 // Do ints take an entire long register or just half?
1481 const bool Matcher::int_in_long = false;
1482
1483 // Return whether or not this register is ever used as an argument. This
1484 // function is used on startup to build the trampoline stubs in generateOptoStub.
1485 // Registers not mentioned will be killed by the VM call in the trampoline, and
1486 // arguments in those registers not be available to the callee.
1487 bool Matcher::can_be_java_arg( int reg ) {
1488 if( reg == ECX_num || reg == EDX_num ) return true;
1489 if( (reg == XMM0_num || reg == XMM1_num ) && UseSSE>=1 ) return true;
1490 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true;
1491 return false;
1492 }
1493
1494 bool Matcher::is_spillable_arg( int reg ) {
1495 return can_be_java_arg(reg);
1496 }
1497
1498 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1499 // Use hardware integer DIV instruction when
1500 // it is faster than a code which use multiply.
1501 // Only when constant divisor fits into 32 bit
1502 // (min_jint is excluded to get only correct
1503 // positive 32 bit values from negative).
1504 return VM_Version::has_fast_idiv() &&
1505 (divisor == (int)divisor && divisor != min_jint);
1506 }
1507
1508 // Register for DIVI projection of divmodI
1509 RegMask Matcher::divI_proj_mask() {
1510 return EAX_REG_mask();
1511 }
1512
1513 // Register for MODI projection of divmodI
1514 RegMask Matcher::modI_proj_mask() {
1515 return EDX_REG_mask();
1516 }
1517
1518 // Register for DIVL projection of divmodL
1519 RegMask Matcher::divL_proj_mask() {
1520 ShouldNotReachHere();
1521 return RegMask();
1522 }
1523
1524 // Register for MODL projection of divmodL
1525 RegMask Matcher::modL_proj_mask() {
1526 ShouldNotReachHere();
1527 return RegMask();
1528 }
1529
1530 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1531 return NO_REG_mask();
1532 }
1533
1534 // Returns true if the high 32 bits of the value is known to be zero.
1535 bool is_operand_hi32_zero(Node* n) {
1536 int opc = n->Opcode();
1537 if (opc == Op_AndL) {
1538 Node* o2 = n->in(2);
1539 if (o2->is_Con() && (o2->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1540 return true;
1541 }
1542 }
1543 if (opc == Op_ConL && (n->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1544 return true;
1545 }
1546 return false;
1547 }
1548
1549 %}
1550
1551 //----------ENCODING BLOCK-----------------------------------------------------
1552 // This block specifies the encoding classes used by the compiler to output
1553 // byte streams. Encoding classes generate functions which are called by
1554 // Machine Instruction Nodes in order to generate the bit encoding of the
1555 // instruction. Operands specify their base encoding interface with the
1556 // interface keyword. There are currently supported four interfaces,
1557 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1558 // operand to generate a function which returns its register number when
1559 // queried. CONST_INTER causes an operand to generate a function which
1560 // returns the value of the constant when queried. MEMORY_INTER causes an
1561 // operand to generate four functions which return the Base Register, the
1562 // Index Register, the Scale Value, and the Offset Value of the operand when
1563 // queried. COND_INTER causes an operand to generate six functions which
1564 // return the encoding code (ie - encoding bits for the instruction)
1565 // associated with each basic boolean condition for a conditional instruction.
1566 // Instructions specify two basic values for encoding. They use the
1567 // ins_encode keyword to specify their encoding class (which must be one of
1568 // the class names specified in the encoding block), and they use the
1569 // opcode keyword to specify, in order, their primary, secondary, and
1570 // tertiary opcode. Only the opcode sections which a particular instruction
1571 // needs for encoding need to be specified.
1572 encode %{
1573 // Build emit functions for each basic byte or larger field in the intel
1574 // encoding scheme (opcode, rm, sib, immediate), and call them from C++
1575 // code in the enc_class source block. Emit functions will live in the
1576 // main source block for now. In future, we can generalize this by
1577 // adding a syntax that specifies the sizes of fields in an order,
1578 // so that the adlc can build the emit functions automagically
1579
1580 // Emit primary opcode
1581 enc_class OpcP %{
1582 emit_opcode(cbuf, $primary);
1583 %}
1584
1585 // Emit secondary opcode
1586 enc_class OpcS %{
1587 emit_opcode(cbuf, $secondary);
1588 %}
1589
1590 // Emit opcode directly
1591 enc_class Opcode(immI d8) %{
1592 emit_opcode(cbuf, $d8$$constant);
1593 %}
1594
1595 enc_class SizePrefix %{
1596 emit_opcode(cbuf,0x66);
1597 %}
1598
1599 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many)
1600 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1601 %}
1602
1603 enc_class OpcRegReg (immI opcode, rRegI dst, rRegI src) %{ // OpcRegReg(Many)
1604 emit_opcode(cbuf,$opcode$$constant);
1605 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1606 %}
1607
1608 enc_class mov_r32_imm0( rRegI dst ) %{
1609 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32
1610 emit_d32 ( cbuf, 0x0 ); // imm32==0x0
1611 %}
1612
1613 enc_class cdq_enc %{
1614 // Full implementation of Java idiv and irem; checks for
1615 // special case as described in JVM spec., p.243 & p.271.
1616 //
1617 // normal case special case
1618 //
1619 // input : rax,: dividend min_int
1620 // reg: divisor -1
1621 //
1622 // output: rax,: quotient (= rax, idiv reg) min_int
1623 // rdx: remainder (= rax, irem reg) 0
1624 //
1625 // Code sequnce:
1626 //
1627 // 81 F8 00 00 00 80 cmp rax,80000000h
1628 // 0F 85 0B 00 00 00 jne normal_case
1629 // 33 D2 xor rdx,edx
1630 // 83 F9 FF cmp rcx,0FFh
1631 // 0F 84 03 00 00 00 je done
1632 // normal_case:
1633 // 99 cdq
1634 // F7 F9 idiv rax,ecx
1635 // done:
1636 //
1637 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8);
1638 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00);
1639 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h
1640 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85);
1641 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00);
1642 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case
1643 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx
1644 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh
1645 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84);
1646 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00);
1647 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done
1648 // normal_case:
1649 emit_opcode(cbuf,0x99); // cdq
1650 // idiv (note: must be emitted by the user of this rule)
1651 // normal:
1652 %}
1653
1654 // Dense encoding for older common ops
1655 enc_class Opc_plus(immI opcode, rRegI reg) %{
1656 emit_opcode(cbuf, $opcode$$constant + $reg$$reg);
1657 %}
1658
1659
1660 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1661 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit
1662 // Check for 8-bit immediate, and set sign extend bit in opcode
1663 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1664 emit_opcode(cbuf, $primary | 0x02);
1665 }
1666 else { // If 32-bit immediate
1667 emit_opcode(cbuf, $primary);
1668 }
1669 %}
1670
1671 enc_class OpcSErm (rRegI dst, immI imm) %{ // OpcSEr/m
1672 // Emit primary opcode and set sign-extend bit
1673 // Check for 8-bit immediate, and set sign extend bit in opcode
1674 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1675 emit_opcode(cbuf, $primary | 0x02); }
1676 else { // If 32-bit immediate
1677 emit_opcode(cbuf, $primary);
1678 }
1679 // Emit r/m byte with secondary opcode, after primary opcode.
1680 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1681 %}
1682
1683 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits
1684 // Check for 8-bit immediate, and set sign extend bit in opcode
1685 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1686 $$$emit8$imm$$constant;
1687 }
1688 else { // If 32-bit immediate
1689 // Output immediate
1690 $$$emit32$imm$$constant;
1691 }
1692 %}
1693
1694 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{
1695 // Emit primary opcode and set sign-extend bit
1696 // Check for 8-bit immediate, and set sign extend bit in opcode
1697 int con = (int)$imm$$constant; // Throw away top bits
1698 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1699 // Emit r/m byte with secondary opcode, after primary opcode.
1700 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1701 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1702 else emit_d32(cbuf,con);
1703 %}
1704
1705 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{
1706 // Emit primary opcode and set sign-extend bit
1707 // Check for 8-bit immediate, and set sign extend bit in opcode
1708 int con = (int)($imm$$constant >> 32); // Throw away bottom bits
1709 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1710 // Emit r/m byte with tertiary opcode, after primary opcode.
1711 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg));
1712 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1713 else emit_d32(cbuf,con);
1714 %}
1715
1716 enc_class OpcSReg (rRegI dst) %{ // BSWAP
1717 emit_cc(cbuf, $secondary, $dst$$reg );
1718 %}
1719
1720 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP
1721 int destlo = $dst$$reg;
1722 int desthi = HIGH_FROM_LOW(destlo);
1723 // bswap lo
1724 emit_opcode(cbuf, 0x0F);
1725 emit_cc(cbuf, 0xC8, destlo);
1726 // bswap hi
1727 emit_opcode(cbuf, 0x0F);
1728 emit_cc(cbuf, 0xC8, desthi);
1729 // xchg lo and hi
1730 emit_opcode(cbuf, 0x87);
1731 emit_rm(cbuf, 0x3, destlo, desthi);
1732 %}
1733
1734 enc_class RegOpc (rRegI div) %{ // IDIV, IMOD, JMP indirect, ...
1735 emit_rm(cbuf, 0x3, $secondary, $div$$reg );
1736 %}
1737
1738 enc_class enc_cmov(cmpOp cop ) %{ // CMOV
1739 $$$emit8$primary;
1740 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1741 %}
1742
1743 enc_class enc_cmov_dpr(cmpOp cop, regDPR src ) %{ // CMOV
1744 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1);
1745 emit_d8(cbuf, op >> 8 );
1746 emit_d8(cbuf, op & 255);
1747 %}
1748
1749 // emulate a CMOV with a conditional branch around a MOV
1750 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV
1751 // Invert sense of branch from sense of CMOV
1752 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) );
1753 emit_d8( cbuf, $brOffs$$constant );
1754 %}
1755
1756 enc_class enc_PartialSubtypeCheck( ) %{
1757 Register Redi = as_Register(EDI_enc); // result register
1758 Register Reax = as_Register(EAX_enc); // super class
1759 Register Recx = as_Register(ECX_enc); // killed
1760 Register Resi = as_Register(ESI_enc); // sub class
1761 Label miss;
1762
1763 MacroAssembler _masm(&cbuf);
1764 __ check_klass_subtype_slow_path(Resi, Reax, Recx, Redi,
1765 NULL, &miss,
1766 /*set_cond_codes:*/ true);
1767 if ($primary) {
1768 __ xorptr(Redi, Redi);
1769 }
1770 __ bind(miss);
1771 %}
1772
1773 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All
1774 MacroAssembler masm(&cbuf);
1775 int start = masm.offset();
1776 if (UseSSE >= 2) {
1777 if (VerifyFPU) {
1778 masm.verify_FPU(0, "must be empty in SSE2+ mode");
1779 }
1780 } else {
1781 // External c_calling_convention expects the FPU stack to be 'clean'.
1782 // Compiled code leaves it dirty. Do cleanup now.
1783 masm.empty_FPU_stack();
1784 }
1785 if (sizeof_FFree_Float_Stack_All == -1) {
1786 sizeof_FFree_Float_Stack_All = masm.offset() - start;
1787 } else {
1788 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size");
1789 }
1790 %}
1791
1792 enc_class Verify_FPU_For_Leaf %{
1793 if( VerifyFPU ) {
1794 MacroAssembler masm(&cbuf);
1795 masm.verify_FPU( -3, "Returning from Runtime Leaf call");
1796 }
1797 %}
1798
1799 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf
1800 // This is the instruction starting address for relocation info.
1801 cbuf.set_insts_mark();
1802 $$$emit8$primary;
1803 // CALL directly to the runtime
1804 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1805 runtime_call_Relocation::spec(), RELOC_IMM32 );
1806
1807 if (UseSSE >= 2) {
1808 MacroAssembler _masm(&cbuf);
1809 BasicType rt = tf()->return_type();
1810
1811 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) {
1812 // A C runtime call where the return value is unused. In SSE2+
1813 // mode the result needs to be removed from the FPU stack. It's
1814 // likely that this function call could be removed by the
1815 // optimizer if the C function is a pure function.
1816 __ ffree(0);
1817 } else if (rt == T_FLOAT) {
1818 __ lea(rsp, Address(rsp, -4));
1819 __ fstp_s(Address(rsp, 0));
1820 __ movflt(xmm0, Address(rsp, 0));
1821 __ lea(rsp, Address(rsp, 4));
1822 } else if (rt == T_DOUBLE) {
1823 __ lea(rsp, Address(rsp, -8));
1824 __ fstp_d(Address(rsp, 0));
1825 __ movdbl(xmm0, Address(rsp, 0));
1826 __ lea(rsp, Address(rsp, 8));
1827 }
1828 }
1829 %}
1830
1831
1832 enc_class pre_call_resets %{
1833 // If method sets FPU control word restore it here
1834 debug_only(int off0 = cbuf.insts_size());
1835 if (ra_->C->in_24_bit_fp_mode()) {
1836 MacroAssembler _masm(&cbuf);
1837 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1838 }
1839 if (ra_->C->max_vector_size() > 16) {
1840 // Clear upper bits of YMM registers when current compiled code uses
1841 // wide vectors to avoid AVX <-> SSE transition penalty during call.
1842 MacroAssembler _masm(&cbuf);
1843 __ vzeroupper();
1844 }
1845 debug_only(int off1 = cbuf.insts_size());
1846 assert(off1 - off0 == pre_call_resets_size(), "correct size prediction");
1847 %}
1848
1849 enc_class post_call_FPU %{
1850 // If method sets FPU control word do it here also
1851 if (Compile::current()->in_24_bit_fp_mode()) {
1852 MacroAssembler masm(&cbuf);
1853 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
1854 }
1855 %}
1856
1857 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
1858 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1859 // who we intended to call.
1860 cbuf.set_insts_mark();
1861 $$$emit8$primary;
1862 if (!_method) {
1863 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1864 runtime_call_Relocation::spec(), RELOC_IMM32 );
1865 } else if (_optimized_virtual) {
1866 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1867 opt_virtual_call_Relocation::spec(), RELOC_IMM32 );
1868 } else {
1869 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1870 static_call_Relocation::spec(), RELOC_IMM32 );
1871 }
1872 if (_method) { // Emit stub for static call.
1873 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf);
1874 if (stub == NULL) {
1875 ciEnv::current()->record_failure("CodeCache is full");
1876 return;
1877 }
1878 }
1879 %}
1880
1881 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
1882 MacroAssembler _masm(&cbuf);
1883 __ ic_call((address)$meth$$method);
1884 %}
1885
1886 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
1887 int disp = in_bytes(Method::from_compiled_offset());
1888 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small");
1889
1890 // CALL *[EAX+in_bytes(Method::from_compiled_code_entry_point_offset())]
1891 cbuf.set_insts_mark();
1892 $$$emit8$primary;
1893 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte
1894 emit_d8(cbuf, disp); // Displacement
1895
1896 %}
1897
1898 // Following encoding is no longer used, but may be restored if calling
1899 // convention changes significantly.
1900 // Became: Xor_Reg(EBP), Java_To_Runtime( labl )
1901 //
1902 // enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL
1903 // // int ic_reg = Matcher::inline_cache_reg();
1904 // // int ic_encode = Matcher::_regEncode[ic_reg];
1905 // // int imo_reg = Matcher::interpreter_method_oop_reg();
1906 // // int imo_encode = Matcher::_regEncode[imo_reg];
1907 //
1908 // // // Interpreter expects method_oop in EBX, currently a callee-saved register,
1909 // // // so we load it immediately before the call
1910 // // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop
1911 // // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte
1912 //
1913 // // xor rbp,ebp
1914 // emit_opcode(cbuf, 0x33);
1915 // emit_rm(cbuf, 0x3, EBP_enc, EBP_enc);
1916 //
1917 // // CALL to interpreter.
1918 // cbuf.set_insts_mark();
1919 // $$$emit8$primary;
1920 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.insts_end()) - 4),
1921 // runtime_call_Relocation::spec(), RELOC_IMM32 );
1922 // %}
1923
1924 enc_class RegOpcImm (rRegI dst, immI8 shift) %{ // SHL, SAR, SHR
1925 $$$emit8$primary;
1926 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1927 $$$emit8$shift$$constant;
1928 %}
1929
1930 enc_class LdImmI (rRegI dst, immI src) %{ // Load Immediate
1931 // Load immediate does not have a zero or sign extended version
1932 // for 8-bit immediates
1933 emit_opcode(cbuf, 0xB8 + $dst$$reg);
1934 $$$emit32$src$$constant;
1935 %}
1936
1937 enc_class LdImmP (rRegI dst, immI src) %{ // Load Immediate
1938 // Load immediate does not have a zero or sign extended version
1939 // for 8-bit immediates
1940 emit_opcode(cbuf, $primary + $dst$$reg);
1941 $$$emit32$src$$constant;
1942 %}
1943
1944 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate
1945 // Load immediate does not have a zero or sign extended version
1946 // for 8-bit immediates
1947 int dst_enc = $dst$$reg;
1948 int src_con = $src$$constant & 0x0FFFFFFFFL;
1949 if (src_con == 0) {
1950 // xor dst, dst
1951 emit_opcode(cbuf, 0x33);
1952 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1953 } else {
1954 emit_opcode(cbuf, $primary + dst_enc);
1955 emit_d32(cbuf, src_con);
1956 }
1957 %}
1958
1959 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate
1960 // Load immediate does not have a zero or sign extended version
1961 // for 8-bit immediates
1962 int dst_enc = $dst$$reg + 2;
1963 int src_con = ((julong)($src$$constant)) >> 32;
1964 if (src_con == 0) {
1965 // xor dst, dst
1966 emit_opcode(cbuf, 0x33);
1967 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1968 } else {
1969 emit_opcode(cbuf, $primary + dst_enc);
1970 emit_d32(cbuf, src_con);
1971 }
1972 %}
1973
1974
1975 // Encode a reg-reg copy. If it is useless, then empty encoding.
1976 enc_class enc_Copy( rRegI dst, rRegI src ) %{
1977 encode_Copy( cbuf, $dst$$reg, $src$$reg );
1978 %}
1979
1980 enc_class enc_CopyL_Lo( rRegI dst, eRegL src ) %{
1981 encode_Copy( cbuf, $dst$$reg, $src$$reg );
1982 %}
1983
1984 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many)
1985 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1986 %}
1987
1988 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many)
1989 $$$emit8$primary;
1990 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1991 %}
1992
1993 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many)
1994 $$$emit8$secondary;
1995 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
1996 %}
1997
1998 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many)
1999 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2000 %}
2001
2002 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many)
2003 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2004 %}
2005
2006 enc_class RegReg_HiLo( eRegL src, rRegI dst ) %{
2007 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg));
2008 %}
2009
2010 enc_class Con32 (immI src) %{ // Con32(storeImmI)
2011 // Output immediate
2012 $$$emit32$src$$constant;
2013 %}
2014
2015 enc_class Con32FPR_as_bits(immFPR src) %{ // storeF_imm
2016 // Output Float immediate bits
2017 jfloat jf = $src$$constant;
2018 int jf_as_bits = jint_cast( jf );
2019 emit_d32(cbuf, jf_as_bits);
2020 %}
2021
2022 enc_class Con32F_as_bits(immF src) %{ // storeX_imm
2023 // Output Float immediate bits
2024 jfloat jf = $src$$constant;
2025 int jf_as_bits = jint_cast( jf );
2026 emit_d32(cbuf, jf_as_bits);
2027 %}
2028
2029 enc_class Con16 (immI src) %{ // Con16(storeImmI)
2030 // Output immediate
2031 $$$emit16$src$$constant;
2032 %}
2033
2034 enc_class Con_d32(immI src) %{
2035 emit_d32(cbuf,$src$$constant);
2036 %}
2037
2038 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI)
2039 // Output immediate memory reference
2040 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2041 emit_d32(cbuf, 0x00);
2042 %}
2043
2044 enc_class lock_prefix( ) %{
2045 if( os::is_MP() )
2046 emit_opcode(cbuf,0xF0); // [Lock]
2047 %}
2048
2049 // Cmp-xchg long value.
2050 // Note: we need to swap rbx, and rcx before and after the
2051 // cmpxchg8 instruction because the instruction uses
2052 // rcx as the high order word of the new value to store but
2053 // our register encoding uses rbx,.
2054 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{
2055
2056 // XCHG rbx,ecx
2057 emit_opcode(cbuf,0x87);
2058 emit_opcode(cbuf,0xD9);
2059 // [Lock]
2060 if( os::is_MP() )
2061 emit_opcode(cbuf,0xF0);
2062 // CMPXCHG8 [Eptr]
2063 emit_opcode(cbuf,0x0F);
2064 emit_opcode(cbuf,0xC7);
2065 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2066 // XCHG rbx,ecx
2067 emit_opcode(cbuf,0x87);
2068 emit_opcode(cbuf,0xD9);
2069 %}
2070
2071 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{
2072 // [Lock]
2073 if( os::is_MP() )
2074 emit_opcode(cbuf,0xF0);
2075
2076 // CMPXCHG [Eptr]
2077 emit_opcode(cbuf,0x0F);
2078 emit_opcode(cbuf,0xB1);
2079 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2080 %}
2081
2082 enc_class enc_flags_ne_to_boolean( iRegI res ) %{
2083 int res_encoding = $res$$reg;
2084
2085 // MOV res,0
2086 emit_opcode( cbuf, 0xB8 + res_encoding);
2087 emit_d32( cbuf, 0 );
2088 // JNE,s fail
2089 emit_opcode(cbuf,0x75);
2090 emit_d8(cbuf, 5 );
2091 // MOV res,1
2092 emit_opcode( cbuf, 0xB8 + res_encoding);
2093 emit_d32( cbuf, 1 );
2094 // fail:
2095 %}
2096
2097 enc_class set_instruction_start( ) %{
2098 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2099 %}
2100
2101 enc_class RegMem (rRegI ereg, memory mem) %{ // emit_reg_mem
2102 int reg_encoding = $ereg$$reg;
2103 int base = $mem$$base;
2104 int index = $mem$$index;
2105 int scale = $mem$$scale;
2106 int displace = $mem$$disp;
2107 relocInfo::relocType disp_reloc = $mem->disp_reloc();
2108 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2109 %}
2110
2111 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem
2112 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo
2113 int base = $mem$$base;
2114 int index = $mem$$index;
2115 int scale = $mem$$scale;
2116 int displace = $mem$$disp + 4; // Offset is 4 further in memory
2117 assert( $mem->disp_reloc() == relocInfo::none, "Cannot add 4 to oop" );
2118 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, relocInfo::none);
2119 %}
2120
2121 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{
2122 int r1, r2;
2123 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2124 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2125 emit_opcode(cbuf,0x0F);
2126 emit_opcode(cbuf,$tertiary);
2127 emit_rm(cbuf, 0x3, r1, r2);
2128 emit_d8(cbuf,$cnt$$constant);
2129 emit_d8(cbuf,$primary);
2130 emit_rm(cbuf, 0x3, $secondary, r1);
2131 emit_d8(cbuf,$cnt$$constant);
2132 %}
2133
2134 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{
2135 emit_opcode( cbuf, 0x8B ); // Move
2136 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2137 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2138 emit_d8(cbuf,$primary);
2139 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
2140 emit_d8(cbuf,$cnt$$constant-32);
2141 }
2142 emit_d8(cbuf,$primary);
2143 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg));
2144 emit_d8(cbuf,31);
2145 %}
2146
2147 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{
2148 int r1, r2;
2149 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2150 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2151
2152 emit_opcode( cbuf, 0x8B ); // Move r1,r2
2153 emit_rm(cbuf, 0x3, r1, r2);
2154 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2155 emit_opcode(cbuf,$primary);
2156 emit_rm(cbuf, 0x3, $secondary, r1);
2157 emit_d8(cbuf,$cnt$$constant-32);
2158 }
2159 emit_opcode(cbuf,0x33); // XOR r2,r2
2160 emit_rm(cbuf, 0x3, r2, r2);
2161 %}
2162
2163 // Clone of RegMem but accepts an extra parameter to access each
2164 // half of a double in memory; it never needs relocation info.
2165 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, rRegI rm_reg) %{
2166 emit_opcode(cbuf,$opcode$$constant);
2167 int reg_encoding = $rm_reg$$reg;
2168 int base = $mem$$base;
2169 int index = $mem$$index;
2170 int scale = $mem$$scale;
2171 int displace = $mem$$disp + $disp_for_half$$constant;
2172 relocInfo::relocType disp_reloc = relocInfo::none;
2173 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2174 %}
2175
2176 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!!
2177 //
2178 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant
2179 // and it never needs relocation information.
2180 // Frequently used to move data between FPU's Stack Top and memory.
2181 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{
2182 int rm_byte_opcode = $rm_opcode$$constant;
2183 int base = $mem$$base;
2184 int index = $mem$$index;
2185 int scale = $mem$$scale;
2186 int displace = $mem$$disp;
2187 assert( $mem->disp_reloc() == relocInfo::none, "No oops here because no reloc info allowed" );
2188 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, relocInfo::none);
2189 %}
2190
2191 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{
2192 int rm_byte_opcode = $rm_opcode$$constant;
2193 int base = $mem$$base;
2194 int index = $mem$$index;
2195 int scale = $mem$$scale;
2196 int displace = $mem$$disp;
2197 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
2198 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
2199 %}
2200
2201 enc_class RegLea (rRegI dst, rRegI src0, immI src1 ) %{ // emit_reg_lea
2202 int reg_encoding = $dst$$reg;
2203 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2204 int index = 0x04; // 0x04 indicates no index
2205 int scale = 0x00; // 0x00 indicates no scale
2206 int displace = $src1$$constant; // 0x00 indicates no displacement
2207 relocInfo::relocType disp_reloc = relocInfo::none;
2208 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2209 %}
2210
2211 enc_class min_enc (rRegI dst, rRegI src) %{ // MIN
2212 // Compare dst,src
2213 emit_opcode(cbuf,0x3B);
2214 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2215 // jmp dst < src around move
2216 emit_opcode(cbuf,0x7C);
2217 emit_d8(cbuf,2);
2218 // move dst,src
2219 emit_opcode(cbuf,0x8B);
2220 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2221 %}
2222
2223 enc_class max_enc (rRegI dst, rRegI src) %{ // MAX
2224 // Compare dst,src
2225 emit_opcode(cbuf,0x3B);
2226 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2227 // jmp dst > src around move
2228 emit_opcode(cbuf,0x7F);
2229 emit_d8(cbuf,2);
2230 // move dst,src
2231 emit_opcode(cbuf,0x8B);
2232 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2233 %}
2234
2235 enc_class enc_FPR_store(memory mem, regDPR src) %{
2236 // If src is FPR1, we can just FST to store it.
2237 // Else we need to FLD it to FPR1, then FSTP to store/pop it.
2238 int reg_encoding = 0x2; // Just store
2239 int base = $mem$$base;
2240 int index = $mem$$index;
2241 int scale = $mem$$scale;
2242 int displace = $mem$$disp;
2243 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
2244 if( $src$$reg != FPR1L_enc ) {
2245 reg_encoding = 0x3; // Store & pop
2246 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it)
2247 emit_d8( cbuf, 0xC0-1+$src$$reg );
2248 }
2249 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2250 emit_opcode(cbuf,$primary);
2251 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2252 %}
2253
2254 enc_class neg_reg(rRegI dst) %{
2255 // NEG $dst
2256 emit_opcode(cbuf,0xF7);
2257 emit_rm(cbuf, 0x3, 0x03, $dst$$reg );
2258 %}
2259
2260 enc_class setLT_reg(eCXRegI dst) %{
2261 // SETLT $dst
2262 emit_opcode(cbuf,0x0F);
2263 emit_opcode(cbuf,0x9C);
2264 emit_rm( cbuf, 0x3, 0x4, $dst$$reg );
2265 %}
2266
2267 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT
2268 int tmpReg = $tmp$$reg;
2269
2270 // SUB $p,$q
2271 emit_opcode(cbuf,0x2B);
2272 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2273 // SBB $tmp,$tmp
2274 emit_opcode(cbuf,0x1B);
2275 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2276 // AND $tmp,$y
2277 emit_opcode(cbuf,0x23);
2278 emit_rm(cbuf, 0x3, tmpReg, $y$$reg);
2279 // ADD $p,$tmp
2280 emit_opcode(cbuf,0x03);
2281 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2282 %}
2283
2284 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{
2285 // TEST shift,32
2286 emit_opcode(cbuf,0xF7);
2287 emit_rm(cbuf, 0x3, 0, ECX_enc);
2288 emit_d32(cbuf,0x20);
2289 // JEQ,s small
2290 emit_opcode(cbuf, 0x74);
2291 emit_d8(cbuf, 0x04);
2292 // MOV $dst.hi,$dst.lo
2293 emit_opcode( cbuf, 0x8B );
2294 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2295 // CLR $dst.lo
2296 emit_opcode(cbuf, 0x33);
2297 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
2298 // small:
2299 // SHLD $dst.hi,$dst.lo,$shift
2300 emit_opcode(cbuf,0x0F);
2301 emit_opcode(cbuf,0xA5);
2302 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2303 // SHL $dst.lo,$shift"
2304 emit_opcode(cbuf,0xD3);
2305 emit_rm(cbuf, 0x3, 0x4, $dst$$reg );
2306 %}
2307
2308 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{
2309 // TEST shift,32
2310 emit_opcode(cbuf,0xF7);
2311 emit_rm(cbuf, 0x3, 0, ECX_enc);
2312 emit_d32(cbuf,0x20);
2313 // JEQ,s small
2314 emit_opcode(cbuf, 0x74);
2315 emit_d8(cbuf, 0x04);
2316 // MOV $dst.lo,$dst.hi
2317 emit_opcode( cbuf, 0x8B );
2318 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2319 // CLR $dst.hi
2320 emit_opcode(cbuf, 0x33);
2321 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg));
2322 // small:
2323 // SHRD $dst.lo,$dst.hi,$shift
2324 emit_opcode(cbuf,0x0F);
2325 emit_opcode(cbuf,0xAD);
2326 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2327 // SHR $dst.hi,$shift"
2328 emit_opcode(cbuf,0xD3);
2329 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) );
2330 %}
2331
2332 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{
2333 // TEST shift,32
2334 emit_opcode(cbuf,0xF7);
2335 emit_rm(cbuf, 0x3, 0, ECX_enc);
2336 emit_d32(cbuf,0x20);
2337 // JEQ,s small
2338 emit_opcode(cbuf, 0x74);
2339 emit_d8(cbuf, 0x05);
2340 // MOV $dst.lo,$dst.hi
2341 emit_opcode( cbuf, 0x8B );
2342 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2343 // SAR $dst.hi,31
2344 emit_opcode(cbuf, 0xC1);
2345 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) );
2346 emit_d8(cbuf, 0x1F );
2347 // small:
2348 // SHRD $dst.lo,$dst.hi,$shift
2349 emit_opcode(cbuf,0x0F);
2350 emit_opcode(cbuf,0xAD);
2351 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2352 // SAR $dst.hi,$shift"
2353 emit_opcode(cbuf,0xD3);
2354 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) );
2355 %}
2356
2357
2358 // ----------------- Encodings for floating point unit -----------------
2359 // May leave result in FPU-TOS or FPU reg depending on opcodes
2360 enc_class OpcReg_FPR(regFPR src) %{ // FMUL, FDIV
2361 $$$emit8$primary;
2362 emit_rm(cbuf, 0x3, $secondary, $src$$reg );
2363 %}
2364
2365 // Pop argument in FPR0 with FSTP ST(0)
2366 enc_class PopFPU() %{
2367 emit_opcode( cbuf, 0xDD );
2368 emit_d8( cbuf, 0xD8 );
2369 %}
2370
2371 // !!!!! equivalent to Pop_Reg_F
2372 enc_class Pop_Reg_DPR( regDPR dst ) %{
2373 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2374 emit_d8( cbuf, 0xD8+$dst$$reg );
2375 %}
2376
2377 enc_class Push_Reg_DPR( regDPR dst ) %{
2378 emit_opcode( cbuf, 0xD9 );
2379 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1)
2380 %}
2381
2382 enc_class strictfp_bias1( regDPR dst ) %{
2383 emit_opcode( cbuf, 0xDB ); // FLD m80real
2384 emit_opcode( cbuf, 0x2D );
2385 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() );
2386 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2387 emit_opcode( cbuf, 0xC8+$dst$$reg );
2388 %}
2389
2390 enc_class strictfp_bias2( regDPR dst ) %{
2391 emit_opcode( cbuf, 0xDB ); // FLD m80real
2392 emit_opcode( cbuf, 0x2D );
2393 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() );
2394 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2395 emit_opcode( cbuf, 0xC8+$dst$$reg );
2396 %}
2397
2398 // Special case for moving an integer register to a stack slot.
2399 enc_class OpcPRegSS( stackSlotI dst, rRegI src ) %{ // RegSS
2400 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp );
2401 %}
2402
2403 // Special case for moving a register to a stack slot.
2404 enc_class RegSS( stackSlotI dst, rRegI src ) %{ // RegSS
2405 // Opcode already emitted
2406 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte
2407 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
2408 emit_d32(cbuf, $dst$$disp); // Displacement
2409 %}
2410
2411 // Push the integer in stackSlot 'src' onto FP-stack
2412 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src]
2413 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp );
2414 %}
2415
2416 // Push FPU's TOS float to a stack-slot, and pop FPU-stack
2417 enc_class Pop_Mem_FPR( stackSlotF dst ) %{ // FSTP_S [ESP+dst]
2418 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp );
2419 %}
2420
2421 // Same as Pop_Mem_F except for opcode
2422 // Push FPU's TOS double to a stack-slot, and pop FPU-stack
2423 enc_class Pop_Mem_DPR( stackSlotD dst ) %{ // FSTP_D [ESP+dst]
2424 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp );
2425 %}
2426
2427 enc_class Pop_Reg_FPR( regFPR dst ) %{
2428 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2429 emit_d8( cbuf, 0xD8+$dst$$reg );
2430 %}
2431
2432 enc_class Push_Reg_FPR( regFPR dst ) %{
2433 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2434 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2435 %}
2436
2437 // Push FPU's float to a stack-slot, and pop FPU-stack
2438 enc_class Pop_Mem_Reg_FPR( stackSlotF dst, regFPR src ) %{
2439 int pop = 0x02;
2440 if ($src$$reg != FPR1L_enc) {
2441 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2442 emit_d8( cbuf, 0xC0-1+$src$$reg );
2443 pop = 0x03;
2444 }
2445 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst]
2446 %}
2447
2448 // Push FPU's double to a stack-slot, and pop FPU-stack
2449 enc_class Pop_Mem_Reg_DPR( stackSlotD dst, regDPR src ) %{
2450 int pop = 0x02;
2451 if ($src$$reg != FPR1L_enc) {
2452 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2453 emit_d8( cbuf, 0xC0-1+$src$$reg );
2454 pop = 0x03;
2455 }
2456 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst]
2457 %}
2458
2459 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack
2460 enc_class Pop_Reg_Reg_DPR( regDPR dst, regFPR src ) %{
2461 int pop = 0xD0 - 1; // -1 since we skip FLD
2462 if ($src$$reg != FPR1L_enc) {
2463 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1)
2464 emit_d8( cbuf, 0xC0-1+$src$$reg );
2465 pop = 0xD8;
2466 }
2467 emit_opcode( cbuf, 0xDD );
2468 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i)
2469 %}
2470
2471
2472 enc_class Push_Reg_Mod_DPR( regDPR dst, regDPR src) %{
2473 // load dst in FPR0
2474 emit_opcode( cbuf, 0xD9 );
2475 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2476 if ($src$$reg != FPR1L_enc) {
2477 // fincstp
2478 emit_opcode (cbuf, 0xD9);
2479 emit_opcode (cbuf, 0xF7);
2480 // swap src with FPR1:
2481 // FXCH FPR1 with src
2482 emit_opcode(cbuf, 0xD9);
2483 emit_d8(cbuf, 0xC8-1+$src$$reg );
2484 // fdecstp
2485 emit_opcode (cbuf, 0xD9);
2486 emit_opcode (cbuf, 0xF6);
2487 }
2488 %}
2489
2490 enc_class Push_ModD_encoding(regD src0, regD src1) %{
2491 MacroAssembler _masm(&cbuf);
2492 __ subptr(rsp, 8);
2493 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
2494 __ fld_d(Address(rsp, 0));
2495 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
2496 __ fld_d(Address(rsp, 0));
2497 %}
2498
2499 enc_class Push_ModF_encoding(regF src0, regF src1) %{
2500 MacroAssembler _masm(&cbuf);
2501 __ subptr(rsp, 4);
2502 __ movflt(Address(rsp, 0), $src1$$XMMRegister);
2503 __ fld_s(Address(rsp, 0));
2504 __ movflt(Address(rsp, 0), $src0$$XMMRegister);
2505 __ fld_s(Address(rsp, 0));
2506 %}
2507
2508 enc_class Push_ResultD(regD dst) %{
2509 MacroAssembler _masm(&cbuf);
2510 __ fstp_d(Address(rsp, 0));
2511 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2512 __ addptr(rsp, 8);
2513 %}
2514
2515 enc_class Push_ResultF(regF dst, immI d8) %{
2516 MacroAssembler _masm(&cbuf);
2517 __ fstp_s(Address(rsp, 0));
2518 __ movflt($dst$$XMMRegister, Address(rsp, 0));
2519 __ addptr(rsp, $d8$$constant);
2520 %}
2521
2522 enc_class Push_SrcD(regD src) %{
2523 MacroAssembler _masm(&cbuf);
2524 __ subptr(rsp, 8);
2525 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2526 __ fld_d(Address(rsp, 0));
2527 %}
2528
2529 enc_class push_stack_temp_qword() %{
2530 MacroAssembler _masm(&cbuf);
2531 __ subptr(rsp, 8);
2532 %}
2533
2534 enc_class pop_stack_temp_qword() %{
2535 MacroAssembler _masm(&cbuf);
2536 __ addptr(rsp, 8);
2537 %}
2538
2539 enc_class push_xmm_to_fpr1(regD src) %{
2540 MacroAssembler _masm(&cbuf);
2541 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2542 __ fld_d(Address(rsp, 0));
2543 %}
2544
2545 enc_class Push_Result_Mod_DPR( regDPR src) %{
2546 if ($src$$reg != FPR1L_enc) {
2547 // fincstp
2548 emit_opcode (cbuf, 0xD9);
2549 emit_opcode (cbuf, 0xF7);
2550 // FXCH FPR1 with src
2551 emit_opcode(cbuf, 0xD9);
2552 emit_d8(cbuf, 0xC8-1+$src$$reg );
2553 // fdecstp
2554 emit_opcode (cbuf, 0xD9);
2555 emit_opcode (cbuf, 0xF6);
2556 }
2557 // // following asm replaced with Pop_Reg_F or Pop_Mem_F
2558 // // FSTP FPR$dst$$reg
2559 // emit_opcode( cbuf, 0xDD );
2560 // emit_d8( cbuf, 0xD8+$dst$$reg );
2561 %}
2562
2563 enc_class fnstsw_sahf_skip_parity() %{
2564 // fnstsw ax
2565 emit_opcode( cbuf, 0xDF );
2566 emit_opcode( cbuf, 0xE0 );
2567 // sahf
2568 emit_opcode( cbuf, 0x9E );
2569 // jnp ::skip
2570 emit_opcode( cbuf, 0x7B );
2571 emit_opcode( cbuf, 0x05 );
2572 %}
2573
2574 enc_class emitModDPR() %{
2575 // fprem must be iterative
2576 // :: loop
2577 // fprem
2578 emit_opcode( cbuf, 0xD9 );
2579 emit_opcode( cbuf, 0xF8 );
2580 // wait
2581 emit_opcode( cbuf, 0x9b );
2582 // fnstsw ax
2583 emit_opcode( cbuf, 0xDF );
2584 emit_opcode( cbuf, 0xE0 );
2585 // sahf
2586 emit_opcode( cbuf, 0x9E );
2587 // jp ::loop
2588 emit_opcode( cbuf, 0x0F );
2589 emit_opcode( cbuf, 0x8A );
2590 emit_opcode( cbuf, 0xF4 );
2591 emit_opcode( cbuf, 0xFF );
2592 emit_opcode( cbuf, 0xFF );
2593 emit_opcode( cbuf, 0xFF );
2594 %}
2595
2596 enc_class fpu_flags() %{
2597 // fnstsw_ax
2598 emit_opcode( cbuf, 0xDF);
2599 emit_opcode( cbuf, 0xE0);
2600 // test ax,0x0400
2601 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate
2602 emit_opcode( cbuf, 0xA9 );
2603 emit_d16 ( cbuf, 0x0400 );
2604 // // // This sequence works, but stalls for 12-16 cycles on PPro
2605 // // test rax,0x0400
2606 // emit_opcode( cbuf, 0xA9 );
2607 // emit_d32 ( cbuf, 0x00000400 );
2608 //
2609 // jz exit (no unordered comparison)
2610 emit_opcode( cbuf, 0x74 );
2611 emit_d8 ( cbuf, 0x02 );
2612 // mov ah,1 - treat as LT case (set carry flag)
2613 emit_opcode( cbuf, 0xB4 );
2614 emit_d8 ( cbuf, 0x01 );
2615 // sahf
2616 emit_opcode( cbuf, 0x9E);
2617 %}
2618
2619 enc_class cmpF_P6_fixup() %{
2620 // Fixup the integer flags in case comparison involved a NaN
2621 //
2622 // JNP exit (no unordered comparison, P-flag is set by NaN)
2623 emit_opcode( cbuf, 0x7B );
2624 emit_d8 ( cbuf, 0x03 );
2625 // MOV AH,1 - treat as LT case (set carry flag)
2626 emit_opcode( cbuf, 0xB4 );
2627 emit_d8 ( cbuf, 0x01 );
2628 // SAHF
2629 emit_opcode( cbuf, 0x9E);
2630 // NOP // target for branch to avoid branch to branch
2631 emit_opcode( cbuf, 0x90);
2632 %}
2633
2634 // fnstsw_ax();
2635 // sahf();
2636 // movl(dst, nan_result);
2637 // jcc(Assembler::parity, exit);
2638 // movl(dst, less_result);
2639 // jcc(Assembler::below, exit);
2640 // movl(dst, equal_result);
2641 // jcc(Assembler::equal, exit);
2642 // movl(dst, greater_result);
2643
2644 // less_result = 1;
2645 // greater_result = -1;
2646 // equal_result = 0;
2647 // nan_result = -1;
2648
2649 enc_class CmpF_Result(rRegI dst) %{
2650 // fnstsw_ax();
2651 emit_opcode( cbuf, 0xDF);
2652 emit_opcode( cbuf, 0xE0);
2653 // sahf
2654 emit_opcode( cbuf, 0x9E);
2655 // movl(dst, nan_result);
2656 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2657 emit_d32( cbuf, -1 );
2658 // jcc(Assembler::parity, exit);
2659 emit_opcode( cbuf, 0x7A );
2660 emit_d8 ( cbuf, 0x13 );
2661 // movl(dst, less_result);
2662 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2663 emit_d32( cbuf, -1 );
2664 // jcc(Assembler::below, exit);
2665 emit_opcode( cbuf, 0x72 );
2666 emit_d8 ( cbuf, 0x0C );
2667 // movl(dst, equal_result);
2668 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2669 emit_d32( cbuf, 0 );
2670 // jcc(Assembler::equal, exit);
2671 emit_opcode( cbuf, 0x74 );
2672 emit_d8 ( cbuf, 0x05 );
2673 // movl(dst, greater_result);
2674 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2675 emit_d32( cbuf, 1 );
2676 %}
2677
2678
2679 // Compare the longs and set flags
2680 // BROKEN! Do Not use as-is
2681 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{
2682 // CMP $src1.hi,$src2.hi
2683 emit_opcode( cbuf, 0x3B );
2684 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2685 // JNE,s done
2686 emit_opcode(cbuf,0x75);
2687 emit_d8(cbuf, 2 );
2688 // CMP $src1.lo,$src2.lo
2689 emit_opcode( cbuf, 0x3B );
2690 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2691 // done:
2692 %}
2693
2694 enc_class convert_int_long( regL dst, rRegI src ) %{
2695 // mov $dst.lo,$src
2696 int dst_encoding = $dst$$reg;
2697 int src_encoding = $src$$reg;
2698 encode_Copy( cbuf, dst_encoding , src_encoding );
2699 // mov $dst.hi,$src
2700 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding );
2701 // sar $dst.hi,31
2702 emit_opcode( cbuf, 0xC1 );
2703 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) );
2704 emit_d8(cbuf, 0x1F );
2705 %}
2706
2707 enc_class convert_long_double( eRegL src ) %{
2708 // push $src.hi
2709 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2710 // push $src.lo
2711 emit_opcode(cbuf, 0x50+$src$$reg );
2712 // fild 64-bits at [SP]
2713 emit_opcode(cbuf,0xdf);
2714 emit_d8(cbuf, 0x6C);
2715 emit_d8(cbuf, 0x24);
2716 emit_d8(cbuf, 0x00);
2717 // pop stack
2718 emit_opcode(cbuf, 0x83); // add SP, #8
2719 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2720 emit_d8(cbuf, 0x8);
2721 %}
2722
2723 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{
2724 // IMUL EDX:EAX,$src1
2725 emit_opcode( cbuf, 0xF7 );
2726 emit_rm( cbuf, 0x3, 0x5, $src1$$reg );
2727 // SAR EDX,$cnt-32
2728 int shift_count = ((int)$cnt$$constant) - 32;
2729 if (shift_count > 0) {
2730 emit_opcode(cbuf, 0xC1);
2731 emit_rm(cbuf, 0x3, 7, $dst$$reg );
2732 emit_d8(cbuf, shift_count);
2733 }
2734 %}
2735
2736 // this version doesn't have add sp, 8
2737 enc_class convert_long_double2( eRegL src ) %{
2738 // push $src.hi
2739 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2740 // push $src.lo
2741 emit_opcode(cbuf, 0x50+$src$$reg );
2742 // fild 64-bits at [SP]
2743 emit_opcode(cbuf,0xdf);
2744 emit_d8(cbuf, 0x6C);
2745 emit_d8(cbuf, 0x24);
2746 emit_d8(cbuf, 0x00);
2747 %}
2748
2749 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{
2750 // Basic idea: long = (long)int * (long)int
2751 // IMUL EDX:EAX, src
2752 emit_opcode( cbuf, 0xF7 );
2753 emit_rm( cbuf, 0x3, 0x5, $src$$reg);
2754 %}
2755
2756 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{
2757 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
2758 // MUL EDX:EAX, src
2759 emit_opcode( cbuf, 0xF7 );
2760 emit_rm( cbuf, 0x3, 0x4, $src$$reg);
2761 %}
2762
2763 enc_class long_multiply( eADXRegL dst, eRegL src, rRegI tmp ) %{
2764 // Basic idea: lo(result) = lo(x_lo * y_lo)
2765 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
2766 // MOV $tmp,$src.lo
2767 encode_Copy( cbuf, $tmp$$reg, $src$$reg );
2768 // IMUL $tmp,EDX
2769 emit_opcode( cbuf, 0x0F );
2770 emit_opcode( cbuf, 0xAF );
2771 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2772 // MOV EDX,$src.hi
2773 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) );
2774 // IMUL EDX,EAX
2775 emit_opcode( cbuf, 0x0F );
2776 emit_opcode( cbuf, 0xAF );
2777 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2778 // ADD $tmp,EDX
2779 emit_opcode( cbuf, 0x03 );
2780 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2781 // MUL EDX:EAX,$src.lo
2782 emit_opcode( cbuf, 0xF7 );
2783 emit_rm( cbuf, 0x3, 0x4, $src$$reg );
2784 // ADD EDX,ESI
2785 emit_opcode( cbuf, 0x03 );
2786 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg );
2787 %}
2788
2789 enc_class long_multiply_con( eADXRegL dst, immL_127 src, rRegI tmp ) %{
2790 // Basic idea: lo(result) = lo(src * y_lo)
2791 // hi(result) = hi(src * y_lo) + lo(src * y_hi)
2792 // IMUL $tmp,EDX,$src
2793 emit_opcode( cbuf, 0x6B );
2794 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2795 emit_d8( cbuf, (int)$src$$constant );
2796 // MOV EDX,$src
2797 emit_opcode(cbuf, 0xB8 + EDX_enc);
2798 emit_d32( cbuf, (int)$src$$constant );
2799 // MUL EDX:EAX,EDX
2800 emit_opcode( cbuf, 0xF7 );
2801 emit_rm( cbuf, 0x3, 0x4, EDX_enc );
2802 // ADD EDX,ESI
2803 emit_opcode( cbuf, 0x03 );
2804 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg );
2805 %}
2806
2807 enc_class long_div( eRegL src1, eRegL src2 ) %{
2808 // PUSH src1.hi
2809 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
2810 // PUSH src1.lo
2811 emit_opcode(cbuf, 0x50+$src1$$reg );
2812 // PUSH src2.hi
2813 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
2814 // PUSH src2.lo
2815 emit_opcode(cbuf, 0x50+$src2$$reg );
2816 // CALL directly to the runtime
2817 cbuf.set_insts_mark();
2818 emit_opcode(cbuf,0xE8); // Call into runtime
2819 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2820 // Restore stack
2821 emit_opcode(cbuf, 0x83); // add SP, #framesize
2822 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2823 emit_d8(cbuf, 4*4);
2824 %}
2825
2826 enc_class long_mod( eRegL src1, eRegL src2 ) %{
2827 // PUSH src1.hi
2828 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
2829 // PUSH src1.lo
2830 emit_opcode(cbuf, 0x50+$src1$$reg );
2831 // PUSH src2.hi
2832 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
2833 // PUSH src2.lo
2834 emit_opcode(cbuf, 0x50+$src2$$reg );
2835 // CALL directly to the runtime
2836 cbuf.set_insts_mark();
2837 emit_opcode(cbuf,0xE8); // Call into runtime
2838 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2839 // Restore stack
2840 emit_opcode(cbuf, 0x83); // add SP, #framesize
2841 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2842 emit_d8(cbuf, 4*4);
2843 %}
2844
2845 enc_class long_cmp_flags0( eRegL src, rRegI tmp ) %{
2846 // MOV $tmp,$src.lo
2847 emit_opcode(cbuf, 0x8B);
2848 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
2849 // OR $tmp,$src.hi
2850 emit_opcode(cbuf, 0x0B);
2851 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
2852 %}
2853
2854 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{
2855 // CMP $src1.lo,$src2.lo
2856 emit_opcode( cbuf, 0x3B );
2857 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2858 // JNE,s skip
2859 emit_cc(cbuf, 0x70, 0x5);
2860 emit_d8(cbuf,2);
2861 // CMP $src1.hi,$src2.hi
2862 emit_opcode( cbuf, 0x3B );
2863 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2864 %}
2865
2866 enc_class long_cmp_flags2( eRegL src1, eRegL src2, rRegI tmp ) %{
2867 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits
2868 emit_opcode( cbuf, 0x3B );
2869 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2870 // MOV $tmp,$src1.hi
2871 emit_opcode( cbuf, 0x8B );
2872 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) );
2873 // SBB $tmp,$src2.hi\t! Compute flags for long compare
2874 emit_opcode( cbuf, 0x1B );
2875 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) );
2876 %}
2877
2878 enc_class long_cmp_flags3( eRegL src, rRegI tmp ) %{
2879 // XOR $tmp,$tmp
2880 emit_opcode(cbuf,0x33); // XOR
2881 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg);
2882 // CMP $tmp,$src.lo
2883 emit_opcode( cbuf, 0x3B );
2884 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg );
2885 // SBB $tmp,$src.hi
2886 emit_opcode( cbuf, 0x1B );
2887 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) );
2888 %}
2889
2890 // Sniff, sniff... smells like Gnu Superoptimizer
2891 enc_class neg_long( eRegL dst ) %{
2892 emit_opcode(cbuf,0xF7); // NEG hi
2893 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
2894 emit_opcode(cbuf,0xF7); // NEG lo
2895 emit_rm (cbuf,0x3, 0x3, $dst$$reg );
2896 emit_opcode(cbuf,0x83); // SBB hi,0
2897 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
2898 emit_d8 (cbuf,0 );
2899 %}
2900
2901 enc_class enc_pop_rdx() %{
2902 emit_opcode(cbuf,0x5A);
2903 %}
2904
2905 enc_class enc_rethrow() %{
2906 cbuf.set_insts_mark();
2907 emit_opcode(cbuf, 0xE9); // jmp entry
2908 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.insts_end())-4,
2909 runtime_call_Relocation::spec(), RELOC_IMM32 );
2910 %}
2911
2912
2913 // Convert a double to an int. Java semantics require we do complex
2914 // manglelations in the corner cases. So we set the rounding mode to
2915 // 'zero', store the darned double down as an int, and reset the
2916 // rounding mode to 'nearest'. The hardware throws an exception which
2917 // patches up the correct value directly to the stack.
2918 enc_class DPR2I_encoding( regDPR src ) %{
2919 // Flip to round-to-zero mode. We attempted to allow invalid-op
2920 // exceptions here, so that a NAN or other corner-case value will
2921 // thrown an exception (but normal values get converted at full speed).
2922 // However, I2C adapters and other float-stack manglers leave pending
2923 // invalid-op exceptions hanging. We would have to clear them before
2924 // enabling them and that is more expensive than just testing for the
2925 // invalid value Intel stores down in the corner cases.
2926 emit_opcode(cbuf,0xD9); // FLDCW trunc
2927 emit_opcode(cbuf,0x2D);
2928 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
2929 // Allocate a word
2930 emit_opcode(cbuf,0x83); // SUB ESP,4
2931 emit_opcode(cbuf,0xEC);
2932 emit_d8(cbuf,0x04);
2933 // Encoding assumes a double has been pushed into FPR0.
2934 // Store down the double as an int, popping the FPU stack
2935 emit_opcode(cbuf,0xDB); // FISTP [ESP]
2936 emit_opcode(cbuf,0x1C);
2937 emit_d8(cbuf,0x24);
2938 // Restore the rounding mode; mask the exception
2939 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
2940 emit_opcode(cbuf,0x2D);
2941 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
2942 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
2943 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
2944
2945 // Load the converted int; adjust CPU stack
2946 emit_opcode(cbuf,0x58); // POP EAX
2947 emit_opcode(cbuf,0x3D); // CMP EAX,imm
2948 emit_d32 (cbuf,0x80000000); // 0x80000000
2949 emit_opcode(cbuf,0x75); // JNE around_slow_call
2950 emit_d8 (cbuf,0x07); // Size of slow_call
2951 // Push src onto stack slow-path
2952 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
2953 emit_d8 (cbuf,0xC0-1+$src$$reg );
2954 // CALL directly to the runtime
2955 cbuf.set_insts_mark();
2956 emit_opcode(cbuf,0xE8); // Call into runtime
2957 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2958 // Carry on here...
2959 %}
2960
2961 enc_class DPR2L_encoding( regDPR src ) %{
2962 emit_opcode(cbuf,0xD9); // FLDCW trunc
2963 emit_opcode(cbuf,0x2D);
2964 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
2965 // Allocate a word
2966 emit_opcode(cbuf,0x83); // SUB ESP,8
2967 emit_opcode(cbuf,0xEC);
2968 emit_d8(cbuf,0x08);
2969 // Encoding assumes a double has been pushed into FPR0.
2970 // Store down the double as a long, popping the FPU stack
2971 emit_opcode(cbuf,0xDF); // FISTP [ESP]
2972 emit_opcode(cbuf,0x3C);
2973 emit_d8(cbuf,0x24);
2974 // Restore the rounding mode; mask the exception
2975 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
2976 emit_opcode(cbuf,0x2D);
2977 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
2978 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
2979 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
2980
2981 // Load the converted int; adjust CPU stack
2982 emit_opcode(cbuf,0x58); // POP EAX
2983 emit_opcode(cbuf,0x5A); // POP EDX
2984 emit_opcode(cbuf,0x81); // CMP EDX,imm
2985 emit_d8 (cbuf,0xFA); // rdx
2986 emit_d32 (cbuf,0x80000000); // 0x80000000
2987 emit_opcode(cbuf,0x75); // JNE around_slow_call
2988 emit_d8 (cbuf,0x07+4); // Size of slow_call
2989 emit_opcode(cbuf,0x85); // TEST EAX,EAX
2990 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
2991 emit_opcode(cbuf,0x75); // JNE around_slow_call
2992 emit_d8 (cbuf,0x07); // Size of slow_call
2993 // Push src onto stack slow-path
2994 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
2995 emit_d8 (cbuf,0xC0-1+$src$$reg );
2996 // CALL directly to the runtime
2997 cbuf.set_insts_mark();
2998 emit_opcode(cbuf,0xE8); // Call into runtime
2999 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3000 // Carry on here...
3001 %}
3002
3003 enc_class FMul_ST_reg( eRegFPR src1 ) %{
3004 // Operand was loaded from memory into fp ST (stack top)
3005 // FMUL ST,$src /* D8 C8+i */
3006 emit_opcode(cbuf, 0xD8);
3007 emit_opcode(cbuf, 0xC8 + $src1$$reg);
3008 %}
3009
3010 enc_class FAdd_ST_reg( eRegFPR src2 ) %{
3011 // FADDP ST,src2 /* D8 C0+i */
3012 emit_opcode(cbuf, 0xD8);
3013 emit_opcode(cbuf, 0xC0 + $src2$$reg);
3014 //could use FADDP src2,fpST /* DE C0+i */
3015 %}
3016
3017 enc_class FAddP_reg_ST( eRegFPR src2 ) %{
3018 // FADDP src2,ST /* DE C0+i */
3019 emit_opcode(cbuf, 0xDE);
3020 emit_opcode(cbuf, 0xC0 + $src2$$reg);
3021 %}
3022
3023 enc_class subFPR_divFPR_encode( eRegFPR src1, eRegFPR src2) %{
3024 // Operand has been loaded into fp ST (stack top)
3025 // FSUB ST,$src1
3026 emit_opcode(cbuf, 0xD8);
3027 emit_opcode(cbuf, 0xE0 + $src1$$reg);
3028
3029 // FDIV
3030 emit_opcode(cbuf, 0xD8);
3031 emit_opcode(cbuf, 0xF0 + $src2$$reg);
3032 %}
3033
3034 enc_class MulFAddF (eRegFPR src1, eRegFPR src2) %{
3035 // Operand was loaded from memory into fp ST (stack top)
3036 // FADD ST,$src /* D8 C0+i */
3037 emit_opcode(cbuf, 0xD8);
3038 emit_opcode(cbuf, 0xC0 + $src1$$reg);
3039
3040 // FMUL ST,src2 /* D8 C*+i */
3041 emit_opcode(cbuf, 0xD8);
3042 emit_opcode(cbuf, 0xC8 + $src2$$reg);
3043 %}
3044
3045
3046 enc_class MulFAddFreverse (eRegFPR src1, eRegFPR src2) %{
3047 // Operand was loaded from memory into fp ST (stack top)
3048 // FADD ST,$src /* D8 C0+i */
3049 emit_opcode(cbuf, 0xD8);
3050 emit_opcode(cbuf, 0xC0 + $src1$$reg);
3051
3052 // FMULP src2,ST /* DE C8+i */
3053 emit_opcode(cbuf, 0xDE);
3054 emit_opcode(cbuf, 0xC8 + $src2$$reg);
3055 %}
3056
3057 // Atomically load the volatile long
3058 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{
3059 emit_opcode(cbuf,0xDF);
3060 int rm_byte_opcode = 0x05;
3061 int base = $mem$$base;
3062 int index = $mem$$index;
3063 int scale = $mem$$scale;
3064 int displace = $mem$$disp;
3065 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
3066 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
3067 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp );
3068 %}
3069
3070 // Volatile Store Long. Must be atomic, so move it into
3071 // the FP TOS and then do a 64-bit FIST. Has to probe the
3072 // target address before the store (for null-ptr checks)
3073 // so the memory operand is used twice in the encoding.
3074 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{
3075 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp );
3076 cbuf.set_insts_mark(); // Mark start of FIST in case $mem has an oop
3077 emit_opcode(cbuf,0xDF);
3078 int rm_byte_opcode = 0x07;
3079 int base = $mem$$base;
3080 int index = $mem$$index;
3081 int scale = $mem$$scale;
3082 int displace = $mem$$disp;
3083 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
3084 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
3085 %}
3086
3087 // Safepoint Poll. This polls the safepoint page, and causes an
3088 // exception if it is not readable. Unfortunately, it kills the condition code
3089 // in the process
3090 // We current use TESTL [spp],EDI
3091 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0
3092
3093 enc_class Safepoint_Poll() %{
3094 cbuf.relocate(cbuf.insts_mark(), relocInfo::poll_type, 0);
3095 emit_opcode(cbuf,0x85);
3096 emit_rm (cbuf, 0x0, 0x7, 0x5);
3097 emit_d32(cbuf, (intptr_t)os::get_polling_page());
3098 %}
3099 %}
3100
3101
3102 //----------FRAME--------------------------------------------------------------
3103 // Definition of frame structure and management information.
3104 //
3105 // S T A C K L A Y O U T Allocators stack-slot number
3106 // | (to get allocators register number
3107 // G Owned by | | v add OptoReg::stack0())
3108 // r CALLER | |
3109 // o | +--------+ pad to even-align allocators stack-slot
3110 // w V | pad0 | numbers; owned by CALLER
3111 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3112 // h ^ | in | 5
3113 // | | args | 4 Holes in incoming args owned by SELF
3114 // | | | | 3
3115 // | | +--------+
3116 // V | | old out| Empty on Intel, window on Sparc
3117 // | old |preserve| Must be even aligned.
3118 // | SP-+--------+----> Matcher::_old_SP, even aligned
3119 // | | in | 3 area for Intel ret address
3120 // Owned by |preserve| Empty on Sparc.
3121 // SELF +--------+
3122 // | | pad2 | 2 pad to align old SP
3123 // | +--------+ 1
3124 // | | locks | 0
3125 // | +--------+----> OptoReg::stack0(), even aligned
3126 // | | pad1 | 11 pad to align new SP
3127 // | +--------+
3128 // | | | 10
3129 // | | spills | 9 spills
3130 // V | | 8 (pad0 slot for callee)
3131 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3132 // ^ | out | 7
3133 // | | args | 6 Holes in outgoing args owned by CALLEE
3134 // Owned by +--------+
3135 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3136 // | new |preserve| Must be even-aligned.
3137 // | SP-+--------+----> Matcher::_new_SP, even aligned
3138 // | | |
3139 //
3140 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3141 // known from SELF's arguments and the Java calling convention.
3142 // Region 6-7 is determined per call site.
3143 // Note 2: If the calling convention leaves holes in the incoming argument
3144 // area, those holes are owned by SELF. Holes in the outgoing area
3145 // are owned by the CALLEE. Holes should not be nessecary in the
3146 // incoming area, as the Java calling convention is completely under
3147 // the control of the AD file. Doubles can be sorted and packed to
3148 // avoid holes. Holes in the outgoing arguments may be nessecary for
3149 // varargs C calling conventions.
3150 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3151 // even aligned with pad0 as needed.
3152 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3153 // region 6-11 is even aligned; it may be padded out more so that
3154 // the region from SP to FP meets the minimum stack alignment.
3155
3156 frame %{
3157 // What direction does stack grow in (assumed to be same for C & Java)
3158 stack_direction(TOWARDS_LOW);
3159
3160 // These three registers define part of the calling convention
3161 // between compiled code and the interpreter.
3162 inline_cache_reg(EAX); // Inline Cache Register
3163 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter
3164
3165 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3166 cisc_spilling_operand_name(indOffset32);
3167
3168 // Number of stack slots consumed by locking an object
3169 sync_stack_slots(1);
3170
3171 // Compiled code's Frame Pointer
3172 frame_pointer(ESP);
3173 // Interpreter stores its frame pointer in a register which is
3174 // stored to the stack by I2CAdaptors.
3175 // I2CAdaptors convert from interpreted java to compiled java.
3176 interpreter_frame_pointer(EBP);
3177
3178 // Stack alignment requirement
3179 // Alignment size in bytes (128-bit -> 16 bytes)
3180 stack_alignment(StackAlignmentInBytes);
3181
3182 // Number of stack slots between incoming argument block and the start of
3183 // a new frame. The PROLOG must add this many slots to the stack. The
3184 // EPILOG must remove this many slots. Intel needs one slot for
3185 // return address and one for rbp, (must save rbp)
3186 in_preserve_stack_slots(2+VerifyStackAtCalls);
3187
3188 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3189 // for calls to C. Supports the var-args backing area for register parms.
3190 varargs_C_out_slots_killed(0);
3191
3192 // The after-PROLOG location of the return address. Location of
3193 // return address specifies a type (REG or STACK) and a number
3194 // representing the register number (i.e. - use a register name) or
3195 // stack slot.
3196 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
3197 // Otherwise, it is above the locks and verification slot and alignment word
3198 return_addr(STACK - 1 +
3199 round_to((Compile::current()->in_preserve_stack_slots() +
3200 Compile::current()->fixed_slots()),
3201 stack_alignment_in_slots()));
3202
3203 // Body of function which returns an integer array locating
3204 // arguments either in registers or in stack slots. Passed an array
3205 // of ideal registers called "sig" and a "length" count. Stack-slot
3206 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3207 // arguments for a CALLEE. Incoming stack arguments are
3208 // automatically biased by the preserve_stack_slots field above.
3209 calling_convention %{
3210 // No difference between ingoing/outgoing just pass false
3211 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3212 %}
3213
3214
3215 // Body of function which returns an integer array locating
3216 // arguments either in registers or in stack slots. Passed an array
3217 // of ideal registers called "sig" and a "length" count. Stack-slot
3218 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3219 // arguments for a CALLEE. Incoming stack arguments are
3220 // automatically biased by the preserve_stack_slots field above.
3221 c_calling_convention %{
3222 // This is obviously always outgoing
3223 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
3224 %}
3225
3226 // Location of C & interpreter return values
3227 c_return_value %{
3228 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3229 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
3230 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3231
3232 // in SSE2+ mode we want to keep the FPU stack clean so pretend
3233 // that C functions return float and double results in XMM0.
3234 if( ideal_reg == Op_RegD && UseSSE>=2 )
3235 return OptoRegPair(XMM0b_num,XMM0_num);
3236 if( ideal_reg == Op_RegF && UseSSE>=2 )
3237 return OptoRegPair(OptoReg::Bad,XMM0_num);
3238
3239 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3240 %}
3241
3242 // Location of return values
3243 return_value %{
3244 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3245 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
3246 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3247 if( ideal_reg == Op_RegD && UseSSE>=2 )
3248 return OptoRegPair(XMM0b_num,XMM0_num);
3249 if( ideal_reg == Op_RegF && UseSSE>=1 )
3250 return OptoRegPair(OptoReg::Bad,XMM0_num);
3251 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3252 %}
3253
3254 %}
3255
3256 //----------ATTRIBUTES---------------------------------------------------------
3257 //----------Operand Attributes-------------------------------------------------
3258 op_attrib op_cost(0); // Required cost attribute
3259
3260 //----------Instruction Attributes---------------------------------------------
3261 ins_attrib ins_cost(100); // Required cost attribute
3262 ins_attrib ins_size(8); // Required size attribute (in bits)
3263 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3264 // non-matching short branch variant of some
3265 // long branch?
3266 ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2)
3267 // specifies the alignment that some part of the instruction (not
3268 // necessarily the start) requires. If > 1, a compute_padding()
3269 // function must be provided for the instruction
3270
3271 //----------OPERANDS-----------------------------------------------------------
3272 // Operand definitions must precede instruction definitions for correct parsing
3273 // in the ADLC because operands constitute user defined types which are used in
3274 // instruction definitions.
3275
3276 //----------Simple Operands----------------------------------------------------
3277 // Immediate Operands
3278 // Integer Immediate
3279 operand immI() %{
3280 match(ConI);
3281
3282 op_cost(10);
3283 format %{ %}
3284 interface(CONST_INTER);
3285 %}
3286
3287 // Constant for test vs zero
3288 operand immI0() %{
3289 predicate(n->get_int() == 0);
3290 match(ConI);
3291
3292 op_cost(0);
3293 format %{ %}
3294 interface(CONST_INTER);
3295 %}
3296
3297 // Constant for increment
3298 operand immI1() %{
3299 predicate(n->get_int() == 1);
3300 match(ConI);
3301
3302 op_cost(0);
3303 format %{ %}
3304 interface(CONST_INTER);
3305 %}
3306
3307 // Constant for decrement
3308 operand immI_M1() %{
3309 predicate(n->get_int() == -1);
3310 match(ConI);
3311
3312 op_cost(0);
3313 format %{ %}
3314 interface(CONST_INTER);
3315 %}
3316
3317 // Valid scale values for addressing modes
3318 operand immI2() %{
3319 predicate(0 <= n->get_int() && (n->get_int() <= 3));
3320 match(ConI);
3321
3322 format %{ %}
3323 interface(CONST_INTER);
3324 %}
3325
3326 operand immI8() %{
3327 predicate((-128 <= n->get_int()) && (n->get_int() <= 127));
3328 match(ConI);
3329
3330 op_cost(5);
3331 format %{ %}
3332 interface(CONST_INTER);
3333 %}
3334
3335 operand immI16() %{
3336 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
3337 match(ConI);
3338
3339 op_cost(10);
3340 format %{ %}
3341 interface(CONST_INTER);
3342 %}
3343
3344 // Int Immediate non-negative
3345 operand immU31()
3346 %{
3347 predicate(n->get_int() >= 0);
3348 match(ConI);
3349
3350 op_cost(0);
3351 format %{ %}
3352 interface(CONST_INTER);
3353 %}
3354
3355 // Constant for long shifts
3356 operand immI_32() %{
3357 predicate( n->get_int() == 32 );
3358 match(ConI);
3359
3360 op_cost(0);
3361 format %{ %}
3362 interface(CONST_INTER);
3363 %}
3364
3365 operand immI_1_31() %{
3366 predicate( n->get_int() >= 1 && n->get_int() <= 31 );
3367 match(ConI);
3368
3369 op_cost(0);
3370 format %{ %}
3371 interface(CONST_INTER);
3372 %}
3373
3374 operand immI_32_63() %{
3375 predicate( n->get_int() >= 32 && n->get_int() <= 63 );
3376 match(ConI);
3377 op_cost(0);
3378
3379 format %{ %}
3380 interface(CONST_INTER);
3381 %}
3382
3383 operand immI_1() %{
3384 predicate( n->get_int() == 1 );
3385 match(ConI);
3386
3387 op_cost(0);
3388 format %{ %}
3389 interface(CONST_INTER);
3390 %}
3391
3392 operand immI_2() %{
3393 predicate( n->get_int() == 2 );
3394 match(ConI);
3395
3396 op_cost(0);
3397 format %{ %}
3398 interface(CONST_INTER);
3399 %}
3400
3401 operand immI_3() %{
3402 predicate( n->get_int() == 3 );
3403 match(ConI);
3404
3405 op_cost(0);
3406 format %{ %}
3407 interface(CONST_INTER);
3408 %}
3409
3410 // Pointer Immediate
3411 operand immP() %{
3412 match(ConP);
3413
3414 op_cost(10);
3415 format %{ %}
3416 interface(CONST_INTER);
3417 %}
3418
3419 // NULL Pointer Immediate
3420 operand immP0() %{
3421 predicate( n->get_ptr() == 0 );
3422 match(ConP);
3423 op_cost(0);
3424
3425 format %{ %}
3426 interface(CONST_INTER);
3427 %}
3428
3429 // Long Immediate
3430 operand immL() %{
3431 match(ConL);
3432
3433 op_cost(20);
3434 format %{ %}
3435 interface(CONST_INTER);
3436 %}
3437
3438 // Long Immediate zero
3439 operand immL0() %{
3440 predicate( n->get_long() == 0L );
3441 match(ConL);
3442 op_cost(0);
3443
3444 format %{ %}
3445 interface(CONST_INTER);
3446 %}
3447
3448 // Long Immediate zero
3449 operand immL_M1() %{
3450 predicate( n->get_long() == -1L );
3451 match(ConL);
3452 op_cost(0);
3453
3454 format %{ %}
3455 interface(CONST_INTER);
3456 %}
3457
3458 // Long immediate from 0 to 127.
3459 // Used for a shorter form of long mul by 10.
3460 operand immL_127() %{
3461 predicate((0 <= n->get_long()) && (n->get_long() <= 127));
3462 match(ConL);
3463 op_cost(0);
3464
3465 format %{ %}
3466 interface(CONST_INTER);
3467 %}
3468
3469 // Long Immediate: low 32-bit mask
3470 operand immL_32bits() %{
3471 predicate(n->get_long() == 0xFFFFFFFFL);
3472 match(ConL);
3473 op_cost(0);
3474
3475 format %{ %}
3476 interface(CONST_INTER);
3477 %}
3478
3479 // Long Immediate: low 32-bit mask
3480 operand immL32() %{
3481 predicate(n->get_long() == (int)(n->get_long()));
3482 match(ConL);
3483 op_cost(20);
3484
3485 format %{ %}
3486 interface(CONST_INTER);
3487 %}
3488
3489 //Double Immediate zero
3490 operand immDPR0() %{
3491 // Do additional (and counter-intuitive) test against NaN to work around VC++
3492 // bug that generates code such that NaNs compare equal to 0.0
3493 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) );
3494 match(ConD);
3495
3496 op_cost(5);
3497 format %{ %}
3498 interface(CONST_INTER);
3499 %}
3500
3501 // Double Immediate one
3502 operand immDPR1() %{
3503 predicate( UseSSE<=1 && n->getd() == 1.0 );
3504 match(ConD);
3505
3506 op_cost(5);
3507 format %{ %}
3508 interface(CONST_INTER);
3509 %}
3510
3511 // Double Immediate
3512 operand immDPR() %{
3513 predicate(UseSSE<=1);
3514 match(ConD);
3515
3516 op_cost(5);
3517 format %{ %}
3518 interface(CONST_INTER);
3519 %}
3520
3521 operand immD() %{
3522 predicate(UseSSE>=2);
3523 match(ConD);
3524
3525 op_cost(5);
3526 format %{ %}
3527 interface(CONST_INTER);
3528 %}
3529
3530 // Double Immediate zero
3531 operand immD0() %{
3532 // Do additional (and counter-intuitive) test against NaN to work around VC++
3533 // bug that generates code such that NaNs compare equal to 0.0 AND do not
3534 // compare equal to -0.0.
3535 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 );
3536 match(ConD);
3537
3538 format %{ %}
3539 interface(CONST_INTER);
3540 %}
3541
3542 // Float Immediate zero
3543 operand immFPR0() %{
3544 predicate(UseSSE == 0 && n->getf() == 0.0F);
3545 match(ConF);
3546
3547 op_cost(5);
3548 format %{ %}
3549 interface(CONST_INTER);
3550 %}
3551
3552 // Float Immediate one
3553 operand immFPR1() %{
3554 predicate(UseSSE == 0 && n->getf() == 1.0F);
3555 match(ConF);
3556
3557 op_cost(5);
3558 format %{ %}
3559 interface(CONST_INTER);
3560 %}
3561
3562 // Float Immediate
3563 operand immFPR() %{
3564 predicate( UseSSE == 0 );
3565 match(ConF);
3566
3567 op_cost(5);
3568 format %{ %}
3569 interface(CONST_INTER);
3570 %}
3571
3572 // Float Immediate
3573 operand immF() %{
3574 predicate(UseSSE >= 1);
3575 match(ConF);
3576
3577 op_cost(5);
3578 format %{ %}
3579 interface(CONST_INTER);
3580 %}
3581
3582 // Float Immediate zero. Zero and not -0.0
3583 operand immF0() %{
3584 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 );
3585 match(ConF);
3586
3587 op_cost(5);
3588 format %{ %}
3589 interface(CONST_INTER);
3590 %}
3591
3592 // Immediates for special shifts (sign extend)
3593
3594 // Constants for increment
3595 operand immI_16() %{
3596 predicate( n->get_int() == 16 );
3597 match(ConI);
3598
3599 format %{ %}
3600 interface(CONST_INTER);
3601 %}
3602
3603 operand immI_24() %{
3604 predicate( n->get_int() == 24 );
3605 match(ConI);
3606
3607 format %{ %}
3608 interface(CONST_INTER);
3609 %}
3610
3611 // Constant for byte-wide masking
3612 operand immI_255() %{
3613 predicate( n->get_int() == 255 );
3614 match(ConI);
3615
3616 format %{ %}
3617 interface(CONST_INTER);
3618 %}
3619
3620 // Constant for short-wide masking
3621 operand immI_65535() %{
3622 predicate(n->get_int() == 65535);
3623 match(ConI);
3624
3625 format %{ %}
3626 interface(CONST_INTER);
3627 %}
3628
3629 // Register Operands
3630 // Integer Register
3631 operand rRegI() %{
3632 constraint(ALLOC_IN_RC(int_reg));
3633 match(RegI);
3634 match(xRegI);
3635 match(eAXRegI);
3636 match(eBXRegI);
3637 match(eCXRegI);
3638 match(eDXRegI);
3639 match(eDIRegI);
3640 match(eSIRegI);
3641
3642 format %{ %}
3643 interface(REG_INTER);
3644 %}
3645
3646 // Subset of Integer Register
3647 operand xRegI(rRegI reg) %{
3648 constraint(ALLOC_IN_RC(int_x_reg));
3649 match(reg);
3650 match(eAXRegI);
3651 match(eBXRegI);
3652 match(eCXRegI);
3653 match(eDXRegI);
3654
3655 format %{ %}
3656 interface(REG_INTER);
3657 %}
3658
3659 // Special Registers
3660 operand eAXRegI(xRegI reg) %{
3661 constraint(ALLOC_IN_RC(eax_reg));
3662 match(reg);
3663 match(rRegI);
3664
3665 format %{ "EAX" %}
3666 interface(REG_INTER);
3667 %}
3668
3669 // Special Registers
3670 operand eBXRegI(xRegI reg) %{
3671 constraint(ALLOC_IN_RC(ebx_reg));
3672 match(reg);
3673 match(rRegI);
3674
3675 format %{ "EBX" %}
3676 interface(REG_INTER);
3677 %}
3678
3679 operand eCXRegI(xRegI reg) %{
3680 constraint(ALLOC_IN_RC(ecx_reg));
3681 match(reg);
3682 match(rRegI);
3683
3684 format %{ "ECX" %}
3685 interface(REG_INTER);
3686 %}
3687
3688 operand eDXRegI(xRegI reg) %{
3689 constraint(ALLOC_IN_RC(edx_reg));
3690 match(reg);
3691 match(rRegI);
3692
3693 format %{ "EDX" %}
3694 interface(REG_INTER);
3695 %}
3696
3697 operand eDIRegI(xRegI reg) %{
3698 constraint(ALLOC_IN_RC(edi_reg));
3699 match(reg);
3700 match(rRegI);
3701
3702 format %{ "EDI" %}
3703 interface(REG_INTER);
3704 %}
3705
3706 operand naxRegI() %{
3707 constraint(ALLOC_IN_RC(nax_reg));
3708 match(RegI);
3709 match(eCXRegI);
3710 match(eDXRegI);
3711 match(eSIRegI);
3712 match(eDIRegI);
3713
3714 format %{ %}
3715 interface(REG_INTER);
3716 %}
3717
3718 operand nadxRegI() %{
3719 constraint(ALLOC_IN_RC(nadx_reg));
3720 match(RegI);
3721 match(eBXRegI);
3722 match(eCXRegI);
3723 match(eSIRegI);
3724 match(eDIRegI);
3725
3726 format %{ %}
3727 interface(REG_INTER);
3728 %}
3729
3730 operand ncxRegI() %{
3731 constraint(ALLOC_IN_RC(ncx_reg));
3732 match(RegI);
3733 match(eAXRegI);
3734 match(eDXRegI);
3735 match(eSIRegI);
3736 match(eDIRegI);
3737
3738 format %{ %}
3739 interface(REG_INTER);
3740 %}
3741
3742 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg
3743 // //
3744 operand eSIRegI(xRegI reg) %{
3745 constraint(ALLOC_IN_RC(esi_reg));
3746 match(reg);
3747 match(rRegI);
3748
3749 format %{ "ESI" %}
3750 interface(REG_INTER);
3751 %}
3752
3753 // Pointer Register
3754 operand anyRegP() %{
3755 constraint(ALLOC_IN_RC(any_reg));
3756 match(RegP);
3757 match(eAXRegP);
3758 match(eBXRegP);
3759 match(eCXRegP);
3760 match(eDIRegP);
3761 match(eRegP);
3762
3763 format %{ %}
3764 interface(REG_INTER);
3765 %}
3766
3767 operand eRegP() %{
3768 constraint(ALLOC_IN_RC(int_reg));
3769 match(RegP);
3770 match(eAXRegP);
3771 match(eBXRegP);
3772 match(eCXRegP);
3773 match(eDIRegP);
3774
3775 format %{ %}
3776 interface(REG_INTER);
3777 %}
3778
3779 // On windows95, EBP is not safe to use for implicit null tests.
3780 operand eRegP_no_EBP() %{
3781 constraint(ALLOC_IN_RC(int_reg_no_ebp));
3782 match(RegP);
3783 match(eAXRegP);
3784 match(eBXRegP);
3785 match(eCXRegP);
3786 match(eDIRegP);
3787
3788 op_cost(100);
3789 format %{ %}
3790 interface(REG_INTER);
3791 %}
3792
3793 operand naxRegP() %{
3794 constraint(ALLOC_IN_RC(nax_reg));
3795 match(RegP);
3796 match(eBXRegP);
3797 match(eDXRegP);
3798 match(eCXRegP);
3799 match(eSIRegP);
3800 match(eDIRegP);
3801
3802 format %{ %}
3803 interface(REG_INTER);
3804 %}
3805
3806 operand nabxRegP() %{
3807 constraint(ALLOC_IN_RC(nabx_reg));
3808 match(RegP);
3809 match(eCXRegP);
3810 match(eDXRegP);
3811 match(eSIRegP);
3812 match(eDIRegP);
3813
3814 format %{ %}
3815 interface(REG_INTER);
3816 %}
3817
3818 operand pRegP() %{
3819 constraint(ALLOC_IN_RC(p_reg));
3820 match(RegP);
3821 match(eBXRegP);
3822 match(eDXRegP);
3823 match(eSIRegP);
3824 match(eDIRegP);
3825
3826 format %{ %}
3827 interface(REG_INTER);
3828 %}
3829
3830 // Special Registers
3831 // Return a pointer value
3832 operand eAXRegP(eRegP reg) %{
3833 constraint(ALLOC_IN_RC(eax_reg));
3834 match(reg);
3835 format %{ "EAX" %}
3836 interface(REG_INTER);
3837 %}
3838
3839 // Used in AtomicAdd
3840 operand eBXRegP(eRegP reg) %{
3841 constraint(ALLOC_IN_RC(ebx_reg));
3842 match(reg);
3843 format %{ "EBX" %}
3844 interface(REG_INTER);
3845 %}
3846
3847 // Tail-call (interprocedural jump) to interpreter
3848 operand eCXRegP(eRegP reg) %{
3849 constraint(ALLOC_IN_RC(ecx_reg));
3850 match(reg);
3851 format %{ "ECX" %}
3852 interface(REG_INTER);
3853 %}
3854
3855 operand eSIRegP(eRegP reg) %{
3856 constraint(ALLOC_IN_RC(esi_reg));
3857 match(reg);
3858 format %{ "ESI" %}
3859 interface(REG_INTER);
3860 %}
3861
3862 // Used in rep stosw
3863 operand eDIRegP(eRegP reg) %{
3864 constraint(ALLOC_IN_RC(edi_reg));
3865 match(reg);
3866 format %{ "EDI" %}
3867 interface(REG_INTER);
3868 %}
3869
3870 operand eRegL() %{
3871 constraint(ALLOC_IN_RC(long_reg));
3872 match(RegL);
3873 match(eADXRegL);
3874
3875 format %{ %}
3876 interface(REG_INTER);
3877 %}
3878
3879 operand eADXRegL( eRegL reg ) %{
3880 constraint(ALLOC_IN_RC(eadx_reg));
3881 match(reg);
3882
3883 format %{ "EDX:EAX" %}
3884 interface(REG_INTER);
3885 %}
3886
3887 operand eBCXRegL( eRegL reg ) %{
3888 constraint(ALLOC_IN_RC(ebcx_reg));
3889 match(reg);
3890
3891 format %{ "EBX:ECX" %}
3892 interface(REG_INTER);
3893 %}
3894
3895 // Special case for integer high multiply
3896 operand eADXRegL_low_only() %{
3897 constraint(ALLOC_IN_RC(eadx_reg));
3898 match(RegL);
3899
3900 format %{ "EAX" %}
3901 interface(REG_INTER);
3902 %}
3903
3904 // Flags register, used as output of compare instructions
3905 operand eFlagsReg() %{
3906 constraint(ALLOC_IN_RC(int_flags));
3907 match(RegFlags);
3908
3909 format %{ "EFLAGS" %}
3910 interface(REG_INTER);
3911 %}
3912
3913 // Flags register, used as output of FLOATING POINT compare instructions
3914 operand eFlagsRegU() %{
3915 constraint(ALLOC_IN_RC(int_flags));
3916 match(RegFlags);
3917
3918 format %{ "EFLAGS_U" %}
3919 interface(REG_INTER);
3920 %}
3921
3922 operand eFlagsRegUCF() %{
3923 constraint(ALLOC_IN_RC(int_flags));
3924 match(RegFlags);
3925 predicate(false);
3926
3927 format %{ "EFLAGS_U_CF" %}
3928 interface(REG_INTER);
3929 %}
3930
3931 // Condition Code Register used by long compare
3932 operand flagsReg_long_LTGE() %{
3933 constraint(ALLOC_IN_RC(int_flags));
3934 match(RegFlags);
3935 format %{ "FLAGS_LTGE" %}
3936 interface(REG_INTER);
3937 %}
3938 operand flagsReg_long_EQNE() %{
3939 constraint(ALLOC_IN_RC(int_flags));
3940 match(RegFlags);
3941 format %{ "FLAGS_EQNE" %}
3942 interface(REG_INTER);
3943 %}
3944 operand flagsReg_long_LEGT() %{
3945 constraint(ALLOC_IN_RC(int_flags));
3946 match(RegFlags);
3947 format %{ "FLAGS_LEGT" %}
3948 interface(REG_INTER);
3949 %}
3950
3951 // Float register operands
3952 operand regDPR() %{
3953 predicate( UseSSE < 2 );
3954 constraint(ALLOC_IN_RC(fp_dbl_reg));
3955 match(RegD);
3956 match(regDPR1);
3957 match(regDPR2);
3958 format %{ %}
3959 interface(REG_INTER);
3960 %}
3961
3962 operand regDPR1(regDPR reg) %{
3963 predicate( UseSSE < 2 );
3964 constraint(ALLOC_IN_RC(fp_dbl_reg0));
3965 match(reg);
3966 format %{ "FPR1" %}
3967 interface(REG_INTER);
3968 %}
3969
3970 operand regDPR2(regDPR reg) %{
3971 predicate( UseSSE < 2 );
3972 constraint(ALLOC_IN_RC(fp_dbl_reg1));
3973 match(reg);
3974 format %{ "FPR2" %}
3975 interface(REG_INTER);
3976 %}
3977
3978 operand regnotDPR1(regDPR reg) %{
3979 predicate( UseSSE < 2 );
3980 constraint(ALLOC_IN_RC(fp_dbl_notreg0));
3981 match(reg);
3982 format %{ %}
3983 interface(REG_INTER);
3984 %}
3985
3986 // Float register operands
3987 operand regFPR() %{
3988 predicate( UseSSE < 2 );
3989 constraint(ALLOC_IN_RC(fp_flt_reg));
3990 match(RegF);
3991 match(regFPR1);
3992 format %{ %}
3993 interface(REG_INTER);
3994 %}
3995
3996 // Float register operands
3997 operand regFPR1(regFPR reg) %{
3998 predicate( UseSSE < 2 );
3999 constraint(ALLOC_IN_RC(fp_flt_reg0));
4000 match(reg);
4001 format %{ "FPR1" %}
4002 interface(REG_INTER);
4003 %}
4004
4005 // XMM Float register operands
4006 operand regF() %{
4007 predicate( UseSSE>=1 );
4008 constraint(ALLOC_IN_RC(float_reg));
4009 match(RegF);
4010 format %{ %}
4011 interface(REG_INTER);
4012 %}
4013
4014 // XMM Double register operands
4015 operand regD() %{
4016 predicate( UseSSE>=2 );
4017 constraint(ALLOC_IN_RC(double_reg));
4018 match(RegD);
4019 format %{ %}
4020 interface(REG_INTER);
4021 %}
4022
4023
4024 //----------Memory Operands----------------------------------------------------
4025 // Direct Memory Operand
4026 operand direct(immP addr) %{
4027 match(addr);
4028
4029 format %{ "[$addr]" %}
4030 interface(MEMORY_INTER) %{
4031 base(0xFFFFFFFF);
4032 index(0x4);
4033 scale(0x0);
4034 disp($addr);
4035 %}
4036 %}
4037
4038 // Indirect Memory Operand
4039 operand indirect(eRegP reg) %{
4040 constraint(ALLOC_IN_RC(int_reg));
4041 match(reg);
4042
4043 format %{ "[$reg]" %}
4044 interface(MEMORY_INTER) %{
4045 base($reg);
4046 index(0x4);
4047 scale(0x0);
4048 disp(0x0);
4049 %}
4050 %}
4051
4052 // Indirect Memory Plus Short Offset Operand
4053 operand indOffset8(eRegP reg, immI8 off) %{
4054 match(AddP reg off);
4055
4056 format %{ "[$reg + $off]" %}
4057 interface(MEMORY_INTER) %{
4058 base($reg);
4059 index(0x4);
4060 scale(0x0);
4061 disp($off);
4062 %}
4063 %}
4064
4065 // Indirect Memory Plus Long Offset Operand
4066 operand indOffset32(eRegP reg, immI off) %{
4067 match(AddP reg off);
4068
4069 format %{ "[$reg + $off]" %}
4070 interface(MEMORY_INTER) %{
4071 base($reg);
4072 index(0x4);
4073 scale(0x0);
4074 disp($off);
4075 %}
4076 %}
4077
4078 // Indirect Memory Plus Long Offset Operand
4079 operand indOffset32X(rRegI reg, immP off) %{
4080 match(AddP off reg);
4081
4082 format %{ "[$reg + $off]" %}
4083 interface(MEMORY_INTER) %{
4084 base($reg);
4085 index(0x4);
4086 scale(0x0);
4087 disp($off);
4088 %}
4089 %}
4090
4091 // Indirect Memory Plus Index Register Plus Offset Operand
4092 operand indIndexOffset(eRegP reg, rRegI ireg, immI off) %{
4093 match(AddP (AddP reg ireg) off);
4094
4095 op_cost(10);
4096 format %{"[$reg + $off + $ireg]" %}
4097 interface(MEMORY_INTER) %{
4098 base($reg);
4099 index($ireg);
4100 scale(0x0);
4101 disp($off);
4102 %}
4103 %}
4104
4105 // Indirect Memory Plus Index Register Plus Offset Operand
4106 operand indIndex(eRegP reg, rRegI ireg) %{
4107 match(AddP reg ireg);
4108
4109 op_cost(10);
4110 format %{"[$reg + $ireg]" %}
4111 interface(MEMORY_INTER) %{
4112 base($reg);
4113 index($ireg);
4114 scale(0x0);
4115 disp(0x0);
4116 %}
4117 %}
4118
4119 // // -------------------------------------------------------------------------
4120 // // 486 architecture doesn't support "scale * index + offset" with out a base
4121 // // -------------------------------------------------------------------------
4122 // // Scaled Memory Operands
4123 // // Indirect Memory Times Scale Plus Offset Operand
4124 // operand indScaleOffset(immP off, rRegI ireg, immI2 scale) %{
4125 // match(AddP off (LShiftI ireg scale));
4126 //
4127 // op_cost(10);
4128 // format %{"[$off + $ireg << $scale]" %}
4129 // interface(MEMORY_INTER) %{
4130 // base(0x4);
4131 // index($ireg);
4132 // scale($scale);
4133 // disp($off);
4134 // %}
4135 // %}
4136
4137 // Indirect Memory Times Scale Plus Index Register
4138 operand indIndexScale(eRegP reg, rRegI ireg, immI2 scale) %{
4139 match(AddP reg (LShiftI ireg scale));
4140
4141 op_cost(10);
4142 format %{"[$reg + $ireg << $scale]" %}
4143 interface(MEMORY_INTER) %{
4144 base($reg);
4145 index($ireg);
4146 scale($scale);
4147 disp(0x0);
4148 %}
4149 %}
4150
4151 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4152 operand indIndexScaleOffset(eRegP reg, immI off, rRegI ireg, immI2 scale) %{
4153 match(AddP (AddP reg (LShiftI ireg scale)) off);
4154
4155 op_cost(10);
4156 format %{"[$reg + $off + $ireg << $scale]" %}
4157 interface(MEMORY_INTER) %{
4158 base($reg);
4159 index($ireg);
4160 scale($scale);
4161 disp($off);
4162 %}
4163 %}
4164
4165 //----------Load Long Memory Operands------------------------------------------
4166 // The load-long idiom will use it's address expression again after loading
4167 // the first word of the long. If the load-long destination overlaps with
4168 // registers used in the addressing expression, the 2nd half will be loaded
4169 // from a clobbered address. Fix this by requiring that load-long use
4170 // address registers that do not overlap with the load-long target.
4171
4172 // load-long support
4173 operand load_long_RegP() %{
4174 constraint(ALLOC_IN_RC(esi_reg));
4175 match(RegP);
4176 match(eSIRegP);
4177 op_cost(100);
4178 format %{ %}
4179 interface(REG_INTER);
4180 %}
4181
4182 // Indirect Memory Operand Long
4183 operand load_long_indirect(load_long_RegP reg) %{
4184 constraint(ALLOC_IN_RC(esi_reg));
4185 match(reg);
4186
4187 format %{ "[$reg]" %}
4188 interface(MEMORY_INTER) %{
4189 base($reg);
4190 index(0x4);
4191 scale(0x0);
4192 disp(0x0);
4193 %}
4194 %}
4195
4196 // Indirect Memory Plus Long Offset Operand
4197 operand load_long_indOffset32(load_long_RegP reg, immI off) %{
4198 match(AddP reg off);
4199
4200 format %{ "[$reg + $off]" %}
4201 interface(MEMORY_INTER) %{
4202 base($reg);
4203 index(0x4);
4204 scale(0x0);
4205 disp($off);
4206 %}
4207 %}
4208
4209 opclass load_long_memory(load_long_indirect, load_long_indOffset32);
4210
4211
4212 //----------Special Memory Operands--------------------------------------------
4213 // Stack Slot Operand - This operand is used for loading and storing temporary
4214 // values on the stack where a match requires a value to
4215 // flow through memory.
4216 operand stackSlotP(sRegP reg) %{
4217 constraint(ALLOC_IN_RC(stack_slots));
4218 // No match rule because this operand is only generated in matching
4219 format %{ "[$reg]" %}
4220 interface(MEMORY_INTER) %{
4221 base(0x4); // ESP
4222 index(0x4); // No Index
4223 scale(0x0); // No Scale
4224 disp($reg); // Stack Offset
4225 %}
4226 %}
4227
4228 operand stackSlotI(sRegI reg) %{
4229 constraint(ALLOC_IN_RC(stack_slots));
4230 // No match rule because this operand is only generated in matching
4231 format %{ "[$reg]" %}
4232 interface(MEMORY_INTER) %{
4233 base(0x4); // ESP
4234 index(0x4); // No Index
4235 scale(0x0); // No Scale
4236 disp($reg); // Stack Offset
4237 %}
4238 %}
4239
4240 operand stackSlotF(sRegF reg) %{
4241 constraint(ALLOC_IN_RC(stack_slots));
4242 // No match rule because this operand is only generated in matching
4243 format %{ "[$reg]" %}
4244 interface(MEMORY_INTER) %{
4245 base(0x4); // ESP
4246 index(0x4); // No Index
4247 scale(0x0); // No Scale
4248 disp($reg); // Stack Offset
4249 %}
4250 %}
4251
4252 operand stackSlotD(sRegD reg) %{
4253 constraint(ALLOC_IN_RC(stack_slots));
4254 // No match rule because this operand is only generated in matching
4255 format %{ "[$reg]" %}
4256 interface(MEMORY_INTER) %{
4257 base(0x4); // ESP
4258 index(0x4); // No Index
4259 scale(0x0); // No Scale
4260 disp($reg); // Stack Offset
4261 %}
4262 %}
4263
4264 operand stackSlotL(sRegL reg) %{
4265 constraint(ALLOC_IN_RC(stack_slots));
4266 // No match rule because this operand is only generated in matching
4267 format %{ "[$reg]" %}
4268 interface(MEMORY_INTER) %{
4269 base(0x4); // ESP
4270 index(0x4); // No Index
4271 scale(0x0); // No Scale
4272 disp($reg); // Stack Offset
4273 %}
4274 %}
4275
4276 //----------Memory Operands - Win95 Implicit Null Variants----------------
4277 // Indirect Memory Operand
4278 operand indirect_win95_safe(eRegP_no_EBP reg)
4279 %{
4280 constraint(ALLOC_IN_RC(int_reg));
4281 match(reg);
4282
4283 op_cost(100);
4284 format %{ "[$reg]" %}
4285 interface(MEMORY_INTER) %{
4286 base($reg);
4287 index(0x4);
4288 scale(0x0);
4289 disp(0x0);
4290 %}
4291 %}
4292
4293 // Indirect Memory Plus Short Offset Operand
4294 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off)
4295 %{
4296 match(AddP reg off);
4297
4298 op_cost(100);
4299 format %{ "[$reg + $off]" %}
4300 interface(MEMORY_INTER) %{
4301 base($reg);
4302 index(0x4);
4303 scale(0x0);
4304 disp($off);
4305 %}
4306 %}
4307
4308 // Indirect Memory Plus Long Offset Operand
4309 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off)
4310 %{
4311 match(AddP reg off);
4312
4313 op_cost(100);
4314 format %{ "[$reg + $off]" %}
4315 interface(MEMORY_INTER) %{
4316 base($reg);
4317 index(0x4);
4318 scale(0x0);
4319 disp($off);
4320 %}
4321 %}
4322
4323 // Indirect Memory Plus Index Register Plus Offset Operand
4324 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI off)
4325 %{
4326 match(AddP (AddP reg ireg) off);
4327
4328 op_cost(100);
4329 format %{"[$reg + $off + $ireg]" %}
4330 interface(MEMORY_INTER) %{
4331 base($reg);
4332 index($ireg);
4333 scale(0x0);
4334 disp($off);
4335 %}
4336 %}
4337
4338 // Indirect Memory Times Scale Plus Index Register
4339 operand indIndexScale_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI2 scale)
4340 %{
4341 match(AddP reg (LShiftI ireg scale));
4342
4343 op_cost(100);
4344 format %{"[$reg + $ireg << $scale]" %}
4345 interface(MEMORY_INTER) %{
4346 base($reg);
4347 index($ireg);
4348 scale($scale);
4349 disp(0x0);
4350 %}
4351 %}
4352
4353 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4354 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, rRegI ireg, immI2 scale)
4355 %{
4356 match(AddP (AddP reg (LShiftI ireg scale)) off);
4357
4358 op_cost(100);
4359 format %{"[$reg + $off + $ireg << $scale]" %}
4360 interface(MEMORY_INTER) %{
4361 base($reg);
4362 index($ireg);
4363 scale($scale);
4364 disp($off);
4365 %}
4366 %}
4367
4368 //----------Conditional Branch Operands----------------------------------------
4369 // Comparison Op - This is the operation of the comparison, and is limited to
4370 // the following set of codes:
4371 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4372 //
4373 // Other attributes of the comparison, such as unsignedness, are specified
4374 // by the comparison instruction that sets a condition code flags register.
4375 // That result is represented by a flags operand whose subtype is appropriate
4376 // to the unsignedness (etc.) of the comparison.
4377 //
4378 // Later, the instruction which matches both the Comparison Op (a Bool) and
4379 // the flags (produced by the Cmp) specifies the coding of the comparison op
4380 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4381
4382 // Comparision Code
4383 operand cmpOp() %{
4384 match(Bool);
4385
4386 format %{ "" %}
4387 interface(COND_INTER) %{
4388 equal(0x4, "e");
4389 not_equal(0x5, "ne");
4390 less(0xC, "l");
4391 greater_equal(0xD, "ge");
4392 less_equal(0xE, "le");
4393 greater(0xF, "g");
4394 overflow(0x0, "o");
4395 no_overflow(0x1, "no");
4396 %}
4397 %}
4398
4399 // Comparison Code, unsigned compare. Used by FP also, with
4400 // C2 (unordered) turned into GT or LT already. The other bits
4401 // C0 and C3 are turned into Carry & Zero flags.
4402 operand cmpOpU() %{
4403 match(Bool);
4404
4405 format %{ "" %}
4406 interface(COND_INTER) %{
4407 equal(0x4, "e");
4408 not_equal(0x5, "ne");
4409 less(0x2, "b");
4410 greater_equal(0x3, "nb");
4411 less_equal(0x6, "be");
4412 greater(0x7, "nbe");
4413 overflow(0x0, "o");
4414 no_overflow(0x1, "no");
4415 %}
4416 %}
4417
4418 // Floating comparisons that don't require any fixup for the unordered case
4419 operand cmpOpUCF() %{
4420 match(Bool);
4421 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
4422 n->as_Bool()->_test._test == BoolTest::ge ||
4423 n->as_Bool()->_test._test == BoolTest::le ||
4424 n->as_Bool()->_test._test == BoolTest::gt);
4425 format %{ "" %}
4426 interface(COND_INTER) %{
4427 equal(0x4, "e");
4428 not_equal(0x5, "ne");
4429 less(0x2, "b");
4430 greater_equal(0x3, "nb");
4431 less_equal(0x6, "be");
4432 greater(0x7, "nbe");
4433 overflow(0x0, "o");
4434 no_overflow(0x1, "no");
4435 %}
4436 %}
4437
4438
4439 // Floating comparisons that can be fixed up with extra conditional jumps
4440 operand cmpOpUCF2() %{
4441 match(Bool);
4442 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
4443 n->as_Bool()->_test._test == BoolTest::eq);
4444 format %{ "" %}
4445 interface(COND_INTER) %{
4446 equal(0x4, "e");
4447 not_equal(0x5, "ne");
4448 less(0x2, "b");
4449 greater_equal(0x3, "nb");
4450 less_equal(0x6, "be");
4451 greater(0x7, "nbe");
4452 overflow(0x0, "o");
4453 no_overflow(0x1, "no");
4454 %}
4455 %}
4456
4457 // Comparison Code for FP conditional move
4458 operand cmpOp_fcmov() %{
4459 match(Bool);
4460
4461 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4462 n->as_Bool()->_test._test != BoolTest::no_overflow);
4463 format %{ "" %}
4464 interface(COND_INTER) %{
4465 equal (0x0C8);
4466 not_equal (0x1C8);
4467 less (0x0C0);
4468 greater_equal(0x1C0);
4469 less_equal (0x0D0);
4470 greater (0x1D0);
4471 overflow(0x0, "o"); // not really supported by the instruction
4472 no_overflow(0x1, "no"); // not really supported by the instruction
4473 %}
4474 %}
4475
4476 // Comparision Code used in long compares
4477 operand cmpOp_commute() %{
4478 match(Bool);
4479
4480 format %{ "" %}
4481 interface(COND_INTER) %{
4482 equal(0x4, "e");
4483 not_equal(0x5, "ne");
4484 less(0xF, "g");
4485 greater_equal(0xE, "le");
4486 less_equal(0xD, "ge");
4487 greater(0xC, "l");
4488 overflow(0x0, "o");
4489 no_overflow(0x1, "no");
4490 %}
4491 %}
4492
4493 //----------OPERAND CLASSES----------------------------------------------------
4494 // Operand Classes are groups of operands that are used as to simplify
4495 // instruction definitions by not requiring the AD writer to specify separate
4496 // instructions for every form of operand when the instruction accepts
4497 // multiple operand types with the same basic encoding and format. The classic
4498 // case of this is memory operands.
4499
4500 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset,
4501 indIndex, indIndexScale, indIndexScaleOffset);
4502
4503 // Long memory operations are encoded in 2 instructions and a +4 offset.
4504 // This means some kind of offset is always required and you cannot use
4505 // an oop as the offset (done when working on static globals).
4506 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset,
4507 indIndex, indIndexScale, indIndexScaleOffset);
4508
4509
4510 //----------PIPELINE-----------------------------------------------------------
4511 // Rules which define the behavior of the target architectures pipeline.
4512 pipeline %{
4513
4514 //----------ATTRIBUTES---------------------------------------------------------
4515 attributes %{
4516 variable_size_instructions; // Fixed size instructions
4517 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
4518 instruction_unit_size = 1; // An instruction is 1 bytes long
4519 instruction_fetch_unit_size = 16; // The processor fetches one line
4520 instruction_fetch_units = 1; // of 16 bytes
4521
4522 // List of nop instructions
4523 nops( MachNop );
4524 %}
4525
4526 //----------RESOURCES----------------------------------------------------------
4527 // Resources are the functional units available to the machine
4528
4529 // Generic P2/P3 pipeline
4530 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
4531 // 3 instructions decoded per cycle.
4532 // 2 load/store ops per cycle, 1 branch, 1 FPU,
4533 // 2 ALU op, only ALU0 handles mul/div instructions.
4534 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
4535 MS0, MS1, MEM = MS0 | MS1,
4536 BR, FPU,
4537 ALU0, ALU1, ALU = ALU0 | ALU1 );
4538
4539 //----------PIPELINE DESCRIPTION-----------------------------------------------
4540 // Pipeline Description specifies the stages in the machine's pipeline
4541
4542 // Generic P2/P3 pipeline
4543 pipe_desc(S0, S1, S2, S3, S4, S5);
4544
4545 //----------PIPELINE CLASSES---------------------------------------------------
4546 // Pipeline Classes describe the stages in which input and output are
4547 // referenced by the hardware pipeline.
4548
4549 // Naming convention: ialu or fpu
4550 // Then: _reg
4551 // Then: _reg if there is a 2nd register
4552 // Then: _long if it's a pair of instructions implementing a long
4553 // Then: _fat if it requires the big decoder
4554 // Or: _mem if it requires the big decoder and a memory unit.
4555
4556 // Integer ALU reg operation
4557 pipe_class ialu_reg(rRegI dst) %{
4558 single_instruction;
4559 dst : S4(write);
4560 dst : S3(read);
4561 DECODE : S0; // any decoder
4562 ALU : S3; // any alu
4563 %}
4564
4565 // Long ALU reg operation
4566 pipe_class ialu_reg_long(eRegL dst) %{
4567 instruction_count(2);
4568 dst : S4(write);
4569 dst : S3(read);
4570 DECODE : S0(2); // any 2 decoders
4571 ALU : S3(2); // both alus
4572 %}
4573
4574 // Integer ALU reg operation using big decoder
4575 pipe_class ialu_reg_fat(rRegI dst) %{
4576 single_instruction;
4577 dst : S4(write);
4578 dst : S3(read);
4579 D0 : S0; // big decoder only
4580 ALU : S3; // any alu
4581 %}
4582
4583 // Long ALU reg operation using big decoder
4584 pipe_class ialu_reg_long_fat(eRegL dst) %{
4585 instruction_count(2);
4586 dst : S4(write);
4587 dst : S3(read);
4588 D0 : S0(2); // big decoder only; twice
4589 ALU : S3(2); // any 2 alus
4590 %}
4591
4592 // Integer ALU reg-reg operation
4593 pipe_class ialu_reg_reg(rRegI dst, rRegI src) %{
4594 single_instruction;
4595 dst : S4(write);
4596 src : S3(read);
4597 DECODE : S0; // any decoder
4598 ALU : S3; // any alu
4599 %}
4600
4601 // Long ALU reg-reg operation
4602 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{
4603 instruction_count(2);
4604 dst : S4(write);
4605 src : S3(read);
4606 DECODE : S0(2); // any 2 decoders
4607 ALU : S3(2); // both alus
4608 %}
4609
4610 // Integer ALU reg-reg operation
4611 pipe_class ialu_reg_reg_fat(rRegI dst, memory src) %{
4612 single_instruction;
4613 dst : S4(write);
4614 src : S3(read);
4615 D0 : S0; // big decoder only
4616 ALU : S3; // any alu
4617 %}
4618
4619 // Long ALU reg-reg operation
4620 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{
4621 instruction_count(2);
4622 dst : S4(write);
4623 src : S3(read);
4624 D0 : S0(2); // big decoder only; twice
4625 ALU : S3(2); // both alus
4626 %}
4627
4628 // Integer ALU reg-mem operation
4629 pipe_class ialu_reg_mem(rRegI dst, memory mem) %{
4630 single_instruction;
4631 dst : S5(write);
4632 mem : S3(read);
4633 D0 : S0; // big decoder only
4634 ALU : S4; // any alu
4635 MEM : S3; // any mem
4636 %}
4637
4638 // Long ALU reg-mem operation
4639 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{
4640 instruction_count(2);
4641 dst : S5(write);
4642 mem : S3(read);
4643 D0 : S0(2); // big decoder only; twice
4644 ALU : S4(2); // any 2 alus
4645 MEM : S3(2); // both mems
4646 %}
4647
4648 // Integer mem operation (prefetch)
4649 pipe_class ialu_mem(memory mem)
4650 %{
4651 single_instruction;
4652 mem : S3(read);
4653 D0 : S0; // big decoder only
4654 MEM : S3; // any mem
4655 %}
4656
4657 // Integer Store to Memory
4658 pipe_class ialu_mem_reg(memory mem, rRegI src) %{
4659 single_instruction;
4660 mem : S3(read);
4661 src : S5(read);
4662 D0 : S0; // big decoder only
4663 ALU : S4; // any alu
4664 MEM : S3;
4665 %}
4666
4667 // Long Store to Memory
4668 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{
4669 instruction_count(2);
4670 mem : S3(read);
4671 src : S5(read);
4672 D0 : S0(2); // big decoder only; twice
4673 ALU : S4(2); // any 2 alus
4674 MEM : S3(2); // Both mems
4675 %}
4676
4677 // Integer Store to Memory
4678 pipe_class ialu_mem_imm(memory mem) %{
4679 single_instruction;
4680 mem : S3(read);
4681 D0 : S0; // big decoder only
4682 ALU : S4; // any alu
4683 MEM : S3;
4684 %}
4685
4686 // Integer ALU0 reg-reg operation
4687 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src) %{
4688 single_instruction;
4689 dst : S4(write);
4690 src : S3(read);
4691 D0 : S0; // Big decoder only
4692 ALU0 : S3; // only alu0
4693 %}
4694
4695 // Integer ALU0 reg-mem operation
4696 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem) %{
4697 single_instruction;
4698 dst : S5(write);
4699 mem : S3(read);
4700 D0 : S0; // big decoder only
4701 ALU0 : S4; // ALU0 only
4702 MEM : S3; // any mem
4703 %}
4704
4705 // Integer ALU reg-reg operation
4706 pipe_class ialu_cr_reg_reg(eFlagsReg cr, rRegI src1, rRegI src2) %{
4707 single_instruction;
4708 cr : S4(write);
4709 src1 : S3(read);
4710 src2 : S3(read);
4711 DECODE : S0; // any decoder
4712 ALU : S3; // any alu
4713 %}
4714
4715 // Integer ALU reg-imm operation
4716 pipe_class ialu_cr_reg_imm(eFlagsReg cr, rRegI src1) %{
4717 single_instruction;
4718 cr : S4(write);
4719 src1 : S3(read);
4720 DECODE : S0; // any decoder
4721 ALU : S3; // any alu
4722 %}
4723
4724 // Integer ALU reg-mem operation
4725 pipe_class ialu_cr_reg_mem(eFlagsReg cr, rRegI src1, memory src2) %{
4726 single_instruction;
4727 cr : S4(write);
4728 src1 : S3(read);
4729 src2 : S3(read);
4730 D0 : S0; // big decoder only
4731 ALU : S4; // any alu
4732 MEM : S3;
4733 %}
4734
4735 // Conditional move reg-reg
4736 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y ) %{
4737 instruction_count(4);
4738 y : S4(read);
4739 q : S3(read);
4740 p : S3(read);
4741 DECODE : S0(4); // any decoder
4742 %}
4743
4744 // Conditional move reg-reg
4745 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, eFlagsReg cr ) %{
4746 single_instruction;
4747 dst : S4(write);
4748 src : S3(read);
4749 cr : S3(read);
4750 DECODE : S0; // any decoder
4751 %}
4752
4753 // Conditional move reg-mem
4754 pipe_class pipe_cmov_mem( eFlagsReg cr, rRegI dst, memory src) %{
4755 single_instruction;
4756 dst : S4(write);
4757 src : S3(read);
4758 cr : S3(read);
4759 DECODE : S0; // any decoder
4760 MEM : S3;
4761 %}
4762
4763 // Conditional move reg-reg long
4764 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{
4765 single_instruction;
4766 dst : S4(write);
4767 src : S3(read);
4768 cr : S3(read);
4769 DECODE : S0(2); // any 2 decoders
4770 %}
4771
4772 // Conditional move double reg-reg
4773 pipe_class pipe_cmovDPR_reg( eFlagsReg cr, regDPR1 dst, regDPR src) %{
4774 single_instruction;
4775 dst : S4(write);
4776 src : S3(read);
4777 cr : S3(read);
4778 DECODE : S0; // any decoder
4779 %}
4780
4781 // Float reg-reg operation
4782 pipe_class fpu_reg(regDPR dst) %{
4783 instruction_count(2);
4784 dst : S3(read);
4785 DECODE : S0(2); // any 2 decoders
4786 FPU : S3;
4787 %}
4788
4789 // Float reg-reg operation
4790 pipe_class fpu_reg_reg(regDPR dst, regDPR src) %{
4791 instruction_count(2);
4792 dst : S4(write);
4793 src : S3(read);
4794 DECODE : S0(2); // any 2 decoders
4795 FPU : S3;
4796 %}
4797
4798 // Float reg-reg operation
4799 pipe_class fpu_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2) %{
4800 instruction_count(3);
4801 dst : S4(write);
4802 src1 : S3(read);
4803 src2 : S3(read);
4804 DECODE : S0(3); // any 3 decoders
4805 FPU : S3(2);
4806 %}
4807
4808 // Float reg-reg operation
4809 pipe_class fpu_reg_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2, regDPR src3) %{
4810 instruction_count(4);
4811 dst : S4(write);
4812 src1 : S3(read);
4813 src2 : S3(read);
4814 src3 : S3(read);
4815 DECODE : S0(4); // any 3 decoders
4816 FPU : S3(2);
4817 %}
4818
4819 // Float reg-reg operation
4820 pipe_class fpu_reg_mem_reg_reg(regDPR dst, memory src1, regDPR src2, regDPR src3) %{
4821 instruction_count(4);
4822 dst : S4(write);
4823 src1 : S3(read);
4824 src2 : S3(read);
4825 src3 : S3(read);
4826 DECODE : S1(3); // any 3 decoders
4827 D0 : S0; // Big decoder only
4828 FPU : S3(2);
4829 MEM : S3;
4830 %}
4831
4832 // Float reg-mem operation
4833 pipe_class fpu_reg_mem(regDPR dst, memory mem) %{
4834 instruction_count(2);
4835 dst : S5(write);
4836 mem : S3(read);
4837 D0 : S0; // big decoder only
4838 DECODE : S1; // any decoder for FPU POP
4839 FPU : S4;
4840 MEM : S3; // any mem
4841 %}
4842
4843 // Float reg-mem operation
4844 pipe_class fpu_reg_reg_mem(regDPR dst, regDPR src1, memory mem) %{
4845 instruction_count(3);
4846 dst : S5(write);
4847 src1 : S3(read);
4848 mem : S3(read);
4849 D0 : S0; // big decoder only
4850 DECODE : S1(2); // any decoder for FPU POP
4851 FPU : S4;
4852 MEM : S3; // any mem
4853 %}
4854
4855 // Float mem-reg operation
4856 pipe_class fpu_mem_reg(memory mem, regDPR src) %{
4857 instruction_count(2);
4858 src : S5(read);
4859 mem : S3(read);
4860 DECODE : S0; // any decoder for FPU PUSH
4861 D0 : S1; // big decoder only
4862 FPU : S4;
4863 MEM : S3; // any mem
4864 %}
4865
4866 pipe_class fpu_mem_reg_reg(memory mem, regDPR src1, regDPR src2) %{
4867 instruction_count(3);
4868 src1 : S3(read);
4869 src2 : S3(read);
4870 mem : S3(read);
4871 DECODE : S0(2); // any decoder for FPU PUSH
4872 D0 : S1; // big decoder only
4873 FPU : S4;
4874 MEM : S3; // any mem
4875 %}
4876
4877 pipe_class fpu_mem_reg_mem(memory mem, regDPR src1, memory src2) %{
4878 instruction_count(3);
4879 src1 : S3(read);
4880 src2 : S3(read);
4881 mem : S4(read);
4882 DECODE : S0; // any decoder for FPU PUSH
4883 D0 : S0(2); // big decoder only
4884 FPU : S4;
4885 MEM : S3(2); // any mem
4886 %}
4887
4888 pipe_class fpu_mem_mem(memory dst, memory src1) %{
4889 instruction_count(2);
4890 src1 : S3(read);
4891 dst : S4(read);
4892 D0 : S0(2); // big decoder only
4893 MEM : S3(2); // any mem
4894 %}
4895
4896 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{
4897 instruction_count(3);
4898 src1 : S3(read);
4899 src2 : S3(read);
4900 dst : S4(read);
4901 D0 : S0(3); // big decoder only
4902 FPU : S4;
4903 MEM : S3(3); // any mem
4904 %}
4905
4906 pipe_class fpu_mem_reg_con(memory mem, regDPR src1) %{
4907 instruction_count(3);
4908 src1 : S4(read);
4909 mem : S4(read);
4910 DECODE : S0; // any decoder for FPU PUSH
4911 D0 : S0(2); // big decoder only
4912 FPU : S4;
4913 MEM : S3(2); // any mem
4914 %}
4915
4916 // Float load constant
4917 pipe_class fpu_reg_con(regDPR dst) %{
4918 instruction_count(2);
4919 dst : S5(write);
4920 D0 : S0; // big decoder only for the load
4921 DECODE : S1; // any decoder for FPU POP
4922 FPU : S4;
4923 MEM : S3; // any mem
4924 %}
4925
4926 // Float load constant
4927 pipe_class fpu_reg_reg_con(regDPR dst, regDPR src) %{
4928 instruction_count(3);
4929 dst : S5(write);
4930 src : S3(read);
4931 D0 : S0; // big decoder only for the load
4932 DECODE : S1(2); // any decoder for FPU POP
4933 FPU : S4;
4934 MEM : S3; // any mem
4935 %}
4936
4937 // UnConditional branch
4938 pipe_class pipe_jmp( label labl ) %{
4939 single_instruction;
4940 BR : S3;
4941 %}
4942
4943 // Conditional branch
4944 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{
4945 single_instruction;
4946 cr : S1(read);
4947 BR : S3;
4948 %}
4949
4950 // Allocation idiom
4951 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{
4952 instruction_count(1); force_serialization;
4953 fixed_latency(6);
4954 heap_ptr : S3(read);
4955 DECODE : S0(3);
4956 D0 : S2;
4957 MEM : S3;
4958 ALU : S3(2);
4959 dst : S5(write);
4960 BR : S5;
4961 %}
4962
4963 // Generic big/slow expanded idiom
4964 pipe_class pipe_slow( ) %{
4965 instruction_count(10); multiple_bundles; force_serialization;
4966 fixed_latency(100);
4967 D0 : S0(2);
4968 MEM : S3(2);
4969 %}
4970
4971 // The real do-nothing guy
4972 pipe_class empty( ) %{
4973 instruction_count(0);
4974 %}
4975
4976 // Define the class for the Nop node
4977 define %{
4978 MachNop = empty;
4979 %}
4980
4981 %}
4982
4983 //----------INSTRUCTIONS-------------------------------------------------------
4984 //
4985 // match -- States which machine-independent subtree may be replaced
4986 // by this instruction.
4987 // ins_cost -- The estimated cost of this instruction is used by instruction
4988 // selection to identify a minimum cost tree of machine
4989 // instructions that matches a tree of machine-independent
4990 // instructions.
4991 // format -- A string providing the disassembly for this instruction.
4992 // The value of an instruction's operand may be inserted
4993 // by referring to it with a '$' prefix.
4994 // opcode -- Three instruction opcodes may be provided. These are referred
4995 // to within an encode class as $primary, $secondary, and $tertiary
4996 // respectively. The primary opcode is commonly used to
4997 // indicate the type of machine instruction, while secondary
4998 // and tertiary are often used for prefix options or addressing
4999 // modes.
5000 // ins_encode -- A list of encode classes with parameters. The encode class
5001 // name must have been defined in an 'enc_class' specification
5002 // in the encode section of the architecture description.
5003
5004 //----------BSWAP-Instruction--------------------------------------------------
5005 instruct bytes_reverse_int(rRegI dst) %{
5006 match(Set dst (ReverseBytesI dst));
5007
5008 format %{ "BSWAP $dst" %}
5009 opcode(0x0F, 0xC8);
5010 ins_encode( OpcP, OpcSReg(dst) );
5011 ins_pipe( ialu_reg );
5012 %}
5013
5014 instruct bytes_reverse_long(eRegL dst) %{
5015 match(Set dst (ReverseBytesL dst));
5016
5017 format %{ "BSWAP $dst.lo\n\t"
5018 "BSWAP $dst.hi\n\t"
5019 "XCHG $dst.lo $dst.hi" %}
5020
5021 ins_cost(125);
5022 ins_encode( bswap_long_bytes(dst) );
5023 ins_pipe( ialu_reg_reg);
5024 %}
5025
5026 instruct bytes_reverse_unsigned_short(rRegI dst, eFlagsReg cr) %{
5027 match(Set dst (ReverseBytesUS dst));
5028 effect(KILL cr);
5029
5030 format %{ "BSWAP $dst\n\t"
5031 "SHR $dst,16\n\t" %}
5032 ins_encode %{
5033 __ bswapl($dst$$Register);
5034 __ shrl($dst$$Register, 16);
5035 %}
5036 ins_pipe( ialu_reg );
5037 %}
5038
5039 instruct bytes_reverse_short(rRegI dst, eFlagsReg cr) %{
5040 match(Set dst (ReverseBytesS dst));
5041 effect(KILL cr);
5042
5043 format %{ "BSWAP $dst\n\t"
5044 "SAR $dst,16\n\t" %}
5045 ins_encode %{
5046 __ bswapl($dst$$Register);
5047 __ sarl($dst$$Register, 16);
5048 %}
5049 ins_pipe( ialu_reg );
5050 %}
5051
5052
5053 //---------- Zeros Count Instructions ------------------------------------------
5054
5055 instruct countLeadingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{
5056 predicate(UseCountLeadingZerosInstruction);
5057 match(Set dst (CountLeadingZerosI src));
5058 effect(KILL cr);
5059
5060 format %{ "LZCNT $dst, $src\t# count leading zeros (int)" %}
5061 ins_encode %{
5062 __ lzcntl($dst$$Register, $src$$Register);
5063 %}
5064 ins_pipe(ialu_reg);
5065 %}
5066
5067 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, eFlagsReg cr) %{
5068 predicate(!UseCountLeadingZerosInstruction);
5069 match(Set dst (CountLeadingZerosI src));
5070 effect(KILL cr);
5071
5072 format %{ "BSR $dst, $src\t# count leading zeros (int)\n\t"
5073 "JNZ skip\n\t"
5074 "MOV $dst, -1\n"
5075 "skip:\n\t"
5076 "NEG $dst\n\t"
5077 "ADD $dst, 31" %}
5078 ins_encode %{
5079 Register Rdst = $dst$$Register;
5080 Register Rsrc = $src$$Register;
5081 Label skip;
5082 __ bsrl(Rdst, Rsrc);
5083 __ jccb(Assembler::notZero, skip);
5084 __ movl(Rdst, -1);
5085 __ bind(skip);
5086 __ negl(Rdst);
5087 __ addl(Rdst, BitsPerInt - 1);
5088 %}
5089 ins_pipe(ialu_reg);
5090 %}
5091
5092 instruct countLeadingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{
5093 predicate(UseCountLeadingZerosInstruction);
5094 match(Set dst (CountLeadingZerosL src));
5095 effect(TEMP dst, KILL cr);
5096
5097 format %{ "LZCNT $dst, $src.hi\t# count leading zeros (long)\n\t"
5098 "JNC done\n\t"
5099 "LZCNT $dst, $src.lo\n\t"
5100 "ADD $dst, 32\n"
5101 "done:" %}
5102 ins_encode %{
5103 Register Rdst = $dst$$Register;
5104 Register Rsrc = $src$$Register;
5105 Label done;
5106 __ lzcntl(Rdst, HIGH_FROM_LOW(Rsrc));
5107 __ jccb(Assembler::carryClear, done);
5108 __ lzcntl(Rdst, Rsrc);
5109 __ addl(Rdst, BitsPerInt);
5110 __ bind(done);
5111 %}
5112 ins_pipe(ialu_reg);
5113 %}
5114
5115 instruct countLeadingZerosL_bsr(rRegI dst, eRegL src, eFlagsReg cr) %{
5116 predicate(!UseCountLeadingZerosInstruction);
5117 match(Set dst (CountLeadingZerosL src));
5118 effect(TEMP dst, KILL cr);
5119
5120 format %{ "BSR $dst, $src.hi\t# count leading zeros (long)\n\t"
5121 "JZ msw_is_zero\n\t"
5122 "ADD $dst, 32\n\t"
5123 "JMP not_zero\n"
5124 "msw_is_zero:\n\t"
5125 "BSR $dst, $src.lo\n\t"
5126 "JNZ not_zero\n\t"
5127 "MOV $dst, -1\n"
5128 "not_zero:\n\t"
5129 "NEG $dst\n\t"
5130 "ADD $dst, 63\n" %}
5131 ins_encode %{
5132 Register Rdst = $dst$$Register;
5133 Register Rsrc = $src$$Register;
5134 Label msw_is_zero;
5135 Label not_zero;
5136 __ bsrl(Rdst, HIGH_FROM_LOW(Rsrc));
5137 __ jccb(Assembler::zero, msw_is_zero);
5138 __ addl(Rdst, BitsPerInt);
5139 __ jmpb(not_zero);
5140 __ bind(msw_is_zero);
5141 __ bsrl(Rdst, Rsrc);
5142 __ jccb(Assembler::notZero, not_zero);
5143 __ movl(Rdst, -1);
5144 __ bind(not_zero);
5145 __ negl(Rdst);
5146 __ addl(Rdst, BitsPerLong - 1);
5147 %}
5148 ins_pipe(ialu_reg);
5149 %}
5150
5151 instruct countTrailingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{
5152 predicate(UseCountTrailingZerosInstruction);
5153 match(Set dst (CountTrailingZerosI src));
5154 effect(KILL cr);
5155
5156 format %{ "TZCNT $dst, $src\t# count trailing zeros (int)" %}
5157 ins_encode %{
5158 __ tzcntl($dst$$Register, $src$$Register);
5159 %}
5160 ins_pipe(ialu_reg);
5161 %}
5162
5163 instruct countTrailingZerosI_bsf(rRegI dst, rRegI src, eFlagsReg cr) %{
5164 predicate(!UseCountTrailingZerosInstruction);
5165 match(Set dst (CountTrailingZerosI src));
5166 effect(KILL cr);
5167
5168 format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t"
5169 "JNZ done\n\t"
5170 "MOV $dst, 32\n"
5171 "done:" %}
5172 ins_encode %{
5173 Register Rdst = $dst$$Register;
5174 Label done;
5175 __ bsfl(Rdst, $src$$Register);
5176 __ jccb(Assembler::notZero, done);
5177 __ movl(Rdst, BitsPerInt);
5178 __ bind(done);
5179 %}
5180 ins_pipe(ialu_reg);
5181 %}
5182
5183 instruct countTrailingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{
5184 predicate(UseCountTrailingZerosInstruction);
5185 match(Set dst (CountTrailingZerosL src));
5186 effect(TEMP dst, KILL cr);
5187
5188 format %{ "TZCNT $dst, $src.lo\t# count trailing zeros (long) \n\t"
5189 "JNC done\n\t"
5190 "TZCNT $dst, $src.hi\n\t"
5191 "ADD $dst, 32\n"
5192 "done:" %}
5193 ins_encode %{
5194 Register Rdst = $dst$$Register;
5195 Register Rsrc = $src$$Register;
5196 Label done;
5197 __ tzcntl(Rdst, Rsrc);
5198 __ jccb(Assembler::carryClear, done);
5199 __ tzcntl(Rdst, HIGH_FROM_LOW(Rsrc));
5200 __ addl(Rdst, BitsPerInt);
5201 __ bind(done);
5202 %}
5203 ins_pipe(ialu_reg);
5204 %}
5205
5206 instruct countTrailingZerosL_bsf(rRegI dst, eRegL src, eFlagsReg cr) %{
5207 predicate(!UseCountTrailingZerosInstruction);
5208 match(Set dst (CountTrailingZerosL src));
5209 effect(TEMP dst, KILL cr);
5210
5211 format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t"
5212 "JNZ done\n\t"
5213 "BSF $dst, $src.hi\n\t"
5214 "JNZ msw_not_zero\n\t"
5215 "MOV $dst, 32\n"
5216 "msw_not_zero:\n\t"
5217 "ADD $dst, 32\n"
5218 "done:" %}
5219 ins_encode %{
5220 Register Rdst = $dst$$Register;
5221 Register Rsrc = $src$$Register;
5222 Label msw_not_zero;
5223 Label done;
5224 __ bsfl(Rdst, Rsrc);
5225 __ jccb(Assembler::notZero, done);
5226 __ bsfl(Rdst, HIGH_FROM_LOW(Rsrc));
5227 __ jccb(Assembler::notZero, msw_not_zero);
5228 __ movl(Rdst, BitsPerInt);
5229 __ bind(msw_not_zero);
5230 __ addl(Rdst, BitsPerInt);
5231 __ bind(done);
5232 %}
5233 ins_pipe(ialu_reg);
5234 %}
5235
5236
5237 //---------- Population Count Instructions -------------------------------------
5238
5239 instruct popCountI(rRegI dst, rRegI src, eFlagsReg cr) %{
5240 predicate(UsePopCountInstruction);
5241 match(Set dst (PopCountI src));
5242 effect(KILL cr);
5243
5244 format %{ "POPCNT $dst, $src" %}
5245 ins_encode %{
5246 __ popcntl($dst$$Register, $src$$Register);
5247 %}
5248 ins_pipe(ialu_reg);
5249 %}
5250
5251 instruct popCountI_mem(rRegI dst, memory mem, eFlagsReg cr) %{
5252 predicate(UsePopCountInstruction);
5253 match(Set dst (PopCountI (LoadI mem)));
5254 effect(KILL cr);
5255
5256 format %{ "POPCNT $dst, $mem" %}
5257 ins_encode %{
5258 __ popcntl($dst$$Register, $mem$$Address);
5259 %}
5260 ins_pipe(ialu_reg);
5261 %}
5262
5263 // Note: Long.bitCount(long) returns an int.
5264 instruct popCountL(rRegI dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
5265 predicate(UsePopCountInstruction);
5266 match(Set dst (PopCountL src));
5267 effect(KILL cr, TEMP tmp, TEMP dst);
5268
5269 format %{ "POPCNT $dst, $src.lo\n\t"
5270 "POPCNT $tmp, $src.hi\n\t"
5271 "ADD $dst, $tmp" %}
5272 ins_encode %{
5273 __ popcntl($dst$$Register, $src$$Register);
5274 __ popcntl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
5275 __ addl($dst$$Register, $tmp$$Register);
5276 %}
5277 ins_pipe(ialu_reg);
5278 %}
5279
5280 // Note: Long.bitCount(long) returns an int.
5281 instruct popCountL_mem(rRegI dst, memory mem, rRegI tmp, eFlagsReg cr) %{
5282 predicate(UsePopCountInstruction);
5283 match(Set dst (PopCountL (LoadL mem)));
5284 effect(KILL cr, TEMP tmp, TEMP dst);
5285
5286 format %{ "POPCNT $dst, $mem\n\t"
5287 "POPCNT $tmp, $mem+4\n\t"
5288 "ADD $dst, $tmp" %}
5289 ins_encode %{
5290 //__ popcntl($dst$$Register, $mem$$Address$$first);
5291 //__ popcntl($tmp$$Register, $mem$$Address$$second);
5292 __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none));
5293 __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none));
5294 __ addl($dst$$Register, $tmp$$Register);
5295 %}
5296 ins_pipe(ialu_reg);
5297 %}
5298
5299
5300 //----------Load/Store/Move Instructions---------------------------------------
5301 //----------Load Instructions--------------------------------------------------
5302 // Load Byte (8bit signed)
5303 instruct loadB(xRegI dst, memory mem) %{
5304 match(Set dst (LoadB mem));
5305
5306 ins_cost(125);
5307 format %{ "MOVSX8 $dst,$mem\t# byte" %}
5308
5309 ins_encode %{
5310 __ movsbl($dst$$Register, $mem$$Address);
5311 %}
5312
5313 ins_pipe(ialu_reg_mem);
5314 %}
5315
5316 // Load Byte (8bit signed) into Long Register
5317 instruct loadB2L(eRegL dst, memory mem, eFlagsReg cr) %{
5318 match(Set dst (ConvI2L (LoadB mem)));
5319 effect(KILL cr);
5320
5321 ins_cost(375);
5322 format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t"
5323 "MOV $dst.hi,$dst.lo\n\t"
5324 "SAR $dst.hi,7" %}
5325
5326 ins_encode %{
5327 __ movsbl($dst$$Register, $mem$$Address);
5328 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5329 __ sarl(HIGH_FROM_LOW($dst$$Register), 7); // 24+1 MSB are already signed extended.
5330 %}
5331
5332 ins_pipe(ialu_reg_mem);
5333 %}
5334
5335 // Load Unsigned Byte (8bit UNsigned)
5336 instruct loadUB(xRegI dst, memory mem) %{
5337 match(Set dst (LoadUB mem));
5338
5339 ins_cost(125);
5340 format %{ "MOVZX8 $dst,$mem\t# ubyte -> int" %}
5341
5342 ins_encode %{
5343 __ movzbl($dst$$Register, $mem$$Address);
5344 %}
5345
5346 ins_pipe(ialu_reg_mem);
5347 %}
5348
5349 // Load Unsigned Byte (8 bit UNsigned) into Long Register
5350 instruct loadUB2L(eRegL dst, memory mem, eFlagsReg cr) %{
5351 match(Set dst (ConvI2L (LoadUB mem)));
5352 effect(KILL cr);
5353
5354 ins_cost(250);
5355 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t"
5356 "XOR $dst.hi,$dst.hi" %}
5357
5358 ins_encode %{
5359 Register Rdst = $dst$$Register;
5360 __ movzbl(Rdst, $mem$$Address);
5361 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5362 %}
5363
5364 ins_pipe(ialu_reg_mem);
5365 %}
5366
5367 // Load Unsigned Byte (8 bit UNsigned) with mask into Long Register
5368 instruct loadUB2L_immI8(eRegL dst, memory mem, immI8 mask, eFlagsReg cr) %{
5369 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5370 effect(KILL cr);
5371
5372 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte & 8-bit mask -> long\n\t"
5373 "XOR $dst.hi,$dst.hi\n\t"
5374 "AND $dst.lo,$mask" %}
5375 ins_encode %{
5376 Register Rdst = $dst$$Register;
5377 __ movzbl(Rdst, $mem$$Address);
5378 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5379 __ andl(Rdst, $mask$$constant);
5380 %}
5381 ins_pipe(ialu_reg_mem);
5382 %}
5383
5384 // Load Short (16bit signed)
5385 instruct loadS(rRegI dst, memory mem) %{
5386 match(Set dst (LoadS mem));
5387
5388 ins_cost(125);
5389 format %{ "MOVSX $dst,$mem\t# short" %}
5390
5391 ins_encode %{
5392 __ movswl($dst$$Register, $mem$$Address);
5393 %}
5394
5395 ins_pipe(ialu_reg_mem);
5396 %}
5397
5398 // Load Short (16 bit signed) to Byte (8 bit signed)
5399 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5400 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5401
5402 ins_cost(125);
5403 format %{ "MOVSX $dst, $mem\t# short -> byte" %}
5404 ins_encode %{
5405 __ movsbl($dst$$Register, $mem$$Address);
5406 %}
5407 ins_pipe(ialu_reg_mem);
5408 %}
5409
5410 // Load Short (16bit signed) into Long Register
5411 instruct loadS2L(eRegL dst, memory mem, eFlagsReg cr) %{
5412 match(Set dst (ConvI2L (LoadS mem)));
5413 effect(KILL cr);
5414
5415 ins_cost(375);
5416 format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t"
5417 "MOV $dst.hi,$dst.lo\n\t"
5418 "SAR $dst.hi,15" %}
5419
5420 ins_encode %{
5421 __ movswl($dst$$Register, $mem$$Address);
5422 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5423 __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended.
5424 %}
5425
5426 ins_pipe(ialu_reg_mem);
5427 %}
5428
5429 // Load Unsigned Short/Char (16bit unsigned)
5430 instruct loadUS(rRegI dst, memory mem) %{
5431 match(Set dst (LoadUS mem));
5432
5433 ins_cost(125);
5434 format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %}
5435
5436 ins_encode %{
5437 __ movzwl($dst$$Register, $mem$$Address);
5438 %}
5439
5440 ins_pipe(ialu_reg_mem);
5441 %}
5442
5443 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5444 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5445 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5446
5447 ins_cost(125);
5448 format %{ "MOVSX $dst, $mem\t# ushort -> byte" %}
5449 ins_encode %{
5450 __ movsbl($dst$$Register, $mem$$Address);
5451 %}
5452 ins_pipe(ialu_reg_mem);
5453 %}
5454
5455 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
5456 instruct loadUS2L(eRegL dst, memory mem, eFlagsReg cr) %{
5457 match(Set dst (ConvI2L (LoadUS mem)));
5458 effect(KILL cr);
5459
5460 ins_cost(250);
5461 format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t"
5462 "XOR $dst.hi,$dst.hi" %}
5463
5464 ins_encode %{
5465 __ movzwl($dst$$Register, $mem$$Address);
5466 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
5467 %}
5468
5469 ins_pipe(ialu_reg_mem);
5470 %}
5471
5472 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
5473 instruct loadUS2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
5474 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5475 effect(KILL cr);
5476
5477 format %{ "MOVZX8 $dst.lo,$mem\t# ushort/char & 0xFF -> long\n\t"
5478 "XOR $dst.hi,$dst.hi" %}
5479 ins_encode %{
5480 Register Rdst = $dst$$Register;
5481 __ movzbl(Rdst, $mem$$Address);
5482 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5483 %}
5484 ins_pipe(ialu_reg_mem);
5485 %}
5486
5487 // Load Unsigned Short/Char (16 bit UNsigned) with a 16-bit mask into Long Register
5488 instruct loadUS2L_immI16(eRegL dst, memory mem, immI16 mask, eFlagsReg cr) %{
5489 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5490 effect(KILL cr);
5491
5492 format %{ "MOVZX $dst.lo, $mem\t# ushort/char & 16-bit mask -> long\n\t"
5493 "XOR $dst.hi,$dst.hi\n\t"
5494 "AND $dst.lo,$mask" %}
5495 ins_encode %{
5496 Register Rdst = $dst$$Register;
5497 __ movzwl(Rdst, $mem$$Address);
5498 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5499 __ andl(Rdst, $mask$$constant);
5500 %}
5501 ins_pipe(ialu_reg_mem);
5502 %}
5503
5504 // Load Integer
5505 instruct loadI(rRegI dst, memory mem) %{
5506 match(Set dst (LoadI mem));
5507
5508 ins_cost(125);
5509 format %{ "MOV $dst,$mem\t# int" %}
5510
5511 ins_encode %{
5512 __ movl($dst$$Register, $mem$$Address);
5513 %}
5514
5515 ins_pipe(ialu_reg_mem);
5516 %}
5517
5518 // Load Integer (32 bit signed) to Byte (8 bit signed)
5519 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5520 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5521
5522 ins_cost(125);
5523 format %{ "MOVSX $dst, $mem\t# int -> byte" %}
5524 ins_encode %{
5525 __ movsbl($dst$$Register, $mem$$Address);
5526 %}
5527 ins_pipe(ialu_reg_mem);
5528 %}
5529
5530 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
5531 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
5532 match(Set dst (AndI (LoadI mem) mask));
5533
5534 ins_cost(125);
5535 format %{ "MOVZX $dst, $mem\t# int -> ubyte" %}
5536 ins_encode %{
5537 __ movzbl($dst$$Register, $mem$$Address);
5538 %}
5539 ins_pipe(ialu_reg_mem);
5540 %}
5541
5542 // Load Integer (32 bit signed) to Short (16 bit signed)
5543 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
5544 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5545
5546 ins_cost(125);
5547 format %{ "MOVSX $dst, $mem\t# int -> short" %}
5548 ins_encode %{
5549 __ movswl($dst$$Register, $mem$$Address);
5550 %}
5551 ins_pipe(ialu_reg_mem);
5552 %}
5553
5554 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
5555 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
5556 match(Set dst (AndI (LoadI mem) mask));
5557
5558 ins_cost(125);
5559 format %{ "MOVZX $dst, $mem\t# int -> ushort/char" %}
5560 ins_encode %{
5561 __ movzwl($dst$$Register, $mem$$Address);
5562 %}
5563 ins_pipe(ialu_reg_mem);
5564 %}
5565
5566 // Load Integer into Long Register
5567 instruct loadI2L(eRegL dst, memory mem, eFlagsReg cr) %{
5568 match(Set dst (ConvI2L (LoadI mem)));
5569 effect(KILL cr);
5570
5571 ins_cost(375);
5572 format %{ "MOV $dst.lo,$mem\t# int -> long\n\t"
5573 "MOV $dst.hi,$dst.lo\n\t"
5574 "SAR $dst.hi,31" %}
5575
5576 ins_encode %{
5577 __ movl($dst$$Register, $mem$$Address);
5578 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5579 __ sarl(HIGH_FROM_LOW($dst$$Register), 31);
5580 %}
5581
5582 ins_pipe(ialu_reg_mem);
5583 %}
5584
5585 // Load Integer with mask 0xFF into Long Register
5586 instruct loadI2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
5587 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5588 effect(KILL cr);
5589
5590 format %{ "MOVZX8 $dst.lo,$mem\t# int & 0xFF -> long\n\t"
5591 "XOR $dst.hi,$dst.hi" %}
5592 ins_encode %{
5593 Register Rdst = $dst$$Register;
5594 __ movzbl(Rdst, $mem$$Address);
5595 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5596 %}
5597 ins_pipe(ialu_reg_mem);
5598 %}
5599
5600 // Load Integer with mask 0xFFFF into Long Register
5601 instruct loadI2L_immI_65535(eRegL dst, memory mem, immI_65535 mask, eFlagsReg cr) %{
5602 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5603 effect(KILL cr);
5604
5605 format %{ "MOVZX $dst.lo,$mem\t# int & 0xFFFF -> long\n\t"
5606 "XOR $dst.hi,$dst.hi" %}
5607 ins_encode %{
5608 Register Rdst = $dst$$Register;
5609 __ movzwl(Rdst, $mem$$Address);
5610 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5611 %}
5612 ins_pipe(ialu_reg_mem);
5613 %}
5614
5615 // Load Integer with 31-bit mask into Long Register
5616 instruct loadI2L_immU31(eRegL dst, memory mem, immU31 mask, eFlagsReg cr) %{
5617 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5618 effect(KILL cr);
5619
5620 format %{ "MOV $dst.lo,$mem\t# int & 31-bit mask -> long\n\t"
5621 "XOR $dst.hi,$dst.hi\n\t"
5622 "AND $dst.lo,$mask" %}
5623 ins_encode %{
5624 Register Rdst = $dst$$Register;
5625 __ movl(Rdst, $mem$$Address);
5626 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5627 __ andl(Rdst, $mask$$constant);
5628 %}
5629 ins_pipe(ialu_reg_mem);
5630 %}
5631
5632 // Load Unsigned Integer into Long Register
5633 instruct loadUI2L(eRegL dst, memory mem, immL_32bits mask, eFlagsReg cr) %{
5634 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5635 effect(KILL cr);
5636
5637 ins_cost(250);
5638 format %{ "MOV $dst.lo,$mem\t# uint -> long\n\t"
5639 "XOR $dst.hi,$dst.hi" %}
5640
5641 ins_encode %{
5642 __ movl($dst$$Register, $mem$$Address);
5643 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
5644 %}
5645
5646 ins_pipe(ialu_reg_mem);
5647 %}
5648
5649 // Load Long. Cannot clobber address while loading, so restrict address
5650 // register to ESI
5651 instruct loadL(eRegL dst, load_long_memory mem) %{
5652 predicate(!((LoadLNode*)n)->require_atomic_access());
5653 match(Set dst (LoadL mem));
5654
5655 ins_cost(250);
5656 format %{ "MOV $dst.lo,$mem\t# long\n\t"
5657 "MOV $dst.hi,$mem+4" %}
5658
5659 ins_encode %{
5660 Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none);
5661 Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none);
5662 __ movl($dst$$Register, Amemlo);
5663 __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi);
5664 %}
5665
5666 ins_pipe(ialu_reg_long_mem);
5667 %}
5668
5669 // Volatile Load Long. Must be atomic, so do 64-bit FILD
5670 // then store it down to the stack and reload on the int
5671 // side.
5672 instruct loadL_volatile(stackSlotL dst, memory mem) %{
5673 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access());
5674 match(Set dst (LoadL mem));
5675
5676 ins_cost(200);
5677 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
5678 "FISTp $dst" %}
5679 ins_encode(enc_loadL_volatile(mem,dst));
5680 ins_pipe( fpu_reg_mem );
5681 %}
5682
5683 instruct loadLX_volatile(stackSlotL dst, memory mem, regD tmp) %{
5684 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
5685 match(Set dst (LoadL mem));
5686 effect(TEMP tmp);
5687 ins_cost(180);
5688 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
5689 "MOVSD $dst,$tmp" %}
5690 ins_encode %{
5691 __ movdbl($tmp$$XMMRegister, $mem$$Address);
5692 __ movdbl(Address(rsp, $dst$$disp), $tmp$$XMMRegister);
5693 %}
5694 ins_pipe( pipe_slow );
5695 %}
5696
5697 instruct loadLX_reg_volatile(eRegL dst, memory mem, regD tmp) %{
5698 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
5699 match(Set dst (LoadL mem));
5700 effect(TEMP tmp);
5701 ins_cost(160);
5702 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
5703 "MOVD $dst.lo,$tmp\n\t"
5704 "PSRLQ $tmp,32\n\t"
5705 "MOVD $dst.hi,$tmp" %}
5706 ins_encode %{
5707 __ movdbl($tmp$$XMMRegister, $mem$$Address);
5708 __ movdl($dst$$Register, $tmp$$XMMRegister);
5709 __ psrlq($tmp$$XMMRegister, 32);
5710 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
5711 %}
5712 ins_pipe( pipe_slow );
5713 %}
5714
5715 // Load Range
5716 instruct loadRange(rRegI dst, memory mem) %{
5717 match(Set dst (LoadRange mem));
5718
5719 ins_cost(125);
5720 format %{ "MOV $dst,$mem" %}
5721 opcode(0x8B);
5722 ins_encode( OpcP, RegMem(dst,mem));
5723 ins_pipe( ialu_reg_mem );
5724 %}
5725
5726
5727 // Load Pointer
5728 instruct loadP(eRegP dst, memory mem) %{
5729 match(Set dst (LoadP mem));
5730
5731 ins_cost(125);
5732 format %{ "MOV $dst,$mem" %}
5733 opcode(0x8B);
5734 ins_encode( OpcP, RegMem(dst,mem));
5735 ins_pipe( ialu_reg_mem );
5736 %}
5737
5738 // Load Klass Pointer
5739 instruct loadKlass(eRegP dst, memory mem) %{
5740 match(Set dst (LoadKlass mem));
5741
5742 ins_cost(125);
5743 format %{ "MOV $dst,$mem" %}
5744 opcode(0x8B);
5745 ins_encode( OpcP, RegMem(dst,mem));
5746 ins_pipe( ialu_reg_mem );
5747 %}
5748
5749 // Load Double
5750 instruct loadDPR(regDPR dst, memory mem) %{
5751 predicate(UseSSE<=1);
5752 match(Set dst (LoadD mem));
5753
5754 ins_cost(150);
5755 format %{ "FLD_D ST,$mem\n\t"
5756 "FSTP $dst" %}
5757 opcode(0xDD); /* DD /0 */
5758 ins_encode( OpcP, RMopc_Mem(0x00,mem),
5759 Pop_Reg_DPR(dst) );
5760 ins_pipe( fpu_reg_mem );
5761 %}
5762
5763 // Load Double to XMM
5764 instruct loadD(regD dst, memory mem) %{
5765 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
5766 match(Set dst (LoadD mem));
5767 ins_cost(145);
5768 format %{ "MOVSD $dst,$mem" %}
5769 ins_encode %{
5770 __ movdbl ($dst$$XMMRegister, $mem$$Address);
5771 %}
5772 ins_pipe( pipe_slow );
5773 %}
5774
5775 instruct loadD_partial(regD dst, memory mem) %{
5776 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
5777 match(Set dst (LoadD mem));
5778 ins_cost(145);
5779 format %{ "MOVLPD $dst,$mem" %}
5780 ins_encode %{
5781 __ movdbl ($dst$$XMMRegister, $mem$$Address);
5782 %}
5783 ins_pipe( pipe_slow );
5784 %}
5785
5786 // Load to XMM register (single-precision floating point)
5787 // MOVSS instruction
5788 instruct loadF(regF dst, memory mem) %{
5789 predicate(UseSSE>=1);
5790 match(Set dst (LoadF mem));
5791 ins_cost(145);
5792 format %{ "MOVSS $dst,$mem" %}
5793 ins_encode %{
5794 __ movflt ($dst$$XMMRegister, $mem$$Address);
5795 %}
5796 ins_pipe( pipe_slow );
5797 %}
5798
5799 // Load Float
5800 instruct loadFPR(regFPR dst, memory mem) %{
5801 predicate(UseSSE==0);
5802 match(Set dst (LoadF mem));
5803
5804 ins_cost(150);
5805 format %{ "FLD_S ST,$mem\n\t"
5806 "FSTP $dst" %}
5807 opcode(0xD9); /* D9 /0 */
5808 ins_encode( OpcP, RMopc_Mem(0x00,mem),
5809 Pop_Reg_FPR(dst) );
5810 ins_pipe( fpu_reg_mem );
5811 %}
5812
5813 // Load Effective Address
5814 instruct leaP8(eRegP dst, indOffset8 mem) %{
5815 match(Set dst mem);
5816
5817 ins_cost(110);
5818 format %{ "LEA $dst,$mem" %}
5819 opcode(0x8D);
5820 ins_encode( OpcP, RegMem(dst,mem));
5821 ins_pipe( ialu_reg_reg_fat );
5822 %}
5823
5824 instruct leaP32(eRegP dst, indOffset32 mem) %{
5825 match(Set dst mem);
5826
5827 ins_cost(110);
5828 format %{ "LEA $dst,$mem" %}
5829 opcode(0x8D);
5830 ins_encode( OpcP, RegMem(dst,mem));
5831 ins_pipe( ialu_reg_reg_fat );
5832 %}
5833
5834 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{
5835 match(Set dst mem);
5836
5837 ins_cost(110);
5838 format %{ "LEA $dst,$mem" %}
5839 opcode(0x8D);
5840 ins_encode( OpcP, RegMem(dst,mem));
5841 ins_pipe( ialu_reg_reg_fat );
5842 %}
5843
5844 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{
5845 match(Set dst mem);
5846
5847 ins_cost(110);
5848 format %{ "LEA $dst,$mem" %}
5849 opcode(0x8D);
5850 ins_encode( OpcP, RegMem(dst,mem));
5851 ins_pipe( ialu_reg_reg_fat );
5852 %}
5853
5854 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{
5855 match(Set dst mem);
5856
5857 ins_cost(110);
5858 format %{ "LEA $dst,$mem" %}
5859 opcode(0x8D);
5860 ins_encode( OpcP, RegMem(dst,mem));
5861 ins_pipe( ialu_reg_reg_fat );
5862 %}
5863
5864 // Load Constant
5865 instruct loadConI(rRegI dst, immI src) %{
5866 match(Set dst src);
5867
5868 format %{ "MOV $dst,$src" %}
5869 ins_encode( LdImmI(dst, src) );
5870 ins_pipe( ialu_reg_fat );
5871 %}
5872
5873 // Load Constant zero
5874 instruct loadConI0(rRegI dst, immI0 src, eFlagsReg cr) %{
5875 match(Set dst src);
5876 effect(KILL cr);
5877
5878 ins_cost(50);
5879 format %{ "XOR $dst,$dst" %}
5880 opcode(0x33); /* + rd */
5881 ins_encode( OpcP, RegReg( dst, dst ) );
5882 ins_pipe( ialu_reg );
5883 %}
5884
5885 instruct loadConP(eRegP dst, immP src) %{
5886 match(Set dst src);
5887
5888 format %{ "MOV $dst,$src" %}
5889 opcode(0xB8); /* + rd */
5890 ins_encode( LdImmP(dst, src) );
5891 ins_pipe( ialu_reg_fat );
5892 %}
5893
5894 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{
5895 match(Set dst src);
5896 effect(KILL cr);
5897 ins_cost(200);
5898 format %{ "MOV $dst.lo,$src.lo\n\t"
5899 "MOV $dst.hi,$src.hi" %}
5900 opcode(0xB8);
5901 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) );
5902 ins_pipe( ialu_reg_long_fat );
5903 %}
5904
5905 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{
5906 match(Set dst src);
5907 effect(KILL cr);
5908 ins_cost(150);
5909 format %{ "XOR $dst.lo,$dst.lo\n\t"
5910 "XOR $dst.hi,$dst.hi" %}
5911 opcode(0x33,0x33);
5912 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) );
5913 ins_pipe( ialu_reg_long );
5914 %}
5915
5916 // The instruction usage is guarded by predicate in operand immFPR().
5917 instruct loadConFPR(regFPR dst, immFPR con) %{
5918 match(Set dst con);
5919 ins_cost(125);
5920 format %{ "FLD_S ST,[$constantaddress]\t# load from constant table: float=$con\n\t"
5921 "FSTP $dst" %}
5922 ins_encode %{
5923 __ fld_s($constantaddress($con));
5924 __ fstp_d($dst$$reg);
5925 %}
5926 ins_pipe(fpu_reg_con);
5927 %}
5928
5929 // The instruction usage is guarded by predicate in operand immFPR0().
5930 instruct loadConFPR0(regFPR dst, immFPR0 con) %{
5931 match(Set dst con);
5932 ins_cost(125);
5933 format %{ "FLDZ ST\n\t"
5934 "FSTP $dst" %}
5935 ins_encode %{
5936 __ fldz();
5937 __ fstp_d($dst$$reg);
5938 %}
5939 ins_pipe(fpu_reg_con);
5940 %}
5941
5942 // The instruction usage is guarded by predicate in operand immFPR1().
5943 instruct loadConFPR1(regFPR dst, immFPR1 con) %{
5944 match(Set dst con);
5945 ins_cost(125);
5946 format %{ "FLD1 ST\n\t"
5947 "FSTP $dst" %}
5948 ins_encode %{
5949 __ fld1();
5950 __ fstp_d($dst$$reg);
5951 %}
5952 ins_pipe(fpu_reg_con);
5953 %}
5954
5955 // The instruction usage is guarded by predicate in operand immF().
5956 instruct loadConF(regF dst, immF con) %{
5957 match(Set dst con);
5958 ins_cost(125);
5959 format %{ "MOVSS $dst,[$constantaddress]\t# load from constant table: float=$con" %}
5960 ins_encode %{
5961 __ movflt($dst$$XMMRegister, $constantaddress($con));
5962 %}
5963 ins_pipe(pipe_slow);
5964 %}
5965
5966 // The instruction usage is guarded by predicate in operand immF0().
5967 instruct loadConF0(regF dst, immF0 src) %{
5968 match(Set dst src);
5969 ins_cost(100);
5970 format %{ "XORPS $dst,$dst\t# float 0.0" %}
5971 ins_encode %{
5972 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
5973 %}
5974 ins_pipe(pipe_slow);
5975 %}
5976
5977 // The instruction usage is guarded by predicate in operand immDPR().
5978 instruct loadConDPR(regDPR dst, immDPR con) %{
5979 match(Set dst con);
5980 ins_cost(125);
5981
5982 format %{ "FLD_D ST,[$constantaddress]\t# load from constant table: double=$con\n\t"
5983 "FSTP $dst" %}
5984 ins_encode %{
5985 __ fld_d($constantaddress($con));
5986 __ fstp_d($dst$$reg);
5987 %}
5988 ins_pipe(fpu_reg_con);
5989 %}
5990
5991 // The instruction usage is guarded by predicate in operand immDPR0().
5992 instruct loadConDPR0(regDPR dst, immDPR0 con) %{
5993 match(Set dst con);
5994 ins_cost(125);
5995
5996 format %{ "FLDZ ST\n\t"
5997 "FSTP $dst" %}
5998 ins_encode %{
5999 __ fldz();
6000 __ fstp_d($dst$$reg);
6001 %}
6002 ins_pipe(fpu_reg_con);
6003 %}
6004
6005 // The instruction usage is guarded by predicate in operand immDPR1().
6006 instruct loadConDPR1(regDPR dst, immDPR1 con) %{
6007 match(Set dst con);
6008 ins_cost(125);
6009
6010 format %{ "FLD1 ST\n\t"
6011 "FSTP $dst" %}
6012 ins_encode %{
6013 __ fld1();
6014 __ fstp_d($dst$$reg);
6015 %}
6016 ins_pipe(fpu_reg_con);
6017 %}
6018
6019 // The instruction usage is guarded by predicate in operand immD().
6020 instruct loadConD(regD dst, immD con) %{
6021 match(Set dst con);
6022 ins_cost(125);
6023 format %{ "MOVSD $dst,[$constantaddress]\t# load from constant table: double=$con" %}
6024 ins_encode %{
6025 __ movdbl($dst$$XMMRegister, $constantaddress($con));
6026 %}
6027 ins_pipe(pipe_slow);
6028 %}
6029
6030 // The instruction usage is guarded by predicate in operand immD0().
6031 instruct loadConD0(regD dst, immD0 src) %{
6032 match(Set dst src);
6033 ins_cost(100);
6034 format %{ "XORPD $dst,$dst\t# double 0.0" %}
6035 ins_encode %{
6036 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
6037 %}
6038 ins_pipe( pipe_slow );
6039 %}
6040
6041 // Load Stack Slot
6042 instruct loadSSI(rRegI dst, stackSlotI src) %{
6043 match(Set dst src);
6044 ins_cost(125);
6045
6046 format %{ "MOV $dst,$src" %}
6047 opcode(0x8B);
6048 ins_encode( OpcP, RegMem(dst,src));
6049 ins_pipe( ialu_reg_mem );
6050 %}
6051
6052 instruct loadSSL(eRegL dst, stackSlotL src) %{
6053 match(Set dst src);
6054
6055 ins_cost(200);
6056 format %{ "MOV $dst,$src.lo\n\t"
6057 "MOV $dst+4,$src.hi" %}
6058 opcode(0x8B, 0x8B);
6059 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) );
6060 ins_pipe( ialu_mem_long_reg );
6061 %}
6062
6063 // Load Stack Slot
6064 instruct loadSSP(eRegP dst, stackSlotP src) %{
6065 match(Set dst src);
6066 ins_cost(125);
6067
6068 format %{ "MOV $dst,$src" %}
6069 opcode(0x8B);
6070 ins_encode( OpcP, RegMem(dst,src));
6071 ins_pipe( ialu_reg_mem );
6072 %}
6073
6074 // Load Stack Slot
6075 instruct loadSSF(regFPR dst, stackSlotF src) %{
6076 match(Set dst src);
6077 ins_cost(125);
6078
6079 format %{ "FLD_S $src\n\t"
6080 "FSTP $dst" %}
6081 opcode(0xD9); /* D9 /0, FLD m32real */
6082 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6083 Pop_Reg_FPR(dst) );
6084 ins_pipe( fpu_reg_mem );
6085 %}
6086
6087 // Load Stack Slot
6088 instruct loadSSD(regDPR dst, stackSlotD src) %{
6089 match(Set dst src);
6090 ins_cost(125);
6091
6092 format %{ "FLD_D $src\n\t"
6093 "FSTP $dst" %}
6094 opcode(0xDD); /* DD /0, FLD m64real */
6095 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6096 Pop_Reg_DPR(dst) );
6097 ins_pipe( fpu_reg_mem );
6098 %}
6099
6100 // Prefetch instructions.
6101 // Must be safe to execute with invalid address (cannot fault).
6102
6103 instruct prefetchr0( memory mem ) %{
6104 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
6105 match(PrefetchRead mem);
6106 ins_cost(0);
6107 size(0);
6108 format %{ "PREFETCHR (non-SSE is empty encoding)" %}
6109 ins_encode();
6110 ins_pipe(empty);
6111 %}
6112
6113 instruct prefetchr( memory mem ) %{
6114 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch() || ReadPrefetchInstr==3);
6115 match(PrefetchRead mem);
6116 ins_cost(100);
6117
6118 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %}
6119 ins_encode %{
6120 __ prefetchr($mem$$Address);
6121 %}
6122 ins_pipe(ialu_mem);
6123 %}
6124
6125 instruct prefetchrNTA( memory mem ) %{
6126 predicate(UseSSE>=1 && ReadPrefetchInstr==0);
6127 match(PrefetchRead mem);
6128 ins_cost(100);
6129
6130 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %}
6131 ins_encode %{
6132 __ prefetchnta($mem$$Address);
6133 %}
6134 ins_pipe(ialu_mem);
6135 %}
6136
6137 instruct prefetchrT0( memory mem ) %{
6138 predicate(UseSSE>=1 && ReadPrefetchInstr==1);
6139 match(PrefetchRead mem);
6140 ins_cost(100);
6141
6142 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %}
6143 ins_encode %{
6144 __ prefetcht0($mem$$Address);
6145 %}
6146 ins_pipe(ialu_mem);
6147 %}
6148
6149 instruct prefetchrT2( memory mem ) %{
6150 predicate(UseSSE>=1 && ReadPrefetchInstr==2);
6151 match(PrefetchRead mem);
6152 ins_cost(100);
6153
6154 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %}
6155 ins_encode %{
6156 __ prefetcht2($mem$$Address);
6157 %}
6158 ins_pipe(ialu_mem);
6159 %}
6160
6161 instruct prefetchw0( memory mem ) %{
6162 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
6163 match(PrefetchWrite mem);
6164 ins_cost(0);
6165 size(0);
6166 format %{ "Prefetch (non-SSE is empty encoding)" %}
6167 ins_encode();
6168 ins_pipe(empty);
6169 %}
6170
6171 instruct prefetchw( memory mem ) %{
6172 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch());
6173 match( PrefetchWrite mem );
6174 ins_cost(100);
6175
6176 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %}
6177 ins_encode %{
6178 __ prefetchw($mem$$Address);
6179 %}
6180 ins_pipe(ialu_mem);
6181 %}
6182
6183 instruct prefetchwNTA( memory mem ) %{
6184 predicate(UseSSE>=1);
6185 match(PrefetchWrite mem);
6186 ins_cost(100);
6187
6188 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %}
6189 ins_encode %{
6190 __ prefetchnta($mem$$Address);
6191 %}
6192 ins_pipe(ialu_mem);
6193 %}
6194
6195 // Prefetch instructions for allocation.
6196
6197 instruct prefetchAlloc0( memory mem ) %{
6198 predicate(UseSSE==0 && AllocatePrefetchInstr!=3);
6199 match(PrefetchAllocation mem);
6200 ins_cost(0);
6201 size(0);
6202 format %{ "Prefetch allocation (non-SSE is empty encoding)" %}
6203 ins_encode();
6204 ins_pipe(empty);
6205 %}
6206
6207 instruct prefetchAlloc( memory mem ) %{
6208 predicate(AllocatePrefetchInstr==3);
6209 match( PrefetchAllocation mem );
6210 ins_cost(100);
6211
6212 format %{ "PREFETCHW $mem\t! Prefetch allocation into L1 cache and mark modified" %}
6213 ins_encode %{
6214 __ prefetchw($mem$$Address);
6215 %}
6216 ins_pipe(ialu_mem);
6217 %}
6218
6219 instruct prefetchAllocNTA( memory mem ) %{
6220 predicate(UseSSE>=1 && AllocatePrefetchInstr==0);
6221 match(PrefetchAllocation mem);
6222 ins_cost(100);
6223
6224 format %{ "PREFETCHNTA $mem\t! Prefetch allocation into non-temporal cache for write" %}
6225 ins_encode %{
6226 __ prefetchnta($mem$$Address);
6227 %}
6228 ins_pipe(ialu_mem);
6229 %}
6230
6231 instruct prefetchAllocT0( memory mem ) %{
6232 predicate(UseSSE>=1 && AllocatePrefetchInstr==1);
6233 match(PrefetchAllocation mem);
6234 ins_cost(100);
6235
6236 format %{ "PREFETCHT0 $mem\t! Prefetch allocation into L1 and L2 caches for write" %}
6237 ins_encode %{
6238 __ prefetcht0($mem$$Address);
6239 %}
6240 ins_pipe(ialu_mem);
6241 %}
6242
6243 instruct prefetchAllocT2( memory mem ) %{
6244 predicate(UseSSE>=1 && AllocatePrefetchInstr==2);
6245 match(PrefetchAllocation mem);
6246 ins_cost(100);
6247
6248 format %{ "PREFETCHT2 $mem\t! Prefetch allocation into L2 cache for write" %}
6249 ins_encode %{
6250 __ prefetcht2($mem$$Address);
6251 %}
6252 ins_pipe(ialu_mem);
6253 %}
6254
6255 //----------Store Instructions-------------------------------------------------
6256
6257 // Store Byte
6258 instruct storeB(memory mem, xRegI src) %{
6259 match(Set mem (StoreB mem src));
6260
6261 ins_cost(125);
6262 format %{ "MOV8 $mem,$src" %}
6263 opcode(0x88);
6264 ins_encode( OpcP, RegMem( src, mem ) );
6265 ins_pipe( ialu_mem_reg );
6266 %}
6267
6268 // Store Char/Short
6269 instruct storeC(memory mem, rRegI src) %{
6270 match(Set mem (StoreC mem src));
6271
6272 ins_cost(125);
6273 format %{ "MOV16 $mem,$src" %}
6274 opcode(0x89, 0x66);
6275 ins_encode( OpcS, OpcP, RegMem( src, mem ) );
6276 ins_pipe( ialu_mem_reg );
6277 %}
6278
6279 // Store Integer
6280 instruct storeI(memory mem, rRegI src) %{
6281 match(Set mem (StoreI mem src));
6282
6283 ins_cost(125);
6284 format %{ "MOV $mem,$src" %}
6285 opcode(0x89);
6286 ins_encode( OpcP, RegMem( src, mem ) );
6287 ins_pipe( ialu_mem_reg );
6288 %}
6289
6290 // Store Long
6291 instruct storeL(long_memory mem, eRegL src) %{
6292 predicate(!((StoreLNode*)n)->require_atomic_access());
6293 match(Set mem (StoreL mem src));
6294
6295 ins_cost(200);
6296 format %{ "MOV $mem,$src.lo\n\t"
6297 "MOV $mem+4,$src.hi" %}
6298 opcode(0x89, 0x89);
6299 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) );
6300 ins_pipe( ialu_mem_long_reg );
6301 %}
6302
6303 // Store Long to Integer
6304 instruct storeL2I(memory mem, eRegL src) %{
6305 match(Set mem (StoreI mem (ConvL2I src)));
6306
6307 format %{ "MOV $mem,$src.lo\t# long -> int" %}
6308 ins_encode %{
6309 __ movl($mem$$Address, $src$$Register);
6310 %}
6311 ins_pipe(ialu_mem_reg);
6312 %}
6313
6314 // Volatile Store Long. Must be atomic, so move it into
6315 // the FP TOS and then do a 64-bit FIST. Has to probe the
6316 // target address before the store (for null-ptr checks)
6317 // so the memory operand is used twice in the encoding.
6318 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{
6319 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access());
6320 match(Set mem (StoreL mem src));
6321 effect( KILL cr );
6322 ins_cost(400);
6323 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6324 "FILD $src\n\t"
6325 "FISTp $mem\t # 64-bit atomic volatile long store" %}
6326 opcode(0x3B);
6327 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src));
6328 ins_pipe( fpu_reg_mem );
6329 %}
6330
6331 instruct storeLX_volatile(memory mem, stackSlotL src, regD tmp, eFlagsReg cr) %{
6332 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6333 match(Set mem (StoreL mem src));
6334 effect( TEMP tmp, KILL cr );
6335 ins_cost(380);
6336 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6337 "MOVSD $tmp,$src\n\t"
6338 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
6339 ins_encode %{
6340 __ cmpl(rax, $mem$$Address);
6341 __ movdbl($tmp$$XMMRegister, Address(rsp, $src$$disp));
6342 __ movdbl($mem$$Address, $tmp$$XMMRegister);
6343 %}
6344 ins_pipe( pipe_slow );
6345 %}
6346
6347 instruct storeLX_reg_volatile(memory mem, eRegL src, regD tmp2, regD tmp, eFlagsReg cr) %{
6348 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6349 match(Set mem (StoreL mem src));
6350 effect( TEMP tmp2 , TEMP tmp, KILL cr );
6351 ins_cost(360);
6352 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6353 "MOVD $tmp,$src.lo\n\t"
6354 "MOVD $tmp2,$src.hi\n\t"
6355 "PUNPCKLDQ $tmp,$tmp2\n\t"
6356 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
6357 ins_encode %{
6358 __ cmpl(rax, $mem$$Address);
6359 __ movdl($tmp$$XMMRegister, $src$$Register);
6360 __ movdl($tmp2$$XMMRegister, HIGH_FROM_LOW($src$$Register));
6361 __ punpckldq($tmp$$XMMRegister, $tmp2$$XMMRegister);
6362 __ movdbl($mem$$Address, $tmp$$XMMRegister);
6363 %}
6364 ins_pipe( pipe_slow );
6365 %}
6366
6367 // Store Pointer; for storing unknown oops and raw pointers
6368 instruct storeP(memory mem, anyRegP src) %{
6369 match(Set mem (StoreP mem src));
6370
6371 ins_cost(125);
6372 format %{ "MOV $mem,$src" %}
6373 opcode(0x89);
6374 ins_encode( OpcP, RegMem( src, mem ) );
6375 ins_pipe( ialu_mem_reg );
6376 %}
6377
6378 // Store Integer Immediate
6379 instruct storeImmI(memory mem, immI src) %{
6380 match(Set mem (StoreI mem src));
6381
6382 ins_cost(150);
6383 format %{ "MOV $mem,$src" %}
6384 opcode(0xC7); /* C7 /0 */
6385 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
6386 ins_pipe( ialu_mem_imm );
6387 %}
6388
6389 // Store Short/Char Immediate
6390 instruct storeImmI16(memory mem, immI16 src) %{
6391 predicate(UseStoreImmI16);
6392 match(Set mem (StoreC mem src));
6393
6394 ins_cost(150);
6395 format %{ "MOV16 $mem,$src" %}
6396 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
6397 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src ));
6398 ins_pipe( ialu_mem_imm );
6399 %}
6400
6401 // Store Pointer Immediate; null pointers or constant oops that do not
6402 // need card-mark barriers.
6403 instruct storeImmP(memory mem, immP src) %{
6404 match(Set mem (StoreP mem src));
6405
6406 ins_cost(150);
6407 format %{ "MOV $mem,$src" %}
6408 opcode(0xC7); /* C7 /0 */
6409 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
6410 ins_pipe( ialu_mem_imm );
6411 %}
6412
6413 // Store Byte Immediate
6414 instruct storeImmB(memory mem, immI8 src) %{
6415 match(Set mem (StoreB mem src));
6416
6417 ins_cost(150);
6418 format %{ "MOV8 $mem,$src" %}
6419 opcode(0xC6); /* C6 /0 */
6420 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
6421 ins_pipe( ialu_mem_imm );
6422 %}
6423
6424 // Store CMS card-mark Immediate
6425 instruct storeImmCM(memory mem, immI8 src) %{
6426 match(Set mem (StoreCM mem src));
6427
6428 ins_cost(150);
6429 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %}
6430 opcode(0xC6); /* C6 /0 */
6431 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
6432 ins_pipe( ialu_mem_imm );
6433 %}
6434
6435 // Store Double
6436 instruct storeDPR( memory mem, regDPR1 src) %{
6437 predicate(UseSSE<=1);
6438 match(Set mem (StoreD mem src));
6439
6440 ins_cost(100);
6441 format %{ "FST_D $mem,$src" %}
6442 opcode(0xDD); /* DD /2 */
6443 ins_encode( enc_FPR_store(mem,src) );
6444 ins_pipe( fpu_mem_reg );
6445 %}
6446
6447 // Store double does rounding on x86
6448 instruct storeDPR_rounded( memory mem, regDPR1 src) %{
6449 predicate(UseSSE<=1);
6450 match(Set mem (StoreD mem (RoundDouble src)));
6451
6452 ins_cost(100);
6453 format %{ "FST_D $mem,$src\t# round" %}
6454 opcode(0xDD); /* DD /2 */
6455 ins_encode( enc_FPR_store(mem,src) );
6456 ins_pipe( fpu_mem_reg );
6457 %}
6458
6459 // Store XMM register to memory (double-precision floating points)
6460 // MOVSD instruction
6461 instruct storeD(memory mem, regD src) %{
6462 predicate(UseSSE>=2);
6463 match(Set mem (StoreD mem src));
6464 ins_cost(95);
6465 format %{ "MOVSD $mem,$src" %}
6466 ins_encode %{
6467 __ movdbl($mem$$Address, $src$$XMMRegister);
6468 %}
6469 ins_pipe( pipe_slow );
6470 %}
6471
6472 // Store XMM register to memory (single-precision floating point)
6473 // MOVSS instruction
6474 instruct storeF(memory mem, regF src) %{
6475 predicate(UseSSE>=1);
6476 match(Set mem (StoreF mem src));
6477 ins_cost(95);
6478 format %{ "MOVSS $mem,$src" %}
6479 ins_encode %{
6480 __ movflt($mem$$Address, $src$$XMMRegister);
6481 %}
6482 ins_pipe( pipe_slow );
6483 %}
6484
6485 // Store Float
6486 instruct storeFPR( memory mem, regFPR1 src) %{
6487 predicate(UseSSE==0);
6488 match(Set mem (StoreF mem src));
6489
6490 ins_cost(100);
6491 format %{ "FST_S $mem,$src" %}
6492 opcode(0xD9); /* D9 /2 */
6493 ins_encode( enc_FPR_store(mem,src) );
6494 ins_pipe( fpu_mem_reg );
6495 %}
6496
6497 // Store Float does rounding on x86
6498 instruct storeFPR_rounded( memory mem, regFPR1 src) %{
6499 predicate(UseSSE==0);
6500 match(Set mem (StoreF mem (RoundFloat src)));
6501
6502 ins_cost(100);
6503 format %{ "FST_S $mem,$src\t# round" %}
6504 opcode(0xD9); /* D9 /2 */
6505 ins_encode( enc_FPR_store(mem,src) );
6506 ins_pipe( fpu_mem_reg );
6507 %}
6508
6509 // Store Float does rounding on x86
6510 instruct storeFPR_Drounded( memory mem, regDPR1 src) %{
6511 predicate(UseSSE<=1);
6512 match(Set mem (StoreF mem (ConvD2F src)));
6513
6514 ins_cost(100);
6515 format %{ "FST_S $mem,$src\t# D-round" %}
6516 opcode(0xD9); /* D9 /2 */
6517 ins_encode( enc_FPR_store(mem,src) );
6518 ins_pipe( fpu_mem_reg );
6519 %}
6520
6521 // Store immediate Float value (it is faster than store from FPU register)
6522 // The instruction usage is guarded by predicate in operand immFPR().
6523 instruct storeFPR_imm( memory mem, immFPR src) %{
6524 match(Set mem (StoreF mem src));
6525
6526 ins_cost(50);
6527 format %{ "MOV $mem,$src\t# store float" %}
6528 opcode(0xC7); /* C7 /0 */
6529 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32FPR_as_bits( src ));
6530 ins_pipe( ialu_mem_imm );
6531 %}
6532
6533 // Store immediate Float value (it is faster than store from XMM register)
6534 // The instruction usage is guarded by predicate in operand immF().
6535 instruct storeF_imm( memory mem, immF src) %{
6536 match(Set mem (StoreF mem src));
6537
6538 ins_cost(50);
6539 format %{ "MOV $mem,$src\t# store float" %}
6540 opcode(0xC7); /* C7 /0 */
6541 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src ));
6542 ins_pipe( ialu_mem_imm );
6543 %}
6544
6545 // Store Integer to stack slot
6546 instruct storeSSI(stackSlotI dst, rRegI src) %{
6547 match(Set dst src);
6548
6549 ins_cost(100);
6550 format %{ "MOV $dst,$src" %}
6551 opcode(0x89);
6552 ins_encode( OpcPRegSS( dst, src ) );
6553 ins_pipe( ialu_mem_reg );
6554 %}
6555
6556 // Store Integer to stack slot
6557 instruct storeSSP(stackSlotP dst, eRegP src) %{
6558 match(Set dst src);
6559
6560 ins_cost(100);
6561 format %{ "MOV $dst,$src" %}
6562 opcode(0x89);
6563 ins_encode( OpcPRegSS( dst, src ) );
6564 ins_pipe( ialu_mem_reg );
6565 %}
6566
6567 // Store Long to stack slot
6568 instruct storeSSL(stackSlotL dst, eRegL src) %{
6569 match(Set dst src);
6570
6571 ins_cost(200);
6572 format %{ "MOV $dst,$src.lo\n\t"
6573 "MOV $dst+4,$src.hi" %}
6574 opcode(0x89, 0x89);
6575 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
6576 ins_pipe( ialu_mem_long_reg );
6577 %}
6578
6579 //----------MemBar Instructions-----------------------------------------------
6580 // Memory barrier flavors
6581
6582 instruct membar_acquire() %{
6583 match(MemBarAcquire);
6584 match(LoadFence);
6585 ins_cost(400);
6586
6587 size(0);
6588 format %{ "MEMBAR-acquire ! (empty encoding)" %}
6589 ins_encode();
6590 ins_pipe(empty);
6591 %}
6592
6593 instruct membar_acquire_lock() %{
6594 match(MemBarAcquireLock);
6595 ins_cost(0);
6596
6597 size(0);
6598 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
6599 ins_encode( );
6600 ins_pipe(empty);
6601 %}
6602
6603 instruct membar_release() %{
6604 match(MemBarRelease);
6605 match(StoreFence);
6606 ins_cost(400);
6607
6608 size(0);
6609 format %{ "MEMBAR-release ! (empty encoding)" %}
6610 ins_encode( );
6611 ins_pipe(empty);
6612 %}
6613
6614 instruct membar_release_lock() %{
6615 match(MemBarReleaseLock);
6616 ins_cost(0);
6617
6618 size(0);
6619 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
6620 ins_encode( );
6621 ins_pipe(empty);
6622 %}
6623
6624 instruct membar_volatile(eFlagsReg cr) %{
6625 match(MemBarVolatile);
6626 effect(KILL cr);
6627 ins_cost(400);
6628
6629 format %{
6630 $$template
6631 if (os::is_MP()) {
6632 $$emit$$"LOCK ADDL [ESP + #0], 0\t! membar_volatile"
6633 } else {
6634 $$emit$$"MEMBAR-volatile ! (empty encoding)"
6635 }
6636 %}
6637 ins_encode %{
6638 __ membar(Assembler::StoreLoad);
6639 %}
6640 ins_pipe(pipe_slow);
6641 %}
6642
6643 instruct unnecessary_membar_volatile() %{
6644 match(MemBarVolatile);
6645 predicate(Matcher::post_store_load_barrier(n));
6646 ins_cost(0);
6647
6648 size(0);
6649 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
6650 ins_encode( );
6651 ins_pipe(empty);
6652 %}
6653
6654 instruct membar_storestore() %{
6655 match(MemBarStoreStore);
6656 ins_cost(0);
6657
6658 size(0);
6659 format %{ "MEMBAR-storestore (empty encoding)" %}
6660 ins_encode( );
6661 ins_pipe(empty);
6662 %}
6663
6664 //----------Move Instructions--------------------------------------------------
6665 instruct castX2P(eAXRegP dst, eAXRegI src) %{
6666 match(Set dst (CastX2P src));
6667 format %{ "# X2P $dst, $src" %}
6668 ins_encode( /*empty encoding*/ );
6669 ins_cost(0);
6670 ins_pipe(empty);
6671 %}
6672
6673 instruct castP2X(rRegI dst, eRegP src ) %{
6674 match(Set dst (CastP2X src));
6675 ins_cost(50);
6676 format %{ "MOV $dst, $src\t# CastP2X" %}
6677 ins_encode( enc_Copy( dst, src) );
6678 ins_pipe( ialu_reg_reg );
6679 %}
6680
6681 //----------Conditional Move---------------------------------------------------
6682 // Conditional move
6683 instruct jmovI_reg(cmpOp cop, eFlagsReg cr, rRegI dst, rRegI src) %{
6684 predicate(!VM_Version::supports_cmov() );
6685 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6686 ins_cost(200);
6687 format %{ "J$cop,us skip\t# signed cmove\n\t"
6688 "MOV $dst,$src\n"
6689 "skip:" %}
6690 ins_encode %{
6691 Label Lskip;
6692 // Invert sense of branch from sense of CMOV
6693 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6694 __ movl($dst$$Register, $src$$Register);
6695 __ bind(Lskip);
6696 %}
6697 ins_pipe( pipe_cmov_reg );
6698 %}
6699
6700 instruct jmovI_regU(cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src) %{
6701 predicate(!VM_Version::supports_cmov() );
6702 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6703 ins_cost(200);
6704 format %{ "J$cop,us skip\t# unsigned cmove\n\t"
6705 "MOV $dst,$src\n"
6706 "skip:" %}
6707 ins_encode %{
6708 Label Lskip;
6709 // Invert sense of branch from sense of CMOV
6710 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6711 __ movl($dst$$Register, $src$$Register);
6712 __ bind(Lskip);
6713 %}
6714 ins_pipe( pipe_cmov_reg );
6715 %}
6716
6717 instruct cmovI_reg(rRegI dst, rRegI src, eFlagsReg cr, cmpOp cop ) %{
6718 predicate(VM_Version::supports_cmov() );
6719 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6720 ins_cost(200);
6721 format %{ "CMOV$cop $dst,$src" %}
6722 opcode(0x0F,0x40);
6723 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
6724 ins_pipe( pipe_cmov_reg );
6725 %}
6726
6727 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src ) %{
6728 predicate(VM_Version::supports_cmov() );
6729 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6730 ins_cost(200);
6731 format %{ "CMOV$cop $dst,$src" %}
6732 opcode(0x0F,0x40);
6733 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
6734 ins_pipe( pipe_cmov_reg );
6735 %}
6736
6737 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, rRegI src ) %{
6738 predicate(VM_Version::supports_cmov() );
6739 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6740 ins_cost(200);
6741 expand %{
6742 cmovI_regU(cop, cr, dst, src);
6743 %}
6744 %}
6745
6746 // Conditional move
6747 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, rRegI dst, memory src) %{
6748 predicate(VM_Version::supports_cmov() );
6749 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6750 ins_cost(250);
6751 format %{ "CMOV$cop $dst,$src" %}
6752 opcode(0x0F,0x40);
6753 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
6754 ins_pipe( pipe_cmov_mem );
6755 %}
6756
6757 // Conditional move
6758 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, rRegI dst, memory src) %{
6759 predicate(VM_Version::supports_cmov() );
6760 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6761 ins_cost(250);
6762 format %{ "CMOV$cop $dst,$src" %}
6763 opcode(0x0F,0x40);
6764 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
6765 ins_pipe( pipe_cmov_mem );
6766 %}
6767
6768 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, memory src) %{
6769 predicate(VM_Version::supports_cmov() );
6770 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6771 ins_cost(250);
6772 expand %{
6773 cmovI_memU(cop, cr, dst, src);
6774 %}
6775 %}
6776
6777 // Conditional move
6778 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
6779 predicate(VM_Version::supports_cmov() );
6780 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6781 ins_cost(200);
6782 format %{ "CMOV$cop $dst,$src\t# ptr" %}
6783 opcode(0x0F,0x40);
6784 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
6785 ins_pipe( pipe_cmov_reg );
6786 %}
6787
6788 // Conditional move (non-P6 version)
6789 // Note: a CMoveP is generated for stubs and native wrappers
6790 // regardless of whether we are on a P6, so we
6791 // emulate a cmov here
6792 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
6793 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6794 ins_cost(300);
6795 format %{ "Jn$cop skip\n\t"
6796 "MOV $dst,$src\t# pointer\n"
6797 "skip:" %}
6798 opcode(0x8b);
6799 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src));
6800 ins_pipe( pipe_cmov_reg );
6801 %}
6802
6803 // Conditional move
6804 instruct cmovP_regU(cmpOpU cop, eFlagsRegU cr, eRegP dst, eRegP src ) %{
6805 predicate(VM_Version::supports_cmov() );
6806 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6807 ins_cost(200);
6808 format %{ "CMOV$cop $dst,$src\t# ptr" %}
6809 opcode(0x0F,0x40);
6810 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
6811 ins_pipe( pipe_cmov_reg );
6812 %}
6813
6814 instruct cmovP_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegP dst, eRegP src ) %{
6815 predicate(VM_Version::supports_cmov() );
6816 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6817 ins_cost(200);
6818 expand %{
6819 cmovP_regU(cop, cr, dst, src);
6820 %}
6821 %}
6822
6823 // DISABLED: Requires the ADLC to emit a bottom_type call that
6824 // correctly meets the two pointer arguments; one is an incoming
6825 // register but the other is a memory operand. ALSO appears to
6826 // be buggy with implicit null checks.
6827 //
6828 //// Conditional move
6829 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{
6830 // predicate(VM_Version::supports_cmov() );
6831 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
6832 // ins_cost(250);
6833 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
6834 // opcode(0x0F,0x40);
6835 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
6836 // ins_pipe( pipe_cmov_mem );
6837 //%}
6838 //
6839 //// Conditional move
6840 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{
6841 // predicate(VM_Version::supports_cmov() );
6842 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
6843 // ins_cost(250);
6844 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
6845 // opcode(0x0F,0x40);
6846 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
6847 // ins_pipe( pipe_cmov_mem );
6848 //%}
6849
6850 // Conditional move
6851 instruct fcmovDPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regDPR src) %{
6852 predicate(UseSSE<=1);
6853 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6854 ins_cost(200);
6855 format %{ "FCMOV$cop $dst,$src\t# double" %}
6856 opcode(0xDA);
6857 ins_encode( enc_cmov_dpr(cop,src) );
6858 ins_pipe( pipe_cmovDPR_reg );
6859 %}
6860
6861 // Conditional move
6862 instruct fcmovFPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regFPR src) %{
6863 predicate(UseSSE==0);
6864 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6865 ins_cost(200);
6866 format %{ "FCMOV$cop $dst,$src\t# float" %}
6867 opcode(0xDA);
6868 ins_encode( enc_cmov_dpr(cop,src) );
6869 ins_pipe( pipe_cmovDPR_reg );
6870 %}
6871
6872 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
6873 instruct fcmovDPR_regS(cmpOp cop, eFlagsReg cr, regDPR dst, regDPR src) %{
6874 predicate(UseSSE<=1);
6875 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6876 ins_cost(200);
6877 format %{ "Jn$cop skip\n\t"
6878 "MOV $dst,$src\t# double\n"
6879 "skip:" %}
6880 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
6881 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_DPR(src), OpcP, RegOpc(dst) );
6882 ins_pipe( pipe_cmovDPR_reg );
6883 %}
6884
6885 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
6886 instruct fcmovFPR_regS(cmpOp cop, eFlagsReg cr, regFPR dst, regFPR src) %{
6887 predicate(UseSSE==0);
6888 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6889 ins_cost(200);
6890 format %{ "Jn$cop skip\n\t"
6891 "MOV $dst,$src\t# float\n"
6892 "skip:" %}
6893 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
6894 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_FPR(src), OpcP, RegOpc(dst) );
6895 ins_pipe( pipe_cmovDPR_reg );
6896 %}
6897
6898 // No CMOVE with SSE/SSE2
6899 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{
6900 predicate (UseSSE>=1);
6901 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6902 ins_cost(200);
6903 format %{ "Jn$cop skip\n\t"
6904 "MOVSS $dst,$src\t# float\n"
6905 "skip:" %}
6906 ins_encode %{
6907 Label skip;
6908 // Invert sense of branch from sense of CMOV
6909 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
6910 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
6911 __ bind(skip);
6912 %}
6913 ins_pipe( pipe_slow );
6914 %}
6915
6916 // No CMOVE with SSE/SSE2
6917 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{
6918 predicate (UseSSE>=2);
6919 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6920 ins_cost(200);
6921 format %{ "Jn$cop skip\n\t"
6922 "MOVSD $dst,$src\t# float\n"
6923 "skip:" %}
6924 ins_encode %{
6925 Label skip;
6926 // Invert sense of branch from sense of CMOV
6927 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
6928 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6929 __ bind(skip);
6930 %}
6931 ins_pipe( pipe_slow );
6932 %}
6933
6934 // unsigned version
6935 instruct fcmovF_regU(cmpOpU cop, eFlagsRegU cr, regF dst, regF src) %{
6936 predicate (UseSSE>=1);
6937 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6938 ins_cost(200);
6939 format %{ "Jn$cop skip\n\t"
6940 "MOVSS $dst,$src\t# float\n"
6941 "skip:" %}
6942 ins_encode %{
6943 Label skip;
6944 // Invert sense of branch from sense of CMOV
6945 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
6946 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
6947 __ bind(skip);
6948 %}
6949 ins_pipe( pipe_slow );
6950 %}
6951
6952 instruct fcmovF_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regF dst, regF src) %{
6953 predicate (UseSSE>=1);
6954 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6955 ins_cost(200);
6956 expand %{
6957 fcmovF_regU(cop, cr, dst, src);
6958 %}
6959 %}
6960
6961 // unsigned version
6962 instruct fcmovD_regU(cmpOpU cop, eFlagsRegU cr, regD dst, regD src) %{
6963 predicate (UseSSE>=2);
6964 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6965 ins_cost(200);
6966 format %{ "Jn$cop skip\n\t"
6967 "MOVSD $dst,$src\t# float\n"
6968 "skip:" %}
6969 ins_encode %{
6970 Label skip;
6971 // Invert sense of branch from sense of CMOV
6972 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
6973 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6974 __ bind(skip);
6975 %}
6976 ins_pipe( pipe_slow );
6977 %}
6978
6979 instruct fcmovD_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regD dst, regD src) %{
6980 predicate (UseSSE>=2);
6981 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6982 ins_cost(200);
6983 expand %{
6984 fcmovD_regU(cop, cr, dst, src);
6985 %}
6986 %}
6987
6988 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{
6989 predicate(VM_Version::supports_cmov() );
6990 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6991 ins_cost(200);
6992 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
6993 "CMOV$cop $dst.hi,$src.hi" %}
6994 opcode(0x0F,0x40);
6995 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
6996 ins_pipe( pipe_cmov_reg_long );
6997 %}
6998
6999 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{
7000 predicate(VM_Version::supports_cmov() );
7001 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7002 ins_cost(200);
7003 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7004 "CMOV$cop $dst.hi,$src.hi" %}
7005 opcode(0x0F,0x40);
7006 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7007 ins_pipe( pipe_cmov_reg_long );
7008 %}
7009
7010 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{
7011 predicate(VM_Version::supports_cmov() );
7012 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7013 ins_cost(200);
7014 expand %{
7015 cmovL_regU(cop, cr, dst, src);
7016 %}
7017 %}
7018
7019 //----------Arithmetic Instructions--------------------------------------------
7020 //----------Addition Instructions----------------------------------------------
7021
7022 // Integer Addition Instructions
7023 instruct addI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7024 match(Set dst (AddI dst src));
7025 effect(KILL cr);
7026
7027 size(2);
7028 format %{ "ADD $dst,$src" %}
7029 opcode(0x03);
7030 ins_encode( OpcP, RegReg( dst, src) );
7031 ins_pipe( ialu_reg_reg );
7032 %}
7033
7034 instruct addI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7035 match(Set dst (AddI dst src));
7036 effect(KILL cr);
7037
7038 format %{ "ADD $dst,$src" %}
7039 opcode(0x81, 0x00); /* /0 id */
7040 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7041 ins_pipe( ialu_reg );
7042 %}
7043
7044 instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
7045 predicate(UseIncDec);
7046 match(Set dst (AddI dst src));
7047 effect(KILL cr);
7048
7049 size(1);
7050 format %{ "INC $dst" %}
7051 opcode(0x40); /* */
7052 ins_encode( Opc_plus( primary, dst ) );
7053 ins_pipe( ialu_reg );
7054 %}
7055
7056 instruct leaI_eReg_immI(rRegI dst, rRegI src0, immI src1) %{
7057 match(Set dst (AddI src0 src1));
7058 ins_cost(110);
7059
7060 format %{ "LEA $dst,[$src0 + $src1]" %}
7061 opcode(0x8D); /* 0x8D /r */
7062 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7063 ins_pipe( ialu_reg_reg );
7064 %}
7065
7066 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{
7067 match(Set dst (AddP src0 src1));
7068 ins_cost(110);
7069
7070 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %}
7071 opcode(0x8D); /* 0x8D /r */
7072 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7073 ins_pipe( ialu_reg_reg );
7074 %}
7075
7076 instruct decI_eReg(rRegI dst, immI_M1 src, eFlagsReg cr) %{
7077 predicate(UseIncDec);
7078 match(Set dst (AddI dst src));
7079 effect(KILL cr);
7080
7081 size(1);
7082 format %{ "DEC $dst" %}
7083 opcode(0x48); /* */
7084 ins_encode( Opc_plus( primary, dst ) );
7085 ins_pipe( ialu_reg );
7086 %}
7087
7088 instruct addP_eReg(eRegP dst, rRegI src, eFlagsReg cr) %{
7089 match(Set dst (AddP dst src));
7090 effect(KILL cr);
7091
7092 size(2);
7093 format %{ "ADD $dst,$src" %}
7094 opcode(0x03);
7095 ins_encode( OpcP, RegReg( dst, src) );
7096 ins_pipe( ialu_reg_reg );
7097 %}
7098
7099 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{
7100 match(Set dst (AddP dst src));
7101 effect(KILL cr);
7102
7103 format %{ "ADD $dst,$src" %}
7104 opcode(0x81,0x00); /* Opcode 81 /0 id */
7105 // ins_encode( RegImm( dst, src) );
7106 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7107 ins_pipe( ialu_reg );
7108 %}
7109
7110 instruct addI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
7111 match(Set dst (AddI dst (LoadI src)));
7112 effect(KILL cr);
7113
7114 ins_cost(125);
7115 format %{ "ADD $dst,$src" %}
7116 opcode(0x03);
7117 ins_encode( OpcP, RegMem( dst, src) );
7118 ins_pipe( ialu_reg_mem );
7119 %}
7120
7121 instruct addI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
7122 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7123 effect(KILL cr);
7124
7125 ins_cost(150);
7126 format %{ "ADD $dst,$src" %}
7127 opcode(0x01); /* Opcode 01 /r */
7128 ins_encode( OpcP, RegMem( src, dst ) );
7129 ins_pipe( ialu_mem_reg );
7130 %}
7131
7132 // Add Memory with Immediate
7133 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
7134 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7135 effect(KILL cr);
7136
7137 ins_cost(125);
7138 format %{ "ADD $dst,$src" %}
7139 opcode(0x81); /* Opcode 81 /0 id */
7140 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) );
7141 ins_pipe( ialu_mem_imm );
7142 %}
7143
7144 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{
7145 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7146 effect(KILL cr);
7147
7148 ins_cost(125);
7149 format %{ "INC $dst" %}
7150 opcode(0xFF); /* Opcode FF /0 */
7151 ins_encode( OpcP, RMopc_Mem(0x00,dst));
7152 ins_pipe( ialu_mem_imm );
7153 %}
7154
7155 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{
7156 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7157 effect(KILL cr);
7158
7159 ins_cost(125);
7160 format %{ "DEC $dst" %}
7161 opcode(0xFF); /* Opcode FF /1 */
7162 ins_encode( OpcP, RMopc_Mem(0x01,dst));
7163 ins_pipe( ialu_mem_imm );
7164 %}
7165
7166
7167 instruct checkCastPP( eRegP dst ) %{
7168 match(Set dst (CheckCastPP dst));
7169
7170 size(0);
7171 format %{ "#checkcastPP of $dst" %}
7172 ins_encode( /*empty encoding*/ );
7173 ins_pipe( empty );
7174 %}
7175
7176 instruct castPP( eRegP dst ) %{
7177 match(Set dst (CastPP dst));
7178 format %{ "#castPP of $dst" %}
7179 ins_encode( /*empty encoding*/ );
7180 ins_pipe( empty );
7181 %}
7182
7183 instruct castII( rRegI dst ) %{
7184 match(Set dst (CastII dst));
7185 format %{ "#castII of $dst" %}
7186 ins_encode( /*empty encoding*/ );
7187 ins_cost(0);
7188 ins_pipe( empty );
7189 %}
7190
7191
7192 // Load-locked - same as a regular pointer load when used with compare-swap
7193 instruct loadPLocked(eRegP dst, memory mem) %{
7194 match(Set dst (LoadPLocked mem));
7195
7196 ins_cost(125);
7197 format %{ "MOV $dst,$mem\t# Load ptr. locked" %}
7198 opcode(0x8B);
7199 ins_encode( OpcP, RegMem(dst,mem));
7200 ins_pipe( ialu_reg_mem );
7201 %}
7202
7203 // Conditional-store of the updated heap-top.
7204 // Used during allocation of the shared heap.
7205 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
7206 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{
7207 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7208 // EAX is killed if there is contention, but then it's also unused.
7209 // In the common case of no contention, EAX holds the new oop address.
7210 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %}
7211 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) );
7212 ins_pipe( pipe_cmpxchg );
7213 %}
7214
7215 // Conditional-store of an int value.
7216 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel.
7217 instruct storeIConditional( memory mem, eAXRegI oldval, rRegI newval, eFlagsReg cr ) %{
7218 match(Set cr (StoreIConditional mem (Binary oldval newval)));
7219 effect(KILL oldval);
7220 format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %}
7221 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) );
7222 ins_pipe( pipe_cmpxchg );
7223 %}
7224
7225 // Conditional-store of a long value.
7226 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel.
7227 instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7228 match(Set cr (StoreLConditional mem (Binary oldval newval)));
7229 effect(KILL oldval);
7230 format %{ "XCHG EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t"
7231 "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t"
7232 "XCHG EBX,ECX"
7233 %}
7234 ins_encode %{
7235 // Note: we need to swap rbx, and rcx before and after the
7236 // cmpxchg8 instruction because the instruction uses
7237 // rcx as the high order word of the new value to store but
7238 // our register encoding uses rbx.
7239 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
7240 if( os::is_MP() )
7241 __ lock();
7242 __ cmpxchg8($mem$$Address);
7243 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
7244 %}
7245 ins_pipe( pipe_cmpxchg );
7246 %}
7247
7248 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7249
7250 instruct compareAndSwapL( rRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7251 predicate(VM_Version::supports_cx8());
7252 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7253 effect(KILL cr, KILL oldval);
7254 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7255 "MOV $res,0\n\t"
7256 "JNE,s fail\n\t"
7257 "MOV $res,1\n"
7258 "fail:" %}
7259 ins_encode( enc_cmpxchg8(mem_ptr),
7260 enc_flags_ne_to_boolean(res) );
7261 ins_pipe( pipe_cmpxchg );
7262 %}
7263
7264 instruct compareAndSwapP( rRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{
7265 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7266 effect(KILL cr, KILL oldval);
7267 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7268 "MOV $res,0\n\t"
7269 "JNE,s fail\n\t"
7270 "MOV $res,1\n"
7271 "fail:" %}
7272 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7273 ins_pipe( pipe_cmpxchg );
7274 %}
7275
7276 instruct compareAndSwapI( rRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{
7277 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7278 effect(KILL cr, KILL oldval);
7279 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7280 "MOV $res,0\n\t"
7281 "JNE,s fail\n\t"
7282 "MOV $res,1\n"
7283 "fail:" %}
7284 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7285 ins_pipe( pipe_cmpxchg );
7286 %}
7287
7288 instruct xaddI_no_res( memory mem, Universe dummy, immI add, eFlagsReg cr) %{
7289 predicate(n->as_LoadStore()->result_not_used());
7290 match(Set dummy (GetAndAddI mem add));
7291 effect(KILL cr);
7292 format %{ "ADDL [$mem],$add" %}
7293 ins_encode %{
7294 if (os::is_MP()) { __ lock(); }
7295 __ addl($mem$$Address, $add$$constant);
7296 %}
7297 ins_pipe( pipe_cmpxchg );
7298 %}
7299
7300 instruct xaddI( memory mem, rRegI newval, eFlagsReg cr) %{
7301 match(Set newval (GetAndAddI mem newval));
7302 effect(KILL cr);
7303 format %{ "XADDL [$mem],$newval" %}
7304 ins_encode %{
7305 if (os::is_MP()) { __ lock(); }
7306 __ xaddl($mem$$Address, $newval$$Register);
7307 %}
7308 ins_pipe( pipe_cmpxchg );
7309 %}
7310
7311 instruct xchgI( memory mem, rRegI newval) %{
7312 match(Set newval (GetAndSetI mem newval));
7313 format %{ "XCHGL $newval,[$mem]" %}
7314 ins_encode %{
7315 __ xchgl($newval$$Register, $mem$$Address);
7316 %}
7317 ins_pipe( pipe_cmpxchg );
7318 %}
7319
7320 instruct xchgP( memory mem, pRegP newval) %{
7321 match(Set newval (GetAndSetP mem newval));
7322 format %{ "XCHGL $newval,[$mem]" %}
7323 ins_encode %{
7324 __ xchgl($newval$$Register, $mem$$Address);
7325 %}
7326 ins_pipe( pipe_cmpxchg );
7327 %}
7328
7329 //----------Subtraction Instructions-------------------------------------------
7330
7331 // Integer Subtraction Instructions
7332 instruct subI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7333 match(Set dst (SubI dst src));
7334 effect(KILL cr);
7335
7336 size(2);
7337 format %{ "SUB $dst,$src" %}
7338 opcode(0x2B);
7339 ins_encode( OpcP, RegReg( dst, src) );
7340 ins_pipe( ialu_reg_reg );
7341 %}
7342
7343 instruct subI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7344 match(Set dst (SubI dst src));
7345 effect(KILL cr);
7346
7347 format %{ "SUB $dst,$src" %}
7348 opcode(0x81,0x05); /* Opcode 81 /5 */
7349 // ins_encode( RegImm( dst, src) );
7350 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7351 ins_pipe( ialu_reg );
7352 %}
7353
7354 instruct subI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
7355 match(Set dst (SubI dst (LoadI src)));
7356 effect(KILL cr);
7357
7358 ins_cost(125);
7359 format %{ "SUB $dst,$src" %}
7360 opcode(0x2B);
7361 ins_encode( OpcP, RegMem( dst, src) );
7362 ins_pipe( ialu_reg_mem );
7363 %}
7364
7365 instruct subI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
7366 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7367 effect(KILL cr);
7368
7369 ins_cost(150);
7370 format %{ "SUB $dst,$src" %}
7371 opcode(0x29); /* Opcode 29 /r */
7372 ins_encode( OpcP, RegMem( src, dst ) );
7373 ins_pipe( ialu_mem_reg );
7374 %}
7375
7376 // Subtract from a pointer
7377 instruct subP_eReg(eRegP dst, rRegI src, immI0 zero, eFlagsReg cr) %{
7378 match(Set dst (AddP dst (SubI zero src)));
7379 effect(KILL cr);
7380
7381 size(2);
7382 format %{ "SUB $dst,$src" %}
7383 opcode(0x2B);
7384 ins_encode( OpcP, RegReg( dst, src) );
7385 ins_pipe( ialu_reg_reg );
7386 %}
7387
7388 instruct negI_eReg(rRegI dst, immI0 zero, eFlagsReg cr) %{
7389 match(Set dst (SubI zero dst));
7390 effect(KILL cr);
7391
7392 size(2);
7393 format %{ "NEG $dst" %}
7394 opcode(0xF7,0x03); // Opcode F7 /3
7395 ins_encode( OpcP, RegOpc( dst ) );
7396 ins_pipe( ialu_reg );
7397 %}
7398
7399 //----------Multiplication/Division Instructions-------------------------------
7400 // Integer Multiplication Instructions
7401 // Multiply Register
7402 instruct mulI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7403 match(Set dst (MulI dst src));
7404 effect(KILL cr);
7405
7406 size(3);
7407 ins_cost(300);
7408 format %{ "IMUL $dst,$src" %}
7409 opcode(0xAF, 0x0F);
7410 ins_encode( OpcS, OpcP, RegReg( dst, src) );
7411 ins_pipe( ialu_reg_reg_alu0 );
7412 %}
7413
7414 // Multiply 32-bit Immediate
7415 instruct mulI_eReg_imm(rRegI dst, rRegI src, immI imm, eFlagsReg cr) %{
7416 match(Set dst (MulI src imm));
7417 effect(KILL cr);
7418
7419 ins_cost(300);
7420 format %{ "IMUL $dst,$src,$imm" %}
7421 opcode(0x69); /* 69 /r id */
7422 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) );
7423 ins_pipe( ialu_reg_reg_alu0 );
7424 %}
7425
7426 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{
7427 match(Set dst src);
7428 effect(KILL cr);
7429
7430 // Note that this is artificially increased to make it more expensive than loadConL
7431 ins_cost(250);
7432 format %{ "MOV EAX,$src\t// low word only" %}
7433 opcode(0xB8);
7434 ins_encode( LdImmL_Lo(dst, src) );
7435 ins_pipe( ialu_reg_fat );
7436 %}
7437
7438 // Multiply by 32-bit Immediate, taking the shifted high order results
7439 // (special case for shift by 32)
7440 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{
7441 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
7442 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
7443 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
7444 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
7445 effect(USE src1, KILL cr);
7446
7447 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
7448 ins_cost(0*100 + 1*400 - 150);
7449 format %{ "IMUL EDX:EAX,$src1" %}
7450 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
7451 ins_pipe( pipe_slow );
7452 %}
7453
7454 // Multiply by 32-bit Immediate, taking the shifted high order results
7455 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{
7456 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
7457 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
7458 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
7459 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
7460 effect(USE src1, KILL cr);
7461
7462 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
7463 ins_cost(1*100 + 1*400 - 150);
7464 format %{ "IMUL EDX:EAX,$src1\n\t"
7465 "SAR EDX,$cnt-32" %}
7466 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
7467 ins_pipe( pipe_slow );
7468 %}
7469
7470 // Multiply Memory 32-bit Immediate
7471 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, eFlagsReg cr) %{
7472 match(Set dst (MulI (LoadI src) imm));
7473 effect(KILL cr);
7474
7475 ins_cost(300);
7476 format %{ "IMUL $dst,$src,$imm" %}
7477 opcode(0x69); /* 69 /r id */
7478 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) );
7479 ins_pipe( ialu_reg_mem_alu0 );
7480 %}
7481
7482 // Multiply Memory
7483 instruct mulI(rRegI dst, memory src, eFlagsReg cr) %{
7484 match(Set dst (MulI dst (LoadI src)));
7485 effect(KILL cr);
7486
7487 ins_cost(350);
7488 format %{ "IMUL $dst,$src" %}
7489 opcode(0xAF, 0x0F);
7490 ins_encode( OpcS, OpcP, RegMem( dst, src) );
7491 ins_pipe( ialu_reg_mem_alu0 );
7492 %}
7493
7494 // Multiply Register Int to Long
7495 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{
7496 // Basic Idea: long = (long)int * (long)int
7497 match(Set dst (MulL (ConvI2L src) (ConvI2L src1)));
7498 effect(DEF dst, USE src, USE src1, KILL flags);
7499
7500 ins_cost(300);
7501 format %{ "IMUL $dst,$src1" %}
7502
7503 ins_encode( long_int_multiply( dst, src1 ) );
7504 ins_pipe( ialu_reg_reg_alu0 );
7505 %}
7506
7507 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{
7508 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
7509 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask)));
7510 effect(KILL flags);
7511
7512 ins_cost(300);
7513 format %{ "MUL $dst,$src1" %}
7514
7515 ins_encode( long_uint_multiply(dst, src1) );
7516 ins_pipe( ialu_reg_reg_alu0 );
7517 %}
7518
7519 // Multiply Register Long
7520 instruct mulL_eReg(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
7521 match(Set dst (MulL dst src));
7522 effect(KILL cr, TEMP tmp);
7523 ins_cost(4*100+3*400);
7524 // Basic idea: lo(result) = lo(x_lo * y_lo)
7525 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
7526 format %{ "MOV $tmp,$src.lo\n\t"
7527 "IMUL $tmp,EDX\n\t"
7528 "MOV EDX,$src.hi\n\t"
7529 "IMUL EDX,EAX\n\t"
7530 "ADD $tmp,EDX\n\t"
7531 "MUL EDX:EAX,$src.lo\n\t"
7532 "ADD EDX,$tmp" %}
7533 ins_encode( long_multiply( dst, src, tmp ) );
7534 ins_pipe( pipe_slow );
7535 %}
7536
7537 // Multiply Register Long where the left operand's high 32 bits are zero
7538 instruct mulL_eReg_lhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
7539 predicate(is_operand_hi32_zero(n->in(1)));
7540 match(Set dst (MulL dst src));
7541 effect(KILL cr, TEMP tmp);
7542 ins_cost(2*100+2*400);
7543 // Basic idea: lo(result) = lo(x_lo * y_lo)
7544 // hi(result) = hi(x_lo * y_lo) + lo(x_lo * y_hi) where lo(x_hi * y_lo) = 0 because x_hi = 0
7545 format %{ "MOV $tmp,$src.hi\n\t"
7546 "IMUL $tmp,EAX\n\t"
7547 "MUL EDX:EAX,$src.lo\n\t"
7548 "ADD EDX,$tmp" %}
7549 ins_encode %{
7550 __ movl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
7551 __ imull($tmp$$Register, rax);
7552 __ mull($src$$Register);
7553 __ addl(rdx, $tmp$$Register);
7554 %}
7555 ins_pipe( pipe_slow );
7556 %}
7557
7558 // Multiply Register Long where the right operand's high 32 bits are zero
7559 instruct mulL_eReg_rhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
7560 predicate(is_operand_hi32_zero(n->in(2)));
7561 match(Set dst (MulL dst src));
7562 effect(KILL cr, TEMP tmp);
7563 ins_cost(2*100+2*400);
7564 // Basic idea: lo(result) = lo(x_lo * y_lo)
7565 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) where lo(x_lo * y_hi) = 0 because y_hi = 0
7566 format %{ "MOV $tmp,$src.lo\n\t"
7567 "IMUL $tmp,EDX\n\t"
7568 "MUL EDX:EAX,$src.lo\n\t"
7569 "ADD EDX,$tmp" %}
7570 ins_encode %{
7571 __ movl($tmp$$Register, $src$$Register);
7572 __ imull($tmp$$Register, rdx);
7573 __ mull($src$$Register);
7574 __ addl(rdx, $tmp$$Register);
7575 %}
7576 ins_pipe( pipe_slow );
7577 %}
7578
7579 // Multiply Register Long where the left and the right operands' high 32 bits are zero
7580 instruct mulL_eReg_hi0(eADXRegL dst, eRegL src, eFlagsReg cr) %{
7581 predicate(is_operand_hi32_zero(n->in(1)) && is_operand_hi32_zero(n->in(2)));
7582 match(Set dst (MulL dst src));
7583 effect(KILL cr);
7584 ins_cost(1*400);
7585 // Basic idea: lo(result) = lo(x_lo * y_lo)
7586 // hi(result) = hi(x_lo * y_lo) where lo(x_hi * y_lo) = 0 and lo(x_lo * y_hi) = 0 because x_hi = 0 and y_hi = 0
7587 format %{ "MUL EDX:EAX,$src.lo\n\t" %}
7588 ins_encode %{
7589 __ mull($src$$Register);
7590 %}
7591 ins_pipe( pipe_slow );
7592 %}
7593
7594 // Multiply Register Long by small constant
7595 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, rRegI tmp, eFlagsReg cr) %{
7596 match(Set dst (MulL dst src));
7597 effect(KILL cr, TEMP tmp);
7598 ins_cost(2*100+2*400);
7599 size(12);
7600 // Basic idea: lo(result) = lo(src * EAX)
7601 // hi(result) = hi(src * EAX) + lo(src * EDX)
7602 format %{ "IMUL $tmp,EDX,$src\n\t"
7603 "MOV EDX,$src\n\t"
7604 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t"
7605 "ADD EDX,$tmp" %}
7606 ins_encode( long_multiply_con( dst, src, tmp ) );
7607 ins_pipe( pipe_slow );
7608 %}
7609
7610 // Integer DIV with Register
7611 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
7612 match(Set rax (DivI rax div));
7613 effect(KILL rdx, KILL cr);
7614 size(26);
7615 ins_cost(30*100+10*100);
7616 format %{ "CMP EAX,0x80000000\n\t"
7617 "JNE,s normal\n\t"
7618 "XOR EDX,EDX\n\t"
7619 "CMP ECX,-1\n\t"
7620 "JE,s done\n"
7621 "normal: CDQ\n\t"
7622 "IDIV $div\n\t"
7623 "done:" %}
7624 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7625 ins_encode( cdq_enc, OpcP, RegOpc(div) );
7626 ins_pipe( ialu_reg_reg_alu0 );
7627 %}
7628
7629 // Divide Register Long
7630 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
7631 match(Set dst (DivL src1 src2));
7632 effect( KILL cr, KILL cx, KILL bx );
7633 ins_cost(10000);
7634 format %{ "PUSH $src1.hi\n\t"
7635 "PUSH $src1.lo\n\t"
7636 "PUSH $src2.hi\n\t"
7637 "PUSH $src2.lo\n\t"
7638 "CALL SharedRuntime::ldiv\n\t"
7639 "ADD ESP,16" %}
7640 ins_encode( long_div(src1,src2) );
7641 ins_pipe( pipe_slow );
7642 %}
7643
7644 // Integer DIVMOD with Register, both quotient and mod results
7645 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
7646 match(DivModI rax div);
7647 effect(KILL cr);
7648 size(26);
7649 ins_cost(30*100+10*100);
7650 format %{ "CMP EAX,0x80000000\n\t"
7651 "JNE,s normal\n\t"
7652 "XOR EDX,EDX\n\t"
7653 "CMP ECX,-1\n\t"
7654 "JE,s done\n"
7655 "normal: CDQ\n\t"
7656 "IDIV $div\n\t"
7657 "done:" %}
7658 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7659 ins_encode( cdq_enc, OpcP, RegOpc(div) );
7660 ins_pipe( pipe_slow );
7661 %}
7662
7663 // Integer MOD with Register
7664 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{
7665 match(Set rdx (ModI rax div));
7666 effect(KILL rax, KILL cr);
7667
7668 size(26);
7669 ins_cost(300);
7670 format %{ "CDQ\n\t"
7671 "IDIV $div" %}
7672 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7673 ins_encode( cdq_enc, OpcP, RegOpc(div) );
7674 ins_pipe( ialu_reg_reg_alu0 );
7675 %}
7676
7677 // Remainder Register Long
7678 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
7679 match(Set dst (ModL src1 src2));
7680 effect( KILL cr, KILL cx, KILL bx );
7681 ins_cost(10000);
7682 format %{ "PUSH $src1.hi\n\t"
7683 "PUSH $src1.lo\n\t"
7684 "PUSH $src2.hi\n\t"
7685 "PUSH $src2.lo\n\t"
7686 "CALL SharedRuntime::lrem\n\t"
7687 "ADD ESP,16" %}
7688 ins_encode( long_mod(src1,src2) );
7689 ins_pipe( pipe_slow );
7690 %}
7691
7692 // Divide Register Long (no special case since divisor != -1)
7693 instruct divL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{
7694 match(Set dst (DivL dst imm));
7695 effect( TEMP tmp, TEMP tmp2, KILL cr );
7696 ins_cost(1000);
7697 format %{ "MOV $tmp,abs($imm) # ldiv EDX:EAX,$imm\n\t"
7698 "XOR $tmp2,$tmp2\n\t"
7699 "CMP $tmp,EDX\n\t"
7700 "JA,s fast\n\t"
7701 "MOV $tmp2,EAX\n\t"
7702 "MOV EAX,EDX\n\t"
7703 "MOV EDX,0\n\t"
7704 "JLE,s pos\n\t"
7705 "LNEG EAX : $tmp2\n\t"
7706 "DIV $tmp # unsigned division\n\t"
7707 "XCHG EAX,$tmp2\n\t"
7708 "DIV $tmp\n\t"
7709 "LNEG $tmp2 : EAX\n\t"
7710 "JMP,s done\n"
7711 "pos:\n\t"
7712 "DIV $tmp\n\t"
7713 "XCHG EAX,$tmp2\n"
7714 "fast:\n\t"
7715 "DIV $tmp\n"
7716 "done:\n\t"
7717 "MOV EDX,$tmp2\n\t"
7718 "NEG EDX:EAX # if $imm < 0" %}
7719 ins_encode %{
7720 int con = (int)$imm$$constant;
7721 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
7722 int pcon = (con > 0) ? con : -con;
7723 Label Lfast, Lpos, Ldone;
7724
7725 __ movl($tmp$$Register, pcon);
7726 __ xorl($tmp2$$Register,$tmp2$$Register);
7727 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
7728 __ jccb(Assembler::above, Lfast); // result fits into 32 bit
7729
7730 __ movl($tmp2$$Register, $dst$$Register); // save
7731 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
7732 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
7733 __ jccb(Assembler::lessEqual, Lpos); // result is positive
7734
7735 // Negative dividend.
7736 // convert value to positive to use unsigned division
7737 __ lneg($dst$$Register, $tmp2$$Register);
7738 __ divl($tmp$$Register);
7739 __ xchgl($dst$$Register, $tmp2$$Register);
7740 __ divl($tmp$$Register);
7741 // revert result back to negative
7742 __ lneg($tmp2$$Register, $dst$$Register);
7743 __ jmpb(Ldone);
7744
7745 __ bind(Lpos);
7746 __ divl($tmp$$Register); // Use unsigned division
7747 __ xchgl($dst$$Register, $tmp2$$Register);
7748 // Fallthrow for final divide, tmp2 has 32 bit hi result
7749
7750 __ bind(Lfast);
7751 // fast path: src is positive
7752 __ divl($tmp$$Register); // Use unsigned division
7753
7754 __ bind(Ldone);
7755 __ movl(HIGH_FROM_LOW($dst$$Register),$tmp2$$Register);
7756 if (con < 0) {
7757 __ lneg(HIGH_FROM_LOW($dst$$Register), $dst$$Register);
7758 }
7759 %}
7760 ins_pipe( pipe_slow );
7761 %}
7762
7763 // Remainder Register Long (remainder fit into 32 bits)
7764 instruct modL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{
7765 match(Set dst (ModL dst imm));
7766 effect( TEMP tmp, TEMP tmp2, KILL cr );
7767 ins_cost(1000);
7768 format %{ "MOV $tmp,abs($imm) # lrem EDX:EAX,$imm\n\t"
7769 "CMP $tmp,EDX\n\t"
7770 "JA,s fast\n\t"
7771 "MOV $tmp2,EAX\n\t"
7772 "MOV EAX,EDX\n\t"
7773 "MOV EDX,0\n\t"
7774 "JLE,s pos\n\t"
7775 "LNEG EAX : $tmp2\n\t"
7776 "DIV $tmp # unsigned division\n\t"
7777 "MOV EAX,$tmp2\n\t"
7778 "DIV $tmp\n\t"
7779 "NEG EDX\n\t"
7780 "JMP,s done\n"
7781 "pos:\n\t"
7782 "DIV $tmp\n\t"
7783 "MOV EAX,$tmp2\n"
7784 "fast:\n\t"
7785 "DIV $tmp\n"
7786 "done:\n\t"
7787 "MOV EAX,EDX\n\t"
7788 "SAR EDX,31\n\t" %}
7789 ins_encode %{
7790 int con = (int)$imm$$constant;
7791 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
7792 int pcon = (con > 0) ? con : -con;
7793 Label Lfast, Lpos, Ldone;
7794
7795 __ movl($tmp$$Register, pcon);
7796 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
7797 __ jccb(Assembler::above, Lfast); // src is positive and result fits into 32 bit
7798
7799 __ movl($tmp2$$Register, $dst$$Register); // save
7800 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
7801 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
7802 __ jccb(Assembler::lessEqual, Lpos); // result is positive
7803
7804 // Negative dividend.
7805 // convert value to positive to use unsigned division
7806 __ lneg($dst$$Register, $tmp2$$Register);
7807 __ divl($tmp$$Register);
7808 __ movl($dst$$Register, $tmp2$$Register);
7809 __ divl($tmp$$Register);
7810 // revert remainder back to negative
7811 __ negl(HIGH_FROM_LOW($dst$$Register));
7812 __ jmpb(Ldone);
7813
7814 __ bind(Lpos);
7815 __ divl($tmp$$Register);
7816 __ movl($dst$$Register, $tmp2$$Register);
7817
7818 __ bind(Lfast);
7819 // fast path: src is positive
7820 __ divl($tmp$$Register);
7821
7822 __ bind(Ldone);
7823 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
7824 __ sarl(HIGH_FROM_LOW($dst$$Register), 31); // result sign
7825
7826 %}
7827 ins_pipe( pipe_slow );
7828 %}
7829
7830 // Integer Shift Instructions
7831 // Shift Left by one
7832 instruct shlI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
7833 match(Set dst (LShiftI dst shift));
7834 effect(KILL cr);
7835
7836 size(2);
7837 format %{ "SHL $dst,$shift" %}
7838 opcode(0xD1, 0x4); /* D1 /4 */
7839 ins_encode( OpcP, RegOpc( dst ) );
7840 ins_pipe( ialu_reg );
7841 %}
7842
7843 // Shift Left by 8-bit immediate
7844 instruct salI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
7845 match(Set dst (LShiftI dst shift));
7846 effect(KILL cr);
7847
7848 size(3);
7849 format %{ "SHL $dst,$shift" %}
7850 opcode(0xC1, 0x4); /* C1 /4 ib */
7851 ins_encode( RegOpcImm( dst, shift) );
7852 ins_pipe( ialu_reg );
7853 %}
7854
7855 // Shift Left by variable
7856 instruct salI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
7857 match(Set dst (LShiftI dst shift));
7858 effect(KILL cr);
7859
7860 size(2);
7861 format %{ "SHL $dst,$shift" %}
7862 opcode(0xD3, 0x4); /* D3 /4 */
7863 ins_encode( OpcP, RegOpc( dst ) );
7864 ins_pipe( ialu_reg_reg );
7865 %}
7866
7867 // Arithmetic shift right by one
7868 instruct sarI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
7869 match(Set dst (RShiftI dst shift));
7870 effect(KILL cr);
7871
7872 size(2);
7873 format %{ "SAR $dst,$shift" %}
7874 opcode(0xD1, 0x7); /* D1 /7 */
7875 ins_encode( OpcP, RegOpc( dst ) );
7876 ins_pipe( ialu_reg );
7877 %}
7878
7879 // Arithmetic shift right by one
7880 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{
7881 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
7882 effect(KILL cr);
7883 format %{ "SAR $dst,$shift" %}
7884 opcode(0xD1, 0x7); /* D1 /7 */
7885 ins_encode( OpcP, RMopc_Mem(secondary,dst) );
7886 ins_pipe( ialu_mem_imm );
7887 %}
7888
7889 // Arithmetic Shift Right by 8-bit immediate
7890 instruct sarI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
7891 match(Set dst (RShiftI dst shift));
7892 effect(KILL cr);
7893
7894 size(3);
7895 format %{ "SAR $dst,$shift" %}
7896 opcode(0xC1, 0x7); /* C1 /7 ib */
7897 ins_encode( RegOpcImm( dst, shift ) );
7898 ins_pipe( ialu_mem_imm );
7899 %}
7900
7901 // Arithmetic Shift Right by 8-bit immediate
7902 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{
7903 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
7904 effect(KILL cr);
7905
7906 format %{ "SAR $dst,$shift" %}
7907 opcode(0xC1, 0x7); /* C1 /7 ib */
7908 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) );
7909 ins_pipe( ialu_mem_imm );
7910 %}
7911
7912 // Arithmetic Shift Right by variable
7913 instruct sarI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
7914 match(Set dst (RShiftI dst shift));
7915 effect(KILL cr);
7916
7917 size(2);
7918 format %{ "SAR $dst,$shift" %}
7919 opcode(0xD3, 0x7); /* D3 /7 */
7920 ins_encode( OpcP, RegOpc( dst ) );
7921 ins_pipe( ialu_reg_reg );
7922 %}
7923
7924 // Logical shift right by one
7925 instruct shrI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
7926 match(Set dst (URShiftI dst shift));
7927 effect(KILL cr);
7928
7929 size(2);
7930 format %{ "SHR $dst,$shift" %}
7931 opcode(0xD1, 0x5); /* D1 /5 */
7932 ins_encode( OpcP, RegOpc( dst ) );
7933 ins_pipe( ialu_reg );
7934 %}
7935
7936 // Logical Shift Right by 8-bit immediate
7937 instruct shrI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
7938 match(Set dst (URShiftI dst shift));
7939 effect(KILL cr);
7940
7941 size(3);
7942 format %{ "SHR $dst,$shift" %}
7943 opcode(0xC1, 0x5); /* C1 /5 ib */
7944 ins_encode( RegOpcImm( dst, shift) );
7945 ins_pipe( ialu_reg );
7946 %}
7947
7948
7949 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
7950 // This idiom is used by the compiler for the i2b bytecode.
7951 instruct i2b(rRegI dst, xRegI src, immI_24 twentyfour) %{
7952 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
7953
7954 size(3);
7955 format %{ "MOVSX $dst,$src :8" %}
7956 ins_encode %{
7957 __ movsbl($dst$$Register, $src$$Register);
7958 %}
7959 ins_pipe(ialu_reg_reg);
7960 %}
7961
7962 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
7963 // This idiom is used by the compiler the i2s bytecode.
7964 instruct i2s(rRegI dst, xRegI src, immI_16 sixteen) %{
7965 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
7966
7967 size(3);
7968 format %{ "MOVSX $dst,$src :16" %}
7969 ins_encode %{
7970 __ movswl($dst$$Register, $src$$Register);
7971 %}
7972 ins_pipe(ialu_reg_reg);
7973 %}
7974
7975
7976 // Logical Shift Right by variable
7977 instruct shrI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
7978 match(Set dst (URShiftI dst shift));
7979 effect(KILL cr);
7980
7981 size(2);
7982 format %{ "SHR $dst,$shift" %}
7983 opcode(0xD3, 0x5); /* D3 /5 */
7984 ins_encode( OpcP, RegOpc( dst ) );
7985 ins_pipe( ialu_reg_reg );
7986 %}
7987
7988
7989 //----------Logical Instructions-----------------------------------------------
7990 //----------Integer Logical Instructions---------------------------------------
7991 // And Instructions
7992 // And Register with Register
7993 instruct andI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7994 match(Set dst (AndI dst src));
7995 effect(KILL cr);
7996
7997 size(2);
7998 format %{ "AND $dst,$src" %}
7999 opcode(0x23);
8000 ins_encode( OpcP, RegReg( dst, src) );
8001 ins_pipe( ialu_reg_reg );
8002 %}
8003
8004 // And Register with Immediate
8005 instruct andI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8006 match(Set dst (AndI dst src));
8007 effect(KILL cr);
8008
8009 format %{ "AND $dst,$src" %}
8010 opcode(0x81,0x04); /* Opcode 81 /4 */
8011 // ins_encode( RegImm( dst, src) );
8012 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8013 ins_pipe( ialu_reg );
8014 %}
8015
8016 // And Register with Memory
8017 instruct andI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8018 match(Set dst (AndI dst (LoadI src)));
8019 effect(KILL cr);
8020
8021 ins_cost(125);
8022 format %{ "AND $dst,$src" %}
8023 opcode(0x23);
8024 ins_encode( OpcP, RegMem( dst, src) );
8025 ins_pipe( ialu_reg_mem );
8026 %}
8027
8028 // And Memory with Register
8029 instruct andI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8030 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8031 effect(KILL cr);
8032
8033 ins_cost(150);
8034 format %{ "AND $dst,$src" %}
8035 opcode(0x21); /* Opcode 21 /r */
8036 ins_encode( OpcP, RegMem( src, dst ) );
8037 ins_pipe( ialu_mem_reg );
8038 %}
8039
8040 // And Memory with Immediate
8041 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8042 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8043 effect(KILL cr);
8044
8045 ins_cost(125);
8046 format %{ "AND $dst,$src" %}
8047 opcode(0x81, 0x4); /* Opcode 81 /4 id */
8048 // ins_encode( MemImm( dst, src) );
8049 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8050 ins_pipe( ialu_mem_imm );
8051 %}
8052
8053 // BMI1 instructions
8054 instruct andnI_rReg_rReg_rReg(rRegI dst, rRegI src1, rRegI src2, immI_M1 minus_1, eFlagsReg cr) %{
8055 match(Set dst (AndI (XorI src1 minus_1) src2));
8056 predicate(UseBMI1Instructions);
8057 effect(KILL cr);
8058
8059 format %{ "ANDNL $dst, $src1, $src2" %}
8060
8061 ins_encode %{
8062 __ andnl($dst$$Register, $src1$$Register, $src2$$Register);
8063 %}
8064 ins_pipe(ialu_reg);
8065 %}
8066
8067 instruct andnI_rReg_rReg_mem(rRegI dst, rRegI src1, memory src2, immI_M1 minus_1, eFlagsReg cr) %{
8068 match(Set dst (AndI (XorI src1 minus_1) (LoadI src2) ));
8069 predicate(UseBMI1Instructions);
8070 effect(KILL cr);
8071
8072 ins_cost(125);
8073 format %{ "ANDNL $dst, $src1, $src2" %}
8074
8075 ins_encode %{
8076 __ andnl($dst$$Register, $src1$$Register, $src2$$Address);
8077 %}
8078 ins_pipe(ialu_reg_mem);
8079 %}
8080
8081 instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI0 imm_zero, eFlagsReg cr) %{
8082 match(Set dst (AndI (SubI imm_zero src) src));
8083 predicate(UseBMI1Instructions);
8084 effect(KILL cr);
8085
8086 format %{ "BLSIL $dst, $src" %}
8087
8088 ins_encode %{
8089 __ blsil($dst$$Register, $src$$Register);
8090 %}
8091 ins_pipe(ialu_reg);
8092 %}
8093
8094 instruct blsiI_rReg_mem(rRegI dst, memory src, immI0 imm_zero, eFlagsReg cr) %{
8095 match(Set dst (AndI (SubI imm_zero (LoadI src) ) (LoadI src) ));
8096 predicate(UseBMI1Instructions);
8097 effect(KILL cr);
8098
8099 ins_cost(125);
8100 format %{ "BLSIL $dst, $src" %}
8101
8102 ins_encode %{
8103 __ blsil($dst$$Register, $src$$Address);
8104 %}
8105 ins_pipe(ialu_reg_mem);
8106 %}
8107
8108 instruct blsmskI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, eFlagsReg cr)
8109 %{
8110 match(Set dst (XorI (AddI src minus_1) src));
8111 predicate(UseBMI1Instructions);
8112 effect(KILL cr);
8113
8114 format %{ "BLSMSKL $dst, $src" %}
8115
8116 ins_encode %{
8117 __ blsmskl($dst$$Register, $src$$Register);
8118 %}
8119
8120 ins_pipe(ialu_reg);
8121 %}
8122
8123 instruct blsmskI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, eFlagsReg cr)
8124 %{
8125 match(Set dst (XorI (AddI (LoadI src) minus_1) (LoadI src) ));
8126 predicate(UseBMI1Instructions);
8127 effect(KILL cr);
8128
8129 ins_cost(125);
8130 format %{ "BLSMSKL $dst, $src" %}
8131
8132 ins_encode %{
8133 __ blsmskl($dst$$Register, $src$$Address);
8134 %}
8135
8136 ins_pipe(ialu_reg_mem);
8137 %}
8138
8139 instruct blsrI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, eFlagsReg cr)
8140 %{
8141 match(Set dst (AndI (AddI src minus_1) src) );
8142 predicate(UseBMI1Instructions);
8143 effect(KILL cr);
8144
8145 format %{ "BLSRL $dst, $src" %}
8146
8147 ins_encode %{
8148 __ blsrl($dst$$Register, $src$$Register);
8149 %}
8150
8151 ins_pipe(ialu_reg);
8152 %}
8153
8154 instruct blsrI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, eFlagsReg cr)
8155 %{
8156 match(Set dst (AndI (AddI (LoadI src) minus_1) (LoadI src) ));
8157 predicate(UseBMI1Instructions);
8158 effect(KILL cr);
8159
8160 ins_cost(125);
8161 format %{ "BLSRL $dst, $src" %}
8162
8163 ins_encode %{
8164 __ blsrl($dst$$Register, $src$$Address);
8165 %}
8166
8167 ins_pipe(ialu_reg_mem);
8168 %}
8169
8170 // Or Instructions
8171 // Or Register with Register
8172 instruct orI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8173 match(Set dst (OrI dst src));
8174 effect(KILL cr);
8175
8176 size(2);
8177 format %{ "OR $dst,$src" %}
8178 opcode(0x0B);
8179 ins_encode( OpcP, RegReg( dst, src) );
8180 ins_pipe( ialu_reg_reg );
8181 %}
8182
8183 instruct orI_eReg_castP2X(rRegI dst, eRegP src, eFlagsReg cr) %{
8184 match(Set dst (OrI dst (CastP2X src)));
8185 effect(KILL cr);
8186
8187 size(2);
8188 format %{ "OR $dst,$src" %}
8189 opcode(0x0B);
8190 ins_encode( OpcP, RegReg( dst, src) );
8191 ins_pipe( ialu_reg_reg );
8192 %}
8193
8194
8195 // Or Register with Immediate
8196 instruct orI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8197 match(Set dst (OrI dst src));
8198 effect(KILL cr);
8199
8200 format %{ "OR $dst,$src" %}
8201 opcode(0x81,0x01); /* Opcode 81 /1 id */
8202 // ins_encode( RegImm( dst, src) );
8203 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8204 ins_pipe( ialu_reg );
8205 %}
8206
8207 // Or Register with Memory
8208 instruct orI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8209 match(Set dst (OrI dst (LoadI src)));
8210 effect(KILL cr);
8211
8212 ins_cost(125);
8213 format %{ "OR $dst,$src" %}
8214 opcode(0x0B);
8215 ins_encode( OpcP, RegMem( dst, src) );
8216 ins_pipe( ialu_reg_mem );
8217 %}
8218
8219 // Or Memory with Register
8220 instruct orI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8221 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8222 effect(KILL cr);
8223
8224 ins_cost(150);
8225 format %{ "OR $dst,$src" %}
8226 opcode(0x09); /* Opcode 09 /r */
8227 ins_encode( OpcP, RegMem( src, dst ) );
8228 ins_pipe( ialu_mem_reg );
8229 %}
8230
8231 // Or Memory with Immediate
8232 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8233 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8234 effect(KILL cr);
8235
8236 ins_cost(125);
8237 format %{ "OR $dst,$src" %}
8238 opcode(0x81,0x1); /* Opcode 81 /1 id */
8239 // ins_encode( MemImm( dst, src) );
8240 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8241 ins_pipe( ialu_mem_imm );
8242 %}
8243
8244 // ROL/ROR
8245 // ROL expand
8246 instruct rolI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8247 effect(USE_DEF dst, USE shift, KILL cr);
8248
8249 format %{ "ROL $dst, $shift" %}
8250 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8251 ins_encode( OpcP, RegOpc( dst ));
8252 ins_pipe( ialu_reg );
8253 %}
8254
8255 instruct rolI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
8256 effect(USE_DEF dst, USE shift, KILL cr);
8257
8258 format %{ "ROL $dst, $shift" %}
8259 opcode(0xC1, 0x0); /*Opcode /C1 /0 */
8260 ins_encode( RegOpcImm(dst, shift) );
8261 ins_pipe(ialu_reg);
8262 %}
8263
8264 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{
8265 effect(USE_DEF dst, USE shift, KILL cr);
8266
8267 format %{ "ROL $dst, $shift" %}
8268 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8269 ins_encode(OpcP, RegOpc(dst));
8270 ins_pipe( ialu_reg_reg );
8271 %}
8272 // end of ROL expand
8273
8274 // ROL 32bit by one once
8275 instruct rolI_eReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{
8276 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8277
8278 expand %{
8279 rolI_eReg_imm1(dst, lshift, cr);
8280 %}
8281 %}
8282
8283 // ROL 32bit var by imm8 once
8284 instruct rolI_eReg_i8(rRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{
8285 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8286 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8287
8288 expand %{
8289 rolI_eReg_imm8(dst, lshift, cr);
8290 %}
8291 %}
8292
8293 // ROL 32bit var by var once
8294 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8295 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
8296
8297 expand %{
8298 rolI_eReg_CL(dst, shift, cr);
8299 %}
8300 %}
8301
8302 // ROL 32bit var by var once
8303 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8304 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
8305
8306 expand %{
8307 rolI_eReg_CL(dst, shift, cr);
8308 %}
8309 %}
8310
8311 // ROR expand
8312 instruct rorI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8313 effect(USE_DEF dst, USE shift, KILL cr);
8314
8315 format %{ "ROR $dst, $shift" %}
8316 opcode(0xD1,0x1); /* Opcode D1 /1 */
8317 ins_encode( OpcP, RegOpc( dst ) );
8318 ins_pipe( ialu_reg );
8319 %}
8320
8321 instruct rorI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
8322 effect (USE_DEF dst, USE shift, KILL cr);
8323
8324 format %{ "ROR $dst, $shift" %}
8325 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */
8326 ins_encode( RegOpcImm(dst, shift) );
8327 ins_pipe( ialu_reg );
8328 %}
8329
8330 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{
8331 effect(USE_DEF dst, USE shift, KILL cr);
8332
8333 format %{ "ROR $dst, $shift" %}
8334 opcode(0xD3, 0x1); /* Opcode D3 /1 */
8335 ins_encode(OpcP, RegOpc(dst));
8336 ins_pipe( ialu_reg_reg );
8337 %}
8338 // end of ROR expand
8339
8340 // ROR right once
8341 instruct rorI_eReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{
8342 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8343
8344 expand %{
8345 rorI_eReg_imm1(dst, rshift, cr);
8346 %}
8347 %}
8348
8349 // ROR 32bit by immI8 once
8350 instruct rorI_eReg_i8(rRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{
8351 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8352 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8353
8354 expand %{
8355 rorI_eReg_imm8(dst, rshift, cr);
8356 %}
8357 %}
8358
8359 // ROR 32bit var by var once
8360 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8361 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
8362
8363 expand %{
8364 rorI_eReg_CL(dst, shift, cr);
8365 %}
8366 %}
8367
8368 // ROR 32bit var by var once
8369 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8370 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
8371
8372 expand %{
8373 rorI_eReg_CL(dst, shift, cr);
8374 %}
8375 %}
8376
8377 // Xor Instructions
8378 // Xor Register with Register
8379 instruct xorI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8380 match(Set dst (XorI dst src));
8381 effect(KILL cr);
8382
8383 size(2);
8384 format %{ "XOR $dst,$src" %}
8385 opcode(0x33);
8386 ins_encode( OpcP, RegReg( dst, src) );
8387 ins_pipe( ialu_reg_reg );
8388 %}
8389
8390 // Xor Register with Immediate -1
8391 instruct xorI_eReg_im1(rRegI dst, immI_M1 imm) %{
8392 match(Set dst (XorI dst imm));
8393
8394 size(2);
8395 format %{ "NOT $dst" %}
8396 ins_encode %{
8397 __ notl($dst$$Register);
8398 %}
8399 ins_pipe( ialu_reg );
8400 %}
8401
8402 // Xor Register with Immediate
8403 instruct xorI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8404 match(Set dst (XorI dst src));
8405 effect(KILL cr);
8406
8407 format %{ "XOR $dst,$src" %}
8408 opcode(0x81,0x06); /* Opcode 81 /6 id */
8409 // ins_encode( RegImm( dst, src) );
8410 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8411 ins_pipe( ialu_reg );
8412 %}
8413
8414 // Xor Register with Memory
8415 instruct xorI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8416 match(Set dst (XorI dst (LoadI src)));
8417 effect(KILL cr);
8418
8419 ins_cost(125);
8420 format %{ "XOR $dst,$src" %}
8421 opcode(0x33);
8422 ins_encode( OpcP, RegMem(dst, src) );
8423 ins_pipe( ialu_reg_mem );
8424 %}
8425
8426 // Xor Memory with Register
8427 instruct xorI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8428 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8429 effect(KILL cr);
8430
8431 ins_cost(150);
8432 format %{ "XOR $dst,$src" %}
8433 opcode(0x31); /* Opcode 31 /r */
8434 ins_encode( OpcP, RegMem( src, dst ) );
8435 ins_pipe( ialu_mem_reg );
8436 %}
8437
8438 // Xor Memory with Immediate
8439 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8440 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8441 effect(KILL cr);
8442
8443 ins_cost(125);
8444 format %{ "XOR $dst,$src" %}
8445 opcode(0x81,0x6); /* Opcode 81 /6 id */
8446 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8447 ins_pipe( ialu_mem_imm );
8448 %}
8449
8450 //----------Convert Int to Boolean---------------------------------------------
8451
8452 instruct movI_nocopy(rRegI dst, rRegI src) %{
8453 effect( DEF dst, USE src );
8454 format %{ "MOV $dst,$src" %}
8455 ins_encode( enc_Copy( dst, src) );
8456 ins_pipe( ialu_reg_reg );
8457 %}
8458
8459 instruct ci2b( rRegI dst, rRegI src, eFlagsReg cr ) %{
8460 effect( USE_DEF dst, USE src, KILL cr );
8461
8462 size(4);
8463 format %{ "NEG $dst\n\t"
8464 "ADC $dst,$src" %}
8465 ins_encode( neg_reg(dst),
8466 OpcRegReg(0x13,dst,src) );
8467 ins_pipe( ialu_reg_reg_long );
8468 %}
8469
8470 instruct convI2B( rRegI dst, rRegI src, eFlagsReg cr ) %{
8471 match(Set dst (Conv2B src));
8472
8473 expand %{
8474 movI_nocopy(dst,src);
8475 ci2b(dst,src,cr);
8476 %}
8477 %}
8478
8479 instruct movP_nocopy(rRegI dst, eRegP src) %{
8480 effect( DEF dst, USE src );
8481 format %{ "MOV $dst,$src" %}
8482 ins_encode( enc_Copy( dst, src) );
8483 ins_pipe( ialu_reg_reg );
8484 %}
8485
8486 instruct cp2b( rRegI dst, eRegP src, eFlagsReg cr ) %{
8487 effect( USE_DEF dst, USE src, KILL cr );
8488 format %{ "NEG $dst\n\t"
8489 "ADC $dst,$src" %}
8490 ins_encode( neg_reg(dst),
8491 OpcRegReg(0x13,dst,src) );
8492 ins_pipe( ialu_reg_reg_long );
8493 %}
8494
8495 instruct convP2B( rRegI dst, eRegP src, eFlagsReg cr ) %{
8496 match(Set dst (Conv2B src));
8497
8498 expand %{
8499 movP_nocopy(dst,src);
8500 cp2b(dst,src,cr);
8501 %}
8502 %}
8503
8504 instruct cmpLTMask(eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr) %{
8505 match(Set dst (CmpLTMask p q));
8506 effect(KILL cr);
8507 ins_cost(400);
8508
8509 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination
8510 format %{ "XOR $dst,$dst\n\t"
8511 "CMP $p,$q\n\t"
8512 "SETlt $dst\n\t"
8513 "NEG $dst" %}
8514 ins_encode %{
8515 Register Rp = $p$$Register;
8516 Register Rq = $q$$Register;
8517 Register Rd = $dst$$Register;
8518 Label done;
8519 __ xorl(Rd, Rd);
8520 __ cmpl(Rp, Rq);
8521 __ setb(Assembler::less, Rd);
8522 __ negl(Rd);
8523 %}
8524
8525 ins_pipe(pipe_slow);
8526 %}
8527
8528 instruct cmpLTMask0(rRegI dst, immI0 zero, eFlagsReg cr) %{
8529 match(Set dst (CmpLTMask dst zero));
8530 effect(DEF dst, KILL cr);
8531 ins_cost(100);
8532
8533 format %{ "SAR $dst,31\t# cmpLTMask0" %}
8534 ins_encode %{
8535 __ sarl($dst$$Register, 31);
8536 %}
8537 ins_pipe(ialu_reg);
8538 %}
8539
8540 /* better to save a register than avoid a branch */
8541 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, eFlagsReg cr) %{
8542 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8543 effect(KILL cr);
8544 ins_cost(400);
8545 format %{ "SUB $p,$q\t# cadd_cmpLTMask\n\t"
8546 "JGE done\n\t"
8547 "ADD $p,$y\n"
8548 "done: " %}
8549 ins_encode %{
8550 Register Rp = $p$$Register;
8551 Register Rq = $q$$Register;
8552 Register Ry = $y$$Register;
8553 Label done;
8554 __ subl(Rp, Rq);
8555 __ jccb(Assembler::greaterEqual, done);
8556 __ addl(Rp, Ry);
8557 __ bind(done);
8558 %}
8559
8560 ins_pipe(pipe_cmplt);
8561 %}
8562
8563 /* better to save a register than avoid a branch */
8564 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, eFlagsReg cr) %{
8565 match(Set y (AndI (CmpLTMask p q) y));
8566 effect(KILL cr);
8567
8568 ins_cost(300);
8569
8570 format %{ "CMPL $p, $q\t# and_cmpLTMask\n\t"
8571 "JLT done\n\t"
8572 "XORL $y, $y\n"
8573 "done: " %}
8574 ins_encode %{
8575 Register Rp = $p$$Register;
8576 Register Rq = $q$$Register;
8577 Register Ry = $y$$Register;
8578 Label done;
8579 __ cmpl(Rp, Rq);
8580 __ jccb(Assembler::less, done);
8581 __ xorl(Ry, Ry);
8582 __ bind(done);
8583 %}
8584
8585 ins_pipe(pipe_cmplt);
8586 %}
8587
8588 /* If I enable this, I encourage spilling in the inner loop of compress.
8589 instruct cadd_cmpLTMask_mem(ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr) %{
8590 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q)));
8591 */
8592 //----------Overflow Math Instructions-----------------------------------------
8593
8594 instruct overflowAddI_eReg(eFlagsReg cr, eAXRegI op1, rRegI op2)
8595 %{
8596 match(Set cr (OverflowAddI op1 op2));
8597 effect(DEF cr, USE_KILL op1, USE op2);
8598
8599 format %{ "ADD $op1, $op2\t# overflow check int" %}
8600
8601 ins_encode %{
8602 __ addl($op1$$Register, $op2$$Register);
8603 %}
8604 ins_pipe(ialu_reg_reg);
8605 %}
8606
8607 instruct overflowAddI_rReg_imm(eFlagsReg cr, eAXRegI op1, immI op2)
8608 %{
8609 match(Set cr (OverflowAddI op1 op2));
8610 effect(DEF cr, USE_KILL op1, USE op2);
8611
8612 format %{ "ADD $op1, $op2\t# overflow check int" %}
8613
8614 ins_encode %{
8615 __ addl($op1$$Register, $op2$$constant);
8616 %}
8617 ins_pipe(ialu_reg_reg);
8618 %}
8619
8620 instruct overflowSubI_rReg(eFlagsReg cr, rRegI op1, rRegI op2)
8621 %{
8622 match(Set cr (OverflowSubI op1 op2));
8623
8624 format %{ "CMP $op1, $op2\t# overflow check int" %}
8625 ins_encode %{
8626 __ cmpl($op1$$Register, $op2$$Register);
8627 %}
8628 ins_pipe(ialu_reg_reg);
8629 %}
8630
8631 instruct overflowSubI_rReg_imm(eFlagsReg cr, rRegI op1, immI op2)
8632 %{
8633 match(Set cr (OverflowSubI op1 op2));
8634
8635 format %{ "CMP $op1, $op2\t# overflow check int" %}
8636 ins_encode %{
8637 __ cmpl($op1$$Register, $op2$$constant);
8638 %}
8639 ins_pipe(ialu_reg_reg);
8640 %}
8641
8642 instruct overflowNegI_rReg(eFlagsReg cr, immI0 zero, eAXRegI op2)
8643 %{
8644 match(Set cr (OverflowSubI zero op2));
8645 effect(DEF cr, USE_KILL op2);
8646
8647 format %{ "NEG $op2\t# overflow check int" %}
8648 ins_encode %{
8649 __ negl($op2$$Register);
8650 %}
8651 ins_pipe(ialu_reg_reg);
8652 %}
8653
8654 instruct overflowMulI_rReg(eFlagsReg cr, eAXRegI op1, rRegI op2)
8655 %{
8656 match(Set cr (OverflowMulI op1 op2));
8657 effect(DEF cr, USE_KILL op1, USE op2);
8658
8659 format %{ "IMUL $op1, $op2\t# overflow check int" %}
8660 ins_encode %{
8661 __ imull($op1$$Register, $op2$$Register);
8662 %}
8663 ins_pipe(ialu_reg_reg_alu0);
8664 %}
8665
8666 instruct overflowMulI_rReg_imm(eFlagsReg cr, rRegI op1, immI op2, rRegI tmp)
8667 %{
8668 match(Set cr (OverflowMulI op1 op2));
8669 effect(DEF cr, TEMP tmp, USE op1, USE op2);
8670
8671 format %{ "IMUL $tmp, $op1, $op2\t# overflow check int" %}
8672 ins_encode %{
8673 __ imull($tmp$$Register, $op1$$Register, $op2$$constant);
8674 %}
8675 ins_pipe(ialu_reg_reg_alu0);
8676 %}
8677
8678 //----------Long Instructions------------------------------------------------
8679 // Add Long Register with Register
8680 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
8681 match(Set dst (AddL dst src));
8682 effect(KILL cr);
8683 ins_cost(200);
8684 format %{ "ADD $dst.lo,$src.lo\n\t"
8685 "ADC $dst.hi,$src.hi" %}
8686 opcode(0x03, 0x13);
8687 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
8688 ins_pipe( ialu_reg_reg_long );
8689 %}
8690
8691 // Add Long Register with Immediate
8692 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
8693 match(Set dst (AddL dst src));
8694 effect(KILL cr);
8695 format %{ "ADD $dst.lo,$src.lo\n\t"
8696 "ADC $dst.hi,$src.hi" %}
8697 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */
8698 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
8699 ins_pipe( ialu_reg_long );
8700 %}
8701
8702 // Add Long Register with Memory
8703 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
8704 match(Set dst (AddL dst (LoadL mem)));
8705 effect(KILL cr);
8706 ins_cost(125);
8707 format %{ "ADD $dst.lo,$mem\n\t"
8708 "ADC $dst.hi,$mem+4" %}
8709 opcode(0x03, 0x13);
8710 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
8711 ins_pipe( ialu_reg_long_mem );
8712 %}
8713
8714 // Subtract Long Register with Register.
8715 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
8716 match(Set dst (SubL dst src));
8717 effect(KILL cr);
8718 ins_cost(200);
8719 format %{ "SUB $dst.lo,$src.lo\n\t"
8720 "SBB $dst.hi,$src.hi" %}
8721 opcode(0x2B, 0x1B);
8722 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
8723 ins_pipe( ialu_reg_reg_long );
8724 %}
8725
8726 // Subtract Long Register with Immediate
8727 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
8728 match(Set dst (SubL dst src));
8729 effect(KILL cr);
8730 format %{ "SUB $dst.lo,$src.lo\n\t"
8731 "SBB $dst.hi,$src.hi" %}
8732 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */
8733 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
8734 ins_pipe( ialu_reg_long );
8735 %}
8736
8737 // Subtract Long Register with Memory
8738 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
8739 match(Set dst (SubL dst (LoadL mem)));
8740 effect(KILL cr);
8741 ins_cost(125);
8742 format %{ "SUB $dst.lo,$mem\n\t"
8743 "SBB $dst.hi,$mem+4" %}
8744 opcode(0x2B, 0x1B);
8745 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
8746 ins_pipe( ialu_reg_long_mem );
8747 %}
8748
8749 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{
8750 match(Set dst (SubL zero dst));
8751 effect(KILL cr);
8752 ins_cost(300);
8753 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %}
8754 ins_encode( neg_long(dst) );
8755 ins_pipe( ialu_reg_reg_long );
8756 %}
8757
8758 // And Long Register with Register
8759 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
8760 match(Set dst (AndL dst src));
8761 effect(KILL cr);
8762 format %{ "AND $dst.lo,$src.lo\n\t"
8763 "AND $dst.hi,$src.hi" %}
8764 opcode(0x23,0x23);
8765 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
8766 ins_pipe( ialu_reg_reg_long );
8767 %}
8768
8769 // And Long Register with Immediate
8770 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
8771 match(Set dst (AndL dst src));
8772 effect(KILL cr);
8773 format %{ "AND $dst.lo,$src.lo\n\t"
8774 "AND $dst.hi,$src.hi" %}
8775 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */
8776 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
8777 ins_pipe( ialu_reg_long );
8778 %}
8779
8780 // And Long Register with Memory
8781 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
8782 match(Set dst (AndL dst (LoadL mem)));
8783 effect(KILL cr);
8784 ins_cost(125);
8785 format %{ "AND $dst.lo,$mem\n\t"
8786 "AND $dst.hi,$mem+4" %}
8787 opcode(0x23, 0x23);
8788 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
8789 ins_pipe( ialu_reg_long_mem );
8790 %}
8791
8792 // BMI1 instructions
8793 instruct andnL_eReg_eReg_eReg(eRegL dst, eRegL src1, eRegL src2, immL_M1 minus_1, eFlagsReg cr) %{
8794 match(Set dst (AndL (XorL src1 minus_1) src2));
8795 predicate(UseBMI1Instructions);
8796 effect(KILL cr, TEMP dst);
8797
8798 format %{ "ANDNL $dst.lo, $src1.lo, $src2.lo\n\t"
8799 "ANDNL $dst.hi, $src1.hi, $src2.hi"
8800 %}
8801
8802 ins_encode %{
8803 Register Rdst = $dst$$Register;
8804 Register Rsrc1 = $src1$$Register;
8805 Register Rsrc2 = $src2$$Register;
8806 __ andnl(Rdst, Rsrc1, Rsrc2);
8807 __ andnl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc1), HIGH_FROM_LOW(Rsrc2));
8808 %}
8809 ins_pipe(ialu_reg_reg_long);
8810 %}
8811
8812 instruct andnL_eReg_eReg_mem(eRegL dst, eRegL src1, memory src2, immL_M1 minus_1, eFlagsReg cr) %{
8813 match(Set dst (AndL (XorL src1 minus_1) (LoadL src2) ));
8814 predicate(UseBMI1Instructions);
8815 effect(KILL cr, TEMP dst);
8816
8817 ins_cost(125);
8818 format %{ "ANDNL $dst.lo, $src1.lo, $src2\n\t"
8819 "ANDNL $dst.hi, $src1.hi, $src2+4"
8820 %}
8821
8822 ins_encode %{
8823 Register Rdst = $dst$$Register;
8824 Register Rsrc1 = $src1$$Register;
8825 Address src2_hi = Address::make_raw($src2$$base, $src2$$index, $src2$$scale, $src2$$disp + 4, relocInfo::none);
8826
8827 __ andnl(Rdst, Rsrc1, $src2$$Address);
8828 __ andnl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc1), src2_hi);
8829 %}
8830 ins_pipe(ialu_reg_mem);
8831 %}
8832
8833 instruct blsiL_eReg_eReg(eRegL dst, eRegL src, immL0 imm_zero, eFlagsReg cr) %{
8834 match(Set dst (AndL (SubL imm_zero src) src));
8835 predicate(UseBMI1Instructions);
8836 effect(KILL cr, TEMP dst);
8837
8838 format %{ "MOVL $dst.hi, 0\n\t"
8839 "BLSIL $dst.lo, $src.lo\n\t"
8840 "JNZ done\n\t"
8841 "BLSIL $dst.hi, $src.hi\n"
8842 "done:"
8843 %}
8844
8845 ins_encode %{
8846 Label done;
8847 Register Rdst = $dst$$Register;
8848 Register Rsrc = $src$$Register;
8849 __ movl(HIGH_FROM_LOW(Rdst), 0);
8850 __ blsil(Rdst, Rsrc);
8851 __ jccb(Assembler::notZero, done);
8852 __ blsil(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc));
8853 __ bind(done);
8854 %}
8855 ins_pipe(ialu_reg);
8856 %}
8857
8858 instruct blsiL_eReg_mem(eRegL dst, memory src, immL0 imm_zero, eFlagsReg cr) %{
8859 match(Set dst (AndL (SubL imm_zero (LoadL src) ) (LoadL src) ));
8860 predicate(UseBMI1Instructions);
8861 effect(KILL cr, TEMP dst);
8862
8863 ins_cost(125);
8864 format %{ "MOVL $dst.hi, 0\n\t"
8865 "BLSIL $dst.lo, $src\n\t"
8866 "JNZ done\n\t"
8867 "BLSIL $dst.hi, $src+4\n"
8868 "done:"
8869 %}
8870
8871 ins_encode %{
8872 Label done;
8873 Register Rdst = $dst$$Register;
8874 Address src_hi = Address::make_raw($src$$base, $src$$index, $src$$scale, $src$$disp + 4, relocInfo::none);
8875
8876 __ movl(HIGH_FROM_LOW(Rdst), 0);
8877 __ blsil(Rdst, $src$$Address);
8878 __ jccb(Assembler::notZero, done);
8879 __ blsil(HIGH_FROM_LOW(Rdst), src_hi);
8880 __ bind(done);
8881 %}
8882 ins_pipe(ialu_reg_mem);
8883 %}
8884
8885 instruct blsmskL_eReg_eReg(eRegL dst, eRegL src, immL_M1 minus_1, eFlagsReg cr)
8886 %{
8887 match(Set dst (XorL (AddL src minus_1) src));
8888 predicate(UseBMI1Instructions);
8889 effect(KILL cr, TEMP dst);
8890
8891 format %{ "MOVL $dst.hi, 0\n\t"
8892 "BLSMSKL $dst.lo, $src.lo\n\t"
8893 "JNC done\n\t"
8894 "BLSMSKL $dst.hi, $src.hi\n"
8895 "done:"
8896 %}
8897
8898 ins_encode %{
8899 Label done;
8900 Register Rdst = $dst$$Register;
8901 Register Rsrc = $src$$Register;
8902 __ movl(HIGH_FROM_LOW(Rdst), 0);
8903 __ blsmskl(Rdst, Rsrc);
8904 __ jccb(Assembler::carryClear, done);
8905 __ blsmskl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc));
8906 __ bind(done);
8907 %}
8908
8909 ins_pipe(ialu_reg);
8910 %}
8911
8912 instruct blsmskL_eReg_mem(eRegL dst, memory src, immL_M1 minus_1, eFlagsReg cr)
8913 %{
8914 match(Set dst (XorL (AddL (LoadL src) minus_1) (LoadL src) ));
8915 predicate(UseBMI1Instructions);
8916 effect(KILL cr, TEMP dst);
8917
8918 ins_cost(125);
8919 format %{ "MOVL $dst.hi, 0\n\t"
8920 "BLSMSKL $dst.lo, $src\n\t"
8921 "JNC done\n\t"
8922 "BLSMSKL $dst.hi, $src+4\n"
8923 "done:"
8924 %}
8925
8926 ins_encode %{
8927 Label done;
8928 Register Rdst = $dst$$Register;
8929 Address src_hi = Address::make_raw($src$$base, $src$$index, $src$$scale, $src$$disp + 4, relocInfo::none);
8930
8931 __ movl(HIGH_FROM_LOW(Rdst), 0);
8932 __ blsmskl(Rdst, $src$$Address);
8933 __ jccb(Assembler::carryClear, done);
8934 __ blsmskl(HIGH_FROM_LOW(Rdst), src_hi);
8935 __ bind(done);
8936 %}
8937
8938 ins_pipe(ialu_reg_mem);
8939 %}
8940
8941 instruct blsrL_eReg_eReg(eRegL dst, eRegL src, immL_M1 minus_1, eFlagsReg cr)
8942 %{
8943 match(Set dst (AndL (AddL src minus_1) src) );
8944 predicate(UseBMI1Instructions);
8945 effect(KILL cr, TEMP dst);
8946
8947 format %{ "MOVL $dst.hi, $src.hi\n\t"
8948 "BLSRL $dst.lo, $src.lo\n\t"
8949 "JNC done\n\t"
8950 "BLSRL $dst.hi, $src.hi\n"
8951 "done:"
8952 %}
8953
8954 ins_encode %{
8955 Label done;
8956 Register Rdst = $dst$$Register;
8957 Register Rsrc = $src$$Register;
8958 __ movl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc));
8959 __ blsrl(Rdst, Rsrc);
8960 __ jccb(Assembler::carryClear, done);
8961 __ blsrl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc));
8962 __ bind(done);
8963 %}
8964
8965 ins_pipe(ialu_reg);
8966 %}
8967
8968 instruct blsrL_eReg_mem(eRegL dst, memory src, immL_M1 minus_1, eFlagsReg cr)
8969 %{
8970 match(Set dst (AndL (AddL (LoadL src) minus_1) (LoadL src) ));
8971 predicate(UseBMI1Instructions);
8972 effect(KILL cr, TEMP dst);
8973
8974 ins_cost(125);
8975 format %{ "MOVL $dst.hi, $src+4\n\t"
8976 "BLSRL $dst.lo, $src\n\t"
8977 "JNC done\n\t"
8978 "BLSRL $dst.hi, $src+4\n"
8979 "done:"
8980 %}
8981
8982 ins_encode %{
8983 Label done;
8984 Register Rdst = $dst$$Register;
8985 Address src_hi = Address::make_raw($src$$base, $src$$index, $src$$scale, $src$$disp + 4, relocInfo::none);
8986 __ movl(HIGH_FROM_LOW(Rdst), src_hi);
8987 __ blsrl(Rdst, $src$$Address);
8988 __ jccb(Assembler::carryClear, done);
8989 __ blsrl(HIGH_FROM_LOW(Rdst), src_hi);
8990 __ bind(done);
8991 %}
8992
8993 ins_pipe(ialu_reg_mem);
8994 %}
8995
8996 // Or Long Register with Register
8997 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
8998 match(Set dst (OrL dst src));
8999 effect(KILL cr);
9000 format %{ "OR $dst.lo,$src.lo\n\t"
9001 "OR $dst.hi,$src.hi" %}
9002 opcode(0x0B,0x0B);
9003 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9004 ins_pipe( ialu_reg_reg_long );
9005 %}
9006
9007 // Or Long Register with Immediate
9008 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9009 match(Set dst (OrL dst src));
9010 effect(KILL cr);
9011 format %{ "OR $dst.lo,$src.lo\n\t"
9012 "OR $dst.hi,$src.hi" %}
9013 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */
9014 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9015 ins_pipe( ialu_reg_long );
9016 %}
9017
9018 // Or Long Register with Memory
9019 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9020 match(Set dst (OrL dst (LoadL mem)));
9021 effect(KILL cr);
9022 ins_cost(125);
9023 format %{ "OR $dst.lo,$mem\n\t"
9024 "OR $dst.hi,$mem+4" %}
9025 opcode(0x0B,0x0B);
9026 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9027 ins_pipe( ialu_reg_long_mem );
9028 %}
9029
9030 // Xor Long Register with Register
9031 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9032 match(Set dst (XorL dst src));
9033 effect(KILL cr);
9034 format %{ "XOR $dst.lo,$src.lo\n\t"
9035 "XOR $dst.hi,$src.hi" %}
9036 opcode(0x33,0x33);
9037 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9038 ins_pipe( ialu_reg_reg_long );
9039 %}
9040
9041 // Xor Long Register with Immediate -1
9042 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{
9043 match(Set dst (XorL dst imm));
9044 format %{ "NOT $dst.lo\n\t"
9045 "NOT $dst.hi" %}
9046 ins_encode %{
9047 __ notl($dst$$Register);
9048 __ notl(HIGH_FROM_LOW($dst$$Register));
9049 %}
9050 ins_pipe( ialu_reg_long );
9051 %}
9052
9053 // Xor Long Register with Immediate
9054 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9055 match(Set dst (XorL dst src));
9056 effect(KILL cr);
9057 format %{ "XOR $dst.lo,$src.lo\n\t"
9058 "XOR $dst.hi,$src.hi" %}
9059 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */
9060 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9061 ins_pipe( ialu_reg_long );
9062 %}
9063
9064 // Xor Long Register with Memory
9065 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9066 match(Set dst (XorL dst (LoadL mem)));
9067 effect(KILL cr);
9068 ins_cost(125);
9069 format %{ "XOR $dst.lo,$mem\n\t"
9070 "XOR $dst.hi,$mem+4" %}
9071 opcode(0x33,0x33);
9072 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9073 ins_pipe( ialu_reg_long_mem );
9074 %}
9075
9076 // Shift Left Long by 1
9077 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{
9078 predicate(UseNewLongLShift);
9079 match(Set dst (LShiftL dst cnt));
9080 effect(KILL cr);
9081 ins_cost(100);
9082 format %{ "ADD $dst.lo,$dst.lo\n\t"
9083 "ADC $dst.hi,$dst.hi" %}
9084 ins_encode %{
9085 __ addl($dst$$Register,$dst$$Register);
9086 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9087 %}
9088 ins_pipe( ialu_reg_long );
9089 %}
9090
9091 // Shift Left Long by 2
9092 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{
9093 predicate(UseNewLongLShift);
9094 match(Set dst (LShiftL dst cnt));
9095 effect(KILL cr);
9096 ins_cost(100);
9097 format %{ "ADD $dst.lo,$dst.lo\n\t"
9098 "ADC $dst.hi,$dst.hi\n\t"
9099 "ADD $dst.lo,$dst.lo\n\t"
9100 "ADC $dst.hi,$dst.hi" %}
9101 ins_encode %{
9102 __ addl($dst$$Register,$dst$$Register);
9103 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9104 __ addl($dst$$Register,$dst$$Register);
9105 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9106 %}
9107 ins_pipe( ialu_reg_long );
9108 %}
9109
9110 // Shift Left Long by 3
9111 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{
9112 predicate(UseNewLongLShift);
9113 match(Set dst (LShiftL dst cnt));
9114 effect(KILL cr);
9115 ins_cost(100);
9116 format %{ "ADD $dst.lo,$dst.lo\n\t"
9117 "ADC $dst.hi,$dst.hi\n\t"
9118 "ADD $dst.lo,$dst.lo\n\t"
9119 "ADC $dst.hi,$dst.hi\n\t"
9120 "ADD $dst.lo,$dst.lo\n\t"
9121 "ADC $dst.hi,$dst.hi" %}
9122 ins_encode %{
9123 __ addl($dst$$Register,$dst$$Register);
9124 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9125 __ addl($dst$$Register,$dst$$Register);
9126 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9127 __ addl($dst$$Register,$dst$$Register);
9128 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9129 %}
9130 ins_pipe( ialu_reg_long );
9131 %}
9132
9133 // Shift Left Long by 1-31
9134 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9135 match(Set dst (LShiftL dst cnt));
9136 effect(KILL cr);
9137 ins_cost(200);
9138 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t"
9139 "SHL $dst.lo,$cnt" %}
9140 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */
9141 ins_encode( move_long_small_shift(dst,cnt) );
9142 ins_pipe( ialu_reg_long );
9143 %}
9144
9145 // Shift Left Long by 32-63
9146 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9147 match(Set dst (LShiftL dst cnt));
9148 effect(KILL cr);
9149 ins_cost(300);
9150 format %{ "MOV $dst.hi,$dst.lo\n"
9151 "\tSHL $dst.hi,$cnt-32\n"
9152 "\tXOR $dst.lo,$dst.lo" %}
9153 opcode(0xC1, 0x4); /* C1 /4 ib */
9154 ins_encode( move_long_big_shift_clr(dst,cnt) );
9155 ins_pipe( ialu_reg_long );
9156 %}
9157
9158 // Shift Left Long by variable
9159 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9160 match(Set dst (LShiftL dst shift));
9161 effect(KILL cr);
9162 ins_cost(500+200);
9163 size(17);
9164 format %{ "TEST $shift,32\n\t"
9165 "JEQ,s small\n\t"
9166 "MOV $dst.hi,$dst.lo\n\t"
9167 "XOR $dst.lo,$dst.lo\n"
9168 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t"
9169 "SHL $dst.lo,$shift" %}
9170 ins_encode( shift_left_long( dst, shift ) );
9171 ins_pipe( pipe_slow );
9172 %}
9173
9174 // Shift Right Long by 1-31
9175 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9176 match(Set dst (URShiftL dst cnt));
9177 effect(KILL cr);
9178 ins_cost(200);
9179 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9180 "SHR $dst.hi,$cnt" %}
9181 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */
9182 ins_encode( move_long_small_shift(dst,cnt) );
9183 ins_pipe( ialu_reg_long );
9184 %}
9185
9186 // Shift Right Long by 32-63
9187 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9188 match(Set dst (URShiftL dst cnt));
9189 effect(KILL cr);
9190 ins_cost(300);
9191 format %{ "MOV $dst.lo,$dst.hi\n"
9192 "\tSHR $dst.lo,$cnt-32\n"
9193 "\tXOR $dst.hi,$dst.hi" %}
9194 opcode(0xC1, 0x5); /* C1 /5 ib */
9195 ins_encode( move_long_big_shift_clr(dst,cnt) );
9196 ins_pipe( ialu_reg_long );
9197 %}
9198
9199 // Shift Right Long by variable
9200 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9201 match(Set dst (URShiftL dst shift));
9202 effect(KILL cr);
9203 ins_cost(600);
9204 size(17);
9205 format %{ "TEST $shift,32\n\t"
9206 "JEQ,s small\n\t"
9207 "MOV $dst.lo,$dst.hi\n\t"
9208 "XOR $dst.hi,$dst.hi\n"
9209 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9210 "SHR $dst.hi,$shift" %}
9211 ins_encode( shift_right_long( dst, shift ) );
9212 ins_pipe( pipe_slow );
9213 %}
9214
9215 // Shift Right Long by 1-31
9216 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9217 match(Set dst (RShiftL dst cnt));
9218 effect(KILL cr);
9219 ins_cost(200);
9220 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9221 "SAR $dst.hi,$cnt" %}
9222 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */
9223 ins_encode( move_long_small_shift(dst,cnt) );
9224 ins_pipe( ialu_reg_long );
9225 %}
9226
9227 // Shift Right Long by 32-63
9228 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9229 match(Set dst (RShiftL dst cnt));
9230 effect(KILL cr);
9231 ins_cost(300);
9232 format %{ "MOV $dst.lo,$dst.hi\n"
9233 "\tSAR $dst.lo,$cnt-32\n"
9234 "\tSAR $dst.hi,31" %}
9235 opcode(0xC1, 0x7); /* C1 /7 ib */
9236 ins_encode( move_long_big_shift_sign(dst,cnt) );
9237 ins_pipe( ialu_reg_long );
9238 %}
9239
9240 // Shift Right arithmetic Long by variable
9241 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9242 match(Set dst (RShiftL dst shift));
9243 effect(KILL cr);
9244 ins_cost(600);
9245 size(18);
9246 format %{ "TEST $shift,32\n\t"
9247 "JEQ,s small\n\t"
9248 "MOV $dst.lo,$dst.hi\n\t"
9249 "SAR $dst.hi,31\n"
9250 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9251 "SAR $dst.hi,$shift" %}
9252 ins_encode( shift_right_arith_long( dst, shift ) );
9253 ins_pipe( pipe_slow );
9254 %}
9255
9256
9257 //----------Double Instructions------------------------------------------------
9258 // Double Math
9259
9260 // Compare & branch
9261
9262 // P6 version of float compare, sets condition codes in EFLAGS
9263 instruct cmpDPR_cc_P6(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{
9264 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9265 match(Set cr (CmpD src1 src2));
9266 effect(KILL rax);
9267 ins_cost(150);
9268 format %{ "FLD $src1\n\t"
9269 "FUCOMIP ST,$src2 // P6 instruction\n\t"
9270 "JNP exit\n\t"
9271 "MOV ah,1 // saw a NaN, set CF\n\t"
9272 "SAHF\n"
9273 "exit:\tNOP // avoid branch to branch" %}
9274 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9275 ins_encode( Push_Reg_DPR(src1),
9276 OpcP, RegOpc(src2),
9277 cmpF_P6_fixup );
9278 ins_pipe( pipe_slow );
9279 %}
9280
9281 instruct cmpDPR_cc_P6CF(eFlagsRegUCF cr, regDPR src1, regDPR src2) %{
9282 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9283 match(Set cr (CmpD src1 src2));
9284 ins_cost(150);
9285 format %{ "FLD $src1\n\t"
9286 "FUCOMIP ST,$src2 // P6 instruction" %}
9287 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9288 ins_encode( Push_Reg_DPR(src1),
9289 OpcP, RegOpc(src2));
9290 ins_pipe( pipe_slow );
9291 %}
9292
9293 // Compare & branch
9294 instruct cmpDPR_cc(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{
9295 predicate(UseSSE<=1);
9296 match(Set cr (CmpD src1 src2));
9297 effect(KILL rax);
9298 ins_cost(200);
9299 format %{ "FLD $src1\n\t"
9300 "FCOMp $src2\n\t"
9301 "FNSTSW AX\n\t"
9302 "TEST AX,0x400\n\t"
9303 "JZ,s flags\n\t"
9304 "MOV AH,1\t# unordered treat as LT\n"
9305 "flags:\tSAHF" %}
9306 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9307 ins_encode( Push_Reg_DPR(src1),
9308 OpcP, RegOpc(src2),
9309 fpu_flags);
9310 ins_pipe( pipe_slow );
9311 %}
9312
9313 // Compare vs zero into -1,0,1
9314 instruct cmpDPR_0(rRegI dst, regDPR src1, immDPR0 zero, eAXRegI rax, eFlagsReg cr) %{
9315 predicate(UseSSE<=1);
9316 match(Set dst (CmpD3 src1 zero));
9317 effect(KILL cr, KILL rax);
9318 ins_cost(280);
9319 format %{ "FTSTD $dst,$src1" %}
9320 opcode(0xE4, 0xD9);
9321 ins_encode( Push_Reg_DPR(src1),
9322 OpcS, OpcP, PopFPU,
9323 CmpF_Result(dst));
9324 ins_pipe( pipe_slow );
9325 %}
9326
9327 // Compare into -1,0,1
9328 instruct cmpDPR_reg(rRegI dst, regDPR src1, regDPR src2, eAXRegI rax, eFlagsReg cr) %{
9329 predicate(UseSSE<=1);
9330 match(Set dst (CmpD3 src1 src2));
9331 effect(KILL cr, KILL rax);
9332 ins_cost(300);
9333 format %{ "FCMPD $dst,$src1,$src2" %}
9334 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9335 ins_encode( Push_Reg_DPR(src1),
9336 OpcP, RegOpc(src2),
9337 CmpF_Result(dst));
9338 ins_pipe( pipe_slow );
9339 %}
9340
9341 // float compare and set condition codes in EFLAGS by XMM regs
9342 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2) %{
9343 predicate(UseSSE>=2);
9344 match(Set cr (CmpD src1 src2));
9345 ins_cost(145);
9346 format %{ "UCOMISD $src1,$src2\n\t"
9347 "JNP,s exit\n\t"
9348 "PUSHF\t# saw NaN, set CF\n\t"
9349 "AND [rsp], #0xffffff2b\n\t"
9350 "POPF\n"
9351 "exit:" %}
9352 ins_encode %{
9353 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9354 emit_cmpfp_fixup(_masm);
9355 %}
9356 ins_pipe( pipe_slow );
9357 %}
9358
9359 instruct cmpD_ccCF(eFlagsRegUCF cr, regD src1, regD src2) %{
9360 predicate(UseSSE>=2);
9361 match(Set cr (CmpD src1 src2));
9362 ins_cost(100);
9363 format %{ "UCOMISD $src1,$src2" %}
9364 ins_encode %{
9365 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9366 %}
9367 ins_pipe( pipe_slow );
9368 %}
9369
9370 // float compare and set condition codes in EFLAGS by XMM regs
9371 instruct cmpD_ccmem(eFlagsRegU cr, regD src1, memory src2) %{
9372 predicate(UseSSE>=2);
9373 match(Set cr (CmpD src1 (LoadD src2)));
9374 ins_cost(145);
9375 format %{ "UCOMISD $src1,$src2\n\t"
9376 "JNP,s exit\n\t"
9377 "PUSHF\t# saw NaN, set CF\n\t"
9378 "AND [rsp], #0xffffff2b\n\t"
9379 "POPF\n"
9380 "exit:" %}
9381 ins_encode %{
9382 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9383 emit_cmpfp_fixup(_masm);
9384 %}
9385 ins_pipe( pipe_slow );
9386 %}
9387
9388 instruct cmpD_ccmemCF(eFlagsRegUCF cr, regD src1, memory src2) %{
9389 predicate(UseSSE>=2);
9390 match(Set cr (CmpD src1 (LoadD src2)));
9391 ins_cost(100);
9392 format %{ "UCOMISD $src1,$src2" %}
9393 ins_encode %{
9394 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9395 %}
9396 ins_pipe( pipe_slow );
9397 %}
9398
9399 // Compare into -1,0,1 in XMM
9400 instruct cmpD_reg(xRegI dst, regD src1, regD src2, eFlagsReg cr) %{
9401 predicate(UseSSE>=2);
9402 match(Set dst (CmpD3 src1 src2));
9403 effect(KILL cr);
9404 ins_cost(255);
9405 format %{ "UCOMISD $src1, $src2\n\t"
9406 "MOV $dst, #-1\n\t"
9407 "JP,s done\n\t"
9408 "JB,s done\n\t"
9409 "SETNE $dst\n\t"
9410 "MOVZB $dst, $dst\n"
9411 "done:" %}
9412 ins_encode %{
9413 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9414 emit_cmpfp3(_masm, $dst$$Register);
9415 %}
9416 ins_pipe( pipe_slow );
9417 %}
9418
9419 // Compare into -1,0,1 in XMM and memory
9420 instruct cmpD_regmem(xRegI dst, regD src1, memory src2, eFlagsReg cr) %{
9421 predicate(UseSSE>=2);
9422 match(Set dst (CmpD3 src1 (LoadD src2)));
9423 effect(KILL cr);
9424 ins_cost(275);
9425 format %{ "UCOMISD $src1, $src2\n\t"
9426 "MOV $dst, #-1\n\t"
9427 "JP,s done\n\t"
9428 "JB,s done\n\t"
9429 "SETNE $dst\n\t"
9430 "MOVZB $dst, $dst\n"
9431 "done:" %}
9432 ins_encode %{
9433 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9434 emit_cmpfp3(_masm, $dst$$Register);
9435 %}
9436 ins_pipe( pipe_slow );
9437 %}
9438
9439
9440 instruct subDPR_reg(regDPR dst, regDPR src) %{
9441 predicate (UseSSE <=1);
9442 match(Set dst (SubD dst src));
9443
9444 format %{ "FLD $src\n\t"
9445 "DSUBp $dst,ST" %}
9446 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
9447 ins_cost(150);
9448 ins_encode( Push_Reg_DPR(src),
9449 OpcP, RegOpc(dst) );
9450 ins_pipe( fpu_reg_reg );
9451 %}
9452
9453 instruct subDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9454 predicate (UseSSE <=1);
9455 match(Set dst (RoundDouble (SubD src1 src2)));
9456 ins_cost(250);
9457
9458 format %{ "FLD $src2\n\t"
9459 "DSUB ST,$src1\n\t"
9460 "FSTP_D $dst\t# D-round" %}
9461 opcode(0xD8, 0x5);
9462 ins_encode( Push_Reg_DPR(src2),
9463 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) );
9464 ins_pipe( fpu_mem_reg_reg );
9465 %}
9466
9467
9468 instruct subDPR_reg_mem(regDPR dst, memory src) %{
9469 predicate (UseSSE <=1);
9470 match(Set dst (SubD dst (LoadD src)));
9471 ins_cost(150);
9472
9473 format %{ "FLD $src\n\t"
9474 "DSUBp $dst,ST" %}
9475 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9476 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9477 OpcP, RegOpc(dst) );
9478 ins_pipe( fpu_reg_mem );
9479 %}
9480
9481 instruct absDPR_reg(regDPR1 dst, regDPR1 src) %{
9482 predicate (UseSSE<=1);
9483 match(Set dst (AbsD src));
9484 ins_cost(100);
9485 format %{ "FABS" %}
9486 opcode(0xE1, 0xD9);
9487 ins_encode( OpcS, OpcP );
9488 ins_pipe( fpu_reg_reg );
9489 %}
9490
9491 instruct negDPR_reg(regDPR1 dst, regDPR1 src) %{
9492 predicate(UseSSE<=1);
9493 match(Set dst (NegD src));
9494 ins_cost(100);
9495 format %{ "FCHS" %}
9496 opcode(0xE0, 0xD9);
9497 ins_encode( OpcS, OpcP );
9498 ins_pipe( fpu_reg_reg );
9499 %}
9500
9501 instruct addDPR_reg(regDPR dst, regDPR src) %{
9502 predicate(UseSSE<=1);
9503 match(Set dst (AddD dst src));
9504 format %{ "FLD $src\n\t"
9505 "DADD $dst,ST" %}
9506 size(4);
9507 ins_cost(150);
9508 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
9509 ins_encode( Push_Reg_DPR(src),
9510 OpcP, RegOpc(dst) );
9511 ins_pipe( fpu_reg_reg );
9512 %}
9513
9514
9515 instruct addDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9516 predicate(UseSSE<=1);
9517 match(Set dst (RoundDouble (AddD src1 src2)));
9518 ins_cost(250);
9519
9520 format %{ "FLD $src2\n\t"
9521 "DADD ST,$src1\n\t"
9522 "FSTP_D $dst\t# D-round" %}
9523 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/
9524 ins_encode( Push_Reg_DPR(src2),
9525 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) );
9526 ins_pipe( fpu_mem_reg_reg );
9527 %}
9528
9529
9530 instruct addDPR_reg_mem(regDPR dst, memory src) %{
9531 predicate(UseSSE<=1);
9532 match(Set dst (AddD dst (LoadD src)));
9533 ins_cost(150);
9534
9535 format %{ "FLD $src\n\t"
9536 "DADDp $dst,ST" %}
9537 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9538 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9539 OpcP, RegOpc(dst) );
9540 ins_pipe( fpu_reg_mem );
9541 %}
9542
9543 // add-to-memory
9544 instruct addDPR_mem_reg(memory dst, regDPR src) %{
9545 predicate(UseSSE<=1);
9546 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src))));
9547 ins_cost(150);
9548
9549 format %{ "FLD_D $dst\n\t"
9550 "DADD ST,$src\n\t"
9551 "FST_D $dst" %}
9552 opcode(0xDD, 0x0);
9553 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst),
9554 Opcode(0xD8), RegOpc(src),
9555 set_instruction_start,
9556 Opcode(0xDD), RMopc_Mem(0x03,dst) );
9557 ins_pipe( fpu_reg_mem );
9558 %}
9559
9560 instruct addDPR_reg_imm1(regDPR dst, immDPR1 con) %{
9561 predicate(UseSSE<=1);
9562 match(Set dst (AddD dst con));
9563 ins_cost(125);
9564 format %{ "FLD1\n\t"
9565 "DADDp $dst,ST" %}
9566 ins_encode %{
9567 __ fld1();
9568 __ faddp($dst$$reg);
9569 %}
9570 ins_pipe(fpu_reg);
9571 %}
9572
9573 instruct addDPR_reg_imm(regDPR dst, immDPR con) %{
9574 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9575 match(Set dst (AddD dst con));
9576 ins_cost(200);
9577 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9578 "DADDp $dst,ST" %}
9579 ins_encode %{
9580 __ fld_d($constantaddress($con));
9581 __ faddp($dst$$reg);
9582 %}
9583 ins_pipe(fpu_reg_mem);
9584 %}
9585
9586 instruct addDPR_reg_imm_round(stackSlotD dst, regDPR src, immDPR con) %{
9587 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 );
9588 match(Set dst (RoundDouble (AddD src con)));
9589 ins_cost(200);
9590 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9591 "DADD ST,$src\n\t"
9592 "FSTP_D $dst\t# D-round" %}
9593 ins_encode %{
9594 __ fld_d($constantaddress($con));
9595 __ fadd($src$$reg);
9596 __ fstp_d(Address(rsp, $dst$$disp));
9597 %}
9598 ins_pipe(fpu_mem_reg_con);
9599 %}
9600
9601 instruct mulDPR_reg(regDPR dst, regDPR src) %{
9602 predicate(UseSSE<=1);
9603 match(Set dst (MulD dst src));
9604 format %{ "FLD $src\n\t"
9605 "DMULp $dst,ST" %}
9606 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9607 ins_cost(150);
9608 ins_encode( Push_Reg_DPR(src),
9609 OpcP, RegOpc(dst) );
9610 ins_pipe( fpu_reg_reg );
9611 %}
9612
9613 // Strict FP instruction biases argument before multiply then
9614 // biases result to avoid double rounding of subnormals.
9615 //
9616 // scale arg1 by multiplying arg1 by 2^(-15360)
9617 // load arg2
9618 // multiply scaled arg1 by arg2
9619 // rescale product by 2^(15360)
9620 //
9621 instruct strictfp_mulDPR_reg(regDPR1 dst, regnotDPR1 src) %{
9622 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9623 match(Set dst (MulD dst src));
9624 ins_cost(1); // Select this instruction for all strict FP double multiplies
9625
9626 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
9627 "DMULp $dst,ST\n\t"
9628 "FLD $src\n\t"
9629 "DMULp $dst,ST\n\t"
9630 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
9631 "DMULp $dst,ST\n\t" %}
9632 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9633 ins_encode( strictfp_bias1(dst),
9634 Push_Reg_DPR(src),
9635 OpcP, RegOpc(dst),
9636 strictfp_bias2(dst) );
9637 ins_pipe( fpu_reg_reg );
9638 %}
9639
9640 instruct mulDPR_reg_imm(regDPR dst, immDPR con) %{
9641 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9642 match(Set dst (MulD dst con));
9643 ins_cost(200);
9644 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9645 "DMULp $dst,ST" %}
9646 ins_encode %{
9647 __ fld_d($constantaddress($con));
9648 __ fmulp($dst$$reg);
9649 %}
9650 ins_pipe(fpu_reg_mem);
9651 %}
9652
9653
9654 instruct mulDPR_reg_mem(regDPR dst, memory src) %{
9655 predicate( UseSSE<=1 );
9656 match(Set dst (MulD dst (LoadD src)));
9657 ins_cost(200);
9658 format %{ "FLD_D $src\n\t"
9659 "DMULp $dst,ST" %}
9660 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */
9661 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9662 OpcP, RegOpc(dst) );
9663 ins_pipe( fpu_reg_mem );
9664 %}
9665
9666 //
9667 // Cisc-alternate to reg-reg multiply
9668 instruct mulDPR_reg_mem_cisc(regDPR dst, regDPR src, memory mem) %{
9669 predicate( UseSSE<=1 );
9670 match(Set dst (MulD src (LoadD mem)));
9671 ins_cost(250);
9672 format %{ "FLD_D $mem\n\t"
9673 "DMUL ST,$src\n\t"
9674 "FSTP_D $dst" %}
9675 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */
9676 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem),
9677 OpcReg_FPR(src),
9678 Pop_Reg_DPR(dst) );
9679 ins_pipe( fpu_reg_reg_mem );
9680 %}
9681
9682
9683 // MACRO3 -- addDPR a mulDPR
9684 // This instruction is a '2-address' instruction in that the result goes
9685 // back to src2. This eliminates a move from the macro; possibly the
9686 // register allocator will have to add it back (and maybe not).
9687 instruct addDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{
9688 predicate( UseSSE<=1 );
9689 match(Set src2 (AddD (MulD src0 src1) src2));
9690 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
9691 "DMUL ST,$src1\n\t"
9692 "DADDp $src2,ST" %}
9693 ins_cost(250);
9694 opcode(0xDD); /* LoadD DD /0 */
9695 ins_encode( Push_Reg_FPR(src0),
9696 FMul_ST_reg(src1),
9697 FAddP_reg_ST(src2) );
9698 ins_pipe( fpu_reg_reg_reg );
9699 %}
9700
9701
9702 // MACRO3 -- subDPR a mulDPR
9703 instruct subDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{
9704 predicate( UseSSE<=1 );
9705 match(Set src2 (SubD (MulD src0 src1) src2));
9706 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
9707 "DMUL ST,$src1\n\t"
9708 "DSUBRp $src2,ST" %}
9709 ins_cost(250);
9710 ins_encode( Push_Reg_FPR(src0),
9711 FMul_ST_reg(src1),
9712 Opcode(0xDE), Opc_plus(0xE0,src2));
9713 ins_pipe( fpu_reg_reg_reg );
9714 %}
9715
9716
9717 instruct divDPR_reg(regDPR dst, regDPR src) %{
9718 predicate( UseSSE<=1 );
9719 match(Set dst (DivD dst src));
9720
9721 format %{ "FLD $src\n\t"
9722 "FDIVp $dst,ST" %}
9723 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9724 ins_cost(150);
9725 ins_encode( Push_Reg_DPR(src),
9726 OpcP, RegOpc(dst) );
9727 ins_pipe( fpu_reg_reg );
9728 %}
9729
9730 // Strict FP instruction biases argument before division then
9731 // biases result, to avoid double rounding of subnormals.
9732 //
9733 // scale dividend by multiplying dividend by 2^(-15360)
9734 // load divisor
9735 // divide scaled dividend by divisor
9736 // rescale quotient by 2^(15360)
9737 //
9738 instruct strictfp_divDPR_reg(regDPR1 dst, regnotDPR1 src) %{
9739 predicate (UseSSE<=1);
9740 match(Set dst (DivD dst src));
9741 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9742 ins_cost(01);
9743
9744 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
9745 "DMULp $dst,ST\n\t"
9746 "FLD $src\n\t"
9747 "FDIVp $dst,ST\n\t"
9748 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
9749 "DMULp $dst,ST\n\t" %}
9750 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9751 ins_encode( strictfp_bias1(dst),
9752 Push_Reg_DPR(src),
9753 OpcP, RegOpc(dst),
9754 strictfp_bias2(dst) );
9755 ins_pipe( fpu_reg_reg );
9756 %}
9757
9758 instruct divDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9759 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) );
9760 match(Set dst (RoundDouble (DivD src1 src2)));
9761
9762 format %{ "FLD $src1\n\t"
9763 "FDIV ST,$src2\n\t"
9764 "FSTP_D $dst\t# D-round" %}
9765 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */
9766 ins_encode( Push_Reg_DPR(src1),
9767 OpcP, RegOpc(src2), Pop_Mem_DPR(dst) );
9768 ins_pipe( fpu_mem_reg_reg );
9769 %}
9770
9771
9772 instruct modDPR_reg(regDPR dst, regDPR src, eAXRegI rax, eFlagsReg cr) %{
9773 predicate(UseSSE<=1);
9774 match(Set dst (ModD dst src));
9775 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
9776
9777 format %{ "DMOD $dst,$src" %}
9778 ins_cost(250);
9779 ins_encode(Push_Reg_Mod_DPR(dst, src),
9780 emitModDPR(),
9781 Push_Result_Mod_DPR(src),
9782 Pop_Reg_DPR(dst));
9783 ins_pipe( pipe_slow );
9784 %}
9785
9786 instruct modD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eFlagsReg cr) %{
9787 predicate(UseSSE>=2);
9788 match(Set dst (ModD src0 src1));
9789 effect(KILL rax, KILL cr);
9790
9791 format %{ "SUB ESP,8\t # DMOD\n"
9792 "\tMOVSD [ESP+0],$src1\n"
9793 "\tFLD_D [ESP+0]\n"
9794 "\tMOVSD [ESP+0],$src0\n"
9795 "\tFLD_D [ESP+0]\n"
9796 "loop:\tFPREM\n"
9797 "\tFWAIT\n"
9798 "\tFNSTSW AX\n"
9799 "\tSAHF\n"
9800 "\tJP loop\n"
9801 "\tFSTP_D [ESP+0]\n"
9802 "\tMOVSD $dst,[ESP+0]\n"
9803 "\tADD ESP,8\n"
9804 "\tFSTP ST0\t # Restore FPU Stack"
9805 %}
9806 ins_cost(250);
9807 ins_encode( Push_ModD_encoding(src0, src1), emitModDPR(), Push_ResultD(dst), PopFPU);
9808 ins_pipe( pipe_slow );
9809 %}
9810
9811 instruct sinDPR_reg(regDPR1 dst, regDPR1 src) %{
9812 predicate (UseSSE<=1);
9813 match(Set dst (SinD src));
9814 ins_cost(1800);
9815 format %{ "DSIN $dst" %}
9816 opcode(0xD9, 0xFE);
9817 ins_encode( OpcP, OpcS );
9818 ins_pipe( pipe_slow );
9819 %}
9820
9821 instruct sinD_reg(regD dst, eFlagsReg cr) %{
9822 predicate (UseSSE>=2);
9823 match(Set dst (SinD dst));
9824 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9825 ins_cost(1800);
9826 format %{ "DSIN $dst" %}
9827 opcode(0xD9, 0xFE);
9828 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
9829 ins_pipe( pipe_slow );
9830 %}
9831
9832 instruct cosDPR_reg(regDPR1 dst, regDPR1 src) %{
9833 predicate (UseSSE<=1);
9834 match(Set dst (CosD src));
9835 ins_cost(1800);
9836 format %{ "DCOS $dst" %}
9837 opcode(0xD9, 0xFF);
9838 ins_encode( OpcP, OpcS );
9839 ins_pipe( pipe_slow );
9840 %}
9841
9842 instruct cosD_reg(regD dst, eFlagsReg cr) %{
9843 predicate (UseSSE>=2);
9844 match(Set dst (CosD dst));
9845 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9846 ins_cost(1800);
9847 format %{ "DCOS $dst" %}
9848 opcode(0xD9, 0xFF);
9849 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
9850 ins_pipe( pipe_slow );
9851 %}
9852
9853 instruct tanDPR_reg(regDPR1 dst, regDPR1 src) %{
9854 predicate (UseSSE<=1);
9855 match(Set dst(TanD src));
9856 format %{ "DTAN $dst" %}
9857 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan
9858 Opcode(0xDD), Opcode(0xD8)); // fstp st
9859 ins_pipe( pipe_slow );
9860 %}
9861
9862 instruct tanD_reg(regD dst, eFlagsReg cr) %{
9863 predicate (UseSSE>=2);
9864 match(Set dst(TanD dst));
9865 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9866 format %{ "DTAN $dst" %}
9867 ins_encode( Push_SrcD(dst),
9868 Opcode(0xD9), Opcode(0xF2), // fptan
9869 Opcode(0xDD), Opcode(0xD8), // fstp st
9870 Push_ResultD(dst) );
9871 ins_pipe( pipe_slow );
9872 %}
9873
9874 instruct atanDPR_reg(regDPR dst, regDPR src) %{
9875 predicate (UseSSE<=1);
9876 match(Set dst(AtanD dst src));
9877 format %{ "DATA $dst,$src" %}
9878 opcode(0xD9, 0xF3);
9879 ins_encode( Push_Reg_DPR(src),
9880 OpcP, OpcS, RegOpc(dst) );
9881 ins_pipe( pipe_slow );
9882 %}
9883
9884 instruct atanD_reg(regD dst, regD src, eFlagsReg cr) %{
9885 predicate (UseSSE>=2);
9886 match(Set dst(AtanD dst src));
9887 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9888 format %{ "DATA $dst,$src" %}
9889 opcode(0xD9, 0xF3);
9890 ins_encode( Push_SrcD(src),
9891 OpcP, OpcS, Push_ResultD(dst) );
9892 ins_pipe( pipe_slow );
9893 %}
9894
9895 instruct sqrtDPR_reg(regDPR dst, regDPR src) %{
9896 predicate (UseSSE<=1);
9897 match(Set dst (SqrtD src));
9898 format %{ "DSQRT $dst,$src" %}
9899 opcode(0xFA, 0xD9);
9900 ins_encode( Push_Reg_DPR(src),
9901 OpcS, OpcP, Pop_Reg_DPR(dst) );
9902 ins_pipe( pipe_slow );
9903 %}
9904
9905 instruct powDPR_reg(regDPR X, regDPR1 Y, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
9906 predicate (UseSSE<=1);
9907 match(Set Y (PowD X Y)); // Raise X to the Yth power
9908 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
9909 format %{ "fast_pow $X $Y -> $Y // KILL $rax, $rcx, $rdx" %}
9910 ins_encode %{
9911 __ subptr(rsp, 8);
9912 __ fld_s($X$$reg - 1);
9913 __ fast_pow();
9914 __ addptr(rsp, 8);
9915 %}
9916 ins_pipe( pipe_slow );
9917 %}
9918
9919 instruct powD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
9920 predicate (UseSSE>=2);
9921 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
9922 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
9923 format %{ "fast_pow $src0 $src1 -> $dst // KILL $rax, $rcx, $rdx" %}
9924 ins_encode %{
9925 __ subptr(rsp, 8);
9926 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
9927 __ fld_d(Address(rsp, 0));
9928 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
9929 __ fld_d(Address(rsp, 0));
9930 __ fast_pow();
9931 __ fstp_d(Address(rsp, 0));
9932 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
9933 __ addptr(rsp, 8);
9934 %}
9935 ins_pipe( pipe_slow );
9936 %}
9937
9938
9939 instruct expDPR_reg(regDPR1 dpr1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
9940 predicate (UseSSE<=1);
9941 match(Set dpr1 (ExpD dpr1));
9942 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
9943 format %{ "fast_exp $dpr1 -> $dpr1 // KILL $rax, $rcx, $rdx" %}
9944 ins_encode %{
9945 __ fast_exp();
9946 %}
9947 ins_pipe( pipe_slow );
9948 %}
9949
9950 instruct expD_reg(regD dst, regD src, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
9951 predicate (UseSSE>=2);
9952 match(Set dst (ExpD src));
9953 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
9954 format %{ "fast_exp $dst -> $src // KILL $rax, $rcx, $rdx" %}
9955 ins_encode %{
9956 __ subptr(rsp, 8);
9957 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
9958 __ fld_d(Address(rsp, 0));
9959 __ fast_exp();
9960 __ fstp_d(Address(rsp, 0));
9961 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
9962 __ addptr(rsp, 8);
9963 %}
9964 ins_pipe( pipe_slow );
9965 %}
9966
9967 instruct log10DPR_reg(regDPR1 dst, regDPR1 src) %{
9968 predicate (UseSSE<=1);
9969 // The source Double operand on FPU stack
9970 match(Set dst (Log10D src));
9971 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
9972 // fxch ; swap ST(0) with ST(1)
9973 // fyl2x ; compute log_10(2) * log_2(x)
9974 format %{ "FLDLG2 \t\t\t#Log10\n\t"
9975 "FXCH \n\t"
9976 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
9977 %}
9978 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
9979 Opcode(0xD9), Opcode(0xC9), // fxch
9980 Opcode(0xD9), Opcode(0xF1)); // fyl2x
9981
9982 ins_pipe( pipe_slow );
9983 %}
9984
9985 instruct log10D_reg(regD dst, regD src, eFlagsReg cr) %{
9986 predicate (UseSSE>=2);
9987 effect(KILL cr);
9988 match(Set dst (Log10D src));
9989 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
9990 // fyl2x ; compute log_10(2) * log_2(x)
9991 format %{ "FLDLG2 \t\t\t#Log10\n\t"
9992 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
9993 %}
9994 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
9995 Push_SrcD(src),
9996 Opcode(0xD9), Opcode(0xF1), // fyl2x
9997 Push_ResultD(dst));
9998
9999 ins_pipe( pipe_slow );
10000 %}
10001
10002 instruct logDPR_reg(regDPR1 dst, regDPR1 src) %{
10003 predicate (UseSSE<=1);
10004 // The source Double operand on FPU stack
10005 match(Set dst (LogD src));
10006 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10007 // fxch ; swap ST(0) with ST(1)
10008 // fyl2x ; compute log_e(2) * log_2(x)
10009 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10010 "FXCH \n\t"
10011 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10012 %}
10013 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10014 Opcode(0xD9), Opcode(0xC9), // fxch
10015 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10016
10017 ins_pipe( pipe_slow );
10018 %}
10019
10020 instruct logD_reg(regD dst, regD src, eFlagsReg cr) %{
10021 predicate (UseSSE>=2);
10022 effect(KILL cr);
10023 // The source and result Double operands in XMM registers
10024 match(Set dst (LogD src));
10025 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10026 // fyl2x ; compute log_e(2) * log_2(x)
10027 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10028 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10029 %}
10030 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10031 Push_SrcD(src),
10032 Opcode(0xD9), Opcode(0xF1), // fyl2x
10033 Push_ResultD(dst));
10034 ins_pipe( pipe_slow );
10035 %}
10036
10037 //-------------Float Instructions-------------------------------
10038 // Float Math
10039
10040 // Code for float compare:
10041 // fcompp();
10042 // fwait(); fnstsw_ax();
10043 // sahf();
10044 // movl(dst, unordered_result);
10045 // jcc(Assembler::parity, exit);
10046 // movl(dst, less_result);
10047 // jcc(Assembler::below, exit);
10048 // movl(dst, equal_result);
10049 // jcc(Assembler::equal, exit);
10050 // movl(dst, greater_result);
10051 // exit:
10052
10053 // P6 version of float compare, sets condition codes in EFLAGS
10054 instruct cmpFPR_cc_P6(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
10055 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10056 match(Set cr (CmpF src1 src2));
10057 effect(KILL rax);
10058 ins_cost(150);
10059 format %{ "FLD $src1\n\t"
10060 "FUCOMIP ST,$src2 // P6 instruction\n\t"
10061 "JNP exit\n\t"
10062 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t"
10063 "SAHF\n"
10064 "exit:\tNOP // avoid branch to branch" %}
10065 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10066 ins_encode( Push_Reg_DPR(src1),
10067 OpcP, RegOpc(src2),
10068 cmpF_P6_fixup );
10069 ins_pipe( pipe_slow );
10070 %}
10071
10072 instruct cmpFPR_cc_P6CF(eFlagsRegUCF cr, regFPR src1, regFPR src2) %{
10073 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10074 match(Set cr (CmpF src1 src2));
10075 ins_cost(100);
10076 format %{ "FLD $src1\n\t"
10077 "FUCOMIP ST,$src2 // P6 instruction" %}
10078 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10079 ins_encode( Push_Reg_DPR(src1),
10080 OpcP, RegOpc(src2));
10081 ins_pipe( pipe_slow );
10082 %}
10083
10084
10085 // Compare & branch
10086 instruct cmpFPR_cc(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
10087 predicate(UseSSE == 0);
10088 match(Set cr (CmpF src1 src2));
10089 effect(KILL rax);
10090 ins_cost(200);
10091 format %{ "FLD $src1\n\t"
10092 "FCOMp $src2\n\t"
10093 "FNSTSW AX\n\t"
10094 "TEST AX,0x400\n\t"
10095 "JZ,s flags\n\t"
10096 "MOV AH,1\t# unordered treat as LT\n"
10097 "flags:\tSAHF" %}
10098 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10099 ins_encode( Push_Reg_DPR(src1),
10100 OpcP, RegOpc(src2),
10101 fpu_flags);
10102 ins_pipe( pipe_slow );
10103 %}
10104
10105 // Compare vs zero into -1,0,1
10106 instruct cmpFPR_0(rRegI dst, regFPR src1, immFPR0 zero, eAXRegI rax, eFlagsReg cr) %{
10107 predicate(UseSSE == 0);
10108 match(Set dst (CmpF3 src1 zero));
10109 effect(KILL cr, KILL rax);
10110 ins_cost(280);
10111 format %{ "FTSTF $dst,$src1" %}
10112 opcode(0xE4, 0xD9);
10113 ins_encode( Push_Reg_DPR(src1),
10114 OpcS, OpcP, PopFPU,
10115 CmpF_Result(dst));
10116 ins_pipe( pipe_slow );
10117 %}
10118
10119 // Compare into -1,0,1
10120 instruct cmpFPR_reg(rRegI dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
10121 predicate(UseSSE == 0);
10122 match(Set dst (CmpF3 src1 src2));
10123 effect(KILL cr, KILL rax);
10124 ins_cost(300);
10125 format %{ "FCMPF $dst,$src1,$src2" %}
10126 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10127 ins_encode( Push_Reg_DPR(src1),
10128 OpcP, RegOpc(src2),
10129 CmpF_Result(dst));
10130 ins_pipe( pipe_slow );
10131 %}
10132
10133 // float compare and set condition codes in EFLAGS by XMM regs
10134 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2) %{
10135 predicate(UseSSE>=1);
10136 match(Set cr (CmpF src1 src2));
10137 ins_cost(145);
10138 format %{ "UCOMISS $src1,$src2\n\t"
10139 "JNP,s exit\n\t"
10140 "PUSHF\t# saw NaN, set CF\n\t"
10141 "AND [rsp], #0xffffff2b\n\t"
10142 "POPF\n"
10143 "exit:" %}
10144 ins_encode %{
10145 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10146 emit_cmpfp_fixup(_masm);
10147 %}
10148 ins_pipe( pipe_slow );
10149 %}
10150
10151 instruct cmpF_ccCF(eFlagsRegUCF cr, regF src1, regF src2) %{
10152 predicate(UseSSE>=1);
10153 match(Set cr (CmpF src1 src2));
10154 ins_cost(100);
10155 format %{ "UCOMISS $src1,$src2" %}
10156 ins_encode %{
10157 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10158 %}
10159 ins_pipe( pipe_slow );
10160 %}
10161
10162 // float compare and set condition codes in EFLAGS by XMM regs
10163 instruct cmpF_ccmem(eFlagsRegU cr, regF src1, memory src2) %{
10164 predicate(UseSSE>=1);
10165 match(Set cr (CmpF src1 (LoadF src2)));
10166 ins_cost(165);
10167 format %{ "UCOMISS $src1,$src2\n\t"
10168 "JNP,s exit\n\t"
10169 "PUSHF\t# saw NaN, set CF\n\t"
10170 "AND [rsp], #0xffffff2b\n\t"
10171 "POPF\n"
10172 "exit:" %}
10173 ins_encode %{
10174 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10175 emit_cmpfp_fixup(_masm);
10176 %}
10177 ins_pipe( pipe_slow );
10178 %}
10179
10180 instruct cmpF_ccmemCF(eFlagsRegUCF cr, regF src1, memory src2) %{
10181 predicate(UseSSE>=1);
10182 match(Set cr (CmpF src1 (LoadF src2)));
10183 ins_cost(100);
10184 format %{ "UCOMISS $src1,$src2" %}
10185 ins_encode %{
10186 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10187 %}
10188 ins_pipe( pipe_slow );
10189 %}
10190
10191 // Compare into -1,0,1 in XMM
10192 instruct cmpF_reg(xRegI dst, regF src1, regF src2, eFlagsReg cr) %{
10193 predicate(UseSSE>=1);
10194 match(Set dst (CmpF3 src1 src2));
10195 effect(KILL cr);
10196 ins_cost(255);
10197 format %{ "UCOMISS $src1, $src2\n\t"
10198 "MOV $dst, #-1\n\t"
10199 "JP,s done\n\t"
10200 "JB,s done\n\t"
10201 "SETNE $dst\n\t"
10202 "MOVZB $dst, $dst\n"
10203 "done:" %}
10204 ins_encode %{
10205 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10206 emit_cmpfp3(_masm, $dst$$Register);
10207 %}
10208 ins_pipe( pipe_slow );
10209 %}
10210
10211 // Compare into -1,0,1 in XMM and memory
10212 instruct cmpF_regmem(xRegI dst, regF src1, memory src2, eFlagsReg cr) %{
10213 predicate(UseSSE>=1);
10214 match(Set dst (CmpF3 src1 (LoadF src2)));
10215 effect(KILL cr);
10216 ins_cost(275);
10217 format %{ "UCOMISS $src1, $src2\n\t"
10218 "MOV $dst, #-1\n\t"
10219 "JP,s done\n\t"
10220 "JB,s done\n\t"
10221 "SETNE $dst\n\t"
10222 "MOVZB $dst, $dst\n"
10223 "done:" %}
10224 ins_encode %{
10225 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10226 emit_cmpfp3(_masm, $dst$$Register);
10227 %}
10228 ins_pipe( pipe_slow );
10229 %}
10230
10231 // Spill to obtain 24-bit precision
10232 instruct subFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10233 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10234 match(Set dst (SubF src1 src2));
10235
10236 format %{ "FSUB $dst,$src1 - $src2" %}
10237 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */
10238 ins_encode( Push_Reg_FPR(src1),
10239 OpcReg_FPR(src2),
10240 Pop_Mem_FPR(dst) );
10241 ins_pipe( fpu_mem_reg_reg );
10242 %}
10243 //
10244 // This instruction does not round to 24-bits
10245 instruct subFPR_reg(regFPR dst, regFPR src) %{
10246 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10247 match(Set dst (SubF dst src));
10248
10249 format %{ "FSUB $dst,$src" %}
10250 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
10251 ins_encode( Push_Reg_FPR(src),
10252 OpcP, RegOpc(dst) );
10253 ins_pipe( fpu_reg_reg );
10254 %}
10255
10256 // Spill to obtain 24-bit precision
10257 instruct addFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10258 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10259 match(Set dst (AddF src1 src2));
10260
10261 format %{ "FADD $dst,$src1,$src2" %}
10262 opcode(0xD8, 0x0); /* D8 C0+i */
10263 ins_encode( Push_Reg_FPR(src2),
10264 OpcReg_FPR(src1),
10265 Pop_Mem_FPR(dst) );
10266 ins_pipe( fpu_mem_reg_reg );
10267 %}
10268 //
10269 // This instruction does not round to 24-bits
10270 instruct addFPR_reg(regFPR dst, regFPR src) %{
10271 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10272 match(Set dst (AddF dst src));
10273
10274 format %{ "FLD $src\n\t"
10275 "FADDp $dst,ST" %}
10276 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
10277 ins_encode( Push_Reg_FPR(src),
10278 OpcP, RegOpc(dst) );
10279 ins_pipe( fpu_reg_reg );
10280 %}
10281
10282 instruct absFPR_reg(regFPR1 dst, regFPR1 src) %{
10283 predicate(UseSSE==0);
10284 match(Set dst (AbsF src));
10285 ins_cost(100);
10286 format %{ "FABS" %}
10287 opcode(0xE1, 0xD9);
10288 ins_encode( OpcS, OpcP );
10289 ins_pipe( fpu_reg_reg );
10290 %}
10291
10292 instruct negFPR_reg(regFPR1 dst, regFPR1 src) %{
10293 predicate(UseSSE==0);
10294 match(Set dst (NegF src));
10295 ins_cost(100);
10296 format %{ "FCHS" %}
10297 opcode(0xE0, 0xD9);
10298 ins_encode( OpcS, OpcP );
10299 ins_pipe( fpu_reg_reg );
10300 %}
10301
10302 // Cisc-alternate to addFPR_reg
10303 // Spill to obtain 24-bit precision
10304 instruct addFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{
10305 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10306 match(Set dst (AddF src1 (LoadF src2)));
10307
10308 format %{ "FLD $src2\n\t"
10309 "FADD ST,$src1\n\t"
10310 "FSTP_S $dst" %}
10311 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10312 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10313 OpcReg_FPR(src1),
10314 Pop_Mem_FPR(dst) );
10315 ins_pipe( fpu_mem_reg_mem );
10316 %}
10317 //
10318 // Cisc-alternate to addFPR_reg
10319 // This instruction does not round to 24-bits
10320 instruct addFPR_reg_mem(regFPR dst, memory src) %{
10321 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10322 match(Set dst (AddF dst (LoadF src)));
10323
10324 format %{ "FADD $dst,$src" %}
10325 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */
10326 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10327 OpcP, RegOpc(dst) );
10328 ins_pipe( fpu_reg_mem );
10329 %}
10330
10331 // // Following two instructions for _222_mpegaudio
10332 // Spill to obtain 24-bit precision
10333 instruct addFPR24_mem_reg(stackSlotF dst, regFPR src2, memory src1 ) %{
10334 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10335 match(Set dst (AddF src1 src2));
10336
10337 format %{ "FADD $dst,$src1,$src2" %}
10338 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10339 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1),
10340 OpcReg_FPR(src2),
10341 Pop_Mem_FPR(dst) );
10342 ins_pipe( fpu_mem_reg_mem );
10343 %}
10344
10345 // Cisc-spill variant
10346 // Spill to obtain 24-bit precision
10347 instruct addFPR24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{
10348 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10349 match(Set dst (AddF src1 (LoadF src2)));
10350
10351 format %{ "FADD $dst,$src1,$src2 cisc" %}
10352 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10353 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10354 set_instruction_start,
10355 OpcP, RMopc_Mem(secondary,src1),
10356 Pop_Mem_FPR(dst) );
10357 ins_pipe( fpu_mem_mem_mem );
10358 %}
10359
10360 // Spill to obtain 24-bit precision
10361 instruct addFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10362 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10363 match(Set dst (AddF src1 src2));
10364
10365 format %{ "FADD $dst,$src1,$src2" %}
10366 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */
10367 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10368 set_instruction_start,
10369 OpcP, RMopc_Mem(secondary,src1),
10370 Pop_Mem_FPR(dst) );
10371 ins_pipe( fpu_mem_mem_mem );
10372 %}
10373
10374
10375 // Spill to obtain 24-bit precision
10376 instruct addFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{
10377 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10378 match(Set dst (AddF src con));
10379 format %{ "FLD $src\n\t"
10380 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10381 "FSTP_S $dst" %}
10382 ins_encode %{
10383 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10384 __ fadd_s($constantaddress($con));
10385 __ fstp_s(Address(rsp, $dst$$disp));
10386 %}
10387 ins_pipe(fpu_mem_reg_con);
10388 %}
10389 //
10390 // This instruction does not round to 24-bits
10391 instruct addFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{
10392 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10393 match(Set dst (AddF src con));
10394 format %{ "FLD $src\n\t"
10395 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10396 "FSTP $dst" %}
10397 ins_encode %{
10398 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10399 __ fadd_s($constantaddress($con));
10400 __ fstp_d($dst$$reg);
10401 %}
10402 ins_pipe(fpu_reg_reg_con);
10403 %}
10404
10405 // Spill to obtain 24-bit precision
10406 instruct mulFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10407 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10408 match(Set dst (MulF src1 src2));
10409
10410 format %{ "FLD $src1\n\t"
10411 "FMUL $src2\n\t"
10412 "FSTP_S $dst" %}
10413 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */
10414 ins_encode( Push_Reg_FPR(src1),
10415 OpcReg_FPR(src2),
10416 Pop_Mem_FPR(dst) );
10417 ins_pipe( fpu_mem_reg_reg );
10418 %}
10419 //
10420 // This instruction does not round to 24-bits
10421 instruct mulFPR_reg(regFPR dst, regFPR src1, regFPR src2) %{
10422 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10423 match(Set dst (MulF src1 src2));
10424
10425 format %{ "FLD $src1\n\t"
10426 "FMUL $src2\n\t"
10427 "FSTP_S $dst" %}
10428 opcode(0xD8, 0x1); /* D8 C8+i */
10429 ins_encode( Push_Reg_FPR(src2),
10430 OpcReg_FPR(src1),
10431 Pop_Reg_FPR(dst) );
10432 ins_pipe( fpu_reg_reg_reg );
10433 %}
10434
10435
10436 // Spill to obtain 24-bit precision
10437 // Cisc-alternate to reg-reg multiply
10438 instruct mulFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{
10439 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10440 match(Set dst (MulF src1 (LoadF src2)));
10441
10442 format %{ "FLD_S $src2\n\t"
10443 "FMUL $src1\n\t"
10444 "FSTP_S $dst" %}
10445 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */
10446 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10447 OpcReg_FPR(src1),
10448 Pop_Mem_FPR(dst) );
10449 ins_pipe( fpu_mem_reg_mem );
10450 %}
10451 //
10452 // This instruction does not round to 24-bits
10453 // Cisc-alternate to reg-reg multiply
10454 instruct mulFPR_reg_mem(regFPR dst, regFPR src1, memory src2) %{
10455 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10456 match(Set dst (MulF src1 (LoadF src2)));
10457
10458 format %{ "FMUL $dst,$src1,$src2" %}
10459 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */
10460 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10461 OpcReg_FPR(src1),
10462 Pop_Reg_FPR(dst) );
10463 ins_pipe( fpu_reg_reg_mem );
10464 %}
10465
10466 // Spill to obtain 24-bit precision
10467 instruct mulFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10468 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10469 match(Set dst (MulF src1 src2));
10470
10471 format %{ "FMUL $dst,$src1,$src2" %}
10472 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */
10473 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10474 set_instruction_start,
10475 OpcP, RMopc_Mem(secondary,src1),
10476 Pop_Mem_FPR(dst) );
10477 ins_pipe( fpu_mem_mem_mem );
10478 %}
10479
10480 // Spill to obtain 24-bit precision
10481 instruct mulFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{
10482 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10483 match(Set dst (MulF src con));
10484
10485 format %{ "FLD $src\n\t"
10486 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10487 "FSTP_S $dst" %}
10488 ins_encode %{
10489 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10490 __ fmul_s($constantaddress($con));
10491 __ fstp_s(Address(rsp, $dst$$disp));
10492 %}
10493 ins_pipe(fpu_mem_reg_con);
10494 %}
10495 //
10496 // This instruction does not round to 24-bits
10497 instruct mulFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{
10498 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10499 match(Set dst (MulF src con));
10500
10501 format %{ "FLD $src\n\t"
10502 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10503 "FSTP $dst" %}
10504 ins_encode %{
10505 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10506 __ fmul_s($constantaddress($con));
10507 __ fstp_d($dst$$reg);
10508 %}
10509 ins_pipe(fpu_reg_reg_con);
10510 %}
10511
10512
10513 //
10514 // MACRO1 -- subsume unshared load into mulFPR
10515 // This instruction does not round to 24-bits
10516 instruct mulFPR_reg_load1(regFPR dst, regFPR src, memory mem1 ) %{
10517 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10518 match(Set dst (MulF (LoadF mem1) src));
10519
10520 format %{ "FLD $mem1 ===MACRO1===\n\t"
10521 "FMUL ST,$src\n\t"
10522 "FSTP $dst" %}
10523 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */
10524 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1),
10525 OpcReg_FPR(src),
10526 Pop_Reg_FPR(dst) );
10527 ins_pipe( fpu_reg_reg_mem );
10528 %}
10529 //
10530 // MACRO2 -- addFPR a mulFPR which subsumed an unshared load
10531 // This instruction does not round to 24-bits
10532 instruct addFPR_mulFPR_reg_load1(regFPR dst, memory mem1, regFPR src1, regFPR src2) %{
10533 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10534 match(Set dst (AddF (MulF (LoadF mem1) src1) src2));
10535 ins_cost(95);
10536
10537 format %{ "FLD $mem1 ===MACRO2===\n\t"
10538 "FMUL ST,$src1 subsume mulFPR left load\n\t"
10539 "FADD ST,$src2\n\t"
10540 "FSTP $dst" %}
10541 opcode(0xD9); /* LoadF D9 /0 */
10542 ins_encode( OpcP, RMopc_Mem(0x00,mem1),
10543 FMul_ST_reg(src1),
10544 FAdd_ST_reg(src2),
10545 Pop_Reg_FPR(dst) );
10546 ins_pipe( fpu_reg_mem_reg_reg );
10547 %}
10548
10549 // MACRO3 -- addFPR a mulFPR
10550 // This instruction does not round to 24-bits. It is a '2-address'
10551 // instruction in that the result goes back to src2. This eliminates
10552 // a move from the macro; possibly the register allocator will have
10553 // to add it back (and maybe not).
10554 instruct addFPR_mulFPR_reg(regFPR src2, regFPR src1, regFPR src0) %{
10555 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10556 match(Set src2 (AddF (MulF src0 src1) src2));
10557
10558 format %{ "FLD $src0 ===MACRO3===\n\t"
10559 "FMUL ST,$src1\n\t"
10560 "FADDP $src2,ST" %}
10561 opcode(0xD9); /* LoadF D9 /0 */
10562 ins_encode( Push_Reg_FPR(src0),
10563 FMul_ST_reg(src1),
10564 FAddP_reg_ST(src2) );
10565 ins_pipe( fpu_reg_reg_reg );
10566 %}
10567
10568 // MACRO4 -- divFPR subFPR
10569 // This instruction does not round to 24-bits
10570 instruct subFPR_divFPR_reg(regFPR dst, regFPR src1, regFPR src2, regFPR src3) %{
10571 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10572 match(Set dst (DivF (SubF src2 src1) src3));
10573
10574 format %{ "FLD $src2 ===MACRO4===\n\t"
10575 "FSUB ST,$src1\n\t"
10576 "FDIV ST,$src3\n\t"
10577 "FSTP $dst" %}
10578 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10579 ins_encode( Push_Reg_FPR(src2),
10580 subFPR_divFPR_encode(src1,src3),
10581 Pop_Reg_FPR(dst) );
10582 ins_pipe( fpu_reg_reg_reg_reg );
10583 %}
10584
10585 // Spill to obtain 24-bit precision
10586 instruct divFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10587 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10588 match(Set dst (DivF src1 src2));
10589
10590 format %{ "FDIV $dst,$src1,$src2" %}
10591 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/
10592 ins_encode( Push_Reg_FPR(src1),
10593 OpcReg_FPR(src2),
10594 Pop_Mem_FPR(dst) );
10595 ins_pipe( fpu_mem_reg_reg );
10596 %}
10597 //
10598 // This instruction does not round to 24-bits
10599 instruct divFPR_reg(regFPR dst, regFPR src) %{
10600 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10601 match(Set dst (DivF dst src));
10602
10603 format %{ "FDIV $dst,$src" %}
10604 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10605 ins_encode( Push_Reg_FPR(src),
10606 OpcP, RegOpc(dst) );
10607 ins_pipe( fpu_reg_reg );
10608 %}
10609
10610
10611 // Spill to obtain 24-bit precision
10612 instruct modFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
10613 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
10614 match(Set dst (ModF src1 src2));
10615 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10616
10617 format %{ "FMOD $dst,$src1,$src2" %}
10618 ins_encode( Push_Reg_Mod_DPR(src1, src2),
10619 emitModDPR(),
10620 Push_Result_Mod_DPR(src2),
10621 Pop_Mem_FPR(dst));
10622 ins_pipe( pipe_slow );
10623 %}
10624 //
10625 // This instruction does not round to 24-bits
10626 instruct modFPR_reg(regFPR dst, regFPR src, eAXRegI rax, eFlagsReg cr) %{
10627 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
10628 match(Set dst (ModF dst src));
10629 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10630
10631 format %{ "FMOD $dst,$src" %}
10632 ins_encode(Push_Reg_Mod_DPR(dst, src),
10633 emitModDPR(),
10634 Push_Result_Mod_DPR(src),
10635 Pop_Reg_FPR(dst));
10636 ins_pipe( pipe_slow );
10637 %}
10638
10639 instruct modF_reg(regF dst, regF src0, regF src1, eAXRegI rax, eFlagsReg cr) %{
10640 predicate(UseSSE>=1);
10641 match(Set dst (ModF src0 src1));
10642 effect(KILL rax, KILL cr);
10643 format %{ "SUB ESP,4\t # FMOD\n"
10644 "\tMOVSS [ESP+0],$src1\n"
10645 "\tFLD_S [ESP+0]\n"
10646 "\tMOVSS [ESP+0],$src0\n"
10647 "\tFLD_S [ESP+0]\n"
10648 "loop:\tFPREM\n"
10649 "\tFWAIT\n"
10650 "\tFNSTSW AX\n"
10651 "\tSAHF\n"
10652 "\tJP loop\n"
10653 "\tFSTP_S [ESP+0]\n"
10654 "\tMOVSS $dst,[ESP+0]\n"
10655 "\tADD ESP,4\n"
10656 "\tFSTP ST0\t # Restore FPU Stack"
10657 %}
10658 ins_cost(250);
10659 ins_encode( Push_ModF_encoding(src0, src1), emitModDPR(), Push_ResultF(dst,0x4), PopFPU);
10660 ins_pipe( pipe_slow );
10661 %}
10662
10663
10664 //----------Arithmetic Conversion Instructions---------------------------------
10665 // The conversions operations are all Alpha sorted. Please keep it that way!
10666
10667 instruct roundFloat_mem_reg(stackSlotF dst, regFPR src) %{
10668 predicate(UseSSE==0);
10669 match(Set dst (RoundFloat src));
10670 ins_cost(125);
10671 format %{ "FST_S $dst,$src\t# F-round" %}
10672 ins_encode( Pop_Mem_Reg_FPR(dst, src) );
10673 ins_pipe( fpu_mem_reg );
10674 %}
10675
10676 instruct roundDouble_mem_reg(stackSlotD dst, regDPR src) %{
10677 predicate(UseSSE<=1);
10678 match(Set dst (RoundDouble src));
10679 ins_cost(125);
10680 format %{ "FST_D $dst,$src\t# D-round" %}
10681 ins_encode( Pop_Mem_Reg_DPR(dst, src) );
10682 ins_pipe( fpu_mem_reg );
10683 %}
10684
10685 // Force rounding to 24-bit precision and 6-bit exponent
10686 instruct convDPR2FPR_reg(stackSlotF dst, regDPR src) %{
10687 predicate(UseSSE==0);
10688 match(Set dst (ConvD2F src));
10689 format %{ "FST_S $dst,$src\t# F-round" %}
10690 expand %{
10691 roundFloat_mem_reg(dst,src);
10692 %}
10693 %}
10694
10695 // Force rounding to 24-bit precision and 6-bit exponent
10696 instruct convDPR2F_reg(regF dst, regDPR src, eFlagsReg cr) %{
10697 predicate(UseSSE==1);
10698 match(Set dst (ConvD2F src));
10699 effect( KILL cr );
10700 format %{ "SUB ESP,4\n\t"
10701 "FST_S [ESP],$src\t# F-round\n\t"
10702 "MOVSS $dst,[ESP]\n\t"
10703 "ADD ESP,4" %}
10704 ins_encode %{
10705 __ subptr(rsp, 4);
10706 if ($src$$reg != FPR1L_enc) {
10707 __ fld_s($src$$reg-1);
10708 __ fstp_s(Address(rsp, 0));
10709 } else {
10710 __ fst_s(Address(rsp, 0));
10711 }
10712 __ movflt($dst$$XMMRegister, Address(rsp, 0));
10713 __ addptr(rsp, 4);
10714 %}
10715 ins_pipe( pipe_slow );
10716 %}
10717
10718 // Force rounding double precision to single precision
10719 instruct convD2F_reg(regF dst, regD src) %{
10720 predicate(UseSSE>=2);
10721 match(Set dst (ConvD2F src));
10722 format %{ "CVTSD2SS $dst,$src\t# F-round" %}
10723 ins_encode %{
10724 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
10725 %}
10726 ins_pipe( pipe_slow );
10727 %}
10728
10729 instruct convFPR2DPR_reg_reg(regDPR dst, regFPR src) %{
10730 predicate(UseSSE==0);
10731 match(Set dst (ConvF2D src));
10732 format %{ "FST_S $dst,$src\t# D-round" %}
10733 ins_encode( Pop_Reg_Reg_DPR(dst, src));
10734 ins_pipe( fpu_reg_reg );
10735 %}
10736
10737 instruct convFPR2D_reg(stackSlotD dst, regFPR src) %{
10738 predicate(UseSSE==1);
10739 match(Set dst (ConvF2D src));
10740 format %{ "FST_D $dst,$src\t# D-round" %}
10741 expand %{
10742 roundDouble_mem_reg(dst,src);
10743 %}
10744 %}
10745
10746 instruct convF2DPR_reg(regDPR dst, regF src, eFlagsReg cr) %{
10747 predicate(UseSSE==1);
10748 match(Set dst (ConvF2D src));
10749 effect( KILL cr );
10750 format %{ "SUB ESP,4\n\t"
10751 "MOVSS [ESP] $src\n\t"
10752 "FLD_S [ESP]\n\t"
10753 "ADD ESP,4\n\t"
10754 "FSTP $dst\t# D-round" %}
10755 ins_encode %{
10756 __ subptr(rsp, 4);
10757 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10758 __ fld_s(Address(rsp, 0));
10759 __ addptr(rsp, 4);
10760 __ fstp_d($dst$$reg);
10761 %}
10762 ins_pipe( pipe_slow );
10763 %}
10764
10765 instruct convF2D_reg(regD dst, regF src) %{
10766 predicate(UseSSE>=2);
10767 match(Set dst (ConvF2D src));
10768 format %{ "CVTSS2SD $dst,$src\t# D-round" %}
10769 ins_encode %{
10770 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
10771 %}
10772 ins_pipe( pipe_slow );
10773 %}
10774
10775 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
10776 instruct convDPR2I_reg_reg( eAXRegI dst, eDXRegI tmp, regDPR src, eFlagsReg cr ) %{
10777 predicate(UseSSE<=1);
10778 match(Set dst (ConvD2I src));
10779 effect( KILL tmp, KILL cr );
10780 format %{ "FLD $src\t# Convert double to int \n\t"
10781 "FLDCW trunc mode\n\t"
10782 "SUB ESP,4\n\t"
10783 "FISTp [ESP + #0]\n\t"
10784 "FLDCW std/24-bit mode\n\t"
10785 "POP EAX\n\t"
10786 "CMP EAX,0x80000000\n\t"
10787 "JNE,s fast\n\t"
10788 "FLD_D $src\n\t"
10789 "CALL d2i_wrapper\n"
10790 "fast:" %}
10791 ins_encode( Push_Reg_DPR(src), DPR2I_encoding(src) );
10792 ins_pipe( pipe_slow );
10793 %}
10794
10795 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
10796 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{
10797 predicate(UseSSE>=2);
10798 match(Set dst (ConvD2I src));
10799 effect( KILL tmp, KILL cr );
10800 format %{ "CVTTSD2SI $dst, $src\n\t"
10801 "CMP $dst,0x80000000\n\t"
10802 "JNE,s fast\n\t"
10803 "SUB ESP, 8\n\t"
10804 "MOVSD [ESP], $src\n\t"
10805 "FLD_D [ESP]\n\t"
10806 "ADD ESP, 8\n\t"
10807 "CALL d2i_wrapper\n"
10808 "fast:" %}
10809 ins_encode %{
10810 Label fast;
10811 __ cvttsd2sil($dst$$Register, $src$$XMMRegister);
10812 __ cmpl($dst$$Register, 0x80000000);
10813 __ jccb(Assembler::notEqual, fast);
10814 __ subptr(rsp, 8);
10815 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10816 __ fld_d(Address(rsp, 0));
10817 __ addptr(rsp, 8);
10818 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
10819 __ bind(fast);
10820 %}
10821 ins_pipe( pipe_slow );
10822 %}
10823
10824 instruct convDPR2L_reg_reg( eADXRegL dst, regDPR src, eFlagsReg cr ) %{
10825 predicate(UseSSE<=1);
10826 match(Set dst (ConvD2L src));
10827 effect( KILL cr );
10828 format %{ "FLD $src\t# Convert double to long\n\t"
10829 "FLDCW trunc mode\n\t"
10830 "SUB ESP,8\n\t"
10831 "FISTp [ESP + #0]\n\t"
10832 "FLDCW std/24-bit mode\n\t"
10833 "POP EAX\n\t"
10834 "POP EDX\n\t"
10835 "CMP EDX,0x80000000\n\t"
10836 "JNE,s fast\n\t"
10837 "TEST EAX,EAX\n\t"
10838 "JNE,s fast\n\t"
10839 "FLD $src\n\t"
10840 "CALL d2l_wrapper\n"
10841 "fast:" %}
10842 ins_encode( Push_Reg_DPR(src), DPR2L_encoding(src) );
10843 ins_pipe( pipe_slow );
10844 %}
10845
10846 // XMM lacks a float/double->long conversion, so use the old FPU stack.
10847 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{
10848 predicate (UseSSE>=2);
10849 match(Set dst (ConvD2L src));
10850 effect( KILL cr );
10851 format %{ "SUB ESP,8\t# Convert double to long\n\t"
10852 "MOVSD [ESP],$src\n\t"
10853 "FLD_D [ESP]\n\t"
10854 "FLDCW trunc mode\n\t"
10855 "FISTp [ESP + #0]\n\t"
10856 "FLDCW std/24-bit mode\n\t"
10857 "POP EAX\n\t"
10858 "POP EDX\n\t"
10859 "CMP EDX,0x80000000\n\t"
10860 "JNE,s fast\n\t"
10861 "TEST EAX,EAX\n\t"
10862 "JNE,s fast\n\t"
10863 "SUB ESP,8\n\t"
10864 "MOVSD [ESP],$src\n\t"
10865 "FLD_D [ESP]\n\t"
10866 "ADD ESP,8\n\t"
10867 "CALL d2l_wrapper\n"
10868 "fast:" %}
10869 ins_encode %{
10870 Label fast;
10871 __ subptr(rsp, 8);
10872 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10873 __ fld_d(Address(rsp, 0));
10874 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
10875 __ fistp_d(Address(rsp, 0));
10876 // Restore the rounding mode, mask the exception
10877 if (Compile::current()->in_24_bit_fp_mode()) {
10878 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
10879 } else {
10880 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
10881 }
10882 // Load the converted long, adjust CPU stack
10883 __ pop(rax);
10884 __ pop(rdx);
10885 __ cmpl(rdx, 0x80000000);
10886 __ jccb(Assembler::notEqual, fast);
10887 __ testl(rax, rax);
10888 __ jccb(Assembler::notEqual, fast);
10889 __ subptr(rsp, 8);
10890 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10891 __ fld_d(Address(rsp, 0));
10892 __ addptr(rsp, 8);
10893 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
10894 __ bind(fast);
10895 %}
10896 ins_pipe( pipe_slow );
10897 %}
10898
10899 // Convert a double to an int. Java semantics require we do complex
10900 // manglations in the corner cases. So we set the rounding mode to
10901 // 'zero', store the darned double down as an int, and reset the
10902 // rounding mode to 'nearest'. The hardware stores a flag value down
10903 // if we would overflow or converted a NAN; we check for this and
10904 // and go the slow path if needed.
10905 instruct convFPR2I_reg_reg(eAXRegI dst, eDXRegI tmp, regFPR src, eFlagsReg cr ) %{
10906 predicate(UseSSE==0);
10907 match(Set dst (ConvF2I src));
10908 effect( KILL tmp, KILL cr );
10909 format %{ "FLD $src\t# Convert float to int \n\t"
10910 "FLDCW trunc mode\n\t"
10911 "SUB ESP,4\n\t"
10912 "FISTp [ESP + #0]\n\t"
10913 "FLDCW std/24-bit mode\n\t"
10914 "POP EAX\n\t"
10915 "CMP EAX,0x80000000\n\t"
10916 "JNE,s fast\n\t"
10917 "FLD $src\n\t"
10918 "CALL d2i_wrapper\n"
10919 "fast:" %}
10920 // DPR2I_encoding works for FPR2I
10921 ins_encode( Push_Reg_FPR(src), DPR2I_encoding(src) );
10922 ins_pipe( pipe_slow );
10923 %}
10924
10925 // Convert a float in xmm to an int reg.
10926 instruct convF2I_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{
10927 predicate(UseSSE>=1);
10928 match(Set dst (ConvF2I src));
10929 effect( KILL tmp, KILL cr );
10930 format %{ "CVTTSS2SI $dst, $src\n\t"
10931 "CMP $dst,0x80000000\n\t"
10932 "JNE,s fast\n\t"
10933 "SUB ESP, 4\n\t"
10934 "MOVSS [ESP], $src\n\t"
10935 "FLD [ESP]\n\t"
10936 "ADD ESP, 4\n\t"
10937 "CALL d2i_wrapper\n"
10938 "fast:" %}
10939 ins_encode %{
10940 Label fast;
10941 __ cvttss2sil($dst$$Register, $src$$XMMRegister);
10942 __ cmpl($dst$$Register, 0x80000000);
10943 __ jccb(Assembler::notEqual, fast);
10944 __ subptr(rsp, 4);
10945 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10946 __ fld_s(Address(rsp, 0));
10947 __ addptr(rsp, 4);
10948 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
10949 __ bind(fast);
10950 %}
10951 ins_pipe( pipe_slow );
10952 %}
10953
10954 instruct convFPR2L_reg_reg( eADXRegL dst, regFPR src, eFlagsReg cr ) %{
10955 predicate(UseSSE==0);
10956 match(Set dst (ConvF2L src));
10957 effect( KILL cr );
10958 format %{ "FLD $src\t# Convert float to long\n\t"
10959 "FLDCW trunc mode\n\t"
10960 "SUB ESP,8\n\t"
10961 "FISTp [ESP + #0]\n\t"
10962 "FLDCW std/24-bit mode\n\t"
10963 "POP EAX\n\t"
10964 "POP EDX\n\t"
10965 "CMP EDX,0x80000000\n\t"
10966 "JNE,s fast\n\t"
10967 "TEST EAX,EAX\n\t"
10968 "JNE,s fast\n\t"
10969 "FLD $src\n\t"
10970 "CALL d2l_wrapper\n"
10971 "fast:" %}
10972 // DPR2L_encoding works for FPR2L
10973 ins_encode( Push_Reg_FPR(src), DPR2L_encoding(src) );
10974 ins_pipe( pipe_slow );
10975 %}
10976
10977 // XMM lacks a float/double->long conversion, so use the old FPU stack.
10978 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{
10979 predicate (UseSSE>=1);
10980 match(Set dst (ConvF2L src));
10981 effect( KILL cr );
10982 format %{ "SUB ESP,8\t# Convert float to long\n\t"
10983 "MOVSS [ESP],$src\n\t"
10984 "FLD_S [ESP]\n\t"
10985 "FLDCW trunc mode\n\t"
10986 "FISTp [ESP + #0]\n\t"
10987 "FLDCW std/24-bit mode\n\t"
10988 "POP EAX\n\t"
10989 "POP EDX\n\t"
10990 "CMP EDX,0x80000000\n\t"
10991 "JNE,s fast\n\t"
10992 "TEST EAX,EAX\n\t"
10993 "JNE,s fast\n\t"
10994 "SUB ESP,4\t# Convert float to long\n\t"
10995 "MOVSS [ESP],$src\n\t"
10996 "FLD_S [ESP]\n\t"
10997 "ADD ESP,4\n\t"
10998 "CALL d2l_wrapper\n"
10999 "fast:" %}
11000 ins_encode %{
11001 Label fast;
11002 __ subptr(rsp, 8);
11003 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11004 __ fld_s(Address(rsp, 0));
11005 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
11006 __ fistp_d(Address(rsp, 0));
11007 // Restore the rounding mode, mask the exception
11008 if (Compile::current()->in_24_bit_fp_mode()) {
11009 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
11010 } else {
11011 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
11012 }
11013 // Load the converted long, adjust CPU stack
11014 __ pop(rax);
11015 __ pop(rdx);
11016 __ cmpl(rdx, 0x80000000);
11017 __ jccb(Assembler::notEqual, fast);
11018 __ testl(rax, rax);
11019 __ jccb(Assembler::notEqual, fast);
11020 __ subptr(rsp, 4);
11021 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11022 __ fld_s(Address(rsp, 0));
11023 __ addptr(rsp, 4);
11024 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
11025 __ bind(fast);
11026 %}
11027 ins_pipe( pipe_slow );
11028 %}
11029
11030 instruct convI2DPR_reg(regDPR dst, stackSlotI src) %{
11031 predicate( UseSSE<=1 );
11032 match(Set dst (ConvI2D src));
11033 format %{ "FILD $src\n\t"
11034 "FSTP $dst" %}
11035 opcode(0xDB, 0x0); /* DB /0 */
11036 ins_encode(Push_Mem_I(src), Pop_Reg_DPR(dst));
11037 ins_pipe( fpu_reg_mem );
11038 %}
11039
11040 instruct convI2D_reg(regD dst, rRegI src) %{
11041 predicate( UseSSE>=2 && !UseXmmI2D );
11042 match(Set dst (ConvI2D src));
11043 format %{ "CVTSI2SD $dst,$src" %}
11044 ins_encode %{
11045 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
11046 %}
11047 ins_pipe( pipe_slow );
11048 %}
11049
11050 instruct convI2D_mem(regD dst, memory mem) %{
11051 predicate( UseSSE>=2 );
11052 match(Set dst (ConvI2D (LoadI mem)));
11053 format %{ "CVTSI2SD $dst,$mem" %}
11054 ins_encode %{
11055 __ cvtsi2sdl ($dst$$XMMRegister, $mem$$Address);
11056 %}
11057 ins_pipe( pipe_slow );
11058 %}
11059
11060 instruct convXI2D_reg(regD dst, rRegI src)
11061 %{
11062 predicate( UseSSE>=2 && UseXmmI2D );
11063 match(Set dst (ConvI2D src));
11064
11065 format %{ "MOVD $dst,$src\n\t"
11066 "CVTDQ2PD $dst,$dst\t# i2d" %}
11067 ins_encode %{
11068 __ movdl($dst$$XMMRegister, $src$$Register);
11069 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
11070 %}
11071 ins_pipe(pipe_slow); // XXX
11072 %}
11073
11074 instruct convI2DPR_mem(regDPR dst, memory mem) %{
11075 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr());
11076 match(Set dst (ConvI2D (LoadI mem)));
11077 format %{ "FILD $mem\n\t"
11078 "FSTP $dst" %}
11079 opcode(0xDB); /* DB /0 */
11080 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11081 Pop_Reg_DPR(dst));
11082 ins_pipe( fpu_reg_mem );
11083 %}
11084
11085 // Convert a byte to a float; no rounding step needed.
11086 instruct conv24I2FPR_reg(regFPR dst, stackSlotI src) %{
11087 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 );
11088 match(Set dst (ConvI2F src));
11089 format %{ "FILD $src\n\t"
11090 "FSTP $dst" %}
11091
11092 opcode(0xDB, 0x0); /* DB /0 */
11093 ins_encode(Push_Mem_I(src), Pop_Reg_FPR(dst));
11094 ins_pipe( fpu_reg_mem );
11095 %}
11096
11097 // In 24-bit mode, force exponent rounding by storing back out
11098 instruct convI2FPR_SSF(stackSlotF dst, stackSlotI src) %{
11099 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11100 match(Set dst (ConvI2F src));
11101 ins_cost(200);
11102 format %{ "FILD $src\n\t"
11103 "FSTP_S $dst" %}
11104 opcode(0xDB, 0x0); /* DB /0 */
11105 ins_encode( Push_Mem_I(src),
11106 Pop_Mem_FPR(dst));
11107 ins_pipe( fpu_mem_mem );
11108 %}
11109
11110 // In 24-bit mode, force exponent rounding by storing back out
11111 instruct convI2FPR_SSF_mem(stackSlotF dst, memory mem) %{
11112 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11113 match(Set dst (ConvI2F (LoadI mem)));
11114 ins_cost(200);
11115 format %{ "FILD $mem\n\t"
11116 "FSTP_S $dst" %}
11117 opcode(0xDB); /* DB /0 */
11118 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11119 Pop_Mem_FPR(dst));
11120 ins_pipe( fpu_mem_mem );
11121 %}
11122
11123 // This instruction does not round to 24-bits
11124 instruct convI2FPR_reg(regFPR dst, stackSlotI src) %{
11125 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11126 match(Set dst (ConvI2F src));
11127 format %{ "FILD $src\n\t"
11128 "FSTP $dst" %}
11129 opcode(0xDB, 0x0); /* DB /0 */
11130 ins_encode( Push_Mem_I(src),
11131 Pop_Reg_FPR(dst));
11132 ins_pipe( fpu_reg_mem );
11133 %}
11134
11135 // This instruction does not round to 24-bits
11136 instruct convI2FPR_mem(regFPR dst, memory mem) %{
11137 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11138 match(Set dst (ConvI2F (LoadI mem)));
11139 format %{ "FILD $mem\n\t"
11140 "FSTP $dst" %}
11141 opcode(0xDB); /* DB /0 */
11142 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11143 Pop_Reg_FPR(dst));
11144 ins_pipe( fpu_reg_mem );
11145 %}
11146
11147 // Convert an int to a float in xmm; no rounding step needed.
11148 instruct convI2F_reg(regF dst, rRegI src) %{
11149 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F );
11150 match(Set dst (ConvI2F src));
11151 format %{ "CVTSI2SS $dst, $src" %}
11152 ins_encode %{
11153 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
11154 %}
11155 ins_pipe( pipe_slow );
11156 %}
11157
11158 instruct convXI2F_reg(regF dst, rRegI src)
11159 %{
11160 predicate( UseSSE>=2 && UseXmmI2F );
11161 match(Set dst (ConvI2F src));
11162
11163 format %{ "MOVD $dst,$src\n\t"
11164 "CVTDQ2PS $dst,$dst\t# i2f" %}
11165 ins_encode %{
11166 __ movdl($dst$$XMMRegister, $src$$Register);
11167 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
11168 %}
11169 ins_pipe(pipe_slow); // XXX
11170 %}
11171
11172 instruct convI2L_reg( eRegL dst, rRegI src, eFlagsReg cr) %{
11173 match(Set dst (ConvI2L src));
11174 effect(KILL cr);
11175 ins_cost(375);
11176 format %{ "MOV $dst.lo,$src\n\t"
11177 "MOV $dst.hi,$src\n\t"
11178 "SAR $dst.hi,31" %}
11179 ins_encode(convert_int_long(dst,src));
11180 ins_pipe( ialu_reg_reg_long );
11181 %}
11182
11183 // Zero-extend convert int to long
11184 instruct convI2L_reg_zex(eRegL dst, rRegI src, immL_32bits mask, eFlagsReg flags ) %{
11185 match(Set dst (AndL (ConvI2L src) mask) );
11186 effect( KILL flags );
11187 ins_cost(250);
11188 format %{ "MOV $dst.lo,$src\n\t"
11189 "XOR $dst.hi,$dst.hi" %}
11190 opcode(0x33); // XOR
11191 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11192 ins_pipe( ialu_reg_reg_long );
11193 %}
11194
11195 // Zero-extend long
11196 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{
11197 match(Set dst (AndL src mask) );
11198 effect( KILL flags );
11199 ins_cost(250);
11200 format %{ "MOV $dst.lo,$src.lo\n\t"
11201 "XOR $dst.hi,$dst.hi\n\t" %}
11202 opcode(0x33); // XOR
11203 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11204 ins_pipe( ialu_reg_reg_long );
11205 %}
11206
11207 instruct convL2DPR_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{
11208 predicate (UseSSE<=1);
11209 match(Set dst (ConvL2D src));
11210 effect( KILL cr );
11211 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11212 "PUSH $src.lo\n\t"
11213 "FILD ST,[ESP + #0]\n\t"
11214 "ADD ESP,8\n\t"
11215 "FSTP_D $dst\t# D-round" %}
11216 opcode(0xDF, 0x5); /* DF /5 */
11217 ins_encode(convert_long_double(src), Pop_Mem_DPR(dst));
11218 ins_pipe( pipe_slow );
11219 %}
11220
11221 instruct convL2D_reg( regD dst, eRegL src, eFlagsReg cr) %{
11222 predicate (UseSSE>=2);
11223 match(Set dst (ConvL2D src));
11224 effect( KILL cr );
11225 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11226 "PUSH $src.lo\n\t"
11227 "FILD_D [ESP]\n\t"
11228 "FSTP_D [ESP]\n\t"
11229 "MOVSD $dst,[ESP]\n\t"
11230 "ADD ESP,8" %}
11231 opcode(0xDF, 0x5); /* DF /5 */
11232 ins_encode(convert_long_double2(src), Push_ResultD(dst));
11233 ins_pipe( pipe_slow );
11234 %}
11235
11236 instruct convL2F_reg( regF dst, eRegL src, eFlagsReg cr) %{
11237 predicate (UseSSE>=1);
11238 match(Set dst (ConvL2F src));
11239 effect( KILL cr );
11240 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11241 "PUSH $src.lo\n\t"
11242 "FILD_D [ESP]\n\t"
11243 "FSTP_S [ESP]\n\t"
11244 "MOVSS $dst,[ESP]\n\t"
11245 "ADD ESP,8" %}
11246 opcode(0xDF, 0x5); /* DF /5 */
11247 ins_encode(convert_long_double2(src), Push_ResultF(dst,0x8));
11248 ins_pipe( pipe_slow );
11249 %}
11250
11251 instruct convL2FPR_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{
11252 match(Set dst (ConvL2F src));
11253 effect( KILL cr );
11254 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11255 "PUSH $src.lo\n\t"
11256 "FILD ST,[ESP + #0]\n\t"
11257 "ADD ESP,8\n\t"
11258 "FSTP_S $dst\t# F-round" %}
11259 opcode(0xDF, 0x5); /* DF /5 */
11260 ins_encode(convert_long_double(src), Pop_Mem_FPR(dst));
11261 ins_pipe( pipe_slow );
11262 %}
11263
11264 instruct convL2I_reg( rRegI dst, eRegL src ) %{
11265 match(Set dst (ConvL2I src));
11266 effect( DEF dst, USE src );
11267 format %{ "MOV $dst,$src.lo" %}
11268 ins_encode(enc_CopyL_Lo(dst,src));
11269 ins_pipe( ialu_reg_reg );
11270 %}
11271
11272
11273 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
11274 match(Set dst (MoveF2I src));
11275 effect( DEF dst, USE src );
11276 ins_cost(100);
11277 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %}
11278 ins_encode %{
11279 __ movl($dst$$Register, Address(rsp, $src$$disp));
11280 %}
11281 ins_pipe( ialu_reg_mem );
11282 %}
11283
11284 instruct MoveFPR2I_reg_stack(stackSlotI dst, regFPR src) %{
11285 predicate(UseSSE==0);
11286 match(Set dst (MoveF2I src));
11287 effect( DEF dst, USE src );
11288
11289 ins_cost(125);
11290 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %}
11291 ins_encode( Pop_Mem_Reg_FPR(dst, src) );
11292 ins_pipe( fpu_mem_reg );
11293 %}
11294
11295 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regF src) %{
11296 predicate(UseSSE>=1);
11297 match(Set dst (MoveF2I src));
11298 effect( DEF dst, USE src );
11299
11300 ins_cost(95);
11301 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %}
11302 ins_encode %{
11303 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
11304 %}
11305 ins_pipe( pipe_slow );
11306 %}
11307
11308 instruct MoveF2I_reg_reg_sse(rRegI dst, regF src) %{
11309 predicate(UseSSE>=2);
11310 match(Set dst (MoveF2I src));
11311 effect( DEF dst, USE src );
11312 ins_cost(85);
11313 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %}
11314 ins_encode %{
11315 __ movdl($dst$$Register, $src$$XMMRegister);
11316 %}
11317 ins_pipe( pipe_slow );
11318 %}
11319
11320 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
11321 match(Set dst (MoveI2F src));
11322 effect( DEF dst, USE src );
11323
11324 ins_cost(100);
11325 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %}
11326 ins_encode %{
11327 __ movl(Address(rsp, $dst$$disp), $src$$Register);
11328 %}
11329 ins_pipe( ialu_mem_reg );
11330 %}
11331
11332
11333 instruct MoveI2FPR_stack_reg(regFPR dst, stackSlotI src) %{
11334 predicate(UseSSE==0);
11335 match(Set dst (MoveI2F src));
11336 effect(DEF dst, USE src);
11337
11338 ins_cost(125);
11339 format %{ "FLD_S $src\n\t"
11340 "FSTP $dst\t# MoveI2F_stack_reg" %}
11341 opcode(0xD9); /* D9 /0, FLD m32real */
11342 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11343 Pop_Reg_FPR(dst) );
11344 ins_pipe( fpu_reg_mem );
11345 %}
11346
11347 instruct MoveI2F_stack_reg_sse(regF dst, stackSlotI src) %{
11348 predicate(UseSSE>=1);
11349 match(Set dst (MoveI2F src));
11350 effect( DEF dst, USE src );
11351
11352 ins_cost(95);
11353 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %}
11354 ins_encode %{
11355 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
11356 %}
11357 ins_pipe( pipe_slow );
11358 %}
11359
11360 instruct MoveI2F_reg_reg_sse(regF dst, rRegI src) %{
11361 predicate(UseSSE>=2);
11362 match(Set dst (MoveI2F src));
11363 effect( DEF dst, USE src );
11364
11365 ins_cost(85);
11366 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %}
11367 ins_encode %{
11368 __ movdl($dst$$XMMRegister, $src$$Register);
11369 %}
11370 ins_pipe( pipe_slow );
11371 %}
11372
11373 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{
11374 match(Set dst (MoveD2L src));
11375 effect(DEF dst, USE src);
11376
11377 ins_cost(250);
11378 format %{ "MOV $dst.lo,$src\n\t"
11379 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %}
11380 opcode(0x8B, 0x8B);
11381 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src));
11382 ins_pipe( ialu_mem_long_reg );
11383 %}
11384
11385 instruct MoveDPR2L_reg_stack(stackSlotL dst, regDPR src) %{
11386 predicate(UseSSE<=1);
11387 match(Set dst (MoveD2L src));
11388 effect(DEF dst, USE src);
11389
11390 ins_cost(125);
11391 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %}
11392 ins_encode( Pop_Mem_Reg_DPR(dst, src) );
11393 ins_pipe( fpu_mem_reg );
11394 %}
11395
11396 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regD src) %{
11397 predicate(UseSSE>=2);
11398 match(Set dst (MoveD2L src));
11399 effect(DEF dst, USE src);
11400 ins_cost(95);
11401 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %}
11402 ins_encode %{
11403 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
11404 %}
11405 ins_pipe( pipe_slow );
11406 %}
11407
11408 instruct MoveD2L_reg_reg_sse(eRegL dst, regD src, regD tmp) %{
11409 predicate(UseSSE>=2);
11410 match(Set dst (MoveD2L src));
11411 effect(DEF dst, USE src, TEMP tmp);
11412 ins_cost(85);
11413 format %{ "MOVD $dst.lo,$src\n\t"
11414 "PSHUFLW $tmp,$src,0x4E\n\t"
11415 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %}
11416 ins_encode %{
11417 __ movdl($dst$$Register, $src$$XMMRegister);
11418 __ pshuflw($tmp$$XMMRegister, $src$$XMMRegister, 0x4e);
11419 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
11420 %}
11421 ins_pipe( pipe_slow );
11422 %}
11423
11424 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{
11425 match(Set dst (MoveL2D src));
11426 effect(DEF dst, USE src);
11427
11428 ins_cost(200);
11429 format %{ "MOV $dst,$src.lo\n\t"
11430 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %}
11431 opcode(0x89, 0x89);
11432 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
11433 ins_pipe( ialu_mem_long_reg );
11434 %}
11435
11436
11437 instruct MoveL2DPR_stack_reg(regDPR dst, stackSlotL src) %{
11438 predicate(UseSSE<=1);
11439 match(Set dst (MoveL2D src));
11440 effect(DEF dst, USE src);
11441 ins_cost(125);
11442
11443 format %{ "FLD_D $src\n\t"
11444 "FSTP $dst\t# MoveL2D_stack_reg" %}
11445 opcode(0xDD); /* DD /0, FLD m64real */
11446 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11447 Pop_Reg_DPR(dst) );
11448 ins_pipe( fpu_reg_mem );
11449 %}
11450
11451
11452 instruct MoveL2D_stack_reg_sse(regD dst, stackSlotL src) %{
11453 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
11454 match(Set dst (MoveL2D src));
11455 effect(DEF dst, USE src);
11456
11457 ins_cost(95);
11458 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11459 ins_encode %{
11460 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11461 %}
11462 ins_pipe( pipe_slow );
11463 %}
11464
11465 instruct MoveL2D_stack_reg_sse_partial(regD dst, stackSlotL src) %{
11466 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
11467 match(Set dst (MoveL2D src));
11468 effect(DEF dst, USE src);
11469
11470 ins_cost(95);
11471 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11472 ins_encode %{
11473 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11474 %}
11475 ins_pipe( pipe_slow );
11476 %}
11477
11478 instruct MoveL2D_reg_reg_sse(regD dst, eRegL src, regD tmp) %{
11479 predicate(UseSSE>=2);
11480 match(Set dst (MoveL2D src));
11481 effect(TEMP dst, USE src, TEMP tmp);
11482 ins_cost(85);
11483 format %{ "MOVD $dst,$src.lo\n\t"
11484 "MOVD $tmp,$src.hi\n\t"
11485 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %}
11486 ins_encode %{
11487 __ movdl($dst$$XMMRegister, $src$$Register);
11488 __ movdl($tmp$$XMMRegister, HIGH_FROM_LOW($src$$Register));
11489 __ punpckldq($dst$$XMMRegister, $tmp$$XMMRegister);
11490 %}
11491 ins_pipe( pipe_slow );
11492 %}
11493
11494
11495 // =======================================================================
11496 // fast clearing of an array
11497 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
11498 predicate(!UseFastStosb);
11499 match(Set dummy (ClearArray cnt base));
11500 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
11501 format %{ "XOR EAX,EAX\t# ClearArray:\n\t"
11502 "SHL ECX,1\t# Convert doublewords to words\n\t"
11503 "REP STOS\t# store EAX into [EDI++] while ECX--" %}
11504 ins_encode %{
11505 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register);
11506 %}
11507 ins_pipe( pipe_slow );
11508 %}
11509
11510 instruct rep_fast_stosb(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
11511 predicate(UseFastStosb);
11512 match(Set dummy (ClearArray cnt base));
11513 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
11514 format %{ "XOR EAX,EAX\t# ClearArray:\n\t"
11515 "SHL ECX,3\t# Convert doublewords to bytes\n\t"
11516 "REP STOSB\t# store EAX into [EDI++] while ECX--" %}
11517 ins_encode %{
11518 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register);
11519 %}
11520 ins_pipe( pipe_slow );
11521 %}
11522
11523 instruct string_compare(eDIRegP str1, eCXRegI cnt1, eSIRegP str2, eDXRegI cnt2,
11524 eAXRegI result, regD tmp1, eFlagsReg cr) %{
11525 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11526 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11527
11528 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11529 ins_encode %{
11530 __ string_compare($str1$$Register, $str2$$Register,
11531 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11532 $tmp1$$XMMRegister);
11533 %}
11534 ins_pipe( pipe_slow );
11535 %}
11536
11537 // fast string equals
11538 instruct string_equals(eDIRegP str1, eSIRegP str2, eCXRegI cnt, eAXRegI result,
11539 regD tmp1, regD tmp2, eBXRegI tmp3, eFlagsReg cr) %{
11540 match(Set result (StrEquals (Binary str1 str2) cnt));
11541 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
11542
11543 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
11544 ins_encode %{
11545 __ char_arrays_equals(false, $str1$$Register, $str2$$Register,
11546 $cnt$$Register, $result$$Register, $tmp3$$Register,
11547 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11548 %}
11549 ins_pipe( pipe_slow );
11550 %}
11551
11552 // fast search of substring with known size.
11553 instruct string_indexof_con(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, immI int_cnt2,
11554 eBXRegI result, regD vec, eAXRegI cnt2, eCXRegI tmp, eFlagsReg cr) %{
11555 predicate(UseSSE42Intrinsics);
11556 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11557 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11558
11559 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
11560 ins_encode %{
11561 int icnt2 = (int)$int_cnt2$$constant;
11562 if (icnt2 >= 8) {
11563 // IndexOf for constant substrings with size >= 8 elements
11564 // which don't need to be loaded through stack.
11565 __ string_indexofC8($str1$$Register, $str2$$Register,
11566 $cnt1$$Register, $cnt2$$Register,
11567 icnt2, $result$$Register,
11568 $vec$$XMMRegister, $tmp$$Register);
11569 } else {
11570 // Small strings are loaded through stack if they cross page boundary.
11571 __ string_indexof($str1$$Register, $str2$$Register,
11572 $cnt1$$Register, $cnt2$$Register,
11573 icnt2, $result$$Register,
11574 $vec$$XMMRegister, $tmp$$Register);
11575 }
11576 %}
11577 ins_pipe( pipe_slow );
11578 %}
11579
11580 instruct string_indexof(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, eAXRegI cnt2,
11581 eBXRegI result, regD vec, eCXRegI tmp, eFlagsReg cr) %{
11582 predicate(UseSSE42Intrinsics);
11583 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11584 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11585
11586 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
11587 ins_encode %{
11588 __ string_indexof($str1$$Register, $str2$$Register,
11589 $cnt1$$Register, $cnt2$$Register,
11590 (-1), $result$$Register,
11591 $vec$$XMMRegister, $tmp$$Register);
11592 %}
11593 ins_pipe( pipe_slow );
11594 %}
11595
11596 // fast array equals
11597 instruct array_equals(eDIRegP ary1, eSIRegP ary2, eAXRegI result,
11598 regD tmp1, regD tmp2, eCXRegI tmp3, eBXRegI tmp4, eFlagsReg cr)
11599 %{
11600 match(Set result (AryEq ary1 ary2));
11601 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11602 //ins_cost(300);
11603
11604 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11605 ins_encode %{
11606 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register,
11607 $tmp3$$Register, $result$$Register, $tmp4$$Register,
11608 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11609 %}
11610 ins_pipe( pipe_slow );
11611 %}
11612
11613 // encode char[] to byte[] in ISO_8859_1
11614 instruct encode_iso_array(eSIRegP src, eDIRegP dst, eDXRegI len,
11615 regD tmp1, regD tmp2, regD tmp3, regD tmp4,
11616 eCXRegI tmp5, eAXRegI result, eFlagsReg cr) %{
11617 match(Set result (EncodeISOArray src (Binary dst len)));
11618 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
11619
11620 format %{ "Encode array $src,$dst,$len -> $result // KILL ECX, EDX, $tmp1, $tmp2, $tmp3, $tmp4, ESI, EDI " %}
11621 ins_encode %{
11622 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
11623 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11624 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
11625 %}
11626 ins_pipe( pipe_slow );
11627 %}
11628
11629
11630 //----------Control Flow Instructions------------------------------------------
11631 // Signed compare Instructions
11632 instruct compI_eReg(eFlagsReg cr, rRegI op1, rRegI op2) %{
11633 match(Set cr (CmpI op1 op2));
11634 effect( DEF cr, USE op1, USE op2 );
11635 format %{ "CMP $op1,$op2" %}
11636 opcode(0x3B); /* Opcode 3B /r */
11637 ins_encode( OpcP, RegReg( op1, op2) );
11638 ins_pipe( ialu_cr_reg_reg );
11639 %}
11640
11641 instruct compI_eReg_imm(eFlagsReg cr, rRegI op1, immI op2) %{
11642 match(Set cr (CmpI op1 op2));
11643 effect( DEF cr, USE op1 );
11644 format %{ "CMP $op1,$op2" %}
11645 opcode(0x81,0x07); /* Opcode 81 /7 */
11646 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */
11647 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11648 ins_pipe( ialu_cr_reg_imm );
11649 %}
11650
11651 // Cisc-spilled version of cmpI_eReg
11652 instruct compI_eReg_mem(eFlagsReg cr, rRegI op1, memory op2) %{
11653 match(Set cr (CmpI op1 (LoadI op2)));
11654
11655 format %{ "CMP $op1,$op2" %}
11656 ins_cost(500);
11657 opcode(0x3B); /* Opcode 3B /r */
11658 ins_encode( OpcP, RegMem( op1, op2) );
11659 ins_pipe( ialu_cr_reg_mem );
11660 %}
11661
11662 instruct testI_reg( eFlagsReg cr, rRegI src, immI0 zero ) %{
11663 match(Set cr (CmpI src zero));
11664 effect( DEF cr, USE src );
11665
11666 format %{ "TEST $src,$src" %}
11667 opcode(0x85);
11668 ins_encode( OpcP, RegReg( src, src ) );
11669 ins_pipe( ialu_cr_reg_imm );
11670 %}
11671
11672 instruct testI_reg_imm( eFlagsReg cr, rRegI src, immI con, immI0 zero ) %{
11673 match(Set cr (CmpI (AndI src con) zero));
11674
11675 format %{ "TEST $src,$con" %}
11676 opcode(0xF7,0x00);
11677 ins_encode( OpcP, RegOpc(src), Con32(con) );
11678 ins_pipe( ialu_cr_reg_imm );
11679 %}
11680
11681 instruct testI_reg_mem( eFlagsReg cr, rRegI src, memory mem, immI0 zero ) %{
11682 match(Set cr (CmpI (AndI src mem) zero));
11683
11684 format %{ "TEST $src,$mem" %}
11685 opcode(0x85);
11686 ins_encode( OpcP, RegMem( src, mem ) );
11687 ins_pipe( ialu_cr_reg_mem );
11688 %}
11689
11690 // Unsigned compare Instructions; really, same as signed except they
11691 // produce an eFlagsRegU instead of eFlagsReg.
11692 instruct compU_eReg(eFlagsRegU cr, rRegI op1, rRegI op2) %{
11693 match(Set cr (CmpU op1 op2));
11694
11695 format %{ "CMPu $op1,$op2" %}
11696 opcode(0x3B); /* Opcode 3B /r */
11697 ins_encode( OpcP, RegReg( op1, op2) );
11698 ins_pipe( ialu_cr_reg_reg );
11699 %}
11700
11701 instruct compU_eReg_imm(eFlagsRegU cr, rRegI op1, immI op2) %{
11702 match(Set cr (CmpU op1 op2));
11703
11704 format %{ "CMPu $op1,$op2" %}
11705 opcode(0x81,0x07); /* Opcode 81 /7 */
11706 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11707 ins_pipe( ialu_cr_reg_imm );
11708 %}
11709
11710 // // Cisc-spilled version of cmpU_eReg
11711 instruct compU_eReg_mem(eFlagsRegU cr, rRegI op1, memory op2) %{
11712 match(Set cr (CmpU op1 (LoadI op2)));
11713
11714 format %{ "CMPu $op1,$op2" %}
11715 ins_cost(500);
11716 opcode(0x3B); /* Opcode 3B /r */
11717 ins_encode( OpcP, RegMem( op1, op2) );
11718 ins_pipe( ialu_cr_reg_mem );
11719 %}
11720
11721 // // Cisc-spilled version of cmpU_eReg
11722 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, rRegI op2) %{
11723 // match(Set cr (CmpU (LoadI op1) op2));
11724 //
11725 // format %{ "CMPu $op1,$op2" %}
11726 // ins_cost(500);
11727 // opcode(0x39); /* Opcode 39 /r */
11728 // ins_encode( OpcP, RegMem( op1, op2) );
11729 //%}
11730
11731 instruct testU_reg( eFlagsRegU cr, rRegI src, immI0 zero ) %{
11732 match(Set cr (CmpU src zero));
11733
11734 format %{ "TESTu $src,$src" %}
11735 opcode(0x85);
11736 ins_encode( OpcP, RegReg( src, src ) );
11737 ins_pipe( ialu_cr_reg_imm );
11738 %}
11739
11740 // Unsigned pointer compare Instructions
11741 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{
11742 match(Set cr (CmpP op1 op2));
11743
11744 format %{ "CMPu $op1,$op2" %}
11745 opcode(0x3B); /* Opcode 3B /r */
11746 ins_encode( OpcP, RegReg( op1, op2) );
11747 ins_pipe( ialu_cr_reg_reg );
11748 %}
11749
11750 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{
11751 match(Set cr (CmpP op1 op2));
11752
11753 format %{ "CMPu $op1,$op2" %}
11754 opcode(0x81,0x07); /* Opcode 81 /7 */
11755 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11756 ins_pipe( ialu_cr_reg_imm );
11757 %}
11758
11759 // // Cisc-spilled version of cmpP_eReg
11760 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{
11761 match(Set cr (CmpP op1 (LoadP op2)));
11762
11763 format %{ "CMPu $op1,$op2" %}
11764 ins_cost(500);
11765 opcode(0x3B); /* Opcode 3B /r */
11766 ins_encode( OpcP, RegMem( op1, op2) );
11767 ins_pipe( ialu_cr_reg_mem );
11768 %}
11769
11770 // // Cisc-spilled version of cmpP_eReg
11771 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{
11772 // match(Set cr (CmpP (LoadP op1) op2));
11773 //
11774 // format %{ "CMPu $op1,$op2" %}
11775 // ins_cost(500);
11776 // opcode(0x39); /* Opcode 39 /r */
11777 // ins_encode( OpcP, RegMem( op1, op2) );
11778 //%}
11779
11780 // Compare raw pointer (used in out-of-heap check).
11781 // Only works because non-oop pointers must be raw pointers
11782 // and raw pointers have no anti-dependencies.
11783 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{
11784 predicate( n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none );
11785 match(Set cr (CmpP op1 (LoadP op2)));
11786
11787 format %{ "CMPu $op1,$op2" %}
11788 opcode(0x3B); /* Opcode 3B /r */
11789 ins_encode( OpcP, RegMem( op1, op2) );
11790 ins_pipe( ialu_cr_reg_mem );
11791 %}
11792
11793 //
11794 // This will generate a signed flags result. This should be ok
11795 // since any compare to a zero should be eq/neq.
11796 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{
11797 match(Set cr (CmpP src zero));
11798
11799 format %{ "TEST $src,$src" %}
11800 opcode(0x85);
11801 ins_encode( OpcP, RegReg( src, src ) );
11802 ins_pipe( ialu_cr_reg_imm );
11803 %}
11804
11805 // Cisc-spilled version of testP_reg
11806 // This will generate a signed flags result. This should be ok
11807 // since any compare to a zero should be eq/neq.
11808 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{
11809 match(Set cr (CmpP (LoadP op) zero));
11810
11811 format %{ "TEST $op,0xFFFFFFFF" %}
11812 ins_cost(500);
11813 opcode(0xF7); /* Opcode F7 /0 */
11814 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) );
11815 ins_pipe( ialu_cr_reg_imm );
11816 %}
11817
11818 // Yanked all unsigned pointer compare operations.
11819 // Pointer compares are done with CmpP which is already unsigned.
11820
11821 //----------Max and Min--------------------------------------------------------
11822 // Min Instructions
11823 ////
11824 // *** Min and Max using the conditional move are slower than the
11825 // *** branch version on a Pentium III.
11826 // // Conditional move for min
11827 //instruct cmovI_reg_lt( rRegI op2, rRegI op1, eFlagsReg cr ) %{
11828 // effect( USE_DEF op2, USE op1, USE cr );
11829 // format %{ "CMOVlt $op2,$op1\t! min" %}
11830 // opcode(0x4C,0x0F);
11831 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
11832 // ins_pipe( pipe_cmov_reg );
11833 //%}
11834 //
11835 //// Min Register with Register (P6 version)
11836 //instruct minI_eReg_p6( rRegI op1, rRegI op2 ) %{
11837 // predicate(VM_Version::supports_cmov() );
11838 // match(Set op2 (MinI op1 op2));
11839 // ins_cost(200);
11840 // expand %{
11841 // eFlagsReg cr;
11842 // compI_eReg(cr,op1,op2);
11843 // cmovI_reg_lt(op2,op1,cr);
11844 // %}
11845 //%}
11846
11847 // Min Register with Register (generic version)
11848 instruct minI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{
11849 match(Set dst (MinI dst src));
11850 effect(KILL flags);
11851 ins_cost(300);
11852
11853 format %{ "MIN $dst,$src" %}
11854 opcode(0xCC);
11855 ins_encode( min_enc(dst,src) );
11856 ins_pipe( pipe_slow );
11857 %}
11858
11859 // Max Register with Register
11860 // *** Min and Max using the conditional move are slower than the
11861 // *** branch version on a Pentium III.
11862 // // Conditional move for max
11863 //instruct cmovI_reg_gt( rRegI op2, rRegI op1, eFlagsReg cr ) %{
11864 // effect( USE_DEF op2, USE op1, USE cr );
11865 // format %{ "CMOVgt $op2,$op1\t! max" %}
11866 // opcode(0x4F,0x0F);
11867 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
11868 // ins_pipe( pipe_cmov_reg );
11869 //%}
11870 //
11871 // // Max Register with Register (P6 version)
11872 //instruct maxI_eReg_p6( rRegI op1, rRegI op2 ) %{
11873 // predicate(VM_Version::supports_cmov() );
11874 // match(Set op2 (MaxI op1 op2));
11875 // ins_cost(200);
11876 // expand %{
11877 // eFlagsReg cr;
11878 // compI_eReg(cr,op1,op2);
11879 // cmovI_reg_gt(op2,op1,cr);
11880 // %}
11881 //%}
11882
11883 // Max Register with Register (generic version)
11884 instruct maxI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{
11885 match(Set dst (MaxI dst src));
11886 effect(KILL flags);
11887 ins_cost(300);
11888
11889 format %{ "MAX $dst,$src" %}
11890 opcode(0xCC);
11891 ins_encode( max_enc(dst,src) );
11892 ins_pipe( pipe_slow );
11893 %}
11894
11895 // ============================================================================
11896 // Counted Loop limit node which represents exact final iterator value.
11897 // Note: the resulting value should fit into integer range since
11898 // counted loops have limit check on overflow.
11899 instruct loopLimit_eReg(eAXRegI limit, nadxRegI init, immI stride, eDXRegI limit_hi, nadxRegI tmp, eFlagsReg flags) %{
11900 match(Set limit (LoopLimit (Binary init limit) stride));
11901 effect(TEMP limit_hi, TEMP tmp, KILL flags);
11902 ins_cost(300);
11903
11904 format %{ "loopLimit $init,$limit,$stride # $limit = $init + $stride *( $limit - $init + $stride -1)/ $stride, kills $limit_hi" %}
11905 ins_encode %{
11906 int strd = (int)$stride$$constant;
11907 assert(strd != 1 && strd != -1, "sanity");
11908 int m1 = (strd > 0) ? 1 : -1;
11909 // Convert limit to long (EAX:EDX)
11910 __ cdql();
11911 // Convert init to long (init:tmp)
11912 __ movl($tmp$$Register, $init$$Register);
11913 __ sarl($tmp$$Register, 31);
11914 // $limit - $init
11915 __ subl($limit$$Register, $init$$Register);
11916 __ sbbl($limit_hi$$Register, $tmp$$Register);
11917 // + ($stride - 1)
11918 if (strd > 0) {
11919 __ addl($limit$$Register, (strd - 1));
11920 __ adcl($limit_hi$$Register, 0);
11921 __ movl($tmp$$Register, strd);
11922 } else {
11923 __ addl($limit$$Register, (strd + 1));
11924 __ adcl($limit_hi$$Register, -1);
11925 __ lneg($limit_hi$$Register, $limit$$Register);
11926 __ movl($tmp$$Register, -strd);
11927 }
11928 // signed devision: (EAX:EDX) / pos_stride
11929 __ idivl($tmp$$Register);
11930 if (strd < 0) {
11931 // restore sign
11932 __ negl($tmp$$Register);
11933 }
11934 // (EAX) * stride
11935 __ mull($tmp$$Register);
11936 // + init (ignore upper bits)
11937 __ addl($limit$$Register, $init$$Register);
11938 %}
11939 ins_pipe( pipe_slow );
11940 %}
11941
11942 // ============================================================================
11943 // Branch Instructions
11944 // Jump Table
11945 instruct jumpXtnd(rRegI switch_val) %{
11946 match(Jump switch_val);
11947 ins_cost(350);
11948 format %{ "JMP [$constantaddress](,$switch_val,1)\n\t" %}
11949 ins_encode %{
11950 // Jump to Address(table_base + switch_reg)
11951 Address index(noreg, $switch_val$$Register, Address::times_1);
11952 __ jump(ArrayAddress($constantaddress, index));
11953 %}
11954 ins_pipe(pipe_jmp);
11955 %}
11956
11957 // Jump Direct - Label defines a relative address from JMP+1
11958 instruct jmpDir(label labl) %{
11959 match(Goto);
11960 effect(USE labl);
11961
11962 ins_cost(300);
11963 format %{ "JMP $labl" %}
11964 size(5);
11965 ins_encode %{
11966 Label* L = $labl$$label;
11967 __ jmp(*L, false); // Always long jump
11968 %}
11969 ins_pipe( pipe_jmp );
11970 %}
11971
11972 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11973 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{
11974 match(If cop cr);
11975 effect(USE labl);
11976
11977 ins_cost(300);
11978 format %{ "J$cop $labl" %}
11979 size(6);
11980 ins_encode %{
11981 Label* L = $labl$$label;
11982 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11983 %}
11984 ins_pipe( pipe_jcc );
11985 %}
11986
11987 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11988 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{
11989 match(CountedLoopEnd cop cr);
11990 effect(USE labl);
11991
11992 ins_cost(300);
11993 format %{ "J$cop $labl\t# Loop end" %}
11994 size(6);
11995 ins_encode %{
11996 Label* L = $labl$$label;
11997 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11998 %}
11999 ins_pipe( pipe_jcc );
12000 %}
12001
12002 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12003 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12004 match(CountedLoopEnd cop cmp);
12005 effect(USE labl);
12006
12007 ins_cost(300);
12008 format %{ "J$cop,u $labl\t# Loop end" %}
12009 size(6);
12010 ins_encode %{
12011 Label* L = $labl$$label;
12012 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12013 %}
12014 ins_pipe( pipe_jcc );
12015 %}
12016
12017 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12018 match(CountedLoopEnd cop cmp);
12019 effect(USE labl);
12020
12021 ins_cost(200);
12022 format %{ "J$cop,u $labl\t# Loop end" %}
12023 size(6);
12024 ins_encode %{
12025 Label* L = $labl$$label;
12026 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12027 %}
12028 ins_pipe( pipe_jcc );
12029 %}
12030
12031 // Jump Direct Conditional - using unsigned comparison
12032 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12033 match(If cop cmp);
12034 effect(USE labl);
12035
12036 ins_cost(300);
12037 format %{ "J$cop,u $labl" %}
12038 size(6);
12039 ins_encode %{
12040 Label* L = $labl$$label;
12041 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12042 %}
12043 ins_pipe(pipe_jcc);
12044 %}
12045
12046 instruct jmpConUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12047 match(If cop cmp);
12048 effect(USE labl);
12049
12050 ins_cost(200);
12051 format %{ "J$cop,u $labl" %}
12052 size(6);
12053 ins_encode %{
12054 Label* L = $labl$$label;
12055 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12056 %}
12057 ins_pipe(pipe_jcc);
12058 %}
12059
12060 instruct jmpConUCF2(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12061 match(If cop cmp);
12062 effect(USE labl);
12063
12064 ins_cost(200);
12065 format %{ $$template
12066 if ($cop$$cmpcode == Assembler::notEqual) {
12067 $$emit$$"JP,u $labl\n\t"
12068 $$emit$$"J$cop,u $labl"
12069 } else {
12070 $$emit$$"JP,u done\n\t"
12071 $$emit$$"J$cop,u $labl\n\t"
12072 $$emit$$"done:"
12073 }
12074 %}
12075 ins_encode %{
12076 Label* l = $labl$$label;
12077 if ($cop$$cmpcode == Assembler::notEqual) {
12078 __ jcc(Assembler::parity, *l, false);
12079 __ jcc(Assembler::notEqual, *l, false);
12080 } else if ($cop$$cmpcode == Assembler::equal) {
12081 Label done;
12082 __ jccb(Assembler::parity, done);
12083 __ jcc(Assembler::equal, *l, false);
12084 __ bind(done);
12085 } else {
12086 ShouldNotReachHere();
12087 }
12088 %}
12089 ins_pipe(pipe_jcc);
12090 %}
12091
12092 // ============================================================================
12093 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
12094 // array for an instance of the superklass. Set a hidden internal cache on a
12095 // hit (cache is checked with exposed code in gen_subtype_check()). Return
12096 // NZ for a miss or zero for a hit. The encoding ALSO sets flags.
12097 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{
12098 match(Set result (PartialSubtypeCheck sub super));
12099 effect( KILL rcx, KILL cr );
12100
12101 ins_cost(1100); // slightly larger than the next version
12102 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12103 "MOV ECX,[EDI+ArrayKlass::length]\t# length to scan\n\t"
12104 "ADD EDI,ArrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12105 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12106 "JNE,s miss\t\t# Missed: EDI not-zero\n\t"
12107 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t"
12108 "XOR $result,$result\t\t Hit: EDI zero\n\t"
12109 "miss:\t" %}
12110
12111 opcode(0x1); // Force a XOR of EDI
12112 ins_encode( enc_PartialSubtypeCheck() );
12113 ins_pipe( pipe_slow );
12114 %}
12115
12116 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{
12117 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
12118 effect( KILL rcx, KILL result );
12119
12120 ins_cost(1000);
12121 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12122 "MOV ECX,[EDI+ArrayKlass::length]\t# length to scan\n\t"
12123 "ADD EDI,ArrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12124 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12125 "JNE,s miss\t\t# Missed: flags NZ\n\t"
12126 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t"
12127 "miss:\t" %}
12128
12129 opcode(0x0); // No need to XOR EDI
12130 ins_encode( enc_PartialSubtypeCheck() );
12131 ins_pipe( pipe_slow );
12132 %}
12133
12134 // ============================================================================
12135 // Branch Instructions -- short offset versions
12136 //
12137 // These instructions are used to replace jumps of a long offset (the default
12138 // match) with jumps of a shorter offset. These instructions are all tagged
12139 // with the ins_short_branch attribute, which causes the ADLC to suppress the
12140 // match rules in general matching. Instead, the ADLC generates a conversion
12141 // method in the MachNode which can be used to do in-place replacement of the
12142 // long variant with the shorter variant. The compiler will determine if a
12143 // branch can be taken by the is_short_branch_offset() predicate in the machine
12144 // specific code section of the file.
12145
12146 // Jump Direct - Label defines a relative address from JMP+1
12147 instruct jmpDir_short(label labl) %{
12148 match(Goto);
12149 effect(USE labl);
12150
12151 ins_cost(300);
12152 format %{ "JMP,s $labl" %}
12153 size(2);
12154 ins_encode %{
12155 Label* L = $labl$$label;
12156 __ jmpb(*L);
12157 %}
12158 ins_pipe( pipe_jmp );
12159 ins_short_branch(1);
12160 %}
12161
12162 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12163 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{
12164 match(If cop cr);
12165 effect(USE labl);
12166
12167 ins_cost(300);
12168 format %{ "J$cop,s $labl" %}
12169 size(2);
12170 ins_encode %{
12171 Label* L = $labl$$label;
12172 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12173 %}
12174 ins_pipe( pipe_jcc );
12175 ins_short_branch(1);
12176 %}
12177
12178 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12179 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{
12180 match(CountedLoopEnd cop cr);
12181 effect(USE labl);
12182
12183 ins_cost(300);
12184 format %{ "J$cop,s $labl\t# Loop end" %}
12185 size(2);
12186 ins_encode %{
12187 Label* L = $labl$$label;
12188 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12189 %}
12190 ins_pipe( pipe_jcc );
12191 ins_short_branch(1);
12192 %}
12193
12194 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12195 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12196 match(CountedLoopEnd cop cmp);
12197 effect(USE labl);
12198
12199 ins_cost(300);
12200 format %{ "J$cop,us $labl\t# Loop end" %}
12201 size(2);
12202 ins_encode %{
12203 Label* L = $labl$$label;
12204 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12205 %}
12206 ins_pipe( pipe_jcc );
12207 ins_short_branch(1);
12208 %}
12209
12210 instruct jmpLoopEndUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12211 match(CountedLoopEnd cop cmp);
12212 effect(USE labl);
12213
12214 ins_cost(300);
12215 format %{ "J$cop,us $labl\t# Loop end" %}
12216 size(2);
12217 ins_encode %{
12218 Label* L = $labl$$label;
12219 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12220 %}
12221 ins_pipe( pipe_jcc );
12222 ins_short_branch(1);
12223 %}
12224
12225 // Jump Direct Conditional - using unsigned comparison
12226 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12227 match(If cop cmp);
12228 effect(USE labl);
12229
12230 ins_cost(300);
12231 format %{ "J$cop,us $labl" %}
12232 size(2);
12233 ins_encode %{
12234 Label* L = $labl$$label;
12235 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12236 %}
12237 ins_pipe( pipe_jcc );
12238 ins_short_branch(1);
12239 %}
12240
12241 instruct jmpConUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12242 match(If cop cmp);
12243 effect(USE labl);
12244
12245 ins_cost(300);
12246 format %{ "J$cop,us $labl" %}
12247 size(2);
12248 ins_encode %{
12249 Label* L = $labl$$label;
12250 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12251 %}
12252 ins_pipe( pipe_jcc );
12253 ins_short_branch(1);
12254 %}
12255
12256 instruct jmpConUCF2_short(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12257 match(If cop cmp);
12258 effect(USE labl);
12259
12260 ins_cost(300);
12261 format %{ $$template
12262 if ($cop$$cmpcode == Assembler::notEqual) {
12263 $$emit$$"JP,u,s $labl\n\t"
12264 $$emit$$"J$cop,u,s $labl"
12265 } else {
12266 $$emit$$"JP,u,s done\n\t"
12267 $$emit$$"J$cop,u,s $labl\n\t"
12268 $$emit$$"done:"
12269 }
12270 %}
12271 size(4);
12272 ins_encode %{
12273 Label* l = $labl$$label;
12274 if ($cop$$cmpcode == Assembler::notEqual) {
12275 __ jccb(Assembler::parity, *l);
12276 __ jccb(Assembler::notEqual, *l);
12277 } else if ($cop$$cmpcode == Assembler::equal) {
12278 Label done;
12279 __ jccb(Assembler::parity, done);
12280 __ jccb(Assembler::equal, *l);
12281 __ bind(done);
12282 } else {
12283 ShouldNotReachHere();
12284 }
12285 %}
12286 ins_pipe(pipe_jcc);
12287 ins_short_branch(1);
12288 %}
12289
12290 // ============================================================================
12291 // Long Compare
12292 //
12293 // Currently we hold longs in 2 registers. Comparing such values efficiently
12294 // is tricky. The flavor of compare used depends on whether we are testing
12295 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
12296 // The GE test is the negated LT test. The LE test can be had by commuting
12297 // the operands (yielding a GE test) and then negating; negate again for the
12298 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
12299 // NE test is negated from that.
12300
12301 // Due to a shortcoming in the ADLC, it mixes up expressions like:
12302 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
12303 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
12304 // are collapsed internally in the ADLC's dfa-gen code. The match for
12305 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
12306 // foo match ends up with the wrong leaf. One fix is to not match both
12307 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
12308 // both forms beat the trinary form of long-compare and both are very useful
12309 // on Intel which has so few registers.
12310
12311 // Manifest a CmpL result in an integer register. Very painful.
12312 // This is the test to avoid.
12313 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{
12314 match(Set dst (CmpL3 src1 src2));
12315 effect( KILL flags );
12316 ins_cost(1000);
12317 format %{ "XOR $dst,$dst\n\t"
12318 "CMP $src1.hi,$src2.hi\n\t"
12319 "JLT,s m_one\n\t"
12320 "JGT,s p_one\n\t"
12321 "CMP $src1.lo,$src2.lo\n\t"
12322 "JB,s m_one\n\t"
12323 "JEQ,s done\n"
12324 "p_one:\tINC $dst\n\t"
12325 "JMP,s done\n"
12326 "m_one:\tDEC $dst\n"
12327 "done:" %}
12328 ins_encode %{
12329 Label p_one, m_one, done;
12330 __ xorptr($dst$$Register, $dst$$Register);
12331 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register));
12332 __ jccb(Assembler::less, m_one);
12333 __ jccb(Assembler::greater, p_one);
12334 __ cmpl($src1$$Register, $src2$$Register);
12335 __ jccb(Assembler::below, m_one);
12336 __ jccb(Assembler::equal, done);
12337 __ bind(p_one);
12338 __ incrementl($dst$$Register);
12339 __ jmpb(done);
12340 __ bind(m_one);
12341 __ decrementl($dst$$Register);
12342 __ bind(done);
12343 %}
12344 ins_pipe( pipe_slow );
12345 %}
12346
12347 //======
12348 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12349 // compares. Can be used for LE or GT compares by reversing arguments.
12350 // NOT GOOD FOR EQ/NE tests.
12351 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{
12352 match( Set flags (CmpL src zero ));
12353 ins_cost(100);
12354 format %{ "TEST $src.hi,$src.hi" %}
12355 opcode(0x85);
12356 ins_encode( OpcP, RegReg_Hi2( src, src ) );
12357 ins_pipe( ialu_cr_reg_reg );
12358 %}
12359
12360 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12361 // compares. Can be used for LE or GT compares by reversing arguments.
12362 // NOT GOOD FOR EQ/NE tests.
12363 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, rRegI tmp ) %{
12364 match( Set flags (CmpL src1 src2 ));
12365 effect( TEMP tmp );
12366 ins_cost(300);
12367 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12368 "MOV $tmp,$src1.hi\n\t"
12369 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %}
12370 ins_encode( long_cmp_flags2( src1, src2, tmp ) );
12371 ins_pipe( ialu_cr_reg_reg );
12372 %}
12373
12374 // Long compares reg < zero/req OR reg >= zero/req.
12375 // Just a wrapper for a normal branch, plus the predicate test.
12376 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{
12377 match(If cmp flags);
12378 effect(USE labl);
12379 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12380 expand %{
12381 jmpCon(cmp,flags,labl); // JLT or JGE...
12382 %}
12383 %}
12384
12385 // Compare 2 longs and CMOVE longs.
12386 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{
12387 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12388 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12389 ins_cost(400);
12390 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12391 "CMOV$cmp $dst.hi,$src.hi" %}
12392 opcode(0x0F,0x40);
12393 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12394 ins_pipe( pipe_cmov_reg_long );
12395 %}
12396
12397 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{
12398 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12399 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12400 ins_cost(500);
12401 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12402 "CMOV$cmp $dst.hi,$src.hi" %}
12403 opcode(0x0F,0x40);
12404 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12405 ins_pipe( pipe_cmov_reg_long );
12406 %}
12407
12408 // Compare 2 longs and CMOVE ints.
12409 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, rRegI src) %{
12410 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12411 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12412 ins_cost(200);
12413 format %{ "CMOV$cmp $dst,$src" %}
12414 opcode(0x0F,0x40);
12415 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12416 ins_pipe( pipe_cmov_reg );
12417 %}
12418
12419 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, memory src) %{
12420 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12421 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12422 ins_cost(250);
12423 format %{ "CMOV$cmp $dst,$src" %}
12424 opcode(0x0F,0x40);
12425 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12426 ins_pipe( pipe_cmov_mem );
12427 %}
12428
12429 // Compare 2 longs and CMOVE ints.
12430 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{
12431 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12432 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12433 ins_cost(200);
12434 format %{ "CMOV$cmp $dst,$src" %}
12435 opcode(0x0F,0x40);
12436 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12437 ins_pipe( pipe_cmov_reg );
12438 %}
12439
12440 // Compare 2 longs and CMOVE doubles
12441 instruct cmovDDPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regDPR dst, regDPR src) %{
12442 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12443 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12444 ins_cost(200);
12445 expand %{
12446 fcmovDPR_regS(cmp,flags,dst,src);
12447 %}
12448 %}
12449
12450 // Compare 2 longs and CMOVE doubles
12451 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{
12452 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12453 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12454 ins_cost(200);
12455 expand %{
12456 fcmovD_regS(cmp,flags,dst,src);
12457 %}
12458 %}
12459
12460 instruct cmovFFPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regFPR dst, regFPR src) %{
12461 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12462 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12463 ins_cost(200);
12464 expand %{
12465 fcmovFPR_regS(cmp,flags,dst,src);
12466 %}
12467 %}
12468
12469 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{
12470 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12471 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12472 ins_cost(200);
12473 expand %{
12474 fcmovF_regS(cmp,flags,dst,src);
12475 %}
12476 %}
12477
12478 //======
12479 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
12480 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, rRegI tmp ) %{
12481 match( Set flags (CmpL src zero ));
12482 effect(TEMP tmp);
12483 ins_cost(200);
12484 format %{ "MOV $tmp,$src.lo\n\t"
12485 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %}
12486 ins_encode( long_cmp_flags0( src, tmp ) );
12487 ins_pipe( ialu_reg_reg_long );
12488 %}
12489
12490 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
12491 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{
12492 match( Set flags (CmpL src1 src2 ));
12493 ins_cost(200+300);
12494 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12495 "JNE,s skip\n\t"
12496 "CMP $src1.hi,$src2.hi\n\t"
12497 "skip:\t" %}
12498 ins_encode( long_cmp_flags1( src1, src2 ) );
12499 ins_pipe( ialu_cr_reg_reg );
12500 %}
12501
12502 // Long compare reg == zero/reg OR reg != zero/reg
12503 // Just a wrapper for a normal branch, plus the predicate test.
12504 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{
12505 match(If cmp flags);
12506 effect(USE labl);
12507 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12508 expand %{
12509 jmpCon(cmp,flags,labl); // JEQ or JNE...
12510 %}
12511 %}
12512
12513 // Compare 2 longs and CMOVE longs.
12514 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{
12515 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12516 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12517 ins_cost(400);
12518 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12519 "CMOV$cmp $dst.hi,$src.hi" %}
12520 opcode(0x0F,0x40);
12521 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12522 ins_pipe( pipe_cmov_reg_long );
12523 %}
12524
12525 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{
12526 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12527 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12528 ins_cost(500);
12529 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12530 "CMOV$cmp $dst.hi,$src.hi" %}
12531 opcode(0x0F,0x40);
12532 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12533 ins_pipe( pipe_cmov_reg_long );
12534 %}
12535
12536 // Compare 2 longs and CMOVE ints.
12537 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, rRegI src) %{
12538 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12539 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12540 ins_cost(200);
12541 format %{ "CMOV$cmp $dst,$src" %}
12542 opcode(0x0F,0x40);
12543 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12544 ins_pipe( pipe_cmov_reg );
12545 %}
12546
12547 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, memory src) %{
12548 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12549 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12550 ins_cost(250);
12551 format %{ "CMOV$cmp $dst,$src" %}
12552 opcode(0x0F,0x40);
12553 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12554 ins_pipe( pipe_cmov_mem );
12555 %}
12556
12557 // Compare 2 longs and CMOVE ints.
12558 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{
12559 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12560 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12561 ins_cost(200);
12562 format %{ "CMOV$cmp $dst,$src" %}
12563 opcode(0x0F,0x40);
12564 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12565 ins_pipe( pipe_cmov_reg );
12566 %}
12567
12568 // Compare 2 longs and CMOVE doubles
12569 instruct cmovDDPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regDPR dst, regDPR src) %{
12570 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12571 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12572 ins_cost(200);
12573 expand %{
12574 fcmovDPR_regS(cmp,flags,dst,src);
12575 %}
12576 %}
12577
12578 // Compare 2 longs and CMOVE doubles
12579 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{
12580 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12581 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12582 ins_cost(200);
12583 expand %{
12584 fcmovD_regS(cmp,flags,dst,src);
12585 %}
12586 %}
12587
12588 instruct cmovFFPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regFPR dst, regFPR src) %{
12589 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12590 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12591 ins_cost(200);
12592 expand %{
12593 fcmovFPR_regS(cmp,flags,dst,src);
12594 %}
12595 %}
12596
12597 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{
12598 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12599 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12600 ins_cost(200);
12601 expand %{
12602 fcmovF_regS(cmp,flags,dst,src);
12603 %}
12604 %}
12605
12606 //======
12607 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
12608 // Same as cmpL_reg_flags_LEGT except must negate src
12609 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, rRegI tmp ) %{
12610 match( Set flags (CmpL src zero ));
12611 effect( TEMP tmp );
12612 ins_cost(300);
12613 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t"
12614 "CMP $tmp,$src.lo\n\t"
12615 "SBB $tmp,$src.hi\n\t" %}
12616 ins_encode( long_cmp_flags3(src, tmp) );
12617 ins_pipe( ialu_reg_reg_long );
12618 %}
12619
12620 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
12621 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands
12622 // requires a commuted test to get the same result.
12623 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, rRegI tmp ) %{
12624 match( Set flags (CmpL src1 src2 ));
12625 effect( TEMP tmp );
12626 ins_cost(300);
12627 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t"
12628 "MOV $tmp,$src2.hi\n\t"
12629 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %}
12630 ins_encode( long_cmp_flags2( src2, src1, tmp ) );
12631 ins_pipe( ialu_cr_reg_reg );
12632 %}
12633
12634 // Long compares reg < zero/req OR reg >= zero/req.
12635 // Just a wrapper for a normal branch, plus the predicate test
12636 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{
12637 match(If cmp flags);
12638 effect(USE labl);
12639 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le );
12640 ins_cost(300);
12641 expand %{
12642 jmpCon(cmp,flags,labl); // JGT or JLE...
12643 %}
12644 %}
12645
12646 // Compare 2 longs and CMOVE longs.
12647 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{
12648 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12649 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12650 ins_cost(400);
12651 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12652 "CMOV$cmp $dst.hi,$src.hi" %}
12653 opcode(0x0F,0x40);
12654 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12655 ins_pipe( pipe_cmov_reg_long );
12656 %}
12657
12658 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{
12659 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12660 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12661 ins_cost(500);
12662 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12663 "CMOV$cmp $dst.hi,$src.hi+4" %}
12664 opcode(0x0F,0x40);
12665 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12666 ins_pipe( pipe_cmov_reg_long );
12667 %}
12668
12669 // Compare 2 longs and CMOVE ints.
12670 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, rRegI src) %{
12671 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12672 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12673 ins_cost(200);
12674 format %{ "CMOV$cmp $dst,$src" %}
12675 opcode(0x0F,0x40);
12676 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12677 ins_pipe( pipe_cmov_reg );
12678 %}
12679
12680 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, memory src) %{
12681 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12682 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12683 ins_cost(250);
12684 format %{ "CMOV$cmp $dst,$src" %}
12685 opcode(0x0F,0x40);
12686 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12687 ins_pipe( pipe_cmov_mem );
12688 %}
12689
12690 // Compare 2 longs and CMOVE ptrs.
12691 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{
12692 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12693 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12694 ins_cost(200);
12695 format %{ "CMOV$cmp $dst,$src" %}
12696 opcode(0x0F,0x40);
12697 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12698 ins_pipe( pipe_cmov_reg );
12699 %}
12700
12701 // Compare 2 longs and CMOVE doubles
12702 instruct cmovDDPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regDPR dst, regDPR src) %{
12703 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12704 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12705 ins_cost(200);
12706 expand %{
12707 fcmovDPR_regS(cmp,flags,dst,src);
12708 %}
12709 %}
12710
12711 // Compare 2 longs and CMOVE doubles
12712 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{
12713 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12714 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12715 ins_cost(200);
12716 expand %{
12717 fcmovD_regS(cmp,flags,dst,src);
12718 %}
12719 %}
12720
12721 instruct cmovFFPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regFPR dst, regFPR src) %{
12722 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12723 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12724 ins_cost(200);
12725 expand %{
12726 fcmovFPR_regS(cmp,flags,dst,src);
12727 %}
12728 %}
12729
12730
12731 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{
12732 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12733 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12734 ins_cost(200);
12735 expand %{
12736 fcmovF_regS(cmp,flags,dst,src);
12737 %}
12738 %}
12739
12740
12741 // ============================================================================
12742 // Procedure Call/Return Instructions
12743 // Call Java Static Instruction
12744 // Note: If this code changes, the corresponding ret_addr_offset() and
12745 // compute_padding() functions will have to be adjusted.
12746 instruct CallStaticJavaDirect(method meth) %{
12747 match(CallStaticJava);
12748 effect(USE meth);
12749
12750 ins_cost(300);
12751 format %{ "CALL,static " %}
12752 opcode(0xE8); /* E8 cd */
12753 ins_encode( pre_call_resets,
12754 Java_Static_Call( meth ),
12755 call_epilog,
12756 post_call_FPU );
12757 ins_pipe( pipe_slow );
12758 ins_alignment(4);
12759 %}
12760
12761 // Call Java Dynamic Instruction
12762 // Note: If this code changes, the corresponding ret_addr_offset() and
12763 // compute_padding() functions will have to be adjusted.
12764 instruct CallDynamicJavaDirect(method meth) %{
12765 match(CallDynamicJava);
12766 effect(USE meth);
12767
12768 ins_cost(300);
12769 format %{ "MOV EAX,(oop)-1\n\t"
12770 "CALL,dynamic" %}
12771 opcode(0xE8); /* E8 cd */
12772 ins_encode( pre_call_resets,
12773 Java_Dynamic_Call( meth ),
12774 call_epilog,
12775 post_call_FPU );
12776 ins_pipe( pipe_slow );
12777 ins_alignment(4);
12778 %}
12779
12780 // Call Runtime Instruction
12781 instruct CallRuntimeDirect(method meth) %{
12782 match(CallRuntime );
12783 effect(USE meth);
12784
12785 ins_cost(300);
12786 format %{ "CALL,runtime " %}
12787 opcode(0xE8); /* E8 cd */
12788 // Use FFREEs to clear entries in float stack
12789 ins_encode( pre_call_resets,
12790 FFree_Float_Stack_All,
12791 Java_To_Runtime( meth ),
12792 post_call_FPU );
12793 ins_pipe( pipe_slow );
12794 %}
12795
12796 // Call runtime without safepoint
12797 instruct CallLeafDirect(method meth) %{
12798 match(CallLeaf);
12799 effect(USE meth);
12800
12801 ins_cost(300);
12802 format %{ "CALL_LEAF,runtime " %}
12803 opcode(0xE8); /* E8 cd */
12804 ins_encode( pre_call_resets,
12805 FFree_Float_Stack_All,
12806 Java_To_Runtime( meth ),
12807 Verify_FPU_For_Leaf, post_call_FPU );
12808 ins_pipe( pipe_slow );
12809 %}
12810
12811 instruct CallLeafNoFPDirect(method meth) %{
12812 match(CallLeafNoFP);
12813 effect(USE meth);
12814
12815 ins_cost(300);
12816 format %{ "CALL_LEAF_NOFP,runtime " %}
12817 opcode(0xE8); /* E8 cd */
12818 ins_encode(Java_To_Runtime(meth));
12819 ins_pipe( pipe_slow );
12820 %}
12821
12822
12823 // Return Instruction
12824 // Remove the return address & jump to it.
12825 instruct Ret() %{
12826 match(Return);
12827 format %{ "RET" %}
12828 opcode(0xC3);
12829 ins_encode(OpcP);
12830 ins_pipe( pipe_jmp );
12831 %}
12832
12833 // Tail Call; Jump from runtime stub to Java code.
12834 // Also known as an 'interprocedural jump'.
12835 // Target of jump will eventually return to caller.
12836 // TailJump below removes the return address.
12837 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{
12838 match(TailCall jump_target method_oop );
12839 ins_cost(300);
12840 format %{ "JMP $jump_target \t# EBX holds method oop" %}
12841 opcode(0xFF, 0x4); /* Opcode FF /4 */
12842 ins_encode( OpcP, RegOpc(jump_target) );
12843 ins_pipe( pipe_jmp );
12844 %}
12845
12846
12847 // Tail Jump; remove the return address; jump to target.
12848 // TailCall above leaves the return address around.
12849 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{
12850 match( TailJump jump_target ex_oop );
12851 ins_cost(300);
12852 format %{ "POP EDX\t# pop return address into dummy\n\t"
12853 "JMP $jump_target " %}
12854 opcode(0xFF, 0x4); /* Opcode FF /4 */
12855 ins_encode( enc_pop_rdx,
12856 OpcP, RegOpc(jump_target) );
12857 ins_pipe( pipe_jmp );
12858 %}
12859
12860 // Create exception oop: created by stack-crawling runtime code.
12861 // Created exception is now available to this handler, and is setup
12862 // just prior to jumping to this handler. No code emitted.
12863 instruct CreateException( eAXRegP ex_oop )
12864 %{
12865 match(Set ex_oop (CreateEx));
12866
12867 size(0);
12868 // use the following format syntax
12869 format %{ "# exception oop is in EAX; no code emitted" %}
12870 ins_encode();
12871 ins_pipe( empty );
12872 %}
12873
12874
12875 // Rethrow exception:
12876 // The exception oop will come in the first argument position.
12877 // Then JUMP (not call) to the rethrow stub code.
12878 instruct RethrowException()
12879 %{
12880 match(Rethrow);
12881
12882 // use the following format syntax
12883 format %{ "JMP rethrow_stub" %}
12884 ins_encode(enc_rethrow);
12885 ins_pipe( pipe_jmp );
12886 %}
12887
12888 // inlined locking and unlocking
12889
12890 instruct cmpFastLockRTM(eFlagsReg cr, eRegP object, eBXRegP box, eAXRegI tmp, eDXRegI scr, rRegI cx1, rRegI cx2) %{
12891 predicate(Compile::current()->use_rtm());
12892 match(Set cr (FastLock object box));
12893 effect(TEMP tmp, TEMP scr, TEMP cx1, TEMP cx2, USE_KILL box);
12894 ins_cost(300);
12895 format %{ "FASTLOCK $object,$box\t! kills $box,$tmp,$scr,$cx1,$cx2" %}
12896 ins_encode %{
12897 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
12898 $scr$$Register, $cx1$$Register, $cx2$$Register,
12899 _counters, _rtm_counters, _stack_rtm_counters,
12900 ((Method*)(ra_->C->method()->constant_encoding()))->method_data(),
12901 true, ra_->C->profile_rtm());
12902 %}
12903 ins_pipe(pipe_slow);
12904 %}
12905
12906 instruct cmpFastLock(eFlagsReg cr, eRegP object, eBXRegP box, eAXRegI tmp, eRegP scr) %{
12907 predicate(!Compile::current()->use_rtm());
12908 match(Set cr (FastLock object box));
12909 effect(TEMP tmp, TEMP scr, USE_KILL box);
12910 ins_cost(300);
12911 format %{ "FASTLOCK $object,$box\t! kills $box,$tmp,$scr" %}
12912 ins_encode %{
12913 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
12914 $scr$$Register, noreg, noreg, _counters, NULL, NULL, NULL, false, false);
12915 %}
12916 ins_pipe(pipe_slow);
12917 %}
12918
12919 instruct cmpFastUnlock(eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{
12920 match(Set cr (FastUnlock object box));
12921 effect(TEMP tmp, USE_KILL box);
12922 ins_cost(300);
12923 format %{ "FASTUNLOCK $object,$box\t! kills $box,$tmp" %}
12924 ins_encode %{
12925 __ fast_unlock($object$$Register, $box$$Register, $tmp$$Register, ra_->C->use_rtm());
12926 %}
12927 ins_pipe(pipe_slow);
12928 %}
12929
12930
12931
12932 // ============================================================================
12933 // Safepoint Instruction
12934 instruct safePoint_poll(eFlagsReg cr) %{
12935 match(SafePoint);
12936 effect(KILL cr);
12937
12938 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page.
12939 // On SPARC that might be acceptable as we can generate the address with
12940 // just a sethi, saving an or. By polling at offset 0 we can end up
12941 // putting additional pressure on the index-0 in the D$. Because of
12942 // alignment (just like the situation at hand) the lower indices tend
12943 // to see more traffic. It'd be better to change the polling address
12944 // to offset 0 of the last $line in the polling page.
12945
12946 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %}
12947 ins_cost(125);
12948 size(6) ;
12949 ins_encode( Safepoint_Poll() );
12950 ins_pipe( ialu_reg_mem );
12951 %}
12952
12953
12954 // ============================================================================
12955 // This name is KNOWN by the ADLC and cannot be changed.
12956 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
12957 // for this guy.
12958 instruct tlsLoadP(eRegP dst, eFlagsReg cr) %{
12959 match(Set dst (ThreadLocal));
12960 effect(DEF dst, KILL cr);
12961
12962 format %{ "MOV $dst, Thread::current()" %}
12963 ins_encode %{
12964 Register dstReg = as_Register($dst$$reg);
12965 __ get_thread(dstReg);
12966 %}
12967 ins_pipe( ialu_reg_fat );
12968 %}
12969
12970
12971
12972 //----------PEEPHOLE RULES-----------------------------------------------------
12973 // These must follow all instruction definitions as they use the names
12974 // defined in the instructions definitions.
12975 //
12976 // peepmatch ( root_instr_name [preceding_instruction]* );
12977 //
12978 // peepconstraint %{
12979 // (instruction_number.operand_name relational_op instruction_number.operand_name
12980 // [, ...] );
12981 // // instruction numbers are zero-based using left to right order in peepmatch
12982 //
12983 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
12984 // // provide an instruction_number.operand_name for each operand that appears
12985 // // in the replacement instruction's match rule
12986 //
12987 // ---------VM FLAGS---------------------------------------------------------
12988 //
12989 // All peephole optimizations can be turned off using -XX:-OptoPeephole
12990 //
12991 // Each peephole rule is given an identifying number starting with zero and
12992 // increasing by one in the order seen by the parser. An individual peephole
12993 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
12994 // on the command-line.
12995 //
12996 // ---------CURRENT LIMITATIONS----------------------------------------------
12997 //
12998 // Only match adjacent instructions in same basic block
12999 // Only equality constraints
13000 // Only constraints between operands, not (0.dest_reg == EAX_enc)
13001 // Only one replacement instruction
13002 //
13003 // ---------EXAMPLE----------------------------------------------------------
13004 //
13005 // // pertinent parts of existing instructions in architecture description
13006 // instruct movI(rRegI dst, rRegI src) %{
13007 // match(Set dst (CopyI src));
13008 // %}
13009 //
13010 // instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
13011 // match(Set dst (AddI dst src));
13012 // effect(KILL cr);
13013 // %}
13014 //
13015 // // Change (inc mov) to lea
13016 // peephole %{
13017 // // increment preceeded by register-register move
13018 // peepmatch ( incI_eReg movI );
13019 // // require that the destination register of the increment
13020 // // match the destination register of the move
13021 // peepconstraint ( 0.dst == 1.dst );
13022 // // construct a replacement instruction that sets
13023 // // the destination to ( move's source register + one )
13024 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13025 // %}
13026 //
13027 // Implementation no longer uses movX instructions since
13028 // machine-independent system no longer uses CopyX nodes.
13029 //
13030 // peephole %{
13031 // peepmatch ( incI_eReg movI );
13032 // peepconstraint ( 0.dst == 1.dst );
13033 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13034 // %}
13035 //
13036 // peephole %{
13037 // peepmatch ( decI_eReg movI );
13038 // peepconstraint ( 0.dst == 1.dst );
13039 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13040 // %}
13041 //
13042 // peephole %{
13043 // peepmatch ( addI_eReg_imm movI );
13044 // peepconstraint ( 0.dst == 1.dst );
13045 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13046 // %}
13047 //
13048 // peephole %{
13049 // peepmatch ( addP_eReg_imm movP );
13050 // peepconstraint ( 0.dst == 1.dst );
13051 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
13052 // %}
13053
13054 // // Change load of spilled value to only a spill
13055 // instruct storeI(memory mem, rRegI src) %{
13056 // match(Set mem (StoreI mem src));
13057 // %}
13058 //
13059 // instruct loadI(rRegI dst, memory mem) %{
13060 // match(Set dst (LoadI mem));
13061 // %}
13062 //
13063 peephole %{
13064 peepmatch ( loadI storeI );
13065 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
13066 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
13067 %}
13068
13069 //----------SMARTSPILL RULES---------------------------------------------------
13070 // These must follow all instruction definitions as they use the names
13071 // defined in the instructions definitions.