< prev index next >

src/cpu/sparc/vm/vm_version_sparc.cpp

Print this page

        

*** 72,82 **** if ((AllocatePrefetchDistance % AllocatePrefetchStepSize) != 0 || (AllocatePrefetchDistance <= 0)) { AllocatePrefetchDistance = AllocatePrefetchStepSize; } ! if (AllocatePrefetchStyle == 3 && !has_blk_init()) { warning("BIS instructions are not available on this CPU"); FLAG_SET_DEFAULT(AllocatePrefetchStyle, 1); } assert(ArraycopySrcPrefetchDistance < 4096, "invalid value"); --- 72,82 ---- if ((AllocatePrefetchDistance % AllocatePrefetchStepSize) != 0 || (AllocatePrefetchDistance <= 0)) { AllocatePrefetchDistance = AllocatePrefetchStepSize; } ! if (AllocatePrefetchStyle == 3 && (!has_blk_init() || cache_line_size <= 0)) { warning("BIS instructions are not available on this CPU"); FLAG_SET_DEFAULT(AllocatePrefetchStyle, 1); } assert(ArraycopySrcPrefetchDistance < 4096, "invalid value");
*** 136,146 **** // aligned on a single instruction boundary if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) { FLAG_SET_DEFAULT(InteriorEntryAlignment, 4); } if (is_niagara_plus()) { ! if (has_blk_init() && UseTLAB && FLAG_IS_DEFAULT(AllocatePrefetchInstr)) { // Use BIS instruction for TLAB allocation prefetch. FLAG_SET_ERGO(intx, AllocatePrefetchInstr, 1); if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) { FLAG_SET_ERGO(intx, AllocatePrefetchStyle, 3); --- 136,146 ---- // aligned on a single instruction boundary if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) { FLAG_SET_DEFAULT(InteriorEntryAlignment, 4); } if (is_niagara_plus()) { ! if (has_blk_init() && (cache_line_size > 0) && UseTLAB && FLAG_IS_DEFAULT(AllocatePrefetchInstr)) { // Use BIS instruction for TLAB allocation prefetch. FLAG_SET_ERGO(intx, AllocatePrefetchInstr, 1); if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) { FLAG_SET_ERGO(intx, AllocatePrefetchStyle, 3);
< prev index next >