57 if( cache_line_size > AllocatePrefetchStepSize )
58 AllocatePrefetchStepSize = cache_line_size;
59
60 assert(AllocatePrefetchLines > 0, "invalid value");
61 if( AllocatePrefetchLines < 1 ) // set valid value in product VM
62 AllocatePrefetchLines = 3;
63 assert(AllocateInstancePrefetchLines > 0, "invalid value");
64 if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM
65 AllocateInstancePrefetchLines = 1;
66
67 AllocatePrefetchDistance = allocate_prefetch_distance();
68 AllocatePrefetchStyle = allocate_prefetch_style();
69
70 assert((AllocatePrefetchDistance % AllocatePrefetchStepSize) == 0 &&
71 (AllocatePrefetchDistance > 0), "invalid value");
72 if ((AllocatePrefetchDistance % AllocatePrefetchStepSize) != 0 ||
73 (AllocatePrefetchDistance <= 0)) {
74 AllocatePrefetchDistance = AllocatePrefetchStepSize;
75 }
76
77 if (AllocatePrefetchStyle == 3 && !has_blk_init()) {
78 warning("BIS instructions are not available on this CPU");
79 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 1);
80 }
81
82 assert(ArraycopySrcPrefetchDistance < 4096, "invalid value");
83 if (ArraycopySrcPrefetchDistance >= 4096)
84 ArraycopySrcPrefetchDistance = 4064;
85 assert(ArraycopyDstPrefetchDistance < 4096, "invalid value");
86 if (ArraycopyDstPrefetchDistance >= 4096)
87 ArraycopyDstPrefetchDistance = 4064;
88
89 UseSSE = 0; // Only on x86 and x64
90
91 _supports_cx8 = has_v9();
92 _supports_atomic_getset4 = true; // swap instruction
93
94 // There are Fujitsu Sparc64 CPUs which support blk_init as well so
95 // we have to take this check out of the 'is_niagara()' block below.
96 if (has_blk_init()) {
97 // When using CMS or G1, we cannot use memset() in BOT updates
121 if (FLAG_IS_DEFAULT(OptoLoopAlignment)) {
122 FLAG_SET_DEFAULT(OptoLoopAlignment, 4);
123 }
124 #ifdef _LP64
125 // 32-bit oops don't make sense for the 64-bit VM on sparc
126 // since the 32-bit VM has the same registers and smaller objects.
127 Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes);
128 Universe::set_narrow_klass_shift(LogKlassAlignmentInBytes);
129 #endif // _LP64
130 #ifdef COMPILER2
131 // Indirect branch is the same cost as direct
132 if (FLAG_IS_DEFAULT(UseJumpTables)) {
133 FLAG_SET_DEFAULT(UseJumpTables, true);
134 }
135 // Single-issue, so entry and loop tops are
136 // aligned on a single instruction boundary
137 if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) {
138 FLAG_SET_DEFAULT(InteriorEntryAlignment, 4);
139 }
140 if (is_niagara_plus()) {
141 if (has_blk_init() && UseTLAB &&
142 FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
143 // Use BIS instruction for TLAB allocation prefetch.
144 FLAG_SET_ERGO(intx, AllocatePrefetchInstr, 1);
145 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
146 FLAG_SET_ERGO(intx, AllocatePrefetchStyle, 3);
147 }
148 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
149 // Use smaller prefetch distance with BIS
150 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64);
151 }
152 }
153 if (is_T4()) {
154 // Double number of prefetched cache lines on T4
155 // since L2 cache line size is smaller (32 bytes).
156 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) {
157 FLAG_SET_ERGO(intx, AllocatePrefetchLines, AllocatePrefetchLines*2);
158 }
159 if (FLAG_IS_DEFAULT(AllocateInstancePrefetchLines)) {
160 FLAG_SET_ERGO(intx, AllocateInstancePrefetchLines, AllocateInstancePrefetchLines*2);
161 }
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57 if( cache_line_size > AllocatePrefetchStepSize )
58 AllocatePrefetchStepSize = cache_line_size;
59
60 assert(AllocatePrefetchLines > 0, "invalid value");
61 if( AllocatePrefetchLines < 1 ) // set valid value in product VM
62 AllocatePrefetchLines = 3;
63 assert(AllocateInstancePrefetchLines > 0, "invalid value");
64 if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM
65 AllocateInstancePrefetchLines = 1;
66
67 AllocatePrefetchDistance = allocate_prefetch_distance();
68 AllocatePrefetchStyle = allocate_prefetch_style();
69
70 assert((AllocatePrefetchDistance % AllocatePrefetchStepSize) == 0 &&
71 (AllocatePrefetchDistance > 0), "invalid value");
72 if ((AllocatePrefetchDistance % AllocatePrefetchStepSize) != 0 ||
73 (AllocatePrefetchDistance <= 0)) {
74 AllocatePrefetchDistance = AllocatePrefetchStepSize;
75 }
76
77 if (AllocatePrefetchStyle == 3 && (!has_blk_init() || cache_line_size <= 0)) {
78 warning("BIS instructions are not available on this CPU");
79 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 1);
80 }
81
82 assert(ArraycopySrcPrefetchDistance < 4096, "invalid value");
83 if (ArraycopySrcPrefetchDistance >= 4096)
84 ArraycopySrcPrefetchDistance = 4064;
85 assert(ArraycopyDstPrefetchDistance < 4096, "invalid value");
86 if (ArraycopyDstPrefetchDistance >= 4096)
87 ArraycopyDstPrefetchDistance = 4064;
88
89 UseSSE = 0; // Only on x86 and x64
90
91 _supports_cx8 = has_v9();
92 _supports_atomic_getset4 = true; // swap instruction
93
94 // There are Fujitsu Sparc64 CPUs which support blk_init as well so
95 // we have to take this check out of the 'is_niagara()' block below.
96 if (has_blk_init()) {
97 // When using CMS or G1, we cannot use memset() in BOT updates
121 if (FLAG_IS_DEFAULT(OptoLoopAlignment)) {
122 FLAG_SET_DEFAULT(OptoLoopAlignment, 4);
123 }
124 #ifdef _LP64
125 // 32-bit oops don't make sense for the 64-bit VM on sparc
126 // since the 32-bit VM has the same registers and smaller objects.
127 Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes);
128 Universe::set_narrow_klass_shift(LogKlassAlignmentInBytes);
129 #endif // _LP64
130 #ifdef COMPILER2
131 // Indirect branch is the same cost as direct
132 if (FLAG_IS_DEFAULT(UseJumpTables)) {
133 FLAG_SET_DEFAULT(UseJumpTables, true);
134 }
135 // Single-issue, so entry and loop tops are
136 // aligned on a single instruction boundary
137 if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) {
138 FLAG_SET_DEFAULT(InteriorEntryAlignment, 4);
139 }
140 if (is_niagara_plus()) {
141 if (has_blk_init() && (cache_line_size > 0) && UseTLAB &&
142 FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
143 // Use BIS instruction for TLAB allocation prefetch.
144 FLAG_SET_ERGO(intx, AllocatePrefetchInstr, 1);
145 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
146 FLAG_SET_ERGO(intx, AllocatePrefetchStyle, 3);
147 }
148 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
149 // Use smaller prefetch distance with BIS
150 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64);
151 }
152 }
153 if (is_T4()) {
154 // Double number of prefetched cache lines on T4
155 // since L2 cache line size is smaller (32 bytes).
156 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) {
157 FLAG_SET_ERGO(intx, AllocatePrefetchLines, AllocatePrefetchLines*2);
158 }
159 if (FLAG_IS_DEFAULT(AllocateInstancePrefetchLines)) {
160 FLAG_SET_ERGO(intx, AllocateInstancePrefetchLines, AllocateInstancePrefetchLines*2);
161 }
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