1 /*
   2  * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "c1/c1_CFGPrinter.hpp"
  27 #include "c1/c1_CodeStubs.hpp"
  28 #include "c1/c1_Compilation.hpp"
  29 #include "c1/c1_FrameMap.hpp"
  30 #include "c1/c1_IR.hpp"
  31 #include "c1/c1_LIRGenerator.hpp"
  32 #include "c1/c1_LinearScan.hpp"
  33 #include "c1/c1_ValueStack.hpp"
  34 #include "utilities/bitMap.inline.hpp"
  35 #ifdef TARGET_ARCH_x86
  36 # include "vmreg_x86.inline.hpp"
  37 #endif
  38 #ifdef TARGET_ARCH_sparc
  39 # include "vmreg_sparc.inline.hpp"
  40 #endif
  41 #ifdef TARGET_ARCH_zero
  42 # include "vmreg_zero.inline.hpp"
  43 #endif
  44 #ifdef TARGET_ARCH_arm
  45 # include "vmreg_arm.inline.hpp"
  46 #endif
  47 #ifdef TARGET_ARCH_ppc
  48 # include "vmreg_ppc.inline.hpp"
  49 #endif
  50 
  51 
  52 #ifndef PRODUCT
  53 
  54   static LinearScanStatistic _stat_before_alloc;
  55   static LinearScanStatistic _stat_after_asign;
  56   static LinearScanStatistic _stat_final;
  57 
  58   static LinearScanTimers _total_timer;
  59 
  60   // helper macro for short definition of timer
  61   #define TIME_LINEAR_SCAN(timer_name)  TraceTime _block_timer("", _total_timer.timer(LinearScanTimers::timer_name), TimeLinearScan || TimeEachLinearScan, Verbose);
  62 
  63   // helper macro for short definition of trace-output inside code
  64   #define TRACE_LINEAR_SCAN(level, code)       \
  65     if (TraceLinearScanLevel >= level) {       \
  66       code;                                    \
  67     }
  68 
  69 #else
  70 
  71   #define TIME_LINEAR_SCAN(timer_name)
  72   #define TRACE_LINEAR_SCAN(level, code)
  73 
  74 #endif
  75 
  76 // Map BasicType to spill size in 32-bit words, matching VMReg's notion of words
  77 #ifdef _LP64
  78 static int type2spill_size[T_CONFLICT+1]={ -1, 0, 0, 0, 1, 1, 1, 2, 1, 1, 1, 2, 2, 2, 0, 1, -1};
  79 #else
  80 static int type2spill_size[T_CONFLICT+1]={ -1, 0, 0, 0, 1, 1, 1, 2, 1, 1, 1, 2, 1, 1, 0, 1, -1};
  81 #endif
  82 
  83 
  84 // Implementation of LinearScan
  85 
  86 LinearScan::LinearScan(IR* ir, LIRGenerator* gen, FrameMap* frame_map)
  87  : _compilation(ir->compilation())
  88  , _ir(ir)
  89  , _gen(gen)
  90  , _frame_map(frame_map)
  91  , _num_virtual_regs(gen->max_virtual_register_number())
  92  , _has_fpu_registers(false)
  93  , _num_calls(-1)
  94  , _max_spills(0)
  95  , _unused_spill_slot(-1)
  96  , _intervals(0)   // initialized later with correct length
  97  , _new_intervals_from_allocation(new IntervalList())
  98  , _sorted_intervals(NULL)
  99  , _needs_full_resort(false)
 100  , _lir_ops(0)     // initialized later with correct length
 101  , _block_of_op(0) // initialized later with correct length
 102  , _has_info(0)
 103  , _has_call(0)
 104  , _scope_value_cache(0) // initialized later with correct length
 105  , _interval_in_loop(0, 0) // initialized later with correct length
 106  , _cached_blocks(*ir->linear_scan_order())
 107 #ifdef X86
 108  , _fpu_stack_allocator(NULL)
 109 #endif
 110 {
 111   assert(this->ir() != NULL,          "check if valid");
 112   assert(this->compilation() != NULL, "check if valid");
 113   assert(this->gen() != NULL,         "check if valid");
 114   assert(this->frame_map() != NULL,   "check if valid");
 115 }
 116 
 117 
 118 // ********** functions for converting LIR-Operands to register numbers
 119 //
 120 // Emulate a flat register file comprising physical integer registers,
 121 // physical floating-point registers and virtual registers, in that order.
 122 // Virtual registers already have appropriate numbers, since V0 is
 123 // the number of physical registers.
 124 // Returns -1 for hi word if opr is a single word operand.
 125 //
 126 // Note: the inverse operation (calculating an operand for register numbers)
 127 //       is done in calc_operand_for_interval()
 128 
 129 int LinearScan::reg_num(LIR_Opr opr) {
 130   assert(opr->is_register(), "should not call this otherwise");
 131 
 132   if (opr->is_virtual_register()) {
 133     assert(opr->vreg_number() >= nof_regs, "found a virtual register with a fixed-register number");
 134     return opr->vreg_number();
 135   } else if (opr->is_single_cpu()) {
 136     return opr->cpu_regnr();
 137   } else if (opr->is_double_cpu()) {
 138     return opr->cpu_regnrLo();
 139 #ifdef X86
 140   } else if (opr->is_single_xmm()) {
 141     return opr->fpu_regnr() + pd_first_xmm_reg;
 142   } else if (opr->is_double_xmm()) {
 143     return opr->fpu_regnrLo() + pd_first_xmm_reg;
 144 #endif
 145   } else if (opr->is_single_fpu()) {
 146     return opr->fpu_regnr() + pd_first_fpu_reg;
 147   } else if (opr->is_double_fpu()) {
 148     return opr->fpu_regnrLo() + pd_first_fpu_reg;
 149   } else {
 150     ShouldNotReachHere();
 151     return -1;
 152   }
 153 }
 154 
 155 int LinearScan::reg_numHi(LIR_Opr opr) {
 156   assert(opr->is_register(), "should not call this otherwise");
 157 
 158   if (opr->is_virtual_register()) {
 159     return -1;
 160   } else if (opr->is_single_cpu()) {
 161     return -1;
 162   } else if (opr->is_double_cpu()) {
 163     return opr->cpu_regnrHi();
 164 #ifdef X86
 165   } else if (opr->is_single_xmm()) {
 166     return -1;
 167   } else if (opr->is_double_xmm()) {
 168     return -1;
 169 #endif
 170   } else if (opr->is_single_fpu()) {
 171     return -1;
 172   } else if (opr->is_double_fpu()) {
 173     return opr->fpu_regnrHi() + pd_first_fpu_reg;
 174   } else {
 175     ShouldNotReachHere();
 176     return -1;
 177   }
 178 }
 179 
 180 
 181 // ********** functions for classification of intervals
 182 
 183 bool LinearScan::is_precolored_interval(const Interval* i) {
 184   return i->reg_num() < LinearScan::nof_regs;
 185 }
 186 
 187 bool LinearScan::is_virtual_interval(const Interval* i) {
 188   return i->reg_num() >= LIR_OprDesc::vreg_base;
 189 }
 190 
 191 bool LinearScan::is_precolored_cpu_interval(const Interval* i) {
 192   return i->reg_num() < LinearScan::nof_cpu_regs;
 193 }
 194 
 195 bool LinearScan::is_virtual_cpu_interval(const Interval* i) {
 196 #if defined(__SOFTFP__) || defined(E500V2)
 197   return i->reg_num() >= LIR_OprDesc::vreg_base;
 198 #else
 199   return i->reg_num() >= LIR_OprDesc::vreg_base && (i->type() != T_FLOAT && i->type() != T_DOUBLE);
 200 #endif // __SOFTFP__ or E500V2
 201 }
 202 
 203 bool LinearScan::is_precolored_fpu_interval(const Interval* i) {
 204   return i->reg_num() >= LinearScan::nof_cpu_regs && i->reg_num() < LinearScan::nof_regs;
 205 }
 206 
 207 bool LinearScan::is_virtual_fpu_interval(const Interval* i) {
 208 #if defined(__SOFTFP__) || defined(E500V2)
 209   return false;
 210 #else
 211   return i->reg_num() >= LIR_OprDesc::vreg_base && (i->type() == T_FLOAT || i->type() == T_DOUBLE);
 212 #endif // __SOFTFP__ or E500V2
 213 }
 214 
 215 bool LinearScan::is_in_fpu_register(const Interval* i) {
 216   // fixed intervals not needed for FPU stack allocation
 217   return i->reg_num() >= nof_regs && pd_first_fpu_reg <= i->assigned_reg() && i->assigned_reg() <= pd_last_fpu_reg;
 218 }
 219 
 220 bool LinearScan::is_oop_interval(const Interval* i) {
 221   // fixed intervals never contain oops
 222   return i->reg_num() >= nof_regs && i->type() == T_OBJECT;
 223 }
 224 
 225 
 226 // ********** General helper functions
 227 
 228 // compute next unused stack index that can be used for spilling
 229 int LinearScan::allocate_spill_slot(bool double_word) {
 230   int spill_slot;
 231   if (double_word) {
 232     if ((_max_spills & 1) == 1) {
 233       // alignment of double-word values
 234       // the hole because of the alignment is filled with the next single-word value
 235       assert(_unused_spill_slot == -1, "wasting a spill slot");
 236       _unused_spill_slot = _max_spills;
 237       _max_spills++;
 238     }
 239     spill_slot = _max_spills;
 240     _max_spills += 2;
 241 
 242   } else if (_unused_spill_slot != -1) {
 243     // re-use hole that was the result of a previous double-word alignment
 244     spill_slot = _unused_spill_slot;
 245     _unused_spill_slot = -1;
 246 
 247   } else {
 248     spill_slot = _max_spills;
 249     _max_spills++;
 250   }
 251 
 252   int result = spill_slot + LinearScan::nof_regs + frame_map()->argcount();
 253 
 254   // the class OopMapValue uses only 11 bits for storing the name of the
 255   // oop location. So a stack slot bigger than 2^11 leads to an overflow
 256   // that is not reported in product builds. Prevent this by checking the
 257   // spill slot here (altough this value and the later used location name
 258   // are slightly different)
 259   if (result > 2000) {
 260     bailout("too many stack slots used");
 261   }
 262 
 263   return result;
 264 }
 265 
 266 void LinearScan::assign_spill_slot(Interval* it) {
 267   // assign the canonical spill slot of the parent (if a part of the interval
 268   // is already spilled) or allocate a new spill slot
 269   if (it->canonical_spill_slot() >= 0) {
 270     it->assign_reg(it->canonical_spill_slot());
 271   } else {
 272     int spill = allocate_spill_slot(type2spill_size[it->type()] == 2);
 273     it->set_canonical_spill_slot(spill);
 274     it->assign_reg(spill);
 275   }
 276 }
 277 
 278 void LinearScan::propagate_spill_slots() {
 279   if (!frame_map()->finalize_frame(max_spills())) {
 280     bailout("frame too large");
 281   }
 282 }
 283 
 284 // create a new interval with a predefined reg_num
 285 // (only used for parent intervals that are created during the building phase)
 286 Interval* LinearScan::create_interval(int reg_num) {
 287   assert(_intervals.at(reg_num) == NULL, "overwriting exisiting interval");
 288 
 289   Interval* interval = new Interval(reg_num);
 290   _intervals.at_put(reg_num, interval);
 291 
 292   // assign register number for precolored intervals
 293   if (reg_num < LIR_OprDesc::vreg_base) {
 294     interval->assign_reg(reg_num);
 295   }
 296   return interval;
 297 }
 298 
 299 // assign a new reg_num to the interval and append it to the list of intervals
 300 // (only used for child intervals that are created during register allocation)
 301 void LinearScan::append_interval(Interval* it) {
 302   it->set_reg_num(_intervals.length());
 303   _intervals.append(it);
 304   _new_intervals_from_allocation->append(it);
 305 }
 306 
 307 // copy the vreg-flags if an interval is split
 308 void LinearScan::copy_register_flags(Interval* from, Interval* to) {
 309   if (gen()->is_vreg_flag_set(from->reg_num(), LIRGenerator::byte_reg)) {
 310     gen()->set_vreg_flag(to->reg_num(), LIRGenerator::byte_reg);
 311   }
 312   if (gen()->is_vreg_flag_set(from->reg_num(), LIRGenerator::callee_saved)) {
 313     gen()->set_vreg_flag(to->reg_num(), LIRGenerator::callee_saved);
 314   }
 315 
 316   // Note: do not copy the must_start_in_memory flag because it is not necessary for child
 317   //       intervals (only the very beginning of the interval must be in memory)
 318 }
 319 
 320 
 321 // ********** spill move optimization
 322 // eliminate moves from register to stack if stack slot is known to be correct
 323 
 324 // called during building of intervals
 325 void LinearScan::change_spill_definition_pos(Interval* interval, int def_pos) {
 326   assert(interval->is_split_parent(), "can only be called for split parents");
 327 
 328   switch (interval->spill_state()) {
 329     case noDefinitionFound:
 330       assert(interval->spill_definition_pos() == -1, "must no be set before");
 331       interval->set_spill_definition_pos(def_pos);
 332       interval->set_spill_state(oneDefinitionFound);
 333       break;
 334 
 335     case oneDefinitionFound:
 336       assert(def_pos <= interval->spill_definition_pos(), "positions are processed in reverse order when intervals are created");
 337       if (def_pos < interval->spill_definition_pos() - 2) {
 338         // second definition found, so no spill optimization possible for this interval
 339         interval->set_spill_state(noOptimization);
 340       } else {
 341         // two consecutive definitions (because of two-operand LIR form)
 342         assert(block_of_op_with_id(def_pos) == block_of_op_with_id(interval->spill_definition_pos()), "block must be equal");
 343       }
 344       break;
 345 
 346     case noOptimization:
 347       // nothing to do
 348       break;
 349 
 350     default:
 351       assert(false, "other states not allowed at this time");
 352   }
 353 }
 354 
 355 // called during register allocation
 356 void LinearScan::change_spill_state(Interval* interval, int spill_pos) {
 357   switch (interval->spill_state()) {
 358     case oneDefinitionFound: {
 359       int def_loop_depth = block_of_op_with_id(interval->spill_definition_pos())->loop_depth();
 360       int spill_loop_depth = block_of_op_with_id(spill_pos)->loop_depth();
 361 
 362       if (def_loop_depth < spill_loop_depth) {
 363         // the loop depth of the spilling position is higher then the loop depth
 364         // at the definition of the interval -> move write to memory out of loop
 365         // by storing at definitin of the interval
 366         interval->set_spill_state(storeAtDefinition);
 367       } else {
 368         // the interval is currently spilled only once, so for now there is no
 369         // reason to store the interval at the definition
 370         interval->set_spill_state(oneMoveInserted);
 371       }
 372       break;
 373     }
 374 
 375     case oneMoveInserted: {
 376       // the interval is spilled more then once, so it is better to store it to
 377       // memory at the definition
 378       interval->set_spill_state(storeAtDefinition);
 379       break;
 380     }
 381 
 382     case storeAtDefinition:
 383     case startInMemory:
 384     case noOptimization:
 385     case noDefinitionFound:
 386       // nothing to do
 387       break;
 388 
 389     default:
 390       assert(false, "other states not allowed at this time");
 391   }
 392 }
 393 
 394 
 395 bool LinearScan::must_store_at_definition(const Interval* i) {
 396   return i->is_split_parent() && i->spill_state() == storeAtDefinition;
 397 }
 398 
 399 // called once before asignment of register numbers
 400 void LinearScan::eliminate_spill_moves() {
 401   TIME_LINEAR_SCAN(timer_eliminate_spill_moves);
 402   TRACE_LINEAR_SCAN(3, tty->print_cr("***** Eliminating unnecessary spill moves"));
 403 
 404   // collect all intervals that must be stored after their definion.
 405   // the list is sorted by Interval::spill_definition_pos
 406   Interval* interval;
 407   Interval* temp_list;
 408   create_unhandled_lists(&interval, &temp_list, must_store_at_definition, NULL);
 409 
 410 #ifdef ASSERT
 411   Interval* prev = NULL;
 412   Interval* temp = interval;
 413   while (temp != Interval::end()) {
 414     assert(temp->spill_definition_pos() > 0, "invalid spill definition pos");
 415     if (prev != NULL) {
 416       assert(temp->from() >= prev->from(), "intervals not sorted");
 417       assert(temp->spill_definition_pos() >= prev->spill_definition_pos(), "when intervals are sorted by from, then they must also be sorted by spill_definition_pos");
 418     }
 419 
 420     assert(temp->canonical_spill_slot() >= LinearScan::nof_regs, "interval has no spill slot assigned");
 421     assert(temp->spill_definition_pos() >= temp->from(), "invalid order");
 422     assert(temp->spill_definition_pos() <= temp->from() + 2, "only intervals defined once at their start-pos can be optimized");
 423 
 424     TRACE_LINEAR_SCAN(4, tty->print_cr("interval %d (from %d to %d) must be stored at %d", temp->reg_num(), temp->from(), temp->to(), temp->spill_definition_pos()));
 425 
 426     temp = temp->next();
 427   }
 428 #endif
 429 
 430   LIR_InsertionBuffer insertion_buffer;
 431   int num_blocks = block_count();
 432   for (int i = 0; i < num_blocks; i++) {
 433     BlockBegin* block = block_at(i);
 434     LIR_OpList* instructions = block->lir()->instructions_list();
 435     int         num_inst = instructions->length();
 436     bool        has_new = false;
 437 
 438     // iterate all instructions of the block. skip the first because it is always a label
 439     for (int j = 1; j < num_inst; j++) {
 440       LIR_Op* op = instructions->at(j);
 441       int op_id = op->id();
 442 
 443       if (op_id == -1) {
 444         // remove move from register to stack if the stack slot is guaranteed to be correct.
 445         // only moves that have been inserted by LinearScan can be removed.
 446         assert(op->code() == lir_move, "only moves can have a op_id of -1");
 447         assert(op->as_Op1() != NULL, "move must be LIR_Op1");
 448         assert(op->as_Op1()->result_opr()->is_virtual(), "LinearScan inserts only moves to virtual registers");
 449 
 450         LIR_Op1* op1 = (LIR_Op1*)op;
 451         Interval* interval = interval_at(op1->result_opr()->vreg_number());
 452 
 453         if (interval->assigned_reg() >= LinearScan::nof_regs && interval->always_in_memory()) {
 454           // move target is a stack slot that is always correct, so eliminate instruction
 455           TRACE_LINEAR_SCAN(4, tty->print_cr("eliminating move from interval %d to %d", op1->in_opr()->vreg_number(), op1->result_opr()->vreg_number()));
 456           instructions->at_put(j, NULL); // NULL-instructions are deleted by assign_reg_num
 457         }
 458 
 459       } else {
 460         // insert move from register to stack just after the beginning of the interval
 461         assert(interval == Interval::end() || interval->spill_definition_pos() >= op_id, "invalid order");
 462         assert(interval == Interval::end() || (interval->is_split_parent() && interval->spill_state() == storeAtDefinition), "invalid interval");
 463 
 464         while (interval != Interval::end() && interval->spill_definition_pos() == op_id) {
 465           if (!has_new) {
 466             // prepare insertion buffer (appended when all instructions of the block are processed)
 467             insertion_buffer.init(block->lir());
 468             has_new = true;
 469           }
 470 
 471           LIR_Opr from_opr = operand_for_interval(interval);
 472           LIR_Opr to_opr = canonical_spill_opr(interval);
 473           assert(from_opr->is_fixed_cpu() || from_opr->is_fixed_fpu(), "from operand must be a register");
 474           assert(to_opr->is_stack(), "to operand must be a stack slot");
 475 
 476           insertion_buffer.move(j, from_opr, to_opr);
 477           TRACE_LINEAR_SCAN(4, tty->print_cr("inserting move after definition of interval %d to stack slot %d at op_id %d", interval->reg_num(), interval->canonical_spill_slot() - LinearScan::nof_regs, op_id));
 478 
 479           interval = interval->next();
 480         }
 481       }
 482     } // end of instruction iteration
 483 
 484     if (has_new) {
 485       block->lir()->append(&insertion_buffer);
 486     }
 487   } // end of block iteration
 488 
 489   assert(interval == Interval::end(), "missed an interval");
 490 }
 491 
 492 
 493 // ********** Phase 1: number all instructions in all blocks
 494 // Compute depth-first and linear scan block orders, and number LIR_Op nodes for linear scan.
 495 
 496 void LinearScan::number_instructions() {
 497   {
 498     // dummy-timer to measure the cost of the timer itself
 499     // (this time is then subtracted from all other timers to get the real value)
 500     TIME_LINEAR_SCAN(timer_do_nothing);
 501   }
 502   TIME_LINEAR_SCAN(timer_number_instructions);
 503 
 504   // Assign IDs to LIR nodes and build a mapping, lir_ops, from ID to LIR_Op node.
 505   int num_blocks = block_count();
 506   int num_instructions = 0;
 507   int i;
 508   for (i = 0; i < num_blocks; i++) {
 509     num_instructions += block_at(i)->lir()->instructions_list()->length();
 510   }
 511 
 512   // initialize with correct length
 513   _lir_ops = LIR_OpArray(num_instructions);
 514   _block_of_op = BlockBeginArray(num_instructions);
 515 
 516   int op_id = 0;
 517   int idx = 0;
 518 
 519   for (i = 0; i < num_blocks; i++) {
 520     BlockBegin* block = block_at(i);
 521     block->set_first_lir_instruction_id(op_id);
 522     LIR_OpList* instructions = block->lir()->instructions_list();
 523 
 524     int num_inst = instructions->length();
 525     for (int j = 0; j < num_inst; j++) {
 526       LIR_Op* op = instructions->at(j);
 527       op->set_id(op_id);
 528 
 529       _lir_ops.at_put(idx, op);
 530       _block_of_op.at_put(idx, block);
 531       assert(lir_op_with_id(op_id) == op, "must match");
 532 
 533       idx++;
 534       op_id += 2; // numbering of lir_ops by two
 535     }
 536     block->set_last_lir_instruction_id(op_id - 2);
 537   }
 538   assert(idx == num_instructions, "must match");
 539   assert(idx * 2 == op_id, "must match");
 540 
 541   _has_call = BitMap(num_instructions); _has_call.clear();
 542   _has_info = BitMap(num_instructions); _has_info.clear();
 543 }
 544 
 545 
 546 // ********** Phase 2: compute local live sets separately for each block
 547 // (sets live_gen and live_kill for each block)
 548 
 549 void LinearScan::set_live_gen_kill(Value value, LIR_Op* op, BitMap& live_gen, BitMap& live_kill) {
 550   LIR_Opr opr = value->operand();
 551   Constant* con = value->as_Constant();
 552 
 553   // check some asumptions about debug information
 554   assert(!value->type()->is_illegal(), "if this local is used by the interpreter it shouldn't be of indeterminate type");
 555   assert(con == NULL || opr->is_virtual() || opr->is_constant() || opr->is_illegal(), "asumption: Constant instructions have only constant operands");
 556   assert(con != NULL || opr->is_virtual(), "asumption: non-Constant instructions have only virtual operands");
 557 
 558   if ((con == NULL || con->is_pinned()) && opr->is_register()) {
 559     assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 560     int reg = opr->vreg_number();
 561     if (!live_kill.at(reg)) {
 562       live_gen.set_bit(reg);
 563       TRACE_LINEAR_SCAN(4, tty->print_cr("  Setting live_gen for value %c%d, LIR op_id %d, register number %d", value->type()->tchar(), value->id(), op->id(), reg));
 564     }
 565   }
 566 }
 567 
 568 
 569 void LinearScan::compute_local_live_sets() {
 570   TIME_LINEAR_SCAN(timer_compute_local_live_sets);
 571 
 572   int  num_blocks = block_count();
 573   int  live_size = live_set_size();
 574   bool local_has_fpu_registers = false;
 575   int  local_num_calls = 0;
 576   LIR_OpVisitState visitor;
 577 
 578   BitMap2D local_interval_in_loop = BitMap2D(_num_virtual_regs, num_loops());
 579   local_interval_in_loop.clear();
 580 
 581   // iterate all blocks
 582   for (int i = 0; i < num_blocks; i++) {
 583     BlockBegin* block = block_at(i);
 584 
 585     BitMap live_gen(live_size);  live_gen.clear();
 586     BitMap live_kill(live_size); live_kill.clear();
 587 
 588     if (block->is_set(BlockBegin::exception_entry_flag)) {
 589       // Phi functions at the begin of an exception handler are
 590       // implicitly defined (= killed) at the beginning of the block.
 591       for_each_phi_fun(block, phi,
 592         live_kill.set_bit(phi->operand()->vreg_number())
 593       );
 594     }
 595 
 596     LIR_OpList* instructions = block->lir()->instructions_list();
 597     int num_inst = instructions->length();
 598 
 599     // iterate all instructions of the block. skip the first because it is always a label
 600     assert(visitor.no_operands(instructions->at(0)), "first operation must always be a label");
 601     for (int j = 1; j < num_inst; j++) {
 602       LIR_Op* op = instructions->at(j);
 603 
 604       // visit operation to collect all operands
 605       visitor.visit(op);
 606 
 607       if (visitor.has_call()) {
 608         _has_call.set_bit(op->id() >> 1);
 609         local_num_calls++;
 610       }
 611       if (visitor.info_count() > 0) {
 612         _has_info.set_bit(op->id() >> 1);
 613       }
 614 
 615       // iterate input operands of instruction
 616       int k, n, reg;
 617       n = visitor.opr_count(LIR_OpVisitState::inputMode);
 618       for (k = 0; k < n; k++) {
 619         LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, k);
 620         assert(opr->is_register(), "visitor should only return register operands");
 621 
 622         if (opr->is_virtual_register()) {
 623           assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 624           reg = opr->vreg_number();
 625           if (!live_kill.at(reg)) {
 626             live_gen.set_bit(reg);
 627             TRACE_LINEAR_SCAN(4, tty->print_cr("  Setting live_gen for register %d at instruction %d", reg, op->id()));
 628           }
 629           if (block->loop_index() >= 0) {
 630             local_interval_in_loop.set_bit(reg, block->loop_index());
 631           }
 632           local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu();
 633         }
 634 
 635 #ifdef ASSERT
 636         // fixed intervals are never live at block boundaries, so
 637         // they need not be processed in live sets.
 638         // this is checked by these assertions to be sure about it.
 639         // the entry block may have incoming values in registers, which is ok.
 640         if (!opr->is_virtual_register() && block != ir()->start()) {
 641           reg = reg_num(opr);
 642           if (is_processed_reg_num(reg)) {
 643             assert(live_kill.at(reg), "using fixed register that is not defined in this block");
 644           }
 645           reg = reg_numHi(opr);
 646           if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
 647             assert(live_kill.at(reg), "using fixed register that is not defined in this block");
 648           }
 649         }
 650 #endif
 651       }
 652 
 653       // Add uses of live locals from interpreter's point of view for proper debug information generation
 654       n = visitor.info_count();
 655       for (k = 0; k < n; k++) {
 656         CodeEmitInfo* info = visitor.info_at(k);
 657         ValueStack* stack = info->stack();
 658         for_each_state_value(stack, value,
 659           set_live_gen_kill(value, op, live_gen, live_kill)
 660         );
 661       }
 662 
 663       // iterate temp operands of instruction
 664       n = visitor.opr_count(LIR_OpVisitState::tempMode);
 665       for (k = 0; k < n; k++) {
 666         LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, k);
 667         assert(opr->is_register(), "visitor should only return register operands");
 668 
 669         if (opr->is_virtual_register()) {
 670           assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 671           reg = opr->vreg_number();
 672           live_kill.set_bit(reg);
 673           if (block->loop_index() >= 0) {
 674             local_interval_in_loop.set_bit(reg, block->loop_index());
 675           }
 676           local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu();
 677         }
 678 
 679 #ifdef ASSERT
 680         // fixed intervals are never live at block boundaries, so
 681         // they need not be processed in live sets
 682         // process them only in debug mode so that this can be checked
 683         if (!opr->is_virtual_register()) {
 684           reg = reg_num(opr);
 685           if (is_processed_reg_num(reg)) {
 686             live_kill.set_bit(reg_num(opr));
 687           }
 688           reg = reg_numHi(opr);
 689           if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
 690             live_kill.set_bit(reg);
 691           }
 692         }
 693 #endif
 694       }
 695 
 696       // iterate output operands of instruction
 697       n = visitor.opr_count(LIR_OpVisitState::outputMode);
 698       for (k = 0; k < n; k++) {
 699         LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, k);
 700         assert(opr->is_register(), "visitor should only return register operands");
 701 
 702         if (opr->is_virtual_register()) {
 703           assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 704           reg = opr->vreg_number();
 705           live_kill.set_bit(reg);
 706           if (block->loop_index() >= 0) {
 707             local_interval_in_loop.set_bit(reg, block->loop_index());
 708           }
 709           local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu();
 710         }
 711 
 712 #ifdef ASSERT
 713         // fixed intervals are never live at block boundaries, so
 714         // they need not be processed in live sets
 715         // process them only in debug mode so that this can be checked
 716         if (!opr->is_virtual_register()) {
 717           reg = reg_num(opr);
 718           if (is_processed_reg_num(reg)) {
 719             live_kill.set_bit(reg_num(opr));
 720           }
 721           reg = reg_numHi(opr);
 722           if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
 723             live_kill.set_bit(reg);
 724           }
 725         }
 726 #endif
 727       }
 728     } // end of instruction iteration
 729 
 730     block->set_live_gen (live_gen);
 731     block->set_live_kill(live_kill);
 732     block->set_live_in  (BitMap(live_size)); block->live_in().clear();
 733     block->set_live_out (BitMap(live_size)); block->live_out().clear();
 734 
 735     TRACE_LINEAR_SCAN(4, tty->print("live_gen  B%d ", block->block_id()); print_bitmap(block->live_gen()));
 736     TRACE_LINEAR_SCAN(4, tty->print("live_kill B%d ", block->block_id()); print_bitmap(block->live_kill()));
 737   } // end of block iteration
 738 
 739   // propagate local calculated information into LinearScan object
 740   _has_fpu_registers = local_has_fpu_registers;
 741   compilation()->set_has_fpu_code(local_has_fpu_registers);
 742 
 743   _num_calls = local_num_calls;
 744   _interval_in_loop = local_interval_in_loop;
 745 }
 746 
 747 
 748 // ********** Phase 3: perform a backward dataflow analysis to compute global live sets
 749 // (sets live_in and live_out for each block)
 750 
 751 void LinearScan::compute_global_live_sets() {
 752   TIME_LINEAR_SCAN(timer_compute_global_live_sets);
 753 
 754   int  num_blocks = block_count();
 755   bool change_occurred;
 756   bool change_occurred_in_block;
 757   int  iteration_count = 0;
 758   BitMap live_out(live_set_size()); live_out.clear(); // scratch set for calculations
 759 
 760   // Perform a backward dataflow analysis to compute live_out and live_in for each block.
 761   // The loop is executed until a fixpoint is reached (no changes in an iteration)
 762   // Exception handlers must be processed because not all live values are
 763   // present in the state array, e.g. because of global value numbering
 764   do {
 765     change_occurred = false;
 766 
 767     // iterate all blocks in reverse order
 768     for (int i = num_blocks - 1; i >= 0; i--) {
 769       BlockBegin* block = block_at(i);
 770 
 771       change_occurred_in_block = false;
 772 
 773       // live_out(block) is the union of live_in(sux), for successors sux of block
 774       int n = block->number_of_sux();
 775       int e = block->number_of_exception_handlers();
 776       if (n + e > 0) {
 777         // block has successors
 778         if (n > 0) {
 779           live_out.set_from(block->sux_at(0)->live_in());
 780           for (int j = 1; j < n; j++) {
 781             live_out.set_union(block->sux_at(j)->live_in());
 782           }
 783         } else {
 784           live_out.clear();
 785         }
 786         for (int j = 0; j < e; j++) {
 787           live_out.set_union(block->exception_handler_at(j)->live_in());
 788         }
 789 
 790         if (!block->live_out().is_same(live_out)) {
 791           // A change occurred.  Swap the old and new live out sets to avoid copying.
 792           BitMap temp = block->live_out();
 793           block->set_live_out(live_out);
 794           live_out = temp;
 795 
 796           change_occurred = true;
 797           change_occurred_in_block = true;
 798         }
 799       }
 800 
 801       if (iteration_count == 0 || change_occurred_in_block) {
 802         // live_in(block) is the union of live_gen(block) with (live_out(block) & !live_kill(block))
 803         // note: live_in has to be computed only in first iteration or if live_out has changed!
 804         BitMap live_in = block->live_in();
 805         live_in.set_from(block->live_out());
 806         live_in.set_difference(block->live_kill());
 807         live_in.set_union(block->live_gen());
 808       }
 809 
 810 #ifndef PRODUCT
 811       if (TraceLinearScanLevel >= 4) {
 812         char c = ' ';
 813         if (iteration_count == 0 || change_occurred_in_block) {
 814           c = '*';
 815         }
 816         tty->print("(%d) live_in%c  B%d ", iteration_count, c, block->block_id()); print_bitmap(block->live_in());
 817         tty->print("(%d) live_out%c B%d ", iteration_count, c, block->block_id()); print_bitmap(block->live_out());
 818       }
 819 #endif
 820     }
 821     iteration_count++;
 822 
 823     if (change_occurred && iteration_count > 50) {
 824       BAILOUT("too many iterations in compute_global_live_sets");
 825     }
 826   } while (change_occurred);
 827 
 828 
 829 #ifdef ASSERT
 830   // check that fixed intervals are not live at block boundaries
 831   // (live set must be empty at fixed intervals)
 832   for (int i = 0; i < num_blocks; i++) {
 833     BlockBegin* block = block_at(i);
 834     for (int j = 0; j < LIR_OprDesc::vreg_base; j++) {
 835       assert(block->live_in().at(j)  == false, "live_in  set of fixed register must be empty");
 836       assert(block->live_out().at(j) == false, "live_out set of fixed register must be empty");
 837       assert(block->live_gen().at(j) == false, "live_gen set of fixed register must be empty");
 838     }
 839   }
 840 #endif
 841 
 842   // check that the live_in set of the first block is empty
 843   BitMap live_in_args(ir()->start()->live_in().size());
 844   live_in_args.clear();
 845   if (!ir()->start()->live_in().is_same(live_in_args)) {
 846 #ifdef ASSERT
 847     tty->print_cr("Error: live_in set of first block must be empty (when this fails, virtual registers are used before they are defined)");
 848     tty->print_cr("affected registers:");
 849     print_bitmap(ir()->start()->live_in());
 850 
 851     // print some additional information to simplify debugging
 852     for (unsigned int i = 0; i < ir()->start()->live_in().size(); i++) {
 853       if (ir()->start()->live_in().at(i)) {
 854         Instruction* instr = gen()->instruction_for_vreg(i);
 855         tty->print_cr("* vreg %d (HIR instruction %c%d)", i, instr == NULL ? ' ' : instr->type()->tchar(), instr == NULL ? 0 : instr->id());
 856 
 857         for (int j = 0; j < num_blocks; j++) {
 858           BlockBegin* block = block_at(j);
 859           if (block->live_gen().at(i)) {
 860             tty->print_cr("  used in block B%d", block->block_id());
 861           }
 862           if (block->live_kill().at(i)) {
 863             tty->print_cr("  defined in block B%d", block->block_id());
 864           }
 865         }
 866       }
 867     }
 868 
 869 #endif
 870     // when this fails, virtual registers are used before they are defined.
 871     assert(false, "live_in set of first block must be empty");
 872     // bailout of if this occurs in product mode.
 873     bailout("live_in set of first block not empty");
 874   }
 875 }
 876 
 877 
 878 // ********** Phase 4: build intervals
 879 // (fills the list _intervals)
 880 
 881 void LinearScan::add_use(Value value, int from, int to, IntervalUseKind use_kind) {
 882   assert(!value->type()->is_illegal(), "if this value is used by the interpreter it shouldn't be of indeterminate type");
 883   LIR_Opr opr = value->operand();
 884   Constant* con = value->as_Constant();
 885 
 886   if ((con == NULL || con->is_pinned()) && opr->is_register()) {
 887     assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 888     add_use(opr, from, to, use_kind);
 889   }
 890 }
 891 
 892 
 893 void LinearScan::add_def(LIR_Opr opr, int def_pos, IntervalUseKind use_kind) {
 894   TRACE_LINEAR_SCAN(2, tty->print(" def "); opr->print(tty); tty->print_cr(" def_pos %d (%d)", def_pos, use_kind));
 895   assert(opr->is_register(), "should not be called otherwise");
 896 
 897   if (opr->is_virtual_register()) {
 898     assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 899     add_def(opr->vreg_number(), def_pos, use_kind, opr->type_register());
 900 
 901   } else {
 902     int reg = reg_num(opr);
 903     if (is_processed_reg_num(reg)) {
 904       add_def(reg, def_pos, use_kind, opr->type_register());
 905     }
 906     reg = reg_numHi(opr);
 907     if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
 908       add_def(reg, def_pos, use_kind, opr->type_register());
 909     }
 910   }
 911 }
 912 
 913 void LinearScan::add_use(LIR_Opr opr, int from, int to, IntervalUseKind use_kind) {
 914   TRACE_LINEAR_SCAN(2, tty->print(" use "); opr->print(tty); tty->print_cr(" from %d to %d (%d)", from, to, use_kind));
 915   assert(opr->is_register(), "should not be called otherwise");
 916 
 917   if (opr->is_virtual_register()) {
 918     assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 919     add_use(opr->vreg_number(), from, to, use_kind, opr->type_register());
 920 
 921   } else {
 922     int reg = reg_num(opr);
 923     if (is_processed_reg_num(reg)) {
 924       add_use(reg, from, to, use_kind, opr->type_register());
 925     }
 926     reg = reg_numHi(opr);
 927     if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
 928       add_use(reg, from, to, use_kind, opr->type_register());
 929     }
 930   }
 931 }
 932 
 933 void LinearScan::add_temp(LIR_Opr opr, int temp_pos, IntervalUseKind use_kind) {
 934   TRACE_LINEAR_SCAN(2, tty->print(" temp "); opr->print(tty); tty->print_cr(" temp_pos %d (%d)", temp_pos, use_kind));
 935   assert(opr->is_register(), "should not be called otherwise");
 936 
 937   if (opr->is_virtual_register()) {
 938     assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 939     add_temp(opr->vreg_number(), temp_pos, use_kind, opr->type_register());
 940 
 941   } else {
 942     int reg = reg_num(opr);
 943     if (is_processed_reg_num(reg)) {
 944       add_temp(reg, temp_pos, use_kind, opr->type_register());
 945     }
 946     reg = reg_numHi(opr);
 947     if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
 948       add_temp(reg, temp_pos, use_kind, opr->type_register());
 949     }
 950   }
 951 }
 952 
 953 
 954 void LinearScan::add_def(int reg_num, int def_pos, IntervalUseKind use_kind, BasicType type) {
 955   Interval* interval = interval_at(reg_num);
 956   if (interval != NULL) {
 957     assert(interval->reg_num() == reg_num, "wrong interval");
 958 
 959     if (type != T_ILLEGAL) {
 960       interval->set_type(type);
 961     }
 962 
 963     Range* r = interval->first();
 964     if (r->from() <= def_pos) {
 965       // Update the starting point (when a range is first created for a use, its
 966       // start is the beginning of the current block until a def is encountered.)
 967       r->set_from(def_pos);
 968       interval->add_use_pos(def_pos, use_kind);
 969 
 970     } else {
 971       // Dead value - make vacuous interval
 972       // also add use_kind for dead intervals
 973       interval->add_range(def_pos, def_pos + 1);
 974       interval->add_use_pos(def_pos, use_kind);
 975       TRACE_LINEAR_SCAN(2, tty->print_cr("Warning: def of reg %d at %d occurs without use", reg_num, def_pos));
 976     }
 977 
 978   } else {
 979     // Dead value - make vacuous interval
 980     // also add use_kind for dead intervals
 981     interval = create_interval(reg_num);
 982     if (type != T_ILLEGAL) {
 983       interval->set_type(type);
 984     }
 985 
 986     interval->add_range(def_pos, def_pos + 1);
 987     interval->add_use_pos(def_pos, use_kind);
 988     TRACE_LINEAR_SCAN(2, tty->print_cr("Warning: dead value %d at %d in live intervals", reg_num, def_pos));
 989   }
 990 
 991   change_spill_definition_pos(interval, def_pos);
 992   if (use_kind == noUse && interval->spill_state() <= startInMemory) {
 993         // detection of method-parameters and roundfp-results
 994         // TODO: move this directly to position where use-kind is computed
 995     interval->set_spill_state(startInMemory);
 996   }
 997 }
 998 
 999 void LinearScan::add_use(int reg_num, int from, int to, IntervalUseKind use_kind, BasicType type) {
1000   Interval* interval = interval_at(reg_num);
1001   if (interval == NULL) {
1002     interval = create_interval(reg_num);
1003   }
1004   assert(interval->reg_num() == reg_num, "wrong interval");
1005 
1006   if (type != T_ILLEGAL) {
1007     interval->set_type(type);
1008   }
1009 
1010   interval->add_range(from, to);
1011   interval->add_use_pos(to, use_kind);
1012 }
1013 
1014 void LinearScan::add_temp(int reg_num, int temp_pos, IntervalUseKind use_kind, BasicType type) {
1015   Interval* interval = interval_at(reg_num);
1016   if (interval == NULL) {
1017     interval = create_interval(reg_num);
1018   }
1019   assert(interval->reg_num() == reg_num, "wrong interval");
1020 
1021   if (type != T_ILLEGAL) {
1022     interval->set_type(type);
1023   }
1024 
1025   interval->add_range(temp_pos, temp_pos + 1);
1026   interval->add_use_pos(temp_pos, use_kind);
1027 }
1028 
1029 
1030 // the results of this functions are used for optimizing spilling and reloading
1031 // if the functions return shouldHaveRegister and the interval is spilled,
1032 // it is not reloaded to a register.
1033 IntervalUseKind LinearScan::use_kind_of_output_operand(LIR_Op* op, LIR_Opr opr) {
1034   if (op->code() == lir_move) {
1035     assert(op->as_Op1() != NULL, "lir_move must be LIR_Op1");
1036     LIR_Op1* move = (LIR_Op1*)op;
1037     LIR_Opr res = move->result_opr();
1038     bool result_in_memory = res->is_virtual() && gen()->is_vreg_flag_set(res->vreg_number(), LIRGenerator::must_start_in_memory);
1039 
1040     if (result_in_memory) {
1041       // Begin of an interval with must_start_in_memory set.
1042       // This interval will always get a stack slot first, so return noUse.
1043       return noUse;
1044 
1045     } else if (move->in_opr()->is_stack()) {
1046       // method argument (condition must be equal to handle_method_arguments)
1047       return noUse;
1048 
1049     } else if (move->in_opr()->is_register() && move->result_opr()->is_register()) {
1050       // Move from register to register
1051       if (block_of_op_with_id(op->id())->is_set(BlockBegin::osr_entry_flag)) {
1052         // special handling of phi-function moves inside osr-entry blocks
1053         // input operand must have a register instead of output operand (leads to better register allocation)
1054         return shouldHaveRegister;
1055       }
1056     }
1057   }
1058 
1059   if (opr->is_virtual() &&
1060       gen()->is_vreg_flag_set(opr->vreg_number(), LIRGenerator::must_start_in_memory)) {
1061     // result is a stack-slot, so prevent immediate reloading
1062     return noUse;
1063   }
1064 
1065   // all other operands require a register
1066   return mustHaveRegister;
1067 }
1068 
1069 IntervalUseKind LinearScan::use_kind_of_input_operand(LIR_Op* op, LIR_Opr opr) {
1070   if (op->code() == lir_move) {
1071     assert(op->as_Op1() != NULL, "lir_move must be LIR_Op1");
1072     LIR_Op1* move = (LIR_Op1*)op;
1073     LIR_Opr res = move->result_opr();
1074     bool result_in_memory = res->is_virtual() && gen()->is_vreg_flag_set(res->vreg_number(), LIRGenerator::must_start_in_memory);
1075 
1076     if (result_in_memory) {
1077       // Move to an interval with must_start_in_memory set.
1078       // To avoid moves from stack to stack (not allowed) force the input operand to a register
1079       return mustHaveRegister;
1080 
1081     } else if (move->in_opr()->is_register() && move->result_opr()->is_register()) {
1082       // Move from register to register
1083       if (block_of_op_with_id(op->id())->is_set(BlockBegin::osr_entry_flag)) {
1084         // special handling of phi-function moves inside osr-entry blocks
1085         // input operand must have a register instead of output operand (leads to better register allocation)
1086         return mustHaveRegister;
1087       }
1088 
1089       // The input operand is not forced to a register (moves from stack to register are allowed),
1090       // but it is faster if the input operand is in a register
1091       return shouldHaveRegister;
1092     }
1093   }
1094 
1095 
1096 #ifdef X86
1097   if (op->code() == lir_cmove) {
1098     // conditional moves can handle stack operands
1099     assert(op->result_opr()->is_register(), "result must always be in a register");
1100     return shouldHaveRegister;
1101   }
1102 
1103   // optimizations for second input operand of arithmehtic operations on Intel
1104   // this operand is allowed to be on the stack in some cases
1105   BasicType opr_type = opr->type_register();
1106   if (opr_type == T_FLOAT || opr_type == T_DOUBLE) {
1107     if ((UseSSE == 1 && opr_type == T_FLOAT) || UseSSE >= 2) {
1108       // SSE float instruction (T_DOUBLE only supported with SSE2)
1109       switch (op->code()) {
1110         case lir_cmp:
1111         case lir_add:
1112         case lir_sub:
1113         case lir_mul:
1114         case lir_div:
1115         {
1116           assert(op->as_Op2() != NULL, "must be LIR_Op2");
1117           LIR_Op2* op2 = (LIR_Op2*)op;
1118           if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
1119             assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
1120             return shouldHaveRegister;
1121           }
1122         }
1123       }
1124     } else {
1125       // FPU stack float instruction
1126       switch (op->code()) {
1127         case lir_add:
1128         case lir_sub:
1129         case lir_mul:
1130         case lir_div:
1131         {
1132           assert(op->as_Op2() != NULL, "must be LIR_Op2");
1133           LIR_Op2* op2 = (LIR_Op2*)op;
1134           if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
1135             assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
1136             return shouldHaveRegister;
1137           }
1138         }
1139       }
1140     }
1141 
1142   } else if (opr_type != T_LONG) {
1143     // integer instruction (note: long operands must always be in register)
1144     switch (op->code()) {
1145       case lir_cmp:
1146       case lir_add:
1147       case lir_sub:
1148       case lir_logic_and:
1149       case lir_logic_or:
1150       case lir_logic_xor:
1151       {
1152         assert(op->as_Op2() != NULL, "must be LIR_Op2");
1153         LIR_Op2* op2 = (LIR_Op2*)op;
1154         if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
1155           assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
1156           return shouldHaveRegister;
1157         }
1158       }
1159     }
1160   }
1161 #endif // X86
1162 
1163   // all other operands require a register
1164   return mustHaveRegister;
1165 }
1166 
1167 
1168 void LinearScan::handle_method_arguments(LIR_Op* op) {
1169   // special handling for method arguments (moves from stack to virtual register):
1170   // the interval gets no register assigned, but the stack slot.
1171   // it is split before the first use by the register allocator.
1172 
1173   if (op->code() == lir_move) {
1174     assert(op->as_Op1() != NULL, "must be LIR_Op1");
1175     LIR_Op1* move = (LIR_Op1*)op;
1176 
1177     if (move->in_opr()->is_stack()) {
1178 #ifdef ASSERT
1179       int arg_size = compilation()->method()->arg_size();
1180       LIR_Opr o = move->in_opr();
1181       if (o->is_single_stack()) {
1182         assert(o->single_stack_ix() >= 0 && o->single_stack_ix() < arg_size, "out of range");
1183       } else if (o->is_double_stack()) {
1184         assert(o->double_stack_ix() >= 0 && o->double_stack_ix() < arg_size, "out of range");
1185       } else {
1186         ShouldNotReachHere();
1187       }
1188 
1189       assert(move->id() > 0, "invalid id");
1190       assert(block_of_op_with_id(move->id())->number_of_preds() == 0, "move from stack must be in first block");
1191       assert(move->result_opr()->is_virtual(), "result of move must be a virtual register");
1192 
1193       TRACE_LINEAR_SCAN(4, tty->print_cr("found move from stack slot %d to vreg %d", o->is_single_stack() ? o->single_stack_ix() : o->double_stack_ix(), reg_num(move->result_opr())));
1194 #endif
1195 
1196       Interval* interval = interval_at(reg_num(move->result_opr()));
1197 
1198       int stack_slot = LinearScan::nof_regs + (move->in_opr()->is_single_stack() ? move->in_opr()->single_stack_ix() : move->in_opr()->double_stack_ix());
1199       interval->set_canonical_spill_slot(stack_slot);
1200       interval->assign_reg(stack_slot);
1201     }
1202   }
1203 }
1204 
1205 void LinearScan::handle_doubleword_moves(LIR_Op* op) {
1206   // special handling for doubleword move from memory to register:
1207   // in this case the registers of the input address and the result
1208   // registers must not overlap -> add a temp range for the input registers
1209   if (op->code() == lir_move) {
1210     assert(op->as_Op1() != NULL, "must be LIR_Op1");
1211     LIR_Op1* move = (LIR_Op1*)op;
1212 
1213     if (move->result_opr()->is_double_cpu() && move->in_opr()->is_pointer()) {
1214       LIR_Address* address = move->in_opr()->as_address_ptr();
1215       if (address != NULL) {
1216         if (address->base()->is_valid()) {
1217           add_temp(address->base(), op->id(), noUse);
1218         }
1219         if (address->index()->is_valid()) {
1220           add_temp(address->index(), op->id(), noUse);
1221         }
1222       }
1223     }
1224   }
1225 }
1226 
1227 void LinearScan::add_register_hints(LIR_Op* op) {
1228   switch (op->code()) {
1229     case lir_move:      // fall through
1230     case lir_convert: {
1231       assert(op->as_Op1() != NULL, "lir_move, lir_convert must be LIR_Op1");
1232       LIR_Op1* move = (LIR_Op1*)op;
1233 
1234       LIR_Opr move_from = move->in_opr();
1235       LIR_Opr move_to = move->result_opr();
1236 
1237       if (move_to->is_register() && move_from->is_register()) {
1238         Interval* from = interval_at(reg_num(move_from));
1239         Interval* to = interval_at(reg_num(move_to));
1240         if (from != NULL && to != NULL) {
1241           to->set_register_hint(from);
1242           TRACE_LINEAR_SCAN(4, tty->print_cr("operation at op_id %d: added hint from interval %d to %d", move->id(), from->reg_num(), to->reg_num()));
1243         }
1244       }
1245       break;
1246     }
1247     case lir_cmove: {
1248       assert(op->as_Op2() != NULL, "lir_cmove must be LIR_Op2");
1249       LIR_Op2* cmove = (LIR_Op2*)op;
1250 
1251       LIR_Opr move_from = cmove->in_opr1();
1252       LIR_Opr move_to = cmove->result_opr();
1253 
1254       if (move_to->is_register() && move_from->is_register()) {
1255         Interval* from = interval_at(reg_num(move_from));
1256         Interval* to = interval_at(reg_num(move_to));
1257         if (from != NULL && to != NULL) {
1258           to->set_register_hint(from);
1259           TRACE_LINEAR_SCAN(4, tty->print_cr("operation at op_id %d: added hint from interval %d to %d", cmove->id(), from->reg_num(), to->reg_num()));
1260         }
1261       }
1262       break;
1263     }
1264   }
1265 }
1266 
1267 
1268 void LinearScan::build_intervals() {
1269   TIME_LINEAR_SCAN(timer_build_intervals);
1270 
1271   // initialize interval list with expected number of intervals
1272   // (32 is added to have some space for split children without having to resize the list)
1273   _intervals = IntervalList(num_virtual_regs() + 32);
1274   // initialize all slots that are used by build_intervals
1275   _intervals.at_put_grow(num_virtual_regs() - 1, NULL, NULL);
1276 
1277   // create a list with all caller-save registers (cpu, fpu, xmm)
1278   // when an instruction is a call, a temp range is created for all these registers
1279   int num_caller_save_registers = 0;
1280   int caller_save_registers[LinearScan::nof_regs];
1281 
1282   int i;
1283   for (i = 0; i < FrameMap::nof_caller_save_cpu_regs(); i++) {
1284     LIR_Opr opr = FrameMap::caller_save_cpu_reg_at(i);
1285     assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands");
1286     assert(reg_numHi(opr) == -1, "missing addition of range for hi-register");
1287     caller_save_registers[num_caller_save_registers++] = reg_num(opr);
1288   }
1289 
1290   // temp ranges for fpu registers are only created when the method has
1291   // virtual fpu operands. Otherwise no allocation for fpu registers is
1292   // perfomed and so the temp ranges would be useless
1293   if (has_fpu_registers()) {
1294 #ifdef X86
1295     if (UseSSE < 2) {
1296 #endif
1297       for (i = 0; i < FrameMap::nof_caller_save_fpu_regs; i++) {
1298         LIR_Opr opr = FrameMap::caller_save_fpu_reg_at(i);
1299         assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands");
1300         assert(reg_numHi(opr) == -1, "missing addition of range for hi-register");
1301         caller_save_registers[num_caller_save_registers++] = reg_num(opr);
1302       }
1303 #ifdef X86
1304     }
1305     if (UseSSE > 0) {
1306       for (i = 0; i < FrameMap::nof_caller_save_xmm_regs; i++) {
1307         LIR_Opr opr = FrameMap::caller_save_xmm_reg_at(i);
1308         assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands");
1309         assert(reg_numHi(opr) == -1, "missing addition of range for hi-register");
1310         caller_save_registers[num_caller_save_registers++] = reg_num(opr);
1311       }
1312     }
1313 #endif
1314   }
1315   assert(num_caller_save_registers <= LinearScan::nof_regs, "out of bounds");
1316 
1317 
1318   LIR_OpVisitState visitor;
1319 
1320   // iterate all blocks in reverse order
1321   for (i = block_count() - 1; i >= 0; i--) {
1322     BlockBegin* block = block_at(i);
1323     LIR_OpList* instructions = block->lir()->instructions_list();
1324     int         block_from =   block->first_lir_instruction_id();
1325     int         block_to =     block->last_lir_instruction_id();
1326 
1327     assert(block_from == instructions->at(0)->id(), "must be");
1328     assert(block_to   == instructions->at(instructions->length() - 1)->id(), "must be");
1329 
1330     // Update intervals for registers live at the end of this block;
1331     BitMap live = block->live_out();
1332     int size = (int)live.size();
1333     for (int number = (int)live.get_next_one_offset(0, size); number < size; number = (int)live.get_next_one_offset(number + 1, size)) {
1334       assert(live.at(number), "should not stop here otherwise");
1335       assert(number >= LIR_OprDesc::vreg_base, "fixed intervals must not be live on block bounds");
1336       TRACE_LINEAR_SCAN(2, tty->print_cr("live in %d to %d", number, block_to + 2));
1337 
1338       add_use(number, block_from, block_to + 2, noUse, T_ILLEGAL);
1339 
1340       // add special use positions for loop-end blocks when the
1341       // interval is used anywhere inside this loop.  It's possible
1342       // that the block was part of a non-natural loop, so it might
1343       // have an invalid loop index.
1344       if (block->is_set(BlockBegin::linear_scan_loop_end_flag) &&
1345           block->loop_index() != -1 &&
1346           is_interval_in_loop(number, block->loop_index())) {
1347         interval_at(number)->add_use_pos(block_to + 1, loopEndMarker);
1348       }
1349     }
1350 
1351     // iterate all instructions of the block in reverse order.
1352     // skip the first instruction because it is always a label
1353     // definitions of intervals are processed before uses
1354     assert(visitor.no_operands(instructions->at(0)), "first operation must always be a label");
1355     for (int j = instructions->length() - 1; j >= 1; j--) {
1356       LIR_Op* op = instructions->at(j);
1357       int op_id = op->id();
1358 
1359       // visit operation to collect all operands
1360       visitor.visit(op);
1361 
1362       // add a temp range for each register if operation destroys caller-save registers
1363       if (visitor.has_call()) {
1364         for (int k = 0; k < num_caller_save_registers; k++) {
1365           add_temp(caller_save_registers[k], op_id, noUse, T_ILLEGAL);
1366         }
1367         TRACE_LINEAR_SCAN(4, tty->print_cr("operation destroys all caller-save registers"));
1368       }
1369 
1370       // Add any platform dependent temps
1371       pd_add_temps(op);
1372 
1373       // visit definitions (output and temp operands)
1374       int k, n;
1375       n = visitor.opr_count(LIR_OpVisitState::outputMode);
1376       for (k = 0; k < n; k++) {
1377         LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, k);
1378         assert(opr->is_register(), "visitor should only return register operands");
1379         add_def(opr, op_id, use_kind_of_output_operand(op, opr));
1380       }
1381 
1382       n = visitor.opr_count(LIR_OpVisitState::tempMode);
1383       for (k = 0; k < n; k++) {
1384         LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, k);
1385         assert(opr->is_register(), "visitor should only return register operands");
1386         add_temp(opr, op_id, mustHaveRegister);
1387       }
1388 
1389       // visit uses (input operands)
1390       n = visitor.opr_count(LIR_OpVisitState::inputMode);
1391       for (k = 0; k < n; k++) {
1392         LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, k);
1393         assert(opr->is_register(), "visitor should only return register operands");
1394         add_use(opr, block_from, op_id, use_kind_of_input_operand(op, opr));
1395       }
1396 
1397       // Add uses of live locals from interpreter's point of view for proper
1398       // debug information generation
1399       // Treat these operands as temp values (if the life range is extended
1400       // to a call site, the value would be in a register at the call otherwise)
1401       n = visitor.info_count();
1402       for (k = 0; k < n; k++) {
1403         CodeEmitInfo* info = visitor.info_at(k);
1404         ValueStack* stack = info->stack();
1405         for_each_state_value(stack, value,
1406           add_use(value, block_from, op_id + 1, noUse);
1407         );
1408       }
1409 
1410       // special steps for some instructions (especially moves)
1411       handle_method_arguments(op);
1412       handle_doubleword_moves(op);
1413       add_register_hints(op);
1414 
1415     } // end of instruction iteration
1416   } // end of block iteration
1417 
1418 
1419   // add the range [0, 1[ to all fixed intervals
1420   // -> the register allocator need not handle unhandled fixed intervals
1421   for (int n = 0; n < LinearScan::nof_regs; n++) {
1422     Interval* interval = interval_at(n);
1423     if (interval != NULL) {
1424       interval->add_range(0, 1);
1425     }
1426   }
1427 }
1428 
1429 
1430 // ********** Phase 5: actual register allocation
1431 
1432 int LinearScan::interval_cmp(Interval** a, Interval** b) {
1433   if (*a != NULL) {
1434     if (*b != NULL) {
1435       return (*a)->from() - (*b)->from();
1436     } else {
1437       return -1;
1438     }
1439   } else {
1440     if (*b != NULL) {
1441       return 1;
1442     } else {
1443       return 0;
1444     }
1445   }
1446 }
1447 
1448 #ifndef PRODUCT
1449 bool LinearScan::is_sorted(IntervalArray* intervals) {
1450   int from = -1;
1451   int i, j;
1452   for (i = 0; i < intervals->length(); i ++) {
1453     Interval* it = intervals->at(i);
1454     if (it != NULL) {
1455       if (from > it->from()) {
1456         assert(false, "");
1457         return false;
1458       }
1459       from = it->from();
1460     }
1461   }
1462 
1463   // check in both directions if sorted list and unsorted list contain same intervals
1464   for (i = 0; i < interval_count(); i++) {
1465     if (interval_at(i) != NULL) {
1466       int num_found = 0;
1467       for (j = 0; j < intervals->length(); j++) {
1468         if (interval_at(i) == intervals->at(j)) {
1469           num_found++;
1470         }
1471       }
1472       assert(num_found == 1, "lists do not contain same intervals");
1473     }
1474   }
1475   for (j = 0; j < intervals->length(); j++) {
1476     int num_found = 0;
1477     for (i = 0; i < interval_count(); i++) {
1478       if (interval_at(i) == intervals->at(j)) {
1479         num_found++;
1480       }
1481     }
1482     assert(num_found == 1, "lists do not contain same intervals");
1483   }
1484 
1485   return true;
1486 }
1487 #endif
1488 
1489 void LinearScan::add_to_list(Interval** first, Interval** prev, Interval* interval) {
1490   if (*prev != NULL) {
1491     (*prev)->set_next(interval);
1492   } else {
1493     *first = interval;
1494   }
1495   *prev = interval;
1496 }
1497 
1498 void LinearScan::create_unhandled_lists(Interval** list1, Interval** list2, bool (is_list1)(const Interval* i), bool (is_list2)(const Interval* i)) {
1499   assert(is_sorted(_sorted_intervals), "interval list is not sorted");
1500 
1501   *list1 = *list2 = Interval::end();
1502 
1503   Interval* list1_prev = NULL;
1504   Interval* list2_prev = NULL;
1505   Interval* v;
1506 
1507   const int n = _sorted_intervals->length();
1508   for (int i = 0; i < n; i++) {
1509     v = _sorted_intervals->at(i);
1510     if (v == NULL) continue;
1511 
1512     if (is_list1(v)) {
1513       add_to_list(list1, &list1_prev, v);
1514     } else if (is_list2 == NULL || is_list2(v)) {
1515       add_to_list(list2, &list2_prev, v);
1516     }
1517   }
1518 
1519   if (list1_prev != NULL) list1_prev->set_next(Interval::end());
1520   if (list2_prev != NULL) list2_prev->set_next(Interval::end());
1521 
1522   assert(list1_prev == NULL || list1_prev->next() == Interval::end(), "linear list ends not with sentinel");
1523   assert(list2_prev == NULL || list2_prev->next() == Interval::end(), "linear list ends not with sentinel");
1524 }
1525 
1526 
1527 void LinearScan::sort_intervals_before_allocation() {
1528   TIME_LINEAR_SCAN(timer_sort_intervals_before);
1529 
1530   if (_needs_full_resort) {
1531     // There is no known reason why this should occur but just in case...
1532     assert(false, "should never occur");
1533     // Re-sort existing interval list because an Interval::from() has changed
1534     _sorted_intervals->sort(interval_cmp);
1535     _needs_full_resort = false;
1536   }
1537 
1538   IntervalList* unsorted_list = &_intervals;
1539   int unsorted_len = unsorted_list->length();
1540   int sorted_len = 0;
1541   int unsorted_idx;
1542   int sorted_idx = 0;
1543   int sorted_from_max = -1;
1544 
1545   // calc number of items for sorted list (sorted list must not contain NULL values)
1546   for (unsorted_idx = 0; unsorted_idx < unsorted_len; unsorted_idx++) {
1547     if (unsorted_list->at(unsorted_idx) != NULL) {
1548       sorted_len++;
1549     }
1550   }
1551   IntervalArray* sorted_list = new IntervalArray(sorted_len);
1552 
1553   // special sorting algorithm: the original interval-list is almost sorted,
1554   // only some intervals are swapped. So this is much faster than a complete QuickSort
1555   for (unsorted_idx = 0; unsorted_idx < unsorted_len; unsorted_idx++) {
1556     Interval* cur_interval = unsorted_list->at(unsorted_idx);
1557 
1558     if (cur_interval != NULL) {
1559       int cur_from = cur_interval->from();
1560 
1561       if (sorted_from_max <= cur_from) {
1562         sorted_list->at_put(sorted_idx++, cur_interval);
1563         sorted_from_max = cur_interval->from();
1564       } else {
1565         // the asumption that the intervals are already sorted failed,
1566         // so this interval must be sorted in manually
1567         int j;
1568         for (j = sorted_idx - 1; j >= 0 && cur_from < sorted_list->at(j)->from(); j--) {
1569           sorted_list->at_put(j + 1, sorted_list->at(j));
1570         }
1571         sorted_list->at_put(j + 1, cur_interval);
1572         sorted_idx++;
1573       }
1574     }
1575   }
1576   _sorted_intervals = sorted_list;
1577   assert(is_sorted(_sorted_intervals), "intervals unsorted");
1578 }
1579 
1580 void LinearScan::sort_intervals_after_allocation() {
1581   TIME_LINEAR_SCAN(timer_sort_intervals_after);
1582 
1583   if (_needs_full_resort) {
1584     // Re-sort existing interval list because an Interval::from() has changed
1585     _sorted_intervals->sort(interval_cmp);
1586     _needs_full_resort = false;
1587   }
1588 
1589   IntervalArray* old_list      = _sorted_intervals;
1590   IntervalList*  new_list      = _new_intervals_from_allocation;
1591   int old_len = old_list->length();
1592   int new_len = new_list->length();
1593 
1594   if (new_len == 0) {
1595     // no intervals have been added during allocation, so sorted list is already up to date
1596     assert(is_sorted(_sorted_intervals), "intervals unsorted");
1597     return;
1598   }
1599 
1600   // conventional sort-algorithm for new intervals
1601   new_list->sort(interval_cmp);
1602 
1603   // merge old and new list (both already sorted) into one combined list
1604   IntervalArray* combined_list = new IntervalArray(old_len + new_len);
1605   int old_idx = 0;
1606   int new_idx = 0;
1607 
1608   while (old_idx + new_idx < old_len + new_len) {
1609     if (new_idx >= new_len || (old_idx < old_len && old_list->at(old_idx)->from() <= new_list->at(new_idx)->from())) {
1610       combined_list->at_put(old_idx + new_idx, old_list->at(old_idx));
1611       old_idx++;
1612     } else {
1613       combined_list->at_put(old_idx + new_idx, new_list->at(new_idx));
1614       new_idx++;
1615     }
1616   }
1617 
1618   _sorted_intervals = combined_list;
1619   assert(is_sorted(_sorted_intervals), "intervals unsorted");
1620 }
1621 
1622 
1623 void LinearScan::allocate_registers() {
1624   TIME_LINEAR_SCAN(timer_allocate_registers);
1625 
1626   Interval* precolored_cpu_intervals, *not_precolored_cpu_intervals;
1627   Interval* precolored_fpu_intervals, *not_precolored_fpu_intervals;
1628 
1629   create_unhandled_lists(&precolored_cpu_intervals, &not_precolored_cpu_intervals, is_precolored_cpu_interval, is_virtual_cpu_interval);
1630   if (has_fpu_registers()) {
1631     create_unhandled_lists(&precolored_fpu_intervals, &not_precolored_fpu_intervals, is_precolored_fpu_interval, is_virtual_fpu_interval);
1632 #ifdef ASSERT
1633   } else {
1634     // fpu register allocation is omitted because no virtual fpu registers are present
1635     // just check this again...
1636     create_unhandled_lists(&precolored_fpu_intervals, &not_precolored_fpu_intervals, is_precolored_fpu_interval, is_virtual_fpu_interval);
1637     assert(not_precolored_fpu_intervals == Interval::end(), "missed an uncolored fpu interval");
1638 #endif
1639   }
1640 
1641   // allocate cpu registers
1642   LinearScanWalker cpu_lsw(this, precolored_cpu_intervals, not_precolored_cpu_intervals);
1643   cpu_lsw.walk();
1644   cpu_lsw.finish_allocation();
1645 
1646   if (has_fpu_registers()) {
1647     // allocate fpu registers
1648     LinearScanWalker fpu_lsw(this, precolored_fpu_intervals, not_precolored_fpu_intervals);
1649     fpu_lsw.walk();
1650     fpu_lsw.finish_allocation();
1651   }
1652 }
1653 
1654 
1655 // ********** Phase 6: resolve data flow
1656 // (insert moves at edges between blocks if intervals have been split)
1657 
1658 // wrapper for Interval::split_child_at_op_id that performs a bailout in product mode
1659 // instead of returning NULL
1660 Interval* LinearScan::split_child_at_op_id(Interval* interval, int op_id, LIR_OpVisitState::OprMode mode) {
1661   Interval* result = interval->split_child_at_op_id(op_id, mode);
1662   if (result != NULL) {
1663     return result;
1664   }
1665 
1666   assert(false, "must find an interval, but do a clean bailout in product mode");
1667   result = new Interval(LIR_OprDesc::vreg_base);
1668   result->assign_reg(0);
1669   result->set_type(T_INT);
1670   BAILOUT_("LinearScan: interval is NULL", result);
1671 }
1672 
1673 
1674 Interval* LinearScan::interval_at_block_begin(BlockBegin* block, int reg_num) {
1675   assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds");
1676   assert(interval_at(reg_num) != NULL, "no interval found");
1677 
1678   return split_child_at_op_id(interval_at(reg_num), block->first_lir_instruction_id(), LIR_OpVisitState::outputMode);
1679 }
1680 
1681 Interval* LinearScan::interval_at_block_end(BlockBegin* block, int reg_num) {
1682   assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds");
1683   assert(interval_at(reg_num) != NULL, "no interval found");
1684 
1685   return split_child_at_op_id(interval_at(reg_num), block->last_lir_instruction_id() + 1, LIR_OpVisitState::outputMode);
1686 }
1687 
1688 Interval* LinearScan::interval_at_op_id(int reg_num, int op_id) {
1689   assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds");
1690   assert(interval_at(reg_num) != NULL, "no interval found");
1691 
1692   return split_child_at_op_id(interval_at(reg_num), op_id, LIR_OpVisitState::inputMode);
1693 }
1694 
1695 
1696 void LinearScan::resolve_collect_mappings(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver) {
1697   DEBUG_ONLY(move_resolver.check_empty());
1698 
1699   const int num_regs = num_virtual_regs();
1700   const int size = live_set_size();
1701   const BitMap live_at_edge = to_block->live_in();
1702 
1703   // visit all registers where the live_at_edge bit is set
1704   for (int r = (int)live_at_edge.get_next_one_offset(0, size); r < size; r = (int)live_at_edge.get_next_one_offset(r + 1, size)) {
1705     assert(r < num_regs, "live information set for not exisiting interval");
1706     assert(from_block->live_out().at(r) && to_block->live_in().at(r), "interval not live at this edge");
1707 
1708     Interval* from_interval = interval_at_block_end(from_block, r);
1709     Interval* to_interval = interval_at_block_begin(to_block, r);
1710 
1711     if (from_interval != to_interval && (from_interval->assigned_reg() != to_interval->assigned_reg() || from_interval->assigned_regHi() != to_interval->assigned_regHi())) {
1712       // need to insert move instruction
1713       move_resolver.add_mapping(from_interval, to_interval);
1714     }
1715   }
1716 }
1717 
1718 
1719 void LinearScan::resolve_find_insert_pos(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver) {
1720   if (from_block->number_of_sux() <= 1) {
1721     TRACE_LINEAR_SCAN(4, tty->print_cr("inserting moves at end of from_block B%d", from_block->block_id()));
1722 
1723     LIR_OpList* instructions = from_block->lir()->instructions_list();
1724     LIR_OpBranch* branch = instructions->last()->as_OpBranch();
1725     if (branch != NULL) {
1726       // insert moves before branch
1727       assert(branch->cond() == lir_cond_always, "block does not end with an unconditional jump");
1728       move_resolver.set_insert_position(from_block->lir(), instructions->length() - 2);
1729     } else {
1730       move_resolver.set_insert_position(from_block->lir(), instructions->length() - 1);
1731     }
1732 
1733   } else {
1734     TRACE_LINEAR_SCAN(4, tty->print_cr("inserting moves at beginning of to_block B%d", to_block->block_id()));
1735 #ifdef ASSERT
1736     assert(from_block->lir()->instructions_list()->at(0)->as_OpLabel() != NULL, "block does not start with a label");
1737 
1738     // because the number of predecessor edges matches the number of
1739     // successor edges, blocks which are reached by switch statements
1740     // may have be more than one predecessor but it will be guaranteed
1741     // that all predecessors will be the same.
1742     for (int i = 0; i < to_block->number_of_preds(); i++) {
1743       assert(from_block == to_block->pred_at(i), "all critical edges must be broken");
1744     }
1745 #endif
1746 
1747     move_resolver.set_insert_position(to_block->lir(), 0);
1748   }
1749 }
1750 
1751 
1752 // insert necessary moves (spilling or reloading) at edges between blocks if interval has been split
1753 void LinearScan::resolve_data_flow() {
1754   TIME_LINEAR_SCAN(timer_resolve_data_flow);
1755 
1756   int num_blocks = block_count();
1757   MoveResolver move_resolver(this);
1758   BitMap block_completed(num_blocks);  block_completed.clear();
1759   BitMap already_resolved(num_blocks); already_resolved.clear();
1760 
1761   int i;
1762   for (i = 0; i < num_blocks; i++) {
1763     BlockBegin* block = block_at(i);
1764 
1765     // check if block has only one predecessor and only one successor
1766     if (block->number_of_preds() == 1 && block->number_of_sux() == 1 && block->number_of_exception_handlers() == 0) {
1767       LIR_OpList* instructions = block->lir()->instructions_list();
1768       assert(instructions->at(0)->code() == lir_label, "block must start with label");
1769       assert(instructions->last()->code() == lir_branch, "block with successors must end with branch");
1770       assert(instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block with successor must end with unconditional branch");
1771 
1772       // check if block is empty (only label and branch)
1773       if (instructions->length() == 2) {
1774         BlockBegin* pred = block->pred_at(0);
1775         BlockBegin* sux = block->sux_at(0);
1776 
1777         // prevent optimization of two consecutive blocks
1778         if (!block_completed.at(pred->linear_scan_number()) && !block_completed.at(sux->linear_scan_number())) {
1779           TRACE_LINEAR_SCAN(3, tty->print_cr("**** optimizing empty block B%d (pred: B%d, sux: B%d)", block->block_id(), pred->block_id(), sux->block_id()));
1780           block_completed.set_bit(block->linear_scan_number());
1781 
1782           // directly resolve between pred and sux (without looking at the empty block between)
1783           resolve_collect_mappings(pred, sux, move_resolver);
1784           if (move_resolver.has_mappings()) {
1785             move_resolver.set_insert_position(block->lir(), 0);
1786             move_resolver.resolve_and_append_moves();
1787           }
1788         }
1789       }
1790     }
1791   }
1792 
1793 
1794   for (i = 0; i < num_blocks; i++) {
1795     if (!block_completed.at(i)) {
1796       BlockBegin* from_block = block_at(i);
1797       already_resolved.set_from(block_completed);
1798 
1799       int num_sux = from_block->number_of_sux();
1800       for (int s = 0; s < num_sux; s++) {
1801         BlockBegin* to_block = from_block->sux_at(s);
1802 
1803         // check for duplicate edges between the same blocks (can happen with switch blocks)
1804         if (!already_resolved.at(to_block->linear_scan_number())) {
1805           TRACE_LINEAR_SCAN(3, tty->print_cr("**** processing edge between B%d and B%d", from_block->block_id(), to_block->block_id()));
1806           already_resolved.set_bit(to_block->linear_scan_number());
1807 
1808           // collect all intervals that have been split between from_block and to_block
1809           resolve_collect_mappings(from_block, to_block, move_resolver);
1810           if (move_resolver.has_mappings()) {
1811             resolve_find_insert_pos(from_block, to_block, move_resolver);
1812             move_resolver.resolve_and_append_moves();
1813           }
1814         }
1815       }
1816     }
1817   }
1818 }
1819 
1820 
1821 void LinearScan::resolve_exception_entry(BlockBegin* block, int reg_num, MoveResolver &move_resolver) {
1822   if (interval_at(reg_num) == NULL) {
1823     // if a phi function is never used, no interval is created -> ignore this
1824     return;
1825   }
1826 
1827   Interval* interval = interval_at_block_begin(block, reg_num);
1828   int reg = interval->assigned_reg();
1829   int regHi = interval->assigned_regHi();
1830 
1831   if ((reg < nof_regs && interval->always_in_memory()) ||
1832       (use_fpu_stack_allocation() && reg >= pd_first_fpu_reg && reg <= pd_last_fpu_reg)) {
1833     // the interval is split to get a short range that is located on the stack
1834     // in the following two cases:
1835     // * the interval started in memory (e.g. method parameter), but is currently in a register
1836     //   this is an optimization for exception handling that reduces the number of moves that
1837     //   are necessary for resolving the states when an exception uses this exception handler
1838     // * the interval would be on the fpu stack at the begin of the exception handler
1839     //   this is not allowed because of the complicated fpu stack handling on Intel
1840 
1841     // range that will be spilled to memory
1842     int from_op_id = block->first_lir_instruction_id();
1843     int to_op_id = from_op_id + 1;  // short live range of length 1
1844     assert(interval->from() <= from_op_id && interval->to() >= to_op_id,
1845            "no split allowed between exception entry and first instruction");
1846 
1847     if (interval->from() != from_op_id) {
1848       // the part before from_op_id is unchanged
1849       interval = interval->split(from_op_id);
1850       interval->assign_reg(reg, regHi);
1851       append_interval(interval);
1852     } else {
1853       _needs_full_resort = true;
1854     }
1855     assert(interval->from() == from_op_id, "must be true now");
1856 
1857     Interval* spilled_part = interval;
1858     if (interval->to() != to_op_id) {
1859       // the part after to_op_id is unchanged
1860       spilled_part = interval->split_from_start(to_op_id);
1861       append_interval(spilled_part);
1862       move_resolver.add_mapping(spilled_part, interval);
1863     }
1864     assign_spill_slot(spilled_part);
1865 
1866     assert(spilled_part->from() == from_op_id && spilled_part->to() == to_op_id, "just checking");
1867   }
1868 }
1869 
1870 void LinearScan::resolve_exception_entry(BlockBegin* block, MoveResolver &move_resolver) {
1871   assert(block->is_set(BlockBegin::exception_entry_flag), "should not call otherwise");
1872   DEBUG_ONLY(move_resolver.check_empty());
1873 
1874   // visit all registers where the live_in bit is set
1875   int size = live_set_size();
1876   for (int r = (int)block->live_in().get_next_one_offset(0, size); r < size; r = (int)block->live_in().get_next_one_offset(r + 1, size)) {
1877     resolve_exception_entry(block, r, move_resolver);
1878   }
1879 
1880   // the live_in bits are not set for phi functions of the xhandler entry, so iterate them separately
1881   for_each_phi_fun(block, phi,
1882     resolve_exception_entry(block, phi->operand()->vreg_number(), move_resolver)
1883   );
1884 
1885   if (move_resolver.has_mappings()) {
1886     // insert moves after first instruction
1887     move_resolver.set_insert_position(block->lir(), 1);
1888     move_resolver.resolve_and_append_moves();
1889   }
1890 }
1891 
1892 
1893 void LinearScan::resolve_exception_edge(XHandler* handler, int throwing_op_id, int reg_num, Phi* phi, MoveResolver &move_resolver) {
1894   if (interval_at(reg_num) == NULL) {
1895     // if a phi function is never used, no interval is created -> ignore this
1896     return;
1897   }
1898 
1899   // the computation of to_interval is equal to resolve_collect_mappings,
1900   // but from_interval is more complicated because of phi functions
1901   BlockBegin* to_block = handler->entry_block();
1902   Interval* to_interval = interval_at_block_begin(to_block, reg_num);
1903 
1904   if (phi != NULL) {
1905     // phi function of the exception entry block
1906     // no moves are created for this phi function in the LIR_Generator, so the
1907     // interval at the throwing instruction must be searched using the operands
1908     // of the phi function
1909     Value from_value = phi->operand_at(handler->phi_operand());
1910 
1911     // with phi functions it can happen that the same from_value is used in
1912     // multiple mappings, so notify move-resolver that this is allowed
1913     move_resolver.set_multiple_reads_allowed();
1914 
1915     Constant* con = from_value->as_Constant();
1916     if (con != NULL && !con->is_pinned()) {
1917       // unpinned constants may have no register, so add mapping from constant to interval
1918       move_resolver.add_mapping(LIR_OprFact::value_type(con->type()), to_interval);
1919     } else {
1920       // search split child at the throwing op_id
1921       Interval* from_interval = interval_at_op_id(from_value->operand()->vreg_number(), throwing_op_id);
1922       move_resolver.add_mapping(from_interval, to_interval);
1923     }
1924 
1925   } else {
1926     // no phi function, so use reg_num also for from_interval
1927     // search split child at the throwing op_id
1928     Interval* from_interval = interval_at_op_id(reg_num, throwing_op_id);
1929     if (from_interval != to_interval) {
1930       // optimization to reduce number of moves: when to_interval is on stack and
1931       // the stack slot is known to be always correct, then no move is necessary
1932       if (!from_interval->always_in_memory() || from_interval->canonical_spill_slot() != to_interval->assigned_reg()) {
1933         move_resolver.add_mapping(from_interval, to_interval);
1934       }
1935     }
1936   }
1937 }
1938 
1939 void LinearScan::resolve_exception_edge(XHandler* handler, int throwing_op_id, MoveResolver &move_resolver) {
1940   TRACE_LINEAR_SCAN(4, tty->print_cr("resolving exception handler B%d: throwing_op_id=%d", handler->entry_block()->block_id(), throwing_op_id));
1941 
1942   DEBUG_ONLY(move_resolver.check_empty());
1943   assert(handler->lir_op_id() == -1, "already processed this xhandler");
1944   DEBUG_ONLY(handler->set_lir_op_id(throwing_op_id));
1945   assert(handler->entry_code() == NULL, "code already present");
1946 
1947   // visit all registers where the live_in bit is set
1948   BlockBegin* block = handler->entry_block();
1949   int size = live_set_size();
1950   for (int r = (int)block->live_in().get_next_one_offset(0, size); r < size; r = (int)block->live_in().get_next_one_offset(r + 1, size)) {
1951     resolve_exception_edge(handler, throwing_op_id, r, NULL, move_resolver);
1952   }
1953 
1954   // the live_in bits are not set for phi functions of the xhandler entry, so iterate them separately
1955   for_each_phi_fun(block, phi,
1956     resolve_exception_edge(handler, throwing_op_id, phi->operand()->vreg_number(), phi, move_resolver)
1957   );
1958 
1959   if (move_resolver.has_mappings()) {
1960     LIR_List* entry_code = new LIR_List(compilation());
1961     move_resolver.set_insert_position(entry_code, 0);
1962     move_resolver.resolve_and_append_moves();
1963 
1964     entry_code->jump(handler->entry_block());
1965     handler->set_entry_code(entry_code);
1966   }
1967 }
1968 
1969 
1970 void LinearScan::resolve_exception_handlers() {
1971   MoveResolver move_resolver(this);
1972   LIR_OpVisitState visitor;
1973   int num_blocks = block_count();
1974 
1975   int i;
1976   for (i = 0; i < num_blocks; i++) {
1977     BlockBegin* block = block_at(i);
1978     if (block->is_set(BlockBegin::exception_entry_flag)) {
1979       resolve_exception_entry(block, move_resolver);
1980     }
1981   }
1982 
1983   for (i = 0; i < num_blocks; i++) {
1984     BlockBegin* block = block_at(i);
1985     LIR_List* ops = block->lir();
1986     int num_ops = ops->length();
1987 
1988     // iterate all instructions of the block. skip the first because it is always a label
1989     assert(visitor.no_operands(ops->at(0)), "first operation must always be a label");
1990     for (int j = 1; j < num_ops; j++) {
1991       LIR_Op* op = ops->at(j);
1992       int op_id = op->id();
1993 
1994       if (op_id != -1 && has_info(op_id)) {
1995         // visit operation to collect all operands
1996         visitor.visit(op);
1997         assert(visitor.info_count() > 0, "should not visit otherwise");
1998 
1999         XHandlers* xhandlers = visitor.all_xhandler();
2000         int n = xhandlers->length();
2001         for (int k = 0; k < n; k++) {
2002           resolve_exception_edge(xhandlers->handler_at(k), op_id, move_resolver);
2003         }
2004 
2005 #ifdef ASSERT
2006       } else {
2007         visitor.visit(op);
2008         assert(visitor.all_xhandler()->length() == 0, "missed exception handler");
2009 #endif
2010       }
2011     }
2012   }
2013 }
2014 
2015 
2016 // ********** Phase 7: assign register numbers back to LIR
2017 // (includes computation of debug information and oop maps)
2018 
2019 VMReg LinearScan::vm_reg_for_interval(Interval* interval) {
2020   VMReg reg = interval->cached_vm_reg();
2021   if (!reg->is_valid() ) {
2022     reg = vm_reg_for_operand(operand_for_interval(interval));
2023     interval->set_cached_vm_reg(reg);
2024   }
2025   assert(reg == vm_reg_for_operand(operand_for_interval(interval)), "wrong cached value");
2026   return reg;
2027 }
2028 
2029 VMReg LinearScan::vm_reg_for_operand(LIR_Opr opr) {
2030   assert(opr->is_oop(), "currently only implemented for oop operands");
2031   return frame_map()->regname(opr);
2032 }
2033 
2034 
2035 LIR_Opr LinearScan::operand_for_interval(Interval* interval) {
2036   LIR_Opr opr = interval->cached_opr();
2037   if (opr->is_illegal()) {
2038     opr = calc_operand_for_interval(interval);
2039     interval->set_cached_opr(opr);
2040   }
2041 
2042   assert(opr == calc_operand_for_interval(interval), "wrong cached value");
2043   return opr;
2044 }
2045 
2046 LIR_Opr LinearScan::calc_operand_for_interval(const Interval* interval) {
2047   int assigned_reg = interval->assigned_reg();
2048   BasicType type = interval->type();
2049 
2050   if (assigned_reg >= nof_regs) {
2051     // stack slot
2052     assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2053     return LIR_OprFact::stack(assigned_reg - nof_regs, type);
2054 
2055   } else {
2056     // register
2057     switch (type) {
2058       case T_OBJECT: {
2059         assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2060         assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2061         return LIR_OprFact::single_cpu_oop(assigned_reg);
2062       }
2063 
2064       case T_ADDRESS: {
2065         assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2066         assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2067         return LIR_OprFact::single_cpu_address(assigned_reg);
2068       }
2069 
2070 #ifdef __SOFTFP__
2071       case T_FLOAT:  // fall through
2072 #endif // __SOFTFP__
2073       case T_INT: {
2074         assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2075         assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2076         return LIR_OprFact::single_cpu(assigned_reg);
2077       }
2078 
2079 #ifdef __SOFTFP__
2080       case T_DOUBLE:  // fall through
2081 #endif // __SOFTFP__
2082       case T_LONG: {
2083         int assigned_regHi = interval->assigned_regHi();
2084         assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2085         assert(num_physical_regs(T_LONG) == 1 ||
2086                (assigned_regHi >= pd_first_cpu_reg && assigned_regHi <= pd_last_cpu_reg), "no cpu register");
2087 
2088         assert(assigned_reg != assigned_regHi, "invalid allocation");
2089         assert(num_physical_regs(T_LONG) == 1 || assigned_reg < assigned_regHi,
2090                "register numbers must be sorted (ensure that e.g. a move from eax,ebx to ebx,eax can not occur)");
2091         assert((assigned_regHi != any_reg) ^ (num_physical_regs(T_LONG) == 1), "must be match");
2092         if (requires_adjacent_regs(T_LONG)) {
2093           assert(assigned_reg % 2 == 0 && assigned_reg + 1 == assigned_regHi, "must be sequential and even");
2094         }
2095 
2096 #ifdef _LP64
2097         return LIR_OprFact::double_cpu(assigned_reg, assigned_reg);
2098 #else
2099 #if defined(SPARC) || defined(PPC)
2100         return LIR_OprFact::double_cpu(assigned_regHi, assigned_reg);
2101 #else
2102         return LIR_OprFact::double_cpu(assigned_reg, assigned_regHi);
2103 #endif // SPARC
2104 #endif // LP64
2105       }
2106 
2107 #ifndef __SOFTFP__
2108       case T_FLOAT: {
2109 #ifdef X86
2110         if (UseSSE >= 1) {
2111           assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= pd_last_xmm_reg, "no xmm register");
2112           assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2113           return LIR_OprFact::single_xmm(assigned_reg - pd_first_xmm_reg);
2114         }
2115 #endif
2116 
2117         assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2118         assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2119         return LIR_OprFact::single_fpu(assigned_reg - pd_first_fpu_reg);
2120       }
2121 
2122       case T_DOUBLE: {
2123 #ifdef X86
2124         if (UseSSE >= 2) {
2125           assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= pd_last_xmm_reg, "no xmm register");
2126           assert(interval->assigned_regHi() == any_reg, "must not have hi register (double xmm values are stored in one register)");
2127           return LIR_OprFact::double_xmm(assigned_reg - pd_first_xmm_reg);
2128         }
2129 #endif
2130 
2131 #ifdef SPARC
2132         assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2133         assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register");
2134         assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even");
2135         LIR_Opr result = LIR_OprFact::double_fpu(interval->assigned_regHi() - pd_first_fpu_reg, assigned_reg - pd_first_fpu_reg);
2136 #elif defined(ARM)
2137         assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2138         assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register");
2139         assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even");
2140         LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg, interval->assigned_regHi() - pd_first_fpu_reg);
2141 #else
2142         assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2143         assert(interval->assigned_regHi() == any_reg, "must not have hi register (double fpu values are stored in one register on Intel)");
2144         LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg);
2145 #endif
2146         return result;
2147       }
2148 #endif // __SOFTFP__
2149 
2150       default: {
2151         ShouldNotReachHere();
2152         return LIR_OprFact::illegalOpr;
2153       }
2154     }
2155   }
2156 }
2157 
2158 LIR_Opr LinearScan::canonical_spill_opr(Interval* interval) {
2159   assert(interval->canonical_spill_slot() >= nof_regs, "canonical spill slot not set");
2160   return LIR_OprFact::stack(interval->canonical_spill_slot() - nof_regs, interval->type());
2161 }
2162 
2163 LIR_Opr LinearScan::color_lir_opr(LIR_Opr opr, int op_id, LIR_OpVisitState::OprMode mode) {
2164   assert(opr->is_virtual(), "should not call this otherwise");
2165 
2166   Interval* interval = interval_at(opr->vreg_number());
2167   assert(interval != NULL, "interval must exist");
2168 
2169   if (op_id != -1) {
2170 #ifdef ASSERT
2171     BlockBegin* block = block_of_op_with_id(op_id);
2172     if (block->number_of_sux() <= 1 && op_id == block->last_lir_instruction_id()) {
2173       // check if spill moves could have been appended at the end of this block, but
2174       // before the branch instruction. So the split child information for this branch would
2175       // be incorrect.
2176       LIR_OpBranch* branch = block->lir()->instructions_list()->last()->as_OpBranch();
2177       if (branch != NULL) {
2178         if (block->live_out().at(opr->vreg_number())) {
2179           assert(branch->cond() == lir_cond_always, "block does not end with an unconditional jump");
2180           assert(false, "can't get split child for the last branch of a block because the information would be incorrect (moves are inserted before the branch in resolve_data_flow)");
2181         }
2182       }
2183     }
2184 #endif
2185 
2186     // operands are not changed when an interval is split during allocation,
2187     // so search the right interval here
2188     interval = split_child_at_op_id(interval, op_id, mode);
2189   }
2190 
2191   LIR_Opr res = operand_for_interval(interval);
2192 
2193 #ifdef X86
2194   // new semantic for is_last_use: not only set on definite end of interval,
2195   // but also before hole
2196   // This may still miss some cases (e.g. for dead values), but it is not necessary that the
2197   // last use information is completely correct
2198   // information is only needed for fpu stack allocation
2199   if (res->is_fpu_register()) {
2200     if (opr->is_last_use() || op_id == interval->to() || (op_id != -1 && interval->has_hole_between(op_id, op_id + 1))) {
2201       assert(op_id == -1 || !is_block_begin(op_id), "holes at begin of block may also result from control flow");
2202       res = res->make_last_use();
2203     }
2204   }
2205 #endif
2206 
2207   assert(!gen()->is_vreg_flag_set(opr->vreg_number(), LIRGenerator::callee_saved) || !FrameMap::is_caller_save_register(res), "bad allocation");
2208 
2209   return res;
2210 }
2211 
2212 
2213 #ifdef ASSERT
2214 // some methods used to check correctness of debug information
2215 
2216 void assert_no_register_values(GrowableArray<ScopeValue*>* values) {
2217   if (values == NULL) {
2218     return;
2219   }
2220 
2221   for (int i = 0; i < values->length(); i++) {
2222     ScopeValue* value = values->at(i);
2223 
2224     if (value->is_location()) {
2225       Location location = ((LocationValue*)value)->location();
2226       assert(location.where() == Location::on_stack, "value is in register");
2227     }
2228   }
2229 }
2230 
2231 void assert_no_register_values(GrowableArray<MonitorValue*>* values) {
2232   if (values == NULL) {
2233     return;
2234   }
2235 
2236   for (int i = 0; i < values->length(); i++) {
2237     MonitorValue* value = values->at(i);
2238 
2239     if (value->owner()->is_location()) {
2240       Location location = ((LocationValue*)value->owner())->location();
2241       assert(location.where() == Location::on_stack, "owner is in register");
2242     }
2243     assert(value->basic_lock().where() == Location::on_stack, "basic_lock is in register");
2244   }
2245 }
2246 
2247 void assert_equal(Location l1, Location l2) {
2248   assert(l1.where() == l2.where() && l1.type() == l2.type() && l1.offset() == l2.offset(), "");
2249 }
2250 
2251 void assert_equal(ScopeValue* v1, ScopeValue* v2) {
2252   if (v1->is_location()) {
2253     assert(v2->is_location(), "");
2254     assert_equal(((LocationValue*)v1)->location(), ((LocationValue*)v2)->location());
2255   } else if (v1->is_constant_int()) {
2256     assert(v2->is_constant_int(), "");
2257     assert(((ConstantIntValue*)v1)->value() == ((ConstantIntValue*)v2)->value(), "");
2258   } else if (v1->is_constant_double()) {
2259     assert(v2->is_constant_double(), "");
2260     assert(((ConstantDoubleValue*)v1)->value() == ((ConstantDoubleValue*)v2)->value(), "");
2261   } else if (v1->is_constant_long()) {
2262     assert(v2->is_constant_long(), "");
2263     assert(((ConstantLongValue*)v1)->value() == ((ConstantLongValue*)v2)->value(), "");
2264   } else if (v1->is_constant_oop()) {
2265     assert(v2->is_constant_oop(), "");
2266     assert(((ConstantOopWriteValue*)v1)->value() == ((ConstantOopWriteValue*)v2)->value(), "");
2267   } else {
2268     ShouldNotReachHere();
2269   }
2270 }
2271 
2272 void assert_equal(MonitorValue* m1, MonitorValue* m2) {
2273   assert_equal(m1->owner(), m2->owner());
2274   assert_equal(m1->basic_lock(), m2->basic_lock());
2275 }
2276 
2277 void assert_equal(IRScopeDebugInfo* d1, IRScopeDebugInfo* d2) {
2278   assert(d1->scope() == d2->scope(), "not equal");
2279   assert(d1->bci() == d2->bci(), "not equal");
2280 
2281   if (d1->locals() != NULL) {
2282     assert(d1->locals() != NULL && d2->locals() != NULL, "not equal");
2283     assert(d1->locals()->length() == d2->locals()->length(), "not equal");
2284     for (int i = 0; i < d1->locals()->length(); i++) {
2285       assert_equal(d1->locals()->at(i), d2->locals()->at(i));
2286     }
2287   } else {
2288     assert(d1->locals() == NULL && d2->locals() == NULL, "not equal");
2289   }
2290 
2291   if (d1->expressions() != NULL) {
2292     assert(d1->expressions() != NULL && d2->expressions() != NULL, "not equal");
2293     assert(d1->expressions()->length() == d2->expressions()->length(), "not equal");
2294     for (int i = 0; i < d1->expressions()->length(); i++) {
2295       assert_equal(d1->expressions()->at(i), d2->expressions()->at(i));
2296     }
2297   } else {
2298     assert(d1->expressions() == NULL && d2->expressions() == NULL, "not equal");
2299   }
2300 
2301   if (d1->monitors() != NULL) {
2302     assert(d1->monitors() != NULL && d2->monitors() != NULL, "not equal");
2303     assert(d1->monitors()->length() == d2->monitors()->length(), "not equal");
2304     for (int i = 0; i < d1->monitors()->length(); i++) {
2305       assert_equal(d1->monitors()->at(i), d2->monitors()->at(i));
2306     }
2307   } else {
2308     assert(d1->monitors() == NULL && d2->monitors() == NULL, "not equal");
2309   }
2310 
2311   if (d1->caller() != NULL) {
2312     assert(d1->caller() != NULL && d2->caller() != NULL, "not equal");
2313     assert_equal(d1->caller(), d2->caller());
2314   } else {
2315     assert(d1->caller() == NULL && d2->caller() == NULL, "not equal");
2316   }
2317 }
2318 
2319 void check_stack_depth(CodeEmitInfo* info, int stack_end) {
2320   if (info->stack()->bci() != SynchronizationEntryBCI && !info->scope()->method()->is_native()) {
2321     Bytecodes::Code code = info->scope()->method()->java_code_at_bci(info->stack()->bci());
2322     switch (code) {
2323       case Bytecodes::_ifnull    : // fall through
2324       case Bytecodes::_ifnonnull : // fall through
2325       case Bytecodes::_ifeq      : // fall through
2326       case Bytecodes::_ifne      : // fall through
2327       case Bytecodes::_iflt      : // fall through
2328       case Bytecodes::_ifge      : // fall through
2329       case Bytecodes::_ifgt      : // fall through
2330       case Bytecodes::_ifle      : // fall through
2331       case Bytecodes::_if_icmpeq : // fall through
2332       case Bytecodes::_if_icmpne : // fall through
2333       case Bytecodes::_if_icmplt : // fall through
2334       case Bytecodes::_if_icmpge : // fall through
2335       case Bytecodes::_if_icmpgt : // fall through
2336       case Bytecodes::_if_icmple : // fall through
2337       case Bytecodes::_if_acmpeq : // fall through
2338       case Bytecodes::_if_acmpne :
2339         assert(stack_end >= -Bytecodes::depth(code), "must have non-empty expression stack at if bytecode");
2340         break;
2341     }
2342   }
2343 }
2344 
2345 #endif // ASSERT
2346 
2347 
2348 IntervalWalker* LinearScan::init_compute_oop_maps() {
2349   // setup lists of potential oops for walking
2350   Interval* oop_intervals;
2351   Interval* non_oop_intervals;
2352 
2353   create_unhandled_lists(&oop_intervals, &non_oop_intervals, is_oop_interval, NULL);
2354 
2355   // intervals that have no oops inside need not to be processed
2356   // to ensure a walking until the last instruction id, add a dummy interval
2357   // with a high operation id
2358   non_oop_intervals = new Interval(any_reg);
2359   non_oop_intervals->add_range(max_jint - 2, max_jint - 1);
2360 
2361   return new IntervalWalker(this, oop_intervals, non_oop_intervals);
2362 }
2363 
2364 
2365 OopMap* LinearScan::compute_oop_map(IntervalWalker* iw, LIR_Op* op, CodeEmitInfo* info, bool is_call_site) {
2366   TRACE_LINEAR_SCAN(3, tty->print_cr("creating oop map at op_id %d", op->id()));
2367 
2368   // walk before the current operation -> intervals that start at
2369   // the operation (= output operands of the operation) are not
2370   // included in the oop map
2371   iw->walk_before(op->id());
2372 
2373   int frame_size = frame_map()->framesize();
2374   int arg_count = frame_map()->oop_map_arg_count();
2375   OopMap* map = new OopMap(frame_size, arg_count);
2376 
2377   // Check if this is a patch site.
2378   bool is_patch_info = false;
2379   if (op->code() == lir_move) {
2380     assert(!is_call_site, "move must not be a call site");
2381     assert(op->as_Op1() != NULL, "move must be LIR_Op1");
2382     LIR_Op1* move = (LIR_Op1*)op;
2383 
2384     is_patch_info = move->patch_code() != lir_patch_none;
2385   }
2386 
2387   // Iterate through active intervals
2388   for (Interval* interval = iw->active_first(fixedKind); interval != Interval::end(); interval = interval->next()) {
2389     int assigned_reg = interval->assigned_reg();
2390 
2391     assert(interval->current_from() <= op->id() && op->id() <= interval->current_to(), "interval should not be active otherwise");
2392     assert(interval->assigned_regHi() == any_reg, "oop must be single word");
2393     assert(interval->reg_num() >= LIR_OprDesc::vreg_base, "fixed interval found");
2394 
2395     // Check if this range covers the instruction. Intervals that
2396     // start or end at the current operation are not included in the
2397     // oop map, except in the case of patching moves.  For patching
2398     // moves, any intervals which end at this instruction are included
2399     // in the oop map since we may safepoint while doing the patch
2400     // before we've consumed the inputs.
2401     if (is_patch_info || op->id() < interval->current_to()) {
2402 
2403       // caller-save registers must not be included into oop-maps at calls
2404       assert(!is_call_site || assigned_reg >= nof_regs || !is_caller_save(assigned_reg), "interval is in a caller-save register at a call -> register will be overwritten");
2405 
2406       VMReg name = vm_reg_for_interval(interval);
2407       map->set_oop(name);
2408 
2409       // Spill optimization: when the stack value is guaranteed to be always correct,
2410       // then it must be added to the oop map even if the interval is currently in a register
2411       if (interval->always_in_memory() &&
2412           op->id() > interval->spill_definition_pos() &&
2413           interval->assigned_reg() != interval->canonical_spill_slot()) {
2414         assert(interval->spill_definition_pos() > 0, "position not set correctly");
2415         assert(interval->canonical_spill_slot() >= LinearScan::nof_regs, "no spill slot assigned");
2416         assert(interval->assigned_reg() < LinearScan::nof_regs, "interval is on stack, so stack slot is registered twice");
2417 
2418         map->set_oop(frame_map()->slot_regname(interval->canonical_spill_slot() - LinearScan::nof_regs));
2419       }
2420     }
2421   }
2422 
2423   // add oops from lock stack
2424   assert(info->stack() != NULL, "CodeEmitInfo must always have a stack");
2425   int locks_count = info->stack()->total_locks_size();
2426   for (int i = 0; i < locks_count; i++) {
2427     map->set_oop(frame_map()->monitor_object_regname(i));
2428   }
2429 
2430   return map;
2431 }
2432 
2433 
2434 void LinearScan::compute_oop_map(IntervalWalker* iw, const LIR_OpVisitState &visitor, LIR_Op* op) {
2435   assert(visitor.info_count() > 0, "no oop map needed");
2436 
2437   // compute oop_map only for first CodeEmitInfo
2438   // because it is (in most cases) equal for all other infos of the same operation
2439   CodeEmitInfo* first_info = visitor.info_at(0);
2440   OopMap* first_oop_map = compute_oop_map(iw, op, first_info, visitor.has_call());
2441 
2442   for (int i = 0; i < visitor.info_count(); i++) {
2443     CodeEmitInfo* info = visitor.info_at(i);
2444     OopMap* oop_map = first_oop_map;
2445 
2446     if (info->stack()->locks_size() != first_info->stack()->locks_size()) {
2447       // this info has a different number of locks then the precomputed oop map
2448       // (possible for lock and unlock instructions) -> compute oop map with
2449       // correct lock information
2450       oop_map = compute_oop_map(iw, op, info, visitor.has_call());
2451     }
2452 
2453     if (info->_oop_map == NULL) {
2454       info->_oop_map = oop_map;
2455     } else {
2456       // a CodeEmitInfo can not be shared between different LIR-instructions
2457       // because interval splitting can occur anywhere between two instructions
2458       // and so the oop maps must be different
2459       // -> check if the already set oop_map is exactly the one calculated for this operation
2460       assert(info->_oop_map == oop_map, "same CodeEmitInfo used for multiple LIR instructions");
2461     }
2462   }
2463 }
2464 
2465 
2466 // frequently used constants
2467 ConstantOopWriteValue LinearScan::_oop_null_scope_value = ConstantOopWriteValue(NULL);
2468 ConstantIntValue      LinearScan::_int_m1_scope_value = ConstantIntValue(-1);
2469 ConstantIntValue      LinearScan::_int_0_scope_value =  ConstantIntValue(0);
2470 ConstantIntValue      LinearScan::_int_1_scope_value =  ConstantIntValue(1);
2471 ConstantIntValue      LinearScan::_int_2_scope_value =  ConstantIntValue(2);
2472 LocationValue         _illegal_value = LocationValue(Location());
2473 
2474 void LinearScan::init_compute_debug_info() {
2475   // cache for frequently used scope values
2476   // (cpu registers and stack slots)
2477   _scope_value_cache = ScopeValueArray((LinearScan::nof_cpu_regs + frame_map()->argcount() + max_spills()) * 2, NULL);
2478 }
2479 
2480 MonitorValue* LinearScan::location_for_monitor_index(int monitor_index) {
2481   Location loc;
2482   if (!frame_map()->location_for_monitor_object(monitor_index, &loc)) {
2483     bailout("too large frame");
2484   }
2485   ScopeValue* object_scope_value = new LocationValue(loc);
2486 
2487   if (!frame_map()->location_for_monitor_lock(monitor_index, &loc)) {
2488     bailout("too large frame");
2489   }
2490   return new MonitorValue(object_scope_value, loc);
2491 }
2492 
2493 LocationValue* LinearScan::location_for_name(int name, Location::Type loc_type) {
2494   Location loc;
2495   if (!frame_map()->locations_for_slot(name, loc_type, &loc)) {
2496     bailout("too large frame");
2497   }
2498   return new LocationValue(loc);
2499 }
2500 
2501 
2502 int LinearScan::append_scope_value_for_constant(LIR_Opr opr, GrowableArray<ScopeValue*>* scope_values) {
2503   assert(opr->is_constant(), "should not be called otherwise");
2504 
2505   LIR_Const* c = opr->as_constant_ptr();
2506   BasicType t = c->type();
2507   switch (t) {
2508     case T_OBJECT: {
2509       jobject value = c->as_jobject();
2510       if (value == NULL) {
2511         scope_values->append(&_oop_null_scope_value);
2512       } else {
2513         scope_values->append(new ConstantOopWriteValue(c->as_jobject()));
2514       }
2515       return 1;
2516     }
2517 
2518     case T_INT: // fall through
2519     case T_FLOAT: {
2520       int value = c->as_jint_bits();
2521       switch (value) {
2522         case -1: scope_values->append(&_int_m1_scope_value); break;
2523         case 0:  scope_values->append(&_int_0_scope_value); break;
2524         case 1:  scope_values->append(&_int_1_scope_value); break;
2525         case 2:  scope_values->append(&_int_2_scope_value); break;
2526         default: scope_values->append(new ConstantIntValue(c->as_jint_bits())); break;
2527       }
2528       return 1;
2529     }
2530 
2531     case T_LONG: // fall through
2532     case T_DOUBLE: {
2533 #ifdef _LP64
2534       scope_values->append(&_int_0_scope_value);
2535       scope_values->append(new ConstantLongValue(c->as_jlong_bits()));
2536 #else
2537       if (hi_word_offset_in_bytes > lo_word_offset_in_bytes) {
2538         scope_values->append(new ConstantIntValue(c->as_jint_hi_bits()));
2539         scope_values->append(new ConstantIntValue(c->as_jint_lo_bits()));
2540       } else {
2541         scope_values->append(new ConstantIntValue(c->as_jint_lo_bits()));
2542         scope_values->append(new ConstantIntValue(c->as_jint_hi_bits()));
2543       }
2544 #endif
2545       return 2;
2546     }
2547 
2548     case T_ADDRESS: {
2549 #ifdef _LP64
2550       scope_values->append(new ConstantLongValue(c->as_jint()));
2551 #else
2552       scope_values->append(new ConstantIntValue(c->as_jint()));
2553 #endif
2554       return 1;
2555     }
2556 
2557     default:
2558       ShouldNotReachHere();
2559       return -1;
2560   }
2561 }
2562 
2563 int LinearScan::append_scope_value_for_operand(LIR_Opr opr, GrowableArray<ScopeValue*>* scope_values) {
2564   if (opr->is_single_stack()) {
2565     int stack_idx = opr->single_stack_ix();
2566     bool is_oop = opr->is_oop_register();
2567     int cache_idx = (stack_idx + LinearScan::nof_cpu_regs) * 2 + (is_oop ? 1 : 0);
2568 
2569     ScopeValue* sv = _scope_value_cache.at(cache_idx);
2570     if (sv == NULL) {
2571       Location::Type loc_type = is_oop ? Location::oop : Location::normal;
2572       sv = location_for_name(stack_idx, loc_type);
2573       _scope_value_cache.at_put(cache_idx, sv);
2574     }
2575 
2576     // check if cached value is correct
2577     DEBUG_ONLY(assert_equal(sv, location_for_name(stack_idx, is_oop ? Location::oop : Location::normal)));
2578 
2579     scope_values->append(sv);
2580     return 1;
2581 
2582   } else if (opr->is_single_cpu()) {
2583     bool is_oop = opr->is_oop_register();
2584     int cache_idx = opr->cpu_regnr() * 2 + (is_oop ? 1 : 0);
2585     Location::Type int_loc_type = NOT_LP64(Location::normal) LP64_ONLY(Location::int_in_long);
2586 
2587     ScopeValue* sv = _scope_value_cache.at(cache_idx);
2588     if (sv == NULL) {
2589       Location::Type loc_type = is_oop ? Location::oop : int_loc_type;
2590       VMReg rname = frame_map()->regname(opr);
2591       sv = new LocationValue(Location::new_reg_loc(loc_type, rname));
2592       _scope_value_cache.at_put(cache_idx, sv);
2593     }
2594 
2595     // check if cached value is correct
2596     DEBUG_ONLY(assert_equal(sv, new LocationValue(Location::new_reg_loc(is_oop ? Location::oop : int_loc_type, frame_map()->regname(opr)))));
2597 
2598     scope_values->append(sv);
2599     return 1;
2600 
2601 #ifdef X86
2602   } else if (opr->is_single_xmm()) {
2603     VMReg rname = opr->as_xmm_float_reg()->as_VMReg();
2604     LocationValue* sv = new LocationValue(Location::new_reg_loc(Location::normal, rname));
2605 
2606     scope_values->append(sv);
2607     return 1;
2608 #endif
2609 
2610   } else if (opr->is_single_fpu()) {
2611 #ifdef X86
2612     // the exact location of fpu stack values is only known
2613     // during fpu stack allocation, so the stack allocator object
2614     // must be present
2615     assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)");
2616     assert(_fpu_stack_allocator != NULL, "must be present");
2617     opr = _fpu_stack_allocator->to_fpu_stack(opr);
2618 #endif
2619 
2620     Location::Type loc_type = float_saved_as_double ? Location::float_in_dbl : Location::normal;
2621     VMReg rname = frame_map()->fpu_regname(opr->fpu_regnr());
2622     LocationValue* sv = new LocationValue(Location::new_reg_loc(loc_type, rname));
2623 
2624     scope_values->append(sv);
2625     return 1;
2626 
2627   } else {
2628     // double-size operands
2629 
2630     ScopeValue* first;
2631     ScopeValue* second;
2632 
2633     if (opr->is_double_stack()) {
2634 #ifdef _LP64
2635       Location loc1;
2636       Location::Type loc_type = opr->type() == T_LONG ? Location::lng : Location::dbl;
2637       if (!frame_map()->locations_for_slot(opr->double_stack_ix(), loc_type, &loc1, NULL)) {
2638         bailout("too large frame");
2639       }
2640       // Does this reverse on x86 vs. sparc?
2641       first =  new LocationValue(loc1);
2642       second = &_int_0_scope_value;
2643 #else
2644       Location loc1, loc2;
2645       if (!frame_map()->locations_for_slot(opr->double_stack_ix(), Location::normal, &loc1, &loc2)) {
2646         bailout("too large frame");
2647       }
2648       first =  new LocationValue(loc1);
2649       second = new LocationValue(loc2);
2650 #endif // _LP64
2651 
2652     } else if (opr->is_double_cpu()) {
2653 #ifdef _LP64
2654       VMReg rname_first = opr->as_register_lo()->as_VMReg();
2655       first = new LocationValue(Location::new_reg_loc(Location::lng, rname_first));
2656       second = &_int_0_scope_value;
2657 #else
2658       VMReg rname_first = opr->as_register_lo()->as_VMReg();
2659       VMReg rname_second = opr->as_register_hi()->as_VMReg();
2660 
2661       if (hi_word_offset_in_bytes < lo_word_offset_in_bytes) {
2662         // lo/hi and swapped relative to first and second, so swap them
2663         VMReg tmp = rname_first;
2664         rname_first = rname_second;
2665         rname_second = tmp;
2666       }
2667 
2668       first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first));
2669       second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second));
2670 #endif //_LP64
2671 
2672 
2673 #ifdef X86
2674     } else if (opr->is_double_xmm()) {
2675       assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation");
2676       VMReg rname_first  = opr->as_xmm_double_reg()->as_VMReg();
2677 #  ifdef _LP64
2678       first = new LocationValue(Location::new_reg_loc(Location::dbl, rname_first));
2679       second = &_int_0_scope_value;
2680 #  else
2681       first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first));
2682       // %%% This is probably a waste but we'll keep things as they were for now
2683       if (true) {
2684         VMReg rname_second = rname_first->next();
2685         second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second));
2686       }
2687 #  endif
2688 #endif
2689 
2690     } else if (opr->is_double_fpu()) {
2691       // On SPARC, fpu_regnrLo/fpu_regnrHi represents the two halves of
2692       // the double as float registers in the native ordering. On X86,
2693       // fpu_regnrLo is a FPU stack slot whose VMReg represents
2694       // the low-order word of the double and fpu_regnrLo + 1 is the
2695       // name for the other half.  *first and *second must represent the
2696       // least and most significant words, respectively.
2697 
2698 #ifdef X86
2699       // the exact location of fpu stack values is only known
2700       // during fpu stack allocation, so the stack allocator object
2701       // must be present
2702       assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)");
2703       assert(_fpu_stack_allocator != NULL, "must be present");
2704       opr = _fpu_stack_allocator->to_fpu_stack(opr);
2705 
2706       assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrHi is used)");
2707 #endif
2708 #ifdef SPARC
2709       assert(opr->fpu_regnrLo() == opr->fpu_regnrHi() + 1, "assumed in calculation (only fpu_regnrHi is used)");
2710 #endif
2711 #ifdef ARM
2712       assert(opr->fpu_regnrHi() == opr->fpu_regnrLo() + 1, "assumed in calculation (only fpu_regnrLo is used)");
2713 #endif
2714 #ifdef PPC
2715       assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrHi is used)");
2716 #endif
2717 



2718       VMReg rname_first = frame_map()->fpu_regname(opr->fpu_regnrHi());


2719 #ifdef _LP64
2720       first = new LocationValue(Location::new_reg_loc(Location::dbl, rname_first));
2721       second = &_int_0_scope_value;
2722 #else
2723       first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first));
2724       // %%% This is probably a waste but we'll keep things as they were for now
2725       if (true) {
2726         VMReg rname_second = rname_first->next();
2727         second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second));
2728       }
2729 #endif
2730 
2731     } else {
2732       ShouldNotReachHere();
2733       first = NULL;
2734       second = NULL;
2735     }
2736 
2737     assert(first != NULL && second != NULL, "must be set");
2738     // The convention the interpreter uses is that the second local
2739     // holds the first raw word of the native double representation.
2740     // This is actually reasonable, since locals and stack arrays
2741     // grow downwards in all implementations.
2742     // (If, on some machine, the interpreter's Java locals or stack
2743     // were to grow upwards, the embedded doubles would be word-swapped.)
2744     scope_values->append(second);
2745     scope_values->append(first);
2746     return 2;
2747   }
2748 }
2749 
2750 
2751 int LinearScan::append_scope_value(int op_id, Value value, GrowableArray<ScopeValue*>* scope_values) {
2752   if (value != NULL) {
2753     LIR_Opr opr = value->operand();
2754     Constant* con = value->as_Constant();
2755 
2756     assert(con == NULL || opr->is_virtual() || opr->is_constant() || opr->is_illegal(), "asumption: Constant instructions have only constant operands (or illegal if constant is optimized away)");
2757     assert(con != NULL || opr->is_virtual(), "asumption: non-Constant instructions have only virtual operands");
2758 
2759     if (con != NULL && !con->is_pinned() && !opr->is_constant()) {
2760       // Unpinned constants may have a virtual operand for a part of the lifetime
2761       // or may be illegal when it was optimized away,
2762       // so always use a constant operand
2763       opr = LIR_OprFact::value_type(con->type());
2764     }
2765     assert(opr->is_virtual() || opr->is_constant(), "other cases not allowed here");
2766 
2767     if (opr->is_virtual()) {
2768       LIR_OpVisitState::OprMode mode = LIR_OpVisitState::inputMode;
2769 
2770       BlockBegin* block = block_of_op_with_id(op_id);
2771       if (block->number_of_sux() == 1 && op_id == block->last_lir_instruction_id()) {
2772         // generating debug information for the last instruction of a block.
2773         // if this instruction is a branch, spill moves are inserted before this branch
2774         // and so the wrong operand would be returned (spill moves at block boundaries are not
2775         // considered in the live ranges of intervals)
2776         // Solution: use the first op_id of the branch target block instead.
2777         if (block->lir()->instructions_list()->last()->as_OpBranch() != NULL) {
2778           if (block->live_out().at(opr->vreg_number())) {
2779             op_id = block->sux_at(0)->first_lir_instruction_id();
2780             mode = LIR_OpVisitState::outputMode;
2781           }
2782         }
2783       }
2784 
2785       // Get current location of operand
2786       // The operand must be live because debug information is considered when building the intervals
2787       // if the interval is not live, color_lir_opr will cause an assertion failure
2788       opr = color_lir_opr(opr, op_id, mode);
2789       assert(!has_call(op_id) || opr->is_stack() || !is_caller_save(reg_num(opr)), "can not have caller-save register operands at calls");
2790 
2791       // Append to ScopeValue array
2792       return append_scope_value_for_operand(opr, scope_values);
2793 
2794     } else {
2795       assert(value->as_Constant() != NULL, "all other instructions have only virtual operands");
2796       assert(opr->is_constant(), "operand must be constant");
2797 
2798       return append_scope_value_for_constant(opr, scope_values);
2799     }
2800   } else {
2801     // append a dummy value because real value not needed
2802     scope_values->append(&_illegal_value);
2803     return 1;
2804   }
2805 }
2806 
2807 
2808 IRScopeDebugInfo* LinearScan::compute_debug_info_for_scope(int op_id, IRScope* cur_scope, ValueStack* cur_state, ValueStack* innermost_state) {
2809   IRScopeDebugInfo* caller_debug_info = NULL;
2810 
2811   ValueStack* caller_state = cur_state->caller_state();
2812   if (caller_state != NULL) {
2813     // process recursively to compute outermost scope first
2814     caller_debug_info = compute_debug_info_for_scope(op_id, cur_scope->caller(), caller_state, innermost_state);
2815   }
2816 
2817   // initialize these to null.
2818   // If we don't need deopt info or there are no locals, expressions or monitors,
2819   // then these get recorded as no information and avoids the allocation of 0 length arrays.
2820   GrowableArray<ScopeValue*>*   locals      = NULL;
2821   GrowableArray<ScopeValue*>*   expressions = NULL;
2822   GrowableArray<MonitorValue*>* monitors    = NULL;
2823 
2824   // describe local variable values
2825   int nof_locals = cur_state->locals_size();
2826   if (nof_locals > 0) {
2827     locals = new GrowableArray<ScopeValue*>(nof_locals);
2828 
2829     int pos = 0;
2830     while (pos < nof_locals) {
2831       assert(pos < cur_state->locals_size(), "why not?");
2832 
2833       Value local = cur_state->local_at(pos);
2834       pos += append_scope_value(op_id, local, locals);
2835 
2836       assert(locals->length() == pos, "must match");
2837     }
2838     assert(locals->length() == cur_scope->method()->max_locals(), "wrong number of locals");
2839     assert(locals->length() == cur_state->locals_size(), "wrong number of locals");
2840   } else if (cur_scope->method()->max_locals() > 0) {
2841     assert(cur_state->kind() == ValueStack::EmptyExceptionState, "should be");
2842     nof_locals = cur_scope->method()->max_locals();
2843     locals = new GrowableArray<ScopeValue*>(nof_locals);
2844     for(int i = 0; i < nof_locals; i++) {
2845       locals->append(&_illegal_value);
2846     }
2847   }
2848 
2849   // describe expression stack
2850   int nof_stack = cur_state->stack_size();
2851   if (nof_stack > 0) {
2852     expressions = new GrowableArray<ScopeValue*>(nof_stack);
2853 
2854     int pos = 0;
2855     while (pos < nof_stack) {
2856       Value expression = cur_state->stack_at_inc(pos);
2857       append_scope_value(op_id, expression, expressions);
2858 
2859       assert(expressions->length() == pos, "must match");
2860     }
2861     assert(expressions->length() == cur_state->stack_size(), "wrong number of stack entries");
2862   }
2863 
2864   // describe monitors
2865   int nof_locks = cur_state->locks_size();
2866   if (nof_locks > 0) {
2867     int lock_offset = cur_state->caller_state() != NULL ? cur_state->caller_state()->total_locks_size() : 0;
2868     monitors = new GrowableArray<MonitorValue*>(nof_locks);
2869     for (int i = 0; i < nof_locks; i++) {
2870       monitors->append(location_for_monitor_index(lock_offset + i));
2871     }
2872   }
2873 
2874   return new IRScopeDebugInfo(cur_scope, cur_state->bci(), locals, expressions, monitors, caller_debug_info);
2875 }
2876 
2877 
2878 void LinearScan::compute_debug_info(CodeEmitInfo* info, int op_id) {
2879   TRACE_LINEAR_SCAN(3, tty->print_cr("creating debug information at op_id %d", op_id));
2880 
2881   IRScope* innermost_scope = info->scope();
2882   ValueStack* innermost_state = info->stack();
2883 
2884   assert(innermost_scope != NULL && innermost_state != NULL, "why is it missing?");
2885 
2886   DEBUG_ONLY(check_stack_depth(info, innermost_state->stack_size()));
2887 
2888   if (info->_scope_debug_info == NULL) {
2889     // compute debug information
2890     info->_scope_debug_info = compute_debug_info_for_scope(op_id, innermost_scope, innermost_state, innermost_state);
2891   } else {
2892     // debug information already set. Check that it is correct from the current point of view
2893     DEBUG_ONLY(assert_equal(info->_scope_debug_info, compute_debug_info_for_scope(op_id, innermost_scope, innermost_state, innermost_state)));
2894   }
2895 }
2896 
2897 
2898 void LinearScan::assign_reg_num(LIR_OpList* instructions, IntervalWalker* iw) {
2899   LIR_OpVisitState visitor;
2900   int num_inst = instructions->length();
2901   bool has_dead = false;
2902 
2903   for (int j = 0; j < num_inst; j++) {
2904     LIR_Op* op = instructions->at(j);
2905     if (op == NULL) {  // this can happen when spill-moves are removed in eliminate_spill_moves
2906       has_dead = true;
2907       continue;
2908     }
2909     int op_id = op->id();
2910 
2911     // visit instruction to get list of operands
2912     visitor.visit(op);
2913 
2914     // iterate all modes of the visitor and process all virtual operands
2915     for_each_visitor_mode(mode) {
2916       int n = visitor.opr_count(mode);
2917       for (int k = 0; k < n; k++) {
2918         LIR_Opr opr = visitor.opr_at(mode, k);
2919         if (opr->is_virtual_register()) {
2920           visitor.set_opr_at(mode, k, color_lir_opr(opr, op_id, mode));
2921         }
2922       }
2923     }
2924 
2925     if (visitor.info_count() > 0) {
2926       // exception handling
2927       if (compilation()->has_exception_handlers()) {
2928         XHandlers* xhandlers = visitor.all_xhandler();
2929         int n = xhandlers->length();
2930         for (int k = 0; k < n; k++) {
2931           XHandler* handler = xhandlers->handler_at(k);
2932           if (handler->entry_code() != NULL) {
2933             assign_reg_num(handler->entry_code()->instructions_list(), NULL);
2934           }
2935         }
2936       } else {
2937         assert(visitor.all_xhandler()->length() == 0, "missed exception handler");
2938       }
2939 
2940       // compute oop map
2941       assert(iw != NULL, "needed for compute_oop_map");
2942       compute_oop_map(iw, visitor, op);
2943 
2944       // compute debug information
2945       if (!use_fpu_stack_allocation()) {
2946         // compute debug information if fpu stack allocation is not needed.
2947         // when fpu stack allocation is needed, the debug information can not
2948         // be computed here because the exact location of fpu operands is not known
2949         // -> debug information is created inside the fpu stack allocator
2950         int n = visitor.info_count();
2951         for (int k = 0; k < n; k++) {
2952           compute_debug_info(visitor.info_at(k), op_id);
2953         }
2954       }
2955     }
2956 
2957 #ifdef ASSERT
2958     // make sure we haven't made the op invalid.
2959     op->verify();
2960 #endif
2961 
2962     // remove useless moves
2963     if (op->code() == lir_move) {
2964       assert(op->as_Op1() != NULL, "move must be LIR_Op1");
2965       LIR_Op1* move = (LIR_Op1*)op;
2966       LIR_Opr src = move->in_opr();
2967       LIR_Opr dst = move->result_opr();
2968       if (dst == src ||
2969           !dst->is_pointer() && !src->is_pointer() &&
2970           src->is_same_register(dst)) {
2971         instructions->at_put(j, NULL);
2972         has_dead = true;
2973       }
2974     }
2975   }
2976 
2977   if (has_dead) {
2978     // iterate all instructions of the block and remove all null-values.
2979     int insert_point = 0;
2980     for (int j = 0; j < num_inst; j++) {
2981       LIR_Op* op = instructions->at(j);
2982       if (op != NULL) {
2983         if (insert_point != j) {
2984           instructions->at_put(insert_point, op);
2985         }
2986         insert_point++;
2987       }
2988     }
2989     instructions->truncate(insert_point);
2990   }
2991 }
2992 
2993 void LinearScan::assign_reg_num() {
2994   TIME_LINEAR_SCAN(timer_assign_reg_num);
2995 
2996   init_compute_debug_info();
2997   IntervalWalker* iw = init_compute_oop_maps();
2998 
2999   int num_blocks = block_count();
3000   for (int i = 0; i < num_blocks; i++) {
3001     BlockBegin* block = block_at(i);
3002     assign_reg_num(block->lir()->instructions_list(), iw);
3003   }
3004 }
3005 
3006 
3007 void LinearScan::do_linear_scan() {
3008   NOT_PRODUCT(_total_timer.begin_method());
3009 
3010   number_instructions();
3011 
3012   NOT_PRODUCT(print_lir(1, "Before Register Allocation"));
3013 
3014   compute_local_live_sets();
3015   compute_global_live_sets();
3016   CHECK_BAILOUT();
3017 
3018   build_intervals();
3019   CHECK_BAILOUT();
3020   sort_intervals_before_allocation();
3021 
3022   NOT_PRODUCT(print_intervals("Before Register Allocation"));
3023   NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_before_alloc));
3024 
3025   allocate_registers();
3026   CHECK_BAILOUT();
3027 
3028   resolve_data_flow();
3029   if (compilation()->has_exception_handlers()) {
3030     resolve_exception_handlers();
3031   }
3032   // fill in number of spill slots into frame_map
3033   propagate_spill_slots();
3034   CHECK_BAILOUT();
3035 
3036   NOT_PRODUCT(print_intervals("After Register Allocation"));
3037   NOT_PRODUCT(print_lir(2, "LIR after register allocation:"));
3038 
3039   sort_intervals_after_allocation();
3040 
3041   DEBUG_ONLY(verify());
3042 
3043   eliminate_spill_moves();
3044   assign_reg_num();
3045   CHECK_BAILOUT();
3046 
3047   NOT_PRODUCT(print_lir(2, "LIR after assignment of register numbers:"));
3048   NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_after_asign));
3049 
3050   { TIME_LINEAR_SCAN(timer_allocate_fpu_stack);
3051 
3052     if (use_fpu_stack_allocation()) {
3053       allocate_fpu_stack(); // Only has effect on Intel
3054       NOT_PRODUCT(print_lir(2, "LIR after FPU stack allocation:"));
3055     }
3056   }
3057 
3058   { TIME_LINEAR_SCAN(timer_optimize_lir);
3059 
3060     EdgeMoveOptimizer::optimize(ir()->code());
3061     ControlFlowOptimizer::optimize(ir()->code());
3062     // check that cfg is still correct after optimizations
3063     ir()->verify();
3064   }
3065 
3066   NOT_PRODUCT(print_lir(1, "Before Code Generation", false));
3067   NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_final));
3068   NOT_PRODUCT(_total_timer.end_method(this));
3069 }
3070 
3071 
3072 // ********** Printing functions
3073 
3074 #ifndef PRODUCT
3075 
3076 void LinearScan::print_timers(double total) {
3077   _total_timer.print(total);
3078 }
3079 
3080 void LinearScan::print_statistics() {
3081   _stat_before_alloc.print("before allocation");
3082   _stat_after_asign.print("after assignment of register");
3083   _stat_final.print("after optimization");
3084 }
3085 
3086 void LinearScan::print_bitmap(BitMap& b) {
3087   for (unsigned int i = 0; i < b.size(); i++) {
3088     if (b.at(i)) tty->print("%d ", i);
3089   }
3090   tty->cr();
3091 }
3092 
3093 void LinearScan::print_intervals(const char* label) {
3094   if (TraceLinearScanLevel >= 1) {
3095     int i;
3096     tty->cr();
3097     tty->print_cr("%s", label);
3098 
3099     for (i = 0; i < interval_count(); i++) {
3100       Interval* interval = interval_at(i);
3101       if (interval != NULL) {
3102         interval->print();
3103       }
3104     }
3105 
3106     tty->cr();
3107     tty->print_cr("--- Basic Blocks ---");
3108     for (i = 0; i < block_count(); i++) {
3109       BlockBegin* block = block_at(i);
3110       tty->print("B%d [%d, %d, %d, %d] ", block->block_id(), block->first_lir_instruction_id(), block->last_lir_instruction_id(), block->loop_index(), block->loop_depth());
3111     }
3112     tty->cr();
3113     tty->cr();
3114   }
3115 
3116   if (PrintCFGToFile) {
3117     CFGPrinter::print_intervals(&_intervals, label);
3118   }
3119 }
3120 
3121 void LinearScan::print_lir(int level, const char* label, bool hir_valid) {
3122   if (TraceLinearScanLevel >= level) {
3123     tty->cr();
3124     tty->print_cr("%s", label);
3125     print_LIR(ir()->linear_scan_order());
3126     tty->cr();
3127   }
3128 
3129   if (level == 1 && PrintCFGToFile) {
3130     CFGPrinter::print_cfg(ir()->linear_scan_order(), label, hir_valid, true);
3131   }
3132 }
3133 
3134 #endif //PRODUCT
3135 
3136 
3137 // ********** verification functions for allocation
3138 // (check that all intervals have a correct register and that no registers are overwritten)
3139 #ifdef ASSERT
3140 
3141 void LinearScan::verify() {
3142   TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying intervals ******************************************"));
3143   verify_intervals();
3144 
3145   TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying that no oops are in fixed intervals ****************"));
3146   verify_no_oops_in_fixed_intervals();
3147 
3148   TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying that unpinned constants are not alive across block boundaries"));
3149   verify_constants();
3150 
3151   TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying register allocation ********************************"));
3152   verify_registers();
3153 
3154   TRACE_LINEAR_SCAN(2, tty->print_cr("********* no errors found **********************************************"));
3155 }
3156 
3157 void LinearScan::verify_intervals() {
3158   int len = interval_count();
3159   bool has_error = false;
3160 
3161   for (int i = 0; i < len; i++) {
3162     Interval* i1 = interval_at(i);
3163     if (i1 == NULL) continue;
3164 
3165     i1->check_split_children();
3166 
3167     if (i1->reg_num() != i) {
3168       tty->print_cr("Interval %d is on position %d in list", i1->reg_num(), i); i1->print(); tty->cr();
3169       has_error = true;
3170     }
3171 
3172     if (i1->reg_num() >= LIR_OprDesc::vreg_base && i1->type() == T_ILLEGAL) {
3173       tty->print_cr("Interval %d has no type assigned", i1->reg_num()); i1->print(); tty->cr();
3174       has_error = true;
3175     }
3176 
3177     if (i1->assigned_reg() == any_reg) {
3178       tty->print_cr("Interval %d has no register assigned", i1->reg_num()); i1->print(); tty->cr();
3179       has_error = true;
3180     }
3181 
3182     if (i1->assigned_reg() == i1->assigned_regHi()) {
3183       tty->print_cr("Interval %d: low and high register equal", i1->reg_num()); i1->print(); tty->cr();
3184       has_error = true;
3185     }
3186 
3187     if (!is_processed_reg_num(i1->assigned_reg())) {
3188       tty->print_cr("Can not have an Interval for an ignored register"); i1->print(); tty->cr();
3189       has_error = true;
3190     }
3191 
3192     if (i1->first() == Range::end()) {
3193       tty->print_cr("Interval %d has no Range", i1->reg_num()); i1->print(); tty->cr();
3194       has_error = true;
3195     }
3196 
3197     for (Range* r = i1->first(); r != Range::end(); r = r->next()) {
3198       if (r->from() >= r->to()) {
3199         tty->print_cr("Interval %d has zero length range", i1->reg_num()); i1->print(); tty->cr();
3200         has_error = true;
3201       }
3202     }
3203 
3204     for (int j = i + 1; j < len; j++) {
3205       Interval* i2 = interval_at(j);
3206       if (i2 == NULL) continue;
3207 
3208       // special intervals that are created in MoveResolver
3209       // -> ignore them because the range information has no meaning there
3210       if (i1->from() == 1 && i1->to() == 2) continue;
3211       if (i2->from() == 1 && i2->to() == 2) continue;
3212 
3213       int r1 = i1->assigned_reg();
3214       int r1Hi = i1->assigned_regHi();
3215       int r2 = i2->assigned_reg();
3216       int r2Hi = i2->assigned_regHi();
3217       if (i1->intersects(i2) && (r1 == r2 || r1 == r2Hi || (r1Hi != any_reg && (r1Hi == r2 || r1Hi == r2Hi)))) {
3218         tty->print_cr("Intervals %d and %d overlap and have the same register assigned", i1->reg_num(), i2->reg_num());
3219         i1->print(); tty->cr();
3220         i2->print(); tty->cr();
3221         has_error = true;
3222       }
3223     }
3224   }
3225 
3226   assert(has_error == false, "register allocation invalid");
3227 }
3228 
3229 
3230 void LinearScan::verify_no_oops_in_fixed_intervals() {
3231   Interval* fixed_intervals;
3232   Interval* other_intervals;
3233   create_unhandled_lists(&fixed_intervals, &other_intervals, is_precolored_cpu_interval, NULL);
3234 
3235   // to ensure a walking until the last instruction id, add a dummy interval
3236   // with a high operation id
3237   other_intervals = new Interval(any_reg);
3238   other_intervals->add_range(max_jint - 2, max_jint - 1);
3239   IntervalWalker* iw = new IntervalWalker(this, fixed_intervals, other_intervals);
3240 
3241   LIR_OpVisitState visitor;
3242   for (int i = 0; i < block_count(); i++) {
3243     BlockBegin* block = block_at(i);
3244 
3245     LIR_OpList* instructions = block->lir()->instructions_list();
3246 
3247     for (int j = 0; j < instructions->length(); j++) {
3248       LIR_Op* op = instructions->at(j);
3249       int op_id = op->id();
3250 
3251       visitor.visit(op);
3252 
3253       if (visitor.info_count() > 0) {
3254         iw->walk_before(op->id());
3255         bool check_live = true;
3256         if (op->code() == lir_move) {
3257           LIR_Op1* move = (LIR_Op1*)op;
3258           check_live = (move->patch_code() == lir_patch_none);
3259         }
3260         LIR_OpBranch* branch = op->as_OpBranch();
3261         if (branch != NULL && branch->stub() != NULL && branch->stub()->is_exception_throw_stub()) {
3262           // Don't bother checking the stub in this case since the
3263           // exception stub will never return to normal control flow.
3264           check_live = false;
3265         }
3266 
3267         // Make sure none of the fixed registers is live across an
3268         // oopmap since we can't handle that correctly.
3269         if (check_live) {
3270           for (Interval* interval = iw->active_first(fixedKind);
3271                interval != Interval::end();
3272                interval = interval->next()) {
3273             if (interval->current_to() > op->id() + 1) {
3274               // This interval is live out of this op so make sure
3275               // that this interval represents some value that's
3276               // referenced by this op either as an input or output.
3277               bool ok = false;
3278               for_each_visitor_mode(mode) {
3279                 int n = visitor.opr_count(mode);
3280                 for (int k = 0; k < n; k++) {
3281                   LIR_Opr opr = visitor.opr_at(mode, k);
3282                   if (opr->is_fixed_cpu()) {
3283                     if (interval_at(reg_num(opr)) == interval) {
3284                       ok = true;
3285                       break;
3286                     }
3287                     int hi = reg_numHi(opr);
3288                     if (hi != -1 && interval_at(hi) == interval) {
3289                       ok = true;
3290                       break;
3291                     }
3292                   }
3293                 }
3294               }
3295               assert(ok, "fixed intervals should never be live across an oopmap point");
3296             }
3297           }
3298         }
3299       }
3300 
3301       // oop-maps at calls do not contain registers, so check is not needed
3302       if (!visitor.has_call()) {
3303 
3304         for_each_visitor_mode(mode) {
3305           int n = visitor.opr_count(mode);
3306           for (int k = 0; k < n; k++) {
3307             LIR_Opr opr = visitor.opr_at(mode, k);
3308 
3309             if (opr->is_fixed_cpu() && opr->is_oop()) {
3310               // operand is a non-virtual cpu register and contains an oop
3311               TRACE_LINEAR_SCAN(4, op->print_on(tty); tty->print("checking operand "); opr->print(); tty->cr());
3312 
3313               Interval* interval = interval_at(reg_num(opr));
3314               assert(interval != NULL, "no interval");
3315 
3316               if (mode == LIR_OpVisitState::inputMode) {
3317                 if (interval->to() >= op_id + 1) {
3318                   assert(interval->to() < op_id + 2 ||
3319                          interval->has_hole_between(op_id, op_id + 2),
3320                          "oop input operand live after instruction");
3321                 }
3322               } else if (mode == LIR_OpVisitState::outputMode) {
3323                 if (interval->from() <= op_id - 1) {
3324                   assert(interval->has_hole_between(op_id - 1, op_id),
3325                          "oop input operand live after instruction");
3326                 }
3327               }
3328             }
3329           }
3330         }
3331       }
3332     }
3333   }
3334 }
3335 
3336 
3337 void LinearScan::verify_constants() {
3338   int num_regs = num_virtual_regs();
3339   int size = live_set_size();
3340   int num_blocks = block_count();
3341 
3342   for (int i = 0; i < num_blocks; i++) {
3343     BlockBegin* block = block_at(i);
3344     BitMap live_at_edge = block->live_in();
3345 
3346     // visit all registers where the live_at_edge bit is set
3347     for (int r = (int)live_at_edge.get_next_one_offset(0, size); r < size; r = (int)live_at_edge.get_next_one_offset(r + 1, size)) {
3348       TRACE_LINEAR_SCAN(4, tty->print("checking interval %d of block B%d", r, block->block_id()));
3349 
3350       Value value = gen()->instruction_for_vreg(r);
3351 
3352       assert(value != NULL, "all intervals live across block boundaries must have Value");
3353       assert(value->operand()->is_register() && value->operand()->is_virtual(), "value must have virtual operand");
3354       assert(value->operand()->vreg_number() == r, "register number must match");
3355       // TKR assert(value->as_Constant() == NULL || value->is_pinned(), "only pinned constants can be alive accross block boundaries");
3356     }
3357   }
3358 }
3359 
3360 
3361 class RegisterVerifier: public StackObj {
3362  private:
3363   LinearScan*   _allocator;
3364   BlockList     _work_list;      // all blocks that must be processed
3365   IntervalsList _saved_states;   // saved information of previous check
3366 
3367   // simplified access to methods of LinearScan
3368   Compilation*  compilation() const              { return _allocator->compilation(); }
3369   Interval*     interval_at(int reg_num) const   { return _allocator->interval_at(reg_num); }
3370   int           reg_num(LIR_Opr opr) const       { return _allocator->reg_num(opr); }
3371 
3372   // currently, only registers are processed
3373   int           state_size()                     { return LinearScan::nof_regs; }
3374 
3375   // accessors
3376   IntervalList* state_for_block(BlockBegin* block) { return _saved_states.at(block->block_id()); }
3377   void          set_state_for_block(BlockBegin* block, IntervalList* saved_state) { _saved_states.at_put(block->block_id(), saved_state); }
3378   void          add_to_work_list(BlockBegin* block) { if (!_work_list.contains(block)) _work_list.append(block); }
3379 
3380   // helper functions
3381   IntervalList* copy(IntervalList* input_state);
3382   void          state_put(IntervalList* input_state, int reg, Interval* interval);
3383   bool          check_state(IntervalList* input_state, int reg, Interval* interval);
3384 
3385   void process_block(BlockBegin* block);
3386   void process_xhandler(XHandler* xhandler, IntervalList* input_state);
3387   void process_successor(BlockBegin* block, IntervalList* input_state);
3388   void process_operations(LIR_List* ops, IntervalList* input_state);
3389 
3390  public:
3391   RegisterVerifier(LinearScan* allocator)
3392     : _allocator(allocator)
3393     , _work_list(16)
3394     , _saved_states(BlockBegin::number_of_blocks(), NULL)
3395   { }
3396 
3397   void verify(BlockBegin* start);
3398 };
3399 
3400 
3401 // entry function from LinearScan that starts the verification
3402 void LinearScan::verify_registers() {
3403   RegisterVerifier verifier(this);
3404   verifier.verify(block_at(0));
3405 }
3406 
3407 
3408 void RegisterVerifier::verify(BlockBegin* start) {
3409   // setup input registers (method arguments) for first block
3410   IntervalList* input_state = new IntervalList(state_size(), NULL);
3411   CallingConvention* args = compilation()->frame_map()->incoming_arguments();
3412   for (int n = 0; n < args->length(); n++) {
3413     LIR_Opr opr = args->at(n);
3414     if (opr->is_register()) {
3415       Interval* interval = interval_at(reg_num(opr));
3416 
3417       if (interval->assigned_reg() < state_size()) {
3418         input_state->at_put(interval->assigned_reg(), interval);
3419       }
3420       if (interval->assigned_regHi() != LinearScan::any_reg && interval->assigned_regHi() < state_size()) {
3421         input_state->at_put(interval->assigned_regHi(), interval);
3422       }
3423     }
3424   }
3425 
3426   set_state_for_block(start, input_state);
3427   add_to_work_list(start);
3428 
3429   // main loop for verification
3430   do {
3431     BlockBegin* block = _work_list.at(0);
3432     _work_list.remove_at(0);
3433 
3434     process_block(block);
3435   } while (!_work_list.is_empty());
3436 }
3437 
3438 void RegisterVerifier::process_block(BlockBegin* block) {
3439   TRACE_LINEAR_SCAN(2, tty->cr(); tty->print_cr("process_block B%d", block->block_id()));
3440 
3441   // must copy state because it is modified
3442   IntervalList* input_state = copy(state_for_block(block));
3443 
3444   if (TraceLinearScanLevel >= 4) {
3445     tty->print_cr("Input-State of intervals:");
3446     tty->print("    ");
3447     for (int i = 0; i < state_size(); i++) {
3448       if (input_state->at(i) != NULL) {
3449         tty->print(" %4d", input_state->at(i)->reg_num());
3450       } else {
3451         tty->print("   __");
3452       }
3453     }
3454     tty->cr();
3455     tty->cr();
3456   }
3457 
3458   // process all operations of the block
3459   process_operations(block->lir(), input_state);
3460 
3461   // iterate all successors
3462   for (int i = 0; i < block->number_of_sux(); i++) {
3463     process_successor(block->sux_at(i), input_state);
3464   }
3465 }
3466 
3467 void RegisterVerifier::process_xhandler(XHandler* xhandler, IntervalList* input_state) {
3468   TRACE_LINEAR_SCAN(2, tty->print_cr("process_xhandler B%d", xhandler->entry_block()->block_id()));
3469 
3470   // must copy state because it is modified
3471   input_state = copy(input_state);
3472 
3473   if (xhandler->entry_code() != NULL) {
3474     process_operations(xhandler->entry_code(), input_state);
3475   }
3476   process_successor(xhandler->entry_block(), input_state);
3477 }
3478 
3479 void RegisterVerifier::process_successor(BlockBegin* block, IntervalList* input_state) {
3480   IntervalList* saved_state = state_for_block(block);
3481 
3482   if (saved_state != NULL) {
3483     // this block was already processed before.
3484     // check if new input_state is consistent with saved_state
3485 
3486     bool saved_state_correct = true;
3487     for (int i = 0; i < state_size(); i++) {
3488       if (input_state->at(i) != saved_state->at(i)) {
3489         // current input_state and previous saved_state assume a different
3490         // interval in this register -> assume that this register is invalid
3491         if (saved_state->at(i) != NULL) {
3492           // invalidate old calculation only if it assumed that
3493           // register was valid. when the register was already invalid,
3494           // then the old calculation was correct.
3495           saved_state_correct = false;
3496           saved_state->at_put(i, NULL);
3497 
3498           TRACE_LINEAR_SCAN(4, tty->print_cr("process_successor B%d: invalidating slot %d", block->block_id(), i));
3499         }
3500       }
3501     }
3502 
3503     if (saved_state_correct) {
3504       // already processed block with correct input_state
3505       TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: previous visit already correct", block->block_id()));
3506     } else {
3507       // must re-visit this block
3508       TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: must re-visit because input state changed", block->block_id()));
3509       add_to_work_list(block);
3510     }
3511 
3512   } else {
3513     // block was not processed before, so set initial input_state
3514     TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: initial visit", block->block_id()));
3515 
3516     set_state_for_block(block, copy(input_state));
3517     add_to_work_list(block);
3518   }
3519 }
3520 
3521 
3522 IntervalList* RegisterVerifier::copy(IntervalList* input_state) {
3523   IntervalList* copy_state = new IntervalList(input_state->length());
3524   copy_state->push_all(input_state);
3525   return copy_state;
3526 }
3527 
3528 void RegisterVerifier::state_put(IntervalList* input_state, int reg, Interval* interval) {
3529   if (reg != LinearScan::any_reg && reg < state_size()) {
3530     if (interval != NULL) {
3531       TRACE_LINEAR_SCAN(4, tty->print_cr("        reg[%d] = %d", reg, interval->reg_num()));
3532     } else if (input_state->at(reg) != NULL) {
3533       TRACE_LINEAR_SCAN(4, tty->print_cr("        reg[%d] = NULL", reg));
3534     }
3535 
3536     input_state->at_put(reg, interval);
3537   }
3538 }
3539 
3540 bool RegisterVerifier::check_state(IntervalList* input_state, int reg, Interval* interval) {
3541   if (reg != LinearScan::any_reg && reg < state_size()) {
3542     if (input_state->at(reg) != interval) {
3543       tty->print_cr("!! Error in register allocation: register %d does not contain interval %d", reg, interval->reg_num());
3544       return true;
3545     }
3546   }
3547   return false;
3548 }
3549 
3550 void RegisterVerifier::process_operations(LIR_List* ops, IntervalList* input_state) {
3551   // visit all instructions of the block
3552   LIR_OpVisitState visitor;
3553   bool has_error = false;
3554 
3555   for (int i = 0; i < ops->length(); i++) {
3556     LIR_Op* op = ops->at(i);
3557     visitor.visit(op);
3558 
3559     TRACE_LINEAR_SCAN(4, op->print_on(tty));
3560 
3561     // check if input operands are correct
3562     int j;
3563     int n = visitor.opr_count(LIR_OpVisitState::inputMode);
3564     for (j = 0; j < n; j++) {
3565       LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, j);
3566       if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) {
3567         Interval* interval = interval_at(reg_num(opr));
3568         if (op->id() != -1) {
3569           interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::inputMode);
3570         }
3571 
3572         has_error |= check_state(input_state, interval->assigned_reg(),   interval->split_parent());
3573         has_error |= check_state(input_state, interval->assigned_regHi(), interval->split_parent());
3574 
3575         // When an operand is marked with is_last_use, then the fpu stack allocator
3576         // removes the register from the fpu stack -> the register contains no value
3577         if (opr->is_last_use()) {
3578           state_put(input_state, interval->assigned_reg(),   NULL);
3579           state_put(input_state, interval->assigned_regHi(), NULL);
3580         }
3581       }
3582     }
3583 
3584     // invalidate all caller save registers at calls
3585     if (visitor.has_call()) {
3586       for (j = 0; j < FrameMap::nof_caller_save_cpu_regs(); j++) {
3587         state_put(input_state, reg_num(FrameMap::caller_save_cpu_reg_at(j)), NULL);
3588       }
3589       for (j = 0; j < FrameMap::nof_caller_save_fpu_regs; j++) {
3590         state_put(input_state, reg_num(FrameMap::caller_save_fpu_reg_at(j)), NULL);
3591       }
3592 
3593 #ifdef X86
3594       for (j = 0; j < FrameMap::nof_caller_save_xmm_regs; j++) {
3595         state_put(input_state, reg_num(FrameMap::caller_save_xmm_reg_at(j)), NULL);
3596       }
3597 #endif
3598     }
3599 
3600     // process xhandler before output and temp operands
3601     XHandlers* xhandlers = visitor.all_xhandler();
3602     n = xhandlers->length();
3603     for (int k = 0; k < n; k++) {
3604       process_xhandler(xhandlers->handler_at(k), input_state);
3605     }
3606 
3607     // set temp operands (some operations use temp operands also as output operands, so can't set them NULL)
3608     n = visitor.opr_count(LIR_OpVisitState::tempMode);
3609     for (j = 0; j < n; j++) {
3610       LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, j);
3611       if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) {
3612         Interval* interval = interval_at(reg_num(opr));
3613         if (op->id() != -1) {
3614           interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::tempMode);
3615         }
3616 
3617         state_put(input_state, interval->assigned_reg(),   interval->split_parent());
3618         state_put(input_state, interval->assigned_regHi(), interval->split_parent());
3619       }
3620     }
3621 
3622     // set output operands
3623     n = visitor.opr_count(LIR_OpVisitState::outputMode);
3624     for (j = 0; j < n; j++) {
3625       LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, j);
3626       if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) {
3627         Interval* interval = interval_at(reg_num(opr));
3628         if (op->id() != -1) {
3629           interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::outputMode);
3630         }
3631 
3632         state_put(input_state, interval->assigned_reg(),   interval->split_parent());
3633         state_put(input_state, interval->assigned_regHi(), interval->split_parent());
3634       }
3635     }
3636   }
3637   assert(has_error == false, "Error in register allocation");
3638 }
3639 
3640 #endif // ASSERT
3641 
3642 
3643 
3644 // **** Implementation of MoveResolver ******************************
3645 
3646 MoveResolver::MoveResolver(LinearScan* allocator) :
3647   _allocator(allocator),
3648   _multiple_reads_allowed(false),
3649   _mapping_from(8),
3650   _mapping_from_opr(8),
3651   _mapping_to(8),
3652   _insert_list(NULL),
3653   _insert_idx(-1),
3654   _insertion_buffer()
3655 {
3656   for (int i = 0; i < LinearScan::nof_regs; i++) {
3657     _register_blocked[i] = 0;
3658   }
3659   DEBUG_ONLY(check_empty());
3660 }
3661 
3662 
3663 #ifdef ASSERT
3664 
3665 void MoveResolver::check_empty() {
3666   assert(_mapping_from.length() == 0 && _mapping_from_opr.length() == 0 && _mapping_to.length() == 0, "list must be empty before and after processing");
3667   for (int i = 0; i < LinearScan::nof_regs; i++) {
3668     assert(register_blocked(i) == 0, "register map must be empty before and after processing");
3669   }
3670   assert(_multiple_reads_allowed == false, "must have default value");
3671 }
3672 
3673 void MoveResolver::verify_before_resolve() {
3674   assert(_mapping_from.length() == _mapping_from_opr.length(), "length must be equal");
3675   assert(_mapping_from.length() == _mapping_to.length(), "length must be equal");
3676   assert(_insert_list != NULL && _insert_idx != -1, "insert position not set");
3677 
3678   int i, j;
3679   if (!_multiple_reads_allowed) {
3680     for (i = 0; i < _mapping_from.length(); i++) {
3681       for (j = i + 1; j < _mapping_from.length(); j++) {
3682         assert(_mapping_from.at(i) == NULL || _mapping_from.at(i) != _mapping_from.at(j), "cannot read from same interval twice");
3683       }
3684     }
3685   }
3686 
3687   for (i = 0; i < _mapping_to.length(); i++) {
3688     for (j = i + 1; j < _mapping_to.length(); j++) {
3689       assert(_mapping_to.at(i) != _mapping_to.at(j), "cannot write to same interval twice");
3690     }
3691   }
3692 
3693 
3694   BitMap used_regs(LinearScan::nof_regs + allocator()->frame_map()->argcount() + allocator()->max_spills());
3695   used_regs.clear();
3696   if (!_multiple_reads_allowed) {
3697     for (i = 0; i < _mapping_from.length(); i++) {
3698       Interval* it = _mapping_from.at(i);
3699       if (it != NULL) {
3700         assert(!used_regs.at(it->assigned_reg()), "cannot read from same register twice");
3701         used_regs.set_bit(it->assigned_reg());
3702 
3703         if (it->assigned_regHi() != LinearScan::any_reg) {
3704           assert(!used_regs.at(it->assigned_regHi()), "cannot read from same register twice");
3705           used_regs.set_bit(it->assigned_regHi());
3706         }
3707       }
3708     }
3709   }
3710 
3711   used_regs.clear();
3712   for (i = 0; i < _mapping_to.length(); i++) {
3713     Interval* it = _mapping_to.at(i);
3714     assert(!used_regs.at(it->assigned_reg()), "cannot write to same register twice");
3715     used_regs.set_bit(it->assigned_reg());
3716 
3717     if (it->assigned_regHi() != LinearScan::any_reg) {
3718       assert(!used_regs.at(it->assigned_regHi()), "cannot write to same register twice");
3719       used_regs.set_bit(it->assigned_regHi());
3720     }
3721   }
3722 
3723   used_regs.clear();
3724   for (i = 0; i < _mapping_from.length(); i++) {
3725     Interval* it = _mapping_from.at(i);
3726     if (it != NULL && it->assigned_reg() >= LinearScan::nof_regs) {
3727       used_regs.set_bit(it->assigned_reg());
3728     }
3729   }
3730   for (i = 0; i < _mapping_to.length(); i++) {
3731     Interval* it = _mapping_to.at(i);
3732     assert(!used_regs.at(it->assigned_reg()) || it->assigned_reg() == _mapping_from.at(i)->assigned_reg(), "stack slots used in _mapping_from must be disjoint to _mapping_to");
3733   }
3734 }
3735 
3736 #endif // ASSERT
3737 
3738 
3739 // mark assigned_reg and assigned_regHi of the interval as blocked
3740 void MoveResolver::block_registers(Interval* it) {
3741   int reg = it->assigned_reg();
3742   if (reg < LinearScan::nof_regs) {
3743     assert(_multiple_reads_allowed || register_blocked(reg) == 0, "register already marked as used");
3744     set_register_blocked(reg, 1);
3745   }
3746   reg = it->assigned_regHi();
3747   if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) {
3748     assert(_multiple_reads_allowed || register_blocked(reg) == 0, "register already marked as used");
3749     set_register_blocked(reg, 1);
3750   }
3751 }
3752 
3753 // mark assigned_reg and assigned_regHi of the interval as unblocked
3754 void MoveResolver::unblock_registers(Interval* it) {
3755   int reg = it->assigned_reg();
3756   if (reg < LinearScan::nof_regs) {
3757     assert(register_blocked(reg) > 0, "register already marked as unused");
3758     set_register_blocked(reg, -1);
3759   }
3760   reg = it->assigned_regHi();
3761   if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) {
3762     assert(register_blocked(reg) > 0, "register already marked as unused");
3763     set_register_blocked(reg, -1);
3764   }
3765 }
3766 
3767 // check if assigned_reg and assigned_regHi of the to-interval are not blocked (or only blocked by from)
3768 bool MoveResolver::save_to_process_move(Interval* from, Interval* to) {
3769   int from_reg = -1;
3770   int from_regHi = -1;
3771   if (from != NULL) {
3772     from_reg = from->assigned_reg();
3773     from_regHi = from->assigned_regHi();
3774   }
3775 
3776   int reg = to->assigned_reg();
3777   if (reg < LinearScan::nof_regs) {
3778     if (register_blocked(reg) > 1 || (register_blocked(reg) == 1 && reg != from_reg && reg != from_regHi)) {
3779       return false;
3780     }
3781   }
3782   reg = to->assigned_regHi();
3783   if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) {
3784     if (register_blocked(reg) > 1 || (register_blocked(reg) == 1 && reg != from_reg && reg != from_regHi)) {
3785       return false;
3786     }
3787   }
3788 
3789   return true;
3790 }
3791 
3792 
3793 void MoveResolver::create_insertion_buffer(LIR_List* list) {
3794   assert(!_insertion_buffer.initialized(), "overwriting existing buffer");
3795   _insertion_buffer.init(list);
3796 }
3797 
3798 void MoveResolver::append_insertion_buffer() {
3799   if (_insertion_buffer.initialized()) {
3800     _insertion_buffer.lir_list()->append(&_insertion_buffer);
3801   }
3802   assert(!_insertion_buffer.initialized(), "must be uninitialized now");
3803 
3804   _insert_list = NULL;
3805   _insert_idx = -1;
3806 }
3807 
3808 void MoveResolver::insert_move(Interval* from_interval, Interval* to_interval) {
3809   assert(from_interval->reg_num() != to_interval->reg_num(), "from and to interval equal");
3810   assert(from_interval->type() == to_interval->type(), "move between different types");
3811   assert(_insert_list != NULL && _insert_idx != -1, "must setup insert position first");
3812   assert(_insertion_buffer.lir_list() == _insert_list, "wrong insertion buffer");
3813 
3814   LIR_Opr from_opr = LIR_OprFact::virtual_register(from_interval->reg_num(), from_interval->type());
3815   LIR_Opr to_opr = LIR_OprFact::virtual_register(to_interval->reg_num(), to_interval->type());
3816 
3817   if (!_multiple_reads_allowed) {
3818     // the last_use flag is an optimization for FPU stack allocation. When the same
3819     // input interval is used in more than one move, then it is too difficult to determine
3820     // if this move is really the last use.
3821     from_opr = from_opr->make_last_use();
3822   }
3823   _insertion_buffer.move(_insert_idx, from_opr, to_opr);
3824 
3825   TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: inserted move from register %d (%d, %d) to %d (%d, %d)", from_interval->reg_num(), from_interval->assigned_reg(), from_interval->assigned_regHi(), to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
3826 }
3827 
3828 void MoveResolver::insert_move(LIR_Opr from_opr, Interval* to_interval) {
3829   assert(from_opr->type() == to_interval->type(), "move between different types");
3830   assert(_insert_list != NULL && _insert_idx != -1, "must setup insert position first");
3831   assert(_insertion_buffer.lir_list() == _insert_list, "wrong insertion buffer");
3832 
3833   LIR_Opr to_opr = LIR_OprFact::virtual_register(to_interval->reg_num(), to_interval->type());
3834   _insertion_buffer.move(_insert_idx, from_opr, to_opr);
3835 
3836   TRACE_LINEAR_SCAN(4, tty->print("MoveResolver: inserted move from constant "); from_opr->print(); tty->print_cr("  to %d (%d, %d)", to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
3837 }
3838 
3839 
3840 void MoveResolver::resolve_mappings() {
3841   TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: resolving mappings for Block B%d, index %d", _insert_list->block() != NULL ? _insert_list->block()->block_id() : -1, _insert_idx));
3842   DEBUG_ONLY(verify_before_resolve());
3843 
3844   // Block all registers that are used as input operands of a move.
3845   // When a register is blocked, no move to this register is emitted.
3846   // This is necessary for detecting cycles in moves.
3847   int i;
3848   for (i = _mapping_from.length() - 1; i >= 0; i--) {
3849     Interval* from_interval = _mapping_from.at(i);
3850     if (from_interval != NULL) {
3851       block_registers(from_interval);
3852     }
3853   }
3854 
3855   int spill_candidate = -1;
3856   while (_mapping_from.length() > 0) {
3857     bool processed_interval = false;
3858 
3859     for (i = _mapping_from.length() - 1; i >= 0; i--) {
3860       Interval* from_interval = _mapping_from.at(i);
3861       Interval* to_interval = _mapping_to.at(i);
3862 
3863       if (save_to_process_move(from_interval, to_interval)) {
3864         // this inverval can be processed because target is free
3865         if (from_interval != NULL) {
3866           insert_move(from_interval, to_interval);
3867           unblock_registers(from_interval);
3868         } else {
3869           insert_move(_mapping_from_opr.at(i), to_interval);
3870         }
3871         _mapping_from.remove_at(i);
3872         _mapping_from_opr.remove_at(i);
3873         _mapping_to.remove_at(i);
3874 
3875         processed_interval = true;
3876       } else if (from_interval != NULL && from_interval->assigned_reg() < LinearScan::nof_regs) {
3877         // this interval cannot be processed now because target is not free
3878         // it starts in a register, so it is a possible candidate for spilling
3879         spill_candidate = i;
3880       }
3881     }
3882 
3883     if (!processed_interval) {
3884       // no move could be processed because there is a cycle in the move list
3885       // (e.g. r1 -> r2, r2 -> r1), so one interval must be spilled to memory
3886       assert(spill_candidate != -1, "no interval in register for spilling found");
3887 
3888       // create a new spill interval and assign a stack slot to it
3889       Interval* from_interval = _mapping_from.at(spill_candidate);
3890       Interval* spill_interval = new Interval(-1);
3891       spill_interval->set_type(from_interval->type());
3892 
3893       // add a dummy range because real position is difficult to calculate
3894       // Note: this range is a special case when the integrity of the allocation is checked
3895       spill_interval->add_range(1, 2);
3896 
3897       //       do not allocate a new spill slot for temporary interval, but
3898       //       use spill slot assigned to from_interval. Otherwise moves from
3899       //       one stack slot to another can happen (not allowed by LIR_Assembler
3900       int spill_slot = from_interval->canonical_spill_slot();
3901       if (spill_slot < 0) {
3902         spill_slot = allocator()->allocate_spill_slot(type2spill_size[spill_interval->type()] == 2);
3903         from_interval->set_canonical_spill_slot(spill_slot);
3904       }
3905       spill_interval->assign_reg(spill_slot);
3906       allocator()->append_interval(spill_interval);
3907 
3908       TRACE_LINEAR_SCAN(4, tty->print_cr("created new Interval %d for spilling", spill_interval->reg_num()));
3909 
3910       // insert a move from register to stack and update the mapping
3911       insert_move(from_interval, spill_interval);
3912       _mapping_from.at_put(spill_candidate, spill_interval);
3913       unblock_registers(from_interval);
3914     }
3915   }
3916 
3917   // reset to default value
3918   _multiple_reads_allowed = false;
3919 
3920   // check that all intervals have been processed
3921   DEBUG_ONLY(check_empty());
3922 }
3923 
3924 
3925 void MoveResolver::set_insert_position(LIR_List* insert_list, int insert_idx) {
3926   TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: setting insert position to Block B%d, index %d", insert_list->block() != NULL ? insert_list->block()->block_id() : -1, insert_idx));
3927   assert(_insert_list == NULL && _insert_idx == -1, "use move_insert_position instead of set_insert_position when data already set");
3928 
3929   create_insertion_buffer(insert_list);
3930   _insert_list = insert_list;
3931   _insert_idx = insert_idx;
3932 }
3933 
3934 void MoveResolver::move_insert_position(LIR_List* insert_list, int insert_idx) {
3935   TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: moving insert position to Block B%d, index %d", insert_list->block() != NULL ? insert_list->block()->block_id() : -1, insert_idx));
3936 
3937   if (_insert_list != NULL && (insert_list != _insert_list || insert_idx != _insert_idx)) {
3938     // insert position changed -> resolve current mappings
3939     resolve_mappings();
3940   }
3941 
3942   if (insert_list != _insert_list) {
3943     // block changed -> append insertion_buffer because it is
3944     // bound to a specific block and create a new insertion_buffer
3945     append_insertion_buffer();
3946     create_insertion_buffer(insert_list);
3947   }
3948 
3949   _insert_list = insert_list;
3950   _insert_idx = insert_idx;
3951 }
3952 
3953 void MoveResolver::add_mapping(Interval* from_interval, Interval* to_interval) {
3954   TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: adding mapping from %d (%d, %d) to %d (%d, %d)", from_interval->reg_num(), from_interval->assigned_reg(), from_interval->assigned_regHi(), to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
3955 
3956   _mapping_from.append(from_interval);
3957   _mapping_from_opr.append(LIR_OprFact::illegalOpr);
3958   _mapping_to.append(to_interval);
3959 }
3960 
3961 
3962 void MoveResolver::add_mapping(LIR_Opr from_opr, Interval* to_interval) {
3963   TRACE_LINEAR_SCAN(4, tty->print("MoveResolver: adding mapping from "); from_opr->print(); tty->print_cr(" to %d (%d, %d)", to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
3964   assert(from_opr->is_constant(), "only for constants");
3965 
3966   _mapping_from.append(NULL);
3967   _mapping_from_opr.append(from_opr);
3968   _mapping_to.append(to_interval);
3969 }
3970 
3971 void MoveResolver::resolve_and_append_moves() {
3972   if (has_mappings()) {
3973     resolve_mappings();
3974   }
3975   append_insertion_buffer();
3976 }
3977 
3978 
3979 
3980 // **** Implementation of Range *************************************
3981 
3982 Range::Range(int from, int to, Range* next) :
3983   _from(from),
3984   _to(to),
3985   _next(next)
3986 {
3987 }
3988 
3989 // initialize sentinel
3990 Range* Range::_end = NULL;
3991 void Range::initialize(Arena* arena) {
3992   _end = new (arena) Range(max_jint, max_jint, NULL);
3993 }
3994 
3995 int Range::intersects_at(Range* r2) const {
3996   const Range* r1 = this;
3997 
3998   assert(r1 != NULL && r2 != NULL, "null ranges not allowed");
3999   assert(r1 != _end && r2 != _end, "empty ranges not allowed");
4000 
4001   do {
4002     if (r1->from() < r2->from()) {
4003       if (r1->to() <= r2->from()) {
4004         r1 = r1->next(); if (r1 == _end) return -1;
4005       } else {
4006         return r2->from();
4007       }
4008     } else if (r2->from() < r1->from()) {
4009       if (r2->to() <= r1->from()) {
4010         r2 = r2->next(); if (r2 == _end) return -1;
4011       } else {
4012         return r1->from();
4013       }
4014     } else { // r1->from() == r2->from()
4015       if (r1->from() == r1->to()) {
4016         r1 = r1->next(); if (r1 == _end) return -1;
4017       } else if (r2->from() == r2->to()) {
4018         r2 = r2->next(); if (r2 == _end) return -1;
4019       } else {
4020         return r1->from();
4021       }
4022     }
4023   } while (true);
4024 }
4025 
4026 #ifndef PRODUCT
4027 void Range::print(outputStream* out) const {
4028   out->print("[%d, %d[ ", _from, _to);
4029 }
4030 #endif
4031 
4032 
4033 
4034 // **** Implementation of Interval **********************************
4035 
4036 // initialize sentinel
4037 Interval* Interval::_end = NULL;
4038 void Interval::initialize(Arena* arena) {
4039   Range::initialize(arena);
4040   _end = new (arena) Interval(-1);
4041 }
4042 
4043 Interval::Interval(int reg_num) :
4044   _reg_num(reg_num),
4045   _type(T_ILLEGAL),
4046   _first(Range::end()),
4047   _use_pos_and_kinds(12),
4048   _current(Range::end()),
4049   _next(_end),
4050   _state(invalidState),
4051   _assigned_reg(LinearScan::any_reg),
4052   _assigned_regHi(LinearScan::any_reg),
4053   _cached_to(-1),
4054   _cached_opr(LIR_OprFact::illegalOpr),
4055   _cached_vm_reg(VMRegImpl::Bad()),
4056   _split_children(0),
4057   _canonical_spill_slot(-1),
4058   _insert_move_when_activated(false),
4059   _register_hint(NULL),
4060   _spill_state(noDefinitionFound),
4061   _spill_definition_pos(-1)
4062 {
4063   _split_parent = this;
4064   _current_split_child = this;
4065 }
4066 
4067 int Interval::calc_to() {
4068   assert(_first != Range::end(), "interval has no range");
4069 
4070   Range* r = _first;
4071   while (r->next() != Range::end()) {
4072     r = r->next();
4073   }
4074   return r->to();
4075 }
4076 
4077 
4078 #ifdef ASSERT
4079 // consistency check of split-children
4080 void Interval::check_split_children() {
4081   if (_split_children.length() > 0) {
4082     assert(is_split_parent(), "only split parents can have children");
4083 
4084     for (int i = 0; i < _split_children.length(); i++) {
4085       Interval* i1 = _split_children.at(i);
4086 
4087       assert(i1->split_parent() == this, "not a split child of this interval");
4088       assert(i1->type() == type(), "must be equal for all split children");
4089       assert(i1->canonical_spill_slot() == canonical_spill_slot(), "must be equal for all split children");
4090 
4091       for (int j = i + 1; j < _split_children.length(); j++) {
4092         Interval* i2 = _split_children.at(j);
4093 
4094         assert(i1->reg_num() != i2->reg_num(), "same register number");
4095 
4096         if (i1->from() < i2->from()) {
4097           assert(i1->to() <= i2->from() && i1->to() < i2->to(), "intervals overlapping");
4098         } else {
4099           assert(i2->from() < i1->from(), "intervals start at same op_id");
4100           assert(i2->to() <= i1->from() && i2->to() < i1->to(), "intervals overlapping");
4101         }
4102       }
4103     }
4104   }
4105 }
4106 #endif // ASSERT
4107 
4108 Interval* Interval::register_hint(bool search_split_child) const {
4109   if (!search_split_child) {
4110     return _register_hint;
4111   }
4112 
4113   if (_register_hint != NULL) {
4114     assert(_register_hint->is_split_parent(), "ony split parents are valid hint registers");
4115 
4116     if (_register_hint->assigned_reg() >= 0 && _register_hint->assigned_reg() < LinearScan::nof_regs) {
4117       return _register_hint;
4118 
4119     } else if (_register_hint->_split_children.length() > 0) {
4120       // search the first split child that has a register assigned
4121       int len = _register_hint->_split_children.length();
4122       for (int i = 0; i < len; i++) {
4123         Interval* cur = _register_hint->_split_children.at(i);
4124 
4125         if (cur->assigned_reg() >= 0 && cur->assigned_reg() < LinearScan::nof_regs) {
4126           return cur;
4127         }
4128       }
4129     }
4130   }
4131 
4132   // no hint interval found that has a register assigned
4133   return NULL;
4134 }
4135 
4136 
4137 Interval* Interval::split_child_at_op_id(int op_id, LIR_OpVisitState::OprMode mode) {
4138   assert(is_split_parent(), "can only be called for split parents");
4139   assert(op_id >= 0, "invalid op_id (method can not be called for spill moves)");
4140 
4141   Interval* result;
4142   if (_split_children.length() == 0) {
4143     result = this;
4144   } else {
4145     result = NULL;
4146     int len = _split_children.length();
4147 
4148     // in outputMode, the end of the interval (op_id == cur->to()) is not valid
4149     int to_offset = (mode == LIR_OpVisitState::outputMode ? 0 : 1);
4150 
4151     int i;
4152     for (i = 0; i < len; i++) {
4153       Interval* cur = _split_children.at(i);
4154       if (cur->from() <= op_id && op_id < cur->to() + to_offset) {
4155         if (i > 0) {
4156           // exchange current split child to start of list (faster access for next call)
4157           _split_children.at_put(i, _split_children.at(0));
4158           _split_children.at_put(0, cur);
4159         }
4160 
4161         // interval found
4162         result = cur;
4163         break;
4164       }
4165     }
4166 
4167 #ifdef ASSERT
4168     for (i = 0; i < len; i++) {
4169       Interval* tmp = _split_children.at(i);
4170       if (tmp != result && tmp->from() <= op_id && op_id < tmp->to() + to_offset) {
4171         tty->print_cr("two valid result intervals found for op_id %d: %d and %d", op_id, result->reg_num(), tmp->reg_num());
4172         result->print();
4173         tmp->print();
4174         assert(false, "two valid result intervals found");
4175       }
4176     }
4177 #endif
4178   }
4179 
4180   assert(result != NULL, "no matching interval found");
4181   assert(result->covers(op_id, mode), "op_id not covered by interval");
4182 
4183   return result;
4184 }
4185 
4186 
4187 // returns the last split child that ends before the given op_id
4188 Interval* Interval::split_child_before_op_id(int op_id) {
4189   assert(op_id >= 0, "invalid op_id");
4190 
4191   Interval* parent = split_parent();
4192   Interval* result = NULL;
4193 
4194   int len = parent->_split_children.length();
4195   assert(len > 0, "no split children available");
4196 
4197   for (int i = len - 1; i >= 0; i--) {
4198     Interval* cur = parent->_split_children.at(i);
4199     if (cur->to() <= op_id && (result == NULL || result->to() < cur->to())) {
4200       result = cur;
4201     }
4202   }
4203 
4204   assert(result != NULL, "no split child found");
4205   return result;
4206 }
4207 
4208 
4209 // checks if op_id is covered by any split child
4210 bool Interval::split_child_covers(int op_id, LIR_OpVisitState::OprMode mode) {
4211   assert(is_split_parent(), "can only be called for split parents");
4212   assert(op_id >= 0, "invalid op_id (method can not be called for spill moves)");
4213 
4214   if (_split_children.length() == 0) {
4215     // simple case if interval was not split
4216     return covers(op_id, mode);
4217 
4218   } else {
4219     // extended case: check all split children
4220     int len = _split_children.length();
4221     for (int i = 0; i < len; i++) {
4222       Interval* cur = _split_children.at(i);
4223       if (cur->covers(op_id, mode)) {
4224         return true;
4225       }
4226     }
4227     return false;
4228   }
4229 }
4230 
4231 
4232 // Note: use positions are sorted descending -> first use has highest index
4233 int Interval::first_usage(IntervalUseKind min_use_kind) const {
4234   assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
4235 
4236   for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4237     if (_use_pos_and_kinds.at(i + 1) >= min_use_kind) {
4238       return _use_pos_and_kinds.at(i);
4239     }
4240   }
4241   return max_jint;
4242 }
4243 
4244 int Interval::next_usage(IntervalUseKind min_use_kind, int from) const {
4245   assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
4246 
4247   for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4248     if (_use_pos_and_kinds.at(i) >= from && _use_pos_and_kinds.at(i + 1) >= min_use_kind) {
4249       return _use_pos_and_kinds.at(i);
4250     }
4251   }
4252   return max_jint;
4253 }
4254 
4255 int Interval::next_usage_exact(IntervalUseKind exact_use_kind, int from) const {
4256   assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
4257 
4258   for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4259     if (_use_pos_and_kinds.at(i) >= from && _use_pos_and_kinds.at(i + 1) == exact_use_kind) {
4260       return _use_pos_and_kinds.at(i);
4261     }
4262   }
4263   return max_jint;
4264 }
4265 
4266 int Interval::previous_usage(IntervalUseKind min_use_kind, int from) const {
4267   assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
4268 
4269   int prev = 0;
4270   for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4271     if (_use_pos_and_kinds.at(i) > from) {
4272       return prev;
4273     }
4274     if (_use_pos_and_kinds.at(i + 1) >= min_use_kind) {
4275       prev = _use_pos_and_kinds.at(i);
4276     }
4277   }
4278   return prev;
4279 }
4280 
4281 void Interval::add_use_pos(int pos, IntervalUseKind use_kind) {
4282   assert(covers(pos, LIR_OpVisitState::inputMode), "use position not covered by live range");
4283 
4284   // do not add use positions for precolored intervals because
4285   // they are never used
4286   if (use_kind != noUse && reg_num() >= LIR_OprDesc::vreg_base) {
4287 #ifdef ASSERT
4288     assert(_use_pos_and_kinds.length() % 2 == 0, "must be");
4289     for (int i = 0; i < _use_pos_and_kinds.length(); i += 2) {
4290       assert(pos <= _use_pos_and_kinds.at(i), "already added a use-position with lower position");
4291       assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
4292       if (i > 0) {
4293         assert(_use_pos_and_kinds.at(i) < _use_pos_and_kinds.at(i - 2), "not sorted descending");
4294       }
4295     }
4296 #endif
4297 
4298     // Note: add_use is called in descending order, so list gets sorted
4299     //       automatically by just appending new use positions
4300     int len = _use_pos_and_kinds.length();
4301     if (len == 0 || _use_pos_and_kinds.at(len - 2) > pos) {
4302       _use_pos_and_kinds.append(pos);
4303       _use_pos_and_kinds.append(use_kind);
4304     } else if (_use_pos_and_kinds.at(len - 1) < use_kind) {
4305       assert(_use_pos_and_kinds.at(len - 2) == pos, "list not sorted correctly");
4306       _use_pos_and_kinds.at_put(len - 1, use_kind);
4307     }
4308   }
4309 }
4310 
4311 void Interval::add_range(int from, int to) {
4312   assert(from < to, "invalid range");
4313   assert(first() == Range::end() || to < first()->next()->from(), "not inserting at begin of interval");
4314   assert(from <= first()->to(), "not inserting at begin of interval");
4315 
4316   if (first()->from() <= to) {
4317     // join intersecting ranges
4318     first()->set_from(MIN2(from, first()->from()));
4319     first()->set_to  (MAX2(to,   first()->to()));
4320   } else {
4321     // insert new range
4322     _first = new Range(from, to, first());
4323   }
4324 }
4325 
4326 Interval* Interval::new_split_child() {
4327   // allocate new interval
4328   Interval* result = new Interval(-1);
4329   result->set_type(type());
4330 
4331   Interval* parent = split_parent();
4332   result->_split_parent = parent;
4333   result->set_register_hint(parent);
4334 
4335   // insert new interval in children-list of parent
4336   if (parent->_split_children.length() == 0) {
4337     assert(is_split_parent(), "list must be initialized at first split");
4338 
4339     parent->_split_children = IntervalList(4);
4340     parent->_split_children.append(this);
4341   }
4342   parent->_split_children.append(result);
4343 
4344   return result;
4345 }
4346 
4347 // split this interval at the specified position and return
4348 // the remainder as a new interval.
4349 //
4350 // when an interval is split, a bi-directional link is established between the original interval
4351 // (the split parent) and the intervals that are split off this interval (the split children)
4352 // When a split child is split again, the new created interval is also a direct child
4353 // of the original parent (there is no tree of split children stored, but a flat list)
4354 // All split children are spilled to the same stack slot (stored in _canonical_spill_slot)
4355 //
4356 // Note: The new interval has no valid reg_num
4357 Interval* Interval::split(int split_pos) {
4358   assert(LinearScan::is_virtual_interval(this), "cannot split fixed intervals");
4359 
4360   // allocate new interval
4361   Interval* result = new_split_child();
4362 
4363   // split the ranges
4364   Range* prev = NULL;
4365   Range* cur = _first;
4366   while (cur != Range::end() && cur->to() <= split_pos) {
4367     prev = cur;
4368     cur = cur->next();
4369   }
4370   assert(cur != Range::end(), "split interval after end of last range");
4371 
4372   if (cur->from() < split_pos) {
4373     result->_first = new Range(split_pos, cur->to(), cur->next());
4374     cur->set_to(split_pos);
4375     cur->set_next(Range::end());
4376 
4377   } else {
4378     assert(prev != NULL, "split before start of first range");
4379     result->_first = cur;
4380     prev->set_next(Range::end());
4381   }
4382   result->_current = result->_first;
4383   _cached_to = -1; // clear cached value
4384 
4385   // split list of use positions
4386   int total_len = _use_pos_and_kinds.length();
4387   int start_idx = total_len - 2;
4388   while (start_idx >= 0 && _use_pos_and_kinds.at(start_idx) < split_pos) {
4389     start_idx -= 2;
4390   }
4391 
4392   intStack new_use_pos_and_kinds(total_len - start_idx);
4393   int i;
4394   for (i = start_idx + 2; i < total_len; i++) {
4395     new_use_pos_and_kinds.append(_use_pos_and_kinds.at(i));
4396   }
4397 
4398   _use_pos_and_kinds.truncate(start_idx + 2);
4399   result->_use_pos_and_kinds = _use_pos_and_kinds;
4400   _use_pos_and_kinds = new_use_pos_and_kinds;
4401 
4402 #ifdef ASSERT
4403   assert(_use_pos_and_kinds.length() % 2 == 0, "must have use kind for each use pos");
4404   assert(result->_use_pos_and_kinds.length() % 2 == 0, "must have use kind for each use pos");
4405   assert(_use_pos_and_kinds.length() + result->_use_pos_and_kinds.length() == total_len, "missed some entries");
4406 
4407   for (i = 0; i < _use_pos_and_kinds.length(); i += 2) {
4408     assert(_use_pos_and_kinds.at(i) < split_pos, "must be");
4409     assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
4410   }
4411   for (i = 0; i < result->_use_pos_and_kinds.length(); i += 2) {
4412     assert(result->_use_pos_and_kinds.at(i) >= split_pos, "must be");
4413     assert(result->_use_pos_and_kinds.at(i + 1) >= firstValidKind && result->_use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
4414   }
4415 #endif
4416 
4417   return result;
4418 }
4419 
4420 // split this interval at the specified position and return
4421 // the head as a new interval (the original interval is the tail)
4422 //
4423 // Currently, only the first range can be split, and the new interval
4424 // must not have split positions
4425 Interval* Interval::split_from_start(int split_pos) {
4426   assert(LinearScan::is_virtual_interval(this), "cannot split fixed intervals");
4427   assert(split_pos > from() && split_pos < to(), "can only split inside interval");
4428   assert(split_pos > _first->from() && split_pos <= _first->to(), "can only split inside first range");
4429   assert(first_usage(noUse) > split_pos, "can not split when use positions are present");
4430 
4431   // allocate new interval
4432   Interval* result = new_split_child();
4433 
4434   // the new created interval has only one range (checked by assertion above),
4435   // so the splitting of the ranges is very simple
4436   result->add_range(_first->from(), split_pos);
4437 
4438   if (split_pos == _first->to()) {
4439     assert(_first->next() != Range::end(), "must not be at end");
4440     _first = _first->next();
4441   } else {
4442     _first->set_from(split_pos);
4443   }
4444 
4445   return result;
4446 }
4447 
4448 
4449 // returns true if the op_id is inside the interval
4450 bool Interval::covers(int op_id, LIR_OpVisitState::OprMode mode) const {
4451   Range* cur  = _first;
4452 
4453   while (cur != Range::end() && cur->to() < op_id) {
4454     cur = cur->next();
4455   }
4456   if (cur != Range::end()) {
4457     assert(cur->to() != cur->next()->from(), "ranges not separated");
4458 
4459     if (mode == LIR_OpVisitState::outputMode) {
4460       return cur->from() <= op_id && op_id < cur->to();
4461     } else {
4462       return cur->from() <= op_id && op_id <= cur->to();
4463     }
4464   }
4465   return false;
4466 }
4467 
4468 // returns true if the interval has any hole between hole_from and hole_to
4469 // (even if the hole has only the length 1)
4470 bool Interval::has_hole_between(int hole_from, int hole_to) {
4471   assert(hole_from < hole_to, "check");
4472   assert(from() <= hole_from && hole_to <= to(), "index out of interval");
4473 
4474   Range* cur  = _first;
4475   while (cur != Range::end()) {
4476     assert(cur->to() < cur->next()->from(), "no space between ranges");
4477 
4478     // hole-range starts before this range -> hole
4479     if (hole_from < cur->from()) {
4480       return true;
4481 
4482     // hole-range completely inside this range -> no hole
4483     } else if (hole_to <= cur->to()) {
4484       return false;
4485 
4486     // overlapping of hole-range with this range -> hole
4487     } else if (hole_from <= cur->to()) {
4488       return true;
4489     }
4490 
4491     cur = cur->next();
4492   }
4493 
4494   return false;
4495 }
4496 
4497 
4498 #ifndef PRODUCT
4499 void Interval::print(outputStream* out) const {
4500   const char* SpillState2Name[] = { "no definition", "no spill store", "one spill store", "store at definition", "start in memory", "no optimization" };
4501   const char* UseKind2Name[] = { "N", "L", "S", "M" };
4502 
4503   const char* type_name;
4504   LIR_Opr opr = LIR_OprFact::illegal();
4505   if (reg_num() < LIR_OprDesc::vreg_base) {
4506     type_name = "fixed";
4507     // need a temporary operand for fixed intervals because type() cannot be called
4508     if (assigned_reg() >= pd_first_cpu_reg && assigned_reg() <= pd_last_cpu_reg) {
4509       opr = LIR_OprFact::single_cpu(assigned_reg());
4510     } else if (assigned_reg() >= pd_first_fpu_reg && assigned_reg() <= pd_last_fpu_reg) {
4511       opr = LIR_OprFact::single_fpu(assigned_reg() - pd_first_fpu_reg);
4512 #ifdef X86
4513     } else if (assigned_reg() >= pd_first_xmm_reg && assigned_reg() <= pd_last_xmm_reg) {
4514       opr = LIR_OprFact::single_xmm(assigned_reg() - pd_first_xmm_reg);
4515 #endif
4516     } else {
4517       ShouldNotReachHere();
4518     }
4519   } else {
4520     type_name = type2name(type());
4521     if (assigned_reg() != -1 &&
4522         (LinearScan::num_physical_regs(type()) == 1 || assigned_regHi() != -1)) {
4523       opr = LinearScan::calc_operand_for_interval(this);
4524     }
4525   }
4526 
4527   out->print("%d %s ", reg_num(), type_name);
4528   if (opr->is_valid()) {
4529     out->print("\"");
4530     opr->print(out);
4531     out->print("\" ");
4532   }
4533   out->print("%d %d ", split_parent()->reg_num(), (register_hint(false) != NULL ? register_hint(false)->reg_num() : -1));
4534 
4535   // print ranges
4536   Range* cur = _first;
4537   while (cur != Range::end()) {
4538     cur->print(out);
4539     cur = cur->next();
4540     assert(cur != NULL, "range list not closed with range sentinel");
4541   }
4542 
4543   // print use positions
4544   int prev = 0;
4545   assert(_use_pos_and_kinds.length() % 2 == 0, "must be");
4546   for (int i =_use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4547     assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
4548     assert(prev < _use_pos_and_kinds.at(i), "use positions not sorted");
4549 
4550     out->print("%d %s ", _use_pos_and_kinds.at(i), UseKind2Name[_use_pos_and_kinds.at(i + 1)]);
4551     prev = _use_pos_and_kinds.at(i);
4552   }
4553 
4554   out->print(" \"%s\"", SpillState2Name[spill_state()]);
4555   out->cr();
4556 }
4557 #endif
4558 
4559 
4560 
4561 // **** Implementation of IntervalWalker ****************************
4562 
4563 IntervalWalker::IntervalWalker(LinearScan* allocator, Interval* unhandled_fixed_first, Interval* unhandled_any_first)
4564  : _compilation(allocator->compilation())
4565  , _allocator(allocator)
4566 {
4567   _unhandled_first[fixedKind] = unhandled_fixed_first;
4568   _unhandled_first[anyKind]   = unhandled_any_first;
4569   _active_first[fixedKind]    = Interval::end();
4570   _inactive_first[fixedKind]  = Interval::end();
4571   _active_first[anyKind]      = Interval::end();
4572   _inactive_first[anyKind]    = Interval::end();
4573   _current_position = -1;
4574   _current = NULL;
4575   next_interval();
4576 }
4577 
4578 
4579 // append interval at top of list
4580 void IntervalWalker::append_unsorted(Interval** list, Interval* interval) {
4581   interval->set_next(*list); *list = interval;
4582 }
4583 
4584 
4585 // append interval in order of current range from()
4586 void IntervalWalker::append_sorted(Interval** list, Interval* interval) {
4587   Interval* prev = NULL;
4588   Interval* cur  = *list;
4589   while (cur->current_from() < interval->current_from()) {
4590     prev = cur; cur = cur->next();
4591   }
4592   if (prev == NULL) {
4593     *list = interval;
4594   } else {
4595     prev->set_next(interval);
4596   }
4597   interval->set_next(cur);
4598 }
4599 
4600 void IntervalWalker::append_to_unhandled(Interval** list, Interval* interval) {
4601   assert(interval->from() >= current()->current_from(), "cannot append new interval before current walk position");
4602 
4603   Interval* prev = NULL;
4604   Interval* cur  = *list;
4605   while (cur->from() < interval->from() || (cur->from() == interval->from() && cur->first_usage(noUse) < interval->first_usage(noUse))) {
4606     prev = cur; cur = cur->next();
4607   }
4608   if (prev == NULL) {
4609     *list = interval;
4610   } else {
4611     prev->set_next(interval);
4612   }
4613   interval->set_next(cur);
4614 }
4615 
4616 
4617 inline bool IntervalWalker::remove_from_list(Interval** list, Interval* i) {
4618   while (*list != Interval::end() && *list != i) {
4619     list = (*list)->next_addr();
4620   }
4621   if (*list != Interval::end()) {
4622     assert(*list == i, "check");
4623     *list = (*list)->next();
4624     return true;
4625   } else {
4626     return false;
4627   }
4628 }
4629 
4630 void IntervalWalker::remove_from_list(Interval* i) {
4631   bool deleted;
4632 
4633   if (i->state() == activeState) {
4634     deleted = remove_from_list(active_first_addr(anyKind), i);
4635   } else {
4636     assert(i->state() == inactiveState, "invalid state");
4637     deleted = remove_from_list(inactive_first_addr(anyKind), i);
4638   }
4639 
4640   assert(deleted, "interval has not been found in list");
4641 }
4642 
4643 
4644 void IntervalWalker::walk_to(IntervalState state, int from) {
4645   assert (state == activeState || state == inactiveState, "wrong state");
4646   for_each_interval_kind(kind) {
4647     Interval** prev = state == activeState ? active_first_addr(kind) : inactive_first_addr(kind);
4648     Interval* next   = *prev;
4649     while (next->current_from() <= from) {
4650       Interval* cur = next;
4651       next = cur->next();
4652 
4653       bool range_has_changed = false;
4654       while (cur->current_to() <= from) {
4655         cur->next_range();
4656         range_has_changed = true;
4657       }
4658 
4659       // also handle move from inactive list to active list
4660       range_has_changed = range_has_changed || (state == inactiveState && cur->current_from() <= from);
4661 
4662       if (range_has_changed) {
4663         // remove cur from list
4664         *prev = next;
4665         if (cur->current_at_end()) {
4666           // move to handled state (not maintained as a list)
4667           cur->set_state(handledState);
4668           interval_moved(cur, kind, state, handledState);
4669         } else if (cur->current_from() <= from){
4670           // sort into active list
4671           append_sorted(active_first_addr(kind), cur);
4672           cur->set_state(activeState);
4673           if (*prev == cur) {
4674             assert(state == activeState, "check");
4675             prev = cur->next_addr();
4676           }
4677           interval_moved(cur, kind, state, activeState);
4678         } else {
4679           // sort into inactive list
4680           append_sorted(inactive_first_addr(kind), cur);
4681           cur->set_state(inactiveState);
4682           if (*prev == cur) {
4683             assert(state == inactiveState, "check");
4684             prev = cur->next_addr();
4685           }
4686           interval_moved(cur, kind, state, inactiveState);
4687         }
4688       } else {
4689         prev = cur->next_addr();
4690         continue;
4691       }
4692     }
4693   }
4694 }
4695 
4696 
4697 void IntervalWalker::next_interval() {
4698   IntervalKind kind;
4699   Interval* any   = _unhandled_first[anyKind];
4700   Interval* fixed = _unhandled_first[fixedKind];
4701 
4702   if (any != Interval::end()) {
4703     // intervals may start at same position -> prefer fixed interval
4704     kind = fixed != Interval::end() && fixed->from() <= any->from() ? fixedKind : anyKind;
4705 
4706     assert (kind == fixedKind && fixed->from() <= any->from() ||
4707             kind == anyKind   && any->from() <= fixed->from(), "wrong interval!!!");
4708     assert(any == Interval::end() || fixed == Interval::end() || any->from() != fixed->from() || kind == fixedKind, "if fixed and any-Interval start at same position, fixed must be processed first");
4709 
4710   } else if (fixed != Interval::end()) {
4711     kind = fixedKind;
4712   } else {
4713     _current = NULL; return;
4714   }
4715   _current_kind = kind;
4716   _current = _unhandled_first[kind];
4717   _unhandled_first[kind] = _current->next();
4718   _current->set_next(Interval::end());
4719   _current->rewind_range();
4720 }
4721 
4722 
4723 void IntervalWalker::walk_to(int lir_op_id) {
4724   assert(_current_position <= lir_op_id, "can not walk backwards");
4725   while (current() != NULL) {
4726     bool is_active = current()->from() <= lir_op_id;
4727     int id = is_active ? current()->from() : lir_op_id;
4728 
4729     TRACE_LINEAR_SCAN(2, if (_current_position < id) { tty->cr(); tty->print_cr("walk_to(%d) **************************************************************", id); })
4730 
4731     // set _current_position prior to call of walk_to
4732     _current_position = id;
4733 
4734     // call walk_to even if _current_position == id
4735     walk_to(activeState, id);
4736     walk_to(inactiveState, id);
4737 
4738     if (is_active) {
4739       current()->set_state(activeState);
4740       if (activate_current()) {
4741         append_sorted(active_first_addr(current_kind()), current());
4742         interval_moved(current(), current_kind(), unhandledState, activeState);
4743       }
4744 
4745       next_interval();
4746     } else {
4747       return;
4748     }
4749   }
4750 }
4751 
4752 void IntervalWalker::interval_moved(Interval* interval, IntervalKind kind, IntervalState from, IntervalState to) {
4753 #ifndef PRODUCT
4754   if (TraceLinearScanLevel >= 4) {
4755     #define print_state(state) \
4756     switch(state) {\
4757       case unhandledState: tty->print("unhandled"); break;\
4758       case activeState: tty->print("active"); break;\
4759       case inactiveState: tty->print("inactive"); break;\
4760       case handledState: tty->print("handled"); break;\
4761       default: ShouldNotReachHere(); \
4762     }
4763 
4764     print_state(from); tty->print(" to "); print_state(to);
4765     tty->fill_to(23);
4766     interval->print();
4767 
4768     #undef print_state
4769   }
4770 #endif
4771 }
4772 
4773 
4774 
4775 // **** Implementation of LinearScanWalker **************************
4776 
4777 LinearScanWalker::LinearScanWalker(LinearScan* allocator, Interval* unhandled_fixed_first, Interval* unhandled_any_first)
4778   : IntervalWalker(allocator, unhandled_fixed_first, unhandled_any_first)
4779   , _move_resolver(allocator)
4780 {
4781   for (int i = 0; i < LinearScan::nof_regs; i++) {
4782     _spill_intervals[i] = new IntervalList(2);
4783   }
4784 }
4785 
4786 
4787 inline void LinearScanWalker::init_use_lists(bool only_process_use_pos) {
4788   for (int i = _first_reg; i <= _last_reg; i++) {
4789     _use_pos[i] = max_jint;
4790 
4791     if (!only_process_use_pos) {
4792       _block_pos[i] = max_jint;
4793       _spill_intervals[i]->clear();
4794     }
4795   }
4796 }
4797 
4798 inline void LinearScanWalker::exclude_from_use(int reg) {
4799   assert(reg < LinearScan::nof_regs, "interval must have a register assigned (stack slots not allowed)");
4800   if (reg >= _first_reg && reg <= _last_reg) {
4801     _use_pos[reg] = 0;
4802   }
4803 }
4804 inline void LinearScanWalker::exclude_from_use(Interval* i) {
4805   assert(i->assigned_reg() != any_reg, "interval has no register assigned");
4806 
4807   exclude_from_use(i->assigned_reg());
4808   exclude_from_use(i->assigned_regHi());
4809 }
4810 
4811 inline void LinearScanWalker::set_use_pos(int reg, Interval* i, int use_pos, bool only_process_use_pos) {
4812   assert(use_pos != 0, "must use exclude_from_use to set use_pos to 0");
4813 
4814   if (reg >= _first_reg && reg <= _last_reg) {
4815     if (_use_pos[reg] > use_pos) {
4816       _use_pos[reg] = use_pos;
4817     }
4818     if (!only_process_use_pos) {
4819       _spill_intervals[reg]->append(i);
4820     }
4821   }
4822 }
4823 inline void LinearScanWalker::set_use_pos(Interval* i, int use_pos, bool only_process_use_pos) {
4824   assert(i->assigned_reg() != any_reg, "interval has no register assigned");
4825   if (use_pos != -1) {
4826     set_use_pos(i->assigned_reg(), i, use_pos, only_process_use_pos);
4827     set_use_pos(i->assigned_regHi(), i, use_pos, only_process_use_pos);
4828   }
4829 }
4830 
4831 inline void LinearScanWalker::set_block_pos(int reg, Interval* i, int block_pos) {
4832   if (reg >= _first_reg && reg <= _last_reg) {
4833     if (_block_pos[reg] > block_pos) {
4834       _block_pos[reg] = block_pos;
4835     }
4836     if (_use_pos[reg] > block_pos) {
4837       _use_pos[reg] = block_pos;
4838     }
4839   }
4840 }
4841 inline void LinearScanWalker::set_block_pos(Interval* i, int block_pos) {
4842   assert(i->assigned_reg() != any_reg, "interval has no register assigned");
4843   if (block_pos != -1) {
4844     set_block_pos(i->assigned_reg(), i, block_pos);
4845     set_block_pos(i->assigned_regHi(), i, block_pos);
4846   }
4847 }
4848 
4849 
4850 void LinearScanWalker::free_exclude_active_fixed() {
4851   Interval* list = active_first(fixedKind);
4852   while (list != Interval::end()) {
4853     assert(list->assigned_reg() < LinearScan::nof_regs, "active interval must have a register assigned");
4854     exclude_from_use(list);
4855     list = list->next();
4856   }
4857 }
4858 
4859 void LinearScanWalker::free_exclude_active_any() {
4860   Interval* list = active_first(anyKind);
4861   while (list != Interval::end()) {
4862     exclude_from_use(list);
4863     list = list->next();
4864   }
4865 }
4866 
4867 void LinearScanWalker::free_collect_inactive_fixed(Interval* cur) {
4868   Interval* list = inactive_first(fixedKind);
4869   while (list != Interval::end()) {
4870     if (cur->to() <= list->current_from()) {
4871       assert(list->current_intersects_at(cur) == -1, "must not intersect");
4872       set_use_pos(list, list->current_from(), true);
4873     } else {
4874       set_use_pos(list, list->current_intersects_at(cur), true);
4875     }
4876     list = list->next();
4877   }
4878 }
4879 
4880 void LinearScanWalker::free_collect_inactive_any(Interval* cur) {
4881   Interval* list = inactive_first(anyKind);
4882   while (list != Interval::end()) {
4883     set_use_pos(list, list->current_intersects_at(cur), true);
4884     list = list->next();
4885   }
4886 }
4887 
4888 void LinearScanWalker::free_collect_unhandled(IntervalKind kind, Interval* cur) {
4889   Interval* list = unhandled_first(kind);
4890   while (list != Interval::end()) {
4891     set_use_pos(list, list->intersects_at(cur), true);
4892     if (kind == fixedKind && cur->to() <= list->from()) {
4893       set_use_pos(list, list->from(), true);
4894     }
4895     list = list->next();
4896   }
4897 }
4898 
4899 void LinearScanWalker::spill_exclude_active_fixed() {
4900   Interval* list = active_first(fixedKind);
4901   while (list != Interval::end()) {
4902     exclude_from_use(list);
4903     list = list->next();
4904   }
4905 }
4906 
4907 void LinearScanWalker::spill_block_unhandled_fixed(Interval* cur) {
4908   Interval* list = unhandled_first(fixedKind);
4909   while (list != Interval::end()) {
4910     set_block_pos(list, list->intersects_at(cur));
4911     list = list->next();
4912   }
4913 }
4914 
4915 void LinearScanWalker::spill_block_inactive_fixed(Interval* cur) {
4916   Interval* list = inactive_first(fixedKind);
4917   while (list != Interval::end()) {
4918     if (cur->to() > list->current_from()) {
4919       set_block_pos(list, list->current_intersects_at(cur));
4920     } else {
4921       assert(list->current_intersects_at(cur) == -1, "invalid optimization: intervals intersect");
4922     }
4923 
4924     list = list->next();
4925   }
4926 }
4927 
4928 void LinearScanWalker::spill_collect_active_any() {
4929   Interval* list = active_first(anyKind);
4930   while (list != Interval::end()) {
4931     set_use_pos(list, MIN2(list->next_usage(loopEndMarker, _current_position), list->to()), false);
4932     list = list->next();
4933   }
4934 }
4935 
4936 void LinearScanWalker::spill_collect_inactive_any(Interval* cur) {
4937   Interval* list = inactive_first(anyKind);
4938   while (list != Interval::end()) {
4939     if (list->current_intersects(cur)) {
4940       set_use_pos(list, MIN2(list->next_usage(loopEndMarker, _current_position), list->to()), false);
4941     }
4942     list = list->next();
4943   }
4944 }
4945 
4946 
4947 void LinearScanWalker::insert_move(int op_id, Interval* src_it, Interval* dst_it) {
4948   // output all moves here. When source and target are equal, the move is
4949   // optimized away later in assign_reg_nums
4950 
4951   op_id = (op_id + 1) & ~1;
4952   BlockBegin* op_block = allocator()->block_of_op_with_id(op_id);
4953   assert(op_id > 0 && allocator()->block_of_op_with_id(op_id - 2) == op_block, "cannot insert move at block boundary");
4954 
4955   // calculate index of instruction inside instruction list of current block
4956   // the minimal index (for a block with no spill moves) can be calculated because the
4957   // numbering of instructions is known.
4958   // When the block already contains spill moves, the index must be increased until the
4959   // correct index is reached.
4960   LIR_OpList* list = op_block->lir()->instructions_list();
4961   int index = (op_id - list->at(0)->id()) / 2;
4962   assert(list->at(index)->id() <= op_id, "error in calculation");
4963 
4964   while (list->at(index)->id() != op_id) {
4965     index++;
4966     assert(0 <= index && index < list->length(), "index out of bounds");
4967   }
4968   assert(1 <= index && index < list->length(), "index out of bounds");
4969   assert(list->at(index)->id() == op_id, "error in calculation");
4970 
4971   // insert new instruction before instruction at position index
4972   _move_resolver.move_insert_position(op_block->lir(), index - 1);
4973   _move_resolver.add_mapping(src_it, dst_it);
4974 }
4975 
4976 
4977 int LinearScanWalker::find_optimal_split_pos(BlockBegin* min_block, BlockBegin* max_block, int max_split_pos) {
4978   int from_block_nr = min_block->linear_scan_number();
4979   int to_block_nr = max_block->linear_scan_number();
4980 
4981   assert(0 <= from_block_nr && from_block_nr < block_count(), "out of range");
4982   assert(0 <= to_block_nr && to_block_nr < block_count(), "out of range");
4983   assert(from_block_nr < to_block_nr, "must cross block boundary");
4984 
4985   // Try to split at end of max_block. If this would be after
4986   // max_split_pos, then use the begin of max_block
4987   int optimal_split_pos = max_block->last_lir_instruction_id() + 2;
4988   if (optimal_split_pos > max_split_pos) {
4989     optimal_split_pos = max_block->first_lir_instruction_id();
4990   }
4991 
4992   int min_loop_depth = max_block->loop_depth();
4993   for (int i = to_block_nr - 1; i >= from_block_nr; i--) {
4994     BlockBegin* cur = block_at(i);
4995 
4996     if (cur->loop_depth() < min_loop_depth) {
4997       // block with lower loop-depth found -> split at the end of this block
4998       min_loop_depth = cur->loop_depth();
4999       optimal_split_pos = cur->last_lir_instruction_id() + 2;
5000     }
5001   }
5002   assert(optimal_split_pos > allocator()->max_lir_op_id() || allocator()->is_block_begin(optimal_split_pos), "algorithm must move split pos to block boundary");
5003 
5004   return optimal_split_pos;
5005 }
5006 
5007 
5008 int LinearScanWalker::find_optimal_split_pos(Interval* it, int min_split_pos, int max_split_pos, bool do_loop_optimization) {
5009   int optimal_split_pos = -1;
5010   if (min_split_pos == max_split_pos) {
5011     // trivial case, no optimization of split position possible
5012     TRACE_LINEAR_SCAN(4, tty->print_cr("      min-pos and max-pos are equal, no optimization possible"));
5013     optimal_split_pos = min_split_pos;
5014 
5015   } else {
5016     assert(min_split_pos < max_split_pos, "must be true then");
5017     assert(min_split_pos > 0, "cannot access min_split_pos - 1 otherwise");
5018 
5019     // reason for using min_split_pos - 1: when the minimal split pos is exactly at the
5020     // beginning of a block, then min_split_pos is also a possible split position.
5021     // Use the block before as min_block, because then min_block->last_lir_instruction_id() + 2 == min_split_pos
5022     BlockBegin* min_block = allocator()->block_of_op_with_id(min_split_pos - 1);
5023 
5024     // reason for using max_split_pos - 1: otherwise there would be an assertion failure
5025     // when an interval ends at the end of the last block of the method
5026     // (in this case, max_split_pos == allocator()->max_lir_op_id() + 2, and there is no
5027     // block at this op_id)
5028     BlockBegin* max_block = allocator()->block_of_op_with_id(max_split_pos - 1);
5029 
5030     assert(min_block->linear_scan_number() <= max_block->linear_scan_number(), "invalid order");
5031     if (min_block == max_block) {
5032       // split position cannot be moved to block boundary, so split as late as possible
5033       TRACE_LINEAR_SCAN(4, tty->print_cr("      cannot move split pos to block boundary because min_pos and max_pos are in same block"));
5034       optimal_split_pos = max_split_pos;
5035 
5036     } else if (it->has_hole_between(max_split_pos - 1, max_split_pos) && !allocator()->is_block_begin(max_split_pos)) {
5037       // Do not move split position if the interval has a hole before max_split_pos.
5038       // Intervals resulting from Phi-Functions have more than one definition (marked
5039       // as mustHaveRegister) with a hole before each definition. When the register is needed
5040       // for the second definition, an earlier reloading is unnecessary.
5041       TRACE_LINEAR_SCAN(4, tty->print_cr("      interval has hole just before max_split_pos, so splitting at max_split_pos"));
5042       optimal_split_pos = max_split_pos;
5043 
5044     } else {
5045       // seach optimal block boundary between min_split_pos and max_split_pos
5046       TRACE_LINEAR_SCAN(4, tty->print_cr("      moving split pos to optimal block boundary between block B%d and B%d", min_block->block_id(), max_block->block_id()));
5047 
5048       if (do_loop_optimization) {
5049         // Loop optimization: if a loop-end marker is found between min- and max-position,
5050         // then split before this loop
5051         int loop_end_pos = it->next_usage_exact(loopEndMarker, min_block->last_lir_instruction_id() + 2);
5052         TRACE_LINEAR_SCAN(4, tty->print_cr("      loop optimization: loop end found at pos %d", loop_end_pos));
5053 
5054         assert(loop_end_pos > min_split_pos, "invalid order");
5055         if (loop_end_pos < max_split_pos) {
5056           // loop-end marker found between min- and max-position
5057           // if it is not the end marker for the same loop as the min-position, then move
5058           // the max-position to this loop block.
5059           // Desired result: uses tagged as shouldHaveRegister inside a loop cause a reloading
5060           // of the interval (normally, only mustHaveRegister causes a reloading)
5061           BlockBegin* loop_block = allocator()->block_of_op_with_id(loop_end_pos);
5062 
5063           TRACE_LINEAR_SCAN(4, tty->print_cr("      interval is used in loop that ends in block B%d, so trying to move max_block back from B%d to B%d", loop_block->block_id(), max_block->block_id(), loop_block->block_id()));
5064           assert(loop_block != min_block, "loop_block and min_block must be different because block boundary is needed between");
5065 
5066           optimal_split_pos = find_optimal_split_pos(min_block, loop_block, loop_block->last_lir_instruction_id() + 2);
5067           if (optimal_split_pos == loop_block->last_lir_instruction_id() + 2) {
5068             optimal_split_pos = -1;
5069             TRACE_LINEAR_SCAN(4, tty->print_cr("      loop optimization not necessary"));
5070           } else {
5071             TRACE_LINEAR_SCAN(4, tty->print_cr("      loop optimization successful"));
5072           }
5073         }
5074       }
5075 
5076       if (optimal_split_pos == -1) {
5077         // not calculated by loop optimization
5078         optimal_split_pos = find_optimal_split_pos(min_block, max_block, max_split_pos);
5079       }
5080     }
5081   }
5082   TRACE_LINEAR_SCAN(4, tty->print_cr("      optimal split position: %d", optimal_split_pos));
5083 
5084   return optimal_split_pos;
5085 }
5086 
5087 
5088 /*
5089   split an interval at the optimal position between min_split_pos and
5090   max_split_pos in two parts:
5091   1) the left part has already a location assigned
5092   2) the right part is sorted into to the unhandled-list
5093 */
5094 void LinearScanWalker::split_before_usage(Interval* it, int min_split_pos, int max_split_pos) {
5095   TRACE_LINEAR_SCAN(2, tty->print   ("----- splitting interval: "); it->print());
5096   TRACE_LINEAR_SCAN(2, tty->print_cr("      between %d and %d", min_split_pos, max_split_pos));
5097 
5098   assert(it->from() < min_split_pos,         "cannot split at start of interval");
5099   assert(current_position() < min_split_pos, "cannot split before current position");
5100   assert(min_split_pos <= max_split_pos,     "invalid order");
5101   assert(max_split_pos <= it->to(),          "cannot split after end of interval");
5102 
5103   int optimal_split_pos = find_optimal_split_pos(it, min_split_pos, max_split_pos, true);
5104 
5105   assert(min_split_pos <= optimal_split_pos && optimal_split_pos <= max_split_pos, "out of range");
5106   assert(optimal_split_pos <= it->to(),  "cannot split after end of interval");
5107   assert(optimal_split_pos > it->from(), "cannot split at start of interval");
5108 
5109   if (optimal_split_pos == it->to() && it->next_usage(mustHaveRegister, min_split_pos) == max_jint) {
5110     // the split position would be just before the end of the interval
5111     // -> no split at all necessary
5112     TRACE_LINEAR_SCAN(4, tty->print_cr("      no split necessary because optimal split position is at end of interval"));
5113     return;
5114   }
5115 
5116   // must calculate this before the actual split is performed and before split position is moved to odd op_id
5117   bool move_necessary = !allocator()->is_block_begin(optimal_split_pos) && !it->has_hole_between(optimal_split_pos - 1, optimal_split_pos);
5118 
5119   if (!allocator()->is_block_begin(optimal_split_pos)) {
5120     // move position before actual instruction (odd op_id)
5121     optimal_split_pos = (optimal_split_pos - 1) | 1;
5122   }
5123 
5124   TRACE_LINEAR_SCAN(4, tty->print_cr("      splitting at position %d", optimal_split_pos));
5125   assert(allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 1), "split pos must be odd when not on block boundary");
5126   assert(!allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 0), "split pos must be even on block boundary");
5127 
5128   Interval* split_part = it->split(optimal_split_pos);
5129 
5130   allocator()->append_interval(split_part);
5131   allocator()->copy_register_flags(it, split_part);
5132   split_part->set_insert_move_when_activated(move_necessary);
5133   append_to_unhandled(unhandled_first_addr(anyKind), split_part);
5134 
5135   TRACE_LINEAR_SCAN(2, tty->print_cr("      split interval in two parts (insert_move_when_activated: %d)", move_necessary));
5136   TRACE_LINEAR_SCAN(2, tty->print   ("      "); it->print());
5137   TRACE_LINEAR_SCAN(2, tty->print   ("      "); split_part->print());
5138 }
5139 
5140 /*
5141   split an interval at the optimal position between min_split_pos and
5142   max_split_pos in two parts:
5143   1) the left part has already a location assigned
5144   2) the right part is always on the stack and therefore ignored in further processing
5145 */
5146 void LinearScanWalker::split_for_spilling(Interval* it) {
5147   // calculate allowed range of splitting position
5148   int max_split_pos = current_position();
5149   int min_split_pos = MAX2(it->previous_usage(shouldHaveRegister, max_split_pos) + 1, it->from());
5150 
5151   TRACE_LINEAR_SCAN(2, tty->print   ("----- splitting and spilling interval: "); it->print());
5152   TRACE_LINEAR_SCAN(2, tty->print_cr("      between %d and %d", min_split_pos, max_split_pos));
5153 
5154   assert(it->state() == activeState,     "why spill interval that is not active?");
5155   assert(it->from() <= min_split_pos,    "cannot split before start of interval");
5156   assert(min_split_pos <= max_split_pos, "invalid order");
5157   assert(max_split_pos < it->to(),       "cannot split at end end of interval");
5158   assert(current_position() < it->to(),  "interval must not end before current position");
5159 
5160   if (min_split_pos == it->from()) {
5161     // the whole interval is never used, so spill it entirely to memory
5162     TRACE_LINEAR_SCAN(2, tty->print_cr("      spilling entire interval because split pos is at beginning of interval"));
5163     assert(it->first_usage(shouldHaveRegister) > current_position(), "interval must not have use position before current_position");
5164 
5165     allocator()->assign_spill_slot(it);
5166     allocator()->change_spill_state(it, min_split_pos);
5167 
5168     // Also kick parent intervals out of register to memory when they have no use
5169     // position. This avoids short interval in register surrounded by intervals in
5170     // memory -> avoid useless moves from memory to register and back
5171     Interval* parent = it;
5172     while (parent != NULL && parent->is_split_child()) {
5173       parent = parent->split_child_before_op_id(parent->from());
5174 
5175       if (parent->assigned_reg() < LinearScan::nof_regs) {
5176         if (parent->first_usage(shouldHaveRegister) == max_jint) {
5177           // parent is never used, so kick it out of its assigned register
5178           TRACE_LINEAR_SCAN(4, tty->print_cr("      kicking out interval %d out of its register because it is never used", parent->reg_num()));
5179           allocator()->assign_spill_slot(parent);
5180         } else {
5181           // do not go further back because the register is actually used by the interval
5182           parent = NULL;
5183         }
5184       }
5185     }
5186 
5187   } else {
5188     // search optimal split pos, split interval and spill only the right hand part
5189     int optimal_split_pos = find_optimal_split_pos(it, min_split_pos, max_split_pos, false);
5190 
5191     assert(min_split_pos <= optimal_split_pos && optimal_split_pos <= max_split_pos, "out of range");
5192     assert(optimal_split_pos < it->to(), "cannot split at end of interval");
5193     assert(optimal_split_pos >= it->from(), "cannot split before start of interval");
5194 
5195     if (!allocator()->is_block_begin(optimal_split_pos)) {
5196       // move position before actual instruction (odd op_id)
5197       optimal_split_pos = (optimal_split_pos - 1) | 1;
5198     }
5199 
5200     TRACE_LINEAR_SCAN(4, tty->print_cr("      splitting at position %d", optimal_split_pos));
5201     assert(allocator()->is_block_begin(optimal_split_pos)  || (optimal_split_pos % 2 == 1), "split pos must be odd when not on block boundary");
5202     assert(!allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 0), "split pos must be even on block boundary");
5203 
5204     Interval* spilled_part = it->split(optimal_split_pos);
5205     allocator()->append_interval(spilled_part);
5206     allocator()->assign_spill_slot(spilled_part);
5207     allocator()->change_spill_state(spilled_part, optimal_split_pos);
5208 
5209     if (!allocator()->is_block_begin(optimal_split_pos)) {
5210       TRACE_LINEAR_SCAN(4, tty->print_cr("      inserting move from interval %d to %d", it->reg_num(), spilled_part->reg_num()));
5211       insert_move(optimal_split_pos, it, spilled_part);
5212     }
5213 
5214     // the current_split_child is needed later when moves are inserted for reloading
5215     assert(spilled_part->current_split_child() == it, "overwriting wrong current_split_child");
5216     spilled_part->make_current_split_child();
5217 
5218     TRACE_LINEAR_SCAN(2, tty->print_cr("      split interval in two parts"));
5219     TRACE_LINEAR_SCAN(2, tty->print   ("      "); it->print());
5220     TRACE_LINEAR_SCAN(2, tty->print   ("      "); spilled_part->print());
5221   }
5222 }
5223 
5224 
5225 void LinearScanWalker::split_stack_interval(Interval* it) {
5226   int min_split_pos = current_position() + 1;
5227   int max_split_pos = MIN2(it->first_usage(shouldHaveRegister), it->to());
5228 
5229   split_before_usage(it, min_split_pos, max_split_pos);
5230 }
5231 
5232 void LinearScanWalker::split_when_partial_register_available(Interval* it, int register_available_until) {
5233   int min_split_pos = MAX2(it->previous_usage(shouldHaveRegister, register_available_until), it->from() + 1);
5234   int max_split_pos = register_available_until;
5235 
5236   split_before_usage(it, min_split_pos, max_split_pos);
5237 }
5238 
5239 void LinearScanWalker::split_and_spill_interval(Interval* it) {
5240   assert(it->state() == activeState || it->state() == inactiveState, "other states not allowed");
5241 
5242   int current_pos = current_position();
5243   if (it->state() == inactiveState) {
5244     // the interval is currently inactive, so no spill slot is needed for now.
5245     // when the split part is activated, the interval has a new chance to get a register,
5246     // so in the best case no stack slot is necessary
5247     assert(it->has_hole_between(current_pos - 1, current_pos + 1), "interval can not be inactive otherwise");
5248     split_before_usage(it, current_pos + 1, current_pos + 1);
5249 
5250   } else {
5251     // search the position where the interval must have a register and split
5252     // at the optimal position before.
5253     // The new created part is added to the unhandled list and will get a register
5254     // when it is activated
5255     int min_split_pos = current_pos + 1;
5256     int max_split_pos = MIN2(it->next_usage(mustHaveRegister, min_split_pos), it->to());
5257 
5258     split_before_usage(it, min_split_pos, max_split_pos);
5259 
5260     assert(it->next_usage(mustHaveRegister, current_pos) == max_jint, "the remaining part is spilled to stack and therefore has no register");
5261     split_for_spilling(it);
5262   }
5263 }
5264 
5265 
5266 int LinearScanWalker::find_free_reg(int reg_needed_until, int interval_to, int hint_reg, int ignore_reg, bool* need_split) {
5267   int min_full_reg = any_reg;
5268   int max_partial_reg = any_reg;
5269 
5270   for (int i = _first_reg; i <= _last_reg; i++) {
5271     if (i == ignore_reg) {
5272       // this register must be ignored
5273 
5274     } else if (_use_pos[i] >= interval_to) {
5275       // this register is free for the full interval
5276       if (min_full_reg == any_reg || i == hint_reg || (_use_pos[i] < _use_pos[min_full_reg] && min_full_reg != hint_reg)) {
5277         min_full_reg = i;
5278       }
5279     } else if (_use_pos[i] > reg_needed_until) {
5280       // this register is at least free until reg_needed_until
5281       if (max_partial_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_partial_reg] && max_partial_reg != hint_reg)) {
5282         max_partial_reg = i;
5283       }
5284     }
5285   }
5286 
5287   if (min_full_reg != any_reg) {
5288     return min_full_reg;
5289   } else if (max_partial_reg != any_reg) {
5290     *need_split = true;
5291     return max_partial_reg;
5292   } else {
5293     return any_reg;
5294   }
5295 }
5296 
5297 int LinearScanWalker::find_free_double_reg(int reg_needed_until, int interval_to, int hint_reg, bool* need_split) {
5298   assert((_last_reg - _first_reg + 1) % 2 == 0, "adjust algorithm");
5299 
5300   int min_full_reg = any_reg;
5301   int max_partial_reg = any_reg;
5302 
5303   for (int i = _first_reg; i < _last_reg; i+=2) {
5304     if (_use_pos[i] >= interval_to && _use_pos[i + 1] >= interval_to) {
5305       // this register is free for the full interval
5306       if (min_full_reg == any_reg || i == hint_reg || (_use_pos[i] < _use_pos[min_full_reg] && min_full_reg != hint_reg)) {
5307         min_full_reg = i;
5308       }
5309     } else if (_use_pos[i] > reg_needed_until && _use_pos[i + 1] > reg_needed_until) {
5310       // this register is at least free until reg_needed_until
5311       if (max_partial_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_partial_reg] && max_partial_reg != hint_reg)) {
5312         max_partial_reg = i;
5313       }
5314     }
5315   }
5316 
5317   if (min_full_reg != any_reg) {
5318     return min_full_reg;
5319   } else if (max_partial_reg != any_reg) {
5320     *need_split = true;
5321     return max_partial_reg;
5322   } else {
5323     return any_reg;
5324   }
5325 }
5326 
5327 
5328 bool LinearScanWalker::alloc_free_reg(Interval* cur) {
5329   TRACE_LINEAR_SCAN(2, tty->print("trying to find free register for "); cur->print());
5330 
5331   init_use_lists(true);
5332   free_exclude_active_fixed();
5333   free_exclude_active_any();
5334   free_collect_inactive_fixed(cur);
5335   free_collect_inactive_any(cur);
5336 //  free_collect_unhandled(fixedKind, cur);
5337   assert(unhandled_first(fixedKind) == Interval::end(), "must not have unhandled fixed intervals because all fixed intervals have a use at position 0");
5338 
5339   // _use_pos contains the start of the next interval that has this register assigned
5340   // (either as a fixed register or a normal allocated register in the past)
5341   // only intervals overlapping with cur are processed, non-overlapping invervals can be ignored safely
5342   TRACE_LINEAR_SCAN(4, tty->print_cr("      state of registers:"));
5343   TRACE_LINEAR_SCAN(4, for (int i = _first_reg; i <= _last_reg; i++) tty->print_cr("      reg %d: use_pos: %d", i, _use_pos[i]));
5344 
5345   int hint_reg, hint_regHi;
5346   Interval* register_hint = cur->register_hint();
5347   if (register_hint != NULL) {
5348     hint_reg = register_hint->assigned_reg();
5349     hint_regHi = register_hint->assigned_regHi();
5350 
5351     if (allocator()->is_precolored_cpu_interval(register_hint)) {
5352       assert(hint_reg != any_reg && hint_regHi == any_reg, "must be for fixed intervals");
5353       hint_regHi = hint_reg + 1;  // connect e.g. eax-edx
5354     }
5355     TRACE_LINEAR_SCAN(4, tty->print("      hint registers %d, %d from interval ", hint_reg, hint_regHi); register_hint->print());
5356 
5357   } else {
5358     hint_reg = any_reg;
5359     hint_regHi = any_reg;
5360   }
5361   assert(hint_reg == any_reg || hint_reg != hint_regHi, "hint reg and regHi equal");
5362   assert(cur->assigned_reg() == any_reg && cur->assigned_regHi() == any_reg, "register already assigned to interval");
5363 
5364   // the register must be free at least until this position
5365   int reg_needed_until = cur->from() + 1;
5366   int interval_to = cur->to();
5367 
5368   bool need_split = false;
5369   int split_pos = -1;
5370   int reg = any_reg;
5371   int regHi = any_reg;
5372 
5373   if (_adjacent_regs) {
5374     reg = find_free_double_reg(reg_needed_until, interval_to, hint_reg, &need_split);
5375     regHi = reg + 1;
5376     if (reg == any_reg) {
5377       return false;
5378     }
5379     split_pos = MIN2(_use_pos[reg], _use_pos[regHi]);
5380 
5381   } else {
5382     reg = find_free_reg(reg_needed_until, interval_to, hint_reg, any_reg, &need_split);
5383     if (reg == any_reg) {
5384       return false;
5385     }
5386     split_pos = _use_pos[reg];
5387 
5388     if (_num_phys_regs == 2) {
5389       regHi = find_free_reg(reg_needed_until, interval_to, hint_regHi, reg, &need_split);
5390 
5391       if (_use_pos[reg] < interval_to && regHi == any_reg) {
5392         // do not split interval if only one register can be assigned until the split pos
5393         // (when one register is found for the whole interval, split&spill is only
5394         // performed for the hi register)
5395         return false;
5396 
5397       } else if (regHi != any_reg) {
5398         split_pos = MIN2(split_pos, _use_pos[regHi]);
5399 
5400         // sort register numbers to prevent e.g. a move from eax,ebx to ebx,eax
5401         if (reg > regHi) {
5402           int temp = reg;
5403           reg = regHi;
5404           regHi = temp;
5405         }
5406       }
5407     }
5408   }
5409 
5410   cur->assign_reg(reg, regHi);
5411   TRACE_LINEAR_SCAN(2, tty->print_cr("selected register %d, %d", reg, regHi));
5412 
5413   assert(split_pos > 0, "invalid split_pos");
5414   if (need_split) {
5415     // register not available for full interval, so split it
5416     split_when_partial_register_available(cur, split_pos);
5417   }
5418 
5419   // only return true if interval is completely assigned
5420   return _num_phys_regs == 1 || regHi != any_reg;
5421 }
5422 
5423 
5424 int LinearScanWalker::find_locked_reg(int reg_needed_until, int interval_to, int hint_reg, int ignore_reg, bool* need_split) {
5425   int max_reg = any_reg;
5426 
5427   for (int i = _first_reg; i <= _last_reg; i++) {
5428     if (i == ignore_reg) {
5429       // this register must be ignored
5430 
5431     } else if (_use_pos[i] > reg_needed_until) {
5432       if (max_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_reg] && max_reg != hint_reg)) {
5433         max_reg = i;
5434       }
5435     }
5436   }
5437 
5438   if (max_reg != any_reg && _block_pos[max_reg] <= interval_to) {
5439     *need_split = true;
5440   }
5441 
5442   return max_reg;
5443 }
5444 
5445 int LinearScanWalker::find_locked_double_reg(int reg_needed_until, int interval_to, int hint_reg, bool* need_split) {
5446   assert((_last_reg - _first_reg + 1) % 2 == 0, "adjust algorithm");
5447 
5448   int max_reg = any_reg;
5449 
5450   for (int i = _first_reg; i < _last_reg; i+=2) {
5451     if (_use_pos[i] > reg_needed_until && _use_pos[i + 1] > reg_needed_until) {
5452       if (max_reg == any_reg || _use_pos[i] > _use_pos[max_reg]) {
5453         max_reg = i;
5454       }
5455     }
5456   }
5457 
5458   if (_block_pos[max_reg] <= interval_to || _block_pos[max_reg + 1] <= interval_to) {
5459     *need_split = true;
5460   }
5461 
5462   return max_reg;
5463 }
5464 
5465 void LinearScanWalker::split_and_spill_intersecting_intervals(int reg, int regHi) {
5466   assert(reg != any_reg, "no register assigned");
5467 
5468   for (int i = 0; i < _spill_intervals[reg]->length(); i++) {
5469     Interval* it = _spill_intervals[reg]->at(i);
5470     remove_from_list(it);
5471     split_and_spill_interval(it);
5472   }
5473 
5474   if (regHi != any_reg) {
5475     IntervalList* processed = _spill_intervals[reg];
5476     for (int i = 0; i < _spill_intervals[regHi]->length(); i++) {
5477       Interval* it = _spill_intervals[regHi]->at(i);
5478       if (processed->index_of(it) == -1) {
5479         remove_from_list(it);
5480         split_and_spill_interval(it);
5481       }
5482     }
5483   }
5484 }
5485 
5486 
5487 // Split an Interval and spill it to memory so that cur can be placed in a register
5488 void LinearScanWalker::alloc_locked_reg(Interval* cur) {
5489   TRACE_LINEAR_SCAN(2, tty->print("need to split and spill to get register for "); cur->print());
5490 
5491   // collect current usage of registers
5492   init_use_lists(false);
5493   spill_exclude_active_fixed();
5494 //  spill_block_unhandled_fixed(cur);
5495   assert(unhandled_first(fixedKind) == Interval::end(), "must not have unhandled fixed intervals because all fixed intervals have a use at position 0");
5496   spill_block_inactive_fixed(cur);
5497   spill_collect_active_any();
5498   spill_collect_inactive_any(cur);
5499 
5500 #ifndef PRODUCT
5501   if (TraceLinearScanLevel >= 4) {
5502     tty->print_cr("      state of registers:");
5503     for (int i = _first_reg; i <= _last_reg; i++) {
5504       tty->print("      reg %d: use_pos: %d, block_pos: %d, intervals: ", i, _use_pos[i], _block_pos[i]);
5505       for (int j = 0; j < _spill_intervals[i]->length(); j++) {
5506         tty->print("%d ", _spill_intervals[i]->at(j)->reg_num());
5507       }
5508       tty->cr();
5509     }
5510   }
5511 #endif
5512 
5513   // the register must be free at least until this position
5514   int reg_needed_until = MIN2(cur->first_usage(mustHaveRegister), cur->from() + 1);
5515   int interval_to = cur->to();
5516   assert (reg_needed_until > 0 && reg_needed_until < max_jint, "interval has no use");
5517 
5518   int split_pos = 0;
5519   int use_pos = 0;
5520   bool need_split = false;
5521   int reg, regHi;
5522 
5523   if (_adjacent_regs) {
5524     reg = find_locked_double_reg(reg_needed_until, interval_to, any_reg, &need_split);
5525     regHi = reg + 1;
5526 
5527     if (reg != any_reg) {
5528       use_pos = MIN2(_use_pos[reg], _use_pos[regHi]);
5529       split_pos = MIN2(_block_pos[reg], _block_pos[regHi]);
5530     }
5531   } else {
5532     reg = find_locked_reg(reg_needed_until, interval_to, any_reg, cur->assigned_reg(), &need_split);
5533     regHi = any_reg;
5534 
5535     if (reg != any_reg) {
5536       use_pos = _use_pos[reg];
5537       split_pos = _block_pos[reg];
5538 
5539       if (_num_phys_regs == 2) {
5540         if (cur->assigned_reg() != any_reg) {
5541           regHi = reg;
5542           reg = cur->assigned_reg();
5543         } else {
5544           regHi = find_locked_reg(reg_needed_until, interval_to, any_reg, reg, &need_split);
5545           if (regHi != any_reg) {
5546             use_pos = MIN2(use_pos, _use_pos[regHi]);
5547             split_pos = MIN2(split_pos, _block_pos[regHi]);
5548           }
5549         }
5550 
5551         if (regHi != any_reg && reg > regHi) {
5552           // sort register numbers to prevent e.g. a move from eax,ebx to ebx,eax
5553           int temp = reg;
5554           reg = regHi;
5555           regHi = temp;
5556         }
5557       }
5558     }
5559   }
5560 
5561   if (reg == any_reg || (_num_phys_regs == 2 && regHi == any_reg) || use_pos <= cur->first_usage(mustHaveRegister)) {
5562     // the first use of cur is later than the spilling position -> spill cur
5563     TRACE_LINEAR_SCAN(4, tty->print_cr("able to spill current interval. first_usage(register): %d, use_pos: %d", cur->first_usage(mustHaveRegister), use_pos));
5564 
5565     if (cur->first_usage(mustHaveRegister) <= cur->from() + 1) {
5566       assert(false, "cannot spill interval that is used in first instruction (possible reason: no register found)");
5567       // assign a reasonable register and do a bailout in product mode to avoid errors
5568       allocator()->assign_spill_slot(cur);
5569       BAILOUT("LinearScan: no register found");
5570     }
5571 
5572     split_and_spill_interval(cur);
5573   } else {
5574     TRACE_LINEAR_SCAN(4, tty->print_cr("decided to use register %d, %d", reg, regHi));
5575     assert(reg != any_reg && (_num_phys_regs == 1 || regHi != any_reg), "no register found");
5576     assert(split_pos > 0, "invalid split_pos");
5577     assert(need_split == false || split_pos > cur->from(), "splitting interval at from");
5578 
5579     cur->assign_reg(reg, regHi);
5580     if (need_split) {
5581       // register not available for full interval, so split it
5582       split_when_partial_register_available(cur, split_pos);
5583     }
5584 
5585     // perform splitting and spilling for all affected intervalls
5586     split_and_spill_intersecting_intervals(reg, regHi);
5587   }
5588 }
5589 
5590 bool LinearScanWalker::no_allocation_possible(Interval* cur) {
5591 #ifdef X86
5592   // fast calculation of intervals that can never get a register because the
5593   // the next instruction is a call that blocks all registers
5594   // Note: this does not work if callee-saved registers are available (e.g. on Sparc)
5595 
5596   // check if this interval is the result of a split operation
5597   // (an interval got a register until this position)
5598   int pos = cur->from();
5599   if ((pos & 1) == 1) {
5600     // the current instruction is a call that blocks all registers
5601     if (pos < allocator()->max_lir_op_id() && allocator()->has_call(pos + 1)) {
5602       TRACE_LINEAR_SCAN(4, tty->print_cr("      free register cannot be available because all registers blocked by following call"));
5603 
5604       // safety check that there is really no register available
5605       assert(alloc_free_reg(cur) == false, "found a register for this interval");
5606       return true;
5607     }
5608 
5609   }
5610 #endif
5611   return false;
5612 }
5613 
5614 void LinearScanWalker::init_vars_for_alloc(Interval* cur) {
5615   BasicType type = cur->type();
5616   _num_phys_regs = LinearScan::num_physical_regs(type);
5617   _adjacent_regs = LinearScan::requires_adjacent_regs(type);
5618 
5619   if (pd_init_regs_for_alloc(cur)) {
5620     // the appropriate register range was selected.
5621   } else if (type == T_FLOAT || type == T_DOUBLE) {
5622     _first_reg = pd_first_fpu_reg;
5623     _last_reg = pd_last_fpu_reg;
5624   } else {
5625     _first_reg = pd_first_cpu_reg;
5626     _last_reg = FrameMap::last_cpu_reg();
5627   }
5628 
5629   assert(0 <= _first_reg && _first_reg < LinearScan::nof_regs, "out of range");
5630   assert(0 <= _last_reg && _last_reg < LinearScan::nof_regs, "out of range");
5631 }
5632 
5633 
5634 bool LinearScanWalker::is_move(LIR_Op* op, Interval* from, Interval* to) {
5635   if (op->code() != lir_move) {
5636     return false;
5637   }
5638   assert(op->as_Op1() != NULL, "move must be LIR_Op1");
5639 
5640   LIR_Opr in = ((LIR_Op1*)op)->in_opr();
5641   LIR_Opr res = ((LIR_Op1*)op)->result_opr();
5642   return in->is_virtual() && res->is_virtual() && in->vreg_number() == from->reg_num() && res->vreg_number() == to->reg_num();
5643 }
5644 
5645 // optimization (especially for phi functions of nested loops):
5646 // assign same spill slot to non-intersecting intervals
5647 void LinearScanWalker::combine_spilled_intervals(Interval* cur) {
5648   if (cur->is_split_child()) {
5649     // optimization is only suitable for split parents
5650     return;
5651   }
5652 
5653   Interval* register_hint = cur->register_hint(false);
5654   if (register_hint == NULL) {
5655     // cur is not the target of a move, otherwise register_hint would be set
5656     return;
5657   }
5658   assert(register_hint->is_split_parent(), "register hint must be split parent");
5659 
5660   if (cur->spill_state() != noOptimization || register_hint->spill_state() != noOptimization) {
5661     // combining the stack slots for intervals where spill move optimization is applied
5662     // is not benefitial and would cause problems
5663     return;
5664   }
5665 
5666   int begin_pos = cur->from();
5667   int end_pos = cur->to();
5668   if (end_pos > allocator()->max_lir_op_id() || (begin_pos & 1) != 0 || (end_pos & 1) != 0) {
5669     // safety check that lir_op_with_id is allowed
5670     return;
5671   }
5672 
5673   if (!is_move(allocator()->lir_op_with_id(begin_pos), register_hint, cur) || !is_move(allocator()->lir_op_with_id(end_pos), cur, register_hint)) {
5674     // cur and register_hint are not connected with two moves
5675     return;
5676   }
5677 
5678   Interval* begin_hint = register_hint->split_child_at_op_id(begin_pos, LIR_OpVisitState::inputMode);
5679   Interval* end_hint = register_hint->split_child_at_op_id(end_pos, LIR_OpVisitState::outputMode);
5680   if (begin_hint == end_hint || begin_hint->to() != begin_pos || end_hint->from() != end_pos) {
5681     // register_hint must be split, otherwise the re-writing of use positions does not work
5682     return;
5683   }
5684 
5685   assert(begin_hint->assigned_reg() != any_reg, "must have register assigned");
5686   assert(end_hint->assigned_reg() == any_reg, "must not have register assigned");
5687   assert(cur->first_usage(mustHaveRegister) == begin_pos, "must have use position at begin of interval because of move");
5688   assert(end_hint->first_usage(mustHaveRegister) == end_pos, "must have use position at begin of interval because of move");
5689 
5690   if (begin_hint->assigned_reg() < LinearScan::nof_regs) {
5691     // register_hint is not spilled at begin_pos, so it would not be benefitial to immediately spill cur
5692     return;
5693   }
5694   assert(register_hint->canonical_spill_slot() != -1, "must be set when part of interval was spilled");
5695 
5696   // modify intervals such that cur gets the same stack slot as register_hint
5697   // delete use positions to prevent the intervals to get a register at beginning
5698   cur->set_canonical_spill_slot(register_hint->canonical_spill_slot());
5699   cur->remove_first_use_pos();
5700   end_hint->remove_first_use_pos();
5701 }
5702 
5703 
5704 // allocate a physical register or memory location to an interval
5705 bool LinearScanWalker::activate_current() {
5706   Interval* cur = current();
5707   bool result = true;
5708 
5709   TRACE_LINEAR_SCAN(2, tty->print   ("+++++ activating interval "); cur->print());
5710   TRACE_LINEAR_SCAN(4, tty->print_cr("      split_parent: %d, insert_move_when_activated: %d", cur->split_parent()->reg_num(), cur->insert_move_when_activated()));
5711 
5712   if (cur->assigned_reg() >= LinearScan::nof_regs) {
5713     // activating an interval that has a stack slot assigned -> split it at first use position
5714     // used for method parameters
5715     TRACE_LINEAR_SCAN(4, tty->print_cr("      interval has spill slot assigned (method parameter) -> split it before first use"));
5716 
5717     split_stack_interval(cur);
5718     result = false;
5719 
5720   } else if (allocator()->gen()->is_vreg_flag_set(cur->reg_num(), LIRGenerator::must_start_in_memory)) {
5721     // activating an interval that must start in a stack slot, but may get a register later
5722     // used for lir_roundfp: rounding is done by store to stack and reload later
5723     TRACE_LINEAR_SCAN(4, tty->print_cr("      interval must start in stack slot -> split it before first use"));
5724     assert(cur->assigned_reg() == any_reg && cur->assigned_regHi() == any_reg, "register already assigned");
5725 
5726     allocator()->assign_spill_slot(cur);
5727     split_stack_interval(cur);
5728     result = false;
5729 
5730   } else if (cur->assigned_reg() == any_reg) {
5731     // interval has not assigned register -> normal allocation
5732     // (this is the normal case for most intervals)
5733     TRACE_LINEAR_SCAN(4, tty->print_cr("      normal allocation of register"));
5734 
5735     // assign same spill slot to non-intersecting intervals
5736     combine_spilled_intervals(cur);
5737 
5738     init_vars_for_alloc(cur);
5739     if (no_allocation_possible(cur) || !alloc_free_reg(cur)) {
5740       // no empty register available.
5741       // split and spill another interval so that this interval gets a register
5742       alloc_locked_reg(cur);
5743     }
5744 
5745     // spilled intervals need not be move to active-list
5746     if (cur->assigned_reg() >= LinearScan::nof_regs) {
5747       result = false;
5748     }
5749   }
5750 
5751   // load spilled values that become active from stack slot to register
5752   if (cur->insert_move_when_activated()) {
5753     assert(cur->is_split_child(), "must be");
5754     assert(cur->current_split_child() != NULL, "must be");
5755     assert(cur->current_split_child()->reg_num() != cur->reg_num(), "cannot insert move between same interval");
5756     TRACE_LINEAR_SCAN(4, tty->print_cr("Inserting move from interval %d to %d because insert_move_when_activated is set", cur->current_split_child()->reg_num(), cur->reg_num()));
5757 
5758     insert_move(cur->from(), cur->current_split_child(), cur);
5759   }
5760   cur->make_current_split_child();
5761 
5762   return result; // true = interval is moved to active list
5763 }
5764 
5765 
5766 // Implementation of EdgeMoveOptimizer
5767 
5768 EdgeMoveOptimizer::EdgeMoveOptimizer() :
5769   _edge_instructions(4),
5770   _edge_instructions_idx(4)
5771 {
5772 }
5773 
5774 void EdgeMoveOptimizer::optimize(BlockList* code) {
5775   EdgeMoveOptimizer optimizer = EdgeMoveOptimizer();
5776 
5777   // ignore the first block in the list (index 0 is not processed)
5778   for (int i = code->length() - 1; i >= 1; i--) {
5779     BlockBegin* block = code->at(i);
5780 
5781     if (block->number_of_preds() > 1 && !block->is_set(BlockBegin::exception_entry_flag)) {
5782       optimizer.optimize_moves_at_block_end(block);
5783     }
5784     if (block->number_of_sux() == 2) {
5785       optimizer.optimize_moves_at_block_begin(block);
5786     }
5787   }
5788 }
5789 
5790 
5791 // clear all internal data structures
5792 void EdgeMoveOptimizer::init_instructions() {
5793   _edge_instructions.clear();
5794   _edge_instructions_idx.clear();
5795 }
5796 
5797 // append a lir-instruction-list and the index of the current operation in to the list
5798 void EdgeMoveOptimizer::append_instructions(LIR_OpList* instructions, int instructions_idx) {
5799   _edge_instructions.append(instructions);
5800   _edge_instructions_idx.append(instructions_idx);
5801 }
5802 
5803 // return the current operation of the given edge (predecessor or successor)
5804 LIR_Op* EdgeMoveOptimizer::instruction_at(int edge) {
5805   LIR_OpList* instructions = _edge_instructions.at(edge);
5806   int idx = _edge_instructions_idx.at(edge);
5807 
5808   if (idx < instructions->length()) {
5809     return instructions->at(idx);
5810   } else {
5811     return NULL;
5812   }
5813 }
5814 
5815 // removes the current operation of the given edge (predecessor or successor)
5816 void EdgeMoveOptimizer::remove_cur_instruction(int edge, bool decrement_index) {
5817   LIR_OpList* instructions = _edge_instructions.at(edge);
5818   int idx = _edge_instructions_idx.at(edge);
5819   instructions->remove_at(idx);
5820 
5821   if (decrement_index) {
5822     _edge_instructions_idx.at_put(edge, idx - 1);
5823   }
5824 }
5825 
5826 
5827 bool EdgeMoveOptimizer::operations_different(LIR_Op* op1, LIR_Op* op2) {
5828   if (op1 == NULL || op2 == NULL) {
5829     // at least one block is already empty -> no optimization possible
5830     return true;
5831   }
5832 
5833   if (op1->code() == lir_move && op2->code() == lir_move) {
5834     assert(op1->as_Op1() != NULL, "move must be LIR_Op1");
5835     assert(op2->as_Op1() != NULL, "move must be LIR_Op1");
5836     LIR_Op1* move1 = (LIR_Op1*)op1;
5837     LIR_Op1* move2 = (LIR_Op1*)op2;
5838     if (move1->info() == move2->info() && move1->in_opr() == move2->in_opr() && move1->result_opr() == move2->result_opr()) {
5839       // these moves are exactly equal and can be optimized
5840       return false;
5841     }
5842 
5843   } else if (op1->code() == lir_fxch && op2->code() == lir_fxch) {
5844     assert(op1->as_Op1() != NULL, "fxch must be LIR_Op1");
5845     assert(op2->as_Op1() != NULL, "fxch must be LIR_Op1");
5846     LIR_Op1* fxch1 = (LIR_Op1*)op1;
5847     LIR_Op1* fxch2 = (LIR_Op1*)op2;
5848     if (fxch1->in_opr()->as_jint() == fxch2->in_opr()->as_jint()) {
5849       // equal FPU stack operations can be optimized
5850       return false;
5851     }
5852 
5853   } else if (op1->code() == lir_fpop_raw && op2->code() == lir_fpop_raw) {
5854     // equal FPU stack operations can be optimized
5855     return false;
5856   }
5857 
5858   // no optimization possible
5859   return true;
5860 }
5861 
5862 void EdgeMoveOptimizer::optimize_moves_at_block_end(BlockBegin* block) {
5863   TRACE_LINEAR_SCAN(4, tty->print_cr("optimizing moves at end of block B%d", block->block_id()));
5864 
5865   if (block->is_predecessor(block)) {
5866     // currently we can't handle this correctly.
5867     return;
5868   }
5869 
5870   init_instructions();
5871   int num_preds = block->number_of_preds();
5872   assert(num_preds > 1, "do not call otherwise");
5873   assert(!block->is_set(BlockBegin::exception_entry_flag), "exception handlers not allowed");
5874 
5875   // setup a list with the lir-instructions of all predecessors
5876   int i;
5877   for (i = 0; i < num_preds; i++) {
5878     BlockBegin* pred = block->pred_at(i);
5879     LIR_OpList* pred_instructions = pred->lir()->instructions_list();
5880 
5881     if (pred->number_of_sux() != 1) {
5882       // this can happen with switch-statements where multiple edges are between
5883       // the same blocks.
5884       return;
5885     }
5886 
5887     assert(pred->number_of_sux() == 1, "can handle only one successor");
5888     assert(pred->sux_at(0) == block, "invalid control flow");
5889     assert(pred_instructions->last()->code() == lir_branch, "block with successor must end with branch");
5890     assert(pred_instructions->last()->as_OpBranch() != NULL, "branch must be LIR_OpBranch");
5891     assert(pred_instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block must end with unconditional branch");
5892 
5893     if (pred_instructions->last()->info() != NULL) {
5894       // can not optimize instructions when debug info is needed
5895       return;
5896     }
5897 
5898     // ignore the unconditional branch at the end of the block
5899     append_instructions(pred_instructions, pred_instructions->length() - 2);
5900   }
5901 
5902 
5903   // process lir-instructions while all predecessors end with the same instruction
5904   while (true) {
5905     LIR_Op* op = instruction_at(0);
5906     for (i = 1; i < num_preds; i++) {
5907       if (operations_different(op, instruction_at(i))) {
5908         // these instructions are different and cannot be optimized ->
5909         // no further optimization possible
5910         return;
5911       }
5912     }
5913 
5914     TRACE_LINEAR_SCAN(4, tty->print("found instruction that is equal in all %d predecessors: ", num_preds); op->print());
5915 
5916     // insert the instruction at the beginning of the current block
5917     block->lir()->insert_before(1, op);
5918 
5919     // delete the instruction at the end of all predecessors
5920     for (i = 0; i < num_preds; i++) {
5921       remove_cur_instruction(i, true);
5922     }
5923   }
5924 }
5925 
5926 
5927 void EdgeMoveOptimizer::optimize_moves_at_block_begin(BlockBegin* block) {
5928   TRACE_LINEAR_SCAN(4, tty->print_cr("optimization moves at begin of block B%d", block->block_id()));
5929 
5930   init_instructions();
5931   int num_sux = block->number_of_sux();
5932 
5933   LIR_OpList* cur_instructions = block->lir()->instructions_list();
5934 
5935   assert(num_sux == 2, "method should not be called otherwise");
5936   assert(cur_instructions->last()->code() == lir_branch, "block with successor must end with branch");
5937   assert(cur_instructions->last()->as_OpBranch() != NULL, "branch must be LIR_OpBranch");
5938   assert(cur_instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block must end with unconditional branch");
5939 
5940   if (cur_instructions->last()->info() != NULL) {
5941     // can no optimize instructions when debug info is needed
5942     return;
5943   }
5944 
5945   LIR_Op* branch = cur_instructions->at(cur_instructions->length() - 2);
5946   if (branch->info() != NULL || (branch->code() != lir_branch && branch->code() != lir_cond_float_branch)) {
5947     // not a valid case for optimization
5948     // currently, only blocks that end with two branches (conditional branch followed
5949     // by unconditional branch) are optimized
5950     return;
5951   }
5952 
5953   // now it is guaranteed that the block ends with two branch instructions.
5954   // the instructions are inserted at the end of the block before these two branches
5955   int insert_idx = cur_instructions->length() - 2;
5956 
5957   int i;
5958 #ifdef ASSERT
5959   for (i = insert_idx - 1; i >= 0; i--) {
5960     LIR_Op* op = cur_instructions->at(i);
5961     if ((op->code() == lir_branch || op->code() == lir_cond_float_branch) && ((LIR_OpBranch*)op)->block() != NULL) {
5962       assert(false, "block with two successors can have only two branch instructions");
5963     }
5964   }
5965 #endif
5966 
5967   // setup a list with the lir-instructions of all successors
5968   for (i = 0; i < num_sux; i++) {
5969     BlockBegin* sux = block->sux_at(i);
5970     LIR_OpList* sux_instructions = sux->lir()->instructions_list();
5971 
5972     assert(sux_instructions->at(0)->code() == lir_label, "block must start with label");
5973 
5974     if (sux->number_of_preds() != 1) {
5975       // this can happen with switch-statements where multiple edges are between
5976       // the same blocks.
5977       return;
5978     }
5979     assert(sux->pred_at(0) == block, "invalid control flow");
5980     assert(!sux->is_set(BlockBegin::exception_entry_flag), "exception handlers not allowed");
5981 
5982     // ignore the label at the beginning of the block
5983     append_instructions(sux_instructions, 1);
5984   }
5985 
5986   // process lir-instructions while all successors begin with the same instruction
5987   while (true) {
5988     LIR_Op* op = instruction_at(0);
5989     for (i = 1; i < num_sux; i++) {
5990       if (operations_different(op, instruction_at(i))) {
5991         // these instructions are different and cannot be optimized ->
5992         // no further optimization possible
5993         return;
5994       }
5995     }
5996 
5997     TRACE_LINEAR_SCAN(4, tty->print("----- found instruction that is equal in all %d successors: ", num_sux); op->print());
5998 
5999     // insert instruction at end of current block
6000     block->lir()->insert_before(insert_idx, op);
6001     insert_idx++;
6002 
6003     // delete the instructions at the beginning of all successors
6004     for (i = 0; i < num_sux; i++) {
6005       remove_cur_instruction(i, false);
6006     }
6007   }
6008 }
6009 
6010 
6011 // Implementation of ControlFlowOptimizer
6012 
6013 ControlFlowOptimizer::ControlFlowOptimizer() :
6014   _original_preds(4)
6015 {
6016 }
6017 
6018 void ControlFlowOptimizer::optimize(BlockList* code) {
6019   ControlFlowOptimizer optimizer = ControlFlowOptimizer();
6020 
6021   // push the OSR entry block to the end so that we're not jumping over it.
6022   BlockBegin* osr_entry = code->at(0)->end()->as_Base()->osr_entry();
6023   if (osr_entry) {
6024     int index = osr_entry->linear_scan_number();
6025     assert(code->at(index) == osr_entry, "wrong index");
6026     code->remove_at(index);
6027     code->append(osr_entry);
6028   }
6029 
6030   optimizer.reorder_short_loops(code);
6031   optimizer.delete_empty_blocks(code);
6032   optimizer.delete_unnecessary_jumps(code);
6033   optimizer.delete_jumps_to_return(code);
6034 }
6035 
6036 void ControlFlowOptimizer::reorder_short_loop(BlockList* code, BlockBegin* header_block, int header_idx) {
6037   int i = header_idx + 1;
6038   int max_end = MIN2(header_idx + ShortLoopSize, code->length());
6039   while (i < max_end && code->at(i)->loop_depth() >= header_block->loop_depth()) {
6040     i++;
6041   }
6042 
6043   if (i == code->length() || code->at(i)->loop_depth() < header_block->loop_depth()) {
6044     int end_idx = i - 1;
6045     BlockBegin* end_block = code->at(end_idx);
6046 
6047     if (end_block->number_of_sux() == 1 && end_block->sux_at(0) == header_block) {
6048       // short loop from header_idx to end_idx found -> reorder blocks such that
6049       // the header_block is the last block instead of the first block of the loop
6050       TRACE_LINEAR_SCAN(1, tty->print_cr("Reordering short loop: length %d, header B%d, end B%d",
6051                                          end_idx - header_idx + 1,
6052                                          header_block->block_id(), end_block->block_id()));
6053 
6054       for (int j = header_idx; j < end_idx; j++) {
6055         code->at_put(j, code->at(j + 1));
6056       }
6057       code->at_put(end_idx, header_block);
6058 
6059       // correct the flags so that any loop alignment occurs in the right place.
6060       assert(code->at(end_idx)->is_set(BlockBegin::backward_branch_target_flag), "must be backward branch target");
6061       code->at(end_idx)->clear(BlockBegin::backward_branch_target_flag);
6062       code->at(header_idx)->set(BlockBegin::backward_branch_target_flag);
6063     }
6064   }
6065 }
6066 
6067 void ControlFlowOptimizer::reorder_short_loops(BlockList* code) {
6068   for (int i = code->length() - 1; i >= 0; i--) {
6069     BlockBegin* block = code->at(i);
6070 
6071     if (block->is_set(BlockBegin::linear_scan_loop_header_flag)) {
6072       reorder_short_loop(code, block, i);
6073     }
6074   }
6075 
6076   DEBUG_ONLY(verify(code));
6077 }
6078 
6079 // only blocks with exactly one successor can be deleted. Such blocks
6080 // must always end with an unconditional branch to this successor
6081 bool ControlFlowOptimizer::can_delete_block(BlockBegin* block) {
6082   if (block->number_of_sux() != 1 || block->number_of_exception_handlers() != 0 || block->is_entry_block()) {
6083     return false;
6084   }
6085 
6086   LIR_OpList* instructions = block->lir()->instructions_list();
6087 
6088   assert(instructions->length() >= 2, "block must have label and branch");
6089   assert(instructions->at(0)->code() == lir_label, "first instruction must always be a label");
6090   assert(instructions->last()->as_OpBranch() != NULL, "last instrcution must always be a branch");
6091   assert(instructions->last()->as_OpBranch()->cond() == lir_cond_always, "branch must be unconditional");
6092   assert(instructions->last()->as_OpBranch()->block() == block->sux_at(0), "branch target must be the successor");
6093 
6094   // block must have exactly one successor
6095 
6096   if (instructions->length() == 2 && instructions->last()->info() == NULL) {
6097     return true;
6098   }
6099   return false;
6100 }
6101 
6102 // substitute branch targets in all branch-instructions of this blocks
6103 void ControlFlowOptimizer::substitute_branch_target(BlockBegin* block, BlockBegin* target_from, BlockBegin* target_to) {
6104   TRACE_LINEAR_SCAN(3, tty->print_cr("Deleting empty block: substituting from B%d to B%d inside B%d", target_from->block_id(), target_to->block_id(), block->block_id()));
6105 
6106   LIR_OpList* instructions = block->lir()->instructions_list();
6107 
6108   assert(instructions->at(0)->code() == lir_label, "first instruction must always be a label");
6109   for (int i = instructions->length() - 1; i >= 1; i--) {
6110     LIR_Op* op = instructions->at(i);
6111 
6112     if (op->code() == lir_branch || op->code() == lir_cond_float_branch) {
6113       assert(op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch");
6114       LIR_OpBranch* branch = (LIR_OpBranch*)op;
6115 
6116       if (branch->block() == target_from) {
6117         branch->change_block(target_to);
6118       }
6119       if (branch->ublock() == target_from) {
6120         branch->change_ublock(target_to);
6121       }
6122     }
6123   }
6124 }
6125 
6126 void ControlFlowOptimizer::delete_empty_blocks(BlockList* code) {
6127   int old_pos = 0;
6128   int new_pos = 0;
6129   int num_blocks = code->length();
6130 
6131   while (old_pos < num_blocks) {
6132     BlockBegin* block = code->at(old_pos);
6133 
6134     if (can_delete_block(block)) {
6135       BlockBegin* new_target = block->sux_at(0);
6136 
6137       // propagate backward branch target flag for correct code alignment
6138       if (block->is_set(BlockBegin::backward_branch_target_flag)) {
6139         new_target->set(BlockBegin::backward_branch_target_flag);
6140       }
6141 
6142       // collect a list with all predecessors that contains each predecessor only once
6143       // the predecessors of cur are changed during the substitution, so a copy of the
6144       // predecessor list is necessary
6145       int j;
6146       _original_preds.clear();
6147       for (j = block->number_of_preds() - 1; j >= 0; j--) {
6148         BlockBegin* pred = block->pred_at(j);
6149         if (_original_preds.index_of(pred) == -1) {
6150           _original_preds.append(pred);
6151         }
6152       }
6153 
6154       for (j = _original_preds.length() - 1; j >= 0; j--) {
6155         BlockBegin* pred = _original_preds.at(j);
6156         substitute_branch_target(pred, block, new_target);
6157         pred->substitute_sux(block, new_target);
6158       }
6159     } else {
6160       // adjust position of this block in the block list if blocks before
6161       // have been deleted
6162       if (new_pos != old_pos) {
6163         code->at_put(new_pos, code->at(old_pos));
6164       }
6165       new_pos++;
6166     }
6167     old_pos++;
6168   }
6169   code->truncate(new_pos);
6170 
6171   DEBUG_ONLY(verify(code));
6172 }
6173 
6174 void ControlFlowOptimizer::delete_unnecessary_jumps(BlockList* code) {
6175   // skip the last block because there a branch is always necessary
6176   for (int i = code->length() - 2; i >= 0; i--) {
6177     BlockBegin* block = code->at(i);
6178     LIR_OpList* instructions = block->lir()->instructions_list();
6179 
6180     LIR_Op* last_op = instructions->last();
6181     if (last_op->code() == lir_branch) {
6182       assert(last_op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch");
6183       LIR_OpBranch* last_branch = (LIR_OpBranch*)last_op;
6184 
6185       assert(last_branch->block() != NULL, "last branch must always have a block as target");
6186       assert(last_branch->label() == last_branch->block()->label(), "must be equal");
6187 
6188       if (last_branch->info() == NULL) {
6189         if (last_branch->block() == code->at(i + 1)) {
6190 
6191           TRACE_LINEAR_SCAN(3, tty->print_cr("Deleting unconditional branch at end of block B%d", block->block_id()));
6192 
6193           // delete last branch instruction
6194           instructions->truncate(instructions->length() - 1);
6195 
6196         } else {
6197           LIR_Op* prev_op = instructions->at(instructions->length() - 2);
6198           if (prev_op->code() == lir_branch || prev_op->code() == lir_cond_float_branch) {
6199             assert(prev_op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch");
6200             LIR_OpBranch* prev_branch = (LIR_OpBranch*)prev_op;
6201 
6202             LIR_Op2* prev_cmp = NULL;
6203 
6204             for(int j = instructions->length() - 3; j >= 0 && prev_cmp == NULL; j--) {
6205               prev_op = instructions->at(j);
6206               if(prev_op->code() == lir_cmp) {
6207                 assert(prev_op->as_Op2() != NULL, "branch must be of type LIR_Op2");
6208                 prev_cmp = (LIR_Op2*)prev_op;
6209                 assert(prev_branch->cond() == prev_cmp->condition(), "should be the same");
6210               }
6211             }
6212             assert(prev_cmp != NULL, "should have found comp instruction for branch");
6213             if (prev_branch->block() == code->at(i + 1) && prev_branch->info() == NULL) {
6214 
6215               TRACE_LINEAR_SCAN(3, tty->print_cr("Negating conditional branch and deleting unconditional branch at end of block B%d", block->block_id()));
6216 
6217               // eliminate a conditional branch to the immediate successor
6218               prev_branch->change_block(last_branch->block());
6219               prev_branch->negate_cond();
6220               prev_cmp->set_condition(prev_branch->cond());
6221               instructions->truncate(instructions->length() - 1);
6222             }
6223           }
6224         }
6225       }
6226     }
6227   }
6228 
6229   DEBUG_ONLY(verify(code));
6230 }
6231 
6232 void ControlFlowOptimizer::delete_jumps_to_return(BlockList* code) {
6233 #ifdef ASSERT
6234   BitMap return_converted(BlockBegin::number_of_blocks());
6235   return_converted.clear();
6236 #endif
6237 
6238   for (int i = code->length() - 1; i >= 0; i--) {
6239     BlockBegin* block = code->at(i);
6240     LIR_OpList* cur_instructions = block->lir()->instructions_list();
6241     LIR_Op*     cur_last_op = cur_instructions->last();
6242 
6243     assert(cur_instructions->at(0)->code() == lir_label, "first instruction must always be a label");
6244     if (cur_instructions->length() == 2 && cur_last_op->code() == lir_return) {
6245       // the block contains only a label and a return
6246       // if a predecessor ends with an unconditional jump to this block, then the jump
6247       // can be replaced with a return instruction
6248       //
6249       // Note: the original block with only a return statement cannot be deleted completely
6250       //       because the predecessors might have other (conditional) jumps to this block
6251       //       -> this may lead to unnecesary return instructions in the final code
6252 
6253       assert(cur_last_op->info() == NULL, "return instructions do not have debug information");
6254       assert(block->number_of_sux() == 0 ||
6255              (return_converted.at(block->block_id()) && block->number_of_sux() == 1),
6256              "blocks that end with return must not have successors");
6257 
6258       assert(cur_last_op->as_Op1() != NULL, "return must be LIR_Op1");
6259       LIR_Opr return_opr = ((LIR_Op1*)cur_last_op)->in_opr();
6260 
6261       for (int j = block->number_of_preds() - 1; j >= 0; j--) {
6262         BlockBegin* pred = block->pred_at(j);
6263         LIR_OpList* pred_instructions = pred->lir()->instructions_list();
6264         LIR_Op*     pred_last_op = pred_instructions->last();
6265 
6266         if (pred_last_op->code() == lir_branch) {
6267           assert(pred_last_op->as_OpBranch() != NULL, "branch must be LIR_OpBranch");
6268           LIR_OpBranch* pred_last_branch = (LIR_OpBranch*)pred_last_op;
6269 
6270           if (pred_last_branch->block() == block && pred_last_branch->cond() == lir_cond_always && pred_last_branch->info() == NULL) {
6271             // replace the jump to a return with a direct return
6272             // Note: currently the edge between the blocks is not deleted
6273             pred_instructions->at_put(pred_instructions->length() - 1, new LIR_Op1(lir_return, return_opr));
6274 #ifdef ASSERT
6275             return_converted.set_bit(pred->block_id());
6276 #endif
6277           }
6278         }
6279       }
6280     }
6281   }
6282 }
6283 
6284 
6285 #ifdef ASSERT
6286 void ControlFlowOptimizer::verify(BlockList* code) {
6287   for (int i = 0; i < code->length(); i++) {
6288     BlockBegin* block = code->at(i);
6289     LIR_OpList* instructions = block->lir()->instructions_list();
6290 
6291     int j;
6292     for (j = 0; j < instructions->length(); j++) {
6293       LIR_OpBranch* op_branch = instructions->at(j)->as_OpBranch();
6294 
6295       if (op_branch != NULL) {
6296         assert(op_branch->block() == NULL || code->index_of(op_branch->block()) != -1, "branch target not valid");
6297         assert(op_branch->ublock() == NULL || code->index_of(op_branch->ublock()) != -1, "branch target not valid");
6298       }
6299     }
6300 
6301     for (j = 0; j < block->number_of_sux() - 1; j++) {
6302       BlockBegin* sux = block->sux_at(j);
6303       assert(code->index_of(sux) != -1, "successor not valid");
6304     }
6305 
6306     for (j = 0; j < block->number_of_preds() - 1; j++) {
6307       BlockBegin* pred = block->pred_at(j);
6308       assert(code->index_of(pred) != -1, "successor not valid");
6309     }
6310   }
6311 }
6312 #endif
6313 
6314 
6315 #ifndef PRODUCT
6316 
6317 // Implementation of LinearStatistic
6318 
6319 const char* LinearScanStatistic::counter_name(int counter_idx) {
6320   switch (counter_idx) {
6321     case counter_method:          return "compiled methods";
6322     case counter_fpu_method:      return "methods using fpu";
6323     case counter_loop_method:     return "methods with loops";
6324     case counter_exception_method:return "methods with xhandler";
6325 
6326     case counter_loop:            return "loops";
6327     case counter_block:           return "blocks";
6328     case counter_loop_block:      return "blocks inside loop";
6329     case counter_exception_block: return "exception handler entries";
6330     case counter_interval:        return "intervals";
6331     case counter_fixed_interval:  return "fixed intervals";
6332     case counter_range:           return "ranges";
6333     case counter_fixed_range:     return "fixed ranges";
6334     case counter_use_pos:         return "use positions";
6335     case counter_fixed_use_pos:   return "fixed use positions";
6336     case counter_spill_slots:     return "spill slots";
6337 
6338     // counter for classes of lir instructions
6339     case counter_instruction:     return "total instructions";
6340     case counter_label:           return "labels";
6341     case counter_entry:           return "method entries";
6342     case counter_return:          return "method returns";
6343     case counter_call:            return "method calls";
6344     case counter_move:            return "moves";
6345     case counter_cmp:             return "compare";
6346     case counter_cond_branch:     return "conditional branches";
6347     case counter_uncond_branch:   return "unconditional branches";
6348     case counter_stub_branch:     return "branches to stub";
6349     case counter_alu:             return "artithmetic + logic";
6350     case counter_alloc:           return "allocations";
6351     case counter_sync:            return "synchronisation";
6352     case counter_throw:           return "throw";
6353     case counter_unwind:          return "unwind";
6354     case counter_typecheck:       return "type+null-checks";
6355     case counter_fpu_stack:       return "fpu-stack";
6356     case counter_misc_inst:       return "other instructions";
6357     case counter_other_inst:      return "misc. instructions";
6358 
6359     // counter for different types of moves
6360     case counter_move_total:      return "total moves";
6361     case counter_move_reg_reg:    return "register->register";
6362     case counter_move_reg_stack:  return "register->stack";
6363     case counter_move_stack_reg:  return "stack->register";
6364     case counter_move_stack_stack:return "stack->stack";
6365     case counter_move_reg_mem:    return "register->memory";
6366     case counter_move_mem_reg:    return "memory->register";
6367     case counter_move_const_any:  return "constant->any";
6368 
6369     case blank_line_1:            return "";
6370     case blank_line_2:            return "";
6371 
6372     default: ShouldNotReachHere(); return "";
6373   }
6374 }
6375 
6376 LinearScanStatistic::Counter LinearScanStatistic::base_counter(int counter_idx) {
6377   if (counter_idx == counter_fpu_method || counter_idx == counter_loop_method || counter_idx == counter_exception_method) {
6378     return counter_method;
6379   } else if (counter_idx == counter_loop_block || counter_idx == counter_exception_block) {
6380     return counter_block;
6381   } else if (counter_idx >= counter_instruction && counter_idx <= counter_other_inst) {
6382     return counter_instruction;
6383   } else if (counter_idx >= counter_move_total && counter_idx <= counter_move_const_any) {
6384     return counter_move_total;
6385   }
6386   return invalid_counter;
6387 }
6388 
6389 LinearScanStatistic::LinearScanStatistic() {
6390   for (int i = 0; i < number_of_counters; i++) {
6391     _counters_sum[i] = 0;
6392     _counters_max[i] = -1;
6393   }
6394 
6395 }
6396 
6397 // add the method-local numbers to the total sum
6398 void LinearScanStatistic::sum_up(LinearScanStatistic &method_statistic) {
6399   for (int i = 0; i < number_of_counters; i++) {
6400     _counters_sum[i] += method_statistic._counters_sum[i];
6401     _counters_max[i] = MAX2(_counters_max[i], method_statistic._counters_sum[i]);
6402   }
6403 }
6404 
6405 void LinearScanStatistic::print(const char* title) {
6406   if (CountLinearScan || TraceLinearScanLevel > 0) {
6407     tty->cr();
6408     tty->print_cr("***** LinearScan statistic - %s *****", title);
6409 
6410     for (int i = 0; i < number_of_counters; i++) {
6411       if (_counters_sum[i] > 0 || _counters_max[i] >= 0) {
6412         tty->print("%25s: %8d", counter_name(i), _counters_sum[i]);
6413 
6414         if (base_counter(i) != invalid_counter) {
6415           tty->print("  (%5.1f%%) ", _counters_sum[i] * 100.0 / _counters_sum[base_counter(i)]);
6416         } else {
6417           tty->print("           ");
6418         }
6419 
6420         if (_counters_max[i] >= 0) {
6421           tty->print("%8d", _counters_max[i]);
6422         }
6423       }
6424       tty->cr();
6425     }
6426   }
6427 }
6428 
6429 void LinearScanStatistic::collect(LinearScan* allocator) {
6430   inc_counter(counter_method);
6431   if (allocator->has_fpu_registers()) {
6432     inc_counter(counter_fpu_method);
6433   }
6434   if (allocator->num_loops() > 0) {
6435     inc_counter(counter_loop_method);
6436   }
6437   inc_counter(counter_loop, allocator->num_loops());
6438   inc_counter(counter_spill_slots, allocator->max_spills());
6439 
6440   int i;
6441   for (i = 0; i < allocator->interval_count(); i++) {
6442     Interval* cur = allocator->interval_at(i);
6443 
6444     if (cur != NULL) {
6445       inc_counter(counter_interval);
6446       inc_counter(counter_use_pos, cur->num_use_positions());
6447       if (LinearScan::is_precolored_interval(cur)) {
6448         inc_counter(counter_fixed_interval);
6449         inc_counter(counter_fixed_use_pos, cur->num_use_positions());
6450       }
6451 
6452       Range* range = cur->first();
6453       while (range != Range::end()) {
6454         inc_counter(counter_range);
6455         if (LinearScan::is_precolored_interval(cur)) {
6456           inc_counter(counter_fixed_range);
6457         }
6458         range = range->next();
6459       }
6460     }
6461   }
6462 
6463   bool has_xhandlers = false;
6464   // Note: only count blocks that are in code-emit order
6465   for (i = 0; i < allocator->ir()->code()->length(); i++) {
6466     BlockBegin* cur = allocator->ir()->code()->at(i);
6467 
6468     inc_counter(counter_block);
6469     if (cur->loop_depth() > 0) {
6470       inc_counter(counter_loop_block);
6471     }
6472     if (cur->is_set(BlockBegin::exception_entry_flag)) {
6473       inc_counter(counter_exception_block);
6474       has_xhandlers = true;
6475     }
6476 
6477     LIR_OpList* instructions = cur->lir()->instructions_list();
6478     for (int j = 0; j < instructions->length(); j++) {
6479       LIR_Op* op = instructions->at(j);
6480 
6481       inc_counter(counter_instruction);
6482 
6483       switch (op->code()) {
6484         case lir_label:           inc_counter(counter_label); break;
6485         case lir_std_entry:
6486         case lir_osr_entry:       inc_counter(counter_entry); break;
6487         case lir_return:          inc_counter(counter_return); break;
6488 
6489         case lir_rtcall:
6490         case lir_static_call:
6491         case lir_optvirtual_call:
6492         case lir_virtual_call:    inc_counter(counter_call); break;
6493 
6494         case lir_move: {
6495           inc_counter(counter_move);
6496           inc_counter(counter_move_total);
6497 
6498           LIR_Opr in = op->as_Op1()->in_opr();
6499           LIR_Opr res = op->as_Op1()->result_opr();
6500           if (in->is_register()) {
6501             if (res->is_register()) {
6502               inc_counter(counter_move_reg_reg);
6503             } else if (res->is_stack()) {
6504               inc_counter(counter_move_reg_stack);
6505             } else if (res->is_address()) {
6506               inc_counter(counter_move_reg_mem);
6507             } else {
6508               ShouldNotReachHere();
6509             }
6510           } else if (in->is_stack()) {
6511             if (res->is_register()) {
6512               inc_counter(counter_move_stack_reg);
6513             } else {
6514               inc_counter(counter_move_stack_stack);
6515             }
6516           } else if (in->is_address()) {
6517             assert(res->is_register(), "must be");
6518             inc_counter(counter_move_mem_reg);
6519           } else if (in->is_constant()) {
6520             inc_counter(counter_move_const_any);
6521           } else {
6522             ShouldNotReachHere();
6523           }
6524           break;
6525         }
6526 
6527         case lir_cmp:             inc_counter(counter_cmp); break;
6528 
6529         case lir_branch:
6530         case lir_cond_float_branch: {
6531           LIR_OpBranch* branch = op->as_OpBranch();
6532           if (branch->block() == NULL) {
6533             inc_counter(counter_stub_branch);
6534           } else if (branch->cond() == lir_cond_always) {
6535             inc_counter(counter_uncond_branch);
6536           } else {
6537             inc_counter(counter_cond_branch);
6538           }
6539           break;
6540         }
6541 
6542         case lir_neg:
6543         case lir_add:
6544         case lir_sub:
6545         case lir_mul:
6546         case lir_mul_strictfp:
6547         case lir_div:
6548         case lir_div_strictfp:
6549         case lir_rem:
6550         case lir_sqrt:
6551         case lir_sin:
6552         case lir_cos:
6553         case lir_abs:
6554         case lir_log10:
6555         case lir_log:
6556         case lir_logic_and:
6557         case lir_logic_or:
6558         case lir_logic_xor:
6559         case lir_shl:
6560         case lir_shr:
6561         case lir_ushr:            inc_counter(counter_alu); break;
6562 
6563         case lir_alloc_object:
6564         case lir_alloc_array:     inc_counter(counter_alloc); break;
6565 
6566         case lir_monaddr:
6567         case lir_lock:
6568         case lir_unlock:          inc_counter(counter_sync); break;
6569 
6570         case lir_throw:           inc_counter(counter_throw); break;
6571 
6572         case lir_unwind:          inc_counter(counter_unwind); break;
6573 
6574         case lir_null_check:
6575         case lir_leal:
6576         case lir_instanceof:
6577         case lir_checkcast:
6578         case lir_store_check:     inc_counter(counter_typecheck); break;
6579 
6580         case lir_fpop_raw:
6581         case lir_fxch:
6582         case lir_fld:             inc_counter(counter_fpu_stack); break;
6583 
6584         case lir_nop:
6585         case lir_push:
6586         case lir_pop:
6587         case lir_convert:
6588         case lir_roundfp:
6589         case lir_cmove:           inc_counter(counter_misc_inst); break;
6590 
6591         default:                  inc_counter(counter_other_inst); break;
6592       }
6593     }
6594   }
6595 
6596   if (has_xhandlers) {
6597     inc_counter(counter_exception_method);
6598   }
6599 }
6600 
6601 void LinearScanStatistic::compute(LinearScan* allocator, LinearScanStatistic &global_statistic) {
6602   if (CountLinearScan || TraceLinearScanLevel > 0) {
6603 
6604     LinearScanStatistic local_statistic = LinearScanStatistic();
6605 
6606     local_statistic.collect(allocator);
6607     global_statistic.sum_up(local_statistic);
6608 
6609     if (TraceLinearScanLevel > 2) {
6610       local_statistic.print("current local statistic");
6611     }
6612   }
6613 }
6614 
6615 
6616 // Implementation of LinearTimers
6617 
6618 LinearScanTimers::LinearScanTimers() {
6619   for (int i = 0; i < number_of_timers; i++) {
6620     timer(i)->reset();
6621   }
6622 }
6623 
6624 const char* LinearScanTimers::timer_name(int idx) {
6625   switch (idx) {
6626     case timer_do_nothing:               return "Nothing (Time Check)";
6627     case timer_number_instructions:      return "Number Instructions";
6628     case timer_compute_local_live_sets:  return "Local Live Sets";
6629     case timer_compute_global_live_sets: return "Global Live Sets";
6630     case timer_build_intervals:          return "Build Intervals";
6631     case timer_sort_intervals_before:    return "Sort Intervals Before";
6632     case timer_allocate_registers:       return "Allocate Registers";
6633     case timer_resolve_data_flow:        return "Resolve Data Flow";
6634     case timer_sort_intervals_after:     return "Sort Intervals After";
6635     case timer_eliminate_spill_moves:    return "Spill optimization";
6636     case timer_assign_reg_num:           return "Assign Reg Num";
6637     case timer_allocate_fpu_stack:       return "Allocate FPU Stack";
6638     case timer_optimize_lir:             return "Optimize LIR";
6639     default: ShouldNotReachHere();       return "";
6640   }
6641 }
6642 
6643 void LinearScanTimers::begin_method() {
6644   if (TimeEachLinearScan) {
6645     // reset all timers to measure only current method
6646     for (int i = 0; i < number_of_timers; i++) {
6647       timer(i)->reset();
6648     }
6649   }
6650 }
6651 
6652 void LinearScanTimers::end_method(LinearScan* allocator) {
6653   if (TimeEachLinearScan) {
6654 
6655     double c = timer(timer_do_nothing)->seconds();
6656     double total = 0;
6657     for (int i = 1; i < number_of_timers; i++) {
6658       total += timer(i)->seconds() - c;
6659     }
6660 
6661     if (total >= 0.0005) {
6662       // print all information in one line for automatic processing
6663       tty->print("@"); allocator->compilation()->method()->print_name();
6664 
6665       tty->print("@ %d ", allocator->compilation()->method()->code_size());
6666       tty->print("@ %d ", allocator->block_at(allocator->block_count() - 1)->last_lir_instruction_id() / 2);
6667       tty->print("@ %d ", allocator->block_count());
6668       tty->print("@ %d ", allocator->num_virtual_regs());
6669       tty->print("@ %d ", allocator->interval_count());
6670       tty->print("@ %d ", allocator->_num_calls);
6671       tty->print("@ %d ", allocator->num_loops());
6672 
6673       tty->print("@ %6.6f ", total);
6674       for (int i = 1; i < number_of_timers; i++) {
6675         tty->print("@ %4.1f ", ((timer(i)->seconds() - c) / total) * 100);
6676       }
6677       tty->cr();
6678     }
6679   }
6680 }
6681 
6682 void LinearScanTimers::print(double total_time) {
6683   if (TimeLinearScan) {
6684     // correction value: sum of dummy-timer that only measures the time that
6685     // is necesary to start and stop itself
6686     double c = timer(timer_do_nothing)->seconds();
6687 
6688     for (int i = 0; i < number_of_timers; i++) {
6689       double t = timer(i)->seconds();
6690       tty->print_cr("    %25s: %6.3f s (%4.1f%%)  corrected: %6.3f s (%4.1f%%)", timer_name(i), t, (t / total_time) * 100.0, t - c, (t - c) / (total_time - 2 * number_of_timers * c) * 100);
6691     }
6692   }
6693 }
6694 
6695 #endif // #ifndef PRODUCT
--- EOF ---