1 /*
2 * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "c1/c1_InstructionPrinter.hpp"
27 #include "c1/c1_LIR.hpp"
28 #include "c1/c1_LIRAssembler.hpp"
29 #include "c1/c1_ValueStack.hpp"
30 #include "ci/ciInstance.hpp"
31 #include "runtime/sharedRuntime.hpp"
32
33 Register LIR_OprDesc::as_register() const {
34 return FrameMap::cpu_rnr2reg(cpu_regnr());
35 }
36
37 Register LIR_OprDesc::as_register_lo() const {
38 return FrameMap::cpu_rnr2reg(cpu_regnrLo());
39 }
40
41 Register LIR_OprDesc::as_register_hi() const {
42 return FrameMap::cpu_rnr2reg(cpu_regnrHi());
43 }
44
45 #if defined(X86)
46
47 XMMRegister LIR_OprDesc::as_xmm_float_reg() const {
48 return FrameMap::nr2xmmreg(xmm_regnr());
49 }
50
51 XMMRegister LIR_OprDesc::as_xmm_double_reg() const {
52 assert(xmm_regnrLo() == xmm_regnrHi(), "assumed in calculation");
53 return FrameMap::nr2xmmreg(xmm_regnrLo());
54 }
55
56 #endif // X86
57
58 #if defined(SPARC) || defined(PPC)
59
60 FloatRegister LIR_OprDesc::as_float_reg() const {
61 return FrameMap::nr2floatreg(fpu_regnr());
62 }
63
64 FloatRegister LIR_OprDesc::as_double_reg() const {
65 return FrameMap::nr2floatreg(fpu_regnrHi());
66 }
67
68 #endif
69
70 #ifdef ARM
71
72 FloatRegister LIR_OprDesc::as_float_reg() const {
73 return as_FloatRegister(fpu_regnr());
74 }
75
76 FloatRegister LIR_OprDesc::as_double_reg() const {
77 return as_FloatRegister(fpu_regnrLo());
78 }
79
80 #endif
81
82
83 LIR_Opr LIR_OprFact::illegalOpr = LIR_OprFact::illegal();
84
85 LIR_Opr LIR_OprFact::value_type(ValueType* type) {
86 ValueTag tag = type->tag();
87 switch (tag) {
88 case metaDataTag : {
89 ClassConstant* c = type->as_ClassConstant();
90 if (c != NULL && !c->value()->is_loaded()) {
91 return LIR_OprFact::metadataConst(NULL);
92 } else if (c != NULL) {
93 return LIR_OprFact::metadataConst(c->value()->constant_encoding());
94 } else {
95 MethodConstant* m = type->as_MethodConstant();
96 assert (m != NULL, "not a class or a method?");
97 return LIR_OprFact::metadataConst(m->value()->constant_encoding());
98 }
99 }
100 case objectTag : {
101 return LIR_OprFact::oopConst(type->as_ObjectType()->encoding());
102 }
103 case addressTag: return LIR_OprFact::addressConst(type->as_AddressConstant()->value());
104 case intTag : return LIR_OprFact::intConst(type->as_IntConstant()->value());
105 case floatTag : return LIR_OprFact::floatConst(type->as_FloatConstant()->value());
106 case longTag : return LIR_OprFact::longConst(type->as_LongConstant()->value());
107 case doubleTag : return LIR_OprFact::doubleConst(type->as_DoubleConstant()->value());
108 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1);
109 }
110 }
111
112
113 LIR_Opr LIR_OprFact::dummy_value_type(ValueType* type) {
114 switch (type->tag()) {
115 case objectTag: return LIR_OprFact::oopConst(NULL);
116 case addressTag:return LIR_OprFact::addressConst(0);
117 case intTag: return LIR_OprFact::intConst(0);
118 case floatTag: return LIR_OprFact::floatConst(0.0);
119 case longTag: return LIR_OprFact::longConst(0);
120 case doubleTag: return LIR_OprFact::doubleConst(0.0);
121 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1);
122 }
123 return illegalOpr;
124 }
125
126
127
128 //---------------------------------------------------
129
130
131 LIR_Address::Scale LIR_Address::scale(BasicType type) {
132 int elem_size = type2aelembytes(type);
133 switch (elem_size) {
134 case 1: return LIR_Address::times_1;
135 case 2: return LIR_Address::times_2;
136 case 4: return LIR_Address::times_4;
137 case 8: return LIR_Address::times_8;
138 }
139 ShouldNotReachHere();
140 return LIR_Address::times_1;
141 }
142
143
144 #ifndef PRODUCT
145 void LIR_Address::verify() const {
146 #if defined(SPARC) || defined(PPC)
147 assert(scale() == times_1, "Scaled addressing mode not available on SPARC/PPC and should not be used");
148 assert(disp() == 0 || index()->is_illegal(), "can't have both");
149 #endif
150 #ifdef ARM
151 assert(disp() == 0 || index()->is_illegal(), "can't have both");
152 // Note: offsets higher than 4096 must not be rejected here. They can
153 // be handled by the back-end or will be rejected if not.
154 #endif
155 #ifdef _LP64
156 assert(base()->is_cpu_register(), "wrong base operand");
157 assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand");
158 assert(base()->type() == T_OBJECT || base()->type() == T_LONG || base()->type() == T_METADATA,
159 "wrong type for addresses");
160 #else
161 assert(base()->is_single_cpu(), "wrong base operand");
162 assert(index()->is_illegal() || index()->is_single_cpu(), "wrong index operand");
163 assert(base()->type() == T_OBJECT || base()->type() == T_INT || base()->type() == T_METADATA,
164 "wrong type for addresses");
165 #endif
166 }
167 #endif
168
169
170 //---------------------------------------------------
171
172 char LIR_OprDesc::type_char(BasicType t) {
173 switch (t) {
174 case T_ARRAY:
175 t = T_OBJECT;
176 case T_BOOLEAN:
177 case T_CHAR:
178 case T_FLOAT:
179 case T_DOUBLE:
180 case T_BYTE:
181 case T_SHORT:
182 case T_INT:
183 case T_LONG:
184 case T_OBJECT:
185 case T_ADDRESS:
186 case T_VOID:
187 return ::type2char(t);
188 case T_METADATA:
189 return 'M';
190 case T_ILLEGAL:
191 return '?';
192
193 default:
194 ShouldNotReachHere();
195 return '?';
196 }
197 }
198
199 #ifndef PRODUCT
200 void LIR_OprDesc::validate_type() const {
201
202 #ifdef ASSERT
203 if (!is_pointer() && !is_illegal()) {
204 OprKind kindfield = kind_field(); // Factored out because of compiler bug, see 8002160
205 switch (as_BasicType(type_field())) {
206 case T_LONG:
207 assert((kindfield == cpu_register || kindfield == stack_value) &&
208 size_field() == double_size, "must match");
209 break;
210 case T_FLOAT:
211 // FP return values can be also in CPU registers on ARM and PPC (softfp ABI)
212 assert((kindfield == fpu_register || kindfield == stack_value
213 ARM_ONLY(|| kindfield == cpu_register)
214 PPC_ONLY(|| kindfield == cpu_register) ) &&
215 size_field() == single_size, "must match");
216 break;
217 case T_DOUBLE:
218 // FP return values can be also in CPU registers on ARM and PPC (softfp ABI)
219 assert((kindfield == fpu_register || kindfield == stack_value
220 ARM_ONLY(|| kindfield == cpu_register)
221 PPC_ONLY(|| kindfield == cpu_register) ) &&
222 size_field() == double_size, "must match");
223 break;
224 case T_BOOLEAN:
225 case T_CHAR:
226 case T_BYTE:
227 case T_SHORT:
228 case T_INT:
229 case T_ADDRESS:
230 case T_OBJECT:
231 case T_METADATA:
232 case T_ARRAY:
233 assert((kindfield == cpu_register || kindfield == stack_value) &&
234 size_field() == single_size, "must match");
235 break;
236
237 case T_ILLEGAL:
238 // XXX TKR also means unknown right now
239 // assert(is_illegal(), "must match");
240 break;
241
242 default:
243 ShouldNotReachHere();
244 }
245 }
246 #endif
247
248 }
249 #endif // PRODUCT
250
251
252 bool LIR_OprDesc::is_oop() const {
253 if (is_pointer()) {
254 return pointer()->is_oop_pointer();
255 } else {
256 OprType t= type_field();
257 assert(t != unknown_type, "not set");
258 return t == object_type;
259 }
260 }
261
262
263
264 void LIR_Op2::verify() const {
265 #ifdef ASSERT
266 switch (code()) {
267 case lir_cmove:
268 case lir_xchg:
269 break;
270
271 default:
272 assert(!result_opr()->is_register() || !result_opr()->is_oop_register(),
273 "can't produce oops from arith");
274 }
275
276 if (TwoOperandLIRForm) {
277 switch (code()) {
278 case lir_add:
279 case lir_sub:
280 case lir_mul:
281 case lir_mul_strictfp:
282 case lir_div:
283 case lir_div_strictfp:
284 case lir_rem:
285 case lir_logic_and:
286 case lir_logic_or:
287 case lir_logic_xor:
288 case lir_shl:
289 case lir_shr:
290 assert(in_opr1() == result_opr(), "opr1 and result must match");
291 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid");
292 break;
293
294 // special handling for lir_ushr because of write barriers
295 case lir_ushr:
296 assert(in_opr1() == result_opr() || in_opr2()->is_constant(), "opr1 and result must match or shift count is constant");
297 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid");
298 break;
299
300 }
301 }
302 #endif
303 }
304
305
306 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block)
307 : LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
308 , _cond(cond)
309 , _type(type)
310 , _label(block->label())
311 , _block(block)
312 , _ublock(NULL)
313 , _stub(NULL) {
314 }
315
316 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, CodeStub* stub) :
317 LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
318 , _cond(cond)
319 , _type(type)
320 , _label(stub->entry())
321 , _block(NULL)
322 , _ublock(NULL)
323 , _stub(stub) {
324 }
325
326 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block, BlockBegin* ublock)
327 : LIR_Op(lir_cond_float_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
328 , _cond(cond)
329 , _type(type)
330 , _label(block->label())
331 , _block(block)
332 , _ublock(ublock)
333 , _stub(NULL)
334 {
335 }
336
337 void LIR_OpBranch::change_block(BlockBegin* b) {
338 assert(_block != NULL, "must have old block");
339 assert(_block->label() == label(), "must be equal");
340
341 _block = b;
342 _label = b->label();
343 }
344
345 void LIR_OpBranch::change_ublock(BlockBegin* b) {
346 assert(_ublock != NULL, "must have old block");
347 _ublock = b;
348 }
349
350 void LIR_OpBranch::negate_cond() {
351 switch (_cond) {
352 case lir_cond_equal: _cond = lir_cond_notEqual; break;
353 case lir_cond_notEqual: _cond = lir_cond_equal; break;
354 case lir_cond_less: _cond = lir_cond_greaterEqual; break;
355 case lir_cond_lessEqual: _cond = lir_cond_greater; break;
356 case lir_cond_greaterEqual: _cond = lir_cond_less; break;
357 case lir_cond_greater: _cond = lir_cond_lessEqual; break;
358 default: ShouldNotReachHere();
359 }
360 }
361
362
363 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr result, LIR_Opr object, ciKlass* klass,
364 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3,
365 bool fast_check, CodeEmitInfo* info_for_patch,
366 CodeStub* stub)
367
368 : LIR_Op(code, result, NULL)
369 , _object(object)
370 , _array(LIR_OprFact::illegalOpr)
371 , _klass(klass)
372 , _tmp1(tmp1)
373 , _tmp2(tmp2)
374 , _tmp3(tmp3)
375 , _fast_check(fast_check)
376 , _stub(stub)
377 , _info_for_patch(info_for_patch)
378 , _info_for_exception(NULL)
379 , _profiled_method(NULL)
380 , _profiled_bci(-1)
381 , _should_profile(false)
382 {
383 assert (code == lir_checkcast || code == lir_instanceof, "expects checkcast or instanceof only");
384 }
385
386
387
388 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, CodeEmitInfo* info_for_exception)
389 : LIR_Op(code, LIR_OprFact::illegalOpr, NULL)
390 , _object(object)
391 , _array(array)
392 , _klass(NULL)
393 , _tmp1(tmp1)
394 , _tmp2(tmp2)
395 , _tmp3(tmp3)
396 , _fast_check(false)
397 , _stub(NULL)
398 , _info_for_patch(NULL)
399 , _info_for_exception(info_for_exception)
400 , _profiled_method(NULL)
401 , _profiled_bci(-1)
402 , _should_profile(false)
403 {
404 if (code == lir_store_check) {
405 _stub = new ArrayStoreExceptionStub(object, info_for_exception);
406 assert(info_for_exception != NULL, "store_check throws exceptions");
407 } else {
408 ShouldNotReachHere();
409 }
410 }
411
412
413 LIR_OpArrayCopy::LIR_OpArrayCopy(LIR_Opr src, LIR_Opr src_pos, LIR_Opr dst, LIR_Opr dst_pos, LIR_Opr length,
414 LIR_Opr tmp, ciArrayKlass* expected_type, int flags, CodeEmitInfo* info)
415 : LIR_Op(lir_arraycopy, LIR_OprFact::illegalOpr, info)
416 , _tmp(tmp)
417 , _src(src)
418 , _src_pos(src_pos)
419 , _dst(dst)
420 , _dst_pos(dst_pos)
421 , _flags(flags)
422 , _expected_type(expected_type)
423 , _length(length) {
424 _stub = new ArrayCopyStub(this);
425 }
426
427 LIR_OpUpdateCRC32::LIR_OpUpdateCRC32(LIR_Opr crc, LIR_Opr val, LIR_Opr res)
428 : LIR_Op(lir_updatecrc32, res, NULL)
429 , _crc(crc)
430 , _val(val) {
431 }
432
433 //-------------------verify--------------------------
434
435 void LIR_Op1::verify() const {
436 switch(code()) {
437 case lir_move:
438 assert(in_opr()->is_valid() && result_opr()->is_valid(), "must be");
439 break;
440 case lir_null_check:
441 assert(in_opr()->is_register(), "must be");
442 break;
443 case lir_return:
444 assert(in_opr()->is_register() || in_opr()->is_illegal(), "must be");
445 break;
446 }
447 }
448
449 void LIR_OpRTCall::verify() const {
450 assert(strcmp(Runtime1::name_for_address(addr()), "<unknown function>") != 0, "unknown function");
451 }
452
453 //-------------------visits--------------------------
454
455 // complete rework of LIR instruction visitor.
456 // The virtual calls for each instruction type is replaced by a big
457 // switch that adds the operands for each instruction
458
459 void LIR_OpVisitState::visit(LIR_Op* op) {
460 // copy information from the LIR_Op
461 reset();
462 set_op(op);
463
464 switch (op->code()) {
465
466 // LIR_Op0
467 case lir_word_align: // result and info always invalid
468 case lir_backwardbranch_target: // result and info always invalid
469 case lir_build_frame: // result and info always invalid
470 case lir_fpop_raw: // result and info always invalid
471 case lir_24bit_FPU: // result and info always invalid
472 case lir_reset_FPU: // result and info always invalid
473 case lir_breakpoint: // result and info always invalid
474 case lir_membar: // result and info always invalid
475 case lir_membar_acquire: // result and info always invalid
476 case lir_membar_release: // result and info always invalid
477 case lir_membar_loadload: // result and info always invalid
478 case lir_membar_storestore: // result and info always invalid
479 case lir_membar_loadstore: // result and info always invalid
480 case lir_membar_storeload: // result and info always invalid
481 {
482 assert(op->as_Op0() != NULL, "must be");
483 assert(op->_info == NULL, "info not used by this instruction");
484 assert(op->_result->is_illegal(), "not used");
485 break;
486 }
487
488 case lir_nop: // may have info, result always invalid
489 case lir_std_entry: // may have result, info always invalid
490 case lir_osr_entry: // may have result, info always invalid
491 case lir_get_thread: // may have result, info always invalid
492 {
493 assert(op->as_Op0() != NULL, "must be");
494 if (op->_info != NULL) do_info(op->_info);
495 if (op->_result->is_valid()) do_output(op->_result);
496 break;
497 }
498
499
500 // LIR_OpLabel
501 case lir_label: // result and info always invalid
502 {
503 assert(op->as_OpLabel() != NULL, "must be");
504 assert(op->_info == NULL, "info not used by this instruction");
505 assert(op->_result->is_illegal(), "not used");
506 break;
507 }
508
509
510 // LIR_Op1
511 case lir_fxch: // input always valid, result and info always invalid
512 case lir_fld: // input always valid, result and info always invalid
513 case lir_ffree: // input always valid, result and info always invalid
514 case lir_push: // input always valid, result and info always invalid
515 case lir_pop: // input always valid, result and info always invalid
516 case lir_return: // input always valid, result and info always invalid
517 case lir_leal: // input and result always valid, info always invalid
518 case lir_neg: // input and result always valid, info always invalid
519 case lir_monaddr: // input and result always valid, info always invalid
520 case lir_null_check: // input and info always valid, result always invalid
521 case lir_move: // input and result always valid, may have info
522 case lir_pack64: // input and result always valid
523 case lir_unpack64: // input and result always valid
524 case lir_prefetchr: // input always valid, result and info always invalid
525 case lir_prefetchw: // input always valid, result and info always invalid
526 {
527 assert(op->as_Op1() != NULL, "must be");
528 LIR_Op1* op1 = (LIR_Op1*)op;
529
530 if (op1->_info) do_info(op1->_info);
531 if (op1->_opr->is_valid()) do_input(op1->_opr);
532 if (op1->_result->is_valid()) do_output(op1->_result);
533
534 break;
535 }
536
537 case lir_safepoint:
538 {
539 assert(op->as_Op1() != NULL, "must be");
540 LIR_Op1* op1 = (LIR_Op1*)op;
541
542 assert(op1->_info != NULL, ""); do_info(op1->_info);
543 if (op1->_opr->is_valid()) do_temp(op1->_opr); // safepoints on SPARC need temporary register
544 assert(op1->_result->is_illegal(), "safepoint does not produce value");
545
546 break;
547 }
548
549 // LIR_OpConvert;
550 case lir_convert: // input and result always valid, info always invalid
551 {
552 assert(op->as_OpConvert() != NULL, "must be");
553 LIR_OpConvert* opConvert = (LIR_OpConvert*)op;
554
555 assert(opConvert->_info == NULL, "must be");
556 if (opConvert->_opr->is_valid()) do_input(opConvert->_opr);
557 if (opConvert->_result->is_valid()) do_output(opConvert->_result);
558 #ifdef PPC
559 if (opConvert->_tmp1->is_valid()) do_temp(opConvert->_tmp1);
560 if (opConvert->_tmp2->is_valid()) do_temp(opConvert->_tmp2);
561 #endif
562 do_stub(opConvert->_stub);
563
564 break;
565 }
566
567 // LIR_OpBranch;
568 case lir_branch: // may have info, input and result register always invalid
569 case lir_cond_float_branch: // may have info, input and result register always invalid
570 {
571 assert(op->as_OpBranch() != NULL, "must be");
572 LIR_OpBranch* opBranch = (LIR_OpBranch*)op;
573
574 if (opBranch->_info != NULL) do_info(opBranch->_info);
575 assert(opBranch->_result->is_illegal(), "not used");
576 if (opBranch->_stub != NULL) opBranch->stub()->visit(this);
577
578 break;
579 }
580
581
582 // LIR_OpAllocObj
583 case lir_alloc_object:
584 {
585 assert(op->as_OpAllocObj() != NULL, "must be");
586 LIR_OpAllocObj* opAllocObj = (LIR_OpAllocObj*)op;
587
588 if (opAllocObj->_info) do_info(opAllocObj->_info);
589 if (opAllocObj->_opr->is_valid()) { do_input(opAllocObj->_opr);
590 do_temp(opAllocObj->_opr);
591 }
592 if (opAllocObj->_tmp1->is_valid()) do_temp(opAllocObj->_tmp1);
593 if (opAllocObj->_tmp2->is_valid()) do_temp(opAllocObj->_tmp2);
594 if (opAllocObj->_tmp3->is_valid()) do_temp(opAllocObj->_tmp3);
595 if (opAllocObj->_tmp4->is_valid()) do_temp(opAllocObj->_tmp4);
596 if (opAllocObj->_result->is_valid()) do_output(opAllocObj->_result);
597 do_stub(opAllocObj->_stub);
598 break;
599 }
600
601
602 // LIR_OpRoundFP;
603 case lir_roundfp: {
604 assert(op->as_OpRoundFP() != NULL, "must be");
605 LIR_OpRoundFP* opRoundFP = (LIR_OpRoundFP*)op;
606
607 assert(op->_info == NULL, "info not used by this instruction");
608 assert(opRoundFP->_tmp->is_illegal(), "not used");
609 do_input(opRoundFP->_opr);
610 do_output(opRoundFP->_result);
611
612 break;
613 }
614
615
616 // LIR_Op2
617 case lir_cmp:
618 case lir_cmp_l2i:
619 case lir_ucmp_fd2i:
620 case lir_cmp_fd2i:
621 case lir_add:
622 case lir_sub:
623 case lir_mul:
624 case lir_div:
625 case lir_rem:
626 case lir_sqrt:
627 case lir_abs:
628 case lir_logic_and:
629 case lir_logic_or:
630 case lir_logic_xor:
631 case lir_shl:
632 case lir_shr:
633 case lir_ushr:
634 case lir_xadd:
635 case lir_xchg:
636 case lir_assert:
637 {
638 assert(op->as_Op2() != NULL, "must be");
639 LIR_Op2* op2 = (LIR_Op2*)op;
640 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
641 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
642
643 if (op2->_info) do_info(op2->_info);
644 if (op2->_opr1->is_valid()) do_input(op2->_opr1);
645 if (op2->_opr2->is_valid()) do_input(op2->_opr2);
646 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1);
647 if (op2->_result->is_valid()) do_output(op2->_result);
648 if (op->code() == lir_xchg || op->code() == lir_xadd) {
649 // on ARM and PPC, return value is loaded first so could
650 // destroy inputs. On other platforms that implement those
651 // (x86, sparc), the extra constrainsts are harmless.
652 if (op2->_opr1->is_valid()) do_temp(op2->_opr1);
653 if (op2->_opr2->is_valid()) do_temp(op2->_opr2);
654 }
655
656 break;
657 }
658
659 // special handling for cmove: right input operand must not be equal
660 // to the result operand, otherwise the backend fails
661 case lir_cmove:
662 {
663 assert(op->as_Op2() != NULL, "must be");
664 LIR_Op2* op2 = (LIR_Op2*)op;
665
666 assert(op2->_info == NULL && op2->_tmp1->is_illegal() && op2->_tmp2->is_illegal() &&
667 op2->_tmp3->is_illegal() && op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
668 assert(op2->_opr1->is_valid() && op2->_opr2->is_valid() && op2->_result->is_valid(), "used");
669
670 do_input(op2->_opr1);
671 do_input(op2->_opr2);
672 do_temp(op2->_opr2);
673 do_output(op2->_result);
674
675 break;
676 }
677
678 // vspecial handling for strict operations: register input operands
679 // as temp to guarantee that they do not overlap with other
680 // registers
681 case lir_mul_strictfp:
682 case lir_div_strictfp:
683 {
684 assert(op->as_Op2() != NULL, "must be");
685 LIR_Op2* op2 = (LIR_Op2*)op;
686
687 assert(op2->_info == NULL, "not used");
688 assert(op2->_opr1->is_valid(), "used");
689 assert(op2->_opr2->is_valid(), "used");
690 assert(op2->_result->is_valid(), "used");
691 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
692 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
693
694 do_input(op2->_opr1); do_temp(op2->_opr1);
695 do_input(op2->_opr2); do_temp(op2->_opr2);
696 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1);
697 do_output(op2->_result);
698
699 break;
700 }
701
702 case lir_throw: {
703 assert(op->as_Op2() != NULL, "must be");
704 LIR_Op2* op2 = (LIR_Op2*)op;
705
706 if (op2->_info) do_info(op2->_info);
707 if (op2->_opr1->is_valid()) do_temp(op2->_opr1);
708 if (op2->_opr2->is_valid()) do_input(op2->_opr2); // exception object is input parameter
709 assert(op2->_result->is_illegal(), "no result");
710 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
711 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
712
713 break;
714 }
715
716 case lir_unwind: {
717 assert(op->as_Op1() != NULL, "must be");
718 LIR_Op1* op1 = (LIR_Op1*)op;
719
720 assert(op1->_info == NULL, "no info");
721 assert(op1->_opr->is_valid(), "exception oop"); do_input(op1->_opr);
722 assert(op1->_result->is_illegal(), "no result");
723
724 break;
725 }
726
727
728 case lir_tan:
729 case lir_sin:
730 case lir_cos:
731 case lir_log:
732 case lir_log10:
733 case lir_exp: {
734 assert(op->as_Op2() != NULL, "must be");
735 LIR_Op2* op2 = (LIR_Op2*)op;
736
737 // On x86 tan/sin/cos need two temporary fpu stack slots and
738 // log/log10 need one so handle opr2 and tmp as temp inputs.
739 // Register input operand as temp to guarantee that it doesn't
740 // overlap with the input.
741 assert(op2->_info == NULL, "not used");
742 assert(op2->_tmp5->is_illegal(), "not used");
743 assert(op2->_tmp2->is_valid() == (op->code() == lir_exp), "not used");
744 assert(op2->_tmp3->is_valid() == (op->code() == lir_exp), "not used");
745 assert(op2->_tmp4->is_valid() == (op->code() == lir_exp), "not used");
746 assert(op2->_opr1->is_valid(), "used");
747 do_input(op2->_opr1); do_temp(op2->_opr1);
748
749 if (op2->_opr2->is_valid()) do_temp(op2->_opr2);
750 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1);
751 if (op2->_tmp2->is_valid()) do_temp(op2->_tmp2);
752 if (op2->_tmp3->is_valid()) do_temp(op2->_tmp3);
753 if (op2->_tmp4->is_valid()) do_temp(op2->_tmp4);
754 if (op2->_result->is_valid()) do_output(op2->_result);
755
756 break;
757 }
758
759 case lir_pow: {
760 assert(op->as_Op2() != NULL, "must be");
761 LIR_Op2* op2 = (LIR_Op2*)op;
762
763 // On x86 pow needs two temporary fpu stack slots: tmp1 and
764 // tmp2. Register input operands as temps to guarantee that it
765 // doesn't overlap with the temporary slots.
766 assert(op2->_info == NULL, "not used");
767 assert(op2->_opr1->is_valid() && op2->_opr2->is_valid(), "used");
768 assert(op2->_tmp1->is_valid() && op2->_tmp2->is_valid() && op2->_tmp3->is_valid()
769 && op2->_tmp4->is_valid() && op2->_tmp5->is_valid(), "used");
770 assert(op2->_result->is_valid(), "used");
771
772 do_input(op2->_opr1); do_temp(op2->_opr1);
773 do_input(op2->_opr2); do_temp(op2->_opr2);
774 do_temp(op2->_tmp1);
775 do_temp(op2->_tmp2);
776 do_temp(op2->_tmp3);
777 do_temp(op2->_tmp4);
778 do_temp(op2->_tmp5);
779 do_output(op2->_result);
780
781 break;
782 }
783
784 // LIR_Op3
785 case lir_idiv:
786 case lir_irem: {
787 assert(op->as_Op3() != NULL, "must be");
788 LIR_Op3* op3= (LIR_Op3*)op;
789
790 if (op3->_info) do_info(op3->_info);
791 if (op3->_opr1->is_valid()) do_input(op3->_opr1);
792
793 // second operand is input and temp, so ensure that second operand
794 // and third operand get not the same register
795 if (op3->_opr2->is_valid()) do_input(op3->_opr2);
796 if (op3->_opr2->is_valid()) do_temp(op3->_opr2);
797 if (op3->_opr3->is_valid()) do_temp(op3->_opr3);
798
799 if (op3->_result->is_valid()) do_output(op3->_result);
800
801 break;
802 }
803
804
805 // LIR_OpJavaCall
806 case lir_static_call:
807 case lir_optvirtual_call:
808 case lir_icvirtual_call:
809 case lir_virtual_call:
810 case lir_dynamic_call: {
811 LIR_OpJavaCall* opJavaCall = op->as_OpJavaCall();
812 assert(opJavaCall != NULL, "must be");
813
814 if (opJavaCall->_receiver->is_valid()) do_input(opJavaCall->_receiver);
815
816 // only visit register parameters
817 int n = opJavaCall->_arguments->length();
818 for (int i = opJavaCall->_receiver->is_valid() ? 1 : 0; i < n; i++) {
819 if (!opJavaCall->_arguments->at(i)->is_pointer()) {
820 do_input(*opJavaCall->_arguments->adr_at(i));
821 }
822 }
823
824 if (opJavaCall->_info) do_info(opJavaCall->_info);
825 if (opJavaCall->is_method_handle_invoke()) {
826 opJavaCall->_method_handle_invoke_SP_save_opr = FrameMap::method_handle_invoke_SP_save_opr();
827 do_temp(opJavaCall->_method_handle_invoke_SP_save_opr);
828 }
829 do_call();
830 if (opJavaCall->_result->is_valid()) do_output(opJavaCall->_result);
831
832 break;
833 }
834
835
836 // LIR_OpRTCall
837 case lir_rtcall: {
838 assert(op->as_OpRTCall() != NULL, "must be");
839 LIR_OpRTCall* opRTCall = (LIR_OpRTCall*)op;
840
841 // only visit register parameters
842 int n = opRTCall->_arguments->length();
843 for (int i = 0; i < n; i++) {
844 if (!opRTCall->_arguments->at(i)->is_pointer()) {
845 do_input(*opRTCall->_arguments->adr_at(i));
846 }
847 }
848 if (opRTCall->_info) do_info(opRTCall->_info);
849 if (opRTCall->_tmp->is_valid()) do_temp(opRTCall->_tmp);
850 do_call();
851 if (opRTCall->_result->is_valid()) do_output(opRTCall->_result);
852
853 break;
854 }
855
856
857 // LIR_OpArrayCopy
858 case lir_arraycopy: {
859 assert(op->as_OpArrayCopy() != NULL, "must be");
860 LIR_OpArrayCopy* opArrayCopy = (LIR_OpArrayCopy*)op;
861
862 assert(opArrayCopy->_result->is_illegal(), "unused");
863 assert(opArrayCopy->_src->is_valid(), "used"); do_input(opArrayCopy->_src); do_temp(opArrayCopy->_src);
864 assert(opArrayCopy->_src_pos->is_valid(), "used"); do_input(opArrayCopy->_src_pos); do_temp(opArrayCopy->_src_pos);
865 assert(opArrayCopy->_dst->is_valid(), "used"); do_input(opArrayCopy->_dst); do_temp(opArrayCopy->_dst);
866 assert(opArrayCopy->_dst_pos->is_valid(), "used"); do_input(opArrayCopy->_dst_pos); do_temp(opArrayCopy->_dst_pos);
867 assert(opArrayCopy->_length->is_valid(), "used"); do_input(opArrayCopy->_length); do_temp(opArrayCopy->_length);
868 assert(opArrayCopy->_tmp->is_valid(), "used"); do_temp(opArrayCopy->_tmp);
869 if (opArrayCopy->_info) do_info(opArrayCopy->_info);
870
871 // the implementation of arraycopy always has a call into the runtime
872 do_call();
873
874 break;
875 }
876
877
878 // LIR_OpUpdateCRC32
879 case lir_updatecrc32: {
880 assert(op->as_OpUpdateCRC32() != NULL, "must be");
881 LIR_OpUpdateCRC32* opUp = (LIR_OpUpdateCRC32*)op;
882
883 assert(opUp->_crc->is_valid(), "used"); do_input(opUp->_crc); do_temp(opUp->_crc);
884 assert(opUp->_val->is_valid(), "used"); do_input(opUp->_val); do_temp(opUp->_val);
885 assert(opUp->_result->is_valid(), "used"); do_output(opUp->_result);
886 assert(opUp->_info == NULL, "no info for LIR_OpUpdateCRC32");
887
888 break;
889 }
890
891
892 // LIR_OpLock
893 case lir_lock:
894 case lir_unlock: {
895 assert(op->as_OpLock() != NULL, "must be");
896 LIR_OpLock* opLock = (LIR_OpLock*)op;
897
898 if (opLock->_info) do_info(opLock->_info);
899
900 // TODO: check if these operands really have to be temp
901 // (or if input is sufficient). This may have influence on the oop map!
902 assert(opLock->_lock->is_valid(), "used"); do_temp(opLock->_lock);
903 assert(opLock->_hdr->is_valid(), "used"); do_temp(opLock->_hdr);
904 assert(opLock->_obj->is_valid(), "used"); do_temp(opLock->_obj);
905
906 if (opLock->_scratch->is_valid()) do_temp(opLock->_scratch);
907 assert(opLock->_result->is_illegal(), "unused");
908
909 do_stub(opLock->_stub);
910
911 break;
912 }
913
914
915 // LIR_OpDelay
916 case lir_delay_slot: {
917 assert(op->as_OpDelay() != NULL, "must be");
918 LIR_OpDelay* opDelay = (LIR_OpDelay*)op;
919
920 visit(opDelay->delay_op());
921 break;
922 }
923
924 // LIR_OpTypeCheck
925 case lir_instanceof:
926 case lir_checkcast:
927 case lir_store_check: {
928 assert(op->as_OpTypeCheck() != NULL, "must be");
929 LIR_OpTypeCheck* opTypeCheck = (LIR_OpTypeCheck*)op;
930
931 if (opTypeCheck->_info_for_exception) do_info(opTypeCheck->_info_for_exception);
932 if (opTypeCheck->_info_for_patch) do_info(opTypeCheck->_info_for_patch);
933 if (opTypeCheck->_object->is_valid()) do_input(opTypeCheck->_object);
934 if (op->code() == lir_store_check && opTypeCheck->_object->is_valid()) {
935 do_temp(opTypeCheck->_object);
936 }
937 if (opTypeCheck->_array->is_valid()) do_input(opTypeCheck->_array);
938 if (opTypeCheck->_tmp1->is_valid()) do_temp(opTypeCheck->_tmp1);
939 if (opTypeCheck->_tmp2->is_valid()) do_temp(opTypeCheck->_tmp2);
940 if (opTypeCheck->_tmp3->is_valid()) do_temp(opTypeCheck->_tmp3);
941 if (opTypeCheck->_result->is_valid()) do_output(opTypeCheck->_result);
942 do_stub(opTypeCheck->_stub);
943 break;
944 }
945
946 // LIR_OpCompareAndSwap
947 case lir_cas_long:
948 case lir_cas_obj:
949 case lir_cas_int: {
950 assert(op->as_OpCompareAndSwap() != NULL, "must be");
951 LIR_OpCompareAndSwap* opCompareAndSwap = (LIR_OpCompareAndSwap*)op;
952
953 assert(opCompareAndSwap->_addr->is_valid(), "used");
954 assert(opCompareAndSwap->_cmp_value->is_valid(), "used");
955 assert(opCompareAndSwap->_new_value->is_valid(), "used");
956 if (opCompareAndSwap->_info) do_info(opCompareAndSwap->_info);
957 do_input(opCompareAndSwap->_addr);
958 do_temp(opCompareAndSwap->_addr);
959 do_input(opCompareAndSwap->_cmp_value);
960 do_temp(opCompareAndSwap->_cmp_value);
961 do_input(opCompareAndSwap->_new_value);
962 do_temp(opCompareAndSwap->_new_value);
963 if (opCompareAndSwap->_tmp1->is_valid()) do_temp(opCompareAndSwap->_tmp1);
964 if (opCompareAndSwap->_tmp2->is_valid()) do_temp(opCompareAndSwap->_tmp2);
965 if (opCompareAndSwap->_result->is_valid()) do_output(opCompareAndSwap->_result);
966
967 break;
968 }
969
970
971 // LIR_OpAllocArray;
972 case lir_alloc_array: {
973 assert(op->as_OpAllocArray() != NULL, "must be");
974 LIR_OpAllocArray* opAllocArray = (LIR_OpAllocArray*)op;
975
976 if (opAllocArray->_info) do_info(opAllocArray->_info);
977 if (opAllocArray->_klass->is_valid()) do_input(opAllocArray->_klass); do_temp(opAllocArray->_klass);
978 if (opAllocArray->_len->is_valid()) do_input(opAllocArray->_len); do_temp(opAllocArray->_len);
979 if (opAllocArray->_tmp1->is_valid()) do_temp(opAllocArray->_tmp1);
980 if (opAllocArray->_tmp2->is_valid()) do_temp(opAllocArray->_tmp2);
981 if (opAllocArray->_tmp3->is_valid()) do_temp(opAllocArray->_tmp3);
982 if (opAllocArray->_tmp4->is_valid()) do_temp(opAllocArray->_tmp4);
983 if (opAllocArray->_result->is_valid()) do_output(opAllocArray->_result);
984 do_stub(opAllocArray->_stub);
985 break;
986 }
987
988 // LIR_OpProfileCall:
989 case lir_profile_call: {
990 assert(op->as_OpProfileCall() != NULL, "must be");
991 LIR_OpProfileCall* opProfileCall = (LIR_OpProfileCall*)op;
992
993 if (opProfileCall->_recv->is_valid()) do_temp(opProfileCall->_recv);
994 assert(opProfileCall->_mdo->is_valid(), "used"); do_temp(opProfileCall->_mdo);
995 assert(opProfileCall->_tmp1->is_valid(), "used"); do_temp(opProfileCall->_tmp1);
996 break;
997 }
998
999 // LIR_OpProfileType:
1000 case lir_profile_type: {
1001 assert(op->as_OpProfileType() != NULL, "must be");
1002 LIR_OpProfileType* opProfileType = (LIR_OpProfileType*)op;
1003
1004 do_input(opProfileType->_mdp); do_temp(opProfileType->_mdp);
1005 do_input(opProfileType->_obj);
1006 do_temp(opProfileType->_tmp);
1007 break;
1008 }
1009
1010 // LIR_OpCrypto_CBC_AES
1011 case lir_crypto_cbc_aes: {
1012 assert(op->as_OpCrypto_CBC_AES() != NULL, "must be");
1013 LIR_OpCrypto_CBC_AES* opCrypto_CBC_AES = (LIR_OpCrypto_CBC_AES*)op;
1014
1015 do_input(opCrypto_CBC_AES->_recv);
1016 do_input(opCrypto_CBC_AES->_src);
1017 do_input(opCrypto_CBC_AES->_src_off);
1018 do_input(opCrypto_CBC_AES->_src_len);
1019 do_input(opCrypto_CBC_AES->_dst);
1020 do_input(opCrypto_CBC_AES->_dst_off);
1021 do_input(opCrypto_CBC_AES->_insof);
1022
1023 do_temp(opCrypto_CBC_AES->_recv);
1024
1025 if (opCrypto_CBC_AES->_info) do_info(opCrypto_CBC_AES->_info);
1026 do_call();
1027 if (opCrypto_CBC_AES->_result->is_valid()) do_output(opCrypto_CBC_AES->_result);
1028
1029 break;
1030 }
1031
1032 default:
1033 ShouldNotReachHere();
1034 }
1035 }
1036
1037
1038 void LIR_OpVisitState::do_stub(CodeStub* stub) {
1039 if (stub != NULL) {
1040 stub->visit(this);
1041 }
1042 }
1043
1044 XHandlers* LIR_OpVisitState::all_xhandler() {
1045 XHandlers* result = NULL;
1046
1047 int i;
1048 for (i = 0; i < info_count(); i++) {
1049 if (info_at(i)->exception_handlers() != NULL) {
1050 result = info_at(i)->exception_handlers();
1051 break;
1052 }
1053 }
1054
1055 #ifdef ASSERT
1056 for (i = 0; i < info_count(); i++) {
1057 assert(info_at(i)->exception_handlers() == NULL ||
1058 info_at(i)->exception_handlers() == result,
1059 "only one xhandler list allowed per LIR-operation");
1060 }
1061 #endif
1062
1063 if (result != NULL) {
1064 return result;
1065 } else {
1066 return new XHandlers();
1067 }
1068
1069 return result;
1070 }
1071
1072
1073 #ifdef ASSERT
1074 bool LIR_OpVisitState::no_operands(LIR_Op* op) {
1075 visit(op);
1076
1077 return opr_count(inputMode) == 0 &&
1078 opr_count(outputMode) == 0 &&
1079 opr_count(tempMode) == 0 &&
1080 info_count() == 0 &&
1081 !has_call() &&
1082 !has_slow_case();
1083 }
1084 #endif
1085
1086 //---------------------------------------------------
1087
1088
1089 void LIR_OpJavaCall::emit_code(LIR_Assembler* masm) {
1090 masm->emit_call(this);
1091 }
1092
1093 void LIR_OpRTCall::emit_code(LIR_Assembler* masm) {
1094 masm->emit_rtcall(this);
1095 }
1096
1097 void LIR_OpLabel::emit_code(LIR_Assembler* masm) {
1098 masm->emit_opLabel(this);
1099 }
1100
1101 void LIR_OpArrayCopy::emit_code(LIR_Assembler* masm) {
1102 masm->emit_arraycopy(this);
1103 masm->emit_code_stub(stub());
1104 }
1105
1106 void LIR_OpUpdateCRC32::emit_code(LIR_Assembler* masm) {
1107 masm->emit_updatecrc32(this);
1108 }
1109
1110 void LIR_Op0::emit_code(LIR_Assembler* masm) {
1111 masm->emit_op0(this);
1112 }
1113
1114 void LIR_Op1::emit_code(LIR_Assembler* masm) {
1115 masm->emit_op1(this);
1116 }
1117
1118 void LIR_OpAllocObj::emit_code(LIR_Assembler* masm) {
1119 masm->emit_alloc_obj(this);
1120 masm->emit_code_stub(stub());
1121 }
1122
1123 void LIR_OpBranch::emit_code(LIR_Assembler* masm) {
1124 masm->emit_opBranch(this);
1125 if (stub()) {
1126 masm->emit_code_stub(stub());
1127 }
1128 }
1129
1130 void LIR_OpConvert::emit_code(LIR_Assembler* masm) {
1131 masm->emit_opConvert(this);
1132 if (stub() != NULL) {
1133 masm->emit_code_stub(stub());
1134 }
1135 }
1136
1137 void LIR_Op2::emit_code(LIR_Assembler* masm) {
1138 masm->emit_op2(this);
1139 }
1140
1141 void LIR_OpAllocArray::emit_code(LIR_Assembler* masm) {
1142 masm->emit_alloc_array(this);
1143 masm->emit_code_stub(stub());
1144 }
1145
1146 void LIR_OpTypeCheck::emit_code(LIR_Assembler* masm) {
1147 masm->emit_opTypeCheck(this);
1148 if (stub()) {
1149 masm->emit_code_stub(stub());
1150 }
1151 }
1152
1153 void LIR_OpCompareAndSwap::emit_code(LIR_Assembler* masm) {
1154 masm->emit_compare_and_swap(this);
1155 }
1156
1157 void LIR_OpCrypto_CBC_AES::emit_code(LIR_Assembler* masm) {
1158 masm->emit_crypto_cbc_aes(this);
1159 }
1160
1161 void LIR_Op3::emit_code(LIR_Assembler* masm) {
1162 masm->emit_op3(this);
1163 }
1164
1165 void LIR_OpLock::emit_code(LIR_Assembler* masm) {
1166 masm->emit_lock(this);
1167 if (stub()) {
1168 masm->emit_code_stub(stub());
1169 }
1170 }
1171
1172 #ifdef ASSERT
1173 void LIR_OpAssert::emit_code(LIR_Assembler* masm) {
1174 masm->emit_assert(this);
1175 }
1176 #endif
1177
1178 void LIR_OpDelay::emit_code(LIR_Assembler* masm) {
1179 masm->emit_delay(this);
1180 }
1181
1182 void LIR_OpProfileCall::emit_code(LIR_Assembler* masm) {
1183 masm->emit_profile_call(this);
1184 }
1185
1186 void LIR_OpProfileType::emit_code(LIR_Assembler* masm) {
1187 masm->emit_profile_type(this);
1188 }
1189
1190 // LIR_List
1191 LIR_List::LIR_List(Compilation* compilation, BlockBegin* block)
1192 : _operations(8)
1193 , _compilation(compilation)
1194 #ifndef PRODUCT
1195 , _block(block)
1196 #endif
1197 #ifdef ASSERT
1198 , _file(NULL)
1199 , _line(0)
1200 #endif
1201 { }
1202
1203
1204 #ifdef ASSERT
1205 void LIR_List::set_file_and_line(const char * file, int line) {
1206 const char * f = strrchr(file, '/');
1207 if (f == NULL) f = strrchr(file, '\\');
1208 if (f == NULL) {
1209 f = file;
1210 } else {
1211 f++;
1212 }
1213 _file = f;
1214 _line = line;
1215 }
1216 #endif
1217
1218
1219 void LIR_List::append(LIR_InsertionBuffer* buffer) {
1220 assert(this == buffer->lir_list(), "wrong lir list");
1221 const int n = _operations.length();
1222
1223 if (buffer->number_of_ops() > 0) {
1224 // increase size of instructions list
1225 _operations.at_grow(n + buffer->number_of_ops() - 1, NULL);
1226 // insert ops from buffer into instructions list
1227 int op_index = buffer->number_of_ops() - 1;
1228 int ip_index = buffer->number_of_insertion_points() - 1;
1229 int from_index = n - 1;
1230 int to_index = _operations.length() - 1;
1231 for (; ip_index >= 0; ip_index --) {
1232 int index = buffer->index_at(ip_index);
1233 // make room after insertion point
1234 while (index < from_index) {
1235 _operations.at_put(to_index --, _operations.at(from_index --));
1236 }
1237 // insert ops from buffer
1238 for (int i = buffer->count_at(ip_index); i > 0; i --) {
1239 _operations.at_put(to_index --, buffer->op_at(op_index --));
1240 }
1241 }
1242 }
1243
1244 buffer->finish();
1245 }
1246
1247
1248 void LIR_List::oop2reg_patch(jobject o, LIR_Opr reg, CodeEmitInfo* info) {
1249 assert(reg->type() == T_OBJECT, "bad reg");
1250 append(new LIR_Op1(lir_move, LIR_OprFact::oopConst(o), reg, T_OBJECT, lir_patch_normal, info));
1251 }
1252
1253 void LIR_List::klass2reg_patch(Metadata* o, LIR_Opr reg, CodeEmitInfo* info) {
1254 assert(reg->type() == T_METADATA, "bad reg");
1255 append(new LIR_Op1(lir_move, LIR_OprFact::metadataConst(o), reg, T_METADATA, lir_patch_normal, info));
1256 }
1257
1258 void LIR_List::load(LIR_Address* addr, LIR_Opr src, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1259 append(new LIR_Op1(
1260 lir_move,
1261 LIR_OprFact::address(addr),
1262 src,
1263 addr->type(),
1264 patch_code,
1265 info));
1266 }
1267
1268
1269 void LIR_List::volatile_load_mem_reg(LIR_Address* address, LIR_Opr dst, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1270 append(new LIR_Op1(
1271 lir_move,
1272 LIR_OprFact::address(address),
1273 dst,
1274 address->type(),
1275 patch_code,
1276 info, lir_move_volatile));
1277 }
1278
1279 void LIR_List::volatile_load_unsafe_reg(LIR_Opr base, LIR_Opr offset, LIR_Opr dst, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1280 append(new LIR_Op1(
1281 lir_move,
1282 LIR_OprFact::address(new LIR_Address(base, offset, type)),
1283 dst,
1284 type,
1285 patch_code,
1286 info, lir_move_volatile));
1287 }
1288
1289
1290 void LIR_List::prefetch(LIR_Address* addr, bool is_store) {
1291 append(new LIR_Op1(
1292 is_store ? lir_prefetchw : lir_prefetchr,
1293 LIR_OprFact::address(addr)));
1294 }
1295
1296
1297 void LIR_List::store_mem_int(jint v, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1298 append(new LIR_Op1(
1299 lir_move,
1300 LIR_OprFact::intConst(v),
1301 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)),
1302 type,
1303 patch_code,
1304 info));
1305 }
1306
1307
1308 void LIR_List::store_mem_oop(jobject o, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1309 append(new LIR_Op1(
1310 lir_move,
1311 LIR_OprFact::oopConst(o),
1312 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)),
1313 type,
1314 patch_code,
1315 info));
1316 }
1317
1318
1319 void LIR_List::store(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1320 append(new LIR_Op1(
1321 lir_move,
1322 src,
1323 LIR_OprFact::address(addr),
1324 addr->type(),
1325 patch_code,
1326 info));
1327 }
1328
1329
1330 void LIR_List::volatile_store_mem_reg(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1331 append(new LIR_Op1(
1332 lir_move,
1333 src,
1334 LIR_OprFact::address(addr),
1335 addr->type(),
1336 patch_code,
1337 info,
1338 lir_move_volatile));
1339 }
1340
1341 void LIR_List::volatile_store_unsafe_reg(LIR_Opr src, LIR_Opr base, LIR_Opr offset, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1342 append(new LIR_Op1(
1343 lir_move,
1344 src,
1345 LIR_OprFact::address(new LIR_Address(base, offset, type)),
1346 type,
1347 patch_code,
1348 info, lir_move_volatile));
1349 }
1350
1351
1352 void LIR_List::idiv(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1353 append(new LIR_Op3(
1354 lir_idiv,
1355 left,
1356 right,
1357 tmp,
1358 res,
1359 info));
1360 }
1361
1362
1363 void LIR_List::idiv(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1364 append(new LIR_Op3(
1365 lir_idiv,
1366 left,
1367 LIR_OprFact::intConst(right),
1368 tmp,
1369 res,
1370 info));
1371 }
1372
1373
1374 void LIR_List::irem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1375 append(new LIR_Op3(
1376 lir_irem,
1377 left,
1378 right,
1379 tmp,
1380 res,
1381 info));
1382 }
1383
1384
1385 void LIR_List::irem(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1386 append(new LIR_Op3(
1387 lir_irem,
1388 left,
1389 LIR_OprFact::intConst(right),
1390 tmp,
1391 res,
1392 info));
1393 }
1394
1395
1396 void LIR_List::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) {
1397 append(new LIR_Op2(
1398 lir_cmp,
1399 condition,
1400 LIR_OprFact::address(new LIR_Address(base, disp, T_INT)),
1401 LIR_OprFact::intConst(c),
1402 info));
1403 }
1404
1405
1406 void LIR_List::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Address* addr, CodeEmitInfo* info) {
1407 append(new LIR_Op2(
1408 lir_cmp,
1409 condition,
1410 reg,
1411 LIR_OprFact::address(addr),
1412 info));
1413 }
1414
1415 void LIR_List::allocate_object(LIR_Opr dst, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4,
1416 int header_size, int object_size, LIR_Opr klass, bool init_check, CodeStub* stub) {
1417 append(new LIR_OpAllocObj(
1418 klass,
1419 dst,
1420 t1,
1421 t2,
1422 t3,
1423 t4,
1424 header_size,
1425 object_size,
1426 init_check,
1427 stub));
1428 }
1429
1430 void LIR_List::allocate_array(LIR_Opr dst, LIR_Opr len, LIR_Opr t1,LIR_Opr t2, LIR_Opr t3,LIR_Opr t4, BasicType type, LIR_Opr klass, CodeStub* stub) {
1431 append(new LIR_OpAllocArray(
1432 klass,
1433 len,
1434 dst,
1435 t1,
1436 t2,
1437 t3,
1438 t4,
1439 type,
1440 stub));
1441 }
1442
1443 void LIR_List::shift_left(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1444 append(new LIR_Op2(
1445 lir_shl,
1446 value,
1447 count,
1448 dst,
1449 tmp));
1450 }
1451
1452 void LIR_List::shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1453 append(new LIR_Op2(
1454 lir_shr,
1455 value,
1456 count,
1457 dst,
1458 tmp));
1459 }
1460
1461
1462 void LIR_List::unsigned_shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1463 append(new LIR_Op2(
1464 lir_ushr,
1465 value,
1466 count,
1467 dst,
1468 tmp));
1469 }
1470
1471 void LIR_List::fcmp2int(LIR_Opr left, LIR_Opr right, LIR_Opr dst, bool is_unordered_less) {
1472 append(new LIR_Op2(is_unordered_less ? lir_ucmp_fd2i : lir_cmp_fd2i,
1473 left,
1474 right,
1475 dst));
1476 }
1477
1478 void LIR_List::lock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub, CodeEmitInfo* info) {
1479 append(new LIR_OpLock(
1480 lir_lock,
1481 hdr,
1482 obj,
1483 lock,
1484 scratch,
1485 stub,
1486 info));
1487 }
1488
1489 void LIR_List::unlock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub) {
1490 append(new LIR_OpLock(
1491 lir_unlock,
1492 hdr,
1493 obj,
1494 lock,
1495 scratch,
1496 stub,
1497 NULL));
1498 }
1499
1500
1501 void check_LIR() {
1502 // cannot do the proper checking as PRODUCT and other modes return different results
1503 // guarantee(sizeof(LIR_OprDesc) == wordSize, "may not have a v-table");
1504 }
1505
1506
1507
1508 void LIR_List::checkcast (LIR_Opr result, LIR_Opr object, ciKlass* klass,
1509 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check,
1510 CodeEmitInfo* info_for_patch, CodeStub* stub,
1511 ciMethod* profiled_method, int profiled_bci) {
1512 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_checkcast, result, object, klass,
1513 tmp1, tmp2, tmp3, fast_check, info_for_patch, stub);
1514 if (profiled_method != NULL) {
1515 c->set_profiled_method(profiled_method);
1516 c->set_profiled_bci(profiled_bci);
1517 c->set_should_profile(true);
1518 }
1519 append(c);
1520 }
1521
1522 void LIR_List::instanceof(LIR_Opr result, LIR_Opr object, ciKlass* klass, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check, CodeEmitInfo* info_for_patch, ciMethod* profiled_method, int profiled_bci) {
1523 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_instanceof, result, object, klass, tmp1, tmp2, tmp3, fast_check, info_for_patch, NULL);
1524 if (profiled_method != NULL) {
1525 c->set_profiled_method(profiled_method);
1526 c->set_profiled_bci(profiled_bci);
1527 c->set_should_profile(true);
1528 }
1529 append(c);
1530 }
1531
1532
1533 void LIR_List::store_check(LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3,
1534 CodeEmitInfo* info_for_exception, ciMethod* profiled_method, int profiled_bci) {
1535 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_store_check, object, array, tmp1, tmp2, tmp3, info_for_exception);
1536 if (profiled_method != NULL) {
1537 c->set_profiled_method(profiled_method);
1538 c->set_profiled_bci(profiled_bci);
1539 c->set_should_profile(true);
1540 }
1541 append(c);
1542 }
1543
1544
1545 void LIR_List::cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1546 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1547 append(new LIR_OpCompareAndSwap(lir_cas_long, addr, cmp_value, new_value, t1, t2, result));
1548 }
1549
1550 void LIR_List::cas_obj(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1551 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1552 append(new LIR_OpCompareAndSwap(lir_cas_obj, addr, cmp_value, new_value, t1, t2, result));
1553 }
1554
1555 void LIR_List::cas_int(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1556 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1557 append(new LIR_OpCompareAndSwap(lir_cas_int, addr, cmp_value, new_value, t1, t2, result));
1558 }
1559
1560
1561 #ifdef PRODUCT
1562
1563 void print_LIR(BlockList* blocks) {
1564 }
1565
1566 #else
1567 // LIR_OprDesc
1568 void LIR_OprDesc::print() const {
1569 print(tty);
1570 }
1571
1572 void LIR_OprDesc::print(outputStream* out) const {
1573 if (is_illegal()) {
1574 return;
1575 }
1576
1577 out->print("[");
1578 if (is_pointer()) {
1579 pointer()->print_value_on(out);
1580 } else if (is_single_stack()) {
1581 out->print("stack:%d", single_stack_ix());
1582 } else if (is_double_stack()) {
1583 out->print("dbl_stack:%d",double_stack_ix());
1584 } else if (is_virtual()) {
1585 out->print("R%d", vreg_number());
1586 } else if (is_single_cpu()) {
1587 out->print(as_register()->name());
1588 } else if (is_double_cpu()) {
1589 out->print(as_register_hi()->name());
1590 out->print(as_register_lo()->name());
1591 #if defined(X86)
1592 } else if (is_single_xmm()) {
1593 out->print(as_xmm_float_reg()->name());
1594 } else if (is_double_xmm()) {
1595 out->print(as_xmm_double_reg()->name());
1596 } else if (is_single_fpu()) {
1597 out->print("fpu%d", fpu_regnr());
1598 } else if (is_double_fpu()) {
1599 out->print("fpu%d", fpu_regnrLo());
1600 #elif defined(ARM)
1601 } else if (is_single_fpu()) {
1602 out->print("s%d", fpu_regnr());
1603 } else if (is_double_fpu()) {
1604 out->print("d%d", fpu_regnrLo() >> 1);
1605 #else
1606 } else if (is_single_fpu()) {
1607 out->print(as_float_reg()->name());
1608 } else if (is_double_fpu()) {
1609 out->print(as_double_reg()->name());
1610 #endif
1611
1612 } else if (is_illegal()) {
1613 out->print("-");
1614 } else {
1615 out->print("Unknown Operand");
1616 }
1617 if (!is_illegal()) {
1618 out->print("|%c", type_char());
1619 }
1620 if (is_register() && is_last_use()) {
1621 out->print("(last_use)");
1622 }
1623 out->print("]");
1624 }
1625
1626
1627 // LIR_Address
1628 void LIR_Const::print_value_on(outputStream* out) const {
1629 switch (type()) {
1630 case T_ADDRESS:out->print("address:%d",as_jint()); break;
1631 case T_INT: out->print("int:%d", as_jint()); break;
1632 case T_LONG: out->print("lng:" JLONG_FORMAT, as_jlong()); break;
1633 case T_FLOAT: out->print("flt:%f", as_jfloat()); break;
1634 case T_DOUBLE: out->print("dbl:%f", as_jdouble()); break;
1635 case T_OBJECT: out->print("obj:0x%x", as_jobject()); break;
1636 case T_METADATA: out->print("metadata:0x%x", as_metadata());break;
1637 default: out->print("%3d:0x%x",type(), as_jdouble()); break;
1638 }
1639 }
1640
1641 // LIR_Address
1642 void LIR_Address::print_value_on(outputStream* out) const {
1643 out->print("Base:"); _base->print(out);
1644 if (!_index->is_illegal()) {
1645 out->print(" Index:"); _index->print(out);
1646 switch (scale()) {
1647 case times_1: break;
1648 case times_2: out->print(" * 2"); break;
1649 case times_4: out->print(" * 4"); break;
1650 case times_8: out->print(" * 8"); break;
1651 }
1652 }
1653 out->print(" Disp: %d", _disp);
1654 }
1655
1656 // debug output of block header without InstructionPrinter
1657 // (because phi functions are not necessary for LIR)
1658 static void print_block(BlockBegin* x) {
1659 // print block id
1660 BlockEnd* end = x->end();
1661 tty->print("B%d ", x->block_id());
1662
1663 // print flags
1664 if (x->is_set(BlockBegin::std_entry_flag)) tty->print("std ");
1665 if (x->is_set(BlockBegin::osr_entry_flag)) tty->print("osr ");
1666 if (x->is_set(BlockBegin::exception_entry_flag)) tty->print("ex ");
1667 if (x->is_set(BlockBegin::subroutine_entry_flag)) tty->print("jsr ");
1668 if (x->is_set(BlockBegin::backward_branch_target_flag)) tty->print("bb ");
1669 if (x->is_set(BlockBegin::linear_scan_loop_header_flag)) tty->print("lh ");
1670 if (x->is_set(BlockBegin::linear_scan_loop_end_flag)) tty->print("le ");
1671
1672 // print block bci range
1673 tty->print("[%d, %d] ", x->bci(), (end == NULL ? -1 : end->printable_bci()));
1674
1675 // print predecessors and successors
1676 if (x->number_of_preds() > 0) {
1677 tty->print("preds: ");
1678 for (int i = 0; i < x->number_of_preds(); i ++) {
1679 tty->print("B%d ", x->pred_at(i)->block_id());
1680 }
1681 }
1682
1683 if (x->number_of_sux() > 0) {
1684 tty->print("sux: ");
1685 for (int i = 0; i < x->number_of_sux(); i ++) {
1686 tty->print("B%d ", x->sux_at(i)->block_id());
1687 }
1688 }
1689
1690 // print exception handlers
1691 if (x->number_of_exception_handlers() > 0) {
1692 tty->print("xhandler: ");
1693 for (int i = 0; i < x->number_of_exception_handlers(); i++) {
1694 tty->print("B%d ", x->exception_handler_at(i)->block_id());
1695 }
1696 }
1697
1698 tty->cr();
1699 }
1700
1701 void print_LIR(BlockList* blocks) {
1702 tty->print_cr("LIR:");
1703 int i;
1704 for (i = 0; i < blocks->length(); i++) {
1705 BlockBegin* bb = blocks->at(i);
1706 print_block(bb);
1707 tty->print("__id_Instruction___________________________________________"); tty->cr();
1708 bb->lir()->print_instructions();
1709 }
1710 }
1711
1712 void LIR_List::print_instructions() {
1713 for (int i = 0; i < _operations.length(); i++) {
1714 _operations.at(i)->print(); tty->cr();
1715 }
1716 tty->cr();
1717 }
1718
1719 // LIR_Ops printing routines
1720 // LIR_Op
1721 void LIR_Op::print_on(outputStream* out) const {
1722 if (id() != -1 || PrintCFGToFile) {
1723 out->print("%4d ", id());
1724 } else {
1725 out->print(" ");
1726 }
1727 out->print(name()); out->print(" ");
1728 print_instr(out);
1729 if (info() != NULL) out->print(" [bci:%d]", info()->stack()->bci());
1730 #ifdef ASSERT
1731 if (Verbose && _file != NULL) {
1732 out->print(" (%s:%d)", _file, _line);
1733 }
1734 #endif
1735 }
1736
1737 const char * LIR_Op::name() const {
1738 const char* s = NULL;
1739 switch(code()) {
1740 // LIR_Op0
1741 case lir_membar: s = "membar"; break;
1742 case lir_membar_acquire: s = "membar_acquire"; break;
1743 case lir_membar_release: s = "membar_release"; break;
1744 case lir_membar_loadload: s = "membar_loadload"; break;
1745 case lir_membar_storestore: s = "membar_storestore"; break;
1746 case lir_membar_loadstore: s = "membar_loadstore"; break;
1747 case lir_membar_storeload: s = "membar_storeload"; break;
1748 case lir_word_align: s = "word_align"; break;
1749 case lir_label: s = "label"; break;
1750 case lir_nop: s = "nop"; break;
1751 case lir_backwardbranch_target: s = "backbranch"; break;
1752 case lir_std_entry: s = "std_entry"; break;
1753 case lir_osr_entry: s = "osr_entry"; break;
1754 case lir_build_frame: s = "build_frm"; break;
1755 case lir_fpop_raw: s = "fpop_raw"; break;
1756 case lir_24bit_FPU: s = "24bit_FPU"; break;
1757 case lir_reset_FPU: s = "reset_FPU"; break;
1758 case lir_breakpoint: s = "breakpoint"; break;
1759 case lir_get_thread: s = "get_thread"; break;
1760 // LIR_Op1
1761 case lir_fxch: s = "fxch"; break;
1762 case lir_fld: s = "fld"; break;
1763 case lir_ffree: s = "ffree"; break;
1764 case lir_push: s = "push"; break;
1765 case lir_pop: s = "pop"; break;
1766 case lir_null_check: s = "null_check"; break;
1767 case lir_return: s = "return"; break;
1768 case lir_safepoint: s = "safepoint"; break;
1769 case lir_neg: s = "neg"; break;
1770 case lir_leal: s = "leal"; break;
1771 case lir_branch: s = "branch"; break;
1772 case lir_cond_float_branch: s = "flt_cond_br"; break;
1773 case lir_move: s = "move"; break;
1774 case lir_roundfp: s = "roundfp"; break;
1775 case lir_rtcall: s = "rtcall"; break;
1776 case lir_throw: s = "throw"; break;
1777 case lir_unwind: s = "unwind"; break;
1778 case lir_convert: s = "convert"; break;
1779 case lir_alloc_object: s = "alloc_obj"; break;
1780 case lir_monaddr: s = "mon_addr"; break;
1781 case lir_pack64: s = "pack64"; break;
1782 case lir_unpack64: s = "unpack64"; break;
1783 // LIR_Op2
1784 case lir_cmp: s = "cmp"; break;
1785 case lir_cmp_l2i: s = "cmp_l2i"; break;
1786 case lir_ucmp_fd2i: s = "ucomp_fd2i"; break;
1787 case lir_cmp_fd2i: s = "comp_fd2i"; break;
1788 case lir_cmove: s = "cmove"; break;
1789 case lir_add: s = "add"; break;
1790 case lir_sub: s = "sub"; break;
1791 case lir_mul: s = "mul"; break;
1792 case lir_mul_strictfp: s = "mul_strictfp"; break;
1793 case lir_div: s = "div"; break;
1794 case lir_div_strictfp: s = "div_strictfp"; break;
1795 case lir_rem: s = "rem"; break;
1796 case lir_abs: s = "abs"; break;
1797 case lir_sqrt: s = "sqrt"; break;
1798 case lir_sin: s = "sin"; break;
1799 case lir_cos: s = "cos"; break;
1800 case lir_tan: s = "tan"; break;
1801 case lir_log: s = "log"; break;
1802 case lir_log10: s = "log10"; break;
1803 case lir_exp: s = "exp"; break;
1804 case lir_pow: s = "pow"; break;
1805 case lir_logic_and: s = "logic_and"; break;
1806 case lir_logic_or: s = "logic_or"; break;
1807 case lir_logic_xor: s = "logic_xor"; break;
1808 case lir_shl: s = "shift_left"; break;
1809 case lir_shr: s = "shift_right"; break;
1810 case lir_ushr: s = "ushift_right"; break;
1811 case lir_alloc_array: s = "alloc_array"; break;
1812 case lir_xadd: s = "xadd"; break;
1813 case lir_xchg: s = "xchg"; break;
1814 // LIR_Op3
1815 case lir_idiv: s = "idiv"; break;
1816 case lir_irem: s = "irem"; break;
1817 // LIR_OpJavaCall
1818 case lir_static_call: s = "static"; break;
1819 case lir_optvirtual_call: s = "optvirtual"; break;
1820 case lir_icvirtual_call: s = "icvirtual"; break;
1821 case lir_virtual_call: s = "virtual"; break;
1822 case lir_dynamic_call: s = "dynamic"; break;
1823 // LIR_OpArrayCopy
1824 case lir_arraycopy: s = "arraycopy"; break;
1825 // LIR_OpUpdateCRC32
1826 case lir_updatecrc32: s = "updatecrc32"; break;
1827 // LIR_OpLock
1828 case lir_lock: s = "lock"; break;
1829 case lir_unlock: s = "unlock"; break;
1830 // LIR_OpDelay
1831 case lir_delay_slot: s = "delay"; break;
1832 // LIR_OpTypeCheck
1833 case lir_instanceof: s = "instanceof"; break;
1834 case lir_checkcast: s = "checkcast"; break;
1835 case lir_store_check: s = "store_check"; break;
1836 // LIR_OpCompareAndSwap
1837 case lir_cas_long: s = "cas_long"; break;
1838 case lir_cas_obj: s = "cas_obj"; break;
1839 case lir_cas_int: s = "cas_int"; break;
1840 // LIR_OpProfileCall
1841 case lir_profile_call: s = "profile_call"; break;
1842 // LIR_OpProfileType
1843 case lir_profile_type: s = "profile_type"; break;
1844 // LIR_OpAssert
1845 #ifdef ASSERT
1846 case lir_assert: s = "assert"; break;
1847 #endif
1848 case lir_none: ShouldNotReachHere();break;
1849 default: s = "illegal_op"; break;
1850 }
1851 return s;
1852 }
1853
1854 // LIR_OpJavaCall
1855 void LIR_OpJavaCall::print_instr(outputStream* out) const {
1856 out->print("call: ");
1857 out->print("[addr: 0x%x]", address());
1858 if (receiver()->is_valid()) {
1859 out->print(" [recv: "); receiver()->print(out); out->print("]");
1860 }
1861 if (result_opr()->is_valid()) {
1862 out->print(" [result: "); result_opr()->print(out); out->print("]");
1863 }
1864 }
1865
1866 // LIR_OpLabel
1867 void LIR_OpLabel::print_instr(outputStream* out) const {
1868 out->print("[label:0x%x]", _label);
1869 }
1870
1871 // LIR_OpArrayCopy
1872 void LIR_OpArrayCopy::print_instr(outputStream* out) const {
1873 src()->print(out); out->print(" ");
1874 src_pos()->print(out); out->print(" ");
1875 dst()->print(out); out->print(" ");
1876 dst_pos()->print(out); out->print(" ");
1877 length()->print(out); out->print(" ");
1878 tmp()->print(out); out->print(" ");
1879 }
1880
1881 // LIR_OpUpdateCRC32
1882 void LIR_OpUpdateCRC32::print_instr(outputStream* out) const {
1883 crc()->print(out); out->print(" ");
1884 val()->print(out); out->print(" ");
1885 result_opr()->print(out); out->print(" ");
1886 }
1887
1888 // LIR_OpCompareAndSwap
1889 void LIR_OpCompareAndSwap::print_instr(outputStream* out) const {
1890 addr()->print(out); out->print(" ");
1891 cmp_value()->print(out); out->print(" ");
1892 new_value()->print(out); out->print(" ");
1893 tmp1()->print(out); out->print(" ");
1894 tmp2()->print(out); out->print(" ");
1895
1896 }
1897
1898 // LIR_Op0
1899 void LIR_Op0::print_instr(outputStream* out) const {
1900 result_opr()->print(out);
1901 }
1902
1903 // LIR_Op1
1904 const char * LIR_Op1::name() const {
1905 if (code() == lir_move) {
1906 switch (move_kind()) {
1907 case lir_move_normal:
1908 return "move";
1909 case lir_move_unaligned:
1910 return "unaligned move";
1911 case lir_move_volatile:
1912 return "volatile_move";
1913 case lir_move_wide:
1914 return "wide_move";
1915 default:
1916 ShouldNotReachHere();
1917 return "illegal_op";
1918 }
1919 } else {
1920 return LIR_Op::name();
1921 }
1922 }
1923
1924
1925 void LIR_Op1::print_instr(outputStream* out) const {
1926 _opr->print(out); out->print(" ");
1927 result_opr()->print(out); out->print(" ");
1928 print_patch_code(out, patch_code());
1929 }
1930
1931
1932 // LIR_Op1
1933 void LIR_OpRTCall::print_instr(outputStream* out) const {
1934 intx a = (intx)addr();
1935 out->print(Runtime1::name_for_address(addr()));
1936 out->print(" ");
1937 tmp()->print(out);
1938 }
1939
1940 void LIR_Op1::print_patch_code(outputStream* out, LIR_PatchCode code) {
1941 switch(code) {
1942 case lir_patch_none: break;
1943 case lir_patch_low: out->print("[patch_low]"); break;
1944 case lir_patch_high: out->print("[patch_high]"); break;
1945 case lir_patch_volatile_normal: out->print("[patch_volatile_normal]"); break;
1946 case lir_patch_normal: out->print("[patch_normal]"); break;
1947 default: ShouldNotReachHere();
1948 }
1949 }
1950
1951 // LIR_OpBranch
1952 void LIR_OpBranch::print_instr(outputStream* out) const {
1953 print_condition(out, cond()); out->print(" ");
1954 if (block() != NULL) {
1955 out->print("[B%d] ", block()->block_id());
1956 } else if (stub() != NULL) {
1957 out->print("[");
1958 stub()->print_name(out);
1959 out->print(": 0x%x]", stub());
1960 if (stub()->info() != NULL) out->print(" [bci:%d]", stub()->info()->stack()->bci());
1961 } else {
1962 out->print("[label:0x%x] ", label());
1963 }
1964 if (ublock() != NULL) {
1965 out->print("unordered: [B%d] ", ublock()->block_id());
1966 }
1967 }
1968
1969 void LIR_Op::print_condition(outputStream* out, LIR_Condition cond) {
1970 switch(cond) {
1971 case lir_cond_equal: out->print("[EQ]"); break;
1972 case lir_cond_notEqual: out->print("[NE]"); break;
1973 case lir_cond_less: out->print("[LT]"); break;
1974 case lir_cond_lessEqual: out->print("[LE]"); break;
1975 case lir_cond_greaterEqual: out->print("[GE]"); break;
1976 case lir_cond_greater: out->print("[GT]"); break;
1977 case lir_cond_belowEqual: out->print("[BE]"); break;
1978 case lir_cond_aboveEqual: out->print("[AE]"); break;
1979 case lir_cond_always: out->print("[AL]"); break;
1980 default: out->print("[%d]",cond); break;
1981 }
1982 }
1983
1984 // LIR_OpConvert
1985 void LIR_OpConvert::print_instr(outputStream* out) const {
1986 print_bytecode(out, bytecode());
1987 in_opr()->print(out); out->print(" ");
1988 result_opr()->print(out); out->print(" ");
1989 #ifdef PPC
1990 if(tmp1()->is_valid()) {
1991 tmp1()->print(out); out->print(" ");
1992 tmp2()->print(out); out->print(" ");
1993 }
1994 #endif
1995 }
1996
1997 void LIR_OpConvert::print_bytecode(outputStream* out, Bytecodes::Code code) {
1998 switch(code) {
1999 case Bytecodes::_d2f: out->print("[d2f] "); break;
2000 case Bytecodes::_d2i: out->print("[d2i] "); break;
2001 case Bytecodes::_d2l: out->print("[d2l] "); break;
2002 case Bytecodes::_f2d: out->print("[f2d] "); break;
2003 case Bytecodes::_f2i: out->print("[f2i] "); break;
2004 case Bytecodes::_f2l: out->print("[f2l] "); break;
2005 case Bytecodes::_i2b: out->print("[i2b] "); break;
2006 case Bytecodes::_i2c: out->print("[i2c] "); break;
2007 case Bytecodes::_i2d: out->print("[i2d] "); break;
2008 case Bytecodes::_i2f: out->print("[i2f] "); break;
2009 case Bytecodes::_i2l: out->print("[i2l] "); break;
2010 case Bytecodes::_i2s: out->print("[i2s] "); break;
2011 case Bytecodes::_l2i: out->print("[l2i] "); break;
2012 case Bytecodes::_l2f: out->print("[l2f] "); break;
2013 case Bytecodes::_l2d: out->print("[l2d] "); break;
2014 default:
2015 out->print("[?%d]",code);
2016 break;
2017 }
2018 }
2019
2020 void LIR_OpAllocObj::print_instr(outputStream* out) const {
2021 klass()->print(out); out->print(" ");
2022 obj()->print(out); out->print(" ");
2023 tmp1()->print(out); out->print(" ");
2024 tmp2()->print(out); out->print(" ");
2025 tmp3()->print(out); out->print(" ");
2026 tmp4()->print(out); out->print(" ");
2027 out->print("[hdr:%d]", header_size()); out->print(" ");
2028 out->print("[obj:%d]", object_size()); out->print(" ");
2029 out->print("[lbl:0x%x]", stub()->entry());
2030 }
2031
2032 void LIR_OpRoundFP::print_instr(outputStream* out) const {
2033 _opr->print(out); out->print(" ");
2034 tmp()->print(out); out->print(" ");
2035 result_opr()->print(out); out->print(" ");
2036 }
2037
2038 // LIR_Op2
2039 void LIR_Op2::print_instr(outputStream* out) const {
2040 if (code() == lir_cmove) {
2041 print_condition(out, condition()); out->print(" ");
2042 }
2043 in_opr1()->print(out); out->print(" ");
2044 in_opr2()->print(out); out->print(" ");
2045 if (tmp1_opr()->is_valid()) { tmp1_opr()->print(out); out->print(" "); }
2046 if (tmp2_opr()->is_valid()) { tmp2_opr()->print(out); out->print(" "); }
2047 if (tmp3_opr()->is_valid()) { tmp3_opr()->print(out); out->print(" "); }
2048 if (tmp4_opr()->is_valid()) { tmp4_opr()->print(out); out->print(" "); }
2049 if (tmp5_opr()->is_valid()) { tmp5_opr()->print(out); out->print(" "); }
2050 result_opr()->print(out);
2051 }
2052
2053 void LIR_OpAllocArray::print_instr(outputStream* out) const {
2054 klass()->print(out); out->print(" ");
2055 len()->print(out); out->print(" ");
2056 obj()->print(out); out->print(" ");
2057 tmp1()->print(out); out->print(" ");
2058 tmp2()->print(out); out->print(" ");
2059 tmp3()->print(out); out->print(" ");
2060 tmp4()->print(out); out->print(" ");
2061 out->print("[type:0x%x]", type()); out->print(" ");
2062 out->print("[label:0x%x]", stub()->entry());
2063 }
2064
2065
2066 void LIR_OpTypeCheck::print_instr(outputStream* out) const {
2067 object()->print(out); out->print(" ");
2068 if (code() == lir_store_check) {
2069 array()->print(out); out->print(" ");
2070 }
2071 if (code() != lir_store_check) {
2072 klass()->print_name_on(out); out->print(" ");
2073 if (fast_check()) out->print("fast_check ");
2074 }
2075 tmp1()->print(out); out->print(" ");
2076 tmp2()->print(out); out->print(" ");
2077 tmp3()->print(out); out->print(" ");
2078 result_opr()->print(out); out->print(" ");
2079 if (info_for_exception() != NULL) out->print(" [bci:%d]", info_for_exception()->stack()->bci());
2080 }
2081
2082
2083 // LIR_Op3
2084 void LIR_Op3::print_instr(outputStream* out) const {
2085 in_opr1()->print(out); out->print(" ");
2086 in_opr2()->print(out); out->print(" ");
2087 in_opr3()->print(out); out->print(" ");
2088 result_opr()->print(out);
2089 }
2090
2091
2092 void LIR_OpLock::print_instr(outputStream* out) const {
2093 hdr_opr()->print(out); out->print(" ");
2094 obj_opr()->print(out); out->print(" ");
2095 lock_opr()->print(out); out->print(" ");
2096 if (_scratch->is_valid()) {
2097 _scratch->print(out); out->print(" ");
2098 }
2099 out->print("[lbl:0x%x]", stub()->entry());
2100 }
2101
2102 #ifdef ASSERT
2103 void LIR_OpAssert::print_instr(outputStream* out) const {
2104 print_condition(out, condition()); out->print(" ");
2105 in_opr1()->print(out); out->print(" ");
2106 in_opr2()->print(out); out->print(", \"");
2107 out->print(msg()); out->print("\"");
2108 }
2109 #endif
2110
2111
2112 void LIR_OpDelay::print_instr(outputStream* out) const {
2113 _op->print_on(out);
2114 }
2115
2116
2117 // LIR_OpProfileCall
2118 void LIR_OpProfileCall::print_instr(outputStream* out) const {
2119 profiled_method()->name()->print_symbol_on(out);
2120 out->print(".");
2121 profiled_method()->holder()->name()->print_symbol_on(out);
2122 out->print(" @ %d ", profiled_bci());
2123 mdo()->print(out); out->print(" ");
2124 recv()->print(out); out->print(" ");
2125 tmp1()->print(out); out->print(" ");
2126 }
2127
2128 // LIR_OpProfileType
2129 void LIR_OpProfileType::print_instr(outputStream* out) const {
2130 out->print("exact = "); exact_klass()->print_name_on(out);
2131 out->print("current = "); ciTypeEntries::print_ciklass(out, current_klass());
2132 mdp()->print(out); out->print(" ");
2133 obj()->print(out); out->print(" ");
2134 tmp()->print(out); out->print(" ");
2135 }
2136
2137 void LIR_OpCrypto_CBC_AES::print_instr(outputStream* out) const {
2138 src()->print(out); out->print(" ");
2139 src_off()->print(out); out->print(" ");
2140 src_len()->print(out); out->print(" ");
2141 dst()->print(out); out->print(" ");
2142 dst_off()->print(out); out->print(" ");
2143 }
2144 #endif // PRODUCT
2145
2146 // Implementation of LIR_InsertionBuffer
2147
2148 void LIR_InsertionBuffer::append(int index, LIR_Op* op) {
2149 assert(_index_and_count.length() % 2 == 0, "must have a count for each index");
2150
2151 int i = number_of_insertion_points() - 1;
2152 if (i < 0 || index_at(i) < index) {
2153 append_new(index, 1);
2154 } else {
2155 assert(index_at(i) == index, "can append LIR_Ops in ascending order only");
2156 assert(count_at(i) > 0, "check");
2157 set_count_at(i, count_at(i) + 1);
2158 }
2159 _ops.push(op);
2160
2161 DEBUG_ONLY(verify());
2162 }
2163
2164 #ifdef ASSERT
2165 void LIR_InsertionBuffer::verify() {
2166 int sum = 0;
2167 int prev_idx = -1;
2168
2169 for (int i = 0; i < number_of_insertion_points(); i++) {
2170 assert(prev_idx < index_at(i), "index must be ordered ascending");
2171 sum += count_at(i);
2172 }
2173 assert(sum == number_of_ops(), "wrong total sum");
2174 }
2175 #endif